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irda: fix smsc-ircc2 section mismatch warning
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / s2io.c
CommitLineData
1da177e4 1/************************************************************************
776bd20f 2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
926bd900 3 * Copyright(c) 2002-2010 Exar Corp.
d44570e4 4 *
1da177e4
LT		 5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
20346722
K		 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
1da177e4
LT		 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
20346722 21 * Francois Romieu : For pointing out all code part that were
1da177e4 22 * deprecated and also styling related comments.
20346722 23 * Grant Grundler : For helping me get rid of some Architecture
1da177e4
LT		 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
20346722 26 *
1da177e4 27 * The module loadable parameters that are supported by the driver and a brief
a2a20aef 28 * explanation of all the variables.
9dc737a7 29 *
20346722
K		 30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
9dc737a7
AR		 32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
da6971d8 34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
6d517a27 35 * values are 1, 2.
1da177e4 36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
20346722 37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
1da177e4 38 * Tx descriptors that can be associated with each corresponding FIFO.
9dc737a7 39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
8abc4d5b 40 * 2(MSI_X). Default value is '2(MSI_X)'
9dc737a7
AR		 41 * lro_max_pkts: This parameter defines maximum number of packets can be
42 * aggregated as a single large packet
926930b2
SS		 43 * napi: This parameter used to enable/disable NAPI (polling Rx)
44 * Possible values '1' for enable and '0' for disable. Default is '1'
45 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
46 * Possible values '1' for enable and '0' for disable. Default is '0'
47 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
48 * Possible values '1' for enable , '0' for disable.
49 * Default is '2' - which means disable in promisc mode
50 * and enable in non-promiscuous mode.
3a3d5756
SH		 51 * multiq: This parameter used to enable/disable MULTIQUEUE support.
52 * Possible values '1' for enable and '0' for disable. Default is '0'
1da177e4
LT		 53 ************************************************************************/
54
6cef2b8e
JP		 55#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
56
1da177e4
LT		 57#include <linux/module.h>
58#include <linux/types.h>
59#include <linux/errno.h>
60#include <linux/ioport.h>
61#include <linux/pci.h>
1e7f0bd8 62#include <linux/dma-mapping.h>
1da177e4
LT		 63#include <linux/kernel.h>
64#include <linux/netdevice.h>
65#include <linux/etherdevice.h>
40239396 66#include <linux/mdio.h>
1da177e4
LT		 67#include <linux/skbuff.h>
68#include <linux/init.h>
69#include <linux/delay.h>
70#include <linux/stddef.h>
71#include <linux/ioctl.h>
72#include <linux/timex.h>
1da177e4 73#include <linux/ethtool.h>
1da177e4 74#include <linux/workqueue.h>
be3a6b02 75#include <linux/if_vlan.h>
7d3d0439
RA		 76#include <linux/ip.h>
77#include <linux/tcp.h>
d44570e4
JP		 78#include <linux/uaccess.h>
79#include <linux/io.h>
5a0e3ad6 80#include <linux/slab.h>
70c71606 81#include <linux/prefetch.h>
7d3d0439 82#include <net/tcp.h>
1da177e4 83
1da177e4 84#include <asm/system.h>
fe931395 85#include <asm/div64.h>
330ce0de 86#include <asm/irq.h>
1da177e4
LT		 87
88/* local include */
89#include "s2io.h"
90#include "s2io-regs.h"
91
11410b62 92#define DRV_VERSION "2.0.26.28"
6c1792f4 93
1da177e4 94/* S2io Driver name & version. */
c0dbf37e
JM		 95static const char s2io_driver_name[] = "Neterion";
96static const char s2io_driver_version[] = DRV_VERSION;
1da177e4 97
c0dbf37e
JM		 98static const int rxd_size[2] = {32, 48};
99static const int rxd_count[2] = {127, 85};
da6971d8 100
1ee6dd77 101static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
5e25b9dd
K		 102{
103 int ret;
104
105 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
d44570e4 106 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
5e25b9dd
K		 107
108 return ret;
109}
110
20346722 111/*
1da177e4
LT		 112 * Cards with following subsystem_id have a link state indication
113 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
114 * macro below identifies these cards given the subsystem_id.
115 */
d44570e4
JP		 116#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
117 (dev_type == XFRAME_I_DEVICE) ? \
118 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
119 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
1da177e4
LT		 120
121#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
122 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
1da177e4 123
d44570e4 124static inline int is_s2io_card_up(const struct s2io_nic *sp)
92b84437
SS		 125{
126 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
127}
128
1da177e4 129/* Ethtool related variables and Macros. */
6fce365d 130static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
1da177e4
LT		 131 "Register test\t(offline)",
132 "Eeprom test\t(offline)",
133 "Link test\t(online)",
134 "RLDRAM test\t(offline)",
135 "BIST Test\t(offline)"
136};
137
6fce365d 138static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
1da177e4
LT		 139 {"tmac_frms"},
140 {"tmac_data_octets"},
141 {"tmac_drop_frms"},
142 {"tmac_mcst_frms"},
143 {"tmac_bcst_frms"},
144 {"tmac_pause_ctrl_frms"},
bd1034f0
AR		 145 {"tmac_ttl_octets"},
146 {"tmac_ucst_frms"},
147 {"tmac_nucst_frms"},
1da177e4 148 {"tmac_any_err_frms"},
bd1034f0 149 {"tmac_ttl_less_fb_octets"},
1da177e4
LT		 150 {"tmac_vld_ip_octets"},
151 {"tmac_vld_ip"},
152 {"tmac_drop_ip"},
153 {"tmac_icmp"},
154 {"tmac_rst_tcp"},
155 {"tmac_tcp"},
156 {"tmac_udp"},
157 {"rmac_vld_frms"},
158 {"rmac_data_octets"},
159 {"rmac_fcs_err_frms"},
160 {"rmac_drop_frms"},
161 {"rmac_vld_mcst_frms"},
162 {"rmac_vld_bcst_frms"},
163 {"rmac_in_rng_len_err_frms"},
bd1034f0 164 {"rmac_out_rng_len_err_frms"},
1da177e4
LT		 165 {"rmac_long_frms"},
166 {"rmac_pause_ctrl_frms"},
bd1034f0
AR		 167 {"rmac_unsup_ctrl_frms"},
168 {"rmac_ttl_octets"},
169 {"rmac_accepted_ucst_frms"},
170 {"rmac_accepted_nucst_frms"},
1da177e4 171 {"rmac_discarded_frms"},
bd1034f0
AR		 172 {"rmac_drop_events"},
173 {"rmac_ttl_less_fb_octets"},
174 {"rmac_ttl_frms"},
1da177e4
LT		 175 {"rmac_usized_frms"},
176 {"rmac_osized_frms"},
177 {"rmac_frag_frms"},
178 {"rmac_jabber_frms"},
bd1034f0
AR		 179 {"rmac_ttl_64_frms"},
180 {"rmac_ttl_65_127_frms"},
181 {"rmac_ttl_128_255_frms"},
182 {"rmac_ttl_256_511_frms"},
183 {"rmac_ttl_512_1023_frms"},
184 {"rmac_ttl_1024_1518_frms"},
1da177e4
LT		 185 {"rmac_ip"},
186 {"rmac_ip_octets"},
187 {"rmac_hdr_err_ip"},
188 {"rmac_drop_ip"},
189 {"rmac_icmp"},
190 {"rmac_tcp"},
191 {"rmac_udp"},
192 {"rmac_err_drp_udp"},
bd1034f0
AR		 193 {"rmac_xgmii_err_sym"},
194 {"rmac_frms_q0"},
195 {"rmac_frms_q1"},
196 {"rmac_frms_q2"},
197 {"rmac_frms_q3"},
198 {"rmac_frms_q4"},
199 {"rmac_frms_q5"},
200 {"rmac_frms_q6"},
201 {"rmac_frms_q7"},
202 {"rmac_full_q0"},
203 {"rmac_full_q1"},
204 {"rmac_full_q2"},
205 {"rmac_full_q3"},
206 {"rmac_full_q4"},
207 {"rmac_full_q5"},
208 {"rmac_full_q6"},
209 {"rmac_full_q7"},
1da177e4 210 {"rmac_pause_cnt"},
bd1034f0
AR		 211 {"rmac_xgmii_data_err_cnt"},
212 {"rmac_xgmii_ctrl_err_cnt"},
1da177e4
LT		 213 {"rmac_accepted_ip"},
214 {"rmac_err_tcp"},
bd1034f0
AR		 215 {"rd_req_cnt"},
216 {"new_rd_req_cnt"},
217 {"new_rd_req_rtry_cnt"},
218 {"rd_rtry_cnt"},
219 {"wr_rtry_rd_ack_cnt"},
220 {"wr_req_cnt"},
221 {"new_wr_req_cnt"},
222 {"new_wr_req_rtry_cnt"},
223 {"wr_rtry_cnt"},
224 {"wr_disc_cnt"},
225 {"rd_rtry_wr_ack_cnt"},
226 {"txp_wr_cnt"},
227 {"txd_rd_cnt"},
228 {"txd_wr_cnt"},
229 {"rxd_rd_cnt"},
230 {"rxd_wr_cnt"},
231 {"txf_rd_cnt"},
fa1f0cb3
SS		 232 {"rxf_wr_cnt"}
233};
234
6fce365d 235static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
bd1034f0
AR		 236 {"rmac_ttl_1519_4095_frms"},
237 {"rmac_ttl_4096_8191_frms"},
238 {"rmac_ttl_8192_max_frms"},
239 {"rmac_ttl_gt_max_frms"},
240 {"rmac_osized_alt_frms"},
241 {"rmac_jabber_alt_frms"},
242 {"rmac_gt_max_alt_frms"},
243 {"rmac_vlan_frms"},
244 {"rmac_len_discard"},
245 {"rmac_fcs_discard"},
246 {"rmac_pf_discard"},
247 {"rmac_da_discard"},
248 {"rmac_red_discard"},
249 {"rmac_rts_discard"},
250 {"rmac_ingm_full_discard"},
fa1f0cb3
SS		 251 {"link_fault_cnt"}
252};
253
6fce365d 254static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
7ba013ac
K		 255 {"\n DRIVER STATISTICS"},
256 {"single_bit_ecc_errs"},
257 {"double_bit_ecc_errs"},
bd1034f0
AR		 258 {"parity_err_cnt"},
259 {"serious_err_cnt"},
260 {"soft_reset_cnt"},
261 {"fifo_full_cnt"},
8116f3cf
SS		 262 {"ring_0_full_cnt"},
263 {"ring_1_full_cnt"},
264 {"ring_2_full_cnt"},
265 {"ring_3_full_cnt"},
266 {"ring_4_full_cnt"},
267 {"ring_5_full_cnt"},
268 {"ring_6_full_cnt"},
269 {"ring_7_full_cnt"},
43b7c451
SH		 270 {"alarm_transceiver_temp_high"},
271 {"alarm_transceiver_temp_low"},
272 {"alarm_laser_bias_current_high"},
273 {"alarm_laser_bias_current_low"},
274 {"alarm_laser_output_power_high"},
275 {"alarm_laser_output_power_low"},
276 {"warn_transceiver_temp_high"},
277 {"warn_transceiver_temp_low"},
278 {"warn_laser_bias_current_high"},
279 {"warn_laser_bias_current_low"},
280 {"warn_laser_output_power_high"},
281 {"warn_laser_output_power_low"},
282 {"lro_aggregated_pkts"},
283 {"lro_flush_both_count"},
284 {"lro_out_of_sequence_pkts"},
285 {"lro_flush_due_to_max_pkts"},
286 {"lro_avg_aggr_pkts"},
287 {"mem_alloc_fail_cnt"},
288 {"pci_map_fail_cnt"},
289 {"watchdog_timer_cnt"},
290 {"mem_allocated"},
291 {"mem_freed"},
292 {"link_up_cnt"},
293 {"link_down_cnt"},
294 {"link_up_time"},
295 {"link_down_time"},
296 {"tx_tcode_buf_abort_cnt"},
297 {"tx_tcode_desc_abort_cnt"},
298 {"tx_tcode_parity_err_cnt"},
299 {"tx_tcode_link_loss_cnt"},
300 {"tx_tcode_list_proc_err_cnt"},
301 {"rx_tcode_parity_err_cnt"},
302 {"rx_tcode_abort_cnt"},
303 {"rx_tcode_parity_abort_cnt"},
304 {"rx_tcode_rda_fail_cnt"},
305 {"rx_tcode_unkn_prot_cnt"},
306 {"rx_tcode_fcs_err_cnt"},
307 {"rx_tcode_buf_size_err_cnt"},
308 {"rx_tcode_rxd_corrupt_cnt"},
309 {"rx_tcode_unkn_err_cnt"},
8116f3cf
SS		 310 {"tda_err_cnt"},
311 {"pfc_err_cnt"},
312 {"pcc_err_cnt"},
313 {"tti_err_cnt"},
314 {"tpa_err_cnt"},
315 {"sm_err_cnt"},
316 {"lso_err_cnt"},
317 {"mac_tmac_err_cnt"},
318 {"mac_rmac_err_cnt"},
319 {"xgxs_txgxs_err_cnt"},
320 {"xgxs_rxgxs_err_cnt"},
321 {"rc_err_cnt"},
322 {"prc_pcix_err_cnt"},
323 {"rpa_err_cnt"},
324 {"rda_err_cnt"},
325 {"rti_err_cnt"},
326 {"mc_err_cnt"}
1da177e4
LT		 327};
328
4c3616cd
AMR		 329#define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
330#define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
331#define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
fa1f0cb3 332
d44570e4
JP		 333#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
334#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
fa1f0cb3 335
d44570e4
JP		 336#define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
337#define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
1da177e4 338
4c3616cd 339#define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
d44570e4 340#define S2IO_STRINGS_LEN (S2IO_TEST_LEN * ETH_GSTRING_LEN)
1da177e4 341
d44570e4
JP		 342#define S2IO_TIMER_CONF(timer, handle, arg, exp) \
343 init_timer(&timer); \
344 timer.function = handle; \
345 timer.data = (unsigned long)arg; \
346 mod_timer(&timer, (jiffies + exp)) \
25fff88e 347
2fd37688
SS		 348/* copy mac addr to def_mac_addr array */
349static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
350{
351 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
352 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
353 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
354 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
355 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
356 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
357}
04025095 358
be3a6b02
K		 359/* Add the vlan */
360static void s2io_vlan_rx_register(struct net_device *dev,
04025095 361 struct vlan_group *grp)
be3a6b02 362{
2fda096d 363 int i;
4cf1653a 364 struct s2io_nic *nic = netdev_priv(dev);
2fda096d 365 unsigned long flags[MAX_TX_FIFOS];
2fda096d 366 struct config_param *config = &nic->config;
ffb5df6c 367 struct mac_info *mac_control = &nic->mac_control;
2fda096d 368
13d866a9
JP		 369 for (i = 0; i < config->tx_fifo_num; i++) {
370 struct fifo_info *fifo = &mac_control->fifos[i];
371
372 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
373 }
be3a6b02 374
be3a6b02 375 nic->vlgrp = grp;
13d866a9
JP		 376
377 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
378 struct fifo_info *fifo = &mac_control->fifos[i];
379
380 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
381 }
be3a6b02
K		 382}
383
cdb5bf02 384/* Unregister the vlan */
04025095 385static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
cdb5bf02
SH		 386{
387 int i;
4cf1653a 388 struct s2io_nic *nic = netdev_priv(dev);
cdb5bf02 389 unsigned long flags[MAX_TX_FIFOS];
cdb5bf02 390 struct config_param *config = &nic->config;
ffb5df6c 391 struct mac_info *mac_control = &nic->mac_control;
cdb5bf02 392
13d866a9
JP		 393 for (i = 0; i < config->tx_fifo_num; i++) {
394 struct fifo_info *fifo = &mac_control->fifos[i];
395
396 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
397 }
cdb5bf02
SH		 398
399 if (nic->vlgrp)
400 vlan_group_set_device(nic->vlgrp, vid, NULL);
401
13d866a9
JP		 402 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
403 struct fifo_info *fifo = &mac_control->fifos[i];
404
405 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
406 }
cdb5bf02
SH		 407}
408
20346722 409/*
1da177e4
LT		 410 * Constants to be programmed into the Xena's registers, to configure
411 * the XAUI.
412 */
413
1da177e4 414#define END_SIGN 0x0
f71e1309 415static const u64 herc_act_dtx_cfg[] = {
541ae68f 416 /* Set address */
e960fc5c 417 0x8000051536750000ULL, 0x80000515367500E0ULL,
541ae68f 418 /* Write data */
e960fc5c 419 0x8000051536750004ULL, 0x80000515367500E4ULL,
541ae68f
K		 420 /* Set address */
421 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
422 /* Write data */
423 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
424 /* Set address */
e960fc5c 425 0x801205150D440000ULL, 0x801205150D4400E0ULL,
426 /* Write data */
427 0x801205150D440004ULL, 0x801205150D4400E4ULL,
428 /* Set address */
541ae68f
K		 429 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
430 /* Write data */
431 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
432 /* Done */
433 END_SIGN
434};
435
f71e1309 436static const u64 xena_dtx_cfg[] = {
c92ca04b 437 /* Set address */
1da177e4 438 0x8000051500000000ULL, 0x80000515000000E0ULL,
c92ca04b
AR		 439 /* Write data */
440 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
441 /* Set address */
442 0x8001051500000000ULL, 0x80010515000000E0ULL,
443 /* Write data */
444 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
445 /* Set address */
1da177e4 446 0x8002051500000000ULL, 0x80020515000000E0ULL,
c92ca04b
AR		 447 /* Write data */
448 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1da177e4
LT		 449 END_SIGN
450};
451
20346722 452/*
1da177e4
LT		 453 * Constants for Fixing the MacAddress problem seen mostly on
454 * Alpha machines.
455 */
f71e1309 456static const u64 fix_mac[] = {
1da177e4
LT		 457 0x0060000000000000ULL, 0x0060600000000000ULL,
458 0x0040600000000000ULL, 0x0000600000000000ULL,
459 0x0020600000000000ULL, 0x0060600000000000ULL,
460 0x0020600000000000ULL, 0x0060600000000000ULL,
461 0x0020600000000000ULL, 0x0060600000000000ULL,
462 0x0020600000000000ULL, 0x0060600000000000ULL,
463 0x0020600000000000ULL, 0x0060600000000000ULL,
464 0x0020600000000000ULL, 0x0060600000000000ULL,
465 0x0020600000000000ULL, 0x0060600000000000ULL,
466 0x0020600000000000ULL, 0x0060600000000000ULL,
467 0x0020600000000000ULL, 0x0060600000000000ULL,
468 0x0020600000000000ULL, 0x0060600000000000ULL,
469 0x0020600000000000ULL, 0x0000600000000000ULL,
470 0x0040600000000000ULL, 0x0060600000000000ULL,
471 END_SIGN
472};
473
b41477f3
AR		 474MODULE_LICENSE("GPL");
475MODULE_VERSION(DRV_VERSION);
476
477
1da177e4 478/* Module Loadable parameters. */
6cfc482b 479S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
b41477f3 480S2IO_PARM_INT(rx_ring_num, 1);
3a3d5756 481S2IO_PARM_INT(multiq, 0);
b41477f3
AR		 482S2IO_PARM_INT(rx_ring_mode, 1);
483S2IO_PARM_INT(use_continuous_tx_intrs, 1);
484S2IO_PARM_INT(rmac_pause_time, 0x100);
485S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
486S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
487S2IO_PARM_INT(shared_splits, 0);
488S2IO_PARM_INT(tmac_util_period, 5);
489S2IO_PARM_INT(rmac_util_period, 5);
b41477f3 490S2IO_PARM_INT(l3l4hdr_size, 128);
6cfc482b
SH		 491/* 0 is no steering, 1 is Priority steering, 2 is Default steering */
492S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
303bcb4b 493/* Frequency of Rx desc syncs expressed as power of 2 */
b41477f3 494S2IO_PARM_INT(rxsync_frequency, 3);
eccb8628 495/* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
8abc4d5b 496S2IO_PARM_INT(intr_type, 2);
7d3d0439 497/* Large receive offload feature */
43b7c451 498
7d3d0439
RA		 499/* Max pkts to be aggregated by LRO at one time. If not specified,
500 * aggregation happens until we hit max IP pkt size(64K)
501 */
b41477f3 502S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
b41477f3 503S2IO_PARM_INT(indicate_max_pkts, 0);
db874e65
SS		 504
505S2IO_PARM_INT(napi, 1);
506S2IO_PARM_INT(ufo, 0);
926930b2 507S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
b41477f3
AR		 508
509static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
d44570e4 510{DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
b41477f3 511static unsigned int rx_ring_sz[MAX_RX_RINGS] =
d44570e4 512{[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
b41477f3 513static unsigned int rts_frm_len[MAX_RX_RINGS] =
d44570e4 514{[0 ...(MAX_RX_RINGS - 1)] = 0 };
b41477f3
AR		 515
516module_param_array(tx_fifo_len, uint, NULL, 0);
517module_param_array(rx_ring_sz, uint, NULL, 0);
518module_param_array(rts_frm_len, uint, NULL, 0);
1da177e4 519
20346722 520/*
1da177e4 521 * S2IO device table.
20346722 522 * This table lists all the devices that this driver supports.
1da177e4 523 */
a3aa1884 524static DEFINE_PCI_DEVICE_TABLE(s2io_tbl) = {
1da177e4
LT		 525 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
526 PCI_ANY_ID, PCI_ANY_ID},
527 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
528 PCI_ANY_ID, PCI_ANY_ID},
529 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
d44570e4
JP		 530 PCI_ANY_ID, PCI_ANY_ID},
531 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
532 PCI_ANY_ID, PCI_ANY_ID},
1da177e4
LT		 533 {0,}
534};
535
536MODULE_DEVICE_TABLE(pci, s2io_tbl);
537
d796fdb7
LV		 538static struct pci_error_handlers s2io_err_handler = {
539 .error_detected = s2io_io_error_detected,
540 .slot_reset = s2io_io_slot_reset,
541 .resume = s2io_io_resume,
542};
543
1da177e4 544static struct pci_driver s2io_driver = {
d44570e4
JP		 545 .name = "S2IO",
546 .id_table = s2io_tbl,
547 .probe = s2io_init_nic,
548 .remove = __devexit_p(s2io_rem_nic),
549 .err_handler = &s2io_err_handler,
1da177e4
LT		 550};
551
552/* A simplifier macro used both by init and free shared_mem Fns(). */
553#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
554
3a3d5756
SH		 555/* netqueue manipulation helper functions */
556static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
557{
fd2ea0a7
DM		 558 if (!sp->config.multiq) {
559 int i;
560
3a3d5756
SH		 561 for (i = 0; i < sp->config.tx_fifo_num; i++)
562 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
3a3d5756 563 }
fd2ea0a7 564 netif_tx_stop_all_queues(sp->dev);
3a3d5756
SH		 565}
566
567static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
568{
fd2ea0a7 569 if (!sp->config.multiq)
3a3d5756
SH		 570 sp->mac_control.fifos[fifo_no].queue_state =
571 FIFO_QUEUE_STOP;
fd2ea0a7
DM		 572
573 netif_tx_stop_all_queues(sp->dev);
3a3d5756
SH		 574}
575
576static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
577{
fd2ea0a7
DM		 578 if (!sp->config.multiq) {
579 int i;
580
3a3d5756
SH		 581 for (i = 0; i < sp->config.tx_fifo_num; i++)
582 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
3a3d5756 583 }
fd2ea0a7 584 netif_tx_start_all_queues(sp->dev);
3a3d5756
SH		 585}
586
587static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
588{
fd2ea0a7 589 if (!sp->config.multiq)
3a3d5756
SH		 590 sp->mac_control.fifos[fifo_no].queue_state =
591 FIFO_QUEUE_START;
fd2ea0a7
DM		 592
593 netif_tx_start_all_queues(sp->dev);
3a3d5756
SH		 594}
595
596static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
597{
fd2ea0a7
DM		 598 if (!sp->config.multiq) {
599 int i;
600
3a3d5756
SH		 601 for (i = 0; i < sp->config.tx_fifo_num; i++)
602 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
3a3d5756 603 }
fd2ea0a7 604 netif_tx_wake_all_queues(sp->dev);
3a3d5756
SH		 605}
606
607static inline void s2io_wake_tx_queue(
608 struct fifo_info *fifo, int cnt, u8 multiq)
609{
610
3a3d5756
SH		 611 if (multiq) {
612 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
613 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
b19fa1fa 614 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
3a3d5756
SH		 615 if (netif_queue_stopped(fifo->dev)) {
616 fifo->queue_state = FIFO_QUEUE_START;
617 netif_wake_queue(fifo->dev);
618 }
619 }
620}
621
1da177e4
LT		 622/**
623 * init_shared_mem - Allocation and Initialization of Memory
624 * @nic: Device private variable.
20346722
K		 625 * Description: The function allocates all the memory areas shared
626 * between the NIC and the driver. This includes Tx descriptors,
1da177e4
LT		 627 * Rx descriptors and the statistics block.
628 */
629
630static int init_shared_mem(struct s2io_nic *nic)
631{
632 u32 size;
633 void *tmp_v_addr, *tmp_v_addr_next;
634 dma_addr_t tmp_p_addr, tmp_p_addr_next;
1ee6dd77 635 struct RxD_block *pre_rxd_blk = NULL;
372cc597 636 int i, j, blk_cnt;
1da177e4
LT		 637 int lst_size, lst_per_page;
638 struct net_device *dev = nic->dev;
8ae418cf 639 unsigned long tmp;
1ee6dd77 640 struct buffAdd *ba;
ffb5df6c
JP		 641 struct config_param *config = &nic->config;
642 struct mac_info *mac_control = &nic->mac_control;
491976b2 643 unsigned long long mem_allocated = 0;
1da177e4 644
13d866a9 645 /* Allocation and initialization of TXDLs in FIFOs */
1da177e4
LT		 646 size = 0;
647 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 648 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
649
650 size += tx_cfg->fifo_len;
1da177e4
LT		 651 }
652 if (size > MAX_AVAILABLE_TXDS) {
9e39f7c5
JP		 653 DBG_PRINT(ERR_DBG,
654 "Too many TxDs requested: %d, max supported: %d\n",
655 size, MAX_AVAILABLE_TXDS);
b41477f3 656 return -EINVAL;
1da177e4
LT		 657 }
658
2fda096d
SR		 659 size = 0;
660 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 661 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
662
663 size = tx_cfg->fifo_len;
2fda096d
SR		 664 /*
665 * Legal values are from 2 to 8192
666 */
667 if (size < 2) {
9e39f7c5
JP		 668 DBG_PRINT(ERR_DBG, "Fifo %d: Invalid length (%d) - "
669 "Valid lengths are 2 through 8192\n",
670 i, size);
2fda096d
SR		 671 return -EINVAL;
672 }
673 }
674
1ee6dd77 675 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 676 lst_per_page = PAGE_SIZE / lst_size;
677
678 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 679 struct fifo_info *fifo = &mac_control->fifos[i];
680 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
681 int fifo_len = tx_cfg->fifo_len;
1ee6dd77 682 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
13d866a9
JP		 683
684 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
685 if (!fifo->list_info) {
d44570e4 686 DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
1da177e4
LT		 687 return -ENOMEM;
688 }
491976b2 689 mem_allocated += list_holder_size;
1da177e4
LT		 690 }
691 for (i = 0; i < config->tx_fifo_num; i++) {
692 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
693 lst_per_page);
13d866a9
JP		 694 struct fifo_info *fifo = &mac_control->fifos[i];
695 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
696
697 fifo->tx_curr_put_info.offset = 0;
698 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
699 fifo->tx_curr_get_info.offset = 0;
700 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
701 fifo->fifo_no = i;
702 fifo->nic = nic;
703 fifo->max_txds = MAX_SKB_FRAGS + 2;
704 fifo->dev = dev;
20346722 705
1da177e4
LT		 706 for (j = 0; j < page_num; j++) {
707 int k = 0;
708 dma_addr_t tmp_p;
709 void *tmp_v;
710 tmp_v = pci_alloc_consistent(nic->pdev,
711 PAGE_SIZE, &tmp_p);
712 if (!tmp_v) {
9e39f7c5
JP		 713 DBG_PRINT(INFO_DBG,
714 "pci_alloc_consistent failed for TxDL\n");
1da177e4
LT		 715 return -ENOMEM;
716 }
776bd20f 717 /* If we got a zero DMA address(can happen on
718 * certain platforms like PPC), reallocate.
719 * Store virtual address of page we don't want,
720 * to be freed later.
721 */
722 if (!tmp_p) {
723 mac_control->zerodma_virt_addr = tmp_v;
6aa20a22 724 DBG_PRINT(INIT_DBG,
9e39f7c5
JP		 725 "%s: Zero DMA address for TxDL. "
726 "Virtual address %p\n",
727 dev->name, tmp_v);
776bd20f 728 tmp_v = pci_alloc_consistent(nic->pdev,
d44570e4 729 PAGE_SIZE, &tmp_p);
776bd20f 730 if (!tmp_v) {
0c61ed5f 731 DBG_PRINT(INFO_DBG,
9e39f7c5 732 "pci_alloc_consistent failed for TxDL\n");
776bd20f 733 return -ENOMEM;
734 }
491976b2 735 mem_allocated += PAGE_SIZE;
776bd20f 736 }
1da177e4
LT		 737 while (k < lst_per_page) {
738 int l = (j * lst_per_page) + k;
13d866a9 739 if (l == tx_cfg->fifo_len)
20346722 740 break;
13d866a9 741 fifo->list_info[l].list_virt_addr =
d44570e4 742 tmp_v + (k * lst_size);
13d866a9 743 fifo->list_info[l].list_phy_addr =
d44570e4 744 tmp_p + (k * lst_size);
1da177e4
LT		 745 k++;
746 }
747 }
748 }
1da177e4 749
2fda096d 750 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 751 struct fifo_info *fifo = &mac_control->fifos[i];
752 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
753
754 size = tx_cfg->fifo_len;
755 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
756 if (!fifo->ufo_in_band_v)
2fda096d
SR		 757 return -ENOMEM;
758 mem_allocated += (size * sizeof(u64));
759 }
fed5eccd 760
1da177e4
LT		 761 /* Allocation and initialization of RXDs in Rings */
762 size = 0;
763 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 764 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
765 struct ring_info *ring = &mac_control->rings[i];
766
767 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
9e39f7c5
JP		 768 DBG_PRINT(ERR_DBG, "%s: Ring%d RxD count is not a "
769 "multiple of RxDs per Block\n",
770 dev->name, i);
1da177e4
LT		 771 return FAILURE;
772 }
13d866a9
JP		 773 size += rx_cfg->num_rxd;
774 ring->block_count = rx_cfg->num_rxd /
d44570e4 775 (rxd_count[nic->rxd_mode] + 1);
13d866a9 776 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
1da177e4 777 }
da6971d8 778 if (nic->rxd_mode == RXD_MODE_1)
1ee6dd77 779 size = (size * (sizeof(struct RxD1)));
da6971d8 780 else
1ee6dd77 781 size = (size * (sizeof(struct RxD3)));
1da177e4
LT		 782
783 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 784 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
785 struct ring_info *ring = &mac_control->rings[i];
786
787 ring->rx_curr_get_info.block_index = 0;
788 ring->rx_curr_get_info.offset = 0;
789 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
790 ring->rx_curr_put_info.block_index = 0;
791 ring->rx_curr_put_info.offset = 0;
792 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
793 ring->nic = nic;
794 ring->ring_no = i;
13d866a9
JP		 795
796 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
1da177e4
LT		 797 /* Allocating all the Rx blocks */
798 for (j = 0; j < blk_cnt; j++) {
1ee6dd77 799 struct rx_block_info *rx_blocks;
da6971d8
AR		 800 int l;
801
13d866a9 802 rx_blocks = &ring->rx_blocks[j];
d44570e4 803 size = SIZE_OF_BLOCK; /* size is always page size */
1da177e4
LT		 804 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
805 &tmp_p_addr);
806 if (tmp_v_addr == NULL) {
807 /*
20346722
K		 808 * In case of failure, free_shared_mem()
809 * is called, which should free any
810 * memory that was alloced till the
1da177e4
LT		 811 * failure happened.
812 */
da6971d8 813 rx_blocks->block_virt_addr = tmp_v_addr;
1da177e4
LT		 814 return -ENOMEM;
815 }
491976b2 816 mem_allocated += size;
1da177e4 817 memset(tmp_v_addr, 0, size);
4f870320
JP		 818
819 size = sizeof(struct rxd_info) *
820 rxd_count[nic->rxd_mode];
da6971d8
AR		 821 rx_blocks->block_virt_addr = tmp_v_addr;
822 rx_blocks->block_dma_addr = tmp_p_addr;
4f870320 823 rx_blocks->rxds = kmalloc(size, GFP_KERNEL);
372cc597
SS		 824 if (!rx_blocks->rxds)
825 return -ENOMEM;
4f870320 826 mem_allocated += size;
d44570e4 827 for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
da6971d8
AR		 828 rx_blocks->rxds[l].virt_addr =
829 rx_blocks->block_virt_addr +
830 (rxd_size[nic->rxd_mode] * l);
831 rx_blocks->rxds[l].dma_addr =
832 rx_blocks->block_dma_addr +
833 (rxd_size[nic->rxd_mode] * l);
834 }
1da177e4
LT		 835 }
836 /* Interlinking all Rx Blocks */
837 for (j = 0; j < blk_cnt; j++) {
13d866a9
JP		 838 int next = (j + 1) % blk_cnt;
839 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
840 tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
841 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
842 tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
1da177e4 843
43d620c8 844 pre_rxd_blk = tmp_v_addr;
1da177e4 845 pre_rxd_blk->reserved_2_pNext_RxD_block =
d44570e4 846 (unsigned long)tmp_v_addr_next;
1da177e4 847 pre_rxd_blk->pNext_RxD_Blk_physical =
d44570e4 848 (u64)tmp_p_addr_next;
1da177e4
LT		 849 }
850 }
6d517a27 851 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 852 /*
853 * Allocation of Storages for buffer addresses in 2BUFF mode
854 * and the buffers as well.
855 */
856 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 857 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
858 struct ring_info *ring = &mac_control->rings[i];
859
860 blk_cnt = rx_cfg->num_rxd /
d44570e4 861 (rxd_count[nic->rxd_mode] + 1);
4f870320
JP		 862 size = sizeof(struct buffAdd *) * blk_cnt;
863 ring->ba = kmalloc(size, GFP_KERNEL);
13d866a9 864 if (!ring->ba)
1da177e4 865 return -ENOMEM;
4f870320 866 mem_allocated += size;
da6971d8
AR		 867 for (j = 0; j < blk_cnt; j++) {
868 int k = 0;
4f870320
JP		 869
870 size = sizeof(struct buffAdd) *
871 (rxd_count[nic->rxd_mode] + 1);
872 ring->ba[j] = kmalloc(size, GFP_KERNEL);
13d866a9 873 if (!ring->ba[j])
1da177e4 874 return -ENOMEM;
4f870320 875 mem_allocated += size;
da6971d8 876 while (k != rxd_count[nic->rxd_mode]) {
13d866a9 877 ba = &ring->ba[j][k];
4f870320
JP		 878 size = BUF0_LEN + ALIGN_SIZE;
879 ba->ba_0_org = kmalloc(size, GFP_KERNEL);
da6971d8
AR		 880 if (!ba->ba_0_org)
881 return -ENOMEM;
4f870320 882 mem_allocated += size;
da6971d8
AR		 883 tmp = (unsigned long)ba->ba_0_org;
884 tmp += ALIGN_SIZE;
d44570e4
JP		 885 tmp &= ~((unsigned long)ALIGN_SIZE);
886 ba->ba_0 = (void *)tmp;
da6971d8 887
4f870320
JP		 888 size = BUF1_LEN + ALIGN_SIZE;
889 ba->ba_1_org = kmalloc(size, GFP_KERNEL);
da6971d8
AR		 890 if (!ba->ba_1_org)
891 return -ENOMEM;
4f870320 892 mem_allocated += size;
d44570e4 893 tmp = (unsigned long)ba->ba_1_org;
da6971d8 894 tmp += ALIGN_SIZE;
d44570e4
JP		 895 tmp &= ~((unsigned long)ALIGN_SIZE);
896 ba->ba_1 = (void *)tmp;
da6971d8
AR		 897 k++;
898 }
1da177e4
LT		 899 }
900 }
901 }
1da177e4
LT		 902
903 /* Allocation and initialization of Statistics block */
1ee6dd77 904 size = sizeof(struct stat_block);
d44570e4
JP		 905 mac_control->stats_mem =
906 pci_alloc_consistent(nic->pdev, size,
907 &mac_control->stats_mem_phy);
1da177e4
LT		 908
909 if (!mac_control->stats_mem) {
20346722
K		 910 /*
911 * In case of failure, free_shared_mem() is called, which
912 * should free any memory that was alloced till the
1da177e4
LT		 913 * failure happened.
914 */
915 return -ENOMEM;
916 }
491976b2 917 mem_allocated += size;
1da177e4
LT		 918 mac_control->stats_mem_sz = size;
919
920 tmp_v_addr = mac_control->stats_mem;
43d620c8 921 mac_control->stats_info = tmp_v_addr;
1da177e4 922 memset(tmp_v_addr, 0, size);
3a22813a
BL		 923 DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n",
924 dev_name(&nic->pdev->dev), (unsigned long long)tmp_p_addr);
491976b2 925 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
1da177e4
LT		 926 return SUCCESS;
927}
928
20346722
K		 929/**
930 * free_shared_mem - Free the allocated Memory
1da177e4
LT		 931 * @nic: Device private variable.
932 * Description: This function is to free all memory locations allocated by
933 * the init_shared_mem() function and return it to the kernel.
934 */
935
936static void free_shared_mem(struct s2io_nic *nic)
937{
938 int i, j, blk_cnt, size;
939 void *tmp_v_addr;
940 dma_addr_t tmp_p_addr;
1da177e4 941 int lst_size, lst_per_page;
8910b49f 942 struct net_device *dev;
491976b2 943 int page_num = 0;
ffb5df6c
JP		 944 struct config_param *config;
945 struct mac_info *mac_control;
946 struct stat_block *stats;
947 struct swStat *swstats;
1da177e4
LT		 948
949 if (!nic)
950 return;
951
8910b49f
MG		 952 dev = nic->dev;
953
1da177e4 954 config = &nic->config;
ffb5df6c
JP		 955 mac_control = &nic->mac_control;
956 stats = mac_control->stats_info;
957 swstats = &stats->sw_stat;
1da177e4 958
d44570e4 959 lst_size = sizeof(struct TxD) * config->max_txds;
1da177e4
LT		 960 lst_per_page = PAGE_SIZE / lst_size;
961
962 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 963 struct fifo_info *fifo = &mac_control->fifos[i];
964 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
965
966 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
1da177e4
LT		 967 for (j = 0; j < page_num; j++) {
968 int mem_blks = (j * lst_per_page);
13d866a9
JP		 969 struct list_info_hold *fli;
970
971 if (!fifo->list_info)
6aa20a22 972 return;
13d866a9
JP		 973
974 fli = &fifo->list_info[mem_blks];
975 if (!fli->list_virt_addr)
1da177e4
LT		 976 break;
977 pci_free_consistent(nic->pdev, PAGE_SIZE,
13d866a9
JP		 978 fli->list_virt_addr,
979 fli->list_phy_addr);
ffb5df6c 980 swstats->mem_freed += PAGE_SIZE;
1da177e4 981 }
776bd20f 982 /* If we got a zero DMA address during allocation,
983 * free the page now
984 */
985 if (mac_control->zerodma_virt_addr) {
986 pci_free_consistent(nic->pdev, PAGE_SIZE,
987 mac_control->zerodma_virt_addr,
988 (dma_addr_t)0);
6aa20a22 989 DBG_PRINT(INIT_DBG,
9e39f7c5
JP		 990 "%s: Freeing TxDL with zero DMA address. "
991 "Virtual address %p\n",
992 dev->name, mac_control->zerodma_virt_addr);
ffb5df6c 993 swstats->mem_freed += PAGE_SIZE;
776bd20f 994 }
13d866a9 995 kfree(fifo->list_info);
82c2d023 996 swstats->mem_freed += tx_cfg->fifo_len *
d44570e4 997 sizeof(struct list_info_hold);
1da177e4
LT		 998 }
999
1da177e4 1000 size = SIZE_OF_BLOCK;
1da177e4 1001 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1002 struct ring_info *ring = &mac_control->rings[i];
1003
1004 blk_cnt = ring->block_count;
1da177e4 1005 for (j = 0; j < blk_cnt; j++) {
13d866a9
JP		 1006 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
1007 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
1da177e4
LT		 1008 if (tmp_v_addr == NULL)
1009 break;
1010 pci_free_consistent(nic->pdev, size,
1011 tmp_v_addr, tmp_p_addr);
ffb5df6c 1012 swstats->mem_freed += size;
13d866a9 1013 kfree(ring->rx_blocks[j].rxds);
ffb5df6c
JP		 1014 swstats->mem_freed += sizeof(struct rxd_info) *
1015 rxd_count[nic->rxd_mode];
1da177e4
LT		 1016 }
1017 }
1018
6d517a27 1019 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 1020 /* Freeing buffer storage addresses in 2BUFF mode. */
1021 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1022 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1023 struct ring_info *ring = &mac_control->rings[i];
1024
1025 blk_cnt = rx_cfg->num_rxd /
1026 (rxd_count[nic->rxd_mode] + 1);
da6971d8
AR		 1027 for (j = 0; j < blk_cnt; j++) {
1028 int k = 0;
13d866a9 1029 if (!ring->ba[j])
da6971d8
AR		 1030 continue;
1031 while (k != rxd_count[nic->rxd_mode]) {
13d866a9 1032 struct buffAdd *ba = &ring->ba[j][k];
da6971d8 1033 kfree(ba->ba_0_org);
ffb5df6c
JP		 1034 swstats->mem_freed +=
1035 BUF0_LEN + ALIGN_SIZE;
da6971d8 1036 kfree(ba->ba_1_org);
ffb5df6c
JP		 1037 swstats->mem_freed +=
1038 BUF1_LEN + ALIGN_SIZE;
da6971d8
AR		 1039 k++;
1040 }
13d866a9 1041 kfree(ring->ba[j]);
ffb5df6c
JP		 1042 swstats->mem_freed += sizeof(struct buffAdd) *
1043 (rxd_count[nic->rxd_mode] + 1);
1da177e4 1044 }
13d866a9 1045 kfree(ring->ba);
ffb5df6c
JP		 1046 swstats->mem_freed += sizeof(struct buffAdd *) *
1047 blk_cnt;
1da177e4 1048 }
1da177e4 1049 }
1da177e4 1050
2fda096d 1051 for (i = 0; i < nic->config.tx_fifo_num; i++) {
13d866a9
JP		 1052 struct fifo_info *fifo = &mac_control->fifos[i];
1053 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1054
1055 if (fifo->ufo_in_band_v) {
ffb5df6c
JP		 1056 swstats->mem_freed += tx_cfg->fifo_len *
1057 sizeof(u64);
13d866a9 1058 kfree(fifo->ufo_in_band_v);
2fda096d
SR		 1059 }
1060 }
1061
1da177e4 1062 if (mac_control->stats_mem) {
ffb5df6c 1063 swstats->mem_freed += mac_control->stats_mem_sz;
1da177e4
LT		 1064 pci_free_consistent(nic->pdev,
1065 mac_control->stats_mem_sz,
1066 mac_control->stats_mem,
1067 mac_control->stats_mem_phy);
491976b2 1068 }
1da177e4
LT		 1069}
1070
541ae68f
K		 1071/**
1072 * s2io_verify_pci_mode -
1073 */
1074
1ee6dd77 1075static int s2io_verify_pci_mode(struct s2io_nic *nic)
541ae68f 1076{
1ee6dd77 1077 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 1078 register u64 val64 = 0;
1079 int mode;
1080
1081 val64 = readq(&bar0->pci_mode);
1082 mode = (u8)GET_PCI_MODE(val64);
1083
d44570e4 1084 if (val64 & PCI_MODE_UNKNOWN_MODE)
541ae68f
K		 1085 return -1; /* Unknown PCI mode */
1086 return mode;
1087}
1088
c92ca04b
AR		 1089#define NEC_VENID 0x1033
1090#define NEC_DEVID 0x0125
1091static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1092{
1093 struct pci_dev *tdev = NULL;
26d36b64
AC		 1094 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1095 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
7ad62dbc 1096 if (tdev->bus == s2io_pdev->bus->parent) {
26d36b64 1097 pci_dev_put(tdev);
c92ca04b 1098 return 1;
7ad62dbc 1099 }
c92ca04b
AR		 1100 }
1101 }
1102 return 0;
1103}
541ae68f 1104
7b32a312 1105static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
541ae68f
K		 1106/**
1107 * s2io_print_pci_mode -
1108 */
1ee6dd77 1109static int s2io_print_pci_mode(struct s2io_nic *nic)
541ae68f 1110{
1ee6dd77 1111 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 1112 register u64 val64 = 0;
1113 int mode;
1114 struct config_param *config = &nic->config;
9e39f7c5 1115 const char *pcimode;
541ae68f
K		 1116
1117 val64 = readq(&bar0->pci_mode);
1118 mode = (u8)GET_PCI_MODE(val64);
1119
d44570e4 1120 if (val64 & PCI_MODE_UNKNOWN_MODE)
541ae68f
K		 1121 return -1; /* Unknown PCI mode */
1122
c92ca04b
AR		 1123 config->bus_speed = bus_speed[mode];
1124
1125 if (s2io_on_nec_bridge(nic->pdev)) {
1126 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
d44570e4 1127 nic->dev->name);
c92ca04b
AR		 1128 return mode;
1129 }
1130
d44570e4
JP		 1131 switch (mode) {
1132 case PCI_MODE_PCI_33:
9e39f7c5 1133 pcimode = "33MHz PCI bus";
d44570e4
JP		 1134 break;
1135 case PCI_MODE_PCI_66:
9e39f7c5 1136 pcimode = "66MHz PCI bus";
d44570e4
JP		 1137 break;
1138 case PCI_MODE_PCIX_M1_66:
9e39f7c5 1139 pcimode = "66MHz PCIX(M1) bus";
d44570e4
JP		 1140 break;
1141 case PCI_MODE_PCIX_M1_100:
9e39f7c5 1142 pcimode = "100MHz PCIX(M1) bus";
d44570e4
JP		 1143 break;
1144 case PCI_MODE_PCIX_M1_133:
9e39f7c5 1145 pcimode = "133MHz PCIX(M1) bus";
d44570e4
JP		 1146 break;
1147 case PCI_MODE_PCIX_M2_66:
9e39f7c5 1148 pcimode = "133MHz PCIX(M2) bus";
d44570e4
JP		 1149 break;
1150 case PCI_MODE_PCIX_M2_100:
9e39f7c5 1151 pcimode = "200MHz PCIX(M2) bus";
d44570e4
JP		 1152 break;
1153 case PCI_MODE_PCIX_M2_133:
9e39f7c5 1154 pcimode = "266MHz PCIX(M2) bus";
d44570e4
JP		 1155 break;
1156 default:
9e39f7c5
JP		 1157 pcimode = "unsupported bus!";
1158 mode = -1;
541ae68f
K		 1159 }
1160
9e39f7c5
JP		 1161 DBG_PRINT(ERR_DBG, "%s: Device is on %d bit %s\n",
1162 nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode);
1163
541ae68f
K		 1164 return mode;
1165}
1166
b7c5678f
RV		 1167/**
1168 * init_tti - Initialization transmit traffic interrupt scheme
1169 * @nic: device private variable
1170 * @link: link status (UP/DOWN) used to enable/disable continuous
1171 * transmit interrupts
1172 * Description: The function configures transmit traffic interrupts
1173 * Return Value: SUCCESS on success and
1174 * '-1' on failure
1175 */
1176
0d66afe7 1177static int init_tti(struct s2io_nic *nic, int link)
b7c5678f
RV		 1178{
1179 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1180 register u64 val64 = 0;
1181 int i;
ffb5df6c 1182 struct config_param *config = &nic->config;
b7c5678f
RV		 1183
1184 for (i = 0; i < config->tx_fifo_num; i++) {
1185 /*
1186 * TTI Initialization. Default Tx timer gets us about
1187 * 250 interrupts per sec. Continuous interrupts are enabled
1188 * by default.
1189 */
1190 if (nic->device_type == XFRAME_II_DEVICE) {
1191 int count = (nic->config.bus_speed * 125)/2;
1192 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1193 } else
1194 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1195
1196 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
d44570e4
JP		 1197 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1198 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1199 TTI_DATA1_MEM_TX_TIMER_AC_EN;
ac731ab6
SH		 1200 if (i == 0)
1201 if (use_continuous_tx_intrs && (link == LINK_UP))
1202 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
b7c5678f
RV		 1203 writeq(val64, &bar0->tti_data1_mem);
1204
ac731ab6
SH		 1205 if (nic->config.intr_type == MSI_X) {
1206 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1207 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1208 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1209 TTI_DATA2_MEM_TX_UFC_D(0x300);
1210 } else {
1211 if ((nic->config.tx_steering_type ==
d44570e4
JP		 1212 TX_DEFAULT_STEERING) &&
1213 (config->tx_fifo_num > 1) &&
1214 (i >= nic->udp_fifo_idx) &&
1215 (i < (nic->udp_fifo_idx +
1216 nic->total_udp_fifos)))
ac731ab6
SH		 1217 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1218 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1219 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1220 TTI_DATA2_MEM_TX_UFC_D(0x120);
1221 else
1222 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1223 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1224 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1225 TTI_DATA2_MEM_TX_UFC_D(0x80);
1226 }
b7c5678f
RV		 1227
1228 writeq(val64, &bar0->tti_data2_mem);
1229
d44570e4
JP		 1230 val64 = TTI_CMD_MEM_WE |
1231 TTI_CMD_MEM_STROBE_NEW_CMD |
1232 TTI_CMD_MEM_OFFSET(i);
b7c5678f
RV		 1233 writeq(val64, &bar0->tti_command_mem);
1234
1235 if (wait_for_cmd_complete(&bar0->tti_command_mem,
d44570e4
JP		 1236 TTI_CMD_MEM_STROBE_NEW_CMD,
1237 S2IO_BIT_RESET) != SUCCESS)
b7c5678f
RV		 1238 return FAILURE;
1239 }
1240
1241 return SUCCESS;
1242}
1243
20346722
K		 1244/**
1245 * init_nic - Initialization of hardware
b7c5678f 1246 * @nic: device private variable
20346722
K		 1247 * Description: The function sequentially configures every block
1248 * of the H/W from their reset values.
1249 * Return Value: SUCCESS on success and
1da177e4
LT		 1250 * '-1' on failure (endian settings incorrect).
1251 */
1252
1253static int init_nic(struct s2io_nic *nic)
1254{
1ee6dd77 1255 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1256 struct net_device *dev = nic->dev;
1257 register u64 val64 = 0;
1258 void __iomem *add;
1259 u32 time;
1260 int i, j;
c92ca04b 1261 int dtx_cnt = 0;
1da177e4 1262 unsigned long long mem_share;
20346722 1263 int mem_size;
ffb5df6c
JP		 1264 struct config_param *config = &nic->config;
1265 struct mac_info *mac_control = &nic->mac_control;
1da177e4 1266
5e25b9dd 1267 /* to set the swapper controle on the card */
d44570e4
JP		 1268 if (s2io_set_swapper(nic)) {
1269 DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
9f74ffde 1270 return -EIO;
1da177e4
LT		 1271 }
1272
541ae68f
K		 1273 /*
1274 * Herc requires EOI to be removed from reset before XGXS, so..
1275 */
1276 if (nic->device_type & XFRAME_II_DEVICE) {
1277 val64 = 0xA500000000ULL;
1278 writeq(val64, &bar0->sw_reset);
1279 msleep(500);
1280 val64 = readq(&bar0->sw_reset);
1281 }
1282
1da177e4
LT		 1283 /* Remove XGXS from reset state */
1284 val64 = 0;
1285 writeq(val64, &bar0->sw_reset);
1da177e4 1286 msleep(500);
20346722 1287 val64 = readq(&bar0->sw_reset);
1da177e4 1288
7962024e
SH		 1289 /* Ensure that it's safe to access registers by checking
1290 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1291 */
1292 if (nic->device_type == XFRAME_II_DEVICE) {
1293 for (i = 0; i < 50; i++) {
1294 val64 = readq(&bar0->adapter_status);
1295 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1296 break;
1297 msleep(10);
1298 }
1299 if (i == 50)
1300 return -ENODEV;
1301 }
1302
1da177e4
LT		 1303 /* Enable Receiving broadcasts */
1304 add = &bar0->mac_cfg;
1305 val64 = readq(&bar0->mac_cfg);
1306 val64 |= MAC_RMAC_BCAST_ENABLE;
1307 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 1308 writel((u32)val64, add);
1da177e4
LT		 1309 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1310 writel((u32) (val64 >> 32), (add + 4));
1311
1312 /* Read registers in all blocks */
1313 val64 = readq(&bar0->mac_int_mask);
1314 val64 = readq(&bar0->mc_int_mask);
1315 val64 = readq(&bar0->xgxs_int_mask);
1316
1317 /* Set MTU */
1318 val64 = dev->mtu;
1319 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1320
541ae68f
K		 1321 if (nic->device_type & XFRAME_II_DEVICE) {
1322 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
303bcb4b 1323 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1da177e4 1324 &bar0->dtx_control, UF);
541ae68f
K		 1325 if (dtx_cnt & 0x1)
1326 msleep(1); /* Necessary!! */
1da177e4
LT		 1327 dtx_cnt++;
1328 }
541ae68f 1329 } else {
c92ca04b
AR		 1330 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1331 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1332 &bar0->dtx_control, UF);
1333 val64 = readq(&bar0->dtx_control);
1334 dtx_cnt++;
1da177e4
LT		 1335 }
1336 }
1337
1338 /* Tx DMA Initialization */
1339 val64 = 0;
1340 writeq(val64, &bar0->tx_fifo_partition_0);
1341 writeq(val64, &bar0->tx_fifo_partition_1);
1342 writeq(val64, &bar0->tx_fifo_partition_2);
1343 writeq(val64, &bar0->tx_fifo_partition_3);
1344
1da177e4 1345 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 1346 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1347
1348 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1349 vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1da177e4
LT		 1350
1351 if (i == (config->tx_fifo_num - 1)) {
1352 if (i % 2 == 0)
1353 i++;
1354 }
1355
1356 switch (i) {
1357 case 1:
1358 writeq(val64, &bar0->tx_fifo_partition_0);
1359 val64 = 0;
b7c5678f 1360 j = 0;
1da177e4
LT		 1361 break;
1362 case 3:
1363 writeq(val64, &bar0->tx_fifo_partition_1);
1364 val64 = 0;
b7c5678f 1365 j = 0;
1da177e4
LT		 1366 break;
1367 case 5:
1368 writeq(val64, &bar0->tx_fifo_partition_2);
1369 val64 = 0;
b7c5678f 1370 j = 0;
1da177e4
LT		 1371 break;
1372 case 7:
1373 writeq(val64, &bar0->tx_fifo_partition_3);
b7c5678f
RV		 1374 val64 = 0;
1375 j = 0;
1376 break;
1377 default:
1378 j++;
1da177e4
LT		 1379 break;
1380 }
1381 }
1382
5e25b9dd
K		 1383 /*
1384 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1385 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1386 */
d44570e4 1387 if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
5e25b9dd
K		 1388 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1389
1da177e4
LT		 1390 val64 = readq(&bar0->tx_fifo_partition_0);
1391 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
d44570e4 1392 &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1da177e4 1393
20346722
K		 1394 /*
1395 * Initialization of Tx_PA_CONFIG register to ignore packet
1da177e4
LT		 1396 * integrity checking.
1397 */
1398 val64 = readq(&bar0->tx_pa_cfg);
d44570e4
JP		 1399 val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1400 TX_PA_CFG_IGNORE_SNAP_OUI |
1401 TX_PA_CFG_IGNORE_LLC_CTRL |
1402 TX_PA_CFG_IGNORE_L2_ERR;
1da177e4
LT		 1403 writeq(val64, &bar0->tx_pa_cfg);
1404
1405 /* Rx DMA intialization. */
1406 val64 = 0;
1407 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1408 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1409
1410 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1da177e4
LT		 1411 }
1412 writeq(val64, &bar0->rx_queue_priority);
1413
20346722
K		 1414 /*
1415 * Allocating equal share of memory to all the
1da177e4
LT		 1416 * configured Rings.
1417 */
1418 val64 = 0;
541ae68f
K		 1419 if (nic->device_type & XFRAME_II_DEVICE)
1420 mem_size = 32;
1421 else
1422 mem_size = 64;
1423
1da177e4
LT		 1424 for (i = 0; i < config->rx_ring_num; i++) {
1425 switch (i) {
1426 case 0:
20346722
K		 1427 mem_share = (mem_size / config->rx_ring_num +
1428 mem_size % config->rx_ring_num);
1da177e4
LT		 1429 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1430 continue;
1431 case 1:
20346722 1432 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1433 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1434 continue;
1435 case 2:
20346722 1436 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1437 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1438 continue;
1439 case 3:
20346722 1440 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1441 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1442 continue;
1443 case 4:
20346722 1444 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1445 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1446 continue;
1447 case 5:
20346722 1448 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1449 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1450 continue;
1451 case 6:
20346722 1452 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1453 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1454 continue;
1455 case 7:
20346722 1456 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1457 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1458 continue;
1459 }
1460 }
1461 writeq(val64, &bar0->rx_queue_cfg);
1462
20346722 1463 /*
5e25b9dd 1464 * Filling Tx round robin registers
b7c5678f 1465 * as per the number of FIFOs for equal scheduling priority
1da177e4 1466 */
5e25b9dd
K		 1467 switch (config->tx_fifo_num) {
1468 case 1:
b7c5678f 1469 val64 = 0x0;
5e25b9dd
K		 1470 writeq(val64, &bar0->tx_w_round_robin_0);
1471 writeq(val64, &bar0->tx_w_round_robin_1);
1472 writeq(val64, &bar0->tx_w_round_robin_2);
1473 writeq(val64, &bar0->tx_w_round_robin_3);
1474 writeq(val64, &bar0->tx_w_round_robin_4);
1475 break;
1476 case 2:
b7c5678f 1477 val64 = 0x0001000100010001ULL;
5e25b9dd 1478 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1479 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1480 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1481 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1482 val64 = 0x0001000100000000ULL;
5e25b9dd
K		 1483 writeq(val64, &bar0->tx_w_round_robin_4);
1484 break;
1485 case 3:
b7c5678f 1486 val64 = 0x0001020001020001ULL;
5e25b9dd 1487 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1488 val64 = 0x0200010200010200ULL;
5e25b9dd 1489 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1490 val64 = 0x0102000102000102ULL;
5e25b9dd 1491 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1492 val64 = 0x0001020001020001ULL;
5e25b9dd 1493 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1494 val64 = 0x0200010200000000ULL;
5e25b9dd
K		 1495 writeq(val64, &bar0->tx_w_round_robin_4);
1496 break;
1497 case 4:
b7c5678f 1498 val64 = 0x0001020300010203ULL;
5e25b9dd 1499 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1500 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1501 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1502 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1503 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1504 writeq(val64, &bar0->tx_w_round_robin_4);
1505 break;
1506 case 5:
b7c5678f 1507 val64 = 0x0001020304000102ULL;
5e25b9dd 1508 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1509 val64 = 0x0304000102030400ULL;
5e25b9dd 1510 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1511 val64 = 0x0102030400010203ULL;
5e25b9dd 1512 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1513 val64 = 0x0400010203040001ULL;
5e25b9dd 1514 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1515 val64 = 0x0203040000000000ULL;
5e25b9dd
K		 1516 writeq(val64, &bar0->tx_w_round_robin_4);
1517 break;
1518 case 6:
b7c5678f 1519 val64 = 0x0001020304050001ULL;
5e25b9dd 1520 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1521 val64 = 0x0203040500010203ULL;
5e25b9dd 1522 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1523 val64 = 0x0405000102030405ULL;
5e25b9dd 1524 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1525 val64 = 0x0001020304050001ULL;
5e25b9dd 1526 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1527 val64 = 0x0203040500000000ULL;
5e25b9dd
K		 1528 writeq(val64, &bar0->tx_w_round_robin_4);
1529 break;
1530 case 7:
b7c5678f 1531 val64 = 0x0001020304050600ULL;
5e25b9dd 1532 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1533 val64 = 0x0102030405060001ULL;
5e25b9dd 1534 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1535 val64 = 0x0203040506000102ULL;
5e25b9dd 1536 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1537 val64 = 0x0304050600010203ULL;
5e25b9dd 1538 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1539 val64 = 0x0405060000000000ULL;
5e25b9dd
K		 1540 writeq(val64, &bar0->tx_w_round_robin_4);
1541 break;
1542 case 8:
b7c5678f 1543 val64 = 0x0001020304050607ULL;
5e25b9dd 1544 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1545 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1546 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1547 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1548 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1549 writeq(val64, &bar0->tx_w_round_robin_4);
1550 break;
1551 }
1552
b41477f3 1553 /* Enable all configured Tx FIFO partitions */
5d3213cc
AR		 1554 val64 = readq(&bar0->tx_fifo_partition_0);
1555 val64 |= (TX_FIFO_PARTITION_EN);
1556 writeq(val64, &bar0->tx_fifo_partition_0);
1557
5e25b9dd 1558 /* Filling the Rx round robin registers as per the
0425b46a
SH		 1559 * number of Rings and steering based on QoS with
1560 * equal priority.
1561 */
5e25b9dd
K		 1562 switch (config->rx_ring_num) {
1563 case 1:
0425b46a
SH		 1564 val64 = 0x0;
1565 writeq(val64, &bar0->rx_w_round_robin_0);
1566 writeq(val64, &bar0->rx_w_round_robin_1);
1567 writeq(val64, &bar0->rx_w_round_robin_2);
1568 writeq(val64, &bar0->rx_w_round_robin_3);
1569 writeq(val64, &bar0->rx_w_round_robin_4);
1570
5e25b9dd
K		 1571 val64 = 0x8080808080808080ULL;
1572 writeq(val64, &bar0->rts_qos_steering);
1573 break;
1574 case 2:
0425b46a 1575 val64 = 0x0001000100010001ULL;
5e25b9dd 1576 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1577 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1578 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1579 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1580 val64 = 0x0001000100000000ULL;
5e25b9dd
K		 1581 writeq(val64, &bar0->rx_w_round_robin_4);
1582
1583 val64 = 0x8080808040404040ULL;
1584 writeq(val64, &bar0->rts_qos_steering);
1585 break;
1586 case 3:
0425b46a 1587 val64 = 0x0001020001020001ULL;
5e25b9dd 1588 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1589 val64 = 0x0200010200010200ULL;
5e25b9dd 1590 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1591 val64 = 0x0102000102000102ULL;
5e25b9dd 1592 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1593 val64 = 0x0001020001020001ULL;
5e25b9dd 1594 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1595 val64 = 0x0200010200000000ULL;
5e25b9dd
K		 1596 writeq(val64, &bar0->rx_w_round_robin_4);
1597
1598 val64 = 0x8080804040402020ULL;
1599 writeq(val64, &bar0->rts_qos_steering);
1600 break;
1601 case 4:
0425b46a 1602 val64 = 0x0001020300010203ULL;
5e25b9dd 1603 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1604 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1605 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1606 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1607 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1608 writeq(val64, &bar0->rx_w_round_robin_4);
1609
1610 val64 = 0x8080404020201010ULL;
1611 writeq(val64, &bar0->rts_qos_steering);
1612 break;
1613 case 5:
0425b46a 1614 val64 = 0x0001020304000102ULL;
5e25b9dd 1615 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1616 val64 = 0x0304000102030400ULL;
5e25b9dd 1617 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1618 val64 = 0x0102030400010203ULL;
5e25b9dd 1619 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1620 val64 = 0x0400010203040001ULL;
5e25b9dd 1621 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1622 val64 = 0x0203040000000000ULL;
5e25b9dd
K		 1623 writeq(val64, &bar0->rx_w_round_robin_4);
1624
1625 val64 = 0x8080404020201008ULL;
1626 writeq(val64, &bar0->rts_qos_steering);
1627 break;
1628 case 6:
0425b46a 1629 val64 = 0x0001020304050001ULL;
5e25b9dd 1630 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1631 val64 = 0x0203040500010203ULL;
5e25b9dd 1632 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1633 val64 = 0x0405000102030405ULL;
5e25b9dd 1634 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1635 val64 = 0x0001020304050001ULL;
5e25b9dd 1636 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1637 val64 = 0x0203040500000000ULL;
5e25b9dd
K		 1638 writeq(val64, &bar0->rx_w_round_robin_4);
1639
1640 val64 = 0x8080404020100804ULL;
1641 writeq(val64, &bar0->rts_qos_steering);
1642 break;
1643 case 7:
0425b46a 1644 val64 = 0x0001020304050600ULL;
5e25b9dd 1645 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1646 val64 = 0x0102030405060001ULL;
5e25b9dd 1647 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1648 val64 = 0x0203040506000102ULL;
5e25b9dd 1649 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1650 val64 = 0x0304050600010203ULL;
5e25b9dd 1651 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1652 val64 = 0x0405060000000000ULL;
5e25b9dd
K		 1653 writeq(val64, &bar0->rx_w_round_robin_4);
1654
1655 val64 = 0x8080402010080402ULL;
1656 writeq(val64, &bar0->rts_qos_steering);
1657 break;
1658 case 8:
0425b46a 1659 val64 = 0x0001020304050607ULL;
5e25b9dd 1660 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1661 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1662 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1663 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1664 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1665 writeq(val64, &bar0->rx_w_round_robin_4);
1666
1667 val64 = 0x8040201008040201ULL;
1668 writeq(val64, &bar0->rts_qos_steering);
1669 break;
1670 }
1da177e4
LT		 1671
1672 /* UDP Fix */
1673 val64 = 0;
20346722 1674 for (i = 0; i < 8; i++)
1da177e4
LT		 1675 writeq(val64, &bar0->rts_frm_len_n[i]);
1676
5e25b9dd
K		 1677 /* Set the default rts frame length for the rings configured */
1678 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1679 for (i = 0 ; i < config->rx_ring_num ; i++)
1680 writeq(val64, &bar0->rts_frm_len_n[i]);
1681
1682 /* Set the frame length for the configured rings
1683 * desired by the user
1684 */
1685 for (i = 0; i < config->rx_ring_num; i++) {
1686 /* If rts_frm_len[i] == 0 then it is assumed that user not
1687 * specified frame length steering.
1688 * If the user provides the frame length then program
1689 * the rts_frm_len register for those values or else
1690 * leave it as it is.
1691 */
1692 if (rts_frm_len[i] != 0) {
1693 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
d44570e4 1694 &bar0->rts_frm_len_n[i]);
5e25b9dd
K		 1695 }
1696 }
8a4bdbaa 1697
9fc93a41
SS		 1698 /* Disable differentiated services steering logic */
1699 for (i = 0; i < 64; i++) {
1700 if (rts_ds_steer(nic, i, 0) == FAILURE) {
9e39f7c5
JP		 1701 DBG_PRINT(ERR_DBG,
1702 "%s: rts_ds_steer failed on codepoint %d\n",
1703 dev->name, i);
9f74ffde 1704 return -ENODEV;
9fc93a41
SS		 1705 }
1706 }
1707
20346722 1708 /* Program statistics memory */
1da177e4 1709 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1da177e4 1710
541ae68f
K		 1711 if (nic->device_type == XFRAME_II_DEVICE) {
1712 val64 = STAT_BC(0x320);
1713 writeq(val64, &bar0->stat_byte_cnt);
1714 }
1715
20346722 1716 /*
1da177e4
LT		 1717 * Initializing the sampling rate for the device to calculate the
1718 * bandwidth utilization.
1719 */
1720 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
d44570e4 1721 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1da177e4
LT		 1722 writeq(val64, &bar0->mac_link_util);
1723
20346722
K		 1724 /*
1725 * Initializing the Transmit and Receive Traffic Interrupt
1da177e4
LT		 1726 * Scheme.
1727 */
1da177e4 1728
b7c5678f
RV		 1729 /* Initialize TTI */
1730 if (SUCCESS != init_tti(nic, nic->last_link_state))
1731 return -ENODEV;
1da177e4 1732
8a4bdbaa
SS		 1733 /* RTI Initialization */
1734 if (nic->device_type == XFRAME_II_DEVICE) {
541ae68f 1735 /*
8a4bdbaa
SS		 1736 * Programmed to generate Apprx 500 Intrs per
1737 * second
1738 */
1739 int count = (nic->config.bus_speed * 125)/4;
1740 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1741 } else
1742 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1743 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
d44570e4
JP		 1744 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1745 RTI_DATA1_MEM_RX_URNG_C(0x30) |
1746 RTI_DATA1_MEM_RX_TIMER_AC_EN;
8a4bdbaa
SS		 1747
1748 writeq(val64, &bar0->rti_data1_mem);
1749
1750 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1751 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1752 if (nic->config.intr_type == MSI_X)
d44570e4
JP		 1753 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1754 RTI_DATA2_MEM_RX_UFC_D(0x40));
8a4bdbaa 1755 else
d44570e4
JP		 1756 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1757 RTI_DATA2_MEM_RX_UFC_D(0x80));
8a4bdbaa 1758 writeq(val64, &bar0->rti_data2_mem);
1da177e4 1759
8a4bdbaa 1760 for (i = 0; i < config->rx_ring_num; i++) {
d44570e4
JP		 1761 val64 = RTI_CMD_MEM_WE |
1762 RTI_CMD_MEM_STROBE_NEW_CMD |
1763 RTI_CMD_MEM_OFFSET(i);
8a4bdbaa 1764 writeq(val64, &bar0->rti_command_mem);
1da177e4 1765
8a4bdbaa
SS		 1766 /*
1767 * Once the operation completes, the Strobe bit of the
1768 * command register will be reset. We poll for this
1769 * particular condition. We wait for a maximum of 500ms
1770 * for the operation to complete, if it's not complete
1771 * by then we return error.
1772 */
1773 time = 0;
f957bcf0 1774 while (true) {
8a4bdbaa
SS		 1775 val64 = readq(&bar0->rti_command_mem);
1776 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1777 break;
b6e3f982 1778
8a4bdbaa 1779 if (time > 10) {
9e39f7c5 1780 DBG_PRINT(ERR_DBG, "%s: RTI init failed\n",
8a4bdbaa 1781 dev->name);
9f74ffde 1782 return -ENODEV;
b6e3f982 1783 }
8a4bdbaa
SS		 1784 time++;
1785 msleep(50);
1da177e4 1786 }
1da177e4
LT		 1787 }
1788
20346722
K		 1789 /*
1790 * Initializing proper values as Pause threshold into all
1da177e4
LT		 1791 * the 8 Queues on Rx side.
1792 */
1793 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1794 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1795
1796 /* Disable RMAC PAD STRIPPING */
509a2671 1797 add = &bar0->mac_cfg;
1da177e4
LT		 1798 val64 = readq(&bar0->mac_cfg);
1799 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1800 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1801 writel((u32) (val64), add);
1802 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1803 writel((u32) (val64 >> 32), (add + 4));
1804 val64 = readq(&bar0->mac_cfg);
1805
7d3d0439
RA		 1806 /* Enable FCS stripping by adapter */
1807 add = &bar0->mac_cfg;
1808 val64 = readq(&bar0->mac_cfg);
1809 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1810 if (nic->device_type == XFRAME_II_DEVICE)
1811 writeq(val64, &bar0->mac_cfg);
1812 else {
1813 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1814 writel((u32) (val64), add);
1815 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1816 writel((u32) (val64 >> 32), (add + 4));
1817 }
1818
20346722
K		 1819 /*
1820 * Set the time value to be inserted in the pause frame
1da177e4
LT		 1821 * generated by xena.
1822 */
1823 val64 = readq(&bar0->rmac_pause_cfg);
1824 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1825 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1826 writeq(val64, &bar0->rmac_pause_cfg);
1827
20346722 1828 /*
1da177e4
LT		 1829 * Set the Threshold Limit for Generating the pause frame
1830 * If the amount of data in any Queue exceeds ratio of
1831 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1832 * pause frame is generated
1833 */
1834 val64 = 0;
1835 for (i = 0; i < 4; i++) {
d44570e4
JP		 1836 val64 |= (((u64)0xFF00 |
1837 nic->mac_control.mc_pause_threshold_q0q3)
1838 << (i * 2 * 8));
1da177e4
LT		 1839 }
1840 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1841
1842 val64 = 0;
1843 for (i = 0; i < 4; i++) {
d44570e4
JP		 1844 val64 |= (((u64)0xFF00 |
1845 nic->mac_control.mc_pause_threshold_q4q7)
1846 << (i * 2 * 8));
1da177e4
LT		 1847 }
1848 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1849
20346722
K		 1850 /*
1851 * TxDMA will stop Read request if the number of read split has
1da177e4
LT		 1852 * exceeded the limit pointed by shared_splits
1853 */
1854 val64 = readq(&bar0->pic_control);
1855 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1856 writeq(val64, &bar0->pic_control);
1857
863c11a9
AR		 1858 if (nic->config.bus_speed == 266) {
1859 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1860 writeq(0x0, &bar0->read_retry_delay);
1861 writeq(0x0, &bar0->write_retry_delay);
1862 }
1863
541ae68f
K		 1864 /*
1865 * Programming the Herc to split every write transaction
1866 * that does not start on an ADB to reduce disconnects.
1867 */
1868 if (nic->device_type == XFRAME_II_DEVICE) {
19a60522
SS		 1869 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1870 MISC_LINK_STABILITY_PRD(3);
863c11a9
AR		 1871 writeq(val64, &bar0->misc_control);
1872 val64 = readq(&bar0->pic_control2);
b7b5a128 1873 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
863c11a9 1874 writeq(val64, &bar0->pic_control2);
541ae68f 1875 }
c92ca04b
AR		 1876 if (strstr(nic->product_name, "CX4")) {
1877 val64 = TMAC_AVG_IPG(0x17);
1878 writeq(val64, &bar0->tmac_avg_ipg);
a371a07d
K		 1879 }
1880
1da177e4
LT		 1881 return SUCCESS;
1882}
a371a07d
K		 1883#define LINK_UP_DOWN_INTERRUPT 1
1884#define MAC_RMAC_ERR_TIMER 2
1885
1ee6dd77 1886static int s2io_link_fault_indication(struct s2io_nic *nic)
a371a07d
K		 1887{
1888 if (nic->device_type == XFRAME_II_DEVICE)
1889 return LINK_UP_DOWN_INTERRUPT;
1890 else
1891 return MAC_RMAC_ERR_TIMER;
1892}
8116f3cf 1893
9caab458
SS		 1894/**
1895 * do_s2io_write_bits - update alarm bits in alarm register
1896 * @value: alarm bits
1897 * @flag: interrupt status
1898 * @addr: address value
1899 * Description: update alarm bits in alarm register
1900 * Return Value:
1901 * NONE.
1902 */
1903static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1904{
1905 u64 temp64;
1906
1907 temp64 = readq(addr);
1908
d44570e4
JP		 1909 if (flag == ENABLE_INTRS)
1910 temp64 &= ~((u64)value);
9caab458 1911 else
d44570e4 1912 temp64 |= ((u64)value);
9caab458
SS		 1913 writeq(temp64, addr);
1914}
1da177e4 1915
43b7c451 1916static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
9caab458
SS		 1917{
1918 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1919 register u64 gen_int_mask = 0;
01e16faa 1920 u64 interruptible;
9caab458 1921
01e16faa 1922 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
9caab458 1923 if (mask & TX_DMA_INTR) {
9caab458
SS		 1924 gen_int_mask |= TXDMA_INT_M;
1925
1926 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
d44570e4
JP		 1927 TXDMA_PCC_INT | TXDMA_TTI_INT |
1928 TXDMA_LSO_INT | TXDMA_TPA_INT |
1929 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
9caab458
SS		 1930
1931 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
d44570e4
JP		 1932 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1933 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1934 &bar0->pfc_err_mask);
9caab458
SS		 1935
1936 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
d44570e4
JP		 1937 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1938 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
9caab458
SS		 1939
1940 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
d44570e4
JP		 1941 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1942 PCC_N_SERR | PCC_6_COF_OV_ERR |
1943 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1944 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1945 PCC_TXB_ECC_SG_ERR,
1946 flag, &bar0->pcc_err_mask);
9caab458
SS		 1947
1948 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
d44570e4 1949 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
9caab458
SS		 1950
1951 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
d44570e4
JP		 1952 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1953 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1954 flag, &bar0->lso_err_mask);
9caab458
SS		 1955
1956 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
d44570e4 1957 flag, &bar0->tpa_err_mask);
9caab458
SS		 1958
1959 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
9caab458
SS		 1960 }
1961
1962 if (mask & TX_MAC_INTR) {
1963 gen_int_mask |= TXMAC_INT_M;
1964 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
d44570e4 1965 &bar0->mac_int_mask);
9caab458 1966 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
d44570e4
JP		 1967 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1968 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1969 flag, &bar0->mac_tmac_err_mask);
9caab458
SS		 1970 }
1971
1972 if (mask & TX_XGXS_INTR) {
1973 gen_int_mask |= TXXGXS_INT_M;
1974 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
d44570e4 1975 &bar0->xgxs_int_mask);
9caab458 1976 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
d44570e4
JP		 1977 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1978 flag, &bar0->xgxs_txgxs_err_mask);
9caab458
SS		 1979 }
1980
1981 if (mask & RX_DMA_INTR) {
1982 gen_int_mask |= RXDMA_INT_M;
1983 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
d44570e4
JP		 1984 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1985 flag, &bar0->rxdma_int_mask);
9caab458 1986 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
d44570e4
JP		 1987 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1988 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1989 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
9caab458 1990 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
d44570e4
JP		 1991 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1992 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1993 &bar0->prc_pcix_err_mask);
9caab458 1994 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
d44570e4
JP		 1995 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1996 &bar0->rpa_err_mask);
9caab458 1997 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
d44570e4
JP		 1998 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
1999 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
2000 RDA_FRM_ECC_SG_ERR |
2001 RDA_MISC_ERR|RDA_PCIX_ERR,
2002 flag, &bar0->rda_err_mask);
9caab458 2003 do_s2io_write_bits(RTI_SM_ERR_ALARM |
d44570e4
JP		 2004 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2005 flag, &bar0->rti_err_mask);
9caab458
SS		 2006 }
2007
2008 if (mask & RX_MAC_INTR) {
2009 gen_int_mask |= RXMAC_INT_M;
2010 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
d44570e4
JP		 2011 &bar0->mac_int_mask);
2012 interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2013 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2014 RMAC_DOUBLE_ECC_ERR);
01e16faa
SH		 2015 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2016 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2017 do_s2io_write_bits(interruptible,
d44570e4 2018 flag, &bar0->mac_rmac_err_mask);
9caab458
SS		 2019 }
2020
d44570e4 2021 if (mask & RX_XGXS_INTR) {
9caab458
SS		 2022 gen_int_mask |= RXXGXS_INT_M;
2023 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
d44570e4 2024 &bar0->xgxs_int_mask);
9caab458 2025 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
d44570e4 2026 &bar0->xgxs_rxgxs_err_mask);
9caab458
SS		 2027 }
2028
2029 if (mask & MC_INTR) {
2030 gen_int_mask |= MC_INT_M;
d44570e4
JP		 2031 do_s2io_write_bits(MC_INT_MASK_MC_INT,
2032 flag, &bar0->mc_int_mask);
9caab458 2033 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
d44570e4
JP		 2034 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2035 &bar0->mc_err_mask);
9caab458
SS		 2036 }
2037 nic->general_int_mask = gen_int_mask;
2038
2039 /* Remove this line when alarm interrupts are enabled */
2040 nic->general_int_mask = 0;
2041}
d44570e4 2042
20346722
K		 2043/**
2044 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1da177e4
LT		 2045 * @nic: device private variable,
2046 * @mask: A mask indicating which Intr block must be modified and,
2047 * @flag: A flag indicating whether to enable or disable the Intrs.
2048 * Description: This function will either disable or enable the interrupts
20346722
K		 2049 * depending on the flag argument. The mask argument can be used to
2050 * enable/disable any Intr block.
1da177e4
LT		 2051 * Return Value: NONE.
2052 */
2053
2054static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2055{
1ee6dd77 2056 struct XENA_dev_config __iomem *bar0 = nic->bar0;
9caab458
SS		 2057 register u64 temp64 = 0, intr_mask = 0;
2058
2059 intr_mask = nic->general_int_mask;
1da177e4
LT		 2060
2061 /* Top level interrupt classification */
2062 /* PIC Interrupts */
9caab458 2063 if (mask & TX_PIC_INTR) {
1da177e4 2064 /* Enable PIC Intrs in the general intr mask register */
9caab458 2065 intr_mask |= TXPIC_INT_M;
1da177e4 2066 if (flag == ENABLE_INTRS) {
20346722 2067 /*
a371a07d 2068 * If Hercules adapter enable GPIO otherwise
b41477f3 2069 * disable all PCIX, Flash, MDIO, IIC and GPIO
20346722
K		 2070 * interrupts for now.
2071 * TODO
1da177e4 2072 */
a371a07d 2073 if (s2io_link_fault_indication(nic) ==
d44570e4 2074 LINK_UP_DOWN_INTERRUPT) {
9caab458 2075 do_s2io_write_bits(PIC_INT_GPIO, flag,
d44570e4 2076 &bar0->pic_int_mask);
9caab458 2077 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
d44570e4 2078 &bar0->gpio_int_mask);
9caab458 2079 } else
a371a07d 2080 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4 2081 } else if (flag == DISABLE_INTRS) {
20346722
K		 2082 /*
2083 * Disable PIC Intrs in the general
2084 * intr mask register
1da177e4
LT		 2085 */
2086 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4
LT		 2087 }
2088 }
2089
1da177e4
LT		 2090 /* Tx traffic interrupts */
2091 if (mask & TX_TRAFFIC_INTR) {
9caab458 2092 intr_mask |= TXTRAFFIC_INT_M;
1da177e4 2093 if (flag == ENABLE_INTRS) {
20346722 2094 /*
1da177e4 2095 * Enable all the Tx side interrupts
20346722 2096 * writing 0 Enables all 64 TX interrupt levels
1da177e4
LT		 2097 */
2098 writeq(0x0, &bar0->tx_traffic_mask);
2099 } else if (flag == DISABLE_INTRS) {
20346722
K		 2100 /*
2101 * Disable Tx Traffic Intrs in the general intr mask
1da177e4
LT		 2102 * register.
2103 */
2104 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1da177e4
LT		 2105 }
2106 }
2107
2108 /* Rx traffic interrupts */
2109 if (mask & RX_TRAFFIC_INTR) {
9caab458 2110 intr_mask |= RXTRAFFIC_INT_M;
1da177e4 2111 if (flag == ENABLE_INTRS) {
1da177e4
LT		 2112 /* writing 0 Enables all 8 RX interrupt levels */
2113 writeq(0x0, &bar0->rx_traffic_mask);
2114 } else if (flag == DISABLE_INTRS) {
20346722
K		 2115 /*
2116 * Disable Rx Traffic Intrs in the general intr mask
1da177e4
LT		 2117 * register.
2118 */
2119 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1da177e4
LT		 2120 }
2121 }
9caab458
SS		 2122
2123 temp64 = readq(&bar0->general_int_mask);
2124 if (flag == ENABLE_INTRS)
d44570e4 2125 temp64 &= ~((u64)intr_mask);
9caab458
SS		 2126 else
2127 temp64 = DISABLE_ALL_INTRS;
2128 writeq(temp64, &bar0->general_int_mask);
2129
2130 nic->general_int_mask = readq(&bar0->general_int_mask);
1da177e4
LT		 2131}
2132
19a60522
SS		 2133/**
2134 * verify_pcc_quiescent- Checks for PCC quiescent state
2135 * Return: 1 If PCC is quiescence
2136 * 0 If PCC is not quiescence
2137 */
1ee6dd77 2138static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
20346722 2139{
19a60522 2140 int ret = 0, herc;
1ee6dd77 2141 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522 2142 u64 val64 = readq(&bar0->adapter_status);
8a4bdbaa 2143
19a60522 2144 herc = (sp->device_type == XFRAME_II_DEVICE);
20346722 2145
f957bcf0 2146 if (flag == false) {
44c10138 2147 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
19a60522 2148 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2149 ret = 1;
19a60522
SS		 2150 } else {
2151 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2152 ret = 1;
20346722
K		 2153 }
2154 } else {
44c10138 2155 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
5e25b9dd 2156 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
19a60522 2157 ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2158 ret = 1;
5e25b9dd
K		 2159 } else {
2160 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
19a60522 2161 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2162 ret = 1;
20346722
K		 2163 }
2164 }
2165
2166 return ret;
2167}
2168/**
2169 * verify_xena_quiescence - Checks whether the H/W is ready
1da177e4 2170 * Description: Returns whether the H/W is ready to go or not. Depending
20346722 2171 * on whether adapter enable bit was written or not the comparison
1da177e4
LT		 2172 * differs and the calling function passes the input argument flag to
2173 * indicate this.
20346722 2174 * Return: 1 If xena is quiescence
1da177e4
LT		 2175 * 0 If Xena is not quiescence
2176 */
2177
1ee6dd77 2178static int verify_xena_quiescence(struct s2io_nic *sp)
1da177e4 2179{
19a60522 2180 int mode;
1ee6dd77 2181 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 2182 u64 val64 = readq(&bar0->adapter_status);
2183 mode = s2io_verify_pci_mode(sp);
1da177e4 2184
19a60522 2185 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
9e39f7c5 2186 DBG_PRINT(ERR_DBG, "TDMA is not ready!\n");
19a60522
SS		 2187 return 0;
2188 }
2189 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
9e39f7c5 2190 DBG_PRINT(ERR_DBG, "RDMA is not ready!\n");
19a60522
SS		 2191 return 0;
2192 }
2193 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
9e39f7c5 2194 DBG_PRINT(ERR_DBG, "PFC is not ready!\n");
19a60522
SS		 2195 return 0;
2196 }
2197 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
9e39f7c5 2198 DBG_PRINT(ERR_DBG, "TMAC BUF is not empty!\n");
19a60522
SS		 2199 return 0;
2200 }
2201 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
9e39f7c5 2202 DBG_PRINT(ERR_DBG, "PIC is not QUIESCENT!\n");
19a60522
SS		 2203 return 0;
2204 }
2205 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
9e39f7c5 2206 DBG_PRINT(ERR_DBG, "MC_DRAM is not ready!\n");
19a60522
SS		 2207 return 0;
2208 }
2209 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
9e39f7c5 2210 DBG_PRINT(ERR_DBG, "MC_QUEUES is not ready!\n");
19a60522
SS		 2211 return 0;
2212 }
2213 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
9e39f7c5 2214 DBG_PRINT(ERR_DBG, "M_PLL is not locked!\n");
19a60522 2215 return 0;
1da177e4
LT		 2216 }
2217
19a60522
SS		 2218 /*
2219 * In PCI 33 mode, the P_PLL is not used, and therefore,
2220 * the the P_PLL_LOCK bit in the adapter_status register will
2221 * not be asserted.
2222 */
2223 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
d44570e4
JP		 2224 sp->device_type == XFRAME_II_DEVICE &&
2225 mode != PCI_MODE_PCI_33) {
9e39f7c5 2226 DBG_PRINT(ERR_DBG, "P_PLL is not locked!\n");
19a60522
SS		 2227 return 0;
2228 }
2229 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
d44570e4 2230 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
9e39f7c5 2231 DBG_PRINT(ERR_DBG, "RC_PRC is not QUIESCENT!\n");
19a60522
SS		 2232 return 0;
2233 }
2234 return 1;
1da177e4
LT		 2235}
2236
2237/**
2238 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2239 * @sp: Pointer to device specifc structure
20346722 2240 * Description :
1da177e4
LT		 2241 * New procedure to clear mac address reading problems on Alpha platforms
2242 *
2243 */
2244
d44570e4 2245static void fix_mac_address(struct s2io_nic *sp)
1da177e4 2246{
1ee6dd77 2247 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 2248 int i = 0;
2249
2250 while (fix_mac[i] != END_SIGN) {
2251 writeq(fix_mac[i++], &bar0->gpio_control);
20346722 2252 udelay(10);
d83d282b 2253 (void) readq(&bar0->gpio_control);
1da177e4
LT		 2254 }
2255}
2256
2257/**
20346722 2258 * start_nic - Turns the device on
1da177e4 2259 * @nic : device private variable.
20346722
K		 2260 * Description:
2261 * This function actually turns the device on. Before this function is
2262 * called,all Registers are configured from their reset states
2263 * and shared memory is allocated but the NIC is still quiescent. On
1da177e4
LT		 2264 * calling this function, the device interrupts are cleared and the NIC is
2265 * literally switched on by writing into the adapter control register.
20346722 2266 * Return Value:
1da177e4
LT		 2267 * SUCCESS on success and -1 on failure.
2268 */
2269
2270static int start_nic(struct s2io_nic *nic)
2271{
1ee6dd77 2272 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 2273 struct net_device *dev = nic->dev;
2274 register u64 val64 = 0;
20346722 2275 u16 subid, i;
ffb5df6c
JP		 2276 struct config_param *config = &nic->config;
2277 struct mac_info *mac_control = &nic->mac_control;
1da177e4
LT		 2278
2279 /* PRC Initialization and configuration */
2280 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2281 struct ring_info *ring = &mac_control->rings[i];
2282
d44570e4 2283 writeq((u64)ring->rx_blocks[0].block_dma_addr,
1da177e4
LT		 2284 &bar0->prc_rxd0_n[i]);
2285
2286 val64 = readq(&bar0->prc_ctrl_n[i]);
da6971d8
AR		 2287 if (nic->rxd_mode == RXD_MODE_1)
2288 val64 |= PRC_CTRL_RC_ENABLED;
2289 else
2290 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
863c11a9
AR		 2291 if (nic->device_type == XFRAME_II_DEVICE)
2292 val64 |= PRC_CTRL_GROUP_READS;
2293 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2294 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1da177e4
LT		 2295 writeq(val64, &bar0->prc_ctrl_n[i]);
2296 }
2297
da6971d8
AR		 2298 if (nic->rxd_mode == RXD_MODE_3B) {
2299 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2300 val64 = readq(&bar0->rx_pa_cfg);
2301 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2302 writeq(val64, &bar0->rx_pa_cfg);
2303 }
1da177e4 2304
926930b2
SS		 2305 if (vlan_tag_strip == 0) {
2306 val64 = readq(&bar0->rx_pa_cfg);
2307 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2308 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 2309 nic->vlan_strip_flag = 0;
926930b2
SS		 2310 }
2311
20346722 2312 /*
1da177e4
LT		 2313 * Enabling MC-RLDRAM. After enabling the device, we timeout
2314 * for around 100ms, which is approximately the time required
2315 * for the device to be ready for operation.
2316 */
2317 val64 = readq(&bar0->mc_rldram_mrs);
2318 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2319 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2320 val64 = readq(&bar0->mc_rldram_mrs);
2321
20346722 2322 msleep(100); /* Delay by around 100 ms. */
1da177e4
LT		 2323
2324 /* Enabling ECC Protection. */
2325 val64 = readq(&bar0->adapter_control);
2326 val64 &= ~ADAPTER_ECC_EN;
2327 writeq(val64, &bar0->adapter_control);
2328
20346722
K		 2329 /*
2330 * Verify if the device is ready to be enabled, if so enable
1da177e4
LT		 2331 * it.
2332 */
2333 val64 = readq(&bar0->adapter_status);
19a60522 2334 if (!verify_xena_quiescence(nic)) {
9e39f7c5
JP		 2335 DBG_PRINT(ERR_DBG, "%s: device is not ready, "
2336 "Adapter status reads: 0x%llx\n",
2337 dev->name, (unsigned long long)val64);
1da177e4
LT		 2338 return FAILURE;
2339 }
2340
20346722 2341 /*
1da177e4 2342 * With some switches, link might be already up at this point.
20346722
K		 2343 * Because of this weird behavior, when we enable laser,
2344 * we may not get link. We need to handle this. We cannot
2345 * figure out which switch is misbehaving. So we are forced to
2346 * make a global change.
1da177e4
LT		 2347 */
2348
2349 /* Enabling Laser. */
2350 val64 = readq(&bar0->adapter_control);
2351 val64 |= ADAPTER_EOI_TX_ON;
2352 writeq(val64, &bar0->adapter_control);
2353
c92ca04b
AR		 2354 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2355 /*
25985edc 2356 * Dont see link state interrupts initially on some switches,
c92ca04b
AR		 2357 * so directly scheduling the link state task here.
2358 */
2359 schedule_work(&nic->set_link_task);
2360 }
1da177e4
LT		 2361 /* SXE-002: Initialize link and activity LED */
2362 subid = nic->pdev->subsystem_device;
541ae68f
K		 2363 if (((subid & 0xFF) >= 0x07) &&
2364 (nic->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 2365 val64 = readq(&bar0->gpio_control);
2366 val64 |= 0x0000800000000000ULL;
2367 writeq(val64, &bar0->gpio_control);
2368 val64 = 0x0411040400000000ULL;
509a2671 2369 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 2370 }
2371
1da177e4
LT		 2372 return SUCCESS;
2373}
fed5eccd
AR		 2374/**
2375 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2376 */
d44570e4
JP		 2377static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2378 struct TxD *txdlp, int get_off)
fed5eccd 2379{
1ee6dd77 2380 struct s2io_nic *nic = fifo_data->nic;
fed5eccd 2381 struct sk_buff *skb;
1ee6dd77 2382 struct TxD *txds;
fed5eccd
AR		 2383 u16 j, frg_cnt;
2384
2385 txds = txdlp;
2fda096d 2386 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
d44570e4
JP		 2387 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2388 sizeof(u64), PCI_DMA_TODEVICE);
fed5eccd
AR		 2389 txds++;
2390 }
2391
d44570e4 2392 skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
fed5eccd 2393 if (!skb) {
1ee6dd77 2394 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2395 return NULL;
2396 }
d44570e4 2397 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
e743d313 2398 skb_headlen(skb), PCI_DMA_TODEVICE);
fed5eccd
AR		 2399 frg_cnt = skb_shinfo(skb)->nr_frags;
2400 if (frg_cnt) {
2401 txds++;
2402 for (j = 0; j < frg_cnt; j++, txds++) {
2403 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2404 if (!txds->Buffer_Pointer)
2405 break;
d44570e4
JP		 2406 pci_unmap_page(nic->pdev,
2407 (dma_addr_t)txds->Buffer_Pointer,
fed5eccd
AR		 2408 frag->size, PCI_DMA_TODEVICE);
2409 }
2410 }
d44570e4
JP		 2411 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2412 return skb;
fed5eccd 2413}
1da177e4 2414
20346722
K		 2415/**
2416 * free_tx_buffers - Free all queued Tx buffers
1da177e4 2417 * @nic : device private variable.
20346722 2418 * Description:
1da177e4 2419 * Free all queued Tx buffers.
20346722 2420 * Return Value: void
d44570e4 2421 */
1da177e4
LT		 2422
2423static void free_tx_buffers(struct s2io_nic *nic)
2424{
2425 struct net_device *dev = nic->dev;
2426 struct sk_buff *skb;
1ee6dd77 2427 struct TxD *txdp;
1da177e4 2428 int i, j;
fed5eccd 2429 int cnt = 0;
ffb5df6c
JP		 2430 struct config_param *config = &nic->config;
2431 struct mac_info *mac_control = &nic->mac_control;
2432 struct stat_block *stats = mac_control->stats_info;
2433 struct swStat *swstats = &stats->sw_stat;
1da177e4
LT		 2434
2435 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 2436 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2437 struct fifo_info *fifo = &mac_control->fifos[i];
2fda096d 2438 unsigned long flags;
13d866a9
JP		 2439
2440 spin_lock_irqsave(&fifo->tx_lock, flags);
2441 for (j = 0; j < tx_cfg->fifo_len; j++) {
43d620c8 2442 txdp = fifo->list_info[j].list_virt_addr;
fed5eccd
AR		 2443 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2444 if (skb) {
ffb5df6c 2445 swstats->mem_freed += skb->truesize;
fed5eccd
AR		 2446 dev_kfree_skb(skb);
2447 cnt++;
1da177e4 2448 }
1da177e4
LT		 2449 }
2450 DBG_PRINT(INTR_DBG,
9e39f7c5 2451 "%s: forcibly freeing %d skbs on FIFO%d\n",
1da177e4 2452 dev->name, cnt, i);
13d866a9
JP		 2453 fifo->tx_curr_get_info.offset = 0;
2454 fifo->tx_curr_put_info.offset = 0;
2455 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4
LT		 2456 }
2457}
2458
20346722
K		 2459/**
2460 * stop_nic - To stop the nic
1da177e4 2461 * @nic ; device private variable.
20346722
K		 2462 * Description:
2463 * This function does exactly the opposite of what the start_nic()
1da177e4
LT		 2464 * function does. This function is called to stop the device.
2465 * Return Value:
2466 * void.
2467 */
2468
2469static void stop_nic(struct s2io_nic *nic)
2470{
1ee6dd77 2471 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 2472 register u64 val64 = 0;
5d3213cc 2473 u16 interruptible;
1da177e4
LT		 2474
2475 /* Disable all interrupts */
9caab458 2476 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
e960fc5c 2477 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 2478 interruptible |= TX_PIC_INTR;
1da177e4
LT		 2479 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2480
5d3213cc
AR		 2481 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2482 val64 = readq(&bar0->adapter_control);
2483 val64 &= ~(ADAPTER_CNTL_EN);
2484 writeq(val64, &bar0->adapter_control);
1da177e4
LT		 2485}
2486
20346722
K		 2487/**
2488 * fill_rx_buffers - Allocates the Rx side skbs
0425b46a 2489 * @ring_info: per ring structure
3f78d885
SH		 2490 * @from_card_up: If this is true, we will map the buffer to get
2491 * the dma address for buf0 and buf1 to give it to the card.
2492 * Else we will sync the already mapped buffer to give it to the card.
20346722 2493 * Description:
1da177e4
LT		 2494 * The function allocates Rx side skbs and puts the physical
2495 * address of these buffers into the RxD buffer pointers, so that the NIC
2496 * can DMA the received frame into these locations.
2497 * The NIC supports 3 receive modes, viz
2498 * 1. single buffer,
2499 * 2. three buffer and
2500 * 3. Five buffer modes.
20346722
K		 2501 * Each mode defines how many fragments the received frame will be split
2502 * up into by the NIC. The frame is split into L3 header, L4 Header,
1da177e4
LT		 2503 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2504 * is split into 3 fragments. As of now only single buffer mode is
2505 * supported.
2506 * Return Value:
2507 * SUCCESS on success or an appropriate -ve value on failure.
2508 */
8d8bb39b 2509static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
d44570e4 2510 int from_card_up)
1da177e4 2511{
1da177e4 2512 struct sk_buff *skb;
1ee6dd77 2513 struct RxD_t *rxdp;
0425b46a 2514 int off, size, block_no, block_no1;
1da177e4 2515 u32 alloc_tab = 0;
20346722 2516 u32 alloc_cnt;
20346722 2517 u64 tmp;
1ee6dd77 2518 struct buffAdd *ba;
1ee6dd77 2519 struct RxD_t *first_rxdp = NULL;
363dc367 2520 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
0425b46a 2521 int rxd_index = 0;
6d517a27
VP		 2522 struct RxD1 *rxdp1;
2523 struct RxD3 *rxdp3;
ffb5df6c 2524 struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat;
1da177e4 2525
0425b46a 2526 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
1da177e4 2527
0425b46a 2528 block_no1 = ring->rx_curr_get_info.block_index;
1da177e4 2529 while (alloc_tab < alloc_cnt) {
0425b46a 2530 block_no = ring->rx_curr_put_info.block_index;
1da177e4 2531
0425b46a
SH		 2532 off = ring->rx_curr_put_info.offset;
2533
2534 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2535
2536 rxd_index = off + 1;
2537 if (block_no)
2538 rxd_index += (block_no * ring->rxd_count);
da6971d8 2539
7d2e3cb7 2540 if ((block_no == block_no1) &&
d44570e4
JP		 2541 (off == ring->rx_curr_get_info.offset) &&
2542 (rxdp->Host_Control)) {
9e39f7c5
JP		 2543 DBG_PRINT(INTR_DBG, "%s: Get and Put info equated\n",
2544 ring->dev->name);
1da177e4
LT		 2545 goto end;
2546 }
0425b46a
SH		 2547 if (off && (off == ring->rxd_count)) {
2548 ring->rx_curr_put_info.block_index++;
2549 if (ring->rx_curr_put_info.block_index ==
d44570e4 2550 ring->block_count)
0425b46a
SH		 2551 ring->rx_curr_put_info.block_index = 0;
2552 block_no = ring->rx_curr_put_info.block_index;
2553 off = 0;
2554 ring->rx_curr_put_info.offset = off;
2555 rxdp = ring->rx_blocks[block_no].block_virt_addr;
1da177e4 2556 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
0425b46a
SH		 2557 ring->dev->name, rxdp);
2558
1da177e4 2559 }
c9fcbf47 2560
da6971d8 2561 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
d44570e4
JP		 2562 ((ring->rxd_mode == RXD_MODE_3B) &&
2563 (rxdp->Control_2 & s2BIT(0)))) {
0425b46a 2564 ring->rx_curr_put_info.offset = off;
1da177e4
LT		 2565 goto end;
2566 }
da6971d8 2567 /* calculate size of skb based on ring mode */
d44570e4
JP		 2568 size = ring->mtu +
2569 HEADER_ETHERNET_II_802_3_SIZE +
2570 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
0425b46a 2571 if (ring->rxd_mode == RXD_MODE_1)
da6971d8 2572 size += NET_IP_ALIGN;
da6971d8 2573 else
0425b46a 2574 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
1da177e4 2575
da6971d8
AR		 2576 /* allocate skb */
2577 skb = dev_alloc_skb(size);
d44570e4 2578 if (!skb) {
9e39f7c5
JP		 2579 DBG_PRINT(INFO_DBG, "%s: Could not allocate skb\n",
2580 ring->dev->name);
303bcb4b
K		 2581 if (first_rxdp) {
2582 wmb();
2583 first_rxdp->Control_1 |= RXD_OWN_XENA;
2584 }
ffb5df6c 2585 swstats->mem_alloc_fail_cnt++;
7d2e3cb7 2586
da6971d8
AR		 2587 return -ENOMEM ;
2588 }
ffb5df6c 2589 swstats->mem_allocated += skb->truesize;
0425b46a
SH		 2590
2591 if (ring->rxd_mode == RXD_MODE_1) {
da6971d8 2592 /* 1 buffer mode - normal operation mode */
d44570e4 2593 rxdp1 = (struct RxD1 *)rxdp;
1ee6dd77 2594 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2595 skb_reserve(skb, NET_IP_ALIGN);
d44570e4
JP		 2596 rxdp1->Buffer0_ptr =
2597 pci_map_single(ring->pdev, skb->data,
2598 size - NET_IP_ALIGN,
2599 PCI_DMA_FROMDEVICE);
8d8bb39b 2600 if (pci_dma_mapping_error(nic->pdev,
d44570e4 2601 rxdp1->Buffer0_ptr))
491abf25
VP		 2602 goto pci_map_failed;
2603
8a4bdbaa 2604 rxdp->Control_2 =
491976b2 2605 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
d44570e4 2606 rxdp->Host_Control = (unsigned long)skb;
0425b46a 2607 } else if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8 2608 /*
6d517a27
VP		 2609 * 2 buffer mode -
2610 * 2 buffer mode provides 128
da6971d8 2611 * byte aligned receive buffers.
da6971d8
AR		 2612 */
2613
d44570e4 2614 rxdp3 = (struct RxD3 *)rxdp;
491976b2 2615 /* save buffer pointers to avoid frequent dma mapping */
6d517a27
VP		 2616 Buffer0_ptr = rxdp3->Buffer0_ptr;
2617 Buffer1_ptr = rxdp3->Buffer1_ptr;
1ee6dd77 2618 memset(rxdp, 0, sizeof(struct RxD3));
363dc367 2619 /* restore the buffer pointers for dma sync*/
6d517a27
VP		 2620 rxdp3->Buffer0_ptr = Buffer0_ptr;
2621 rxdp3->Buffer1_ptr = Buffer1_ptr;
363dc367 2622
0425b46a 2623 ba = &ring->ba[block_no][off];
da6971d8 2624 skb_reserve(skb, BUF0_LEN);
d44570e4 2625 tmp = (u64)(unsigned long)skb->data;
da6971d8
AR		 2626 tmp += ALIGN_SIZE;
2627 tmp &= ~ALIGN_SIZE;
2628 skb->data = (void *) (unsigned long)tmp;
27a884dc 2629 skb_reset_tail_pointer(skb);
da6971d8 2630
3f78d885 2631 if (from_card_up) {
6d517a27 2632 rxdp3->Buffer0_ptr =
d44570e4
JP		 2633 pci_map_single(ring->pdev, ba->ba_0,
2634 BUF0_LEN,
2635 PCI_DMA_FROMDEVICE);
2636 if (pci_dma_mapping_error(nic->pdev,
2637 rxdp3->Buffer0_ptr))
3f78d885
SH		 2638 goto pci_map_failed;
2639 } else
0425b46a 2640 pci_dma_sync_single_for_device(ring->pdev,
d44570e4
JP		 2641 (dma_addr_t)rxdp3->Buffer0_ptr,
2642 BUF0_LEN,
2643 PCI_DMA_FROMDEVICE);
491abf25 2644
da6971d8 2645 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
0425b46a 2646 if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 2647 /* Two buffer mode */
2648
2649 /*
6aa20a22 2650 * Buffer2 will have L3/L4 header plus
da6971d8
AR		 2651 * L4 payload
2652 */
d44570e4
JP		 2653 rxdp3->Buffer2_ptr = pci_map_single(ring->pdev,
2654 skb->data,
2655 ring->mtu + 4,
2656 PCI_DMA_FROMDEVICE);
da6971d8 2657
8d8bb39b 2658 if (pci_dma_mapping_error(nic->pdev,
d44570e4 2659 rxdp3->Buffer2_ptr))
491abf25
VP		 2660 goto pci_map_failed;
2661
3f78d885 2662 if (from_card_up) {
0425b46a
SH		 2663 rxdp3->Buffer1_ptr =
2664 pci_map_single(ring->pdev,
d44570e4
JP		 2665 ba->ba_1,
2666 BUF1_LEN,
2667 PCI_DMA_FROMDEVICE);
0425b46a 2668
8d8bb39b 2669 if (pci_dma_mapping_error(nic->pdev,
d44570e4
JP		 2670 rxdp3->Buffer1_ptr)) {
2671 pci_unmap_single(ring->pdev,
2672 (dma_addr_t)(unsigned long)
2673 skb->data,
2674 ring->mtu + 4,
2675 PCI_DMA_FROMDEVICE);
3f78d885
SH		 2676 goto pci_map_failed;
2677 }
75c30b13 2678 }
da6971d8
AR		 2679 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2680 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
d44570e4 2681 (ring->mtu + 4);
da6971d8 2682 }
b7b5a128 2683 rxdp->Control_2 |= s2BIT(0);
0425b46a 2684 rxdp->Host_Control = (unsigned long) (skb);
1da177e4 2685 }
303bcb4b
K		 2686 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2687 rxdp->Control_1 |= RXD_OWN_XENA;
1da177e4 2688 off++;
0425b46a 2689 if (off == (ring->rxd_count + 1))
da6971d8 2690 off = 0;
0425b46a 2691 ring->rx_curr_put_info.offset = off;
20346722 2692
da6971d8 2693 rxdp->Control_2 |= SET_RXD_MARKER;
303bcb4b
K		 2694 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2695 if (first_rxdp) {
2696 wmb();
2697 first_rxdp->Control_1 |= RXD_OWN_XENA;
2698 }
2699 first_rxdp = rxdp;
2700 }
0425b46a 2701 ring->rx_bufs_left += 1;
1da177e4
LT		 2702 alloc_tab++;
2703 }
2704
d44570e4 2705end:
303bcb4b
K		 2706 /* Transfer ownership of first descriptor to adapter just before
2707 * exiting. Before that, use memory barrier so that ownership
2708 * and other fields are seen by adapter correctly.
2709 */
2710 if (first_rxdp) {
2711 wmb();
2712 first_rxdp->Control_1 |= RXD_OWN_XENA;
2713 }
2714
1da177e4 2715 return SUCCESS;
d44570e4 2716
491abf25 2717pci_map_failed:
ffb5df6c
JP		 2718 swstats->pci_map_fail_cnt++;
2719 swstats->mem_freed += skb->truesize;
491abf25
VP		 2720 dev_kfree_skb_irq(skb);
2721 return -ENOMEM;
1da177e4
LT		 2722}
2723
da6971d8
AR		 2724static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2725{
2726 struct net_device *dev = sp->dev;
2727 int j;
2728 struct sk_buff *skb;
1ee6dd77 2729 struct RxD_t *rxdp;
6d517a27
VP		 2730 struct RxD1 *rxdp1;
2731 struct RxD3 *rxdp3;
ffb5df6c
JP		 2732 struct mac_info *mac_control = &sp->mac_control;
2733 struct stat_block *stats = mac_control->stats_info;
2734 struct swStat *swstats = &stats->sw_stat;
da6971d8 2735
da6971d8
AR		 2736 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2737 rxdp = mac_control->rings[ring_no].
d44570e4
JP		 2738 rx_blocks[blk].rxds[j].virt_addr;
2739 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2740 if (!skb)
da6971d8 2741 continue;
da6971d8 2742 if (sp->rxd_mode == RXD_MODE_1) {
d44570e4
JP		 2743 rxdp1 = (struct RxD1 *)rxdp;
2744 pci_unmap_single(sp->pdev,
2745 (dma_addr_t)rxdp1->Buffer0_ptr,
2746 dev->mtu +
2747 HEADER_ETHERNET_II_802_3_SIZE +
2748 HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2749 PCI_DMA_FROMDEVICE);
1ee6dd77 2750 memset(rxdp, 0, sizeof(struct RxD1));
d44570e4
JP		 2751 } else if (sp->rxd_mode == RXD_MODE_3B) {
2752 rxdp3 = (struct RxD3 *)rxdp;
d44570e4
JP		 2753 pci_unmap_single(sp->pdev,
2754 (dma_addr_t)rxdp3->Buffer0_ptr,
2755 BUF0_LEN,
2756 PCI_DMA_FROMDEVICE);
2757 pci_unmap_single(sp->pdev,
2758 (dma_addr_t)rxdp3->Buffer1_ptr,
2759 BUF1_LEN,
2760 PCI_DMA_FROMDEVICE);
2761 pci_unmap_single(sp->pdev,
2762 (dma_addr_t)rxdp3->Buffer2_ptr,
2763 dev->mtu + 4,
2764 PCI_DMA_FROMDEVICE);
1ee6dd77 2765 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8 2766 }
ffb5df6c 2767 swstats->mem_freed += skb->truesize;
da6971d8 2768 dev_kfree_skb(skb);
0425b46a 2769 mac_control->rings[ring_no].rx_bufs_left -= 1;
da6971d8
AR		 2770 }
2771}
2772
1da177e4 2773/**
20346722 2774 * free_rx_buffers - Frees all Rx buffers
1da177e4 2775 * @sp: device private variable.
20346722 2776 * Description:
1da177e4
LT		 2777 * This function will free all Rx buffers allocated by host.
2778 * Return Value:
2779 * NONE.
2780 */
2781
2782static void free_rx_buffers(struct s2io_nic *sp)
2783{
2784 struct net_device *dev = sp->dev;
da6971d8 2785 int i, blk = 0, buf_cnt = 0;
ffb5df6c
JP		 2786 struct config_param *config = &sp->config;
2787 struct mac_info *mac_control = &sp->mac_control;
1da177e4
LT		 2788
2789 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2790 struct ring_info *ring = &mac_control->rings[i];
2791
da6971d8 2792 for (blk = 0; blk < rx_ring_sz[i]; blk++)
d44570e4 2793 free_rxd_blk(sp, i, blk);
1da177e4 2794
13d866a9
JP		 2795 ring->rx_curr_put_info.block_index = 0;
2796 ring->rx_curr_get_info.block_index = 0;
2797 ring->rx_curr_put_info.offset = 0;
2798 ring->rx_curr_get_info.offset = 0;
2799 ring->rx_bufs_left = 0;
9e39f7c5 2800 DBG_PRINT(INIT_DBG, "%s: Freed 0x%x Rx Buffers on ring%d\n",
1da177e4
LT		 2801 dev->name, buf_cnt, i);
2802 }
2803}
2804
8d8bb39b 2805static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
f61e0a35 2806{
8d8bb39b 2807 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
9e39f7c5
JP		 2808 DBG_PRINT(INFO_DBG, "%s: Out of memory in Rx Intr!!\n",
2809 ring->dev->name);
f61e0a35
SH		 2810 }
2811 return 0;
2812}
2813
1da177e4
LT		 2814/**
2815 * s2io_poll - Rx interrupt handler for NAPI support
bea3348e 2816 * @napi : pointer to the napi structure.
20346722 2817 * @budget : The number of packets that were budgeted to be processed
1da177e4
LT		 2818 * during one pass through the 'Poll" function.
2819 * Description:
2820 * Comes into picture only if NAPI support has been incorporated. It does
2821 * the same thing that rx_intr_handler does, but not in a interrupt context
2822 * also It will process only a given number of packets.
2823 * Return value:
2824 * 0 on success and 1 if there are No Rx packets to be processed.
2825 */
2826
f61e0a35 2827static int s2io_poll_msix(struct napi_struct *napi, int budget)
1da177e4 2828{
f61e0a35
SH		 2829 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2830 struct net_device *dev = ring->dev;
f61e0a35 2831 int pkts_processed = 0;
1a79d1c3
AV		 2832 u8 __iomem *addr = NULL;
2833 u8 val8 = 0;
4cf1653a 2834 struct s2io_nic *nic = netdev_priv(dev);
1ee6dd77 2835 struct XENA_dev_config __iomem *bar0 = nic->bar0;
f61e0a35 2836 int budget_org = budget;
1da177e4 2837
f61e0a35
SH		 2838 if (unlikely(!is_s2io_card_up(nic)))
2839 return 0;
1da177e4 2840
f61e0a35 2841 pkts_processed = rx_intr_handler(ring, budget);
8d8bb39b 2842 s2io_chk_rx_buffers(nic, ring);
1da177e4 2843
f61e0a35 2844 if (pkts_processed < budget_org) {
288379f0 2845 napi_complete(napi);
f61e0a35 2846 /*Re Enable MSI-Rx Vector*/
1a79d1c3 2847 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
f61e0a35
SH		 2848 addr += 7 - ring->ring_no;
2849 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2850 writeb(val8, addr);
2851 val8 = readb(addr);
1da177e4 2852 }
f61e0a35
SH		 2853 return pkts_processed;
2854}
d44570e4 2855
f61e0a35
SH		 2856static int s2io_poll_inta(struct napi_struct *napi, int budget)
2857{
2858 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
f61e0a35
SH		 2859 int pkts_processed = 0;
2860 int ring_pkts_processed, i;
2861 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2862 int budget_org = budget;
ffb5df6c
JP		 2863 struct config_param *config = &nic->config;
2864 struct mac_info *mac_control = &nic->mac_control;
1da177e4 2865
f61e0a35
SH		 2866 if (unlikely(!is_s2io_card_up(nic)))
2867 return 0;
1da177e4 2868
1da177e4 2869 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9 2870 struct ring_info *ring = &mac_control->rings[i];
f61e0a35 2871 ring_pkts_processed = rx_intr_handler(ring, budget);
8d8bb39b 2872 s2io_chk_rx_buffers(nic, ring);
f61e0a35
SH		 2873 pkts_processed += ring_pkts_processed;
2874 budget -= ring_pkts_processed;
2875 if (budget <= 0)
1da177e4 2876 break;
1da177e4 2877 }
f61e0a35 2878 if (pkts_processed < budget_org) {
288379f0 2879 napi_complete(napi);
f61e0a35
SH		 2880 /* Re enable the Rx interrupts for the ring */
2881 writeq(0, &bar0->rx_traffic_mask);
2882 readl(&bar0->rx_traffic_mask);
2883 }
2884 return pkts_processed;
1da177e4 2885}
20346722 2886
b41477f3 2887#ifdef CONFIG_NET_POLL_CONTROLLER
612eff0e 2888/**
b41477f3 2889 * s2io_netpoll - netpoll event handler entry point
612eff0e
BH		 2890 * @dev : pointer to the device structure.
2891 * Description:
b41477f3
AR		 2892 * This function will be called by upper layer to check for events on the
2893 * interface in situations where interrupts are disabled. It is used for
2894 * specific in-kernel networking tasks, such as remote consoles and kernel
2895 * debugging over the network (example netdump in RedHat).
612eff0e 2896 */
612eff0e
BH		 2897static void s2io_netpoll(struct net_device *dev)
2898{
4cf1653a 2899 struct s2io_nic *nic = netdev_priv(dev);
1ee6dd77 2900 struct XENA_dev_config __iomem *bar0 = nic->bar0;
b41477f3 2901 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
612eff0e 2902 int i;
ffb5df6c
JP		 2903 struct config_param *config = &nic->config;
2904 struct mac_info *mac_control = &nic->mac_control;
612eff0e 2905
d796fdb7
LV		 2906 if (pci_channel_offline(nic->pdev))
2907 return;
2908
612eff0e
BH		 2909 disable_irq(dev->irq);
2910
612eff0e 2911 writeq(val64, &bar0->rx_traffic_int);
b41477f3
AR		 2912 writeq(val64, &bar0->tx_traffic_int);
2913
6aa20a22 2914 /* we need to free up the transmitted skbufs or else netpoll will
b41477f3
AR		 2915 * run out of skbs and will fail and eventually netpoll application such
2916 * as netdump will fail.
2917 */
2918 for (i = 0; i < config->tx_fifo_num; i++)
2919 tx_intr_handler(&mac_control->fifos[i]);
612eff0e 2920
b41477f3 2921 /* check for received packet and indicate up to network */
13d866a9
JP		 2922 for (i = 0; i < config->rx_ring_num; i++) {
2923 struct ring_info *ring = &mac_control->rings[i];
2924
2925 rx_intr_handler(ring, 0);
2926 }
612eff0e
BH		 2927
2928 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2929 struct ring_info *ring = &mac_control->rings[i];
2930
2931 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
9e39f7c5
JP		 2932 DBG_PRINT(INFO_DBG,
2933 "%s: Out of memory in Rx Netpoll!!\n",
2934 dev->name);
612eff0e
BH		 2935 break;
2936 }
2937 }
612eff0e 2938 enable_irq(dev->irq);
612eff0e
BH		 2939}
2940#endif
2941
20346722 2942/**
1da177e4 2943 * rx_intr_handler - Rx interrupt handler
f61e0a35
SH		 2944 * @ring_info: per ring structure.
2945 * @budget: budget for napi processing.
20346722
K		 2946 * Description:
2947 * If the interrupt is because of a received frame or if the
1da177e4 2948 * receive ring contains fresh as yet un-processed frames,this function is
20346722
K		 2949 * called. It picks out the RxD at which place the last Rx processing had
2950 * stopped and sends the skb to the OSM's Rx handler and then increments
1da177e4
LT		 2951 * the offset.
2952 * Return Value:
f61e0a35 2953 * No. of napi packets processed.
1da177e4 2954 */
f61e0a35 2955static int rx_intr_handler(struct ring_info *ring_data, int budget)
1da177e4 2956{
c9fcbf47 2957 int get_block, put_block;
1ee6dd77
RB		 2958 struct rx_curr_get_info get_info, put_info;
2959 struct RxD_t *rxdp;
1da177e4 2960 struct sk_buff *skb;
f61e0a35 2961 int pkt_cnt = 0, napi_pkts = 0;
7d3d0439 2962 int i;
d44570e4
JP		 2963 struct RxD1 *rxdp1;
2964 struct RxD3 *rxdp3;
7d3d0439 2965
20346722
K		 2966 get_info = ring_data->rx_curr_get_info;
2967 get_block = get_info.block_index;
1ee6dd77 2968 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
20346722 2969 put_block = put_info.block_index;
da6971d8 2970 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
db874e65 2971
da6971d8 2972 while (RXD_IS_UP2DT(rxdp)) {
db874e65
SS		 2973 /*
2974 * If your are next to put index then it's
2975 * FIFO full condition
2976 */
da6971d8
AR		 2977 if ((get_block == put_block) &&
2978 (get_info.offset + 1) == put_info.offset) {
0425b46a 2979 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
d44570e4 2980 ring_data->dev->name);
da6971d8
AR		 2981 break;
2982 }
d44570e4 2983 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
20346722 2984 if (skb == NULL) {
9e39f7c5 2985 DBG_PRINT(ERR_DBG, "%s: NULL skb in Rx Intr\n",
0425b46a 2986 ring_data->dev->name);
f61e0a35 2987 return 0;
1da177e4 2988 }
0425b46a 2989 if (ring_data->rxd_mode == RXD_MODE_1) {
d44570e4 2990 rxdp1 = (struct RxD1 *)rxdp;
0425b46a 2991 pci_unmap_single(ring_data->pdev, (dma_addr_t)
d44570e4
JP		 2992 rxdp1->Buffer0_ptr,
2993 ring_data->mtu +
2994 HEADER_ETHERNET_II_802_3_SIZE +
2995 HEADER_802_2_SIZE +
2996 HEADER_SNAP_SIZE,
2997 PCI_DMA_FROMDEVICE);
0425b46a 2998 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
d44570e4
JP		 2999 rxdp3 = (struct RxD3 *)rxdp;
3000 pci_dma_sync_single_for_cpu(ring_data->pdev,
3001 (dma_addr_t)rxdp3->Buffer0_ptr,
3002 BUF0_LEN,
3003 PCI_DMA_FROMDEVICE);
3004 pci_unmap_single(ring_data->pdev,
3005 (dma_addr_t)rxdp3->Buffer2_ptr,
3006 ring_data->mtu + 4,
3007 PCI_DMA_FROMDEVICE);
da6971d8 3008 }
863c11a9 3009 prefetch(skb->data);
20346722
K		 3010 rx_osm_handler(ring_data, rxdp);
3011 get_info.offset++;
da6971d8
AR		 3012 ring_data->rx_curr_get_info.offset = get_info.offset;
3013 rxdp = ring_data->rx_blocks[get_block].
d44570e4 3014 rxds[get_info.offset].virt_addr;
0425b46a 3015 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
20346722 3016 get_info.offset = 0;
da6971d8 3017 ring_data->rx_curr_get_info.offset = get_info.offset;
20346722 3018 get_block++;
da6971d8
AR		 3019 if (get_block == ring_data->block_count)
3020 get_block = 0;
3021 ring_data->rx_curr_get_info.block_index = get_block;
20346722
K		 3022 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3023 }
1da177e4 3024
f61e0a35
SH		 3025 if (ring_data->nic->config.napi) {
3026 budget--;
3027 napi_pkts++;
3028 if (!budget)
0425b46a
SH		 3029 break;
3030 }
20346722 3031 pkt_cnt++;
1da177e4
LT		 3032 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3033 break;
3034 }
0425b46a 3035 if (ring_data->lro) {
7d3d0439 3036 /* Clear all LRO sessions before exiting */
d44570e4 3037 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 3038 struct lro *lro = &ring_data->lro0_n[i];
7d3d0439 3039 if (lro->in_use) {
0425b46a 3040 update_L3L4_header(ring_data->nic, lro);
cdb5bf02 3041 queue_rx_frame(lro->parent, lro->vlan_tag);
7d3d0439
RA		 3042 clear_lro_session(lro);
3043 }
3044 }
3045 }
d44570e4 3046 return napi_pkts;
1da177e4 3047}
20346722
K		 3048
3049/**
1da177e4
LT		 3050 * tx_intr_handler - Transmit interrupt handler
3051 * @nic : device private variable
20346722
K		 3052 * Description:
3053 * If an interrupt was raised to indicate DMA complete of the
3054 * Tx packet, this function is called. It identifies the last TxD
3055 * whose buffer was freed and frees all skbs whose data have already
1da177e4
LT		 3056 * DMA'ed into the NICs internal memory.
3057 * Return Value:
3058 * NONE
3059 */
3060
1ee6dd77 3061static void tx_intr_handler(struct fifo_info *fifo_data)
1da177e4 3062{
1ee6dd77 3063 struct s2io_nic *nic = fifo_data->nic;
1ee6dd77 3064 struct tx_curr_get_info get_info, put_info;
3a3d5756 3065 struct sk_buff *skb = NULL;
1ee6dd77 3066 struct TxD *txdlp;
3a3d5756 3067 int pkt_cnt = 0;
2fda096d 3068 unsigned long flags = 0;
f9046eb3 3069 u8 err_mask;
ffb5df6c
JP		 3070 struct stat_block *stats = nic->mac_control.stats_info;
3071 struct swStat *swstats = &stats->sw_stat;
1da177e4 3072
2fda096d 3073 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
d44570e4 3074 return;
2fda096d 3075
20346722 3076 get_info = fifo_data->tx_curr_get_info;
1ee6dd77 3077 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
43d620c8 3078 txdlp = fifo_data->list_info[get_info.offset].list_virt_addr;
20346722
K		 3079 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3080 (get_info.offset != put_info.offset) &&
3081 (txdlp->Host_Control)) {
3082 /* Check for TxD errors */
3083 if (txdlp->Control_1 & TXD_T_CODE) {
3084 unsigned long long err;
3085 err = txdlp->Control_1 & TXD_T_CODE;
bd1034f0 3086 if (err & 0x1) {
ffb5df6c 3087 swstats->parity_err_cnt++;
bd1034f0 3088 }
491976b2
SH		 3089
3090 /* update t_code statistics */
f9046eb3 3091 err_mask = err >> 48;
d44570e4
JP		 3092 switch (err_mask) {
3093 case 2:
ffb5df6c 3094 swstats->tx_buf_abort_cnt++;
491976b2
SH		 3095 break;
3096
d44570e4 3097 case 3:
ffb5df6c 3098 swstats->tx_desc_abort_cnt++;
491976b2
SH		 3099 break;
3100
d44570e4 3101 case 7:
ffb5df6c 3102 swstats->tx_parity_err_cnt++;
491976b2
SH		 3103 break;
3104
d44570e4 3105 case 10:
ffb5df6c 3106 swstats->tx_link_loss_cnt++;
491976b2
SH		 3107 break;
3108
d44570e4 3109 case 15:
ffb5df6c 3110 swstats->tx_list_proc_err_cnt++;
491976b2 3111 break;
d44570e4 3112 }
20346722 3113 }
1da177e4 3114
fed5eccd 3115 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
20346722 3116 if (skb == NULL) {
2fda096d 3117 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
9e39f7c5
JP		 3118 DBG_PRINT(ERR_DBG, "%s: NULL skb in Tx Free Intr\n",
3119 __func__);
20346722
K		 3120 return;
3121 }
3a3d5756 3122 pkt_cnt++;
20346722 3123
20346722 3124 /* Updating the statistics block */
ffb5df6c 3125 swstats->mem_freed += skb->truesize;
20346722
K		 3126 dev_kfree_skb_irq(skb);
3127
3128 get_info.offset++;
863c11a9
AR		 3129 if (get_info.offset == get_info.fifo_len + 1)
3130 get_info.offset = 0;
43d620c8 3131 txdlp = fifo_data->list_info[get_info.offset].list_virt_addr;
d44570e4 3132 fifo_data->tx_curr_get_info.offset = get_info.offset;
1da177e4
LT		 3133 }
3134
3a3d5756 3135 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
2fda096d
SR		 3136
3137 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
1da177e4
LT		 3138}
3139
bd1034f0
AR		 3140/**
3141 * s2io_mdio_write - Function to write in to MDIO registers
3142 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3143 * @addr : address value
3144 * @value : data value
3145 * @dev : pointer to net_device structure
3146 * Description:
3147 * This function is used to write values to the MDIO registers
3148 * NONE
3149 */
d44570e4
JP		 3150static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3151 struct net_device *dev)
bd1034f0 3152{
d44570e4 3153 u64 val64;
4cf1653a 3154 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3155 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0 3156
d44570e4
JP		 3157 /* address transaction */
3158 val64 = MDIO_MMD_INDX_ADDR(addr) |
3159 MDIO_MMD_DEV_ADDR(mmd_type) |
3160 MDIO_MMS_PRT_ADDR(0x0);
bd1034f0
AR		 3161 writeq(val64, &bar0->mdio_control);
3162 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3163 writeq(val64, &bar0->mdio_control);
3164 udelay(100);
3165
d44570e4
JP		 3166 /* Data transaction */
3167 val64 = MDIO_MMD_INDX_ADDR(addr) |
3168 MDIO_MMD_DEV_ADDR(mmd_type) |
3169 MDIO_MMS_PRT_ADDR(0x0) |
3170 MDIO_MDIO_DATA(value) |
3171 MDIO_OP(MDIO_OP_WRITE_TRANS);
bd1034f0
AR		 3172 writeq(val64, &bar0->mdio_control);
3173 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3174 writeq(val64, &bar0->mdio_control);
3175 udelay(100);
3176
d44570e4
JP		 3177 val64 = MDIO_MMD_INDX_ADDR(addr) |
3178 MDIO_MMD_DEV_ADDR(mmd_type) |
3179 MDIO_MMS_PRT_ADDR(0x0) |
3180 MDIO_OP(MDIO_OP_READ_TRANS);
bd1034f0
AR		 3181 writeq(val64, &bar0->mdio_control);
3182 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3183 writeq(val64, &bar0->mdio_control);
3184 udelay(100);
bd1034f0
AR		 3185}
3186
3187/**
3188 * s2io_mdio_read - Function to write in to MDIO registers
3189 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3190 * @addr : address value
3191 * @dev : pointer to net_device structure
3192 * Description:
3193 * This function is used to read values to the MDIO registers
3194 * NONE
3195 */
3196static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3197{
3198 u64 val64 = 0x0;
3199 u64 rval64 = 0x0;
4cf1653a 3200 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3201 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3202
3203 /* address transaction */
d44570e4
JP		 3204 val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3205 | MDIO_MMD_DEV_ADDR(mmd_type)
3206 | MDIO_MMS_PRT_ADDR(0x0));
bd1034f0
AR		 3207 writeq(val64, &bar0->mdio_control);
3208 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3209 writeq(val64, &bar0->mdio_control);
3210 udelay(100);
3211
3212 /* Data transaction */
d44570e4
JP		 3213 val64 = MDIO_MMD_INDX_ADDR(addr) |
3214 MDIO_MMD_DEV_ADDR(mmd_type) |
3215 MDIO_MMS_PRT_ADDR(0x0) |
3216 MDIO_OP(MDIO_OP_READ_TRANS);
bd1034f0
AR		 3217 writeq(val64, &bar0->mdio_control);
3218 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3219 writeq(val64, &bar0->mdio_control);
3220 udelay(100);
3221
3222 /* Read the value from regs */
3223 rval64 = readq(&bar0->mdio_control);
3224 rval64 = rval64 & 0xFFFF0000;
3225 rval64 = rval64 >> 16;
3226 return rval64;
3227}
d44570e4 3228
bd1034f0
AR		 3229/**
3230 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
fbfecd37 3231 * @counter : counter value to be updated
bd1034f0
AR		 3232 * @flag : flag to indicate the status
3233 * @type : counter type
3234 * Description:
3235 * This function is to check the status of the xpak counters value
3236 * NONE
3237 */
3238
d44570e4
JP		 3239static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3240 u16 flag, u16 type)
bd1034f0
AR		 3241{
3242 u64 mask = 0x3;
3243 u64 val64;
3244 int i;
d44570e4 3245 for (i = 0; i < index; i++)
bd1034f0
AR		 3246 mask = mask << 0x2;
3247
d44570e4 3248 if (flag > 0) {
bd1034f0
AR		 3249 *counter = *counter + 1;
3250 val64 = *regs_stat & mask;
3251 val64 = val64 >> (index * 0x2);
3252 val64 = val64 + 1;
d44570e4
JP		 3253 if (val64 == 3) {
3254 switch (type) {
bd1034f0 3255 case 1:
9e39f7c5
JP		 3256 DBG_PRINT(ERR_DBG,
3257 "Take Xframe NIC out of service.\n");
3258 DBG_PRINT(ERR_DBG,
3259"Excessive temperatures may result in premature transceiver failure.\n");
d44570e4 3260 break;
bd1034f0 3261 case 2:
9e39f7c5
JP		 3262 DBG_PRINT(ERR_DBG,
3263 "Take Xframe NIC out of service.\n");
3264 DBG_PRINT(ERR_DBG,
3265"Excessive bias currents may indicate imminent laser diode failure.\n");
d44570e4 3266 break;
bd1034f0 3267 case 3:
9e39f7c5
JP		 3268 DBG_PRINT(ERR_DBG,
3269 "Take Xframe NIC out of service.\n");
3270 DBG_PRINT(ERR_DBG,
3271"Excessive laser output power may saturate far-end receiver.\n");
d44570e4 3272 break;
bd1034f0 3273 default:
d44570e4
JP		 3274 DBG_PRINT(ERR_DBG,
3275 "Incorrect XPAK Alarm type\n");
bd1034f0
AR		 3276 }
3277 val64 = 0x0;
3278 }
3279 val64 = val64 << (index * 0x2);
3280 *regs_stat = (*regs_stat & (~mask)) | (val64);
3281
3282 } else {
3283 *regs_stat = *regs_stat & (~mask);
3284 }
3285}
3286
3287/**
3288 * s2io_updt_xpak_counter - Function to update the xpak counters
3289 * @dev : pointer to net_device struct
3290 * Description:
3291 * This function is to upate the status of the xpak counters value
3292 * NONE
3293 */
3294static void s2io_updt_xpak_counter(struct net_device *dev)
3295{
3296 u16 flag = 0x0;
3297 u16 type = 0x0;
3298 u16 val16 = 0x0;
3299 u64 val64 = 0x0;
3300 u64 addr = 0x0;
3301
4cf1653a 3302 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c
JP		 3303 struct stat_block *stats = sp->mac_control.stats_info;
3304 struct xpakStat *xstats = &stats->xpak_stat;
bd1034f0
AR		 3305
3306 /* Check the communication with the MDIO slave */
40239396 3307 addr = MDIO_CTRL1;
bd1034f0 3308 val64 = 0x0;
40239396 3309 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
d44570e4 3310 if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
9e39f7c5
JP		 3311 DBG_PRINT(ERR_DBG,
3312 "ERR: MDIO slave access failed - Returned %llx\n",
3313 (unsigned long long)val64);
bd1034f0
AR		 3314 return;
3315 }
3316
40239396 3317 /* Check for the expected value of control reg 1 */
d44570e4 3318 if (val64 != MDIO_CTRL1_SPEED10G) {
9e39f7c5
JP		 3319 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - "
3320 "Returned: %llx- Expected: 0x%x\n",
40239396 3321 (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
bd1034f0
AR		 3322 return;
3323 }
3324
3325 /* Loading the DOM register to MDIO register */
3326 addr = 0xA100;
40239396
BH		 3327 s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3328 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3329
3330 /* Reading the Alarm flags */
3331 addr = 0xA070;
3332 val64 = 0x0;
40239396 3333 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3334
3335 flag = CHECKBIT(val64, 0x7);
3336 type = 1;
ffb5df6c
JP		 3337 s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high,
3338 &xstats->xpak_regs_stat,
d44570e4 3339 0x0, flag, type);
bd1034f0 3340
d44570e4 3341 if (CHECKBIT(val64, 0x6))
ffb5df6c 3342 xstats->alarm_transceiver_temp_low++;
bd1034f0
AR		 3343
3344 flag = CHECKBIT(val64, 0x3);
3345 type = 2;
ffb5df6c
JP		 3346 s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high,
3347 &xstats->xpak_regs_stat,
d44570e4 3348 0x2, flag, type);
bd1034f0 3349
d44570e4 3350 if (CHECKBIT(val64, 0x2))
ffb5df6c 3351 xstats->alarm_laser_bias_current_low++;
bd1034f0
AR		 3352
3353 flag = CHECKBIT(val64, 0x1);
3354 type = 3;
ffb5df6c
JP		 3355 s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high,
3356 &xstats->xpak_regs_stat,
d44570e4 3357 0x4, flag, type);
bd1034f0 3358
d44570e4 3359 if (CHECKBIT(val64, 0x0))
ffb5df6c 3360 xstats->alarm_laser_output_power_low++;
bd1034f0
AR		 3361
3362 /* Reading the Warning flags */
3363 addr = 0xA074;
3364 val64 = 0x0;
40239396 3365 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0 3366
d44570e4 3367 if (CHECKBIT(val64, 0x7))
ffb5df6c 3368 xstats->warn_transceiver_temp_high++;
bd1034f0 3369
d44570e4 3370 if (CHECKBIT(val64, 0x6))
ffb5df6c 3371 xstats->warn_transceiver_temp_low++;
bd1034f0 3372
d44570e4 3373 if (CHECKBIT(val64, 0x3))
ffb5df6c 3374 xstats->warn_laser_bias_current_high++;
bd1034f0 3375
d44570e4 3376 if (CHECKBIT(val64, 0x2))
ffb5df6c 3377 xstats->warn_laser_bias_current_low++;
bd1034f0 3378
d44570e4 3379 if (CHECKBIT(val64, 0x1))
ffb5df6c 3380 xstats->warn_laser_output_power_high++;
bd1034f0 3381
d44570e4 3382 if (CHECKBIT(val64, 0x0))
ffb5df6c 3383 xstats->warn_laser_output_power_low++;
bd1034f0
AR		 3384}
3385
20346722 3386/**
1da177e4 3387 * wait_for_cmd_complete - waits for a command to complete.
20346722 3388 * @sp : private member of the device structure, which is a pointer to the
1da177e4 3389 * s2io_nic structure.
20346722
K		 3390 * Description: Function that waits for a command to Write into RMAC
3391 * ADDR DATA registers to be completed and returns either success or
3392 * error depending on whether the command was complete or not.
1da177e4
LT		 3393 * Return value:
3394 * SUCCESS on success and FAILURE on failure.
3395 */
3396
9fc93a41 3397static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
d44570e4 3398 int bit_state)
1da177e4 3399{
9fc93a41 3400 int ret = FAILURE, cnt = 0, delay = 1;
1da177e4
LT		 3401 u64 val64;
3402
9fc93a41
SS		 3403 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3404 return FAILURE;
3405
3406 do {
c92ca04b 3407 val64 = readq(addr);
9fc93a41
SS		 3408 if (bit_state == S2IO_BIT_RESET) {
3409 if (!(val64 & busy_bit)) {
3410 ret = SUCCESS;
3411 break;
3412 }
3413 } else {
2d146eb1 3414 if (val64 & busy_bit) {
9fc93a41
SS		 3415 ret = SUCCESS;
3416 break;
3417 }
1da177e4 3418 }
c92ca04b 3419
d44570e4 3420 if (in_interrupt())
9fc93a41 3421 mdelay(delay);
c92ca04b 3422 else
9fc93a41 3423 msleep(delay);
c92ca04b 3424
9fc93a41
SS		 3425 if (++cnt >= 10)
3426 delay = 50;
3427 } while (cnt < 20);
1da177e4
LT		 3428 return ret;
3429}
19a60522
SS		 3430/*
3431 * check_pci_device_id - Checks if the device id is supported
3432 * @id : device id
3433 * Description: Function to check if the pci device id is supported by driver.
3434 * Return value: Actual device id if supported else PCI_ANY_ID
3435 */
3436static u16 check_pci_device_id(u16 id)
3437{
3438 switch (id) {
3439 case PCI_DEVICE_ID_HERC_WIN:
3440 case PCI_DEVICE_ID_HERC_UNI:
3441 return XFRAME_II_DEVICE;
3442 case PCI_DEVICE_ID_S2IO_UNI:
3443 case PCI_DEVICE_ID_S2IO_WIN:
3444 return XFRAME_I_DEVICE;
3445 default:
3446 return PCI_ANY_ID;
3447 }
3448}
1da177e4 3449
20346722
K		 3450/**
3451 * s2io_reset - Resets the card.
1da177e4
LT		 3452 * @sp : private member of the device structure.
3453 * Description: Function to Reset the card. This function then also
20346722 3454 * restores the previously saved PCI configuration space registers as
1da177e4
LT		 3455 * the card reset also resets the configuration space.
3456 * Return value:
3457 * void.
3458 */
3459
d44570e4 3460static void s2io_reset(struct s2io_nic *sp)
1da177e4 3461{
1ee6dd77 3462 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 3463 u64 val64;
5e25b9dd 3464 u16 subid, pci_cmd;
19a60522
SS		 3465 int i;
3466 u16 val16;
491976b2
SH		 3467 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3468 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
ffb5df6c
JP		 3469 struct stat_block *stats;
3470 struct swStat *swstats;
491976b2 3471
9e39f7c5 3472 DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n",
3a22813a 3473 __func__, pci_name(sp->pdev));
1da177e4 3474
0b1f7ebe 3475 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
e960fc5c 3476 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
0b1f7ebe 3477
1da177e4
LT		 3478 val64 = SW_RESET_ALL;
3479 writeq(val64, &bar0->sw_reset);
d44570e4 3480 if (strstr(sp->product_name, "CX4"))
c92ca04b 3481 msleep(750);
19a60522
SS		 3482 msleep(250);
3483 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
1da177e4 3484
19a60522
SS		 3485 /* Restore the PCI state saved during initialization. */
3486 pci_restore_state(sp->pdev);
b8a623bf 3487 pci_save_state(sp->pdev);
19a60522
SS		 3488 pci_read_config_word(sp->pdev, 0x2, &val16);
3489 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3490 break;
3491 msleep(200);
3492 }
1da177e4 3493
d44570e4
JP		 3494 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3495 DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
19a60522
SS		 3496
3497 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3498
3499 s2io_init_pci(sp);
1da177e4 3500
20346722
K		 3501 /* Set swapper to enable I/O register access */
3502 s2io_set_swapper(sp);
3503
faa4f796
SH		 3504 /* restore mac_addr entries */
3505 do_s2io_restore_unicast_mc(sp);
3506
cc6e7c44
RA		 3507 /* Restore the MSIX table entries from local variables */
3508 restore_xmsi_data(sp);
3509
5e25b9dd 3510 /* Clear certain PCI/PCI-X fields after reset */
303bcb4b 3511 if (sp->device_type == XFRAME_II_DEVICE) {
b41477f3 3512 /* Clear "detected parity error" bit */
303bcb4b 3513 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
5e25b9dd 3514
303bcb4b
K		 3515 /* Clearing PCIX Ecc status register */
3516 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
5e25b9dd 3517
303bcb4b 3518 /* Clearing PCI_STATUS error reflected here */
b7b5a128 3519 writeq(s2BIT(62), &bar0->txpic_int_reg);
303bcb4b 3520 }
5e25b9dd 3521
20346722 3522 /* Reset device statistics maintained by OS */
d44570e4 3523 memset(&sp->stats, 0, sizeof(struct net_device_stats));
8a4bdbaa 3524
ffb5df6c
JP		 3525 stats = sp->mac_control.stats_info;
3526 swstats = &stats->sw_stat;
3527
491976b2 3528 /* save link up/down time/cnt, reset/memory/watchdog cnt */
ffb5df6c
JP		 3529 up_cnt = swstats->link_up_cnt;
3530 down_cnt = swstats->link_down_cnt;
3531 up_time = swstats->link_up_time;
3532 down_time = swstats->link_down_time;
3533 reset_cnt = swstats->soft_reset_cnt;
3534 mem_alloc_cnt = swstats->mem_allocated;
3535 mem_free_cnt = swstats->mem_freed;
3536 watchdog_cnt = swstats->watchdog_timer_cnt;
3537
3538 memset(stats, 0, sizeof(struct stat_block));
3539
491976b2 3540 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
ffb5df6c
JP		 3541 swstats->link_up_cnt = up_cnt;
3542 swstats->link_down_cnt = down_cnt;
3543 swstats->link_up_time = up_time;
3544 swstats->link_down_time = down_time;
3545 swstats->soft_reset_cnt = reset_cnt;
3546 swstats->mem_allocated = mem_alloc_cnt;
3547 swstats->mem_freed = mem_free_cnt;
3548 swstats->watchdog_timer_cnt = watchdog_cnt;
20346722 3549
1da177e4
LT		 3550 /* SXE-002: Configure link and activity LED to turn it off */
3551 subid = sp->pdev->subsystem_device;
541ae68f
K		 3552 if (((subid & 0xFF) >= 0x07) &&
3553 (sp->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 3554 val64 = readq(&bar0->gpio_control);
3555 val64 |= 0x0000800000000000ULL;
3556 writeq(val64, &bar0->gpio_control);
3557 val64 = 0x0411040400000000ULL;
509a2671 3558 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 3559 }
3560
541ae68f 3561 /*
25985edc 3562 * Clear spurious ECC interrupts that would have occurred on
541ae68f
K		 3563 * XFRAME II cards after reset.
3564 */
3565 if (sp->device_type == XFRAME_II_DEVICE) {
3566 val64 = readq(&bar0->pcc_err_reg);
3567 writeq(val64, &bar0->pcc_err_reg);
3568 }
3569
f957bcf0 3570 sp->device_enabled_once = false;
1da177e4
LT		 3571}
3572
3573/**
20346722
K		 3574 * s2io_set_swapper - to set the swapper controle on the card
3575 * @sp : private member of the device structure,
1da177e4 3576 * pointer to the s2io_nic structure.
20346722 3577 * Description: Function to set the swapper control on the card
1da177e4
LT		 3578 * correctly depending on the 'endianness' of the system.
3579 * Return value:
3580 * SUCCESS on success and FAILURE on failure.
3581 */
3582
d44570e4 3583static int s2io_set_swapper(struct s2io_nic *sp)
1da177e4
LT		 3584{
3585 struct net_device *dev = sp->dev;
1ee6dd77 3586 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 3587 u64 val64, valt, valr;
3588
20346722 3589 /*
1da177e4
LT		 3590 * Set proper endian settings and verify the same by reading
3591 * the PIF Feed-back register.
3592 */
3593
3594 val64 = readq(&bar0->pif_rd_swapper_fb);
3595 if (val64 != 0x0123456789ABCDEFULL) {
3596 int i = 0;
85a56498
JM		 3597 static const u64 value[] = {
3598 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3599 0x8100008181000081ULL, /* FE=1, SE=0 */
3600 0x4200004242000042ULL, /* FE=0, SE=1 */
3601 0 /* FE=0, SE=0 */
3602 };
1da177e4 3603
d44570e4 3604 while (i < 4) {
1da177e4
LT		 3605 writeq(value[i], &bar0->swapper_ctrl);
3606 val64 = readq(&bar0->pif_rd_swapper_fb);
3607 if (val64 == 0x0123456789ABCDEFULL)
3608 break;
3609 i++;
3610 }
3611 if (i == 4) {
9e39f7c5
JP		 3612 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, "
3613 "feedback read %llx\n",
3614 dev->name, (unsigned long long)val64);
1da177e4
LT		 3615 return FAILURE;
3616 }
3617 valr = value[i];
3618 } else {
3619 valr = readq(&bar0->swapper_ctrl);
3620 }
3621
3622 valt = 0x0123456789ABCDEFULL;
3623 writeq(valt, &bar0->xmsi_address);
3624 val64 = readq(&bar0->xmsi_address);
3625
d44570e4 3626 if (val64 != valt) {
1da177e4 3627 int i = 0;
85a56498
JM		 3628 static const u64 value[] = {
3629 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3630 0x0081810000818100ULL, /* FE=1, SE=0 */
3631 0x0042420000424200ULL, /* FE=0, SE=1 */
3632 0 /* FE=0, SE=0 */
3633 };
1da177e4 3634
d44570e4 3635 while (i < 4) {
1da177e4
LT		 3636 writeq((value[i] | valr), &bar0->swapper_ctrl);
3637 writeq(valt, &bar0->xmsi_address);
3638 val64 = readq(&bar0->xmsi_address);
d44570e4 3639 if (val64 == valt)
1da177e4
LT		 3640 break;
3641 i++;
3642 }
d44570e4 3643 if (i == 4) {
20346722 3644 unsigned long long x = val64;
9e39f7c5
JP		 3645 DBG_PRINT(ERR_DBG,
3646 "Write failed, Xmsi_addr reads:0x%llx\n", x);
1da177e4
LT		 3647 return FAILURE;
3648 }
3649 }
3650 val64 = readq(&bar0->swapper_ctrl);
3651 val64 &= 0xFFFF000000000000ULL;
3652
d44570e4 3653#ifdef __BIG_ENDIAN
20346722
K		 3654 /*
3655 * The device by default set to a big endian format, so a
1da177e4
LT		 3656 * big endian driver need not set anything.
3657 */
3658 val64 |= (SWAPPER_CTRL_TXP_FE |
d44570e4
JP		 3659 SWAPPER_CTRL_TXP_SE |
3660 SWAPPER_CTRL_TXD_R_FE |
3661 SWAPPER_CTRL_TXD_W_FE |
3662 SWAPPER_CTRL_TXF_R_FE |
3663 SWAPPER_CTRL_RXD_R_FE |
3664 SWAPPER_CTRL_RXD_W_FE |
3665 SWAPPER_CTRL_RXF_W_FE |
3666 SWAPPER_CTRL_XMSI_FE |
3667 SWAPPER_CTRL_STATS_FE |
3668 SWAPPER_CTRL_STATS_SE);
eaae7f72 3669 if (sp->config.intr_type == INTA)
cc6e7c44 3670 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3671 writeq(val64, &bar0->swapper_ctrl);
3672#else
20346722 3673 /*
1da177e4 3674 * Initially we enable all bits to make it accessible by the
20346722 3675 * driver, then we selectively enable only those bits that
1da177e4
LT		 3676 * we want to set.
3677 */
3678 val64 |= (SWAPPER_CTRL_TXP_FE |
d44570e4
JP		 3679 SWAPPER_CTRL_TXP_SE |
3680 SWAPPER_CTRL_TXD_R_FE |
3681 SWAPPER_CTRL_TXD_R_SE |
3682 SWAPPER_CTRL_TXD_W_FE |
3683 SWAPPER_CTRL_TXD_W_SE |
3684 SWAPPER_CTRL_TXF_R_FE |
3685 SWAPPER_CTRL_RXD_R_FE |
3686 SWAPPER_CTRL_RXD_R_SE |
3687 SWAPPER_CTRL_RXD_W_FE |
3688 SWAPPER_CTRL_RXD_W_SE |
3689 SWAPPER_CTRL_RXF_W_FE |
3690 SWAPPER_CTRL_XMSI_FE |
3691 SWAPPER_CTRL_STATS_FE |
3692 SWAPPER_CTRL_STATS_SE);
eaae7f72 3693 if (sp->config.intr_type == INTA)
cc6e7c44 3694 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3695 writeq(val64, &bar0->swapper_ctrl);
3696#endif
3697 val64 = readq(&bar0->swapper_ctrl);
3698
20346722
K		 3699 /*
3700 * Verifying if endian settings are accurate by reading a
1da177e4
LT		 3701 * feedback register.
3702 */
3703 val64 = readq(&bar0->pif_rd_swapper_fb);
3704 if (val64 != 0x0123456789ABCDEFULL) {
3705 /* Endian settings are incorrect, calls for another dekko. */
9e39f7c5
JP		 3706 DBG_PRINT(ERR_DBG,
3707 "%s: Endian settings are wrong, feedback read %llx\n",
3708 dev->name, (unsigned long long)val64);
1da177e4
LT		 3709 return FAILURE;
3710 }
3711
3712 return SUCCESS;
3713}
3714
1ee6dd77 3715static int wait_for_msix_trans(struct s2io_nic *nic, int i)
cc6e7c44 3716{
1ee6dd77 3717 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3718 u64 val64;
3719 int ret = 0, cnt = 0;
3720
3721 do {
3722 val64 = readq(&bar0->xmsi_access);
b7b5a128 3723 if (!(val64 & s2BIT(15)))
cc6e7c44
RA		 3724 break;
3725 mdelay(1);
3726 cnt++;
d44570e4 3727 } while (cnt < 5);
cc6e7c44
RA		 3728 if (cnt == 5) {
3729 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3730 ret = 1;
3731 }
3732
3733 return ret;
3734}
3735
1ee6dd77 3736static void restore_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3737{
1ee6dd77 3738 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44 3739 u64 val64;
f61e0a35
SH		 3740 int i, msix_index;
3741
f61e0a35
SH		 3742 if (nic->device_type == XFRAME_I_DEVICE)
3743 return;
cc6e7c44 3744
d44570e4
JP		 3745 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3746 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
cc6e7c44
RA		 3747 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3748 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
f61e0a35 3749 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
cc6e7c44 3750 writeq(val64, &bar0->xmsi_access);
f61e0a35 3751 if (wait_for_msix_trans(nic, msix_index)) {
9e39f7c5
JP		 3752 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3753 __func__, msix_index);
cc6e7c44
RA		 3754 continue;
3755 }
3756 }
3757}
3758
1ee6dd77 3759static void store_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3760{
1ee6dd77 3761 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44 3762 u64 val64, addr, data;
f61e0a35
SH		 3763 int i, msix_index;
3764
3765 if (nic->device_type == XFRAME_I_DEVICE)
3766 return;
cc6e7c44
RA		 3767
3768 /* Store and display */
d44570e4
JP		 3769 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3770 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
f61e0a35 3771 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
cc6e7c44 3772 writeq(val64, &bar0->xmsi_access);
f61e0a35 3773 if (wait_for_msix_trans(nic, msix_index)) {
9e39f7c5
JP		 3774 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3775 __func__, msix_index);
cc6e7c44
RA		 3776 continue;
3777 }
3778 addr = readq(&bar0->xmsi_address);
3779 data = readq(&bar0->xmsi_data);
3780 if (addr && data) {
3781 nic->msix_info[i].addr = addr;
3782 nic->msix_info[i].data = data;
3783 }
3784 }
3785}
3786
1ee6dd77 3787static int s2io_enable_msi_x(struct s2io_nic *nic)
cc6e7c44 3788{
1ee6dd77 3789 struct XENA_dev_config __iomem *bar0 = nic->bar0;
ac731ab6 3790 u64 rx_mat;
cc6e7c44
RA		 3791 u16 msi_control; /* Temp variable */
3792 int ret, i, j, msix_indx = 1;
4f870320 3793 int size;
ffb5df6c
JP		 3794 struct stat_block *stats = nic->mac_control.stats_info;
3795 struct swStat *swstats = &stats->sw_stat;
cc6e7c44 3796
4f870320 3797 size = nic->num_entries * sizeof(struct msix_entry);
44364a03 3798 nic->entries = kzalloc(size, GFP_KERNEL);
bd684e43 3799 if (!nic->entries) {
d44570e4
JP		 3800 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3801 __func__);
ffb5df6c 3802 swstats->mem_alloc_fail_cnt++;
cc6e7c44
RA		 3803 return -ENOMEM;
3804 }
ffb5df6c 3805 swstats->mem_allocated += size;
f61e0a35 3806
4f870320 3807 size = nic->num_entries * sizeof(struct s2io_msix_entry);
44364a03 3808 nic->s2io_entries = kzalloc(size, GFP_KERNEL);
bd684e43 3809 if (!nic->s2io_entries) {
8a4bdbaa 3810 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
d44570e4 3811 __func__);
ffb5df6c 3812 swstats->mem_alloc_fail_cnt++;
cc6e7c44 3813 kfree(nic->entries);
ffb5df6c 3814 swstats->mem_freed
f61e0a35 3815 += (nic->num_entries * sizeof(struct msix_entry));
cc6e7c44
RA		 3816 return -ENOMEM;
3817 }
ffb5df6c 3818 swstats->mem_allocated += size;
cc6e7c44 3819
ac731ab6
SH		 3820 nic->entries[0].entry = 0;
3821 nic->s2io_entries[0].entry = 0;
3822 nic->s2io_entries[0].in_use = MSIX_FLG;
3823 nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3824 nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3825
f61e0a35
SH		 3826 for (i = 1; i < nic->num_entries; i++) {
3827 nic->entries[i].entry = ((i - 1) * 8) + 1;
3828 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
cc6e7c44
RA		 3829 nic->s2io_entries[i].arg = NULL;
3830 nic->s2io_entries[i].in_use = 0;
3831 }
3832
8a4bdbaa 3833 rx_mat = readq(&bar0->rx_mat);
f61e0a35 3834 for (j = 0; j < nic->config.rx_ring_num; j++) {
8a4bdbaa 3835 rx_mat |= RX_MAT_SET(j, msix_indx);
f61e0a35
SH		 3836 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3837 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3838 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3839 msix_indx += 8;
cc6e7c44 3840 }
8a4bdbaa 3841 writeq(rx_mat, &bar0->rx_mat);
f61e0a35 3842 readq(&bar0->rx_mat);
cc6e7c44 3843
f61e0a35 3844 ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
c92ca04b 3845 /* We fail init if error or we get less vectors than min required */
cc6e7c44 3846 if (ret) {
9e39f7c5 3847 DBG_PRINT(ERR_DBG, "Enabling MSI-X failed\n");
cc6e7c44 3848 kfree(nic->entries);
ffb5df6c
JP		 3849 swstats->mem_freed += nic->num_entries *
3850 sizeof(struct msix_entry);
cc6e7c44 3851 kfree(nic->s2io_entries);
ffb5df6c
JP		 3852 swstats->mem_freed += nic->num_entries *
3853 sizeof(struct s2io_msix_entry);
cc6e7c44
RA		 3854 nic->entries = NULL;
3855 nic->s2io_entries = NULL;
3856 return -ENOMEM;
3857 }
3858
3859 /*
3860 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3861 * in the herc NIC. (Temp change, needs to be removed later)
3862 */
3863 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3864 msi_control |= 0x1; /* Enable MSI */
3865 pci_write_config_word(nic->pdev, 0x42, msi_control);
3866
3867 return 0;
3868}
3869
8abc4d5b 3870/* Handle software interrupt used during MSI(X) test */
33390a70 3871static irqreturn_t s2io_test_intr(int irq, void *dev_id)
8abc4d5b
SS		 3872{
3873 struct s2io_nic *sp = dev_id;
3874
3875 sp->msi_detected = 1;
3876 wake_up(&sp->msi_wait);
3877
3878 return IRQ_HANDLED;
3879}
3880
3881/* Test interrupt path by forcing a a software IRQ */
33390a70 3882static int s2io_test_msi(struct s2io_nic *sp)
8abc4d5b
SS		 3883{
3884 struct pci_dev *pdev = sp->pdev;
3885 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3886 int err;
3887 u64 val64, saved64;
3888
3889 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
d44570e4 3890 sp->name, sp);
8abc4d5b
SS		 3891 if (err) {
3892 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
d44570e4 3893 sp->dev->name, pci_name(pdev), pdev->irq);
8abc4d5b
SS		 3894 return err;
3895 }
3896
d44570e4 3897 init_waitqueue_head(&sp->msi_wait);
8abc4d5b
SS		 3898 sp->msi_detected = 0;
3899
3900 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3901 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3902 val64 |= SCHED_INT_CTRL_TIMER_EN;
3903 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3904 writeq(val64, &bar0->scheduled_int_ctrl);
3905
3906 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3907
3908 if (!sp->msi_detected) {
3909 /* MSI(X) test failed, go back to INTx mode */
2450022a 3910 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
9e39f7c5
JP		 3911 "using MSI(X) during test\n",
3912 sp->dev->name, pci_name(pdev));
8abc4d5b
SS		 3913
3914 err = -EOPNOTSUPP;
3915 }
3916
3917 free_irq(sp->entries[1].vector, sp);
3918
3919 writeq(saved64, &bar0->scheduled_int_ctrl);
3920
3921 return err;
3922}
18b2b7bd
SH		 3923
3924static void remove_msix_isr(struct s2io_nic *sp)
3925{
3926 int i;
3927 u16 msi_control;
3928
f61e0a35 3929 for (i = 0; i < sp->num_entries; i++) {
d44570e4 3930 if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
18b2b7bd
SH		 3931 int vector = sp->entries[i].vector;
3932 void *arg = sp->s2io_entries[i].arg;
3933 free_irq(vector, arg);
3934 }
3935 }
3936
3937 kfree(sp->entries);
3938 kfree(sp->s2io_entries);
3939 sp->entries = NULL;
3940 sp->s2io_entries = NULL;
3941
3942 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3943 msi_control &= 0xFFFE; /* Disable MSI */
3944 pci_write_config_word(sp->pdev, 0x42, msi_control);
3945
3946 pci_disable_msix(sp->pdev);
3947}
3948
3949static void remove_inta_isr(struct s2io_nic *sp)
3950{
3951 struct net_device *dev = sp->dev;
3952
3953 free_irq(sp->pdev->irq, dev);
3954}
3955
1da177e4
LT		 3956/* ********************************************************* *
3957 * Functions defined below concern the OS part of the driver *
3958 * ********************************************************* */
3959
20346722 3960/**
1da177e4
LT		 3961 * s2io_open - open entry point of the driver
3962 * @dev : pointer to the device structure.
3963 * Description:
3964 * This function is the open entry point of the driver. It mainly calls a
3965 * function to allocate Rx buffers and inserts them into the buffer
20346722 3966 * descriptors and then enables the Rx part of the NIC.
1da177e4
LT		 3967 * Return value:
3968 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3969 * file on failure.
3970 */
3971
ac1f60db 3972static int s2io_open(struct net_device *dev)
1da177e4 3973{
4cf1653a 3974 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c 3975 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 3976 int err = 0;
3977
20346722
K		 3978 /*
3979 * Make sure you have link off by default every time
1da177e4
LT		 3980 * Nic is initialized
3981 */
3982 netif_carrier_off(dev);
0b1f7ebe 3983 sp->last_link_state = 0;
1da177e4
LT		 3984
3985 /* Initialize H/W and enable interrupts */
c92ca04b
AR		 3986 err = s2io_card_up(sp);
3987 if (err) {
1da177e4
LT		 3988 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3989 dev->name);
e6a8fee2 3990 goto hw_init_failed;
1da177e4
LT		 3991 }
3992
2fd37688 3993 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
1da177e4 3994 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
e6a8fee2 3995 s2io_card_down(sp);
20346722 3996 err = -ENODEV;
e6a8fee2 3997 goto hw_init_failed;
1da177e4 3998 }
3a3d5756 3999 s2io_start_all_tx_queue(sp);
1da177e4 4000 return 0;
20346722 4001
20346722 4002hw_init_failed:
eaae7f72 4003 if (sp->config.intr_type == MSI_X) {
491976b2 4004 if (sp->entries) {
cc6e7c44 4005 kfree(sp->entries);
ffb5df6c
JP		 4006 swstats->mem_freed += sp->num_entries *
4007 sizeof(struct msix_entry);
491976b2
SH		 4008 }
4009 if (sp->s2io_entries) {
cc6e7c44 4010 kfree(sp->s2io_entries);
ffb5df6c
JP		 4011 swstats->mem_freed += sp->num_entries *
4012 sizeof(struct s2io_msix_entry);
491976b2 4013 }
cc6e7c44 4014 }
20346722 4015 return err;
1da177e4
LT		 4016}
4017
4018/**
4019 * s2io_close -close entry point of the driver
4020 * @dev : device pointer.
4021 * Description:
4022 * This is the stop entry point of the driver. It needs to undo exactly
4023 * whatever was done by the open entry point,thus it's usually referred to
4024 * as the close function.Among other things this function mainly stops the
4025 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4026 * Return value:
4027 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4028 * file on failure.
4029 */
4030
ac1f60db 4031static int s2io_close(struct net_device *dev)
1da177e4 4032{
4cf1653a 4033 struct s2io_nic *sp = netdev_priv(dev);
faa4f796
SH		 4034 struct config_param *config = &sp->config;
4035 u64 tmp64;
4036 int offset;
cc6e7c44 4037
9f74ffde 4038 /* Return if the device is already closed *
d44570e4
JP		 4039 * Can happen when s2io_card_up failed in change_mtu *
4040 */
9f74ffde
SH		 4041 if (!is_s2io_card_up(sp))
4042 return 0;
4043
3a3d5756 4044 s2io_stop_all_tx_queue(sp);
faa4f796
SH		 4045 /* delete all populated mac entries */
4046 for (offset = 1; offset < config->max_mc_addr; offset++) {
4047 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4048 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4049 do_s2io_delete_unicast_mc(sp, tmp64);
4050 }
4051
e6a8fee2 4052 s2io_card_down(sp);
cc6e7c44 4053
1da177e4
LT		 4054 return 0;
4055}
4056
4057/**
4058 * s2io_xmit - Tx entry point of te driver
4059 * @skb : the socket buffer containing the Tx data.
4060 * @dev : device pointer.
4061 * Description :
4062 * This function is the Tx entry point of the driver. S2IO NIC supports
4063 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
25985edc 4064 * NOTE: when device can't queue the pkt,just the trans_start variable will
1da177e4
LT		 4065 * not be upadted.
4066 * Return value:
4067 * 0 on success & 1 on failure.
4068 */
4069
61357325 4070static netdev_tx_t s2io_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 4071{
4cf1653a 4072 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 4073 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4074 register u64 val64;
1ee6dd77
RB		 4075 struct TxD *txdp;
4076 struct TxFIFO_element __iomem *tx_fifo;
2fda096d 4077 unsigned long flags = 0;
be3a6b02 4078 u16 vlan_tag = 0;
2fda096d 4079 struct fifo_info *fifo = NULL;
6cfc482b 4080 int do_spin_lock = 1;
75c30b13 4081 int offload_type;
6cfc482b 4082 int enable_per_list_interrupt = 0;
ffb5df6c
JP		 4083 struct config_param *config = &sp->config;
4084 struct mac_info *mac_control = &sp->mac_control;
4085 struct stat_block *stats = mac_control->stats_info;
4086 struct swStat *swstats = &stats->sw_stat;
1da177e4 4087
20346722 4088 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
491976b2
SH		 4089
4090 if (unlikely(skb->len <= 0)) {
9e39f7c5 4091 DBG_PRINT(TX_DBG, "%s: Buffer has no data..\n", dev->name);
491976b2 4092 dev_kfree_skb_any(skb);
6ed10654 4093 return NETDEV_TX_OK;
2fda096d 4094 }
491976b2 4095
92b84437 4096 if (!is_s2io_card_up(sp)) {
20346722 4097 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
1da177e4 4098 dev->name);
20346722 4099 dev_kfree_skb(skb);
6ed10654 4100 return NETDEV_TX_OK;
1da177e4
LT		 4101 }
4102
4103 queue = 0;
eab6d18d 4104 if (vlan_tx_tag_present(skb))
be3a6b02 4105 vlan_tag = vlan_tx_tag_get(skb);
6cfc482b
SH		 4106 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4107 if (skb->protocol == htons(ETH_P_IP)) {
4108 struct iphdr *ip;
4109 struct tcphdr *th;
4110 ip = ip_hdr(skb);
4111
4112 if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4113 th = (struct tcphdr *)(((unsigned char *)ip) +
d44570e4 4114 ip->ihl*4);
6cfc482b
SH		 4115
4116 if (ip->protocol == IPPROTO_TCP) {
4117 queue_len = sp->total_tcp_fifos;
4118 queue = (ntohs(th->source) +
d44570e4
JP		 4119 ntohs(th->dest)) &
4120 sp->fifo_selector[queue_len - 1];
6cfc482b
SH		 4121 if (queue >= queue_len)
4122 queue = queue_len - 1;
4123 } else if (ip->protocol == IPPROTO_UDP) {
4124 queue_len = sp->total_udp_fifos;
4125 queue = (ntohs(th->source) +
d44570e4
JP		 4126 ntohs(th->dest)) &
4127 sp->fifo_selector[queue_len - 1];
6cfc482b
SH		 4128 if (queue >= queue_len)
4129 queue = queue_len - 1;
4130 queue += sp->udp_fifo_idx;
4131 if (skb->len > 1024)
4132 enable_per_list_interrupt = 1;
4133 do_spin_lock = 0;
4134 }
4135 }
4136 }
4137 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4138 /* get fifo number based on skb->priority value */
4139 queue = config->fifo_mapping
d44570e4 4140 [skb->priority & (MAX_TX_FIFOS - 1)];
6cfc482b 4141 fifo = &mac_control->fifos[queue];
3a3d5756 4142
6cfc482b
SH		 4143 if (do_spin_lock)
4144 spin_lock_irqsave(&fifo->tx_lock, flags);
4145 else {
4146 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4147 return NETDEV_TX_LOCKED;
4148 }
be3a6b02 4149
3a3d5756
SH		 4150 if (sp->config.multiq) {
4151 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4152 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4153 return NETDEV_TX_BUSY;
4154 }
b19fa1fa 4155 } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
3a3d5756
SH		 4156 if (netif_queue_stopped(dev)) {
4157 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4158 return NETDEV_TX_BUSY;
4159 }
4160 }
4161
d44570e4
JP		 4162 put_off = (u16)fifo->tx_curr_put_info.offset;
4163 get_off = (u16)fifo->tx_curr_get_info.offset;
43d620c8 4164 txdp = fifo->list_info[put_off].list_virt_addr;
20346722 4165
2fda096d 4166 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
1da177e4 4167 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4168 if (txdp->Host_Control ||
d44570e4 4169 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
776bd20f 4170 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3a3d5756 4171 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4172 dev_kfree_skb(skb);
2fda096d 4173 spin_unlock_irqrestore(&fifo->tx_lock, flags);
6ed10654 4174 return NETDEV_TX_OK;
1da177e4 4175 }
0b1f7ebe 4176
75c30b13 4177 offload_type = s2io_offload_type(skb);
75c30b13 4178 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1da177e4 4179 txdp->Control_1 |= TXD_TCP_LSO_EN;
75c30b13 4180 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
1da177e4 4181 }
84fa7933 4182 if (skb->ip_summed == CHECKSUM_PARTIAL) {
d44570e4
JP		 4183 txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4184 TXD_TX_CKO_TCP_EN |
4185 TXD_TX_CKO_UDP_EN);
1da177e4 4186 }
fed5eccd
AR		 4187 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4188 txdp->Control_1 |= TXD_LIST_OWN_XENA;
2fda096d 4189 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
6cfc482b
SH		 4190 if (enable_per_list_interrupt)
4191 if (put_off & (queue_len >> 5))
4192 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
3a3d5756 4193 if (vlan_tag) {
be3a6b02
K		 4194 txdp->Control_2 |= TXD_VLAN_ENABLE;
4195 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4196 }
4197
e743d313 4198 frg_len = skb_headlen(skb);
75c30b13 4199 if (offload_type == SKB_GSO_UDP) {
fed5eccd
AR		 4200 int ufo_size;
4201
75c30b13 4202 ufo_size = s2io_udp_mss(skb);
fed5eccd
AR		 4203 ufo_size &= ~7;
4204 txdp->Control_1 |= TXD_UFO_EN;
4205 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4206 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4207#ifdef __BIG_ENDIAN
3459feb8 4208 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
2fda096d 4209 fifo->ufo_in_band_v[put_off] =
d44570e4 4210 (__force u64)skb_shinfo(skb)->ip6_frag_id;
fed5eccd 4211#else
2fda096d 4212 fifo->ufo_in_band_v[put_off] =
d44570e4 4213 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
fed5eccd 4214#endif
2fda096d 4215 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
fed5eccd 4216 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
d44570e4
JP		 4217 fifo->ufo_in_band_v,
4218 sizeof(u64),
4219 PCI_DMA_TODEVICE);
8d8bb39b 4220 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
491abf25 4221 goto pci_map_failed;
fed5eccd 4222 txdp++;
fed5eccd 4223 }
1da177e4 4224
d44570e4
JP		 4225 txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data,
4226 frg_len, PCI_DMA_TODEVICE);
8d8bb39b 4227 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
491abf25
VP		 4228 goto pci_map_failed;
4229
d44570e4 4230 txdp->Host_Control = (unsigned long)skb;
fed5eccd 4231 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
75c30b13 4232 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4233 txdp->Control_1 |= TXD_UFO_EN;
4234
4235 frg_cnt = skb_shinfo(skb)->nr_frags;
1da177e4
LT		 4236 /* For fragmented SKB. */
4237 for (i = 0; i < frg_cnt; i++) {
4238 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0b1f7ebe
K		 4239 /* A '0' length fragment will be ignored */
4240 if (!frag->size)
4241 continue;
1da177e4 4242 txdp++;
d44570e4
JP		 4243 txdp->Buffer_Pointer = (u64)pci_map_page(sp->pdev, frag->page,
4244 frag->page_offset,
4245 frag->size,
4246 PCI_DMA_TODEVICE);
efd51b5c 4247 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
75c30b13 4248 if (offload_type == SKB_GSO_UDP)
fed5eccd 4249 txdp->Control_1 |= TXD_UFO_EN;
1da177e4
LT		 4250 }
4251 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4252
75c30b13 4253 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4254 frg_cnt++; /* as Txd0 was used for inband header */
4255
1da177e4 4256 tx_fifo = mac_control->tx_FIFO_start[queue];
2fda096d 4257 val64 = fifo->list_info[put_off].list_phy_addr;
1da177e4
LT		 4258 writeq(val64, &tx_fifo->TxDL_Pointer);
4259
4260 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4261 TX_FIFO_LAST_LIST);
75c30b13 4262 if (offload_type)
fed5eccd 4263 val64 |= TX_FIFO_SPECIAL_FUNC;
75c30b13 4264
1da177e4
LT		 4265 writeq(val64, &tx_fifo->List_Control);
4266
303bcb4b
K		 4267 mmiowb();
4268
1da177e4 4269 put_off++;
2fda096d 4270 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
863c11a9 4271 put_off = 0;
2fda096d 4272 fifo->tx_curr_put_info.offset = put_off;
1da177e4
LT		 4273
4274 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4275 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
ffb5df6c 4276 swstats->fifo_full_cnt++;
1da177e4
LT		 4277 DBG_PRINT(TX_DBG,
4278 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4279 put_off, get_off);
3a3d5756 4280 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4281 }
ffb5df6c 4282 swstats->mem_allocated += skb->truesize;
2fda096d 4283 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4 4284
f6f4bfa3
SH		 4285 if (sp->config.intr_type == MSI_X)
4286 tx_intr_handler(fifo);
4287
6ed10654 4288 return NETDEV_TX_OK;
ffb5df6c 4289
491abf25 4290pci_map_failed:
ffb5df6c 4291 swstats->pci_map_fail_cnt++;
3a3d5756 4292 s2io_stop_tx_queue(sp, fifo->fifo_no);
ffb5df6c 4293 swstats->mem_freed += skb->truesize;
491abf25 4294 dev_kfree_skb(skb);
2fda096d 4295 spin_unlock_irqrestore(&fifo->tx_lock, flags);
6ed10654 4296 return NETDEV_TX_OK;
1da177e4
LT		 4297}
4298
25fff88e
K		 4299static void
4300s2io_alarm_handle(unsigned long data)
4301{
1ee6dd77 4302 struct s2io_nic *sp = (struct s2io_nic *)data;
8116f3cf 4303 struct net_device *dev = sp->dev;
25fff88e 4304
8116f3cf 4305 s2io_handle_errors(dev);
25fff88e
K		 4306 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4307}
4308
7d12e780 4309static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
cc6e7c44 4310{
1ee6dd77
RB		 4311 struct ring_info *ring = (struct ring_info *)dev_id;
4312 struct s2io_nic *sp = ring->nic;
f61e0a35 4313 struct XENA_dev_config __iomem *bar0 = sp->bar0;
cc6e7c44 4314
f61e0a35 4315 if (unlikely(!is_s2io_card_up(sp)))
92b84437 4316 return IRQ_HANDLED;
92b84437 4317
f61e0a35 4318 if (sp->config.napi) {
1a79d1c3
AV		 4319 u8 __iomem *addr = NULL;
4320 u8 val8 = 0;
f61e0a35 4321
1a79d1c3 4322 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
f61e0a35
SH		 4323 addr += (7 - ring->ring_no);
4324 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4325 writeb(val8, addr);
4326 val8 = readb(addr);
288379f0 4327 napi_schedule(&ring->napi);
f61e0a35
SH		 4328 } else {
4329 rx_intr_handler(ring, 0);
8d8bb39b 4330 s2io_chk_rx_buffers(sp, ring);
f61e0a35 4331 }
7d3d0439 4332
cc6e7c44
RA		 4333 return IRQ_HANDLED;
4334}
4335
7d12e780 4336static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
cc6e7c44 4337{
ac731ab6
SH		 4338 int i;
4339 struct fifo_info *fifos = (struct fifo_info *)dev_id;
4340 struct s2io_nic *sp = fifos->nic;
4341 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4342 struct config_param *config = &sp->config;
4343 u64 reason;
cc6e7c44 4344
ac731ab6
SH		 4345 if (unlikely(!is_s2io_card_up(sp)))
4346 return IRQ_NONE;
4347
4348 reason = readq(&bar0->general_int_status);
4349 if (unlikely(reason == S2IO_MINUS_ONE))
4350 /* Nothing much can be done. Get out */
92b84437 4351 return IRQ_HANDLED;
92b84437 4352
01e16faa
SH		 4353 if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4354 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
ac731ab6 4355
01e16faa
SH		 4356 if (reason & GEN_INTR_TXPIC)
4357 s2io_txpic_intr_handle(sp);
ac731ab6 4358
01e16faa
SH		 4359 if (reason & GEN_INTR_TXTRAFFIC)
4360 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
ac731ab6 4361
01e16faa
SH		 4362 for (i = 0; i < config->tx_fifo_num; i++)
4363 tx_intr_handler(&fifos[i]);
ac731ab6 4364
01e16faa
SH		 4365 writeq(sp->general_int_mask, &bar0->general_int_mask);
4366 readl(&bar0->general_int_status);
4367 return IRQ_HANDLED;
4368 }
4369 /* The interrupt was not raised by us */
4370 return IRQ_NONE;
cc6e7c44 4371}
ac731ab6 4372
1ee6dd77 4373static void s2io_txpic_intr_handle(struct s2io_nic *sp)
a371a07d 4374{
1ee6dd77 4375 struct XENA_dev_config __iomem *bar0 = sp->bar0;
a371a07d
K		 4376 u64 val64;
4377
4378 val64 = readq(&bar0->pic_int_status);
4379 if (val64 & PIC_INT_GPIO) {
4380 val64 = readq(&bar0->gpio_int_reg);
4381 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4382 (val64 & GPIO_INT_REG_LINK_UP)) {
c92ca04b
AR		 4383 /*
4384 * This is unstable state so clear both up/down
4385 * interrupt and adapter to re-evaluate the link state.
4386 */
d44570e4 4387 val64 |= GPIO_INT_REG_LINK_DOWN;
a371a07d
K		 4388 val64 |= GPIO_INT_REG_LINK_UP;
4389 writeq(val64, &bar0->gpio_int_reg);
a371a07d 4390 val64 = readq(&bar0->gpio_int_mask);
c92ca04b
AR		 4391 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4392 GPIO_INT_MASK_LINK_DOWN);
a371a07d 4393 writeq(val64, &bar0->gpio_int_mask);
d44570e4 4394 } else if (val64 & GPIO_INT_REG_LINK_UP) {
c92ca04b 4395 val64 = readq(&bar0->adapter_status);
d44570e4 4396 /* Enable Adapter */
19a60522
SS		 4397 val64 = readq(&bar0->adapter_control);
4398 val64 |= ADAPTER_CNTL_EN;
4399 writeq(val64, &bar0->adapter_control);
4400 val64 |= ADAPTER_LED_ON;
4401 writeq(val64, &bar0->adapter_control);
4402 if (!sp->device_enabled_once)
4403 sp->device_enabled_once = 1;
c92ca04b 4404
19a60522
SS		 4405 s2io_link(sp, LINK_UP);
4406 /*
4407 * unmask link down interrupt and mask link-up
4408 * intr
4409 */
4410 val64 = readq(&bar0->gpio_int_mask);
4411 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4412 val64 |= GPIO_INT_MASK_LINK_UP;
4413 writeq(val64, &bar0->gpio_int_mask);
c92ca04b 4414
d44570e4 4415 } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
c92ca04b 4416 val64 = readq(&bar0->adapter_status);
19a60522
SS		 4417 s2io_link(sp, LINK_DOWN);
4418 /* Link is down so unmaks link up interrupt */
4419 val64 = readq(&bar0->gpio_int_mask);
4420 val64 &= ~GPIO_INT_MASK_LINK_UP;
4421 val64 |= GPIO_INT_MASK_LINK_DOWN;
4422 writeq(val64, &bar0->gpio_int_mask);
ac1f90d6
SS		 4423
4424 /* turn off LED */
4425 val64 = readq(&bar0->adapter_control);
d44570e4 4426 val64 = val64 & (~ADAPTER_LED_ON);
ac1f90d6 4427 writeq(val64, &bar0->adapter_control);
a371a07d
K		 4428 }
4429 }
c92ca04b 4430 val64 = readq(&bar0->gpio_int_mask);
a371a07d
K		 4431}
4432
8116f3cf
SS		 4433/**
4434 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4435 * @value: alarm bits
4436 * @addr: address value
4437 * @cnt: counter variable
4438 * Description: Check for alarm and increment the counter
4439 * Return Value:
4440 * 1 - if alarm bit set
4441 * 0 - if alarm bit is not set
4442 */
d44570e4
JP		 4443static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4444 unsigned long long *cnt)
8116f3cf
SS		 4445{
4446 u64 val64;
4447 val64 = readq(addr);
d44570e4 4448 if (val64 & value) {
8116f3cf
SS		 4449 writeq(val64, addr);
4450 (*cnt)++;
4451 return 1;
4452 }
4453 return 0;
4454
4455}
4456
4457/**
4458 * s2io_handle_errors - Xframe error indication handler
4459 * @nic: device private variable
4460 * Description: Handle alarms such as loss of link, single or
4461 * double ECC errors, critical and serious errors.
4462 * Return Value:
4463 * NONE
4464 */
d44570e4 4465static void s2io_handle_errors(void *dev_id)
8116f3cf 4466{
d44570e4 4467 struct net_device *dev = (struct net_device *)dev_id;
4cf1653a 4468 struct s2io_nic *sp = netdev_priv(dev);
8116f3cf 4469 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d44570e4 4470 u64 temp64 = 0, val64 = 0;
8116f3cf
SS		 4471 int i = 0;
4472
4473 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4474 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4475
92b84437 4476 if (!is_s2io_card_up(sp))
8116f3cf
SS		 4477 return;
4478
4479 if (pci_channel_offline(sp->pdev))
4480 return;
4481
4482 memset(&sw_stat->ring_full_cnt, 0,
d44570e4 4483 sizeof(sw_stat->ring_full_cnt));
8116f3cf
SS		 4484
4485 /* Handling the XPAK counters update */
d44570e4 4486 if (stats->xpak_timer_count < 72000) {
8116f3cf
SS		 4487 /* waiting for an hour */
4488 stats->xpak_timer_count++;
4489 } else {
4490 s2io_updt_xpak_counter(dev);
4491 /* reset the count to zero */
4492 stats->xpak_timer_count = 0;
4493 }
4494
4495 /* Handling link status change error Intr */
4496 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4497 val64 = readq(&bar0->mac_rmac_err_reg);
4498 writeq(val64, &bar0->mac_rmac_err_reg);
4499 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4500 schedule_work(&sp->set_link_task);
4501 }
4502
4503 /* In case of a serious error, the device will be Reset. */
4504 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
d44570e4 4505 &sw_stat->serious_err_cnt))
8116f3cf
SS		 4506 goto reset;
4507
4508 /* Check for data parity error */
4509 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
d44570e4 4510 &sw_stat->parity_err_cnt))
8116f3cf
SS		 4511 goto reset;
4512
4513 /* Check for ring full counter */
4514 if (sp->device_type == XFRAME_II_DEVICE) {
4515 val64 = readq(&bar0->ring_bump_counter1);
d44570e4
JP		 4516 for (i = 0; i < 4; i++) {
4517 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
8116f3cf
SS		 4518 temp64 >>= 64 - ((i+1)*16);
4519 sw_stat->ring_full_cnt[i] += temp64;
4520 }
4521
4522 val64 = readq(&bar0->ring_bump_counter2);
d44570e4
JP		 4523 for (i = 0; i < 4; i++) {
4524 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
8116f3cf 4525 temp64 >>= 64 - ((i+1)*16);
d44570e4 4526 sw_stat->ring_full_cnt[i+4] += temp64;
8116f3cf
SS		 4527 }
4528 }
4529
4530 val64 = readq(&bar0->txdma_int_status);
4531 /*check for pfc_err*/
4532 if (val64 & TXDMA_PFC_INT) {
d44570e4
JP		 4533 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4534 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4535 PFC_PCIX_ERR,
4536 &bar0->pfc_err_reg,
4537 &sw_stat->pfc_err_cnt))
8116f3cf 4538 goto reset;
d44570e4
JP		 4539 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4540 &bar0->pfc_err_reg,
4541 &sw_stat->pfc_err_cnt);
8116f3cf
SS		 4542 }
4543
4544 /*check for tda_err*/
4545 if (val64 & TXDMA_TDA_INT) {
d44570e4
JP		 4546 if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4547 TDA_SM0_ERR_ALARM |
4548 TDA_SM1_ERR_ALARM,
4549 &bar0->tda_err_reg,
4550 &sw_stat->tda_err_cnt))
8116f3cf
SS		 4551 goto reset;
4552 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
d44570e4
JP		 4553 &bar0->tda_err_reg,
4554 &sw_stat->tda_err_cnt);
8116f3cf
SS		 4555 }
4556 /*check for pcc_err*/
4557 if (val64 & TXDMA_PCC_INT) {
d44570e4
JP		 4558 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4559 PCC_N_SERR | PCC_6_COF_OV_ERR |
4560 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4561 PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4562 PCC_TXB_ECC_DB_ERR,
4563 &bar0->pcc_err_reg,
4564 &sw_stat->pcc_err_cnt))
8116f3cf
SS		 4565 goto reset;
4566 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
d44570e4
JP		 4567 &bar0->pcc_err_reg,
4568 &sw_stat->pcc_err_cnt);
8116f3cf
SS		 4569 }
4570
4571 /*check for tti_err*/
4572 if (val64 & TXDMA_TTI_INT) {
d44570e4
JP		 4573 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4574 &bar0->tti_err_reg,
4575 &sw_stat->tti_err_cnt))
8116f3cf
SS		 4576 goto reset;
4577 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
d44570e4
JP		 4578 &bar0->tti_err_reg,
4579 &sw_stat->tti_err_cnt);
8116f3cf
SS		 4580 }
4581
4582 /*check for lso_err*/
4583 if (val64 & TXDMA_LSO_INT) {
d44570e4
JP		 4584 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4585 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4586 &bar0->lso_err_reg,
4587 &sw_stat->lso_err_cnt))
8116f3cf
SS		 4588 goto reset;
4589 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
d44570e4
JP		 4590 &bar0->lso_err_reg,
4591 &sw_stat->lso_err_cnt);
8116f3cf
SS		 4592 }
4593
4594 /*check for tpa_err*/
4595 if (val64 & TXDMA_TPA_INT) {
d44570e4
JP		 4596 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4597 &bar0->tpa_err_reg,
4598 &sw_stat->tpa_err_cnt))
8116f3cf 4599 goto reset;
d44570e4
JP		 4600 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4601 &bar0->tpa_err_reg,
4602 &sw_stat->tpa_err_cnt);
8116f3cf
SS		 4603 }
4604
4605 /*check for sm_err*/
4606 if (val64 & TXDMA_SM_INT) {
d44570e4
JP		 4607 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4608 &bar0->sm_err_reg,
4609 &sw_stat->sm_err_cnt))
8116f3cf
SS		 4610 goto reset;
4611 }
4612
4613 val64 = readq(&bar0->mac_int_status);
4614 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4615 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
d44570e4
JP		 4616 &bar0->mac_tmac_err_reg,
4617 &sw_stat->mac_tmac_err_cnt))
8116f3cf 4618 goto reset;
d44570e4
JP		 4619 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4620 TMAC_DESC_ECC_SG_ERR |
4621 TMAC_DESC_ECC_DB_ERR,
4622 &bar0->mac_tmac_err_reg,
4623 &sw_stat->mac_tmac_err_cnt);
8116f3cf
SS		 4624 }
4625
4626 val64 = readq(&bar0->xgxs_int_status);
4627 if (val64 & XGXS_INT_STATUS_TXGXS) {
4628 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
d44570e4
JP		 4629 &bar0->xgxs_txgxs_err_reg,
4630 &sw_stat->xgxs_txgxs_err_cnt))
8116f3cf
SS		 4631 goto reset;
4632 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
d44570e4
JP		 4633 &bar0->xgxs_txgxs_err_reg,
4634 &sw_stat->xgxs_txgxs_err_cnt);
8116f3cf
SS		 4635 }
4636
4637 val64 = readq(&bar0->rxdma_int_status);
4638 if (val64 & RXDMA_INT_RC_INT_M) {
d44570e4
JP		 4639 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4640 RC_FTC_ECC_DB_ERR |
4641 RC_PRCn_SM_ERR_ALARM |
4642 RC_FTC_SM_ERR_ALARM,
4643 &bar0->rc_err_reg,
4644 &sw_stat->rc_err_cnt))
8116f3cf 4645 goto reset;
d44570e4
JP		 4646 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4647 RC_FTC_ECC_SG_ERR |
4648 RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4649 &sw_stat->rc_err_cnt);
4650 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4651 PRC_PCI_AB_WR_Rn |
4652 PRC_PCI_AB_F_WR_Rn,
4653 &bar0->prc_pcix_err_reg,
4654 &sw_stat->prc_pcix_err_cnt))
8116f3cf 4655 goto reset;
d44570e4
JP		 4656 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4657 PRC_PCI_DP_WR_Rn |
4658 PRC_PCI_DP_F_WR_Rn,
4659 &bar0->prc_pcix_err_reg,
4660 &sw_stat->prc_pcix_err_cnt);
8116f3cf
SS		 4661 }
4662
4663 if (val64 & RXDMA_INT_RPA_INT_M) {
4664 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
d44570e4
JP		 4665 &bar0->rpa_err_reg,
4666 &sw_stat->rpa_err_cnt))
8116f3cf
SS		 4667 goto reset;
4668 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
d44570e4
JP		 4669 &bar0->rpa_err_reg,
4670 &sw_stat->rpa_err_cnt);
8116f3cf
SS		 4671 }
4672
4673 if (val64 & RXDMA_INT_RDA_INT_M) {
d44570e4
JP		 4674 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4675 RDA_FRM_ECC_DB_N_AERR |
4676 RDA_SM1_ERR_ALARM |
4677 RDA_SM0_ERR_ALARM |
4678 RDA_RXD_ECC_DB_SERR,
4679 &bar0->rda_err_reg,
4680 &sw_stat->rda_err_cnt))
8116f3cf 4681 goto reset;
d44570e4
JP		 4682 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4683 RDA_FRM_ECC_SG_ERR |
4684 RDA_MISC_ERR |
4685 RDA_PCIX_ERR,
4686 &bar0->rda_err_reg,
4687 &sw_stat->rda_err_cnt);
8116f3cf
SS		 4688 }
4689
4690 if (val64 & RXDMA_INT_RTI_INT_M) {
d44570e4
JP		 4691 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4692 &bar0->rti_err_reg,
4693 &sw_stat->rti_err_cnt))
8116f3cf
SS		 4694 goto reset;
4695 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
d44570e4
JP		 4696 &bar0->rti_err_reg,
4697 &sw_stat->rti_err_cnt);
8116f3cf
SS		 4698 }
4699
4700 val64 = readq(&bar0->mac_int_status);
4701 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4702 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
d44570e4
JP		 4703 &bar0->mac_rmac_err_reg,
4704 &sw_stat->mac_rmac_err_cnt))
8116f3cf 4705 goto reset;
d44570e4
JP		 4706 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4707 RMAC_SINGLE_ECC_ERR |
4708 RMAC_DOUBLE_ECC_ERR,
4709 &bar0->mac_rmac_err_reg,
4710 &sw_stat->mac_rmac_err_cnt);
8116f3cf
SS		 4711 }
4712
4713 val64 = readq(&bar0->xgxs_int_status);
4714 if (val64 & XGXS_INT_STATUS_RXGXS) {
4715 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
d44570e4
JP		 4716 &bar0->xgxs_rxgxs_err_reg,
4717 &sw_stat->xgxs_rxgxs_err_cnt))
8116f3cf
SS		 4718 goto reset;
4719 }
4720
4721 val64 = readq(&bar0->mc_int_status);
d44570e4
JP		 4722 if (val64 & MC_INT_STATUS_MC_INT) {
4723 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4724 &bar0->mc_err_reg,
4725 &sw_stat->mc_err_cnt))
8116f3cf
SS		 4726 goto reset;
4727
4728 /* Handling Ecc errors */
4729 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4730 writeq(val64, &bar0->mc_err_reg);
4731 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4732 sw_stat->double_ecc_errs++;
4733 if (sp->device_type != XFRAME_II_DEVICE) {
4734 /*
4735 * Reset XframeI only if critical error
4736 */
4737 if (val64 &
d44570e4
JP		 4738 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4739 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4740 goto reset;
4741 }
8116f3cf
SS		 4742 } else
4743 sw_stat->single_ecc_errs++;
4744 }
4745 }
4746 return;
4747
4748reset:
3a3d5756 4749 s2io_stop_all_tx_queue(sp);
8116f3cf
SS		 4750 schedule_work(&sp->rst_timer_task);
4751 sw_stat->soft_reset_cnt++;
8116f3cf
SS		 4752}
4753
1da177e4
LT		 4754/**
4755 * s2io_isr - ISR handler of the device .
4756 * @irq: the irq of the device.
4757 * @dev_id: a void pointer to the dev structure of the NIC.
20346722
K		 4758 * Description: This function is the ISR handler of the device. It
4759 * identifies the reason for the interrupt and calls the relevant
4760 * service routines. As a contongency measure, this ISR allocates the
1da177e4
LT		 4761 * recv buffers, if their numbers are below the panic value which is
4762 * presently set to 25% of the original number of rcv buffers allocated.
4763 * Return value:
20346722 4764 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
1da177e4
LT		 4765 * IRQ_NONE: will be returned if interrupt is not from our device
4766 */
7d12e780 4767static irqreturn_t s2io_isr(int irq, void *dev_id)
1da177e4 4768{
d44570e4 4769 struct net_device *dev = (struct net_device *)dev_id;
4cf1653a 4770 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 4771 struct XENA_dev_config __iomem *bar0 = sp->bar0;
20346722 4772 int i;
19a60522 4773 u64 reason = 0;
1ee6dd77 4774 struct mac_info *mac_control;
1da177e4
LT		 4775 struct config_param *config;
4776
d796fdb7
LV		 4777 /* Pretend we handled any irq's from a disconnected card */
4778 if (pci_channel_offline(sp->pdev))
4779 return IRQ_NONE;
4780
596c5c97 4781 if (!is_s2io_card_up(sp))
92b84437 4782 return IRQ_NONE;
92b84437 4783
1da177e4 4784 config = &sp->config;
ffb5df6c 4785 mac_control = &sp->mac_control;
1da177e4 4786
20346722 4787 /*
1da177e4
LT		 4788 * Identify the cause for interrupt and call the appropriate
4789 * interrupt handler. Causes for the interrupt could be;
4790 * 1. Rx of packet.
4791 * 2. Tx complete.
4792 * 3. Link down.
1da177e4
LT		 4793 */
4794 reason = readq(&bar0->general_int_status);
4795
d44570e4
JP		 4796 if (unlikely(reason == S2IO_MINUS_ONE))
4797 return IRQ_HANDLED; /* Nothing much can be done. Get out */
5d3213cc 4798
d44570e4
JP		 4799 if (reason &
4800 (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
596c5c97
SS		 4801 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4802
4803 if (config->napi) {
4804 if (reason & GEN_INTR_RXTRAFFIC) {
288379f0 4805 napi_schedule(&sp->napi);
f61e0a35
SH		 4806 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4807 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4808 readl(&bar0->rx_traffic_int);
db874e65 4809 }
596c5c97
SS		 4810 } else {
4811 /*
4812 * rx_traffic_int reg is an R1 register, writing all 1's
4813 * will ensure that the actual interrupt causing bit
4814 * get's cleared and hence a read can be avoided.
4815 */
4816 if (reason & GEN_INTR_RXTRAFFIC)
19a60522 4817 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
596c5c97 4818
13d866a9
JP		 4819 for (i = 0; i < config->rx_ring_num; i++) {
4820 struct ring_info *ring = &mac_control->rings[i];
4821
4822 rx_intr_handler(ring, 0);
4823 }
db874e65 4824 }
596c5c97 4825
db874e65 4826 /*
596c5c97 4827 * tx_traffic_int reg is an R1 register, writing all 1's
db874e65
SS		 4828 * will ensure that the actual interrupt causing bit get's
4829 * cleared and hence a read can be avoided.
4830 */
596c5c97
SS		 4831 if (reason & GEN_INTR_TXTRAFFIC)
4832 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
19a60522 4833
596c5c97
SS		 4834 for (i = 0; i < config->tx_fifo_num; i++)
4835 tx_intr_handler(&mac_control->fifos[i]);
1da177e4 4836
596c5c97
SS		 4837 if (reason & GEN_INTR_TXPIC)
4838 s2io_txpic_intr_handle(sp);
fe113638 4839
596c5c97
SS		 4840 /*
4841 * Reallocate the buffers from the interrupt handler itself.
4842 */
4843 if (!config->napi) {
13d866a9
JP		 4844 for (i = 0; i < config->rx_ring_num; i++) {
4845 struct ring_info *ring = &mac_control->rings[i];
4846
4847 s2io_chk_rx_buffers(sp, ring);
4848 }
596c5c97
SS		 4849 }
4850 writeq(sp->general_int_mask, &bar0->general_int_mask);
4851 readl(&bar0->general_int_status);
20346722 4852
596c5c97 4853 return IRQ_HANDLED;
db874e65 4854
d44570e4 4855 } else if (!reason) {
596c5c97
SS		 4856 /* The interrupt was not raised by us */
4857 return IRQ_NONE;
4858 }
db874e65 4859
1da177e4
LT		 4860 return IRQ_HANDLED;
4861}
4862
7ba013ac
K		 4863/**
4864 * s2io_updt_stats -
4865 */
1ee6dd77 4866static void s2io_updt_stats(struct s2io_nic *sp)
7ba013ac 4867{
1ee6dd77 4868 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7ba013ac
K		 4869 u64 val64;
4870 int cnt = 0;
4871
92b84437 4872 if (is_s2io_card_up(sp)) {
7ba013ac
K		 4873 /* Apprx 30us on a 133 MHz bus */
4874 val64 = SET_UPDT_CLICKS(10) |
4875 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4876 writeq(val64, &bar0->stat_cfg);
4877 do {
4878 udelay(100);
4879 val64 = readq(&bar0->stat_cfg);
b7b5a128 4880 if (!(val64 & s2BIT(0)))
7ba013ac
K		 4881 break;
4882 cnt++;
4883 if (cnt == 5)
4884 break; /* Updt failed */
d44570e4 4885 } while (1);
8a4bdbaa 4886 }
7ba013ac
K		 4887}
4888
1da177e4 4889/**
20346722 4890 * s2io_get_stats - Updates the device statistics structure.
1da177e4
LT		 4891 * @dev : pointer to the device structure.
4892 * Description:
20346722 4893 * This function updates the device statistics structure in the s2io_nic
1da177e4
LT		 4894 * structure and returns a pointer to the same.
4895 * Return value:
4896 * pointer to the updated net_device_stats structure.
4897 */
ac1f60db 4898static struct net_device_stats *s2io_get_stats(struct net_device *dev)
1da177e4 4899{
4cf1653a 4900 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c
JP		 4901 struct mac_info *mac_control = &sp->mac_control;
4902 struct stat_block *stats = mac_control->stats_info;
4a490432 4903 u64 delta;
1da177e4 4904
7ba013ac
K		 4905 /* Configure Stats for immediate updt */
4906 s2io_updt_stats(sp);
4907
4a490432
JM		 4908 /* A device reset will cause the on-adapter statistics to be zero'ed.
4909 * This can be done while running by changing the MTU. To prevent the
4910 * system from having the stats zero'ed, the driver keeps a copy of the
4911 * last update to the system (which is also zero'ed on reset). This
4912 * enables the driver to accurately know the delta between the last
4913 * update and the current update.
4914 */
4915 delta = ((u64) le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
4916 le32_to_cpu(stats->rmac_vld_frms)) - sp->stats.rx_packets;
4917 sp->stats.rx_packets += delta;
4918 dev->stats.rx_packets += delta;
4919
4920 delta = ((u64) le32_to_cpu(stats->tmac_frms_oflow) << 32 |
4921 le32_to_cpu(stats->tmac_frms)) - sp->stats.tx_packets;
4922 sp->stats.tx_packets += delta;
4923 dev->stats.tx_packets += delta;
4924
4925 delta = ((u64) le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
4926 le32_to_cpu(stats->rmac_data_octets)) - sp->stats.rx_bytes;
4927 sp->stats.rx_bytes += delta;
4928 dev->stats.rx_bytes += delta;
4929
4930 delta = ((u64) le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
4931 le32_to_cpu(stats->tmac_data_octets)) - sp->stats.tx_bytes;
4932 sp->stats.tx_bytes += delta;
4933 dev->stats.tx_bytes += delta;
4934
4935 delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_errors;
4936 sp->stats.rx_errors += delta;
4937 dev->stats.rx_errors += delta;
4938
4939 delta = ((u64) le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
4940 le32_to_cpu(stats->tmac_any_err_frms)) - sp->stats.tx_errors;
4941 sp->stats.tx_errors += delta;
4942 dev->stats.tx_errors += delta;
4943
4944 delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_dropped;
4945 sp->stats.rx_dropped += delta;
4946 dev->stats.rx_dropped += delta;
4947
4948 delta = le64_to_cpu(stats->tmac_drop_frms) - sp->stats.tx_dropped;
4949 sp->stats.tx_dropped += delta;
4950 dev->stats.tx_dropped += delta;
4951
4952 /* The adapter MAC interprets pause frames as multicast packets, but
4953 * does not pass them up. This erroneously increases the multicast
4954 * packet count and needs to be deducted when the multicast frame count
4955 * is queried.
4956 */
4957 delta = (u64) le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
4958 le32_to_cpu(stats->rmac_vld_mcst_frms);
4959 delta -= le64_to_cpu(stats->rmac_pause_ctrl_frms);
4960 delta -= sp->stats.multicast;
4961 sp->stats.multicast += delta;
4962 dev->stats.multicast += delta;
1da177e4 4963
4a490432
JM		 4964 delta = ((u64) le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
4965 le32_to_cpu(stats->rmac_usized_frms)) +
4966 le64_to_cpu(stats->rmac_long_frms) - sp->stats.rx_length_errors;
4967 sp->stats.rx_length_errors += delta;
4968 dev->stats.rx_length_errors += delta;
13d866a9 4969
4a490432
JM		 4970 delta = le64_to_cpu(stats->rmac_fcs_err_frms) - sp->stats.rx_crc_errors;
4971 sp->stats.rx_crc_errors += delta;
4972 dev->stats.rx_crc_errors += delta;
0425b46a 4973
d44570e4 4974 return &dev->stats;
1da177e4
LT		 4975}
4976
4977/**
4978 * s2io_set_multicast - entry point for multicast address enable/disable.
4979 * @dev : pointer to the device structure
4980 * Description:
20346722
K		 4981 * This function is a driver entry point which gets called by the kernel
4982 * whenever multicast addresses must be enabled/disabled. This also gets
1da177e4
LT		 4983 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4984 * determine, if multicast address must be enabled or if promiscuous mode
4985 * is to be disabled etc.
4986 * Return value:
4987 * void.
4988 */
4989
4990static void s2io_set_multicast(struct net_device *dev)
4991{
4992 int i, j, prev_cnt;
22bedad3 4993 struct netdev_hw_addr *ha;
4cf1653a 4994 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 4995 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 4996 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
d44570e4 4997 0xfeffffffffffULL;
faa4f796 4998 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
1da177e4 4999 void __iomem *add;
faa4f796 5000 struct config_param *config = &sp->config;
1da177e4
LT		 5001
5002 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
5003 /* Enable all Multicast addresses */
5004 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
5005 &bar0->rmac_addr_data0_mem);
5006 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
5007 &bar0->rmac_addr_data1_mem);
5008 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5009 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5010 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
1da177e4
LT		 5011 writeq(val64, &bar0->rmac_addr_cmd_mem);
5012 /* Wait till command completes */
c92ca04b 5013 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5014 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5015 S2IO_BIT_RESET);
1da177e4
LT		 5016
5017 sp->m_cast_flg = 1;
faa4f796 5018 sp->all_multi_pos = config->max_mc_addr - 1;
1da177e4
LT		 5019 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
5020 /* Disable all Multicast addresses */
5021 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5022 &bar0->rmac_addr_data0_mem);
5e25b9dd
K		 5023 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
5024 &bar0->rmac_addr_data1_mem);
1da177e4 5025 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5026 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5027 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
1da177e4
LT		 5028 writeq(val64, &bar0->rmac_addr_cmd_mem);
5029 /* Wait till command completes */
c92ca04b 5030 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5031 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5032 S2IO_BIT_RESET);
1da177e4
LT		 5033
5034 sp->m_cast_flg = 0;
5035 sp->all_multi_pos = 0;
5036 }
5037
5038 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
5039 /* Put the NIC into promiscuous mode */
5040 add = &bar0->mac_cfg;
5041 val64 = readq(&bar0->mac_cfg);
5042 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5043
5044 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 5045 writel((u32)val64, add);
1da177e4
LT		 5046 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5047 writel((u32) (val64 >> 32), (add + 4));
5048
926930b2
SS		 5049 if (vlan_tag_strip != 1) {
5050 val64 = readq(&bar0->rx_pa_cfg);
5051 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5052 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 5053 sp->vlan_strip_flag = 0;
926930b2
SS		 5054 }
5055
1da177e4
LT		 5056 val64 = readq(&bar0->mac_cfg);
5057 sp->promisc_flg = 1;
776bd20f 5058 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
1da177e4
LT		 5059 dev->name);
5060 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5061 /* Remove the NIC from promiscuous mode */
5062 add = &bar0->mac_cfg;
5063 val64 = readq(&bar0->mac_cfg);
5064 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5065
5066 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 5067 writel((u32)val64, add);
1da177e4
LT		 5068 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5069 writel((u32) (val64 >> 32), (add + 4));
5070
926930b2
SS		 5071 if (vlan_tag_strip != 0) {
5072 val64 = readq(&bar0->rx_pa_cfg);
5073 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5074 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 5075 sp->vlan_strip_flag = 1;
926930b2
SS		 5076 }
5077
1da177e4
LT		 5078 val64 = readq(&bar0->mac_cfg);
5079 sp->promisc_flg = 0;
9e39f7c5 5080 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name);
1da177e4
LT		 5081 }
5082
5083 /* Update individual M_CAST address list */
4cd24eaf
JP		 5084 if ((!sp->m_cast_flg) && netdev_mc_count(dev)) {
5085 if (netdev_mc_count(dev) >
faa4f796 5086 (config->max_mc_addr - config->max_mac_addr)) {
9e39f7c5
JP		 5087 DBG_PRINT(ERR_DBG,
5088 "%s: No more Rx filters can be added - "
5089 "please enable ALL_MULTI instead\n",
1da177e4 5090 dev->name);
1da177e4
LT		 5091 return;
5092 }
5093
5094 prev_cnt = sp->mc_addr_count;
4cd24eaf 5095 sp->mc_addr_count = netdev_mc_count(dev);
1da177e4
LT		 5096
5097 /* Clear out the previous list of Mc in the H/W. */
5098 for (i = 0; i < prev_cnt; i++) {
5099 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5100 &bar0->rmac_addr_data0_mem);
5101 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
d44570e4 5102 &bar0->rmac_addr_data1_mem);
1da177e4 5103 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5104 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5105 RMAC_ADDR_CMD_MEM_OFFSET
5106 (config->mc_start_offset + i);
1da177e4
LT		 5107 writeq(val64, &bar0->rmac_addr_cmd_mem);
5108
5109 /* Wait for command completes */
c92ca04b 5110 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5111 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5112 S2IO_BIT_RESET)) {
9e39f7c5
JP		 5113 DBG_PRINT(ERR_DBG,
5114 "%s: Adding Multicasts failed\n",
5115 dev->name);
1da177e4
LT		 5116 return;
5117 }
5118 }
5119
5120 /* Create the new Rx filter list and update the same in H/W. */
5508590c 5121 i = 0;
22bedad3 5122 netdev_for_each_mc_addr(ha, dev) {
a7a80d5a 5123 mac_addr = 0;
1da177e4 5124 for (j = 0; j < ETH_ALEN; j++) {
22bedad3 5125 mac_addr |= ha->addr[j];
1da177e4
LT		 5126 mac_addr <<= 8;
5127 }
5128 mac_addr >>= 8;
5129 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5130 &bar0->rmac_addr_data0_mem);
5131 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
d44570e4 5132 &bar0->rmac_addr_data1_mem);
1da177e4 5133 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5134 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5135 RMAC_ADDR_CMD_MEM_OFFSET
5136 (i + config->mc_start_offset);
1da177e4
LT		 5137 writeq(val64, &bar0->rmac_addr_cmd_mem);
5138
5139 /* Wait for command completes */
c92ca04b 5140 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5141 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5142 S2IO_BIT_RESET)) {
9e39f7c5
JP		 5143 DBG_PRINT(ERR_DBG,
5144 "%s: Adding Multicasts failed\n",
5145 dev->name);
1da177e4
LT		 5146 return;
5147 }
5508590c 5148 i++;
1da177e4
LT		 5149 }
5150 }
5151}
5152
faa4f796
SH		 5153/* read from CAM unicast & multicast addresses and store it in
5154 * def_mac_addr structure
5155 */
dac499f9 5156static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
faa4f796
SH		 5157{
5158 int offset;
5159 u64 mac_addr = 0x0;
5160 struct config_param *config = &sp->config;
5161
5162 /* store unicast & multicast mac addresses */
5163 for (offset = 0; offset < config->max_mc_addr; offset++) {
5164 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5165 /* if read fails disable the entry */
5166 if (mac_addr == FAILURE)
5167 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5168 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5169 }
5170}
5171
5172/* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5173static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5174{
5175 int offset;
5176 struct config_param *config = &sp->config;
5177 /* restore unicast mac address */
5178 for (offset = 0; offset < config->max_mac_addr; offset++)
5179 do_s2io_prog_unicast(sp->dev,
d44570e4 5180 sp->def_mac_addr[offset].mac_addr);
faa4f796
SH		 5181
5182 /* restore multicast mac address */
5183 for (offset = config->mc_start_offset;
d44570e4 5184 offset < config->max_mc_addr; offset++)
faa4f796
SH		 5185 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5186}
5187
5188/* add a multicast MAC address to CAM */
5189static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5190{
5191 int i;
5192 u64 mac_addr = 0;
5193 struct config_param *config = &sp->config;
5194
5195 for (i = 0; i < ETH_ALEN; i++) {
5196 mac_addr <<= 8;
5197 mac_addr |= addr[i];
5198 }
5199 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5200 return SUCCESS;
5201
5202 /* check if the multicast mac already preset in CAM */
5203 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5204 u64 tmp64;
5205 tmp64 = do_s2io_read_unicast_mc(sp, i);
5206 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5207 break;
5208
5209 if (tmp64 == mac_addr)
5210 return SUCCESS;
5211 }
5212 if (i == config->max_mc_addr) {
5213 DBG_PRINT(ERR_DBG,
d44570e4 5214 "CAM full no space left for multicast MAC\n");
faa4f796
SH		 5215 return FAILURE;
5216 }
5217 /* Update the internal structure with this new mac address */
5218 do_s2io_copy_mac_addr(sp, i, mac_addr);
5219
d44570e4 5220 return do_s2io_add_mac(sp, mac_addr, i);
faa4f796
SH		 5221}
5222
5223/* add MAC address to CAM */
5224static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
2fd37688
SS		 5225{
5226 u64 val64;
5227 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5228
5229 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
d44570e4 5230 &bar0->rmac_addr_data0_mem);
2fd37688 5231
d44570e4 5232 val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
2fd37688
SS		 5233 RMAC_ADDR_CMD_MEM_OFFSET(off);
5234 writeq(val64, &bar0->rmac_addr_cmd_mem);
5235
5236 /* Wait till command completes */
5237 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5238 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5239 S2IO_BIT_RESET)) {
faa4f796 5240 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
2fd37688
SS		 5241 return FAILURE;
5242 }
5243 return SUCCESS;
5244}
faa4f796
SH		 5245/* deletes a specified unicast/multicast mac entry from CAM */
5246static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5247{
5248 int offset;
5249 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5250 struct config_param *config = &sp->config;
5251
5252 for (offset = 1;
d44570e4 5253 offset < config->max_mc_addr; offset++) {
faa4f796
SH		 5254 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5255 if (tmp64 == addr) {
5256 /* disable the entry by writing 0xffffffffffffULL */
5257 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5258 return FAILURE;
5259 /* store the new mac list from CAM */
5260 do_s2io_store_unicast_mc(sp);
5261 return SUCCESS;
5262 }
5263 }
5264 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
d44570e4 5265 (unsigned long long)addr);
faa4f796
SH		 5266 return FAILURE;
5267}
5268
5269/* read mac entries from CAM */
5270static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5271{
5272 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5273 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5274
5275 /* read mac addr */
d44570e4 5276 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
faa4f796
SH		 5277 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5278 writeq(val64, &bar0->rmac_addr_cmd_mem);
5279
5280 /* Wait till command completes */
5281 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5282 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5283 S2IO_BIT_RESET)) {
faa4f796
SH		 5284 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5285 return FAILURE;
5286 }
5287 tmp64 = readq(&bar0->rmac_addr_data0_mem);
d44570e4
JP		 5288
5289 return tmp64 >> 16;
faa4f796 5290}
2fd37688
SS		 5291
5292/**
5293 * s2io_set_mac_addr driver entry point
5294 */
faa4f796 5295
2fd37688
SS		 5296static int s2io_set_mac_addr(struct net_device *dev, void *p)
5297{
5298 struct sockaddr *addr = p;
5299
5300 if (!is_valid_ether_addr(addr->sa_data))
5301 return -EINVAL;
5302
5303 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5304
5305 /* store the MAC address in CAM */
d44570e4 5306 return do_s2io_prog_unicast(dev, dev->dev_addr);
2fd37688 5307}
1da177e4 5308/**
2fd37688 5309 * do_s2io_prog_unicast - Programs the Xframe mac address
1da177e4
LT		 5310 * @dev : pointer to the device structure.
5311 * @addr: a uchar pointer to the new mac address which is to be set.
20346722 5312 * Description : This procedure will program the Xframe to receive
1da177e4 5313 * frames with new Mac Address
20346722 5314 * Return value: SUCCESS on success and an appropriate (-)ve integer
1da177e4
LT		 5315 * as defined in errno.h file on failure.
5316 */
faa4f796 5317
2fd37688 5318static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
1da177e4 5319{
4cf1653a 5320 struct s2io_nic *sp = netdev_priv(dev);
2fd37688 5321 register u64 mac_addr = 0, perm_addr = 0;
1da177e4 5322 int i;
faa4f796
SH		 5323 u64 tmp64;
5324 struct config_param *config = &sp->config;
1da177e4 5325
20346722 5326 /*
d44570e4
JP		 5327 * Set the new MAC address as the new unicast filter and reflect this
5328 * change on the device address registered with the OS. It will be
5329 * at offset 0.
5330 */
1da177e4
LT		 5331 for (i = 0; i < ETH_ALEN; i++) {
5332 mac_addr <<= 8;
5333 mac_addr |= addr[i];
2fd37688
SS		 5334 perm_addr <<= 8;
5335 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
d8d70caf
SS		 5336 }
5337
2fd37688
SS		 5338 /* check if the dev_addr is different than perm_addr */
5339 if (mac_addr == perm_addr)
d8d70caf
SS		 5340 return SUCCESS;
5341
faa4f796
SH		 5342 /* check if the mac already preset in CAM */
5343 for (i = 1; i < config->max_mac_addr; i++) {
5344 tmp64 = do_s2io_read_unicast_mc(sp, i);
5345 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5346 break;
5347
5348 if (tmp64 == mac_addr) {
5349 DBG_PRINT(INFO_DBG,
d44570e4
JP		 5350 "MAC addr:0x%llx already present in CAM\n",
5351 (unsigned long long)mac_addr);
faa4f796
SH		 5352 return SUCCESS;
5353 }
5354 }
5355 if (i == config->max_mac_addr) {
5356 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5357 return FAILURE;
5358 }
d8d70caf 5359 /* Update the internal structure with this new mac address */
faa4f796 5360 do_s2io_copy_mac_addr(sp, i, mac_addr);
d44570e4
JP		 5361
5362 return do_s2io_add_mac(sp, mac_addr, i);
1da177e4
LT		 5363}
5364
5365/**
20346722 5366 * s2io_ethtool_sset - Sets different link parameters.
1da177e4
LT		 5367 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5368 * @info: pointer to the structure with parameters given by ethtool to set
5369 * link information.
5370 * Description:
20346722 5371 * The function sets different link parameters provided by the user onto
1da177e4
LT		 5372 * the NIC.
5373 * Return value:
5374 * 0 on success.
d44570e4 5375 */
1da177e4
LT		 5376
5377static int s2io_ethtool_sset(struct net_device *dev,
5378 struct ethtool_cmd *info)
5379{
4cf1653a 5380 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 5381 if ((info->autoneg == AUTONEG_ENABLE) ||
25db0338 5382 (ethtool_cmd_speed(info) != SPEED_10000) ||
d44570e4 5383 (info->duplex != DUPLEX_FULL))
1da177e4
LT		 5384 return -EINVAL;
5385 else {
5386 s2io_close(sp->dev);
5387 s2io_open(sp->dev);
5388 }
5389
5390 return 0;
5391}
5392
5393/**
20346722 5394 * s2io_ethtol_gset - Return link specific information.
1da177e4
LT		 5395 * @sp : private member of the device structure, pointer to the
5396 * s2io_nic structure.
5397 * @info : pointer to the structure with parameters given by ethtool
5398 * to return link information.
5399 * Description:
5400 * Returns link specific information like speed, duplex etc.. to ethtool.
5401 * Return value :
5402 * return 0 on success.
5403 */
5404
5405static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5406{
4cf1653a 5407 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5408 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5409 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5410 info->port = PORT_FIBRE;
1a7eb72b
SS		 5411
5412 /* info->transceiver */
5413 info->transceiver = XCVR_EXTERNAL;
1da177e4
LT		 5414
5415 if (netif_carrier_ok(sp->dev)) {
70739497 5416 ethtool_cmd_speed_set(info, SPEED_10000);
1da177e4
LT		 5417 info->duplex = DUPLEX_FULL;
5418 } else {
70739497 5419 ethtool_cmd_speed_set(info, -1);
1da177e4
LT		 5420 info->duplex = -1;
5421 }
5422
5423 info->autoneg = AUTONEG_DISABLE;
5424 return 0;
5425}
5426
5427/**
20346722
K		 5428 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5429 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5430 * s2io_nic structure.
5431 * @info : pointer to the structure with parameters given by ethtool to
5432 * return driver information.
5433 * Description:
5434 * Returns driver specefic information like name, version etc.. to ethtool.
5435 * Return value:
5436 * void
5437 */
5438
5439static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5440 struct ethtool_drvinfo *info)
5441{
4cf1653a 5442 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 5443
dbc2309d
JL		 5444 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5445 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5446 strncpy(info->fw_version, "", sizeof(info->fw_version));
5447 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
1da177e4
LT		 5448 info->regdump_len = XENA_REG_SPACE;
5449 info->eedump_len = XENA_EEPROM_SPACE;
1da177e4
LT		 5450}
5451
5452/**
5453 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
20346722 5454 * @sp: private member of the device structure, which is a pointer to the
1da177e4 5455 * s2io_nic structure.
20346722 5456 * @regs : pointer to the structure with parameters given by ethtool for
1da177e4
LT		 5457 * dumping the registers.
5458 * @reg_space: The input argumnet into which all the registers are dumped.
5459 * Description:
5460 * Dumps the entire register space of xFrame NIC into the user given
5461 * buffer area.
5462 * Return value :
5463 * void .
d44570e4 5464 */
1da177e4
LT		 5465
5466static void s2io_ethtool_gregs(struct net_device *dev,
5467 struct ethtool_regs *regs, void *space)
5468{
5469 int i;
5470 u64 reg;
d44570e4 5471 u8 *reg_space = (u8 *)space;
4cf1653a 5472 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5473
5474 regs->len = XENA_REG_SPACE;
5475 regs->version = sp->pdev->subsystem_device;
5476
5477 for (i = 0; i < regs->len; i += 8) {
5478 reg = readq(sp->bar0 + i);
5479 memcpy((reg_space + i), &reg, 8);
5480 }
5481}
5482
034e3450 5483/*
5484 * s2io_set_led - control NIC led
d44570e4 5485 */
034e3450 5486static void s2io_set_led(struct s2io_nic *sp, bool on)
1da177e4 5487{
1ee6dd77 5488 struct XENA_dev_config __iomem *bar0 = sp->bar0;
034e3450 5489 u16 subid = sp->pdev->subsystem_device;
5490 u64 val64;
1da177e4 5491
541ae68f 5492 if ((sp->device_type == XFRAME_II_DEVICE) ||
d44570e4 5493 ((subid & 0xFF) >= 0x07)) {
1da177e4 5494 val64 = readq(&bar0->gpio_control);
034e3450 5495 if (on)
5496 val64 |= GPIO_CTRL_GPIO_0;
5497 else
5498 val64 &= ~GPIO_CTRL_GPIO_0;
5499
1da177e4
LT		 5500 writeq(val64, &bar0->gpio_control);
5501 } else {
5502 val64 = readq(&bar0->adapter_control);
034e3450 5503 if (on)
5504 val64 |= ADAPTER_LED_ON;
5505 else
5506 val64 &= ~ADAPTER_LED_ON;
5507
1da177e4
LT		 5508 writeq(val64, &bar0->adapter_control);
5509 }
5510
1da177e4
LT		 5511}
5512
5513/**
034e3450 5514 * s2io_ethtool_set_led - To physically identify the nic on the system.
5515 * @dev : network device
5516 * @state: led setting
5517 *
1da177e4 5518 * Description: Used to physically identify the NIC on the system.
20346722 5519 * The Link LED will blink for a time specified by the user for
1da177e4 5520 * identification.
20346722 5521 * NOTE: The Link has to be Up to be able to blink the LED. Hence
1da177e4 5522 * identification is possible only if it's link is up.
1da177e4
LT		 5523 */
5524
034e3450 5525static int s2io_ethtool_set_led(struct net_device *dev,
5526 enum ethtool_phys_id_state state)
1da177e4 5527{
4cf1653a 5528 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5529 struct XENA_dev_config __iomem *bar0 = sp->bar0;
034e3450 5530 u16 subid = sp->pdev->subsystem_device;
1da177e4 5531
d44570e4 5532 if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) {
034e3450 5533 u64 val64 = readq(&bar0->adapter_control);
1da177e4 5534 if (!(val64 & ADAPTER_CNTL_EN)) {
6cef2b8e 5535 pr_err("Adapter Link down, cannot blink LED\n");
034e3450 5536 return -EAGAIN;
1da177e4
LT		 5537 }
5538 }
1da177e4 5539
034e3450 5540 switch (state) {
5541 case ETHTOOL_ID_ACTIVE:
5542 sp->adapt_ctrl_org = readq(&bar0->gpio_control);
fce55922 5543 return 1; /* cycle on/off once per second */
034e3450 5544
5545 case ETHTOOL_ID_ON:
5546 s2io_set_led(sp, true);
5547 break;
5548
5549 case ETHTOOL_ID_OFF:
5550 s2io_set_led(sp, false);
5551 break;
5552
5553 case ETHTOOL_ID_INACTIVE:
5554 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid))
5555 writeq(sp->adapt_ctrl_org, &bar0->gpio_control);
1da177e4
LT		 5556 }
5557
5558 return 0;
5559}
5560
0cec35eb 5561static void s2io_ethtool_gringparam(struct net_device *dev,
d44570e4 5562 struct ethtool_ringparam *ering)
0cec35eb 5563{
4cf1653a 5564 struct s2io_nic *sp = netdev_priv(dev);
d44570e4 5565 int i, tx_desc_count = 0, rx_desc_count = 0;
0cec35eb 5566
1853e2e1 5567 if (sp->rxd_mode == RXD_MODE_1) {
0cec35eb 5568 ering->rx_max_pending = MAX_RX_DESC_1;
1853e2e1
JM		 5569 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5570 } else {
0cec35eb 5571 ering->rx_max_pending = MAX_RX_DESC_2;
1853e2e1
JM		 5572 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5573 }
0cec35eb 5574
1853e2e1 5575 ering->rx_mini_max_pending = 0;
0cec35eb 5576 ering->tx_max_pending = MAX_TX_DESC;
8a4bdbaa 5577
1853e2e1 5578 for (i = 0; i < sp->config.rx_ring_num; i++)
0cec35eb 5579 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
0cec35eb 5580 ering->rx_pending = rx_desc_count;
0cec35eb 5581 ering->rx_jumbo_pending = rx_desc_count;
1853e2e1
JM		 5582 ering->rx_mini_pending = 0;
5583
5584 for (i = 0; i < sp->config.tx_fifo_num; i++)
5585 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5586 ering->tx_pending = tx_desc_count;
5587 DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds);
0cec35eb
SH		 5588}
5589
1da177e4
LT		 5590/**
5591 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
20346722
K		 5592 * @sp : private member of the device structure, which is a pointer to the
5593 * s2io_nic structure.
1da177e4
LT		 5594 * @ep : pointer to the structure with pause parameters given by ethtool.
5595 * Description:
5596 * Returns the Pause frame generation and reception capability of the NIC.
5597 * Return value:
5598 * void
5599 */
5600static void s2io_ethtool_getpause_data(struct net_device *dev,
5601 struct ethtool_pauseparam *ep)
5602{
5603 u64 val64;
4cf1653a 5604 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5605 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5606
5607 val64 = readq(&bar0->rmac_pause_cfg);
5608 if (val64 & RMAC_PAUSE_GEN_ENABLE)
f957bcf0 5609 ep->tx_pause = true;
1da177e4 5610 if (val64 & RMAC_PAUSE_RX_ENABLE)
f957bcf0
TK		 5611 ep->rx_pause = true;
5612 ep->autoneg = false;
1da177e4
LT		 5613}
5614
5615/**
5616 * s2io_ethtool_setpause_data - set/reset pause frame generation.
20346722 5617 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5618 * s2io_nic structure.
5619 * @ep : pointer to the structure with pause parameters given by ethtool.
5620 * Description:
5621 * It can be used to set or reset Pause frame generation or reception
5622 * support of the NIC.
5623 * Return value:
5624 * int, returns 0 on Success
5625 */
5626
5627static int s2io_ethtool_setpause_data(struct net_device *dev,
d44570e4 5628 struct ethtool_pauseparam *ep)
1da177e4
LT		 5629{
5630 u64 val64;
4cf1653a 5631 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5632 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5633
5634 val64 = readq(&bar0->rmac_pause_cfg);
5635 if (ep->tx_pause)
5636 val64 |= RMAC_PAUSE_GEN_ENABLE;
5637 else
5638 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5639 if (ep->rx_pause)
5640 val64 |= RMAC_PAUSE_RX_ENABLE;
5641 else
5642 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5643 writeq(val64, &bar0->rmac_pause_cfg);
5644 return 0;
5645}
5646
5647/**
5648 * read_eeprom - reads 4 bytes of data from user given offset.
20346722 5649 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5650 * s2io_nic structure.
5651 * @off : offset at which the data must be written
5652 * @data : Its an output parameter where the data read at the given
20346722 5653 * offset is stored.
1da177e4 5654 * Description:
20346722 5655 * Will read 4 bytes of data from the user given offset and return the
1da177e4
LT		 5656 * read data.
5657 * NOTE: Will allow to read only part of the EEPROM visible through the
5658 * I2C bus.
5659 * Return value:
5660 * -1 on failure and 0 on success.
5661 */
5662
5663#define S2IO_DEV_ID 5
d44570e4 5664static int read_eeprom(struct s2io_nic *sp, int off, u64 *data)
1da177e4
LT		 5665{
5666 int ret = -1;
5667 u32 exit_cnt = 0;
5668 u64 val64;
1ee6dd77 5669 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5670
ad4ebed0 5671 if (sp->device_type == XFRAME_I_DEVICE) {
d44570e4
JP		 5672 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5673 I2C_CONTROL_ADDR(off) |
5674 I2C_CONTROL_BYTE_CNT(0x3) |
5675 I2C_CONTROL_READ |
5676 I2C_CONTROL_CNTL_START;
ad4ebed0 5677 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
1da177e4 5678
ad4ebed0 5679 while (exit_cnt < 5) {
5680 val64 = readq(&bar0->i2c_control);
5681 if (I2C_CONTROL_CNTL_END(val64)) {
5682 *data = I2C_CONTROL_GET_DATA(val64);
5683 ret = 0;
5684 break;
5685 }
5686 msleep(50);
5687 exit_cnt++;
1da177e4 5688 }
1da177e4
LT		 5689 }
5690
ad4ebed0 5691 if (sp->device_type == XFRAME_II_DEVICE) {
5692 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5693 SPI_CONTROL_BYTECNT(0x3) |
ad4ebed0 5694 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5695 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5696 val64 |= SPI_CONTROL_REQ;
5697 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5698 while (exit_cnt < 5) {
5699 val64 = readq(&bar0->spi_control);
5700 if (val64 & SPI_CONTROL_NACK) {
5701 ret = 1;
5702 break;
5703 } else if (val64 & SPI_CONTROL_DONE) {
5704 *data = readq(&bar0->spi_data);
5705 *data &= 0xffffff;
5706 ret = 0;
5707 break;
5708 }
5709 msleep(50);
5710 exit_cnt++;
5711 }
5712 }
1da177e4
LT		 5713 return ret;
5714}
5715
5716/**
5717 * write_eeprom - actually writes the relevant part of the data value.
5718 * @sp : private member of the device structure, which is a pointer to the
5719 * s2io_nic structure.
5720 * @off : offset at which the data must be written
5721 * @data : The data that is to be written
20346722 5722 * @cnt : Number of bytes of the data that are actually to be written into
1da177e4
LT		 5723 * the Eeprom. (max of 3)
5724 * Description:
5725 * Actually writes the relevant part of the data value into the Eeprom
5726 * through the I2C bus.
5727 * Return value:
5728 * 0 on success, -1 on failure.
5729 */
5730
d44570e4 5731static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt)
1da177e4
LT		 5732{
5733 int exit_cnt = 0, ret = -1;
5734 u64 val64;
1ee6dd77 5735 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5736
ad4ebed0 5737 if (sp->device_type == XFRAME_I_DEVICE) {
d44570e4
JP		 5738 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5739 I2C_CONTROL_ADDR(off) |
5740 I2C_CONTROL_BYTE_CNT(cnt) |
5741 I2C_CONTROL_SET_DATA((u32)data) |
5742 I2C_CONTROL_CNTL_START;
ad4ebed0 5743 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5744
5745 while (exit_cnt < 5) {
5746 val64 = readq(&bar0->i2c_control);
5747 if (I2C_CONTROL_CNTL_END(val64)) {
5748 if (!(val64 & I2C_CONTROL_NACK))
5749 ret = 0;
5750 break;
5751 }
5752 msleep(50);
5753 exit_cnt++;
5754 }
5755 }
1da177e4 5756
ad4ebed0 5757 if (sp->device_type == XFRAME_II_DEVICE) {
5758 int write_cnt = (cnt == 8) ? 0 : cnt;
d44570e4 5759 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
ad4ebed0 5760
5761 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5762 SPI_CONTROL_BYTECNT(write_cnt) |
ad4ebed0 5763 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5764 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5765 val64 |= SPI_CONTROL_REQ;
5766 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5767 while (exit_cnt < 5) {
5768 val64 = readq(&bar0->spi_control);
5769 if (val64 & SPI_CONTROL_NACK) {
5770 ret = 1;
5771 break;
5772 } else if (val64 & SPI_CONTROL_DONE) {
1da177e4 5773 ret = 0;
ad4ebed0 5774 break;
5775 }
5776 msleep(50);
5777 exit_cnt++;
1da177e4 5778 }
1da177e4 5779 }
1da177e4
LT		 5780 return ret;
5781}
1ee6dd77 5782static void s2io_vpd_read(struct s2io_nic *nic)
9dc737a7 5783{
b41477f3
AR		 5784 u8 *vpd_data;
5785 u8 data;
9c179780 5786 int i = 0, cnt, len, fail = 0;
9dc737a7 5787 int vpd_addr = 0x80;
ffb5df6c 5788 struct swStat *swstats = &nic->mac_control.stats_info->sw_stat;
9dc737a7
AR		 5789
5790 if (nic->device_type == XFRAME_II_DEVICE) {
5791 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5792 vpd_addr = 0x80;
d44570e4 5793 } else {
9dc737a7
AR		 5794 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5795 vpd_addr = 0x50;
5796 }
19a60522 5797 strcpy(nic->serial_num, "NOT AVAILABLE");
9dc737a7 5798
b41477f3 5799 vpd_data = kmalloc(256, GFP_KERNEL);
c53d4945 5800 if (!vpd_data) {
ffb5df6c 5801 swstats->mem_alloc_fail_cnt++;
b41477f3 5802 return;
c53d4945 5803 }
ffb5df6c 5804 swstats->mem_allocated += 256;
b41477f3 5805
d44570e4 5806 for (i = 0; i < 256; i += 4) {
9dc737a7
AR		 5807 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5808 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5809 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
d44570e4 5810 for (cnt = 0; cnt < 5; cnt++) {
9dc737a7
AR		 5811 msleep(2);
5812 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5813 if (data == 0x80)
5814 break;
5815 }
5816 if (cnt >= 5) {
5817 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5818 fail = 1;
5819 break;
5820 }
5821 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5822 (u32 *)&vpd_data[i]);
5823 }
19a60522 5824
d44570e4 5825 if (!fail) {
19a60522 5826 /* read serial number of adapter */
9c179780 5827 for (cnt = 0; cnt < 252; cnt++) {
d44570e4 5828 if ((vpd_data[cnt] == 'S') &&
9c179780
KV		 5829 (vpd_data[cnt+1] == 'N')) {
5830 len = vpd_data[cnt+2];
5831 if (len < min(VPD_STRING_LEN, 256-cnt-2)) {
5832 memcpy(nic->serial_num,
5833 &vpd_data[cnt + 3],
5834 len);
5835 memset(nic->serial_num+len,
5836 0,
5837 VPD_STRING_LEN-len);
5838 break;
5839 }
19a60522
SS		 5840 }
5841 }
5842 }
5843
9c179780
KV		 5844 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5845 len = vpd_data[1];
5846 memcpy(nic->product_name, &vpd_data[3], len);
5847 nic->product_name[len] = 0;
5848 }
b41477f3 5849 kfree(vpd_data);
ffb5df6c 5850 swstats->mem_freed += 256;
9dc737a7
AR		 5851}
5852
1da177e4
LT		 5853/**
5854 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5855 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
20346722 5856 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5857 * containing all relevant information.
5858 * @data_buf : user defined value to be written into Eeprom.
5859 * Description: Reads the values stored in the Eeprom at given offset
5860 * for a given length. Stores these values int the input argument data
5861 * buffer 'data_buf' and returns these to the caller (ethtool.)
5862 * Return value:
5863 * int 0 on success
5864 */
5865
5866static int s2io_ethtool_geeprom(struct net_device *dev,
d44570e4 5867 struct ethtool_eeprom *eeprom, u8 * data_buf)
1da177e4 5868{
ad4ebed0 5869 u32 i, valid;
5870 u64 data;
4cf1653a 5871 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5872
5873 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5874
5875 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5876 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5877
5878 for (i = 0; i < eeprom->len; i += 4) {
5879 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5880 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5881 return -EFAULT;
5882 }
5883 valid = INV(data);
5884 memcpy((data_buf + i), &valid, 4);
5885 }
5886 return 0;
5887}
5888
5889/**
5890 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5891 * @sp : private member of the device structure, which is a pointer to the
5892 * s2io_nic structure.
20346722 5893 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5894 * containing all relevant information.
5895 * @data_buf ; user defined value to be written into Eeprom.
5896 * Description:
5897 * Tries to write the user provided value in the Eeprom, at the offset
5898 * given by the user.
5899 * Return value:
5900 * 0 on success, -EFAULT on failure.
5901 */
5902
5903static int s2io_ethtool_seeprom(struct net_device *dev,
5904 struct ethtool_eeprom *eeprom,
d44570e4 5905 u8 *data_buf)
1da177e4
LT		 5906{
5907 int len = eeprom->len, cnt = 0;
ad4ebed0 5908 u64 valid = 0, data;
4cf1653a 5909 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5910
5911 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5912 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 5913 "ETHTOOL_WRITE_EEPROM Err: "
5914 "Magic value is wrong, it is 0x%x should be 0x%x\n",
5915 (sp->pdev->vendor | (sp->pdev->device << 16)),
5916 eeprom->magic);
1da177e4
LT		 5917 return -EFAULT;
5918 }
5919
5920 while (len) {
d44570e4
JP		 5921 data = (u32)data_buf[cnt] & 0x000000FF;
5922 if (data)
5923 valid = (u32)(data << 24);
5924 else
1da177e4
LT		 5925 valid = data;
5926
5927 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5928 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 5929 "ETHTOOL_WRITE_EEPROM Err: "
5930 "Cannot write into the specified offset\n");
1da177e4
LT		 5931 return -EFAULT;
5932 }
5933 cnt++;
5934 len--;
5935 }
5936
5937 return 0;
5938}
5939
5940/**
20346722
K		 5941 * s2io_register_test - reads and writes into all clock domains.
5942 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5943 * s2io_nic structure.
5944 * @data : variable that returns the result of each of the test conducted b
5945 * by the driver.
5946 * Description:
5947 * Read and write into all clock domains. The NIC has 3 clock domains,
5948 * see that registers in all the three regions are accessible.
5949 * Return value:
5950 * 0 on success.
5951 */
5952
d44570e4 5953static int s2io_register_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 5954{
1ee6dd77 5955 struct XENA_dev_config __iomem *bar0 = sp->bar0;
ad4ebed0 5956 u64 val64 = 0, exp_val;
1da177e4
LT		 5957 int fail = 0;
5958
20346722
K		 5959 val64 = readq(&bar0->pif_rd_swapper_fb);
5960 if (val64 != 0x123456789abcdefULL) {
1da177e4 5961 fail = 1;
9e39f7c5 5962 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 1);
1da177e4
LT		 5963 }
5964
5965 val64 = readq(&bar0->rmac_pause_cfg);
5966 if (val64 != 0xc000ffff00000000ULL) {
5967 fail = 1;
9e39f7c5 5968 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 2);
1da177e4
LT		 5969 }
5970
5971 val64 = readq(&bar0->rx_queue_cfg);
ad4ebed0 5972 if (sp->device_type == XFRAME_II_DEVICE)
5973 exp_val = 0x0404040404040404ULL;
5974 else
5975 exp_val = 0x0808080808080808ULL;
5976 if (val64 != exp_val) {
1da177e4 5977 fail = 1;
9e39f7c5 5978 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 3);
1da177e4
LT		 5979 }
5980
5981 val64 = readq(&bar0->xgxs_efifo_cfg);
5982 if (val64 != 0x000000001923141EULL) {
5983 fail = 1;
9e39f7c5 5984 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 4);
1da177e4
LT		 5985 }
5986
5987 val64 = 0x5A5A5A5A5A5A5A5AULL;
5988 writeq(val64, &bar0->xmsi_data);
5989 val64 = readq(&bar0->xmsi_data);
5990 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5991 fail = 1;
9e39f7c5 5992 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 1);
1da177e4
LT		 5993 }
5994
5995 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5996 writeq(val64, &bar0->xmsi_data);
5997 val64 = readq(&bar0->xmsi_data);
5998 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5999 fail = 1;
9e39f7c5 6000 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 2);
1da177e4
LT		 6001 }
6002
6003 *data = fail;
ad4ebed0 6004 return fail;
1da177e4
LT		 6005}
6006
6007/**
20346722 6008 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
1da177e4
LT		 6009 * @sp : private member of the device structure, which is a pointer to the
6010 * s2io_nic structure.
6011 * @data:variable that returns the result of each of the test conducted by
6012 * the driver.
6013 * Description:
20346722 6014 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
1da177e4
LT		 6015 * register.
6016 * Return value:
6017 * 0 on success.
6018 */
6019
d44570e4 6020static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data)
1da177e4
LT		 6021{
6022 int fail = 0;
ad4ebed0 6023 u64 ret_data, org_4F0, org_7F0;
6024 u8 saved_4F0 = 0, saved_7F0 = 0;
6025 struct net_device *dev = sp->dev;
1da177e4
LT		 6026
6027 /* Test Write Error at offset 0 */
ad4ebed0 6028 /* Note that SPI interface allows write access to all areas
6029 * of EEPROM. Hence doing all negative testing only for Xframe I.
6030 */
6031 if (sp->device_type == XFRAME_I_DEVICE)
6032 if (!write_eeprom(sp, 0, 0, 3))
6033 fail = 1;
6034
6035 /* Save current values at offsets 0x4F0 and 0x7F0 */
6036 if (!read_eeprom(sp, 0x4F0, &org_4F0))
6037 saved_4F0 = 1;
6038 if (!read_eeprom(sp, 0x7F0, &org_7F0))
6039 saved_7F0 = 1;
1da177e4
LT		 6040
6041 /* Test Write at offset 4f0 */
ad4ebed0 6042 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
1da177e4
LT		 6043 fail = 1;
6044 if (read_eeprom(sp, 0x4F0, &ret_data))
6045 fail = 1;
6046
ad4ebed0 6047 if (ret_data != 0x012345) {
26b7625c 6048 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
d44570e4
JP		 6049 "Data written %llx Data read %llx\n",
6050 dev->name, (unsigned long long)0x12345,
6051 (unsigned long long)ret_data);
1da177e4 6052 fail = 1;
ad4ebed0 6053 }
1da177e4
LT		 6054
6055 /* Reset the EEPROM data go FFFF */
ad4ebed0 6056 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
1da177e4
LT		 6057
6058 /* Test Write Request Error at offset 0x7c */
ad4ebed0 6059 if (sp->device_type == XFRAME_I_DEVICE)
6060 if (!write_eeprom(sp, 0x07C, 0, 3))
6061 fail = 1;
1da177e4 6062
ad4ebed0 6063 /* Test Write Request at offset 0x7f0 */
6064 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
1da177e4 6065 fail = 1;
ad4ebed0 6066 if (read_eeprom(sp, 0x7F0, &ret_data))
1da177e4
LT		 6067 fail = 1;
6068
ad4ebed0 6069 if (ret_data != 0x012345) {
26b7625c 6070 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
d44570e4
JP		 6071 "Data written %llx Data read %llx\n",
6072 dev->name, (unsigned long long)0x12345,
6073 (unsigned long long)ret_data);
1da177e4 6074 fail = 1;
ad4ebed0 6075 }
1da177e4
LT		 6076
6077 /* Reset the EEPROM data go FFFF */
ad4ebed0 6078 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
1da177e4 6079
ad4ebed0 6080 if (sp->device_type == XFRAME_I_DEVICE) {
6081 /* Test Write Error at offset 0x80 */
6082 if (!write_eeprom(sp, 0x080, 0, 3))
6083 fail = 1;
1da177e4 6084
ad4ebed0 6085 /* Test Write Error at offset 0xfc */
6086 if (!write_eeprom(sp, 0x0FC, 0, 3))
6087 fail = 1;
1da177e4 6088
ad4ebed0 6089 /* Test Write Error at offset 0x100 */
6090 if (!write_eeprom(sp, 0x100, 0, 3))
6091 fail = 1;
1da177e4 6092
ad4ebed0 6093 /* Test Write Error at offset 4ec */
6094 if (!write_eeprom(sp, 0x4EC, 0, 3))
6095 fail = 1;
6096 }
6097
6098 /* Restore values at offsets 0x4F0 and 0x7F0 */
6099 if (saved_4F0)
6100 write_eeprom(sp, 0x4F0, org_4F0, 3);
6101 if (saved_7F0)
6102 write_eeprom(sp, 0x7F0, org_7F0, 3);
1da177e4
LT		 6103
6104 *data = fail;
ad4ebed0 6105 return fail;
1da177e4
LT		 6106}
6107
6108/**
6109 * s2io_bist_test - invokes the MemBist test of the card .
20346722 6110 * @sp : private member of the device structure, which is a pointer to the
1da177e4 6111 * s2io_nic structure.
20346722 6112 * @data:variable that returns the result of each of the test conducted by
1da177e4
LT		 6113 * the driver.
6114 * Description:
6115 * This invokes the MemBist test of the card. We give around
6116 * 2 secs time for the Test to complete. If it's still not complete
20346722 6117 * within this peiod, we consider that the test failed.
1da177e4
LT		 6118 * Return value:
6119 * 0 on success and -1 on failure.
6120 */
6121
d44570e4 6122static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data)
1da177e4
LT		 6123{
6124 u8 bist = 0;
6125 int cnt = 0, ret = -1;
6126
6127 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6128 bist |= PCI_BIST_START;
6129 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6130
6131 while (cnt < 20) {
6132 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6133 if (!(bist & PCI_BIST_START)) {
6134 *data = (bist & PCI_BIST_CODE_MASK);
6135 ret = 0;
6136 break;
6137 }
6138 msleep(100);
6139 cnt++;
6140 }
6141
6142 return ret;
6143}
6144
6145/**
20346722
K		 6146 * s2io-link_test - verifies the link state of the nic
6147 * @sp ; private member of the device structure, which is a pointer to the
1da177e4
LT		 6148 * s2io_nic structure.
6149 * @data: variable that returns the result of each of the test conducted by
6150 * the driver.
6151 * Description:
20346722 6152 * The function verifies the link state of the NIC and updates the input
1da177e4
LT		 6153 * argument 'data' appropriately.
6154 * Return value:
6155 * 0 on success.
6156 */
6157
d44570e4 6158static int s2io_link_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 6159{
1ee6dd77 6160 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 6161 u64 val64;
6162
6163 val64 = readq(&bar0->adapter_status);
d44570e4 6164 if (!(LINK_IS_UP(val64)))
1da177e4 6165 *data = 1;
c92ca04b
AR		 6166 else
6167 *data = 0;
1da177e4 6168
b41477f3 6169 return *data;
1da177e4
LT		 6170}
6171
6172/**
20346722
K		 6173 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6174 * @sp - private member of the device structure, which is a pointer to the
1da177e4 6175 * s2io_nic structure.
20346722 6176 * @data - variable that returns the result of each of the test
1da177e4
LT		 6177 * conducted by the driver.
6178 * Description:
20346722 6179 * This is one of the offline test that tests the read and write
1da177e4
LT		 6180 * access to the RldRam chip on the NIC.
6181 * Return value:
6182 * 0 on success.
6183 */
6184
d44570e4 6185static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 6186{
1ee6dd77 6187 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 6188 u64 val64;
ad4ebed0 6189 int cnt, iteration = 0, test_fail = 0;
1da177e4
LT		 6190
6191 val64 = readq(&bar0->adapter_control);
6192 val64 &= ~ADAPTER_ECC_EN;
6193 writeq(val64, &bar0->adapter_control);
6194
6195 val64 = readq(&bar0->mc_rldram_test_ctrl);
6196 val64 |= MC_RLDRAM_TEST_MODE;
ad4ebed0 6197 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6198
6199 val64 = readq(&bar0->mc_rldram_mrs);
6200 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6201 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6202
6203 val64 |= MC_RLDRAM_MRS_ENABLE;
6204 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6205
6206 while (iteration < 2) {
6207 val64 = 0x55555555aaaa0000ULL;
d44570e4 6208 if (iteration == 1)
1da177e4 6209 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6210 writeq(val64, &bar0->mc_rldram_test_d0);
6211
6212 val64 = 0xaaaa5a5555550000ULL;
d44570e4 6213 if (iteration == 1)
1da177e4 6214 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6215 writeq(val64, &bar0->mc_rldram_test_d1);
6216
6217 val64 = 0x55aaaaaaaa5a0000ULL;
d44570e4 6218 if (iteration == 1)
1da177e4 6219 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6220 writeq(val64, &bar0->mc_rldram_test_d2);
6221
ad4ebed0 6222 val64 = (u64) (0x0000003ffffe0100ULL);
1da177e4
LT		 6223 writeq(val64, &bar0->mc_rldram_test_add);
6224
d44570e4
JP		 6225 val64 = MC_RLDRAM_TEST_MODE |
6226 MC_RLDRAM_TEST_WRITE |
6227 MC_RLDRAM_TEST_GO;
ad4ebed0 6228 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6229
6230 for (cnt = 0; cnt < 5; cnt++) {
6231 val64 = readq(&bar0->mc_rldram_test_ctrl);
6232 if (val64 & MC_RLDRAM_TEST_DONE)
6233 break;
6234 msleep(200);
6235 }
6236
6237 if (cnt == 5)
6238 break;
6239
ad4ebed0 6240 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6241 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6242
6243 for (cnt = 0; cnt < 5; cnt++) {
6244 val64 = readq(&bar0->mc_rldram_test_ctrl);
6245 if (val64 & MC_RLDRAM_TEST_DONE)
6246 break;
6247 msleep(500);
6248 }
6249
6250 if (cnt == 5)
6251 break;
6252
6253 val64 = readq(&bar0->mc_rldram_test_ctrl);
ad4ebed0 6254 if (!(val64 & MC_RLDRAM_TEST_PASS))
6255 test_fail = 1;
1da177e4
LT		 6256
6257 iteration++;
6258 }
6259
ad4ebed0 6260 *data = test_fail;
1da177e4 6261
ad4ebed0 6262 /* Bring the adapter out of test mode */
6263 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6264
6265 return test_fail;
1da177e4
LT		 6266}
6267
6268/**
6269 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6270 * @sp : private member of the device structure, which is a pointer to the
6271 * s2io_nic structure.
6272 * @ethtest : pointer to a ethtool command specific structure that will be
6273 * returned to the user.
20346722 6274 * @data : variable that returns the result of each of the test
1da177e4
LT		 6275 * conducted by the driver.
6276 * Description:
6277 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6278 * the health of the card.
6279 * Return value:
6280 * void
6281 */
6282
6283static void s2io_ethtool_test(struct net_device *dev,
6284 struct ethtool_test *ethtest,
d44570e4 6285 uint64_t *data)
1da177e4 6286{
4cf1653a 6287 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 6288 int orig_state = netif_running(sp->dev);
6289
6290 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6291 /* Offline Tests. */
20346722 6292 if (orig_state)
1da177e4 6293 s2io_close(sp->dev);
1da177e4
LT		 6294
6295 if (s2io_register_test(sp, &data[0]))
6296 ethtest->flags |= ETH_TEST_FL_FAILED;
6297
6298 s2io_reset(sp);
1da177e4
LT		 6299
6300 if (s2io_rldram_test(sp, &data[3]))
6301 ethtest->flags |= ETH_TEST_FL_FAILED;
6302
6303 s2io_reset(sp);
1da177e4
LT		 6304
6305 if (s2io_eeprom_test(sp, &data[1]))
6306 ethtest->flags |= ETH_TEST_FL_FAILED;
6307
6308 if (s2io_bist_test(sp, &data[4]))
6309 ethtest->flags |= ETH_TEST_FL_FAILED;
6310
6311 if (orig_state)
6312 s2io_open(sp->dev);
6313
6314 data[2] = 0;
6315 } else {
6316 /* Online Tests. */
6317 if (!orig_state) {
d44570e4 6318 DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n",
1da177e4
LT		 6319 dev->name);
6320 data[0] = -1;
6321 data[1] = -1;
6322 data[2] = -1;
6323 data[3] = -1;
6324 data[4] = -1;
6325 }
6326
6327 if (s2io_link_test(sp, &data[2]))
6328 ethtest->flags |= ETH_TEST_FL_FAILED;
6329
6330 data[0] = 0;
6331 data[1] = 0;
6332 data[3] = 0;
6333 data[4] = 0;
6334 }
6335}
6336
6337static void s2io_get_ethtool_stats(struct net_device *dev,
6338 struct ethtool_stats *estats,
d44570e4 6339 u64 *tmp_stats)
1da177e4 6340{
8116f3cf 6341 int i = 0, k;
4cf1653a 6342 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c
JP		 6343 struct stat_block *stats = sp->mac_control.stats_info;
6344 struct swStat *swstats = &stats->sw_stat;
6345 struct xpakStat *xstats = &stats->xpak_stat;
1da177e4 6346
7ba013ac 6347 s2io_updt_stats(sp);
541ae68f 6348 tmp_stats[i++] =
ffb5df6c
JP		 6349 (u64)le32_to_cpu(stats->tmac_frms_oflow) << 32 |
6350 le32_to_cpu(stats->tmac_frms);
541ae68f 6351 tmp_stats[i++] =
ffb5df6c
JP		 6352 (u64)le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
6353 le32_to_cpu(stats->tmac_data_octets);
6354 tmp_stats[i++] = le64_to_cpu(stats->tmac_drop_frms);
541ae68f 6355 tmp_stats[i++] =
ffb5df6c
JP		 6356 (u64)le32_to_cpu(stats->tmac_mcst_frms_oflow) << 32 |
6357 le32_to_cpu(stats->tmac_mcst_frms);
541ae68f 6358 tmp_stats[i++] =
ffb5df6c
JP		 6359 (u64)le32_to_cpu(stats->tmac_bcst_frms_oflow) << 32 |
6360 le32_to_cpu(stats->tmac_bcst_frms);
6361 tmp_stats[i++] = le64_to_cpu(stats->tmac_pause_ctrl_frms);
bd1034f0 6362 tmp_stats[i++] =
ffb5df6c
JP		 6363 (u64)le32_to_cpu(stats->tmac_ttl_octets_oflow) << 32 |
6364 le32_to_cpu(stats->tmac_ttl_octets);
bd1034f0 6365 tmp_stats[i++] =
ffb5df6c
JP		 6366 (u64)le32_to_cpu(stats->tmac_ucst_frms_oflow) << 32 |
6367 le32_to_cpu(stats->tmac_ucst_frms);
d44570e4 6368 tmp_stats[i++] =
ffb5df6c
JP		 6369 (u64)le32_to_cpu(stats->tmac_nucst_frms_oflow) << 32 |
6370 le32_to_cpu(stats->tmac_nucst_frms);
541ae68f 6371 tmp_stats[i++] =
ffb5df6c
JP		 6372 (u64)le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
6373 le32_to_cpu(stats->tmac_any_err_frms);
6374 tmp_stats[i++] = le64_to_cpu(stats->tmac_ttl_less_fb_octets);
6375 tmp_stats[i++] = le64_to_cpu(stats->tmac_vld_ip_octets);
541ae68f 6376 tmp_stats[i++] =
ffb5df6c
JP		 6377 (u64)le32_to_cpu(stats->tmac_vld_ip_oflow) << 32 |
6378 le32_to_cpu(stats->tmac_vld_ip);
541ae68f 6379 tmp_stats[i++] =
ffb5df6c
JP		 6380 (u64)le32_to_cpu(stats->tmac_drop_ip_oflow) << 32 |
6381 le32_to_cpu(stats->tmac_drop_ip);
541ae68f 6382 tmp_stats[i++] =
ffb5df6c
JP		 6383 (u64)le32_to_cpu(stats->tmac_icmp_oflow) << 32 |
6384 le32_to_cpu(stats->tmac_icmp);
541ae68f 6385 tmp_stats[i++] =
ffb5df6c
JP		 6386 (u64)le32_to_cpu(stats->tmac_rst_tcp_oflow) << 32 |
6387 le32_to_cpu(stats->tmac_rst_tcp);
6388 tmp_stats[i++] = le64_to_cpu(stats->tmac_tcp);
6389 tmp_stats[i++] = (u64)le32_to_cpu(stats->tmac_udp_oflow) << 32 |
6390 le32_to_cpu(stats->tmac_udp);
541ae68f 6391 tmp_stats[i++] =
ffb5df6c
JP		 6392 (u64)le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
6393 le32_to_cpu(stats->rmac_vld_frms);
541ae68f 6394 tmp_stats[i++] =
ffb5df6c
JP		 6395 (u64)le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
6396 le32_to_cpu(stats->rmac_data_octets);
6397 tmp_stats[i++] = le64_to_cpu(stats->rmac_fcs_err_frms);
6398 tmp_stats[i++] = le64_to_cpu(stats->rmac_drop_frms);
541ae68f 6399 tmp_stats[i++] =
ffb5df6c
JP		 6400 (u64)le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
6401 le32_to_cpu(stats->rmac_vld_mcst_frms);
541ae68f 6402 tmp_stats[i++] =
ffb5df6c
JP		 6403 (u64)le32_to_cpu(stats->rmac_vld_bcst_frms_oflow) << 32 |
6404 le32_to_cpu(stats->rmac_vld_bcst_frms);
6405 tmp_stats[i++] = le32_to_cpu(stats->rmac_in_rng_len_err_frms);
6406 tmp_stats[i++] = le32_to_cpu(stats->rmac_out_rng_len_err_frms);
6407 tmp_stats[i++] = le64_to_cpu(stats->rmac_long_frms);
6408 tmp_stats[i++] = le64_to_cpu(stats->rmac_pause_ctrl_frms);
6409 tmp_stats[i++] = le64_to_cpu(stats->rmac_unsup_ctrl_frms);
d44570e4 6410 tmp_stats[i++] =
ffb5df6c
JP		 6411 (u64)le32_to_cpu(stats->rmac_ttl_octets_oflow) << 32 |
6412 le32_to_cpu(stats->rmac_ttl_octets);
bd1034f0 6413 tmp_stats[i++] =
ffb5df6c
JP		 6414 (u64)le32_to_cpu(stats->rmac_accepted_ucst_frms_oflow) << 32
6415 | le32_to_cpu(stats->rmac_accepted_ucst_frms);
d44570e4 6416 tmp_stats[i++] =
ffb5df6c
JP		 6417 (u64)le32_to_cpu(stats->rmac_accepted_nucst_frms_oflow)
6418 << 32 | le32_to_cpu(stats->rmac_accepted_nucst_frms);
541ae68f 6419 tmp_stats[i++] =
ffb5df6c
JP		 6420 (u64)le32_to_cpu(stats->rmac_discarded_frms_oflow) << 32 |
6421 le32_to_cpu(stats->rmac_discarded_frms);
d44570e4 6422 tmp_stats[i++] =
ffb5df6c
JP		 6423 (u64)le32_to_cpu(stats->rmac_drop_events_oflow)
6424 << 32 | le32_to_cpu(stats->rmac_drop_events);
6425 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_less_fb_octets);
6426 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_frms);
541ae68f 6427 tmp_stats[i++] =
ffb5df6c
JP		 6428 (u64)le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
6429 le32_to_cpu(stats->rmac_usized_frms);
541ae68f 6430 tmp_stats[i++] =
ffb5df6c
JP		 6431 (u64)le32_to_cpu(stats->rmac_osized_frms_oflow) << 32 |
6432 le32_to_cpu(stats->rmac_osized_frms);
541ae68f 6433 tmp_stats[i++] =
ffb5df6c
JP		 6434 (u64)le32_to_cpu(stats->rmac_frag_frms_oflow) << 32 |
6435 le32_to_cpu(stats->rmac_frag_frms);
541ae68f 6436 tmp_stats[i++] =
ffb5df6c
JP		 6437 (u64)le32_to_cpu(stats->rmac_jabber_frms_oflow) << 32 |
6438 le32_to_cpu(stats->rmac_jabber_frms);
6439 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_64_frms);
6440 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_65_127_frms);
6441 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_128_255_frms);
6442 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_256_511_frms);
6443 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_512_1023_frms);
6444 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_1024_1518_frms);
bd1034f0 6445 tmp_stats[i++] =
ffb5df6c
JP		 6446 (u64)le32_to_cpu(stats->rmac_ip_oflow) << 32 |
6447 le32_to_cpu(stats->rmac_ip);
6448 tmp_stats[i++] = le64_to_cpu(stats->rmac_ip_octets);
6449 tmp_stats[i++] = le32_to_cpu(stats->rmac_hdr_err_ip);
bd1034f0 6450 tmp_stats[i++] =
ffb5df6c
JP		 6451 (u64)le32_to_cpu(stats->rmac_drop_ip_oflow) << 32 |
6452 le32_to_cpu(stats->rmac_drop_ip);
bd1034f0 6453 tmp_stats[i++] =
ffb5df6c
JP		 6454 (u64)le32_to_cpu(stats->rmac_icmp_oflow) << 32 |
6455 le32_to_cpu(stats->rmac_icmp);
6456 tmp_stats[i++] = le64_to_cpu(stats->rmac_tcp);
bd1034f0 6457 tmp_stats[i++] =
ffb5df6c
JP		 6458 (u64)le32_to_cpu(stats->rmac_udp_oflow) << 32 |
6459 le32_to_cpu(stats->rmac_udp);
541ae68f 6460 tmp_stats[i++] =
ffb5df6c
JP		 6461 (u64)le32_to_cpu(stats->rmac_err_drp_udp_oflow) << 32 |
6462 le32_to_cpu(stats->rmac_err_drp_udp);
6463 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_err_sym);
6464 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q0);
6465 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q1);
6466 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q2);
6467 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q3);
6468 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q4);
6469 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q5);
6470 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q6);
6471 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q7);
6472 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q0);
6473 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q1);
6474 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q2);
6475 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q3);
6476 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q4);
6477 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q5);
6478 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q6);
6479 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q7);
541ae68f 6480 tmp_stats[i++] =
ffb5df6c
JP		 6481 (u64)le32_to_cpu(stats->rmac_pause_cnt_oflow) << 32 |
6482 le32_to_cpu(stats->rmac_pause_cnt);
6483 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_data_err_cnt);
6484 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_ctrl_err_cnt);
541ae68f 6485 tmp_stats[i++] =
ffb5df6c
JP		 6486 (u64)le32_to_cpu(stats->rmac_accepted_ip_oflow) << 32 |
6487 le32_to_cpu(stats->rmac_accepted_ip);
6488 tmp_stats[i++] = le32_to_cpu(stats->rmac_err_tcp);
6489 tmp_stats[i++] = le32_to_cpu(stats->rd_req_cnt);
6490 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_cnt);
6491 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_rtry_cnt);
6492 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_cnt);
6493 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_rd_ack_cnt);
6494 tmp_stats[i++] = le32_to_cpu(stats->wr_req_cnt);
6495 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_cnt);
6496 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_rtry_cnt);
6497 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_cnt);
6498 tmp_stats[i++] = le32_to_cpu(stats->wr_disc_cnt);
6499 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_wr_ack_cnt);
6500 tmp_stats[i++] = le32_to_cpu(stats->txp_wr_cnt);
6501 tmp_stats[i++] = le32_to_cpu(stats->txd_rd_cnt);
6502 tmp_stats[i++] = le32_to_cpu(stats->txd_wr_cnt);
6503 tmp_stats[i++] = le32_to_cpu(stats->rxd_rd_cnt);
6504 tmp_stats[i++] = le32_to_cpu(stats->rxd_wr_cnt);
6505 tmp_stats[i++] = le32_to_cpu(stats->txf_rd_cnt);
6506 tmp_stats[i++] = le32_to_cpu(stats->rxf_wr_cnt);
fa1f0cb3
SS		 6507
6508 /* Enhanced statistics exist only for Hercules */
d44570e4 6509 if (sp->device_type == XFRAME_II_DEVICE) {
fa1f0cb3 6510 tmp_stats[i++] =
ffb5df6c 6511 le64_to_cpu(stats->rmac_ttl_1519_4095_frms);
fa1f0cb3 6512 tmp_stats[i++] =
ffb5df6c 6513 le64_to_cpu(stats->rmac_ttl_4096_8191_frms);
fa1f0cb3 6514 tmp_stats[i++] =
ffb5df6c
JP		 6515 le64_to_cpu(stats->rmac_ttl_8192_max_frms);
6516 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_gt_max_frms);
6517 tmp_stats[i++] = le64_to_cpu(stats->rmac_osized_alt_frms);
6518 tmp_stats[i++] = le64_to_cpu(stats->rmac_jabber_alt_frms);
6519 tmp_stats[i++] = le64_to_cpu(stats->rmac_gt_max_alt_frms);
6520 tmp_stats[i++] = le64_to_cpu(stats->rmac_vlan_frms);
6521 tmp_stats[i++] = le32_to_cpu(stats->rmac_len_discard);
6522 tmp_stats[i++] = le32_to_cpu(stats->rmac_fcs_discard);
6523 tmp_stats[i++] = le32_to_cpu(stats->rmac_pf_discard);
6524 tmp_stats[i++] = le32_to_cpu(stats->rmac_da_discard);
6525 tmp_stats[i++] = le32_to_cpu(stats->rmac_red_discard);
6526 tmp_stats[i++] = le32_to_cpu(stats->rmac_rts_discard);
6527 tmp_stats[i++] = le32_to_cpu(stats->rmac_ingm_full_discard);
6528 tmp_stats[i++] = le32_to_cpu(stats->link_fault_cnt);
fa1f0cb3
SS		 6529 }
6530
7ba013ac 6531 tmp_stats[i++] = 0;
ffb5df6c
JP		 6532 tmp_stats[i++] = swstats->single_ecc_errs;
6533 tmp_stats[i++] = swstats->double_ecc_errs;
6534 tmp_stats[i++] = swstats->parity_err_cnt;
6535 tmp_stats[i++] = swstats->serious_err_cnt;
6536 tmp_stats[i++] = swstats->soft_reset_cnt;
6537 tmp_stats[i++] = swstats->fifo_full_cnt;
8116f3cf 6538 for (k = 0; k < MAX_RX_RINGS; k++)
ffb5df6c
JP		 6539 tmp_stats[i++] = swstats->ring_full_cnt[k];
6540 tmp_stats[i++] = xstats->alarm_transceiver_temp_high;
6541 tmp_stats[i++] = xstats->alarm_transceiver_temp_low;
6542 tmp_stats[i++] = xstats->alarm_laser_bias_current_high;
6543 tmp_stats[i++] = xstats->alarm_laser_bias_current_low;
6544 tmp_stats[i++] = xstats->alarm_laser_output_power_high;
6545 tmp_stats[i++] = xstats->alarm_laser_output_power_low;
6546 tmp_stats[i++] = xstats->warn_transceiver_temp_high;
6547 tmp_stats[i++] = xstats->warn_transceiver_temp_low;
6548 tmp_stats[i++] = xstats->warn_laser_bias_current_high;
6549 tmp_stats[i++] = xstats->warn_laser_bias_current_low;
6550 tmp_stats[i++] = xstats->warn_laser_output_power_high;
6551 tmp_stats[i++] = xstats->warn_laser_output_power_low;
6552 tmp_stats[i++] = swstats->clubbed_frms_cnt;
6553 tmp_stats[i++] = swstats->sending_both;
6554 tmp_stats[i++] = swstats->outof_sequence_pkts;
6555 tmp_stats[i++] = swstats->flush_max_pkts;
6556 if (swstats->num_aggregations) {
6557 u64 tmp = swstats->sum_avg_pkts_aggregated;
bd1034f0 6558 int count = 0;
6aa20a22 6559 /*
bd1034f0
AR		 6560 * Since 64-bit divide does not work on all platforms,
6561 * do repeated subtraction.
6562 */
ffb5df6c
JP		 6563 while (tmp >= swstats->num_aggregations) {
6564 tmp -= swstats->num_aggregations;
bd1034f0
AR		 6565 count++;
6566 }
6567 tmp_stats[i++] = count;
d44570e4 6568 } else
bd1034f0 6569 tmp_stats[i++] = 0;
ffb5df6c
JP		 6570 tmp_stats[i++] = swstats->mem_alloc_fail_cnt;
6571 tmp_stats[i++] = swstats->pci_map_fail_cnt;
6572 tmp_stats[i++] = swstats->watchdog_timer_cnt;
6573 tmp_stats[i++] = swstats->mem_allocated;
6574 tmp_stats[i++] = swstats->mem_freed;
6575 tmp_stats[i++] = swstats->link_up_cnt;
6576 tmp_stats[i++] = swstats->link_down_cnt;
6577 tmp_stats[i++] = swstats->link_up_time;
6578 tmp_stats[i++] = swstats->link_down_time;
6579
6580 tmp_stats[i++] = swstats->tx_buf_abort_cnt;
6581 tmp_stats[i++] = swstats->tx_desc_abort_cnt;
6582 tmp_stats[i++] = swstats->tx_parity_err_cnt;
6583 tmp_stats[i++] = swstats->tx_link_loss_cnt;
6584 tmp_stats[i++] = swstats->tx_list_proc_err_cnt;
6585
6586 tmp_stats[i++] = swstats->rx_parity_err_cnt;
6587 tmp_stats[i++] = swstats->rx_abort_cnt;
6588 tmp_stats[i++] = swstats->rx_parity_abort_cnt;
6589 tmp_stats[i++] = swstats->rx_rda_fail_cnt;
6590 tmp_stats[i++] = swstats->rx_unkn_prot_cnt;
6591 tmp_stats[i++] = swstats->rx_fcs_err_cnt;
6592 tmp_stats[i++] = swstats->rx_buf_size_err_cnt;
6593 tmp_stats[i++] = swstats->rx_rxd_corrupt_cnt;
6594 tmp_stats[i++] = swstats->rx_unkn_err_cnt;
6595 tmp_stats[i++] = swstats->tda_err_cnt;
6596 tmp_stats[i++] = swstats->pfc_err_cnt;
6597 tmp_stats[i++] = swstats->pcc_err_cnt;
6598 tmp_stats[i++] = swstats->tti_err_cnt;
6599 tmp_stats[i++] = swstats->tpa_err_cnt;
6600 tmp_stats[i++] = swstats->sm_err_cnt;
6601 tmp_stats[i++] = swstats->lso_err_cnt;
6602 tmp_stats[i++] = swstats->mac_tmac_err_cnt;
6603 tmp_stats[i++] = swstats->mac_rmac_err_cnt;
6604 tmp_stats[i++] = swstats->xgxs_txgxs_err_cnt;
6605 tmp_stats[i++] = swstats->xgxs_rxgxs_err_cnt;
6606 tmp_stats[i++] = swstats->rc_err_cnt;
6607 tmp_stats[i++] = swstats->prc_pcix_err_cnt;
6608 tmp_stats[i++] = swstats->rpa_err_cnt;
6609 tmp_stats[i++] = swstats->rda_err_cnt;
6610 tmp_stats[i++] = swstats->rti_err_cnt;
6611 tmp_stats[i++] = swstats->mc_err_cnt;
1da177e4
LT		 6612}
6613
ac1f60db 6614static int s2io_ethtool_get_regs_len(struct net_device *dev)
1da177e4 6615{
d44570e4 6616 return XENA_REG_SPACE;
1da177e4
LT		 6617}
6618
6619
ac1f60db 6620static int s2io_get_eeprom_len(struct net_device *dev)
1da177e4 6621{
d44570e4 6622 return XENA_EEPROM_SPACE;
1da177e4
LT		 6623}
6624
b9f2c044 6625static int s2io_get_sset_count(struct net_device *dev, int sset)
1da177e4 6626{
4cf1653a 6627 struct s2io_nic *sp = netdev_priv(dev);
b9f2c044
JG		 6628
6629 switch (sset) {
6630 case ETH_SS_TEST:
6631 return S2IO_TEST_LEN;
6632 case ETH_SS_STATS:
d44570e4 6633 switch (sp->device_type) {
b9f2c044
JG		 6634 case XFRAME_I_DEVICE:
6635 return XFRAME_I_STAT_LEN;
6636 case XFRAME_II_DEVICE:
6637 return XFRAME_II_STAT_LEN;
6638 default:
6639 return 0;
6640 }
6641 default:
6642 return -EOPNOTSUPP;
6643 }
1da177e4 6644}
ac1f60db
AB		 6645
6646static void s2io_ethtool_get_strings(struct net_device *dev,
d44570e4 6647 u32 stringset, u8 *data)
1da177e4 6648{
fa1f0cb3 6649 int stat_size = 0;
4cf1653a 6650 struct s2io_nic *sp = netdev_priv(dev);
fa1f0cb3 6651
1da177e4
LT		 6652 switch (stringset) {
6653 case ETH_SS_TEST:
6654 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6655 break;
6656 case ETH_SS_STATS:
fa1f0cb3 6657 stat_size = sizeof(ethtool_xena_stats_keys);
d44570e4
JP		 6658 memcpy(data, &ethtool_xena_stats_keys, stat_size);
6659 if (sp->device_type == XFRAME_II_DEVICE) {
fa1f0cb3 6660 memcpy(data + stat_size,
d44570e4
JP		 6661 &ethtool_enhanced_stats_keys,
6662 sizeof(ethtool_enhanced_stats_keys));
fa1f0cb3
SS		 6663 stat_size += sizeof(ethtool_enhanced_stats_keys);
6664 }
6665
6666 memcpy(data + stat_size, &ethtool_driver_stats_keys,
d44570e4 6667 sizeof(ethtool_driver_stats_keys));
1da177e4
LT		 6668 }
6669}
1da177e4 6670
b437a8cc 6671static int s2io_set_features(struct net_device *dev, u32 features)
958de193
JM		 6672{
6673 struct s2io_nic *sp = netdev_priv(dev);
b437a8cc 6674 u32 changed = (features ^ dev->features) & NETIF_F_LRO;
958de193
JM		 6675
6676 if (changed && netif_running(dev)) {
b437a8cc
MM		 6677 int rc;
6678
958de193
JM		 6679 s2io_stop_all_tx_queue(sp);
6680 s2io_card_down(sp);
b437a8cc 6681 dev->features = features;
958de193
JM		 6682 rc = s2io_card_up(sp);
6683 if (rc)
6684 s2io_reset(sp);
6685 else
6686 s2io_start_all_tx_queue(sp);
b437a8cc
MM		 6687
6688 return rc ? rc : 1;
958de193
JM		 6689 }
6690
b437a8cc 6691 return 0;
958de193
JM		 6692}
6693
7282d491 6694static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 6695 .get_settings = s2io_ethtool_gset,
6696 .set_settings = s2io_ethtool_sset,
6697 .get_drvinfo = s2io_ethtool_gdrvinfo,
6698 .get_regs_len = s2io_ethtool_get_regs_len,
6699 .get_regs = s2io_ethtool_gregs,
6700 .get_link = ethtool_op_get_link,
6701 .get_eeprom_len = s2io_get_eeprom_len,
6702 .get_eeprom = s2io_ethtool_geeprom,
6703 .set_eeprom = s2io_ethtool_seeprom,
0cec35eb 6704 .get_ringparam = s2io_ethtool_gringparam,
1da177e4
LT		 6705 .get_pauseparam = s2io_ethtool_getpause_data,
6706 .set_pauseparam = s2io_ethtool_setpause_data,
1da177e4
LT		 6707 .self_test = s2io_ethtool_test,
6708 .get_strings = s2io_ethtool_get_strings,
034e3450 6709 .set_phys_id = s2io_ethtool_set_led,
b9f2c044
JG		 6710 .get_ethtool_stats = s2io_get_ethtool_stats,
6711 .get_sset_count = s2io_get_sset_count,
1da177e4
LT		 6712};
6713
6714/**
20346722 6715 * s2io_ioctl - Entry point for the Ioctl
1da177e4
LT		 6716 * @dev : Device pointer.
6717 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6718 * a proprietary structure used to pass information to the driver.
6719 * @cmd : This is used to distinguish between the different commands that
6720 * can be passed to the IOCTL functions.
6721 * Description:
20346722
K		 6722 * Currently there are no special functionality supported in IOCTL, hence
6723 * function always return EOPNOTSUPPORTED
1da177e4
LT		 6724 */
6725
ac1f60db 6726static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1da177e4
LT		 6727{
6728 return -EOPNOTSUPP;
6729}
6730
6731/**
6732 * s2io_change_mtu - entry point to change MTU size for the device.
6733 * @dev : device pointer.
6734 * @new_mtu : the new MTU size for the device.
6735 * Description: A driver entry point to change MTU size for the device.
6736 * Before changing the MTU the device must be stopped.
6737 * Return value:
6738 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6739 * file on failure.
6740 */
6741
ac1f60db 6742static int s2io_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 6743{
4cf1653a 6744 struct s2io_nic *sp = netdev_priv(dev);
9f74ffde 6745 int ret = 0;
1da177e4
LT		 6746
6747 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
d44570e4 6748 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", dev->name);
1da177e4
LT		 6749 return -EPERM;
6750 }
6751
1da177e4 6752 dev->mtu = new_mtu;
d8892c6e 6753 if (netif_running(dev)) {
3a3d5756 6754 s2io_stop_all_tx_queue(sp);
e6a8fee2 6755 s2io_card_down(sp);
9f74ffde
SH		 6756 ret = s2io_card_up(sp);
6757 if (ret) {
d8892c6e 6758 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
b39d66a8 6759 __func__);
9f74ffde 6760 return ret;
d8892c6e 6761 }
3a3d5756 6762 s2io_wake_all_tx_queue(sp);
d8892c6e 6763 } else { /* Device is down */
1ee6dd77 6764 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d8892c6e
K		 6765 u64 val64 = new_mtu;
6766
6767 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6768 }
1da177e4 6769
9f74ffde 6770 return ret;
1da177e4
LT		 6771}
6772
1da177e4
LT		 6773/**
6774 * s2io_set_link - Set the LInk status
6775 * @data: long pointer to device private structue
6776 * Description: Sets the link status for the adapter
6777 */
6778
c4028958 6779static void s2io_set_link(struct work_struct *work)
1da177e4 6780{
d44570e4
JP		 6781 struct s2io_nic *nic = container_of(work, struct s2io_nic,
6782 set_link_task);
1da177e4 6783 struct net_device *dev = nic->dev;
1ee6dd77 6784 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 6785 register u64 val64;
6786 u16 subid;
6787
22747d6b
FR		 6788 rtnl_lock();
6789
6790 if (!netif_running(dev))
6791 goto out_unlock;
6792
92b84437 6793 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
1da177e4 6794 /* The card is being reset, no point doing anything */
22747d6b 6795 goto out_unlock;
1da177e4
LT		 6796 }
6797
6798 subid = nic->pdev->subsystem_device;
a371a07d
K		 6799 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6800 /*
6801 * Allow a small delay for the NICs self initiated
6802 * cleanup to complete.
6803 */
6804 msleep(100);
6805 }
1da177e4
LT		 6806
6807 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6808 if (LINK_IS_UP(val64)) {
6809 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6810 if (verify_xena_quiescence(nic)) {
6811 val64 = readq(&bar0->adapter_control);
6812 val64 |= ADAPTER_CNTL_EN;
1da177e4 6813 writeq(val64, &bar0->adapter_control);
19a60522 6814 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
d44570e4 6815 nic->device_type, subid)) {
19a60522
SS		 6816 val64 = readq(&bar0->gpio_control);
6817 val64 |= GPIO_CTRL_GPIO_0;
6818 writeq(val64, &bar0->gpio_control);
6819 val64 = readq(&bar0->gpio_control);
6820 } else {
6821 val64 |= ADAPTER_LED_ON;
6822 writeq(val64, &bar0->adapter_control);
a371a07d 6823 }
f957bcf0 6824 nic->device_enabled_once = true;
19a60522 6825 } else {
9e39f7c5
JP		 6826 DBG_PRINT(ERR_DBG,
6827 "%s: Error: device is not Quiescent\n",
6828 dev->name);
3a3d5756 6829 s2io_stop_all_tx_queue(nic);
1da177e4 6830 }
19a60522 6831 }
92c48799
SS		 6832 val64 = readq(&bar0->adapter_control);
6833 val64 |= ADAPTER_LED_ON;
6834 writeq(val64, &bar0->adapter_control);
6835 s2io_link(nic, LINK_UP);
19a60522
SS		 6836 } else {
6837 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6838 subid)) {
6839 val64 = readq(&bar0->gpio_control);
6840 val64 &= ~GPIO_CTRL_GPIO_0;
6841 writeq(val64, &bar0->gpio_control);
6842 val64 = readq(&bar0->gpio_control);
1da177e4 6843 }
92c48799
SS		 6844 /* turn off LED */
6845 val64 = readq(&bar0->adapter_control);
d44570e4 6846 val64 = val64 & (~ADAPTER_LED_ON);
92c48799 6847 writeq(val64, &bar0->adapter_control);
19a60522 6848 s2io_link(nic, LINK_DOWN);
1da177e4 6849 }
92b84437 6850 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
22747d6b
FR		 6851
6852out_unlock:
d8d70caf 6853 rtnl_unlock();
1da177e4
LT		 6854}
6855
1ee6dd77 6856static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
d44570e4
JP		 6857 struct buffAdd *ba,
6858 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6859 u64 *temp2, int size)
5d3213cc
AR		 6860{
6861 struct net_device *dev = sp->dev;
491abf25 6862 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
5d3213cc
AR		 6863
6864 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6d517a27 6865 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
5d3213cc
AR		 6866 /* allocate skb */
6867 if (*skb) {
6868 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6869 /*
6870 * As Rx frame are not going to be processed,
6871 * using same mapped address for the Rxd
6872 * buffer pointer
6873 */
6d517a27 6874 rxdp1->Buffer0_ptr = *temp0;
5d3213cc
AR		 6875 } else {
6876 *skb = dev_alloc_skb(size);
6877 if (!(*skb)) {
9e39f7c5
JP		 6878 DBG_PRINT(INFO_DBG,
6879 "%s: Out of memory to allocate %s\n",
6880 dev->name, "1 buf mode SKBs");
ffb5df6c 6881 stats->mem_alloc_fail_cnt++;
5d3213cc
AR		 6882 return -ENOMEM ;
6883 }
ffb5df6c 6884 stats->mem_allocated += (*skb)->truesize;
5d3213cc
AR		 6885 /* storing the mapped addr in a temp variable
6886 * such it will be used for next rxd whose
6887 * Host Control is NULL
6888 */
6d517a27 6889 rxdp1->Buffer0_ptr = *temp0 =
d44570e4
JP		 6890 pci_map_single(sp->pdev, (*skb)->data,
6891 size - NET_IP_ALIGN,
6892 PCI_DMA_FROMDEVICE);
8d8bb39b 6893 if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
491abf25 6894 goto memalloc_failed;
5d3213cc
AR		 6895 rxdp->Host_Control = (unsigned long) (*skb);
6896 }
6897 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6d517a27 6898 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
5d3213cc
AR		 6899 /* Two buffer Mode */
6900 if (*skb) {
6d517a27
VP		 6901 rxdp3->Buffer2_ptr = *temp2;
6902 rxdp3->Buffer0_ptr = *temp0;
6903 rxdp3->Buffer1_ptr = *temp1;
5d3213cc
AR		 6904 } else {
6905 *skb = dev_alloc_skb(size);
2ceaac75 6906 if (!(*skb)) {
9e39f7c5
JP		 6907 DBG_PRINT(INFO_DBG,
6908 "%s: Out of memory to allocate %s\n",
6909 dev->name,
6910 "2 buf mode SKBs");
ffb5df6c 6911 stats->mem_alloc_fail_cnt++;
2ceaac75
DR		 6912 return -ENOMEM;
6913 }
ffb5df6c 6914 stats->mem_allocated += (*skb)->truesize;
6d517a27 6915 rxdp3->Buffer2_ptr = *temp2 =
5d3213cc
AR		 6916 pci_map_single(sp->pdev, (*skb)->data,
6917 dev->mtu + 4,
6918 PCI_DMA_FROMDEVICE);
8d8bb39b 6919 if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
491abf25 6920 goto memalloc_failed;
6d517a27 6921 rxdp3->Buffer0_ptr = *temp0 =
d44570e4
JP		 6922 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6923 PCI_DMA_FROMDEVICE);
8d8bb39b 6924 if (pci_dma_mapping_error(sp->pdev,
d44570e4
JP		 6925 rxdp3->Buffer0_ptr)) {
6926 pci_unmap_single(sp->pdev,
6927 (dma_addr_t)rxdp3->Buffer2_ptr,
6928 dev->mtu + 4,
6929 PCI_DMA_FROMDEVICE);
491abf25
VP		 6930 goto memalloc_failed;
6931 }
5d3213cc
AR		 6932 rxdp->Host_Control = (unsigned long) (*skb);
6933
6934 /* Buffer-1 will be dummy buffer not used */
6d517a27 6935 rxdp3->Buffer1_ptr = *temp1 =
5d3213cc 6936 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
d44570e4 6937 PCI_DMA_FROMDEVICE);
8d8bb39b 6938 if (pci_dma_mapping_error(sp->pdev,
d44570e4
JP		 6939 rxdp3->Buffer1_ptr)) {
6940 pci_unmap_single(sp->pdev,
6941 (dma_addr_t)rxdp3->Buffer0_ptr,
6942 BUF0_LEN, PCI_DMA_FROMDEVICE);
6943 pci_unmap_single(sp->pdev,
6944 (dma_addr_t)rxdp3->Buffer2_ptr,
6945 dev->mtu + 4,
6946 PCI_DMA_FROMDEVICE);
491abf25
VP		 6947 goto memalloc_failed;
6948 }
5d3213cc
AR		 6949 }
6950 }
6951 return 0;
d44570e4
JP		 6952
6953memalloc_failed:
6954 stats->pci_map_fail_cnt++;
6955 stats->mem_freed += (*skb)->truesize;
6956 dev_kfree_skb(*skb);
6957 return -ENOMEM;
5d3213cc 6958}
491abf25 6959
1ee6dd77
RB		 6960static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6961 int size)
5d3213cc
AR		 6962{
6963 struct net_device *dev = sp->dev;
6964 if (sp->rxd_mode == RXD_MODE_1) {
d44570e4 6965 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
5d3213cc
AR		 6966 } else if (sp->rxd_mode == RXD_MODE_3B) {
6967 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6968 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
d44570e4 6969 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu + 4);
5d3213cc
AR		 6970 }
6971}
6972
1ee6dd77 6973static int rxd_owner_bit_reset(struct s2io_nic *sp)
5d3213cc
AR		 6974{
6975 int i, j, k, blk_cnt = 0, size;
5d3213cc 6976 struct config_param *config = &sp->config;
ffb5df6c 6977 struct mac_info *mac_control = &sp->mac_control;
5d3213cc 6978 struct net_device *dev = sp->dev;
1ee6dd77 6979 struct RxD_t *rxdp = NULL;
5d3213cc 6980 struct sk_buff *skb = NULL;
1ee6dd77 6981 struct buffAdd *ba = NULL;
5d3213cc
AR		 6982 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6983
6984 /* Calculate the size based on ring mode */
6985 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6986 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6987 if (sp->rxd_mode == RXD_MODE_1)
6988 size += NET_IP_ALIGN;
6989 else if (sp->rxd_mode == RXD_MODE_3B)
6990 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
5d3213cc
AR		 6991
6992 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 6993 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
6994 struct ring_info *ring = &mac_control->rings[i];
6995
d44570e4 6996 blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] + 1);
5d3213cc
AR		 6997
6998 for (j = 0; j < blk_cnt; j++) {
6999 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
d44570e4
JP		 7000 rxdp = ring->rx_blocks[j].rxds[k].virt_addr;
7001 if (sp->rxd_mode == RXD_MODE_3B)
13d866a9 7002 ba = &ring->ba[j][k];
d44570e4
JP		 7003 if (set_rxd_buffer_pointer(sp, rxdp, ba, &skb,
7004 (u64 *)&temp0_64,
7005 (u64 *)&temp1_64,
7006 (u64 *)&temp2_64,
7007 size) == -ENOMEM) {
ac1f90d6
SS		 7008 return 0;
7009 }
5d3213cc
AR		 7010
7011 set_rxd_buffer_size(sp, rxdp, size);
7012 wmb();
7013 /* flip the Ownership bit to Hardware */
7014 rxdp->Control_1 |= RXD_OWN_XENA;
7015 }
7016 }
7017 }
7018 return 0;
7019
7020}
7021
d44570e4 7022static int s2io_add_isr(struct s2io_nic *sp)
1da177e4 7023{
e6a8fee2 7024 int ret = 0;
c92ca04b 7025 struct net_device *dev = sp->dev;
e6a8fee2 7026 int err = 0;
1da177e4 7027
eaae7f72 7028 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7029 ret = s2io_enable_msi_x(sp);
7030 if (ret) {
7031 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
eaae7f72 7032 sp->config.intr_type = INTA;
20346722 7033 }
1da177e4 7034
d44570e4
JP		 7035 /*
7036 * Store the values of the MSIX table in
7037 * the struct s2io_nic structure
7038 */
e6a8fee2 7039 store_xmsi_data(sp);
c92ca04b 7040
e6a8fee2 7041 /* After proper initialization of H/W, register ISR */
eaae7f72 7042 if (sp->config.intr_type == MSI_X) {
ac731ab6
SH		 7043 int i, msix_rx_cnt = 0;
7044
f61e0a35
SH		 7045 for (i = 0; i < sp->num_entries; i++) {
7046 if (sp->s2io_entries[i].in_use == MSIX_FLG) {
7047 if (sp->s2io_entries[i].type ==
d44570e4 7048 MSIX_RING_TYPE) {
ac731ab6
SH		 7049 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7050 dev->name, i);
7051 err = request_irq(sp->entries[i].vector,
d44570e4
JP		 7052 s2io_msix_ring_handle,
7053 0,
7054 sp->desc[i],
7055 sp->s2io_entries[i].arg);
ac731ab6 7056 } else if (sp->s2io_entries[i].type ==
d44570e4 7057 MSIX_ALARM_TYPE) {
ac731ab6 7058 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
d44570e4 7059 dev->name, i);
ac731ab6 7060 err = request_irq(sp->entries[i].vector,
d44570e4
JP		 7061 s2io_msix_fifo_handle,
7062 0,
7063 sp->desc[i],
7064 sp->s2io_entries[i].arg);
ac731ab6 7065
fb6a825b 7066 }
ac731ab6
SH		 7067 /* if either data or addr is zero print it. */
7068 if (!(sp->msix_info[i].addr &&
d44570e4 7069 sp->msix_info[i].data)) {
ac731ab6 7070 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7071 "%s @Addr:0x%llx Data:0x%llx\n",
7072 sp->desc[i],
7073 (unsigned long long)
7074 sp->msix_info[i].addr,
7075 (unsigned long long)
7076 ntohl(sp->msix_info[i].data));
ac731ab6 7077 } else
fb6a825b 7078 msix_rx_cnt++;
ac731ab6
SH		 7079 if (err) {
7080 remove_msix_isr(sp);
7081
7082 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7083 "%s:MSI-X-%d registration "
7084 "failed\n", dev->name, i);
ac731ab6
SH		 7085
7086 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7087 "%s: Defaulting to INTA\n",
7088 dev->name);
ac731ab6
SH		 7089 sp->config.intr_type = INTA;
7090 break;
fb6a825b 7091 }
ac731ab6
SH		 7092 sp->s2io_entries[i].in_use =
7093 MSIX_REGISTERED_SUCCESS;
c92ca04b 7094 }
e6a8fee2 7095 }
18b2b7bd 7096 if (!err) {
6cef2b8e 7097 pr_info("MSI-X-RX %d entries enabled\n", --msix_rx_cnt);
9e39f7c5
JP		 7098 DBG_PRINT(INFO_DBG,
7099 "MSI-X-TX entries enabled through alarm vector\n");
18b2b7bd 7100 }
e6a8fee2 7101 }
eaae7f72 7102 if (sp->config.intr_type == INTA) {
d44570e4
JP		 7103 err = request_irq((int)sp->pdev->irq, s2io_isr, IRQF_SHARED,
7104 sp->name, dev);
e6a8fee2
AR		 7105 if (err) {
7106 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7107 dev->name);
7108 return -1;
7109 }
7110 }
7111 return 0;
7112}
d44570e4
JP		 7113
7114static void s2io_rem_isr(struct s2io_nic *sp)
e6a8fee2 7115{
18b2b7bd
SH		 7116 if (sp->config.intr_type == MSI_X)
7117 remove_msix_isr(sp);
7118 else
7119 remove_inta_isr(sp);
e6a8fee2
AR		 7120}
7121
d44570e4 7122static void do_s2io_card_down(struct s2io_nic *sp, int do_io)
e6a8fee2
AR		 7123{
7124 int cnt = 0;
1ee6dd77 7125 struct XENA_dev_config __iomem *bar0 = sp->bar0;
e6a8fee2 7126 register u64 val64 = 0;
5f490c96
SH		 7127 struct config_param *config;
7128 config = &sp->config;
e6a8fee2 7129
9f74ffde
SH		 7130 if (!is_s2io_card_up(sp))
7131 return;
7132
e6a8fee2
AR		 7133 del_timer_sync(&sp->alarm_timer);
7134 /* If s2io_set_link task is executing, wait till it completes. */
d44570e4 7135 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state)))
e6a8fee2 7136 msleep(50);
92b84437 7137 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
e6a8fee2 7138
5f490c96 7139 /* Disable napi */
f61e0a35
SH		 7140 if (sp->config.napi) {
7141 int off = 0;
7142 if (config->intr_type == MSI_X) {
7143 for (; off < sp->config.rx_ring_num; off++)
7144 napi_disable(&sp->mac_control.rings[off].napi);
d44570e4 7145 }
f61e0a35
SH		 7146 else
7147 napi_disable(&sp->napi);
7148 }
5f490c96 7149
e6a8fee2 7150 /* disable Tx and Rx traffic on the NIC */
d796fdb7
LV		 7151 if (do_io)
7152 stop_nic(sp);
e6a8fee2
AR		 7153
7154 s2io_rem_isr(sp);
1da177e4 7155
01e16faa
SH		 7156 /* stop the tx queue, indicate link down */
7157 s2io_link(sp, LINK_DOWN);
7158
1da177e4 7159 /* Check if the device is Quiescent and then Reset the NIC */
d44570e4 7160 while (do_io) {
5d3213cc
AR		 7161 /* As per the HW requirement we need to replenish the
7162 * receive buffer to avoid the ring bump. Since there is
7163 * no intention of processing the Rx frame at this pointwe are
70f23fd6 7164 * just setting the ownership bit of rxd in Each Rx
5d3213cc
AR		 7165 * ring to HW and set the appropriate buffer size
7166 * based on the ring mode
7167 */
7168 rxd_owner_bit_reset(sp);
7169
1da177e4 7170 val64 = readq(&bar0->adapter_status);
19a60522 7171 if (verify_xena_quiescence(sp)) {
d44570e4
JP		 7172 if (verify_pcc_quiescent(sp, sp->device_enabled_once))
7173 break;
1da177e4
LT		 7174 }
7175
7176 msleep(50);
7177 cnt++;
7178 if (cnt == 10) {
9e39f7c5
JP		 7179 DBG_PRINT(ERR_DBG, "Device not Quiescent - "
7180 "adapter status reads 0x%llx\n",
d44570e4 7181 (unsigned long long)val64);
1da177e4
LT		 7182 break;
7183 }
d796fdb7
LV		 7184 }
7185 if (do_io)
7186 s2io_reset(sp);
1da177e4 7187
7ba013ac 7188 /* Free all Tx buffers */
1da177e4 7189 free_tx_buffers(sp);
7ba013ac
K		 7190
7191 /* Free all Rx buffers */
1da177e4
LT		 7192 free_rx_buffers(sp);
7193
92b84437 7194 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
1da177e4
LT		 7195}
7196
d44570e4 7197static void s2io_card_down(struct s2io_nic *sp)
d796fdb7
LV		 7198{
7199 do_s2io_card_down(sp, 1);
7200}
7201
d44570e4 7202static int s2io_card_up(struct s2io_nic *sp)
1da177e4 7203{
cc6e7c44 7204 int i, ret = 0;
1da177e4 7205 struct config_param *config;
ffb5df6c 7206 struct mac_info *mac_control;
d44570e4 7207 struct net_device *dev = (struct net_device *)sp->dev;
e6a8fee2 7208 u16 interruptible;
1da177e4
LT		 7209
7210 /* Initialize the H/W I/O registers */
9f74ffde
SH		 7211 ret = init_nic(sp);
7212 if (ret != 0) {
1da177e4
LT		 7213 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7214 dev->name);
9f74ffde
SH		 7215 if (ret != -EIO)
7216 s2io_reset(sp);
7217 return ret;
1da177e4
LT		 7218 }
7219
20346722
K		 7220 /*
7221 * Initializing the Rx buffers. For now we are considering only 1
1da177e4
LT		 7222 * Rx ring and initializing buffers into 30 Rx blocks
7223 */
1da177e4 7224 config = &sp->config;
ffb5df6c 7225 mac_control = &sp->mac_control;
1da177e4
LT		 7226
7227 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7228 struct ring_info *ring = &mac_control->rings[i];
7229
7230 ring->mtu = dev->mtu;
f0c54ace 7231 ring->lro = !!(dev->features & NETIF_F_LRO);
13d866a9 7232 ret = fill_rx_buffers(sp, ring, 1);
0425b46a 7233 if (ret) {
1da177e4
LT		 7234 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7235 dev->name);
7236 s2io_reset(sp);
7237 free_rx_buffers(sp);
7238 return -ENOMEM;
7239 }
7240 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
13d866a9 7241 ring->rx_bufs_left);
1da177e4 7242 }
5f490c96
SH		 7243
7244 /* Initialise napi */
f61e0a35 7245 if (config->napi) {
f61e0a35
SH		 7246 if (config->intr_type == MSI_X) {
7247 for (i = 0; i < sp->config.rx_ring_num; i++)
7248 napi_enable(&sp->mac_control.rings[i].napi);
7249 } else {
7250 napi_enable(&sp->napi);
7251 }
7252 }
5f490c96 7253
19a60522
SS		 7254 /* Maintain the state prior to the open */
7255 if (sp->promisc_flg)
7256 sp->promisc_flg = 0;
7257 if (sp->m_cast_flg) {
7258 sp->m_cast_flg = 0;
d44570e4 7259 sp->all_multi_pos = 0;
19a60522 7260 }
1da177e4
LT		 7261
7262 /* Setting its receive mode */
7263 s2io_set_multicast(dev);
7264
f0c54ace 7265 if (dev->features & NETIF_F_LRO) {
b41477f3 7266 /* Initialize max aggregatable pkts per session based on MTU */
7d3d0439 7267 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
d44570e4 7268 /* Check if we can use (if specified) user provided value */
7d3d0439
RA		 7269 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7270 sp->lro_max_aggr_per_sess = lro_max_pkts;
7271 }
7272
1da177e4
LT		 7273 /* Enable Rx Traffic and interrupts on the NIC */
7274 if (start_nic(sp)) {
7275 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
1da177e4 7276 s2io_reset(sp);
e6a8fee2
AR		 7277 free_rx_buffers(sp);
7278 return -ENODEV;
7279 }
7280
7281 /* Add interrupt service routine */
7282 if (s2io_add_isr(sp) != 0) {
eaae7f72 7283 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7284 s2io_rem_isr(sp);
7285 s2io_reset(sp);
1da177e4
LT		 7286 free_rx_buffers(sp);
7287 return -ENODEV;
7288 }
7289
25fff88e
K		 7290 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7291
01e16faa
SH		 7292 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7293
e6a8fee2 7294 /* Enable select interrupts */
9caab458 7295 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
01e16faa
SH		 7296 if (sp->config.intr_type != INTA) {
7297 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7298 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7299 } else {
e6a8fee2 7300 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 7301 interruptible |= TX_PIC_INTR;
e6a8fee2
AR		 7302 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7303 }
7304
1da177e4
LT		 7305 return 0;
7306}
7307
20346722 7308/**
1da177e4
LT		 7309 * s2io_restart_nic - Resets the NIC.
7310 * @data : long pointer to the device private structure
7311 * Description:
7312 * This function is scheduled to be run by the s2io_tx_watchdog
20346722 7313 * function after 0.5 secs to reset the NIC. The idea is to reduce
1da177e4
LT		 7314 * the run time of the watch dog routine which is run holding a
7315 * spin lock.
7316 */
7317
c4028958 7318static void s2io_restart_nic(struct work_struct *work)
1da177e4 7319{
1ee6dd77 7320 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
c4028958 7321 struct net_device *dev = sp->dev;
1da177e4 7322
22747d6b
FR		 7323 rtnl_lock();
7324
7325 if (!netif_running(dev))
7326 goto out_unlock;
7327
e6a8fee2 7328 s2io_card_down(sp);
1da177e4 7329 if (s2io_card_up(sp)) {
d44570e4 7330 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", dev->name);
1da177e4 7331 }
3a3d5756 7332 s2io_wake_all_tx_queue(sp);
d44570e4 7333 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", dev->name);
22747d6b
FR		 7334out_unlock:
7335 rtnl_unlock();
1da177e4
LT		 7336}
7337
20346722
K		 7338/**
7339 * s2io_tx_watchdog - Watchdog for transmit side.
1da177e4
LT		 7340 * @dev : Pointer to net device structure
7341 * Description:
7342 * This function is triggered if the Tx Queue is stopped
7343 * for a pre-defined amount of time when the Interface is still up.
7344 * If the Interface is jammed in such a situation, the hardware is
7345 * reset (by s2io_close) and restarted again (by s2io_open) to
7346 * overcome any problem that might have been caused in the hardware.
7347 * Return value:
7348 * void
7349 */
7350
7351static void s2io_tx_watchdog(struct net_device *dev)
7352{
4cf1653a 7353 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c 7354 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 7355
7356 if (netif_carrier_ok(dev)) {
ffb5df6c 7357 swstats->watchdog_timer_cnt++;
1da177e4 7358 schedule_work(&sp->rst_timer_task);
ffb5df6c 7359 swstats->soft_reset_cnt++;
1da177e4
LT		 7360 }
7361}
7362
7363/**
7364 * rx_osm_handler - To perform some OS related operations on SKB.
7365 * @sp: private member of the device structure,pointer to s2io_nic structure.
7366 * @skb : the socket buffer pointer.
7367 * @len : length of the packet
7368 * @cksum : FCS checksum of the frame.
7369 * @ring_no : the ring from which this RxD was extracted.
20346722 7370 * Description:
b41477f3 7371 * This function is called by the Rx interrupt serivce routine to perform
1da177e4
LT		 7372 * some OS related operations on the SKB before passing it to the upper
7373 * layers. It mainly checks if the checksum is OK, if so adds it to the
7374 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7375 * to the upper layer. If the checksum is wrong, it increments the Rx
7376 * packet error count, frees the SKB and returns error.
7377 * Return value:
7378 * SUCCESS on success and -1 on failure.
7379 */
1ee6dd77 7380static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
1da177e4 7381{
1ee6dd77 7382 struct s2io_nic *sp = ring_data->nic;
d44570e4 7383 struct net_device *dev = (struct net_device *)ring_data->dev;
20346722 7384 struct sk_buff *skb = (struct sk_buff *)
d44570e4 7385 ((unsigned long)rxdp->Host_Control);
20346722 7386 int ring_no = ring_data->ring_no;
1da177e4 7387 u16 l3_csum, l4_csum;
863c11a9 7388 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
2e6a684b 7389 struct lro *uninitialized_var(lro);
f9046eb3 7390 u8 err_mask;
ffb5df6c 7391 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
da6971d8 7392
20346722 7393 skb->dev = dev;
c92ca04b 7394
863c11a9 7395 if (err) {
bd1034f0 7396 /* Check for parity error */
d44570e4 7397 if (err & 0x1)
ffb5df6c 7398 swstats->parity_err_cnt++;
d44570e4 7399
f9046eb3 7400 err_mask = err >> 48;
d44570e4
JP		 7401 switch (err_mask) {
7402 case 1:
ffb5df6c 7403 swstats->rx_parity_err_cnt++;
491976b2
SH		 7404 break;
7405
d44570e4 7406 case 2:
ffb5df6c 7407 swstats->rx_abort_cnt++;
491976b2
SH		 7408 break;
7409
d44570e4 7410 case 3:
ffb5df6c 7411 swstats->rx_parity_abort_cnt++;
491976b2
SH		 7412 break;
7413
d44570e4 7414 case 4:
ffb5df6c 7415 swstats->rx_rda_fail_cnt++;
491976b2
SH		 7416 break;
7417
d44570e4 7418 case 5:
ffb5df6c 7419 swstats->rx_unkn_prot_cnt++;
491976b2
SH		 7420 break;
7421
d44570e4 7422 case 6:
ffb5df6c 7423 swstats->rx_fcs_err_cnt++;
491976b2 7424 break;
bd1034f0 7425
d44570e4 7426 case 7:
ffb5df6c 7427 swstats->rx_buf_size_err_cnt++;
491976b2
SH		 7428 break;
7429
d44570e4 7430 case 8:
ffb5df6c 7431 swstats->rx_rxd_corrupt_cnt++;
491976b2
SH		 7432 break;
7433
d44570e4 7434 case 15:
ffb5df6c 7435 swstats->rx_unkn_err_cnt++;
491976b2
SH		 7436 break;
7437 }
863c11a9 7438 /*
d44570e4
JP		 7439 * Drop the packet if bad transfer code. Exception being
7440 * 0x5, which could be due to unsupported IPv6 extension header.
7441 * In this case, we let stack handle the packet.
7442 * Note that in this case, since checksum will be incorrect,
7443 * stack will validate the same.
7444 */
f9046eb3
OH		 7445 if (err_mask != 0x5) {
7446 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
d44570e4 7447 dev->name, err_mask);
dc56e634 7448 dev->stats.rx_crc_errors++;
ffb5df6c 7449 swstats->mem_freed
491976b2 7450 += skb->truesize;
863c11a9 7451 dev_kfree_skb(skb);
0425b46a 7452 ring_data->rx_bufs_left -= 1;
863c11a9
AR		 7453 rxdp->Host_Control = 0;
7454 return 0;
7455 }
20346722 7456 }
1da177e4 7457
20346722 7458 rxdp->Host_Control = 0;
da6971d8
AR		 7459 if (sp->rxd_mode == RXD_MODE_1) {
7460 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
20346722 7461
da6971d8 7462 skb_put(skb, len);
6d517a27 7463 } else if (sp->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 7464 int get_block = ring_data->rx_curr_get_info.block_index;
7465 int get_off = ring_data->rx_curr_get_info.offset;
7466 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7467 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7468 unsigned char *buff = skb_push(skb, buf0_len);
7469
1ee6dd77 7470 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
da6971d8 7471 memcpy(buff, ba->ba_0, buf0_len);
6d517a27 7472 skb_put(skb, buf2_len);
da6971d8 7473 }
20346722 7474
d44570e4
JP		 7475 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
7476 ((!ring_data->lro) ||
7477 (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
b437a8cc 7478 (dev->features & NETIF_F_RXCSUM)) {
20346722 7479 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
1da177e4
LT		 7480 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7481 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
20346722 7482 /*
1da177e4
LT		 7483 * NIC verifies if the Checksum of the received
7484 * frame is Ok or not and accordingly returns
7485 * a flag in the RxD.
7486 */
7487 skb->ip_summed = CHECKSUM_UNNECESSARY;
0425b46a 7488 if (ring_data->lro) {
06f0c139 7489 u32 tcp_len = 0;
7d3d0439
RA		 7490 u8 *tcp;
7491 int ret = 0;
7492
0425b46a 7493 ret = s2io_club_tcp_session(ring_data,
d44570e4
JP		 7494 skb->data, &tcp,
7495 &tcp_len, &lro,
7496 rxdp, sp);
7d3d0439 7497 switch (ret) {
d44570e4
JP		 7498 case 3: /* Begin anew */
7499 lro->parent = skb;
7500 goto aggregate;
7501 case 1: /* Aggregate */
7502 lro_append_pkt(sp, lro, skb, tcp_len);
7503 goto aggregate;
7504 case 4: /* Flush session */
7505 lro_append_pkt(sp, lro, skb, tcp_len);
7506 queue_rx_frame(lro->parent,
7507 lro->vlan_tag);
7508 clear_lro_session(lro);
ffb5df6c 7509 swstats->flush_max_pkts++;
d44570e4
JP		 7510 goto aggregate;
7511 case 2: /* Flush both */
7512 lro->parent->data_len = lro->frags_len;
ffb5df6c 7513 swstats->sending_both++;
d44570e4
JP		 7514 queue_rx_frame(lro->parent,
7515 lro->vlan_tag);
7516 clear_lro_session(lro);
7517 goto send_up;
7518 case 0: /* sessions exceeded */
7519 case -1: /* non-TCP or not L2 aggregatable */
7520 case 5: /*
7521 * First pkt in session not
7522 * L3/L4 aggregatable
7523 */
7524 break;
7525 default:
7526 DBG_PRINT(ERR_DBG,
7527 "%s: Samadhana!!\n",
7528 __func__);
7529 BUG();
7d3d0439
RA		 7530 }
7531 }
1da177e4 7532 } else {
20346722
K		 7533 /*
7534 * Packet with erroneous checksum, let the
1da177e4
LT		 7535 * upper layers deal with it.
7536 */
bc8acf2c 7537 skb_checksum_none_assert(skb);
1da177e4 7538 }
cdb5bf02 7539 } else
bc8acf2c 7540 skb_checksum_none_assert(skb);
cdb5bf02 7541
ffb5df6c 7542 swstats->mem_freed += skb->truesize;
7d3d0439 7543send_up:
0c8dfc83 7544 skb_record_rx_queue(skb, ring_no);
cdb5bf02 7545 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7d3d0439 7546aggregate:
0425b46a 7547 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
1da177e4
LT		 7548 return SUCCESS;
7549}
7550
7551/**
7552 * s2io_link - stops/starts the Tx queue.
7553 * @sp : private member of the device structure, which is a pointer to the
7554 * s2io_nic structure.
7555 * @link : inidicates whether link is UP/DOWN.
7556 * Description:
7557 * This function stops/starts the Tx queue depending on whether the link
20346722
K		 7558 * status of the NIC is is down or up. This is called by the Alarm
7559 * interrupt handler whenever a link change interrupt comes up.
1da177e4
LT		 7560 * Return value:
7561 * void.
7562 */
7563
d44570e4 7564static void s2io_link(struct s2io_nic *sp, int link)
1da177e4 7565{
d44570e4 7566 struct net_device *dev = (struct net_device *)sp->dev;
ffb5df6c 7567 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 7568
7569 if (link != sp->last_link_state) {
b7c5678f 7570 init_tti(sp, link);
1da177e4
LT		 7571 if (link == LINK_DOWN) {
7572 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
3a3d5756 7573 s2io_stop_all_tx_queue(sp);
1da177e4 7574 netif_carrier_off(dev);
ffb5df6c
JP		 7575 if (swstats->link_up_cnt)
7576 swstats->link_up_time =
7577 jiffies - sp->start_time;
7578 swstats->link_down_cnt++;
1da177e4
LT		 7579 } else {
7580 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
ffb5df6c
JP		 7581 if (swstats->link_down_cnt)
7582 swstats->link_down_time =
d44570e4 7583 jiffies - sp->start_time;
ffb5df6c 7584 swstats->link_up_cnt++;
1da177e4 7585 netif_carrier_on(dev);
3a3d5756 7586 s2io_wake_all_tx_queue(sp);
1da177e4
LT		 7587 }
7588 }
7589 sp->last_link_state = link;
491976b2 7590 sp->start_time = jiffies;
1da177e4
LT		 7591}
7592
20346722
K		 7593/**
7594 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7595 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 7596 * s2io_nic structure.
7597 * Description:
7598 * This function initializes a few of the PCI and PCI-X configuration registers
7599 * with recommended values.
7600 * Return value:
7601 * void
7602 */
7603
d44570e4 7604static void s2io_init_pci(struct s2io_nic *sp)
1da177e4 7605{
20346722 7606 u16 pci_cmd = 0, pcix_cmd = 0;
1da177e4
LT		 7607
7608 /* Enable Data Parity Error Recovery in PCI-X command register. */
7609 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7610 &(pcix_cmd));
1da177e4 7611 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7612 (pcix_cmd | 1));
1da177e4 7613 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7614 &(pcix_cmd));
1da177e4
LT		 7615
7616 /* Set the PErr Response bit in PCI command register. */
7617 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7618 pci_write_config_word(sp->pdev, PCI_COMMAND,
7619 (pci_cmd | PCI_COMMAND_PARITY));
7620 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
1da177e4
LT		 7621}
7622
3a3d5756 7623static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
d44570e4 7624 u8 *dev_multiq)
9dc737a7 7625{
1853e2e1
JM		 7626 int i;
7627
d44570e4 7628 if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) {
9e39f7c5 7629 DBG_PRINT(ERR_DBG, "Requested number of tx fifos "
d44570e4 7630 "(%d) not supported\n", tx_fifo_num);
6cfc482b
SH		 7631
7632 if (tx_fifo_num < 1)
7633 tx_fifo_num = 1;
7634 else
7635 tx_fifo_num = MAX_TX_FIFOS;
7636
9e39f7c5 7637 DBG_PRINT(ERR_DBG, "Default to %d tx fifos\n", tx_fifo_num);
9dc737a7 7638 }
2fda096d 7639
6cfc482b 7640 if (multiq)
3a3d5756 7641 *dev_multiq = multiq;
6cfc482b
SH		 7642
7643 if (tx_steering_type && (1 == tx_fifo_num)) {
7644 if (tx_steering_type != TX_DEFAULT_STEERING)
7645 DBG_PRINT(ERR_DBG,
9e39f7c5 7646 "Tx steering is not supported with "
d44570e4 7647 "one fifo. Disabling Tx steering.\n");
6cfc482b
SH		 7648 tx_steering_type = NO_STEERING;
7649 }
7650
7651 if ((tx_steering_type < NO_STEERING) ||
d44570e4
JP		 7652 (tx_steering_type > TX_DEFAULT_STEERING)) {
7653 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 7654 "Requested transmit steering not supported\n");
7655 DBG_PRINT(ERR_DBG, "Disabling transmit steering\n");
6cfc482b 7656 tx_steering_type = NO_STEERING;
3a3d5756
SH		 7657 }
7658
0425b46a 7659 if (rx_ring_num > MAX_RX_RINGS) {
d44570e4 7660 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 7661 "Requested number of rx rings not supported\n");
7662 DBG_PRINT(ERR_DBG, "Default to %d rx rings\n",
d44570e4 7663 MAX_RX_RINGS);
0425b46a 7664 rx_ring_num = MAX_RX_RINGS;
9dc737a7 7665 }
0425b46a 7666
eccb8628 7667 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
9e39f7c5 7668 DBG_PRINT(ERR_DBG, "Wrong intr_type requested. "
9dc737a7
AR		 7669 "Defaulting to INTA\n");
7670 *dev_intr_type = INTA;
7671 }
596c5c97 7672
9dc737a7 7673 if ((*dev_intr_type == MSI_X) &&
d44570e4
JP		 7674 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7675 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
9e39f7c5 7676 DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. "
d44570e4 7677 "Defaulting to INTA\n");
9dc737a7
AR		 7678 *dev_intr_type = INTA;
7679 }
fb6a825b 7680
6d517a27 7681 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
9e39f7c5
JP		 7682 DBG_PRINT(ERR_DBG, "Requested ring mode not supported\n");
7683 DBG_PRINT(ERR_DBG, "Defaulting to 1-buffer mode\n");
6d517a27 7684 rx_ring_mode = 1;
9dc737a7 7685 }
1853e2e1
JM		 7686
7687 for (i = 0; i < MAX_RX_RINGS; i++)
7688 if (rx_ring_sz[i] > MAX_RX_BLOCKS_PER_RING) {
7689 DBG_PRINT(ERR_DBG, "Requested rx ring size not "
7690 "supported\nDefaulting to %d\n",
7691 MAX_RX_BLOCKS_PER_RING);
7692 rx_ring_sz[i] = MAX_RX_BLOCKS_PER_RING;
7693 }
7694
9dc737a7
AR		 7695 return SUCCESS;
7696}
7697
9fc93a41
SS		 7698/**
7699 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7700 * or Traffic class respectively.
b7c5678f 7701 * @nic: device private variable
9fc93a41
SS		 7702 * Description: The function configures the receive steering to
7703 * desired receive ring.
7704 * Return Value: SUCCESS on success and
7705 * '-1' on failure (endian settings incorrect).
7706 */
7707static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7708{
7709 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7710 register u64 val64 = 0;
7711
7712 if (ds_codepoint > 63)
7713 return FAILURE;
7714
7715 val64 = RTS_DS_MEM_DATA(ring);
7716 writeq(val64, &bar0->rts_ds_mem_data);
7717
7718 val64 = RTS_DS_MEM_CTRL_WE |
7719 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7720 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7721
7722 writeq(val64, &bar0->rts_ds_mem_ctrl);
7723
7724 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
d44570e4
JP		 7725 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7726 S2IO_BIT_RESET);
9fc93a41
SS		 7727}
7728
04025095
SH		 7729static const struct net_device_ops s2io_netdev_ops = {
7730 .ndo_open = s2io_open,
7731 .ndo_stop = s2io_close,
7732 .ndo_get_stats = s2io_get_stats,
7733 .ndo_start_xmit = s2io_xmit,
7734 .ndo_validate_addr = eth_validate_addr,
7735 .ndo_set_multicast_list = s2io_set_multicast,
7736 .ndo_do_ioctl = s2io_ioctl,
7737 .ndo_set_mac_address = s2io_set_mac_addr,
7738 .ndo_change_mtu = s2io_change_mtu,
b437a8cc 7739 .ndo_set_features = s2io_set_features,
04025095
SH		 7740 .ndo_vlan_rx_register = s2io_vlan_rx_register,
7741 .ndo_vlan_rx_kill_vid = s2io_vlan_rx_kill_vid,
7742 .ndo_tx_timeout = s2io_tx_watchdog,
7743#ifdef CONFIG_NET_POLL_CONTROLLER
7744 .ndo_poll_controller = s2io_netpoll,
7745#endif
7746};
7747
1da177e4 7748/**
20346722 7749 * s2io_init_nic - Initialization of the adapter .
1da177e4
LT		 7750 * @pdev : structure containing the PCI related information of the device.
7751 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7752 * Description:
7753 * The function initializes an adapter identified by the pci_dec structure.
20346722
K		 7754 * All OS related initialization including memory and device structure and
7755 * initlaization of the device private variable is done. Also the swapper
7756 * control register is initialized to enable read and write into the I/O
1da177e4
LT		 7757 * registers of the device.
7758 * Return value:
7759 * returns 0 on success and negative on failure.
7760 */
7761
7762static int __devinit
7763s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7764{
1ee6dd77 7765 struct s2io_nic *sp;
1da177e4 7766 struct net_device *dev;
1da177e4 7767 int i, j, ret;
f957bcf0 7768 int dma_flag = false;
1da177e4
LT		 7769 u32 mac_up, mac_down;
7770 u64 val64 = 0, tmp64 = 0;
1ee6dd77 7771 struct XENA_dev_config __iomem *bar0 = NULL;
1da177e4 7772 u16 subid;
1da177e4 7773 struct config_param *config;
ffb5df6c 7774 struct mac_info *mac_control;
541ae68f 7775 int mode;
cc6e7c44 7776 u8 dev_intr_type = intr_type;
3a3d5756 7777 u8 dev_multiq = 0;
1da177e4 7778
3a3d5756
SH		 7779 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7780 if (ret)
9dc737a7 7781 return ret;
1da177e4 7782
d44570e4
JP		 7783 ret = pci_enable_device(pdev);
7784 if (ret) {
1da177e4 7785 DBG_PRINT(ERR_DBG,
9e39f7c5 7786 "%s: pci_enable_device failed\n", __func__);
1da177e4
LT		 7787 return ret;
7788 }
7789
6a35528a 7790 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
9e39f7c5 7791 DBG_PRINT(INIT_DBG, "%s: Using 64bit DMA\n", __func__);
f957bcf0 7792 dma_flag = true;
d44570e4 7793 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4 7794 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7795 "Unable to obtain 64bit DMA "
7796 "for consistent allocations\n");
1da177e4
LT		 7797 pci_disable_device(pdev);
7798 return -ENOMEM;
7799 }
284901a9 7800 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
9e39f7c5 7801 DBG_PRINT(INIT_DBG, "%s: Using 32bit DMA\n", __func__);
1da177e4
LT		 7802 } else {
7803 pci_disable_device(pdev);
7804 return -ENOMEM;
7805 }
d44570e4
JP		 7806 ret = pci_request_regions(pdev, s2io_driver_name);
7807 if (ret) {
9e39f7c5 7808 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x\n",
d44570e4 7809 __func__, ret);
eccb8628
VP		 7810 pci_disable_device(pdev);
7811 return -ENODEV;
1da177e4 7812 }
3a3d5756 7813 if (dev_multiq)
6cfc482b 7814 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
3a3d5756 7815 else
b19fa1fa 7816 dev = alloc_etherdev(sizeof(struct s2io_nic));
1da177e4
LT		 7817 if (dev == NULL) {
7818 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7819 pci_disable_device(pdev);
7820 pci_release_regions(pdev);
7821 return -ENODEV;
7822 }
7823
7824 pci_set_master(pdev);
7825 pci_set_drvdata(pdev, dev);
1da177e4
LT		 7826 SET_NETDEV_DEV(dev, &pdev->dev);
7827
7828 /* Private member variable initialized to s2io NIC structure */
4cf1653a 7829 sp = netdev_priv(dev);
1da177e4
LT		 7830 sp->dev = dev;
7831 sp->pdev = pdev;
1da177e4 7832 sp->high_dma_flag = dma_flag;
f957bcf0 7833 sp->device_enabled_once = false;
da6971d8
AR		 7834 if (rx_ring_mode == 1)
7835 sp->rxd_mode = RXD_MODE_1;
7836 if (rx_ring_mode == 2)
7837 sp->rxd_mode = RXD_MODE_3B;
da6971d8 7838
eaae7f72 7839 sp->config.intr_type = dev_intr_type;
1da177e4 7840
541ae68f 7841 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
d44570e4 7842 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
541ae68f
K		 7843 sp->device_type = XFRAME_II_DEVICE;
7844 else
7845 sp->device_type = XFRAME_I_DEVICE;
7846
6aa20a22 7847
1da177e4
LT		 7848 /* Initialize some PCI/PCI-X fields of the NIC. */
7849 s2io_init_pci(sp);
7850
20346722 7851 /*
1da177e4 7852 * Setting the device configuration parameters.
20346722
K		 7853 * Most of these parameters can be specified by the user during
7854 * module insertion as they are module loadable parameters. If
7855 * these parameters are not not specified during load time, they
1da177e4
LT		 7856 * are initialized with default values.
7857 */
1da177e4 7858 config = &sp->config;
ffb5df6c 7859 mac_control = &sp->mac_control;
1da177e4 7860
596c5c97 7861 config->napi = napi;
6cfc482b 7862 config->tx_steering_type = tx_steering_type;
596c5c97 7863
1da177e4 7864 /* Tx side parameters. */
6cfc482b
SH		 7865 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7866 config->tx_fifo_num = MAX_TX_FIFOS;
7867 else
7868 config->tx_fifo_num = tx_fifo_num;
7869
7870 /* Initialize the fifos used for tx steering */
7871 if (config->tx_fifo_num < 5) {
d44570e4
JP		 7872 if (config->tx_fifo_num == 1)
7873 sp->total_tcp_fifos = 1;
7874 else
7875 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7876 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7877 sp->total_udp_fifos = 1;
7878 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
6cfc482b
SH		 7879 } else {
7880 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
d44570e4 7881 FIFO_OTHER_MAX_NUM);
6cfc482b
SH		 7882 sp->udp_fifo_idx = sp->total_tcp_fifos;
7883 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7884 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7885 }
7886
3a3d5756 7887 config->multiq = dev_multiq;
6cfc482b 7888 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 7889 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7890
7891 tx_cfg->fifo_len = tx_fifo_len[i];
7892 tx_cfg->fifo_priority = i;
1da177e4
LT		 7893 }
7894
20346722
K		 7895 /* mapping the QoS priority to the configured fifos */
7896 for (i = 0; i < MAX_TX_FIFOS; i++)
3a3d5756 7897 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
20346722 7898
6cfc482b
SH		 7899 /* map the hashing selector table to the configured fifos */
7900 for (i = 0; i < config->tx_fifo_num; i++)
7901 sp->fifo_selector[i] = fifo_selector[i];
7902
7903
1da177e4
LT		 7904 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7905 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 7906 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7907
7908 tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7909 if (tx_cfg->fifo_len < 65) {
1da177e4
LT		 7910 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7911 break;
7912 }
7913 }
fed5eccd
AR		 7914 /* + 2 because one Txd for skb->data and one Txd for UFO */
7915 config->max_txds = MAX_SKB_FRAGS + 2;
1da177e4
LT		 7916
7917 /* Rx side parameters. */
1da177e4 7918 config->rx_ring_num = rx_ring_num;
0425b46a 7919 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7920 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7921 struct ring_info *ring = &mac_control->rings[i];
7922
7923 rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
7924 rx_cfg->ring_priority = i;
7925 ring->rx_bufs_left = 0;
7926 ring->rxd_mode = sp->rxd_mode;
7927 ring->rxd_count = rxd_count[sp->rxd_mode];
7928 ring->pdev = sp->pdev;
7929 ring->dev = sp->dev;
1da177e4
LT		 7930 }
7931
7932 for (i = 0; i < rx_ring_num; i++) {
13d866a9
JP		 7933 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7934
7935 rx_cfg->ring_org = RING_ORG_BUFF1;
7936 rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
1da177e4
LT		 7937 }
7938
7939 /* Setting Mac Control parameters */
7940 mac_control->rmac_pause_time = rmac_pause_time;
7941 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7942 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7943
7944
1da177e4
LT		 7945 /* initialize the shared memory used by the NIC and the host */
7946 if (init_shared_mem(sp)) {
d44570e4 7947 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", dev->name);
1da177e4
LT		 7948 ret = -ENOMEM;
7949 goto mem_alloc_failed;
7950 }
7951
275f165f 7952 sp->bar0 = pci_ioremap_bar(pdev, 0);
1da177e4 7953 if (!sp->bar0) {
19a60522 7954 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
1da177e4
LT		 7955 dev->name);
7956 ret = -ENOMEM;
7957 goto bar0_remap_failed;
7958 }
7959
275f165f 7960 sp->bar1 = pci_ioremap_bar(pdev, 2);
1da177e4 7961 if (!sp->bar1) {
19a60522 7962 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
1da177e4
LT		 7963 dev->name);
7964 ret = -ENOMEM;
7965 goto bar1_remap_failed;
7966 }
7967
7968 dev->irq = pdev->irq;
d44570e4 7969 dev->base_addr = (unsigned long)sp->bar0;
1da177e4
LT		 7970
7971 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7972 for (j = 0; j < MAX_TX_FIFOS; j++) {
43d620c8 7973 mac_control->tx_FIFO_start[j] = sp->bar1 + (j * 0x00020000);
1da177e4
LT		 7974 }
7975
7976 /* Driver entry points */
04025095 7977 dev->netdev_ops = &s2io_netdev_ops;
1da177e4 7978 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
b437a8cc
MM		 7979 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
7980 NETIF_F_TSO | NETIF_F_TSO6 |
7981 NETIF_F_RXCSUM | NETIF_F_LRO;
7982 dev->features |= dev->hw_features |
7983 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7984 if (sp->device_type & XFRAME_II_DEVICE) {
7985 dev->hw_features |= NETIF_F_UFO;
7986 if (ufo)
7987 dev->features |= NETIF_F_UFO;
7988 }
f957bcf0 7989 if (sp->high_dma_flag == true)
1da177e4 7990 dev->features |= NETIF_F_HIGHDMA;
1da177e4 7991 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
c4028958
DH		 7992 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7993 INIT_WORK(&sp->set_link_task, s2io_set_link);
1da177e4 7994
e960fc5c 7995 pci_save_state(sp->pdev);
1da177e4
LT		 7996
7997 /* Setting swapper control on the NIC, for proper reset operation */
7998 if (s2io_set_swapper(sp)) {
9e39f7c5 7999 DBG_PRINT(ERR_DBG, "%s: swapper settings are wrong\n",
1da177e4
LT		 8000 dev->name);
8001 ret = -EAGAIN;
8002 goto set_swap_failed;
8003 }
8004
541ae68f
K		 8005 /* Verify if the Herc works on the slot its placed into */
8006 if (sp->device_type & XFRAME_II_DEVICE) {
8007 mode = s2io_verify_pci_mode(sp);
8008 if (mode < 0) {
9e39f7c5
JP		 8009 DBG_PRINT(ERR_DBG, "%s: Unsupported PCI bus mode\n",
8010 __func__);
541ae68f
K		 8011 ret = -EBADSLT;
8012 goto set_swap_failed;
8013 }
8014 }
8015
f61e0a35
SH		 8016 if (sp->config.intr_type == MSI_X) {
8017 sp->num_entries = config->rx_ring_num + 1;
8018 ret = s2io_enable_msi_x(sp);
8019
8020 if (!ret) {
8021 ret = s2io_test_msi(sp);
8022 /* rollback MSI-X, will re-enable during add_isr() */
8023 remove_msix_isr(sp);
8024 }
8025 if (ret) {
8026
8027 DBG_PRINT(ERR_DBG,
9e39f7c5 8028 "MSI-X requested but failed to enable\n");
f61e0a35
SH		 8029 sp->config.intr_type = INTA;
8030 }
8031 }
8032
8033 if (config->intr_type == MSI_X) {
13d866a9
JP		 8034 for (i = 0; i < config->rx_ring_num ; i++) {
8035 struct ring_info *ring = &mac_control->rings[i];
8036
8037 netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64);
8038 }
f61e0a35
SH		 8039 } else {
8040 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
8041 }
8042
541ae68f
K		 8043 /* Not needed for Herc */
8044 if (sp->device_type & XFRAME_I_DEVICE) {
8045 /*
8046 * Fix for all "FFs" MAC address problems observed on
8047 * Alpha platforms
8048 */
8049 fix_mac_address(sp);
8050 s2io_reset(sp);
8051 }
1da177e4
LT		 8052
8053 /*
1da177e4
LT		 8054 * MAC address initialization.
8055 * For now only one mac address will be read and used.
8056 */
8057 bar0 = sp->bar0;
8058 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
d44570e4 8059 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
1da177e4 8060 writeq(val64, &bar0->rmac_addr_cmd_mem);
c92ca04b 8061 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 8062 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
8063 S2IO_BIT_RESET);
1da177e4 8064 tmp64 = readq(&bar0->rmac_addr_data0_mem);
d44570e4 8065 mac_down = (u32)tmp64;
1da177e4
LT		 8066 mac_up = (u32) (tmp64 >> 32);
8067
1da177e4
LT		 8068 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8069 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8070 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8071 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8072 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8073 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8074
1da177e4
LT		 8075 /* Set the factory defined MAC address initially */
8076 dev->addr_len = ETH_ALEN;
8077 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
2fd37688 8078 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
1da177e4 8079
faa4f796
SH		 8080 /* initialize number of multicast & unicast MAC entries variables */
8081 if (sp->device_type == XFRAME_I_DEVICE) {
8082 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8083 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8084 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8085 } else if (sp->device_type == XFRAME_II_DEVICE) {
8086 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8087 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8088 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8089 }
8090
8091 /* store mac addresses from CAM to s2io_nic structure */
8092 do_s2io_store_unicast_mc(sp);
8093
f61e0a35
SH		 8094 /* Configure MSIX vector for number of rings configured plus one */
8095 if ((sp->device_type == XFRAME_II_DEVICE) &&
d44570e4 8096 (config->intr_type == MSI_X))
f61e0a35
SH		 8097 sp->num_entries = config->rx_ring_num + 1;
8098
d44570e4 8099 /* Store the values of the MSIX table in the s2io_nic structure */
c77dd43e 8100 store_xmsi_data(sp);
b41477f3
AR		 8101 /* reset Nic and bring it to known state */
8102 s2io_reset(sp);
8103
1da177e4 8104 /*
99993af6 8105 * Initialize link state flags
541ae68f 8106 * and the card state parameter
1da177e4 8107 */
92b84437 8108 sp->state = 0;
1da177e4 8109
1da177e4 8110 /* Initialize spinlocks */
13d866a9
JP		 8111 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8112 struct fifo_info *fifo = &mac_control->fifos[i];
8113
8114 spin_lock_init(&fifo->tx_lock);
8115 }
db874e65 8116
20346722
K		 8117 /*
8118 * SXE-002: Configure link and activity LED to init state
8119 * on driver load.
1da177e4
LT		 8120 */
8121 subid = sp->pdev->subsystem_device;
8122 if ((subid & 0xFF) >= 0x07) {
8123 val64 = readq(&bar0->gpio_control);
8124 val64 |= 0x0000800000000000ULL;
8125 writeq(val64, &bar0->gpio_control);
8126 val64 = 0x0411040400000000ULL;
d44570e4 8127 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 8128 val64 = readq(&bar0->gpio_control);
8129 }
8130
8131 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8132
8133 if (register_netdev(dev)) {
8134 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8135 ret = -ENODEV;
8136 goto register_failed;
8137 }
9dc737a7 8138 s2io_vpd_read(sp);
926bd900 8139 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2010 Exar Corp.\n");
d44570e4 8140 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name,
44c10138 8141 sp->product_name, pdev->revision);
b41477f3
AR		 8142 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8143 s2io_driver_version);
9e39f7c5
JP		 8144 DBG_PRINT(ERR_DBG, "%s: MAC Address: %pM\n", dev->name, dev->dev_addr);
8145 DBG_PRINT(ERR_DBG, "Serial number: %s\n", sp->serial_num);
9dc737a7 8146 if (sp->device_type & XFRAME_II_DEVICE) {
0b1f7ebe 8147 mode = s2io_print_pci_mode(sp);
541ae68f 8148 if (mode < 0) {
541ae68f 8149 ret = -EBADSLT;
9dc737a7 8150 unregister_netdev(dev);
541ae68f
K		 8151 goto set_swap_failed;
8152 }
541ae68f 8153 }
d44570e4
JP		 8154 switch (sp->rxd_mode) {
8155 case RXD_MODE_1:
8156 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8157 dev->name);
8158 break;
8159 case RXD_MODE_3B:
8160 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8161 dev->name);
8162 break;
9dc737a7 8163 }
db874e65 8164
f61e0a35
SH		 8165 switch (sp->config.napi) {
8166 case 0:
8167 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8168 break;
8169 case 1:
db874e65 8170 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
f61e0a35
SH		 8171 break;
8172 }
3a3d5756
SH		 8173
8174 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
d44570e4 8175 sp->config.tx_fifo_num);
3a3d5756 8176
0425b46a
SH		 8177 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8178 sp->config.rx_ring_num);
8179
d44570e4
JP		 8180 switch (sp->config.intr_type) {
8181 case INTA:
8182 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8183 break;
8184 case MSI_X:
8185 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8186 break;
9dc737a7 8187 }
3a3d5756 8188 if (sp->config.multiq) {
13d866a9
JP		 8189 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8190 struct fifo_info *fifo = &mac_control->fifos[i];
8191
8192 fifo->multiq = config->multiq;
8193 }
3a3d5756 8194 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
d44570e4 8195 dev->name);
3a3d5756
SH		 8196 } else
8197 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
d44570e4 8198 dev->name);
3a3d5756 8199
6cfc482b
SH		 8200 switch (sp->config.tx_steering_type) {
8201 case NO_STEERING:
d44570e4
JP		 8202 DBG_PRINT(ERR_DBG, "%s: No steering enabled for transmit\n",
8203 dev->name);
8204 break;
6cfc482b 8205 case TX_PRIORITY_STEERING:
d44570e4
JP		 8206 DBG_PRINT(ERR_DBG,
8207 "%s: Priority steering enabled for transmit\n",
8208 dev->name);
6cfc482b
SH		 8209 break;
8210 case TX_DEFAULT_STEERING:
d44570e4
JP		 8211 DBG_PRINT(ERR_DBG,
8212 "%s: Default steering enabled for transmit\n",
8213 dev->name);
6cfc482b
SH		 8214 }
8215
f0c54ace
AW		 8216 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
8217 dev->name);
db874e65 8218 if (ufo)
d44570e4
JP		 8219 DBG_PRINT(ERR_DBG,
8220 "%s: UDP Fragmentation Offload(UFO) enabled\n",
8221 dev->name);
7ba013ac 8222 /* Initialize device name */
9dc737a7 8223 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7ba013ac 8224
cd0fce03
BL		 8225 if (vlan_tag_strip)
8226 sp->vlan_strip_flag = 1;
8227 else
8228 sp->vlan_strip_flag = 0;
8229
20346722
K		 8230 /*
8231 * Make Link state as off at this point, when the Link change
8232 * interrupt comes the state will be automatically changed to
1da177e4
LT		 8233 * the right state.
8234 */
8235 netif_carrier_off(dev);
1da177e4
LT		 8236
8237 return 0;
8238
d44570e4
JP		 8239register_failed:
8240set_swap_failed:
1da177e4 8241 iounmap(sp->bar1);
d44570e4 8242bar1_remap_failed:
1da177e4 8243 iounmap(sp->bar0);
d44570e4
JP		 8244bar0_remap_failed:
8245mem_alloc_failed:
1da177e4
LT		 8246 free_shared_mem(sp);
8247 pci_disable_device(pdev);
eccb8628 8248 pci_release_regions(pdev);
1da177e4
LT		 8249 pci_set_drvdata(pdev, NULL);
8250 free_netdev(dev);
8251
8252 return ret;
8253}
8254
8255/**
20346722 8256 * s2io_rem_nic - Free the PCI device
1da177e4 8257 * @pdev: structure containing the PCI related information of the device.
20346722 8258 * Description: This function is called by the Pci subsystem to release a
1da177e4 8259 * PCI device and free up all resource held up by the device. This could
20346722 8260 * be in response to a Hot plug event or when the driver is to be removed
1da177e4
LT		 8261 * from memory.
8262 */
8263
8264static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8265{
a31ff388 8266 struct net_device *dev = pci_get_drvdata(pdev);
1ee6dd77 8267 struct s2io_nic *sp;
1da177e4
LT		 8268
8269 if (dev == NULL) {
8270 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8271 return;
8272 }
8273
4cf1653a 8274 sp = netdev_priv(dev);
23f333a2
TH		 8275
8276 cancel_work_sync(&sp->rst_timer_task);
8277 cancel_work_sync(&sp->set_link_task);
8278
1da177e4
LT		 8279 unregister_netdev(dev);
8280
8281 free_shared_mem(sp);
8282 iounmap(sp->bar0);
8283 iounmap(sp->bar1);
eccb8628 8284 pci_release_regions(pdev);
1da177e4 8285 pci_set_drvdata(pdev, NULL);
1da177e4 8286 free_netdev(dev);
19a60522 8287 pci_disable_device(pdev);
1da177e4
LT		 8288}
8289
8290/**
8291 * s2io_starter - Entry point for the driver
8292 * Description: This function is the entry point for the driver. It verifies
8293 * the module loadable parameters and initializes PCI configuration space.
8294 */
8295
43b7c451 8296static int __init s2io_starter(void)
1da177e4 8297{
29917620 8298 return pci_register_driver(&s2io_driver);
1da177e4
LT		 8299}
8300
8301/**
20346722 8302 * s2io_closer - Cleanup routine for the driver
1da177e4
LT		 8303 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8304 */
8305
372cc597 8306static __exit void s2io_closer(void)
1da177e4
LT		 8307{
8308 pci_unregister_driver(&s2io_driver);
8309 DBG_PRINT(INIT_DBG, "cleanup done\n");
8310}
8311
8312module_init(s2io_starter);
8313module_exit(s2io_closer);
7d3d0439 8314
6aa20a22 8315static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
d44570e4
JP		 8316 struct tcphdr **tcp, struct RxD_t *rxdp,
8317 struct s2io_nic *sp)
7d3d0439
RA		 8318{
8319 int ip_off;
8320 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8321
8322 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
d44570e4
JP		 8323 DBG_PRINT(INIT_DBG,
8324 "%s: Non-TCP frames not supported for LRO\n",
b39d66a8 8325 __func__);
7d3d0439
RA		 8326 return -1;
8327 }
8328
cdb5bf02 8329 /* Checking for DIX type or DIX type with VLAN */
d44570e4 8330 if ((l2_type == 0) || (l2_type == 4)) {
cdb5bf02
SH		 8331 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8332 /*
8333 * If vlan stripping is disabled and the frame is VLAN tagged,
8334 * shift the offset by the VLAN header size bytes.
8335 */
cd0fce03 8336 if ((!sp->vlan_strip_flag) &&
d44570e4 8337 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
cdb5bf02
SH		 8338 ip_off += HEADER_VLAN_SIZE;
8339 } else {
7d3d0439 8340 /* LLC, SNAP etc are considered non-mergeable */
cdb5bf02 8341 return -1;
7d3d0439
RA		 8342 }
8343
8344 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8345 ip_len = (u8)((*ip)->ihl);
8346 ip_len <<= 2;
8347 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8348
8349 return 0;
8350}
8351
1ee6dd77 8352static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 8353 struct tcphdr *tcp)
8354{
d44570e4
JP		 8355 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8356 if ((lro->iph->saddr != ip->saddr) ||
8357 (lro->iph->daddr != ip->daddr) ||
8358 (lro->tcph->source != tcp->source) ||
8359 (lro->tcph->dest != tcp->dest))
7d3d0439
RA		 8360 return -1;
8361 return 0;
8362}
8363
8364static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8365{
d44570e4 8366 return ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2);
7d3d0439
RA		 8367}
8368
1ee6dd77 8369static void initiate_new_session(struct lro *lro, u8 *l2h,
d44570e4
JP		 8370 struct iphdr *ip, struct tcphdr *tcp,
8371 u32 tcp_pyld_len, u16 vlan_tag)
7d3d0439 8372{
d44570e4 8373 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8374 lro->l2h = l2h;
8375 lro->iph = ip;
8376 lro->tcph = tcp;
8377 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
c8855953 8378 lro->tcp_ack = tcp->ack_seq;
7d3d0439
RA		 8379 lro->sg_num = 1;
8380 lro->total_len = ntohs(ip->tot_len);
8381 lro->frags_len = 0;
cdb5bf02 8382 lro->vlan_tag = vlan_tag;
6aa20a22 8383 /*
d44570e4
JP		 8384 * Check if we saw TCP timestamp.
8385 * Other consistency checks have already been done.
8386 */
7d3d0439 8387 if (tcp->doff == 8) {
c8855953
SR		 8388 __be32 *ptr;
8389 ptr = (__be32 *)(tcp+1);
7d3d0439 8390 lro->saw_ts = 1;
c8855953 8391 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8392 lro->cur_tsecr = *(ptr+2);
8393 }
8394 lro->in_use = 1;
8395}
8396
1ee6dd77 8397static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7d3d0439
RA		 8398{
8399 struct iphdr *ip = lro->iph;
8400 struct tcphdr *tcp = lro->tcph;
bd4f3ae1 8401 __sum16 nchk;
ffb5df6c
JP		 8402 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8403
d44570e4 8404 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8405
8406 /* Update L3 header */
8407 ip->tot_len = htons(lro->total_len);
8408 ip->check = 0;
8409 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8410 ip->check = nchk;
8411
8412 /* Update L4 header */
8413 tcp->ack_seq = lro->tcp_ack;
8414 tcp->window = lro->window;
8415
8416 /* Update tsecr field if this session has timestamps enabled */
8417 if (lro->saw_ts) {
c8855953 8418 __be32 *ptr = (__be32 *)(tcp + 1);
7d3d0439
RA		 8419 *(ptr+2) = lro->cur_tsecr;
8420 }
8421
8422 /* Update counters required for calculation of
8423 * average no. of packets aggregated.
8424 */
ffb5df6c
JP		 8425 swstats->sum_avg_pkts_aggregated += lro->sg_num;
8426 swstats->num_aggregations++;
7d3d0439
RA		 8427}
8428
1ee6dd77 8429static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
d44570e4 8430 struct tcphdr *tcp, u32 l4_pyld)
7d3d0439 8431{
d44570e4 8432 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8433 lro->total_len += l4_pyld;
8434 lro->frags_len += l4_pyld;
8435 lro->tcp_next_seq += l4_pyld;
8436 lro->sg_num++;
8437
8438 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8439 lro->tcp_ack = tcp->ack_seq;
8440 lro->window = tcp->window;
6aa20a22 8441
7d3d0439 8442 if (lro->saw_ts) {
c8855953 8443 __be32 *ptr;
7d3d0439 8444 /* Update tsecr and tsval from this packet */
c8855953
SR		 8445 ptr = (__be32 *)(tcp+1);
8446 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8447 lro->cur_tsecr = *(ptr + 2);
8448 }
8449}
8450
1ee6dd77 8451static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7d3d0439
RA		 8452 struct tcphdr *tcp, u32 tcp_pyld_len)
8453{
7d3d0439
RA		 8454 u8 *ptr;
8455
d44570e4 8456 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
79dc1901 8457
7d3d0439
RA		 8458 if (!tcp_pyld_len) {
8459 /* Runt frame or a pure ack */
8460 return -1;
8461 }
8462
8463 if (ip->ihl != 5) /* IP has options */
8464 return -1;
8465
75c30b13
AR		 8466 /* If we see CE codepoint in IP header, packet is not mergeable */
8467 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8468 return -1;
8469
8470 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
d44570e4
JP		 8471 if (tcp->urg || tcp->psh || tcp->rst ||
8472 tcp->syn || tcp->fin ||
8473 tcp->ece || tcp->cwr || !tcp->ack) {
7d3d0439
RA		 8474 /*
8475 * Currently recognize only the ack control word and
8476 * any other control field being set would result in
8477 * flushing the LRO session
8478 */
8479 return -1;
8480 }
8481
6aa20a22 8482 /*
7d3d0439
RA		 8483 * Allow only one TCP timestamp option. Don't aggregate if
8484 * any other options are detected.
8485 */
8486 if (tcp->doff != 5 && tcp->doff != 8)
8487 return -1;
8488
8489 if (tcp->doff == 8) {
6aa20a22 8490 ptr = (u8 *)(tcp + 1);
7d3d0439
RA		 8491 while (*ptr == TCPOPT_NOP)
8492 ptr++;
8493 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8494 return -1;
8495
8496 /* Ensure timestamp value increases monotonically */
8497 if (l_lro)
c8855953 8498 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
7d3d0439
RA		 8499 return -1;
8500
8501 /* timestamp echo reply should be non-zero */
c8855953 8502 if (*((__be32 *)(ptr+6)) == 0)
7d3d0439
RA		 8503 return -1;
8504 }
8505
8506 return 0;
8507}
8508
d44570e4
JP		 8509static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
8510 u8 **tcp, u32 *tcp_len, struct lro **lro,
8511 struct RxD_t *rxdp, struct s2io_nic *sp)
7d3d0439
RA		 8512{
8513 struct iphdr *ip;
8514 struct tcphdr *tcph;
8515 int ret = 0, i;
cdb5bf02 8516 u16 vlan_tag = 0;
ffb5df6c 8517 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7d3d0439 8518
d44570e4
JP		 8519 ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8520 rxdp, sp);
8521 if (ret)
7d3d0439 8522 return ret;
7d3d0439 8523
d44570e4
JP		 8524 DBG_PRINT(INFO_DBG, "IP Saddr: %x Daddr: %x\n", ip->saddr, ip->daddr);
8525
cdb5bf02 8526 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
7d3d0439
RA		 8527 tcph = (struct tcphdr *)*tcp;
8528 *tcp_len = get_l4_pyld_length(ip, tcph);
d44570e4 8529 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 8530 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8531 if (l_lro->in_use) {
8532 if (check_for_socket_match(l_lro, ip, tcph))
8533 continue;
8534 /* Sock pair matched */
8535 *lro = l_lro;
8536
8537 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
9e39f7c5
JP		 8538 DBG_PRINT(INFO_DBG, "%s: Out of sequence. "
8539 "expected 0x%x, actual 0x%x\n",
8540 __func__,
7d3d0439
RA		 8541 (*lro)->tcp_next_seq,
8542 ntohl(tcph->seq));
8543
ffb5df6c 8544 swstats->outof_sequence_pkts++;
7d3d0439
RA		 8545 ret = 2;
8546 break;
8547 }
8548
d44570e4
JP		 8549 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,
8550 *tcp_len))
7d3d0439
RA		 8551 ret = 1; /* Aggregate */
8552 else
8553 ret = 2; /* Flush both */
8554 break;
8555 }
8556 }
8557
8558 if (ret == 0) {
8559 /* Before searching for available LRO objects,
8560 * check if the pkt is L3/L4 aggregatable. If not
8561 * don't create new LRO session. Just send this
8562 * packet up.
8563 */
d44570e4 8564 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len))
7d3d0439 8565 return 5;
7d3d0439 8566
d44570e4 8567 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 8568 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8569 if (!(l_lro->in_use)) {
8570 *lro = l_lro;
8571 ret = 3; /* Begin anew */
8572 break;
8573 }
8574 }
8575 }
8576
8577 if (ret == 0) { /* sessions exceeded */
9e39f7c5 8578 DBG_PRINT(INFO_DBG, "%s: All LRO sessions already in use\n",
b39d66a8 8579 __func__);
7d3d0439
RA		 8580 *lro = NULL;
8581 return ret;
8582 }
8583
8584 switch (ret) {
d44570e4
JP		 8585 case 3:
8586 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8587 vlan_tag);
8588 break;
8589 case 2:
8590 update_L3L4_header(sp, *lro);
8591 break;
8592 case 1:
8593 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8594 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
7d3d0439 8595 update_L3L4_header(sp, *lro);
d44570e4
JP		 8596 ret = 4; /* Flush the LRO */
8597 }
8598 break;
8599 default:
9e39f7c5 8600 DBG_PRINT(ERR_DBG, "%s: Don't know, can't say!!\n", __func__);
d44570e4 8601 break;
7d3d0439
RA		 8602 }
8603
8604 return ret;
8605}
8606
1ee6dd77 8607static void clear_lro_session(struct lro *lro)
7d3d0439 8608{
1ee6dd77 8609 static u16 lro_struct_size = sizeof(struct lro);
7d3d0439
RA		 8610
8611 memset(lro, 0, lro_struct_size);
8612}
8613
cdb5bf02 8614static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
7d3d0439
RA		 8615{
8616 struct net_device *dev = skb->dev;
4cf1653a 8617 struct s2io_nic *sp = netdev_priv(dev);
7d3d0439
RA		 8618
8619 skb->protocol = eth_type_trans(skb, dev);
d44570e4 8620 if (sp->vlgrp && vlan_tag && (sp->vlan_strip_flag)) {
cdb5bf02
SH		 8621 /* Queueing the vlan frame to the upper layer */
8622 if (sp->config.napi)
8623 vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8624 else
8625 vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8626 } else {
8627 if (sp->config.napi)
8628 netif_receive_skb(skb);
8629 else
8630 netif_rx(skb);
8631 }
7d3d0439
RA		 8632}
8633
1ee6dd77 8634static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
d44570e4 8635 struct sk_buff *skb, u32 tcp_len)
7d3d0439 8636{
75c30b13 8637 struct sk_buff *first = lro->parent;
ffb5df6c 8638 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7d3d0439
RA		 8639
8640 first->len += tcp_len;
8641 first->data_len = lro->frags_len;
8642 skb_pull(skb, (skb->len - tcp_len));
75c30b13
AR		 8643 if (skb_shinfo(first)->frag_list)
8644 lro->last_frag->next = skb;
7d3d0439
RA		 8645 else
8646 skb_shinfo(first)->frag_list = skb;
372cc597 8647 first->truesize += skb->truesize;
75c30b13 8648 lro->last_frag = skb;
ffb5df6c 8649 swstats->clubbed_frms_cnt++;
7d3d0439 8650}
d796fdb7
LV		 8651
8652/**
8653 * s2io_io_error_detected - called when PCI error is detected
8654 * @pdev: Pointer to PCI device
8453d43f 8655 * @state: The current pci connection state
d796fdb7
LV		 8656 *
8657 * This function is called after a PCI bus error affecting
8658 * this device has been detected.
8659 */
8660static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
d44570e4 8661 pci_channel_state_t state)
d796fdb7
LV		 8662{
8663 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8664 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8665
8666 netif_device_detach(netdev);
8667
1e3c8bd6
DN		 8668 if (state == pci_channel_io_perm_failure)
8669 return PCI_ERS_RESULT_DISCONNECT;
8670
d796fdb7
LV		 8671 if (netif_running(netdev)) {
8672 /* Bring down the card, while avoiding PCI I/O */
8673 do_s2io_card_down(sp, 0);
d796fdb7
LV		 8674 }
8675 pci_disable_device(pdev);
8676
8677 return PCI_ERS_RESULT_NEED_RESET;
8678}
8679
8680/**
8681 * s2io_io_slot_reset - called after the pci bus has been reset.
8682 * @pdev: Pointer to PCI device
8683 *
8684 * Restart the card from scratch, as if from a cold-boot.
8685 * At this point, the card has exprienced a hard reset,
8686 * followed by fixups by BIOS, and has its config space
8687 * set up identically to what it was at cold boot.
8688 */
8689static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8690{
8691 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8692 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8693
8694 if (pci_enable_device(pdev)) {
6cef2b8e 8695 pr_err("Cannot re-enable PCI device after reset.\n");
d796fdb7
LV		 8696 return PCI_ERS_RESULT_DISCONNECT;
8697 }
8698
8699 pci_set_master(pdev);
8700 s2io_reset(sp);
8701
8702 return PCI_ERS_RESULT_RECOVERED;
8703}
8704
8705/**
8706 * s2io_io_resume - called when traffic can start flowing again.
8707 * @pdev: Pointer to PCI device
8708 *
8709 * This callback is called when the error recovery driver tells
8710 * us that its OK to resume normal operation.
8711 */
8712static void s2io_io_resume(struct pci_dev *pdev)
8713{
8714 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8715 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8716
8717 if (netif_running(netdev)) {
8718 if (s2io_card_up(sp)) {
6cef2b8e 8719 pr_err("Can't bring device back up after reset.\n");
d796fdb7
LV		 8720 return;
8721 }
8722
8723 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8724 s2io_card_down(sp);
6cef2b8e 8725 pr_err("Can't restore mac addr after reset.\n");
d796fdb7
LV		 8726 return;
8727 }
8728 }
8729
8730 netif_device_attach(netdev);
fd2ea0a7 8731 netif_tx_wake_all_queues(netdev);
d796fdb7 8732}
kernel source for telekom puls (alcatel/mediatek)