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qla3xxx: Bumping driver version number
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / net / s2io.c
CommitLineData
1da177e4 1/************************************************************************
776bd20f 2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
1da177e4
LT		 3 * Copyright(c) 2002-2005 Neterion Inc.
4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
20346722
K		 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
1da177e4
LT		 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
20346722 21 * Francois Romieu : For pointing out all code part that were
1da177e4 22 * deprecated and also styling related comments.
20346722 23 * Grant Grundler : For helping me get rid of some Architecture
1da177e4
LT		 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
20346722 26 *
1da177e4
LT		 27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
9dc737a7 29 *
20346722
K		 30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
9dc737a7
AR		 32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
da6971d8
AR		 34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35 * values are 1, 2 and 3.
1da177e4 36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
20346722 37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
1da177e4 38 * Tx descriptors that can be associated with each corresponding FIFO.
9dc737a7
AR		 39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 1(MSI), 2(MSI_X). Default value is '0(INTA)'
41 * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
1da177e4
LT		 45 ************************************************************************/
46
1da177e4
LT		 47#include <linux/module.h>
48#include <linux/types.h>
49#include <linux/errno.h>
50#include <linux/ioport.h>
51#include <linux/pci.h>
1e7f0bd8 52#include <linux/dma-mapping.h>
1da177e4
LT		 53#include <linux/kernel.h>
54#include <linux/netdevice.h>
55#include <linux/etherdevice.h>
56#include <linux/skbuff.h>
57#include <linux/init.h>
58#include <linux/delay.h>
59#include <linux/stddef.h>
60#include <linux/ioctl.h>
61#include <linux/timex.h>
1da177e4 62#include <linux/ethtool.h>
1da177e4 63#include <linux/workqueue.h>
be3a6b02 64#include <linux/if_vlan.h>
7d3d0439
RA		 65#include <linux/ip.h>
66#include <linux/tcp.h>
67#include <net/tcp.h>
1da177e4 68
1da177e4
LT		 69#include <asm/system.h>
70#include <asm/uaccess.h>
20346722 71#include <asm/io.h>
fe931395 72#include <asm/div64.h>
330ce0de 73#include <asm/irq.h>
1da177e4
LT		 74
75/* local include */
76#include "s2io.h"
77#include "s2io-regs.h"
78
1ee6dd77 79#define DRV_VERSION "2.0.16.1"
6c1792f4 80
1da177e4 81/* S2io Driver name & version. */
20346722 82static char s2io_driver_name[] = "Neterion";
6c1792f4 83static char s2io_driver_version[] = DRV_VERSION;
1da177e4 84
26df54bf
AB		 85static int rxd_size[4] = {32,48,48,64};
86static int rxd_count[4] = {127,85,85,63};
da6971d8 87
1ee6dd77 88static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
5e25b9dd
K		 89{
90 int ret;
91
92 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
93 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
94
95 return ret;
96}
97
20346722 98/*
1da177e4
LT		 99 * Cards with following subsystem_id have a link state indication
100 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
101 * macro below identifies these cards given the subsystem_id.
102 */
541ae68f
K		 103#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
104 (dev_type == XFRAME_I_DEVICE) ? \
105 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
106 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
1da177e4
LT		 107
108#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
109 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
110#define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
111#define PANIC 1
112#define LOW 2
1ee6dd77 113static inline int rx_buffer_level(struct s2io_nic * sp, int rxb_size, int ring)
1da177e4 114{
1ee6dd77 115 struct mac_info *mac_control;
20346722
K		 116
117 mac_control = &sp->mac_control;
863c11a9
AR		 118 if (rxb_size <= rxd_count[sp->rxd_mode])
119 return PANIC;
120 else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
121 return LOW;
122 return 0;
1da177e4
LT		 123}
124
125/* Ethtool related variables and Macros. */
126static char s2io_gstrings[][ETH_GSTRING_LEN] = {
127 "Register test\t(offline)",
128 "Eeprom test\t(offline)",
129 "Link test\t(online)",
130 "RLDRAM test\t(offline)",
131 "BIST Test\t(offline)"
132};
133
134static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
135 {"tmac_frms"},
136 {"tmac_data_octets"},
137 {"tmac_drop_frms"},
138 {"tmac_mcst_frms"},
139 {"tmac_bcst_frms"},
140 {"tmac_pause_ctrl_frms"},
bd1034f0
AR		 141 {"tmac_ttl_octets"},
142 {"tmac_ucst_frms"},
143 {"tmac_nucst_frms"},
1da177e4 144 {"tmac_any_err_frms"},
bd1034f0 145 {"tmac_ttl_less_fb_octets"},
1da177e4
LT		 146 {"tmac_vld_ip_octets"},
147 {"tmac_vld_ip"},
148 {"tmac_drop_ip"},
149 {"tmac_icmp"},
150 {"tmac_rst_tcp"},
151 {"tmac_tcp"},
152 {"tmac_udp"},
153 {"rmac_vld_frms"},
154 {"rmac_data_octets"},
155 {"rmac_fcs_err_frms"},
156 {"rmac_drop_frms"},
157 {"rmac_vld_mcst_frms"},
158 {"rmac_vld_bcst_frms"},
159 {"rmac_in_rng_len_err_frms"},
bd1034f0 160 {"rmac_out_rng_len_err_frms"},
1da177e4
LT		 161 {"rmac_long_frms"},
162 {"rmac_pause_ctrl_frms"},
bd1034f0
AR		 163 {"rmac_unsup_ctrl_frms"},
164 {"rmac_ttl_octets"},
165 {"rmac_accepted_ucst_frms"},
166 {"rmac_accepted_nucst_frms"},
1da177e4 167 {"rmac_discarded_frms"},
bd1034f0
AR		 168 {"rmac_drop_events"},
169 {"rmac_ttl_less_fb_octets"},
170 {"rmac_ttl_frms"},
1da177e4
LT		 171 {"rmac_usized_frms"},
172 {"rmac_osized_frms"},
173 {"rmac_frag_frms"},
174 {"rmac_jabber_frms"},
bd1034f0
AR		 175 {"rmac_ttl_64_frms"},
176 {"rmac_ttl_65_127_frms"},
177 {"rmac_ttl_128_255_frms"},
178 {"rmac_ttl_256_511_frms"},
179 {"rmac_ttl_512_1023_frms"},
180 {"rmac_ttl_1024_1518_frms"},
1da177e4
LT		 181 {"rmac_ip"},
182 {"rmac_ip_octets"},
183 {"rmac_hdr_err_ip"},
184 {"rmac_drop_ip"},
185 {"rmac_icmp"},
186 {"rmac_tcp"},
187 {"rmac_udp"},
188 {"rmac_err_drp_udp"},
bd1034f0
AR		 189 {"rmac_xgmii_err_sym"},
190 {"rmac_frms_q0"},
191 {"rmac_frms_q1"},
192 {"rmac_frms_q2"},
193 {"rmac_frms_q3"},
194 {"rmac_frms_q4"},
195 {"rmac_frms_q5"},
196 {"rmac_frms_q6"},
197 {"rmac_frms_q7"},
198 {"rmac_full_q0"},
199 {"rmac_full_q1"},
200 {"rmac_full_q2"},
201 {"rmac_full_q3"},
202 {"rmac_full_q4"},
203 {"rmac_full_q5"},
204 {"rmac_full_q6"},
205 {"rmac_full_q7"},
1da177e4 206 {"rmac_pause_cnt"},
bd1034f0
AR		 207 {"rmac_xgmii_data_err_cnt"},
208 {"rmac_xgmii_ctrl_err_cnt"},
1da177e4
LT		 209 {"rmac_accepted_ip"},
210 {"rmac_err_tcp"},
bd1034f0
AR		 211 {"rd_req_cnt"},
212 {"new_rd_req_cnt"},
213 {"new_rd_req_rtry_cnt"},
214 {"rd_rtry_cnt"},
215 {"wr_rtry_rd_ack_cnt"},
216 {"wr_req_cnt"},
217 {"new_wr_req_cnt"},
218 {"new_wr_req_rtry_cnt"},
219 {"wr_rtry_cnt"},
220 {"wr_disc_cnt"},
221 {"rd_rtry_wr_ack_cnt"},
222 {"txp_wr_cnt"},
223 {"txd_rd_cnt"},
224 {"txd_wr_cnt"},
225 {"rxd_rd_cnt"},
226 {"rxd_wr_cnt"},
227 {"txf_rd_cnt"},
228 {"rxf_wr_cnt"},
229 {"rmac_ttl_1519_4095_frms"},
230 {"rmac_ttl_4096_8191_frms"},
231 {"rmac_ttl_8192_max_frms"},
232 {"rmac_ttl_gt_max_frms"},
233 {"rmac_osized_alt_frms"},
234 {"rmac_jabber_alt_frms"},
235 {"rmac_gt_max_alt_frms"},
236 {"rmac_vlan_frms"},
237 {"rmac_len_discard"},
238 {"rmac_fcs_discard"},
239 {"rmac_pf_discard"},
240 {"rmac_da_discard"},
241 {"rmac_red_discard"},
242 {"rmac_rts_discard"},
243 {"rmac_ingm_full_discard"},
244 {"link_fault_cnt"},
7ba013ac
K		 245 {"\n DRIVER STATISTICS"},
246 {"single_bit_ecc_errs"},
247 {"double_bit_ecc_errs"},
bd1034f0
AR		 248 {"parity_err_cnt"},
249 {"serious_err_cnt"},
250 {"soft_reset_cnt"},
251 {"fifo_full_cnt"},
252 {"ring_full_cnt"},
253 ("alarm_transceiver_temp_high"),
254 ("alarm_transceiver_temp_low"),
255 ("alarm_laser_bias_current_high"),
256 ("alarm_laser_bias_current_low"),
257 ("alarm_laser_output_power_high"),
258 ("alarm_laser_output_power_low"),
259 ("warn_transceiver_temp_high"),
260 ("warn_transceiver_temp_low"),
261 ("warn_laser_bias_current_high"),
262 ("warn_laser_bias_current_low"),
263 ("warn_laser_output_power_high"),
264 ("warn_laser_output_power_low"),
7d3d0439
RA		 265 ("lro_aggregated_pkts"),
266 ("lro_flush_both_count"),
267 ("lro_out_of_sequence_pkts"),
268 ("lro_flush_due_to_max_pkts"),
269 ("lro_avg_aggr_pkts"),
1da177e4
LT		 270};
271
272#define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
273#define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
274
275#define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN
276#define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
277
25fff88e
K		 278#define S2IO_TIMER_CONF(timer, handle, arg, exp) \
279 init_timer(&timer); \
280 timer.function = handle; \
281 timer.data = (unsigned long) arg; \
282 mod_timer(&timer, (jiffies + exp)) \
283
be3a6b02
K		 284/* Add the vlan */
285static void s2io_vlan_rx_register(struct net_device *dev,
286 struct vlan_group *grp)
287{
1ee6dd77 288 struct s2io_nic *nic = dev->priv;
be3a6b02
K		 289 unsigned long flags;
290
291 spin_lock_irqsave(&nic->tx_lock, flags);
292 nic->vlgrp = grp;
293 spin_unlock_irqrestore(&nic->tx_lock, flags);
294}
295
296/* Unregister the vlan */
297static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
298{
1ee6dd77 299 struct s2io_nic *nic = dev->priv;
be3a6b02
K		 300 unsigned long flags;
301
302 spin_lock_irqsave(&nic->tx_lock, flags);
303 if (nic->vlgrp)
304 nic->vlgrp->vlan_devices[vid] = NULL;
305 spin_unlock_irqrestore(&nic->tx_lock, flags);
306}
307
20346722 308/*
1da177e4
LT		 309 * Constants to be programmed into the Xena's registers, to configure
310 * the XAUI.
311 */
312
1da177e4 313#define END_SIGN 0x0
f71e1309 314static const u64 herc_act_dtx_cfg[] = {
541ae68f 315 /* Set address */
e960fc5c 316 0x8000051536750000ULL, 0x80000515367500E0ULL,
541ae68f 317 /* Write data */
e960fc5c 318 0x8000051536750004ULL, 0x80000515367500E4ULL,
541ae68f
K		 319 /* Set address */
320 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
321 /* Write data */
322 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
323 /* Set address */
e960fc5c 324 0x801205150D440000ULL, 0x801205150D4400E0ULL,
325 /* Write data */
326 0x801205150D440004ULL, 0x801205150D4400E4ULL,
327 /* Set address */
541ae68f
K		 328 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
329 /* Write data */
330 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
331 /* Done */
332 END_SIGN
333};
334
f71e1309 335static const u64 xena_dtx_cfg[] = {
c92ca04b 336 /* Set address */
1da177e4 337 0x8000051500000000ULL, 0x80000515000000E0ULL,
c92ca04b
AR		 338 /* Write data */
339 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
340 /* Set address */
341 0x8001051500000000ULL, 0x80010515000000E0ULL,
342 /* Write data */
343 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
344 /* Set address */
1da177e4 345 0x8002051500000000ULL, 0x80020515000000E0ULL,
c92ca04b
AR		 346 /* Write data */
347 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1da177e4
LT		 348 END_SIGN
349};
350
20346722 351/*
1da177e4
LT		 352 * Constants for Fixing the MacAddress problem seen mostly on
353 * Alpha machines.
354 */
f71e1309 355static const u64 fix_mac[] = {
1da177e4
LT		 356 0x0060000000000000ULL, 0x0060600000000000ULL,
357 0x0040600000000000ULL, 0x0000600000000000ULL,
358 0x0020600000000000ULL, 0x0060600000000000ULL,
359 0x0020600000000000ULL, 0x0060600000000000ULL,
360 0x0020600000000000ULL, 0x0060600000000000ULL,
361 0x0020600000000000ULL, 0x0060600000000000ULL,
362 0x0020600000000000ULL, 0x0060600000000000ULL,
363 0x0020600000000000ULL, 0x0060600000000000ULL,
364 0x0020600000000000ULL, 0x0060600000000000ULL,
365 0x0020600000000000ULL, 0x0060600000000000ULL,
366 0x0020600000000000ULL, 0x0060600000000000ULL,
367 0x0020600000000000ULL, 0x0060600000000000ULL,
368 0x0020600000000000ULL, 0x0000600000000000ULL,
369 0x0040600000000000ULL, 0x0060600000000000ULL,
370 END_SIGN
371};
372
b41477f3
AR		 373MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
374MODULE_LICENSE("GPL");
375MODULE_VERSION(DRV_VERSION);
376
377
1da177e4 378/* Module Loadable parameters. */
b41477f3
AR		 379S2IO_PARM_INT(tx_fifo_num, 1);
380S2IO_PARM_INT(rx_ring_num, 1);
381
382
383S2IO_PARM_INT(rx_ring_mode, 1);
384S2IO_PARM_INT(use_continuous_tx_intrs, 1);
385S2IO_PARM_INT(rmac_pause_time, 0x100);
386S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
387S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
388S2IO_PARM_INT(shared_splits, 0);
389S2IO_PARM_INT(tmac_util_period, 5);
390S2IO_PARM_INT(rmac_util_period, 5);
391S2IO_PARM_INT(bimodal, 0);
392S2IO_PARM_INT(l3l4hdr_size, 128);
303bcb4b 393/* Frequency of Rx desc syncs expressed as power of 2 */
b41477f3 394S2IO_PARM_INT(rxsync_frequency, 3);
cc6e7c44 395/* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
b41477f3 396S2IO_PARM_INT(intr_type, 0);
7d3d0439 397/* Large receive offload feature */
b41477f3 398S2IO_PARM_INT(lro, 0);
7d3d0439
RA		 399/* Max pkts to be aggregated by LRO at one time. If not specified,
400 * aggregation happens until we hit max IP pkt size(64K)
401 */
b41477f3 402S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
b41477f3 403S2IO_PARM_INT(indicate_max_pkts, 0);
db874e65
SS		 404
405S2IO_PARM_INT(napi, 1);
406S2IO_PARM_INT(ufo, 0);
b41477f3
AR		 407
408static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
409 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
410static unsigned int rx_ring_sz[MAX_RX_RINGS] =
411 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
412static unsigned int rts_frm_len[MAX_RX_RINGS] =
413 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
414
415module_param_array(tx_fifo_len, uint, NULL, 0);
416module_param_array(rx_ring_sz, uint, NULL, 0);
417module_param_array(rts_frm_len, uint, NULL, 0);
1da177e4 418
20346722 419/*
1da177e4 420 * S2IO device table.
20346722 421 * This table lists all the devices that this driver supports.
1da177e4
LT		 422 */
423static struct pci_device_id s2io_tbl[] __devinitdata = {
424 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
425 PCI_ANY_ID, PCI_ANY_ID},
426 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
427 PCI_ANY_ID, PCI_ANY_ID},
428 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
20346722
K		 429 PCI_ANY_ID, PCI_ANY_ID},
430 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
431 PCI_ANY_ID, PCI_ANY_ID},
1da177e4
LT		 432 {0,}
433};
434
435MODULE_DEVICE_TABLE(pci, s2io_tbl);
436
437static struct pci_driver s2io_driver = {
438 .name = "S2IO",
439 .id_table = s2io_tbl,
440 .probe = s2io_init_nic,
441 .remove = __devexit_p(s2io_rem_nic),
442};
443
444/* A simplifier macro used both by init and free shared_mem Fns(). */
445#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
446
447/**
448 * init_shared_mem - Allocation and Initialization of Memory
449 * @nic: Device private variable.
20346722
K		 450 * Description: The function allocates all the memory areas shared
451 * between the NIC and the driver. This includes Tx descriptors,
1da177e4
LT		 452 * Rx descriptors and the statistics block.
453 */
454
455static int init_shared_mem(struct s2io_nic *nic)
456{
457 u32 size;
458 void *tmp_v_addr, *tmp_v_addr_next;
459 dma_addr_t tmp_p_addr, tmp_p_addr_next;
1ee6dd77 460 struct RxD_block *pre_rxd_blk = NULL;
372cc597 461 int i, j, blk_cnt;
1da177e4
LT		 462 int lst_size, lst_per_page;
463 struct net_device *dev = nic->dev;
8ae418cf 464 unsigned long tmp;
1ee6dd77 465 struct buffAdd *ba;
1da177e4 466
1ee6dd77 467 struct mac_info *mac_control;
1da177e4
LT		 468 struct config_param *config;
469
470 mac_control = &nic->mac_control;
471 config = &nic->config;
472
473
474 /* Allocation and initialization of TXDLs in FIOFs */
475 size = 0;
476 for (i = 0; i < config->tx_fifo_num; i++) {
477 size += config->tx_cfg[i].fifo_len;
478 }
479 if (size > MAX_AVAILABLE_TXDS) {
b41477f3 480 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
0b1f7ebe 481 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
b41477f3 482 return -EINVAL;
1da177e4
LT		 483 }
484
1ee6dd77 485 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 486 lst_per_page = PAGE_SIZE / lst_size;
487
488 for (i = 0; i < config->tx_fifo_num; i++) {
489 int fifo_len = config->tx_cfg[i].fifo_len;
1ee6dd77 490 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
20346722
K		 491 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
492 GFP_KERNEL);
493 if (!mac_control->fifos[i].list_info) {
1da177e4
LT		 494 DBG_PRINT(ERR_DBG,
495 "Malloc failed for list_info\n");
496 return -ENOMEM;
497 }
20346722 498 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
1da177e4
LT		 499 }
500 for (i = 0; i < config->tx_fifo_num; i++) {
501 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
502 lst_per_page);
20346722
K		 503 mac_control->fifos[i].tx_curr_put_info.offset = 0;
504 mac_control->fifos[i].tx_curr_put_info.fifo_len =
1da177e4 505 config->tx_cfg[i].fifo_len - 1;
20346722
K		 506 mac_control->fifos[i].tx_curr_get_info.offset = 0;
507 mac_control->fifos[i].tx_curr_get_info.fifo_len =
1da177e4 508 config->tx_cfg[i].fifo_len - 1;
20346722
K		 509 mac_control->fifos[i].fifo_no = i;
510 mac_control->fifos[i].nic = nic;
fed5eccd 511 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
20346722 512
1da177e4
LT		 513 for (j = 0; j < page_num; j++) {
514 int k = 0;
515 dma_addr_t tmp_p;
516 void *tmp_v;
517 tmp_v = pci_alloc_consistent(nic->pdev,
518 PAGE_SIZE, &tmp_p);
519 if (!tmp_v) {
520 DBG_PRINT(ERR_DBG,
521 "pci_alloc_consistent ");
522 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
523 return -ENOMEM;
524 }
776bd20f 525 /* If we got a zero DMA address(can happen on
526 * certain platforms like PPC), reallocate.
527 * Store virtual address of page we don't want,
528 * to be freed later.
529 */
530 if (!tmp_p) {
531 mac_control->zerodma_virt_addr = tmp_v;
6aa20a22 532 DBG_PRINT(INIT_DBG,
776bd20f 533 "%s: Zero DMA address for TxDL. ", dev->name);
6aa20a22 534 DBG_PRINT(INIT_DBG,
6b4d617d 535 "Virtual address %p\n", tmp_v);
776bd20f 536 tmp_v = pci_alloc_consistent(nic->pdev,
537 PAGE_SIZE, &tmp_p);
538 if (!tmp_v) {
539 DBG_PRINT(ERR_DBG,
540 "pci_alloc_consistent ");
541 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
542 return -ENOMEM;
543 }
544 }
1da177e4
LT		 545 while (k < lst_per_page) {
546 int l = (j * lst_per_page) + k;
547 if (l == config->tx_cfg[i].fifo_len)
20346722
K		 548 break;
549 mac_control->fifos[i].list_info[l].list_virt_addr =
1da177e4 550 tmp_v + (k * lst_size);
20346722 551 mac_control->fifos[i].list_info[l].list_phy_addr =
1da177e4
LT		 552 tmp_p + (k * lst_size);
553 k++;
554 }
555 }
556 }
1da177e4 557
4384247b 558 nic->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
fed5eccd
AR		 559 if (!nic->ufo_in_band_v)
560 return -ENOMEM;
561
1da177e4
LT		 562 /* Allocation and initialization of RXDs in Rings */
563 size = 0;
564 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 565 if (config->rx_cfg[i].num_rxd %
566 (rxd_count[nic->rxd_mode] + 1)) {
1da177e4
LT		 567 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
568 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
569 i);
570 DBG_PRINT(ERR_DBG, "RxDs per Block");
571 return FAILURE;
572 }
573 size += config->rx_cfg[i].num_rxd;
20346722 574 mac_control->rings[i].block_count =
da6971d8
AR		 575 config->rx_cfg[i].num_rxd /
576 (rxd_count[nic->rxd_mode] + 1 );
577 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
578 mac_control->rings[i].block_count;
1da177e4 579 }
da6971d8 580 if (nic->rxd_mode == RXD_MODE_1)
1ee6dd77 581 size = (size * (sizeof(struct RxD1)));
da6971d8 582 else
1ee6dd77 583 size = (size * (sizeof(struct RxD3)));
1da177e4
LT		 584
585 for (i = 0; i < config->rx_ring_num; i++) {
20346722
K		 586 mac_control->rings[i].rx_curr_get_info.block_index = 0;
587 mac_control->rings[i].rx_curr_get_info.offset = 0;
588 mac_control->rings[i].rx_curr_get_info.ring_len =
1da177e4 589 config->rx_cfg[i].num_rxd - 1;
20346722
K		 590 mac_control->rings[i].rx_curr_put_info.block_index = 0;
591 mac_control->rings[i].rx_curr_put_info.offset = 0;
592 mac_control->rings[i].rx_curr_put_info.ring_len =
1da177e4 593 config->rx_cfg[i].num_rxd - 1;
20346722
K		 594 mac_control->rings[i].nic = nic;
595 mac_control->rings[i].ring_no = i;
596
da6971d8
AR		 597 blk_cnt = config->rx_cfg[i].num_rxd /
598 (rxd_count[nic->rxd_mode] + 1);
1da177e4
LT		 599 /* Allocating all the Rx blocks */
600 for (j = 0; j < blk_cnt; j++) {
1ee6dd77 601 struct rx_block_info *rx_blocks;
da6971d8
AR		 602 int l;
603
604 rx_blocks = &mac_control->rings[i].rx_blocks[j];
605 size = SIZE_OF_BLOCK; //size is always page size
1da177e4
LT		 606 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
607 &tmp_p_addr);
608 if (tmp_v_addr == NULL) {
609 /*
20346722
K		 610 * In case of failure, free_shared_mem()
611 * is called, which should free any
612 * memory that was alloced till the
1da177e4
LT		 613 * failure happened.
614 */
da6971d8 615 rx_blocks->block_virt_addr = tmp_v_addr;
1da177e4
LT		 616 return -ENOMEM;
617 }
618 memset(tmp_v_addr, 0, size);
da6971d8
AR		 619 rx_blocks->block_virt_addr = tmp_v_addr;
620 rx_blocks->block_dma_addr = tmp_p_addr;
1ee6dd77 621 rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
da6971d8
AR		 622 rxd_count[nic->rxd_mode],
623 GFP_KERNEL);
372cc597
SS		 624 if (!rx_blocks->rxds)
625 return -ENOMEM;
da6971d8
AR		 626 for (l=0; l<rxd_count[nic->rxd_mode];l++) {
627 rx_blocks->rxds[l].virt_addr =
628 rx_blocks->block_virt_addr +
629 (rxd_size[nic->rxd_mode] * l);
630 rx_blocks->rxds[l].dma_addr =
631 rx_blocks->block_dma_addr +
632 (rxd_size[nic->rxd_mode] * l);
633 }
1da177e4
LT		 634 }
635 /* Interlinking all Rx Blocks */
636 for (j = 0; j < blk_cnt; j++) {
20346722
K		 637 tmp_v_addr =
638 mac_control->rings[i].rx_blocks[j].block_virt_addr;
1da177e4 639 tmp_v_addr_next =
20346722 640 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4 641 blk_cnt].block_virt_addr;
20346722
K		 642 tmp_p_addr =
643 mac_control->rings[i].rx_blocks[j].block_dma_addr;
1da177e4 644 tmp_p_addr_next =
20346722 645 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4
LT		 646 blk_cnt].block_dma_addr;
647
1ee6dd77 648 pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
1da177e4
LT		 649 pre_rxd_blk->reserved_2_pNext_RxD_block =
650 (unsigned long) tmp_v_addr_next;
1da177e4
LT		 651 pre_rxd_blk->pNext_RxD_Blk_physical =
652 (u64) tmp_p_addr_next;
653 }
654 }
da6971d8
AR		 655 if (nic->rxd_mode >= RXD_MODE_3A) {
656 /*
657 * Allocation of Storages for buffer addresses in 2BUFF mode
658 * and the buffers as well.
659 */
660 for (i = 0; i < config->rx_ring_num; i++) {
661 blk_cnt = config->rx_cfg[i].num_rxd /
662 (rxd_count[nic->rxd_mode]+ 1);
663 mac_control->rings[i].ba =
1ee6dd77 664 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
1da177e4 665 GFP_KERNEL);
da6971d8 666 if (!mac_control->rings[i].ba)
1da177e4 667 return -ENOMEM;
da6971d8
AR		 668 for (j = 0; j < blk_cnt; j++) {
669 int k = 0;
670 mac_control->rings[i].ba[j] =
1ee6dd77 671 kmalloc((sizeof(struct buffAdd) *
da6971d8
AR		 672 (rxd_count[nic->rxd_mode] + 1)),
673 GFP_KERNEL);
674 if (!mac_control->rings[i].ba[j])
1da177e4 675 return -ENOMEM;
da6971d8
AR		 676 while (k != rxd_count[nic->rxd_mode]) {
677 ba = &mac_control->rings[i].ba[j][k];
678
679 ba->ba_0_org = (void *) kmalloc
680 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
681 if (!ba->ba_0_org)
682 return -ENOMEM;
683 tmp = (unsigned long)ba->ba_0_org;
684 tmp += ALIGN_SIZE;
685 tmp &= ~((unsigned long) ALIGN_SIZE);
686 ba->ba_0 = (void *) tmp;
687
688 ba->ba_1_org = (void *) kmalloc
689 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
690 if (!ba->ba_1_org)
691 return -ENOMEM;
692 tmp = (unsigned long) ba->ba_1_org;
693 tmp += ALIGN_SIZE;
694 tmp &= ~((unsigned long) ALIGN_SIZE);
695 ba->ba_1 = (void *) tmp;
696 k++;
697 }
1da177e4
LT		 698 }
699 }
700 }
1da177e4
LT		 701
702 /* Allocation and initialization of Statistics block */
1ee6dd77 703 size = sizeof(struct stat_block);
1da177e4
LT		 704 mac_control->stats_mem = pci_alloc_consistent
705 (nic->pdev, size, &mac_control->stats_mem_phy);
706
707 if (!mac_control->stats_mem) {
20346722
K		 708 /*
709 * In case of failure, free_shared_mem() is called, which
710 * should free any memory that was alloced till the
1da177e4
LT		 711 * failure happened.
712 */
713 return -ENOMEM;
714 }
715 mac_control->stats_mem_sz = size;
716
717 tmp_v_addr = mac_control->stats_mem;
1ee6dd77 718 mac_control->stats_info = (struct stat_block *) tmp_v_addr;
1da177e4 719 memset(tmp_v_addr, 0, size);
1da177e4
LT		 720 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
721 (unsigned long long) tmp_p_addr);
722
723 return SUCCESS;
724}
725
20346722
K		 726/**
727 * free_shared_mem - Free the allocated Memory
1da177e4
LT		 728 * @nic: Device private variable.
729 * Description: This function is to free all memory locations allocated by
730 * the init_shared_mem() function and return it to the kernel.
731 */
732
733static void free_shared_mem(struct s2io_nic *nic)
734{
735 int i, j, blk_cnt, size;
736 void *tmp_v_addr;
737 dma_addr_t tmp_p_addr;
1ee6dd77 738 struct mac_info *mac_control;
1da177e4
LT		 739 struct config_param *config;
740 int lst_size, lst_per_page;
776bd20f 741 struct net_device *dev = nic->dev;
1da177e4
LT		 742
743 if (!nic)
744 return;
745
746 mac_control = &nic->mac_control;
747 config = &nic->config;
748
1ee6dd77 749 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 750 lst_per_page = PAGE_SIZE / lst_size;
751
752 for (i = 0; i < config->tx_fifo_num; i++) {
753 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
754 lst_per_page);
755 for (j = 0; j < page_num; j++) {
756 int mem_blks = (j * lst_per_page);
776bd20f 757 if (!mac_control->fifos[i].list_info)
6aa20a22 758 return;
776bd20f 759 if (!mac_control->fifos[i].list_info[mem_blks].
760 list_virt_addr)
1da177e4
LT		 761 break;
762 pci_free_consistent(nic->pdev, PAGE_SIZE,
20346722
K		 763 mac_control->fifos[i].
764 list_info[mem_blks].
1da177e4 765 list_virt_addr,
20346722
K		 766 mac_control->fifos[i].
767 list_info[mem_blks].
1da177e4
LT		 768 list_phy_addr);
769 }
776bd20f 770 /* If we got a zero DMA address during allocation,
771 * free the page now
772 */
773 if (mac_control->zerodma_virt_addr) {
774 pci_free_consistent(nic->pdev, PAGE_SIZE,
775 mac_control->zerodma_virt_addr,
776 (dma_addr_t)0);
6aa20a22 777 DBG_PRINT(INIT_DBG,
6b4d617d
AM		 778 "%s: Freeing TxDL with zero DMA addr. ",
779 dev->name);
780 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
781 mac_control->zerodma_virt_addr);
776bd20f 782 }
20346722 783 kfree(mac_control->fifos[i].list_info);
1da177e4
LT		 784 }
785
1da177e4 786 size = SIZE_OF_BLOCK;
1da177e4 787 for (i = 0; i < config->rx_ring_num; i++) {
20346722 788 blk_cnt = mac_control->rings[i].block_count;
1da177e4 789 for (j = 0; j < blk_cnt; j++) {
20346722
K		 790 tmp_v_addr = mac_control->rings[i].rx_blocks[j].
791 block_virt_addr;
792 tmp_p_addr = mac_control->rings[i].rx_blocks[j].
793 block_dma_addr;
1da177e4
LT		 794 if (tmp_v_addr == NULL)
795 break;
796 pci_free_consistent(nic->pdev, size,
797 tmp_v_addr, tmp_p_addr);
da6971d8 798 kfree(mac_control->rings[i].rx_blocks[j].rxds);
1da177e4
LT		 799 }
800 }
801
da6971d8
AR		 802 if (nic->rxd_mode >= RXD_MODE_3A) {
803 /* Freeing buffer storage addresses in 2BUFF mode. */
804 for (i = 0; i < config->rx_ring_num; i++) {
805 blk_cnt = config->rx_cfg[i].num_rxd /
806 (rxd_count[nic->rxd_mode] + 1);
807 for (j = 0; j < blk_cnt; j++) {
808 int k = 0;
809 if (!mac_control->rings[i].ba[j])
810 continue;
811 while (k != rxd_count[nic->rxd_mode]) {
1ee6dd77 812 struct buffAdd *ba =
da6971d8
AR		 813 &mac_control->rings[i].ba[j][k];
814 kfree(ba->ba_0_org);
815 kfree(ba->ba_1_org);
816 k++;
817 }
818 kfree(mac_control->rings[i].ba[j]);
1da177e4 819 }
da6971d8 820 kfree(mac_control->rings[i].ba);
1da177e4 821 }
1da177e4 822 }
1da177e4
LT		 823
824 if (mac_control->stats_mem) {
825 pci_free_consistent(nic->pdev,
826 mac_control->stats_mem_sz,
827 mac_control->stats_mem,
828 mac_control->stats_mem_phy);
829 }
fed5eccd
AR		 830 if (nic->ufo_in_band_v)
831 kfree(nic->ufo_in_band_v);
1da177e4
LT		 832}
833
541ae68f
K		 834/**
835 * s2io_verify_pci_mode -
836 */
837
1ee6dd77 838static int s2io_verify_pci_mode(struct s2io_nic *nic)
541ae68f 839{
1ee6dd77 840 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 841 register u64 val64 = 0;
842 int mode;
843
844 val64 = readq(&bar0->pci_mode);
845 mode = (u8)GET_PCI_MODE(val64);
846
847 if ( val64 & PCI_MODE_UNKNOWN_MODE)
848 return -1; /* Unknown PCI mode */
849 return mode;
850}
851
c92ca04b
AR		 852#define NEC_VENID 0x1033
853#define NEC_DEVID 0x0125
854static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
855{
856 struct pci_dev *tdev = NULL;
26d36b64
AC		 857 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
858 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
c92ca04b 859 if (tdev->bus == s2io_pdev->bus->parent)
26d36b64 860 pci_dev_put(tdev);
c92ca04b
AR		 861 return 1;
862 }
863 }
864 return 0;
865}
541ae68f 866
7b32a312 867static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
541ae68f
K		 868/**
869 * s2io_print_pci_mode -
870 */
1ee6dd77 871static int s2io_print_pci_mode(struct s2io_nic *nic)
541ae68f 872{
1ee6dd77 873 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 874 register u64 val64 = 0;
875 int mode;
876 struct config_param *config = &nic->config;
877
878 val64 = readq(&bar0->pci_mode);
879 mode = (u8)GET_PCI_MODE(val64);
880
881 if ( val64 & PCI_MODE_UNKNOWN_MODE)
882 return -1; /* Unknown PCI mode */
883
c92ca04b
AR		 884 config->bus_speed = bus_speed[mode];
885
886 if (s2io_on_nec_bridge(nic->pdev)) {
887 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
888 nic->dev->name);
889 return mode;
890 }
891
541ae68f
K		 892 if (val64 & PCI_MODE_32_BITS) {
893 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
894 } else {
895 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
896 }
897
898 switch(mode) {
899 case PCI_MODE_PCI_33:
900 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
541ae68f
K		 901 break;
902 case PCI_MODE_PCI_66:
903 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
541ae68f
K		 904 break;
905 case PCI_MODE_PCIX_M1_66:
906 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
541ae68f
K		 907 break;
908 case PCI_MODE_PCIX_M1_100:
909 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
541ae68f
K		 910 break;
911 case PCI_MODE_PCIX_M1_133:
912 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
541ae68f
K		 913 break;
914 case PCI_MODE_PCIX_M2_66:
915 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
541ae68f
K		 916 break;
917 case PCI_MODE_PCIX_M2_100:
918 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
541ae68f
K		 919 break;
920 case PCI_MODE_PCIX_M2_133:
921 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
541ae68f
K		 922 break;
923 default:
924 return -1; /* Unsupported bus speed */
925 }
926
927 return mode;
928}
929
20346722
K		 930/**
931 * init_nic - Initialization of hardware
1da177e4 932 * @nic: device peivate variable
20346722
K		 933 * Description: The function sequentially configures every block
934 * of the H/W from their reset values.
935 * Return Value: SUCCESS on success and
1da177e4
LT		 936 * '-1' on failure (endian settings incorrect).
937 */
938
939static int init_nic(struct s2io_nic *nic)
940{
1ee6dd77 941 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 942 struct net_device *dev = nic->dev;
943 register u64 val64 = 0;
944 void __iomem *add;
945 u32 time;
946 int i, j;
1ee6dd77 947 struct mac_info *mac_control;
1da177e4 948 struct config_param *config;
c92ca04b 949 int dtx_cnt = 0;
1da177e4 950 unsigned long long mem_share;
20346722 951 int mem_size;
1da177e4
LT		 952
953 mac_control = &nic->mac_control;
954 config = &nic->config;
955
5e25b9dd 956 /* to set the swapper controle on the card */
20346722 957 if(s2io_set_swapper(nic)) {
1da177e4
LT		 958 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
959 return -1;
960 }
961
541ae68f
K		 962 /*
963 * Herc requires EOI to be removed from reset before XGXS, so..
964 */
965 if (nic->device_type & XFRAME_II_DEVICE) {
966 val64 = 0xA500000000ULL;
967 writeq(val64, &bar0->sw_reset);
968 msleep(500);
969 val64 = readq(&bar0->sw_reset);
970 }
971
1da177e4
LT		 972 /* Remove XGXS from reset state */
973 val64 = 0;
974 writeq(val64, &bar0->sw_reset);
1da177e4 975 msleep(500);
20346722 976 val64 = readq(&bar0->sw_reset);
1da177e4
LT		 977
978 /* Enable Receiving broadcasts */
979 add = &bar0->mac_cfg;
980 val64 = readq(&bar0->mac_cfg);
981 val64 |= MAC_RMAC_BCAST_ENABLE;
982 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
983 writel((u32) val64, add);
984 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
985 writel((u32) (val64 >> 32), (add + 4));
986
987 /* Read registers in all blocks */
988 val64 = readq(&bar0->mac_int_mask);
989 val64 = readq(&bar0->mc_int_mask);
990 val64 = readq(&bar0->xgxs_int_mask);
991
992 /* Set MTU */
993 val64 = dev->mtu;
994 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
995
541ae68f
K		 996 if (nic->device_type & XFRAME_II_DEVICE) {
997 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
303bcb4b 998 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1da177e4 999 &bar0->dtx_control, UF);
541ae68f
K		 1000 if (dtx_cnt & 0x1)
1001 msleep(1); /* Necessary!! */
1da177e4
LT		 1002 dtx_cnt++;
1003 }
541ae68f 1004 } else {
c92ca04b
AR		 1005 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1006 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1007 &bar0->dtx_control, UF);
1008 val64 = readq(&bar0->dtx_control);
1009 dtx_cnt++;
1da177e4
LT		 1010 }
1011 }
1012
1013 /* Tx DMA Initialization */
1014 val64 = 0;
1015 writeq(val64, &bar0->tx_fifo_partition_0);
1016 writeq(val64, &bar0->tx_fifo_partition_1);
1017 writeq(val64, &bar0->tx_fifo_partition_2);
1018 writeq(val64, &bar0->tx_fifo_partition_3);
1019
1020
1021 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1022 val64 |=
1023 vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
1024 13) | vBIT(config->tx_cfg[i].fifo_priority,
1025 ((i * 32) + 5), 3);
1026
1027 if (i == (config->tx_fifo_num - 1)) {
1028 if (i % 2 == 0)
1029 i++;
1030 }
1031
1032 switch (i) {
1033 case 1:
1034 writeq(val64, &bar0->tx_fifo_partition_0);
1035 val64 = 0;
1036 break;
1037 case 3:
1038 writeq(val64, &bar0->tx_fifo_partition_1);
1039 val64 = 0;
1040 break;
1041 case 5:
1042 writeq(val64, &bar0->tx_fifo_partition_2);
1043 val64 = 0;
1044 break;
1045 case 7:
1046 writeq(val64, &bar0->tx_fifo_partition_3);
1047 break;
1048 }
1049 }
1050
5e25b9dd
K		 1051 /*
1052 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1053 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1054 */
541ae68f
K		 1055 if ((nic->device_type == XFRAME_I_DEVICE) &&
1056 (get_xena_rev_id(nic->pdev) < 4))
5e25b9dd
K		 1057 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1058
1da177e4
LT		 1059 val64 = readq(&bar0->tx_fifo_partition_0);
1060 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1061 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1062
20346722
K		 1063 /*
1064 * Initialization of Tx_PA_CONFIG register to ignore packet
1da177e4
LT		 1065 * integrity checking.
1066 */
1067 val64 = readq(&bar0->tx_pa_cfg);
1068 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1069 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1070 writeq(val64, &bar0->tx_pa_cfg);
1071
1072 /* Rx DMA intialization. */
1073 val64 = 0;
1074 for (i = 0; i < config->rx_ring_num; i++) {
1075 val64 |=
1076 vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1077 3);
1078 }
1079 writeq(val64, &bar0->rx_queue_priority);
1080
20346722
K		 1081 /*
1082 * Allocating equal share of memory to all the
1da177e4
LT		 1083 * configured Rings.
1084 */
1085 val64 = 0;
541ae68f
K		 1086 if (nic->device_type & XFRAME_II_DEVICE)
1087 mem_size = 32;
1088 else
1089 mem_size = 64;
1090
1da177e4
LT		 1091 for (i = 0; i < config->rx_ring_num; i++) {
1092 switch (i) {
1093 case 0:
20346722
K		 1094 mem_share = (mem_size / config->rx_ring_num +
1095 mem_size % config->rx_ring_num);
1da177e4
LT		 1096 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1097 continue;
1098 case 1:
20346722 1099 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1100 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1101 continue;
1102 case 2:
20346722 1103 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1104 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1105 continue;
1106 case 3:
20346722 1107 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1108 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1109 continue;
1110 case 4:
20346722 1111 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1112 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1113 continue;
1114 case 5:
20346722 1115 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1116 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1117 continue;
1118 case 6:
20346722 1119 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1120 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1121 continue;
1122 case 7:
20346722 1123 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1124 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1125 continue;
1126 }
1127 }
1128 writeq(val64, &bar0->rx_queue_cfg);
1129
20346722 1130 /*
5e25b9dd
K		 1131 * Filling Tx round robin registers
1132 * as per the number of FIFOs
1da177e4 1133 */
5e25b9dd
K		 1134 switch (config->tx_fifo_num) {
1135 case 1:
1136 val64 = 0x0000000000000000ULL;
1137 writeq(val64, &bar0->tx_w_round_robin_0);
1138 writeq(val64, &bar0->tx_w_round_robin_1);
1139 writeq(val64, &bar0->tx_w_round_robin_2);
1140 writeq(val64, &bar0->tx_w_round_robin_3);
1141 writeq(val64, &bar0->tx_w_round_robin_4);
1142 break;
1143 case 2:
1144 val64 = 0x0000010000010000ULL;
1145 writeq(val64, &bar0->tx_w_round_robin_0);
1146 val64 = 0x0100000100000100ULL;
1147 writeq(val64, &bar0->tx_w_round_robin_1);
1148 val64 = 0x0001000001000001ULL;
1149 writeq(val64, &bar0->tx_w_round_robin_2);
1150 val64 = 0x0000010000010000ULL;
1151 writeq(val64, &bar0->tx_w_round_robin_3);
1152 val64 = 0x0100000000000000ULL;
1153 writeq(val64, &bar0->tx_w_round_robin_4);
1154 break;
1155 case 3:
1156 val64 = 0x0001000102000001ULL;
1157 writeq(val64, &bar0->tx_w_round_robin_0);
1158 val64 = 0x0001020000010001ULL;
1159 writeq(val64, &bar0->tx_w_round_robin_1);
1160 val64 = 0x0200000100010200ULL;
1161 writeq(val64, &bar0->tx_w_round_robin_2);
1162 val64 = 0x0001000102000001ULL;
1163 writeq(val64, &bar0->tx_w_round_robin_3);
1164 val64 = 0x0001020000000000ULL;
1165 writeq(val64, &bar0->tx_w_round_robin_4);
1166 break;
1167 case 4:
1168 val64 = 0x0001020300010200ULL;
1169 writeq(val64, &bar0->tx_w_round_robin_0);
1170 val64 = 0x0100000102030001ULL;
1171 writeq(val64, &bar0->tx_w_round_robin_1);
1172 val64 = 0x0200010000010203ULL;
1173 writeq(val64, &bar0->tx_w_round_robin_2);
1174 val64 = 0x0001020001000001ULL;
1175 writeq(val64, &bar0->tx_w_round_robin_3);
1176 val64 = 0x0203000100000000ULL;
1177 writeq(val64, &bar0->tx_w_round_robin_4);
1178 break;
1179 case 5:
1180 val64 = 0x0001000203000102ULL;
1181 writeq(val64, &bar0->tx_w_round_robin_0);
1182 val64 = 0x0001020001030004ULL;
1183 writeq(val64, &bar0->tx_w_round_robin_1);
1184 val64 = 0x0001000203000102ULL;
1185 writeq(val64, &bar0->tx_w_round_robin_2);
1186 val64 = 0x0001020001030004ULL;
1187 writeq(val64, &bar0->tx_w_round_robin_3);
1188 val64 = 0x0001000000000000ULL;
1189 writeq(val64, &bar0->tx_w_round_robin_4);
1190 break;
1191 case 6:
1192 val64 = 0x0001020304000102ULL;
1193 writeq(val64, &bar0->tx_w_round_robin_0);
1194 val64 = 0x0304050001020001ULL;
1195 writeq(val64, &bar0->tx_w_round_robin_1);
1196 val64 = 0x0203000100000102ULL;
1197 writeq(val64, &bar0->tx_w_round_robin_2);
1198 val64 = 0x0304000102030405ULL;
1199 writeq(val64, &bar0->tx_w_round_robin_3);
1200 val64 = 0x0001000200000000ULL;
1201 writeq(val64, &bar0->tx_w_round_robin_4);
1202 break;
1203 case 7:
1204 val64 = 0x0001020001020300ULL;
1205 writeq(val64, &bar0->tx_w_round_robin_0);
1206 val64 = 0x0102030400010203ULL;
1207 writeq(val64, &bar0->tx_w_round_robin_1);
1208 val64 = 0x0405060001020001ULL;
1209 writeq(val64, &bar0->tx_w_round_robin_2);
1210 val64 = 0x0304050000010200ULL;
1211 writeq(val64, &bar0->tx_w_round_robin_3);
1212 val64 = 0x0102030000000000ULL;
1213 writeq(val64, &bar0->tx_w_round_robin_4);
1214 break;
1215 case 8:
1216 val64 = 0x0001020300040105ULL;
1217 writeq(val64, &bar0->tx_w_round_robin_0);
1218 val64 = 0x0200030106000204ULL;
1219 writeq(val64, &bar0->tx_w_round_robin_1);
1220 val64 = 0x0103000502010007ULL;
1221 writeq(val64, &bar0->tx_w_round_robin_2);
1222 val64 = 0x0304010002060500ULL;
1223 writeq(val64, &bar0->tx_w_round_robin_3);
1224 val64 = 0x0103020400000000ULL;
1225 writeq(val64, &bar0->tx_w_round_robin_4);
1226 break;
1227 }
1228
b41477f3 1229 /* Enable all configured Tx FIFO partitions */
5d3213cc
AR		 1230 val64 = readq(&bar0->tx_fifo_partition_0);
1231 val64 |= (TX_FIFO_PARTITION_EN);
1232 writeq(val64, &bar0->tx_fifo_partition_0);
1233
5e25b9dd
K		 1234 /* Filling the Rx round robin registers as per the
1235 * number of Rings and steering based on QoS.
1236 */
1237 switch (config->rx_ring_num) {
1238 case 1:
1239 val64 = 0x8080808080808080ULL;
1240 writeq(val64, &bar0->rts_qos_steering);
1241 break;
1242 case 2:
1243 val64 = 0x0000010000010000ULL;
1244 writeq(val64, &bar0->rx_w_round_robin_0);
1245 val64 = 0x0100000100000100ULL;
1246 writeq(val64, &bar0->rx_w_round_robin_1);
1247 val64 = 0x0001000001000001ULL;
1248 writeq(val64, &bar0->rx_w_round_robin_2);
1249 val64 = 0x0000010000010000ULL;
1250 writeq(val64, &bar0->rx_w_round_robin_3);
1251 val64 = 0x0100000000000000ULL;
1252 writeq(val64, &bar0->rx_w_round_robin_4);
1253
1254 val64 = 0x8080808040404040ULL;
1255 writeq(val64, &bar0->rts_qos_steering);
1256 break;
1257 case 3:
1258 val64 = 0x0001000102000001ULL;
1259 writeq(val64, &bar0->rx_w_round_robin_0);
1260 val64 = 0x0001020000010001ULL;
1261 writeq(val64, &bar0->rx_w_round_robin_1);
1262 val64 = 0x0200000100010200ULL;
1263 writeq(val64, &bar0->rx_w_round_robin_2);
1264 val64 = 0x0001000102000001ULL;
1265 writeq(val64, &bar0->rx_w_round_robin_3);
1266 val64 = 0x0001020000000000ULL;
1267 writeq(val64, &bar0->rx_w_round_robin_4);
1268
1269 val64 = 0x8080804040402020ULL;
1270 writeq(val64, &bar0->rts_qos_steering);
1271 break;
1272 case 4:
1273 val64 = 0x0001020300010200ULL;
1274 writeq(val64, &bar0->rx_w_round_robin_0);
1275 val64 = 0x0100000102030001ULL;
1276 writeq(val64, &bar0->rx_w_round_robin_1);
1277 val64 = 0x0200010000010203ULL;
1278 writeq(val64, &bar0->rx_w_round_robin_2);
6aa20a22 1279 val64 = 0x0001020001000001ULL;
5e25b9dd
K		 1280 writeq(val64, &bar0->rx_w_round_robin_3);
1281 val64 = 0x0203000100000000ULL;
1282 writeq(val64, &bar0->rx_w_round_robin_4);
1283
1284 val64 = 0x8080404020201010ULL;
1285 writeq(val64, &bar0->rts_qos_steering);
1286 break;
1287 case 5:
1288 val64 = 0x0001000203000102ULL;
1289 writeq(val64, &bar0->rx_w_round_robin_0);
1290 val64 = 0x0001020001030004ULL;
1291 writeq(val64, &bar0->rx_w_round_robin_1);
1292 val64 = 0x0001000203000102ULL;
1293 writeq(val64, &bar0->rx_w_round_robin_2);
1294 val64 = 0x0001020001030004ULL;
1295 writeq(val64, &bar0->rx_w_round_robin_3);
1296 val64 = 0x0001000000000000ULL;
1297 writeq(val64, &bar0->rx_w_round_robin_4);
1298
1299 val64 = 0x8080404020201008ULL;
1300 writeq(val64, &bar0->rts_qos_steering);
1301 break;
1302 case 6:
1303 val64 = 0x0001020304000102ULL;
1304 writeq(val64, &bar0->rx_w_round_robin_0);
1305 val64 = 0x0304050001020001ULL;
1306 writeq(val64, &bar0->rx_w_round_robin_1);
1307 val64 = 0x0203000100000102ULL;
1308 writeq(val64, &bar0->rx_w_round_robin_2);
1309 val64 = 0x0304000102030405ULL;
1310 writeq(val64, &bar0->rx_w_round_robin_3);
1311 val64 = 0x0001000200000000ULL;
1312 writeq(val64, &bar0->rx_w_round_robin_4);
1313
1314 val64 = 0x8080404020100804ULL;
1315 writeq(val64, &bar0->rts_qos_steering);
1316 break;
1317 case 7:
1318 val64 = 0x0001020001020300ULL;
1319 writeq(val64, &bar0->rx_w_round_robin_0);
1320 val64 = 0x0102030400010203ULL;
1321 writeq(val64, &bar0->rx_w_round_robin_1);
1322 val64 = 0x0405060001020001ULL;
1323 writeq(val64, &bar0->rx_w_round_robin_2);
1324 val64 = 0x0304050000010200ULL;
1325 writeq(val64, &bar0->rx_w_round_robin_3);
1326 val64 = 0x0102030000000000ULL;
1327 writeq(val64, &bar0->rx_w_round_robin_4);
1328
1329 val64 = 0x8080402010080402ULL;
1330 writeq(val64, &bar0->rts_qos_steering);
1331 break;
1332 case 8:
1333 val64 = 0x0001020300040105ULL;
1334 writeq(val64, &bar0->rx_w_round_robin_0);
1335 val64 = 0x0200030106000204ULL;
1336 writeq(val64, &bar0->rx_w_round_robin_1);
1337 val64 = 0x0103000502010007ULL;
1338 writeq(val64, &bar0->rx_w_round_robin_2);
1339 val64 = 0x0304010002060500ULL;
1340 writeq(val64, &bar0->rx_w_round_robin_3);
1341 val64 = 0x0103020400000000ULL;
1342 writeq(val64, &bar0->rx_w_round_robin_4);
1343
1344 val64 = 0x8040201008040201ULL;
1345 writeq(val64, &bar0->rts_qos_steering);
1346 break;
1347 }
1da177e4
LT		 1348
1349 /* UDP Fix */
1350 val64 = 0;
20346722 1351 for (i = 0; i < 8; i++)
1da177e4
LT		 1352 writeq(val64, &bar0->rts_frm_len_n[i]);
1353
5e25b9dd
K		 1354 /* Set the default rts frame length for the rings configured */
1355 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1356 for (i = 0 ; i < config->rx_ring_num ; i++)
1357 writeq(val64, &bar0->rts_frm_len_n[i]);
1358
1359 /* Set the frame length for the configured rings
1360 * desired by the user
1361 */
1362 for (i = 0; i < config->rx_ring_num; i++) {
1363 /* If rts_frm_len[i] == 0 then it is assumed that user not
1364 * specified frame length steering.
1365 * If the user provides the frame length then program
1366 * the rts_frm_len register for those values or else
1367 * leave it as it is.
1368 */
1369 if (rts_frm_len[i] != 0) {
1370 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1371 &bar0->rts_frm_len_n[i]);
1372 }
1373 }
1da177e4 1374
20346722 1375 /* Program statistics memory */
1da177e4 1376 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1da177e4 1377
541ae68f
K		 1378 if (nic->device_type == XFRAME_II_DEVICE) {
1379 val64 = STAT_BC(0x320);
1380 writeq(val64, &bar0->stat_byte_cnt);
1381 }
1382
20346722 1383 /*
1da177e4
LT		 1384 * Initializing the sampling rate for the device to calculate the
1385 * bandwidth utilization.
1386 */
1387 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1388 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1389 writeq(val64, &bar0->mac_link_util);
1390
1391
20346722
K		 1392 /*
1393 * Initializing the Transmit and Receive Traffic Interrupt
1da177e4
LT		 1394 * Scheme.
1395 */
20346722
K		 1396 /*
1397 * TTI Initialization. Default Tx timer gets us about
1da177e4
LT		 1398 * 250 interrupts per sec. Continuous interrupts are enabled
1399 * by default.
1400 */
541ae68f
K		 1401 if (nic->device_type == XFRAME_II_DEVICE) {
1402 int count = (nic->config.bus_speed * 125)/2;
1403 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1404 } else {
1405
1406 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1407 }
1408 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1da177e4 1409 TTI_DATA1_MEM_TX_URNG_B(0x10) |
5e25b9dd 1410 TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
541ae68f
K		 1411 if (use_continuous_tx_intrs)
1412 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1da177e4
LT		 1413 writeq(val64, &bar0->tti_data1_mem);
1414
1415 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1416 TTI_DATA2_MEM_TX_UFC_B(0x20) |
19a60522 1417 TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1da177e4
LT		 1418 writeq(val64, &bar0->tti_data2_mem);
1419
1420 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1421 writeq(val64, &bar0->tti_command_mem);
1422
20346722 1423 /*
1da177e4
LT		 1424 * Once the operation completes, the Strobe bit of the command
1425 * register will be reset. We poll for this particular condition
1426 * We wait for a maximum of 500ms for the operation to complete,
1427 * if it's not complete by then we return error.
1428 */
1429 time = 0;
1430 while (TRUE) {
1431 val64 = readq(&bar0->tti_command_mem);
1432 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1433 break;
1434 }
1435 if (time > 10) {
1436 DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1437 dev->name);
1438 return -1;
1439 }
1440 msleep(50);
1441 time++;
1442 }
1443
b6e3f982
K		 1444 if (nic->config.bimodal) {
1445 int k = 0;
1446 for (k = 0; k < config->rx_ring_num; k++) {
1447 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1448 val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1449 writeq(val64, &bar0->tti_command_mem);
541ae68f 1450
541ae68f 1451 /*
b6e3f982
K		 1452 * Once the operation completes, the Strobe bit of the command
1453 * register will be reset. We poll for this particular condition
1454 * We wait for a maximum of 500ms for the operation to complete,
1455 * if it's not complete by then we return error.
1456 */
1457 time = 0;
1458 while (TRUE) {
1459 val64 = readq(&bar0->tti_command_mem);
1460 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1461 break;
1462 }
1463 if (time > 10) {
1464 DBG_PRINT(ERR_DBG,
1465 "%s: TTI init Failed\n",
1466 dev->name);
1467 return -1;
1468 }
1469 time++;
1470 msleep(50);
1471 }
1472 }
541ae68f 1473 } else {
1da177e4 1474
b6e3f982
K		 1475 /* RTI Initialization */
1476 if (nic->device_type == XFRAME_II_DEVICE) {
1477 /*
1478 * Programmed to generate Apprx 500 Intrs per
1479 * second
1480 */
1481 int count = (nic->config.bus_speed * 125)/4;
1482 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1483 } else {
1484 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1485 }
1486 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1487 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1488 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1da177e4 1489
b6e3f982 1490 writeq(val64, &bar0->rti_data1_mem);
1da177e4 1491
b6e3f982 1492 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
cc6e7c44
RA		 1493 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1494 if (nic->intr_type == MSI_X)
1495 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1496 RTI_DATA2_MEM_RX_UFC_D(0x40));
1497 else
1498 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1499 RTI_DATA2_MEM_RX_UFC_D(0x80));
b6e3f982 1500 writeq(val64, &bar0->rti_data2_mem);
1da177e4 1501
b6e3f982
K		 1502 for (i = 0; i < config->rx_ring_num; i++) {
1503 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1504 | RTI_CMD_MEM_OFFSET(i);
1505 writeq(val64, &bar0->rti_command_mem);
1506
1507 /*
1508 * Once the operation completes, the Strobe bit of the
1509 * command register will be reset. We poll for this
1510 * particular condition. We wait for a maximum of 500ms
1511 * for the operation to complete, if it's not complete
1512 * by then we return error.
1513 */
1514 time = 0;
1515 while (TRUE) {
1516 val64 = readq(&bar0->rti_command_mem);
1517 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1518 break;
1519 }
1520 if (time > 10) {
1521 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1522 dev->name);
1523 return -1;
1524 }
1525 time++;
1526 msleep(50);
1527 }
1da177e4 1528 }
1da177e4
LT		 1529 }
1530
20346722
K		 1531 /*
1532 * Initializing proper values as Pause threshold into all
1da177e4
LT		 1533 * the 8 Queues on Rx side.
1534 */
1535 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1536 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1537
1538 /* Disable RMAC PAD STRIPPING */
509a2671 1539 add = &bar0->mac_cfg;
1da177e4
LT		 1540 val64 = readq(&bar0->mac_cfg);
1541 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1542 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1543 writel((u32) (val64), add);
1544 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1545 writel((u32) (val64 >> 32), (add + 4));
1546 val64 = readq(&bar0->mac_cfg);
1547
7d3d0439
RA		 1548 /* Enable FCS stripping by adapter */
1549 add = &bar0->mac_cfg;
1550 val64 = readq(&bar0->mac_cfg);
1551 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1552 if (nic->device_type == XFRAME_II_DEVICE)
1553 writeq(val64, &bar0->mac_cfg);
1554 else {
1555 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1556 writel((u32) (val64), add);
1557 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1558 writel((u32) (val64 >> 32), (add + 4));
1559 }
1560
20346722
K		 1561 /*
1562 * Set the time value to be inserted in the pause frame
1da177e4
LT		 1563 * generated by xena.
1564 */
1565 val64 = readq(&bar0->rmac_pause_cfg);
1566 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1567 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1568 writeq(val64, &bar0->rmac_pause_cfg);
1569
20346722 1570 /*
1da177e4
LT		 1571 * Set the Threshold Limit for Generating the pause frame
1572 * If the amount of data in any Queue exceeds ratio of
1573 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1574 * pause frame is generated
1575 */
1576 val64 = 0;
1577 for (i = 0; i < 4; i++) {
1578 val64 |=
1579 (((u64) 0xFF00 | nic->mac_control.
1580 mc_pause_threshold_q0q3)
1581 << (i * 2 * 8));
1582 }
1583 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1584
1585 val64 = 0;
1586 for (i = 0; i < 4; i++) {
1587 val64 |=
1588 (((u64) 0xFF00 | nic->mac_control.
1589 mc_pause_threshold_q4q7)
1590 << (i * 2 * 8));
1591 }
1592 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1593
20346722
K		 1594 /*
1595 * TxDMA will stop Read request if the number of read split has
1da177e4
LT		 1596 * exceeded the limit pointed by shared_splits
1597 */
1598 val64 = readq(&bar0->pic_control);
1599 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1600 writeq(val64, &bar0->pic_control);
1601
863c11a9
AR		 1602 if (nic->config.bus_speed == 266) {
1603 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1604 writeq(0x0, &bar0->read_retry_delay);
1605 writeq(0x0, &bar0->write_retry_delay);
1606 }
1607
541ae68f
K		 1608 /*
1609 * Programming the Herc to split every write transaction
1610 * that does not start on an ADB to reduce disconnects.
1611 */
1612 if (nic->device_type == XFRAME_II_DEVICE) {
19a60522
SS		 1613 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1614 MISC_LINK_STABILITY_PRD(3);
863c11a9
AR		 1615 writeq(val64, &bar0->misc_control);
1616 val64 = readq(&bar0->pic_control2);
1617 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
1618 writeq(val64, &bar0->pic_control2);
541ae68f 1619 }
c92ca04b
AR		 1620 if (strstr(nic->product_name, "CX4")) {
1621 val64 = TMAC_AVG_IPG(0x17);
1622 writeq(val64, &bar0->tmac_avg_ipg);
a371a07d
K		 1623 }
1624
1da177e4
LT		 1625 return SUCCESS;
1626}
a371a07d
K		 1627#define LINK_UP_DOWN_INTERRUPT 1
1628#define MAC_RMAC_ERR_TIMER 2
1629
1ee6dd77 1630static int s2io_link_fault_indication(struct s2io_nic *nic)
a371a07d 1631{
cc6e7c44
RA		 1632 if (nic->intr_type != INTA)
1633 return MAC_RMAC_ERR_TIMER;
a371a07d
K		 1634 if (nic->device_type == XFRAME_II_DEVICE)
1635 return LINK_UP_DOWN_INTERRUPT;
1636 else
1637 return MAC_RMAC_ERR_TIMER;
1638}
1da177e4 1639
20346722
K		 1640/**
1641 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1da177e4
LT		 1642 * @nic: device private variable,
1643 * @mask: A mask indicating which Intr block must be modified and,
1644 * @flag: A flag indicating whether to enable or disable the Intrs.
1645 * Description: This function will either disable or enable the interrupts
20346722
K		 1646 * depending on the flag argument. The mask argument can be used to
1647 * enable/disable any Intr block.
1da177e4
LT		 1648 * Return Value: NONE.
1649 */
1650
1651static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1652{
1ee6dd77 1653 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1654 register u64 val64 = 0, temp64 = 0;
1655
1656 /* Top level interrupt classification */
1657 /* PIC Interrupts */
1658 if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1659 /* Enable PIC Intrs in the general intr mask register */
a113ae06 1660 val64 = TXPIC_INT_M;
1da177e4
LT		 1661 if (flag == ENABLE_INTRS) {
1662 temp64 = readq(&bar0->general_int_mask);
1663 temp64 &= ~((u64) val64);
1664 writeq(temp64, &bar0->general_int_mask);
20346722 1665 /*
a371a07d 1666 * If Hercules adapter enable GPIO otherwise
b41477f3 1667 * disable all PCIX, Flash, MDIO, IIC and GPIO
20346722
K		 1668 * interrupts for now.
1669 * TODO
1da177e4 1670 */
a371a07d
K		 1671 if (s2io_link_fault_indication(nic) ==
1672 LINK_UP_DOWN_INTERRUPT ) {
1673 temp64 = readq(&bar0->pic_int_mask);
1674 temp64 &= ~((u64) PIC_INT_GPIO);
1675 writeq(temp64, &bar0->pic_int_mask);
1676 temp64 = readq(&bar0->gpio_int_mask);
1677 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1678 writeq(temp64, &bar0->gpio_int_mask);
1679 } else {
1680 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1681 }
20346722 1682 /*
1da177e4
LT		 1683 * No MSI Support is available presently, so TTI and
1684 * RTI interrupts are also disabled.
1685 */
1686 } else if (flag == DISABLE_INTRS) {
20346722
K		 1687 /*
1688 * Disable PIC Intrs in the general
1689 * intr mask register
1da177e4
LT		 1690 */
1691 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1692 temp64 = readq(&bar0->general_int_mask);
1693 val64 |= temp64;
1694 writeq(val64, &bar0->general_int_mask);
1695 }
1696 }
1697
1da177e4
LT		 1698 /* MAC Interrupts */
1699 /* Enabling/Disabling MAC interrupts */
1700 if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1701 val64 = TXMAC_INT_M | RXMAC_INT_M;
1702 if (flag == ENABLE_INTRS) {
1703 temp64 = readq(&bar0->general_int_mask);
1704 temp64 &= ~((u64) val64);
1705 writeq(temp64, &bar0->general_int_mask);
20346722
K		 1706 /*
1707 * All MAC block error interrupts are disabled for now
1da177e4
LT		 1708 * TODO
1709 */
1da177e4 1710 } else if (flag == DISABLE_INTRS) {
20346722
K		 1711 /*
1712 * Disable MAC Intrs in the general intr mask register
1da177e4
LT		 1713 */
1714 writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1715 writeq(DISABLE_ALL_INTRS,
1716 &bar0->mac_rmac_err_mask);
1717
1718 temp64 = readq(&bar0->general_int_mask);
1719 val64 |= temp64;
1720 writeq(val64, &bar0->general_int_mask);
1721 }
1722 }
1723
1da177e4
LT		 1724 /* Tx traffic interrupts */
1725 if (mask & TX_TRAFFIC_INTR) {
1726 val64 = TXTRAFFIC_INT_M;
1727 if (flag == ENABLE_INTRS) {
1728 temp64 = readq(&bar0->general_int_mask);
1729 temp64 &= ~((u64) val64);
1730 writeq(temp64, &bar0->general_int_mask);
20346722 1731 /*
1da177e4 1732 * Enable all the Tx side interrupts
20346722 1733 * writing 0 Enables all 64 TX interrupt levels
1da177e4
LT		 1734 */
1735 writeq(0x0, &bar0->tx_traffic_mask);
1736 } else if (flag == DISABLE_INTRS) {
20346722
K		 1737 /*
1738 * Disable Tx Traffic Intrs in the general intr mask
1da177e4
LT		 1739 * register.
1740 */
1741 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1742 temp64 = readq(&bar0->general_int_mask);
1743 val64 |= temp64;
1744 writeq(val64, &bar0->general_int_mask);
1745 }
1746 }
1747
1748 /* Rx traffic interrupts */
1749 if (mask & RX_TRAFFIC_INTR) {
1750 val64 = RXTRAFFIC_INT_M;
1751 if (flag == ENABLE_INTRS) {
1752 temp64 = readq(&bar0->general_int_mask);
1753 temp64 &= ~((u64) val64);
1754 writeq(temp64, &bar0->general_int_mask);
1755 /* writing 0 Enables all 8 RX interrupt levels */
1756 writeq(0x0, &bar0->rx_traffic_mask);
1757 } else if (flag == DISABLE_INTRS) {
20346722
K		 1758 /*
1759 * Disable Rx Traffic Intrs in the general intr mask
1da177e4
LT		 1760 * register.
1761 */
1762 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1763 temp64 = readq(&bar0->general_int_mask);
1764 val64 |= temp64;
1765 writeq(val64, &bar0->general_int_mask);
1766 }
1767 }
1768}
1769
19a60522
SS		 1770/**
1771 * verify_pcc_quiescent- Checks for PCC quiescent state
1772 * Return: 1 If PCC is quiescence
1773 * 0 If PCC is not quiescence
1774 */
1ee6dd77 1775static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
20346722 1776{
19a60522 1777 int ret = 0, herc;
1ee6dd77 1778 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 1779 u64 val64 = readq(&bar0->adapter_status);
1780
1781 herc = (sp->device_type == XFRAME_II_DEVICE);
20346722
K		 1782
1783 if (flag == FALSE) {
19a60522
SS		 1784 if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) {
1785 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 1786 ret = 1;
19a60522
SS		 1787 } else {
1788 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 1789 ret = 1;
20346722
K		 1790 }
1791 } else {
19a60522 1792 if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) {
5e25b9dd 1793 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
19a60522 1794 ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 1795 ret = 1;
5e25b9dd
K		 1796 } else {
1797 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
19a60522 1798 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 1799 ret = 1;
20346722
K		 1800 }
1801 }
1802
1803 return ret;
1804}
1805/**
1806 * verify_xena_quiescence - Checks whether the H/W is ready
1da177e4 1807 * Description: Returns whether the H/W is ready to go or not. Depending
20346722 1808 * on whether adapter enable bit was written or not the comparison
1da177e4
LT		 1809 * differs and the calling function passes the input argument flag to
1810 * indicate this.
20346722 1811 * Return: 1 If xena is quiescence
1da177e4
LT		 1812 * 0 If Xena is not quiescence
1813 */
1814
1ee6dd77 1815static int verify_xena_quiescence(struct s2io_nic *sp)
1da177e4 1816{
19a60522 1817 int mode;
1ee6dd77 1818 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 1819 u64 val64 = readq(&bar0->adapter_status);
1820 mode = s2io_verify_pci_mode(sp);
1da177e4 1821
19a60522
SS		 1822 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
1823 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
1824 return 0;
1825 }
1826 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
1827 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
1828 return 0;
1829 }
1830 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
1831 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
1832 return 0;
1833 }
1834 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
1835 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
1836 return 0;
1837 }
1838 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
1839 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
1840 return 0;
1841 }
1842 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
1843 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
1844 return 0;
1845 }
1846 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
1847 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
1848 return 0;
1849 }
1850 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
1851 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
1852 return 0;
1da177e4
LT		 1853 }
1854
19a60522
SS		 1855 /*
1856 * In PCI 33 mode, the P_PLL is not used, and therefore,
1857 * the the P_PLL_LOCK bit in the adapter_status register will
1858 * not be asserted.
1859 */
1860 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
1861 sp->device_type == XFRAME_II_DEVICE && mode !=
1862 PCI_MODE_PCI_33) {
1863 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
1864 return 0;
1865 }
1866 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1867 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1868 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
1869 return 0;
1870 }
1871 return 1;
1da177e4
LT		 1872}
1873
1874/**
1875 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
1876 * @sp: Pointer to device specifc structure
20346722 1877 * Description :
1da177e4
LT		 1878 * New procedure to clear mac address reading problems on Alpha platforms
1879 *
1880 */
1881
1ee6dd77 1882static void fix_mac_address(struct s2io_nic * sp)
1da177e4 1883{
1ee6dd77 1884 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 1885 u64 val64;
1886 int i = 0;
1887
1888 while (fix_mac[i] != END_SIGN) {
1889 writeq(fix_mac[i++], &bar0->gpio_control);
20346722 1890 udelay(10);
1da177e4
LT		 1891 val64 = readq(&bar0->gpio_control);
1892 }
1893}
1894
1895/**
20346722 1896 * start_nic - Turns the device on
1da177e4 1897 * @nic : device private variable.
20346722
K		 1898 * Description:
1899 * This function actually turns the device on. Before this function is
1900 * called,all Registers are configured from their reset states
1901 * and shared memory is allocated but the NIC is still quiescent. On
1da177e4
LT		 1902 * calling this function, the device interrupts are cleared and the NIC is
1903 * literally switched on by writing into the adapter control register.
20346722 1904 * Return Value:
1da177e4
LT		 1905 * SUCCESS on success and -1 on failure.
1906 */
1907
1908static int start_nic(struct s2io_nic *nic)
1909{
1ee6dd77 1910 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1911 struct net_device *dev = nic->dev;
1912 register u64 val64 = 0;
20346722 1913 u16 subid, i;
1ee6dd77 1914 struct mac_info *mac_control;
1da177e4
LT		 1915 struct config_param *config;
1916
1917 mac_control = &nic->mac_control;
1918 config = &nic->config;
1919
1920 /* PRC Initialization and configuration */
1921 for (i = 0; i < config->rx_ring_num; i++) {
20346722 1922 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
1da177e4
LT		 1923 &bar0->prc_rxd0_n[i]);
1924
1925 val64 = readq(&bar0->prc_ctrl_n[i]);
b6e3f982
K		 1926 if (nic->config.bimodal)
1927 val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
da6971d8
AR		 1928 if (nic->rxd_mode == RXD_MODE_1)
1929 val64 |= PRC_CTRL_RC_ENABLED;
1930 else
1931 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
863c11a9
AR		 1932 if (nic->device_type == XFRAME_II_DEVICE)
1933 val64 |= PRC_CTRL_GROUP_READS;
1934 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
1935 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1da177e4
LT		 1936 writeq(val64, &bar0->prc_ctrl_n[i]);
1937 }
1938
da6971d8
AR		 1939 if (nic->rxd_mode == RXD_MODE_3B) {
1940 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
1941 val64 = readq(&bar0->rx_pa_cfg);
1942 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
1943 writeq(val64, &bar0->rx_pa_cfg);
1944 }
1da177e4 1945
20346722 1946 /*
1da177e4
LT		 1947 * Enabling MC-RLDRAM. After enabling the device, we timeout
1948 * for around 100ms, which is approximately the time required
1949 * for the device to be ready for operation.
1950 */
1951 val64 = readq(&bar0->mc_rldram_mrs);
1952 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
1953 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
1954 val64 = readq(&bar0->mc_rldram_mrs);
1955
20346722 1956 msleep(100); /* Delay by around 100 ms. */
1da177e4
LT		 1957
1958 /* Enabling ECC Protection. */
1959 val64 = readq(&bar0->adapter_control);
1960 val64 &= ~ADAPTER_ECC_EN;
1961 writeq(val64, &bar0->adapter_control);
1962
20346722
K		 1963 /*
1964 * Clearing any possible Link state change interrupts that
1da177e4
LT		 1965 * could have popped up just before Enabling the card.
1966 */
1967 val64 = readq(&bar0->mac_rmac_err_reg);
1968 if (val64)
1969 writeq(val64, &bar0->mac_rmac_err_reg);
1970
20346722
K		 1971 /*
1972 * Verify if the device is ready to be enabled, if so enable
1da177e4
LT		 1973 * it.
1974 */
1975 val64 = readq(&bar0->adapter_status);
19a60522 1976 if (!verify_xena_quiescence(nic)) {
1da177e4
LT		 1977 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
1978 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
1979 (unsigned long long) val64);
1980 return FAILURE;
1981 }
1982
20346722 1983 /*
1da177e4 1984 * With some switches, link might be already up at this point.
20346722
K		 1985 * Because of this weird behavior, when we enable laser,
1986 * we may not get link. We need to handle this. We cannot
1987 * figure out which switch is misbehaving. So we are forced to
1988 * make a global change.
1da177e4
LT		 1989 */
1990
1991 /* Enabling Laser. */
1992 val64 = readq(&bar0->adapter_control);
1993 val64 |= ADAPTER_EOI_TX_ON;
1994 writeq(val64, &bar0->adapter_control);
1995
c92ca04b
AR		 1996 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
1997 /*
1998 * Dont see link state interrupts initally on some switches,
1999 * so directly scheduling the link state task here.
2000 */
2001 schedule_work(&nic->set_link_task);
2002 }
1da177e4
LT		 2003 /* SXE-002: Initialize link and activity LED */
2004 subid = nic->pdev->subsystem_device;
541ae68f
K		 2005 if (((subid & 0xFF) >= 0x07) &&
2006 (nic->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 2007 val64 = readq(&bar0->gpio_control);
2008 val64 |= 0x0000800000000000ULL;
2009 writeq(val64, &bar0->gpio_control);
2010 val64 = 0x0411040400000000ULL;
509a2671 2011 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 2012 }
2013
1da177e4
LT		 2014 return SUCCESS;
2015}
fed5eccd
AR		 2016/**
2017 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2018 */
1ee6dd77
RB		 2019static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2020 TxD *txdlp, int get_off)
fed5eccd 2021{
1ee6dd77 2022 struct s2io_nic *nic = fifo_data->nic;
fed5eccd 2023 struct sk_buff *skb;
1ee6dd77 2024 struct TxD *txds;
fed5eccd
AR		 2025 u16 j, frg_cnt;
2026
2027 txds = txdlp;
26b7625c 2028 if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
fed5eccd
AR		 2029 pci_unmap_single(nic->pdev, (dma_addr_t)
2030 txds->Buffer_Pointer, sizeof(u64),
2031 PCI_DMA_TODEVICE);
2032 txds++;
2033 }
2034
2035 skb = (struct sk_buff *) ((unsigned long)
2036 txds->Host_Control);
2037 if (!skb) {
1ee6dd77 2038 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2039 return NULL;
2040 }
2041 pci_unmap_single(nic->pdev, (dma_addr_t)
2042 txds->Buffer_Pointer,
2043 skb->len - skb->data_len,
2044 PCI_DMA_TODEVICE);
2045 frg_cnt = skb_shinfo(skb)->nr_frags;
2046 if (frg_cnt) {
2047 txds++;
2048 for (j = 0; j < frg_cnt; j++, txds++) {
2049 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2050 if (!txds->Buffer_Pointer)
2051 break;
6aa20a22 2052 pci_unmap_page(nic->pdev, (dma_addr_t)
fed5eccd
AR		 2053 txds->Buffer_Pointer,
2054 frag->size, PCI_DMA_TODEVICE);
2055 }
2056 }
1ee6dd77 2057 memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2058 return(skb);
2059}
1da177e4 2060
20346722
K		 2061/**
2062 * free_tx_buffers - Free all queued Tx buffers
1da177e4 2063 * @nic : device private variable.
20346722 2064 * Description:
1da177e4 2065 * Free all queued Tx buffers.
20346722 2066 * Return Value: void
1da177e4
LT		 2067*/
2068
2069static void free_tx_buffers(struct s2io_nic *nic)
2070{
2071 struct net_device *dev = nic->dev;
2072 struct sk_buff *skb;
1ee6dd77 2073 struct TxD *txdp;
1da177e4 2074 int i, j;
1ee6dd77 2075 struct mac_info *mac_control;
1da177e4 2076 struct config_param *config;
fed5eccd 2077 int cnt = 0;
1da177e4
LT		 2078
2079 mac_control = &nic->mac_control;
2080 config = &nic->config;
2081
2082 for (i = 0; i < config->tx_fifo_num; i++) {
2083 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
1ee6dd77 2084 txdp = (struct TxD *) mac_control->fifos[i].list_info[j].
1da177e4 2085 list_virt_addr;
fed5eccd
AR		 2086 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2087 if (skb) {
2088 dev_kfree_skb(skb);
2089 cnt++;
1da177e4 2090 }
1da177e4
LT		 2091 }
2092 DBG_PRINT(INTR_DBG,
2093 "%s:forcibly freeing %d skbs on FIFO%d\n",
2094 dev->name, cnt, i);
20346722
K		 2095 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2096 mac_control->fifos[i].tx_curr_put_info.offset = 0;
1da177e4
LT		 2097 }
2098}
2099
20346722
K		 2100/**
2101 * stop_nic - To stop the nic
1da177e4 2102 * @nic ; device private variable.
20346722
K		 2103 * Description:
2104 * This function does exactly the opposite of what the start_nic()
1da177e4
LT		 2105 * function does. This function is called to stop the device.
2106 * Return Value:
2107 * void.
2108 */
2109
2110static void stop_nic(struct s2io_nic *nic)
2111{
1ee6dd77 2112 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 2113 register u64 val64 = 0;
5d3213cc 2114 u16 interruptible;
1ee6dd77 2115 struct mac_info *mac_control;
1da177e4
LT		 2116 struct config_param *config;
2117
2118 mac_control = &nic->mac_control;
2119 config = &nic->config;
2120
2121 /* Disable all interrupts */
e960fc5c 2122 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
a371a07d
K		 2123 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2124 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
1da177e4
LT		 2125 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2126
5d3213cc
AR		 2127 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2128 val64 = readq(&bar0->adapter_control);
2129 val64 &= ~(ADAPTER_CNTL_EN);
2130 writeq(val64, &bar0->adapter_control);
1da177e4
LT		 2131}
2132
1ee6dd77
RB		 2133static int fill_rxd_3buf(struct s2io_nic *nic, struct RxD_t *rxdp, struct \
2134 sk_buff *skb)
da6971d8
AR		 2135{
2136 struct net_device *dev = nic->dev;
2137 struct sk_buff *frag_list;
50eb8006 2138 void *tmp;
da6971d8
AR		 2139
2140 /* Buffer-1 receives L3/L4 headers */
1ee6dd77 2141 ((struct RxD3*)rxdp)->Buffer1_ptr = pci_map_single
da6971d8
AR		 2142 (nic->pdev, skb->data, l3l4hdr_size + 4,
2143 PCI_DMA_FROMDEVICE);
2144
2145 /* skb_shinfo(skb)->frag_list will have L4 data payload */
2146 skb_shinfo(skb)->frag_list = dev_alloc_skb(dev->mtu + ALIGN_SIZE);
2147 if (skb_shinfo(skb)->frag_list == NULL) {
2148 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n ", dev->name);
2149 return -ENOMEM ;
2150 }
2151 frag_list = skb_shinfo(skb)->frag_list;
372cc597 2152 skb->truesize += frag_list->truesize;
da6971d8 2153 frag_list->next = NULL;
50eb8006
JG		 2154 tmp = (void *)ALIGN((long)frag_list->data, ALIGN_SIZE + 1);
2155 frag_list->data = tmp;
2156 frag_list->tail = tmp;
da6971d8
AR		 2157
2158 /* Buffer-2 receives L4 data payload */
1ee6dd77 2159 ((struct RxD3*)rxdp)->Buffer2_ptr = pci_map_single(nic->pdev,
da6971d8
AR		 2160 frag_list->data, dev->mtu,
2161 PCI_DMA_FROMDEVICE);
2162 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
2163 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
2164
2165 return SUCCESS;
2166}
2167
20346722
K		 2168/**
2169 * fill_rx_buffers - Allocates the Rx side skbs
1da177e4 2170 * @nic: device private variable
20346722
K		 2171 * @ring_no: ring number
2172 * Description:
1da177e4
LT		 2173 * The function allocates Rx side skbs and puts the physical
2174 * address of these buffers into the RxD buffer pointers, so that the NIC
2175 * can DMA the received frame into these locations.
2176 * The NIC supports 3 receive modes, viz
2177 * 1. single buffer,
2178 * 2. three buffer and
2179 * 3. Five buffer modes.
20346722
K		 2180 * Each mode defines how many fragments the received frame will be split
2181 * up into by the NIC. The frame is split into L3 header, L4 Header,
1da177e4
LT		 2182 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2183 * is split into 3 fragments. As of now only single buffer mode is
2184 * supported.
2185 * Return Value:
2186 * SUCCESS on success or an appropriate -ve value on failure.
2187 */
2188
ac1f60db 2189static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1da177e4
LT		 2190{
2191 struct net_device *dev = nic->dev;
2192 struct sk_buff *skb;
1ee6dd77 2193 struct RxD_t *rxdp;
1da177e4 2194 int off, off1, size, block_no, block_no1;
1da177e4 2195 u32 alloc_tab = 0;
20346722 2196 u32 alloc_cnt;
1ee6dd77 2197 struct mac_info *mac_control;
1da177e4 2198 struct config_param *config;
20346722 2199 u64 tmp;
1ee6dd77 2200 struct buffAdd *ba;
1da177e4 2201 unsigned long flags;
1ee6dd77 2202 struct RxD_t *first_rxdp = NULL;
1da177e4
LT		 2203
2204 mac_control = &nic->mac_control;
2205 config = &nic->config;
20346722
K		 2206 alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2207 atomic_read(&nic->rx_bufs_left[ring_no]);
1da177e4 2208
5d3213cc 2209 block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
863c11a9 2210 off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
1da177e4 2211 while (alloc_tab < alloc_cnt) {
20346722 2212 block_no = mac_control->rings[ring_no].rx_curr_put_info.
1da177e4 2213 block_index;
20346722 2214 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
1da177e4 2215
da6971d8
AR		 2216 rxdp = mac_control->rings[ring_no].
2217 rx_blocks[block_no].rxds[off].virt_addr;
2218
2219 if ((block_no == block_no1) && (off == off1) &&
2220 (rxdp->Host_Control)) {
2221 DBG_PRINT(INTR_DBG, "%s: Get and Put",
2222 dev->name);
1da177e4
LT		 2223 DBG_PRINT(INTR_DBG, " info equated\n");
2224 goto end;
2225 }
da6971d8 2226 if (off && (off == rxd_count[nic->rxd_mode])) {
20346722 2227 mac_control->rings[ring_no].rx_curr_put_info.
1da177e4 2228 block_index++;
da6971d8
AR		 2229 if (mac_control->rings[ring_no].rx_curr_put_info.
2230 block_index == mac_control->rings[ring_no].
2231 block_count)
2232 mac_control->rings[ring_no].rx_curr_put_info.
2233 block_index = 0;
2234 block_no = mac_control->rings[ring_no].
2235 rx_curr_put_info.block_index;
2236 if (off == rxd_count[nic->rxd_mode])
2237 off = 0;
20346722 2238 mac_control->rings[ring_no].rx_curr_put_info.
da6971d8
AR		 2239 offset = off;
2240 rxdp = mac_control->rings[ring_no].
2241 rx_blocks[block_no].block_virt_addr;
1da177e4
LT		 2242 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2243 dev->name, rxdp);
2244 }
db874e65
SS		 2245 if(!napi) {
2246 spin_lock_irqsave(&nic->put_lock, flags);
2247 mac_control->rings[ring_no].put_pos =
2248 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2249 spin_unlock_irqrestore(&nic->put_lock, flags);
2250 } else {
2251 mac_control->rings[ring_no].put_pos =
2252 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2253 }
da6971d8
AR		 2254 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2255 ((nic->rxd_mode >= RXD_MODE_3A) &&
2256 (rxdp->Control_2 & BIT(0)))) {
20346722 2257 mac_control->rings[ring_no].rx_curr_put_info.
da6971d8 2258 offset = off;
1da177e4
LT		 2259 goto end;
2260 }
da6971d8
AR		 2261 /* calculate size of skb based on ring mode */
2262 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2263 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2264 if (nic->rxd_mode == RXD_MODE_1)
2265 size += NET_IP_ALIGN;
2266 else if (nic->rxd_mode == RXD_MODE_3B)
2267 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2268 else
2269 size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
1da177e4 2270
da6971d8
AR		 2271 /* allocate skb */
2272 skb = dev_alloc_skb(size);
2273 if(!skb) {
1da177e4
LT		 2274 DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
2275 DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
303bcb4b
K		 2276 if (first_rxdp) {
2277 wmb();
2278 first_rxdp->Control_1 |= RXD_OWN_XENA;
2279 }
da6971d8
AR		 2280 return -ENOMEM ;
2281 }
2282 if (nic->rxd_mode == RXD_MODE_1) {
2283 /* 1 buffer mode - normal operation mode */
1ee6dd77 2284 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2285 skb_reserve(skb, NET_IP_ALIGN);
1ee6dd77 2286 ((struct RxD1*)rxdp)->Buffer0_ptr = pci_map_single
863c11a9
AR		 2287 (nic->pdev, skb->data, size - NET_IP_ALIGN,
2288 PCI_DMA_FROMDEVICE);
2289 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
da6971d8
AR		 2290
2291 } else if (nic->rxd_mode >= RXD_MODE_3A) {
2292 /*
2293 * 2 or 3 buffer mode -
2294 * Both 2 buffer mode and 3 buffer mode provides 128
2295 * byte aligned receive buffers.
2296 *
2297 * 3 buffer mode provides header separation where in
2298 * skb->data will have L3/L4 headers where as
2299 * skb_shinfo(skb)->frag_list will have the L4 data
2300 * payload
2301 */
2302
1ee6dd77 2303 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8
AR		 2304 ba = &mac_control->rings[ring_no].ba[block_no][off];
2305 skb_reserve(skb, BUF0_LEN);
2306 tmp = (u64)(unsigned long) skb->data;
2307 tmp += ALIGN_SIZE;
2308 tmp &= ~ALIGN_SIZE;
2309 skb->data = (void *) (unsigned long)tmp;
2310 skb->tail = (void *) (unsigned long)tmp;
2311
1ee6dd77
RB		 2312 if (!(((struct RxD3*)rxdp)->Buffer0_ptr))
2313 ((struct RxD3*)rxdp)->Buffer0_ptr =
75c30b13 2314 pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
da6971d8 2315 PCI_DMA_FROMDEVICE);
75c30b13
AR		 2316 else
2317 pci_dma_sync_single_for_device(nic->pdev,
1ee6dd77 2318 (dma_addr_t) ((struct RxD3*)rxdp)->Buffer0_ptr,
75c30b13 2319 BUF0_LEN, PCI_DMA_FROMDEVICE);
da6971d8
AR		 2320 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2321 if (nic->rxd_mode == RXD_MODE_3B) {
2322 /* Two buffer mode */
2323
2324 /*
6aa20a22 2325 * Buffer2 will have L3/L4 header plus
da6971d8
AR		 2326 * L4 payload
2327 */
1ee6dd77 2328 ((struct RxD3*)rxdp)->Buffer2_ptr = pci_map_single
da6971d8
AR		 2329 (nic->pdev, skb->data, dev->mtu + 4,
2330 PCI_DMA_FROMDEVICE);
2331
75c30b13 2332 /* Buffer-1 will be dummy buffer. Not used */
1ee6dd77
RB		 2333 if (!(((struct RxD3*)rxdp)->Buffer1_ptr)) {
2334 ((struct RxD3*)rxdp)->Buffer1_ptr =
6aa20a22 2335 pci_map_single(nic->pdev,
75c30b13
AR		 2336 ba->ba_1, BUF1_LEN,
2337 PCI_DMA_FROMDEVICE);
2338 }
da6971d8
AR		 2339 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2340 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2341 (dev->mtu + 4);
2342 } else {
2343 /* 3 buffer mode */
2344 if (fill_rxd_3buf(nic, rxdp, skb) == -ENOMEM) {
2345 dev_kfree_skb_irq(skb);
2346 if (first_rxdp) {
2347 wmb();
2348 first_rxdp->Control_1 |=
2349 RXD_OWN_XENA;
2350 }
2351 return -ENOMEM ;
2352 }
2353 }
2354 rxdp->Control_2 |= BIT(0);
1da177e4 2355 }
1da177e4 2356 rxdp->Host_Control = (unsigned long) (skb);
303bcb4b
K		 2357 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2358 rxdp->Control_1 |= RXD_OWN_XENA;
1da177e4 2359 off++;
da6971d8
AR		 2360 if (off == (rxd_count[nic->rxd_mode] + 1))
2361 off = 0;
20346722 2362 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
20346722 2363
da6971d8 2364 rxdp->Control_2 |= SET_RXD_MARKER;
303bcb4b
K		 2365 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2366 if (first_rxdp) {
2367 wmb();
2368 first_rxdp->Control_1 |= RXD_OWN_XENA;
2369 }
2370 first_rxdp = rxdp;
2371 }
1da177e4
LT		 2372 atomic_inc(&nic->rx_bufs_left[ring_no]);
2373 alloc_tab++;
2374 }
2375
2376 end:
303bcb4b
K		 2377 /* Transfer ownership of first descriptor to adapter just before
2378 * exiting. Before that, use memory barrier so that ownership
2379 * and other fields are seen by adapter correctly.
2380 */
2381 if (first_rxdp) {
2382 wmb();
2383 first_rxdp->Control_1 |= RXD_OWN_XENA;
2384 }
2385
1da177e4
LT		 2386 return SUCCESS;
2387}
2388
da6971d8
AR		 2389static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2390{
2391 struct net_device *dev = sp->dev;
2392 int j;
2393 struct sk_buff *skb;
1ee6dd77
RB		 2394 struct RxD_t *rxdp;
2395 struct mac_info *mac_control;
2396 struct buffAdd *ba;
da6971d8
AR		 2397
2398 mac_control = &sp->mac_control;
2399 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2400 rxdp = mac_control->rings[ring_no].
2401 rx_blocks[blk].rxds[j].virt_addr;
2402 skb = (struct sk_buff *)
2403 ((unsigned long) rxdp->Host_Control);
2404 if (!skb) {
2405 continue;
2406 }
2407 if (sp->rxd_mode == RXD_MODE_1) {
2408 pci_unmap_single(sp->pdev, (dma_addr_t)
1ee6dd77 2409 ((struct RxD1*)rxdp)->Buffer0_ptr,
da6971d8
AR		 2410 dev->mtu +
2411 HEADER_ETHERNET_II_802_3_SIZE
2412 + HEADER_802_2_SIZE +
2413 HEADER_SNAP_SIZE,
2414 PCI_DMA_FROMDEVICE);
1ee6dd77 2415 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8
AR		 2416 } else if(sp->rxd_mode == RXD_MODE_3B) {
2417 ba = &mac_control->rings[ring_no].
2418 ba[blk][j];
2419 pci_unmap_single(sp->pdev, (dma_addr_t)
1ee6dd77 2420 ((struct RxD3*)rxdp)->Buffer0_ptr,
da6971d8
AR		 2421 BUF0_LEN,
2422 PCI_DMA_FROMDEVICE);
2423 pci_unmap_single(sp->pdev, (dma_addr_t)
1ee6dd77 2424 ((struct RxD3*)rxdp)->Buffer1_ptr,
da6971d8
AR		 2425 BUF1_LEN,
2426 PCI_DMA_FROMDEVICE);
2427 pci_unmap_single(sp->pdev, (dma_addr_t)
1ee6dd77 2428 ((struct RxD3*)rxdp)->Buffer2_ptr,
da6971d8
AR		 2429 dev->mtu + 4,
2430 PCI_DMA_FROMDEVICE);
1ee6dd77 2431 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8
AR		 2432 } else {
2433 pci_unmap_single(sp->pdev, (dma_addr_t)
1ee6dd77 2434 ((struct RxD3*)rxdp)->Buffer0_ptr, BUF0_LEN,
da6971d8
AR		 2435 PCI_DMA_FROMDEVICE);
2436 pci_unmap_single(sp->pdev, (dma_addr_t)
1ee6dd77 2437 ((struct RxD3*)rxdp)->Buffer1_ptr,
da6971d8
AR		 2438 l3l4hdr_size + 4,
2439 PCI_DMA_FROMDEVICE);
2440 pci_unmap_single(sp->pdev, (dma_addr_t)
1ee6dd77 2441 ((struct RxD3*)rxdp)->Buffer2_ptr, dev->mtu,
da6971d8 2442 PCI_DMA_FROMDEVICE);
1ee6dd77 2443 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8
AR		 2444 }
2445 dev_kfree_skb(skb);
2446 atomic_dec(&sp->rx_bufs_left[ring_no]);
2447 }
2448}
2449
1da177e4 2450/**
20346722 2451 * free_rx_buffers - Frees all Rx buffers
1da177e4 2452 * @sp: device private variable.
20346722 2453 * Description:
1da177e4
LT		 2454 * This function will free all Rx buffers allocated by host.
2455 * Return Value:
2456 * NONE.
2457 */
2458
2459static void free_rx_buffers(struct s2io_nic *sp)
2460{
2461 struct net_device *dev = sp->dev;
da6971d8 2462 int i, blk = 0, buf_cnt = 0;
1ee6dd77 2463 struct mac_info *mac_control;
1da177e4 2464 struct config_param *config;
1da177e4
LT		 2465
2466 mac_control = &sp->mac_control;
2467 config = &sp->config;
2468
2469 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 2470 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2471 free_rxd_blk(sp,i,blk);
1da177e4 2472
20346722
K		 2473 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2474 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2475 mac_control->rings[i].rx_curr_put_info.offset = 0;
2476 mac_control->rings[i].rx_curr_get_info.offset = 0;
1da177e4
LT		 2477 atomic_set(&sp->rx_bufs_left[i], 0);
2478 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2479 dev->name, buf_cnt, i);
2480 }
2481}
2482
2483/**
2484 * s2io_poll - Rx interrupt handler for NAPI support
2485 * @dev : pointer to the device structure.
20346722 2486 * @budget : The number of packets that were budgeted to be processed
1da177e4
LT		 2487 * during one pass through the 'Poll" function.
2488 * Description:
2489 * Comes into picture only if NAPI support has been incorporated. It does
2490 * the same thing that rx_intr_handler does, but not in a interrupt context
2491 * also It will process only a given number of packets.
2492 * Return value:
2493 * 0 on success and 1 if there are No Rx packets to be processed.
2494 */
2495
1da177e4
LT		 2496static int s2io_poll(struct net_device *dev, int *budget)
2497{
1ee6dd77 2498 struct s2io_nic *nic = dev->priv;
20346722 2499 int pkt_cnt = 0, org_pkts_to_process;
1ee6dd77 2500 struct mac_info *mac_control;
1da177e4 2501 struct config_param *config;
1ee6dd77 2502 struct XENA_dev_config __iomem *bar0 = nic->bar0;
20346722 2503 int i;
1da177e4 2504
7ba013ac 2505 atomic_inc(&nic->isr_cnt);
1da177e4
LT		 2506 mac_control = &nic->mac_control;
2507 config = &nic->config;
2508
20346722
K		 2509 nic->pkts_to_process = *budget;
2510 if (nic->pkts_to_process > dev->quota)
2511 nic->pkts_to_process = dev->quota;
2512 org_pkts_to_process = nic->pkts_to_process;
1da177e4 2513
19a60522
SS		 2514 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
2515 readl(&bar0->rx_traffic_int);
1da177e4
LT		 2516
2517 for (i = 0; i < config->rx_ring_num; i++) {
20346722
K		 2518 rx_intr_handler(&mac_control->rings[i]);
2519 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2520 if (!nic->pkts_to_process) {
2521 /* Quota for the current iteration has been met */
2522 goto no_rx;
1da177e4 2523 }
1da177e4
LT		 2524 }
2525 if (!pkt_cnt)
2526 pkt_cnt = 1;
2527
2528 dev->quota -= pkt_cnt;
2529 *budget -= pkt_cnt;
2530 netif_rx_complete(dev);
2531
2532 for (i = 0; i < config->rx_ring_num; i++) {
2533 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2534 DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2535 DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2536 break;
2537 }
2538 }
2539 /* Re enable the Rx interrupts. */
c92ca04b 2540 writeq(0x0, &bar0->rx_traffic_mask);
19a60522 2541 readl(&bar0->rx_traffic_mask);
7ba013ac 2542 atomic_dec(&nic->isr_cnt);
1da177e4
LT		 2543 return 0;
2544
20346722 2545no_rx:
1da177e4
LT		 2546 dev->quota -= pkt_cnt;
2547 *budget -= pkt_cnt;
2548
2549 for (i = 0; i < config->rx_ring_num; i++) {
2550 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2551 DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2552 DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2553 break;
2554 }
2555 }
7ba013ac 2556 atomic_dec(&nic->isr_cnt);
1da177e4
LT		 2557 return 1;
2558}
20346722 2559
b41477f3 2560#ifdef CONFIG_NET_POLL_CONTROLLER
612eff0e 2561/**
b41477f3 2562 * s2io_netpoll - netpoll event handler entry point
612eff0e
BH		 2563 * @dev : pointer to the device structure.
2564 * Description:
b41477f3
AR		 2565 * This function will be called by upper layer to check for events on the
2566 * interface in situations where interrupts are disabled. It is used for
2567 * specific in-kernel networking tasks, such as remote consoles and kernel
2568 * debugging over the network (example netdump in RedHat).
612eff0e 2569 */
612eff0e
BH		 2570static void s2io_netpoll(struct net_device *dev)
2571{
1ee6dd77
RB		 2572 struct s2io_nic *nic = dev->priv;
2573 struct mac_info *mac_control;
612eff0e 2574 struct config_param *config;
1ee6dd77 2575 struct XENA_dev_config __iomem *bar0 = nic->bar0;
b41477f3 2576 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
612eff0e
BH		 2577 int i;
2578
2579 disable_irq(dev->irq);
2580
2581 atomic_inc(&nic->isr_cnt);
2582 mac_control = &nic->mac_control;
2583 config = &nic->config;
2584
612eff0e 2585 writeq(val64, &bar0->rx_traffic_int);
b41477f3
AR		 2586 writeq(val64, &bar0->tx_traffic_int);
2587
6aa20a22 2588 /* we need to free up the transmitted skbufs or else netpoll will
b41477f3
AR		 2589 * run out of skbs and will fail and eventually netpoll application such
2590 * as netdump will fail.
2591 */
2592 for (i = 0; i < config->tx_fifo_num; i++)
2593 tx_intr_handler(&mac_control->fifos[i]);
612eff0e 2594
b41477f3 2595 /* check for received packet and indicate up to network */
612eff0e
BH		 2596 for (i = 0; i < config->rx_ring_num; i++)
2597 rx_intr_handler(&mac_control->rings[i]);
2598
2599 for (i = 0; i < config->rx_ring_num; i++) {
2600 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2601 DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2602 DBG_PRINT(ERR_DBG, " in Rx Netpoll!!\n");
2603 break;
2604 }
2605 }
2606 atomic_dec(&nic->isr_cnt);
2607 enable_irq(dev->irq);
2608 return;
2609}
2610#endif
2611
20346722 2612/**
1da177e4
LT		 2613 * rx_intr_handler - Rx interrupt handler
2614 * @nic: device private variable.
20346722
K		 2615 * Description:
2616 * If the interrupt is because of a received frame or if the
1da177e4 2617 * receive ring contains fresh as yet un-processed frames,this function is
20346722
K		 2618 * called. It picks out the RxD at which place the last Rx processing had
2619 * stopped and sends the skb to the OSM's Rx handler and then increments
1da177e4
LT		 2620 * the offset.
2621 * Return Value:
2622 * NONE.
2623 */
1ee6dd77 2624static void rx_intr_handler(struct ring_info *ring_data)
1da177e4 2625{
1ee6dd77 2626 struct s2io_nic *nic = ring_data->nic;
1da177e4 2627 struct net_device *dev = (struct net_device *) nic->dev;
da6971d8 2628 int get_block, put_block, put_offset;
1ee6dd77
RB		 2629 struct rx_curr_get_info get_info, put_info;
2630 struct RxD_t *rxdp;
1da177e4 2631 struct sk_buff *skb;
20346722 2632 int pkt_cnt = 0;
7d3d0439
RA		 2633 int i;
2634
7ba013ac
K		 2635 spin_lock(&nic->rx_lock);
2636 if (atomic_read(&nic->card_state) == CARD_DOWN) {
776bd20f 2637 DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
7ba013ac
K		 2638 __FUNCTION__, dev->name);
2639 spin_unlock(&nic->rx_lock);
776bd20f 2640 return;
7ba013ac
K		 2641 }
2642
20346722
K		 2643 get_info = ring_data->rx_curr_get_info;
2644 get_block = get_info.block_index;
1ee6dd77 2645 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
20346722 2646 put_block = put_info.block_index;
da6971d8 2647 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
db874e65
SS		 2648 if (!napi) {
2649 spin_lock(&nic->put_lock);
2650 put_offset = ring_data->put_pos;
2651 spin_unlock(&nic->put_lock);
2652 } else
2653 put_offset = ring_data->put_pos;
2654
da6971d8 2655 while (RXD_IS_UP2DT(rxdp)) {
db874e65
SS		 2656 /*
2657 * If your are next to put index then it's
2658 * FIFO full condition
2659 */
da6971d8
AR		 2660 if ((get_block == put_block) &&
2661 (get_info.offset + 1) == put_info.offset) {
75c30b13 2662 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
da6971d8
AR		 2663 break;
2664 }
20346722
K		 2665 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2666 if (skb == NULL) {
2667 DBG_PRINT(ERR_DBG, "%s: The skb is ",
2668 dev->name);
2669 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
7ba013ac 2670 spin_unlock(&nic->rx_lock);
20346722 2671 return;
1da177e4 2672 }
da6971d8
AR		 2673 if (nic->rxd_mode == RXD_MODE_1) {
2674 pci_unmap_single(nic->pdev, (dma_addr_t)
1ee6dd77 2675 ((struct RxD1*)rxdp)->Buffer0_ptr,
20346722
K		 2676 dev->mtu +
2677 HEADER_ETHERNET_II_802_3_SIZE +
2678 HEADER_802_2_SIZE +
2679 HEADER_SNAP_SIZE,
2680 PCI_DMA_FROMDEVICE);
da6971d8 2681 } else if (nic->rxd_mode == RXD_MODE_3B) {
75c30b13 2682 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
1ee6dd77 2683 ((struct RxD3*)rxdp)->Buffer0_ptr,
20346722 2684 BUF0_LEN, PCI_DMA_FROMDEVICE);
da6971d8 2685 pci_unmap_single(nic->pdev, (dma_addr_t)
1ee6dd77 2686 ((struct RxD3*)rxdp)->Buffer2_ptr,
da6971d8 2687 dev->mtu + 4,
20346722 2688 PCI_DMA_FROMDEVICE);
da6971d8 2689 } else {
75c30b13 2690 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
1ee6dd77 2691 ((struct RxD3*)rxdp)->Buffer0_ptr, BUF0_LEN,
da6971d8
AR		 2692 PCI_DMA_FROMDEVICE);
2693 pci_unmap_single(nic->pdev, (dma_addr_t)
1ee6dd77 2694 ((struct RxD3*)rxdp)->Buffer1_ptr,
da6971d8
AR		 2695 l3l4hdr_size + 4,
2696 PCI_DMA_FROMDEVICE);
2697 pci_unmap_single(nic->pdev, (dma_addr_t)
1ee6dd77 2698 ((struct RxD3*)rxdp)->Buffer2_ptr,
da6971d8
AR		 2699 dev->mtu, PCI_DMA_FROMDEVICE);
2700 }
863c11a9 2701 prefetch(skb->data);
20346722
K		 2702 rx_osm_handler(ring_data, rxdp);
2703 get_info.offset++;
da6971d8
AR		 2704 ring_data->rx_curr_get_info.offset = get_info.offset;
2705 rxdp = ring_data->rx_blocks[get_block].
2706 rxds[get_info.offset].virt_addr;
2707 if (get_info.offset == rxd_count[nic->rxd_mode]) {
20346722 2708 get_info.offset = 0;
da6971d8 2709 ring_data->rx_curr_get_info.offset = get_info.offset;
20346722 2710 get_block++;
da6971d8
AR		 2711 if (get_block == ring_data->block_count)
2712 get_block = 0;
2713 ring_data->rx_curr_get_info.block_index = get_block;
20346722
K		 2714 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2715 }
1da177e4 2716
20346722 2717 nic->pkts_to_process -= 1;
db874e65 2718 if ((napi) && (!nic->pkts_to_process))
20346722 2719 break;
20346722 2720 pkt_cnt++;
1da177e4
LT		 2721 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2722 break;
2723 }
7d3d0439
RA		 2724 if (nic->lro) {
2725 /* Clear all LRO sessions before exiting */
2726 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 2727 struct lro *lro = &nic->lro0_n[i];
7d3d0439
RA		 2728 if (lro->in_use) {
2729 update_L3L4_header(nic, lro);
2730 queue_rx_frame(lro->parent);
2731 clear_lro_session(lro);
2732 }
2733 }
2734 }
2735
7ba013ac 2736 spin_unlock(&nic->rx_lock);
1da177e4 2737}
20346722
K		 2738
2739/**
1da177e4
LT		 2740 * tx_intr_handler - Transmit interrupt handler
2741 * @nic : device private variable
20346722
K		 2742 * Description:
2743 * If an interrupt was raised to indicate DMA complete of the
2744 * Tx packet, this function is called. It identifies the last TxD
2745 * whose buffer was freed and frees all skbs whose data have already
1da177e4
LT		 2746 * DMA'ed into the NICs internal memory.
2747 * Return Value:
2748 * NONE
2749 */
2750
1ee6dd77 2751static void tx_intr_handler(struct fifo_info *fifo_data)
1da177e4 2752{
1ee6dd77 2753 struct s2io_nic *nic = fifo_data->nic;
1da177e4 2754 struct net_device *dev = (struct net_device *) nic->dev;
1ee6dd77 2755 struct tx_curr_get_info get_info, put_info;
1da177e4 2756 struct sk_buff *skb;
1ee6dd77 2757 struct TxD *txdlp;
1da177e4 2758
20346722 2759 get_info = fifo_data->tx_curr_get_info;
1ee6dd77
RB		 2760 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
2761 txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
20346722
K		 2762 list_virt_addr;
2763 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2764 (get_info.offset != put_info.offset) &&
2765 (txdlp->Host_Control)) {
2766 /* Check for TxD errors */
2767 if (txdlp->Control_1 & TXD_T_CODE) {
2768 unsigned long long err;
2769 err = txdlp->Control_1 & TXD_T_CODE;
bd1034f0
AR		 2770 if (err & 0x1) {
2771 nic->mac_control.stats_info->sw_stat.
2772 parity_err_cnt++;
2773 }
776bd20f 2774 if ((err >> 48) == 0xA) {
2775 DBG_PRINT(TX_DBG, "TxD returned due \
19a60522 2776 to loss of link\n");
776bd20f 2777 }
2778 else {
19a60522 2779 DBG_PRINT(ERR_DBG, "***TxD error %llx\n", err);
776bd20f 2780 }
20346722 2781 }
1da177e4 2782
fed5eccd 2783 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
20346722
K		 2784 if (skb == NULL) {
2785 DBG_PRINT(ERR_DBG, "%s: Null skb ",
2786 __FUNCTION__);
2787 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2788 return;
2789 }
2790
20346722 2791 /* Updating the statistics block */
20346722
K		 2792 nic->stats.tx_bytes += skb->len;
2793 dev_kfree_skb_irq(skb);
2794
2795 get_info.offset++;
863c11a9
AR		 2796 if (get_info.offset == get_info.fifo_len + 1)
2797 get_info.offset = 0;
1ee6dd77 2798 txdlp = (struct TxD *) fifo_data->list_info
20346722
K		 2799 [get_info.offset].list_virt_addr;
2800 fifo_data->tx_curr_get_info.offset =
2801 get_info.offset;
1da177e4
LT		 2802 }
2803
2804 spin_lock(&nic->tx_lock);
2805 if (netif_queue_stopped(dev))
2806 netif_wake_queue(dev);
2807 spin_unlock(&nic->tx_lock);
2808}
2809
bd1034f0
AR		 2810/**
2811 * s2io_mdio_write - Function to write in to MDIO registers
2812 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2813 * @addr : address value
2814 * @value : data value
2815 * @dev : pointer to net_device structure
2816 * Description:
2817 * This function is used to write values to the MDIO registers
2818 * NONE
2819 */
2820static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
2821{
2822 u64 val64 = 0x0;
1ee6dd77
RB		 2823 struct s2io_nic *sp = dev->priv;
2824 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 2825
2826 //address transaction
2827 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2828 | MDIO_MMD_DEV_ADDR(mmd_type)
2829 | MDIO_MMS_PRT_ADDR(0x0);
2830 writeq(val64, &bar0->mdio_control);
2831 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2832 writeq(val64, &bar0->mdio_control);
2833 udelay(100);
2834
2835 //Data transaction
2836 val64 = 0x0;
2837 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2838 | MDIO_MMD_DEV_ADDR(mmd_type)
2839 | MDIO_MMS_PRT_ADDR(0x0)
2840 | MDIO_MDIO_DATA(value)
2841 | MDIO_OP(MDIO_OP_WRITE_TRANS);
2842 writeq(val64, &bar0->mdio_control);
2843 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2844 writeq(val64, &bar0->mdio_control);
2845 udelay(100);
2846
2847 val64 = 0x0;
2848 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2849 | MDIO_MMD_DEV_ADDR(mmd_type)
2850 | MDIO_MMS_PRT_ADDR(0x0)
2851 | MDIO_OP(MDIO_OP_READ_TRANS);
2852 writeq(val64, &bar0->mdio_control);
2853 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2854 writeq(val64, &bar0->mdio_control);
2855 udelay(100);
2856
2857}
2858
2859/**
2860 * s2io_mdio_read - Function to write in to MDIO registers
2861 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2862 * @addr : address value
2863 * @dev : pointer to net_device structure
2864 * Description:
2865 * This function is used to read values to the MDIO registers
2866 * NONE
2867 */
2868static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
2869{
2870 u64 val64 = 0x0;
2871 u64 rval64 = 0x0;
1ee6dd77
RB		 2872 struct s2io_nic *sp = dev->priv;
2873 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 2874
2875 /* address transaction */
2876 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2877 | MDIO_MMD_DEV_ADDR(mmd_type)
2878 | MDIO_MMS_PRT_ADDR(0x0);
2879 writeq(val64, &bar0->mdio_control);
2880 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2881 writeq(val64, &bar0->mdio_control);
2882 udelay(100);
2883
2884 /* Data transaction */
2885 val64 = 0x0;
2886 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2887 | MDIO_MMD_DEV_ADDR(mmd_type)
2888 | MDIO_MMS_PRT_ADDR(0x0)
2889 | MDIO_OP(MDIO_OP_READ_TRANS);
2890 writeq(val64, &bar0->mdio_control);
2891 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2892 writeq(val64, &bar0->mdio_control);
2893 udelay(100);
2894
2895 /* Read the value from regs */
2896 rval64 = readq(&bar0->mdio_control);
2897 rval64 = rval64 & 0xFFFF0000;
2898 rval64 = rval64 >> 16;
2899 return rval64;
2900}
2901/**
2902 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
2903 * @counter : couter value to be updated
2904 * @flag : flag to indicate the status
2905 * @type : counter type
2906 * Description:
2907 * This function is to check the status of the xpak counters value
2908 * NONE
2909 */
2910
2911static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
2912{
2913 u64 mask = 0x3;
2914 u64 val64;
2915 int i;
2916 for(i = 0; i <index; i++)
2917 mask = mask << 0x2;
2918
2919 if(flag > 0)
2920 {
2921 *counter = *counter + 1;
2922 val64 = *regs_stat & mask;
2923 val64 = val64 >> (index * 0x2);
2924 val64 = val64 + 1;
2925 if(val64 == 3)
2926 {
2927 switch(type)
2928 {
2929 case 1:
2930 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
2931 "service. Excessive temperatures may "
2932 "result in premature transceiver "
2933 "failure \n");
2934 break;
2935 case 2:
2936 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
2937 "service Excessive bias currents may "
2938 "indicate imminent laser diode "
2939 "failure \n");
2940 break;
2941 case 3:
2942 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
2943 "service Excessive laser output "
2944 "power may saturate far-end "
2945 "receiver\n");
2946 break;
2947 default:
2948 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
2949 "type \n");
2950 }
2951 val64 = 0x0;
2952 }
2953 val64 = val64 << (index * 0x2);
2954 *regs_stat = (*regs_stat & (~mask)) | (val64);
2955
2956 } else {
2957 *regs_stat = *regs_stat & (~mask);
2958 }
2959}
2960
2961/**
2962 * s2io_updt_xpak_counter - Function to update the xpak counters
2963 * @dev : pointer to net_device struct
2964 * Description:
2965 * This function is to upate the status of the xpak counters value
2966 * NONE
2967 */
2968static void s2io_updt_xpak_counter(struct net_device *dev)
2969{
2970 u16 flag = 0x0;
2971 u16 type = 0x0;
2972 u16 val16 = 0x0;
2973 u64 val64 = 0x0;
2974 u64 addr = 0x0;
2975
1ee6dd77
RB		 2976 struct s2io_nic *sp = dev->priv;
2977 struct stat_block *stat_info = sp->mac_control.stats_info;
bd1034f0
AR		 2978
2979 /* Check the communication with the MDIO slave */
2980 addr = 0x0000;
2981 val64 = 0x0;
2982 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
2983 if((val64 == 0xFFFF) || (val64 == 0x0000))
2984 {
2985 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
2986 "Returned %llx\n", (unsigned long long)val64);
2987 return;
2988 }
2989
2990 /* Check for the expecte value of 2040 at PMA address 0x0000 */
2991 if(val64 != 0x2040)
2992 {
2993 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
2994 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
2995 (unsigned long long)val64);
2996 return;
2997 }
2998
2999 /* Loading the DOM register to MDIO register */
3000 addr = 0xA100;
3001 s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3002 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3003
3004 /* Reading the Alarm flags */
3005 addr = 0xA070;
3006 val64 = 0x0;
3007 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3008
3009 flag = CHECKBIT(val64, 0x7);
3010 type = 1;
3011 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3012 &stat_info->xpak_stat.xpak_regs_stat,
3013 0x0, flag, type);
3014
3015 if(CHECKBIT(val64, 0x6))
3016 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3017
3018 flag = CHECKBIT(val64, 0x3);
3019 type = 2;
3020 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3021 &stat_info->xpak_stat.xpak_regs_stat,
3022 0x2, flag, type);
3023
3024 if(CHECKBIT(val64, 0x2))
3025 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3026
3027 flag = CHECKBIT(val64, 0x1);
3028 type = 3;
3029 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3030 &stat_info->xpak_stat.xpak_regs_stat,
3031 0x4, flag, type);
3032
3033 if(CHECKBIT(val64, 0x0))
3034 stat_info->xpak_stat.alarm_laser_output_power_low++;
3035
3036 /* Reading the Warning flags */
3037 addr = 0xA074;
3038 val64 = 0x0;
3039 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3040
3041 if(CHECKBIT(val64, 0x7))
3042 stat_info->xpak_stat.warn_transceiver_temp_high++;
3043
3044 if(CHECKBIT(val64, 0x6))
3045 stat_info->xpak_stat.warn_transceiver_temp_low++;
3046
3047 if(CHECKBIT(val64, 0x3))
3048 stat_info->xpak_stat.warn_laser_bias_current_high++;
3049
3050 if(CHECKBIT(val64, 0x2))
3051 stat_info->xpak_stat.warn_laser_bias_current_low++;
3052
3053 if(CHECKBIT(val64, 0x1))
3054 stat_info->xpak_stat.warn_laser_output_power_high++;
3055
3056 if(CHECKBIT(val64, 0x0))
3057 stat_info->xpak_stat.warn_laser_output_power_low++;
3058}
3059
20346722 3060/**
1da177e4
LT		 3061 * alarm_intr_handler - Alarm Interrrupt handler
3062 * @nic: device private variable
20346722 3063 * Description: If the interrupt was neither because of Rx packet or Tx
1da177e4 3064 * complete, this function is called. If the interrupt was to indicate
20346722
K		 3065 * a loss of link, the OSM link status handler is invoked for any other
3066 * alarm interrupt the block that raised the interrupt is displayed
1da177e4
LT		 3067 * and a H/W reset is issued.
3068 * Return Value:
3069 * NONE
3070*/
3071
3072static void alarm_intr_handler(struct s2io_nic *nic)
3073{
3074 struct net_device *dev = (struct net_device *) nic->dev;
1ee6dd77 3075 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 3076 register u64 val64 = 0, err_reg = 0;
bd1034f0
AR		 3077 u64 cnt;
3078 int i;
372cc597
SS		 3079 if (atomic_read(&nic->card_state) == CARD_DOWN)
3080 return;
bd1034f0
AR		 3081 nic->mac_control.stats_info->sw_stat.ring_full_cnt = 0;
3082 /* Handling the XPAK counters update */
3083 if(nic->mac_control.stats_info->xpak_stat.xpak_timer_count < 72000) {
3084 /* waiting for an hour */
3085 nic->mac_control.stats_info->xpak_stat.xpak_timer_count++;
3086 } else {
3087 s2io_updt_xpak_counter(dev);
3088 /* reset the count to zero */
3089 nic->mac_control.stats_info->xpak_stat.xpak_timer_count = 0;
3090 }
1da177e4
LT		 3091
3092 /* Handling link status change error Intr */
a371a07d
K		 3093 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
3094 err_reg = readq(&bar0->mac_rmac_err_reg);
3095 writeq(err_reg, &bar0->mac_rmac_err_reg);
3096 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
3097 schedule_work(&nic->set_link_task);
3098 }
1da177e4
LT		 3099 }
3100
5e25b9dd
K		 3101 /* Handling Ecc errors */
3102 val64 = readq(&bar0->mc_err_reg);
3103 writeq(val64, &bar0->mc_err_reg);
3104 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
3105 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
7ba013ac
K		 3106 nic->mac_control.stats_info->sw_stat.
3107 double_ecc_errs++;
776bd20f 3108 DBG_PRINT(INIT_DBG, "%s: Device indicates ",
5e25b9dd 3109 dev->name);
776bd20f 3110 DBG_PRINT(INIT_DBG, "double ECC error!!\n");
e960fc5c 3111 if (nic->device_type != XFRAME_II_DEVICE) {
776bd20f 3112 /* Reset XframeI only if critical error */
3113 if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
3114 MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
3115 netif_stop_queue(dev);
3116 schedule_work(&nic->rst_timer_task);
bd1034f0
AR		 3117 nic->mac_control.stats_info->sw_stat.
3118 soft_reset_cnt++;
776bd20f 3119 }
e960fc5c 3120 }
5e25b9dd 3121 } else {
7ba013ac
K		 3122 nic->mac_control.stats_info->sw_stat.
3123 single_ecc_errs++;
5e25b9dd
K		 3124 }
3125 }
3126
1da177e4
LT		 3127 /* In case of a serious error, the device will be Reset. */
3128 val64 = readq(&bar0->serr_source);
3129 if (val64 & SERR_SOURCE_ANY) {
bd1034f0 3130 nic->mac_control.stats_info->sw_stat.serious_err_cnt++;
1da177e4 3131 DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
6aa20a22 3132 DBG_PRINT(ERR_DBG, "serious error %llx!!\n",
776bd20f 3133 (unsigned long long)val64);
1da177e4
LT		 3134 netif_stop_queue(dev);
3135 schedule_work(&nic->rst_timer_task);
bd1034f0 3136 nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
1da177e4
LT		 3137 }
3138
3139 /*
3140 * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
3141 * Error occurs, the adapter will be recycled by disabling the
20346722 3142 * adapter enable bit and enabling it again after the device
1da177e4
LT		 3143 * becomes Quiescent.
3144 */
3145 val64 = readq(&bar0->pcc_err_reg);
3146 writeq(val64, &bar0->pcc_err_reg);
3147 if (val64 & PCC_FB_ECC_DB_ERR) {
3148 u64 ac = readq(&bar0->adapter_control);
3149 ac &= ~(ADAPTER_CNTL_EN);
3150 writeq(ac, &bar0->adapter_control);
3151 ac = readq(&bar0->adapter_control);
3152 schedule_work(&nic->set_link_task);
3153 }
bd1034f0
AR		 3154 /* Check for data parity error */
3155 val64 = readq(&bar0->pic_int_status);
3156 if (val64 & PIC_INT_GPIO) {
3157 val64 = readq(&bar0->gpio_int_reg);
3158 if (val64 & GPIO_INT_REG_DP_ERR_INT) {
3159 nic->mac_control.stats_info->sw_stat.parity_err_cnt++;
3160 schedule_work(&nic->rst_timer_task);
3161 nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3162 }
3163 }
3164
3165 /* Check for ring full counter */
3166 if (nic->device_type & XFRAME_II_DEVICE) {
3167 val64 = readq(&bar0->ring_bump_counter1);
3168 for (i=0; i<4; i++) {
3169 cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3170 cnt >>= 64 - ((i+1)*16);
3171 nic->mac_control.stats_info->sw_stat.ring_full_cnt
3172 += cnt;
3173 }
3174
3175 val64 = readq(&bar0->ring_bump_counter2);
3176 for (i=0; i<4; i++) {
3177 cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3178 cnt >>= 64 - ((i+1)*16);
3179 nic->mac_control.stats_info->sw_stat.ring_full_cnt
3180 += cnt;
3181 }
3182 }
1da177e4
LT		 3183
3184 /* Other type of interrupts are not being handled now, TODO */
3185}
3186
20346722 3187/**
1da177e4 3188 * wait_for_cmd_complete - waits for a command to complete.
20346722 3189 * @sp : private member of the device structure, which is a pointer to the
1da177e4 3190 * s2io_nic structure.
20346722
K		 3191 * Description: Function that waits for a command to Write into RMAC
3192 * ADDR DATA registers to be completed and returns either success or
3193 * error depending on whether the command was complete or not.
1da177e4
LT		 3194 * Return value:
3195 * SUCCESS on success and FAILURE on failure.
3196 */
3197
cc3afe6f 3198static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit)
1da177e4 3199{
1da177e4
LT		 3200 int ret = FAILURE, cnt = 0;
3201 u64 val64;
3202
3203 while (TRUE) {
c92ca04b
AR		 3204 val64 = readq(addr);
3205 if (!(val64 & busy_bit)) {
1da177e4
LT		 3206 ret = SUCCESS;
3207 break;
3208 }
c92ca04b
AR		 3209
3210 if(in_interrupt())
3211 mdelay(50);
3212 else
3213 msleep(50);
3214
1da177e4
LT		 3215 if (cnt++ > 10)
3216 break;
3217 }
1da177e4
LT		 3218 return ret;
3219}
19a60522
SS		 3220/*
3221 * check_pci_device_id - Checks if the device id is supported
3222 * @id : device id
3223 * Description: Function to check if the pci device id is supported by driver.
3224 * Return value: Actual device id if supported else PCI_ANY_ID
3225 */
3226static u16 check_pci_device_id(u16 id)
3227{
3228 switch (id) {
3229 case PCI_DEVICE_ID_HERC_WIN:
3230 case PCI_DEVICE_ID_HERC_UNI:
3231 return XFRAME_II_DEVICE;
3232 case PCI_DEVICE_ID_S2IO_UNI:
3233 case PCI_DEVICE_ID_S2IO_WIN:
3234 return XFRAME_I_DEVICE;
3235 default:
3236 return PCI_ANY_ID;
3237 }
3238}
1da177e4 3239
20346722
K		 3240/**
3241 * s2io_reset - Resets the card.
1da177e4
LT		 3242 * @sp : private member of the device structure.
3243 * Description: Function to Reset the card. This function then also
20346722 3244 * restores the previously saved PCI configuration space registers as
1da177e4
LT		 3245 * the card reset also resets the configuration space.
3246 * Return value:
3247 * void.
3248 */
3249
1ee6dd77 3250static void s2io_reset(struct s2io_nic * sp)
1da177e4 3251{
1ee6dd77 3252 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 3253 u64 val64;
5e25b9dd 3254 u16 subid, pci_cmd;
19a60522
SS		 3255 int i;
3256 u16 val16;
3257 DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3258 __FUNCTION__, sp->dev->name);
1da177e4 3259
0b1f7ebe 3260 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
e960fc5c 3261 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
0b1f7ebe 3262
19a60522
SS		 3263 if (sp->device_type == XFRAME_II_DEVICE) {
3264 int ret;
3265 ret = pci_set_power_state(sp->pdev, 3);
3266 if (!ret)
3267 ret = pci_set_power_state(sp->pdev, 0);
3268 else {
3269 DBG_PRINT(ERR_DBG,"%s PME based SW_Reset failed!\n",
3270 __FUNCTION__);
3271 goto old_way;
3272 }
3273 msleep(20);
3274 goto new_way;
3275 }
3276old_way:
1da177e4
LT		 3277 val64 = SW_RESET_ALL;
3278 writeq(val64, &bar0->sw_reset);
19a60522 3279new_way:
c92ca04b
AR		 3280 if (strstr(sp->product_name, "CX4")) {
3281 msleep(750);
3282 }
19a60522
SS		 3283 msleep(250);
3284 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
1da177e4 3285
19a60522
SS		 3286 /* Restore the PCI state saved during initialization. */
3287 pci_restore_state(sp->pdev);
3288 pci_read_config_word(sp->pdev, 0x2, &val16);
3289 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3290 break;
3291 msleep(200);
3292 }
1da177e4 3293
19a60522
SS		 3294 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3295 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
3296 }
3297
3298 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3299
3300 s2io_init_pci(sp);
1da177e4 3301
20346722
K		 3302 /* Set swapper to enable I/O register access */
3303 s2io_set_swapper(sp);
3304
cc6e7c44
RA		 3305 /* Restore the MSIX table entries from local variables */
3306 restore_xmsi_data(sp);
3307
5e25b9dd 3308 /* Clear certain PCI/PCI-X fields after reset */
303bcb4b 3309 if (sp->device_type == XFRAME_II_DEVICE) {
b41477f3 3310 /* Clear "detected parity error" bit */
303bcb4b 3311 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
5e25b9dd 3312
303bcb4b
K		 3313 /* Clearing PCIX Ecc status register */
3314 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
5e25b9dd 3315
303bcb4b
K		 3316 /* Clearing PCI_STATUS error reflected here */
3317 writeq(BIT(62), &bar0->txpic_int_reg);
3318 }
5e25b9dd 3319
20346722
K		 3320 /* Reset device statistics maintained by OS */
3321 memset(&sp->stats, 0, sizeof (struct net_device_stats));
3322
1da177e4
LT		 3323 /* SXE-002: Configure link and activity LED to turn it off */
3324 subid = sp->pdev->subsystem_device;
541ae68f
K		 3325 if (((subid & 0xFF) >= 0x07) &&
3326 (sp->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 3327 val64 = readq(&bar0->gpio_control);
3328 val64 |= 0x0000800000000000ULL;
3329 writeq(val64, &bar0->gpio_control);
3330 val64 = 0x0411040400000000ULL;
509a2671 3331 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 3332 }
3333
541ae68f
K		 3334 /*
3335 * Clear spurious ECC interrupts that would have occured on
3336 * XFRAME II cards after reset.
3337 */
3338 if (sp->device_type == XFRAME_II_DEVICE) {
3339 val64 = readq(&bar0->pcc_err_reg);
3340 writeq(val64, &bar0->pcc_err_reg);
3341 }
3342
1da177e4
LT		 3343 sp->device_enabled_once = FALSE;
3344}
3345
3346/**
20346722
K		 3347 * s2io_set_swapper - to set the swapper controle on the card
3348 * @sp : private member of the device structure,
1da177e4 3349 * pointer to the s2io_nic structure.
20346722 3350 * Description: Function to set the swapper control on the card
1da177e4
LT		 3351 * correctly depending on the 'endianness' of the system.
3352 * Return value:
3353 * SUCCESS on success and FAILURE on failure.
3354 */
3355
1ee6dd77 3356static int s2io_set_swapper(struct s2io_nic * sp)
1da177e4
LT		 3357{
3358 struct net_device *dev = sp->dev;
1ee6dd77 3359 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 3360 u64 val64, valt, valr;
3361
20346722 3362 /*
1da177e4
LT		 3363 * Set proper endian settings and verify the same by reading
3364 * the PIF Feed-back register.
3365 */
3366
3367 val64 = readq(&bar0->pif_rd_swapper_fb);
3368 if (val64 != 0x0123456789ABCDEFULL) {
3369 int i = 0;
3370 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3371 0x8100008181000081ULL, /* FE=1, SE=0 */
3372 0x4200004242000042ULL, /* FE=0, SE=1 */
3373 0}; /* FE=0, SE=0 */
3374
3375 while(i<4) {
3376 writeq(value[i], &bar0->swapper_ctrl);
3377 val64 = readq(&bar0->pif_rd_swapper_fb);
3378 if (val64 == 0x0123456789ABCDEFULL)
3379 break;
3380 i++;
3381 }
3382 if (i == 4) {
3383 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3384 dev->name);
3385 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3386 (unsigned long long) val64);
3387 return FAILURE;
3388 }
3389 valr = value[i];
3390 } else {
3391 valr = readq(&bar0->swapper_ctrl);
3392 }
3393
3394 valt = 0x0123456789ABCDEFULL;
3395 writeq(valt, &bar0->xmsi_address);
3396 val64 = readq(&bar0->xmsi_address);
3397
3398 if(val64 != valt) {
3399 int i = 0;
3400 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3401 0x0081810000818100ULL, /* FE=1, SE=0 */
3402 0x0042420000424200ULL, /* FE=0, SE=1 */
3403 0}; /* FE=0, SE=0 */
3404
3405 while(i<4) {
3406 writeq((value[i] | valr), &bar0->swapper_ctrl);
3407 writeq(valt, &bar0->xmsi_address);
3408 val64 = readq(&bar0->xmsi_address);
3409 if(val64 == valt)
3410 break;
3411 i++;
3412 }
3413 if(i == 4) {
20346722 3414 unsigned long long x = val64;
1da177e4 3415 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
20346722 3416 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
1da177e4
LT		 3417 return FAILURE;
3418 }
3419 }
3420 val64 = readq(&bar0->swapper_ctrl);
3421 val64 &= 0xFFFF000000000000ULL;
3422
3423#ifdef __BIG_ENDIAN
20346722
K		 3424 /*
3425 * The device by default set to a big endian format, so a
1da177e4
LT		 3426 * big endian driver need not set anything.
3427 */
3428 val64 |= (SWAPPER_CTRL_TXP_FE |
3429 SWAPPER_CTRL_TXP_SE |
3430 SWAPPER_CTRL_TXD_R_FE |
3431 SWAPPER_CTRL_TXD_W_FE |
3432 SWAPPER_CTRL_TXF_R_FE |
3433 SWAPPER_CTRL_RXD_R_FE |
3434 SWAPPER_CTRL_RXD_W_FE |
3435 SWAPPER_CTRL_RXF_W_FE |
3436 SWAPPER_CTRL_XMSI_FE |
1da177e4 3437 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
92383340 3438 if (sp->intr_type == INTA)
cc6e7c44 3439 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3440 writeq(val64, &bar0->swapper_ctrl);
3441#else
20346722 3442 /*
1da177e4 3443 * Initially we enable all bits to make it accessible by the
20346722 3444 * driver, then we selectively enable only those bits that
1da177e4
LT		 3445 * we want to set.
3446 */
3447 val64 |= (SWAPPER_CTRL_TXP_FE |
3448 SWAPPER_CTRL_TXP_SE |
3449 SWAPPER_CTRL_TXD_R_FE |
3450 SWAPPER_CTRL_TXD_R_SE |
3451 SWAPPER_CTRL_TXD_W_FE |
3452 SWAPPER_CTRL_TXD_W_SE |
3453 SWAPPER_CTRL_TXF_R_FE |
3454 SWAPPER_CTRL_RXD_R_FE |
3455 SWAPPER_CTRL_RXD_R_SE |
3456 SWAPPER_CTRL_RXD_W_FE |
3457 SWAPPER_CTRL_RXD_W_SE |
3458 SWAPPER_CTRL_RXF_W_FE |
3459 SWAPPER_CTRL_XMSI_FE |
1da177e4 3460 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
cc6e7c44
RA		 3461 if (sp->intr_type == INTA)
3462 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3463 writeq(val64, &bar0->swapper_ctrl);
3464#endif
3465 val64 = readq(&bar0->swapper_ctrl);
3466
20346722
K		 3467 /*
3468 * Verifying if endian settings are accurate by reading a
1da177e4
LT		 3469 * feedback register.
3470 */
3471 val64 = readq(&bar0->pif_rd_swapper_fb);
3472 if (val64 != 0x0123456789ABCDEFULL) {
3473 /* Endian settings are incorrect, calls for another dekko. */
3474 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3475 dev->name);
3476 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3477 (unsigned long long) val64);
3478 return FAILURE;
3479 }
3480
3481 return SUCCESS;
3482}
3483
1ee6dd77 3484static int wait_for_msix_trans(struct s2io_nic *nic, int i)
cc6e7c44 3485{
1ee6dd77 3486 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3487 u64 val64;
3488 int ret = 0, cnt = 0;
3489
3490 do {
3491 val64 = readq(&bar0->xmsi_access);
3492 if (!(val64 & BIT(15)))
3493 break;
3494 mdelay(1);
3495 cnt++;
3496 } while(cnt < 5);
3497 if (cnt == 5) {
3498 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3499 ret = 1;
3500 }
3501
3502 return ret;
3503}
3504
1ee6dd77 3505static void restore_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3506{
1ee6dd77 3507 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3508 u64 val64;
3509 int i;
3510
75c30b13 3511 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
cc6e7c44
RA		 3512 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3513 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3514 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
3515 writeq(val64, &bar0->xmsi_access);
3516 if (wait_for_msix_trans(nic, i)) {
3517 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3518 continue;
3519 }
3520 }
3521}
3522
1ee6dd77 3523static void store_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3524{
1ee6dd77 3525 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3526 u64 val64, addr, data;
3527 int i;
3528
3529 /* Store and display */
75c30b13 3530 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
cc6e7c44
RA		 3531 val64 = (BIT(15) | vBIT(i, 26, 6));
3532 writeq(val64, &bar0->xmsi_access);
3533 if (wait_for_msix_trans(nic, i)) {
3534 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3535 continue;
3536 }
3537 addr = readq(&bar0->xmsi_address);
3538 data = readq(&bar0->xmsi_data);
3539 if (addr && data) {
3540 nic->msix_info[i].addr = addr;
3541 nic->msix_info[i].data = data;
3542 }
3543 }
3544}
3545
1ee6dd77 3546int s2io_enable_msi(struct s2io_nic *nic)
cc6e7c44 3547{
1ee6dd77 3548 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3549 u16 msi_ctrl, msg_val;
3550 struct config_param *config = &nic->config;
3551 struct net_device *dev = nic->dev;
3552 u64 val64, tx_mat, rx_mat;
3553 int i, err;
3554
3555 val64 = readq(&bar0->pic_control);
3556 val64 &= ~BIT(1);
3557 writeq(val64, &bar0->pic_control);
3558
3559 err = pci_enable_msi(nic->pdev);
3560 if (err) {
3561 DBG_PRINT(ERR_DBG, "%s: enabling MSI failed\n",
3562 nic->dev->name);
3563 return err;
3564 }
3565
3566 /*
3567 * Enable MSI and use MSI-1 in stead of the standard MSI-0
3568 * for interrupt handling.
3569 */
3570 pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3571 msg_val ^= 0x1;
3572 pci_write_config_word(nic->pdev, 0x4c, msg_val);
3573 pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3574
3575 pci_read_config_word(nic->pdev, 0x42, &msi_ctrl);
3576 msi_ctrl |= 0x10;
3577 pci_write_config_word(nic->pdev, 0x42, msi_ctrl);
3578
3579 /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */
3580 tx_mat = readq(&bar0->tx_mat0_n[0]);
3581 for (i=0; i<config->tx_fifo_num; i++) {
3582 tx_mat |= TX_MAT_SET(i, 1);
3583 }
3584 writeq(tx_mat, &bar0->tx_mat0_n[0]);
3585
3586 rx_mat = readq(&bar0->rx_mat);
3587 for (i=0; i<config->rx_ring_num; i++) {
3588 rx_mat |= RX_MAT_SET(i, 1);
3589 }
3590 writeq(rx_mat, &bar0->rx_mat);
3591
3592 dev->irq = nic->pdev->irq;
3593 return 0;
3594}
3595
1ee6dd77 3596static int s2io_enable_msi_x(struct s2io_nic *nic)
cc6e7c44 3597{
1ee6dd77 3598 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3599 u64 tx_mat, rx_mat;
3600 u16 msi_control; /* Temp variable */
3601 int ret, i, j, msix_indx = 1;
3602
3603 nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry),
3604 GFP_KERNEL);
3605 if (nic->entries == NULL) {
3606 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3607 return -ENOMEM;
3608 }
3609 memset(nic->entries, 0, MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3610
3611 nic->s2io_entries =
3612 kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry),
3613 GFP_KERNEL);
3614 if (nic->s2io_entries == NULL) {
3615 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3616 kfree(nic->entries);
3617 return -ENOMEM;
3618 }
3619 memset(nic->s2io_entries, 0,
3620 MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3621
3622 for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3623 nic->entries[i].entry = i;
3624 nic->s2io_entries[i].entry = i;
3625 nic->s2io_entries[i].arg = NULL;
3626 nic->s2io_entries[i].in_use = 0;
3627 }
3628
3629 tx_mat = readq(&bar0->tx_mat0_n[0]);
3630 for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3631 tx_mat |= TX_MAT_SET(i, msix_indx);
3632 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3633 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3634 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3635 }
3636 writeq(tx_mat, &bar0->tx_mat0_n[0]);
3637
3638 if (!nic->config.bimodal) {
3639 rx_mat = readq(&bar0->rx_mat);
3640 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3641 rx_mat |= RX_MAT_SET(j, msix_indx);
3642 nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3643 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3644 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3645 }
3646 writeq(rx_mat, &bar0->rx_mat);
3647 } else {
3648 tx_mat = readq(&bar0->tx_mat0_n[7]);
3649 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3650 tx_mat |= TX_MAT_SET(i, msix_indx);
3651 nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3652 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3653 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3654 }
3655 writeq(tx_mat, &bar0->tx_mat0_n[7]);
3656 }
3657
c92ca04b 3658 nic->avail_msix_vectors = 0;
cc6e7c44 3659 ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
c92ca04b
AR		 3660 /* We fail init if error or we get less vectors than min required */
3661 if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3662 nic->avail_msix_vectors = ret;
3663 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3664 }
cc6e7c44
RA		 3665 if (ret) {
3666 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3667 kfree(nic->entries);
3668 kfree(nic->s2io_entries);
3669 nic->entries = NULL;
3670 nic->s2io_entries = NULL;
c92ca04b 3671 nic->avail_msix_vectors = 0;
cc6e7c44
RA		 3672 return -ENOMEM;
3673 }
c92ca04b
AR		 3674 if (!nic->avail_msix_vectors)
3675 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
cc6e7c44
RA		 3676
3677 /*
3678 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3679 * in the herc NIC. (Temp change, needs to be removed later)
3680 */
3681 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3682 msi_control |= 0x1; /* Enable MSI */
3683 pci_write_config_word(nic->pdev, 0x42, msi_control);
3684
3685 return 0;
3686}
3687
1da177e4
LT		 3688/* ********************************************************* *
3689 * Functions defined below concern the OS part of the driver *
3690 * ********************************************************* */
3691
20346722 3692/**
1da177e4
LT		 3693 * s2io_open - open entry point of the driver
3694 * @dev : pointer to the device structure.
3695 * Description:
3696 * This function is the open entry point of the driver. It mainly calls a
3697 * function to allocate Rx buffers and inserts them into the buffer
20346722 3698 * descriptors and then enables the Rx part of the NIC.
1da177e4
LT		 3699 * Return value:
3700 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3701 * file on failure.
3702 */
3703
ac1f60db 3704static int s2io_open(struct net_device *dev)
1da177e4 3705{
1ee6dd77 3706 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 3707 int err = 0;
3708
20346722
K		 3709 /*
3710 * Make sure you have link off by default every time
1da177e4
LT		 3711 * Nic is initialized
3712 */
3713 netif_carrier_off(dev);
0b1f7ebe 3714 sp->last_link_state = 0;
1da177e4
LT		 3715
3716 /* Initialize H/W and enable interrupts */
c92ca04b
AR		 3717 err = s2io_card_up(sp);
3718 if (err) {
1da177e4
LT		 3719 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3720 dev->name);
e6a8fee2 3721 goto hw_init_failed;
1da177e4
LT		 3722 }
3723
3724 if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
3725 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
e6a8fee2 3726 s2io_card_down(sp);
20346722 3727 err = -ENODEV;
e6a8fee2 3728 goto hw_init_failed;
1da177e4
LT		 3729 }
3730
3731 netif_start_queue(dev);
3732 return 0;
20346722 3733
20346722 3734hw_init_failed:
cc6e7c44
RA		 3735 if (sp->intr_type == MSI_X) {
3736 if (sp->entries)
3737 kfree(sp->entries);
3738 if (sp->s2io_entries)
3739 kfree(sp->s2io_entries);
3740 }
20346722 3741 return err;
1da177e4
LT		 3742}
3743
3744/**
3745 * s2io_close -close entry point of the driver
3746 * @dev : device pointer.
3747 * Description:
3748 * This is the stop entry point of the driver. It needs to undo exactly
3749 * whatever was done by the open entry point,thus it's usually referred to
3750 * as the close function.Among other things this function mainly stops the
3751 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3752 * Return value:
3753 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3754 * file on failure.
3755 */
3756
ac1f60db 3757static int s2io_close(struct net_device *dev)
1da177e4 3758{
1ee6dd77 3759 struct s2io_nic *sp = dev->priv;
cc6e7c44 3760
1da177e4
LT		 3761 netif_stop_queue(dev);
3762 /* Reset card, kill tasklet and free Tx and Rx buffers. */
e6a8fee2 3763 s2io_card_down(sp);
cc6e7c44 3764
1da177e4
LT		 3765 sp->device_close_flag = TRUE; /* Device is shut down. */
3766 return 0;
3767}
3768
3769/**
3770 * s2io_xmit - Tx entry point of te driver
3771 * @skb : the socket buffer containing the Tx data.
3772 * @dev : device pointer.
3773 * Description :
3774 * This function is the Tx entry point of the driver. S2IO NIC supports
3775 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
3776 * NOTE: when device cant queue the pkt,just the trans_start variable will
3777 * not be upadted.
3778 * Return value:
3779 * 0 on success & 1 on failure.
3780 */
3781
ac1f60db 3782static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 3783{
1ee6dd77 3784 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 3785 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3786 register u64 val64;
1ee6dd77
RB		 3787 struct TxD *txdp;
3788 struct TxFIFO_element __iomem *tx_fifo;
1da177e4 3789 unsigned long flags;
be3a6b02
K		 3790 u16 vlan_tag = 0;
3791 int vlan_priority = 0;
1ee6dd77 3792 struct mac_info *mac_control;
1da177e4 3793 struct config_param *config;
75c30b13 3794 int offload_type;
1da177e4
LT		 3795
3796 mac_control = &sp->mac_control;
3797 config = &sp->config;
3798
20346722 3799 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
1da177e4 3800 spin_lock_irqsave(&sp->tx_lock, flags);
1da177e4 3801 if (atomic_read(&sp->card_state) == CARD_DOWN) {
20346722 3802 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
1da177e4
LT		 3803 dev->name);
3804 spin_unlock_irqrestore(&sp->tx_lock, flags);
20346722
K		 3805 dev_kfree_skb(skb);
3806 return 0;
1da177e4
LT		 3807 }
3808
3809 queue = 0;
1da177e4 3810
be3a6b02
K		 3811 /* Get Fifo number to Transmit based on vlan priority */
3812 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3813 vlan_tag = vlan_tx_tag_get(skb);
3814 vlan_priority = vlan_tag >> 13;
3815 queue = config->fifo_mapping[vlan_priority];
3816 }
3817
20346722
K		 3818 put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
3819 get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
1ee6dd77 3820 txdp = (struct TxD *) mac_control->fifos[queue].list_info[put_off].
20346722
K		 3821 list_virt_addr;
3822
3823 queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
1da177e4 3824 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9
AR		 3825 if (txdp->Host_Control ||
3826 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
776bd20f 3827 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
1da177e4
LT		 3828 netif_stop_queue(dev);
3829 dev_kfree_skb(skb);
3830 spin_unlock_irqrestore(&sp->tx_lock, flags);
3831 return 0;
3832 }
0b1f7ebe
K		 3833
3834 /* A buffer with no data will be dropped */
3835 if (!skb->len) {
3836 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
3837 dev_kfree_skb(skb);
3838 spin_unlock_irqrestore(&sp->tx_lock, flags);
3839 return 0;
3840 }
3841
75c30b13 3842 offload_type = s2io_offload_type(skb);
75c30b13 3843 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1da177e4 3844 txdp->Control_1 |= TXD_TCP_LSO_EN;
75c30b13 3845 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
1da177e4 3846 }
84fa7933 3847 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 3848 txdp->Control_2 |=
3849 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
3850 TXD_TX_CKO_UDP_EN);
3851 }
fed5eccd
AR		 3852 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
3853 txdp->Control_1 |= TXD_LIST_OWN_XENA;
1da177e4 3854 txdp->Control_2 |= config->tx_intr_type;
d8892c6e 3855
be3a6b02
K		 3856 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3857 txdp->Control_2 |= TXD_VLAN_ENABLE;
3858 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
3859 }
3860
fed5eccd 3861 frg_len = skb->len - skb->data_len;
75c30b13 3862 if (offload_type == SKB_GSO_UDP) {
fed5eccd
AR		 3863 int ufo_size;
3864
75c30b13 3865 ufo_size = s2io_udp_mss(skb);
fed5eccd
AR		 3866 ufo_size &= ~7;
3867 txdp->Control_1 |= TXD_UFO_EN;
3868 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
3869 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
3870#ifdef __BIG_ENDIAN
3871 sp->ufo_in_band_v[put_off] =
3872 (u64)skb_shinfo(skb)->ip6_frag_id;
3873#else
3874 sp->ufo_in_band_v[put_off] =
3875 (u64)skb_shinfo(skb)->ip6_frag_id << 32;
3876#endif
3877 txdp->Host_Control = (unsigned long)sp->ufo_in_band_v;
3878 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
3879 sp->ufo_in_band_v,
3880 sizeof(u64), PCI_DMA_TODEVICE);
3881 txdp++;
fed5eccd 3882 }
1da177e4 3883
fed5eccd
AR		 3884 txdp->Buffer_Pointer = pci_map_single
3885 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
3886 txdp->Host_Control = (unsigned long) skb;
3887 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
75c30b13 3888 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 3889 txdp->Control_1 |= TXD_UFO_EN;
3890
3891 frg_cnt = skb_shinfo(skb)->nr_frags;
1da177e4
LT		 3892 /* For fragmented SKB. */
3893 for (i = 0; i < frg_cnt; i++) {
3894 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0b1f7ebe
K		 3895 /* A '0' length fragment will be ignored */
3896 if (!frag->size)
3897 continue;
1da177e4
LT		 3898 txdp++;
3899 txdp->Buffer_Pointer = (u64) pci_map_page
3900 (sp->pdev, frag->page, frag->page_offset,
3901 frag->size, PCI_DMA_TODEVICE);
efd51b5c 3902 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
75c30b13 3903 if (offload_type == SKB_GSO_UDP)
fed5eccd 3904 txdp->Control_1 |= TXD_UFO_EN;
1da177e4
LT		 3905 }
3906 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
3907
75c30b13 3908 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 3909 frg_cnt++; /* as Txd0 was used for inband header */
3910
1da177e4 3911 tx_fifo = mac_control->tx_FIFO_start[queue];
20346722 3912 val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
1da177e4
LT		 3913 writeq(val64, &tx_fifo->TxDL_Pointer);
3914
3915 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
3916 TX_FIFO_LAST_LIST);
75c30b13 3917 if (offload_type)
fed5eccd 3918 val64 |= TX_FIFO_SPECIAL_FUNC;
75c30b13 3919
1da177e4
LT		 3920 writeq(val64, &tx_fifo->List_Control);
3921
303bcb4b
K		 3922 mmiowb();
3923
1da177e4 3924 put_off++;
863c11a9
AR		 3925 if (put_off == mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1)
3926 put_off = 0;
20346722 3927 mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
1da177e4
LT		 3928
3929 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 3930 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
bd1034f0 3931 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
1da177e4
LT		 3932 DBG_PRINT(TX_DBG,
3933 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
3934 put_off, get_off);
3935 netif_stop_queue(dev);
3936 }
3937
3938 dev->trans_start = jiffies;
3939 spin_unlock_irqrestore(&sp->tx_lock, flags);
3940
3941 return 0;
3942}
3943
25fff88e
K		 3944static void
3945s2io_alarm_handle(unsigned long data)
3946{
1ee6dd77 3947 struct s2io_nic *sp = (struct s2io_nic *)data;
25fff88e
K		 3948
3949 alarm_intr_handler(sp);
3950 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
3951}
3952
1ee6dd77 3953static int s2io_chk_rx_buffers(struct s2io_nic *sp, int rng_n)
75c30b13
AR		 3954{
3955 int rxb_size, level;
3956
3957 if (!sp->lro) {
3958 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
3959 level = rx_buffer_level(sp, rxb_size, rng_n);
3960
3961 if ((level == PANIC) && (!TASKLET_IN_USE)) {
3962 int ret;
3963 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
3964 DBG_PRINT(INTR_DBG, "PANIC levels\n");
3965 if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
3966 DBG_PRINT(ERR_DBG, "Out of memory in %s",
3967 __FUNCTION__);
3968 clear_bit(0, (&sp->tasklet_status));
3969 return -1;
3970 }
3971 clear_bit(0, (&sp->tasklet_status));
3972 } else if (level == LOW)
3973 tasklet_schedule(&sp->task);
3974
3975 } else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
3976 DBG_PRINT(ERR_DBG, "%s:Out of memory", sp->dev->name);
3977 DBG_PRINT(ERR_DBG, " in Rx Intr!!\n");
3978 }
3979 return 0;
3980}
3981
7d12e780 3982static irqreturn_t s2io_msi_handle(int irq, void *dev_id)
cc6e7c44
RA		 3983{
3984 struct net_device *dev = (struct net_device *) dev_id;
1ee6dd77 3985 struct s2io_nic *sp = dev->priv;
cc6e7c44 3986 int i;
1ee6dd77 3987 struct mac_info *mac_control;
cc6e7c44
RA		 3988 struct config_param *config;
3989
3990 atomic_inc(&sp->isr_cnt);
3991 mac_control = &sp->mac_control;
3992 config = &sp->config;
3993 DBG_PRINT(INTR_DBG, "%s: MSI handler\n", __FUNCTION__);
3994
3995 /* If Intr is because of Rx Traffic */
3996 for (i = 0; i < config->rx_ring_num; i++)
3997 rx_intr_handler(&mac_control->rings[i]);
3998
3999 /* If Intr is because of Tx Traffic */
4000 for (i = 0; i < config->tx_fifo_num; i++)
4001 tx_intr_handler(&mac_control->fifos[i]);
4002
4003 /*
4004 * If the Rx buffer count is below the panic threshold then
4005 * reallocate the buffers from the interrupt handler itself,
4006 * else schedule a tasklet to reallocate the buffers.
4007 */
75c30b13
AR		 4008 for (i = 0; i < config->rx_ring_num; i++)
4009 s2io_chk_rx_buffers(sp, i);
cc6e7c44
RA		 4010
4011 atomic_dec(&sp->isr_cnt);
4012 return IRQ_HANDLED;
4013}
4014
7d12e780 4015static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
cc6e7c44 4016{
1ee6dd77
RB		 4017 struct ring_info *ring = (struct ring_info *)dev_id;
4018 struct s2io_nic *sp = ring->nic;
cc6e7c44
RA		 4019
4020 atomic_inc(&sp->isr_cnt);
cc6e7c44 4021
75c30b13
AR		 4022 rx_intr_handler(ring);
4023 s2io_chk_rx_buffers(sp, ring->ring_no);
7d3d0439 4024
cc6e7c44 4025 atomic_dec(&sp->isr_cnt);
cc6e7c44
RA		 4026 return IRQ_HANDLED;
4027}
4028
7d12e780 4029static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
cc6e7c44 4030{
1ee6dd77
RB		 4031 struct fifo_info *fifo = (struct fifo_info *)dev_id;
4032 struct s2io_nic *sp = fifo->nic;
cc6e7c44
RA		 4033
4034 atomic_inc(&sp->isr_cnt);
4035 tx_intr_handler(fifo);
4036 atomic_dec(&sp->isr_cnt);
4037 return IRQ_HANDLED;
4038}
1ee6dd77 4039static void s2io_txpic_intr_handle(struct s2io_nic *sp)
a371a07d 4040{
1ee6dd77 4041 struct XENA_dev_config __iomem *bar0 = sp->bar0;
a371a07d
K		 4042 u64 val64;
4043
4044 val64 = readq(&bar0->pic_int_status);
4045 if (val64 & PIC_INT_GPIO) {
4046 val64 = readq(&bar0->gpio_int_reg);
4047 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4048 (val64 & GPIO_INT_REG_LINK_UP)) {
c92ca04b
AR		 4049 /*
4050 * This is unstable state so clear both up/down
4051 * interrupt and adapter to re-evaluate the link state.
4052 */
a371a07d
K		 4053 val64 |= GPIO_INT_REG_LINK_DOWN;
4054 val64 |= GPIO_INT_REG_LINK_UP;
4055 writeq(val64, &bar0->gpio_int_reg);
a371a07d 4056 val64 = readq(&bar0->gpio_int_mask);
c92ca04b
AR		 4057 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4058 GPIO_INT_MASK_LINK_DOWN);
a371a07d 4059 writeq(val64, &bar0->gpio_int_mask);
a371a07d 4060 }
c92ca04b
AR		 4061 else if (val64 & GPIO_INT_REG_LINK_UP) {
4062 val64 = readq(&bar0->adapter_status);
c92ca04b 4063 /* Enable Adapter */
19a60522
SS		 4064 val64 = readq(&bar0->adapter_control);
4065 val64 |= ADAPTER_CNTL_EN;
4066 writeq(val64, &bar0->adapter_control);
4067 val64 |= ADAPTER_LED_ON;
4068 writeq(val64, &bar0->adapter_control);
4069 if (!sp->device_enabled_once)
4070 sp->device_enabled_once = 1;
c92ca04b 4071
19a60522
SS		 4072 s2io_link(sp, LINK_UP);
4073 /*
4074 * unmask link down interrupt and mask link-up
4075 * intr
4076 */
4077 val64 = readq(&bar0->gpio_int_mask);
4078 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4079 val64 |= GPIO_INT_MASK_LINK_UP;
4080 writeq(val64, &bar0->gpio_int_mask);
c92ca04b 4081
c92ca04b
AR		 4082 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4083 val64 = readq(&bar0->adapter_status);
19a60522
SS		 4084 s2io_link(sp, LINK_DOWN);
4085 /* Link is down so unmaks link up interrupt */
4086 val64 = readq(&bar0->gpio_int_mask);
4087 val64 &= ~GPIO_INT_MASK_LINK_UP;
4088 val64 |= GPIO_INT_MASK_LINK_DOWN;
4089 writeq(val64, &bar0->gpio_int_mask);
a371a07d
K		 4090 }
4091 }
c92ca04b 4092 val64 = readq(&bar0->gpio_int_mask);
a371a07d
K		 4093}
4094
1da177e4
LT		 4095/**
4096 * s2io_isr - ISR handler of the device .
4097 * @irq: the irq of the device.
4098 * @dev_id: a void pointer to the dev structure of the NIC.
20346722
K		 4099 * Description: This function is the ISR handler of the device. It
4100 * identifies the reason for the interrupt and calls the relevant
4101 * service routines. As a contongency measure, this ISR allocates the
1da177e4
LT		 4102 * recv buffers, if their numbers are below the panic value which is
4103 * presently set to 25% of the original number of rcv buffers allocated.
4104 * Return value:
20346722 4105 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
1da177e4
LT		 4106 * IRQ_NONE: will be returned if interrupt is not from our device
4107 */
7d12e780 4108static irqreturn_t s2io_isr(int irq, void *dev_id)
1da177e4
LT		 4109{
4110 struct net_device *dev = (struct net_device *) dev_id;
1ee6dd77
RB		 4111 struct s2io_nic *sp = dev->priv;
4112 struct XENA_dev_config __iomem *bar0 = sp->bar0;
20346722 4113 int i;
19a60522 4114 u64 reason = 0;
1ee6dd77 4115 struct mac_info *mac_control;
1da177e4
LT		 4116 struct config_param *config;
4117
7ba013ac 4118 atomic_inc(&sp->isr_cnt);
1da177e4
LT		 4119 mac_control = &sp->mac_control;
4120 config = &sp->config;
4121
20346722 4122 /*
1da177e4
LT		 4123 * Identify the cause for interrupt and call the appropriate
4124 * interrupt handler. Causes for the interrupt could be;
4125 * 1. Rx of packet.
4126 * 2. Tx complete.
4127 * 3. Link down.
20346722 4128 * 4. Error in any functional blocks of the NIC.
1da177e4
LT		 4129 */
4130 reason = readq(&bar0->general_int_status);
4131
4132 if (!reason) {
19a60522
SS		 4133 /* The interrupt was not raised by us. */
4134 atomic_dec(&sp->isr_cnt);
4135 return IRQ_NONE;
4136 }
4137 else if (unlikely(reason == S2IO_MINUS_ONE) ) {
4138 /* Disable device and get out */
7ba013ac 4139 atomic_dec(&sp->isr_cnt);
1da177e4
LT		 4140 return IRQ_NONE;
4141 }
5d3213cc 4142
db874e65
SS		 4143 if (napi) {
4144 if (reason & GEN_INTR_RXTRAFFIC) {
19a60522 4145 if ( likely ( netif_rx_schedule_prep(dev)) ) {
db874e65 4146 __netif_rx_schedule(dev);
19a60522 4147 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
db874e65 4148 }
19a60522
SS		 4149 else
4150 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
db874e65
SS		 4151 }
4152 } else {
4153 /*
4154 * Rx handler is called by default, without checking for the
4155 * cause of interrupt.
4156 * rx_traffic_int reg is an R1 register, writing all 1's
4157 * will ensure that the actual interrupt causing bit get's
4158 * cleared and hence a read can be avoided.
4159 */
19a60522
SS		 4160 if (reason & GEN_INTR_RXTRAFFIC)
4161 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4162
db874e65
SS		 4163 for (i = 0; i < config->rx_ring_num; i++) {
4164 rx_intr_handler(&mac_control->rings[i]);
1da177e4
LT		 4165 }
4166 }
1da177e4 4167
863c11a9
AR		 4168 /*
4169 * tx_traffic_int reg is an R1 register, writing all 1's
4170 * will ensure that the actual interrupt causing bit get's
4171 * cleared and hence a read can be avoided.
4172 */
19a60522
SS		 4173 if (reason & GEN_INTR_TXTRAFFIC)
4174 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
fe113638 4175
863c11a9
AR		 4176 for (i = 0; i < config->tx_fifo_num; i++)
4177 tx_intr_handler(&mac_control->fifos[i]);
20346722 4178
a371a07d
K		 4179 if (reason & GEN_INTR_TXPIC)
4180 s2io_txpic_intr_handle(sp);
20346722
K		 4181 /*
4182 * If the Rx buffer count is below the panic threshold then
4183 * reallocate the buffers from the interrupt handler itself,
1da177e4
LT		 4184 * else schedule a tasklet to reallocate the buffers.
4185 */
db874e65
SS		 4186 if (!napi) {
4187 for (i = 0; i < config->rx_ring_num; i++)
4188 s2io_chk_rx_buffers(sp, i);
4189 }
4190
4191 writeq(0, &bar0->general_int_mask);
4192 readl(&bar0->general_int_status);
4193
7ba013ac 4194 atomic_dec(&sp->isr_cnt);
1da177e4
LT		 4195 return IRQ_HANDLED;
4196}
4197
7ba013ac
K		 4198/**
4199 * s2io_updt_stats -
4200 */
1ee6dd77 4201static void s2io_updt_stats(struct s2io_nic *sp)
7ba013ac 4202{
1ee6dd77 4203 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7ba013ac
K		 4204 u64 val64;
4205 int cnt = 0;
4206
4207 if (atomic_read(&sp->card_state) == CARD_UP) {
4208 /* Apprx 30us on a 133 MHz bus */
4209 val64 = SET_UPDT_CLICKS(10) |
4210 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4211 writeq(val64, &bar0->stat_cfg);
4212 do {
4213 udelay(100);
4214 val64 = readq(&bar0->stat_cfg);
4215 if (!(val64 & BIT(0)))
4216 break;
4217 cnt++;
4218 if (cnt == 5)
4219 break; /* Updt failed */
4220 } while(1);
75c30b13 4221 } else {
1ee6dd77 4222 memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
7ba013ac
K		 4223 }
4224}
4225
1da177e4 4226/**
20346722 4227 * s2io_get_stats - Updates the device statistics structure.
1da177e4
LT		 4228 * @dev : pointer to the device structure.
4229 * Description:
20346722 4230 * This function updates the device statistics structure in the s2io_nic
1da177e4
LT		 4231 * structure and returns a pointer to the same.
4232 * Return value:
4233 * pointer to the updated net_device_stats structure.
4234 */
4235
ac1f60db 4236static struct net_device_stats *s2io_get_stats(struct net_device *dev)
1da177e4 4237{
1ee6dd77
RB		 4238 struct s2io_nic *sp = dev->priv;
4239 struct mac_info *mac_control;
1da177e4
LT		 4240 struct config_param *config;
4241
20346722 4242
1da177e4
LT		 4243 mac_control = &sp->mac_control;
4244 config = &sp->config;
4245
7ba013ac
K		 4246 /* Configure Stats for immediate updt */
4247 s2io_updt_stats(sp);
4248
4249 sp->stats.tx_packets =
4250 le32_to_cpu(mac_control->stats_info->tmac_frms);
20346722
K		 4251 sp->stats.tx_errors =
4252 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4253 sp->stats.rx_errors =
ee705dba 4254 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
20346722
K		 4255 sp->stats.multicast =
4256 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
1da177e4 4257 sp->stats.rx_length_errors =
ee705dba 4258 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
1da177e4
LT		 4259
4260 return (&sp->stats);
4261}
4262
4263/**
4264 * s2io_set_multicast - entry point for multicast address enable/disable.
4265 * @dev : pointer to the device structure
4266 * Description:
20346722
K		 4267 * This function is a driver entry point which gets called by the kernel
4268 * whenever multicast addresses must be enabled/disabled. This also gets
1da177e4
LT		 4269 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4270 * determine, if multicast address must be enabled or if promiscuous mode
4271 * is to be disabled etc.
4272 * Return value:
4273 * void.
4274 */
4275
4276static void s2io_set_multicast(struct net_device *dev)
4277{
4278 int i, j, prev_cnt;
4279 struct dev_mc_list *mclist;
1ee6dd77
RB		 4280 struct s2io_nic *sp = dev->priv;
4281 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4282 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4283 0xfeffffffffffULL;
4284 u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
4285 void __iomem *add;
4286
4287 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4288 /* Enable all Multicast addresses */
4289 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4290 &bar0->rmac_addr_data0_mem);
4291 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4292 &bar0->rmac_addr_data1_mem);
4293 val64 = RMAC_ADDR_CMD_MEM_WE |
4294 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4295 RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
4296 writeq(val64, &bar0->rmac_addr_cmd_mem);
4297 /* Wait till command completes */
c92ca04b
AR		 4298 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4299 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
1da177e4
LT		 4300
4301 sp->m_cast_flg = 1;
4302 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
4303 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4304 /* Disable all Multicast addresses */
4305 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4306 &bar0->rmac_addr_data0_mem);
5e25b9dd
K		 4307 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4308 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4309 val64 = RMAC_ADDR_CMD_MEM_WE |
4310 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4311 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4312 writeq(val64, &bar0->rmac_addr_cmd_mem);
4313 /* Wait till command completes */
c92ca04b
AR		 4314 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4315 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
1da177e4
LT		 4316
4317 sp->m_cast_flg = 0;
4318 sp->all_multi_pos = 0;
4319 }
4320
4321 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4322 /* Put the NIC into promiscuous mode */
4323 add = &bar0->mac_cfg;
4324 val64 = readq(&bar0->mac_cfg);
4325 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4326
4327 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4328 writel((u32) val64, add);
4329 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4330 writel((u32) (val64 >> 32), (add + 4));
4331
4332 val64 = readq(&bar0->mac_cfg);
4333 sp->promisc_flg = 1;
776bd20f 4334 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
1da177e4
LT		 4335 dev->name);
4336 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4337 /* Remove the NIC from promiscuous mode */
4338 add = &bar0->mac_cfg;
4339 val64 = readq(&bar0->mac_cfg);
4340 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4341
4342 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4343 writel((u32) val64, add);
4344 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4345 writel((u32) (val64 >> 32), (add + 4));
4346
4347 val64 = readq(&bar0->mac_cfg);
4348 sp->promisc_flg = 0;
776bd20f 4349 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
1da177e4
LT		 4350 dev->name);
4351 }
4352
4353 /* Update individual M_CAST address list */
4354 if ((!sp->m_cast_flg) && dev->mc_count) {
4355 if (dev->mc_count >
4356 (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
4357 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4358 dev->name);
4359 DBG_PRINT(ERR_DBG, "can be added, please enable ");
4360 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4361 return;
4362 }
4363
4364 prev_cnt = sp->mc_addr_count;
4365 sp->mc_addr_count = dev->mc_count;
4366
4367 /* Clear out the previous list of Mc in the H/W. */
4368 for (i = 0; i < prev_cnt; i++) {
4369 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4370 &bar0->rmac_addr_data0_mem);
4371 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 4372 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4373 val64 = RMAC_ADDR_CMD_MEM_WE |
4374 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4375 RMAC_ADDR_CMD_MEM_OFFSET
4376 (MAC_MC_ADDR_START_OFFSET + i);
4377 writeq(val64, &bar0->rmac_addr_cmd_mem);
4378
4379 /* Wait for command completes */
c92ca04b
AR		 4380 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4381 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
1da177e4
LT		 4382 DBG_PRINT(ERR_DBG, "%s: Adding ",
4383 dev->name);
4384 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4385 return;
4386 }
4387 }
4388
4389 /* Create the new Rx filter list and update the same in H/W. */
4390 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4391 i++, mclist = mclist->next) {
4392 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4393 ETH_ALEN);
a7a80d5a 4394 mac_addr = 0;
1da177e4
LT		 4395 for (j = 0; j < ETH_ALEN; j++) {
4396 mac_addr |= mclist->dmi_addr[j];
4397 mac_addr <<= 8;
4398 }
4399 mac_addr >>= 8;
4400 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4401 &bar0->rmac_addr_data0_mem);
4402 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 4403 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4404 val64 = RMAC_ADDR_CMD_MEM_WE |
4405 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4406 RMAC_ADDR_CMD_MEM_OFFSET
4407 (i + MAC_MC_ADDR_START_OFFSET);
4408 writeq(val64, &bar0->rmac_addr_cmd_mem);
4409
4410 /* Wait for command completes */
c92ca04b
AR		 4411 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4412 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
1da177e4
LT		 4413 DBG_PRINT(ERR_DBG, "%s: Adding ",
4414 dev->name);
4415 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4416 return;
4417 }
4418 }
4419 }
4420}
4421
4422/**
20346722 4423 * s2io_set_mac_addr - Programs the Xframe mac address
1da177e4
LT		 4424 * @dev : pointer to the device structure.
4425 * @addr: a uchar pointer to the new mac address which is to be set.
20346722 4426 * Description : This procedure will program the Xframe to receive
1da177e4 4427 * frames with new Mac Address
20346722 4428 * Return value: SUCCESS on success and an appropriate (-)ve integer
1da177e4
LT		 4429 * as defined in errno.h file on failure.
4430 */
4431
26df54bf 4432static int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
1da177e4 4433{
1ee6dd77
RB		 4434 struct s2io_nic *sp = dev->priv;
4435 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4436 register u64 val64, mac_addr = 0;
4437 int i;
4438
20346722 4439 /*
1da177e4
LT		 4440 * Set the new MAC address as the new unicast filter and reflect this
4441 * change on the device address registered with the OS. It will be
20346722 4442 * at offset 0.
1da177e4
LT		 4443 */
4444 for (i = 0; i < ETH_ALEN; i++) {
4445 mac_addr <<= 8;
4446 mac_addr |= addr[i];
4447 }
4448
4449 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4450 &bar0->rmac_addr_data0_mem);
4451
4452 val64 =
4453 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4454 RMAC_ADDR_CMD_MEM_OFFSET(0);
4455 writeq(val64, &bar0->rmac_addr_cmd_mem);
4456 /* Wait till command completes */
c92ca04b
AR		 4457 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4458 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
1da177e4
LT		 4459 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
4460 return FAILURE;
4461 }
4462
4463 return SUCCESS;
4464}
4465
4466/**
20346722 4467 * s2io_ethtool_sset - Sets different link parameters.
1da177e4
LT		 4468 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
4469 * @info: pointer to the structure with parameters given by ethtool to set
4470 * link information.
4471 * Description:
20346722 4472 * The function sets different link parameters provided by the user onto
1da177e4
LT		 4473 * the NIC.
4474 * Return value:
4475 * 0 on success.
4476*/
4477
4478static int s2io_ethtool_sset(struct net_device *dev,
4479 struct ethtool_cmd *info)
4480{
1ee6dd77 4481 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 4482 if ((info->autoneg == AUTONEG_ENABLE) ||
4483 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
4484 return -EINVAL;
4485 else {
4486 s2io_close(sp->dev);
4487 s2io_open(sp->dev);
4488 }
4489
4490 return 0;
4491}
4492
4493/**
20346722 4494 * s2io_ethtol_gset - Return link specific information.
1da177e4
LT		 4495 * @sp : private member of the device structure, pointer to the
4496 * s2io_nic structure.
4497 * @info : pointer to the structure with parameters given by ethtool
4498 * to return link information.
4499 * Description:
4500 * Returns link specific information like speed, duplex etc.. to ethtool.
4501 * Return value :
4502 * return 0 on success.
4503 */
4504
4505static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
4506{
1ee6dd77 4507 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 4508 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4509 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4510 info->port = PORT_FIBRE;
4511 /* info->transceiver?? TODO */
4512
4513 if (netif_carrier_ok(sp->dev)) {
4514 info->speed = 10000;
4515 info->duplex = DUPLEX_FULL;
4516 } else {
4517 info->speed = -1;
4518 info->duplex = -1;
4519 }
4520
4521 info->autoneg = AUTONEG_DISABLE;
4522 return 0;
4523}
4524
4525/**
20346722
K		 4526 * s2io_ethtool_gdrvinfo - Returns driver specific information.
4527 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 4528 * s2io_nic structure.
4529 * @info : pointer to the structure with parameters given by ethtool to
4530 * return driver information.
4531 * Description:
4532 * Returns driver specefic information like name, version etc.. to ethtool.
4533 * Return value:
4534 * void
4535 */
4536
4537static void s2io_ethtool_gdrvinfo(struct net_device *dev,
4538 struct ethtool_drvinfo *info)
4539{
1ee6dd77 4540 struct s2io_nic *sp = dev->priv;
1da177e4 4541
dbc2309d
JL		 4542 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
4543 strncpy(info->version, s2io_driver_version, sizeof(info->version));
4544 strncpy(info->fw_version, "", sizeof(info->fw_version));
4545 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
1da177e4
LT		 4546 info->regdump_len = XENA_REG_SPACE;
4547 info->eedump_len = XENA_EEPROM_SPACE;
4548 info->testinfo_len = S2IO_TEST_LEN;
4549 info->n_stats = S2IO_STAT_LEN;
4550}
4551
4552/**
4553 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
20346722 4554 * @sp: private member of the device structure, which is a pointer to the
1da177e4 4555 * s2io_nic structure.
20346722 4556 * @regs : pointer to the structure with parameters given by ethtool for
1da177e4
LT		 4557 * dumping the registers.
4558 * @reg_space: The input argumnet into which all the registers are dumped.
4559 * Description:
4560 * Dumps the entire register space of xFrame NIC into the user given
4561 * buffer area.
4562 * Return value :
4563 * void .
4564*/
4565
4566static void s2io_ethtool_gregs(struct net_device *dev,
4567 struct ethtool_regs *regs, void *space)
4568{
4569 int i;
4570 u64 reg;
4571 u8 *reg_space = (u8 *) space;
1ee6dd77 4572 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 4573
4574 regs->len = XENA_REG_SPACE;
4575 regs->version = sp->pdev->subsystem_device;
4576
4577 for (i = 0; i < regs->len; i += 8) {
4578 reg = readq(sp->bar0 + i);
4579 memcpy((reg_space + i), &reg, 8);
4580 }
4581}
4582
4583/**
4584 * s2io_phy_id - timer function that alternates adapter LED.
20346722 4585 * @data : address of the private member of the device structure, which
1da177e4 4586 * is a pointer to the s2io_nic structure, provided as an u32.
20346722
K		 4587 * Description: This is actually the timer function that alternates the
4588 * adapter LED bit of the adapter control bit to set/reset every time on
4589 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
1da177e4
LT		 4590 * once every second.
4591*/
4592static void s2io_phy_id(unsigned long data)
4593{
1ee6dd77
RB		 4594 struct s2io_nic *sp = (struct s2io_nic *) data;
4595 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4596 u64 val64 = 0;
4597 u16 subid;
4598
4599 subid = sp->pdev->subsystem_device;
541ae68f
K		 4600 if ((sp->device_type == XFRAME_II_DEVICE) ||
4601 ((subid & 0xFF) >= 0x07)) {
1da177e4
LT		 4602 val64 = readq(&bar0->gpio_control);
4603 val64 ^= GPIO_CTRL_GPIO_0;
4604 writeq(val64, &bar0->gpio_control);
4605 } else {
4606 val64 = readq(&bar0->adapter_control);
4607 val64 ^= ADAPTER_LED_ON;
4608 writeq(val64, &bar0->adapter_control);
4609 }
4610
4611 mod_timer(&sp->id_timer, jiffies + HZ / 2);
4612}
4613
4614/**
4615 * s2io_ethtool_idnic - To physically identify the nic on the system.
4616 * @sp : private member of the device structure, which is a pointer to the
4617 * s2io_nic structure.
20346722 4618 * @id : pointer to the structure with identification parameters given by
1da177e4
LT		 4619 * ethtool.
4620 * Description: Used to physically identify the NIC on the system.
20346722 4621 * The Link LED will blink for a time specified by the user for
1da177e4 4622 * identification.
20346722 4623 * NOTE: The Link has to be Up to be able to blink the LED. Hence
1da177e4
LT		 4624 * identification is possible only if it's link is up.
4625 * Return value:
4626 * int , returns 0 on success
4627 */
4628
4629static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
4630{
4631 u64 val64 = 0, last_gpio_ctrl_val;
1ee6dd77
RB		 4632 struct s2io_nic *sp = dev->priv;
4633 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4634 u16 subid;
4635
4636 subid = sp->pdev->subsystem_device;
4637 last_gpio_ctrl_val = readq(&bar0->gpio_control);
541ae68f
K		 4638 if ((sp->device_type == XFRAME_I_DEVICE) &&
4639 ((subid & 0xFF) < 0x07)) {
1da177e4
LT		 4640 val64 = readq(&bar0->adapter_control);
4641 if (!(val64 & ADAPTER_CNTL_EN)) {
4642 printk(KERN_ERR
4643 "Adapter Link down, cannot blink LED\n");
4644 return -EFAULT;
4645 }
4646 }
4647 if (sp->id_timer.function == NULL) {
4648 init_timer(&sp->id_timer);
4649 sp->id_timer.function = s2io_phy_id;
4650 sp->id_timer.data = (unsigned long) sp;
4651 }
4652 mod_timer(&sp->id_timer, jiffies);
4653 if (data)
20346722 4654 msleep_interruptible(data * HZ);
1da177e4 4655 else
20346722 4656 msleep_interruptible(MAX_FLICKER_TIME);
1da177e4
LT		 4657 del_timer_sync(&sp->id_timer);
4658
541ae68f 4659 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
1da177e4
LT		 4660 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
4661 last_gpio_ctrl_val = readq(&bar0->gpio_control);
4662 }
4663
4664 return 0;
4665}
4666
4667/**
4668 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
20346722
K		 4669 * @sp : private member of the device structure, which is a pointer to the
4670 * s2io_nic structure.
1da177e4
LT		 4671 * @ep : pointer to the structure with pause parameters given by ethtool.
4672 * Description:
4673 * Returns the Pause frame generation and reception capability of the NIC.
4674 * Return value:
4675 * void
4676 */
4677static void s2io_ethtool_getpause_data(struct net_device *dev,
4678 struct ethtool_pauseparam *ep)
4679{
4680 u64 val64;
1ee6dd77
RB		 4681 struct s2io_nic *sp = dev->priv;
4682 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4683
4684 val64 = readq(&bar0->rmac_pause_cfg);
4685 if (val64 & RMAC_PAUSE_GEN_ENABLE)
4686 ep->tx_pause = TRUE;
4687 if (val64 & RMAC_PAUSE_RX_ENABLE)
4688 ep->rx_pause = TRUE;
4689 ep->autoneg = FALSE;
4690}
4691
4692/**
4693 * s2io_ethtool_setpause_data - set/reset pause frame generation.
20346722 4694 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 4695 * s2io_nic structure.
4696 * @ep : pointer to the structure with pause parameters given by ethtool.
4697 * Description:
4698 * It can be used to set or reset Pause frame generation or reception
4699 * support of the NIC.
4700 * Return value:
4701 * int, returns 0 on Success
4702 */
4703
4704static int s2io_ethtool_setpause_data(struct net_device *dev,
20346722 4705 struct ethtool_pauseparam *ep)
1da177e4
LT		 4706{
4707 u64 val64;
1ee6dd77
RB		 4708 struct s2io_nic *sp = dev->priv;
4709 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4710
4711 val64 = readq(&bar0->rmac_pause_cfg);
4712 if (ep->tx_pause)
4713 val64 |= RMAC_PAUSE_GEN_ENABLE;
4714 else
4715 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
4716 if (ep->rx_pause)
4717 val64 |= RMAC_PAUSE_RX_ENABLE;
4718 else
4719 val64 &= ~RMAC_PAUSE_RX_ENABLE;
4720 writeq(val64, &bar0->rmac_pause_cfg);
4721 return 0;
4722}
4723
4724/**
4725 * read_eeprom - reads 4 bytes of data from user given offset.
20346722 4726 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 4727 * s2io_nic structure.
4728 * @off : offset at which the data must be written
4729 * @data : Its an output parameter where the data read at the given
20346722 4730 * offset is stored.
1da177e4 4731 * Description:
20346722 4732 * Will read 4 bytes of data from the user given offset and return the
1da177e4
LT		 4733 * read data.
4734 * NOTE: Will allow to read only part of the EEPROM visible through the
4735 * I2C bus.
4736 * Return value:
4737 * -1 on failure and 0 on success.
4738 */
4739
4740#define S2IO_DEV_ID 5
1ee6dd77 4741static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
1da177e4
LT		 4742{
4743 int ret = -1;
4744 u32 exit_cnt = 0;
4745 u64 val64;
1ee6dd77 4746 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 4747
ad4ebed0 4748 if (sp->device_type == XFRAME_I_DEVICE) {
4749 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4750 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
4751 I2C_CONTROL_CNTL_START;
4752 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
1da177e4 4753
ad4ebed0 4754 while (exit_cnt < 5) {
4755 val64 = readq(&bar0->i2c_control);
4756 if (I2C_CONTROL_CNTL_END(val64)) {
4757 *data = I2C_CONTROL_GET_DATA(val64);
4758 ret = 0;
4759 break;
4760 }
4761 msleep(50);
4762 exit_cnt++;
1da177e4 4763 }
1da177e4
LT		 4764 }
4765
ad4ebed0 4766 if (sp->device_type == XFRAME_II_DEVICE) {
4767 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 4768 SPI_CONTROL_BYTECNT(0x3) |
ad4ebed0 4769 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
4770 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4771 val64 |= SPI_CONTROL_REQ;
4772 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4773 while (exit_cnt < 5) {
4774 val64 = readq(&bar0->spi_control);
4775 if (val64 & SPI_CONTROL_NACK) {
4776 ret = 1;
4777 break;
4778 } else if (val64 & SPI_CONTROL_DONE) {
4779 *data = readq(&bar0->spi_data);
4780 *data &= 0xffffff;
4781 ret = 0;
4782 break;
4783 }
4784 msleep(50);
4785 exit_cnt++;
4786 }
4787 }
1da177e4
LT		 4788 return ret;
4789}
4790
4791/**
4792 * write_eeprom - actually writes the relevant part of the data value.
4793 * @sp : private member of the device structure, which is a pointer to the
4794 * s2io_nic structure.
4795 * @off : offset at which the data must be written
4796 * @data : The data that is to be written
20346722 4797 * @cnt : Number of bytes of the data that are actually to be written into
1da177e4
LT		 4798 * the Eeprom. (max of 3)
4799 * Description:
4800 * Actually writes the relevant part of the data value into the Eeprom
4801 * through the I2C bus.
4802 * Return value:
4803 * 0 on success, -1 on failure.
4804 */
4805
1ee6dd77 4806static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
1da177e4
LT		 4807{
4808 int exit_cnt = 0, ret = -1;
4809 u64 val64;
1ee6dd77 4810 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 4811
ad4ebed0 4812 if (sp->device_type == XFRAME_I_DEVICE) {
4813 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4814 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
4815 I2C_CONTROL_CNTL_START;
4816 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4817
4818 while (exit_cnt < 5) {
4819 val64 = readq(&bar0->i2c_control);
4820 if (I2C_CONTROL_CNTL_END(val64)) {
4821 if (!(val64 & I2C_CONTROL_NACK))
4822 ret = 0;
4823 break;
4824 }
4825 msleep(50);
4826 exit_cnt++;
4827 }
4828 }
1da177e4 4829
ad4ebed0 4830 if (sp->device_type == XFRAME_II_DEVICE) {
4831 int write_cnt = (cnt == 8) ? 0 : cnt;
4832 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
4833
4834 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 4835 SPI_CONTROL_BYTECNT(write_cnt) |
ad4ebed0 4836 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
4837 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4838 val64 |= SPI_CONTROL_REQ;
4839 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4840 while (exit_cnt < 5) {
4841 val64 = readq(&bar0->spi_control);
4842 if (val64 & SPI_CONTROL_NACK) {
4843 ret = 1;
4844 break;
4845 } else if (val64 & SPI_CONTROL_DONE) {
1da177e4 4846 ret = 0;
ad4ebed0 4847 break;
4848 }
4849 msleep(50);
4850 exit_cnt++;
1da177e4 4851 }
1da177e4 4852 }
1da177e4
LT		 4853 return ret;
4854}
1ee6dd77 4855static void s2io_vpd_read(struct s2io_nic *nic)
9dc737a7 4856{
b41477f3
AR		 4857 u8 *vpd_data;
4858 u8 data;
9dc737a7
AR		 4859 int i=0, cnt, fail = 0;
4860 int vpd_addr = 0x80;
4861
4862 if (nic->device_type == XFRAME_II_DEVICE) {
4863 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
4864 vpd_addr = 0x80;
4865 }
4866 else {
4867 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
4868 vpd_addr = 0x50;
4869 }
19a60522 4870 strcpy(nic->serial_num, "NOT AVAILABLE");
9dc737a7 4871
b41477f3
AR		 4872 vpd_data = kmalloc(256, GFP_KERNEL);
4873 if (!vpd_data)
4874 return;
4875
9dc737a7
AR		 4876 for (i = 0; i < 256; i +=4 ) {
4877 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
4878 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
4879 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
4880 for (cnt = 0; cnt <5; cnt++) {
4881 msleep(2);
4882 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
4883 if (data == 0x80)
4884 break;
4885 }
4886 if (cnt >= 5) {
4887 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
4888 fail = 1;
4889 break;
4890 }
4891 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
4892 (u32 *)&vpd_data[i]);
4893 }
19a60522
SS		 4894
4895 if(!fail) {
4896 /* read serial number of adapter */
4897 for (cnt = 0; cnt < 256; cnt++) {
4898 if ((vpd_data[cnt] == 'S') &&
4899 (vpd_data[cnt+1] == 'N') &&
4900 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
4901 memset(nic->serial_num, 0, VPD_STRING_LEN);
4902 memcpy(nic->serial_num, &vpd_data[cnt + 3],
4903 vpd_data[cnt+2]);
4904 break;
4905 }
4906 }
4907 }
4908
4909 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
9dc737a7
AR		 4910 memset(nic->product_name, 0, vpd_data[1]);
4911 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
4912 }
b41477f3 4913 kfree(vpd_data);
9dc737a7
AR		 4914}
4915
1da177e4
LT		 4916/**
4917 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
4918 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
20346722 4919 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 4920 * containing all relevant information.
4921 * @data_buf : user defined value to be written into Eeprom.
4922 * Description: Reads the values stored in the Eeprom at given offset
4923 * for a given length. Stores these values int the input argument data
4924 * buffer 'data_buf' and returns these to the caller (ethtool.)
4925 * Return value:
4926 * int 0 on success
4927 */
4928
4929static int s2io_ethtool_geeprom(struct net_device *dev,
20346722 4930 struct ethtool_eeprom *eeprom, u8 * data_buf)
1da177e4 4931{
ad4ebed0 4932 u32 i, valid;
4933 u64 data;
1ee6dd77 4934 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 4935
4936 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
4937
4938 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
4939 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
4940
4941 for (i = 0; i < eeprom->len; i += 4) {
4942 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
4943 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
4944 return -EFAULT;
4945 }
4946 valid = INV(data);
4947 memcpy((data_buf + i), &valid, 4);
4948 }
4949 return 0;
4950}
4951
4952/**
4953 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
4954 * @sp : private member of the device structure, which is a pointer to the
4955 * s2io_nic structure.
20346722 4956 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 4957 * containing all relevant information.
4958 * @data_buf ; user defined value to be written into Eeprom.
4959 * Description:
4960 * Tries to write the user provided value in the Eeprom, at the offset
4961 * given by the user.
4962 * Return value:
4963 * 0 on success, -EFAULT on failure.
4964 */
4965
4966static int s2io_ethtool_seeprom(struct net_device *dev,
4967 struct ethtool_eeprom *eeprom,
4968 u8 * data_buf)
4969{
4970 int len = eeprom->len, cnt = 0;
ad4ebed0 4971 u64 valid = 0, data;
1ee6dd77 4972 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 4973
4974 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
4975 DBG_PRINT(ERR_DBG,
4976 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
4977 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
4978 eeprom->magic);
4979 return -EFAULT;
4980 }
4981
4982 while (len) {
4983 data = (u32) data_buf[cnt] & 0x000000FF;
4984 if (data) {
4985 valid = (u32) (data << 24);
4986 } else
4987 valid = data;
4988
4989 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
4990 DBG_PRINT(ERR_DBG,
4991 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
4992 DBG_PRINT(ERR_DBG,
4993 "write into the specified offset\n");
4994 return -EFAULT;
4995 }
4996 cnt++;
4997 len--;
4998 }
4999
5000 return 0;
5001}
5002
5003/**
20346722
K		 5004 * s2io_register_test - reads and writes into all clock domains.
5005 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5006 * s2io_nic structure.
5007 * @data : variable that returns the result of each of the test conducted b
5008 * by the driver.
5009 * Description:
5010 * Read and write into all clock domains. The NIC has 3 clock domains,
5011 * see that registers in all the three regions are accessible.
5012 * Return value:
5013 * 0 on success.
5014 */
5015
1ee6dd77 5016static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5017{
1ee6dd77 5018 struct XENA_dev_config __iomem *bar0 = sp->bar0;
ad4ebed0 5019 u64 val64 = 0, exp_val;
1da177e4
LT		 5020 int fail = 0;
5021
20346722
K		 5022 val64 = readq(&bar0->pif_rd_swapper_fb);
5023 if (val64 != 0x123456789abcdefULL) {
1da177e4
LT		 5024 fail = 1;
5025 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5026 }
5027
5028 val64 = readq(&bar0->rmac_pause_cfg);
5029 if (val64 != 0xc000ffff00000000ULL) {
5030 fail = 1;
5031 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5032 }
5033
5034 val64 = readq(&bar0->rx_queue_cfg);
ad4ebed0 5035 if (sp->device_type == XFRAME_II_DEVICE)
5036 exp_val = 0x0404040404040404ULL;
5037 else
5038 exp_val = 0x0808080808080808ULL;
5039 if (val64 != exp_val) {
1da177e4
LT		 5040 fail = 1;
5041 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5042 }
5043
5044 val64 = readq(&bar0->xgxs_efifo_cfg);
5045 if (val64 != 0x000000001923141EULL) {
5046 fail = 1;
5047 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5048 }
5049
5050 val64 = 0x5A5A5A5A5A5A5A5AULL;
5051 writeq(val64, &bar0->xmsi_data);
5052 val64 = readq(&bar0->xmsi_data);
5053 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5054 fail = 1;
5055 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5056 }
5057
5058 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5059 writeq(val64, &bar0->xmsi_data);
5060 val64 = readq(&bar0->xmsi_data);
5061 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5062 fail = 1;
5063 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5064 }
5065
5066 *data = fail;
ad4ebed0 5067 return fail;
1da177e4
LT		 5068}
5069
5070/**
20346722 5071 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
1da177e4
LT		 5072 * @sp : private member of the device structure, which is a pointer to the
5073 * s2io_nic structure.
5074 * @data:variable that returns the result of each of the test conducted by
5075 * the driver.
5076 * Description:
20346722 5077 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
1da177e4
LT		 5078 * register.
5079 * Return value:
5080 * 0 on success.
5081 */
5082
1ee6dd77 5083static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 5084{
5085 int fail = 0;
ad4ebed0 5086 u64 ret_data, org_4F0, org_7F0;
5087 u8 saved_4F0 = 0, saved_7F0 = 0;
5088 struct net_device *dev = sp->dev;
1da177e4
LT		 5089
5090 /* Test Write Error at offset 0 */
ad4ebed0 5091 /* Note that SPI interface allows write access to all areas
5092 * of EEPROM. Hence doing all negative testing only for Xframe I.
5093 */
5094 if (sp->device_type == XFRAME_I_DEVICE)
5095 if (!write_eeprom(sp, 0, 0, 3))
5096 fail = 1;
5097
5098 /* Save current values at offsets 0x4F0 and 0x7F0 */
5099 if (!read_eeprom(sp, 0x4F0, &org_4F0))
5100 saved_4F0 = 1;
5101 if (!read_eeprom(sp, 0x7F0, &org_7F0))
5102 saved_7F0 = 1;
1da177e4
LT		 5103
5104 /* Test Write at offset 4f0 */
ad4ebed0 5105 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
1da177e4
LT		 5106 fail = 1;
5107 if (read_eeprom(sp, 0x4F0, &ret_data))
5108 fail = 1;
5109
ad4ebed0 5110 if (ret_data != 0x012345) {
26b7625c
AM		 5111 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5112 "Data written %llx Data read %llx\n",
5113 dev->name, (unsigned long long)0x12345,
5114 (unsigned long long)ret_data);
1da177e4 5115 fail = 1;
ad4ebed0 5116 }
1da177e4
LT		 5117
5118 /* Reset the EEPROM data go FFFF */
ad4ebed0 5119 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
1da177e4
LT		 5120
5121 /* Test Write Request Error at offset 0x7c */
ad4ebed0 5122 if (sp->device_type == XFRAME_I_DEVICE)
5123 if (!write_eeprom(sp, 0x07C, 0, 3))
5124 fail = 1;
1da177e4 5125
ad4ebed0 5126 /* Test Write Request at offset 0x7f0 */
5127 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
1da177e4 5128 fail = 1;
ad4ebed0 5129 if (read_eeprom(sp, 0x7F0, &ret_data))
1da177e4
LT		 5130 fail = 1;
5131
ad4ebed0 5132 if (ret_data != 0x012345) {
26b7625c
AM		 5133 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
5134 "Data written %llx Data read %llx\n",
5135 dev->name, (unsigned long long)0x12345,
5136 (unsigned long long)ret_data);
1da177e4 5137 fail = 1;
ad4ebed0 5138 }
1da177e4
LT		 5139
5140 /* Reset the EEPROM data go FFFF */
ad4ebed0 5141 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
1da177e4 5142
ad4ebed0 5143 if (sp->device_type == XFRAME_I_DEVICE) {
5144 /* Test Write Error at offset 0x80 */
5145 if (!write_eeprom(sp, 0x080, 0, 3))
5146 fail = 1;
1da177e4 5147
ad4ebed0 5148 /* Test Write Error at offset 0xfc */
5149 if (!write_eeprom(sp, 0x0FC, 0, 3))
5150 fail = 1;
1da177e4 5151
ad4ebed0 5152 /* Test Write Error at offset 0x100 */
5153 if (!write_eeprom(sp, 0x100, 0, 3))
5154 fail = 1;
1da177e4 5155
ad4ebed0 5156 /* Test Write Error at offset 4ec */
5157 if (!write_eeprom(sp, 0x4EC, 0, 3))
5158 fail = 1;
5159 }
5160
5161 /* Restore values at offsets 0x4F0 and 0x7F0 */
5162 if (saved_4F0)
5163 write_eeprom(sp, 0x4F0, org_4F0, 3);
5164 if (saved_7F0)
5165 write_eeprom(sp, 0x7F0, org_7F0, 3);
1da177e4
LT		 5166
5167 *data = fail;
ad4ebed0 5168 return fail;
1da177e4
LT		 5169}
5170
5171/**
5172 * s2io_bist_test - invokes the MemBist test of the card .
20346722 5173 * @sp : private member of the device structure, which is a pointer to the
1da177e4 5174 * s2io_nic structure.
20346722 5175 * @data:variable that returns the result of each of the test conducted by
1da177e4
LT		 5176 * the driver.
5177 * Description:
5178 * This invokes the MemBist test of the card. We give around
5179 * 2 secs time for the Test to complete. If it's still not complete
20346722 5180 * within this peiod, we consider that the test failed.
1da177e4
LT		 5181 * Return value:
5182 * 0 on success and -1 on failure.
5183 */
5184
1ee6dd77 5185static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 5186{
5187 u8 bist = 0;
5188 int cnt = 0, ret = -1;
5189
5190 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5191 bist |= PCI_BIST_START;
5192 pci_write_config_word(sp->pdev, PCI_BIST, bist);
5193
5194 while (cnt < 20) {
5195 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5196 if (!(bist & PCI_BIST_START)) {
5197 *data = (bist & PCI_BIST_CODE_MASK);
5198 ret = 0;
5199 break;
5200 }
5201 msleep(100);
5202 cnt++;
5203 }
5204
5205 return ret;
5206}
5207
5208/**
20346722
K		 5209 * s2io-link_test - verifies the link state of the nic
5210 * @sp ; private member of the device structure, which is a pointer to the
1da177e4
LT		 5211 * s2io_nic structure.
5212 * @data: variable that returns the result of each of the test conducted by
5213 * the driver.
5214 * Description:
20346722 5215 * The function verifies the link state of the NIC and updates the input
1da177e4
LT		 5216 * argument 'data' appropriately.
5217 * Return value:
5218 * 0 on success.
5219 */
5220
1ee6dd77 5221static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5222{
1ee6dd77 5223 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5224 u64 val64;
5225
5226 val64 = readq(&bar0->adapter_status);
c92ca04b 5227 if(!(LINK_IS_UP(val64)))
1da177e4 5228 *data = 1;
c92ca04b
AR		 5229 else
5230 *data = 0;
1da177e4 5231
b41477f3 5232 return *data;
1da177e4
LT		 5233}
5234
5235/**
20346722
K		 5236 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
5237 * @sp - private member of the device structure, which is a pointer to the
1da177e4 5238 * s2io_nic structure.
20346722 5239 * @data - variable that returns the result of each of the test
1da177e4
LT		 5240 * conducted by the driver.
5241 * Description:
20346722 5242 * This is one of the offline test that tests the read and write
1da177e4
LT		 5243 * access to the RldRam chip on the NIC.
5244 * Return value:
5245 * 0 on success.
5246 */
5247
1ee6dd77 5248static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5249{
1ee6dd77 5250 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5251 u64 val64;
ad4ebed0 5252 int cnt, iteration = 0, test_fail = 0;
1da177e4
LT		 5253
5254 val64 = readq(&bar0->adapter_control);
5255 val64 &= ~ADAPTER_ECC_EN;
5256 writeq(val64, &bar0->adapter_control);
5257
5258 val64 = readq(&bar0->mc_rldram_test_ctrl);
5259 val64 |= MC_RLDRAM_TEST_MODE;
ad4ebed0 5260 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 5261
5262 val64 = readq(&bar0->mc_rldram_mrs);
5263 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
5264 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5265
5266 val64 |= MC_RLDRAM_MRS_ENABLE;
5267 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5268
5269 while (iteration < 2) {
5270 val64 = 0x55555555aaaa0000ULL;
5271 if (iteration == 1) {
5272 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5273 }
5274 writeq(val64, &bar0->mc_rldram_test_d0);
5275
5276 val64 = 0xaaaa5a5555550000ULL;
5277 if (iteration == 1) {
5278 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5279 }
5280 writeq(val64, &bar0->mc_rldram_test_d1);
5281
5282 val64 = 0x55aaaaaaaa5a0000ULL;
5283 if (iteration == 1) {
5284 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5285 }
5286 writeq(val64, &bar0->mc_rldram_test_d2);
5287
ad4ebed0 5288 val64 = (u64) (0x0000003ffffe0100ULL);
1da177e4
LT		 5289 writeq(val64, &bar0->mc_rldram_test_add);
5290
ad4ebed0 5291 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
5292 MC_RLDRAM_TEST_GO;
5293 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 5294
5295 for (cnt = 0; cnt < 5; cnt++) {
5296 val64 = readq(&bar0->mc_rldram_test_ctrl);
5297 if (val64 & MC_RLDRAM_TEST_DONE)
5298 break;
5299 msleep(200);
5300 }
5301
5302 if (cnt == 5)
5303 break;
5304
ad4ebed0 5305 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
5306 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 5307
5308 for (cnt = 0; cnt < 5; cnt++) {
5309 val64 = readq(&bar0->mc_rldram_test_ctrl);
5310 if (val64 & MC_RLDRAM_TEST_DONE)
5311 break;
5312 msleep(500);
5313 }
5314
5315 if (cnt == 5)
5316 break;
5317
5318 val64 = readq(&bar0->mc_rldram_test_ctrl);
ad4ebed0 5319 if (!(val64 & MC_RLDRAM_TEST_PASS))
5320 test_fail = 1;
1da177e4
LT		 5321
5322 iteration++;
5323 }
5324
ad4ebed0 5325 *data = test_fail;
1da177e4 5326
ad4ebed0 5327 /* Bring the adapter out of test mode */
5328 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
5329
5330 return test_fail;
1da177e4
LT		 5331}
5332
5333/**
5334 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
5335 * @sp : private member of the device structure, which is a pointer to the
5336 * s2io_nic structure.
5337 * @ethtest : pointer to a ethtool command specific structure that will be
5338 * returned to the user.
20346722 5339 * @data : variable that returns the result of each of the test
1da177e4
LT		 5340 * conducted by the driver.
5341 * Description:
5342 * This function conducts 6 tests ( 4 offline and 2 online) to determine
5343 * the health of the card.
5344 * Return value:
5345 * void
5346 */
5347
5348static void s2io_ethtool_test(struct net_device *dev,
5349 struct ethtool_test *ethtest,
5350 uint64_t * data)
5351{
1ee6dd77 5352 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5353 int orig_state = netif_running(sp->dev);
5354
5355 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
5356 /* Offline Tests. */
20346722 5357 if (orig_state)
1da177e4 5358 s2io_close(sp->dev);
1da177e4
LT		 5359
5360 if (s2io_register_test(sp, &data[0]))
5361 ethtest->flags |= ETH_TEST_FL_FAILED;
5362
5363 s2io_reset(sp);
1da177e4
LT		 5364
5365 if (s2io_rldram_test(sp, &data[3]))
5366 ethtest->flags |= ETH_TEST_FL_FAILED;
5367
5368 s2io_reset(sp);
1da177e4
LT		 5369
5370 if (s2io_eeprom_test(sp, &data[1]))
5371 ethtest->flags |= ETH_TEST_FL_FAILED;
5372
5373 if (s2io_bist_test(sp, &data[4]))
5374 ethtest->flags |= ETH_TEST_FL_FAILED;
5375
5376 if (orig_state)
5377 s2io_open(sp->dev);
5378
5379 data[2] = 0;
5380 } else {
5381 /* Online Tests. */
5382 if (!orig_state) {
5383 DBG_PRINT(ERR_DBG,
5384 "%s: is not up, cannot run test\n",
5385 dev->name);
5386 data[0] = -1;
5387 data[1] = -1;
5388 data[2] = -1;
5389 data[3] = -1;
5390 data[4] = -1;
5391 }
5392
5393 if (s2io_link_test(sp, &data[2]))
5394 ethtest->flags |= ETH_TEST_FL_FAILED;
5395
5396 data[0] = 0;
5397 data[1] = 0;
5398 data[3] = 0;
5399 data[4] = 0;
5400 }
5401}
5402
5403static void s2io_get_ethtool_stats(struct net_device *dev,
5404 struct ethtool_stats *estats,
5405 u64 * tmp_stats)
5406{
5407 int i = 0;
1ee6dd77
RB		 5408 struct s2io_nic *sp = dev->priv;
5409 struct stat_block *stat_info = sp->mac_control.stats_info;
1da177e4 5410
7ba013ac 5411 s2io_updt_stats(sp);
541ae68f
K		 5412 tmp_stats[i++] =
5413 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
5414 le32_to_cpu(stat_info->tmac_frms);
5415 tmp_stats[i++] =
5416 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
5417 le32_to_cpu(stat_info->tmac_data_octets);
1da177e4 5418 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
541ae68f
K		 5419 tmp_stats[i++] =
5420 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
5421 le32_to_cpu(stat_info->tmac_mcst_frms);
5422 tmp_stats[i++] =
5423 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
5424 le32_to_cpu(stat_info->tmac_bcst_frms);
1da177e4 5425 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
bd1034f0
AR		 5426 tmp_stats[i++] =
5427 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
5428 le32_to_cpu(stat_info->tmac_ttl_octets);
5429 tmp_stats[i++] =
5430 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
5431 le32_to_cpu(stat_info->tmac_ucst_frms);
5432 tmp_stats[i++] =
5433 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
5434 le32_to_cpu(stat_info->tmac_nucst_frms);
541ae68f
K		 5435 tmp_stats[i++] =
5436 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
5437 le32_to_cpu(stat_info->tmac_any_err_frms);
bd1034f0 5438 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
1da177e4 5439 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
541ae68f
K		 5440 tmp_stats[i++] =
5441 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
5442 le32_to_cpu(stat_info->tmac_vld_ip);
5443 tmp_stats[i++] =
5444 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
5445 le32_to_cpu(stat_info->tmac_drop_ip);
5446 tmp_stats[i++] =
5447 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
5448 le32_to_cpu(stat_info->tmac_icmp);
5449 tmp_stats[i++] =
5450 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
5451 le32_to_cpu(stat_info->tmac_rst_tcp);
1da177e4 5452 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
541ae68f
K		 5453 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
5454 le32_to_cpu(stat_info->tmac_udp);
5455 tmp_stats[i++] =
5456 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
5457 le32_to_cpu(stat_info->rmac_vld_frms);
5458 tmp_stats[i++] =
5459 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
5460 le32_to_cpu(stat_info->rmac_data_octets);
1da177e4
LT		 5461 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
5462 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
541ae68f
K		 5463 tmp_stats[i++] =
5464 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
5465 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
5466 tmp_stats[i++] =
5467 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
5468 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
1da177e4 5469 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
bd1034f0 5470 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
1da177e4
LT		 5471 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
5472 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
bd1034f0
AR		 5473 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
5474 tmp_stats[i++] =
5475 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
5476 le32_to_cpu(stat_info->rmac_ttl_octets);
5477 tmp_stats[i++] =
5478 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
5479 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
5480 tmp_stats[i++] =
5481 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
5482 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
541ae68f
K		 5483 tmp_stats[i++] =
5484 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
5485 le32_to_cpu(stat_info->rmac_discarded_frms);
bd1034f0
AR		 5486 tmp_stats[i++] =
5487 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
5488 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
5489 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
5490 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
541ae68f
K		 5491 tmp_stats[i++] =
5492 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
5493 le32_to_cpu(stat_info->rmac_usized_frms);
5494 tmp_stats[i++] =
5495 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
5496 le32_to_cpu(stat_info->rmac_osized_frms);
5497 tmp_stats[i++] =
5498 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
5499 le32_to_cpu(stat_info->rmac_frag_frms);
5500 tmp_stats[i++] =
5501 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
5502 le32_to_cpu(stat_info->rmac_jabber_frms);
bd1034f0
AR		 5503 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
5504 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
5505 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
5506 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
5507 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
5508 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
5509 tmp_stats[i++] =
5510 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
541ae68f 5511 le32_to_cpu(stat_info->rmac_ip);
1da177e4
LT		 5512 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
5513 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
bd1034f0
AR		 5514 tmp_stats[i++] =
5515 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
541ae68f 5516 le32_to_cpu(stat_info->rmac_drop_ip);
bd1034f0
AR		 5517 tmp_stats[i++] =
5518 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
541ae68f 5519 le32_to_cpu(stat_info->rmac_icmp);
1da177e4 5520 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
bd1034f0
AR		 5521 tmp_stats[i++] =
5522 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
541ae68f
K		 5523 le32_to_cpu(stat_info->rmac_udp);
5524 tmp_stats[i++] =
5525 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
5526 le32_to_cpu(stat_info->rmac_err_drp_udp);
bd1034f0
AR		 5527 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
5528 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
5529 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
5530 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
5531 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
5532 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
5533 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
5534 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
5535 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
5536 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
5537 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
5538 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
5539 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
5540 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
5541 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
5542 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
5543 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
541ae68f
K		 5544 tmp_stats[i++] =
5545 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
5546 le32_to_cpu(stat_info->rmac_pause_cnt);
bd1034f0
AR		 5547 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
5548 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
541ae68f
K		 5549 tmp_stats[i++] =
5550 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
5551 le32_to_cpu(stat_info->rmac_accepted_ip);
1da177e4 5552 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
bd1034f0
AR		 5553 tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
5554 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
5555 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
5556 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
5557 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
5558 tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
5559 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
5560 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
5561 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
5562 tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
5563 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
5564 tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
5565 tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
5566 tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
5567 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
5568 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
5569 tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
5570 tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
5571 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
5572 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
5573 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
5574 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
5575 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
5576 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
5577 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
5578 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
5579 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
5580 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
5581 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
5582 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
5583 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
5584 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
5585 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
5586 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
7ba013ac
K		 5587 tmp_stats[i++] = 0;
5588 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
5589 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
bd1034f0
AR		 5590 tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
5591 tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
5592 tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
5593 tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
5594 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt;
5595 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
5596 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
5597 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
5598 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
5599 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
5600 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
5601 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
5602 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
5603 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
5604 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
5605 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
5606 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
7d3d0439
RA		 5607 tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
5608 tmp_stats[i++] = stat_info->sw_stat.sending_both;
5609 tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
5610 tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
fe931395 5611 if (stat_info->sw_stat.num_aggregations) {
bd1034f0
AR		 5612 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
5613 int count = 0;
6aa20a22 5614 /*
bd1034f0
AR		 5615 * Since 64-bit divide does not work on all platforms,
5616 * do repeated subtraction.
5617 */
5618 while (tmp >= stat_info->sw_stat.num_aggregations) {
5619 tmp -= stat_info->sw_stat.num_aggregations;
5620 count++;
5621 }
5622 tmp_stats[i++] = count;
fe931395 5623 }
bd1034f0
AR		 5624 else
5625 tmp_stats[i++] = 0;
1da177e4
LT		 5626}
5627
ac1f60db 5628static int s2io_ethtool_get_regs_len(struct net_device *dev)
1da177e4
LT		 5629{
5630 return (XENA_REG_SPACE);
5631}
5632
5633
ac1f60db 5634static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
1da177e4 5635{
1ee6dd77 5636 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5637
5638 return (sp->rx_csum);
5639}
ac1f60db
AB		 5640
5641static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
1da177e4 5642{
1ee6dd77 5643 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5644
5645 if (data)
5646 sp->rx_csum = 1;
5647 else
5648 sp->rx_csum = 0;
5649
5650 return 0;
5651}
ac1f60db
AB		 5652
5653static int s2io_get_eeprom_len(struct net_device *dev)
1da177e4
LT		 5654{
5655 return (XENA_EEPROM_SPACE);
5656}
5657
ac1f60db 5658static int s2io_ethtool_self_test_count(struct net_device *dev)
1da177e4
LT		 5659{
5660 return (S2IO_TEST_LEN);
5661}
ac1f60db
AB		 5662
5663static void s2io_ethtool_get_strings(struct net_device *dev,
5664 u32 stringset, u8 * data)
1da177e4
LT		 5665{
5666 switch (stringset) {
5667 case ETH_SS_TEST:
5668 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
5669 break;
5670 case ETH_SS_STATS:
5671 memcpy(data, &ethtool_stats_keys,
5672 sizeof(ethtool_stats_keys));
5673 }
5674}
1da177e4
LT		 5675static int s2io_ethtool_get_stats_count(struct net_device *dev)
5676{
5677 return (S2IO_STAT_LEN);
5678}
5679
ac1f60db 5680static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
1da177e4
LT		 5681{
5682 if (data)
5683 dev->features |= NETIF_F_IP_CSUM;
5684 else
5685 dev->features &= ~NETIF_F_IP_CSUM;
5686
5687 return 0;
5688}
5689
75c30b13
AR		 5690static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
5691{
5692 return (dev->features & NETIF_F_TSO) != 0;
5693}
5694static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
5695{
5696 if (data)
5697 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
5698 else
5699 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
5700
5701 return 0;
5702}
1da177e4 5703
7282d491 5704static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 5705 .get_settings = s2io_ethtool_gset,
5706 .set_settings = s2io_ethtool_sset,
5707 .get_drvinfo = s2io_ethtool_gdrvinfo,
5708 .get_regs_len = s2io_ethtool_get_regs_len,
5709 .get_regs = s2io_ethtool_gregs,
5710 .get_link = ethtool_op_get_link,
5711 .get_eeprom_len = s2io_get_eeprom_len,
5712 .get_eeprom = s2io_ethtool_geeprom,
5713 .set_eeprom = s2io_ethtool_seeprom,
5714 .get_pauseparam = s2io_ethtool_getpause_data,
5715 .set_pauseparam = s2io_ethtool_setpause_data,
5716 .get_rx_csum = s2io_ethtool_get_rx_csum,
5717 .set_rx_csum = s2io_ethtool_set_rx_csum,
5718 .get_tx_csum = ethtool_op_get_tx_csum,
5719 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
5720 .get_sg = ethtool_op_get_sg,
5721 .set_sg = ethtool_op_set_sg,
75c30b13
AR		 5722 .get_tso = s2io_ethtool_op_get_tso,
5723 .set_tso = s2io_ethtool_op_set_tso,
fed5eccd
AR		 5724 .get_ufo = ethtool_op_get_ufo,
5725 .set_ufo = ethtool_op_set_ufo,
1da177e4
LT		 5726 .self_test_count = s2io_ethtool_self_test_count,
5727 .self_test = s2io_ethtool_test,
5728 .get_strings = s2io_ethtool_get_strings,
5729 .phys_id = s2io_ethtool_idnic,
5730 .get_stats_count = s2io_ethtool_get_stats_count,
5731 .get_ethtool_stats = s2io_get_ethtool_stats
5732};
5733
5734/**
20346722 5735 * s2io_ioctl - Entry point for the Ioctl
1da177e4
LT		 5736 * @dev : Device pointer.
5737 * @ifr : An IOCTL specefic structure, that can contain a pointer to
5738 * a proprietary structure used to pass information to the driver.
5739 * @cmd : This is used to distinguish between the different commands that
5740 * can be passed to the IOCTL functions.
5741 * Description:
20346722
K		 5742 * Currently there are no special functionality supported in IOCTL, hence
5743 * function always return EOPNOTSUPPORTED
1da177e4
LT		 5744 */
5745
ac1f60db 5746static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1da177e4
LT		 5747{
5748 return -EOPNOTSUPP;
5749}
5750
5751/**
5752 * s2io_change_mtu - entry point to change MTU size for the device.
5753 * @dev : device pointer.
5754 * @new_mtu : the new MTU size for the device.
5755 * Description: A driver entry point to change MTU size for the device.
5756 * Before changing the MTU the device must be stopped.
5757 * Return value:
5758 * 0 on success and an appropriate (-)ve integer as defined in errno.h
5759 * file on failure.
5760 */
5761
ac1f60db 5762static int s2io_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 5763{
1ee6dd77 5764 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5765
5766 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
5767 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
5768 dev->name);
5769 return -EPERM;
5770 }
5771
1da177e4 5772 dev->mtu = new_mtu;
d8892c6e 5773 if (netif_running(dev)) {
e6a8fee2 5774 s2io_card_down(sp);
d8892c6e
K		 5775 netif_stop_queue(dev);
5776 if (s2io_card_up(sp)) {
5777 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
5778 __FUNCTION__);
5779 }
5780 if (netif_queue_stopped(dev))
5781 netif_wake_queue(dev);
5782 } else { /* Device is down */
1ee6dd77 5783 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d8892c6e
K		 5784 u64 val64 = new_mtu;
5785
5786 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
5787 }
1da177e4
LT		 5788
5789 return 0;
5790}
5791
5792/**
5793 * s2io_tasklet - Bottom half of the ISR.
5794 * @dev_adr : address of the device structure in dma_addr_t format.
5795 * Description:
5796 * This is the tasklet or the bottom half of the ISR. This is
20346722 5797 * an extension of the ISR which is scheduled by the scheduler to be run
1da177e4 5798 * when the load on the CPU is low. All low priority tasks of the ISR can
20346722 5799 * be pushed into the tasklet. For now the tasklet is used only to
1da177e4
LT		 5800 * replenish the Rx buffers in the Rx buffer descriptors.
5801 * Return value:
5802 * void.
5803 */
5804
5805static void s2io_tasklet(unsigned long dev_addr)
5806{
5807 struct net_device *dev = (struct net_device *) dev_addr;
1ee6dd77 5808 struct s2io_nic *sp = dev->priv;
1da177e4 5809 int i, ret;
1ee6dd77 5810 struct mac_info *mac_control;
1da177e4
LT		 5811 struct config_param *config;
5812
5813 mac_control = &sp->mac_control;
5814 config = &sp->config;
5815
5816 if (!TASKLET_IN_USE) {
5817 for (i = 0; i < config->rx_ring_num; i++) {
5818 ret = fill_rx_buffers(sp, i);
5819 if (ret == -ENOMEM) {
5820 DBG_PRINT(ERR_DBG, "%s: Out of ",
5821 dev->name);
5822 DBG_PRINT(ERR_DBG, "memory in tasklet\n");
5823 break;
5824 } else if (ret == -EFILL) {
5825 DBG_PRINT(ERR_DBG,
5826 "%s: Rx Ring %d is full\n",
5827 dev->name, i);
5828 break;
5829 }
5830 }
5831 clear_bit(0, (&sp->tasklet_status));
5832 }
5833}
5834
5835/**
5836 * s2io_set_link - Set the LInk status
5837 * @data: long pointer to device private structue
5838 * Description: Sets the link status for the adapter
5839 */
5840
c4028958 5841static void s2io_set_link(struct work_struct *work)
1da177e4 5842{
1ee6dd77 5843 struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
1da177e4 5844 struct net_device *dev = nic->dev;
1ee6dd77 5845 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 5846 register u64 val64;
5847 u16 subid;
5848
22747d6b
FR		 5849 rtnl_lock();
5850
5851 if (!netif_running(dev))
5852 goto out_unlock;
5853
1da177e4
LT		 5854 if (test_and_set_bit(0, &(nic->link_state))) {
5855 /* The card is being reset, no point doing anything */
22747d6b 5856 goto out_unlock;
1da177e4
LT		 5857 }
5858
5859 subid = nic->pdev->subsystem_device;
a371a07d
K		 5860 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
5861 /*
5862 * Allow a small delay for the NICs self initiated
5863 * cleanup to complete.
5864 */
5865 msleep(100);
5866 }
1da177e4
LT		 5867
5868 val64 = readq(&bar0->adapter_status);
19a60522
SS		 5869 if (LINK_IS_UP(val64)) {
5870 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
5871 if (verify_xena_quiescence(nic)) {
5872 val64 = readq(&bar0->adapter_control);
5873 val64 |= ADAPTER_CNTL_EN;
1da177e4 5874 writeq(val64, &bar0->adapter_control);
19a60522
SS		 5875 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
5876 nic->device_type, subid)) {
5877 val64 = readq(&bar0->gpio_control);
5878 val64 |= GPIO_CTRL_GPIO_0;
5879 writeq(val64, &bar0->gpio_control);
5880 val64 = readq(&bar0->gpio_control);
5881 } else {
5882 val64 |= ADAPTER_LED_ON;
5883 writeq(val64, &bar0->adapter_control);
a371a07d 5884 }
1da177e4 5885 nic->device_enabled_once = TRUE;
19a60522
SS		 5886 } else {
5887 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
5888 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
5889 netif_stop_queue(dev);
1da177e4 5890 }
19a60522
SS		 5891 }
5892 val64 = readq(&bar0->adapter_status);
5893 if (!LINK_IS_UP(val64)) {
5894 DBG_PRINT(ERR_DBG, "%s:", dev->name);
5895 DBG_PRINT(ERR_DBG, " Link down after enabling ");
5896 DBG_PRINT(ERR_DBG, "device \n");
5897 } else
1da177e4 5898 s2io_link(nic, LINK_UP);
19a60522
SS		 5899 } else {
5900 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
5901 subid)) {
5902 val64 = readq(&bar0->gpio_control);
5903 val64 &= ~GPIO_CTRL_GPIO_0;
5904 writeq(val64, &bar0->gpio_control);
5905 val64 = readq(&bar0->gpio_control);
1da177e4 5906 }
19a60522 5907 s2io_link(nic, LINK_DOWN);
1da177e4
LT		 5908 }
5909 clear_bit(0, &(nic->link_state));
22747d6b
FR		 5910
5911out_unlock:
5912 rtnl_lock();
1da177e4
LT		 5913}
5914
1ee6dd77
RB		 5915static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
5916 struct buffAdd *ba,
5917 struct sk_buff **skb, u64 *temp0, u64 *temp1,
5918 u64 *temp2, int size)
5d3213cc
AR		 5919{
5920 struct net_device *dev = sp->dev;
5921 struct sk_buff *frag_list;
5922
5923 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
5924 /* allocate skb */
5925 if (*skb) {
5926 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
5927 /*
5928 * As Rx frame are not going to be processed,
5929 * using same mapped address for the Rxd
5930 * buffer pointer
5931 */
1ee6dd77 5932 ((struct RxD1*)rxdp)->Buffer0_ptr = *temp0;
5d3213cc
AR		 5933 } else {
5934 *skb = dev_alloc_skb(size);
5935 if (!(*skb)) {
5936 DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
5937 DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
5938 return -ENOMEM ;
5939 }
5940 /* storing the mapped addr in a temp variable
5941 * such it will be used for next rxd whose
5942 * Host Control is NULL
5943 */
1ee6dd77 5944 ((struct RxD1*)rxdp)->Buffer0_ptr = *temp0 =
5d3213cc
AR		 5945 pci_map_single( sp->pdev, (*skb)->data,
5946 size - NET_IP_ALIGN,
5947 PCI_DMA_FROMDEVICE);
5948 rxdp->Host_Control = (unsigned long) (*skb);
5949 }
5950 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
5951 /* Two buffer Mode */
5952 if (*skb) {
1ee6dd77
RB		 5953 ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2;
5954 ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0;
5955 ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1;
5d3213cc
AR		 5956 } else {
5957 *skb = dev_alloc_skb(size);
2ceaac75
DR		 5958 if (!(*skb)) {
5959 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n",
19a60522 5960 dev->name);
2ceaac75
DR		 5961 return -ENOMEM;
5962 }
1ee6dd77 5963 ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2 =
5d3213cc
AR		 5964 pci_map_single(sp->pdev, (*skb)->data,
5965 dev->mtu + 4,
5966 PCI_DMA_FROMDEVICE);
1ee6dd77 5967 ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0 =
5d3213cc
AR		 5968 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
5969 PCI_DMA_FROMDEVICE);
5970 rxdp->Host_Control = (unsigned long) (*skb);
5971
5972 /* Buffer-1 will be dummy buffer not used */
1ee6dd77 5973 ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1 =
5d3213cc
AR		 5974 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
5975 PCI_DMA_FROMDEVICE);
5976 }
5977 } else if ((rxdp->Host_Control == 0)) {
5978 /* Three buffer mode */
5979 if (*skb) {
1ee6dd77
RB		 5980 ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0;
5981 ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1;
5982 ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2;
5d3213cc
AR		 5983 } else {
5984 *skb = dev_alloc_skb(size);
2ceaac75
DR		 5985 if (!(*skb)) {
5986 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n",
5987 dev->name);
5988 return -ENOMEM;
5989 }
1ee6dd77 5990 ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0 =
5d3213cc
AR		 5991 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
5992 PCI_DMA_FROMDEVICE);
5993 /* Buffer-1 receives L3/L4 headers */
1ee6dd77 5994 ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1 =
5d3213cc
AR		 5995 pci_map_single( sp->pdev, (*skb)->data,
5996 l3l4hdr_size + 4,
5997 PCI_DMA_FROMDEVICE);
5998 /*
5999 * skb_shinfo(skb)->frag_list will have L4
6000 * data payload
6001 */
6002 skb_shinfo(*skb)->frag_list = dev_alloc_skb(dev->mtu +
6003 ALIGN_SIZE);
6004 if (skb_shinfo(*skb)->frag_list == NULL) {
6005 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb \
6006 failed\n ", dev->name);
6007 return -ENOMEM ;
6008 }
6009 frag_list = skb_shinfo(*skb)->frag_list;
6010 frag_list->next = NULL;
6011 /*
6012 * Buffer-2 receives L4 data payload
6013 */
1ee6dd77 6014 ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2 =
5d3213cc
AR		 6015 pci_map_single( sp->pdev, frag_list->data,
6016 dev->mtu, PCI_DMA_FROMDEVICE);
6017 }
6018 }
6019 return 0;
6020}
1ee6dd77
RB		 6021static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6022 int size)
5d3213cc
AR		 6023{
6024 struct net_device *dev = sp->dev;
6025 if (sp->rxd_mode == RXD_MODE_1) {
6026 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6027 } else if (sp->rxd_mode == RXD_MODE_3B) {
6028 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6029 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6030 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
6031 } else {
6032 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6033 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
6034 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
6035 }
6036}
6037
1ee6dd77 6038static int rxd_owner_bit_reset(struct s2io_nic *sp)
5d3213cc
AR		 6039{
6040 int i, j, k, blk_cnt = 0, size;
1ee6dd77 6041 struct mac_info * mac_control = &sp->mac_control;
5d3213cc
AR		 6042 struct config_param *config = &sp->config;
6043 struct net_device *dev = sp->dev;
1ee6dd77 6044 struct RxD_t *rxdp = NULL;
5d3213cc 6045 struct sk_buff *skb = NULL;
1ee6dd77 6046 struct buffAdd *ba = NULL;
5d3213cc
AR		 6047 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6048
6049 /* Calculate the size based on ring mode */
6050 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6051 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6052 if (sp->rxd_mode == RXD_MODE_1)
6053 size += NET_IP_ALIGN;
6054 else if (sp->rxd_mode == RXD_MODE_3B)
6055 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6056 else
6057 size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
6058
6059 for (i = 0; i < config->rx_ring_num; i++) {
6060 blk_cnt = config->rx_cfg[i].num_rxd /
6061 (rxd_count[sp->rxd_mode] +1);
6062
6063 for (j = 0; j < blk_cnt; j++) {
6064 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6065 rxdp = mac_control->rings[i].
6066 rx_blocks[j].rxds[k].virt_addr;
6067 if(sp->rxd_mode >= RXD_MODE_3A)
6068 ba = &mac_control->rings[i].ba[j][k];
6069 set_rxd_buffer_pointer(sp, rxdp, ba,
6070 &skb,(u64 *)&temp0_64,
6071 (u64 *)&temp1_64,
6072 (u64 *)&temp2_64, size);
6073
6074 set_rxd_buffer_size(sp, rxdp, size);
6075 wmb();
6076 /* flip the Ownership bit to Hardware */
6077 rxdp->Control_1 |= RXD_OWN_XENA;
6078 }
6079 }
6080 }
6081 return 0;
6082
6083}
6084
1ee6dd77 6085static int s2io_add_isr(struct s2io_nic * sp)
1da177e4 6086{
e6a8fee2 6087 int ret = 0;
c92ca04b 6088 struct net_device *dev = sp->dev;
e6a8fee2 6089 int err = 0;
1da177e4 6090
e6a8fee2
AR		 6091 if (sp->intr_type == MSI)
6092 ret = s2io_enable_msi(sp);
6093 else if (sp->intr_type == MSI_X)
6094 ret = s2io_enable_msi_x(sp);
6095 if (ret) {
6096 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6097 sp->intr_type = INTA;
20346722 6098 }
1da177e4 6099
1ee6dd77 6100 /* Store the values of the MSIX table in the struct s2io_nic structure */
e6a8fee2 6101 store_xmsi_data(sp);
c92ca04b 6102
e6a8fee2
AR		 6103 /* After proper initialization of H/W, register ISR */
6104 if (sp->intr_type == MSI) {
6105 err = request_irq((int) sp->pdev->irq, s2io_msi_handle,
6106 IRQF_SHARED, sp->name, dev);
6107 if (err) {
6108 pci_disable_msi(sp->pdev);
6109 DBG_PRINT(ERR_DBG, "%s: MSI registration failed\n",
6110 dev->name);
6111 return -1;
6112 }
6113 }
6114 if (sp->intr_type == MSI_X) {
6115 int i;
c92ca04b 6116
e6a8fee2
AR		 6117 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
6118 if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
6119 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
6120 dev->name, i);
6121 err = request_irq(sp->entries[i].vector,
6122 s2io_msix_fifo_handle, 0, sp->desc[i],
6123 sp->s2io_entries[i].arg);
6124 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc[i],
6125 (unsigned long long)sp->msix_info[i].addr);
6126 } else {
6127 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
6128 dev->name, i);
6129 err = request_irq(sp->entries[i].vector,
6130 s2io_msix_ring_handle, 0, sp->desc[i],
6131 sp->s2io_entries[i].arg);
6132 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc[i],
6133 (unsigned long long)sp->msix_info[i].addr);
c92ca04b 6134 }
e6a8fee2
AR		 6135 if (err) {
6136 DBG_PRINT(ERR_DBG,"%s:MSI-X-%d registration "
6137 "failed\n", dev->name, i);
6138 DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
6139 return -1;
6140 }
6141 sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
6142 }
6143 }
6144 if (sp->intr_type == INTA) {
6145 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
6146 sp->name, dev);
6147 if (err) {
6148 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
6149 dev->name);
6150 return -1;
6151 }
6152 }
6153 return 0;
6154}
1ee6dd77 6155static void s2io_rem_isr(struct s2io_nic * sp)
e6a8fee2
AR		 6156{
6157 int cnt = 0;
6158 struct net_device *dev = sp->dev;
6159
6160 if (sp->intr_type == MSI_X) {
6161 int i;
6162 u16 msi_control;
6163
6164 for (i=1; (sp->s2io_entries[i].in_use ==
6165 MSIX_REGISTERED_SUCCESS); i++) {
6166 int vector = sp->entries[i].vector;
6167 void *arg = sp->s2io_entries[i].arg;
6168
6169 free_irq(vector, arg);
6170 }
6171 pci_read_config_word(sp->pdev, 0x42, &msi_control);
6172 msi_control &= 0xFFFE; /* Disable MSI */
6173 pci_write_config_word(sp->pdev, 0x42, msi_control);
6174
6175 pci_disable_msix(sp->pdev);
6176 } else {
6177 free_irq(sp->pdev->irq, dev);
6178 if (sp->intr_type == MSI) {
6179 u16 val;
6180
6181 pci_disable_msi(sp->pdev);
6182 pci_read_config_word(sp->pdev, 0x4c, &val);
6183 val ^= 0x1;
6184 pci_write_config_word(sp->pdev, 0x4c, val);
c92ca04b
AR		 6185 }
6186 }
6187 /* Waiting till all Interrupt handlers are complete */
6188 cnt = 0;
6189 do {
6190 msleep(10);
6191 if (!atomic_read(&sp->isr_cnt))
6192 break;
6193 cnt++;
6194 } while(cnt < 5);
e6a8fee2
AR		 6195}
6196
1ee6dd77 6197static void s2io_card_down(struct s2io_nic * sp)
e6a8fee2
AR		 6198{
6199 int cnt = 0;
1ee6dd77 6200 struct XENA_dev_config __iomem *bar0 = sp->bar0;
e6a8fee2
AR		 6201 unsigned long flags;
6202 register u64 val64 = 0;
6203
6204 del_timer_sync(&sp->alarm_timer);
6205 /* If s2io_set_link task is executing, wait till it completes. */
6206 while (test_and_set_bit(0, &(sp->link_state))) {
6207 msleep(50);
6208 }
6209 atomic_set(&sp->card_state, CARD_DOWN);
6210
6211 /* disable Tx and Rx traffic on the NIC */
6212 stop_nic(sp);
6213
6214 s2io_rem_isr(sp);
1da177e4
LT		 6215
6216 /* Kill tasklet. */
6217 tasklet_kill(&sp->task);
6218
6219 /* Check if the device is Quiescent and then Reset the NIC */
6220 do {
5d3213cc
AR		 6221 /* As per the HW requirement we need to replenish the
6222 * receive buffer to avoid the ring bump. Since there is
6223 * no intention of processing the Rx frame at this pointwe are
6224 * just settting the ownership bit of rxd in Each Rx
6225 * ring to HW and set the appropriate buffer size
6226 * based on the ring mode
6227 */
6228 rxd_owner_bit_reset(sp);
6229
1da177e4 6230 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6231 if (verify_xena_quiescence(sp)) {
6232 if(verify_pcc_quiescent(sp, sp->device_enabled_once))
1da177e4
LT		 6233 break;
6234 }
6235
6236 msleep(50);
6237 cnt++;
6238 if (cnt == 10) {
6239 DBG_PRINT(ERR_DBG,
6240 "s2io_close:Device not Quiescent ");
6241 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
6242 (unsigned long long) val64);
6243 break;
6244 }
6245 } while (1);
1da177e4
LT		 6246 s2io_reset(sp);
6247
7ba013ac
K		 6248 spin_lock_irqsave(&sp->tx_lock, flags);
6249 /* Free all Tx buffers */
1da177e4 6250 free_tx_buffers(sp);
7ba013ac
K		 6251 spin_unlock_irqrestore(&sp->tx_lock, flags);
6252
6253 /* Free all Rx buffers */
6254 spin_lock_irqsave(&sp->rx_lock, flags);
1da177e4 6255 free_rx_buffers(sp);
7ba013ac 6256 spin_unlock_irqrestore(&sp->rx_lock, flags);
1da177e4 6257
1da177e4
LT		 6258 clear_bit(0, &(sp->link_state));
6259}
6260
1ee6dd77 6261static int s2io_card_up(struct s2io_nic * sp)
1da177e4 6262{
cc6e7c44 6263 int i, ret = 0;
1ee6dd77 6264 struct mac_info *mac_control;
1da177e4
LT		 6265 struct config_param *config;
6266 struct net_device *dev = (struct net_device *) sp->dev;
e6a8fee2 6267 u16 interruptible;
1da177e4
LT		 6268
6269 /* Initialize the H/W I/O registers */
6270 if (init_nic(sp) != 0) {
6271 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
6272 dev->name);
e6a8fee2 6273 s2io_reset(sp);
1da177e4
LT		 6274 return -ENODEV;
6275 }
6276
20346722
K		 6277 /*
6278 * Initializing the Rx buffers. For now we are considering only 1
1da177e4
LT		 6279 * Rx ring and initializing buffers into 30 Rx blocks
6280 */
6281 mac_control = &sp->mac_control;
6282 config = &sp->config;
6283
6284 for (i = 0; i < config->rx_ring_num; i++) {
6285 if ((ret = fill_rx_buffers(sp, i))) {
6286 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
6287 dev->name);
6288 s2io_reset(sp);
6289 free_rx_buffers(sp);
6290 return -ENOMEM;
6291 }
6292 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
6293 atomic_read(&sp->rx_bufs_left[i]));
6294 }
19a60522
SS		 6295 /* Maintain the state prior to the open */
6296 if (sp->promisc_flg)
6297 sp->promisc_flg = 0;
6298 if (sp->m_cast_flg) {
6299 sp->m_cast_flg = 0;
6300 sp->all_multi_pos= 0;
6301 }
1da177e4
LT		 6302
6303 /* Setting its receive mode */
6304 s2io_set_multicast(dev);
6305
7d3d0439 6306 if (sp->lro) {
b41477f3 6307 /* Initialize max aggregatable pkts per session based on MTU */
7d3d0439
RA		 6308 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
6309 /* Check if we can use(if specified) user provided value */
6310 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
6311 sp->lro_max_aggr_per_sess = lro_max_pkts;
6312 }
6313
1da177e4
LT		 6314 /* Enable Rx Traffic and interrupts on the NIC */
6315 if (start_nic(sp)) {
6316 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
1da177e4 6317 s2io_reset(sp);
e6a8fee2
AR		 6318 free_rx_buffers(sp);
6319 return -ENODEV;
6320 }
6321
6322 /* Add interrupt service routine */
6323 if (s2io_add_isr(sp) != 0) {
6324 if (sp->intr_type == MSI_X)
6325 s2io_rem_isr(sp);
6326 s2io_reset(sp);
1da177e4
LT		 6327 free_rx_buffers(sp);
6328 return -ENODEV;
6329 }
6330
25fff88e
K		 6331 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
6332
e6a8fee2
AR		 6333 /* Enable tasklet for the device */
6334 tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
6335
6336 /* Enable select interrupts */
6337 if (sp->intr_type != INTA)
6338 en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS);
6339 else {
6340 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
6341 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
6342 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
6343 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
6344 }
6345
6346
1da177e4
LT		 6347 atomic_set(&sp->card_state, CARD_UP);
6348 return 0;
6349}
6350
20346722 6351/**
1da177e4
LT		 6352 * s2io_restart_nic - Resets the NIC.
6353 * @data : long pointer to the device private structure
6354 * Description:
6355 * This function is scheduled to be run by the s2io_tx_watchdog
20346722 6356 * function after 0.5 secs to reset the NIC. The idea is to reduce
1da177e4
LT		 6357 * the run time of the watch dog routine which is run holding a
6358 * spin lock.
6359 */
6360
c4028958 6361static void s2io_restart_nic(struct work_struct *work)
1da177e4 6362{
1ee6dd77 6363 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
c4028958 6364 struct net_device *dev = sp->dev;
1da177e4 6365
22747d6b
FR		 6366 rtnl_lock();
6367
6368 if (!netif_running(dev))
6369 goto out_unlock;
6370
e6a8fee2 6371 s2io_card_down(sp);
1da177e4
LT		 6372 if (s2io_card_up(sp)) {
6373 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6374 dev->name);
6375 }
6376 netif_wake_queue(dev);
6377 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
6378 dev->name);
22747d6b
FR		 6379out_unlock:
6380 rtnl_unlock();
1da177e4
LT		 6381}
6382
20346722
K		 6383/**
6384 * s2io_tx_watchdog - Watchdog for transmit side.
1da177e4
LT		 6385 * @dev : Pointer to net device structure
6386 * Description:
6387 * This function is triggered if the Tx Queue is stopped
6388 * for a pre-defined amount of time when the Interface is still up.
6389 * If the Interface is jammed in such a situation, the hardware is
6390 * reset (by s2io_close) and restarted again (by s2io_open) to
6391 * overcome any problem that might have been caused in the hardware.
6392 * Return value:
6393 * void
6394 */
6395
6396static void s2io_tx_watchdog(struct net_device *dev)
6397{
1ee6dd77 6398 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 6399
6400 if (netif_carrier_ok(dev)) {
6401 schedule_work(&sp->rst_timer_task);
bd1034f0 6402 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
1da177e4
LT		 6403 }
6404}
6405
6406/**
6407 * rx_osm_handler - To perform some OS related operations on SKB.
6408 * @sp: private member of the device structure,pointer to s2io_nic structure.
6409 * @skb : the socket buffer pointer.
6410 * @len : length of the packet
6411 * @cksum : FCS checksum of the frame.
6412 * @ring_no : the ring from which this RxD was extracted.
20346722 6413 * Description:
b41477f3 6414 * This function is called by the Rx interrupt serivce routine to perform
1da177e4
LT		 6415 * some OS related operations on the SKB before passing it to the upper
6416 * layers. It mainly checks if the checksum is OK, if so adds it to the
6417 * SKBs cksum variable, increments the Rx packet count and passes the SKB
6418 * to the upper layer. If the checksum is wrong, it increments the Rx
6419 * packet error count, frees the SKB and returns error.
6420 * Return value:
6421 * SUCCESS on success and -1 on failure.
6422 */
1ee6dd77 6423static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
1da177e4 6424{
1ee6dd77 6425 struct s2io_nic *sp = ring_data->nic;
1da177e4 6426 struct net_device *dev = (struct net_device *) sp->dev;
20346722
K		 6427 struct sk_buff *skb = (struct sk_buff *)
6428 ((unsigned long) rxdp->Host_Control);
6429 int ring_no = ring_data->ring_no;
1da177e4 6430 u16 l3_csum, l4_csum;
863c11a9 6431 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
1ee6dd77 6432 struct lro *lro;
da6971d8 6433
20346722 6434 skb->dev = dev;
c92ca04b 6435
863c11a9 6436 if (err) {
bd1034f0
AR		 6437 /* Check for parity error */
6438 if (err & 0x1) {
6439 sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
6440 }
6441
863c11a9
AR		 6442 /*
6443 * Drop the packet if bad transfer code. Exception being
6444 * 0x5, which could be due to unsupported IPv6 extension header.
6445 * In this case, we let stack handle the packet.
6446 * Note that in this case, since checksum will be incorrect,
6447 * stack will validate the same.
6448 */
6449 if (err && ((err >> 48) != 0x5)) {
6450 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
6451 dev->name, err);
6452 sp->stats.rx_crc_errors++;
6453 dev_kfree_skb(skb);
6454 atomic_dec(&sp->rx_bufs_left[ring_no]);
6455 rxdp->Host_Control = 0;
6456 return 0;
6457 }
20346722 6458 }
1da177e4 6459
20346722
K		 6460 /* Updating statistics */
6461 rxdp->Host_Control = 0;
6462 sp->rx_pkt_count++;
6463 sp->stats.rx_packets++;
da6971d8
AR		 6464 if (sp->rxd_mode == RXD_MODE_1) {
6465 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
20346722 6466
da6971d8
AR		 6467 sp->stats.rx_bytes += len;
6468 skb_put(skb, len);
6469
6470 } else if (sp->rxd_mode >= RXD_MODE_3A) {
6471 int get_block = ring_data->rx_curr_get_info.block_index;
6472 int get_off = ring_data->rx_curr_get_info.offset;
6473 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
6474 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
6475 unsigned char *buff = skb_push(skb, buf0_len);
6476
1ee6dd77 6477 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
da6971d8
AR		 6478 sp->stats.rx_bytes += buf0_len + buf2_len;
6479 memcpy(buff, ba->ba_0, buf0_len);
6480
6481 if (sp->rxd_mode == RXD_MODE_3A) {
6482 int buf1_len = RXD_GET_BUFFER1_SIZE_3(rxdp->Control_2);
6483
6484 skb_put(skb, buf1_len);
6485 skb->len += buf2_len;
6486 skb->data_len += buf2_len;
da6971d8
AR		 6487 skb_put(skb_shinfo(skb)->frag_list, buf2_len);
6488 sp->stats.rx_bytes += buf1_len;
6489
6490 } else
6491 skb_put(skb, buf2_len);
6492 }
20346722 6493
7d3d0439
RA		 6494 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!sp->lro) ||
6495 (sp->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
20346722
K		 6496 (sp->rx_csum)) {
6497 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
1da177e4
LT		 6498 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
6499 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
20346722 6500 /*
1da177e4
LT		 6501 * NIC verifies if the Checksum of the received
6502 * frame is Ok or not and accordingly returns
6503 * a flag in the RxD.
6504 */
6505 skb->ip_summed = CHECKSUM_UNNECESSARY;
7d3d0439
RA		 6506 if (sp->lro) {
6507 u32 tcp_len;
6508 u8 *tcp;
6509 int ret = 0;
6510
6511 ret = s2io_club_tcp_session(skb->data, &tcp,
6512 &tcp_len, &lro, rxdp, sp);
6513 switch (ret) {
6514 case 3: /* Begin anew */
6515 lro->parent = skb;
6516 goto aggregate;
6517 case 1: /* Aggregate */
6518 {
6519 lro_append_pkt(sp, lro,
6520 skb, tcp_len);
6521 goto aggregate;
6522 }
6523 case 4: /* Flush session */
6524 {
6525 lro_append_pkt(sp, lro,
6526 skb, tcp_len);
6527 queue_rx_frame(lro->parent);
6528 clear_lro_session(lro);
6529 sp->mac_control.stats_info->
6530 sw_stat.flush_max_pkts++;
6531 goto aggregate;
6532 }
6533 case 2: /* Flush both */
6534 lro->parent->data_len =
6535 lro->frags_len;
6536 sp->mac_control.stats_info->
6537 sw_stat.sending_both++;
6538 queue_rx_frame(lro->parent);
6539 clear_lro_session(lro);
6540 goto send_up;
6541 case 0: /* sessions exceeded */
c92ca04b
AR		 6542 case -1: /* non-TCP or not
6543 * L2 aggregatable
6544 */
7d3d0439
RA		 6545 case 5: /*
6546 * First pkt in session not
6547 * L3/L4 aggregatable
6548 */
6549 break;
6550 default:
6551 DBG_PRINT(ERR_DBG,
6552 "%s: Samadhana!!\n",
6553 __FUNCTION__);
6554 BUG();
6555 }
6556 }
1da177e4 6557 } else {
20346722
K		 6558 /*
6559 * Packet with erroneous checksum, let the
1da177e4
LT		 6560 * upper layers deal with it.
6561 */
6562 skb->ip_summed = CHECKSUM_NONE;
6563 }
6564 } else {
6565 skb->ip_summed = CHECKSUM_NONE;
6566 }
6567
7d3d0439
RA		 6568 if (!sp->lro) {
6569 skb->protocol = eth_type_trans(skb, dev);
7d3d0439
RA		 6570 if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
6571 /* Queueing the vlan frame to the upper layer */
db874e65
SS		 6572 if (napi)
6573 vlan_hwaccel_receive_skb(skb, sp->vlgrp,
6574 RXD_GET_VLAN_TAG(rxdp->Control_2));
6575 else
6576 vlan_hwaccel_rx(skb, sp->vlgrp,
6577 RXD_GET_VLAN_TAG(rxdp->Control_2));
7d3d0439 6578 } else {
db874e65
SS		 6579 if (napi)
6580 netif_receive_skb(skb);
6581 else
6582 netif_rx(skb);
7d3d0439 6583 }
7d3d0439
RA		 6584 } else {
6585send_up:
6586 queue_rx_frame(skb);
6aa20a22 6587 }
1da177e4 6588 dev->last_rx = jiffies;
7d3d0439 6589aggregate:
1da177e4 6590 atomic_dec(&sp->rx_bufs_left[ring_no]);
1da177e4
LT		 6591 return SUCCESS;
6592}
6593
6594/**
6595 * s2io_link - stops/starts the Tx queue.
6596 * @sp : private member of the device structure, which is a pointer to the
6597 * s2io_nic structure.
6598 * @link : inidicates whether link is UP/DOWN.
6599 * Description:
6600 * This function stops/starts the Tx queue depending on whether the link
20346722
K		 6601 * status of the NIC is is down or up. This is called by the Alarm
6602 * interrupt handler whenever a link change interrupt comes up.
1da177e4
LT		 6603 * Return value:
6604 * void.
6605 */
6606
1ee6dd77 6607static void s2io_link(struct s2io_nic * sp, int link)
1da177e4
LT		 6608{
6609 struct net_device *dev = (struct net_device *) sp->dev;
6610
6611 if (link != sp->last_link_state) {
6612 if (link == LINK_DOWN) {
6613 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
6614 netif_carrier_off(dev);
6615 } else {
6616 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
6617 netif_carrier_on(dev);
6618 }
6619 }
6620 sp->last_link_state = link;
6621}
6622
6623/**
20346722
K		 6624 * get_xena_rev_id - to identify revision ID of xena.
6625 * @pdev : PCI Dev structure
6626 * Description:
6627 * Function to identify the Revision ID of xena.
6628 * Return value:
6629 * returns the revision ID of the device.
6630 */
6631
26df54bf 6632static int get_xena_rev_id(struct pci_dev *pdev)
20346722
K		 6633{
6634 u8 id = 0;
6635 int ret;
6636 ret = pci_read_config_byte(pdev, PCI_REVISION_ID, (u8 *) & id);
6637 return id;
6638}
6639
6640/**
6641 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
6642 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 6643 * s2io_nic structure.
6644 * Description:
6645 * This function initializes a few of the PCI and PCI-X configuration registers
6646 * with recommended values.
6647 * Return value:
6648 * void
6649 */
6650
1ee6dd77 6651static void s2io_init_pci(struct s2io_nic * sp)
1da177e4 6652{
20346722 6653 u16 pci_cmd = 0, pcix_cmd = 0;
1da177e4
LT		 6654
6655 /* Enable Data Parity Error Recovery in PCI-X command register. */
6656 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 6657 &(pcix_cmd));
1da177e4 6658 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 6659 (pcix_cmd | 1));
1da177e4 6660 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 6661 &(pcix_cmd));
1da177e4
LT		 6662
6663 /* Set the PErr Response bit in PCI command register. */
6664 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
6665 pci_write_config_word(sp->pdev, PCI_COMMAND,
6666 (pci_cmd | PCI_COMMAND_PARITY));
6667 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
1da177e4
LT		 6668}
6669
9dc737a7
AR		 6670static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
6671{
6672 if ( tx_fifo_num > 8) {
6673 DBG_PRINT(ERR_DBG, "s2io: Requested number of Tx fifos not "
6674 "supported\n");
6675 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Tx fifos\n");
6676 tx_fifo_num = 8;
6677 }
6678 if ( rx_ring_num > 8) {
6679 DBG_PRINT(ERR_DBG, "s2io: Requested number of Rx rings not "
6680 "supported\n");
6681 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
6682 rx_ring_num = 8;
6683 }
db874e65
SS		 6684 if (*dev_intr_type != INTA)
6685 napi = 0;
6686
9dc737a7
AR		 6687#ifndef CONFIG_PCI_MSI
6688 if (*dev_intr_type != INTA) {
6689 DBG_PRINT(ERR_DBG, "s2io: This kernel does not support"
6690 "MSI/MSI-X. Defaulting to INTA\n");
6691 *dev_intr_type = INTA;
6692 }
6693#else
6694 if (*dev_intr_type > MSI_X) {
6695 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
6696 "Defaulting to INTA\n");
6697 *dev_intr_type = INTA;
6698 }
6699#endif
6700 if ((*dev_intr_type == MSI_X) &&
6701 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
6702 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
6aa20a22 6703 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
9dc737a7
AR		 6704 "Defaulting to INTA\n");
6705 *dev_intr_type = INTA;
6706 }
372cc597
SS		 6707 if ( (rx_ring_num > 1) && (*dev_intr_type != INTA) )
6708 napi = 0;
9dc737a7
AR		 6709 if (rx_ring_mode > 3) {
6710 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
6711 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 3-buffer mode\n");
6712 rx_ring_mode = 3;
6713 }
6714 return SUCCESS;
6715}
6716
1da177e4 6717/**
20346722 6718 * s2io_init_nic - Initialization of the adapter .
1da177e4
LT		 6719 * @pdev : structure containing the PCI related information of the device.
6720 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
6721 * Description:
6722 * The function initializes an adapter identified by the pci_dec structure.
20346722
K		 6723 * All OS related initialization including memory and device structure and
6724 * initlaization of the device private variable is done. Also the swapper
6725 * control register is initialized to enable read and write into the I/O
1da177e4
LT		 6726 * registers of the device.
6727 * Return value:
6728 * returns 0 on success and negative on failure.
6729 */
6730
6731static int __devinit
6732s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
6733{
1ee6dd77 6734 struct s2io_nic *sp;
1da177e4 6735 struct net_device *dev;
1da177e4
LT		 6736 int i, j, ret;
6737 int dma_flag = FALSE;
6738 u32 mac_up, mac_down;
6739 u64 val64 = 0, tmp64 = 0;
1ee6dd77 6740 struct XENA_dev_config __iomem *bar0 = NULL;
1da177e4 6741 u16 subid;
1ee6dd77 6742 struct mac_info *mac_control;
1da177e4 6743 struct config_param *config;
541ae68f 6744 int mode;
cc6e7c44 6745 u8 dev_intr_type = intr_type;
1da177e4 6746
9dc737a7
AR		 6747 if ((ret = s2io_verify_parm(pdev, &dev_intr_type)))
6748 return ret;
1da177e4
LT		 6749
6750 if ((ret = pci_enable_device(pdev))) {
6751 DBG_PRINT(ERR_DBG,
6752 "s2io_init_nic: pci_enable_device failed\n");
6753 return ret;
6754 }
6755
1e7f0bd8 6756 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 6757 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
6758 dma_flag = TRUE;
1da177e4 6759 if (pci_set_consistent_dma_mask
1e7f0bd8 6760 (pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 6761 DBG_PRINT(ERR_DBG,
6762 "Unable to obtain 64bit DMA for \
6763 consistent allocations\n");
6764 pci_disable_device(pdev);
6765 return -ENOMEM;
6766 }
1e7f0bd8 6767 } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1da177e4
LT		 6768 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
6769 } else {
6770 pci_disable_device(pdev);
6771 return -ENOMEM;
6772 }
cc6e7c44
RA		 6773 if (dev_intr_type != MSI_X) {
6774 if (pci_request_regions(pdev, s2io_driver_name)) {
b41477f3
AR		 6775 DBG_PRINT(ERR_DBG, "Request Regions failed\n");
6776 pci_disable_device(pdev);
cc6e7c44
RA		 6777 return -ENODEV;
6778 }
6779 }
6780 else {
6781 if (!(request_mem_region(pci_resource_start(pdev, 0),
6782 pci_resource_len(pdev, 0), s2io_driver_name))) {
6783 DBG_PRINT(ERR_DBG, "bar0 Request Regions failed\n");
6784 pci_disable_device(pdev);
6785 return -ENODEV;
6786 }
6787 if (!(request_mem_region(pci_resource_start(pdev, 2),
6788 pci_resource_len(pdev, 2), s2io_driver_name))) {
6789 DBG_PRINT(ERR_DBG, "bar1 Request Regions failed\n");
6790 release_mem_region(pci_resource_start(pdev, 0),
6791 pci_resource_len(pdev, 0));
6792 pci_disable_device(pdev);
6793 return -ENODEV;
6794 }
1da177e4
LT		 6795 }
6796
1ee6dd77 6797 dev = alloc_etherdev(sizeof(struct s2io_nic));
1da177e4
LT		 6798 if (dev == NULL) {
6799 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
6800 pci_disable_device(pdev);
6801 pci_release_regions(pdev);
6802 return -ENODEV;
6803 }
6804
6805 pci_set_master(pdev);
6806 pci_set_drvdata(pdev, dev);
6807 SET_MODULE_OWNER(dev);
6808 SET_NETDEV_DEV(dev, &pdev->dev);
6809
6810 /* Private member variable initialized to s2io NIC structure */
6811 sp = dev->priv;
1ee6dd77 6812 memset(sp, 0, sizeof(struct s2io_nic));
1da177e4
LT		 6813 sp->dev = dev;
6814 sp->pdev = pdev;
1da177e4 6815 sp->high_dma_flag = dma_flag;
1da177e4 6816 sp->device_enabled_once = FALSE;
da6971d8
AR		 6817 if (rx_ring_mode == 1)
6818 sp->rxd_mode = RXD_MODE_1;
6819 if (rx_ring_mode == 2)
6820 sp->rxd_mode = RXD_MODE_3B;
6821 if (rx_ring_mode == 3)
6822 sp->rxd_mode = RXD_MODE_3A;
6823
cc6e7c44 6824 sp->intr_type = dev_intr_type;
1da177e4 6825
541ae68f
K		 6826 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
6827 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
6828 sp->device_type = XFRAME_II_DEVICE;
6829 else
6830 sp->device_type = XFRAME_I_DEVICE;
6831
7d3d0439 6832 sp->lro = lro;
6aa20a22 6833
1da177e4
LT		 6834 /* Initialize some PCI/PCI-X fields of the NIC. */
6835 s2io_init_pci(sp);
6836
20346722 6837 /*
1da177e4 6838 * Setting the device configuration parameters.
20346722
K		 6839 * Most of these parameters can be specified by the user during
6840 * module insertion as they are module loadable parameters. If
6841 * these parameters are not not specified during load time, they
1da177e4
LT		 6842 * are initialized with default values.
6843 */
6844 mac_control = &sp->mac_control;
6845 config = &sp->config;
6846
6847 /* Tx side parameters. */
1da177e4
LT		 6848 config->tx_fifo_num = tx_fifo_num;
6849 for (i = 0; i < MAX_TX_FIFOS; i++) {
6850 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
6851 config->tx_cfg[i].fifo_priority = i;
6852 }
6853
20346722
K		 6854 /* mapping the QoS priority to the configured fifos */
6855 for (i = 0; i < MAX_TX_FIFOS; i++)
6856 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
6857
1da177e4
LT		 6858 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
6859 for (i = 0; i < config->tx_fifo_num; i++) {
6860 config->tx_cfg[i].f_no_snoop =
6861 (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
6862 if (config->tx_cfg[i].fifo_len < 65) {
6863 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
6864 break;
6865 }
6866 }
fed5eccd
AR		 6867 /* + 2 because one Txd for skb->data and one Txd for UFO */
6868 config->max_txds = MAX_SKB_FRAGS + 2;
1da177e4
LT		 6869
6870 /* Rx side parameters. */
1da177e4
LT		 6871 config->rx_ring_num = rx_ring_num;
6872 for (i = 0; i < MAX_RX_RINGS; i++) {
6873 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
da6971d8 6874 (rxd_count[sp->rxd_mode] + 1);
1da177e4
LT		 6875 config->rx_cfg[i].ring_priority = i;
6876 }
6877
6878 for (i = 0; i < rx_ring_num; i++) {
6879 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
6880 config->rx_cfg[i].f_no_snoop =
6881 (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
6882 }
6883
6884 /* Setting Mac Control parameters */
6885 mac_control->rmac_pause_time = rmac_pause_time;
6886 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
6887 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
6888
6889
6890 /* Initialize Ring buffer parameters. */
6891 for (i = 0; i < config->rx_ring_num; i++)
6892 atomic_set(&sp->rx_bufs_left[i], 0);
6893
7ba013ac
K		 6894 /* Initialize the number of ISRs currently running */
6895 atomic_set(&sp->isr_cnt, 0);
6896
1da177e4
LT		 6897 /* initialize the shared memory used by the NIC and the host */
6898 if (init_shared_mem(sp)) {
6899 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
b41477f3 6900 dev->name);
1da177e4
LT		 6901 ret = -ENOMEM;
6902 goto mem_alloc_failed;
6903 }
6904
6905 sp->bar0 = ioremap(pci_resource_start(pdev, 0),
6906 pci_resource_len(pdev, 0));
6907 if (!sp->bar0) {
19a60522 6908 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
1da177e4
LT		 6909 dev->name);
6910 ret = -ENOMEM;
6911 goto bar0_remap_failed;
6912 }
6913
6914 sp->bar1 = ioremap(pci_resource_start(pdev, 2),
6915 pci_resource_len(pdev, 2));
6916 if (!sp->bar1) {
19a60522 6917 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
1da177e4
LT		 6918 dev->name);
6919 ret = -ENOMEM;
6920 goto bar1_remap_failed;
6921 }
6922
6923 dev->irq = pdev->irq;
6924 dev->base_addr = (unsigned long) sp->bar0;
6925
6926 /* Initializing the BAR1 address as the start of the FIFO pointer. */
6927 for (j = 0; j < MAX_TX_FIFOS; j++) {
1ee6dd77 6928 mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
1da177e4
LT		 6929 (sp->bar1 + (j * 0x00020000));
6930 }
6931
6932 /* Driver entry points */
6933 dev->open = &s2io_open;
6934 dev->stop = &s2io_close;
6935 dev->hard_start_xmit = &s2io_xmit;
6936 dev->get_stats = &s2io_get_stats;
6937 dev->set_multicast_list = &s2io_set_multicast;
6938 dev->do_ioctl = &s2io_ioctl;
6939 dev->change_mtu = &s2io_change_mtu;
6940 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
be3a6b02
K		 6941 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6942 dev->vlan_rx_register = s2io_vlan_rx_register;
6943 dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;
20346722 6944
1da177e4
LT		 6945 /*
6946 * will use eth_mac_addr() for dev->set_mac_address
6947 * mac address will be set every time dev->open() is called
6948 */
1da177e4 6949 dev->poll = s2io_poll;
20346722 6950 dev->weight = 32;
1da177e4 6951
612eff0e
BH		 6952#ifdef CONFIG_NET_POLL_CONTROLLER
6953 dev->poll_controller = s2io_netpoll;
6954#endif
6955
1da177e4
LT		 6956 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
6957 if (sp->high_dma_flag == TRUE)
6958 dev->features |= NETIF_F_HIGHDMA;
1da177e4 6959 dev->features |= NETIF_F_TSO;
f83ef8c0 6960 dev->features |= NETIF_F_TSO6;
db874e65 6961 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
fed5eccd
AR		 6962 dev->features |= NETIF_F_UFO;
6963 dev->features |= NETIF_F_HW_CSUM;
6964 }
1da177e4
LT		 6965
6966 dev->tx_timeout = &s2io_tx_watchdog;
6967 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
c4028958
DH		 6968 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
6969 INIT_WORK(&sp->set_link_task, s2io_set_link);
1da177e4 6970
e960fc5c 6971 pci_save_state(sp->pdev);
1da177e4
LT		 6972
6973 /* Setting swapper control on the NIC, for proper reset operation */
6974 if (s2io_set_swapper(sp)) {
6975 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
6976 dev->name);
6977 ret = -EAGAIN;
6978 goto set_swap_failed;
6979 }
6980
541ae68f
K		 6981 /* Verify if the Herc works on the slot its placed into */
6982 if (sp->device_type & XFRAME_II_DEVICE) {
6983 mode = s2io_verify_pci_mode(sp);
6984 if (mode < 0) {
6985 DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
6986 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
6987 ret = -EBADSLT;
6988 goto set_swap_failed;
6989 }
6990 }
6991
6992 /* Not needed for Herc */
6993 if (sp->device_type & XFRAME_I_DEVICE) {
6994 /*
6995 * Fix for all "FFs" MAC address problems observed on
6996 * Alpha platforms
6997 */
6998 fix_mac_address(sp);
6999 s2io_reset(sp);
7000 }
1da177e4
LT		 7001
7002 /*
1da177e4
LT		 7003 * MAC address initialization.
7004 * For now only one mac address will be read and used.
7005 */
7006 bar0 = sp->bar0;
7007 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
7008 RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
7009 writeq(val64, &bar0->rmac_addr_cmd_mem);
c92ca04b
AR		 7010 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
7011 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
1da177e4
LT		 7012 tmp64 = readq(&bar0->rmac_addr_data0_mem);
7013 mac_down = (u32) tmp64;
7014 mac_up = (u32) (tmp64 >> 32);
7015
7016 memset(sp->def_mac_addr[0].mac_addr, 0, sizeof(ETH_ALEN));
7017
7018 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
7019 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
7020 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
7021 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
7022 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
7023 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
7024
1da177e4
LT		 7025 /* Set the factory defined MAC address initially */
7026 dev->addr_len = ETH_ALEN;
7027 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
7028
b41477f3
AR		 7029 /* reset Nic and bring it to known state */
7030 s2io_reset(sp);
7031
1da177e4 7032 /*
20346722 7033 * Initialize the tasklet status and link state flags
541ae68f 7034 * and the card state parameter
1da177e4
LT		 7035 */
7036 atomic_set(&(sp->card_state), 0);
7037 sp->tasklet_status = 0;
7038 sp->link_state = 0;
7039
1da177e4
LT		 7040 /* Initialize spinlocks */
7041 spin_lock_init(&sp->tx_lock);
db874e65
SS		 7042
7043 if (!napi)
7044 spin_lock_init(&sp->put_lock);
7ba013ac 7045 spin_lock_init(&sp->rx_lock);
1da177e4 7046
20346722
K		 7047 /*
7048 * SXE-002: Configure link and activity LED to init state
7049 * on driver load.
1da177e4
LT		 7050 */
7051 subid = sp->pdev->subsystem_device;
7052 if ((subid & 0xFF) >= 0x07) {
7053 val64 = readq(&bar0->gpio_control);
7054 val64 |= 0x0000800000000000ULL;
7055 writeq(val64, &bar0->gpio_control);
7056 val64 = 0x0411040400000000ULL;
7057 writeq(val64, (void __iomem *) bar0 + 0x2700);
7058 val64 = readq(&bar0->gpio_control);
7059 }
7060
7061 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
7062
7063 if (register_netdev(dev)) {
7064 DBG_PRINT(ERR_DBG, "Device registration failed\n");
7065 ret = -ENODEV;
7066 goto register_failed;
7067 }
9dc737a7 7068 s2io_vpd_read(sp);
9dc737a7 7069 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2005 Neterion Inc.\n");
b41477f3
AR		 7070 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
7071 sp->product_name, get_xena_rev_id(sp->pdev));
7072 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
7073 s2io_driver_version);
9dc737a7 7074 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: "
19a60522 7075 "%02x:%02x:%02x:%02x:%02x:%02x", dev->name,
541ae68f
K		 7076 sp->def_mac_addr[0].mac_addr[0],
7077 sp->def_mac_addr[0].mac_addr[1],
7078 sp->def_mac_addr[0].mac_addr[2],
7079 sp->def_mac_addr[0].mac_addr[3],
7080 sp->def_mac_addr[0].mac_addr[4],
7081 sp->def_mac_addr[0].mac_addr[5]);
19a60522 7082 DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
9dc737a7 7083 if (sp->device_type & XFRAME_II_DEVICE) {
0b1f7ebe 7084 mode = s2io_print_pci_mode(sp);
541ae68f 7085 if (mode < 0) {
9dc737a7 7086 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
541ae68f 7087 ret = -EBADSLT;
9dc737a7 7088 unregister_netdev(dev);
541ae68f
K		 7089 goto set_swap_failed;
7090 }
541ae68f 7091 }
9dc737a7
AR		 7092 switch(sp->rxd_mode) {
7093 case RXD_MODE_1:
7094 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
7095 dev->name);
7096 break;
7097 case RXD_MODE_3B:
7098 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
7099 dev->name);
7100 break;
7101 case RXD_MODE_3A:
7102 DBG_PRINT(ERR_DBG, "%s: 3-Buffer receive mode enabled\n",
7103 dev->name);
7104 break;
7105 }
db874e65
SS		 7106
7107 if (napi)
7108 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
9dc737a7
AR		 7109 switch(sp->intr_type) {
7110 case INTA:
7111 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
7112 break;
7113 case MSI:
7114 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI\n", dev->name);
7115 break;
7116 case MSI_X:
7117 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
7118 break;
7119 }
7d3d0439
RA		 7120 if (sp->lro)
7121 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
9dc737a7 7122 dev->name);
db874e65
SS		 7123 if (ufo)
7124 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
7125 " enabled\n", dev->name);
7ba013ac 7126 /* Initialize device name */
9dc737a7 7127 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7ba013ac 7128
b6e3f982
K		 7129 /* Initialize bimodal Interrupts */
7130 sp->config.bimodal = bimodal;
7131 if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
7132 sp->config.bimodal = 0;
7133 DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
7134 dev->name);
7135 }
7136
20346722
K		 7137 /*
7138 * Make Link state as off at this point, when the Link change
7139 * interrupt comes the state will be automatically changed to
1da177e4
LT		 7140 * the right state.
7141 */
7142 netif_carrier_off(dev);
1da177e4
LT		 7143
7144 return 0;
7145
7146 register_failed:
7147 set_swap_failed:
7148 iounmap(sp->bar1);
7149 bar1_remap_failed:
7150 iounmap(sp->bar0);
7151 bar0_remap_failed:
7152 mem_alloc_failed:
7153 free_shared_mem(sp);
7154 pci_disable_device(pdev);
cc6e7c44
RA		 7155 if (dev_intr_type != MSI_X)
7156 pci_release_regions(pdev);
7157 else {
7158 release_mem_region(pci_resource_start(pdev, 0),
7159 pci_resource_len(pdev, 0));
7160 release_mem_region(pci_resource_start(pdev, 2),
7161 pci_resource_len(pdev, 2));
7162 }
1da177e4
LT		 7163 pci_set_drvdata(pdev, NULL);
7164 free_netdev(dev);
7165
7166 return ret;
7167}
7168
7169/**
20346722 7170 * s2io_rem_nic - Free the PCI device
1da177e4 7171 * @pdev: structure containing the PCI related information of the device.
20346722 7172 * Description: This function is called by the Pci subsystem to release a
1da177e4 7173 * PCI device and free up all resource held up by the device. This could
20346722 7174 * be in response to a Hot plug event or when the driver is to be removed
1da177e4
LT		 7175 * from memory.
7176 */
7177
7178static void __devexit s2io_rem_nic(struct pci_dev *pdev)
7179{
7180 struct net_device *dev =
7181 (struct net_device *) pci_get_drvdata(pdev);
1ee6dd77 7182 struct s2io_nic *sp;
1da177e4
LT		 7183
7184 if (dev == NULL) {
7185 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
7186 return;
7187 }
7188
22747d6b
FR		 7189 flush_scheduled_work();
7190
1da177e4
LT		 7191 sp = dev->priv;
7192 unregister_netdev(dev);
7193
7194 free_shared_mem(sp);
7195 iounmap(sp->bar0);
7196 iounmap(sp->bar1);
cc6e7c44
RA		 7197 if (sp->intr_type != MSI_X)
7198 pci_release_regions(pdev);
7199 else {
7200 release_mem_region(pci_resource_start(pdev, 0),
7201 pci_resource_len(pdev, 0));
7202 release_mem_region(pci_resource_start(pdev, 2),
7203 pci_resource_len(pdev, 2));
7204 }
1da177e4 7205 pci_set_drvdata(pdev, NULL);
1da177e4 7206 free_netdev(dev);
19a60522 7207 pci_disable_device(pdev);
1da177e4
LT		 7208}
7209
7210/**
7211 * s2io_starter - Entry point for the driver
7212 * Description: This function is the entry point for the driver. It verifies
7213 * the module loadable parameters and initializes PCI configuration space.
7214 */
7215
7216int __init s2io_starter(void)
7217{
29917620 7218 return pci_register_driver(&s2io_driver);
1da177e4
LT		 7219}
7220
7221/**
20346722 7222 * s2io_closer - Cleanup routine for the driver
1da177e4
LT		 7223 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
7224 */
7225
372cc597 7226static __exit void s2io_closer(void)
1da177e4
LT		 7227{
7228 pci_unregister_driver(&s2io_driver);
7229 DBG_PRINT(INIT_DBG, "cleanup done\n");
7230}
7231
7232module_init(s2io_starter);
7233module_exit(s2io_closer);
7d3d0439 7234
6aa20a22 7235static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
1ee6dd77 7236 struct tcphdr **tcp, struct RxD_t *rxdp)
7d3d0439
RA		 7237{
7238 int ip_off;
7239 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
7240
7241 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
7242 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
7243 __FUNCTION__);
7244 return -1;
7245 }
7246
7247 /* TODO:
7248 * By default the VLAN field in the MAC is stripped by the card, if this
7249 * feature is turned off in rx_pa_cfg register, then the ip_off field
7250 * has to be shifted by a further 2 bytes
7251 */
7252 switch (l2_type) {
7253 case 0: /* DIX type */
7254 case 4: /* DIX type with VLAN */
7255 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
7256 break;
7257 /* LLC, SNAP etc are considered non-mergeable */
7258 default:
7259 return -1;
7260 }
7261
7262 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
7263 ip_len = (u8)((*ip)->ihl);
7264 ip_len <<= 2;
7265 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
7266
7267 return 0;
7268}
7269
1ee6dd77 7270static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 7271 struct tcphdr *tcp)
7272{
7273 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7274 if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
7275 (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
7276 return -1;
7277 return 0;
7278}
7279
7280static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
7281{
7282 return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
7283}
7284
1ee6dd77 7285static void initiate_new_session(struct lro *lro, u8 *l2h,
7d3d0439
RA		 7286 struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len)
7287{
7288 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7289 lro->l2h = l2h;
7290 lro->iph = ip;
7291 lro->tcph = tcp;
7292 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
7293 lro->tcp_ack = ntohl(tcp->ack_seq);
7294 lro->sg_num = 1;
7295 lro->total_len = ntohs(ip->tot_len);
7296 lro->frags_len = 0;
6aa20a22 7297 /*
7d3d0439
RA		 7298 * check if we saw TCP timestamp. Other consistency checks have
7299 * already been done.
7300 */
7301 if (tcp->doff == 8) {
7302 u32 *ptr;
7303 ptr = (u32 *)(tcp+1);
7304 lro->saw_ts = 1;
7305 lro->cur_tsval = *(ptr+1);
7306 lro->cur_tsecr = *(ptr+2);
7307 }
7308 lro->in_use = 1;
7309}
7310
1ee6dd77 7311static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7d3d0439
RA		 7312{
7313 struct iphdr *ip = lro->iph;
7314 struct tcphdr *tcp = lro->tcph;
bd4f3ae1 7315 __sum16 nchk;
1ee6dd77 7316 struct stat_block *statinfo = sp->mac_control.stats_info;
7d3d0439
RA		 7317 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7318
7319 /* Update L3 header */
7320 ip->tot_len = htons(lro->total_len);
7321 ip->check = 0;
7322 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
7323 ip->check = nchk;
7324
7325 /* Update L4 header */
7326 tcp->ack_seq = lro->tcp_ack;
7327 tcp->window = lro->window;
7328
7329 /* Update tsecr field if this session has timestamps enabled */
7330 if (lro->saw_ts) {
7331 u32 *ptr = (u32 *)(tcp + 1);
7332 *(ptr+2) = lro->cur_tsecr;
7333 }
7334
7335 /* Update counters required for calculation of
7336 * average no. of packets aggregated.
7337 */
7338 statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
7339 statinfo->sw_stat.num_aggregations++;
7340}
7341
1ee6dd77 7342static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 7343 struct tcphdr *tcp, u32 l4_pyld)
7344{
7345 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7346 lro->total_len += l4_pyld;
7347 lro->frags_len += l4_pyld;
7348 lro->tcp_next_seq += l4_pyld;
7349 lro->sg_num++;
7350
7351 /* Update ack seq no. and window ad(from this pkt) in LRO object */
7352 lro->tcp_ack = tcp->ack_seq;
7353 lro->window = tcp->window;
6aa20a22 7354
7d3d0439
RA		 7355 if (lro->saw_ts) {
7356 u32 *ptr;
7357 /* Update tsecr and tsval from this packet */
7358 ptr = (u32 *) (tcp + 1);
6aa20a22 7359 lro->cur_tsval = *(ptr + 1);
7d3d0439
RA		 7360 lro->cur_tsecr = *(ptr + 2);
7361 }
7362}
7363
1ee6dd77 7364static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7d3d0439
RA		 7365 struct tcphdr *tcp, u32 tcp_pyld_len)
7366{
7d3d0439
RA		 7367 u8 *ptr;
7368
79dc1901
AM		 7369 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7370
7d3d0439
RA		 7371 if (!tcp_pyld_len) {
7372 /* Runt frame or a pure ack */
7373 return -1;
7374 }
7375
7376 if (ip->ihl != 5) /* IP has options */
7377 return -1;
7378
75c30b13
AR		 7379 /* If we see CE codepoint in IP header, packet is not mergeable */
7380 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
7381 return -1;
7382
7383 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7d3d0439 7384 if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
75c30b13 7385 tcp->ece || tcp->cwr || !tcp->ack) {
7d3d0439
RA		 7386 /*
7387 * Currently recognize only the ack control word and
7388 * any other control field being set would result in
7389 * flushing the LRO session
7390 */
7391 return -1;
7392 }
7393
6aa20a22 7394 /*
7d3d0439
RA		 7395 * Allow only one TCP timestamp option. Don't aggregate if
7396 * any other options are detected.
7397 */
7398 if (tcp->doff != 5 && tcp->doff != 8)
7399 return -1;
7400
7401 if (tcp->doff == 8) {
6aa20a22 7402 ptr = (u8 *)(tcp + 1);
7d3d0439
RA		 7403 while (*ptr == TCPOPT_NOP)
7404 ptr++;
7405 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
7406 return -1;
7407
7408 /* Ensure timestamp value increases monotonically */
7409 if (l_lro)
7410 if (l_lro->cur_tsval > *((u32 *)(ptr+2)))
7411 return -1;
7412
7413 /* timestamp echo reply should be non-zero */
6aa20a22 7414 if (*((u32 *)(ptr+6)) == 0)
7d3d0439
RA		 7415 return -1;
7416 }
7417
7418 return 0;
7419}
7420
7421static int
1ee6dd77
RB		 7422s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
7423 struct RxD_t *rxdp, struct s2io_nic *sp)
7d3d0439
RA		 7424{
7425 struct iphdr *ip;
7426 struct tcphdr *tcph;
7427 int ret = 0, i;
7428
7429 if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
7430 rxdp))) {
7431 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
7432 ip->saddr, ip->daddr);
7433 } else {
7434 return ret;
7435 }
7436
7437 tcph = (struct tcphdr *)*tcp;
7438 *tcp_len = get_l4_pyld_length(ip, tcph);
7439 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 7440 struct lro *l_lro = &sp->lro0_n[i];
7d3d0439
RA		 7441 if (l_lro->in_use) {
7442 if (check_for_socket_match(l_lro, ip, tcph))
7443 continue;
7444 /* Sock pair matched */
7445 *lro = l_lro;
7446
7447 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
7448 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
7449 "0x%x, actual 0x%x\n", __FUNCTION__,
7450 (*lro)->tcp_next_seq,
7451 ntohl(tcph->seq));
7452
7453 sp->mac_control.stats_info->
7454 sw_stat.outof_sequence_pkts++;
7455 ret = 2;
7456 break;
7457 }
7458
7459 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
7460 ret = 1; /* Aggregate */
7461 else
7462 ret = 2; /* Flush both */
7463 break;
7464 }
7465 }
7466
7467 if (ret == 0) {
7468 /* Before searching for available LRO objects,
7469 * check if the pkt is L3/L4 aggregatable. If not
7470 * don't create new LRO session. Just send this
7471 * packet up.
7472 */
7473 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
7474 return 5;
7475 }
7476
7477 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 7478 struct lro *l_lro = &sp->lro0_n[i];
7d3d0439
RA		 7479 if (!(l_lro->in_use)) {
7480 *lro = l_lro;
7481 ret = 3; /* Begin anew */
7482 break;
7483 }
7484 }
7485 }
7486
7487 if (ret == 0) { /* sessions exceeded */
7488 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
7489 __FUNCTION__);
7490 *lro = NULL;
7491 return ret;
7492 }
7493
7494 switch (ret) {
7495 case 3:
7496 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len);
7497 break;
7498 case 2:
7499 update_L3L4_header(sp, *lro);
7500 break;
7501 case 1:
7502 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
7503 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
7504 update_L3L4_header(sp, *lro);
7505 ret = 4; /* Flush the LRO */
7506 }
7507 break;
7508 default:
7509 DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
7510 __FUNCTION__);
7511 break;
7512 }
7513
7514 return ret;
7515}
7516
1ee6dd77 7517static void clear_lro_session(struct lro *lro)
7d3d0439 7518{
1ee6dd77 7519 static u16 lro_struct_size = sizeof(struct lro);
7d3d0439
RA		 7520
7521 memset(lro, 0, lro_struct_size);
7522}
7523
7524static void queue_rx_frame(struct sk_buff *skb)
7525{
7526 struct net_device *dev = skb->dev;
7527
7528 skb->protocol = eth_type_trans(skb, dev);
db874e65
SS		 7529 if (napi)
7530 netif_receive_skb(skb);
7531 else
7532 netif_rx(skb);
7d3d0439
RA		 7533}
7534
1ee6dd77
RB		 7535static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
7536 struct sk_buff *skb,
7d3d0439
RA		 7537 u32 tcp_len)
7538{
75c30b13 7539 struct sk_buff *first = lro->parent;
7d3d0439
RA		 7540
7541 first->len += tcp_len;
7542 first->data_len = lro->frags_len;
7543 skb_pull(skb, (skb->len - tcp_len));
75c30b13
AR		 7544 if (skb_shinfo(first)->frag_list)
7545 lro->last_frag->next = skb;
7d3d0439
RA		 7546 else
7547 skb_shinfo(first)->frag_list = skb;
372cc597 7548 first->truesize += skb->truesize;
75c30b13 7549 lro->last_frag = skb;
7d3d0439
RA		 7550 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
7551 return;
7552}