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s2io: Making LRO and UFO as module loadable parameter.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / s2io.c
CommitLineData
1da177e4 1/************************************************************************
776bd20f 2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
1da177e4
LT		 3 * Copyright(c) 2002-2005 Neterion Inc.
4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
20346722
K		 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
1da177e4
LT		 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
20346722 21 * Francois Romieu : For pointing out all code part that were
1da177e4 22 * deprecated and also styling related comments.
20346722 23 * Grant Grundler : For helping me get rid of some Architecture
1da177e4
LT		 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
20346722 26 *
1da177e4
LT		 27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
9dc737a7 29 *
20346722
K		 30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
9dc737a7
AR		 32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
da6971d8
AR		 34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35 * values are 1, 2 and 3.
1da177e4 36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
20346722 37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
1da177e4 38 * Tx descriptors that can be associated with each corresponding FIFO.
9dc737a7
AR		 39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 1(MSI), 2(MSI_X). Default value is '0(INTA)'
41 * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
1da177e4
LT		 45 ************************************************************************/
46
1da177e4
LT		 47#include <linux/module.h>
48#include <linux/types.h>
49#include <linux/errno.h>
50#include <linux/ioport.h>
51#include <linux/pci.h>
1e7f0bd8 52#include <linux/dma-mapping.h>
1da177e4
LT		 53#include <linux/kernel.h>
54#include <linux/netdevice.h>
55#include <linux/etherdevice.h>
56#include <linux/skbuff.h>
57#include <linux/init.h>
58#include <linux/delay.h>
59#include <linux/stddef.h>
60#include <linux/ioctl.h>
61#include <linux/timex.h>
62#include <linux/sched.h>
63#include <linux/ethtool.h>
1da177e4 64#include <linux/workqueue.h>
be3a6b02 65#include <linux/if_vlan.h>
7d3d0439
RA		 66#include <linux/ip.h>
67#include <linux/tcp.h>
68#include <net/tcp.h>
1da177e4 69
1da177e4
LT		 70#include <asm/system.h>
71#include <asm/uaccess.h>
20346722 72#include <asm/io.h>
fe931395 73#include <asm/div64.h>
330ce0de 74#include <asm/irq.h>
1da177e4
LT		 75
76/* local include */
77#include "s2io.h"
78#include "s2io-regs.h"
79
75c30b13 80#define DRV_VERSION "2.0.15.2"
6c1792f4 81
1da177e4 82/* S2io Driver name & version. */
20346722 83static char s2io_driver_name[] = "Neterion";
6c1792f4 84static char s2io_driver_version[] = DRV_VERSION;
1da177e4 85
26df54bf
AB		 86static int rxd_size[4] = {32,48,48,64};
87static int rxd_count[4] = {127,85,85,63};
da6971d8 88
5e25b9dd
K		 89static inline int RXD_IS_UP2DT(RxD_t *rxdp)
90{
91 int ret;
92
93 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
94 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
95
96 return ret;
97}
98
20346722 99/*
1da177e4
LT		 100 * Cards with following subsystem_id have a link state indication
101 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
102 * macro below identifies these cards given the subsystem_id.
103 */
541ae68f
K		 104#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
105 (dev_type == XFRAME_I_DEVICE) ? \
106 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
107 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
1da177e4
LT		 108
109#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
110 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
111#define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
112#define PANIC 1
113#define LOW 2
114static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
115{
20346722
K		 116 mac_info_t *mac_control;
117
118 mac_control = &sp->mac_control;
863c11a9
AR		 119 if (rxb_size <= rxd_count[sp->rxd_mode])
120 return PANIC;
121 else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
122 return LOW;
123 return 0;
1da177e4
LT		 124}
125
126/* Ethtool related variables and Macros. */
127static char s2io_gstrings[][ETH_GSTRING_LEN] = {
128 "Register test\t(offline)",
129 "Eeprom test\t(offline)",
130 "Link test\t(online)",
131 "RLDRAM test\t(offline)",
132 "BIST Test\t(offline)"
133};
134
135static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
136 {"tmac_frms"},
137 {"tmac_data_octets"},
138 {"tmac_drop_frms"},
139 {"tmac_mcst_frms"},
140 {"tmac_bcst_frms"},
141 {"tmac_pause_ctrl_frms"},
bd1034f0
AR		 142 {"tmac_ttl_octets"},
143 {"tmac_ucst_frms"},
144 {"tmac_nucst_frms"},
1da177e4 145 {"tmac_any_err_frms"},
bd1034f0 146 {"tmac_ttl_less_fb_octets"},
1da177e4
LT		 147 {"tmac_vld_ip_octets"},
148 {"tmac_vld_ip"},
149 {"tmac_drop_ip"},
150 {"tmac_icmp"},
151 {"tmac_rst_tcp"},
152 {"tmac_tcp"},
153 {"tmac_udp"},
154 {"rmac_vld_frms"},
155 {"rmac_data_octets"},
156 {"rmac_fcs_err_frms"},
157 {"rmac_drop_frms"},
158 {"rmac_vld_mcst_frms"},
159 {"rmac_vld_bcst_frms"},
160 {"rmac_in_rng_len_err_frms"},
bd1034f0 161 {"rmac_out_rng_len_err_frms"},
1da177e4
LT		 162 {"rmac_long_frms"},
163 {"rmac_pause_ctrl_frms"},
bd1034f0
AR		 164 {"rmac_unsup_ctrl_frms"},
165 {"rmac_ttl_octets"},
166 {"rmac_accepted_ucst_frms"},
167 {"rmac_accepted_nucst_frms"},
1da177e4 168 {"rmac_discarded_frms"},
bd1034f0
AR		 169 {"rmac_drop_events"},
170 {"rmac_ttl_less_fb_octets"},
171 {"rmac_ttl_frms"},
1da177e4
LT		 172 {"rmac_usized_frms"},
173 {"rmac_osized_frms"},
174 {"rmac_frag_frms"},
175 {"rmac_jabber_frms"},
bd1034f0
AR		 176 {"rmac_ttl_64_frms"},
177 {"rmac_ttl_65_127_frms"},
178 {"rmac_ttl_128_255_frms"},
179 {"rmac_ttl_256_511_frms"},
180 {"rmac_ttl_512_1023_frms"},
181 {"rmac_ttl_1024_1518_frms"},
1da177e4
LT		 182 {"rmac_ip"},
183 {"rmac_ip_octets"},
184 {"rmac_hdr_err_ip"},
185 {"rmac_drop_ip"},
186 {"rmac_icmp"},
187 {"rmac_tcp"},
188 {"rmac_udp"},
189 {"rmac_err_drp_udp"},
bd1034f0
AR		 190 {"rmac_xgmii_err_sym"},
191 {"rmac_frms_q0"},
192 {"rmac_frms_q1"},
193 {"rmac_frms_q2"},
194 {"rmac_frms_q3"},
195 {"rmac_frms_q4"},
196 {"rmac_frms_q5"},
197 {"rmac_frms_q6"},
198 {"rmac_frms_q7"},
199 {"rmac_full_q0"},
200 {"rmac_full_q1"},
201 {"rmac_full_q2"},
202 {"rmac_full_q3"},
203 {"rmac_full_q4"},
204 {"rmac_full_q5"},
205 {"rmac_full_q6"},
206 {"rmac_full_q7"},
1da177e4 207 {"rmac_pause_cnt"},
bd1034f0
AR		 208 {"rmac_xgmii_data_err_cnt"},
209 {"rmac_xgmii_ctrl_err_cnt"},
1da177e4
LT		 210 {"rmac_accepted_ip"},
211 {"rmac_err_tcp"},
bd1034f0
AR		 212 {"rd_req_cnt"},
213 {"new_rd_req_cnt"},
214 {"new_rd_req_rtry_cnt"},
215 {"rd_rtry_cnt"},
216 {"wr_rtry_rd_ack_cnt"},
217 {"wr_req_cnt"},
218 {"new_wr_req_cnt"},
219 {"new_wr_req_rtry_cnt"},
220 {"wr_rtry_cnt"},
221 {"wr_disc_cnt"},
222 {"rd_rtry_wr_ack_cnt"},
223 {"txp_wr_cnt"},
224 {"txd_rd_cnt"},
225 {"txd_wr_cnt"},
226 {"rxd_rd_cnt"},
227 {"rxd_wr_cnt"},
228 {"txf_rd_cnt"},
229 {"rxf_wr_cnt"},
230 {"rmac_ttl_1519_4095_frms"},
231 {"rmac_ttl_4096_8191_frms"},
232 {"rmac_ttl_8192_max_frms"},
233 {"rmac_ttl_gt_max_frms"},
234 {"rmac_osized_alt_frms"},
235 {"rmac_jabber_alt_frms"},
236 {"rmac_gt_max_alt_frms"},
237 {"rmac_vlan_frms"},
238 {"rmac_len_discard"},
239 {"rmac_fcs_discard"},
240 {"rmac_pf_discard"},
241 {"rmac_da_discard"},
242 {"rmac_red_discard"},
243 {"rmac_rts_discard"},
244 {"rmac_ingm_full_discard"},
245 {"link_fault_cnt"},
7ba013ac
K		 246 {"\n DRIVER STATISTICS"},
247 {"single_bit_ecc_errs"},
248 {"double_bit_ecc_errs"},
bd1034f0
AR		 249 {"parity_err_cnt"},
250 {"serious_err_cnt"},
251 {"soft_reset_cnt"},
252 {"fifo_full_cnt"},
253 {"ring_full_cnt"},
254 ("alarm_transceiver_temp_high"),
255 ("alarm_transceiver_temp_low"),
256 ("alarm_laser_bias_current_high"),
257 ("alarm_laser_bias_current_low"),
258 ("alarm_laser_output_power_high"),
259 ("alarm_laser_output_power_low"),
260 ("warn_transceiver_temp_high"),
261 ("warn_transceiver_temp_low"),
262 ("warn_laser_bias_current_high"),
263 ("warn_laser_bias_current_low"),
264 ("warn_laser_output_power_high"),
265 ("warn_laser_output_power_low"),
7d3d0439
RA		 266 ("lro_aggregated_pkts"),
267 ("lro_flush_both_count"),
268 ("lro_out_of_sequence_pkts"),
269 ("lro_flush_due_to_max_pkts"),
270 ("lro_avg_aggr_pkts"),
1da177e4
LT		 271};
272
273#define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
274#define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
275
276#define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN
277#define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
278
25fff88e
K		 279#define S2IO_TIMER_CONF(timer, handle, arg, exp) \
280 init_timer(&timer); \
281 timer.function = handle; \
282 timer.data = (unsigned long) arg; \
283 mod_timer(&timer, (jiffies + exp)) \
284
be3a6b02
K		 285/* Add the vlan */
286static void s2io_vlan_rx_register(struct net_device *dev,
287 struct vlan_group *grp)
288{
289 nic_t *nic = dev->priv;
290 unsigned long flags;
291
292 spin_lock_irqsave(&nic->tx_lock, flags);
293 nic->vlgrp = grp;
294 spin_unlock_irqrestore(&nic->tx_lock, flags);
295}
296
297/* Unregister the vlan */
298static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
299{
300 nic_t *nic = dev->priv;
301 unsigned long flags;
302
303 spin_lock_irqsave(&nic->tx_lock, flags);
304 if (nic->vlgrp)
305 nic->vlgrp->vlan_devices[vid] = NULL;
306 spin_unlock_irqrestore(&nic->tx_lock, flags);
307}
308
20346722 309/*
1da177e4
LT		 310 * Constants to be programmed into the Xena's registers, to configure
311 * the XAUI.
312 */
313
1da177e4 314#define END_SIGN 0x0
f71e1309 315static const u64 herc_act_dtx_cfg[] = {
541ae68f 316 /* Set address */
e960fc5c 317 0x8000051536750000ULL, 0x80000515367500E0ULL,
541ae68f 318 /* Write data */
e960fc5c 319 0x8000051536750004ULL, 0x80000515367500E4ULL,
541ae68f
K		 320 /* Set address */
321 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
322 /* Write data */
323 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
324 /* Set address */
e960fc5c 325 0x801205150D440000ULL, 0x801205150D4400E0ULL,
326 /* Write data */
327 0x801205150D440004ULL, 0x801205150D4400E4ULL,
328 /* Set address */
541ae68f
K		 329 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
330 /* Write data */
331 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
332 /* Done */
333 END_SIGN
334};
335
f71e1309 336static const u64 xena_dtx_cfg[] = {
c92ca04b 337 /* Set address */
1da177e4 338 0x8000051500000000ULL, 0x80000515000000E0ULL,
c92ca04b
AR		 339 /* Write data */
340 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
341 /* Set address */
342 0x8001051500000000ULL, 0x80010515000000E0ULL,
343 /* Write data */
344 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
345 /* Set address */
1da177e4 346 0x8002051500000000ULL, 0x80020515000000E0ULL,
c92ca04b
AR		 347 /* Write data */
348 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1da177e4
LT		 349 END_SIGN
350};
351
20346722 352/*
1da177e4
LT		 353 * Constants for Fixing the MacAddress problem seen mostly on
354 * Alpha machines.
355 */
f71e1309 356static const u64 fix_mac[] = {
1da177e4
LT		 357 0x0060000000000000ULL, 0x0060600000000000ULL,
358 0x0040600000000000ULL, 0x0000600000000000ULL,
359 0x0020600000000000ULL, 0x0060600000000000ULL,
360 0x0020600000000000ULL, 0x0060600000000000ULL,
361 0x0020600000000000ULL, 0x0060600000000000ULL,
362 0x0020600000000000ULL, 0x0060600000000000ULL,
363 0x0020600000000000ULL, 0x0060600000000000ULL,
364 0x0020600000000000ULL, 0x0060600000000000ULL,
365 0x0020600000000000ULL, 0x0060600000000000ULL,
366 0x0020600000000000ULL, 0x0060600000000000ULL,
367 0x0020600000000000ULL, 0x0060600000000000ULL,
368 0x0020600000000000ULL, 0x0060600000000000ULL,
369 0x0020600000000000ULL, 0x0000600000000000ULL,
370 0x0040600000000000ULL, 0x0060600000000000ULL,
371 END_SIGN
372};
373
b41477f3
AR		 374MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
375MODULE_LICENSE("GPL");
376MODULE_VERSION(DRV_VERSION);
377
378
1da177e4 379/* Module Loadable parameters. */
b41477f3
AR		 380S2IO_PARM_INT(tx_fifo_num, 1);
381S2IO_PARM_INT(rx_ring_num, 1);
382
383
384S2IO_PARM_INT(rx_ring_mode, 1);
385S2IO_PARM_INT(use_continuous_tx_intrs, 1);
386S2IO_PARM_INT(rmac_pause_time, 0x100);
387S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
388S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
389S2IO_PARM_INT(shared_splits, 0);
390S2IO_PARM_INT(tmac_util_period, 5);
391S2IO_PARM_INT(rmac_util_period, 5);
392S2IO_PARM_INT(bimodal, 0);
393S2IO_PARM_INT(l3l4hdr_size, 128);
303bcb4b 394/* Frequency of Rx desc syncs expressed as power of 2 */
b41477f3 395S2IO_PARM_INT(rxsync_frequency, 3);
cc6e7c44 396/* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
b41477f3 397S2IO_PARM_INT(intr_type, 0);
7d3d0439 398/* Large receive offload feature */
b41477f3 399S2IO_PARM_INT(lro, 0);
7d3d0439
RA		 400/* Max pkts to be aggregated by LRO at one time. If not specified,
401 * aggregation happens until we hit max IP pkt size(64K)
402 */
b41477f3 403S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
b41477f3 404S2IO_PARM_INT(indicate_max_pkts, 0);
db874e65
SS		 405
406S2IO_PARM_INT(napi, 1);
407S2IO_PARM_INT(ufo, 0);
b41477f3
AR		 408
409static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
410 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
411static unsigned int rx_ring_sz[MAX_RX_RINGS] =
412 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
413static unsigned int rts_frm_len[MAX_RX_RINGS] =
414 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
415
416module_param_array(tx_fifo_len, uint, NULL, 0);
417module_param_array(rx_ring_sz, uint, NULL, 0);
418module_param_array(rts_frm_len, uint, NULL, 0);
1da177e4 419
20346722 420/*
1da177e4 421 * S2IO device table.
20346722 422 * This table lists all the devices that this driver supports.
1da177e4
LT		 423 */
424static struct pci_device_id s2io_tbl[] __devinitdata = {
425 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
426 PCI_ANY_ID, PCI_ANY_ID},
427 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
428 PCI_ANY_ID, PCI_ANY_ID},
429 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
20346722
K		 430 PCI_ANY_ID, PCI_ANY_ID},
431 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
432 PCI_ANY_ID, PCI_ANY_ID},
1da177e4
LT		 433 {0,}
434};
435
436MODULE_DEVICE_TABLE(pci, s2io_tbl);
437
438static struct pci_driver s2io_driver = {
439 .name = "S2IO",
440 .id_table = s2io_tbl,
441 .probe = s2io_init_nic,
442 .remove = __devexit_p(s2io_rem_nic),
443};
444
445/* A simplifier macro used both by init and free shared_mem Fns(). */
446#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
447
448/**
449 * init_shared_mem - Allocation and Initialization of Memory
450 * @nic: Device private variable.
20346722
K		 451 * Description: The function allocates all the memory areas shared
452 * between the NIC and the driver. This includes Tx descriptors,
1da177e4
LT		 453 * Rx descriptors and the statistics block.
454 */
455
456static int init_shared_mem(struct s2io_nic *nic)
457{
458 u32 size;
459 void *tmp_v_addr, *tmp_v_addr_next;
460 dma_addr_t tmp_p_addr, tmp_p_addr_next;
461 RxD_block_t *pre_rxd_blk = NULL;
20346722 462 int i, j, blk_cnt, rx_sz, tx_sz;
1da177e4
LT		 463 int lst_size, lst_per_page;
464 struct net_device *dev = nic->dev;
8ae418cf 465 unsigned long tmp;
1da177e4 466 buffAdd_t *ba;
1da177e4
LT		 467
468 mac_info_t *mac_control;
469 struct config_param *config;
470
471 mac_control = &nic->mac_control;
472 config = &nic->config;
473
474
475 /* Allocation and initialization of TXDLs in FIOFs */
476 size = 0;
477 for (i = 0; i < config->tx_fifo_num; i++) {
478 size += config->tx_cfg[i].fifo_len;
479 }
480 if (size > MAX_AVAILABLE_TXDS) {
b41477f3 481 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
0b1f7ebe 482 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
b41477f3 483 return -EINVAL;
1da177e4
LT		 484 }
485
486 lst_size = (sizeof(TxD_t) * config->max_txds);
20346722 487 tx_sz = lst_size * size;
1da177e4
LT		 488 lst_per_page = PAGE_SIZE / lst_size;
489
490 for (i = 0; i < config->tx_fifo_num; i++) {
491 int fifo_len = config->tx_cfg[i].fifo_len;
492 int list_holder_size = fifo_len * sizeof(list_info_hold_t);
20346722
K		 493 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
494 GFP_KERNEL);
495 if (!mac_control->fifos[i].list_info) {
1da177e4
LT		 496 DBG_PRINT(ERR_DBG,
497 "Malloc failed for list_info\n");
498 return -ENOMEM;
499 }
20346722 500 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
1da177e4
LT		 501 }
502 for (i = 0; i < config->tx_fifo_num; i++) {
503 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
504 lst_per_page);
20346722
K		 505 mac_control->fifos[i].tx_curr_put_info.offset = 0;
506 mac_control->fifos[i].tx_curr_put_info.fifo_len =
1da177e4 507 config->tx_cfg[i].fifo_len - 1;
20346722
K		 508 mac_control->fifos[i].tx_curr_get_info.offset = 0;
509 mac_control->fifos[i].tx_curr_get_info.fifo_len =
1da177e4 510 config->tx_cfg[i].fifo_len - 1;
20346722
K		 511 mac_control->fifos[i].fifo_no = i;
512 mac_control->fifos[i].nic = nic;
fed5eccd 513 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
20346722 514
1da177e4
LT		 515 for (j = 0; j < page_num; j++) {
516 int k = 0;
517 dma_addr_t tmp_p;
518 void *tmp_v;
519 tmp_v = pci_alloc_consistent(nic->pdev,
520 PAGE_SIZE, &tmp_p);
521 if (!tmp_v) {
522 DBG_PRINT(ERR_DBG,
523 "pci_alloc_consistent ");
524 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
525 return -ENOMEM;
526 }
776bd20f 527 /* If we got a zero DMA address(can happen on
528 * certain platforms like PPC), reallocate.
529 * Store virtual address of page we don't want,
530 * to be freed later.
531 */
532 if (!tmp_p) {
533 mac_control->zerodma_virt_addr = tmp_v;
6aa20a22 534 DBG_PRINT(INIT_DBG,
776bd20f 535 "%s: Zero DMA address for TxDL. ", dev->name);
6aa20a22 536 DBG_PRINT(INIT_DBG,
6b4d617d 537 "Virtual address %p\n", tmp_v);
776bd20f 538 tmp_v = pci_alloc_consistent(nic->pdev,
539 PAGE_SIZE, &tmp_p);
540 if (!tmp_v) {
541 DBG_PRINT(ERR_DBG,
542 "pci_alloc_consistent ");
543 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
544 return -ENOMEM;
545 }
546 }
1da177e4
LT		 547 while (k < lst_per_page) {
548 int l = (j * lst_per_page) + k;
549 if (l == config->tx_cfg[i].fifo_len)
20346722
K		 550 break;
551 mac_control->fifos[i].list_info[l].list_virt_addr =
1da177e4 552 tmp_v + (k * lst_size);
20346722 553 mac_control->fifos[i].list_info[l].list_phy_addr =
1da177e4
LT		 554 tmp_p + (k * lst_size);
555 k++;
556 }
557 }
558 }
1da177e4 559
4384247b 560 nic->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
fed5eccd
AR		 561 if (!nic->ufo_in_band_v)
562 return -ENOMEM;
563
1da177e4
LT		 564 /* Allocation and initialization of RXDs in Rings */
565 size = 0;
566 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 567 if (config->rx_cfg[i].num_rxd %
568 (rxd_count[nic->rxd_mode] + 1)) {
1da177e4
LT		 569 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
570 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
571 i);
572 DBG_PRINT(ERR_DBG, "RxDs per Block");
573 return FAILURE;
574 }
575 size += config->rx_cfg[i].num_rxd;
20346722 576 mac_control->rings[i].block_count =
da6971d8
AR		 577 config->rx_cfg[i].num_rxd /
578 (rxd_count[nic->rxd_mode] + 1 );
579 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
580 mac_control->rings[i].block_count;
1da177e4 581 }
da6971d8
AR		 582 if (nic->rxd_mode == RXD_MODE_1)
583 size = (size * (sizeof(RxD1_t)));
584 else
585 size = (size * (sizeof(RxD3_t)));
20346722 586 rx_sz = size;
1da177e4
LT		 587
588 for (i = 0; i < config->rx_ring_num; i++) {
20346722
K		 589 mac_control->rings[i].rx_curr_get_info.block_index = 0;
590 mac_control->rings[i].rx_curr_get_info.offset = 0;
591 mac_control->rings[i].rx_curr_get_info.ring_len =
1da177e4 592 config->rx_cfg[i].num_rxd - 1;
20346722
K		 593 mac_control->rings[i].rx_curr_put_info.block_index = 0;
594 mac_control->rings[i].rx_curr_put_info.offset = 0;
595 mac_control->rings[i].rx_curr_put_info.ring_len =
1da177e4 596 config->rx_cfg[i].num_rxd - 1;
20346722
K		 597 mac_control->rings[i].nic = nic;
598 mac_control->rings[i].ring_no = i;
599
da6971d8
AR		 600 blk_cnt = config->rx_cfg[i].num_rxd /
601 (rxd_count[nic->rxd_mode] + 1);
1da177e4
LT		 602 /* Allocating all the Rx blocks */
603 for (j = 0; j < blk_cnt; j++) {
da6971d8
AR		 604 rx_block_info_t *rx_blocks;
605 int l;
606
607 rx_blocks = &mac_control->rings[i].rx_blocks[j];
608 size = SIZE_OF_BLOCK; //size is always page size
1da177e4
LT		 609 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
610 &tmp_p_addr);
611 if (tmp_v_addr == NULL) {
612 /*
20346722
K		 613 * In case of failure, free_shared_mem()
614 * is called, which should free any
615 * memory that was alloced till the
1da177e4
LT		 616 * failure happened.
617 */
da6971d8 618 rx_blocks->block_virt_addr = tmp_v_addr;
1da177e4
LT		 619 return -ENOMEM;
620 }
621 memset(tmp_v_addr, 0, size);
da6971d8
AR		 622 rx_blocks->block_virt_addr = tmp_v_addr;
623 rx_blocks->block_dma_addr = tmp_p_addr;
624 rx_blocks->rxds = kmalloc(sizeof(rxd_info_t)*
625 rxd_count[nic->rxd_mode],
626 GFP_KERNEL);
627 for (l=0; l<rxd_count[nic->rxd_mode];l++) {
628 rx_blocks->rxds[l].virt_addr =
629 rx_blocks->block_virt_addr +
630 (rxd_size[nic->rxd_mode] * l);
631 rx_blocks->rxds[l].dma_addr =
632 rx_blocks->block_dma_addr +
633 (rxd_size[nic->rxd_mode] * l);
634 }
1da177e4
LT		 635 }
636 /* Interlinking all Rx Blocks */
637 for (j = 0; j < blk_cnt; j++) {
20346722
K		 638 tmp_v_addr =
639 mac_control->rings[i].rx_blocks[j].block_virt_addr;
1da177e4 640 tmp_v_addr_next =
20346722 641 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4 642 blk_cnt].block_virt_addr;
20346722
K		 643 tmp_p_addr =
644 mac_control->rings[i].rx_blocks[j].block_dma_addr;
1da177e4 645 tmp_p_addr_next =
20346722 646 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4
LT		 647 blk_cnt].block_dma_addr;
648
649 pre_rxd_blk = (RxD_block_t *) tmp_v_addr;
1da177e4
LT		 650 pre_rxd_blk->reserved_2_pNext_RxD_block =
651 (unsigned long) tmp_v_addr_next;
1da177e4
LT		 652 pre_rxd_blk->pNext_RxD_Blk_physical =
653 (u64) tmp_p_addr_next;
654 }
655 }
da6971d8
AR		 656 if (nic->rxd_mode >= RXD_MODE_3A) {
657 /*
658 * Allocation of Storages for buffer addresses in 2BUFF mode
659 * and the buffers as well.
660 */
661 for (i = 0; i < config->rx_ring_num; i++) {
662 blk_cnt = config->rx_cfg[i].num_rxd /
663 (rxd_count[nic->rxd_mode]+ 1);
664 mac_control->rings[i].ba =
665 kmalloc((sizeof(buffAdd_t *) * blk_cnt),
1da177e4 666 GFP_KERNEL);
da6971d8 667 if (!mac_control->rings[i].ba)
1da177e4 668 return -ENOMEM;
da6971d8
AR		 669 for (j = 0; j < blk_cnt; j++) {
670 int k = 0;
671 mac_control->rings[i].ba[j] =
672 kmalloc((sizeof(buffAdd_t) *
673 (rxd_count[nic->rxd_mode] + 1)),
674 GFP_KERNEL);
675 if (!mac_control->rings[i].ba[j])
1da177e4 676 return -ENOMEM;
da6971d8
AR		 677 while (k != rxd_count[nic->rxd_mode]) {
678 ba = &mac_control->rings[i].ba[j][k];
679
680 ba->ba_0_org = (void *) kmalloc
681 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
682 if (!ba->ba_0_org)
683 return -ENOMEM;
684 tmp = (unsigned long)ba->ba_0_org;
685 tmp += ALIGN_SIZE;
686 tmp &= ~((unsigned long) ALIGN_SIZE);
687 ba->ba_0 = (void *) tmp;
688
689 ba->ba_1_org = (void *) kmalloc
690 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
691 if (!ba->ba_1_org)
692 return -ENOMEM;
693 tmp = (unsigned long) ba->ba_1_org;
694 tmp += ALIGN_SIZE;
695 tmp &= ~((unsigned long) ALIGN_SIZE);
696 ba->ba_1 = (void *) tmp;
697 k++;
698 }
1da177e4
LT		 699 }
700 }
701 }
1da177e4
LT		 702
703 /* Allocation and initialization of Statistics block */
704 size = sizeof(StatInfo_t);
705 mac_control->stats_mem = pci_alloc_consistent
706 (nic->pdev, size, &mac_control->stats_mem_phy);
707
708 if (!mac_control->stats_mem) {
20346722
K		 709 /*
710 * In case of failure, free_shared_mem() is called, which
711 * should free any memory that was alloced till the
1da177e4
LT		 712 * failure happened.
713 */
714 return -ENOMEM;
715 }
716 mac_control->stats_mem_sz = size;
717
718 tmp_v_addr = mac_control->stats_mem;
719 mac_control->stats_info = (StatInfo_t *) tmp_v_addr;
720 memset(tmp_v_addr, 0, size);
1da177e4
LT		 721 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
722 (unsigned long long) tmp_p_addr);
723
724 return SUCCESS;
725}
726
20346722
K		 727/**
728 * free_shared_mem - Free the allocated Memory
1da177e4
LT		 729 * @nic: Device private variable.
730 * Description: This function is to free all memory locations allocated by
731 * the init_shared_mem() function and return it to the kernel.
732 */
733
734static void free_shared_mem(struct s2io_nic *nic)
735{
736 int i, j, blk_cnt, size;
737 void *tmp_v_addr;
738 dma_addr_t tmp_p_addr;
739 mac_info_t *mac_control;
740 struct config_param *config;
741 int lst_size, lst_per_page;
776bd20f 742 struct net_device *dev = nic->dev;
1da177e4
LT		 743
744 if (!nic)
745 return;
746
747 mac_control = &nic->mac_control;
748 config = &nic->config;
749
750 lst_size = (sizeof(TxD_t) * config->max_txds);
751 lst_per_page = PAGE_SIZE / lst_size;
752
753 for (i = 0; i < config->tx_fifo_num; i++) {
754 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
755 lst_per_page);
756 for (j = 0; j < page_num; j++) {
757 int mem_blks = (j * lst_per_page);
776bd20f 758 if (!mac_control->fifos[i].list_info)
6aa20a22 759 return;
776bd20f 760 if (!mac_control->fifos[i].list_info[mem_blks].
761 list_virt_addr)
1da177e4
LT		 762 break;
763 pci_free_consistent(nic->pdev, PAGE_SIZE,
20346722
K		 764 mac_control->fifos[i].
765 list_info[mem_blks].
1da177e4 766 list_virt_addr,
20346722
K		 767 mac_control->fifos[i].
768 list_info[mem_blks].
1da177e4
LT		 769 list_phy_addr);
770 }
776bd20f 771 /* If we got a zero DMA address during allocation,
772 * free the page now
773 */
774 if (mac_control->zerodma_virt_addr) {
775 pci_free_consistent(nic->pdev, PAGE_SIZE,
776 mac_control->zerodma_virt_addr,
777 (dma_addr_t)0);
6aa20a22 778 DBG_PRINT(INIT_DBG,
6b4d617d
AM		 779 "%s: Freeing TxDL with zero DMA addr. ",
780 dev->name);
781 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
782 mac_control->zerodma_virt_addr);
776bd20f 783 }
20346722 784 kfree(mac_control->fifos[i].list_info);
1da177e4
LT		 785 }
786
1da177e4 787 size = SIZE_OF_BLOCK;
1da177e4 788 for (i = 0; i < config->rx_ring_num; i++) {
20346722 789 blk_cnt = mac_control->rings[i].block_count;
1da177e4 790 for (j = 0; j < blk_cnt; j++) {
20346722
K		 791 tmp_v_addr = mac_control->rings[i].rx_blocks[j].
792 block_virt_addr;
793 tmp_p_addr = mac_control->rings[i].rx_blocks[j].
794 block_dma_addr;
1da177e4
LT		 795 if (tmp_v_addr == NULL)
796 break;
797 pci_free_consistent(nic->pdev, size,
798 tmp_v_addr, tmp_p_addr);
da6971d8 799 kfree(mac_control->rings[i].rx_blocks[j].rxds);
1da177e4
LT		 800 }
801 }
802
da6971d8
AR		 803 if (nic->rxd_mode >= RXD_MODE_3A) {
804 /* Freeing buffer storage addresses in 2BUFF mode. */
805 for (i = 0; i < config->rx_ring_num; i++) {
806 blk_cnt = config->rx_cfg[i].num_rxd /
807 (rxd_count[nic->rxd_mode] + 1);
808 for (j = 0; j < blk_cnt; j++) {
809 int k = 0;
810 if (!mac_control->rings[i].ba[j])
811 continue;
812 while (k != rxd_count[nic->rxd_mode]) {
813 buffAdd_t *ba =
814 &mac_control->rings[i].ba[j][k];
815 kfree(ba->ba_0_org);
816 kfree(ba->ba_1_org);
817 k++;
818 }
819 kfree(mac_control->rings[i].ba[j]);
1da177e4 820 }
da6971d8 821 kfree(mac_control->rings[i].ba);
1da177e4 822 }
1da177e4 823 }
1da177e4
LT		 824
825 if (mac_control->stats_mem) {
826 pci_free_consistent(nic->pdev,
827 mac_control->stats_mem_sz,
828 mac_control->stats_mem,
829 mac_control->stats_mem_phy);
830 }
fed5eccd
AR		 831 if (nic->ufo_in_band_v)
832 kfree(nic->ufo_in_band_v);
1da177e4
LT		 833}
834
541ae68f
K		 835/**
836 * s2io_verify_pci_mode -
837 */
838
839static int s2io_verify_pci_mode(nic_t *nic)
840{
509a2671 841 XENA_dev_config_t __iomem *bar0 = nic->bar0;
541ae68f
K		 842 register u64 val64 = 0;
843 int mode;
844
845 val64 = readq(&bar0->pci_mode);
846 mode = (u8)GET_PCI_MODE(val64);
847
848 if ( val64 & PCI_MODE_UNKNOWN_MODE)
849 return -1; /* Unknown PCI mode */
850 return mode;
851}
852
c92ca04b
AR		 853#define NEC_VENID 0x1033
854#define NEC_DEVID 0x0125
855static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
856{
857 struct pci_dev *tdev = NULL;
26d36b64
AC		 858 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
859 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
c92ca04b 860 if (tdev->bus == s2io_pdev->bus->parent)
26d36b64 861 pci_dev_put(tdev);
c92ca04b
AR		 862 return 1;
863 }
864 }
865 return 0;
866}
541ae68f 867
7b32a312 868static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
541ae68f
K		 869/**
870 * s2io_print_pci_mode -
871 */
872static int s2io_print_pci_mode(nic_t *nic)
873{
509a2671 874 XENA_dev_config_t __iomem *bar0 = nic->bar0;
541ae68f
K		 875 register u64 val64 = 0;
876 int mode;
877 struct config_param *config = &nic->config;
878
879 val64 = readq(&bar0->pci_mode);
880 mode = (u8)GET_PCI_MODE(val64);
881
882 if ( val64 & PCI_MODE_UNKNOWN_MODE)
883 return -1; /* Unknown PCI mode */
884
c92ca04b
AR		 885 config->bus_speed = bus_speed[mode];
886
887 if (s2io_on_nec_bridge(nic->pdev)) {
888 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
889 nic->dev->name);
890 return mode;
891 }
892
541ae68f
K		 893 if (val64 & PCI_MODE_32_BITS) {
894 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
895 } else {
896 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
897 }
898
899 switch(mode) {
900 case PCI_MODE_PCI_33:
901 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
541ae68f
K		 902 break;
903 case PCI_MODE_PCI_66:
904 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
541ae68f
K		 905 break;
906 case PCI_MODE_PCIX_M1_66:
907 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
541ae68f
K		 908 break;
909 case PCI_MODE_PCIX_M1_100:
910 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
541ae68f
K		 911 break;
912 case PCI_MODE_PCIX_M1_133:
913 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
541ae68f
K		 914 break;
915 case PCI_MODE_PCIX_M2_66:
916 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
541ae68f
K		 917 break;
918 case PCI_MODE_PCIX_M2_100:
919 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
541ae68f
K		 920 break;
921 case PCI_MODE_PCIX_M2_133:
922 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
541ae68f
K		 923 break;
924 default:
925 return -1; /* Unsupported bus speed */
926 }
927
928 return mode;
929}
930
20346722
K		 931/**
932 * init_nic - Initialization of hardware
1da177e4 933 * @nic: device peivate variable
20346722
K		 934 * Description: The function sequentially configures every block
935 * of the H/W from their reset values.
936 * Return Value: SUCCESS on success and
1da177e4
LT		 937 * '-1' on failure (endian settings incorrect).
938 */
939
940static int init_nic(struct s2io_nic *nic)
941{
942 XENA_dev_config_t __iomem *bar0 = nic->bar0;
943 struct net_device *dev = nic->dev;
944 register u64 val64 = 0;
945 void __iomem *add;
946 u32 time;
947 int i, j;
948 mac_info_t *mac_control;
949 struct config_param *config;
c92ca04b 950 int dtx_cnt = 0;
1da177e4 951 unsigned long long mem_share;
20346722 952 int mem_size;
1da177e4
LT		 953
954 mac_control = &nic->mac_control;
955 config = &nic->config;
956
5e25b9dd 957 /* to set the swapper controle on the card */
20346722 958 if(s2io_set_swapper(nic)) {
1da177e4
LT		 959 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
960 return -1;
961 }
962
541ae68f
K		 963 /*
964 * Herc requires EOI to be removed from reset before XGXS, so..
965 */
966 if (nic->device_type & XFRAME_II_DEVICE) {
967 val64 = 0xA500000000ULL;
968 writeq(val64, &bar0->sw_reset);
969 msleep(500);
970 val64 = readq(&bar0->sw_reset);
971 }
972
1da177e4
LT		 973 /* Remove XGXS from reset state */
974 val64 = 0;
975 writeq(val64, &bar0->sw_reset);
1da177e4 976 msleep(500);
20346722 977 val64 = readq(&bar0->sw_reset);
1da177e4
LT		 978
979 /* Enable Receiving broadcasts */
980 add = &bar0->mac_cfg;
981 val64 = readq(&bar0->mac_cfg);
982 val64 |= MAC_RMAC_BCAST_ENABLE;
983 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
984 writel((u32) val64, add);
985 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
986 writel((u32) (val64 >> 32), (add + 4));
987
988 /* Read registers in all blocks */
989 val64 = readq(&bar0->mac_int_mask);
990 val64 = readq(&bar0->mc_int_mask);
991 val64 = readq(&bar0->xgxs_int_mask);
992
993 /* Set MTU */
994 val64 = dev->mtu;
995 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
996
541ae68f
K		 997 if (nic->device_type & XFRAME_II_DEVICE) {
998 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
303bcb4b 999 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1da177e4 1000 &bar0->dtx_control, UF);
541ae68f
K		 1001 if (dtx_cnt & 0x1)
1002 msleep(1); /* Necessary!! */
1da177e4
LT		 1003 dtx_cnt++;
1004 }
541ae68f 1005 } else {
c92ca04b
AR		 1006 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1007 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1008 &bar0->dtx_control, UF);
1009 val64 = readq(&bar0->dtx_control);
1010 dtx_cnt++;
1da177e4
LT		 1011 }
1012 }
1013
1014 /* Tx DMA Initialization */
1015 val64 = 0;
1016 writeq(val64, &bar0->tx_fifo_partition_0);
1017 writeq(val64, &bar0->tx_fifo_partition_1);
1018 writeq(val64, &bar0->tx_fifo_partition_2);
1019 writeq(val64, &bar0->tx_fifo_partition_3);
1020
1021
1022 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1023 val64 |=
1024 vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
1025 13) | vBIT(config->tx_cfg[i].fifo_priority,
1026 ((i * 32) + 5), 3);
1027
1028 if (i == (config->tx_fifo_num - 1)) {
1029 if (i % 2 == 0)
1030 i++;
1031 }
1032
1033 switch (i) {
1034 case 1:
1035 writeq(val64, &bar0->tx_fifo_partition_0);
1036 val64 = 0;
1037 break;
1038 case 3:
1039 writeq(val64, &bar0->tx_fifo_partition_1);
1040 val64 = 0;
1041 break;
1042 case 5:
1043 writeq(val64, &bar0->tx_fifo_partition_2);
1044 val64 = 0;
1045 break;
1046 case 7:
1047 writeq(val64, &bar0->tx_fifo_partition_3);
1048 break;
1049 }
1050 }
1051
5e25b9dd
K		 1052 /*
1053 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1054 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1055 */
541ae68f
K		 1056 if ((nic->device_type == XFRAME_I_DEVICE) &&
1057 (get_xena_rev_id(nic->pdev) < 4))
5e25b9dd
K		 1058 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1059
1da177e4
LT		 1060 val64 = readq(&bar0->tx_fifo_partition_0);
1061 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1062 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1063
20346722
K		 1064 /*
1065 * Initialization of Tx_PA_CONFIG register to ignore packet
1da177e4
LT		 1066 * integrity checking.
1067 */
1068 val64 = readq(&bar0->tx_pa_cfg);
1069 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1070 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1071 writeq(val64, &bar0->tx_pa_cfg);
1072
1073 /* Rx DMA intialization. */
1074 val64 = 0;
1075 for (i = 0; i < config->rx_ring_num; i++) {
1076 val64 |=
1077 vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1078 3);
1079 }
1080 writeq(val64, &bar0->rx_queue_priority);
1081
20346722
K		 1082 /*
1083 * Allocating equal share of memory to all the
1da177e4
LT		 1084 * configured Rings.
1085 */
1086 val64 = 0;
541ae68f
K		 1087 if (nic->device_type & XFRAME_II_DEVICE)
1088 mem_size = 32;
1089 else
1090 mem_size = 64;
1091
1da177e4
LT		 1092 for (i = 0; i < config->rx_ring_num; i++) {
1093 switch (i) {
1094 case 0:
20346722
K		 1095 mem_share = (mem_size / config->rx_ring_num +
1096 mem_size % config->rx_ring_num);
1da177e4
LT		 1097 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1098 continue;
1099 case 1:
20346722 1100 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1101 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1102 continue;
1103 case 2:
20346722 1104 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1105 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1106 continue;
1107 case 3:
20346722 1108 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1109 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1110 continue;
1111 case 4:
20346722 1112 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1113 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1114 continue;
1115 case 5:
20346722 1116 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1117 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1118 continue;
1119 case 6:
20346722 1120 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1121 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1122 continue;
1123 case 7:
20346722 1124 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1125 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1126 continue;
1127 }
1128 }
1129 writeq(val64, &bar0->rx_queue_cfg);
1130
20346722 1131 /*
5e25b9dd
K		 1132 * Filling Tx round robin registers
1133 * as per the number of FIFOs
1da177e4 1134 */
5e25b9dd
K		 1135 switch (config->tx_fifo_num) {
1136 case 1:
1137 val64 = 0x0000000000000000ULL;
1138 writeq(val64, &bar0->tx_w_round_robin_0);
1139 writeq(val64, &bar0->tx_w_round_robin_1);
1140 writeq(val64, &bar0->tx_w_round_robin_2);
1141 writeq(val64, &bar0->tx_w_round_robin_3);
1142 writeq(val64, &bar0->tx_w_round_robin_4);
1143 break;
1144 case 2:
1145 val64 = 0x0000010000010000ULL;
1146 writeq(val64, &bar0->tx_w_round_robin_0);
1147 val64 = 0x0100000100000100ULL;
1148 writeq(val64, &bar0->tx_w_round_robin_1);
1149 val64 = 0x0001000001000001ULL;
1150 writeq(val64, &bar0->tx_w_round_robin_2);
1151 val64 = 0x0000010000010000ULL;
1152 writeq(val64, &bar0->tx_w_round_robin_3);
1153 val64 = 0x0100000000000000ULL;
1154 writeq(val64, &bar0->tx_w_round_robin_4);
1155 break;
1156 case 3:
1157 val64 = 0x0001000102000001ULL;
1158 writeq(val64, &bar0->tx_w_round_robin_0);
1159 val64 = 0x0001020000010001ULL;
1160 writeq(val64, &bar0->tx_w_round_robin_1);
1161 val64 = 0x0200000100010200ULL;
1162 writeq(val64, &bar0->tx_w_round_robin_2);
1163 val64 = 0x0001000102000001ULL;
1164 writeq(val64, &bar0->tx_w_round_robin_3);
1165 val64 = 0x0001020000000000ULL;
1166 writeq(val64, &bar0->tx_w_round_robin_4);
1167 break;
1168 case 4:
1169 val64 = 0x0001020300010200ULL;
1170 writeq(val64, &bar0->tx_w_round_robin_0);
1171 val64 = 0x0100000102030001ULL;
1172 writeq(val64, &bar0->tx_w_round_robin_1);
1173 val64 = 0x0200010000010203ULL;
1174 writeq(val64, &bar0->tx_w_round_robin_2);
1175 val64 = 0x0001020001000001ULL;
1176 writeq(val64, &bar0->tx_w_round_robin_3);
1177 val64 = 0x0203000100000000ULL;
1178 writeq(val64, &bar0->tx_w_round_robin_4);
1179 break;
1180 case 5:
1181 val64 = 0x0001000203000102ULL;
1182 writeq(val64, &bar0->tx_w_round_robin_0);
1183 val64 = 0x0001020001030004ULL;
1184 writeq(val64, &bar0->tx_w_round_robin_1);
1185 val64 = 0x0001000203000102ULL;
1186 writeq(val64, &bar0->tx_w_round_robin_2);
1187 val64 = 0x0001020001030004ULL;
1188 writeq(val64, &bar0->tx_w_round_robin_3);
1189 val64 = 0x0001000000000000ULL;
1190 writeq(val64, &bar0->tx_w_round_robin_4);
1191 break;
1192 case 6:
1193 val64 = 0x0001020304000102ULL;
1194 writeq(val64, &bar0->tx_w_round_robin_0);
1195 val64 = 0x0304050001020001ULL;
1196 writeq(val64, &bar0->tx_w_round_robin_1);
1197 val64 = 0x0203000100000102ULL;
1198 writeq(val64, &bar0->tx_w_round_robin_2);
1199 val64 = 0x0304000102030405ULL;
1200 writeq(val64, &bar0->tx_w_round_robin_3);
1201 val64 = 0x0001000200000000ULL;
1202 writeq(val64, &bar0->tx_w_round_robin_4);
1203 break;
1204 case 7:
1205 val64 = 0x0001020001020300ULL;
1206 writeq(val64, &bar0->tx_w_round_robin_0);
1207 val64 = 0x0102030400010203ULL;
1208 writeq(val64, &bar0->tx_w_round_robin_1);
1209 val64 = 0x0405060001020001ULL;
1210 writeq(val64, &bar0->tx_w_round_robin_2);
1211 val64 = 0x0304050000010200ULL;
1212 writeq(val64, &bar0->tx_w_round_robin_3);
1213 val64 = 0x0102030000000000ULL;
1214 writeq(val64, &bar0->tx_w_round_robin_4);
1215 break;
1216 case 8:
1217 val64 = 0x0001020300040105ULL;
1218 writeq(val64, &bar0->tx_w_round_robin_0);
1219 val64 = 0x0200030106000204ULL;
1220 writeq(val64, &bar0->tx_w_round_robin_1);
1221 val64 = 0x0103000502010007ULL;
1222 writeq(val64, &bar0->tx_w_round_robin_2);
1223 val64 = 0x0304010002060500ULL;
1224 writeq(val64, &bar0->tx_w_round_robin_3);
1225 val64 = 0x0103020400000000ULL;
1226 writeq(val64, &bar0->tx_w_round_robin_4);
1227 break;
1228 }
1229
b41477f3 1230 /* Enable all configured Tx FIFO partitions */
5d3213cc
AR		 1231 val64 = readq(&bar0->tx_fifo_partition_0);
1232 val64 |= (TX_FIFO_PARTITION_EN);
1233 writeq(val64, &bar0->tx_fifo_partition_0);
1234
5e25b9dd
K		 1235 /* Filling the Rx round robin registers as per the
1236 * number of Rings and steering based on QoS.
1237 */
1238 switch (config->rx_ring_num) {
1239 case 1:
1240 val64 = 0x8080808080808080ULL;
1241 writeq(val64, &bar0->rts_qos_steering);
1242 break;
1243 case 2:
1244 val64 = 0x0000010000010000ULL;
1245 writeq(val64, &bar0->rx_w_round_robin_0);
1246 val64 = 0x0100000100000100ULL;
1247 writeq(val64, &bar0->rx_w_round_robin_1);
1248 val64 = 0x0001000001000001ULL;
1249 writeq(val64, &bar0->rx_w_round_robin_2);
1250 val64 = 0x0000010000010000ULL;
1251 writeq(val64, &bar0->rx_w_round_robin_3);
1252 val64 = 0x0100000000000000ULL;
1253 writeq(val64, &bar0->rx_w_round_robin_4);
1254
1255 val64 = 0x8080808040404040ULL;
1256 writeq(val64, &bar0->rts_qos_steering);
1257 break;
1258 case 3:
1259 val64 = 0x0001000102000001ULL;
1260 writeq(val64, &bar0->rx_w_round_robin_0);
1261 val64 = 0x0001020000010001ULL;
1262 writeq(val64, &bar0->rx_w_round_robin_1);
1263 val64 = 0x0200000100010200ULL;
1264 writeq(val64, &bar0->rx_w_round_robin_2);
1265 val64 = 0x0001000102000001ULL;
1266 writeq(val64, &bar0->rx_w_round_robin_3);
1267 val64 = 0x0001020000000000ULL;
1268 writeq(val64, &bar0->rx_w_round_robin_4);
1269
1270 val64 = 0x8080804040402020ULL;
1271 writeq(val64, &bar0->rts_qos_steering);
1272 break;
1273 case 4:
1274 val64 = 0x0001020300010200ULL;
1275 writeq(val64, &bar0->rx_w_round_robin_0);
1276 val64 = 0x0100000102030001ULL;
1277 writeq(val64, &bar0->rx_w_round_robin_1);
1278 val64 = 0x0200010000010203ULL;
1279 writeq(val64, &bar0->rx_w_round_robin_2);
6aa20a22 1280 val64 = 0x0001020001000001ULL;
5e25b9dd
K		 1281 writeq(val64, &bar0->rx_w_round_robin_3);
1282 val64 = 0x0203000100000000ULL;
1283 writeq(val64, &bar0->rx_w_round_robin_4);
1284
1285 val64 = 0x8080404020201010ULL;
1286 writeq(val64, &bar0->rts_qos_steering);
1287 break;
1288 case 5:
1289 val64 = 0x0001000203000102ULL;
1290 writeq(val64, &bar0->rx_w_round_robin_0);
1291 val64 = 0x0001020001030004ULL;
1292 writeq(val64, &bar0->rx_w_round_robin_1);
1293 val64 = 0x0001000203000102ULL;
1294 writeq(val64, &bar0->rx_w_round_robin_2);
1295 val64 = 0x0001020001030004ULL;
1296 writeq(val64, &bar0->rx_w_round_robin_3);
1297 val64 = 0x0001000000000000ULL;
1298 writeq(val64, &bar0->rx_w_round_robin_4);
1299
1300 val64 = 0x8080404020201008ULL;
1301 writeq(val64, &bar0->rts_qos_steering);
1302 break;
1303 case 6:
1304 val64 = 0x0001020304000102ULL;
1305 writeq(val64, &bar0->rx_w_round_robin_0);
1306 val64 = 0x0304050001020001ULL;
1307 writeq(val64, &bar0->rx_w_round_robin_1);
1308 val64 = 0x0203000100000102ULL;
1309 writeq(val64, &bar0->rx_w_round_robin_2);
1310 val64 = 0x0304000102030405ULL;
1311 writeq(val64, &bar0->rx_w_round_robin_3);
1312 val64 = 0x0001000200000000ULL;
1313 writeq(val64, &bar0->rx_w_round_robin_4);
1314
1315 val64 = 0x8080404020100804ULL;
1316 writeq(val64, &bar0->rts_qos_steering);
1317 break;
1318 case 7:
1319 val64 = 0x0001020001020300ULL;
1320 writeq(val64, &bar0->rx_w_round_robin_0);
1321 val64 = 0x0102030400010203ULL;
1322 writeq(val64, &bar0->rx_w_round_robin_1);
1323 val64 = 0x0405060001020001ULL;
1324 writeq(val64, &bar0->rx_w_round_robin_2);
1325 val64 = 0x0304050000010200ULL;
1326 writeq(val64, &bar0->rx_w_round_robin_3);
1327 val64 = 0x0102030000000000ULL;
1328 writeq(val64, &bar0->rx_w_round_robin_4);
1329
1330 val64 = 0x8080402010080402ULL;
1331 writeq(val64, &bar0->rts_qos_steering);
1332 break;
1333 case 8:
1334 val64 = 0x0001020300040105ULL;
1335 writeq(val64, &bar0->rx_w_round_robin_0);
1336 val64 = 0x0200030106000204ULL;
1337 writeq(val64, &bar0->rx_w_round_robin_1);
1338 val64 = 0x0103000502010007ULL;
1339 writeq(val64, &bar0->rx_w_round_robin_2);
1340 val64 = 0x0304010002060500ULL;
1341 writeq(val64, &bar0->rx_w_round_robin_3);
1342 val64 = 0x0103020400000000ULL;
1343 writeq(val64, &bar0->rx_w_round_robin_4);
1344
1345 val64 = 0x8040201008040201ULL;
1346 writeq(val64, &bar0->rts_qos_steering);
1347 break;
1348 }
1da177e4
LT		 1349
1350 /* UDP Fix */
1351 val64 = 0;
20346722 1352 for (i = 0; i < 8; i++)
1da177e4
LT		 1353 writeq(val64, &bar0->rts_frm_len_n[i]);
1354
5e25b9dd
K		 1355 /* Set the default rts frame length for the rings configured */
1356 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1357 for (i = 0 ; i < config->rx_ring_num ; i++)
1358 writeq(val64, &bar0->rts_frm_len_n[i]);
1359
1360 /* Set the frame length for the configured rings
1361 * desired by the user
1362 */
1363 for (i = 0; i < config->rx_ring_num; i++) {
1364 /* If rts_frm_len[i] == 0 then it is assumed that user not
1365 * specified frame length steering.
1366 * If the user provides the frame length then program
1367 * the rts_frm_len register for those values or else
1368 * leave it as it is.
1369 */
1370 if (rts_frm_len[i] != 0) {
1371 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1372 &bar0->rts_frm_len_n[i]);
1373 }
1374 }
1da177e4 1375
20346722 1376 /* Program statistics memory */
1da177e4 1377 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1da177e4 1378
541ae68f
K		 1379 if (nic->device_type == XFRAME_II_DEVICE) {
1380 val64 = STAT_BC(0x320);
1381 writeq(val64, &bar0->stat_byte_cnt);
1382 }
1383
20346722 1384 /*
1da177e4
LT		 1385 * Initializing the sampling rate for the device to calculate the
1386 * bandwidth utilization.
1387 */
1388 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1389 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1390 writeq(val64, &bar0->mac_link_util);
1391
1392
20346722
K		 1393 /*
1394 * Initializing the Transmit and Receive Traffic Interrupt
1da177e4
LT		 1395 * Scheme.
1396 */
20346722
K		 1397 /*
1398 * TTI Initialization. Default Tx timer gets us about
1da177e4
LT		 1399 * 250 interrupts per sec. Continuous interrupts are enabled
1400 * by default.
1401 */
541ae68f
K		 1402 if (nic->device_type == XFRAME_II_DEVICE) {
1403 int count = (nic->config.bus_speed * 125)/2;
1404 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1405 } else {
1406
1407 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1408 }
1409 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1da177e4 1410 TTI_DATA1_MEM_TX_URNG_B(0x10) |
5e25b9dd 1411 TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
541ae68f
K		 1412 if (use_continuous_tx_intrs)
1413 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1da177e4
LT		 1414 writeq(val64, &bar0->tti_data1_mem);
1415
1416 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1417 TTI_DATA2_MEM_TX_UFC_B(0x20) |
5e25b9dd 1418 TTI_DATA2_MEM_TX_UFC_C(0x70) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1da177e4
LT		 1419 writeq(val64, &bar0->tti_data2_mem);
1420
1421 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1422 writeq(val64, &bar0->tti_command_mem);
1423
20346722 1424 /*
1da177e4
LT		 1425 * Once the operation completes, the Strobe bit of the command
1426 * register will be reset. We poll for this particular condition
1427 * We wait for a maximum of 500ms for the operation to complete,
1428 * if it's not complete by then we return error.
1429 */
1430 time = 0;
1431 while (TRUE) {
1432 val64 = readq(&bar0->tti_command_mem);
1433 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1434 break;
1435 }
1436 if (time > 10) {
1437 DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1438 dev->name);
1439 return -1;
1440 }
1441 msleep(50);
1442 time++;
1443 }
1444
b6e3f982
K		 1445 if (nic->config.bimodal) {
1446 int k = 0;
1447 for (k = 0; k < config->rx_ring_num; k++) {
1448 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1449 val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1450 writeq(val64, &bar0->tti_command_mem);
541ae68f 1451
541ae68f 1452 /*
b6e3f982
K		 1453 * Once the operation completes, the Strobe bit of the command
1454 * register will be reset. We poll for this particular condition
1455 * We wait for a maximum of 500ms for the operation to complete,
1456 * if it's not complete by then we return error.
1457 */
1458 time = 0;
1459 while (TRUE) {
1460 val64 = readq(&bar0->tti_command_mem);
1461 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1462 break;
1463 }
1464 if (time > 10) {
1465 DBG_PRINT(ERR_DBG,
1466 "%s: TTI init Failed\n",
1467 dev->name);
1468 return -1;
1469 }
1470 time++;
1471 msleep(50);
1472 }
1473 }
541ae68f 1474 } else {
1da177e4 1475
b6e3f982
K		 1476 /* RTI Initialization */
1477 if (nic->device_type == XFRAME_II_DEVICE) {
1478 /*
1479 * Programmed to generate Apprx 500 Intrs per
1480 * second
1481 */
1482 int count = (nic->config.bus_speed * 125)/4;
1483 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1484 } else {
1485 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1486 }
1487 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1488 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1489 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1da177e4 1490
b6e3f982 1491 writeq(val64, &bar0->rti_data1_mem);
1da177e4 1492
b6e3f982 1493 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
cc6e7c44
RA		 1494 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1495 if (nic->intr_type == MSI_X)
1496 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1497 RTI_DATA2_MEM_RX_UFC_D(0x40));
1498 else
1499 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1500 RTI_DATA2_MEM_RX_UFC_D(0x80));
b6e3f982 1501 writeq(val64, &bar0->rti_data2_mem);
1da177e4 1502
b6e3f982
K		 1503 for (i = 0; i < config->rx_ring_num; i++) {
1504 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1505 | RTI_CMD_MEM_OFFSET(i);
1506 writeq(val64, &bar0->rti_command_mem);
1507
1508 /*
1509 * Once the operation completes, the Strobe bit of the
1510 * command register will be reset. We poll for this
1511 * particular condition. We wait for a maximum of 500ms
1512 * for the operation to complete, if it's not complete
1513 * by then we return error.
1514 */
1515 time = 0;
1516 while (TRUE) {
1517 val64 = readq(&bar0->rti_command_mem);
1518 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1519 break;
1520 }
1521 if (time > 10) {
1522 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1523 dev->name);
1524 return -1;
1525 }
1526 time++;
1527 msleep(50);
1528 }
1da177e4 1529 }
1da177e4
LT		 1530 }
1531
20346722
K		 1532 /*
1533 * Initializing proper values as Pause threshold into all
1da177e4
LT		 1534 * the 8 Queues on Rx side.
1535 */
1536 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1537 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1538
1539 /* Disable RMAC PAD STRIPPING */
509a2671 1540 add = &bar0->mac_cfg;
1da177e4
LT		 1541 val64 = readq(&bar0->mac_cfg);
1542 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1543 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1544 writel((u32) (val64), add);
1545 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1546 writel((u32) (val64 >> 32), (add + 4));
1547 val64 = readq(&bar0->mac_cfg);
1548
7d3d0439
RA		 1549 /* Enable FCS stripping by adapter */
1550 add = &bar0->mac_cfg;
1551 val64 = readq(&bar0->mac_cfg);
1552 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1553 if (nic->device_type == XFRAME_II_DEVICE)
1554 writeq(val64, &bar0->mac_cfg);
1555 else {
1556 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1557 writel((u32) (val64), add);
1558 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1559 writel((u32) (val64 >> 32), (add + 4));
1560 }
1561
20346722
K		 1562 /*
1563 * Set the time value to be inserted in the pause frame
1da177e4
LT		 1564 * generated by xena.
1565 */
1566 val64 = readq(&bar0->rmac_pause_cfg);
1567 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1568 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1569 writeq(val64, &bar0->rmac_pause_cfg);
1570
20346722 1571 /*
1da177e4
LT		 1572 * Set the Threshold Limit for Generating the pause frame
1573 * If the amount of data in any Queue exceeds ratio of
1574 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1575 * pause frame is generated
1576 */
1577 val64 = 0;
1578 for (i = 0; i < 4; i++) {
1579 val64 |=
1580 (((u64) 0xFF00 | nic->mac_control.
1581 mc_pause_threshold_q0q3)
1582 << (i * 2 * 8));
1583 }
1584 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1585
1586 val64 = 0;
1587 for (i = 0; i < 4; i++) {
1588 val64 |=
1589 (((u64) 0xFF00 | nic->mac_control.
1590 mc_pause_threshold_q4q7)
1591 << (i * 2 * 8));
1592 }
1593 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1594
20346722
K		 1595 /*
1596 * TxDMA will stop Read request if the number of read split has
1da177e4
LT		 1597 * exceeded the limit pointed by shared_splits
1598 */
1599 val64 = readq(&bar0->pic_control);
1600 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1601 writeq(val64, &bar0->pic_control);
1602
863c11a9
AR		 1603 if (nic->config.bus_speed == 266) {
1604 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1605 writeq(0x0, &bar0->read_retry_delay);
1606 writeq(0x0, &bar0->write_retry_delay);
1607 }
1608
541ae68f
K		 1609 /*
1610 * Programming the Herc to split every write transaction
1611 * that does not start on an ADB to reduce disconnects.
1612 */
1613 if (nic->device_type == XFRAME_II_DEVICE) {
863c11a9
AR		 1614 val64 = EXT_REQ_EN | MISC_LINK_STABILITY_PRD(3);
1615 writeq(val64, &bar0->misc_control);
1616 val64 = readq(&bar0->pic_control2);
1617 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
1618 writeq(val64, &bar0->pic_control2);
541ae68f 1619 }
c92ca04b
AR		 1620 if (strstr(nic->product_name, "CX4")) {
1621 val64 = TMAC_AVG_IPG(0x17);
1622 writeq(val64, &bar0->tmac_avg_ipg);
a371a07d
K		 1623 }
1624
1da177e4
LT		 1625 return SUCCESS;
1626}
a371a07d
K		 1627#define LINK_UP_DOWN_INTERRUPT 1
1628#define MAC_RMAC_ERR_TIMER 2
1629
ac1f60db 1630static int s2io_link_fault_indication(nic_t *nic)
a371a07d 1631{
cc6e7c44
RA		 1632 if (nic->intr_type != INTA)
1633 return MAC_RMAC_ERR_TIMER;
a371a07d
K		 1634 if (nic->device_type == XFRAME_II_DEVICE)
1635 return LINK_UP_DOWN_INTERRUPT;
1636 else
1637 return MAC_RMAC_ERR_TIMER;
1638}
1da177e4 1639
20346722
K		 1640/**
1641 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1da177e4
LT		 1642 * @nic: device private variable,
1643 * @mask: A mask indicating which Intr block must be modified and,
1644 * @flag: A flag indicating whether to enable or disable the Intrs.
1645 * Description: This function will either disable or enable the interrupts
20346722
K		 1646 * depending on the flag argument. The mask argument can be used to
1647 * enable/disable any Intr block.
1da177e4
LT		 1648 * Return Value: NONE.
1649 */
1650
1651static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1652{
1653 XENA_dev_config_t __iomem *bar0 = nic->bar0;
1654 register u64 val64 = 0, temp64 = 0;
1655
1656 /* Top level interrupt classification */
1657 /* PIC Interrupts */
1658 if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1659 /* Enable PIC Intrs in the general intr mask register */
1660 val64 = TXPIC_INT_M | PIC_RX_INT_M;
1661 if (flag == ENABLE_INTRS) {
1662 temp64 = readq(&bar0->general_int_mask);
1663 temp64 &= ~((u64) val64);
1664 writeq(temp64, &bar0->general_int_mask);
20346722 1665 /*
a371a07d 1666 * If Hercules adapter enable GPIO otherwise
b41477f3 1667 * disable all PCIX, Flash, MDIO, IIC and GPIO
20346722
K		 1668 * interrupts for now.
1669 * TODO
1da177e4 1670 */
a371a07d
K		 1671 if (s2io_link_fault_indication(nic) ==
1672 LINK_UP_DOWN_INTERRUPT ) {
1673 temp64 = readq(&bar0->pic_int_mask);
1674 temp64 &= ~((u64) PIC_INT_GPIO);
1675 writeq(temp64, &bar0->pic_int_mask);
1676 temp64 = readq(&bar0->gpio_int_mask);
1677 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1678 writeq(temp64, &bar0->gpio_int_mask);
1679 } else {
1680 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1681 }
20346722 1682 /*
1da177e4
LT		 1683 * No MSI Support is available presently, so TTI and
1684 * RTI interrupts are also disabled.
1685 */
1686 } else if (flag == DISABLE_INTRS) {
20346722
K		 1687 /*
1688 * Disable PIC Intrs in the general
1689 * intr mask register
1da177e4
LT		 1690 */
1691 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1692 temp64 = readq(&bar0->general_int_mask);
1693 val64 |= temp64;
1694 writeq(val64, &bar0->general_int_mask);
1695 }
1696 }
1697
1698 /* DMA Interrupts */
1699 /* Enabling/Disabling Tx DMA interrupts */
1700 if (mask & TX_DMA_INTR) {
1701 /* Enable TxDMA Intrs in the general intr mask register */
1702 val64 = TXDMA_INT_M;
1703 if (flag == ENABLE_INTRS) {
1704 temp64 = readq(&bar0->general_int_mask);
1705 temp64 &= ~((u64) val64);
1706 writeq(temp64, &bar0->general_int_mask);
20346722
K		 1707 /*
1708 * Keep all interrupts other than PFC interrupt
1da177e4
LT		 1709 * and PCC interrupt disabled in DMA level.
1710 */
1711 val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M |
1712 TXDMA_PCC_INT_M);
1713 writeq(val64, &bar0->txdma_int_mask);
20346722
K		 1714 /*
1715 * Enable only the MISC error 1 interrupt in PFC block
1da177e4
LT		 1716 */
1717 val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);
1718 writeq(val64, &bar0->pfc_err_mask);
20346722
K		 1719 /*
1720 * Enable only the FB_ECC error interrupt in PCC block
1da177e4
LT		 1721 */
1722 val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR);
1723 writeq(val64, &bar0->pcc_err_mask);
1724 } else if (flag == DISABLE_INTRS) {
20346722
K		 1725 /*
1726 * Disable TxDMA Intrs in the general intr mask
1727 * register
1da177e4
LT		 1728 */
1729 writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);
1730 writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);
1731 temp64 = readq(&bar0->general_int_mask);
1732 val64 |= temp64;
1733 writeq(val64, &bar0->general_int_mask);
1734 }
1735 }
1736
1737 /* Enabling/Disabling Rx DMA interrupts */
1738 if (mask & RX_DMA_INTR) {
1739 /* Enable RxDMA Intrs in the general intr mask register */
1740 val64 = RXDMA_INT_M;
1741 if (flag == ENABLE_INTRS) {
1742 temp64 = readq(&bar0->general_int_mask);
1743 temp64 &= ~((u64) val64);
1744 writeq(temp64, &bar0->general_int_mask);
20346722
K		 1745 /*
1746 * All RxDMA block interrupts are disabled for now
1747 * TODO
1da177e4
LT		 1748 */
1749 writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1750 } else if (flag == DISABLE_INTRS) {
20346722
K		 1751 /*
1752 * Disable RxDMA Intrs in the general intr mask
1753 * register
1da177e4
LT		 1754 */
1755 writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1756 temp64 = readq(&bar0->general_int_mask);
1757 val64 |= temp64;
1758 writeq(val64, &bar0->general_int_mask);
1759 }
1760 }
1761
1762 /* MAC Interrupts */
1763 /* Enabling/Disabling MAC interrupts */
1764 if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1765 val64 = TXMAC_INT_M | RXMAC_INT_M;
1766 if (flag == ENABLE_INTRS) {
1767 temp64 = readq(&bar0->general_int_mask);
1768 temp64 &= ~((u64) val64);
1769 writeq(temp64, &bar0->general_int_mask);
20346722
K		 1770 /*
1771 * All MAC block error interrupts are disabled for now
1da177e4
LT		 1772 * TODO
1773 */
1da177e4 1774 } else if (flag == DISABLE_INTRS) {
20346722
K		 1775 /*
1776 * Disable MAC Intrs in the general intr mask register
1da177e4
LT		 1777 */
1778 writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1779 writeq(DISABLE_ALL_INTRS,
1780 &bar0->mac_rmac_err_mask);
1781
1782 temp64 = readq(&bar0->general_int_mask);
1783 val64 |= temp64;
1784 writeq(val64, &bar0->general_int_mask);
1785 }
1786 }
1787
1788 /* XGXS Interrupts */
1789 if (mask & (TX_XGXS_INTR | RX_XGXS_INTR)) {
1790 val64 = TXXGXS_INT_M | RXXGXS_INT_M;
1791 if (flag == ENABLE_INTRS) {
1792 temp64 = readq(&bar0->general_int_mask);
1793 temp64 &= ~((u64) val64);
1794 writeq(temp64, &bar0->general_int_mask);
20346722 1795 /*
1da177e4 1796 * All XGXS block error interrupts are disabled for now
20346722 1797 * TODO
1da177e4
LT		 1798 */
1799 writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1800 } else if (flag == DISABLE_INTRS) {
20346722
K		 1801 /*
1802 * Disable MC Intrs in the general intr mask register
1da177e4
LT		 1803 */
1804 writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1805 temp64 = readq(&bar0->general_int_mask);
1806 val64 |= temp64;
1807 writeq(val64, &bar0->general_int_mask);
1808 }
1809 }
1810
1811 /* Memory Controller(MC) interrupts */
1812 if (mask & MC_INTR) {
1813 val64 = MC_INT_M;
1814 if (flag == ENABLE_INTRS) {
1815 temp64 = readq(&bar0->general_int_mask);
1816 temp64 &= ~((u64) val64);
1817 writeq(temp64, &bar0->general_int_mask);
20346722 1818 /*
5e25b9dd 1819 * Enable all MC Intrs.
1da177e4 1820 */
5e25b9dd
K		 1821 writeq(0x0, &bar0->mc_int_mask);
1822 writeq(0x0, &bar0->mc_err_mask);
1da177e4
LT		 1823 } else if (flag == DISABLE_INTRS) {
1824 /*
1825 * Disable MC Intrs in the general intr mask register
1826 */
1827 writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
1828 temp64 = readq(&bar0->general_int_mask);
1829 val64 |= temp64;
1830 writeq(val64, &bar0->general_int_mask);
1831 }
1832 }
1833
1834
1835 /* Tx traffic interrupts */
1836 if (mask & TX_TRAFFIC_INTR) {
1837 val64 = TXTRAFFIC_INT_M;
1838 if (flag == ENABLE_INTRS) {
1839 temp64 = readq(&bar0->general_int_mask);
1840 temp64 &= ~((u64) val64);
1841 writeq(temp64, &bar0->general_int_mask);
20346722 1842 /*
1da177e4 1843 * Enable all the Tx side interrupts
20346722 1844 * writing 0 Enables all 64 TX interrupt levels
1da177e4
LT		 1845 */
1846 writeq(0x0, &bar0->tx_traffic_mask);
1847 } else if (flag == DISABLE_INTRS) {
20346722
K		 1848 /*
1849 * Disable Tx Traffic Intrs in the general intr mask
1da177e4
LT		 1850 * register.
1851 */
1852 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1853 temp64 = readq(&bar0->general_int_mask);
1854 val64 |= temp64;
1855 writeq(val64, &bar0->general_int_mask);
1856 }
1857 }
1858
1859 /* Rx traffic interrupts */
1860 if (mask & RX_TRAFFIC_INTR) {
1861 val64 = RXTRAFFIC_INT_M;
1862 if (flag == ENABLE_INTRS) {
1863 temp64 = readq(&bar0->general_int_mask);
1864 temp64 &= ~((u64) val64);
1865 writeq(temp64, &bar0->general_int_mask);
1866 /* writing 0 Enables all 8 RX interrupt levels */
1867 writeq(0x0, &bar0->rx_traffic_mask);
1868 } else if (flag == DISABLE_INTRS) {
20346722
K		 1869 /*
1870 * Disable Rx Traffic Intrs in the general intr mask
1da177e4
LT		 1871 * register.
1872 */
1873 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1874 temp64 = readq(&bar0->general_int_mask);
1875 val64 |= temp64;
1876 writeq(val64, &bar0->general_int_mask);
1877 }
1878 }
1879}
1880
541ae68f 1881static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc)
20346722
K		 1882{
1883 int ret = 0;
1884
1885 if (flag == FALSE) {
541ae68f 1886 if ((!herc && (rev_id >= 4)) || herc) {
5e25b9dd
K		 1887 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1888 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1889 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1890 ret = 1;
1891 }
541ae68f 1892 }else {
5e25b9dd
K		 1893 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1894 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1895 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1896 ret = 1;
1897 }
20346722
K		 1898 }
1899 } else {
541ae68f 1900 if ((!herc && (rev_id >= 4)) || herc) {
5e25b9dd
K		 1901 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1902 ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1903 (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1904 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1905 ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1906 ret = 1;
1907 }
1908 } else {
1909 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
1910 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1911 (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1912 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1913 ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1914 ret = 1;
1915 }
20346722
K		 1916 }
1917 }
1918
1919 return ret;
1920}
1921/**
1922 * verify_xena_quiescence - Checks whether the H/W is ready
1da177e4
LT		 1923 * @val64 : Value read from adapter status register.
1924 * @flag : indicates if the adapter enable bit was ever written once
1925 * before.
1926 * Description: Returns whether the H/W is ready to go or not. Depending
20346722 1927 * on whether adapter enable bit was written or not the comparison
1da177e4
LT		 1928 * differs and the calling function passes the input argument flag to
1929 * indicate this.
20346722 1930 * Return: 1 If xena is quiescence
1da177e4
LT		 1931 * 0 If Xena is not quiescence
1932 */
1933
20346722 1934static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag)
1da177e4 1935{
541ae68f 1936 int ret = 0, herc;
1da177e4 1937 u64 tmp64 = ~((u64) val64);
5e25b9dd 1938 int rev_id = get_xena_rev_id(sp->pdev);
1da177e4 1939
541ae68f 1940 herc = (sp->device_type == XFRAME_II_DEVICE);
1da177e4
LT		 1941 if (!
1942 (tmp64 &
1943 (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY |
1944 ADAPTER_STATUS_PFC_READY | ADAPTER_STATUS_TMAC_BUF_EMPTY |
1945 ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY |
1946 ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK |
1947 ADAPTER_STATUS_P_PLL_LOCK))) {
541ae68f 1948 ret = check_prc_pcc_state(val64, flag, rev_id, herc);
1da177e4
LT		 1949 }
1950
1951 return ret;
1952}
1953
1954/**
1955 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
1956 * @sp: Pointer to device specifc structure
20346722 1957 * Description :
1da177e4
LT		 1958 * New procedure to clear mac address reading problems on Alpha platforms
1959 *
1960 */
1961
ac1f60db 1962static void fix_mac_address(nic_t * sp)
1da177e4
LT		 1963{
1964 XENA_dev_config_t __iomem *bar0 = sp->bar0;
1965 u64 val64;
1966 int i = 0;
1967
1968 while (fix_mac[i] != END_SIGN) {
1969 writeq(fix_mac[i++], &bar0->gpio_control);
20346722 1970 udelay(10);
1da177e4
LT		 1971 val64 = readq(&bar0->gpio_control);
1972 }
1973}
1974
1975/**
20346722 1976 * start_nic - Turns the device on
1da177e4 1977 * @nic : device private variable.
20346722
K		 1978 * Description:
1979 * This function actually turns the device on. Before this function is
1980 * called,all Registers are configured from their reset states
1981 * and shared memory is allocated but the NIC is still quiescent. On
1da177e4
LT		 1982 * calling this function, the device interrupts are cleared and the NIC is
1983 * literally switched on by writing into the adapter control register.
20346722 1984 * Return Value:
1da177e4
LT		 1985 * SUCCESS on success and -1 on failure.
1986 */
1987
1988static int start_nic(struct s2io_nic *nic)
1989{
1990 XENA_dev_config_t __iomem *bar0 = nic->bar0;
1991 struct net_device *dev = nic->dev;
1992 register u64 val64 = 0;
20346722 1993 u16 subid, i;
1da177e4
LT		 1994 mac_info_t *mac_control;
1995 struct config_param *config;
1996
1997 mac_control = &nic->mac_control;
1998 config = &nic->config;
1999
2000 /* PRC Initialization and configuration */
2001 for (i = 0; i < config->rx_ring_num; i++) {
20346722 2002 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
1da177e4
LT		 2003 &bar0->prc_rxd0_n[i]);
2004
2005 val64 = readq(&bar0->prc_ctrl_n[i]);
b6e3f982
K		 2006 if (nic->config.bimodal)
2007 val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
da6971d8
AR		 2008 if (nic->rxd_mode == RXD_MODE_1)
2009 val64 |= PRC_CTRL_RC_ENABLED;
2010 else
2011 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
863c11a9
AR		 2012 if (nic->device_type == XFRAME_II_DEVICE)
2013 val64 |= PRC_CTRL_GROUP_READS;
2014 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2015 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1da177e4
LT		 2016 writeq(val64, &bar0->prc_ctrl_n[i]);
2017 }
2018
da6971d8
AR		 2019 if (nic->rxd_mode == RXD_MODE_3B) {
2020 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2021 val64 = readq(&bar0->rx_pa_cfg);
2022 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2023 writeq(val64, &bar0->rx_pa_cfg);
2024 }
1da177e4 2025
20346722 2026 /*
1da177e4
LT		 2027 * Enabling MC-RLDRAM. After enabling the device, we timeout
2028 * for around 100ms, which is approximately the time required
2029 * for the device to be ready for operation.
2030 */
2031 val64 = readq(&bar0->mc_rldram_mrs);
2032 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2033 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2034 val64 = readq(&bar0->mc_rldram_mrs);
2035
20346722 2036 msleep(100); /* Delay by around 100 ms. */
1da177e4
LT		 2037
2038 /* Enabling ECC Protection. */
2039 val64 = readq(&bar0->adapter_control);
2040 val64 &= ~ADAPTER_ECC_EN;
2041 writeq(val64, &bar0->adapter_control);
2042
20346722
K		 2043 /*
2044 * Clearing any possible Link state change interrupts that
1da177e4
LT		 2045 * could have popped up just before Enabling the card.
2046 */
2047 val64 = readq(&bar0->mac_rmac_err_reg);
2048 if (val64)
2049 writeq(val64, &bar0->mac_rmac_err_reg);
2050
20346722
K		 2051 /*
2052 * Verify if the device is ready to be enabled, if so enable
1da177e4
LT		 2053 * it.
2054 */
2055 val64 = readq(&bar0->adapter_status);
20346722 2056 if (!verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
1da177e4
LT		 2057 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2058 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2059 (unsigned long long) val64);
2060 return FAILURE;
2061 }
2062
20346722 2063 /*
1da177e4 2064 * With some switches, link might be already up at this point.
20346722
K		 2065 * Because of this weird behavior, when we enable laser,
2066 * we may not get link. We need to handle this. We cannot
2067 * figure out which switch is misbehaving. So we are forced to
2068 * make a global change.
1da177e4
LT		 2069 */
2070
2071 /* Enabling Laser. */
2072 val64 = readq(&bar0->adapter_control);
2073 val64 |= ADAPTER_EOI_TX_ON;
2074 writeq(val64, &bar0->adapter_control);
2075
c92ca04b
AR		 2076 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2077 /*
2078 * Dont see link state interrupts initally on some switches,
2079 * so directly scheduling the link state task here.
2080 */
2081 schedule_work(&nic->set_link_task);
2082 }
1da177e4
LT		 2083 /* SXE-002: Initialize link and activity LED */
2084 subid = nic->pdev->subsystem_device;
541ae68f
K		 2085 if (((subid & 0xFF) >= 0x07) &&
2086 (nic->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 2087 val64 = readq(&bar0->gpio_control);
2088 val64 |= 0x0000800000000000ULL;
2089 writeq(val64, &bar0->gpio_control);
2090 val64 = 0x0411040400000000ULL;
509a2671 2091 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 2092 }
2093
1da177e4
LT		 2094 return SUCCESS;
2095}
fed5eccd
AR		 2096/**
2097 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2098 */
2099static struct sk_buff *s2io_txdl_getskb(fifo_info_t *fifo_data, TxD_t *txdlp, int get_off)
2100{
2101 nic_t *nic = fifo_data->nic;
2102 struct sk_buff *skb;
2103 TxD_t *txds;
2104 u16 j, frg_cnt;
2105
2106 txds = txdlp;
26b7625c 2107 if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
fed5eccd
AR		 2108 pci_unmap_single(nic->pdev, (dma_addr_t)
2109 txds->Buffer_Pointer, sizeof(u64),
2110 PCI_DMA_TODEVICE);
2111 txds++;
2112 }
2113
2114 skb = (struct sk_buff *) ((unsigned long)
2115 txds->Host_Control);
2116 if (!skb) {
2117 memset(txdlp, 0, (sizeof(TxD_t) * fifo_data->max_txds));
2118 return NULL;
2119 }
2120 pci_unmap_single(nic->pdev, (dma_addr_t)
2121 txds->Buffer_Pointer,
2122 skb->len - skb->data_len,
2123 PCI_DMA_TODEVICE);
2124 frg_cnt = skb_shinfo(skb)->nr_frags;
2125 if (frg_cnt) {
2126 txds++;
2127 for (j = 0; j < frg_cnt; j++, txds++) {
2128 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2129 if (!txds->Buffer_Pointer)
2130 break;
6aa20a22 2131 pci_unmap_page(nic->pdev, (dma_addr_t)
fed5eccd
AR		 2132 txds->Buffer_Pointer,
2133 frag->size, PCI_DMA_TODEVICE);
2134 }
2135 }
b41477f3 2136 memset(txdlp,0, (sizeof(TxD_t) * fifo_data->max_txds));
fed5eccd
AR		 2137 return(skb);
2138}
1da177e4 2139
20346722
K		 2140/**
2141 * free_tx_buffers - Free all queued Tx buffers
1da177e4 2142 * @nic : device private variable.
20346722 2143 * Description:
1da177e4 2144 * Free all queued Tx buffers.
20346722 2145 * Return Value: void
1da177e4
LT		 2146*/
2147
2148static void free_tx_buffers(struct s2io_nic *nic)
2149{
2150 struct net_device *dev = nic->dev;
2151 struct sk_buff *skb;
2152 TxD_t *txdp;
2153 int i, j;
2154 mac_info_t *mac_control;
2155 struct config_param *config;
fed5eccd 2156 int cnt = 0;
1da177e4
LT		 2157
2158 mac_control = &nic->mac_control;
2159 config = &nic->config;
2160
2161 for (i = 0; i < config->tx_fifo_num; i++) {
2162 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
20346722 2163 txdp = (TxD_t *) mac_control->fifos[i].list_info[j].
1da177e4 2164 list_virt_addr;
fed5eccd
AR		 2165 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2166 if (skb) {
2167 dev_kfree_skb(skb);
2168 cnt++;
1da177e4 2169 }
1da177e4
LT		 2170 }
2171 DBG_PRINT(INTR_DBG,
2172 "%s:forcibly freeing %d skbs on FIFO%d\n",
2173 dev->name, cnt, i);
20346722
K		 2174 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2175 mac_control->fifos[i].tx_curr_put_info.offset = 0;
1da177e4
LT		 2176 }
2177}
2178
20346722
K		 2179/**
2180 * stop_nic - To stop the nic
1da177e4 2181 * @nic ; device private variable.
20346722
K		 2182 * Description:
2183 * This function does exactly the opposite of what the start_nic()
1da177e4
LT		 2184 * function does. This function is called to stop the device.
2185 * Return Value:
2186 * void.
2187 */
2188
2189static void stop_nic(struct s2io_nic *nic)
2190{
2191 XENA_dev_config_t __iomem *bar0 = nic->bar0;
2192 register u64 val64 = 0;
5d3213cc 2193 u16 interruptible;
1da177e4
LT		 2194 mac_info_t *mac_control;
2195 struct config_param *config;
2196
2197 mac_control = &nic->mac_control;
2198 config = &nic->config;
2199
2200 /* Disable all interrupts */
e960fc5c 2201 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
a371a07d
K		 2202 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2203 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
1da177e4
LT		 2204 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2205
5d3213cc
AR		 2206 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2207 val64 = readq(&bar0->adapter_control);
2208 val64 &= ~(ADAPTER_CNTL_EN);
2209 writeq(val64, &bar0->adapter_control);
1da177e4
LT		 2210}
2211
26df54bf 2212static int fill_rxd_3buf(nic_t *nic, RxD_t *rxdp, struct sk_buff *skb)
da6971d8
AR		 2213{
2214 struct net_device *dev = nic->dev;
2215 struct sk_buff *frag_list;
50eb8006 2216 void *tmp;
da6971d8
AR		 2217
2218 /* Buffer-1 receives L3/L4 headers */
2219 ((RxD3_t*)rxdp)->Buffer1_ptr = pci_map_single
2220 (nic->pdev, skb->data, l3l4hdr_size + 4,
2221 PCI_DMA_FROMDEVICE);
2222
2223 /* skb_shinfo(skb)->frag_list will have L4 data payload */
2224 skb_shinfo(skb)->frag_list = dev_alloc_skb(dev->mtu + ALIGN_SIZE);
2225 if (skb_shinfo(skb)->frag_list == NULL) {
2226 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n ", dev->name);
2227 return -ENOMEM ;
2228 }
2229 frag_list = skb_shinfo(skb)->frag_list;
2230 frag_list->next = NULL;
50eb8006
JG		 2231 tmp = (void *)ALIGN((long)frag_list->data, ALIGN_SIZE + 1);
2232 frag_list->data = tmp;
2233 frag_list->tail = tmp;
da6971d8
AR		 2234
2235 /* Buffer-2 receives L4 data payload */
2236 ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single(nic->pdev,
2237 frag_list->data, dev->mtu,
2238 PCI_DMA_FROMDEVICE);
2239 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
2240 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
2241
2242 return SUCCESS;
2243}
2244
20346722
K		 2245/**
2246 * fill_rx_buffers - Allocates the Rx side skbs
1da177e4 2247 * @nic: device private variable
20346722
K		 2248 * @ring_no: ring number
2249 * Description:
1da177e4
LT		 2250 * The function allocates Rx side skbs and puts the physical
2251 * address of these buffers into the RxD buffer pointers, so that the NIC
2252 * can DMA the received frame into these locations.
2253 * The NIC supports 3 receive modes, viz
2254 * 1. single buffer,
2255 * 2. three buffer and
2256 * 3. Five buffer modes.
20346722
K		 2257 * Each mode defines how many fragments the received frame will be split
2258 * up into by the NIC. The frame is split into L3 header, L4 Header,
1da177e4
LT		 2259 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2260 * is split into 3 fragments. As of now only single buffer mode is
2261 * supported.
2262 * Return Value:
2263 * SUCCESS on success or an appropriate -ve value on failure.
2264 */
2265
ac1f60db 2266static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1da177e4
LT		 2267{
2268 struct net_device *dev = nic->dev;
2269 struct sk_buff *skb;
2270 RxD_t *rxdp;
2271 int off, off1, size, block_no, block_no1;
1da177e4 2272 u32 alloc_tab = 0;
20346722 2273 u32 alloc_cnt;
1da177e4
LT		 2274 mac_info_t *mac_control;
2275 struct config_param *config;
20346722 2276 u64 tmp;
1da177e4 2277 buffAdd_t *ba;
1da177e4 2278 unsigned long flags;
303bcb4b 2279 RxD_t *first_rxdp = NULL;
1da177e4
LT		 2280
2281 mac_control = &nic->mac_control;
2282 config = &nic->config;
20346722
K		 2283 alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2284 atomic_read(&nic->rx_bufs_left[ring_no]);
1da177e4 2285
5d3213cc 2286 block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
863c11a9 2287 off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
1da177e4 2288 while (alloc_tab < alloc_cnt) {
20346722 2289 block_no = mac_control->rings[ring_no].rx_curr_put_info.
1da177e4 2290 block_index;
20346722 2291 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
1da177e4 2292
da6971d8
AR		 2293 rxdp = mac_control->rings[ring_no].
2294 rx_blocks[block_no].rxds[off].virt_addr;
2295
2296 if ((block_no == block_no1) && (off == off1) &&
2297 (rxdp->Host_Control)) {
2298 DBG_PRINT(INTR_DBG, "%s: Get and Put",
2299 dev->name);
1da177e4
LT		 2300 DBG_PRINT(INTR_DBG, " info equated\n");
2301 goto end;
2302 }
da6971d8 2303 if (off && (off == rxd_count[nic->rxd_mode])) {
20346722 2304 mac_control->rings[ring_no].rx_curr_put_info.
1da177e4 2305 block_index++;
da6971d8
AR		 2306 if (mac_control->rings[ring_no].rx_curr_put_info.
2307 block_index == mac_control->rings[ring_no].
2308 block_count)
2309 mac_control->rings[ring_no].rx_curr_put_info.
2310 block_index = 0;
2311 block_no = mac_control->rings[ring_no].
2312 rx_curr_put_info.block_index;
2313 if (off == rxd_count[nic->rxd_mode])
2314 off = 0;
20346722 2315 mac_control->rings[ring_no].rx_curr_put_info.
da6971d8
AR		 2316 offset = off;
2317 rxdp = mac_control->rings[ring_no].
2318 rx_blocks[block_no].block_virt_addr;
1da177e4
LT		 2319 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2320 dev->name, rxdp);
2321 }
db874e65
SS		 2322 if(!napi) {
2323 spin_lock_irqsave(&nic->put_lock, flags);
2324 mac_control->rings[ring_no].put_pos =
2325 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2326 spin_unlock_irqrestore(&nic->put_lock, flags);
2327 } else {
2328 mac_control->rings[ring_no].put_pos =
2329 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2330 }
da6971d8
AR		 2331 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2332 ((nic->rxd_mode >= RXD_MODE_3A) &&
2333 (rxdp->Control_2 & BIT(0)))) {
20346722 2334 mac_control->rings[ring_no].rx_curr_put_info.
da6971d8 2335 offset = off;
1da177e4
LT		 2336 goto end;
2337 }
da6971d8
AR		 2338 /* calculate size of skb based on ring mode */
2339 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2340 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2341 if (nic->rxd_mode == RXD_MODE_1)
2342 size += NET_IP_ALIGN;
2343 else if (nic->rxd_mode == RXD_MODE_3B)
2344 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2345 else
2346 size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
1da177e4 2347
da6971d8
AR		 2348 /* allocate skb */
2349 skb = dev_alloc_skb(size);
2350 if(!skb) {
1da177e4
LT		 2351 DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
2352 DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
303bcb4b
K		 2353 if (first_rxdp) {
2354 wmb();
2355 first_rxdp->Control_1 |= RXD_OWN_XENA;
2356 }
da6971d8
AR		 2357 return -ENOMEM ;
2358 }
2359 if (nic->rxd_mode == RXD_MODE_1) {
2360 /* 1 buffer mode - normal operation mode */
2361 memset(rxdp, 0, sizeof(RxD1_t));
2362 skb_reserve(skb, NET_IP_ALIGN);
2363 ((RxD1_t*)rxdp)->Buffer0_ptr = pci_map_single
863c11a9
AR		 2364 (nic->pdev, skb->data, size - NET_IP_ALIGN,
2365 PCI_DMA_FROMDEVICE);
2366 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
da6971d8
AR		 2367
2368 } else if (nic->rxd_mode >= RXD_MODE_3A) {
2369 /*
2370 * 2 or 3 buffer mode -
2371 * Both 2 buffer mode and 3 buffer mode provides 128
2372 * byte aligned receive buffers.
2373 *
2374 * 3 buffer mode provides header separation where in
2375 * skb->data will have L3/L4 headers where as
2376 * skb_shinfo(skb)->frag_list will have the L4 data
2377 * payload
2378 */
2379
2380 memset(rxdp, 0, sizeof(RxD3_t));
2381 ba = &mac_control->rings[ring_no].ba[block_no][off];
2382 skb_reserve(skb, BUF0_LEN);
2383 tmp = (u64)(unsigned long) skb->data;
2384 tmp += ALIGN_SIZE;
2385 tmp &= ~ALIGN_SIZE;
2386 skb->data = (void *) (unsigned long)tmp;
2387 skb->tail = (void *) (unsigned long)tmp;
2388
75c30b13
AR		 2389 if (!(((RxD3_t*)rxdp)->Buffer0_ptr))
2390 ((RxD3_t*)rxdp)->Buffer0_ptr =
2391 pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
da6971d8 2392 PCI_DMA_FROMDEVICE);
75c30b13
AR		 2393 else
2394 pci_dma_sync_single_for_device(nic->pdev,
2395 (dma_addr_t) ((RxD3_t*)rxdp)->Buffer0_ptr,
2396 BUF0_LEN, PCI_DMA_FROMDEVICE);
da6971d8
AR		 2397 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2398 if (nic->rxd_mode == RXD_MODE_3B) {
2399 /* Two buffer mode */
2400
2401 /*
6aa20a22 2402 * Buffer2 will have L3/L4 header plus
da6971d8
AR		 2403 * L4 payload
2404 */
2405 ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single
2406 (nic->pdev, skb->data, dev->mtu + 4,
2407 PCI_DMA_FROMDEVICE);
2408
75c30b13
AR		 2409 /* Buffer-1 will be dummy buffer. Not used */
2410 if (!(((RxD3_t*)rxdp)->Buffer1_ptr)) {
2411 ((RxD3_t*)rxdp)->Buffer1_ptr =
6aa20a22 2412 pci_map_single(nic->pdev,
75c30b13
AR		 2413 ba->ba_1, BUF1_LEN,
2414 PCI_DMA_FROMDEVICE);
2415 }
da6971d8
AR		 2416 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2417 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2418 (dev->mtu + 4);
2419 } else {
2420 /* 3 buffer mode */
2421 if (fill_rxd_3buf(nic, rxdp, skb) == -ENOMEM) {
2422 dev_kfree_skb_irq(skb);
2423 if (first_rxdp) {
2424 wmb();
2425 first_rxdp->Control_1 |=
2426 RXD_OWN_XENA;
2427 }
2428 return -ENOMEM ;
2429 }
2430 }
2431 rxdp->Control_2 |= BIT(0);
1da177e4 2432 }
1da177e4 2433 rxdp->Host_Control = (unsigned long) (skb);
303bcb4b
K		 2434 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2435 rxdp->Control_1 |= RXD_OWN_XENA;
1da177e4 2436 off++;
da6971d8
AR		 2437 if (off == (rxd_count[nic->rxd_mode] + 1))
2438 off = 0;
20346722 2439 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
20346722 2440
da6971d8 2441 rxdp->Control_2 |= SET_RXD_MARKER;
303bcb4b
K		 2442 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2443 if (first_rxdp) {
2444 wmb();
2445 first_rxdp->Control_1 |= RXD_OWN_XENA;
2446 }
2447 first_rxdp = rxdp;
2448 }
1da177e4
LT		 2449 atomic_inc(&nic->rx_bufs_left[ring_no]);
2450 alloc_tab++;
2451 }
2452
2453 end:
303bcb4b
K		 2454 /* Transfer ownership of first descriptor to adapter just before
2455 * exiting. Before that, use memory barrier so that ownership
2456 * and other fields are seen by adapter correctly.
2457 */
2458 if (first_rxdp) {
2459 wmb();
2460 first_rxdp->Control_1 |= RXD_OWN_XENA;
2461 }
2462
1da177e4
LT		 2463 return SUCCESS;
2464}
2465
da6971d8
AR		 2466static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2467{
2468 struct net_device *dev = sp->dev;
2469 int j;
2470 struct sk_buff *skb;
2471 RxD_t *rxdp;
2472 mac_info_t *mac_control;
2473 buffAdd_t *ba;
2474
2475 mac_control = &sp->mac_control;
2476 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2477 rxdp = mac_control->rings[ring_no].
2478 rx_blocks[blk].rxds[j].virt_addr;
2479 skb = (struct sk_buff *)
2480 ((unsigned long) rxdp->Host_Control);
2481 if (!skb) {
2482 continue;
2483 }
2484 if (sp->rxd_mode == RXD_MODE_1) {
2485 pci_unmap_single(sp->pdev, (dma_addr_t)
2486 ((RxD1_t*)rxdp)->Buffer0_ptr,
2487 dev->mtu +
2488 HEADER_ETHERNET_II_802_3_SIZE
2489 + HEADER_802_2_SIZE +
2490 HEADER_SNAP_SIZE,
2491 PCI_DMA_FROMDEVICE);
2492 memset(rxdp, 0, sizeof(RxD1_t));
2493 } else if(sp->rxd_mode == RXD_MODE_3B) {
2494 ba = &mac_control->rings[ring_no].
2495 ba[blk][j];
2496 pci_unmap_single(sp->pdev, (dma_addr_t)
2497 ((RxD3_t*)rxdp)->Buffer0_ptr,
2498 BUF0_LEN,
2499 PCI_DMA_FROMDEVICE);
2500 pci_unmap_single(sp->pdev, (dma_addr_t)
2501 ((RxD3_t*)rxdp)->Buffer1_ptr,
2502 BUF1_LEN,
2503 PCI_DMA_FROMDEVICE);
2504 pci_unmap_single(sp->pdev, (dma_addr_t)
2505 ((RxD3_t*)rxdp)->Buffer2_ptr,
2506 dev->mtu + 4,
2507 PCI_DMA_FROMDEVICE);
2508 memset(rxdp, 0, sizeof(RxD3_t));
2509 } else {
2510 pci_unmap_single(sp->pdev, (dma_addr_t)
2511 ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2512 PCI_DMA_FROMDEVICE);
2513 pci_unmap_single(sp->pdev, (dma_addr_t)
6aa20a22 2514 ((RxD3_t*)rxdp)->Buffer1_ptr,
da6971d8
AR		 2515 l3l4hdr_size + 4,
2516 PCI_DMA_FROMDEVICE);
2517 pci_unmap_single(sp->pdev, (dma_addr_t)
2518 ((RxD3_t*)rxdp)->Buffer2_ptr, dev->mtu,
2519 PCI_DMA_FROMDEVICE);
2520 memset(rxdp, 0, sizeof(RxD3_t));
2521 }
2522 dev_kfree_skb(skb);
2523 atomic_dec(&sp->rx_bufs_left[ring_no]);
2524 }
2525}
2526
1da177e4 2527/**
20346722 2528 * free_rx_buffers - Frees all Rx buffers
1da177e4 2529 * @sp: device private variable.
20346722 2530 * Description:
1da177e4
LT		 2531 * This function will free all Rx buffers allocated by host.
2532 * Return Value:
2533 * NONE.
2534 */
2535
2536static void free_rx_buffers(struct s2io_nic *sp)
2537{
2538 struct net_device *dev = sp->dev;
da6971d8 2539 int i, blk = 0, buf_cnt = 0;
1da177e4
LT		 2540 mac_info_t *mac_control;
2541 struct config_param *config;
1da177e4
LT		 2542
2543 mac_control = &sp->mac_control;
2544 config = &sp->config;
2545
2546 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 2547 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2548 free_rxd_blk(sp,i,blk);
1da177e4 2549
20346722
K		 2550 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2551 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2552 mac_control->rings[i].rx_curr_put_info.offset = 0;
2553 mac_control->rings[i].rx_curr_get_info.offset = 0;
1da177e4
LT		 2554 atomic_set(&sp->rx_bufs_left[i], 0);
2555 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2556 dev->name, buf_cnt, i);
2557 }
2558}
2559
2560/**
2561 * s2io_poll - Rx interrupt handler for NAPI support
2562 * @dev : pointer to the device structure.
20346722 2563 * @budget : The number of packets that were budgeted to be processed
1da177e4
LT		 2564 * during one pass through the 'Poll" function.
2565 * Description:
2566 * Comes into picture only if NAPI support has been incorporated. It does
2567 * the same thing that rx_intr_handler does, but not in a interrupt context
2568 * also It will process only a given number of packets.
2569 * Return value:
2570 * 0 on success and 1 if there are No Rx packets to be processed.
2571 */
2572
1da177e4
LT		 2573static int s2io_poll(struct net_device *dev, int *budget)
2574{
2575 nic_t *nic = dev->priv;
20346722 2576 int pkt_cnt = 0, org_pkts_to_process;
1da177e4
LT		 2577 mac_info_t *mac_control;
2578 struct config_param *config;
509a2671 2579 XENA_dev_config_t __iomem *bar0 = nic->bar0;
863c11a9 2580 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
20346722 2581 int i;
1da177e4 2582
7ba013ac 2583 atomic_inc(&nic->isr_cnt);
1da177e4
LT		 2584 mac_control = &nic->mac_control;
2585 config = &nic->config;
2586
20346722
K		 2587 nic->pkts_to_process = *budget;
2588 if (nic->pkts_to_process > dev->quota)
2589 nic->pkts_to_process = dev->quota;
2590 org_pkts_to_process = nic->pkts_to_process;
1da177e4 2591
1da177e4 2592 writeq(val64, &bar0->rx_traffic_int);
863c11a9 2593 val64 = readl(&bar0->rx_traffic_int);
1da177e4
LT		 2594
2595 for (i = 0; i < config->rx_ring_num; i++) {
20346722
K		 2596 rx_intr_handler(&mac_control->rings[i]);
2597 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2598 if (!nic->pkts_to_process) {
2599 /* Quota for the current iteration has been met */
2600 goto no_rx;
1da177e4 2601 }
1da177e4
LT		 2602 }
2603 if (!pkt_cnt)
2604 pkt_cnt = 1;
2605
2606 dev->quota -= pkt_cnt;
2607 *budget -= pkt_cnt;
2608 netif_rx_complete(dev);
2609
2610 for (i = 0; i < config->rx_ring_num; i++) {
2611 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2612 DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2613 DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2614 break;
2615 }
2616 }
2617 /* Re enable the Rx interrupts. */
c92ca04b
AR		 2618 writeq(0x0, &bar0->rx_traffic_mask);
2619 val64 = readl(&bar0->rx_traffic_mask);
7ba013ac 2620 atomic_dec(&nic->isr_cnt);
1da177e4
LT		 2621 return 0;
2622
20346722 2623no_rx:
1da177e4
LT		 2624 dev->quota -= pkt_cnt;
2625 *budget -= pkt_cnt;
2626
2627 for (i = 0; i < config->rx_ring_num; i++) {
2628 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2629 DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2630 DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2631 break;
2632 }
2633 }
7ba013ac 2634 atomic_dec(&nic->isr_cnt);
1da177e4
LT		 2635 return 1;
2636}
20346722 2637
b41477f3 2638#ifdef CONFIG_NET_POLL_CONTROLLER
612eff0e 2639/**
b41477f3 2640 * s2io_netpoll - netpoll event handler entry point
612eff0e
BH		 2641 * @dev : pointer to the device structure.
2642 * Description:
b41477f3
AR		 2643 * This function will be called by upper layer to check for events on the
2644 * interface in situations where interrupts are disabled. It is used for
2645 * specific in-kernel networking tasks, such as remote consoles and kernel
2646 * debugging over the network (example netdump in RedHat).
612eff0e 2647 */
612eff0e
BH		 2648static void s2io_netpoll(struct net_device *dev)
2649{
2650 nic_t *nic = dev->priv;
2651 mac_info_t *mac_control;
2652 struct config_param *config;
2653 XENA_dev_config_t __iomem *bar0 = nic->bar0;
b41477f3 2654 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
612eff0e
BH		 2655 int i;
2656
2657 disable_irq(dev->irq);
2658
2659 atomic_inc(&nic->isr_cnt);
2660 mac_control = &nic->mac_control;
2661 config = &nic->config;
2662
612eff0e 2663 writeq(val64, &bar0->rx_traffic_int);
b41477f3
AR		 2664 writeq(val64, &bar0->tx_traffic_int);
2665
6aa20a22 2666 /* we need to free up the transmitted skbufs or else netpoll will
b41477f3
AR		 2667 * run out of skbs and will fail and eventually netpoll application such
2668 * as netdump will fail.
2669 */
2670 for (i = 0; i < config->tx_fifo_num; i++)
2671 tx_intr_handler(&mac_control->fifos[i]);
612eff0e 2672
b41477f3 2673 /* check for received packet and indicate up to network */
612eff0e
BH		 2674 for (i = 0; i < config->rx_ring_num; i++)
2675 rx_intr_handler(&mac_control->rings[i]);
2676
2677 for (i = 0; i < config->rx_ring_num; i++) {
2678 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2679 DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2680 DBG_PRINT(ERR_DBG, " in Rx Netpoll!!\n");
2681 break;
2682 }
2683 }
2684 atomic_dec(&nic->isr_cnt);
2685 enable_irq(dev->irq);
2686 return;
2687}
2688#endif
2689
20346722 2690/**
1da177e4
LT		 2691 * rx_intr_handler - Rx interrupt handler
2692 * @nic: device private variable.
20346722
K		 2693 * Description:
2694 * If the interrupt is because of a received frame or if the
1da177e4 2695 * receive ring contains fresh as yet un-processed frames,this function is
20346722
K		 2696 * called. It picks out the RxD at which place the last Rx processing had
2697 * stopped and sends the skb to the OSM's Rx handler and then increments
1da177e4
LT		 2698 * the offset.
2699 * Return Value:
2700 * NONE.
2701 */
20346722 2702static void rx_intr_handler(ring_info_t *ring_data)
1da177e4 2703{
20346722 2704 nic_t *nic = ring_data->nic;
1da177e4 2705 struct net_device *dev = (struct net_device *) nic->dev;
da6971d8 2706 int get_block, put_block, put_offset;
1da177e4
LT		 2707 rx_curr_get_info_t get_info, put_info;
2708 RxD_t *rxdp;
2709 struct sk_buff *skb;
20346722 2710 int pkt_cnt = 0;
7d3d0439
RA		 2711 int i;
2712
7ba013ac
K		 2713 spin_lock(&nic->rx_lock);
2714 if (atomic_read(&nic->card_state) == CARD_DOWN) {
776bd20f 2715 DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
7ba013ac
K		 2716 __FUNCTION__, dev->name);
2717 spin_unlock(&nic->rx_lock);
776bd20f 2718 return;
7ba013ac
K		 2719 }
2720
20346722
K		 2721 get_info = ring_data->rx_curr_get_info;
2722 get_block = get_info.block_index;
2723 put_info = ring_data->rx_curr_put_info;
2724 put_block = put_info.block_index;
da6971d8 2725 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
db874e65
SS		 2726 if (!napi) {
2727 spin_lock(&nic->put_lock);
2728 put_offset = ring_data->put_pos;
2729 spin_unlock(&nic->put_lock);
2730 } else
2731 put_offset = ring_data->put_pos;
2732
da6971d8 2733 while (RXD_IS_UP2DT(rxdp)) {
db874e65
SS		 2734 /*
2735 * If your are next to put index then it's
2736 * FIFO full condition
2737 */
da6971d8
AR		 2738 if ((get_block == put_block) &&
2739 (get_info.offset + 1) == put_info.offset) {
75c30b13 2740 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
da6971d8
AR		 2741 break;
2742 }
20346722
K		 2743 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2744 if (skb == NULL) {
2745 DBG_PRINT(ERR_DBG, "%s: The skb is ",
2746 dev->name);
2747 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
7ba013ac 2748 spin_unlock(&nic->rx_lock);
20346722 2749 return;
1da177e4 2750 }
da6971d8
AR		 2751 if (nic->rxd_mode == RXD_MODE_1) {
2752 pci_unmap_single(nic->pdev, (dma_addr_t)
2753 ((RxD1_t*)rxdp)->Buffer0_ptr,
20346722
K		 2754 dev->mtu +
2755 HEADER_ETHERNET_II_802_3_SIZE +
2756 HEADER_802_2_SIZE +
2757 HEADER_SNAP_SIZE,
2758 PCI_DMA_FROMDEVICE);
da6971d8 2759 } else if (nic->rxd_mode == RXD_MODE_3B) {
75c30b13 2760 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
da6971d8 2761 ((RxD3_t*)rxdp)->Buffer0_ptr,
20346722 2762 BUF0_LEN, PCI_DMA_FROMDEVICE);
da6971d8
AR		 2763 pci_unmap_single(nic->pdev, (dma_addr_t)
2764 ((RxD3_t*)rxdp)->Buffer2_ptr,
2765 dev->mtu + 4,
20346722 2766 PCI_DMA_FROMDEVICE);
da6971d8 2767 } else {
75c30b13 2768 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
da6971d8
AR		 2769 ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2770 PCI_DMA_FROMDEVICE);
2771 pci_unmap_single(nic->pdev, (dma_addr_t)
2772 ((RxD3_t*)rxdp)->Buffer1_ptr,
2773 l3l4hdr_size + 4,
2774 PCI_DMA_FROMDEVICE);
2775 pci_unmap_single(nic->pdev, (dma_addr_t)
2776 ((RxD3_t*)rxdp)->Buffer2_ptr,
2777 dev->mtu, PCI_DMA_FROMDEVICE);
2778 }
863c11a9 2779 prefetch(skb->data);
20346722
K		 2780 rx_osm_handler(ring_data, rxdp);
2781 get_info.offset++;
da6971d8
AR		 2782 ring_data->rx_curr_get_info.offset = get_info.offset;
2783 rxdp = ring_data->rx_blocks[get_block].
2784 rxds[get_info.offset].virt_addr;
2785 if (get_info.offset == rxd_count[nic->rxd_mode]) {
20346722 2786 get_info.offset = 0;
da6971d8 2787 ring_data->rx_curr_get_info.offset = get_info.offset;
20346722 2788 get_block++;
da6971d8
AR		 2789 if (get_block == ring_data->block_count)
2790 get_block = 0;
2791 ring_data->rx_curr_get_info.block_index = get_block;
20346722
K		 2792 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2793 }
1da177e4 2794
20346722 2795 nic->pkts_to_process -= 1;
db874e65 2796 if ((napi) && (!nic->pkts_to_process))
20346722 2797 break;
20346722 2798 pkt_cnt++;
1da177e4
LT		 2799 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2800 break;
2801 }
7d3d0439
RA		 2802 if (nic->lro) {
2803 /* Clear all LRO sessions before exiting */
2804 for (i=0; i<MAX_LRO_SESSIONS; i++) {
2805 lro_t *lro = &nic->lro0_n[i];
2806 if (lro->in_use) {
2807 update_L3L4_header(nic, lro);
2808 queue_rx_frame(lro->parent);
2809 clear_lro_session(lro);
2810 }
2811 }
2812 }
2813
7ba013ac 2814 spin_unlock(&nic->rx_lock);
1da177e4 2815}
20346722
K		 2816
2817/**
1da177e4
LT		 2818 * tx_intr_handler - Transmit interrupt handler
2819 * @nic : device private variable
20346722
K		 2820 * Description:
2821 * If an interrupt was raised to indicate DMA complete of the
2822 * Tx packet, this function is called. It identifies the last TxD
2823 * whose buffer was freed and frees all skbs whose data have already
1da177e4
LT		 2824 * DMA'ed into the NICs internal memory.
2825 * Return Value:
2826 * NONE
2827 */
2828
20346722 2829static void tx_intr_handler(fifo_info_t *fifo_data)
1da177e4 2830{
20346722 2831 nic_t *nic = fifo_data->nic;
1da177e4
LT		 2832 struct net_device *dev = (struct net_device *) nic->dev;
2833 tx_curr_get_info_t get_info, put_info;
2834 struct sk_buff *skb;
2835 TxD_t *txdlp;
1da177e4 2836
20346722
K		 2837 get_info = fifo_data->tx_curr_get_info;
2838 put_info = fifo_data->tx_curr_put_info;
2839 txdlp = (TxD_t *) fifo_data->list_info[get_info.offset].
2840 list_virt_addr;
2841 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2842 (get_info.offset != put_info.offset) &&
2843 (txdlp->Host_Control)) {
2844 /* Check for TxD errors */
2845 if (txdlp->Control_1 & TXD_T_CODE) {
2846 unsigned long long err;
2847 err = txdlp->Control_1 & TXD_T_CODE;
bd1034f0
AR		 2848 if (err & 0x1) {
2849 nic->mac_control.stats_info->sw_stat.
2850 parity_err_cnt++;
2851 }
776bd20f 2852 if ((err >> 48) == 0xA) {
2853 DBG_PRINT(TX_DBG, "TxD returned due \
cc6e7c44 2854to loss of link\n");
776bd20f 2855 }
2856 else {
2857 DBG_PRINT(ERR_DBG, "***TxD error \
cc6e7c44 2858%llx\n", err);
776bd20f 2859 }
20346722 2860 }
1da177e4 2861
fed5eccd 2862 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
20346722
K		 2863 if (skb == NULL) {
2864 DBG_PRINT(ERR_DBG, "%s: Null skb ",
2865 __FUNCTION__);
2866 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2867 return;
2868 }
2869
20346722 2870 /* Updating the statistics block */
20346722
K		 2871 nic->stats.tx_bytes += skb->len;
2872 dev_kfree_skb_irq(skb);
2873
2874 get_info.offset++;
863c11a9
AR		 2875 if (get_info.offset == get_info.fifo_len + 1)
2876 get_info.offset = 0;
20346722
K		 2877 txdlp = (TxD_t *) fifo_data->list_info
2878 [get_info.offset].list_virt_addr;
2879 fifo_data->tx_curr_get_info.offset =
2880 get_info.offset;
1da177e4
LT		 2881 }
2882
2883 spin_lock(&nic->tx_lock);
2884 if (netif_queue_stopped(dev))
2885 netif_wake_queue(dev);
2886 spin_unlock(&nic->tx_lock);
2887}
2888
bd1034f0
AR		 2889/**
2890 * s2io_mdio_write - Function to write in to MDIO registers
2891 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2892 * @addr : address value
2893 * @value : data value
2894 * @dev : pointer to net_device structure
2895 * Description:
2896 * This function is used to write values to the MDIO registers
2897 * NONE
2898 */
2899static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
2900{
2901 u64 val64 = 0x0;
2902 nic_t *sp = dev->priv;
cc3afe6f 2903 XENA_dev_config_t __iomem *bar0 = sp->bar0;
bd1034f0
AR		 2904
2905 //address transaction
2906 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2907 | MDIO_MMD_DEV_ADDR(mmd_type)
2908 | MDIO_MMS_PRT_ADDR(0x0);
2909 writeq(val64, &bar0->mdio_control);
2910 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2911 writeq(val64, &bar0->mdio_control);
2912 udelay(100);
2913
2914 //Data transaction
2915 val64 = 0x0;
2916 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2917 | MDIO_MMD_DEV_ADDR(mmd_type)
2918 | MDIO_MMS_PRT_ADDR(0x0)
2919 | MDIO_MDIO_DATA(value)
2920 | MDIO_OP(MDIO_OP_WRITE_TRANS);
2921 writeq(val64, &bar0->mdio_control);
2922 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2923 writeq(val64, &bar0->mdio_control);
2924 udelay(100);
2925
2926 val64 = 0x0;
2927 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2928 | MDIO_MMD_DEV_ADDR(mmd_type)
2929 | MDIO_MMS_PRT_ADDR(0x0)
2930 | MDIO_OP(MDIO_OP_READ_TRANS);
2931 writeq(val64, &bar0->mdio_control);
2932 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2933 writeq(val64, &bar0->mdio_control);
2934 udelay(100);
2935
2936}
2937
2938/**
2939 * s2io_mdio_read - Function to write in to MDIO registers
2940 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2941 * @addr : address value
2942 * @dev : pointer to net_device structure
2943 * Description:
2944 * This function is used to read values to the MDIO registers
2945 * NONE
2946 */
2947static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
2948{
2949 u64 val64 = 0x0;
2950 u64 rval64 = 0x0;
2951 nic_t *sp = dev->priv;
cc3afe6f 2952 XENA_dev_config_t __iomem *bar0 = sp->bar0;
bd1034f0
AR		 2953
2954 /* address transaction */
2955 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2956 | MDIO_MMD_DEV_ADDR(mmd_type)
2957 | MDIO_MMS_PRT_ADDR(0x0);
2958 writeq(val64, &bar0->mdio_control);
2959 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2960 writeq(val64, &bar0->mdio_control);
2961 udelay(100);
2962
2963 /* Data transaction */
2964 val64 = 0x0;
2965 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2966 | MDIO_MMD_DEV_ADDR(mmd_type)
2967 | MDIO_MMS_PRT_ADDR(0x0)
2968 | MDIO_OP(MDIO_OP_READ_TRANS);
2969 writeq(val64, &bar0->mdio_control);
2970 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2971 writeq(val64, &bar0->mdio_control);
2972 udelay(100);
2973
2974 /* Read the value from regs */
2975 rval64 = readq(&bar0->mdio_control);
2976 rval64 = rval64 & 0xFFFF0000;
2977 rval64 = rval64 >> 16;
2978 return rval64;
2979}
2980/**
2981 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
2982 * @counter : couter value to be updated
2983 * @flag : flag to indicate the status
2984 * @type : counter type
2985 * Description:
2986 * This function is to check the status of the xpak counters value
2987 * NONE
2988 */
2989
2990static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
2991{
2992 u64 mask = 0x3;
2993 u64 val64;
2994 int i;
2995 for(i = 0; i <index; i++)
2996 mask = mask << 0x2;
2997
2998 if(flag > 0)
2999 {
3000 *counter = *counter + 1;
3001 val64 = *regs_stat & mask;
3002 val64 = val64 >> (index * 0x2);
3003 val64 = val64 + 1;
3004 if(val64 == 3)
3005 {
3006 switch(type)
3007 {
3008 case 1:
3009 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3010 "service. Excessive temperatures may "
3011 "result in premature transceiver "
3012 "failure \n");
3013 break;
3014 case 2:
3015 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3016 "service Excessive bias currents may "
3017 "indicate imminent laser diode "
3018 "failure \n");
3019 break;
3020 case 3:
3021 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3022 "service Excessive laser output "
3023 "power may saturate far-end "
3024 "receiver\n");
3025 break;
3026 default:
3027 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3028 "type \n");
3029 }
3030 val64 = 0x0;
3031 }
3032 val64 = val64 << (index * 0x2);
3033 *regs_stat = (*regs_stat & (~mask)) | (val64);
3034
3035 } else {
3036 *regs_stat = *regs_stat & (~mask);
3037 }
3038}
3039
3040/**
3041 * s2io_updt_xpak_counter - Function to update the xpak counters
3042 * @dev : pointer to net_device struct
3043 * Description:
3044 * This function is to upate the status of the xpak counters value
3045 * NONE
3046 */
3047static void s2io_updt_xpak_counter(struct net_device *dev)
3048{
3049 u16 flag = 0x0;
3050 u16 type = 0x0;
3051 u16 val16 = 0x0;
3052 u64 val64 = 0x0;
3053 u64 addr = 0x0;
3054
3055 nic_t *sp = dev->priv;
3056 StatInfo_t *stat_info = sp->mac_control.stats_info;
3057
3058 /* Check the communication with the MDIO slave */
3059 addr = 0x0000;
3060 val64 = 0x0;
3061 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3062 if((val64 == 0xFFFF) || (val64 == 0x0000))
3063 {
3064 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3065 "Returned %llx\n", (unsigned long long)val64);
3066 return;
3067 }
3068
3069 /* Check for the expecte value of 2040 at PMA address 0x0000 */
3070 if(val64 != 0x2040)
3071 {
3072 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3073 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3074 (unsigned long long)val64);
3075 return;
3076 }
3077
3078 /* Loading the DOM register to MDIO register */
3079 addr = 0xA100;
3080 s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3081 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3082
3083 /* Reading the Alarm flags */
3084 addr = 0xA070;
3085 val64 = 0x0;
3086 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3087
3088 flag = CHECKBIT(val64, 0x7);
3089 type = 1;
3090 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3091 &stat_info->xpak_stat.xpak_regs_stat,
3092 0x0, flag, type);
3093
3094 if(CHECKBIT(val64, 0x6))
3095 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3096
3097 flag = CHECKBIT(val64, 0x3);
3098 type = 2;
3099 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3100 &stat_info->xpak_stat.xpak_regs_stat,
3101 0x2, flag, type);
3102
3103 if(CHECKBIT(val64, 0x2))
3104 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3105
3106 flag = CHECKBIT(val64, 0x1);
3107 type = 3;
3108 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3109 &stat_info->xpak_stat.xpak_regs_stat,
3110 0x4, flag, type);
3111
3112 if(CHECKBIT(val64, 0x0))
3113 stat_info->xpak_stat.alarm_laser_output_power_low++;
3114
3115 /* Reading the Warning flags */
3116 addr = 0xA074;
3117 val64 = 0x0;
3118 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3119
3120 if(CHECKBIT(val64, 0x7))
3121 stat_info->xpak_stat.warn_transceiver_temp_high++;
3122
3123 if(CHECKBIT(val64, 0x6))
3124 stat_info->xpak_stat.warn_transceiver_temp_low++;
3125
3126 if(CHECKBIT(val64, 0x3))
3127 stat_info->xpak_stat.warn_laser_bias_current_high++;
3128
3129 if(CHECKBIT(val64, 0x2))
3130 stat_info->xpak_stat.warn_laser_bias_current_low++;
3131
3132 if(CHECKBIT(val64, 0x1))
3133 stat_info->xpak_stat.warn_laser_output_power_high++;
3134
3135 if(CHECKBIT(val64, 0x0))
3136 stat_info->xpak_stat.warn_laser_output_power_low++;
3137}
3138
20346722 3139/**
1da177e4
LT		 3140 * alarm_intr_handler - Alarm Interrrupt handler
3141 * @nic: device private variable
20346722 3142 * Description: If the interrupt was neither because of Rx packet or Tx
1da177e4 3143 * complete, this function is called. If the interrupt was to indicate
20346722
K		 3144 * a loss of link, the OSM link status handler is invoked for any other
3145 * alarm interrupt the block that raised the interrupt is displayed
1da177e4
LT		 3146 * and a H/W reset is issued.
3147 * Return Value:
3148 * NONE
3149*/
3150
3151static void alarm_intr_handler(struct s2io_nic *nic)
3152{
3153 struct net_device *dev = (struct net_device *) nic->dev;
3154 XENA_dev_config_t __iomem *bar0 = nic->bar0;
3155 register u64 val64 = 0, err_reg = 0;
bd1034f0
AR		 3156 u64 cnt;
3157 int i;
3158 nic->mac_control.stats_info->sw_stat.ring_full_cnt = 0;
3159 /* Handling the XPAK counters update */
3160 if(nic->mac_control.stats_info->xpak_stat.xpak_timer_count < 72000) {
3161 /* waiting for an hour */
3162 nic->mac_control.stats_info->xpak_stat.xpak_timer_count++;
3163 } else {
3164 s2io_updt_xpak_counter(dev);
3165 /* reset the count to zero */
3166 nic->mac_control.stats_info->xpak_stat.xpak_timer_count = 0;
3167 }
1da177e4
LT		 3168
3169 /* Handling link status change error Intr */
a371a07d
K		 3170 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
3171 err_reg = readq(&bar0->mac_rmac_err_reg);
3172 writeq(err_reg, &bar0->mac_rmac_err_reg);
3173 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
3174 schedule_work(&nic->set_link_task);
3175 }
1da177e4
LT		 3176 }
3177
5e25b9dd
K		 3178 /* Handling Ecc errors */
3179 val64 = readq(&bar0->mc_err_reg);
3180 writeq(val64, &bar0->mc_err_reg);
3181 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
3182 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
7ba013ac
K		 3183 nic->mac_control.stats_info->sw_stat.
3184 double_ecc_errs++;
776bd20f 3185 DBG_PRINT(INIT_DBG, "%s: Device indicates ",
5e25b9dd 3186 dev->name);
776bd20f 3187 DBG_PRINT(INIT_DBG, "double ECC error!!\n");
e960fc5c 3188 if (nic->device_type != XFRAME_II_DEVICE) {
776bd20f 3189 /* Reset XframeI only if critical error */
3190 if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
3191 MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
3192 netif_stop_queue(dev);
3193 schedule_work(&nic->rst_timer_task);
bd1034f0
AR		 3194 nic->mac_control.stats_info->sw_stat.
3195 soft_reset_cnt++;
776bd20f 3196 }
e960fc5c 3197 }
5e25b9dd 3198 } else {
7ba013ac
K		 3199 nic->mac_control.stats_info->sw_stat.
3200 single_ecc_errs++;
5e25b9dd
K		 3201 }
3202 }
3203
1da177e4
LT		 3204 /* In case of a serious error, the device will be Reset. */
3205 val64 = readq(&bar0->serr_source);
3206 if (val64 & SERR_SOURCE_ANY) {
bd1034f0 3207 nic->mac_control.stats_info->sw_stat.serious_err_cnt++;
1da177e4 3208 DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
6aa20a22 3209 DBG_PRINT(ERR_DBG, "serious error %llx!!\n",
776bd20f 3210 (unsigned long long)val64);
1da177e4
LT		 3211 netif_stop_queue(dev);
3212 schedule_work(&nic->rst_timer_task);
bd1034f0 3213 nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
1da177e4
LT		 3214 }
3215
3216 /*
3217 * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
3218 * Error occurs, the adapter will be recycled by disabling the
20346722 3219 * adapter enable bit and enabling it again after the device
1da177e4
LT		 3220 * becomes Quiescent.
3221 */
3222 val64 = readq(&bar0->pcc_err_reg);
3223 writeq(val64, &bar0->pcc_err_reg);
3224 if (val64 & PCC_FB_ECC_DB_ERR) {
3225 u64 ac = readq(&bar0->adapter_control);
3226 ac &= ~(ADAPTER_CNTL_EN);
3227 writeq(ac, &bar0->adapter_control);
3228 ac = readq(&bar0->adapter_control);
3229 schedule_work(&nic->set_link_task);
3230 }
bd1034f0
AR		 3231 /* Check for data parity error */
3232 val64 = readq(&bar0->pic_int_status);
3233 if (val64 & PIC_INT_GPIO) {
3234 val64 = readq(&bar0->gpio_int_reg);
3235 if (val64 & GPIO_INT_REG_DP_ERR_INT) {
3236 nic->mac_control.stats_info->sw_stat.parity_err_cnt++;
3237 schedule_work(&nic->rst_timer_task);
3238 nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3239 }
3240 }
3241
3242 /* Check for ring full counter */
3243 if (nic->device_type & XFRAME_II_DEVICE) {
3244 val64 = readq(&bar0->ring_bump_counter1);
3245 for (i=0; i<4; i++) {
3246 cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3247 cnt >>= 64 - ((i+1)*16);
3248 nic->mac_control.stats_info->sw_stat.ring_full_cnt
3249 += cnt;
3250 }
3251
3252 val64 = readq(&bar0->ring_bump_counter2);
3253 for (i=0; i<4; i++) {
3254 cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3255 cnt >>= 64 - ((i+1)*16);
3256 nic->mac_control.stats_info->sw_stat.ring_full_cnt
3257 += cnt;
3258 }
3259 }
1da177e4
LT		 3260
3261 /* Other type of interrupts are not being handled now, TODO */
3262}
3263
20346722 3264/**
1da177e4 3265 * wait_for_cmd_complete - waits for a command to complete.
20346722 3266 * @sp : private member of the device structure, which is a pointer to the
1da177e4 3267 * s2io_nic structure.
20346722
K		 3268 * Description: Function that waits for a command to Write into RMAC
3269 * ADDR DATA registers to be completed and returns either success or
3270 * error depending on whether the command was complete or not.
1da177e4
LT		 3271 * Return value:
3272 * SUCCESS on success and FAILURE on failure.
3273 */
3274
cc3afe6f 3275static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit)
1da177e4 3276{
1da177e4
LT		 3277 int ret = FAILURE, cnt = 0;
3278 u64 val64;
3279
3280 while (TRUE) {
c92ca04b
AR		 3281 val64 = readq(addr);
3282 if (!(val64 & busy_bit)) {
1da177e4
LT		 3283 ret = SUCCESS;
3284 break;
3285 }
c92ca04b
AR		 3286
3287 if(in_interrupt())
3288 mdelay(50);
3289 else
3290 msleep(50);
3291
1da177e4
LT		 3292 if (cnt++ > 10)
3293 break;
3294 }
1da177e4
LT		 3295 return ret;
3296}
3297
20346722
K		 3298/**
3299 * s2io_reset - Resets the card.
1da177e4
LT		 3300 * @sp : private member of the device structure.
3301 * Description: Function to Reset the card. This function then also
20346722 3302 * restores the previously saved PCI configuration space registers as
1da177e4
LT		 3303 * the card reset also resets the configuration space.
3304 * Return value:
3305 * void.
3306 */
3307
26df54bf 3308static void s2io_reset(nic_t * sp)
1da177e4
LT		 3309{
3310 XENA_dev_config_t __iomem *bar0 = sp->bar0;
3311 u64 val64;
5e25b9dd 3312 u16 subid, pci_cmd;
1da177e4 3313
0b1f7ebe 3314 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
e960fc5c 3315 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
0b1f7ebe 3316
1da177e4
LT		 3317 val64 = SW_RESET_ALL;
3318 writeq(val64, &bar0->sw_reset);
3319
20346722
K		 3320 /*
3321 * At this stage, if the PCI write is indeed completed, the
3322 * card is reset and so is the PCI Config space of the device.
3323 * So a read cannot be issued at this stage on any of the
1da177e4
LT		 3324 * registers to ensure the write into "sw_reset" register
3325 * has gone through.
3326 * Question: Is there any system call that will explicitly force
3327 * all the write commands still pending on the bus to be pushed
3328 * through?
3329 * As of now I'am just giving a 250ms delay and hoping that the
3330 * PCI write to sw_reset register is done by this time.
3331 */
3332 msleep(250);
c92ca04b
AR		 3333 if (strstr(sp->product_name, "CX4")) {
3334 msleep(750);
3335 }
1da177e4 3336
e960fc5c 3337 /* Restore the PCI state saved during initialization. */
3338 pci_restore_state(sp->pdev);
3339 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
0b1f7ebe 3340 pci_cmd);
1da177e4
LT		 3341 s2io_init_pci(sp);
3342
3343 msleep(250);
3344
20346722
K		 3345 /* Set swapper to enable I/O register access */
3346 s2io_set_swapper(sp);
3347
cc6e7c44
RA		 3348 /* Restore the MSIX table entries from local variables */
3349 restore_xmsi_data(sp);
3350
5e25b9dd 3351 /* Clear certain PCI/PCI-X fields after reset */
303bcb4b 3352 if (sp->device_type == XFRAME_II_DEVICE) {
b41477f3 3353 /* Clear "detected parity error" bit */
303bcb4b 3354 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
5e25b9dd 3355
303bcb4b
K		 3356 /* Clearing PCIX Ecc status register */
3357 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
5e25b9dd 3358
303bcb4b
K		 3359 /* Clearing PCI_STATUS error reflected here */
3360 writeq(BIT(62), &bar0->txpic_int_reg);
3361 }
5e25b9dd 3362
20346722
K		 3363 /* Reset device statistics maintained by OS */
3364 memset(&sp->stats, 0, sizeof (struct net_device_stats));
3365
1da177e4
LT		 3366 /* SXE-002: Configure link and activity LED to turn it off */
3367 subid = sp->pdev->subsystem_device;
541ae68f
K		 3368 if (((subid & 0xFF) >= 0x07) &&
3369 (sp->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 3370 val64 = readq(&bar0->gpio_control);
3371 val64 |= 0x0000800000000000ULL;
3372 writeq(val64, &bar0->gpio_control);
3373 val64 = 0x0411040400000000ULL;
509a2671 3374 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 3375 }
3376
541ae68f
K		 3377 /*
3378 * Clear spurious ECC interrupts that would have occured on
3379 * XFRAME II cards after reset.
3380 */
3381 if (sp->device_type == XFRAME_II_DEVICE) {
3382 val64 = readq(&bar0->pcc_err_reg);
3383 writeq(val64, &bar0->pcc_err_reg);
3384 }
3385
1da177e4
LT		 3386 sp->device_enabled_once = FALSE;
3387}
3388
3389/**
20346722
K		 3390 * s2io_set_swapper - to set the swapper controle on the card
3391 * @sp : private member of the device structure,
1da177e4 3392 * pointer to the s2io_nic structure.
20346722 3393 * Description: Function to set the swapper control on the card
1da177e4
LT		 3394 * correctly depending on the 'endianness' of the system.
3395 * Return value:
3396 * SUCCESS on success and FAILURE on failure.
3397 */
3398
26df54bf 3399static int s2io_set_swapper(nic_t * sp)
1da177e4
LT		 3400{
3401 struct net_device *dev = sp->dev;
3402 XENA_dev_config_t __iomem *bar0 = sp->bar0;
3403 u64 val64, valt, valr;
3404
20346722 3405 /*
1da177e4
LT		 3406 * Set proper endian settings and verify the same by reading
3407 * the PIF Feed-back register.
3408 */
3409
3410 val64 = readq(&bar0->pif_rd_swapper_fb);
3411 if (val64 != 0x0123456789ABCDEFULL) {
3412 int i = 0;
3413 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3414 0x8100008181000081ULL, /* FE=1, SE=0 */
3415 0x4200004242000042ULL, /* FE=0, SE=1 */
3416 0}; /* FE=0, SE=0 */
3417
3418 while(i<4) {
3419 writeq(value[i], &bar0->swapper_ctrl);
3420 val64 = readq(&bar0->pif_rd_swapper_fb);
3421 if (val64 == 0x0123456789ABCDEFULL)
3422 break;
3423 i++;
3424 }
3425 if (i == 4) {
3426 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3427 dev->name);
3428 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3429 (unsigned long long) val64);
3430 return FAILURE;
3431 }
3432 valr = value[i];
3433 } else {
3434 valr = readq(&bar0->swapper_ctrl);
3435 }
3436
3437 valt = 0x0123456789ABCDEFULL;
3438 writeq(valt, &bar0->xmsi_address);
3439 val64 = readq(&bar0->xmsi_address);
3440
3441 if(val64 != valt) {
3442 int i = 0;
3443 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3444 0x0081810000818100ULL, /* FE=1, SE=0 */
3445 0x0042420000424200ULL, /* FE=0, SE=1 */
3446 0}; /* FE=0, SE=0 */
3447
3448 while(i<4) {
3449 writeq((value[i] | valr), &bar0->swapper_ctrl);
3450 writeq(valt, &bar0->xmsi_address);
3451 val64 = readq(&bar0->xmsi_address);
3452 if(val64 == valt)
3453 break;
3454 i++;
3455 }
3456 if(i == 4) {
20346722 3457 unsigned long long x = val64;
1da177e4 3458 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
20346722 3459 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
1da177e4
LT		 3460 return FAILURE;
3461 }
3462 }
3463 val64 = readq(&bar0->swapper_ctrl);
3464 val64 &= 0xFFFF000000000000ULL;
3465
3466#ifdef __BIG_ENDIAN
20346722
K		 3467 /*
3468 * The device by default set to a big endian format, so a
1da177e4
LT		 3469 * big endian driver need not set anything.
3470 */
3471 val64 |= (SWAPPER_CTRL_TXP_FE |
3472 SWAPPER_CTRL_TXP_SE |
3473 SWAPPER_CTRL_TXD_R_FE |
3474 SWAPPER_CTRL_TXD_W_FE |
3475 SWAPPER_CTRL_TXF_R_FE |
3476 SWAPPER_CTRL_RXD_R_FE |
3477 SWAPPER_CTRL_RXD_W_FE |
3478 SWAPPER_CTRL_RXF_W_FE |
3479 SWAPPER_CTRL_XMSI_FE |
1da177e4 3480 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
92383340 3481 if (sp->intr_type == INTA)
cc6e7c44 3482 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3483 writeq(val64, &bar0->swapper_ctrl);
3484#else
20346722 3485 /*
1da177e4 3486 * Initially we enable all bits to make it accessible by the
20346722 3487 * driver, then we selectively enable only those bits that
1da177e4
LT		 3488 * we want to set.
3489 */
3490 val64 |= (SWAPPER_CTRL_TXP_FE |
3491 SWAPPER_CTRL_TXP_SE |
3492 SWAPPER_CTRL_TXD_R_FE |
3493 SWAPPER_CTRL_TXD_R_SE |
3494 SWAPPER_CTRL_TXD_W_FE |
3495 SWAPPER_CTRL_TXD_W_SE |
3496 SWAPPER_CTRL_TXF_R_FE |
3497 SWAPPER_CTRL_RXD_R_FE |
3498 SWAPPER_CTRL_RXD_R_SE |
3499 SWAPPER_CTRL_RXD_W_FE |
3500 SWAPPER_CTRL_RXD_W_SE |
3501 SWAPPER_CTRL_RXF_W_FE |
3502 SWAPPER_CTRL_XMSI_FE |
1da177e4 3503 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
cc6e7c44
RA		 3504 if (sp->intr_type == INTA)
3505 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3506 writeq(val64, &bar0->swapper_ctrl);
3507#endif
3508 val64 = readq(&bar0->swapper_ctrl);
3509
20346722
K		 3510 /*
3511 * Verifying if endian settings are accurate by reading a
1da177e4
LT		 3512 * feedback register.
3513 */
3514 val64 = readq(&bar0->pif_rd_swapper_fb);
3515 if (val64 != 0x0123456789ABCDEFULL) {
3516 /* Endian settings are incorrect, calls for another dekko. */
3517 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3518 dev->name);
3519 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3520 (unsigned long long) val64);
3521 return FAILURE;
3522 }
3523
3524 return SUCCESS;
3525}
3526
ac1f60db 3527static int wait_for_msix_trans(nic_t *nic, int i)
cc6e7c44 3528{
37eb47ed 3529 XENA_dev_config_t __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3530 u64 val64;
3531 int ret = 0, cnt = 0;
3532
3533 do {
3534 val64 = readq(&bar0->xmsi_access);
3535 if (!(val64 & BIT(15)))
3536 break;
3537 mdelay(1);
3538 cnt++;
3539 } while(cnt < 5);
3540 if (cnt == 5) {
3541 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3542 ret = 1;
3543 }
3544
3545 return ret;
3546}
3547
26df54bf 3548static void restore_xmsi_data(nic_t *nic)
cc6e7c44 3549{
37eb47ed 3550 XENA_dev_config_t __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3551 u64 val64;
3552 int i;
3553
75c30b13 3554 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
cc6e7c44
RA		 3555 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3556 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3557 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
3558 writeq(val64, &bar0->xmsi_access);
3559 if (wait_for_msix_trans(nic, i)) {
3560 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3561 continue;
3562 }
3563 }
3564}
3565
ac1f60db 3566static void store_xmsi_data(nic_t *nic)
cc6e7c44 3567{
37eb47ed 3568 XENA_dev_config_t __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3569 u64 val64, addr, data;
3570 int i;
3571
3572 /* Store and display */
75c30b13 3573 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
cc6e7c44
RA		 3574 val64 = (BIT(15) | vBIT(i, 26, 6));
3575 writeq(val64, &bar0->xmsi_access);
3576 if (wait_for_msix_trans(nic, i)) {
3577 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3578 continue;
3579 }
3580 addr = readq(&bar0->xmsi_address);
3581 data = readq(&bar0->xmsi_data);
3582 if (addr && data) {
3583 nic->msix_info[i].addr = addr;
3584 nic->msix_info[i].data = data;
3585 }
3586 }
3587}
3588
3589int s2io_enable_msi(nic_t *nic)
3590{
37eb47ed 3591 XENA_dev_config_t __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3592 u16 msi_ctrl, msg_val;
3593 struct config_param *config = &nic->config;
3594 struct net_device *dev = nic->dev;
3595 u64 val64, tx_mat, rx_mat;
3596 int i, err;
3597
3598 val64 = readq(&bar0->pic_control);
3599 val64 &= ~BIT(1);
3600 writeq(val64, &bar0->pic_control);
3601
3602 err = pci_enable_msi(nic->pdev);
3603 if (err) {
3604 DBG_PRINT(ERR_DBG, "%s: enabling MSI failed\n",
3605 nic->dev->name);
3606 return err;
3607 }
3608
3609 /*
3610 * Enable MSI and use MSI-1 in stead of the standard MSI-0
3611 * for interrupt handling.
3612 */
3613 pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3614 msg_val ^= 0x1;
3615 pci_write_config_word(nic->pdev, 0x4c, msg_val);
3616 pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3617
3618 pci_read_config_word(nic->pdev, 0x42, &msi_ctrl);
3619 msi_ctrl |= 0x10;
3620 pci_write_config_word(nic->pdev, 0x42, msi_ctrl);
3621
3622 /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */
3623 tx_mat = readq(&bar0->tx_mat0_n[0]);
3624 for (i=0; i<config->tx_fifo_num; i++) {
3625 tx_mat |= TX_MAT_SET(i, 1);
3626 }
3627 writeq(tx_mat, &bar0->tx_mat0_n[0]);
3628
3629 rx_mat = readq(&bar0->rx_mat);
3630 for (i=0; i<config->rx_ring_num; i++) {
3631 rx_mat |= RX_MAT_SET(i, 1);
3632 }
3633 writeq(rx_mat, &bar0->rx_mat);
3634
3635 dev->irq = nic->pdev->irq;
3636 return 0;
3637}
3638
26df54bf 3639static int s2io_enable_msi_x(nic_t *nic)
cc6e7c44 3640{
37eb47ed 3641 XENA_dev_config_t __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3642 u64 tx_mat, rx_mat;
3643 u16 msi_control; /* Temp variable */
3644 int ret, i, j, msix_indx = 1;
3645
3646 nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry),
3647 GFP_KERNEL);
3648 if (nic->entries == NULL) {
3649 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3650 return -ENOMEM;
3651 }
3652 memset(nic->entries, 0, MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3653
3654 nic->s2io_entries =
3655 kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry),
3656 GFP_KERNEL);
3657 if (nic->s2io_entries == NULL) {
3658 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3659 kfree(nic->entries);
3660 return -ENOMEM;
3661 }
3662 memset(nic->s2io_entries, 0,
3663 MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3664
3665 for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3666 nic->entries[i].entry = i;
3667 nic->s2io_entries[i].entry = i;
3668 nic->s2io_entries[i].arg = NULL;
3669 nic->s2io_entries[i].in_use = 0;
3670 }
3671
3672 tx_mat = readq(&bar0->tx_mat0_n[0]);
3673 for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3674 tx_mat |= TX_MAT_SET(i, msix_indx);
3675 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3676 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3677 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3678 }
3679 writeq(tx_mat, &bar0->tx_mat0_n[0]);
3680
3681 if (!nic->config.bimodal) {
3682 rx_mat = readq(&bar0->rx_mat);
3683 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3684 rx_mat |= RX_MAT_SET(j, msix_indx);
3685 nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3686 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3687 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3688 }
3689 writeq(rx_mat, &bar0->rx_mat);
3690 } else {
3691 tx_mat = readq(&bar0->tx_mat0_n[7]);
3692 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3693 tx_mat |= TX_MAT_SET(i, msix_indx);
3694 nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3695 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3696 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3697 }
3698 writeq(tx_mat, &bar0->tx_mat0_n[7]);
3699 }
3700
c92ca04b 3701 nic->avail_msix_vectors = 0;
cc6e7c44 3702 ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
c92ca04b
AR		 3703 /* We fail init if error or we get less vectors than min required */
3704 if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3705 nic->avail_msix_vectors = ret;
3706 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3707 }
cc6e7c44
RA		 3708 if (ret) {
3709 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3710 kfree(nic->entries);
3711 kfree(nic->s2io_entries);
3712 nic->entries = NULL;
3713 nic->s2io_entries = NULL;
c92ca04b 3714 nic->avail_msix_vectors = 0;
cc6e7c44
RA		 3715 return -ENOMEM;
3716 }
c92ca04b
AR		 3717 if (!nic->avail_msix_vectors)
3718 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
cc6e7c44
RA		 3719
3720 /*
3721 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3722 * in the herc NIC. (Temp change, needs to be removed later)
3723 */
3724 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3725 msi_control |= 0x1; /* Enable MSI */
3726 pci_write_config_word(nic->pdev, 0x42, msi_control);
3727
3728 return 0;
3729}
3730
1da177e4
LT		 3731/* ********************************************************* *
3732 * Functions defined below concern the OS part of the driver *
3733 * ********************************************************* */
3734
20346722 3735/**
1da177e4
LT		 3736 * s2io_open - open entry point of the driver
3737 * @dev : pointer to the device structure.
3738 * Description:
3739 * This function is the open entry point of the driver. It mainly calls a
3740 * function to allocate Rx buffers and inserts them into the buffer
20346722 3741 * descriptors and then enables the Rx part of the NIC.
1da177e4
LT		 3742 * Return value:
3743 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3744 * file on failure.
3745 */
3746
ac1f60db 3747static int s2io_open(struct net_device *dev)
1da177e4
LT		 3748{
3749 nic_t *sp = dev->priv;
3750 int err = 0;
3751
20346722
K		 3752 /*
3753 * Make sure you have link off by default every time
1da177e4
LT		 3754 * Nic is initialized
3755 */
3756 netif_carrier_off(dev);
0b1f7ebe 3757 sp->last_link_state = 0;
1da177e4
LT		 3758
3759 /* Initialize H/W and enable interrupts */
c92ca04b
AR		 3760 err = s2io_card_up(sp);
3761 if (err) {
1da177e4
LT		 3762 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3763 dev->name);
e6a8fee2 3764 goto hw_init_failed;
1da177e4
LT		 3765 }
3766
3767 if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
3768 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
e6a8fee2 3769 s2io_card_down(sp);
20346722 3770 err = -ENODEV;
e6a8fee2 3771 goto hw_init_failed;
1da177e4
LT		 3772 }
3773
3774 netif_start_queue(dev);
3775 return 0;
20346722 3776
20346722 3777hw_init_failed:
cc6e7c44
RA		 3778 if (sp->intr_type == MSI_X) {
3779 if (sp->entries)
3780 kfree(sp->entries);
3781 if (sp->s2io_entries)
3782 kfree(sp->s2io_entries);
3783 }
20346722 3784 return err;
1da177e4
LT		 3785}
3786
3787/**
3788 * s2io_close -close entry point of the driver
3789 * @dev : device pointer.
3790 * Description:
3791 * This is the stop entry point of the driver. It needs to undo exactly
3792 * whatever was done by the open entry point,thus it's usually referred to
3793 * as the close function.Among other things this function mainly stops the
3794 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3795 * Return value:
3796 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3797 * file on failure.
3798 */
3799
ac1f60db 3800static int s2io_close(struct net_device *dev)
1da177e4
LT		 3801{
3802 nic_t *sp = dev->priv;
cc6e7c44 3803
1da177e4
LT		 3804 flush_scheduled_work();
3805 netif_stop_queue(dev);
3806 /* Reset card, kill tasklet and free Tx and Rx buffers. */
e6a8fee2 3807 s2io_card_down(sp);
cc6e7c44 3808
1da177e4
LT		 3809 sp->device_close_flag = TRUE; /* Device is shut down. */
3810 return 0;
3811}
3812
3813/**
3814 * s2io_xmit - Tx entry point of te driver
3815 * @skb : the socket buffer containing the Tx data.
3816 * @dev : device pointer.
3817 * Description :
3818 * This function is the Tx entry point of the driver. S2IO NIC supports
3819 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
3820 * NOTE: when device cant queue the pkt,just the trans_start variable will
3821 * not be upadted.
3822 * Return value:
3823 * 0 on success & 1 on failure.
3824 */
3825
ac1f60db 3826static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 3827{
3828 nic_t *sp = dev->priv;
3829 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3830 register u64 val64;
3831 TxD_t *txdp;
3832 TxFIFO_element_t __iomem *tx_fifo;
3833 unsigned long flags;
be3a6b02
K		 3834 u16 vlan_tag = 0;
3835 int vlan_priority = 0;
1da177e4
LT		 3836 mac_info_t *mac_control;
3837 struct config_param *config;
75c30b13 3838 int offload_type;
1da177e4
LT		 3839
3840 mac_control = &sp->mac_control;
3841 config = &sp->config;
3842
20346722 3843 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
1da177e4 3844 spin_lock_irqsave(&sp->tx_lock, flags);
1da177e4 3845 if (atomic_read(&sp->card_state) == CARD_DOWN) {
20346722 3846 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
1da177e4
LT		 3847 dev->name);
3848 spin_unlock_irqrestore(&sp->tx_lock, flags);
20346722
K		 3849 dev_kfree_skb(skb);
3850 return 0;
1da177e4
LT		 3851 }
3852
3853 queue = 0;
1da177e4 3854
be3a6b02
K		 3855 /* Get Fifo number to Transmit based on vlan priority */
3856 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3857 vlan_tag = vlan_tx_tag_get(skb);
3858 vlan_priority = vlan_tag >> 13;
3859 queue = config->fifo_mapping[vlan_priority];
3860 }
3861
20346722
K		 3862 put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
3863 get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
3864 txdp = (TxD_t *) mac_control->fifos[queue].list_info[put_off].
3865 list_virt_addr;
3866
3867 queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
1da177e4 3868 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9
AR		 3869 if (txdp->Host_Control ||
3870 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
776bd20f 3871 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
1da177e4
LT		 3872 netif_stop_queue(dev);
3873 dev_kfree_skb(skb);
3874 spin_unlock_irqrestore(&sp->tx_lock, flags);
3875 return 0;
3876 }
0b1f7ebe
K		 3877
3878 /* A buffer with no data will be dropped */
3879 if (!skb->len) {
3880 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
3881 dev_kfree_skb(skb);
3882 spin_unlock_irqrestore(&sp->tx_lock, flags);
3883 return 0;
3884 }
3885
75c30b13 3886 offload_type = s2io_offload_type(skb);
75c30b13 3887 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1da177e4 3888 txdp->Control_1 |= TXD_TCP_LSO_EN;
75c30b13 3889 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
1da177e4 3890 }
84fa7933 3891 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 3892 txdp->Control_2 |=
3893 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
3894 TXD_TX_CKO_UDP_EN);
3895 }
fed5eccd
AR		 3896 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
3897 txdp->Control_1 |= TXD_LIST_OWN_XENA;
1da177e4 3898 txdp->Control_2 |= config->tx_intr_type;
d8892c6e 3899
be3a6b02
K		 3900 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3901 txdp->Control_2 |= TXD_VLAN_ENABLE;
3902 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
3903 }
3904
fed5eccd 3905 frg_len = skb->len - skb->data_len;
75c30b13 3906 if (offload_type == SKB_GSO_UDP) {
fed5eccd
AR		 3907 int ufo_size;
3908
75c30b13 3909 ufo_size = s2io_udp_mss(skb);
fed5eccd
AR		 3910 ufo_size &= ~7;
3911 txdp->Control_1 |= TXD_UFO_EN;
3912 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
3913 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
3914#ifdef __BIG_ENDIAN
3915 sp->ufo_in_band_v[put_off] =
3916 (u64)skb_shinfo(skb)->ip6_frag_id;
3917#else
3918 sp->ufo_in_band_v[put_off] =
3919 (u64)skb_shinfo(skb)->ip6_frag_id << 32;
3920#endif
3921 txdp->Host_Control = (unsigned long)sp->ufo_in_band_v;
3922 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
3923 sp->ufo_in_band_v,
3924 sizeof(u64), PCI_DMA_TODEVICE);
3925 txdp++;
fed5eccd 3926 }
1da177e4 3927
fed5eccd
AR		 3928 txdp->Buffer_Pointer = pci_map_single
3929 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
3930 txdp->Host_Control = (unsigned long) skb;
3931 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
75c30b13 3932 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 3933 txdp->Control_1 |= TXD_UFO_EN;
3934
3935 frg_cnt = skb_shinfo(skb)->nr_frags;
1da177e4
LT		 3936 /* For fragmented SKB. */
3937 for (i = 0; i < frg_cnt; i++) {
3938 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0b1f7ebe
K		 3939 /* A '0' length fragment will be ignored */
3940 if (!frag->size)
3941 continue;
1da177e4
LT		 3942 txdp++;
3943 txdp->Buffer_Pointer = (u64) pci_map_page
3944 (sp->pdev, frag->page, frag->page_offset,
3945 frag->size, PCI_DMA_TODEVICE);
efd51b5c 3946 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
75c30b13 3947 if (offload_type == SKB_GSO_UDP)
fed5eccd 3948 txdp->Control_1 |= TXD_UFO_EN;
1da177e4
LT		 3949 }
3950 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
3951
75c30b13 3952 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 3953 frg_cnt++; /* as Txd0 was used for inband header */
3954
1da177e4 3955 tx_fifo = mac_control->tx_FIFO_start[queue];
20346722 3956 val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
1da177e4
LT		 3957 writeq(val64, &tx_fifo->TxDL_Pointer);
3958
3959 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
3960 TX_FIFO_LAST_LIST);
75c30b13 3961 if (offload_type)
fed5eccd 3962 val64 |= TX_FIFO_SPECIAL_FUNC;
75c30b13 3963
1da177e4
LT		 3964 writeq(val64, &tx_fifo->List_Control);
3965
303bcb4b
K		 3966 mmiowb();
3967
1da177e4 3968 put_off++;
863c11a9
AR		 3969 if (put_off == mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1)
3970 put_off = 0;
20346722 3971 mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
1da177e4
LT		 3972
3973 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 3974 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
bd1034f0 3975 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
1da177e4
LT		 3976 DBG_PRINT(TX_DBG,
3977 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
3978 put_off, get_off);
3979 netif_stop_queue(dev);
3980 }
3981
3982 dev->trans_start = jiffies;
3983 spin_unlock_irqrestore(&sp->tx_lock, flags);
3984
3985 return 0;
3986}
3987
25fff88e
K		 3988static void
3989s2io_alarm_handle(unsigned long data)
3990{
3991 nic_t *sp = (nic_t *)data;
3992
3993 alarm_intr_handler(sp);
3994 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
3995}
3996
75c30b13
AR		 3997static int s2io_chk_rx_buffers(nic_t *sp, int rng_n)
3998{
3999 int rxb_size, level;
4000
4001 if (!sp->lro) {
4002 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
4003 level = rx_buffer_level(sp, rxb_size, rng_n);
4004
4005 if ((level == PANIC) && (!TASKLET_IN_USE)) {
4006 int ret;
4007 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
4008 DBG_PRINT(INTR_DBG, "PANIC levels\n");
4009 if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
4010 DBG_PRINT(ERR_DBG, "Out of memory in %s",
4011 __FUNCTION__);
4012 clear_bit(0, (&sp->tasklet_status));
4013 return -1;
4014 }
4015 clear_bit(0, (&sp->tasklet_status));
4016 } else if (level == LOW)
4017 tasklet_schedule(&sp->task);
4018
4019 } else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
4020 DBG_PRINT(ERR_DBG, "%s:Out of memory", sp->dev->name);
4021 DBG_PRINT(ERR_DBG, " in Rx Intr!!\n");
4022 }
4023 return 0;
4024}
4025
7d12e780 4026static irqreturn_t s2io_msi_handle(int irq, void *dev_id)
cc6e7c44
RA		 4027{
4028 struct net_device *dev = (struct net_device *) dev_id;
4029 nic_t *sp = dev->priv;
4030 int i;
cc6e7c44
RA		 4031 mac_info_t *mac_control;
4032 struct config_param *config;
4033
4034 atomic_inc(&sp->isr_cnt);
4035 mac_control = &sp->mac_control;
4036 config = &sp->config;
4037 DBG_PRINT(INTR_DBG, "%s: MSI handler\n", __FUNCTION__);
4038
4039 /* If Intr is because of Rx Traffic */
4040 for (i = 0; i < config->rx_ring_num; i++)
4041 rx_intr_handler(&mac_control->rings[i]);
4042
4043 /* If Intr is because of Tx Traffic */
4044 for (i = 0; i < config->tx_fifo_num; i++)
4045 tx_intr_handler(&mac_control->fifos[i]);
4046
4047 /*
4048 * If the Rx buffer count is below the panic threshold then
4049 * reallocate the buffers from the interrupt handler itself,
4050 * else schedule a tasklet to reallocate the buffers.
4051 */
75c30b13
AR		 4052 for (i = 0; i < config->rx_ring_num; i++)
4053 s2io_chk_rx_buffers(sp, i);
cc6e7c44
RA		 4054
4055 atomic_dec(&sp->isr_cnt);
4056 return IRQ_HANDLED;
4057}
4058
7d12e780 4059static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
cc6e7c44
RA		 4060{
4061 ring_info_t *ring = (ring_info_t *)dev_id;
4062 nic_t *sp = ring->nic;
cc6e7c44
RA		 4063
4064 atomic_inc(&sp->isr_cnt);
cc6e7c44 4065
75c30b13
AR		 4066 rx_intr_handler(ring);
4067 s2io_chk_rx_buffers(sp, ring->ring_no);
7d3d0439 4068
cc6e7c44 4069 atomic_dec(&sp->isr_cnt);
cc6e7c44
RA		 4070 return IRQ_HANDLED;
4071}
4072
7d12e780 4073static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
cc6e7c44
RA		 4074{
4075 fifo_info_t *fifo = (fifo_info_t *)dev_id;
4076 nic_t *sp = fifo->nic;
4077
4078 atomic_inc(&sp->isr_cnt);
4079 tx_intr_handler(fifo);
4080 atomic_dec(&sp->isr_cnt);
4081 return IRQ_HANDLED;
4082}
a371a07d
K		 4083static void s2io_txpic_intr_handle(nic_t *sp)
4084{
509a2671 4085 XENA_dev_config_t __iomem *bar0 = sp->bar0;
a371a07d
K		 4086 u64 val64;
4087
4088 val64 = readq(&bar0->pic_int_status);
4089 if (val64 & PIC_INT_GPIO) {
4090 val64 = readq(&bar0->gpio_int_reg);
4091 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4092 (val64 & GPIO_INT_REG_LINK_UP)) {
c92ca04b
AR		 4093 /*
4094 * This is unstable state so clear both up/down
4095 * interrupt and adapter to re-evaluate the link state.
4096 */
a371a07d
K		 4097 val64 |= GPIO_INT_REG_LINK_DOWN;
4098 val64 |= GPIO_INT_REG_LINK_UP;
4099 writeq(val64, &bar0->gpio_int_reg);
a371a07d 4100 val64 = readq(&bar0->gpio_int_mask);
c92ca04b
AR		 4101 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4102 GPIO_INT_MASK_LINK_DOWN);
a371a07d 4103 writeq(val64, &bar0->gpio_int_mask);
a371a07d 4104 }
c92ca04b
AR		 4105 else if (val64 & GPIO_INT_REG_LINK_UP) {
4106 val64 = readq(&bar0->adapter_status);
4107 if (verify_xena_quiescence(sp, val64,
4108 sp->device_enabled_once)) {
4109 /* Enable Adapter */
4110 val64 = readq(&bar0->adapter_control);
4111 val64 |= ADAPTER_CNTL_EN;
4112 writeq(val64, &bar0->adapter_control);
4113 val64 |= ADAPTER_LED_ON;
4114 writeq(val64, &bar0->adapter_control);
4115 if (!sp->device_enabled_once)
4116 sp->device_enabled_once = 1;
4117
4118 s2io_link(sp, LINK_UP);
4119 /*
4120 * unmask link down interrupt and mask link-up
4121 * intr
4122 */
4123 val64 = readq(&bar0->gpio_int_mask);
4124 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4125 val64 |= GPIO_INT_MASK_LINK_UP;
4126 writeq(val64, &bar0->gpio_int_mask);
4127
4128 }
4129 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4130 val64 = readq(&bar0->adapter_status);
4131 if (verify_xena_quiescence(sp, val64,
4132 sp->device_enabled_once)) {
4133 s2io_link(sp, LINK_DOWN);
4134 /* Link is down so unmaks link up interrupt */
4135 val64 = readq(&bar0->gpio_int_mask);
4136 val64 &= ~GPIO_INT_MASK_LINK_UP;
4137 val64 |= GPIO_INT_MASK_LINK_DOWN;
4138 writeq(val64, &bar0->gpio_int_mask);
4139 }
a371a07d
K		 4140 }
4141 }
c92ca04b 4142 val64 = readq(&bar0->gpio_int_mask);
a371a07d
K		 4143}
4144
1da177e4
LT		 4145/**
4146 * s2io_isr - ISR handler of the device .
4147 * @irq: the irq of the device.
4148 * @dev_id: a void pointer to the dev structure of the NIC.
20346722
K		 4149 * Description: This function is the ISR handler of the device. It
4150 * identifies the reason for the interrupt and calls the relevant
4151 * service routines. As a contongency measure, this ISR allocates the
1da177e4
LT		 4152 * recv buffers, if their numbers are below the panic value which is
4153 * presently set to 25% of the original number of rcv buffers allocated.
4154 * Return value:
20346722 4155 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
1da177e4
LT		 4156 * IRQ_NONE: will be returned if interrupt is not from our device
4157 */
7d12e780 4158static irqreturn_t s2io_isr(int irq, void *dev_id)
1da177e4
LT		 4159{
4160 struct net_device *dev = (struct net_device *) dev_id;
4161 nic_t *sp = dev->priv;
4162 XENA_dev_config_t __iomem *bar0 = sp->bar0;
20346722 4163 int i;
5d3213cc 4164 u64 reason = 0, val64, org_mask;
1da177e4
LT		 4165 mac_info_t *mac_control;
4166 struct config_param *config;
4167
7ba013ac 4168 atomic_inc(&sp->isr_cnt);
1da177e4
LT		 4169 mac_control = &sp->mac_control;
4170 config = &sp->config;
4171
20346722 4172 /*
1da177e4
LT		 4173 * Identify the cause for interrupt and call the appropriate
4174 * interrupt handler. Causes for the interrupt could be;
4175 * 1. Rx of packet.
4176 * 2. Tx complete.
4177 * 3. Link down.
20346722 4178 * 4. Error in any functional blocks of the NIC.
1da177e4
LT		 4179 */
4180 reason = readq(&bar0->general_int_status);
4181
4182 if (!reason) {
4183 /* The interrupt was not raised by Xena. */
7ba013ac 4184 atomic_dec(&sp->isr_cnt);
1da177e4
LT		 4185 return IRQ_NONE;
4186 }
4187
863c11a9 4188 val64 = 0xFFFFFFFFFFFFFFFFULL;
5d3213cc
AR		 4189 /* Store current mask before masking all interrupts */
4190 org_mask = readq(&bar0->general_int_mask);
4191 writeq(val64, &bar0->general_int_mask);
4192
db874e65
SS		 4193 if (napi) {
4194 if (reason & GEN_INTR_RXTRAFFIC) {
4195 if (netif_rx_schedule_prep(dev)) {
4196 writeq(val64, &bar0->rx_traffic_mask);
4197 __netif_rx_schedule(dev);
4198 }
4199 }
4200 } else {
4201 /*
4202 * Rx handler is called by default, without checking for the
4203 * cause of interrupt.
4204 * rx_traffic_int reg is an R1 register, writing all 1's
4205 * will ensure that the actual interrupt causing bit get's
4206 * cleared and hence a read can be avoided.
4207 */
4208 writeq(val64, &bar0->rx_traffic_int);
4209 for (i = 0; i < config->rx_ring_num; i++) {
4210 rx_intr_handler(&mac_control->rings[i]);
1da177e4
LT		 4211 }
4212 }
1da177e4 4213
863c11a9
AR		 4214 /*
4215 * tx_traffic_int reg is an R1 register, writing all 1's
4216 * will ensure that the actual interrupt causing bit get's
4217 * cleared and hence a read can be avoided.
4218 */
4219 writeq(val64, &bar0->tx_traffic_int);
fe113638 4220
863c11a9
AR		 4221 for (i = 0; i < config->tx_fifo_num; i++)
4222 tx_intr_handler(&mac_control->fifos[i]);
20346722 4223
a371a07d
K		 4224 if (reason & GEN_INTR_TXPIC)
4225 s2io_txpic_intr_handle(sp);
20346722
K		 4226 /*
4227 * If the Rx buffer count is below the panic threshold then
4228 * reallocate the buffers from the interrupt handler itself,
1da177e4
LT		 4229 * else schedule a tasklet to reallocate the buffers.
4230 */
db874e65
SS		 4231 if (!napi) {
4232 for (i = 0; i < config->rx_ring_num; i++)
4233 s2io_chk_rx_buffers(sp, i);
4234 }
4235
4236 writeq(0, &bar0->general_int_mask);
4237 readl(&bar0->general_int_status);
4238
7ba013ac 4239 atomic_dec(&sp->isr_cnt);
1da177e4
LT		 4240 return IRQ_HANDLED;
4241}
4242
7ba013ac
K		 4243/**
4244 * s2io_updt_stats -
4245 */
4246static void s2io_updt_stats(nic_t *sp)
4247{
4248 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4249 u64 val64;
4250 int cnt = 0;
4251
4252 if (atomic_read(&sp->card_state) == CARD_UP) {
4253 /* Apprx 30us on a 133 MHz bus */
4254 val64 = SET_UPDT_CLICKS(10) |
4255 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4256 writeq(val64, &bar0->stat_cfg);
4257 do {
4258 udelay(100);
4259 val64 = readq(&bar0->stat_cfg);
4260 if (!(val64 & BIT(0)))
4261 break;
4262 cnt++;
4263 if (cnt == 5)
4264 break; /* Updt failed */
4265 } while(1);
75c30b13
AR		 4266 } else {
4267 memset(sp->mac_control.stats_info, 0, sizeof(StatInfo_t));
7ba013ac
K		 4268 }
4269}
4270
1da177e4 4271/**
20346722 4272 * s2io_get_stats - Updates the device statistics structure.
1da177e4
LT		 4273 * @dev : pointer to the device structure.
4274 * Description:
20346722 4275 * This function updates the device statistics structure in the s2io_nic
1da177e4
LT		 4276 * structure and returns a pointer to the same.
4277 * Return value:
4278 * pointer to the updated net_device_stats structure.
4279 */
4280
ac1f60db 4281static struct net_device_stats *s2io_get_stats(struct net_device *dev)
1da177e4
LT		 4282{
4283 nic_t *sp = dev->priv;
4284 mac_info_t *mac_control;
4285 struct config_param *config;
4286
20346722 4287
1da177e4
LT		 4288 mac_control = &sp->mac_control;
4289 config = &sp->config;
4290
7ba013ac
K		 4291 /* Configure Stats for immediate updt */
4292 s2io_updt_stats(sp);
4293
4294 sp->stats.tx_packets =
4295 le32_to_cpu(mac_control->stats_info->tmac_frms);
20346722
K		 4296 sp->stats.tx_errors =
4297 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4298 sp->stats.rx_errors =
ee705dba 4299 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
20346722
K		 4300 sp->stats.multicast =
4301 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
1da177e4 4302 sp->stats.rx_length_errors =
ee705dba 4303 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
1da177e4
LT		 4304
4305 return (&sp->stats);
4306}
4307
4308/**
4309 * s2io_set_multicast - entry point for multicast address enable/disable.
4310 * @dev : pointer to the device structure
4311 * Description:
20346722
K		 4312 * This function is a driver entry point which gets called by the kernel
4313 * whenever multicast addresses must be enabled/disabled. This also gets
1da177e4
LT		 4314 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4315 * determine, if multicast address must be enabled or if promiscuous mode
4316 * is to be disabled etc.
4317 * Return value:
4318 * void.
4319 */
4320
4321static void s2io_set_multicast(struct net_device *dev)
4322{
4323 int i, j, prev_cnt;
4324 struct dev_mc_list *mclist;
4325 nic_t *sp = dev->priv;
4326 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4327 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4328 0xfeffffffffffULL;
4329 u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
4330 void __iomem *add;
4331
4332 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4333 /* Enable all Multicast addresses */
4334 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4335 &bar0->rmac_addr_data0_mem);
4336 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4337 &bar0->rmac_addr_data1_mem);
4338 val64 = RMAC_ADDR_CMD_MEM_WE |
4339 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4340 RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
4341 writeq(val64, &bar0->rmac_addr_cmd_mem);
4342 /* Wait till command completes */
c92ca04b
AR		 4343 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4344 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
1da177e4
LT		 4345
4346 sp->m_cast_flg = 1;
4347 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
4348 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4349 /* Disable all Multicast addresses */
4350 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4351 &bar0->rmac_addr_data0_mem);
5e25b9dd
K		 4352 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4353 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4354 val64 = RMAC_ADDR_CMD_MEM_WE |
4355 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4356 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4357 writeq(val64, &bar0->rmac_addr_cmd_mem);
4358 /* Wait till command completes */
c92ca04b
AR		 4359 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4360 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
1da177e4
LT		 4361
4362 sp->m_cast_flg = 0;
4363 sp->all_multi_pos = 0;
4364 }
4365
4366 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4367 /* Put the NIC into promiscuous mode */
4368 add = &bar0->mac_cfg;
4369 val64 = readq(&bar0->mac_cfg);
4370 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4371
4372 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4373 writel((u32) val64, add);
4374 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4375 writel((u32) (val64 >> 32), (add + 4));
4376
4377 val64 = readq(&bar0->mac_cfg);
4378 sp->promisc_flg = 1;
776bd20f 4379 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
1da177e4
LT		 4380 dev->name);
4381 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4382 /* Remove the NIC from promiscuous mode */
4383 add = &bar0->mac_cfg;
4384 val64 = readq(&bar0->mac_cfg);
4385 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4386
4387 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4388 writel((u32) val64, add);
4389 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4390 writel((u32) (val64 >> 32), (add + 4));
4391
4392 val64 = readq(&bar0->mac_cfg);
4393 sp->promisc_flg = 0;
776bd20f 4394 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
1da177e4
LT		 4395 dev->name);
4396 }
4397
4398 /* Update individual M_CAST address list */
4399 if ((!sp->m_cast_flg) && dev->mc_count) {
4400 if (dev->mc_count >
4401 (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
4402 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4403 dev->name);
4404 DBG_PRINT(ERR_DBG, "can be added, please enable ");
4405 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4406 return;
4407 }
4408
4409 prev_cnt = sp->mc_addr_count;
4410 sp->mc_addr_count = dev->mc_count;
4411
4412 /* Clear out the previous list of Mc in the H/W. */
4413 for (i = 0; i < prev_cnt; i++) {
4414 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4415 &bar0->rmac_addr_data0_mem);
4416 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 4417 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4418 val64 = RMAC_ADDR_CMD_MEM_WE |
4419 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4420 RMAC_ADDR_CMD_MEM_OFFSET
4421 (MAC_MC_ADDR_START_OFFSET + i);
4422 writeq(val64, &bar0->rmac_addr_cmd_mem);
4423
4424 /* Wait for command completes */
c92ca04b
AR		 4425 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4426 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
1da177e4
LT		 4427 DBG_PRINT(ERR_DBG, "%s: Adding ",
4428 dev->name);
4429 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4430 return;
4431 }
4432 }
4433
4434 /* Create the new Rx filter list and update the same in H/W. */
4435 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4436 i++, mclist = mclist->next) {
4437 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4438 ETH_ALEN);
a7a80d5a 4439 mac_addr = 0;
1da177e4
LT		 4440 for (j = 0; j < ETH_ALEN; j++) {
4441 mac_addr |= mclist->dmi_addr[j];
4442 mac_addr <<= 8;
4443 }
4444 mac_addr >>= 8;
4445 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4446 &bar0->rmac_addr_data0_mem);
4447 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 4448 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4449 val64 = RMAC_ADDR_CMD_MEM_WE |
4450 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4451 RMAC_ADDR_CMD_MEM_OFFSET
4452 (i + MAC_MC_ADDR_START_OFFSET);
4453 writeq(val64, &bar0->rmac_addr_cmd_mem);
4454
4455 /* Wait for command completes */
c92ca04b
AR		 4456 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4457 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
1da177e4
LT		 4458 DBG_PRINT(ERR_DBG, "%s: Adding ",
4459 dev->name);
4460 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4461 return;
4462 }
4463 }
4464 }
4465}
4466
4467/**
20346722 4468 * s2io_set_mac_addr - Programs the Xframe mac address
1da177e4
LT		 4469 * @dev : pointer to the device structure.
4470 * @addr: a uchar pointer to the new mac address which is to be set.
20346722 4471 * Description : This procedure will program the Xframe to receive
1da177e4 4472 * frames with new Mac Address
20346722 4473 * Return value: SUCCESS on success and an appropriate (-)ve integer
1da177e4
LT		 4474 * as defined in errno.h file on failure.
4475 */
4476
26df54bf 4477static int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
1da177e4
LT		 4478{
4479 nic_t *sp = dev->priv;
4480 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4481 register u64 val64, mac_addr = 0;
4482 int i;
4483
20346722 4484 /*
1da177e4
LT		 4485 * Set the new MAC address as the new unicast filter and reflect this
4486 * change on the device address registered with the OS. It will be
20346722 4487 * at offset 0.
1da177e4
LT		 4488 */
4489 for (i = 0; i < ETH_ALEN; i++) {
4490 mac_addr <<= 8;
4491 mac_addr |= addr[i];
4492 }
4493
4494 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4495 &bar0->rmac_addr_data0_mem);
4496
4497 val64 =
4498 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4499 RMAC_ADDR_CMD_MEM_OFFSET(0);
4500 writeq(val64, &bar0->rmac_addr_cmd_mem);
4501 /* Wait till command completes */
c92ca04b
AR		 4502 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4503 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
1da177e4
LT		 4504 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
4505 return FAILURE;
4506 }
4507
4508 return SUCCESS;
4509}
4510
4511/**
20346722 4512 * s2io_ethtool_sset - Sets different link parameters.
1da177e4
LT		 4513 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
4514 * @info: pointer to the structure with parameters given by ethtool to set
4515 * link information.
4516 * Description:
20346722 4517 * The function sets different link parameters provided by the user onto
1da177e4
LT		 4518 * the NIC.
4519 * Return value:
4520 * 0 on success.
4521*/
4522
4523static int s2io_ethtool_sset(struct net_device *dev,
4524 struct ethtool_cmd *info)
4525{
4526 nic_t *sp = dev->priv;
4527 if ((info->autoneg == AUTONEG_ENABLE) ||
4528 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
4529 return -EINVAL;
4530 else {
4531 s2io_close(sp->dev);
4532 s2io_open(sp->dev);
4533 }
4534
4535 return 0;
4536}
4537
4538/**
20346722 4539 * s2io_ethtol_gset - Return link specific information.
1da177e4
LT		 4540 * @sp : private member of the device structure, pointer to the
4541 * s2io_nic structure.
4542 * @info : pointer to the structure with parameters given by ethtool
4543 * to return link information.
4544 * Description:
4545 * Returns link specific information like speed, duplex etc.. to ethtool.
4546 * Return value :
4547 * return 0 on success.
4548 */
4549
4550static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
4551{
4552 nic_t *sp = dev->priv;
4553 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4554 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4555 info->port = PORT_FIBRE;
4556 /* info->transceiver?? TODO */
4557
4558 if (netif_carrier_ok(sp->dev)) {
4559 info->speed = 10000;
4560 info->duplex = DUPLEX_FULL;
4561 } else {
4562 info->speed = -1;
4563 info->duplex = -1;
4564 }
4565
4566 info->autoneg = AUTONEG_DISABLE;
4567 return 0;
4568}
4569
4570/**
20346722
K		 4571 * s2io_ethtool_gdrvinfo - Returns driver specific information.
4572 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 4573 * s2io_nic structure.
4574 * @info : pointer to the structure with parameters given by ethtool to
4575 * return driver information.
4576 * Description:
4577 * Returns driver specefic information like name, version etc.. to ethtool.
4578 * Return value:
4579 * void
4580 */
4581
4582static void s2io_ethtool_gdrvinfo(struct net_device *dev,
4583 struct ethtool_drvinfo *info)
4584{
4585 nic_t *sp = dev->priv;
4586
dbc2309d
JL		 4587 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
4588 strncpy(info->version, s2io_driver_version, sizeof(info->version));
4589 strncpy(info->fw_version, "", sizeof(info->fw_version));
4590 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
1da177e4
LT		 4591 info->regdump_len = XENA_REG_SPACE;
4592 info->eedump_len = XENA_EEPROM_SPACE;
4593 info->testinfo_len = S2IO_TEST_LEN;
4594 info->n_stats = S2IO_STAT_LEN;
4595}
4596
4597/**
4598 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
20346722 4599 * @sp: private member of the device structure, which is a pointer to the
1da177e4 4600 * s2io_nic structure.
20346722 4601 * @regs : pointer to the structure with parameters given by ethtool for
1da177e4
LT		 4602 * dumping the registers.
4603 * @reg_space: The input argumnet into which all the registers are dumped.
4604 * Description:
4605 * Dumps the entire register space of xFrame NIC into the user given
4606 * buffer area.
4607 * Return value :
4608 * void .
4609*/
4610
4611static void s2io_ethtool_gregs(struct net_device *dev,
4612 struct ethtool_regs *regs, void *space)
4613{
4614 int i;
4615 u64 reg;
4616 u8 *reg_space = (u8 *) space;
4617 nic_t *sp = dev->priv;
4618
4619 regs->len = XENA_REG_SPACE;
4620 regs->version = sp->pdev->subsystem_device;
4621
4622 for (i = 0; i < regs->len; i += 8) {
4623 reg = readq(sp->bar0 + i);
4624 memcpy((reg_space + i), &reg, 8);
4625 }
4626}
4627
4628/**
4629 * s2io_phy_id - timer function that alternates adapter LED.
20346722 4630 * @data : address of the private member of the device structure, which
1da177e4 4631 * is a pointer to the s2io_nic structure, provided as an u32.
20346722
K		 4632 * Description: This is actually the timer function that alternates the
4633 * adapter LED bit of the adapter control bit to set/reset every time on
4634 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
1da177e4
LT		 4635 * once every second.
4636*/
4637static void s2io_phy_id(unsigned long data)
4638{
4639 nic_t *sp = (nic_t *) data;
4640 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4641 u64 val64 = 0;
4642 u16 subid;
4643
4644 subid = sp->pdev->subsystem_device;
541ae68f
K		 4645 if ((sp->device_type == XFRAME_II_DEVICE) ||
4646 ((subid & 0xFF) >= 0x07)) {
1da177e4
LT		 4647 val64 = readq(&bar0->gpio_control);
4648 val64 ^= GPIO_CTRL_GPIO_0;
4649 writeq(val64, &bar0->gpio_control);
4650 } else {
4651 val64 = readq(&bar0->adapter_control);
4652 val64 ^= ADAPTER_LED_ON;
4653 writeq(val64, &bar0->adapter_control);
4654 }
4655
4656 mod_timer(&sp->id_timer, jiffies + HZ / 2);
4657}
4658
4659/**
4660 * s2io_ethtool_idnic - To physically identify the nic on the system.
4661 * @sp : private member of the device structure, which is a pointer to the
4662 * s2io_nic structure.
20346722 4663 * @id : pointer to the structure with identification parameters given by
1da177e4
LT		 4664 * ethtool.
4665 * Description: Used to physically identify the NIC on the system.
20346722 4666 * The Link LED will blink for a time specified by the user for
1da177e4 4667 * identification.
20346722 4668 * NOTE: The Link has to be Up to be able to blink the LED. Hence
1da177e4
LT		 4669 * identification is possible only if it's link is up.
4670 * Return value:
4671 * int , returns 0 on success
4672 */
4673
4674static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
4675{
4676 u64 val64 = 0, last_gpio_ctrl_val;
4677 nic_t *sp = dev->priv;
4678 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4679 u16 subid;
4680
4681 subid = sp->pdev->subsystem_device;
4682 last_gpio_ctrl_val = readq(&bar0->gpio_control);
541ae68f
K		 4683 if ((sp->device_type == XFRAME_I_DEVICE) &&
4684 ((subid & 0xFF) < 0x07)) {
1da177e4
LT		 4685 val64 = readq(&bar0->adapter_control);
4686 if (!(val64 & ADAPTER_CNTL_EN)) {
4687 printk(KERN_ERR
4688 "Adapter Link down, cannot blink LED\n");
4689 return -EFAULT;
4690 }
4691 }
4692 if (sp->id_timer.function == NULL) {
4693 init_timer(&sp->id_timer);
4694 sp->id_timer.function = s2io_phy_id;
4695 sp->id_timer.data = (unsigned long) sp;
4696 }
4697 mod_timer(&sp->id_timer, jiffies);
4698 if (data)
20346722 4699 msleep_interruptible(data * HZ);
1da177e4 4700 else
20346722 4701 msleep_interruptible(MAX_FLICKER_TIME);
1da177e4
LT		 4702 del_timer_sync(&sp->id_timer);
4703
541ae68f 4704 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
1da177e4
LT		 4705 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
4706 last_gpio_ctrl_val = readq(&bar0->gpio_control);
4707 }
4708
4709 return 0;
4710}
4711
4712/**
4713 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
20346722
K		 4714 * @sp : private member of the device structure, which is a pointer to the
4715 * s2io_nic structure.
1da177e4
LT		 4716 * @ep : pointer to the structure with pause parameters given by ethtool.
4717 * Description:
4718 * Returns the Pause frame generation and reception capability of the NIC.
4719 * Return value:
4720 * void
4721 */
4722static void s2io_ethtool_getpause_data(struct net_device *dev,
4723 struct ethtool_pauseparam *ep)
4724{
4725 u64 val64;
4726 nic_t *sp = dev->priv;
4727 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4728
4729 val64 = readq(&bar0->rmac_pause_cfg);
4730 if (val64 & RMAC_PAUSE_GEN_ENABLE)
4731 ep->tx_pause = TRUE;
4732 if (val64 & RMAC_PAUSE_RX_ENABLE)
4733 ep->rx_pause = TRUE;
4734 ep->autoneg = FALSE;
4735}
4736
4737/**
4738 * s2io_ethtool_setpause_data - set/reset pause frame generation.
20346722 4739 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 4740 * s2io_nic structure.
4741 * @ep : pointer to the structure with pause parameters given by ethtool.
4742 * Description:
4743 * It can be used to set or reset Pause frame generation or reception
4744 * support of the NIC.
4745 * Return value:
4746 * int, returns 0 on Success
4747 */
4748
4749static int s2io_ethtool_setpause_data(struct net_device *dev,
20346722 4750 struct ethtool_pauseparam *ep)
1da177e4
LT		 4751{
4752 u64 val64;
4753 nic_t *sp = dev->priv;
4754 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4755
4756 val64 = readq(&bar0->rmac_pause_cfg);
4757 if (ep->tx_pause)
4758 val64 |= RMAC_PAUSE_GEN_ENABLE;
4759 else
4760 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
4761 if (ep->rx_pause)
4762 val64 |= RMAC_PAUSE_RX_ENABLE;
4763 else
4764 val64 &= ~RMAC_PAUSE_RX_ENABLE;
4765 writeq(val64, &bar0->rmac_pause_cfg);
4766 return 0;
4767}
4768
4769/**
4770 * read_eeprom - reads 4 bytes of data from user given offset.
20346722 4771 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 4772 * s2io_nic structure.
4773 * @off : offset at which the data must be written
4774 * @data : Its an output parameter where the data read at the given
20346722 4775 * offset is stored.
1da177e4 4776 * Description:
20346722 4777 * Will read 4 bytes of data from the user given offset and return the
1da177e4
LT		 4778 * read data.
4779 * NOTE: Will allow to read only part of the EEPROM visible through the
4780 * I2C bus.
4781 * Return value:
4782 * -1 on failure and 0 on success.
4783 */
4784
4785#define S2IO_DEV_ID 5
ad4ebed0 4786static int read_eeprom(nic_t * sp, int off, u64 * data)
1da177e4
LT		 4787{
4788 int ret = -1;
4789 u32 exit_cnt = 0;
4790 u64 val64;
4791 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4792
ad4ebed0 4793 if (sp->device_type == XFRAME_I_DEVICE) {
4794 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4795 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
4796 I2C_CONTROL_CNTL_START;
4797 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
1da177e4 4798
ad4ebed0 4799 while (exit_cnt < 5) {
4800 val64 = readq(&bar0->i2c_control);
4801 if (I2C_CONTROL_CNTL_END(val64)) {
4802 *data = I2C_CONTROL_GET_DATA(val64);
4803 ret = 0;
4804 break;
4805 }
4806 msleep(50);
4807 exit_cnt++;
1da177e4 4808 }
1da177e4
LT		 4809 }
4810
ad4ebed0 4811 if (sp->device_type == XFRAME_II_DEVICE) {
4812 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 4813 SPI_CONTROL_BYTECNT(0x3) |
ad4ebed0 4814 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
4815 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4816 val64 |= SPI_CONTROL_REQ;
4817 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4818 while (exit_cnt < 5) {
4819 val64 = readq(&bar0->spi_control);
4820 if (val64 & SPI_CONTROL_NACK) {
4821 ret = 1;
4822 break;
4823 } else if (val64 & SPI_CONTROL_DONE) {
4824 *data = readq(&bar0->spi_data);
4825 *data &= 0xffffff;
4826 ret = 0;
4827 break;
4828 }
4829 msleep(50);
4830 exit_cnt++;
4831 }
4832 }
1da177e4
LT		 4833 return ret;
4834}
4835
4836/**
4837 * write_eeprom - actually writes the relevant part of the data value.
4838 * @sp : private member of the device structure, which is a pointer to the
4839 * s2io_nic structure.
4840 * @off : offset at which the data must be written
4841 * @data : The data that is to be written
20346722 4842 * @cnt : Number of bytes of the data that are actually to be written into
1da177e4
LT		 4843 * the Eeprom. (max of 3)
4844 * Description:
4845 * Actually writes the relevant part of the data value into the Eeprom
4846 * through the I2C bus.
4847 * Return value:
4848 * 0 on success, -1 on failure.
4849 */
4850
ad4ebed0 4851static int write_eeprom(nic_t * sp, int off, u64 data, int cnt)
1da177e4
LT		 4852{
4853 int exit_cnt = 0, ret = -1;
4854 u64 val64;
4855 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4856
ad4ebed0 4857 if (sp->device_type == XFRAME_I_DEVICE) {
4858 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4859 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
4860 I2C_CONTROL_CNTL_START;
4861 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4862
4863 while (exit_cnt < 5) {
4864 val64 = readq(&bar0->i2c_control);
4865 if (I2C_CONTROL_CNTL_END(val64)) {
4866 if (!(val64 & I2C_CONTROL_NACK))
4867 ret = 0;
4868 break;
4869 }
4870 msleep(50);
4871 exit_cnt++;
4872 }
4873 }
1da177e4 4874
ad4ebed0 4875 if (sp->device_type == XFRAME_II_DEVICE) {
4876 int write_cnt = (cnt == 8) ? 0 : cnt;
4877 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
4878
4879 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 4880 SPI_CONTROL_BYTECNT(write_cnt) |
ad4ebed0 4881 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
4882 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4883 val64 |= SPI_CONTROL_REQ;
4884 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4885 while (exit_cnt < 5) {
4886 val64 = readq(&bar0->spi_control);
4887 if (val64 & SPI_CONTROL_NACK) {
4888 ret = 1;
4889 break;
4890 } else if (val64 & SPI_CONTROL_DONE) {
1da177e4 4891 ret = 0;
ad4ebed0 4892 break;
4893 }
4894 msleep(50);
4895 exit_cnt++;
1da177e4 4896 }
1da177e4 4897 }
1da177e4
LT		 4898 return ret;
4899}
9dc737a7
AR		 4900static void s2io_vpd_read(nic_t *nic)
4901{
b41477f3
AR		 4902 u8 *vpd_data;
4903 u8 data;
9dc737a7
AR		 4904 int i=0, cnt, fail = 0;
4905 int vpd_addr = 0x80;
4906
4907 if (nic->device_type == XFRAME_II_DEVICE) {
4908 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
4909 vpd_addr = 0x80;
4910 }
4911 else {
4912 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
4913 vpd_addr = 0x50;
4914 }
4915
b41477f3
AR		 4916 vpd_data = kmalloc(256, GFP_KERNEL);
4917 if (!vpd_data)
4918 return;
4919
9dc737a7
AR		 4920 for (i = 0; i < 256; i +=4 ) {
4921 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
4922 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
4923 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
4924 for (cnt = 0; cnt <5; cnt++) {
4925 msleep(2);
4926 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
4927 if (data == 0x80)
4928 break;
4929 }
4930 if (cnt >= 5) {
4931 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
4932 fail = 1;
4933 break;
4934 }
4935 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
4936 (u32 *)&vpd_data[i]);
4937 }
4938 if ((!fail) && (vpd_data[1] < VPD_PRODUCT_NAME_LEN)) {
4939 memset(nic->product_name, 0, vpd_data[1]);
4940 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
4941 }
b41477f3 4942 kfree(vpd_data);
9dc737a7
AR		 4943}
4944
1da177e4
LT		 4945/**
4946 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
4947 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
20346722 4948 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 4949 * containing all relevant information.
4950 * @data_buf : user defined value to be written into Eeprom.
4951 * Description: Reads the values stored in the Eeprom at given offset
4952 * for a given length. Stores these values int the input argument data
4953 * buffer 'data_buf' and returns these to the caller (ethtool.)
4954 * Return value:
4955 * int 0 on success
4956 */
4957
4958static int s2io_ethtool_geeprom(struct net_device *dev,
20346722 4959 struct ethtool_eeprom *eeprom, u8 * data_buf)
1da177e4 4960{
ad4ebed0 4961 u32 i, valid;
4962 u64 data;
1da177e4
LT		 4963 nic_t *sp = dev->priv;
4964
4965 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
4966
4967 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
4968 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
4969
4970 for (i = 0; i < eeprom->len; i += 4) {
4971 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
4972 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
4973 return -EFAULT;
4974 }
4975 valid = INV(data);
4976 memcpy((data_buf + i), &valid, 4);
4977 }
4978 return 0;
4979}
4980
4981/**
4982 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
4983 * @sp : private member of the device structure, which is a pointer to the
4984 * s2io_nic structure.
20346722 4985 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 4986 * containing all relevant information.
4987 * @data_buf ; user defined value to be written into Eeprom.
4988 * Description:
4989 * Tries to write the user provided value in the Eeprom, at the offset
4990 * given by the user.
4991 * Return value:
4992 * 0 on success, -EFAULT on failure.
4993 */
4994
4995static int s2io_ethtool_seeprom(struct net_device *dev,
4996 struct ethtool_eeprom *eeprom,
4997 u8 * data_buf)
4998{
4999 int len = eeprom->len, cnt = 0;
ad4ebed0 5000 u64 valid = 0, data;
1da177e4
LT		 5001 nic_t *sp = dev->priv;
5002
5003 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5004 DBG_PRINT(ERR_DBG,
5005 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5006 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5007 eeprom->magic);
5008 return -EFAULT;
5009 }
5010
5011 while (len) {
5012 data = (u32) data_buf[cnt] & 0x000000FF;
5013 if (data) {
5014 valid = (u32) (data << 24);
5015 } else
5016 valid = data;
5017
5018 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5019 DBG_PRINT(ERR_DBG,
5020 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5021 DBG_PRINT(ERR_DBG,
5022 "write into the specified offset\n");
5023 return -EFAULT;
5024 }
5025 cnt++;
5026 len--;
5027 }
5028
5029 return 0;
5030}
5031
5032/**
20346722
K		 5033 * s2io_register_test - reads and writes into all clock domains.
5034 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5035 * s2io_nic structure.
5036 * @data : variable that returns the result of each of the test conducted b
5037 * by the driver.
5038 * Description:
5039 * Read and write into all clock domains. The NIC has 3 clock domains,
5040 * see that registers in all the three regions are accessible.
5041 * Return value:
5042 * 0 on success.
5043 */
5044
5045static int s2io_register_test(nic_t * sp, uint64_t * data)
5046{
5047 XENA_dev_config_t __iomem *bar0 = sp->bar0;
ad4ebed0 5048 u64 val64 = 0, exp_val;
1da177e4
LT		 5049 int fail = 0;
5050
20346722
K		 5051 val64 = readq(&bar0->pif_rd_swapper_fb);
5052 if (val64 != 0x123456789abcdefULL) {
1da177e4
LT		 5053 fail = 1;
5054 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5055 }
5056
5057 val64 = readq(&bar0->rmac_pause_cfg);
5058 if (val64 != 0xc000ffff00000000ULL) {
5059 fail = 1;
5060 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5061 }
5062
5063 val64 = readq(&bar0->rx_queue_cfg);
ad4ebed0 5064 if (sp->device_type == XFRAME_II_DEVICE)
5065 exp_val = 0x0404040404040404ULL;
5066 else
5067 exp_val = 0x0808080808080808ULL;
5068 if (val64 != exp_val) {
1da177e4
LT		 5069 fail = 1;
5070 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5071 }
5072
5073 val64 = readq(&bar0->xgxs_efifo_cfg);
5074 if (val64 != 0x000000001923141EULL) {
5075 fail = 1;
5076 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5077 }
5078
5079 val64 = 0x5A5A5A5A5A5A5A5AULL;
5080 writeq(val64, &bar0->xmsi_data);
5081 val64 = readq(&bar0->xmsi_data);
5082 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5083 fail = 1;
5084 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5085 }
5086
5087 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5088 writeq(val64, &bar0->xmsi_data);
5089 val64 = readq(&bar0->xmsi_data);
5090 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5091 fail = 1;
5092 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5093 }
5094
5095 *data = fail;
ad4ebed0 5096 return fail;
1da177e4
LT		 5097}
5098
5099/**
20346722 5100 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
1da177e4
LT		 5101 * @sp : private member of the device structure, which is a pointer to the
5102 * s2io_nic structure.
5103 * @data:variable that returns the result of each of the test conducted by
5104 * the driver.
5105 * Description:
20346722 5106 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
1da177e4
LT		 5107 * register.
5108 * Return value:
5109 * 0 on success.
5110 */
5111
5112static int s2io_eeprom_test(nic_t * sp, uint64_t * data)
5113{
5114 int fail = 0;
ad4ebed0 5115 u64 ret_data, org_4F0, org_7F0;
5116 u8 saved_4F0 = 0, saved_7F0 = 0;
5117 struct net_device *dev = sp->dev;
1da177e4
LT		 5118
5119 /* Test Write Error at offset 0 */
ad4ebed0 5120 /* Note that SPI interface allows write access to all areas
5121 * of EEPROM. Hence doing all negative testing only for Xframe I.
5122 */
5123 if (sp->device_type == XFRAME_I_DEVICE)
5124 if (!write_eeprom(sp, 0, 0, 3))
5125 fail = 1;
5126
5127 /* Save current values at offsets 0x4F0 and 0x7F0 */
5128 if (!read_eeprom(sp, 0x4F0, &org_4F0))
5129 saved_4F0 = 1;
5130 if (!read_eeprom(sp, 0x7F0, &org_7F0))
5131 saved_7F0 = 1;
1da177e4
LT		 5132
5133 /* Test Write at offset 4f0 */
ad4ebed0 5134 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
1da177e4
LT		 5135 fail = 1;
5136 if (read_eeprom(sp, 0x4F0, &ret_data))
5137 fail = 1;
5138
ad4ebed0 5139 if (ret_data != 0x012345) {
26b7625c
AM		 5140 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5141 "Data written %llx Data read %llx\n",
5142 dev->name, (unsigned long long)0x12345,
5143 (unsigned long long)ret_data);
1da177e4 5144 fail = 1;
ad4ebed0 5145 }
1da177e4
LT		 5146
5147 /* Reset the EEPROM data go FFFF */
ad4ebed0 5148 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
1da177e4
LT		 5149
5150 /* Test Write Request Error at offset 0x7c */
ad4ebed0 5151 if (sp->device_type == XFRAME_I_DEVICE)
5152 if (!write_eeprom(sp, 0x07C, 0, 3))
5153 fail = 1;
1da177e4 5154
ad4ebed0 5155 /* Test Write Request at offset 0x7f0 */
5156 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
1da177e4 5157 fail = 1;
ad4ebed0 5158 if (read_eeprom(sp, 0x7F0, &ret_data))
1da177e4
LT		 5159 fail = 1;
5160
ad4ebed0 5161 if (ret_data != 0x012345) {
26b7625c
AM		 5162 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
5163 "Data written %llx Data read %llx\n",
5164 dev->name, (unsigned long long)0x12345,
5165 (unsigned long long)ret_data);
1da177e4 5166 fail = 1;
ad4ebed0 5167 }
1da177e4
LT		 5168
5169 /* Reset the EEPROM data go FFFF */
ad4ebed0 5170 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
1da177e4 5171
ad4ebed0 5172 if (sp->device_type == XFRAME_I_DEVICE) {
5173 /* Test Write Error at offset 0x80 */
5174 if (!write_eeprom(sp, 0x080, 0, 3))
5175 fail = 1;
1da177e4 5176
ad4ebed0 5177 /* Test Write Error at offset 0xfc */
5178 if (!write_eeprom(sp, 0x0FC, 0, 3))
5179 fail = 1;
1da177e4 5180
ad4ebed0 5181 /* Test Write Error at offset 0x100 */
5182 if (!write_eeprom(sp, 0x100, 0, 3))
5183 fail = 1;
1da177e4 5184
ad4ebed0 5185 /* Test Write Error at offset 4ec */
5186 if (!write_eeprom(sp, 0x4EC, 0, 3))
5187 fail = 1;
5188 }
5189
5190 /* Restore values at offsets 0x4F0 and 0x7F0 */
5191 if (saved_4F0)
5192 write_eeprom(sp, 0x4F0, org_4F0, 3);
5193 if (saved_7F0)
5194 write_eeprom(sp, 0x7F0, org_7F0, 3);
1da177e4
LT		 5195
5196 *data = fail;
ad4ebed0 5197 return fail;
1da177e4
LT		 5198}
5199
5200/**
5201 * s2io_bist_test - invokes the MemBist test of the card .
20346722 5202 * @sp : private member of the device structure, which is a pointer to the
1da177e4 5203 * s2io_nic structure.
20346722 5204 * @data:variable that returns the result of each of the test conducted by
1da177e4
LT		 5205 * the driver.
5206 * Description:
5207 * This invokes the MemBist test of the card. We give around
5208 * 2 secs time for the Test to complete. If it's still not complete
20346722 5209 * within this peiod, we consider that the test failed.
1da177e4
LT		 5210 * Return value:
5211 * 0 on success and -1 on failure.
5212 */
5213
5214static int s2io_bist_test(nic_t * sp, uint64_t * data)
5215{
5216 u8 bist = 0;
5217 int cnt = 0, ret = -1;
5218
5219 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5220 bist |= PCI_BIST_START;
5221 pci_write_config_word(sp->pdev, PCI_BIST, bist);
5222
5223 while (cnt < 20) {
5224 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5225 if (!(bist & PCI_BIST_START)) {
5226 *data = (bist & PCI_BIST_CODE_MASK);
5227 ret = 0;
5228 break;
5229 }
5230 msleep(100);
5231 cnt++;
5232 }
5233
5234 return ret;
5235}
5236
5237/**
20346722
K		 5238 * s2io-link_test - verifies the link state of the nic
5239 * @sp ; private member of the device structure, which is a pointer to the
1da177e4
LT		 5240 * s2io_nic structure.
5241 * @data: variable that returns the result of each of the test conducted by
5242 * the driver.
5243 * Description:
20346722 5244 * The function verifies the link state of the NIC and updates the input
1da177e4
LT		 5245 * argument 'data' appropriately.
5246 * Return value:
5247 * 0 on success.
5248 */
5249
5250static int s2io_link_test(nic_t * sp, uint64_t * data)
5251{
5252 XENA_dev_config_t __iomem *bar0 = sp->bar0;
5253 u64 val64;
5254
5255 val64 = readq(&bar0->adapter_status);
c92ca04b 5256 if(!(LINK_IS_UP(val64)))
1da177e4 5257 *data = 1;
c92ca04b
AR		 5258 else
5259 *data = 0;
1da177e4 5260
b41477f3 5261 return *data;
1da177e4
LT		 5262}
5263
5264/**
20346722
K		 5265 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
5266 * @sp - private member of the device structure, which is a pointer to the
1da177e4 5267 * s2io_nic structure.
20346722 5268 * @data - variable that returns the result of each of the test
1da177e4
LT		 5269 * conducted by the driver.
5270 * Description:
20346722 5271 * This is one of the offline test that tests the read and write
1da177e4
LT		 5272 * access to the RldRam chip on the NIC.
5273 * Return value:
5274 * 0 on success.
5275 */
5276
5277static int s2io_rldram_test(nic_t * sp, uint64_t * data)
5278{
5279 XENA_dev_config_t __iomem *bar0 = sp->bar0;
5280 u64 val64;
ad4ebed0 5281 int cnt, iteration = 0, test_fail = 0;
1da177e4
LT		 5282
5283 val64 = readq(&bar0->adapter_control);
5284 val64 &= ~ADAPTER_ECC_EN;
5285 writeq(val64, &bar0->adapter_control);
5286
5287 val64 = readq(&bar0->mc_rldram_test_ctrl);
5288 val64 |= MC_RLDRAM_TEST_MODE;
ad4ebed0 5289 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 5290
5291 val64 = readq(&bar0->mc_rldram_mrs);
5292 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
5293 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5294
5295 val64 |= MC_RLDRAM_MRS_ENABLE;
5296 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5297
5298 while (iteration < 2) {
5299 val64 = 0x55555555aaaa0000ULL;
5300 if (iteration == 1) {
5301 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5302 }
5303 writeq(val64, &bar0->mc_rldram_test_d0);
5304
5305 val64 = 0xaaaa5a5555550000ULL;
5306 if (iteration == 1) {
5307 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5308 }
5309 writeq(val64, &bar0->mc_rldram_test_d1);
5310
5311 val64 = 0x55aaaaaaaa5a0000ULL;
5312 if (iteration == 1) {
5313 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5314 }
5315 writeq(val64, &bar0->mc_rldram_test_d2);
5316
ad4ebed0 5317 val64 = (u64) (0x0000003ffffe0100ULL);
1da177e4
LT		 5318 writeq(val64, &bar0->mc_rldram_test_add);
5319
ad4ebed0 5320 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
5321 MC_RLDRAM_TEST_GO;
5322 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 5323
5324 for (cnt = 0; cnt < 5; cnt++) {
5325 val64 = readq(&bar0->mc_rldram_test_ctrl);
5326 if (val64 & MC_RLDRAM_TEST_DONE)
5327 break;
5328 msleep(200);
5329 }
5330
5331 if (cnt == 5)
5332 break;
5333
ad4ebed0 5334 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
5335 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 5336
5337 for (cnt = 0; cnt < 5; cnt++) {
5338 val64 = readq(&bar0->mc_rldram_test_ctrl);
5339 if (val64 & MC_RLDRAM_TEST_DONE)
5340 break;
5341 msleep(500);
5342 }
5343
5344 if (cnt == 5)
5345 break;
5346
5347 val64 = readq(&bar0->mc_rldram_test_ctrl);
ad4ebed0 5348 if (!(val64 & MC_RLDRAM_TEST_PASS))
5349 test_fail = 1;
1da177e4
LT		 5350
5351 iteration++;
5352 }
5353
ad4ebed0 5354 *data = test_fail;
1da177e4 5355
ad4ebed0 5356 /* Bring the adapter out of test mode */
5357 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
5358
5359 return test_fail;
1da177e4
LT		 5360}
5361
5362/**
5363 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
5364 * @sp : private member of the device structure, which is a pointer to the
5365 * s2io_nic structure.
5366 * @ethtest : pointer to a ethtool command specific structure that will be
5367 * returned to the user.
20346722 5368 * @data : variable that returns the result of each of the test
1da177e4
LT		 5369 * conducted by the driver.
5370 * Description:
5371 * This function conducts 6 tests ( 4 offline and 2 online) to determine
5372 * the health of the card.
5373 * Return value:
5374 * void
5375 */
5376
5377static void s2io_ethtool_test(struct net_device *dev,
5378 struct ethtool_test *ethtest,
5379 uint64_t * data)
5380{
5381 nic_t *sp = dev->priv;
5382 int orig_state = netif_running(sp->dev);
5383
5384 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
5385 /* Offline Tests. */
20346722 5386 if (orig_state)
1da177e4 5387 s2io_close(sp->dev);
1da177e4
LT		 5388
5389 if (s2io_register_test(sp, &data[0]))
5390 ethtest->flags |= ETH_TEST_FL_FAILED;
5391
5392 s2io_reset(sp);
1da177e4
LT		 5393
5394 if (s2io_rldram_test(sp, &data[3]))
5395 ethtest->flags |= ETH_TEST_FL_FAILED;
5396
5397 s2io_reset(sp);
1da177e4
LT		 5398
5399 if (s2io_eeprom_test(sp, &data[1]))
5400 ethtest->flags |= ETH_TEST_FL_FAILED;
5401
5402 if (s2io_bist_test(sp, &data[4]))
5403 ethtest->flags |= ETH_TEST_FL_FAILED;
5404
5405 if (orig_state)
5406 s2io_open(sp->dev);
5407
5408 data[2] = 0;
5409 } else {
5410 /* Online Tests. */
5411 if (!orig_state) {
5412 DBG_PRINT(ERR_DBG,
5413 "%s: is not up, cannot run test\n",
5414 dev->name);
5415 data[0] = -1;
5416 data[1] = -1;
5417 data[2] = -1;
5418 data[3] = -1;
5419 data[4] = -1;
5420 }
5421
5422 if (s2io_link_test(sp, &data[2]))
5423 ethtest->flags |= ETH_TEST_FL_FAILED;
5424
5425 data[0] = 0;
5426 data[1] = 0;
5427 data[3] = 0;
5428 data[4] = 0;
5429 }
5430}
5431
5432static void s2io_get_ethtool_stats(struct net_device *dev,
5433 struct ethtool_stats *estats,
5434 u64 * tmp_stats)
5435{
5436 int i = 0;
5437 nic_t *sp = dev->priv;
5438 StatInfo_t *stat_info = sp->mac_control.stats_info;
5439
7ba013ac 5440 s2io_updt_stats(sp);
541ae68f
K		 5441 tmp_stats[i++] =
5442 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
5443 le32_to_cpu(stat_info->tmac_frms);
5444 tmp_stats[i++] =
5445 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
5446 le32_to_cpu(stat_info->tmac_data_octets);
1da177e4 5447 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
541ae68f
K		 5448 tmp_stats[i++] =
5449 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
5450 le32_to_cpu(stat_info->tmac_mcst_frms);
5451 tmp_stats[i++] =
5452 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
5453 le32_to_cpu(stat_info->tmac_bcst_frms);
1da177e4 5454 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
bd1034f0
AR		 5455 tmp_stats[i++] =
5456 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
5457 le32_to_cpu(stat_info->tmac_ttl_octets);
5458 tmp_stats[i++] =
5459 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
5460 le32_to_cpu(stat_info->tmac_ucst_frms);
5461 tmp_stats[i++] =
5462 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
5463 le32_to_cpu(stat_info->tmac_nucst_frms);
541ae68f
K		 5464 tmp_stats[i++] =
5465 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
5466 le32_to_cpu(stat_info->tmac_any_err_frms);
bd1034f0 5467 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
1da177e4 5468 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
541ae68f
K		 5469 tmp_stats[i++] =
5470 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
5471 le32_to_cpu(stat_info->tmac_vld_ip);
5472 tmp_stats[i++] =
5473 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
5474 le32_to_cpu(stat_info->tmac_drop_ip);
5475 tmp_stats[i++] =
5476 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
5477 le32_to_cpu(stat_info->tmac_icmp);
5478 tmp_stats[i++] =
5479 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
5480 le32_to_cpu(stat_info->tmac_rst_tcp);
1da177e4 5481 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
541ae68f
K		 5482 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
5483 le32_to_cpu(stat_info->tmac_udp);
5484 tmp_stats[i++] =
5485 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
5486 le32_to_cpu(stat_info->rmac_vld_frms);
5487 tmp_stats[i++] =
5488 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
5489 le32_to_cpu(stat_info->rmac_data_octets);
1da177e4
LT		 5490 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
5491 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
541ae68f
K		 5492 tmp_stats[i++] =
5493 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
5494 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
5495 tmp_stats[i++] =
5496 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
5497 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
1da177e4 5498 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
bd1034f0 5499 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
1da177e4
LT		 5500 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
5501 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
bd1034f0
AR		 5502 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
5503 tmp_stats[i++] =
5504 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
5505 le32_to_cpu(stat_info->rmac_ttl_octets);
5506 tmp_stats[i++] =
5507 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
5508 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
5509 tmp_stats[i++] =
5510 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
5511 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
541ae68f
K		 5512 tmp_stats[i++] =
5513 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
5514 le32_to_cpu(stat_info->rmac_discarded_frms);
bd1034f0
AR		 5515 tmp_stats[i++] =
5516 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
5517 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
5518 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
5519 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
541ae68f
K		 5520 tmp_stats[i++] =
5521 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
5522 le32_to_cpu(stat_info->rmac_usized_frms);
5523 tmp_stats[i++] =
5524 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
5525 le32_to_cpu(stat_info->rmac_osized_frms);
5526 tmp_stats[i++] =
5527 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
5528 le32_to_cpu(stat_info->rmac_frag_frms);
5529 tmp_stats[i++] =
5530 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
5531 le32_to_cpu(stat_info->rmac_jabber_frms);
bd1034f0
AR		 5532 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
5533 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
5534 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
5535 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
5536 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
5537 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
5538 tmp_stats[i++] =
5539 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
541ae68f 5540 le32_to_cpu(stat_info->rmac_ip);
1da177e4
LT		 5541 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
5542 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
bd1034f0
AR		 5543 tmp_stats[i++] =
5544 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
541ae68f 5545 le32_to_cpu(stat_info->rmac_drop_ip);
bd1034f0
AR		 5546 tmp_stats[i++] =
5547 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
541ae68f 5548 le32_to_cpu(stat_info->rmac_icmp);
1da177e4 5549 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
bd1034f0
AR		 5550 tmp_stats[i++] =
5551 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
541ae68f
K		 5552 le32_to_cpu(stat_info->rmac_udp);
5553 tmp_stats[i++] =
5554 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
5555 le32_to_cpu(stat_info->rmac_err_drp_udp);
bd1034f0
AR		 5556 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
5557 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
5558 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
5559 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
5560 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
5561 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
5562 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
5563 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
5564 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
5565 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
5566 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
5567 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
5568 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
5569 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
5570 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
5571 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
5572 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
541ae68f
K		 5573 tmp_stats[i++] =
5574 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
5575 le32_to_cpu(stat_info->rmac_pause_cnt);
bd1034f0
AR		 5576 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
5577 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
541ae68f
K		 5578 tmp_stats[i++] =
5579 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
5580 le32_to_cpu(stat_info->rmac_accepted_ip);
1da177e4 5581 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
bd1034f0
AR		 5582 tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
5583 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
5584 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
5585 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
5586 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
5587 tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
5588 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
5589 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
5590 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
5591 tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
5592 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
5593 tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
5594 tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
5595 tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
5596 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
5597 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
5598 tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
5599 tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
5600 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
5601 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
5602 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
5603 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
5604 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
5605 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
5606 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
5607 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
5608 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
5609 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
5610 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
5611 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
5612 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
5613 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
5614 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
5615 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
7ba013ac
K		 5616 tmp_stats[i++] = 0;
5617 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
5618 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
bd1034f0
AR		 5619 tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
5620 tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
5621 tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
5622 tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
5623 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt;
5624 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
5625 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
5626 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
5627 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
5628 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
5629 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
5630 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
5631 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
5632 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
5633 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
5634 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
5635 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
7d3d0439
RA		 5636 tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
5637 tmp_stats[i++] = stat_info->sw_stat.sending_both;
5638 tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
5639 tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
fe931395 5640 if (stat_info->sw_stat.num_aggregations) {
bd1034f0
AR		 5641 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
5642 int count = 0;
6aa20a22 5643 /*
bd1034f0
AR		 5644 * Since 64-bit divide does not work on all platforms,
5645 * do repeated subtraction.
5646 */
5647 while (tmp >= stat_info->sw_stat.num_aggregations) {
5648 tmp -= stat_info->sw_stat.num_aggregations;
5649 count++;
5650 }
5651 tmp_stats[i++] = count;
fe931395 5652 }
bd1034f0
AR		 5653 else
5654 tmp_stats[i++] = 0;
1da177e4
LT		 5655}
5656
ac1f60db 5657static int s2io_ethtool_get_regs_len(struct net_device *dev)
1da177e4
LT		 5658{
5659 return (XENA_REG_SPACE);
5660}
5661
5662
ac1f60db 5663static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
1da177e4
LT		 5664{
5665 nic_t *sp = dev->priv;
5666
5667 return (sp->rx_csum);
5668}
ac1f60db
AB		 5669
5670static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
1da177e4
LT		 5671{
5672 nic_t *sp = dev->priv;
5673
5674 if (data)
5675 sp->rx_csum = 1;
5676 else
5677 sp->rx_csum = 0;
5678
5679 return 0;
5680}
ac1f60db
AB		 5681
5682static int s2io_get_eeprom_len(struct net_device *dev)
1da177e4
LT		 5683{
5684 return (XENA_EEPROM_SPACE);
5685}
5686
ac1f60db 5687static int s2io_ethtool_self_test_count(struct net_device *dev)
1da177e4
LT		 5688{
5689 return (S2IO_TEST_LEN);
5690}
ac1f60db
AB		 5691
5692static void s2io_ethtool_get_strings(struct net_device *dev,
5693 u32 stringset, u8 * data)
1da177e4
LT		 5694{
5695 switch (stringset) {
5696 case ETH_SS_TEST:
5697 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
5698 break;
5699 case ETH_SS_STATS:
5700 memcpy(data, &ethtool_stats_keys,
5701 sizeof(ethtool_stats_keys));
5702 }
5703}
1da177e4
LT		 5704static int s2io_ethtool_get_stats_count(struct net_device *dev)
5705{
5706 return (S2IO_STAT_LEN);
5707}
5708
ac1f60db 5709static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
1da177e4
LT		 5710{
5711 if (data)
5712 dev->features |= NETIF_F_IP_CSUM;
5713 else
5714 dev->features &= ~NETIF_F_IP_CSUM;
5715
5716 return 0;
5717}
5718
75c30b13
AR		 5719static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
5720{
5721 return (dev->features & NETIF_F_TSO) != 0;
5722}
5723static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
5724{
5725 if (data)
5726 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
5727 else
5728 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
5729
5730 return 0;
5731}
1da177e4 5732
7282d491 5733static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 5734 .get_settings = s2io_ethtool_gset,
5735 .set_settings = s2io_ethtool_sset,
5736 .get_drvinfo = s2io_ethtool_gdrvinfo,
5737 .get_regs_len = s2io_ethtool_get_regs_len,
5738 .get_regs = s2io_ethtool_gregs,
5739 .get_link = ethtool_op_get_link,
5740 .get_eeprom_len = s2io_get_eeprom_len,
5741 .get_eeprom = s2io_ethtool_geeprom,
5742 .set_eeprom = s2io_ethtool_seeprom,
5743 .get_pauseparam = s2io_ethtool_getpause_data,
5744 .set_pauseparam = s2io_ethtool_setpause_data,
5745 .get_rx_csum = s2io_ethtool_get_rx_csum,
5746 .set_rx_csum = s2io_ethtool_set_rx_csum,
5747 .get_tx_csum = ethtool_op_get_tx_csum,
5748 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
5749 .get_sg = ethtool_op_get_sg,
5750 .set_sg = ethtool_op_set_sg,
75c30b13
AR		 5751 .get_tso = s2io_ethtool_op_get_tso,
5752 .set_tso = s2io_ethtool_op_set_tso,
fed5eccd
AR		 5753 .get_ufo = ethtool_op_get_ufo,
5754 .set_ufo = ethtool_op_set_ufo,
1da177e4
LT		 5755 .self_test_count = s2io_ethtool_self_test_count,
5756 .self_test = s2io_ethtool_test,
5757 .get_strings = s2io_ethtool_get_strings,
5758 .phys_id = s2io_ethtool_idnic,
5759 .get_stats_count = s2io_ethtool_get_stats_count,
5760 .get_ethtool_stats = s2io_get_ethtool_stats
5761};
5762
5763/**
20346722 5764 * s2io_ioctl - Entry point for the Ioctl
1da177e4
LT		 5765 * @dev : Device pointer.
5766 * @ifr : An IOCTL specefic structure, that can contain a pointer to
5767 * a proprietary structure used to pass information to the driver.
5768 * @cmd : This is used to distinguish between the different commands that
5769 * can be passed to the IOCTL functions.
5770 * Description:
20346722
K		 5771 * Currently there are no special functionality supported in IOCTL, hence
5772 * function always return EOPNOTSUPPORTED
1da177e4
LT		 5773 */
5774
ac1f60db 5775static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1da177e4
LT		 5776{
5777 return -EOPNOTSUPP;
5778}
5779
5780/**
5781 * s2io_change_mtu - entry point to change MTU size for the device.
5782 * @dev : device pointer.
5783 * @new_mtu : the new MTU size for the device.
5784 * Description: A driver entry point to change MTU size for the device.
5785 * Before changing the MTU the device must be stopped.
5786 * Return value:
5787 * 0 on success and an appropriate (-)ve integer as defined in errno.h
5788 * file on failure.
5789 */
5790
ac1f60db 5791static int s2io_change_mtu(struct net_device *dev, int new_mtu)
1da177e4
LT		 5792{
5793 nic_t *sp = dev->priv;
1da177e4
LT		 5794
5795 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
5796 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
5797 dev->name);
5798 return -EPERM;
5799 }
5800
1da177e4 5801 dev->mtu = new_mtu;
d8892c6e 5802 if (netif_running(dev)) {
e6a8fee2 5803 s2io_card_down(sp);
d8892c6e
K		 5804 netif_stop_queue(dev);
5805 if (s2io_card_up(sp)) {
5806 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
5807 __FUNCTION__);
5808 }
5809 if (netif_queue_stopped(dev))
5810 netif_wake_queue(dev);
5811 } else { /* Device is down */
5812 XENA_dev_config_t __iomem *bar0 = sp->bar0;
5813 u64 val64 = new_mtu;
5814
5815 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
5816 }
1da177e4
LT		 5817
5818 return 0;
5819}
5820
5821/**
5822 * s2io_tasklet - Bottom half of the ISR.
5823 * @dev_adr : address of the device structure in dma_addr_t format.
5824 * Description:
5825 * This is the tasklet or the bottom half of the ISR. This is
20346722 5826 * an extension of the ISR which is scheduled by the scheduler to be run
1da177e4 5827 * when the load on the CPU is low. All low priority tasks of the ISR can
20346722 5828 * be pushed into the tasklet. For now the tasklet is used only to
1da177e4
LT		 5829 * replenish the Rx buffers in the Rx buffer descriptors.
5830 * Return value:
5831 * void.
5832 */
5833
5834static void s2io_tasklet(unsigned long dev_addr)
5835{
5836 struct net_device *dev = (struct net_device *) dev_addr;
5837 nic_t *sp = dev->priv;
5838 int i, ret;
5839 mac_info_t *mac_control;
5840 struct config_param *config;
5841
5842 mac_control = &sp->mac_control;
5843 config = &sp->config;
5844
5845 if (!TASKLET_IN_USE) {
5846 for (i = 0; i < config->rx_ring_num; i++) {
5847 ret = fill_rx_buffers(sp, i);
5848 if (ret == -ENOMEM) {
5849 DBG_PRINT(ERR_DBG, "%s: Out of ",
5850 dev->name);
5851 DBG_PRINT(ERR_DBG, "memory in tasklet\n");
5852 break;
5853 } else if (ret == -EFILL) {
5854 DBG_PRINT(ERR_DBG,
5855 "%s: Rx Ring %d is full\n",
5856 dev->name, i);
5857 break;
5858 }
5859 }
5860 clear_bit(0, (&sp->tasklet_status));
5861 }
5862}
5863
5864/**
5865 * s2io_set_link - Set the LInk status
5866 * @data: long pointer to device private structue
5867 * Description: Sets the link status for the adapter
5868 */
5869
c4028958 5870static void s2io_set_link(struct work_struct *work)
1da177e4 5871{
c4028958 5872 nic_t *nic = container_of(work, nic_t, set_link_task);
1da177e4
LT		 5873 struct net_device *dev = nic->dev;
5874 XENA_dev_config_t __iomem *bar0 = nic->bar0;
5875 register u64 val64;
5876 u16 subid;
5877
5878 if (test_and_set_bit(0, &(nic->link_state))) {
5879 /* The card is being reset, no point doing anything */
5880 return;
5881 }
5882
5883 subid = nic->pdev->subsystem_device;
a371a07d
K		 5884 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
5885 /*
5886 * Allow a small delay for the NICs self initiated
5887 * cleanup to complete.
5888 */
5889 msleep(100);
5890 }
1da177e4
LT		 5891
5892 val64 = readq(&bar0->adapter_status);
20346722 5893 if (verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
1da177e4
LT		 5894 if (LINK_IS_UP(val64)) {
5895 val64 = readq(&bar0->adapter_control);
5896 val64 |= ADAPTER_CNTL_EN;
5897 writeq(val64, &bar0->adapter_control);
541ae68f
K		 5898 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
5899 subid)) {
1da177e4
LT		 5900 val64 = readq(&bar0->gpio_control);
5901 val64 |= GPIO_CTRL_GPIO_0;
5902 writeq(val64, &bar0->gpio_control);
5903 val64 = readq(&bar0->gpio_control);
5904 } else {
5905 val64 |= ADAPTER_LED_ON;
5906 writeq(val64, &bar0->adapter_control);
5907 }
a371a07d
K		 5908 if (s2io_link_fault_indication(nic) ==
5909 MAC_RMAC_ERR_TIMER) {
5910 val64 = readq(&bar0->adapter_status);
5911 if (!LINK_IS_UP(val64)) {
5912 DBG_PRINT(ERR_DBG, "%s:", dev->name);
5913 DBG_PRINT(ERR_DBG, " Link down");
5914 DBG_PRINT(ERR_DBG, "after ");
5915 DBG_PRINT(ERR_DBG, "enabling ");
5916 DBG_PRINT(ERR_DBG, "device \n");
5917 }
1da177e4
LT		 5918 }
5919 if (nic->device_enabled_once == FALSE) {
5920 nic->device_enabled_once = TRUE;
5921 }
5922 s2io_link(nic, LINK_UP);
5923 } else {
541ae68f
K		 5924 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
5925 subid)) {
1da177e4
LT		 5926 val64 = readq(&bar0->gpio_control);
5927 val64 &= ~GPIO_CTRL_GPIO_0;
5928 writeq(val64, &bar0->gpio_control);
5929 val64 = readq(&bar0->gpio_control);
5930 }
5931 s2io_link(nic, LINK_DOWN);
5932 }
5933 } else { /* NIC is not Quiescent. */
5934 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
5935 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
5936 netif_stop_queue(dev);
5937 }
5938 clear_bit(0, &(nic->link_state));
5939}
5940
5d3213cc
AR		 5941static int set_rxd_buffer_pointer(nic_t *sp, RxD_t *rxdp, buffAdd_t *ba,
5942 struct sk_buff **skb, u64 *temp0, u64 *temp1,
5943 u64 *temp2, int size)
5944{
5945 struct net_device *dev = sp->dev;
5946 struct sk_buff *frag_list;
5947
5948 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
5949 /* allocate skb */
5950 if (*skb) {
5951 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
5952 /*
5953 * As Rx frame are not going to be processed,
5954 * using same mapped address for the Rxd
5955 * buffer pointer
5956 */
5957 ((RxD1_t*)rxdp)->Buffer0_ptr = *temp0;
5958 } else {
5959 *skb = dev_alloc_skb(size);
5960 if (!(*skb)) {
5961 DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
5962 DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
5963 return -ENOMEM ;
5964 }
5965 /* storing the mapped addr in a temp variable
5966 * such it will be used for next rxd whose
5967 * Host Control is NULL
5968 */
5969 ((RxD1_t*)rxdp)->Buffer0_ptr = *temp0 =
5970 pci_map_single( sp->pdev, (*skb)->data,
5971 size - NET_IP_ALIGN,
5972 PCI_DMA_FROMDEVICE);
5973 rxdp->Host_Control = (unsigned long) (*skb);
5974 }
5975 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
5976 /* Two buffer Mode */
5977 if (*skb) {
5978 ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2;
5979 ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0;
5980 ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1;
5981 } else {
5982 *skb = dev_alloc_skb(size);
2ceaac75
DR		 5983 if (!(*skb)) {
5984 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n",
5985 dev->name);
5986 return -ENOMEM;
5987 }
5d3213cc
AR		 5988 ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2 =
5989 pci_map_single(sp->pdev, (*skb)->data,
5990 dev->mtu + 4,
5991 PCI_DMA_FROMDEVICE);
5992 ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0 =
5993 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
5994 PCI_DMA_FROMDEVICE);
5995 rxdp->Host_Control = (unsigned long) (*skb);
5996
5997 /* Buffer-1 will be dummy buffer not used */
5998 ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1 =
5999 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6000 PCI_DMA_FROMDEVICE);
6001 }
6002 } else if ((rxdp->Host_Control == 0)) {
6003 /* Three buffer mode */
6004 if (*skb) {
6005 ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0;
6006 ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1;
6007 ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2;
6008 } else {
6009 *skb = dev_alloc_skb(size);
2ceaac75
DR		 6010 if (!(*skb)) {
6011 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n",
6012 dev->name);
6013 return -ENOMEM;
6014 }
5d3213cc
AR		 6015 ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0 =
6016 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6017 PCI_DMA_FROMDEVICE);
6018 /* Buffer-1 receives L3/L4 headers */
6019 ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1 =
6020 pci_map_single( sp->pdev, (*skb)->data,
6021 l3l4hdr_size + 4,
6022 PCI_DMA_FROMDEVICE);
6023 /*
6024 * skb_shinfo(skb)->frag_list will have L4
6025 * data payload
6026 */
6027 skb_shinfo(*skb)->frag_list = dev_alloc_skb(dev->mtu +
6028 ALIGN_SIZE);
6029 if (skb_shinfo(*skb)->frag_list == NULL) {
6030 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb \
6031 failed\n ", dev->name);
6032 return -ENOMEM ;
6033 }
6034 frag_list = skb_shinfo(*skb)->frag_list;
6035 frag_list->next = NULL;
6036 /*
6037 * Buffer-2 receives L4 data payload
6038 */
6039 ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2 =
6040 pci_map_single( sp->pdev, frag_list->data,
6041 dev->mtu, PCI_DMA_FROMDEVICE);
6042 }
6043 }
6044 return 0;
6045}
6046static void set_rxd_buffer_size(nic_t *sp, RxD_t *rxdp, int size)
6047{
6048 struct net_device *dev = sp->dev;
6049 if (sp->rxd_mode == RXD_MODE_1) {
6050 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6051 } else if (sp->rxd_mode == RXD_MODE_3B) {
6052 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6053 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6054 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
6055 } else {
6056 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6057 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
6058 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
6059 }
6060}
6061
6062static int rxd_owner_bit_reset(nic_t *sp)
6063{
6064 int i, j, k, blk_cnt = 0, size;
6065 mac_info_t * mac_control = &sp->mac_control;
6066 struct config_param *config = &sp->config;
6067 struct net_device *dev = sp->dev;
6068 RxD_t *rxdp = NULL;
6069 struct sk_buff *skb = NULL;
6070 buffAdd_t *ba = NULL;
6071 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6072
6073 /* Calculate the size based on ring mode */
6074 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6075 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6076 if (sp->rxd_mode == RXD_MODE_1)
6077 size += NET_IP_ALIGN;
6078 else if (sp->rxd_mode == RXD_MODE_3B)
6079 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6080 else
6081 size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
6082
6083 for (i = 0; i < config->rx_ring_num; i++) {
6084 blk_cnt = config->rx_cfg[i].num_rxd /
6085 (rxd_count[sp->rxd_mode] +1);
6086
6087 for (j = 0; j < blk_cnt; j++) {
6088 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6089 rxdp = mac_control->rings[i].
6090 rx_blocks[j].rxds[k].virt_addr;
6091 if(sp->rxd_mode >= RXD_MODE_3A)
6092 ba = &mac_control->rings[i].ba[j][k];
6093 set_rxd_buffer_pointer(sp, rxdp, ba,
6094 &skb,(u64 *)&temp0_64,
6095 (u64 *)&temp1_64,
6096 (u64 *)&temp2_64, size);
6097
6098 set_rxd_buffer_size(sp, rxdp, size);
6099 wmb();
6100 /* flip the Ownership bit to Hardware */
6101 rxdp->Control_1 |= RXD_OWN_XENA;
6102 }
6103 }
6104 }
6105 return 0;
6106
6107}
6108
e6a8fee2 6109static int s2io_add_isr(nic_t * sp)
1da177e4 6110{
e6a8fee2 6111 int ret = 0;
c92ca04b 6112 struct net_device *dev = sp->dev;
e6a8fee2 6113 int err = 0;
1da177e4 6114
e6a8fee2
AR		 6115 if (sp->intr_type == MSI)
6116 ret = s2io_enable_msi(sp);
6117 else if (sp->intr_type == MSI_X)
6118 ret = s2io_enable_msi_x(sp);
6119 if (ret) {
6120 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6121 sp->intr_type = INTA;
20346722 6122 }
1da177e4 6123
e6a8fee2
AR		 6124 /* Store the values of the MSIX table in the nic_t structure */
6125 store_xmsi_data(sp);
c92ca04b 6126
e6a8fee2
AR		 6127 /* After proper initialization of H/W, register ISR */
6128 if (sp->intr_type == MSI) {
6129 err = request_irq((int) sp->pdev->irq, s2io_msi_handle,
6130 IRQF_SHARED, sp->name, dev);
6131 if (err) {
6132 pci_disable_msi(sp->pdev);
6133 DBG_PRINT(ERR_DBG, "%s: MSI registration failed\n",
6134 dev->name);
6135 return -1;
6136 }
6137 }
6138 if (sp->intr_type == MSI_X) {
6139 int i;
c92ca04b 6140
e6a8fee2
AR		 6141 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
6142 if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
6143 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
6144 dev->name, i);
6145 err = request_irq(sp->entries[i].vector,
6146 s2io_msix_fifo_handle, 0, sp->desc[i],
6147 sp->s2io_entries[i].arg);
6148 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc[i],
6149 (unsigned long long)sp->msix_info[i].addr);
6150 } else {
6151 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
6152 dev->name, i);
6153 err = request_irq(sp->entries[i].vector,
6154 s2io_msix_ring_handle, 0, sp->desc[i],
6155 sp->s2io_entries[i].arg);
6156 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc[i],
6157 (unsigned long long)sp->msix_info[i].addr);
c92ca04b 6158 }
e6a8fee2
AR		 6159 if (err) {
6160 DBG_PRINT(ERR_DBG,"%s:MSI-X-%d registration "
6161 "failed\n", dev->name, i);
6162 DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
6163 return -1;
6164 }
6165 sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
6166 }
6167 }
6168 if (sp->intr_type == INTA) {
6169 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
6170 sp->name, dev);
6171 if (err) {
6172 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
6173 dev->name);
6174 return -1;
6175 }
6176 }
6177 return 0;
6178}
6179static void s2io_rem_isr(nic_t * sp)
6180{
6181 int cnt = 0;
6182 struct net_device *dev = sp->dev;
6183
6184 if (sp->intr_type == MSI_X) {
6185 int i;
6186 u16 msi_control;
6187
6188 for (i=1; (sp->s2io_entries[i].in_use ==
6189 MSIX_REGISTERED_SUCCESS); i++) {
6190 int vector = sp->entries[i].vector;
6191 void *arg = sp->s2io_entries[i].arg;
6192
6193 free_irq(vector, arg);
6194 }
6195 pci_read_config_word(sp->pdev, 0x42, &msi_control);
6196 msi_control &= 0xFFFE; /* Disable MSI */
6197 pci_write_config_word(sp->pdev, 0x42, msi_control);
6198
6199 pci_disable_msix(sp->pdev);
6200 } else {
6201 free_irq(sp->pdev->irq, dev);
6202 if (sp->intr_type == MSI) {
6203 u16 val;
6204
6205 pci_disable_msi(sp->pdev);
6206 pci_read_config_word(sp->pdev, 0x4c, &val);
6207 val ^= 0x1;
6208 pci_write_config_word(sp->pdev, 0x4c, val);
c92ca04b
AR		 6209 }
6210 }
6211 /* Waiting till all Interrupt handlers are complete */
6212 cnt = 0;
6213 do {
6214 msleep(10);
6215 if (!atomic_read(&sp->isr_cnt))
6216 break;
6217 cnt++;
6218 } while(cnt < 5);
e6a8fee2
AR		 6219}
6220
6221static void s2io_card_down(nic_t * sp)
6222{
6223 int cnt = 0;
6224 XENA_dev_config_t __iomem *bar0 = sp->bar0;
6225 unsigned long flags;
6226 register u64 val64 = 0;
6227
6228 del_timer_sync(&sp->alarm_timer);
6229 /* If s2io_set_link task is executing, wait till it completes. */
6230 while (test_and_set_bit(0, &(sp->link_state))) {
6231 msleep(50);
6232 }
6233 atomic_set(&sp->card_state, CARD_DOWN);
6234
6235 /* disable Tx and Rx traffic on the NIC */
6236 stop_nic(sp);
6237
6238 s2io_rem_isr(sp);
1da177e4
LT		 6239
6240 /* Kill tasklet. */
6241 tasklet_kill(&sp->task);
6242
6243 /* Check if the device is Quiescent and then Reset the NIC */
6244 do {
5d3213cc
AR		 6245 /* As per the HW requirement we need to replenish the
6246 * receive buffer to avoid the ring bump. Since there is
6247 * no intention of processing the Rx frame at this pointwe are
6248 * just settting the ownership bit of rxd in Each Rx
6249 * ring to HW and set the appropriate buffer size
6250 * based on the ring mode
6251 */
6252 rxd_owner_bit_reset(sp);
6253
1da177e4 6254 val64 = readq(&bar0->adapter_status);
20346722 6255 if (verify_xena_quiescence(sp, val64, sp->device_enabled_once)) {
1da177e4
LT		 6256 break;
6257 }
6258
6259 msleep(50);
6260 cnt++;
6261 if (cnt == 10) {
6262 DBG_PRINT(ERR_DBG,
6263 "s2io_close:Device not Quiescent ");
6264 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
6265 (unsigned long long) val64);
6266 break;
6267 }
6268 } while (1);
1da177e4
LT		 6269 s2io_reset(sp);
6270
7ba013ac
K		 6271 spin_lock_irqsave(&sp->tx_lock, flags);
6272 /* Free all Tx buffers */
1da177e4 6273 free_tx_buffers(sp);
7ba013ac
K		 6274 spin_unlock_irqrestore(&sp->tx_lock, flags);
6275
6276 /* Free all Rx buffers */
6277 spin_lock_irqsave(&sp->rx_lock, flags);
1da177e4 6278 free_rx_buffers(sp);
7ba013ac 6279 spin_unlock_irqrestore(&sp->rx_lock, flags);
1da177e4 6280
1da177e4
LT		 6281 clear_bit(0, &(sp->link_state));
6282}
6283
6284static int s2io_card_up(nic_t * sp)
6285{
cc6e7c44 6286 int i, ret = 0;
1da177e4
LT		 6287 mac_info_t *mac_control;
6288 struct config_param *config;
6289 struct net_device *dev = (struct net_device *) sp->dev;
e6a8fee2 6290 u16 interruptible;
1da177e4
LT		 6291
6292 /* Initialize the H/W I/O registers */
6293 if (init_nic(sp) != 0) {
6294 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
6295 dev->name);
e6a8fee2 6296 s2io_reset(sp);
1da177e4
LT		 6297 return -ENODEV;
6298 }
6299
20346722
K		 6300 /*
6301 * Initializing the Rx buffers. For now we are considering only 1
1da177e4
LT		 6302 * Rx ring and initializing buffers into 30 Rx blocks
6303 */
6304 mac_control = &sp->mac_control;
6305 config = &sp->config;
6306
6307 for (i = 0; i < config->rx_ring_num; i++) {
6308 if ((ret = fill_rx_buffers(sp, i))) {
6309 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
6310 dev->name);
6311 s2io_reset(sp);
6312 free_rx_buffers(sp);
6313 return -ENOMEM;
6314 }
6315 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
6316 atomic_read(&sp->rx_bufs_left[i]));
6317 }
6318
6319 /* Setting its receive mode */
6320 s2io_set_multicast(dev);
6321
7d3d0439 6322 if (sp->lro) {
b41477f3 6323 /* Initialize max aggregatable pkts per session based on MTU */
7d3d0439
RA		 6324 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
6325 /* Check if we can use(if specified) user provided value */
6326 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
6327 sp->lro_max_aggr_per_sess = lro_max_pkts;
6328 }
6329
1da177e4
LT		 6330 /* Enable Rx Traffic and interrupts on the NIC */
6331 if (start_nic(sp)) {
6332 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
1da177e4 6333 s2io_reset(sp);
e6a8fee2
AR		 6334 free_rx_buffers(sp);
6335 return -ENODEV;
6336 }
6337
6338 /* Add interrupt service routine */
6339 if (s2io_add_isr(sp) != 0) {
6340 if (sp->intr_type == MSI_X)
6341 s2io_rem_isr(sp);
6342 s2io_reset(sp);
1da177e4
LT		 6343 free_rx_buffers(sp);
6344 return -ENODEV;
6345 }
6346
25fff88e
K		 6347 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
6348
e6a8fee2
AR		 6349 /* Enable tasklet for the device */
6350 tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
6351
6352 /* Enable select interrupts */
6353 if (sp->intr_type != INTA)
6354 en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS);
6355 else {
6356 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
6357 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
6358 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
6359 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
6360 }
6361
6362
1da177e4
LT		 6363 atomic_set(&sp->card_state, CARD_UP);
6364 return 0;
6365}
6366
20346722 6367/**
1da177e4
LT		 6368 * s2io_restart_nic - Resets the NIC.
6369 * @data : long pointer to the device private structure
6370 * Description:
6371 * This function is scheduled to be run by the s2io_tx_watchdog
20346722 6372 * function after 0.5 secs to reset the NIC. The idea is to reduce
1da177e4
LT		 6373 * the run time of the watch dog routine which is run holding a
6374 * spin lock.
6375 */
6376
c4028958 6377static void s2io_restart_nic(struct work_struct *work)
1da177e4 6378{
c4028958
DH		 6379 nic_t *sp = container_of(work, nic_t, rst_timer_task);
6380 struct net_device *dev = sp->dev;
1da177e4 6381
e6a8fee2 6382 s2io_card_down(sp);
1da177e4
LT		 6383 if (s2io_card_up(sp)) {
6384 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6385 dev->name);
6386 }
6387 netif_wake_queue(dev);
6388 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
6389 dev->name);
20346722 6390
1da177e4
LT		 6391}
6392
20346722
K		 6393/**
6394 * s2io_tx_watchdog - Watchdog for transmit side.
1da177e4
LT		 6395 * @dev : Pointer to net device structure
6396 * Description:
6397 * This function is triggered if the Tx Queue is stopped
6398 * for a pre-defined amount of time when the Interface is still up.
6399 * If the Interface is jammed in such a situation, the hardware is
6400 * reset (by s2io_close) and restarted again (by s2io_open) to
6401 * overcome any problem that might have been caused in the hardware.
6402 * Return value:
6403 * void
6404 */
6405
6406static void s2io_tx_watchdog(struct net_device *dev)
6407{
6408 nic_t *sp = dev->priv;
6409
6410 if (netif_carrier_ok(dev)) {
6411 schedule_work(&sp->rst_timer_task);
bd1034f0 6412 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
1da177e4
LT		 6413 }
6414}
6415
6416/**
6417 * rx_osm_handler - To perform some OS related operations on SKB.
6418 * @sp: private member of the device structure,pointer to s2io_nic structure.
6419 * @skb : the socket buffer pointer.
6420 * @len : length of the packet
6421 * @cksum : FCS checksum of the frame.
6422 * @ring_no : the ring from which this RxD was extracted.
20346722 6423 * Description:
b41477f3 6424 * This function is called by the Rx interrupt serivce routine to perform
1da177e4
LT		 6425 * some OS related operations on the SKB before passing it to the upper
6426 * layers. It mainly checks if the checksum is OK, if so adds it to the
6427 * SKBs cksum variable, increments the Rx packet count and passes the SKB
6428 * to the upper layer. If the checksum is wrong, it increments the Rx
6429 * packet error count, frees the SKB and returns error.
6430 * Return value:
6431 * SUCCESS on success and -1 on failure.
6432 */
20346722 6433static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp)
1da177e4 6434{
20346722 6435 nic_t *sp = ring_data->nic;
1da177e4 6436 struct net_device *dev = (struct net_device *) sp->dev;
20346722
K		 6437 struct sk_buff *skb = (struct sk_buff *)
6438 ((unsigned long) rxdp->Host_Control);
6439 int ring_no = ring_data->ring_no;
1da177e4 6440 u16 l3_csum, l4_csum;
863c11a9 6441 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
7d3d0439 6442 lro_t *lro;
da6971d8 6443
20346722 6444 skb->dev = dev;
c92ca04b 6445
863c11a9 6446 if (err) {
bd1034f0
AR		 6447 /* Check for parity error */
6448 if (err & 0x1) {
6449 sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
6450 }
6451
863c11a9
AR		 6452 /*
6453 * Drop the packet if bad transfer code. Exception being
6454 * 0x5, which could be due to unsupported IPv6 extension header.
6455 * In this case, we let stack handle the packet.
6456 * Note that in this case, since checksum will be incorrect,
6457 * stack will validate the same.
6458 */
6459 if (err && ((err >> 48) != 0x5)) {
6460 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
6461 dev->name, err);
6462 sp->stats.rx_crc_errors++;
6463 dev_kfree_skb(skb);
6464 atomic_dec(&sp->rx_bufs_left[ring_no]);
6465 rxdp->Host_Control = 0;
6466 return 0;
6467 }
20346722 6468 }
1da177e4 6469
20346722
K		 6470 /* Updating statistics */
6471 rxdp->Host_Control = 0;
6472 sp->rx_pkt_count++;
6473 sp->stats.rx_packets++;
da6971d8
AR		 6474 if (sp->rxd_mode == RXD_MODE_1) {
6475 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
20346722 6476
da6971d8
AR		 6477 sp->stats.rx_bytes += len;
6478 skb_put(skb, len);
6479
6480 } else if (sp->rxd_mode >= RXD_MODE_3A) {
6481 int get_block = ring_data->rx_curr_get_info.block_index;
6482 int get_off = ring_data->rx_curr_get_info.offset;
6483 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
6484 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
6485 unsigned char *buff = skb_push(skb, buf0_len);
6486
6487 buffAdd_t *ba = &ring_data->ba[get_block][get_off];
6488 sp->stats.rx_bytes += buf0_len + buf2_len;
6489 memcpy(buff, ba->ba_0, buf0_len);
6490
6491 if (sp->rxd_mode == RXD_MODE_3A) {
6492 int buf1_len = RXD_GET_BUFFER1_SIZE_3(rxdp->Control_2);
6493
6494 skb_put(skb, buf1_len);
6495 skb->len += buf2_len;
6496 skb->data_len += buf2_len;
6497 skb->truesize += buf2_len;
6498 skb_put(skb_shinfo(skb)->frag_list, buf2_len);
6499 sp->stats.rx_bytes += buf1_len;
6500
6501 } else
6502 skb_put(skb, buf2_len);
6503 }
20346722 6504
7d3d0439
RA		 6505 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!sp->lro) ||
6506 (sp->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
20346722
K		 6507 (sp->rx_csum)) {
6508 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
1da177e4
LT		 6509 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
6510 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
20346722 6511 /*
1da177e4
LT		 6512 * NIC verifies if the Checksum of the received
6513 * frame is Ok or not and accordingly returns
6514 * a flag in the RxD.
6515 */
6516 skb->ip_summed = CHECKSUM_UNNECESSARY;
7d3d0439
RA		 6517 if (sp->lro) {
6518 u32 tcp_len;
6519 u8 *tcp;
6520 int ret = 0;
6521
6522 ret = s2io_club_tcp_session(skb->data, &tcp,
6523 &tcp_len, &lro, rxdp, sp);
6524 switch (ret) {
6525 case 3: /* Begin anew */
6526 lro->parent = skb;
6527 goto aggregate;
6528 case 1: /* Aggregate */
6529 {
6530 lro_append_pkt(sp, lro,
6531 skb, tcp_len);
6532 goto aggregate;
6533 }
6534 case 4: /* Flush session */
6535 {
6536 lro_append_pkt(sp, lro,
6537 skb, tcp_len);
6538 queue_rx_frame(lro->parent);
6539 clear_lro_session(lro);
6540 sp->mac_control.stats_info->
6541 sw_stat.flush_max_pkts++;
6542 goto aggregate;
6543 }
6544 case 2: /* Flush both */
6545 lro->parent->data_len =
6546 lro->frags_len;
6547 sp->mac_control.stats_info->
6548 sw_stat.sending_both++;
6549 queue_rx_frame(lro->parent);
6550 clear_lro_session(lro);
6551 goto send_up;
6552 case 0: /* sessions exceeded */
c92ca04b
AR		 6553 case -1: /* non-TCP or not
6554 * L2 aggregatable
6555 */
7d3d0439
RA		 6556 case 5: /*
6557 * First pkt in session not
6558 * L3/L4 aggregatable
6559 */
6560 break;
6561 default:
6562 DBG_PRINT(ERR_DBG,
6563 "%s: Samadhana!!\n",
6564 __FUNCTION__);
6565 BUG();
6566 }
6567 }
1da177e4 6568 } else {
20346722
K		 6569 /*
6570 * Packet with erroneous checksum, let the
1da177e4
LT		 6571 * upper layers deal with it.
6572 */
6573 skb->ip_summed = CHECKSUM_NONE;
6574 }
6575 } else {
6576 skb->ip_summed = CHECKSUM_NONE;
6577 }
6578
7d3d0439
RA		 6579 if (!sp->lro) {
6580 skb->protocol = eth_type_trans(skb, dev);
7d3d0439
RA		 6581 if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
6582 /* Queueing the vlan frame to the upper layer */
db874e65
SS		 6583 if (napi)
6584 vlan_hwaccel_receive_skb(skb, sp->vlgrp,
6585 RXD_GET_VLAN_TAG(rxdp->Control_2));
6586 else
6587 vlan_hwaccel_rx(skb, sp->vlgrp,
6588 RXD_GET_VLAN_TAG(rxdp->Control_2));
7d3d0439 6589 } else {
db874e65
SS		 6590 if (napi)
6591 netif_receive_skb(skb);
6592 else
6593 netif_rx(skb);
7d3d0439 6594 }
7d3d0439
RA		 6595 } else {
6596send_up:
6597 queue_rx_frame(skb);
6aa20a22 6598 }
1da177e4 6599 dev->last_rx = jiffies;
7d3d0439 6600aggregate:
1da177e4 6601 atomic_dec(&sp->rx_bufs_left[ring_no]);
1da177e4
LT		 6602 return SUCCESS;
6603}
6604
6605/**
6606 * s2io_link - stops/starts the Tx queue.
6607 * @sp : private member of the device structure, which is a pointer to the
6608 * s2io_nic structure.
6609 * @link : inidicates whether link is UP/DOWN.
6610 * Description:
6611 * This function stops/starts the Tx queue depending on whether the link
20346722
K		 6612 * status of the NIC is is down or up. This is called by the Alarm
6613 * interrupt handler whenever a link change interrupt comes up.
1da177e4
LT		 6614 * Return value:
6615 * void.
6616 */
6617
26df54bf 6618static void s2io_link(nic_t * sp, int link)
1da177e4
LT		 6619{
6620 struct net_device *dev = (struct net_device *) sp->dev;
6621
6622 if (link != sp->last_link_state) {
6623 if (link == LINK_DOWN) {
6624 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
6625 netif_carrier_off(dev);
6626 } else {
6627 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
6628 netif_carrier_on(dev);
6629 }
6630 }
6631 sp->last_link_state = link;
6632}
6633
6634/**
20346722
K		 6635 * get_xena_rev_id - to identify revision ID of xena.
6636 * @pdev : PCI Dev structure
6637 * Description:
6638 * Function to identify the Revision ID of xena.
6639 * Return value:
6640 * returns the revision ID of the device.
6641 */
6642
26df54bf 6643static int get_xena_rev_id(struct pci_dev *pdev)
20346722
K		 6644{
6645 u8 id = 0;
6646 int ret;
6647 ret = pci_read_config_byte(pdev, PCI_REVISION_ID, (u8 *) & id);
6648 return id;
6649}
6650
6651/**
6652 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
6653 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 6654 * s2io_nic structure.
6655 * Description:
6656 * This function initializes a few of the PCI and PCI-X configuration registers
6657 * with recommended values.
6658 * Return value:
6659 * void
6660 */
6661
6662static void s2io_init_pci(nic_t * sp)
6663{
20346722 6664 u16 pci_cmd = 0, pcix_cmd = 0;
1da177e4
LT		 6665
6666 /* Enable Data Parity Error Recovery in PCI-X command register. */
6667 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 6668 &(pcix_cmd));
1da177e4 6669 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 6670 (pcix_cmd | 1));
1da177e4 6671 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 6672 &(pcix_cmd));
1da177e4
LT		 6673
6674 /* Set the PErr Response bit in PCI command register. */
6675 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
6676 pci_write_config_word(sp->pdev, PCI_COMMAND,
6677 (pci_cmd | PCI_COMMAND_PARITY));
6678 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
1da177e4
LT		 6679}
6680
9dc737a7
AR		 6681static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
6682{
6683 if ( tx_fifo_num > 8) {
6684 DBG_PRINT(ERR_DBG, "s2io: Requested number of Tx fifos not "
6685 "supported\n");
6686 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Tx fifos\n");
6687 tx_fifo_num = 8;
6688 }
6689 if ( rx_ring_num > 8) {
6690 DBG_PRINT(ERR_DBG, "s2io: Requested number of Rx rings not "
6691 "supported\n");
6692 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
6693 rx_ring_num = 8;
6694 }
db874e65
SS		 6695 if (*dev_intr_type != INTA)
6696 napi = 0;
6697
9dc737a7
AR		 6698#ifndef CONFIG_PCI_MSI
6699 if (*dev_intr_type != INTA) {
6700 DBG_PRINT(ERR_DBG, "s2io: This kernel does not support"
6701 "MSI/MSI-X. Defaulting to INTA\n");
6702 *dev_intr_type = INTA;
6703 }
6704#else
6705 if (*dev_intr_type > MSI_X) {
6706 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
6707 "Defaulting to INTA\n");
6708 *dev_intr_type = INTA;
6709 }
6710#endif
6711 if ((*dev_intr_type == MSI_X) &&
6712 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
6713 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
6aa20a22 6714 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
9dc737a7
AR		 6715 "Defaulting to INTA\n");
6716 *dev_intr_type = INTA;
6717 }
6718 if (rx_ring_mode > 3) {
6719 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
6720 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 3-buffer mode\n");
6721 rx_ring_mode = 3;
6722 }
6723 return SUCCESS;
6724}
6725
1da177e4 6726/**
20346722 6727 * s2io_init_nic - Initialization of the adapter .
1da177e4
LT		 6728 * @pdev : structure containing the PCI related information of the device.
6729 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
6730 * Description:
6731 * The function initializes an adapter identified by the pci_dec structure.
20346722
K		 6732 * All OS related initialization including memory and device structure and
6733 * initlaization of the device private variable is done. Also the swapper
6734 * control register is initialized to enable read and write into the I/O
1da177e4
LT		 6735 * registers of the device.
6736 * Return value:
6737 * returns 0 on success and negative on failure.
6738 */
6739
6740static int __devinit
6741s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
6742{
6743 nic_t *sp;
6744 struct net_device *dev;
1da177e4
LT		 6745 int i, j, ret;
6746 int dma_flag = FALSE;
6747 u32 mac_up, mac_down;
6748 u64 val64 = 0, tmp64 = 0;
6749 XENA_dev_config_t __iomem *bar0 = NULL;
6750 u16 subid;
6751 mac_info_t *mac_control;
6752 struct config_param *config;
541ae68f 6753 int mode;
cc6e7c44 6754 u8 dev_intr_type = intr_type;
1da177e4 6755
9dc737a7
AR		 6756 if ((ret = s2io_verify_parm(pdev, &dev_intr_type)))
6757 return ret;
1da177e4
LT		 6758
6759 if ((ret = pci_enable_device(pdev))) {
6760 DBG_PRINT(ERR_DBG,
6761 "s2io_init_nic: pci_enable_device failed\n");
6762 return ret;
6763 }
6764
1e7f0bd8 6765 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 6766 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
6767 dma_flag = TRUE;
1da177e4 6768 if (pci_set_consistent_dma_mask
1e7f0bd8 6769 (pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 6770 DBG_PRINT(ERR_DBG,
6771 "Unable to obtain 64bit DMA for \
6772 consistent allocations\n");
6773 pci_disable_device(pdev);
6774 return -ENOMEM;
6775 }
1e7f0bd8 6776 } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1da177e4
LT		 6777 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
6778 } else {
6779 pci_disable_device(pdev);
6780 return -ENOMEM;
6781 }
cc6e7c44
RA		 6782 if (dev_intr_type != MSI_X) {
6783 if (pci_request_regions(pdev, s2io_driver_name)) {
b41477f3
AR		 6784 DBG_PRINT(ERR_DBG, "Request Regions failed\n");
6785 pci_disable_device(pdev);
cc6e7c44
RA		 6786 return -ENODEV;
6787 }
6788 }
6789 else {
6790 if (!(request_mem_region(pci_resource_start(pdev, 0),
6791 pci_resource_len(pdev, 0), s2io_driver_name))) {
6792 DBG_PRINT(ERR_DBG, "bar0 Request Regions failed\n");
6793 pci_disable_device(pdev);
6794 return -ENODEV;
6795 }
6796 if (!(request_mem_region(pci_resource_start(pdev, 2),
6797 pci_resource_len(pdev, 2), s2io_driver_name))) {
6798 DBG_PRINT(ERR_DBG, "bar1 Request Regions failed\n");
6799 release_mem_region(pci_resource_start(pdev, 0),
6800 pci_resource_len(pdev, 0));
6801 pci_disable_device(pdev);
6802 return -ENODEV;
6803 }
1da177e4
LT		 6804 }
6805
6806 dev = alloc_etherdev(sizeof(nic_t));
6807 if (dev == NULL) {
6808 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
6809 pci_disable_device(pdev);
6810 pci_release_regions(pdev);
6811 return -ENODEV;
6812 }
6813
6814 pci_set_master(pdev);
6815 pci_set_drvdata(pdev, dev);
6816 SET_MODULE_OWNER(dev);
6817 SET_NETDEV_DEV(dev, &pdev->dev);
6818
6819 /* Private member variable initialized to s2io NIC structure */
6820 sp = dev->priv;
6821 memset(sp, 0, sizeof(nic_t));
6822 sp->dev = dev;
6823 sp->pdev = pdev;
1da177e4 6824 sp->high_dma_flag = dma_flag;
1da177e4 6825 sp->device_enabled_once = FALSE;
da6971d8
AR		 6826 if (rx_ring_mode == 1)
6827 sp->rxd_mode = RXD_MODE_1;
6828 if (rx_ring_mode == 2)
6829 sp->rxd_mode = RXD_MODE_3B;
6830 if (rx_ring_mode == 3)
6831 sp->rxd_mode = RXD_MODE_3A;
6832
cc6e7c44 6833 sp->intr_type = dev_intr_type;
1da177e4 6834
541ae68f
K		 6835 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
6836 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
6837 sp->device_type = XFRAME_II_DEVICE;
6838 else
6839 sp->device_type = XFRAME_I_DEVICE;
6840
7d3d0439 6841 sp->lro = lro;
6aa20a22 6842
1da177e4
LT		 6843 /* Initialize some PCI/PCI-X fields of the NIC. */
6844 s2io_init_pci(sp);
6845
20346722 6846 /*
1da177e4 6847 * Setting the device configuration parameters.
20346722
K		 6848 * Most of these parameters can be specified by the user during
6849 * module insertion as they are module loadable parameters. If
6850 * these parameters are not not specified during load time, they
1da177e4
LT		 6851 * are initialized with default values.
6852 */
6853 mac_control = &sp->mac_control;
6854 config = &sp->config;
6855
6856 /* Tx side parameters. */
1da177e4
LT		 6857 config->tx_fifo_num = tx_fifo_num;
6858 for (i = 0; i < MAX_TX_FIFOS; i++) {
6859 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
6860 config->tx_cfg[i].fifo_priority = i;
6861 }
6862
20346722
K		 6863 /* mapping the QoS priority to the configured fifos */
6864 for (i = 0; i < MAX_TX_FIFOS; i++)
6865 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
6866
1da177e4
LT		 6867 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
6868 for (i = 0; i < config->tx_fifo_num; i++) {
6869 config->tx_cfg[i].f_no_snoop =
6870 (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
6871 if (config->tx_cfg[i].fifo_len < 65) {
6872 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
6873 break;
6874 }
6875 }
fed5eccd
AR		 6876 /* + 2 because one Txd for skb->data and one Txd for UFO */
6877 config->max_txds = MAX_SKB_FRAGS + 2;
1da177e4
LT		 6878
6879 /* Rx side parameters. */
1da177e4
LT		 6880 config->rx_ring_num = rx_ring_num;
6881 for (i = 0; i < MAX_RX_RINGS; i++) {
6882 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
da6971d8 6883 (rxd_count[sp->rxd_mode] + 1);
1da177e4
LT		 6884 config->rx_cfg[i].ring_priority = i;
6885 }
6886
6887 for (i = 0; i < rx_ring_num; i++) {
6888 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
6889 config->rx_cfg[i].f_no_snoop =
6890 (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
6891 }
6892
6893 /* Setting Mac Control parameters */
6894 mac_control->rmac_pause_time = rmac_pause_time;
6895 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
6896 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
6897
6898
6899 /* Initialize Ring buffer parameters. */
6900 for (i = 0; i < config->rx_ring_num; i++)
6901 atomic_set(&sp->rx_bufs_left[i], 0);
6902
7ba013ac
K		 6903 /* Initialize the number of ISRs currently running */
6904 atomic_set(&sp->isr_cnt, 0);
6905
1da177e4
LT		 6906 /* initialize the shared memory used by the NIC and the host */
6907 if (init_shared_mem(sp)) {
6908 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
b41477f3 6909 dev->name);
1da177e4
LT		 6910 ret = -ENOMEM;
6911 goto mem_alloc_failed;
6912 }
6913
6914 sp->bar0 = ioremap(pci_resource_start(pdev, 0),
6915 pci_resource_len(pdev, 0));
6916 if (!sp->bar0) {
6917 DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem1\n",
6918 dev->name);
6919 ret = -ENOMEM;
6920 goto bar0_remap_failed;
6921 }
6922
6923 sp->bar1 = ioremap(pci_resource_start(pdev, 2),
6924 pci_resource_len(pdev, 2));
6925 if (!sp->bar1) {
6926 DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem2\n",
6927 dev->name);
6928 ret = -ENOMEM;
6929 goto bar1_remap_failed;
6930 }
6931
6932 dev->irq = pdev->irq;
6933 dev->base_addr = (unsigned long) sp->bar0;
6934
6935 /* Initializing the BAR1 address as the start of the FIFO pointer. */
6936 for (j = 0; j < MAX_TX_FIFOS; j++) {
6937 mac_control->tx_FIFO_start[j] = (TxFIFO_element_t __iomem *)
6938 (sp->bar1 + (j * 0x00020000));
6939 }
6940
6941 /* Driver entry points */
6942 dev->open = &s2io_open;
6943 dev->stop = &s2io_close;
6944 dev->hard_start_xmit = &s2io_xmit;
6945 dev->get_stats = &s2io_get_stats;
6946 dev->set_multicast_list = &s2io_set_multicast;
6947 dev->do_ioctl = &s2io_ioctl;
6948 dev->change_mtu = &s2io_change_mtu;
6949 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
be3a6b02
K		 6950 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6951 dev->vlan_rx_register = s2io_vlan_rx_register;
6952 dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;
20346722 6953
1da177e4
LT		 6954 /*
6955 * will use eth_mac_addr() for dev->set_mac_address
6956 * mac address will be set every time dev->open() is called
6957 */
1da177e4 6958 dev->poll = s2io_poll;
20346722 6959 dev->weight = 32;
1da177e4 6960
612eff0e
BH		 6961#ifdef CONFIG_NET_POLL_CONTROLLER
6962 dev->poll_controller = s2io_netpoll;
6963#endif
6964
1da177e4
LT		 6965 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
6966 if (sp->high_dma_flag == TRUE)
6967 dev->features |= NETIF_F_HIGHDMA;
1da177e4 6968 dev->features |= NETIF_F_TSO;
f83ef8c0 6969 dev->features |= NETIF_F_TSO6;
db874e65 6970 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
fed5eccd
AR		 6971 dev->features |= NETIF_F_UFO;
6972 dev->features |= NETIF_F_HW_CSUM;
6973 }
1da177e4
LT		 6974
6975 dev->tx_timeout = &s2io_tx_watchdog;
6976 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
c4028958
DH		 6977 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
6978 INIT_WORK(&sp->set_link_task, s2io_set_link);
1da177e4 6979
e960fc5c 6980 pci_save_state(sp->pdev);
1da177e4
LT		 6981
6982 /* Setting swapper control on the NIC, for proper reset operation */
6983 if (s2io_set_swapper(sp)) {
6984 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
6985 dev->name);
6986 ret = -EAGAIN;
6987 goto set_swap_failed;
6988 }
6989
541ae68f
K		 6990 /* Verify if the Herc works on the slot its placed into */
6991 if (sp->device_type & XFRAME_II_DEVICE) {
6992 mode = s2io_verify_pci_mode(sp);
6993 if (mode < 0) {
6994 DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
6995 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
6996 ret = -EBADSLT;
6997 goto set_swap_failed;
6998 }
6999 }
7000
7001 /* Not needed for Herc */
7002 if (sp->device_type & XFRAME_I_DEVICE) {
7003 /*
7004 * Fix for all "FFs" MAC address problems observed on
7005 * Alpha platforms
7006 */
7007 fix_mac_address(sp);
7008 s2io_reset(sp);
7009 }
1da177e4
LT		 7010
7011 /*
1da177e4
LT		 7012 * MAC address initialization.
7013 * For now only one mac address will be read and used.
7014 */
7015 bar0 = sp->bar0;
7016 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
7017 RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
7018 writeq(val64, &bar0->rmac_addr_cmd_mem);
c92ca04b
AR		 7019 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
7020 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
1da177e4
LT		 7021 tmp64 = readq(&bar0->rmac_addr_data0_mem);
7022 mac_down = (u32) tmp64;
7023 mac_up = (u32) (tmp64 >> 32);
7024
7025 memset(sp->def_mac_addr[0].mac_addr, 0, sizeof(ETH_ALEN));
7026
7027 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
7028 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
7029 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
7030 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
7031 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
7032 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
7033
1da177e4
LT		 7034 /* Set the factory defined MAC address initially */
7035 dev->addr_len = ETH_ALEN;
7036 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
7037
b41477f3
AR		 7038 /* reset Nic and bring it to known state */
7039 s2io_reset(sp);
7040
1da177e4 7041 /*
20346722 7042 * Initialize the tasklet status and link state flags
541ae68f 7043 * and the card state parameter
1da177e4
LT		 7044 */
7045 atomic_set(&(sp->card_state), 0);
7046 sp->tasklet_status = 0;
7047 sp->link_state = 0;
7048
1da177e4
LT		 7049 /* Initialize spinlocks */
7050 spin_lock_init(&sp->tx_lock);
db874e65
SS		 7051
7052 if (!napi)
7053 spin_lock_init(&sp->put_lock);
7ba013ac 7054 spin_lock_init(&sp->rx_lock);
1da177e4 7055
20346722
K		 7056 /*
7057 * SXE-002: Configure link and activity LED to init state
7058 * on driver load.
1da177e4
LT		 7059 */
7060 subid = sp->pdev->subsystem_device;
7061 if ((subid & 0xFF) >= 0x07) {
7062 val64 = readq(&bar0->gpio_control);
7063 val64 |= 0x0000800000000000ULL;
7064 writeq(val64, &bar0->gpio_control);
7065 val64 = 0x0411040400000000ULL;
7066 writeq(val64, (void __iomem *) bar0 + 0x2700);
7067 val64 = readq(&bar0->gpio_control);
7068 }
7069
7070 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
7071
7072 if (register_netdev(dev)) {
7073 DBG_PRINT(ERR_DBG, "Device registration failed\n");
7074 ret = -ENODEV;
7075 goto register_failed;
7076 }
9dc737a7 7077 s2io_vpd_read(sp);
9dc737a7 7078 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2005 Neterion Inc.\n");
b41477f3
AR		 7079 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
7080 sp->product_name, get_xena_rev_id(sp->pdev));
7081 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
7082 s2io_driver_version);
9dc737a7
AR		 7083 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: "
7084 "%02x:%02x:%02x:%02x:%02x:%02x\n", dev->name,
541ae68f
K		 7085 sp->def_mac_addr[0].mac_addr[0],
7086 sp->def_mac_addr[0].mac_addr[1],
7087 sp->def_mac_addr[0].mac_addr[2],
7088 sp->def_mac_addr[0].mac_addr[3],
7089 sp->def_mac_addr[0].mac_addr[4],
7090 sp->def_mac_addr[0].mac_addr[5]);
9dc737a7 7091 if (sp->device_type & XFRAME_II_DEVICE) {
0b1f7ebe 7092 mode = s2io_print_pci_mode(sp);
541ae68f 7093 if (mode < 0) {
9dc737a7 7094 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
541ae68f 7095 ret = -EBADSLT;
9dc737a7 7096 unregister_netdev(dev);
541ae68f
K		 7097 goto set_swap_failed;
7098 }
541ae68f 7099 }
9dc737a7
AR		 7100 switch(sp->rxd_mode) {
7101 case RXD_MODE_1:
7102 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
7103 dev->name);
7104 break;
7105 case RXD_MODE_3B:
7106 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
7107 dev->name);
7108 break;
7109 case RXD_MODE_3A:
7110 DBG_PRINT(ERR_DBG, "%s: 3-Buffer receive mode enabled\n",
7111 dev->name);
7112 break;
7113 }
db874e65
SS		 7114
7115 if (napi)
7116 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
9dc737a7
AR		 7117 switch(sp->intr_type) {
7118 case INTA:
7119 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
7120 break;
7121 case MSI:
7122 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI\n", dev->name);
7123 break;
7124 case MSI_X:
7125 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
7126 break;
7127 }
7d3d0439
RA		 7128 if (sp->lro)
7129 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
9dc737a7 7130 dev->name);
db874e65
SS		 7131 if (ufo)
7132 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
7133 " enabled\n", dev->name);
7ba013ac 7134 /* Initialize device name */
9dc737a7 7135 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7ba013ac 7136
b6e3f982
K		 7137 /* Initialize bimodal Interrupts */
7138 sp->config.bimodal = bimodal;
7139 if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
7140 sp->config.bimodal = 0;
7141 DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
7142 dev->name);
7143 }
7144
20346722
K		 7145 /*
7146 * Make Link state as off at this point, when the Link change
7147 * interrupt comes the state will be automatically changed to
1da177e4
LT		 7148 * the right state.
7149 */
7150 netif_carrier_off(dev);
1da177e4
LT		 7151
7152 return 0;
7153
7154 register_failed:
7155 set_swap_failed:
7156 iounmap(sp->bar1);
7157 bar1_remap_failed:
7158 iounmap(sp->bar0);
7159 bar0_remap_failed:
7160 mem_alloc_failed:
7161 free_shared_mem(sp);
7162 pci_disable_device(pdev);
cc6e7c44
RA		 7163 if (dev_intr_type != MSI_X)
7164 pci_release_regions(pdev);
7165 else {
7166 release_mem_region(pci_resource_start(pdev, 0),
7167 pci_resource_len(pdev, 0));
7168 release_mem_region(pci_resource_start(pdev, 2),
7169 pci_resource_len(pdev, 2));
7170 }
1da177e4
LT		 7171 pci_set_drvdata(pdev, NULL);
7172 free_netdev(dev);
7173
7174 return ret;
7175}
7176
7177/**
20346722 7178 * s2io_rem_nic - Free the PCI device
1da177e4 7179 * @pdev: structure containing the PCI related information of the device.
20346722 7180 * Description: This function is called by the Pci subsystem to release a
1da177e4 7181 * PCI device and free up all resource held up by the device. This could
20346722 7182 * be in response to a Hot plug event or when the driver is to be removed
1da177e4
LT		 7183 * from memory.
7184 */
7185
7186static void __devexit s2io_rem_nic(struct pci_dev *pdev)
7187{
7188 struct net_device *dev =
7189 (struct net_device *) pci_get_drvdata(pdev);
7190 nic_t *sp;
7191
7192 if (dev == NULL) {
7193 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
7194 return;
7195 }
7196
7197 sp = dev->priv;
7198 unregister_netdev(dev);
7199
7200 free_shared_mem(sp);
7201 iounmap(sp->bar0);
7202 iounmap(sp->bar1);
7203 pci_disable_device(pdev);
cc6e7c44
RA		 7204 if (sp->intr_type != MSI_X)
7205 pci_release_regions(pdev);
7206 else {
7207 release_mem_region(pci_resource_start(pdev, 0),
7208 pci_resource_len(pdev, 0));
7209 release_mem_region(pci_resource_start(pdev, 2),
7210 pci_resource_len(pdev, 2));
7211 }
1da177e4 7212 pci_set_drvdata(pdev, NULL);
1da177e4
LT		 7213 free_netdev(dev);
7214}
7215
7216/**
7217 * s2io_starter - Entry point for the driver
7218 * Description: This function is the entry point for the driver. It verifies
7219 * the module loadable parameters and initializes PCI configuration space.
7220 */
7221
7222int __init s2io_starter(void)
7223{
29917620 7224 return pci_register_driver(&s2io_driver);
1da177e4
LT		 7225}
7226
7227/**
20346722 7228 * s2io_closer - Cleanup routine for the driver
1da177e4
LT		 7229 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
7230 */
7231
26df54bf 7232static void s2io_closer(void)
1da177e4
LT		 7233{
7234 pci_unregister_driver(&s2io_driver);
7235 DBG_PRINT(INIT_DBG, "cleanup done\n");
7236}
7237
7238module_init(s2io_starter);
7239module_exit(s2io_closer);
7d3d0439 7240
6aa20a22 7241static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
7d3d0439
RA		 7242 struct tcphdr **tcp, RxD_t *rxdp)
7243{
7244 int ip_off;
7245 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
7246
7247 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
7248 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
7249 __FUNCTION__);
7250 return -1;
7251 }
7252
7253 /* TODO:
7254 * By default the VLAN field in the MAC is stripped by the card, if this
7255 * feature is turned off in rx_pa_cfg register, then the ip_off field
7256 * has to be shifted by a further 2 bytes
7257 */
7258 switch (l2_type) {
7259 case 0: /* DIX type */
7260 case 4: /* DIX type with VLAN */
7261 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
7262 break;
7263 /* LLC, SNAP etc are considered non-mergeable */
7264 default:
7265 return -1;
7266 }
7267
7268 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
7269 ip_len = (u8)((*ip)->ihl);
7270 ip_len <<= 2;
7271 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
7272
7273 return 0;
7274}
7275
7276static int check_for_socket_match(lro_t *lro, struct iphdr *ip,
7277 struct tcphdr *tcp)
7278{
7279 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7280 if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
7281 (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
7282 return -1;
7283 return 0;
7284}
7285
7286static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
7287{
7288 return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
7289}
7290
7291static void initiate_new_session(lro_t *lro, u8 *l2h,
7292 struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len)
7293{
7294 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7295 lro->l2h = l2h;
7296 lro->iph = ip;
7297 lro->tcph = tcp;
7298 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
7299 lro->tcp_ack = ntohl(tcp->ack_seq);
7300 lro->sg_num = 1;
7301 lro->total_len = ntohs(ip->tot_len);
7302 lro->frags_len = 0;
6aa20a22 7303 /*
7d3d0439
RA		 7304 * check if we saw TCP timestamp. Other consistency checks have
7305 * already been done.
7306 */
7307 if (tcp->doff == 8) {
7308 u32 *ptr;
7309 ptr = (u32 *)(tcp+1);
7310 lro->saw_ts = 1;
7311 lro->cur_tsval = *(ptr+1);
7312 lro->cur_tsecr = *(ptr+2);
7313 }
7314 lro->in_use = 1;
7315}
7316
7317static void update_L3L4_header(nic_t *sp, lro_t *lro)
7318{
7319 struct iphdr *ip = lro->iph;
7320 struct tcphdr *tcp = lro->tcph;
7321 u16 nchk;
7322 StatInfo_t *statinfo = sp->mac_control.stats_info;
7323 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7324
7325 /* Update L3 header */
7326 ip->tot_len = htons(lro->total_len);
7327 ip->check = 0;
7328 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
7329 ip->check = nchk;
7330
7331 /* Update L4 header */
7332 tcp->ack_seq = lro->tcp_ack;
7333 tcp->window = lro->window;
7334
7335 /* Update tsecr field if this session has timestamps enabled */
7336 if (lro->saw_ts) {
7337 u32 *ptr = (u32 *)(tcp + 1);
7338 *(ptr+2) = lro->cur_tsecr;
7339 }
7340
7341 /* Update counters required for calculation of
7342 * average no. of packets aggregated.
7343 */
7344 statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
7345 statinfo->sw_stat.num_aggregations++;
7346}
7347
7348static void aggregate_new_rx(lro_t *lro, struct iphdr *ip,
7349 struct tcphdr *tcp, u32 l4_pyld)
7350{
7351 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7352 lro->total_len += l4_pyld;
7353 lro->frags_len += l4_pyld;
7354 lro->tcp_next_seq += l4_pyld;
7355 lro->sg_num++;
7356
7357 /* Update ack seq no. and window ad(from this pkt) in LRO object */
7358 lro->tcp_ack = tcp->ack_seq;
7359 lro->window = tcp->window;
6aa20a22 7360
7d3d0439
RA		 7361 if (lro->saw_ts) {
7362 u32 *ptr;
7363 /* Update tsecr and tsval from this packet */
7364 ptr = (u32 *) (tcp + 1);
6aa20a22 7365 lro->cur_tsval = *(ptr + 1);
7d3d0439
RA		 7366 lro->cur_tsecr = *(ptr + 2);
7367 }
7368}
7369
7370static int verify_l3_l4_lro_capable(lro_t *l_lro, struct iphdr *ip,
7371 struct tcphdr *tcp, u32 tcp_pyld_len)
7372{
7d3d0439
RA		 7373 u8 *ptr;
7374
79dc1901
AM		 7375 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7376
7d3d0439
RA		 7377 if (!tcp_pyld_len) {
7378 /* Runt frame or a pure ack */
7379 return -1;
7380 }
7381
7382 if (ip->ihl != 5) /* IP has options */
7383 return -1;
7384
75c30b13
AR		 7385 /* If we see CE codepoint in IP header, packet is not mergeable */
7386 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
7387 return -1;
7388
7389 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7d3d0439 7390 if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
75c30b13 7391 tcp->ece || tcp->cwr || !tcp->ack) {
7d3d0439
RA		 7392 /*
7393 * Currently recognize only the ack control word and
7394 * any other control field being set would result in
7395 * flushing the LRO session
7396 */
7397 return -1;
7398 }
7399
6aa20a22 7400 /*
7d3d0439
RA		 7401 * Allow only one TCP timestamp option. Don't aggregate if
7402 * any other options are detected.
7403 */
7404 if (tcp->doff != 5 && tcp->doff != 8)
7405 return -1;
7406
7407 if (tcp->doff == 8) {
6aa20a22 7408 ptr = (u8 *)(tcp + 1);
7d3d0439
RA		 7409 while (*ptr == TCPOPT_NOP)
7410 ptr++;
7411 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
7412 return -1;
7413
7414 /* Ensure timestamp value increases monotonically */
7415 if (l_lro)
7416 if (l_lro->cur_tsval > *((u32 *)(ptr+2)))
7417 return -1;
7418
7419 /* timestamp echo reply should be non-zero */
6aa20a22 7420 if (*((u32 *)(ptr+6)) == 0)
7d3d0439
RA		 7421 return -1;
7422 }
7423
7424 return 0;
7425}
7426
7427static int
7428s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, lro_t **lro,
7429 RxD_t *rxdp, nic_t *sp)
7430{
7431 struct iphdr *ip;
7432 struct tcphdr *tcph;
7433 int ret = 0, i;
7434
7435 if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
7436 rxdp))) {
7437 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
7438 ip->saddr, ip->daddr);
7439 } else {
7440 return ret;
7441 }
7442
7443 tcph = (struct tcphdr *)*tcp;
7444 *tcp_len = get_l4_pyld_length(ip, tcph);
7445 for (i=0; i<MAX_LRO_SESSIONS; i++) {
7446 lro_t *l_lro = &sp->lro0_n[i];
7447 if (l_lro->in_use) {
7448 if (check_for_socket_match(l_lro, ip, tcph))
7449 continue;
7450 /* Sock pair matched */
7451 *lro = l_lro;
7452
7453 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
7454 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
7455 "0x%x, actual 0x%x\n", __FUNCTION__,
7456 (*lro)->tcp_next_seq,
7457 ntohl(tcph->seq));
7458
7459 sp->mac_control.stats_info->
7460 sw_stat.outof_sequence_pkts++;
7461 ret = 2;
7462 break;
7463 }
7464
7465 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
7466 ret = 1; /* Aggregate */
7467 else
7468 ret = 2; /* Flush both */
7469 break;
7470 }
7471 }
7472
7473 if (ret == 0) {
7474 /* Before searching for available LRO objects,
7475 * check if the pkt is L3/L4 aggregatable. If not
7476 * don't create new LRO session. Just send this
7477 * packet up.
7478 */
7479 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
7480 return 5;
7481 }
7482
7483 for (i=0; i<MAX_LRO_SESSIONS; i++) {
7484 lro_t *l_lro = &sp->lro0_n[i];
7485 if (!(l_lro->in_use)) {
7486 *lro = l_lro;
7487 ret = 3; /* Begin anew */
7488 break;
7489 }
7490 }
7491 }
7492
7493 if (ret == 0) { /* sessions exceeded */
7494 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
7495 __FUNCTION__);
7496 *lro = NULL;
7497 return ret;
7498 }
7499
7500 switch (ret) {
7501 case 3:
7502 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len);
7503 break;
7504 case 2:
7505 update_L3L4_header(sp, *lro);
7506 break;
7507 case 1:
7508 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
7509 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
7510 update_L3L4_header(sp, *lro);
7511 ret = 4; /* Flush the LRO */
7512 }
7513 break;
7514 default:
7515 DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
7516 __FUNCTION__);
7517 break;
7518 }
7519
7520 return ret;
7521}
7522
7523static void clear_lro_session(lro_t *lro)
7524{
7525 static u16 lro_struct_size = sizeof(lro_t);
7526
7527 memset(lro, 0, lro_struct_size);
7528}
7529
7530static void queue_rx_frame(struct sk_buff *skb)
7531{
7532 struct net_device *dev = skb->dev;
7533
7534 skb->protocol = eth_type_trans(skb, dev);
db874e65
SS		 7535 if (napi)
7536 netif_receive_skb(skb);
7537 else
7538 netif_rx(skb);
7d3d0439
RA		 7539}
7540
7541static void lro_append_pkt(nic_t *sp, lro_t *lro, struct sk_buff *skb,
7542 u32 tcp_len)
7543{
75c30b13 7544 struct sk_buff *first = lro->parent;
7d3d0439
RA		 7545
7546 first->len += tcp_len;
7547 first->data_len = lro->frags_len;
7548 skb_pull(skb, (skb->len - tcp_len));
75c30b13
AR		 7549 if (skb_shinfo(first)->frag_list)
7550 lro->last_frag->next = skb;
7d3d0439
RA		 7551 else
7552 skb_shinfo(first)->frag_list = skb;
75c30b13 7553 lro->last_frag = skb;
7d3d0439
RA		 7554 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
7555 return;
7556}
kernel source for telekom puls (alcatel/mediatek)