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s2io.c: Make more conforming to normal kernel style
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / s2io.c
CommitLineData
1da177e4 1/************************************************************************
776bd20f 2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
0c61ed5f 3 * Copyright(c) 2002-2007 Neterion Inc.
d44570e4 4 *
1da177e4
LT		 5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
20346722
K		 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
1da177e4
LT		 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
20346722 21 * Francois Romieu : For pointing out all code part that were
1da177e4 22 * deprecated and also styling related comments.
20346722 23 * Grant Grundler : For helping me get rid of some Architecture
1da177e4
LT		 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
20346722 26 *
1da177e4
LT		 27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
9dc737a7 29 *
20346722
K		 30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
9dc737a7
AR		 32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
da6971d8 34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
6d517a27 35 * values are 1, 2.
1da177e4 36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
20346722 37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
1da177e4 38 * Tx descriptors that can be associated with each corresponding FIFO.
9dc737a7 39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
8abc4d5b 40 * 2(MSI_X). Default value is '2(MSI_X)'
43b7c451 41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
9dc737a7
AR		 42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
926930b2
SS		 45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
3a3d5756
SH		 53 * multiq: This parameter used to enable/disable MULTIQUEUE support.
54 * Possible values '1' for enable and '0' for disable. Default is '0'
1da177e4
LT		 55 ************************************************************************/
56
1da177e4
LT		 57#include <linux/module.h>
58#include <linux/types.h>
59#include <linux/errno.h>
60#include <linux/ioport.h>
61#include <linux/pci.h>
1e7f0bd8 62#include <linux/dma-mapping.h>
1da177e4
LT		 63#include <linux/kernel.h>
64#include <linux/netdevice.h>
65#include <linux/etherdevice.h>
40239396 66#include <linux/mdio.h>
1da177e4
LT		 67#include <linux/skbuff.h>
68#include <linux/init.h>
69#include <linux/delay.h>
70#include <linux/stddef.h>
71#include <linux/ioctl.h>
72#include <linux/timex.h>
1da177e4 73#include <linux/ethtool.h>
1da177e4 74#include <linux/workqueue.h>
be3a6b02 75#include <linux/if_vlan.h>
7d3d0439
RA		 76#include <linux/ip.h>
77#include <linux/tcp.h>
d44570e4
JP		 78#include <linux/uaccess.h>
79#include <linux/io.h>
7d3d0439 80#include <net/tcp.h>
1da177e4 81
1da177e4 82#include <asm/system.h>
fe931395 83#include <asm/div64.h>
330ce0de 84#include <asm/irq.h>
1da177e4
LT		 85
86/* local include */
87#include "s2io.h"
88#include "s2io-regs.h"
89
29d0a2b0 90#define DRV_VERSION "2.0.26.25"
6c1792f4 91
1da177e4 92/* S2io Driver name & version. */
20346722 93static char s2io_driver_name[] = "Neterion";
6c1792f4 94static char s2io_driver_version[] = DRV_VERSION;
1da177e4 95
d44570e4
JP		 96static int rxd_size[2] = {32, 48};
97static int rxd_count[2] = {127, 85};
da6971d8 98
1ee6dd77 99static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
5e25b9dd
K		 100{
101 int ret;
102
103 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
d44570e4 104 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
5e25b9dd
K		 105
106 return ret;
107}
108
20346722 109/*
1da177e4
LT		 110 * Cards with following subsystem_id have a link state indication
111 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
112 * macro below identifies these cards given the subsystem_id.
113 */
d44570e4
JP		 114#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
115 (dev_type == XFRAME_I_DEVICE) ? \
116 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
117 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
1da177e4
LT		 118
119#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
120 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
1da177e4 121
d44570e4 122static inline int is_s2io_card_up(const struct s2io_nic *sp)
92b84437
SS		 123{
124 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
125}
126
1da177e4 127/* Ethtool related variables and Macros. */
6fce365d 128static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
1da177e4
LT		 129 "Register test\t(offline)",
130 "Eeprom test\t(offline)",
131 "Link test\t(online)",
132 "RLDRAM test\t(offline)",
133 "BIST Test\t(offline)"
134};
135
6fce365d 136static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
1da177e4
LT		 137 {"tmac_frms"},
138 {"tmac_data_octets"},
139 {"tmac_drop_frms"},
140 {"tmac_mcst_frms"},
141 {"tmac_bcst_frms"},
142 {"tmac_pause_ctrl_frms"},
bd1034f0
AR		 143 {"tmac_ttl_octets"},
144 {"tmac_ucst_frms"},
145 {"tmac_nucst_frms"},
1da177e4 146 {"tmac_any_err_frms"},
bd1034f0 147 {"tmac_ttl_less_fb_octets"},
1da177e4
LT		 148 {"tmac_vld_ip_octets"},
149 {"tmac_vld_ip"},
150 {"tmac_drop_ip"},
151 {"tmac_icmp"},
152 {"tmac_rst_tcp"},
153 {"tmac_tcp"},
154 {"tmac_udp"},
155 {"rmac_vld_frms"},
156 {"rmac_data_octets"},
157 {"rmac_fcs_err_frms"},
158 {"rmac_drop_frms"},
159 {"rmac_vld_mcst_frms"},
160 {"rmac_vld_bcst_frms"},
161 {"rmac_in_rng_len_err_frms"},
bd1034f0 162 {"rmac_out_rng_len_err_frms"},
1da177e4
LT		 163 {"rmac_long_frms"},
164 {"rmac_pause_ctrl_frms"},
bd1034f0
AR		 165 {"rmac_unsup_ctrl_frms"},
166 {"rmac_ttl_octets"},
167 {"rmac_accepted_ucst_frms"},
168 {"rmac_accepted_nucst_frms"},
1da177e4 169 {"rmac_discarded_frms"},
bd1034f0
AR		 170 {"rmac_drop_events"},
171 {"rmac_ttl_less_fb_octets"},
172 {"rmac_ttl_frms"},
1da177e4
LT		 173 {"rmac_usized_frms"},
174 {"rmac_osized_frms"},
175 {"rmac_frag_frms"},
176 {"rmac_jabber_frms"},
bd1034f0
AR		 177 {"rmac_ttl_64_frms"},
178 {"rmac_ttl_65_127_frms"},
179 {"rmac_ttl_128_255_frms"},
180 {"rmac_ttl_256_511_frms"},
181 {"rmac_ttl_512_1023_frms"},
182 {"rmac_ttl_1024_1518_frms"},
1da177e4
LT		 183 {"rmac_ip"},
184 {"rmac_ip_octets"},
185 {"rmac_hdr_err_ip"},
186 {"rmac_drop_ip"},
187 {"rmac_icmp"},
188 {"rmac_tcp"},
189 {"rmac_udp"},
190 {"rmac_err_drp_udp"},
bd1034f0
AR		 191 {"rmac_xgmii_err_sym"},
192 {"rmac_frms_q0"},
193 {"rmac_frms_q1"},
194 {"rmac_frms_q2"},
195 {"rmac_frms_q3"},
196 {"rmac_frms_q4"},
197 {"rmac_frms_q5"},
198 {"rmac_frms_q6"},
199 {"rmac_frms_q7"},
200 {"rmac_full_q0"},
201 {"rmac_full_q1"},
202 {"rmac_full_q2"},
203 {"rmac_full_q3"},
204 {"rmac_full_q4"},
205 {"rmac_full_q5"},
206 {"rmac_full_q6"},
207 {"rmac_full_q7"},
1da177e4 208 {"rmac_pause_cnt"},
bd1034f0
AR		 209 {"rmac_xgmii_data_err_cnt"},
210 {"rmac_xgmii_ctrl_err_cnt"},
1da177e4
LT		 211 {"rmac_accepted_ip"},
212 {"rmac_err_tcp"},
bd1034f0
AR		 213 {"rd_req_cnt"},
214 {"new_rd_req_cnt"},
215 {"new_rd_req_rtry_cnt"},
216 {"rd_rtry_cnt"},
217 {"wr_rtry_rd_ack_cnt"},
218 {"wr_req_cnt"},
219 {"new_wr_req_cnt"},
220 {"new_wr_req_rtry_cnt"},
221 {"wr_rtry_cnt"},
222 {"wr_disc_cnt"},
223 {"rd_rtry_wr_ack_cnt"},
224 {"txp_wr_cnt"},
225 {"txd_rd_cnt"},
226 {"txd_wr_cnt"},
227 {"rxd_rd_cnt"},
228 {"rxd_wr_cnt"},
229 {"txf_rd_cnt"},
fa1f0cb3
SS		 230 {"rxf_wr_cnt"}
231};
232
6fce365d 233static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
bd1034f0
AR		 234 {"rmac_ttl_1519_4095_frms"},
235 {"rmac_ttl_4096_8191_frms"},
236 {"rmac_ttl_8192_max_frms"},
237 {"rmac_ttl_gt_max_frms"},
238 {"rmac_osized_alt_frms"},
239 {"rmac_jabber_alt_frms"},
240 {"rmac_gt_max_alt_frms"},
241 {"rmac_vlan_frms"},
242 {"rmac_len_discard"},
243 {"rmac_fcs_discard"},
244 {"rmac_pf_discard"},
245 {"rmac_da_discard"},
246 {"rmac_red_discard"},
247 {"rmac_rts_discard"},
248 {"rmac_ingm_full_discard"},
fa1f0cb3
SS		 249 {"link_fault_cnt"}
250};
251
6fce365d 252static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
7ba013ac
K		 253 {"\n DRIVER STATISTICS"},
254 {"single_bit_ecc_errs"},
255 {"double_bit_ecc_errs"},
bd1034f0
AR		 256 {"parity_err_cnt"},
257 {"serious_err_cnt"},
258 {"soft_reset_cnt"},
259 {"fifo_full_cnt"},
8116f3cf
SS		 260 {"ring_0_full_cnt"},
261 {"ring_1_full_cnt"},
262 {"ring_2_full_cnt"},
263 {"ring_3_full_cnt"},
264 {"ring_4_full_cnt"},
265 {"ring_5_full_cnt"},
266 {"ring_6_full_cnt"},
267 {"ring_7_full_cnt"},
43b7c451
SH		 268 {"alarm_transceiver_temp_high"},
269 {"alarm_transceiver_temp_low"},
270 {"alarm_laser_bias_current_high"},
271 {"alarm_laser_bias_current_low"},
272 {"alarm_laser_output_power_high"},
273 {"alarm_laser_output_power_low"},
274 {"warn_transceiver_temp_high"},
275 {"warn_transceiver_temp_low"},
276 {"warn_laser_bias_current_high"},
277 {"warn_laser_bias_current_low"},
278 {"warn_laser_output_power_high"},
279 {"warn_laser_output_power_low"},
280 {"lro_aggregated_pkts"},
281 {"lro_flush_both_count"},
282 {"lro_out_of_sequence_pkts"},
283 {"lro_flush_due_to_max_pkts"},
284 {"lro_avg_aggr_pkts"},
285 {"mem_alloc_fail_cnt"},
286 {"pci_map_fail_cnt"},
287 {"watchdog_timer_cnt"},
288 {"mem_allocated"},
289 {"mem_freed"},
290 {"link_up_cnt"},
291 {"link_down_cnt"},
292 {"link_up_time"},
293 {"link_down_time"},
294 {"tx_tcode_buf_abort_cnt"},
295 {"tx_tcode_desc_abort_cnt"},
296 {"tx_tcode_parity_err_cnt"},
297 {"tx_tcode_link_loss_cnt"},
298 {"tx_tcode_list_proc_err_cnt"},
299 {"rx_tcode_parity_err_cnt"},
300 {"rx_tcode_abort_cnt"},
301 {"rx_tcode_parity_abort_cnt"},
302 {"rx_tcode_rda_fail_cnt"},
303 {"rx_tcode_unkn_prot_cnt"},
304 {"rx_tcode_fcs_err_cnt"},
305 {"rx_tcode_buf_size_err_cnt"},
306 {"rx_tcode_rxd_corrupt_cnt"},
307 {"rx_tcode_unkn_err_cnt"},
8116f3cf
SS		 308 {"tda_err_cnt"},
309 {"pfc_err_cnt"},
310 {"pcc_err_cnt"},
311 {"tti_err_cnt"},
312 {"tpa_err_cnt"},
313 {"sm_err_cnt"},
314 {"lso_err_cnt"},
315 {"mac_tmac_err_cnt"},
316 {"mac_rmac_err_cnt"},
317 {"xgxs_txgxs_err_cnt"},
318 {"xgxs_rxgxs_err_cnt"},
319 {"rc_err_cnt"},
320 {"prc_pcix_err_cnt"},
321 {"rpa_err_cnt"},
322 {"rda_err_cnt"},
323 {"rti_err_cnt"},
324 {"mc_err_cnt"}
1da177e4
LT		 325};
326
4c3616cd
AMR		 327#define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
328#define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
329#define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
fa1f0cb3 330
d44570e4
JP		 331#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
332#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
fa1f0cb3 333
d44570e4
JP		 334#define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
335#define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
1da177e4 336
4c3616cd 337#define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
d44570e4 338#define S2IO_STRINGS_LEN (S2IO_TEST_LEN * ETH_GSTRING_LEN)
1da177e4 339
d44570e4
JP		 340#define S2IO_TIMER_CONF(timer, handle, arg, exp) \
341 init_timer(&timer); \
342 timer.function = handle; \
343 timer.data = (unsigned long)arg; \
344 mod_timer(&timer, (jiffies + exp)) \
25fff88e 345
2fd37688
SS		 346/* copy mac addr to def_mac_addr array */
347static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
348{
349 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
350 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
351 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
352 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
353 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
354 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
355}
04025095 356
be3a6b02
K		 357/* Add the vlan */
358static void s2io_vlan_rx_register(struct net_device *dev,
04025095 359 struct vlan_group *grp)
be3a6b02 360{
2fda096d 361 int i;
4cf1653a 362 struct s2io_nic *nic = netdev_priv(dev);
2fda096d
SR		 363 unsigned long flags[MAX_TX_FIFOS];
364 struct mac_info *mac_control = &nic->mac_control;
365 struct config_param *config = &nic->config;
366
13d866a9
JP		 367 for (i = 0; i < config->tx_fifo_num; i++) {
368 struct fifo_info *fifo = &mac_control->fifos[i];
369
370 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
371 }
be3a6b02 372
be3a6b02 373 nic->vlgrp = grp;
13d866a9
JP		 374
375 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
376 struct fifo_info *fifo = &mac_control->fifos[i];
377
378 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
379 }
be3a6b02
K		 380}
381
cdb5bf02 382/* Unregister the vlan */
04025095 383static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
cdb5bf02
SH		 384{
385 int i;
4cf1653a 386 struct s2io_nic *nic = netdev_priv(dev);
cdb5bf02
SH		 387 unsigned long flags[MAX_TX_FIFOS];
388 struct mac_info *mac_control = &nic->mac_control;
389 struct config_param *config = &nic->config;
390
13d866a9
JP		 391 for (i = 0; i < config->tx_fifo_num; i++) {
392 struct fifo_info *fifo = &mac_control->fifos[i];
393
394 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
395 }
cdb5bf02
SH		 396
397 if (nic->vlgrp)
398 vlan_group_set_device(nic->vlgrp, vid, NULL);
399
13d866a9
JP		 400 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
401 struct fifo_info *fifo = &mac_control->fifos[i];
402
403 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
404 }
cdb5bf02
SH		 405}
406
20346722 407/*
1da177e4
LT		 408 * Constants to be programmed into the Xena's registers, to configure
409 * the XAUI.
410 */
411
1da177e4 412#define END_SIGN 0x0
f71e1309 413static const u64 herc_act_dtx_cfg[] = {
541ae68f 414 /* Set address */
e960fc5c 415 0x8000051536750000ULL, 0x80000515367500E0ULL,
541ae68f 416 /* Write data */
e960fc5c 417 0x8000051536750004ULL, 0x80000515367500E4ULL,
541ae68f
K		 418 /* Set address */
419 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
420 /* Write data */
421 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
422 /* Set address */
e960fc5c 423 0x801205150D440000ULL, 0x801205150D4400E0ULL,
424 /* Write data */
425 0x801205150D440004ULL, 0x801205150D4400E4ULL,
426 /* Set address */
541ae68f
K		 427 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
428 /* Write data */
429 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
430 /* Done */
431 END_SIGN
432};
433
f71e1309 434static const u64 xena_dtx_cfg[] = {
c92ca04b 435 /* Set address */
1da177e4 436 0x8000051500000000ULL, 0x80000515000000E0ULL,
c92ca04b
AR		 437 /* Write data */
438 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
439 /* Set address */
440 0x8001051500000000ULL, 0x80010515000000E0ULL,
441 /* Write data */
442 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
443 /* Set address */
1da177e4 444 0x8002051500000000ULL, 0x80020515000000E0ULL,
c92ca04b
AR		 445 /* Write data */
446 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1da177e4
LT		 447 END_SIGN
448};
449
20346722 450/*
1da177e4
LT		 451 * Constants for Fixing the MacAddress problem seen mostly on
452 * Alpha machines.
453 */
f71e1309 454static const u64 fix_mac[] = {
1da177e4
LT		 455 0x0060000000000000ULL, 0x0060600000000000ULL,
456 0x0040600000000000ULL, 0x0000600000000000ULL,
457 0x0020600000000000ULL, 0x0060600000000000ULL,
458 0x0020600000000000ULL, 0x0060600000000000ULL,
459 0x0020600000000000ULL, 0x0060600000000000ULL,
460 0x0020600000000000ULL, 0x0060600000000000ULL,
461 0x0020600000000000ULL, 0x0060600000000000ULL,
462 0x0020600000000000ULL, 0x0060600000000000ULL,
463 0x0020600000000000ULL, 0x0060600000000000ULL,
464 0x0020600000000000ULL, 0x0060600000000000ULL,
465 0x0020600000000000ULL, 0x0060600000000000ULL,
466 0x0020600000000000ULL, 0x0060600000000000ULL,
467 0x0020600000000000ULL, 0x0000600000000000ULL,
468 0x0040600000000000ULL, 0x0060600000000000ULL,
469 END_SIGN
470};
471
b41477f3
AR		 472MODULE_LICENSE("GPL");
473MODULE_VERSION(DRV_VERSION);
474
475
1da177e4 476/* Module Loadable parameters. */
6cfc482b 477S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
b41477f3 478S2IO_PARM_INT(rx_ring_num, 1);
3a3d5756 479S2IO_PARM_INT(multiq, 0);
b41477f3
AR		 480S2IO_PARM_INT(rx_ring_mode, 1);
481S2IO_PARM_INT(use_continuous_tx_intrs, 1);
482S2IO_PARM_INT(rmac_pause_time, 0x100);
483S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
484S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
485S2IO_PARM_INT(shared_splits, 0);
486S2IO_PARM_INT(tmac_util_period, 5);
487S2IO_PARM_INT(rmac_util_period, 5);
b41477f3 488S2IO_PARM_INT(l3l4hdr_size, 128);
6cfc482b
SH		 489/* 0 is no steering, 1 is Priority steering, 2 is Default steering */
490S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
303bcb4b 491/* Frequency of Rx desc syncs expressed as power of 2 */
b41477f3 492S2IO_PARM_INT(rxsync_frequency, 3);
eccb8628 493/* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
8abc4d5b 494S2IO_PARM_INT(intr_type, 2);
7d3d0439 495/* Large receive offload feature */
43b7c451
SH		 496static unsigned int lro_enable;
497module_param_named(lro, lro_enable, uint, 0);
498
7d3d0439
RA		 499/* Max pkts to be aggregated by LRO at one time. If not specified,
500 * aggregation happens until we hit max IP pkt size(64K)
501 */
b41477f3 502S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
b41477f3 503S2IO_PARM_INT(indicate_max_pkts, 0);
db874e65
SS		 504
505S2IO_PARM_INT(napi, 1);
506S2IO_PARM_INT(ufo, 0);
926930b2 507S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
b41477f3
AR		 508
509static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
d44570e4 510{DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
b41477f3 511static unsigned int rx_ring_sz[MAX_RX_RINGS] =
d44570e4 512{[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
b41477f3 513static unsigned int rts_frm_len[MAX_RX_RINGS] =
d44570e4 514{[0 ...(MAX_RX_RINGS - 1)] = 0 };
b41477f3
AR		 515
516module_param_array(tx_fifo_len, uint, NULL, 0);
517module_param_array(rx_ring_sz, uint, NULL, 0);
518module_param_array(rts_frm_len, uint, NULL, 0);
1da177e4 519
20346722 520/*
1da177e4 521 * S2IO device table.
20346722 522 * This table lists all the devices that this driver supports.
1da177e4
LT		 523 */
524static struct pci_device_id s2io_tbl[] __devinitdata = {
525 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
526 PCI_ANY_ID, PCI_ANY_ID},
527 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
528 PCI_ANY_ID, PCI_ANY_ID},
529 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
d44570e4
JP		 530 PCI_ANY_ID, PCI_ANY_ID},
531 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
532 PCI_ANY_ID, PCI_ANY_ID},
1da177e4
LT		 533 {0,}
534};
535
536MODULE_DEVICE_TABLE(pci, s2io_tbl);
537
d796fdb7
LV		 538static struct pci_error_handlers s2io_err_handler = {
539 .error_detected = s2io_io_error_detected,
540 .slot_reset = s2io_io_slot_reset,
541 .resume = s2io_io_resume,
542};
543
1da177e4 544static struct pci_driver s2io_driver = {
d44570e4
JP		 545 .name = "S2IO",
546 .id_table = s2io_tbl,
547 .probe = s2io_init_nic,
548 .remove = __devexit_p(s2io_rem_nic),
549 .err_handler = &s2io_err_handler,
1da177e4
LT		 550};
551
552/* A simplifier macro used both by init and free shared_mem Fns(). */
553#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
554
3a3d5756
SH		 555/* netqueue manipulation helper functions */
556static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
557{
fd2ea0a7
DM		 558 if (!sp->config.multiq) {
559 int i;
560
3a3d5756
SH		 561 for (i = 0; i < sp->config.tx_fifo_num; i++)
562 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
3a3d5756 563 }
fd2ea0a7 564 netif_tx_stop_all_queues(sp->dev);
3a3d5756
SH		 565}
566
567static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
568{
fd2ea0a7 569 if (!sp->config.multiq)
3a3d5756
SH		 570 sp->mac_control.fifos[fifo_no].queue_state =
571 FIFO_QUEUE_STOP;
fd2ea0a7
DM		 572
573 netif_tx_stop_all_queues(sp->dev);
3a3d5756
SH		 574}
575
576static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
577{
fd2ea0a7
DM		 578 if (!sp->config.multiq) {
579 int i;
580
3a3d5756
SH		 581 for (i = 0; i < sp->config.tx_fifo_num; i++)
582 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
3a3d5756 583 }
fd2ea0a7 584 netif_tx_start_all_queues(sp->dev);
3a3d5756
SH		 585}
586
587static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
588{
fd2ea0a7 589 if (!sp->config.multiq)
3a3d5756
SH		 590 sp->mac_control.fifos[fifo_no].queue_state =
591 FIFO_QUEUE_START;
fd2ea0a7
DM		 592
593 netif_tx_start_all_queues(sp->dev);
3a3d5756
SH		 594}
595
596static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
597{
fd2ea0a7
DM		 598 if (!sp->config.multiq) {
599 int i;
600
3a3d5756
SH		 601 for (i = 0; i < sp->config.tx_fifo_num; i++)
602 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
3a3d5756 603 }
fd2ea0a7 604 netif_tx_wake_all_queues(sp->dev);
3a3d5756
SH		 605}
606
607static inline void s2io_wake_tx_queue(
608 struct fifo_info *fifo, int cnt, u8 multiq)
609{
610
3a3d5756
SH		 611 if (multiq) {
612 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
613 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
b19fa1fa 614 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
3a3d5756
SH		 615 if (netif_queue_stopped(fifo->dev)) {
616 fifo->queue_state = FIFO_QUEUE_START;
617 netif_wake_queue(fifo->dev);
618 }
619 }
620}
621
1da177e4
LT		 622/**
623 * init_shared_mem - Allocation and Initialization of Memory
624 * @nic: Device private variable.
20346722
K		 625 * Description: The function allocates all the memory areas shared
626 * between the NIC and the driver. This includes Tx descriptors,
1da177e4
LT		 627 * Rx descriptors and the statistics block.
628 */
629
630static int init_shared_mem(struct s2io_nic *nic)
631{
632 u32 size;
633 void *tmp_v_addr, *tmp_v_addr_next;
634 dma_addr_t tmp_p_addr, tmp_p_addr_next;
1ee6dd77 635 struct RxD_block *pre_rxd_blk = NULL;
372cc597 636 int i, j, blk_cnt;
1da177e4
LT		 637 int lst_size, lst_per_page;
638 struct net_device *dev = nic->dev;
8ae418cf 639 unsigned long tmp;
1ee6dd77 640 struct buffAdd *ba;
1da177e4 641
1ee6dd77 642 struct mac_info *mac_control;
1da177e4 643 struct config_param *config;
491976b2 644 unsigned long long mem_allocated = 0;
1da177e4
LT		 645
646 mac_control = &nic->mac_control;
647 config = &nic->config;
648
13d866a9 649 /* Allocation and initialization of TXDLs in FIFOs */
1da177e4
LT		 650 size = 0;
651 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 652 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
653
654 size += tx_cfg->fifo_len;
1da177e4
LT		 655 }
656 if (size > MAX_AVAILABLE_TXDS) {
b41477f3 657 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
d44570e4
JP		 658 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n",
659 size);
b41477f3 660 return -EINVAL;
1da177e4
LT		 661 }
662
2fda096d
SR		 663 size = 0;
664 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 665 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
666
667 size = tx_cfg->fifo_len;
2fda096d
SR		 668 /*
669 * Legal values are from 2 to 8192
670 */
671 if (size < 2) {
672 DBG_PRINT(ERR_DBG, "s2io: Invalid fifo len (%d)", size);
673 DBG_PRINT(ERR_DBG, "for fifo %d\n", i);
674 DBG_PRINT(ERR_DBG, "s2io: Legal values for fifo len"
d44570e4 675 "are 2 to 8192\n");
2fda096d
SR		 676 return -EINVAL;
677 }
678 }
679
1ee6dd77 680 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 681 lst_per_page = PAGE_SIZE / lst_size;
682
683 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 684 struct fifo_info *fifo = &mac_control->fifos[i];
685 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
686 int fifo_len = tx_cfg->fifo_len;
1ee6dd77 687 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
13d866a9
JP		 688
689 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
690 if (!fifo->list_info) {
d44570e4 691 DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
1da177e4
LT		 692 return -ENOMEM;
693 }
491976b2 694 mem_allocated += list_holder_size;
1da177e4
LT		 695 }
696 for (i = 0; i < config->tx_fifo_num; i++) {
697 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
698 lst_per_page);
13d866a9
JP		 699 struct fifo_info *fifo = &mac_control->fifos[i];
700 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
701
702 fifo->tx_curr_put_info.offset = 0;
703 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
704 fifo->tx_curr_get_info.offset = 0;
705 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
706 fifo->fifo_no = i;
707 fifo->nic = nic;
708 fifo->max_txds = MAX_SKB_FRAGS + 2;
709 fifo->dev = dev;
20346722 710
1da177e4
LT		 711 for (j = 0; j < page_num; j++) {
712 int k = 0;
713 dma_addr_t tmp_p;
714 void *tmp_v;
715 tmp_v = pci_alloc_consistent(nic->pdev,
716 PAGE_SIZE, &tmp_p);
717 if (!tmp_v) {
d44570e4 718 DBG_PRINT(INFO_DBG, "pci_alloc_consistent ");
0c61ed5f 719 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
1da177e4
LT		 720 return -ENOMEM;
721 }
776bd20f 722 /* If we got a zero DMA address(can happen on
723 * certain platforms like PPC), reallocate.
724 * Store virtual address of page we don't want,
725 * to be freed later.
726 */
727 if (!tmp_p) {
728 mac_control->zerodma_virt_addr = tmp_v;
6aa20a22 729 DBG_PRINT(INIT_DBG,
d44570e4
JP		 730 "%s: Zero DMA address for TxDL. ",
731 dev->name);
6aa20a22 732 DBG_PRINT(INIT_DBG,
d44570e4 733 "Virtual address %p\n", tmp_v);
776bd20f 734 tmp_v = pci_alloc_consistent(nic->pdev,
d44570e4 735 PAGE_SIZE, &tmp_p);
776bd20f 736 if (!tmp_v) {
0c61ed5f 737 DBG_PRINT(INFO_DBG,
d44570e4
JP		 738 "pci_alloc_consistent ");
739 DBG_PRINT(INFO_DBG,
740 "failed for TxDL\n");
776bd20f 741 return -ENOMEM;
742 }
491976b2 743 mem_allocated += PAGE_SIZE;
776bd20f 744 }
1da177e4
LT		 745 while (k < lst_per_page) {
746 int l = (j * lst_per_page) + k;
13d866a9 747 if (l == tx_cfg->fifo_len)
20346722 748 break;
13d866a9 749 fifo->list_info[l].list_virt_addr =
d44570e4 750 tmp_v + (k * lst_size);
13d866a9 751 fifo->list_info[l].list_phy_addr =
d44570e4 752 tmp_p + (k * lst_size);
1da177e4
LT		 753 k++;
754 }
755 }
756 }
1da177e4 757
2fda096d 758 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 759 struct fifo_info *fifo = &mac_control->fifos[i];
760 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
761
762 size = tx_cfg->fifo_len;
763 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
764 if (!fifo->ufo_in_band_v)
2fda096d
SR		 765 return -ENOMEM;
766 mem_allocated += (size * sizeof(u64));
767 }
fed5eccd 768
1da177e4
LT		 769 /* Allocation and initialization of RXDs in Rings */
770 size = 0;
771 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 772 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
773 struct ring_info *ring = &mac_control->rings[i];
774
775 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
1da177e4 776 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
13d866a9 777 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ", i);
1da177e4
LT		 778 DBG_PRINT(ERR_DBG, "RxDs per Block");
779 return FAILURE;
780 }
13d866a9
JP		 781 size += rx_cfg->num_rxd;
782 ring->block_count = rx_cfg->num_rxd /
d44570e4 783 (rxd_count[nic->rxd_mode] + 1);
13d866a9 784 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
1da177e4 785 }
da6971d8 786 if (nic->rxd_mode == RXD_MODE_1)
1ee6dd77 787 size = (size * (sizeof(struct RxD1)));
da6971d8 788 else
1ee6dd77 789 size = (size * (sizeof(struct RxD3)));
1da177e4
LT		 790
791 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 792 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
793 struct ring_info *ring = &mac_control->rings[i];
794
795 ring->rx_curr_get_info.block_index = 0;
796 ring->rx_curr_get_info.offset = 0;
797 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
798 ring->rx_curr_put_info.block_index = 0;
799 ring->rx_curr_put_info.offset = 0;
800 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
801 ring->nic = nic;
802 ring->ring_no = i;
803 ring->lro = lro_enable;
804
805 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
1da177e4
LT		 806 /* Allocating all the Rx blocks */
807 for (j = 0; j < blk_cnt; j++) {
1ee6dd77 808 struct rx_block_info *rx_blocks;
da6971d8
AR		 809 int l;
810
13d866a9 811 rx_blocks = &ring->rx_blocks[j];
d44570e4 812 size = SIZE_OF_BLOCK; /* size is always page size */
1da177e4
LT		 813 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
814 &tmp_p_addr);
815 if (tmp_v_addr == NULL) {
816 /*
20346722
K		 817 * In case of failure, free_shared_mem()
818 * is called, which should free any
819 * memory that was alloced till the
1da177e4
LT		 820 * failure happened.
821 */
da6971d8 822 rx_blocks->block_virt_addr = tmp_v_addr;
1da177e4
LT		 823 return -ENOMEM;
824 }
491976b2 825 mem_allocated += size;
1da177e4 826 memset(tmp_v_addr, 0, size);
4f870320
JP		 827
828 size = sizeof(struct rxd_info) *
829 rxd_count[nic->rxd_mode];
da6971d8
AR		 830 rx_blocks->block_virt_addr = tmp_v_addr;
831 rx_blocks->block_dma_addr = tmp_p_addr;
4f870320 832 rx_blocks->rxds = kmalloc(size, GFP_KERNEL);
372cc597
SS		 833 if (!rx_blocks->rxds)
834 return -ENOMEM;
4f870320 835 mem_allocated += size;
d44570e4 836 for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
da6971d8
AR		 837 rx_blocks->rxds[l].virt_addr =
838 rx_blocks->block_virt_addr +
839 (rxd_size[nic->rxd_mode] * l);
840 rx_blocks->rxds[l].dma_addr =
841 rx_blocks->block_dma_addr +
842 (rxd_size[nic->rxd_mode] * l);
843 }
1da177e4
LT		 844 }
845 /* Interlinking all Rx Blocks */
846 for (j = 0; j < blk_cnt; j++) {
13d866a9
JP		 847 int next = (j + 1) % blk_cnt;
848 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
849 tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
850 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
851 tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
1da177e4 852
d44570e4 853 pre_rxd_blk = (struct RxD_block *)tmp_v_addr;
1da177e4 854 pre_rxd_blk->reserved_2_pNext_RxD_block =
d44570e4 855 (unsigned long)tmp_v_addr_next;
1da177e4 856 pre_rxd_blk->pNext_RxD_Blk_physical =
d44570e4 857 (u64)tmp_p_addr_next;
1da177e4
LT		 858 }
859 }
6d517a27 860 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 861 /*
862 * Allocation of Storages for buffer addresses in 2BUFF mode
863 * and the buffers as well.
864 */
865 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 866 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
867 struct ring_info *ring = &mac_control->rings[i];
868
869 blk_cnt = rx_cfg->num_rxd /
d44570e4 870 (rxd_count[nic->rxd_mode] + 1);
4f870320
JP		 871 size = sizeof(struct buffAdd *) * blk_cnt;
872 ring->ba = kmalloc(size, GFP_KERNEL);
13d866a9 873 if (!ring->ba)
1da177e4 874 return -ENOMEM;
4f870320 875 mem_allocated += size;
da6971d8
AR		 876 for (j = 0; j < blk_cnt; j++) {
877 int k = 0;
4f870320
JP		 878
879 size = sizeof(struct buffAdd) *
880 (rxd_count[nic->rxd_mode] + 1);
881 ring->ba[j] = kmalloc(size, GFP_KERNEL);
13d866a9 882 if (!ring->ba[j])
1da177e4 883 return -ENOMEM;
4f870320 884 mem_allocated += size;
da6971d8 885 while (k != rxd_count[nic->rxd_mode]) {
13d866a9 886 ba = &ring->ba[j][k];
4f870320
JP		 887 size = BUF0_LEN + ALIGN_SIZE;
888 ba->ba_0_org = kmalloc(size, GFP_KERNEL);
da6971d8
AR		 889 if (!ba->ba_0_org)
890 return -ENOMEM;
4f870320 891 mem_allocated += size;
da6971d8
AR		 892 tmp = (unsigned long)ba->ba_0_org;
893 tmp += ALIGN_SIZE;
d44570e4
JP		 894 tmp &= ~((unsigned long)ALIGN_SIZE);
895 ba->ba_0 = (void *)tmp;
da6971d8 896
4f870320
JP		 897 size = BUF1_LEN + ALIGN_SIZE;
898 ba->ba_1_org = kmalloc(size, GFP_KERNEL);
da6971d8
AR		 899 if (!ba->ba_1_org)
900 return -ENOMEM;
4f870320 901 mem_allocated += size;
d44570e4 902 tmp = (unsigned long)ba->ba_1_org;
da6971d8 903 tmp += ALIGN_SIZE;
d44570e4
JP		 904 tmp &= ~((unsigned long)ALIGN_SIZE);
905 ba->ba_1 = (void *)tmp;
da6971d8
AR		 906 k++;
907 }
1da177e4
LT		 908 }
909 }
910 }
1da177e4
LT		 911
912 /* Allocation and initialization of Statistics block */
1ee6dd77 913 size = sizeof(struct stat_block);
d44570e4
JP		 914 mac_control->stats_mem =
915 pci_alloc_consistent(nic->pdev, size,
916 &mac_control->stats_mem_phy);
1da177e4
LT		 917
918 if (!mac_control->stats_mem) {
20346722
K		 919 /*
920 * In case of failure, free_shared_mem() is called, which
921 * should free any memory that was alloced till the
1da177e4
LT		 922 * failure happened.
923 */
924 return -ENOMEM;
925 }
491976b2 926 mem_allocated += size;
1da177e4
LT		 927 mac_control->stats_mem_sz = size;
928
929 tmp_v_addr = mac_control->stats_mem;
d44570e4 930 mac_control->stats_info = (struct stat_block *)tmp_v_addr;
1da177e4 931 memset(tmp_v_addr, 0, size);
1da177e4 932 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
d44570e4 933 (unsigned long long)tmp_p_addr);
491976b2 934 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
1da177e4
LT		 935 return SUCCESS;
936}
937
20346722
K		 938/**
939 * free_shared_mem - Free the allocated Memory
1da177e4
LT		 940 * @nic: Device private variable.
941 * Description: This function is to free all memory locations allocated by
942 * the init_shared_mem() function and return it to the kernel.
943 */
944
945static void free_shared_mem(struct s2io_nic *nic)
946{
947 int i, j, blk_cnt, size;
948 void *tmp_v_addr;
949 dma_addr_t tmp_p_addr;
1ee6dd77 950 struct mac_info *mac_control;
1da177e4
LT		 951 struct config_param *config;
952 int lst_size, lst_per_page;
8910b49f 953 struct net_device *dev;
491976b2 954 int page_num = 0;
1da177e4
LT		 955
956 if (!nic)
957 return;
958
8910b49f
MG		 959 dev = nic->dev;
960
1da177e4
LT		 961 mac_control = &nic->mac_control;
962 config = &nic->config;
963
d44570e4 964 lst_size = sizeof(struct TxD) * config->max_txds;
1da177e4
LT		 965 lst_per_page = PAGE_SIZE / lst_size;
966
967 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 968 struct fifo_info *fifo = &mac_control->fifos[i];
969 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
970
971 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
1da177e4
LT		 972 for (j = 0; j < page_num; j++) {
973 int mem_blks = (j * lst_per_page);
13d866a9
JP		 974 struct list_info_hold *fli;
975
976 if (!fifo->list_info)
6aa20a22 977 return;
13d866a9
JP		 978
979 fli = &fifo->list_info[mem_blks];
980 if (!fli->list_virt_addr)
1da177e4
LT		 981 break;
982 pci_free_consistent(nic->pdev, PAGE_SIZE,
13d866a9
JP		 983 fli->list_virt_addr,
984 fli->list_phy_addr);
8a4bdbaa 985 nic->mac_control.stats_info->sw_stat.mem_freed
d44570e4 986 += PAGE_SIZE;
1da177e4 987 }
776bd20f 988 /* If we got a zero DMA address during allocation,
989 * free the page now
990 */
991 if (mac_control->zerodma_virt_addr) {
992 pci_free_consistent(nic->pdev, PAGE_SIZE,
993 mac_control->zerodma_virt_addr,
994 (dma_addr_t)0);
6aa20a22 995 DBG_PRINT(INIT_DBG,
d44570e4
JP		 996 "%s: Freeing TxDL with zero DMA addr. ",
997 dev->name);
6b4d617d 998 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
d44570e4 999 mac_control->zerodma_virt_addr);
8a4bdbaa 1000 nic->mac_control.stats_info->sw_stat.mem_freed
d44570e4 1001 += PAGE_SIZE;
776bd20f 1002 }
13d866a9 1003 kfree(fifo->list_info);
8a4bdbaa 1004 nic->mac_control.stats_info->sw_stat.mem_freed +=
d44570e4
JP		 1005 nic->config.tx_cfg[i].fifo_len *
1006 sizeof(struct list_info_hold);
1da177e4
LT		 1007 }
1008
1da177e4 1009 size = SIZE_OF_BLOCK;
1da177e4 1010 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1011 struct ring_info *ring = &mac_control->rings[i];
1012
1013 blk_cnt = ring->block_count;
1da177e4 1014 for (j = 0; j < blk_cnt; j++) {
13d866a9
JP		 1015 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
1016 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
1da177e4
LT		 1017 if (tmp_v_addr == NULL)
1018 break;
1019 pci_free_consistent(nic->pdev, size,
1020 tmp_v_addr, tmp_p_addr);
491976b2 1021 nic->mac_control.stats_info->sw_stat.mem_freed += size;
13d866a9 1022 kfree(ring->rx_blocks[j].rxds);
8a4bdbaa 1023 nic->mac_control.stats_info->sw_stat.mem_freed +=
d44570e4 1024 sizeof(struct rxd_info) * rxd_count[nic->rxd_mode];
1da177e4
LT		 1025 }
1026 }
1027
6d517a27 1028 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 1029 /* Freeing buffer storage addresses in 2BUFF mode. */
1030 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1031 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1032 struct ring_info *ring = &mac_control->rings[i];
1033
1034 blk_cnt = rx_cfg->num_rxd /
1035 (rxd_count[nic->rxd_mode] + 1);
da6971d8
AR		 1036 for (j = 0; j < blk_cnt; j++) {
1037 int k = 0;
13d866a9 1038 if (!ring->ba[j])
da6971d8
AR		 1039 continue;
1040 while (k != rxd_count[nic->rxd_mode]) {
13d866a9 1041 struct buffAdd *ba = &ring->ba[j][k];
da6971d8 1042 kfree(ba->ba_0_org);
491976b2 1043 nic->mac_control.stats_info->sw_stat.\
d44570e4 1044 mem_freed += (BUF0_LEN + ALIGN_SIZE);
da6971d8 1045 kfree(ba->ba_1_org);
491976b2 1046 nic->mac_control.stats_info->sw_stat.\
d44570e4 1047 mem_freed += (BUF1_LEN + ALIGN_SIZE);
da6971d8
AR		 1048 k++;
1049 }
13d866a9 1050 kfree(ring->ba[j]);
9caab458
SS		 1051 nic->mac_control.stats_info->sw_stat.mem_freed +=
1052 (sizeof(struct buffAdd) *
d44570e4 1053 (rxd_count[nic->rxd_mode] + 1));
1da177e4 1054 }
13d866a9 1055 kfree(ring->ba);
8a4bdbaa 1056 nic->mac_control.stats_info->sw_stat.mem_freed +=
d44570e4 1057 (sizeof(struct buffAdd *) * blk_cnt);
1da177e4 1058 }
1da177e4 1059 }
1da177e4 1060
2fda096d 1061 for (i = 0; i < nic->config.tx_fifo_num; i++) {
13d866a9
JP		 1062 struct fifo_info *fifo = &mac_control->fifos[i];
1063 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1064
1065 if (fifo->ufo_in_band_v) {
2fda096d 1066 nic->mac_control.stats_info->sw_stat.mem_freed
13d866a9
JP		 1067 += (tx_cfg->fifo_len * sizeof(u64));
1068 kfree(fifo->ufo_in_band_v);
2fda096d
SR		 1069 }
1070 }
1071
1da177e4 1072 if (mac_control->stats_mem) {
2fda096d
SR		 1073 nic->mac_control.stats_info->sw_stat.mem_freed +=
1074 mac_control->stats_mem_sz;
1da177e4
LT		 1075 pci_free_consistent(nic->pdev,
1076 mac_control->stats_mem_sz,
1077 mac_control->stats_mem,
1078 mac_control->stats_mem_phy);
491976b2 1079 }
1da177e4
LT		 1080}
1081
541ae68f
K		 1082/**
1083 * s2io_verify_pci_mode -
1084 */
1085
1ee6dd77 1086static int s2io_verify_pci_mode(struct s2io_nic *nic)
541ae68f 1087{
1ee6dd77 1088 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 1089 register u64 val64 = 0;
1090 int mode;
1091
1092 val64 = readq(&bar0->pci_mode);
1093 mode = (u8)GET_PCI_MODE(val64);
1094
d44570e4 1095 if (val64 & PCI_MODE_UNKNOWN_MODE)
541ae68f
K		 1096 return -1; /* Unknown PCI mode */
1097 return mode;
1098}
1099
c92ca04b
AR		 1100#define NEC_VENID 0x1033
1101#define NEC_DEVID 0x0125
1102static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1103{
1104 struct pci_dev *tdev = NULL;
26d36b64
AC		 1105 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1106 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
7ad62dbc 1107 if (tdev->bus == s2io_pdev->bus->parent) {
26d36b64 1108 pci_dev_put(tdev);
c92ca04b 1109 return 1;
7ad62dbc 1110 }
c92ca04b
AR		 1111 }
1112 }
1113 return 0;
1114}
541ae68f 1115
7b32a312 1116static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
541ae68f
K		 1117/**
1118 * s2io_print_pci_mode -
1119 */
1ee6dd77 1120static int s2io_print_pci_mode(struct s2io_nic *nic)
541ae68f 1121{
1ee6dd77 1122 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 1123 register u64 val64 = 0;
1124 int mode;
1125 struct config_param *config = &nic->config;
1126
1127 val64 = readq(&bar0->pci_mode);
1128 mode = (u8)GET_PCI_MODE(val64);
1129
d44570e4 1130 if (val64 & PCI_MODE_UNKNOWN_MODE)
541ae68f
K		 1131 return -1; /* Unknown PCI mode */
1132
c92ca04b
AR		 1133 config->bus_speed = bus_speed[mode];
1134
1135 if (s2io_on_nec_bridge(nic->pdev)) {
1136 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
d44570e4 1137 nic->dev->name);
c92ca04b
AR		 1138 return mode;
1139 }
1140
d44570e4
JP		 1141 DBG_PRINT(ERR_DBG, "%s: Device is on %d bit ",
1142 nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64);
541ae68f 1143
d44570e4
JP		 1144 switch (mode) {
1145 case PCI_MODE_PCI_33:
1146 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
1147 break;
1148 case PCI_MODE_PCI_66:
1149 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
1150 break;
1151 case PCI_MODE_PCIX_M1_66:
1152 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
1153 break;
1154 case PCI_MODE_PCIX_M1_100:
1155 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
1156 break;
1157 case PCI_MODE_PCIX_M1_133:
1158 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
1159 break;
1160 case PCI_MODE_PCIX_M2_66:
1161 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
1162 break;
1163 case PCI_MODE_PCIX_M2_100:
1164 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
1165 break;
1166 case PCI_MODE_PCIX_M2_133:
1167 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
1168 break;
1169 default:
1170 return -1; /* Unsupported bus speed */
541ae68f
K		 1171 }
1172
1173 return mode;
1174}
1175
b7c5678f
RV		 1176/**
1177 * init_tti - Initialization transmit traffic interrupt scheme
1178 * @nic: device private variable
1179 * @link: link status (UP/DOWN) used to enable/disable continuous
1180 * transmit interrupts
1181 * Description: The function configures transmit traffic interrupts
1182 * Return Value: SUCCESS on success and
1183 * '-1' on failure
1184 */
1185
0d66afe7 1186static int init_tti(struct s2io_nic *nic, int link)
b7c5678f
RV		 1187{
1188 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1189 register u64 val64 = 0;
1190 int i;
1191 struct config_param *config;
1192
1193 config = &nic->config;
1194
1195 for (i = 0; i < config->tx_fifo_num; i++) {
1196 /*
1197 * TTI Initialization. Default Tx timer gets us about
1198 * 250 interrupts per sec. Continuous interrupts are enabled
1199 * by default.
1200 */
1201 if (nic->device_type == XFRAME_II_DEVICE) {
1202 int count = (nic->config.bus_speed * 125)/2;
1203 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1204 } else
1205 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1206
1207 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
d44570e4
JP		 1208 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1209 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1210 TTI_DATA1_MEM_TX_TIMER_AC_EN;
ac731ab6
SH		 1211 if (i == 0)
1212 if (use_continuous_tx_intrs && (link == LINK_UP))
1213 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
b7c5678f
RV		 1214 writeq(val64, &bar0->tti_data1_mem);
1215
ac731ab6
SH		 1216 if (nic->config.intr_type == MSI_X) {
1217 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1218 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1219 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1220 TTI_DATA2_MEM_TX_UFC_D(0x300);
1221 } else {
1222 if ((nic->config.tx_steering_type ==
d44570e4
JP		 1223 TX_DEFAULT_STEERING) &&
1224 (config->tx_fifo_num > 1) &&
1225 (i >= nic->udp_fifo_idx) &&
1226 (i < (nic->udp_fifo_idx +
1227 nic->total_udp_fifos)))
ac731ab6
SH		 1228 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1229 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1230 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1231 TTI_DATA2_MEM_TX_UFC_D(0x120);
1232 else
1233 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1234 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1235 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1236 TTI_DATA2_MEM_TX_UFC_D(0x80);
1237 }
b7c5678f
RV		 1238
1239 writeq(val64, &bar0->tti_data2_mem);
1240
d44570e4
JP		 1241 val64 = TTI_CMD_MEM_WE |
1242 TTI_CMD_MEM_STROBE_NEW_CMD |
1243 TTI_CMD_MEM_OFFSET(i);
b7c5678f
RV		 1244 writeq(val64, &bar0->tti_command_mem);
1245
1246 if (wait_for_cmd_complete(&bar0->tti_command_mem,
d44570e4
JP		 1247 TTI_CMD_MEM_STROBE_NEW_CMD,
1248 S2IO_BIT_RESET) != SUCCESS)
b7c5678f
RV		 1249 return FAILURE;
1250 }
1251
1252 return SUCCESS;
1253}
1254
20346722
K		 1255/**
1256 * init_nic - Initialization of hardware
b7c5678f 1257 * @nic: device private variable
20346722
K		 1258 * Description: The function sequentially configures every block
1259 * of the H/W from their reset values.
1260 * Return Value: SUCCESS on success and
1da177e4
LT		 1261 * '-1' on failure (endian settings incorrect).
1262 */
1263
1264static int init_nic(struct s2io_nic *nic)
1265{
1ee6dd77 1266 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1267 struct net_device *dev = nic->dev;
1268 register u64 val64 = 0;
1269 void __iomem *add;
1270 u32 time;
1271 int i, j;
1ee6dd77 1272 struct mac_info *mac_control;
1da177e4 1273 struct config_param *config;
c92ca04b 1274 int dtx_cnt = 0;
1da177e4 1275 unsigned long long mem_share;
20346722 1276 int mem_size;
1da177e4
LT		 1277
1278 mac_control = &nic->mac_control;
1279 config = &nic->config;
1280
5e25b9dd 1281 /* to set the swapper controle on the card */
d44570e4
JP		 1282 if (s2io_set_swapper(nic)) {
1283 DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
9f74ffde 1284 return -EIO;
1da177e4
LT		 1285 }
1286
541ae68f
K		 1287 /*
1288 * Herc requires EOI to be removed from reset before XGXS, so..
1289 */
1290 if (nic->device_type & XFRAME_II_DEVICE) {
1291 val64 = 0xA500000000ULL;
1292 writeq(val64, &bar0->sw_reset);
1293 msleep(500);
1294 val64 = readq(&bar0->sw_reset);
1295 }
1296
1da177e4
LT		 1297 /* Remove XGXS from reset state */
1298 val64 = 0;
1299 writeq(val64, &bar0->sw_reset);
1da177e4 1300 msleep(500);
20346722 1301 val64 = readq(&bar0->sw_reset);
1da177e4 1302
7962024e
SH		 1303 /* Ensure that it's safe to access registers by checking
1304 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1305 */
1306 if (nic->device_type == XFRAME_II_DEVICE) {
1307 for (i = 0; i < 50; i++) {
1308 val64 = readq(&bar0->adapter_status);
1309 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1310 break;
1311 msleep(10);
1312 }
1313 if (i == 50)
1314 return -ENODEV;
1315 }
1316
1da177e4
LT		 1317 /* Enable Receiving broadcasts */
1318 add = &bar0->mac_cfg;
1319 val64 = readq(&bar0->mac_cfg);
1320 val64 |= MAC_RMAC_BCAST_ENABLE;
1321 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 1322 writel((u32)val64, add);
1da177e4
LT		 1323 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1324 writel((u32) (val64 >> 32), (add + 4));
1325
1326 /* Read registers in all blocks */
1327 val64 = readq(&bar0->mac_int_mask);
1328 val64 = readq(&bar0->mc_int_mask);
1329 val64 = readq(&bar0->xgxs_int_mask);
1330
1331 /* Set MTU */
1332 val64 = dev->mtu;
1333 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1334
541ae68f
K		 1335 if (nic->device_type & XFRAME_II_DEVICE) {
1336 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
303bcb4b 1337 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1da177e4 1338 &bar0->dtx_control, UF);
541ae68f
K		 1339 if (dtx_cnt & 0x1)
1340 msleep(1); /* Necessary!! */
1da177e4
LT		 1341 dtx_cnt++;
1342 }
541ae68f 1343 } else {
c92ca04b
AR		 1344 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1345 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1346 &bar0->dtx_control, UF);
1347 val64 = readq(&bar0->dtx_control);
1348 dtx_cnt++;
1da177e4
LT		 1349 }
1350 }
1351
1352 /* Tx DMA Initialization */
1353 val64 = 0;
1354 writeq(val64, &bar0->tx_fifo_partition_0);
1355 writeq(val64, &bar0->tx_fifo_partition_1);
1356 writeq(val64, &bar0->tx_fifo_partition_2);
1357 writeq(val64, &bar0->tx_fifo_partition_3);
1358
1da177e4 1359 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 1360 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1361
1362 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1363 vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1da177e4
LT		 1364
1365 if (i == (config->tx_fifo_num - 1)) {
1366 if (i % 2 == 0)
1367 i++;
1368 }
1369
1370 switch (i) {
1371 case 1:
1372 writeq(val64, &bar0->tx_fifo_partition_0);
1373 val64 = 0;
b7c5678f 1374 j = 0;
1da177e4
LT		 1375 break;
1376 case 3:
1377 writeq(val64, &bar0->tx_fifo_partition_1);
1378 val64 = 0;
b7c5678f 1379 j = 0;
1da177e4
LT		 1380 break;
1381 case 5:
1382 writeq(val64, &bar0->tx_fifo_partition_2);
1383 val64 = 0;
b7c5678f 1384 j = 0;
1da177e4
LT		 1385 break;
1386 case 7:
1387 writeq(val64, &bar0->tx_fifo_partition_3);
b7c5678f
RV		 1388 val64 = 0;
1389 j = 0;
1390 break;
1391 default:
1392 j++;
1da177e4
LT		 1393 break;
1394 }
1395 }
1396
5e25b9dd
K		 1397 /*
1398 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1399 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1400 */
d44570e4 1401 if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
5e25b9dd
K		 1402 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1403
1da177e4
LT		 1404 val64 = readq(&bar0->tx_fifo_partition_0);
1405 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
d44570e4 1406 &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1da177e4 1407
20346722
K		 1408 /*
1409 * Initialization of Tx_PA_CONFIG register to ignore packet
1da177e4
LT		 1410 * integrity checking.
1411 */
1412 val64 = readq(&bar0->tx_pa_cfg);
d44570e4
JP		 1413 val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1414 TX_PA_CFG_IGNORE_SNAP_OUI |
1415 TX_PA_CFG_IGNORE_LLC_CTRL |
1416 TX_PA_CFG_IGNORE_L2_ERR;
1da177e4
LT		 1417 writeq(val64, &bar0->tx_pa_cfg);
1418
1419 /* Rx DMA intialization. */
1420 val64 = 0;
1421 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1422 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1423
1424 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1da177e4
LT		 1425 }
1426 writeq(val64, &bar0->rx_queue_priority);
1427
20346722
K		 1428 /*
1429 * Allocating equal share of memory to all the
1da177e4
LT		 1430 * configured Rings.
1431 */
1432 val64 = 0;
541ae68f
K		 1433 if (nic->device_type & XFRAME_II_DEVICE)
1434 mem_size = 32;
1435 else
1436 mem_size = 64;
1437
1da177e4
LT		 1438 for (i = 0; i < config->rx_ring_num; i++) {
1439 switch (i) {
1440 case 0:
20346722
K		 1441 mem_share = (mem_size / config->rx_ring_num +
1442 mem_size % config->rx_ring_num);
1da177e4
LT		 1443 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1444 continue;
1445 case 1:
20346722 1446 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1447 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1448 continue;
1449 case 2:
20346722 1450 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1451 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1452 continue;
1453 case 3:
20346722 1454 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1455 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1456 continue;
1457 case 4:
20346722 1458 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1459 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1460 continue;
1461 case 5:
20346722 1462 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1463 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1464 continue;
1465 case 6:
20346722 1466 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1467 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1468 continue;
1469 case 7:
20346722 1470 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1471 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1472 continue;
1473 }
1474 }
1475 writeq(val64, &bar0->rx_queue_cfg);
1476
20346722 1477 /*
5e25b9dd 1478 * Filling Tx round robin registers
b7c5678f 1479 * as per the number of FIFOs for equal scheduling priority
1da177e4 1480 */
5e25b9dd
K		 1481 switch (config->tx_fifo_num) {
1482 case 1:
b7c5678f 1483 val64 = 0x0;
5e25b9dd
K		 1484 writeq(val64, &bar0->tx_w_round_robin_0);
1485 writeq(val64, &bar0->tx_w_round_robin_1);
1486 writeq(val64, &bar0->tx_w_round_robin_2);
1487 writeq(val64, &bar0->tx_w_round_robin_3);
1488 writeq(val64, &bar0->tx_w_round_robin_4);
1489 break;
1490 case 2:
b7c5678f 1491 val64 = 0x0001000100010001ULL;
5e25b9dd 1492 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1493 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1494 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1495 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1496 val64 = 0x0001000100000000ULL;
5e25b9dd
K		 1497 writeq(val64, &bar0->tx_w_round_robin_4);
1498 break;
1499 case 3:
b7c5678f 1500 val64 = 0x0001020001020001ULL;
5e25b9dd 1501 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1502 val64 = 0x0200010200010200ULL;
5e25b9dd 1503 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1504 val64 = 0x0102000102000102ULL;
5e25b9dd 1505 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1506 val64 = 0x0001020001020001ULL;
5e25b9dd 1507 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1508 val64 = 0x0200010200000000ULL;
5e25b9dd
K		 1509 writeq(val64, &bar0->tx_w_round_robin_4);
1510 break;
1511 case 4:
b7c5678f 1512 val64 = 0x0001020300010203ULL;
5e25b9dd 1513 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1514 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1515 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1516 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1517 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1518 writeq(val64, &bar0->tx_w_round_robin_4);
1519 break;
1520 case 5:
b7c5678f 1521 val64 = 0x0001020304000102ULL;
5e25b9dd 1522 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1523 val64 = 0x0304000102030400ULL;
5e25b9dd 1524 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1525 val64 = 0x0102030400010203ULL;
5e25b9dd 1526 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1527 val64 = 0x0400010203040001ULL;
5e25b9dd 1528 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1529 val64 = 0x0203040000000000ULL;
5e25b9dd
K		 1530 writeq(val64, &bar0->tx_w_round_robin_4);
1531 break;
1532 case 6:
b7c5678f 1533 val64 = 0x0001020304050001ULL;
5e25b9dd 1534 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1535 val64 = 0x0203040500010203ULL;
5e25b9dd 1536 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1537 val64 = 0x0405000102030405ULL;
5e25b9dd 1538 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1539 val64 = 0x0001020304050001ULL;
5e25b9dd 1540 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1541 val64 = 0x0203040500000000ULL;
5e25b9dd
K		 1542 writeq(val64, &bar0->tx_w_round_robin_4);
1543 break;
1544 case 7:
b7c5678f 1545 val64 = 0x0001020304050600ULL;
5e25b9dd 1546 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1547 val64 = 0x0102030405060001ULL;
5e25b9dd 1548 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1549 val64 = 0x0203040506000102ULL;
5e25b9dd 1550 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1551 val64 = 0x0304050600010203ULL;
5e25b9dd 1552 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1553 val64 = 0x0405060000000000ULL;
5e25b9dd
K		 1554 writeq(val64, &bar0->tx_w_round_robin_4);
1555 break;
1556 case 8:
b7c5678f 1557 val64 = 0x0001020304050607ULL;
5e25b9dd 1558 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1559 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1560 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1561 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1562 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1563 writeq(val64, &bar0->tx_w_round_robin_4);
1564 break;
1565 }
1566
b41477f3 1567 /* Enable all configured Tx FIFO partitions */
5d3213cc
AR		 1568 val64 = readq(&bar0->tx_fifo_partition_0);
1569 val64 |= (TX_FIFO_PARTITION_EN);
1570 writeq(val64, &bar0->tx_fifo_partition_0);
1571
5e25b9dd 1572 /* Filling the Rx round robin registers as per the
0425b46a
SH		 1573 * number of Rings and steering based on QoS with
1574 * equal priority.
1575 */
5e25b9dd
K		 1576 switch (config->rx_ring_num) {
1577 case 1:
0425b46a
SH		 1578 val64 = 0x0;
1579 writeq(val64, &bar0->rx_w_round_robin_0);
1580 writeq(val64, &bar0->rx_w_round_robin_1);
1581 writeq(val64, &bar0->rx_w_round_robin_2);
1582 writeq(val64, &bar0->rx_w_round_robin_3);
1583 writeq(val64, &bar0->rx_w_round_robin_4);
1584
5e25b9dd
K		 1585 val64 = 0x8080808080808080ULL;
1586 writeq(val64, &bar0->rts_qos_steering);
1587 break;
1588 case 2:
0425b46a 1589 val64 = 0x0001000100010001ULL;
5e25b9dd 1590 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1591 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1592 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1593 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1594 val64 = 0x0001000100000000ULL;
5e25b9dd
K		 1595 writeq(val64, &bar0->rx_w_round_robin_4);
1596
1597 val64 = 0x8080808040404040ULL;
1598 writeq(val64, &bar0->rts_qos_steering);
1599 break;
1600 case 3:
0425b46a 1601 val64 = 0x0001020001020001ULL;
5e25b9dd 1602 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1603 val64 = 0x0200010200010200ULL;
5e25b9dd 1604 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1605 val64 = 0x0102000102000102ULL;
5e25b9dd 1606 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1607 val64 = 0x0001020001020001ULL;
5e25b9dd 1608 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1609 val64 = 0x0200010200000000ULL;
5e25b9dd
K		 1610 writeq(val64, &bar0->rx_w_round_robin_4);
1611
1612 val64 = 0x8080804040402020ULL;
1613 writeq(val64, &bar0->rts_qos_steering);
1614 break;
1615 case 4:
0425b46a 1616 val64 = 0x0001020300010203ULL;
5e25b9dd 1617 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1618 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1619 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1620 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1621 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1622 writeq(val64, &bar0->rx_w_round_robin_4);
1623
1624 val64 = 0x8080404020201010ULL;
1625 writeq(val64, &bar0->rts_qos_steering);
1626 break;
1627 case 5:
0425b46a 1628 val64 = 0x0001020304000102ULL;
5e25b9dd 1629 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1630 val64 = 0x0304000102030400ULL;
5e25b9dd 1631 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1632 val64 = 0x0102030400010203ULL;
5e25b9dd 1633 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1634 val64 = 0x0400010203040001ULL;
5e25b9dd 1635 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1636 val64 = 0x0203040000000000ULL;
5e25b9dd
K		 1637 writeq(val64, &bar0->rx_w_round_robin_4);
1638
1639 val64 = 0x8080404020201008ULL;
1640 writeq(val64, &bar0->rts_qos_steering);
1641 break;
1642 case 6:
0425b46a 1643 val64 = 0x0001020304050001ULL;
5e25b9dd 1644 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1645 val64 = 0x0203040500010203ULL;
5e25b9dd 1646 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1647 val64 = 0x0405000102030405ULL;
5e25b9dd 1648 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1649 val64 = 0x0001020304050001ULL;
5e25b9dd 1650 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1651 val64 = 0x0203040500000000ULL;
5e25b9dd
K		 1652 writeq(val64, &bar0->rx_w_round_robin_4);
1653
1654 val64 = 0x8080404020100804ULL;
1655 writeq(val64, &bar0->rts_qos_steering);
1656 break;
1657 case 7:
0425b46a 1658 val64 = 0x0001020304050600ULL;
5e25b9dd 1659 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1660 val64 = 0x0102030405060001ULL;
5e25b9dd 1661 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1662 val64 = 0x0203040506000102ULL;
5e25b9dd 1663 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1664 val64 = 0x0304050600010203ULL;
5e25b9dd 1665 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1666 val64 = 0x0405060000000000ULL;
5e25b9dd
K		 1667 writeq(val64, &bar0->rx_w_round_robin_4);
1668
1669 val64 = 0x8080402010080402ULL;
1670 writeq(val64, &bar0->rts_qos_steering);
1671 break;
1672 case 8:
0425b46a 1673 val64 = 0x0001020304050607ULL;
5e25b9dd 1674 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1675 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1676 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1677 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1678 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1679 writeq(val64, &bar0->rx_w_round_robin_4);
1680
1681 val64 = 0x8040201008040201ULL;
1682 writeq(val64, &bar0->rts_qos_steering);
1683 break;
1684 }
1da177e4
LT		 1685
1686 /* UDP Fix */
1687 val64 = 0;
20346722 1688 for (i = 0; i < 8; i++)
1da177e4
LT		 1689 writeq(val64, &bar0->rts_frm_len_n[i]);
1690
5e25b9dd
K		 1691 /* Set the default rts frame length for the rings configured */
1692 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1693 for (i = 0 ; i < config->rx_ring_num ; i++)
1694 writeq(val64, &bar0->rts_frm_len_n[i]);
1695
1696 /* Set the frame length for the configured rings
1697 * desired by the user
1698 */
1699 for (i = 0; i < config->rx_ring_num; i++) {
1700 /* If rts_frm_len[i] == 0 then it is assumed that user not
1701 * specified frame length steering.
1702 * If the user provides the frame length then program
1703 * the rts_frm_len register for those values or else
1704 * leave it as it is.
1705 */
1706 if (rts_frm_len[i] != 0) {
1707 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
d44570e4 1708 &bar0->rts_frm_len_n[i]);
5e25b9dd
K		 1709 }
1710 }
8a4bdbaa 1711
9fc93a41
SS		 1712 /* Disable differentiated services steering logic */
1713 for (i = 0; i < 64; i++) {
1714 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1715 DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
d44570e4 1716 dev->name);
9fc93a41 1717 DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
9f74ffde 1718 return -ENODEV;
9fc93a41
SS		 1719 }
1720 }
1721
20346722 1722 /* Program statistics memory */
1da177e4 1723 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1da177e4 1724
541ae68f
K		 1725 if (nic->device_type == XFRAME_II_DEVICE) {
1726 val64 = STAT_BC(0x320);
1727 writeq(val64, &bar0->stat_byte_cnt);
1728 }
1729
20346722 1730 /*
1da177e4
LT		 1731 * Initializing the sampling rate for the device to calculate the
1732 * bandwidth utilization.
1733 */
1734 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
d44570e4 1735 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1da177e4
LT		 1736 writeq(val64, &bar0->mac_link_util);
1737
20346722
K		 1738 /*
1739 * Initializing the Transmit and Receive Traffic Interrupt
1da177e4
LT		 1740 * Scheme.
1741 */
1da177e4 1742
b7c5678f
RV		 1743 /* Initialize TTI */
1744 if (SUCCESS != init_tti(nic, nic->last_link_state))
1745 return -ENODEV;
1da177e4 1746
8a4bdbaa
SS		 1747 /* RTI Initialization */
1748 if (nic->device_type == XFRAME_II_DEVICE) {
541ae68f 1749 /*
8a4bdbaa
SS		 1750 * Programmed to generate Apprx 500 Intrs per
1751 * second
1752 */
1753 int count = (nic->config.bus_speed * 125)/4;
1754 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1755 } else
1756 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1757 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
d44570e4
JP		 1758 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1759 RTI_DATA1_MEM_RX_URNG_C(0x30) |
1760 RTI_DATA1_MEM_RX_TIMER_AC_EN;
8a4bdbaa
SS		 1761
1762 writeq(val64, &bar0->rti_data1_mem);
1763
1764 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1765 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1766 if (nic->config.intr_type == MSI_X)
d44570e4
JP		 1767 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1768 RTI_DATA2_MEM_RX_UFC_D(0x40));
8a4bdbaa 1769 else
d44570e4
JP		 1770 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1771 RTI_DATA2_MEM_RX_UFC_D(0x80));
8a4bdbaa 1772 writeq(val64, &bar0->rti_data2_mem);
1da177e4 1773
8a4bdbaa 1774 for (i = 0; i < config->rx_ring_num; i++) {
d44570e4
JP		 1775 val64 = RTI_CMD_MEM_WE |
1776 RTI_CMD_MEM_STROBE_NEW_CMD |
1777 RTI_CMD_MEM_OFFSET(i);
8a4bdbaa 1778 writeq(val64, &bar0->rti_command_mem);
1da177e4 1779
8a4bdbaa
SS		 1780 /*
1781 * Once the operation completes, the Strobe bit of the
1782 * command register will be reset. We poll for this
1783 * particular condition. We wait for a maximum of 500ms
1784 * for the operation to complete, if it's not complete
1785 * by then we return error.
1786 */
1787 time = 0;
f957bcf0 1788 while (true) {
8a4bdbaa
SS		 1789 val64 = readq(&bar0->rti_command_mem);
1790 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1791 break;
b6e3f982 1792
8a4bdbaa
SS		 1793 if (time > 10) {
1794 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1795 dev->name);
9f74ffde 1796 return -ENODEV;
b6e3f982 1797 }
8a4bdbaa
SS		 1798 time++;
1799 msleep(50);
1da177e4 1800 }
1da177e4
LT		 1801 }
1802
20346722
K		 1803 /*
1804 * Initializing proper values as Pause threshold into all
1da177e4
LT		 1805 * the 8 Queues on Rx side.
1806 */
1807 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1808 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1809
1810 /* Disable RMAC PAD STRIPPING */
509a2671 1811 add = &bar0->mac_cfg;
1da177e4
LT		 1812 val64 = readq(&bar0->mac_cfg);
1813 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1814 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1815 writel((u32) (val64), add);
1816 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1817 writel((u32) (val64 >> 32), (add + 4));
1818 val64 = readq(&bar0->mac_cfg);
1819
7d3d0439
RA		 1820 /* Enable FCS stripping by adapter */
1821 add = &bar0->mac_cfg;
1822 val64 = readq(&bar0->mac_cfg);
1823 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1824 if (nic->device_type == XFRAME_II_DEVICE)
1825 writeq(val64, &bar0->mac_cfg);
1826 else {
1827 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1828 writel((u32) (val64), add);
1829 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1830 writel((u32) (val64 >> 32), (add + 4));
1831 }
1832
20346722
K		 1833 /*
1834 * Set the time value to be inserted in the pause frame
1da177e4
LT		 1835 * generated by xena.
1836 */
1837 val64 = readq(&bar0->rmac_pause_cfg);
1838 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1839 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1840 writeq(val64, &bar0->rmac_pause_cfg);
1841
20346722 1842 /*
1da177e4
LT		 1843 * Set the Threshold Limit for Generating the pause frame
1844 * If the amount of data in any Queue exceeds ratio of
1845 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1846 * pause frame is generated
1847 */
1848 val64 = 0;
1849 for (i = 0; i < 4; i++) {
d44570e4
JP		 1850 val64 |= (((u64)0xFF00 |
1851 nic->mac_control.mc_pause_threshold_q0q3)
1852 << (i * 2 * 8));
1da177e4
LT		 1853 }
1854 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1855
1856 val64 = 0;
1857 for (i = 0; i < 4; i++) {
d44570e4
JP		 1858 val64 |= (((u64)0xFF00 |
1859 nic->mac_control.mc_pause_threshold_q4q7)
1860 << (i * 2 * 8));
1da177e4
LT		 1861 }
1862 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1863
20346722
K		 1864 /*
1865 * TxDMA will stop Read request if the number of read split has
1da177e4
LT		 1866 * exceeded the limit pointed by shared_splits
1867 */
1868 val64 = readq(&bar0->pic_control);
1869 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1870 writeq(val64, &bar0->pic_control);
1871
863c11a9
AR		 1872 if (nic->config.bus_speed == 266) {
1873 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1874 writeq(0x0, &bar0->read_retry_delay);
1875 writeq(0x0, &bar0->write_retry_delay);
1876 }
1877
541ae68f
K		 1878 /*
1879 * Programming the Herc to split every write transaction
1880 * that does not start on an ADB to reduce disconnects.
1881 */
1882 if (nic->device_type == XFRAME_II_DEVICE) {
19a60522
SS		 1883 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1884 MISC_LINK_STABILITY_PRD(3);
863c11a9
AR		 1885 writeq(val64, &bar0->misc_control);
1886 val64 = readq(&bar0->pic_control2);
b7b5a128 1887 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
863c11a9 1888 writeq(val64, &bar0->pic_control2);
541ae68f 1889 }
c92ca04b
AR		 1890 if (strstr(nic->product_name, "CX4")) {
1891 val64 = TMAC_AVG_IPG(0x17);
1892 writeq(val64, &bar0->tmac_avg_ipg);
a371a07d
K		 1893 }
1894
1da177e4
LT		 1895 return SUCCESS;
1896}
a371a07d
K		 1897#define LINK_UP_DOWN_INTERRUPT 1
1898#define MAC_RMAC_ERR_TIMER 2
1899
1ee6dd77 1900static int s2io_link_fault_indication(struct s2io_nic *nic)
a371a07d
K		 1901{
1902 if (nic->device_type == XFRAME_II_DEVICE)
1903 return LINK_UP_DOWN_INTERRUPT;
1904 else
1905 return MAC_RMAC_ERR_TIMER;
1906}
8116f3cf 1907
9caab458
SS		 1908/**
1909 * do_s2io_write_bits - update alarm bits in alarm register
1910 * @value: alarm bits
1911 * @flag: interrupt status
1912 * @addr: address value
1913 * Description: update alarm bits in alarm register
1914 * Return Value:
1915 * NONE.
1916 */
1917static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1918{
1919 u64 temp64;
1920
1921 temp64 = readq(addr);
1922
d44570e4
JP		 1923 if (flag == ENABLE_INTRS)
1924 temp64 &= ~((u64)value);
9caab458 1925 else
d44570e4 1926 temp64 |= ((u64)value);
9caab458
SS		 1927 writeq(temp64, addr);
1928}
1da177e4 1929
43b7c451 1930static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
9caab458
SS		 1931{
1932 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1933 register u64 gen_int_mask = 0;
01e16faa 1934 u64 interruptible;
9caab458 1935
01e16faa 1936 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
9caab458 1937 if (mask & TX_DMA_INTR) {
9caab458
SS		 1938 gen_int_mask |= TXDMA_INT_M;
1939
1940 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
d44570e4
JP		 1941 TXDMA_PCC_INT | TXDMA_TTI_INT |
1942 TXDMA_LSO_INT | TXDMA_TPA_INT |
1943 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
9caab458
SS		 1944
1945 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
d44570e4
JP		 1946 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1947 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1948 &bar0->pfc_err_mask);
9caab458
SS		 1949
1950 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
d44570e4
JP		 1951 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1952 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
9caab458
SS		 1953
1954 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
d44570e4
JP		 1955 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1956 PCC_N_SERR | PCC_6_COF_OV_ERR |
1957 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1958 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1959 PCC_TXB_ECC_SG_ERR,
1960 flag, &bar0->pcc_err_mask);
9caab458
SS		 1961
1962 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
d44570e4 1963 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
9caab458
SS		 1964
1965 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
d44570e4
JP		 1966 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1967 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1968 flag, &bar0->lso_err_mask);
9caab458
SS		 1969
1970 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
d44570e4 1971 flag, &bar0->tpa_err_mask);
9caab458
SS		 1972
1973 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
9caab458
SS		 1974 }
1975
1976 if (mask & TX_MAC_INTR) {
1977 gen_int_mask |= TXMAC_INT_M;
1978 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
d44570e4 1979 &bar0->mac_int_mask);
9caab458 1980 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
d44570e4
JP		 1981 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1982 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1983 flag, &bar0->mac_tmac_err_mask);
9caab458
SS		 1984 }
1985
1986 if (mask & TX_XGXS_INTR) {
1987 gen_int_mask |= TXXGXS_INT_M;
1988 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
d44570e4 1989 &bar0->xgxs_int_mask);
9caab458 1990 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
d44570e4
JP		 1991 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1992 flag, &bar0->xgxs_txgxs_err_mask);
9caab458
SS		 1993 }
1994
1995 if (mask & RX_DMA_INTR) {
1996 gen_int_mask |= RXDMA_INT_M;
1997 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
d44570e4
JP		 1998 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1999 flag, &bar0->rxdma_int_mask);
9caab458 2000 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
d44570e4
JP		 2001 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
2002 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
2003 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
9caab458 2004 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
d44570e4
JP		 2005 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
2006 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
2007 &bar0->prc_pcix_err_mask);
9caab458 2008 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
d44570e4
JP		 2009 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
2010 &bar0->rpa_err_mask);
9caab458 2011 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
d44570e4
JP		 2012 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
2013 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
2014 RDA_FRM_ECC_SG_ERR |
2015 RDA_MISC_ERR|RDA_PCIX_ERR,
2016 flag, &bar0->rda_err_mask);
9caab458 2017 do_s2io_write_bits(RTI_SM_ERR_ALARM |
d44570e4
JP		 2018 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2019 flag, &bar0->rti_err_mask);
9caab458
SS		 2020 }
2021
2022 if (mask & RX_MAC_INTR) {
2023 gen_int_mask |= RXMAC_INT_M;
2024 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
d44570e4
JP		 2025 &bar0->mac_int_mask);
2026 interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2027 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2028 RMAC_DOUBLE_ECC_ERR);
01e16faa
SH		 2029 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2030 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2031 do_s2io_write_bits(interruptible,
d44570e4 2032 flag, &bar0->mac_rmac_err_mask);
9caab458
SS		 2033 }
2034
d44570e4 2035 if (mask & RX_XGXS_INTR) {
9caab458
SS		 2036 gen_int_mask |= RXXGXS_INT_M;
2037 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
d44570e4 2038 &bar0->xgxs_int_mask);
9caab458 2039 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
d44570e4 2040 &bar0->xgxs_rxgxs_err_mask);
9caab458
SS		 2041 }
2042
2043 if (mask & MC_INTR) {
2044 gen_int_mask |= MC_INT_M;
d44570e4
JP		 2045 do_s2io_write_bits(MC_INT_MASK_MC_INT,
2046 flag, &bar0->mc_int_mask);
9caab458 2047 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
d44570e4
JP		 2048 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2049 &bar0->mc_err_mask);
9caab458
SS		 2050 }
2051 nic->general_int_mask = gen_int_mask;
2052
2053 /* Remove this line when alarm interrupts are enabled */
2054 nic->general_int_mask = 0;
2055}
d44570e4 2056
20346722
K		 2057/**
2058 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1da177e4
LT		 2059 * @nic: device private variable,
2060 * @mask: A mask indicating which Intr block must be modified and,
2061 * @flag: A flag indicating whether to enable or disable the Intrs.
2062 * Description: This function will either disable or enable the interrupts
20346722
K		 2063 * depending on the flag argument. The mask argument can be used to
2064 * enable/disable any Intr block.
1da177e4
LT		 2065 * Return Value: NONE.
2066 */
2067
2068static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2069{
1ee6dd77 2070 struct XENA_dev_config __iomem *bar0 = nic->bar0;
9caab458
SS		 2071 register u64 temp64 = 0, intr_mask = 0;
2072
2073 intr_mask = nic->general_int_mask;
1da177e4
LT		 2074
2075 /* Top level interrupt classification */
2076 /* PIC Interrupts */
9caab458 2077 if (mask & TX_PIC_INTR) {
1da177e4 2078 /* Enable PIC Intrs in the general intr mask register */
9caab458 2079 intr_mask |= TXPIC_INT_M;
1da177e4 2080 if (flag == ENABLE_INTRS) {
20346722 2081 /*
a371a07d 2082 * If Hercules adapter enable GPIO otherwise
b41477f3 2083 * disable all PCIX, Flash, MDIO, IIC and GPIO
20346722
K		 2084 * interrupts for now.
2085 * TODO
1da177e4 2086 */
a371a07d 2087 if (s2io_link_fault_indication(nic) ==
d44570e4 2088 LINK_UP_DOWN_INTERRUPT) {
9caab458 2089 do_s2io_write_bits(PIC_INT_GPIO, flag,
d44570e4 2090 &bar0->pic_int_mask);
9caab458 2091 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
d44570e4 2092 &bar0->gpio_int_mask);
9caab458 2093 } else
a371a07d 2094 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4 2095 } else if (flag == DISABLE_INTRS) {
20346722
K		 2096 /*
2097 * Disable PIC Intrs in the general
2098 * intr mask register
1da177e4
LT		 2099 */
2100 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4
LT		 2101 }
2102 }
2103
1da177e4
LT		 2104 /* Tx traffic interrupts */
2105 if (mask & TX_TRAFFIC_INTR) {
9caab458 2106 intr_mask |= TXTRAFFIC_INT_M;
1da177e4 2107 if (flag == ENABLE_INTRS) {
20346722 2108 /*
1da177e4 2109 * Enable all the Tx side interrupts
20346722 2110 * writing 0 Enables all 64 TX interrupt levels
1da177e4
LT		 2111 */
2112 writeq(0x0, &bar0->tx_traffic_mask);
2113 } else if (flag == DISABLE_INTRS) {
20346722
K		 2114 /*
2115 * Disable Tx Traffic Intrs in the general intr mask
1da177e4
LT		 2116 * register.
2117 */
2118 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1da177e4
LT		 2119 }
2120 }
2121
2122 /* Rx traffic interrupts */
2123 if (mask & RX_TRAFFIC_INTR) {
9caab458 2124 intr_mask |= RXTRAFFIC_INT_M;
1da177e4 2125 if (flag == ENABLE_INTRS) {
1da177e4
LT		 2126 /* writing 0 Enables all 8 RX interrupt levels */
2127 writeq(0x0, &bar0->rx_traffic_mask);
2128 } else if (flag == DISABLE_INTRS) {
20346722
K		 2129 /*
2130 * Disable Rx Traffic Intrs in the general intr mask
1da177e4
LT		 2131 * register.
2132 */
2133 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1da177e4
LT		 2134 }
2135 }
9caab458
SS		 2136
2137 temp64 = readq(&bar0->general_int_mask);
2138 if (flag == ENABLE_INTRS)
d44570e4 2139 temp64 &= ~((u64)intr_mask);
9caab458
SS		 2140 else
2141 temp64 = DISABLE_ALL_INTRS;
2142 writeq(temp64, &bar0->general_int_mask);
2143
2144 nic->general_int_mask = readq(&bar0->general_int_mask);
1da177e4
LT		 2145}
2146
19a60522
SS		 2147/**
2148 * verify_pcc_quiescent- Checks for PCC quiescent state
2149 * Return: 1 If PCC is quiescence
2150 * 0 If PCC is not quiescence
2151 */
1ee6dd77 2152static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
20346722 2153{
19a60522 2154 int ret = 0, herc;
1ee6dd77 2155 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522 2156 u64 val64 = readq(&bar0->adapter_status);
8a4bdbaa 2157
19a60522 2158 herc = (sp->device_type == XFRAME_II_DEVICE);
20346722 2159
f957bcf0 2160 if (flag == false) {
44c10138 2161 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
19a60522 2162 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2163 ret = 1;
19a60522
SS		 2164 } else {
2165 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2166 ret = 1;
20346722
K		 2167 }
2168 } else {
44c10138 2169 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
5e25b9dd 2170 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
19a60522 2171 ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2172 ret = 1;
5e25b9dd
K		 2173 } else {
2174 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
19a60522 2175 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2176 ret = 1;
20346722
K		 2177 }
2178 }
2179
2180 return ret;
2181}
2182/**
2183 * verify_xena_quiescence - Checks whether the H/W is ready
1da177e4 2184 * Description: Returns whether the H/W is ready to go or not. Depending
20346722 2185 * on whether adapter enable bit was written or not the comparison
1da177e4
LT		 2186 * differs and the calling function passes the input argument flag to
2187 * indicate this.
20346722 2188 * Return: 1 If xena is quiescence
1da177e4
LT		 2189 * 0 If Xena is not quiescence
2190 */
2191
1ee6dd77 2192static int verify_xena_quiescence(struct s2io_nic *sp)
1da177e4 2193{
19a60522 2194 int mode;
1ee6dd77 2195 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 2196 u64 val64 = readq(&bar0->adapter_status);
2197 mode = s2io_verify_pci_mode(sp);
1da177e4 2198
19a60522
SS		 2199 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2200 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
2201 return 0;
2202 }
2203 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
d44570e4 2204 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
19a60522
SS		 2205 return 0;
2206 }
2207 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2208 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
2209 return 0;
2210 }
2211 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2212 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
2213 return 0;
2214 }
2215 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2216 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
2217 return 0;
2218 }
2219 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2220 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
2221 return 0;
2222 }
2223 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2224 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
2225 return 0;
2226 }
2227 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2228 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
2229 return 0;
1da177e4
LT		 2230 }
2231
19a60522
SS		 2232 /*
2233 * In PCI 33 mode, the P_PLL is not used, and therefore,
2234 * the the P_PLL_LOCK bit in the adapter_status register will
2235 * not be asserted.
2236 */
2237 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
d44570e4
JP		 2238 sp->device_type == XFRAME_II_DEVICE &&
2239 mode != PCI_MODE_PCI_33) {
19a60522
SS		 2240 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
2241 return 0;
2242 }
2243 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
d44570e4 2244 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
19a60522
SS		 2245 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
2246 return 0;
2247 }
2248 return 1;
1da177e4
LT		 2249}
2250
2251/**
2252 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2253 * @sp: Pointer to device specifc structure
20346722 2254 * Description :
1da177e4
LT		 2255 * New procedure to clear mac address reading problems on Alpha platforms
2256 *
2257 */
2258
d44570e4 2259static void fix_mac_address(struct s2io_nic *sp)
1da177e4 2260{
1ee6dd77 2261 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 2262 u64 val64;
2263 int i = 0;
2264
2265 while (fix_mac[i] != END_SIGN) {
2266 writeq(fix_mac[i++], &bar0->gpio_control);
20346722 2267 udelay(10);
1da177e4
LT		 2268 val64 = readq(&bar0->gpio_control);
2269 }
2270}
2271
2272/**
20346722 2273 * start_nic - Turns the device on
1da177e4 2274 * @nic : device private variable.
20346722
K		 2275 * Description:
2276 * This function actually turns the device on. Before this function is
2277 * called,all Registers are configured from their reset states
2278 * and shared memory is allocated but the NIC is still quiescent. On
1da177e4
LT		 2279 * calling this function, the device interrupts are cleared and the NIC is
2280 * literally switched on by writing into the adapter control register.
20346722 2281 * Return Value:
1da177e4
LT		 2282 * SUCCESS on success and -1 on failure.
2283 */
2284
2285static int start_nic(struct s2io_nic *nic)
2286{
1ee6dd77 2287 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 2288 struct net_device *dev = nic->dev;
2289 register u64 val64 = 0;
20346722 2290 u16 subid, i;
1ee6dd77 2291 struct mac_info *mac_control;
1da177e4
LT		 2292 struct config_param *config;
2293
2294 mac_control = &nic->mac_control;
2295 config = &nic->config;
2296
2297 /* PRC Initialization and configuration */
2298 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2299 struct ring_info *ring = &mac_control->rings[i];
2300
d44570e4 2301 writeq((u64)ring->rx_blocks[0].block_dma_addr,
1da177e4
LT		 2302 &bar0->prc_rxd0_n[i]);
2303
2304 val64 = readq(&bar0->prc_ctrl_n[i]);
da6971d8
AR		 2305 if (nic->rxd_mode == RXD_MODE_1)
2306 val64 |= PRC_CTRL_RC_ENABLED;
2307 else
2308 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
863c11a9
AR		 2309 if (nic->device_type == XFRAME_II_DEVICE)
2310 val64 |= PRC_CTRL_GROUP_READS;
2311 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2312 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1da177e4
LT		 2313 writeq(val64, &bar0->prc_ctrl_n[i]);
2314 }
2315
da6971d8
AR		 2316 if (nic->rxd_mode == RXD_MODE_3B) {
2317 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2318 val64 = readq(&bar0->rx_pa_cfg);
2319 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2320 writeq(val64, &bar0->rx_pa_cfg);
2321 }
1da177e4 2322
926930b2
SS		 2323 if (vlan_tag_strip == 0) {
2324 val64 = readq(&bar0->rx_pa_cfg);
2325 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2326 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 2327 nic->vlan_strip_flag = 0;
926930b2
SS		 2328 }
2329
20346722 2330 /*
1da177e4
LT		 2331 * Enabling MC-RLDRAM. After enabling the device, we timeout
2332 * for around 100ms, which is approximately the time required
2333 * for the device to be ready for operation.
2334 */
2335 val64 = readq(&bar0->mc_rldram_mrs);
2336 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2337 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2338 val64 = readq(&bar0->mc_rldram_mrs);
2339
20346722 2340 msleep(100); /* Delay by around 100 ms. */
1da177e4
LT		 2341
2342 /* Enabling ECC Protection. */
2343 val64 = readq(&bar0->adapter_control);
2344 val64 &= ~ADAPTER_ECC_EN;
2345 writeq(val64, &bar0->adapter_control);
2346
20346722
K		 2347 /*
2348 * Verify if the device is ready to be enabled, if so enable
1da177e4
LT		 2349 * it.
2350 */
2351 val64 = readq(&bar0->adapter_status);
19a60522 2352 if (!verify_xena_quiescence(nic)) {
1da177e4
LT		 2353 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2354 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
d44570e4 2355 (unsigned long long)val64);
1da177e4
LT		 2356 return FAILURE;
2357 }
2358
20346722 2359 /*
1da177e4 2360 * With some switches, link might be already up at this point.
20346722
K		 2361 * Because of this weird behavior, when we enable laser,
2362 * we may not get link. We need to handle this. We cannot
2363 * figure out which switch is misbehaving. So we are forced to
2364 * make a global change.
1da177e4
LT		 2365 */
2366
2367 /* Enabling Laser. */
2368 val64 = readq(&bar0->adapter_control);
2369 val64 |= ADAPTER_EOI_TX_ON;
2370 writeq(val64, &bar0->adapter_control);
2371
c92ca04b
AR		 2372 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2373 /*
2374 * Dont see link state interrupts initally on some switches,
2375 * so directly scheduling the link state task here.
2376 */
2377 schedule_work(&nic->set_link_task);
2378 }
1da177e4
LT		 2379 /* SXE-002: Initialize link and activity LED */
2380 subid = nic->pdev->subsystem_device;
541ae68f
K		 2381 if (((subid & 0xFF) >= 0x07) &&
2382 (nic->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 2383 val64 = readq(&bar0->gpio_control);
2384 val64 |= 0x0000800000000000ULL;
2385 writeq(val64, &bar0->gpio_control);
2386 val64 = 0x0411040400000000ULL;
509a2671 2387 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 2388 }
2389
1da177e4
LT		 2390 return SUCCESS;
2391}
fed5eccd
AR		 2392/**
2393 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2394 */
d44570e4
JP		 2395static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2396 struct TxD *txdlp, int get_off)
fed5eccd 2397{
1ee6dd77 2398 struct s2io_nic *nic = fifo_data->nic;
fed5eccd 2399 struct sk_buff *skb;
1ee6dd77 2400 struct TxD *txds;
fed5eccd
AR		 2401 u16 j, frg_cnt;
2402
2403 txds = txdlp;
2fda096d 2404 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
d44570e4
JP		 2405 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2406 sizeof(u64), PCI_DMA_TODEVICE);
fed5eccd
AR		 2407 txds++;
2408 }
2409
d44570e4 2410 skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
fed5eccd 2411 if (!skb) {
1ee6dd77 2412 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2413 return NULL;
2414 }
d44570e4
JP		 2415 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2416 skb->len - skb->data_len, PCI_DMA_TODEVICE);
fed5eccd
AR		 2417 frg_cnt = skb_shinfo(skb)->nr_frags;
2418 if (frg_cnt) {
2419 txds++;
2420 for (j = 0; j < frg_cnt; j++, txds++) {
2421 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2422 if (!txds->Buffer_Pointer)
2423 break;
d44570e4
JP		 2424 pci_unmap_page(nic->pdev,
2425 (dma_addr_t)txds->Buffer_Pointer,
fed5eccd
AR		 2426 frag->size, PCI_DMA_TODEVICE);
2427 }
2428 }
d44570e4
JP		 2429 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2430 return skb;
fed5eccd 2431}
1da177e4 2432
20346722
K		 2433/**
2434 * free_tx_buffers - Free all queued Tx buffers
1da177e4 2435 * @nic : device private variable.
20346722 2436 * Description:
1da177e4 2437 * Free all queued Tx buffers.
20346722 2438 * Return Value: void
d44570e4 2439 */
1da177e4
LT		 2440
2441static void free_tx_buffers(struct s2io_nic *nic)
2442{
2443 struct net_device *dev = nic->dev;
2444 struct sk_buff *skb;
1ee6dd77 2445 struct TxD *txdp;
1da177e4 2446 int i, j;
1ee6dd77 2447 struct mac_info *mac_control;
1da177e4 2448 struct config_param *config;
fed5eccd 2449 int cnt = 0;
1da177e4
LT		 2450
2451 mac_control = &nic->mac_control;
2452 config = &nic->config;
2453
2454 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 2455 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2456 struct fifo_info *fifo = &mac_control->fifos[i];
2fda096d 2457 unsigned long flags;
13d866a9
JP		 2458
2459 spin_lock_irqsave(&fifo->tx_lock, flags);
2460 for (j = 0; j < tx_cfg->fifo_len; j++) {
2461 txdp = (struct TxD *)fifo->list_info[j].list_virt_addr;
fed5eccd
AR		 2462 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2463 if (skb) {
8a4bdbaa 2464 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 2465 += skb->truesize;
fed5eccd
AR		 2466 dev_kfree_skb(skb);
2467 cnt++;
1da177e4 2468 }
1da177e4
LT		 2469 }
2470 DBG_PRINT(INTR_DBG,
2471 "%s:forcibly freeing %d skbs on FIFO%d\n",
2472 dev->name, cnt, i);
13d866a9
JP		 2473 fifo->tx_curr_get_info.offset = 0;
2474 fifo->tx_curr_put_info.offset = 0;
2475 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4
LT		 2476 }
2477}
2478
20346722
K		 2479/**
2480 * stop_nic - To stop the nic
1da177e4 2481 * @nic ; device private variable.
20346722
K		 2482 * Description:
2483 * This function does exactly the opposite of what the start_nic()
1da177e4
LT		 2484 * function does. This function is called to stop the device.
2485 * Return Value:
2486 * void.
2487 */
2488
2489static void stop_nic(struct s2io_nic *nic)
2490{
1ee6dd77 2491 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 2492 register u64 val64 = 0;
5d3213cc 2493 u16 interruptible;
1ee6dd77 2494 struct mac_info *mac_control;
1da177e4
LT		 2495 struct config_param *config;
2496
2497 mac_control = &nic->mac_control;
2498 config = &nic->config;
2499
2500 /* Disable all interrupts */
9caab458 2501 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
e960fc5c 2502 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 2503 interruptible |= TX_PIC_INTR;
1da177e4
LT		 2504 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2505
5d3213cc
AR		 2506 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2507 val64 = readq(&bar0->adapter_control);
2508 val64 &= ~(ADAPTER_CNTL_EN);
2509 writeq(val64, &bar0->adapter_control);
1da177e4
LT		 2510}
2511
20346722
K		 2512/**
2513 * fill_rx_buffers - Allocates the Rx side skbs
0425b46a 2514 * @ring_info: per ring structure
3f78d885
SH		 2515 * @from_card_up: If this is true, we will map the buffer to get
2516 * the dma address for buf0 and buf1 to give it to the card.
2517 * Else we will sync the already mapped buffer to give it to the card.
20346722 2518 * Description:
1da177e4
LT		 2519 * The function allocates Rx side skbs and puts the physical
2520 * address of these buffers into the RxD buffer pointers, so that the NIC
2521 * can DMA the received frame into these locations.
2522 * The NIC supports 3 receive modes, viz
2523 * 1. single buffer,
2524 * 2. three buffer and
2525 * 3. Five buffer modes.
20346722
K		 2526 * Each mode defines how many fragments the received frame will be split
2527 * up into by the NIC. The frame is split into L3 header, L4 Header,
1da177e4
LT		 2528 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2529 * is split into 3 fragments. As of now only single buffer mode is
2530 * supported.
2531 * Return Value:
2532 * SUCCESS on success or an appropriate -ve value on failure.
2533 */
8d8bb39b 2534static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
d44570e4 2535 int from_card_up)
1da177e4 2536{
1da177e4 2537 struct sk_buff *skb;
1ee6dd77 2538 struct RxD_t *rxdp;
0425b46a 2539 int off, size, block_no, block_no1;
1da177e4 2540 u32 alloc_tab = 0;
20346722 2541 u32 alloc_cnt;
20346722 2542 u64 tmp;
1ee6dd77 2543 struct buffAdd *ba;
1ee6dd77 2544 struct RxD_t *first_rxdp = NULL;
363dc367 2545 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
0425b46a 2546 int rxd_index = 0;
6d517a27
VP		 2547 struct RxD1 *rxdp1;
2548 struct RxD3 *rxdp3;
0425b46a 2549 struct swStat *stats = &ring->nic->mac_control.stats_info->sw_stat;
1da177e4 2550
0425b46a 2551 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
1da177e4 2552
0425b46a 2553 block_no1 = ring->rx_curr_get_info.block_index;
1da177e4 2554 while (alloc_tab < alloc_cnt) {
0425b46a 2555 block_no = ring->rx_curr_put_info.block_index;
1da177e4 2556
0425b46a
SH		 2557 off = ring->rx_curr_put_info.offset;
2558
2559 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2560
2561 rxd_index = off + 1;
2562 if (block_no)
2563 rxd_index += (block_no * ring->rxd_count);
da6971d8 2564
7d2e3cb7 2565 if ((block_no == block_no1) &&
d44570e4
JP		 2566 (off == ring->rx_curr_get_info.offset) &&
2567 (rxdp->Host_Control)) {
2568 DBG_PRINT(INTR_DBG, "%s: Get and Put", ring->dev->name);
1da177e4
LT		 2569 DBG_PRINT(INTR_DBG, " info equated\n");
2570 goto end;
2571 }
0425b46a
SH		 2572 if (off && (off == ring->rxd_count)) {
2573 ring->rx_curr_put_info.block_index++;
2574 if (ring->rx_curr_put_info.block_index ==
d44570e4 2575 ring->block_count)
0425b46a
SH		 2576 ring->rx_curr_put_info.block_index = 0;
2577 block_no = ring->rx_curr_put_info.block_index;
2578 off = 0;
2579 ring->rx_curr_put_info.offset = off;
2580 rxdp = ring->rx_blocks[block_no].block_virt_addr;
1da177e4 2581 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
0425b46a
SH		 2582 ring->dev->name, rxdp);
2583
1da177e4 2584 }
c9fcbf47 2585
da6971d8 2586 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
d44570e4
JP		 2587 ((ring->rxd_mode == RXD_MODE_3B) &&
2588 (rxdp->Control_2 & s2BIT(0)))) {
0425b46a 2589 ring->rx_curr_put_info.offset = off;
1da177e4
LT		 2590 goto end;
2591 }
da6971d8 2592 /* calculate size of skb based on ring mode */
d44570e4
JP		 2593 size = ring->mtu +
2594 HEADER_ETHERNET_II_802_3_SIZE +
2595 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
0425b46a 2596 if (ring->rxd_mode == RXD_MODE_1)
da6971d8 2597 size += NET_IP_ALIGN;
da6971d8 2598 else
0425b46a 2599 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
1da177e4 2600
da6971d8
AR		 2601 /* allocate skb */
2602 skb = dev_alloc_skb(size);
d44570e4 2603 if (!skb) {
0425b46a 2604 DBG_PRINT(INFO_DBG, "%s: Out of ", ring->dev->name);
0c61ed5f 2605 DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
303bcb4b
K		 2606 if (first_rxdp) {
2607 wmb();
2608 first_rxdp->Control_1 |= RXD_OWN_XENA;
2609 }
0425b46a 2610 stats->mem_alloc_fail_cnt++;
7d2e3cb7 2611
da6971d8
AR		 2612 return -ENOMEM ;
2613 }
0425b46a
SH		 2614 stats->mem_allocated += skb->truesize;
2615
2616 if (ring->rxd_mode == RXD_MODE_1) {
da6971d8 2617 /* 1 buffer mode - normal operation mode */
d44570e4 2618 rxdp1 = (struct RxD1 *)rxdp;
1ee6dd77 2619 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2620 skb_reserve(skb, NET_IP_ALIGN);
d44570e4
JP		 2621 rxdp1->Buffer0_ptr =
2622 pci_map_single(ring->pdev, skb->data,
2623 size - NET_IP_ALIGN,
2624 PCI_DMA_FROMDEVICE);
8d8bb39b 2625 if (pci_dma_mapping_error(nic->pdev,
d44570e4 2626 rxdp1->Buffer0_ptr))
491abf25
VP		 2627 goto pci_map_failed;
2628
8a4bdbaa 2629 rxdp->Control_2 =
491976b2 2630 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
d44570e4 2631 rxdp->Host_Control = (unsigned long)skb;
0425b46a 2632 } else if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8 2633 /*
6d517a27
VP		 2634 * 2 buffer mode -
2635 * 2 buffer mode provides 128
da6971d8 2636 * byte aligned receive buffers.
da6971d8
AR		 2637 */
2638
d44570e4 2639 rxdp3 = (struct RxD3 *)rxdp;
491976b2 2640 /* save buffer pointers to avoid frequent dma mapping */
6d517a27
VP		 2641 Buffer0_ptr = rxdp3->Buffer0_ptr;
2642 Buffer1_ptr = rxdp3->Buffer1_ptr;
1ee6dd77 2643 memset(rxdp, 0, sizeof(struct RxD3));
363dc367 2644 /* restore the buffer pointers for dma sync*/
6d517a27
VP		 2645 rxdp3->Buffer0_ptr = Buffer0_ptr;
2646 rxdp3->Buffer1_ptr = Buffer1_ptr;
363dc367 2647
0425b46a 2648 ba = &ring->ba[block_no][off];
da6971d8 2649 skb_reserve(skb, BUF0_LEN);
d44570e4 2650 tmp = (u64)(unsigned long)skb->data;
da6971d8
AR		 2651 tmp += ALIGN_SIZE;
2652 tmp &= ~ALIGN_SIZE;
2653 skb->data = (void *) (unsigned long)tmp;
27a884dc 2654 skb_reset_tail_pointer(skb);
da6971d8 2655
3f78d885 2656 if (from_card_up) {
6d517a27 2657 rxdp3->Buffer0_ptr =
d44570e4
JP		 2658 pci_map_single(ring->pdev, ba->ba_0,
2659 BUF0_LEN,
2660 PCI_DMA_FROMDEVICE);
2661 if (pci_dma_mapping_error(nic->pdev,
2662 rxdp3->Buffer0_ptr))
3f78d885
SH		 2663 goto pci_map_failed;
2664 } else
0425b46a 2665 pci_dma_sync_single_for_device(ring->pdev,
d44570e4
JP		 2666 (dma_addr_t)rxdp3->Buffer0_ptr,
2667 BUF0_LEN,
2668 PCI_DMA_FROMDEVICE);
491abf25 2669
da6971d8 2670 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
0425b46a 2671 if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 2672 /* Two buffer mode */
2673
2674 /*
6aa20a22 2675 * Buffer2 will have L3/L4 header plus
da6971d8
AR		 2676 * L4 payload
2677 */
d44570e4
JP		 2678 rxdp3->Buffer2_ptr = pci_map_single(ring->pdev,
2679 skb->data,
2680 ring->mtu + 4,
2681 PCI_DMA_FROMDEVICE);
da6971d8 2682
8d8bb39b 2683 if (pci_dma_mapping_error(nic->pdev,
d44570e4 2684 rxdp3->Buffer2_ptr))
491abf25
VP		 2685 goto pci_map_failed;
2686
3f78d885 2687 if (from_card_up) {
0425b46a
SH		 2688 rxdp3->Buffer1_ptr =
2689 pci_map_single(ring->pdev,
d44570e4
JP		 2690 ba->ba_1,
2691 BUF1_LEN,
2692 PCI_DMA_FROMDEVICE);
0425b46a 2693
8d8bb39b 2694 if (pci_dma_mapping_error(nic->pdev,
d44570e4
JP		 2695 rxdp3->Buffer1_ptr)) {
2696 pci_unmap_single(ring->pdev,
2697 (dma_addr_t)(unsigned long)
2698 skb->data,
2699 ring->mtu + 4,
2700 PCI_DMA_FROMDEVICE);
3f78d885
SH		 2701 goto pci_map_failed;
2702 }
75c30b13 2703 }
da6971d8
AR		 2704 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2705 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
d44570e4 2706 (ring->mtu + 4);
da6971d8 2707 }
b7b5a128 2708 rxdp->Control_2 |= s2BIT(0);
0425b46a 2709 rxdp->Host_Control = (unsigned long) (skb);
1da177e4 2710 }
303bcb4b
K		 2711 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2712 rxdp->Control_1 |= RXD_OWN_XENA;
1da177e4 2713 off++;
0425b46a 2714 if (off == (ring->rxd_count + 1))
da6971d8 2715 off = 0;
0425b46a 2716 ring->rx_curr_put_info.offset = off;
20346722 2717
da6971d8 2718 rxdp->Control_2 |= SET_RXD_MARKER;
303bcb4b
K		 2719 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2720 if (first_rxdp) {
2721 wmb();
2722 first_rxdp->Control_1 |= RXD_OWN_XENA;
2723 }
2724 first_rxdp = rxdp;
2725 }
0425b46a 2726 ring->rx_bufs_left += 1;
1da177e4
LT		 2727 alloc_tab++;
2728 }
2729
d44570e4 2730end:
303bcb4b
K		 2731 /* Transfer ownership of first descriptor to adapter just before
2732 * exiting. Before that, use memory barrier so that ownership
2733 * and other fields are seen by adapter correctly.
2734 */
2735 if (first_rxdp) {
2736 wmb();
2737 first_rxdp->Control_1 |= RXD_OWN_XENA;
2738 }
2739
1da177e4 2740 return SUCCESS;
d44570e4 2741
491abf25
VP		 2742pci_map_failed:
2743 stats->pci_map_fail_cnt++;
2744 stats->mem_freed += skb->truesize;
2745 dev_kfree_skb_irq(skb);
2746 return -ENOMEM;
1da177e4
LT		 2747}
2748
da6971d8
AR		 2749static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2750{
2751 struct net_device *dev = sp->dev;
2752 int j;
2753 struct sk_buff *skb;
1ee6dd77
RB		 2754 struct RxD_t *rxdp;
2755 struct mac_info *mac_control;
2756 struct buffAdd *ba;
6d517a27
VP		 2757 struct RxD1 *rxdp1;
2758 struct RxD3 *rxdp3;
da6971d8
AR		 2759
2760 mac_control = &sp->mac_control;
2761 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2762 rxdp = mac_control->rings[ring_no].
d44570e4
JP		 2763 rx_blocks[blk].rxds[j].virt_addr;
2764 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2765 if (!skb)
da6971d8 2766 continue;
da6971d8 2767 if (sp->rxd_mode == RXD_MODE_1) {
d44570e4
JP		 2768 rxdp1 = (struct RxD1 *)rxdp;
2769 pci_unmap_single(sp->pdev,
2770 (dma_addr_t)rxdp1->Buffer0_ptr,
2771 dev->mtu +
2772 HEADER_ETHERNET_II_802_3_SIZE +
2773 HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2774 PCI_DMA_FROMDEVICE);
1ee6dd77 2775 memset(rxdp, 0, sizeof(struct RxD1));
d44570e4
JP		 2776 } else if (sp->rxd_mode == RXD_MODE_3B) {
2777 rxdp3 = (struct RxD3 *)rxdp;
2778 ba = &mac_control->rings[ring_no].ba[blk][j];
2779 pci_unmap_single(sp->pdev,
2780 (dma_addr_t)rxdp3->Buffer0_ptr,
2781 BUF0_LEN,
2782 PCI_DMA_FROMDEVICE);
2783 pci_unmap_single(sp->pdev,
2784 (dma_addr_t)rxdp3->Buffer1_ptr,
2785 BUF1_LEN,
2786 PCI_DMA_FROMDEVICE);
2787 pci_unmap_single(sp->pdev,
2788 (dma_addr_t)rxdp3->Buffer2_ptr,
2789 dev->mtu + 4,
2790 PCI_DMA_FROMDEVICE);
1ee6dd77 2791 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8 2792 }
491976b2 2793 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
da6971d8 2794 dev_kfree_skb(skb);
0425b46a 2795 mac_control->rings[ring_no].rx_bufs_left -= 1;
da6971d8
AR		 2796 }
2797}
2798
1da177e4 2799/**
20346722 2800 * free_rx_buffers - Frees all Rx buffers
1da177e4 2801 * @sp: device private variable.
20346722 2802 * Description:
1da177e4
LT		 2803 * This function will free all Rx buffers allocated by host.
2804 * Return Value:
2805 * NONE.
2806 */
2807
2808static void free_rx_buffers(struct s2io_nic *sp)
2809{
2810 struct net_device *dev = sp->dev;
da6971d8 2811 int i, blk = 0, buf_cnt = 0;
1ee6dd77 2812 struct mac_info *mac_control;
1da177e4 2813 struct config_param *config;
1da177e4
LT		 2814
2815 mac_control = &sp->mac_control;
2816 config = &sp->config;
2817
2818 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2819 struct ring_info *ring = &mac_control->rings[i];
2820
da6971d8 2821 for (blk = 0; blk < rx_ring_sz[i]; blk++)
d44570e4 2822 free_rxd_blk(sp, i, blk);
1da177e4 2823
13d866a9
JP		 2824 ring->rx_curr_put_info.block_index = 0;
2825 ring->rx_curr_get_info.block_index = 0;
2826 ring->rx_curr_put_info.offset = 0;
2827 ring->rx_curr_get_info.offset = 0;
2828 ring->rx_bufs_left = 0;
1da177e4
LT		 2829 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2830 dev->name, buf_cnt, i);
2831 }
2832}
2833
8d8bb39b 2834static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
f61e0a35 2835{
8d8bb39b 2836 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
f61e0a35
SH		 2837 DBG_PRINT(INFO_DBG, "%s:Out of memory", ring->dev->name);
2838 DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
2839 }
2840 return 0;
2841}
2842
1da177e4
LT		 2843/**
2844 * s2io_poll - Rx interrupt handler for NAPI support
bea3348e 2845 * @napi : pointer to the napi structure.
20346722 2846 * @budget : The number of packets that were budgeted to be processed
1da177e4
LT		 2847 * during one pass through the 'Poll" function.
2848 * Description:
2849 * Comes into picture only if NAPI support has been incorporated. It does
2850 * the same thing that rx_intr_handler does, but not in a interrupt context
2851 * also It will process only a given number of packets.
2852 * Return value:
2853 * 0 on success and 1 if there are No Rx packets to be processed.
2854 */
2855
f61e0a35 2856static int s2io_poll_msix(struct napi_struct *napi, int budget)
1da177e4 2857{
f61e0a35
SH		 2858 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2859 struct net_device *dev = ring->dev;
1da177e4 2860 struct config_param *config;
f61e0a35
SH		 2861 struct mac_info *mac_control;
2862 int pkts_processed = 0;
1a79d1c3
AV		 2863 u8 __iomem *addr = NULL;
2864 u8 val8 = 0;
4cf1653a 2865 struct s2io_nic *nic = netdev_priv(dev);
1ee6dd77 2866 struct XENA_dev_config __iomem *bar0 = nic->bar0;
f61e0a35 2867 int budget_org = budget;
1da177e4 2868
1da177e4 2869 config = &nic->config;
f61e0a35 2870 mac_control = &nic->mac_control;
1da177e4 2871
f61e0a35
SH		 2872 if (unlikely(!is_s2io_card_up(nic)))
2873 return 0;
1da177e4 2874
f61e0a35 2875 pkts_processed = rx_intr_handler(ring, budget);
8d8bb39b 2876 s2io_chk_rx_buffers(nic, ring);
1da177e4 2877
f61e0a35 2878 if (pkts_processed < budget_org) {
288379f0 2879 napi_complete(napi);
f61e0a35 2880 /*Re Enable MSI-Rx Vector*/
1a79d1c3 2881 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
f61e0a35
SH		 2882 addr += 7 - ring->ring_no;
2883 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2884 writeb(val8, addr);
2885 val8 = readb(addr);
1da177e4 2886 }
f61e0a35
SH		 2887 return pkts_processed;
2888}
d44570e4 2889
f61e0a35
SH		 2890static int s2io_poll_inta(struct napi_struct *napi, int budget)
2891{
2892 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
f61e0a35
SH		 2893 struct config_param *config;
2894 struct mac_info *mac_control;
2895 int pkts_processed = 0;
2896 int ring_pkts_processed, i;
2897 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2898 int budget_org = budget;
1da177e4 2899
f61e0a35
SH		 2900 config = &nic->config;
2901 mac_control = &nic->mac_control;
1da177e4 2902
f61e0a35
SH		 2903 if (unlikely(!is_s2io_card_up(nic)))
2904 return 0;
1da177e4 2905
1da177e4 2906 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9 2907 struct ring_info *ring = &mac_control->rings[i];
f61e0a35 2908 ring_pkts_processed = rx_intr_handler(ring, budget);
8d8bb39b 2909 s2io_chk_rx_buffers(nic, ring);
f61e0a35
SH		 2910 pkts_processed += ring_pkts_processed;
2911 budget -= ring_pkts_processed;
2912 if (budget <= 0)
1da177e4 2913 break;
1da177e4 2914 }
f61e0a35 2915 if (pkts_processed < budget_org) {
288379f0 2916 napi_complete(napi);
f61e0a35
SH		 2917 /* Re enable the Rx interrupts for the ring */
2918 writeq(0, &bar0->rx_traffic_mask);
2919 readl(&bar0->rx_traffic_mask);
2920 }
2921 return pkts_processed;
1da177e4 2922}
20346722 2923
b41477f3 2924#ifdef CONFIG_NET_POLL_CONTROLLER
612eff0e 2925/**
b41477f3 2926 * s2io_netpoll - netpoll event handler entry point
612eff0e
BH		 2927 * @dev : pointer to the device structure.
2928 * Description:
b41477f3
AR		 2929 * This function will be called by upper layer to check for events on the
2930 * interface in situations where interrupts are disabled. It is used for
2931 * specific in-kernel networking tasks, such as remote consoles and kernel
2932 * debugging over the network (example netdump in RedHat).
612eff0e 2933 */
612eff0e
BH		 2934static void s2io_netpoll(struct net_device *dev)
2935{
4cf1653a 2936 struct s2io_nic *nic = netdev_priv(dev);
1ee6dd77 2937 struct mac_info *mac_control;
612eff0e 2938 struct config_param *config;
1ee6dd77 2939 struct XENA_dev_config __iomem *bar0 = nic->bar0;
b41477f3 2940 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
612eff0e
BH		 2941 int i;
2942
d796fdb7
LV		 2943 if (pci_channel_offline(nic->pdev))
2944 return;
2945
612eff0e
BH		 2946 disable_irq(dev->irq);
2947
612eff0e
BH		 2948 mac_control = &nic->mac_control;
2949 config = &nic->config;
2950
612eff0e 2951 writeq(val64, &bar0->rx_traffic_int);
b41477f3
AR		 2952 writeq(val64, &bar0->tx_traffic_int);
2953
6aa20a22 2954 /* we need to free up the transmitted skbufs or else netpoll will
b41477f3
AR		 2955 * run out of skbs and will fail and eventually netpoll application such
2956 * as netdump will fail.
2957 */
2958 for (i = 0; i < config->tx_fifo_num; i++)
2959 tx_intr_handler(&mac_control->fifos[i]);
612eff0e 2960
b41477f3 2961 /* check for received packet and indicate up to network */
13d866a9
JP		 2962 for (i = 0; i < config->rx_ring_num; i++) {
2963 struct ring_info *ring = &mac_control->rings[i];
2964
2965 rx_intr_handler(ring, 0);
2966 }
612eff0e
BH		 2967
2968 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2969 struct ring_info *ring = &mac_control->rings[i];
2970
2971 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
0c61ed5f
RV		 2972 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2973 DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
612eff0e
BH		 2974 break;
2975 }
2976 }
612eff0e
BH		 2977 enable_irq(dev->irq);
2978 return;
2979}
2980#endif
2981
20346722 2982/**
1da177e4 2983 * rx_intr_handler - Rx interrupt handler
f61e0a35
SH		 2984 * @ring_info: per ring structure.
2985 * @budget: budget for napi processing.
20346722
K		 2986 * Description:
2987 * If the interrupt is because of a received frame or if the
1da177e4 2988 * receive ring contains fresh as yet un-processed frames,this function is
20346722
K		 2989 * called. It picks out the RxD at which place the last Rx processing had
2990 * stopped and sends the skb to the OSM's Rx handler and then increments
1da177e4
LT		 2991 * the offset.
2992 * Return Value:
f61e0a35 2993 * No. of napi packets processed.
1da177e4 2994 */
f61e0a35 2995static int rx_intr_handler(struct ring_info *ring_data, int budget)
1da177e4 2996{
c9fcbf47 2997 int get_block, put_block;
1ee6dd77
RB		 2998 struct rx_curr_get_info get_info, put_info;
2999 struct RxD_t *rxdp;
1da177e4 3000 struct sk_buff *skb;
f61e0a35 3001 int pkt_cnt = 0, napi_pkts = 0;
7d3d0439 3002 int i;
d44570e4
JP		 3003 struct RxD1 *rxdp1;
3004 struct RxD3 *rxdp3;
7d3d0439 3005
20346722
K		 3006 get_info = ring_data->rx_curr_get_info;
3007 get_block = get_info.block_index;
1ee6dd77 3008 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
20346722 3009 put_block = put_info.block_index;
da6971d8 3010 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
db874e65 3011
da6971d8 3012 while (RXD_IS_UP2DT(rxdp)) {
db874e65
SS		 3013 /*
3014 * If your are next to put index then it's
3015 * FIFO full condition
3016 */
da6971d8
AR		 3017 if ((get_block == put_block) &&
3018 (get_info.offset + 1) == put_info.offset) {
0425b46a 3019 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
d44570e4 3020 ring_data->dev->name);
da6971d8
AR		 3021 break;
3022 }
d44570e4 3023 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
20346722
K		 3024 if (skb == NULL) {
3025 DBG_PRINT(ERR_DBG, "%s: The skb is ",
0425b46a 3026 ring_data->dev->name);
20346722 3027 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
f61e0a35 3028 return 0;
1da177e4 3029 }
0425b46a 3030 if (ring_data->rxd_mode == RXD_MODE_1) {
d44570e4 3031 rxdp1 = (struct RxD1 *)rxdp;
0425b46a 3032 pci_unmap_single(ring_data->pdev, (dma_addr_t)
d44570e4
JP		 3033 rxdp1->Buffer0_ptr,
3034 ring_data->mtu +
3035 HEADER_ETHERNET_II_802_3_SIZE +
3036 HEADER_802_2_SIZE +
3037 HEADER_SNAP_SIZE,
3038 PCI_DMA_FROMDEVICE);
0425b46a 3039 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
d44570e4
JP		 3040 rxdp3 = (struct RxD3 *)rxdp;
3041 pci_dma_sync_single_for_cpu(ring_data->pdev,
3042 (dma_addr_t)rxdp3->Buffer0_ptr,
3043 BUF0_LEN,
3044 PCI_DMA_FROMDEVICE);
3045 pci_unmap_single(ring_data->pdev,
3046 (dma_addr_t)rxdp3->Buffer2_ptr,
3047 ring_data->mtu + 4,
3048 PCI_DMA_FROMDEVICE);
da6971d8 3049 }
863c11a9 3050 prefetch(skb->data);
20346722
K		 3051 rx_osm_handler(ring_data, rxdp);
3052 get_info.offset++;
da6971d8
AR		 3053 ring_data->rx_curr_get_info.offset = get_info.offset;
3054 rxdp = ring_data->rx_blocks[get_block].
d44570e4 3055 rxds[get_info.offset].virt_addr;
0425b46a 3056 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
20346722 3057 get_info.offset = 0;
da6971d8 3058 ring_data->rx_curr_get_info.offset = get_info.offset;
20346722 3059 get_block++;
da6971d8
AR		 3060 if (get_block == ring_data->block_count)
3061 get_block = 0;
3062 ring_data->rx_curr_get_info.block_index = get_block;
20346722
K		 3063 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3064 }
1da177e4 3065
f61e0a35
SH		 3066 if (ring_data->nic->config.napi) {
3067 budget--;
3068 napi_pkts++;
3069 if (!budget)
0425b46a
SH		 3070 break;
3071 }
20346722 3072 pkt_cnt++;
1da177e4
LT		 3073 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3074 break;
3075 }
0425b46a 3076 if (ring_data->lro) {
7d3d0439 3077 /* Clear all LRO sessions before exiting */
d44570e4 3078 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 3079 struct lro *lro = &ring_data->lro0_n[i];
7d3d0439 3080 if (lro->in_use) {
0425b46a 3081 update_L3L4_header(ring_data->nic, lro);
cdb5bf02 3082 queue_rx_frame(lro->parent, lro->vlan_tag);
7d3d0439
RA		 3083 clear_lro_session(lro);
3084 }
3085 }
3086 }
d44570e4 3087 return napi_pkts;
1da177e4 3088}
20346722
K		 3089
3090/**
1da177e4
LT		 3091 * tx_intr_handler - Transmit interrupt handler
3092 * @nic : device private variable
20346722
K		 3093 * Description:
3094 * If an interrupt was raised to indicate DMA complete of the
3095 * Tx packet, this function is called. It identifies the last TxD
3096 * whose buffer was freed and frees all skbs whose data have already
1da177e4
LT		 3097 * DMA'ed into the NICs internal memory.
3098 * Return Value:
3099 * NONE
3100 */
3101
1ee6dd77 3102static void tx_intr_handler(struct fifo_info *fifo_data)
1da177e4 3103{
1ee6dd77 3104 struct s2io_nic *nic = fifo_data->nic;
1ee6dd77 3105 struct tx_curr_get_info get_info, put_info;
3a3d5756 3106 struct sk_buff *skb = NULL;
1ee6dd77 3107 struct TxD *txdlp;
3a3d5756 3108 int pkt_cnt = 0;
2fda096d 3109 unsigned long flags = 0;
f9046eb3 3110 u8 err_mask;
1da177e4 3111
2fda096d 3112 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
d44570e4 3113 return;
2fda096d 3114
20346722 3115 get_info = fifo_data->tx_curr_get_info;
1ee6dd77 3116 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
d44570e4
JP		 3117 txdlp = (struct TxD *)
3118 fifo_data->list_info[get_info.offset].list_virt_addr;
20346722
K		 3119 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3120 (get_info.offset != put_info.offset) &&
3121 (txdlp->Host_Control)) {
3122 /* Check for TxD errors */
3123 if (txdlp->Control_1 & TXD_T_CODE) {
3124 unsigned long long err;
3125 err = txdlp->Control_1 & TXD_T_CODE;
bd1034f0
AR		 3126 if (err & 0x1) {
3127 nic->mac_control.stats_info->sw_stat.
d44570e4 3128 parity_err_cnt++;
bd1034f0 3129 }
491976b2
SH		 3130
3131 /* update t_code statistics */
f9046eb3 3132 err_mask = err >> 48;
d44570e4
JP		 3133 switch (err_mask) {
3134 case 2:
3135 nic->mac_control.stats_info->sw_stat.
3136 tx_buf_abort_cnt++;
491976b2
SH		 3137 break;
3138
d44570e4
JP		 3139 case 3:
3140 nic->mac_control.stats_info->sw_stat.
3141 tx_desc_abort_cnt++;
491976b2
SH		 3142 break;
3143
d44570e4
JP		 3144 case 7:
3145 nic->mac_control.stats_info->sw_stat.
3146 tx_parity_err_cnt++;
491976b2
SH		 3147 break;
3148
d44570e4
JP		 3149 case 10:
3150 nic->mac_control.stats_info->sw_stat.
3151 tx_link_loss_cnt++;
491976b2
SH		 3152 break;
3153
d44570e4
JP		 3154 case 15:
3155 nic->mac_control.stats_info->sw_stat.
3156 tx_list_proc_err_cnt++;
491976b2 3157 break;
d44570e4 3158 }
20346722 3159 }
1da177e4 3160
fed5eccd 3161 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
20346722 3162 if (skb == NULL) {
2fda096d 3163 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
d44570e4 3164 DBG_PRINT(ERR_DBG, "%s: Null skb ", __func__);
20346722
K		 3165 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
3166 return;
3167 }
3a3d5756 3168 pkt_cnt++;
20346722 3169
20346722 3170 /* Updating the statistics block */
dc56e634 3171 nic->dev->stats.tx_bytes += skb->len;
491976b2 3172 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
20346722
K		 3173 dev_kfree_skb_irq(skb);
3174
3175 get_info.offset++;
863c11a9
AR		 3176 if (get_info.offset == get_info.fifo_len + 1)
3177 get_info.offset = 0;
d44570e4
JP		 3178 txdlp = (struct TxD *)
3179 fifo_data->list_info[get_info.offset].list_virt_addr;
3180 fifo_data->tx_curr_get_info.offset = get_info.offset;
1da177e4
LT		 3181 }
3182
3a3d5756 3183 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
2fda096d
SR		 3184
3185 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
1da177e4
LT		 3186}
3187
bd1034f0
AR		 3188/**
3189 * s2io_mdio_write - Function to write in to MDIO registers
3190 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3191 * @addr : address value
3192 * @value : data value
3193 * @dev : pointer to net_device structure
3194 * Description:
3195 * This function is used to write values to the MDIO registers
3196 * NONE
3197 */
d44570e4
JP		 3198static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3199 struct net_device *dev)
bd1034f0 3200{
d44570e4 3201 u64 val64;
4cf1653a 3202 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3203 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0 3204
d44570e4
JP		 3205 /* address transaction */
3206 val64 = MDIO_MMD_INDX_ADDR(addr) |
3207 MDIO_MMD_DEV_ADDR(mmd_type) |
3208 MDIO_MMS_PRT_ADDR(0x0);
bd1034f0
AR		 3209 writeq(val64, &bar0->mdio_control);
3210 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3211 writeq(val64, &bar0->mdio_control);
3212 udelay(100);
3213
d44570e4
JP		 3214 /* Data transaction */
3215 val64 = MDIO_MMD_INDX_ADDR(addr) |
3216 MDIO_MMD_DEV_ADDR(mmd_type) |
3217 MDIO_MMS_PRT_ADDR(0x0) |
3218 MDIO_MDIO_DATA(value) |
3219 MDIO_OP(MDIO_OP_WRITE_TRANS);
bd1034f0
AR		 3220 writeq(val64, &bar0->mdio_control);
3221 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3222 writeq(val64, &bar0->mdio_control);
3223 udelay(100);
3224
d44570e4
JP		 3225 val64 = MDIO_MMD_INDX_ADDR(addr) |
3226 MDIO_MMD_DEV_ADDR(mmd_type) |
3227 MDIO_MMS_PRT_ADDR(0x0) |
3228 MDIO_OP(MDIO_OP_READ_TRANS);
bd1034f0
AR		 3229 writeq(val64, &bar0->mdio_control);
3230 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3231 writeq(val64, &bar0->mdio_control);
3232 udelay(100);
bd1034f0
AR		 3233}
3234
3235/**
3236 * s2io_mdio_read - Function to write in to MDIO registers
3237 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3238 * @addr : address value
3239 * @dev : pointer to net_device structure
3240 * Description:
3241 * This function is used to read values to the MDIO registers
3242 * NONE
3243 */
3244static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3245{
3246 u64 val64 = 0x0;
3247 u64 rval64 = 0x0;
4cf1653a 3248 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3249 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3250
3251 /* address transaction */
d44570e4
JP		 3252 val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3253 | MDIO_MMD_DEV_ADDR(mmd_type)
3254 | MDIO_MMS_PRT_ADDR(0x0));
bd1034f0
AR		 3255 writeq(val64, &bar0->mdio_control);
3256 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3257 writeq(val64, &bar0->mdio_control);
3258 udelay(100);
3259
3260 /* Data transaction */
d44570e4
JP		 3261 val64 = MDIO_MMD_INDX_ADDR(addr) |
3262 MDIO_MMD_DEV_ADDR(mmd_type) |
3263 MDIO_MMS_PRT_ADDR(0x0) |
3264 MDIO_OP(MDIO_OP_READ_TRANS);
bd1034f0
AR		 3265 writeq(val64, &bar0->mdio_control);
3266 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3267 writeq(val64, &bar0->mdio_control);
3268 udelay(100);
3269
3270 /* Read the value from regs */
3271 rval64 = readq(&bar0->mdio_control);
3272 rval64 = rval64 & 0xFFFF0000;
3273 rval64 = rval64 >> 16;
3274 return rval64;
3275}
d44570e4 3276
bd1034f0
AR		 3277/**
3278 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3279 * @counter : couter value to be updated
3280 * @flag : flag to indicate the status
3281 * @type : counter type
3282 * Description:
3283 * This function is to check the status of the xpak counters value
3284 * NONE
3285 */
3286
d44570e4
JP		 3287static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3288 u16 flag, u16 type)
bd1034f0
AR		 3289{
3290 u64 mask = 0x3;
3291 u64 val64;
3292 int i;
d44570e4 3293 for (i = 0; i < index; i++)
bd1034f0
AR		 3294 mask = mask << 0x2;
3295
d44570e4 3296 if (flag > 0) {
bd1034f0
AR		 3297 *counter = *counter + 1;
3298 val64 = *regs_stat & mask;
3299 val64 = val64 >> (index * 0x2);
3300 val64 = val64 + 1;
d44570e4
JP		 3301 if (val64 == 3) {
3302 switch (type) {
bd1034f0
AR		 3303 case 1:
3304 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3305 "service. Excessive temperatures may "
3306 "result in premature transceiver "
3307 "failure \n");
d44570e4 3308 break;
bd1034f0
AR		 3309 case 2:
3310 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3311 "service Excessive bias currents may "
3312 "indicate imminent laser diode "
3313 "failure \n");
d44570e4 3314 break;
bd1034f0
AR		 3315 case 3:
3316 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3317 "service Excessive laser output "
3318 "power may saturate far-end "
3319 "receiver\n");
d44570e4 3320 break;
bd1034f0 3321 default:
d44570e4
JP		 3322 DBG_PRINT(ERR_DBG,
3323 "Incorrect XPAK Alarm type\n");
bd1034f0
AR		 3324 }
3325 val64 = 0x0;
3326 }
3327 val64 = val64 << (index * 0x2);
3328 *regs_stat = (*regs_stat & (~mask)) | (val64);
3329
3330 } else {
3331 *regs_stat = *regs_stat & (~mask);
3332 }
3333}
3334
3335/**
3336 * s2io_updt_xpak_counter - Function to update the xpak counters
3337 * @dev : pointer to net_device struct
3338 * Description:
3339 * This function is to upate the status of the xpak counters value
3340 * NONE
3341 */
3342static void s2io_updt_xpak_counter(struct net_device *dev)
3343{
3344 u16 flag = 0x0;
3345 u16 type = 0x0;
3346 u16 val16 = 0x0;
3347 u64 val64 = 0x0;
3348 u64 addr = 0x0;
3349
4cf1653a 3350 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3351 struct stat_block *stat_info = sp->mac_control.stats_info;
bd1034f0
AR		 3352
3353 /* Check the communication with the MDIO slave */
40239396 3354 addr = MDIO_CTRL1;
bd1034f0 3355 val64 = 0x0;
40239396 3356 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
d44570e4 3357 if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
bd1034f0
AR		 3358 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3359 "Returned %llx\n", (unsigned long long)val64);
3360 return;
3361 }
3362
40239396 3363 /* Check for the expected value of control reg 1 */
d44570e4 3364 if (val64 != MDIO_CTRL1_SPEED10G) {
bd1034f0 3365 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
40239396
BH		 3366 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x%x\n",
3367 (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
bd1034f0
AR		 3368 return;
3369 }
3370
3371 /* Loading the DOM register to MDIO register */
3372 addr = 0xA100;
40239396
BH		 3373 s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3374 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3375
3376 /* Reading the Alarm flags */
3377 addr = 0xA070;
3378 val64 = 0x0;
40239396 3379 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3380
3381 flag = CHECKBIT(val64, 0x7);
3382 type = 1;
3383 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
d44570e4
JP		 3384 &stat_info->xpak_stat.xpak_regs_stat,
3385 0x0, flag, type);
bd1034f0 3386
d44570e4 3387 if (CHECKBIT(val64, 0x6))
bd1034f0
AR		 3388 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3389
3390 flag = CHECKBIT(val64, 0x3);
3391 type = 2;
3392 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
d44570e4
JP		 3393 &stat_info->xpak_stat.xpak_regs_stat,
3394 0x2, flag, type);
bd1034f0 3395
d44570e4 3396 if (CHECKBIT(val64, 0x2))
bd1034f0
AR		 3397 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3398
3399 flag = CHECKBIT(val64, 0x1);
3400 type = 3;
3401 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
d44570e4
JP		 3402 &stat_info->xpak_stat.xpak_regs_stat,
3403 0x4, flag, type);
bd1034f0 3404
d44570e4 3405 if (CHECKBIT(val64, 0x0))
bd1034f0
AR		 3406 stat_info->xpak_stat.alarm_laser_output_power_low++;
3407
3408 /* Reading the Warning flags */
3409 addr = 0xA074;
3410 val64 = 0x0;
40239396 3411 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0 3412
d44570e4 3413 if (CHECKBIT(val64, 0x7))
bd1034f0
AR		 3414 stat_info->xpak_stat.warn_transceiver_temp_high++;
3415
d44570e4 3416 if (CHECKBIT(val64, 0x6))
bd1034f0
AR		 3417 stat_info->xpak_stat.warn_transceiver_temp_low++;
3418
d44570e4 3419 if (CHECKBIT(val64, 0x3))
bd1034f0
AR		 3420 stat_info->xpak_stat.warn_laser_bias_current_high++;
3421
d44570e4 3422 if (CHECKBIT(val64, 0x2))
bd1034f0
AR		 3423 stat_info->xpak_stat.warn_laser_bias_current_low++;
3424
d44570e4 3425 if (CHECKBIT(val64, 0x1))
bd1034f0
AR		 3426 stat_info->xpak_stat.warn_laser_output_power_high++;
3427
d44570e4 3428 if (CHECKBIT(val64, 0x0))
bd1034f0
AR		 3429 stat_info->xpak_stat.warn_laser_output_power_low++;
3430}
3431
20346722 3432/**
1da177e4 3433 * wait_for_cmd_complete - waits for a command to complete.
20346722 3434 * @sp : private member of the device structure, which is a pointer to the
1da177e4 3435 * s2io_nic structure.
20346722
K		 3436 * Description: Function that waits for a command to Write into RMAC
3437 * ADDR DATA registers to be completed and returns either success or
3438 * error depending on whether the command was complete or not.
1da177e4
LT		 3439 * Return value:
3440 * SUCCESS on success and FAILURE on failure.
3441 */
3442
9fc93a41 3443static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
d44570e4 3444 int bit_state)
1da177e4 3445{
9fc93a41 3446 int ret = FAILURE, cnt = 0, delay = 1;
1da177e4
LT		 3447 u64 val64;
3448
9fc93a41
SS		 3449 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3450 return FAILURE;
3451
3452 do {
c92ca04b 3453 val64 = readq(addr);
9fc93a41
SS		 3454 if (bit_state == S2IO_BIT_RESET) {
3455 if (!(val64 & busy_bit)) {
3456 ret = SUCCESS;
3457 break;
3458 }
3459 } else {
3460 if (!(val64 & busy_bit)) {
3461 ret = SUCCESS;
3462 break;
3463 }
1da177e4 3464 }
c92ca04b 3465
d44570e4 3466 if (in_interrupt())
9fc93a41 3467 mdelay(delay);
c92ca04b 3468 else
9fc93a41 3469 msleep(delay);
c92ca04b 3470
9fc93a41
SS		 3471 if (++cnt >= 10)
3472 delay = 50;
3473 } while (cnt < 20);
1da177e4
LT		 3474 return ret;
3475}
19a60522
SS		 3476/*
3477 * check_pci_device_id - Checks if the device id is supported
3478 * @id : device id
3479 * Description: Function to check if the pci device id is supported by driver.
3480 * Return value: Actual device id if supported else PCI_ANY_ID
3481 */
3482static u16 check_pci_device_id(u16 id)
3483{
3484 switch (id) {
3485 case PCI_DEVICE_ID_HERC_WIN:
3486 case PCI_DEVICE_ID_HERC_UNI:
3487 return XFRAME_II_DEVICE;
3488 case PCI_DEVICE_ID_S2IO_UNI:
3489 case PCI_DEVICE_ID_S2IO_WIN:
3490 return XFRAME_I_DEVICE;
3491 default:
3492 return PCI_ANY_ID;
3493 }
3494}
1da177e4 3495
20346722
K		 3496/**
3497 * s2io_reset - Resets the card.
1da177e4
LT		 3498 * @sp : private member of the device structure.
3499 * Description: Function to Reset the card. This function then also
20346722 3500 * restores the previously saved PCI configuration space registers as
1da177e4
LT		 3501 * the card reset also resets the configuration space.
3502 * Return value:
3503 * void.
3504 */
3505
d44570e4 3506static void s2io_reset(struct s2io_nic *sp)
1da177e4 3507{
1ee6dd77 3508 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 3509 u64 val64;
5e25b9dd 3510 u16 subid, pci_cmd;
19a60522
SS		 3511 int i;
3512 u16 val16;
491976b2
SH		 3513 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3514 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3515
d44570e4
JP		 3516 DBG_PRINT(INIT_DBG, "%s - Resetting XFrame card %s\n",
3517 __func__, sp->dev->name);
1da177e4 3518
0b1f7ebe 3519 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
e960fc5c 3520 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
0b1f7ebe 3521
1da177e4
LT		 3522 val64 = SW_RESET_ALL;
3523 writeq(val64, &bar0->sw_reset);
d44570e4 3524 if (strstr(sp->product_name, "CX4"))
c92ca04b 3525 msleep(750);
19a60522
SS		 3526 msleep(250);
3527 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
1da177e4 3528
19a60522
SS		 3529 /* Restore the PCI state saved during initialization. */
3530 pci_restore_state(sp->pdev);
3531 pci_read_config_word(sp->pdev, 0x2, &val16);
3532 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3533 break;
3534 msleep(200);
3535 }
1da177e4 3536
d44570e4
JP		 3537 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3538 DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
19a60522
SS		 3539
3540 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3541
3542 s2io_init_pci(sp);
1da177e4 3543
20346722
K		 3544 /* Set swapper to enable I/O register access */
3545 s2io_set_swapper(sp);
3546
faa4f796
SH		 3547 /* restore mac_addr entries */
3548 do_s2io_restore_unicast_mc(sp);
3549
cc6e7c44
RA		 3550 /* Restore the MSIX table entries from local variables */
3551 restore_xmsi_data(sp);
3552
5e25b9dd 3553 /* Clear certain PCI/PCI-X fields after reset */
303bcb4b 3554 if (sp->device_type == XFRAME_II_DEVICE) {
b41477f3 3555 /* Clear "detected parity error" bit */
303bcb4b 3556 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
5e25b9dd 3557
303bcb4b
K		 3558 /* Clearing PCIX Ecc status register */
3559 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
5e25b9dd 3560
303bcb4b 3561 /* Clearing PCI_STATUS error reflected here */
b7b5a128 3562 writeq(s2BIT(62), &bar0->txpic_int_reg);
303bcb4b 3563 }
5e25b9dd 3564
20346722 3565 /* Reset device statistics maintained by OS */
d44570e4 3566 memset(&sp->stats, 0, sizeof(struct net_device_stats));
8a4bdbaa 3567
491976b2
SH		 3568 up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3569 down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3570 up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3571 down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
363dc367 3572 reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
491976b2
SH		 3573 mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3574 mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3575 watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3576 /* save link up/down time/cnt, reset/memory/watchdog cnt */
363dc367 3577 memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
491976b2
SH		 3578 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3579 sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3580 sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3581 sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3582 sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
363dc367 3583 sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
491976b2
SH		 3584 sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3585 sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3586 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
20346722 3587
1da177e4
LT		 3588 /* SXE-002: Configure link and activity LED to turn it off */
3589 subid = sp->pdev->subsystem_device;
541ae68f
K		 3590 if (((subid & 0xFF) >= 0x07) &&
3591 (sp->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 3592 val64 = readq(&bar0->gpio_control);
3593 val64 |= 0x0000800000000000ULL;
3594 writeq(val64, &bar0->gpio_control);
3595 val64 = 0x0411040400000000ULL;
509a2671 3596 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 3597 }
3598
541ae68f
K		 3599 /*
3600 * Clear spurious ECC interrupts that would have occured on
3601 * XFRAME II cards after reset.
3602 */
3603 if (sp->device_type == XFRAME_II_DEVICE) {
3604 val64 = readq(&bar0->pcc_err_reg);
3605 writeq(val64, &bar0->pcc_err_reg);
3606 }
3607
f957bcf0 3608 sp->device_enabled_once = false;
1da177e4
LT		 3609}
3610
3611/**
20346722
K		 3612 * s2io_set_swapper - to set the swapper controle on the card
3613 * @sp : private member of the device structure,
1da177e4 3614 * pointer to the s2io_nic structure.
20346722 3615 * Description: Function to set the swapper control on the card
1da177e4
LT		 3616 * correctly depending on the 'endianness' of the system.
3617 * Return value:
3618 * SUCCESS on success and FAILURE on failure.
3619 */
3620
d44570e4 3621static int s2io_set_swapper(struct s2io_nic *sp)
1da177e4
LT		 3622{
3623 struct net_device *dev = sp->dev;
1ee6dd77 3624 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 3625 u64 val64, valt, valr;
3626
20346722 3627 /*
1da177e4
LT		 3628 * Set proper endian settings and verify the same by reading
3629 * the PIF Feed-back register.
3630 */
3631
3632 val64 = readq(&bar0->pif_rd_swapper_fb);
3633 if (val64 != 0x0123456789ABCDEFULL) {
3634 int i = 0;
3635 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3636 0x8100008181000081ULL, /* FE=1, SE=0 */
3637 0x4200004242000042ULL, /* FE=0, SE=1 */
3638 0}; /* FE=0, SE=0 */
3639
d44570e4 3640 while (i < 4) {
1da177e4
LT		 3641 writeq(value[i], &bar0->swapper_ctrl);
3642 val64 = readq(&bar0->pif_rd_swapper_fb);
3643 if (val64 == 0x0123456789ABCDEFULL)
3644 break;
3645 i++;
3646 }
3647 if (i == 4) {
3648 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
d44570e4 3649 dev->name);
1da177e4 3650 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
d44570e4 3651 (unsigned long long)val64);
1da177e4
LT		 3652 return FAILURE;
3653 }
3654 valr = value[i];
3655 } else {
3656 valr = readq(&bar0->swapper_ctrl);
3657 }
3658
3659 valt = 0x0123456789ABCDEFULL;
3660 writeq(valt, &bar0->xmsi_address);
3661 val64 = readq(&bar0->xmsi_address);
3662
d44570e4 3663 if (val64 != valt) {
1da177e4
LT		 3664 int i = 0;
3665 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3666 0x0081810000818100ULL, /* FE=1, SE=0 */
3667 0x0042420000424200ULL, /* FE=0, SE=1 */
3668 0}; /* FE=0, SE=0 */
3669
d44570e4 3670 while (i < 4) {
1da177e4
LT		 3671 writeq((value[i] | valr), &bar0->swapper_ctrl);
3672 writeq(valt, &bar0->xmsi_address);
3673 val64 = readq(&bar0->xmsi_address);
d44570e4 3674 if (val64 == valt)
1da177e4
LT		 3675 break;
3676 i++;
3677 }
d44570e4 3678 if (i == 4) {
20346722 3679 unsigned long long x = val64;
1da177e4 3680 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
20346722 3681 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
1da177e4
LT		 3682 return FAILURE;
3683 }
3684 }
3685 val64 = readq(&bar0->swapper_ctrl);
3686 val64 &= 0xFFFF000000000000ULL;
3687
d44570e4 3688#ifdef __BIG_ENDIAN
20346722
K		 3689 /*
3690 * The device by default set to a big endian format, so a
1da177e4
LT		 3691 * big endian driver need not set anything.
3692 */
3693 val64 |= (SWAPPER_CTRL_TXP_FE |
d44570e4
JP		 3694 SWAPPER_CTRL_TXP_SE |
3695 SWAPPER_CTRL_TXD_R_FE |
3696 SWAPPER_CTRL_TXD_W_FE |
3697 SWAPPER_CTRL_TXF_R_FE |
3698 SWAPPER_CTRL_RXD_R_FE |
3699 SWAPPER_CTRL_RXD_W_FE |
3700 SWAPPER_CTRL_RXF_W_FE |
3701 SWAPPER_CTRL_XMSI_FE |
3702 SWAPPER_CTRL_STATS_FE |
3703 SWAPPER_CTRL_STATS_SE);
eaae7f72 3704 if (sp->config.intr_type == INTA)
cc6e7c44 3705 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3706 writeq(val64, &bar0->swapper_ctrl);
3707#else
20346722 3708 /*
1da177e4 3709 * Initially we enable all bits to make it accessible by the
20346722 3710 * driver, then we selectively enable only those bits that
1da177e4
LT		 3711 * we want to set.
3712 */
3713 val64 |= (SWAPPER_CTRL_TXP_FE |
d44570e4
JP		 3714 SWAPPER_CTRL_TXP_SE |
3715 SWAPPER_CTRL_TXD_R_FE |
3716 SWAPPER_CTRL_TXD_R_SE |
3717 SWAPPER_CTRL_TXD_W_FE |
3718 SWAPPER_CTRL_TXD_W_SE |
3719 SWAPPER_CTRL_TXF_R_FE |
3720 SWAPPER_CTRL_RXD_R_FE |
3721 SWAPPER_CTRL_RXD_R_SE |
3722 SWAPPER_CTRL_RXD_W_FE |
3723 SWAPPER_CTRL_RXD_W_SE |
3724 SWAPPER_CTRL_RXF_W_FE |
3725 SWAPPER_CTRL_XMSI_FE |
3726 SWAPPER_CTRL_STATS_FE |
3727 SWAPPER_CTRL_STATS_SE);
eaae7f72 3728 if (sp->config.intr_type == INTA)
cc6e7c44 3729 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3730 writeq(val64, &bar0->swapper_ctrl);
3731#endif
3732 val64 = readq(&bar0->swapper_ctrl);
3733
20346722
K		 3734 /*
3735 * Verifying if endian settings are accurate by reading a
1da177e4
LT		 3736 * feedback register.
3737 */
3738 val64 = readq(&bar0->pif_rd_swapper_fb);
3739 if (val64 != 0x0123456789ABCDEFULL) {
3740 /* Endian settings are incorrect, calls for another dekko. */
3741 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3742 dev->name);
3743 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
d44570e4 3744 (unsigned long long)val64);
1da177e4
LT		 3745 return FAILURE;
3746 }
3747
3748 return SUCCESS;
3749}
3750
1ee6dd77 3751static int wait_for_msix_trans(struct s2io_nic *nic, int i)
cc6e7c44 3752{
1ee6dd77 3753 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3754 u64 val64;
3755 int ret = 0, cnt = 0;
3756
3757 do {
3758 val64 = readq(&bar0->xmsi_access);
b7b5a128 3759 if (!(val64 & s2BIT(15)))
cc6e7c44
RA		 3760 break;
3761 mdelay(1);
3762 cnt++;
d44570e4 3763 } while (cnt < 5);
cc6e7c44
RA		 3764 if (cnt == 5) {
3765 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3766 ret = 1;
3767 }
3768
3769 return ret;
3770}
3771
1ee6dd77 3772static void restore_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3773{
1ee6dd77 3774 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44 3775 u64 val64;
f61e0a35
SH		 3776 int i, msix_index;
3777
f61e0a35
SH		 3778 if (nic->device_type == XFRAME_I_DEVICE)
3779 return;
cc6e7c44 3780
d44570e4
JP		 3781 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3782 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
cc6e7c44
RA		 3783 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3784 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
f61e0a35 3785 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
cc6e7c44 3786 writeq(val64, &bar0->xmsi_access);
f61e0a35 3787 if (wait_for_msix_trans(nic, msix_index)) {
b39d66a8 3788 DBG_PRINT(ERR_DBG, "failed in %s\n", __func__);
cc6e7c44
RA		 3789 continue;
3790 }
3791 }
3792}
3793
1ee6dd77 3794static void store_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3795{
1ee6dd77 3796 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44 3797 u64 val64, addr, data;
f61e0a35
SH		 3798 int i, msix_index;
3799
3800 if (nic->device_type == XFRAME_I_DEVICE)
3801 return;
cc6e7c44
RA		 3802
3803 /* Store and display */
d44570e4
JP		 3804 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3805 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
f61e0a35 3806 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
cc6e7c44 3807 writeq(val64, &bar0->xmsi_access);
f61e0a35 3808 if (wait_for_msix_trans(nic, msix_index)) {
b39d66a8 3809 DBG_PRINT(ERR_DBG, "failed in %s\n", __func__);
cc6e7c44
RA		 3810 continue;
3811 }
3812 addr = readq(&bar0->xmsi_address);
3813 data = readq(&bar0->xmsi_data);
3814 if (addr && data) {
3815 nic->msix_info[i].addr = addr;
3816 nic->msix_info[i].data = data;
3817 }
3818 }
3819}
3820
1ee6dd77 3821static int s2io_enable_msi_x(struct s2io_nic *nic)
cc6e7c44 3822{
1ee6dd77 3823 struct XENA_dev_config __iomem *bar0 = nic->bar0;
ac731ab6 3824 u64 rx_mat;
cc6e7c44
RA		 3825 u16 msi_control; /* Temp variable */
3826 int ret, i, j, msix_indx = 1;
4f870320 3827 int size;
cc6e7c44 3828
4f870320 3829 size = nic->num_entries * sizeof(struct msix_entry);
44364a03 3830 nic->entries = kzalloc(size, GFP_KERNEL);
bd684e43 3831 if (!nic->entries) {
d44570e4
JP		 3832 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3833 __func__);
c53d4945 3834 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
cc6e7c44
RA		 3835 return -ENOMEM;
3836 }
4f870320 3837 nic->mac_control.stats_info->sw_stat.mem_allocated += size;
f61e0a35 3838
4f870320 3839 size = nic->num_entries * sizeof(struct s2io_msix_entry);
44364a03 3840 nic->s2io_entries = kzalloc(size, GFP_KERNEL);
bd684e43 3841 if (!nic->s2io_entries) {
8a4bdbaa 3842 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
d44570e4 3843 __func__);
c53d4945 3844 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
cc6e7c44 3845 kfree(nic->entries);
8a4bdbaa 3846 nic->mac_control.stats_info->sw_stat.mem_freed
f61e0a35 3847 += (nic->num_entries * sizeof(struct msix_entry));
cc6e7c44
RA		 3848 return -ENOMEM;
3849 }
4f870320 3850 nic->mac_control.stats_info->sw_stat.mem_allocated += size;
cc6e7c44 3851
ac731ab6
SH		 3852 nic->entries[0].entry = 0;
3853 nic->s2io_entries[0].entry = 0;
3854 nic->s2io_entries[0].in_use = MSIX_FLG;
3855 nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3856 nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3857
f61e0a35
SH		 3858 for (i = 1; i < nic->num_entries; i++) {
3859 nic->entries[i].entry = ((i - 1) * 8) + 1;
3860 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
cc6e7c44
RA		 3861 nic->s2io_entries[i].arg = NULL;
3862 nic->s2io_entries[i].in_use = 0;
3863 }
3864
8a4bdbaa 3865 rx_mat = readq(&bar0->rx_mat);
f61e0a35 3866 for (j = 0; j < nic->config.rx_ring_num; j++) {
8a4bdbaa 3867 rx_mat |= RX_MAT_SET(j, msix_indx);
f61e0a35
SH		 3868 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3869 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3870 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3871 msix_indx += 8;
cc6e7c44 3872 }
8a4bdbaa 3873 writeq(rx_mat, &bar0->rx_mat);
f61e0a35 3874 readq(&bar0->rx_mat);
cc6e7c44 3875
f61e0a35 3876 ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
c92ca04b 3877 /* We fail init if error or we get less vectors than min required */
cc6e7c44 3878 if (ret) {
073a2436 3879 DBG_PRINT(ERR_DBG, "s2io: Enabling MSI-X failed\n");
cc6e7c44 3880 kfree(nic->entries);
8a4bdbaa 3881 nic->mac_control.stats_info->sw_stat.mem_freed
f61e0a35 3882 += (nic->num_entries * sizeof(struct msix_entry));
cc6e7c44 3883 kfree(nic->s2io_entries);
8a4bdbaa 3884 nic->mac_control.stats_info->sw_stat.mem_freed
f61e0a35 3885 += (nic->num_entries * sizeof(struct s2io_msix_entry));
cc6e7c44
RA		 3886 nic->entries = NULL;
3887 nic->s2io_entries = NULL;
3888 return -ENOMEM;
3889 }
3890
3891 /*
3892 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3893 * in the herc NIC. (Temp change, needs to be removed later)
3894 */
3895 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3896 msi_control |= 0x1; /* Enable MSI */
3897 pci_write_config_word(nic->pdev, 0x42, msi_control);
3898
3899 return 0;
3900}
3901
8abc4d5b 3902/* Handle software interrupt used during MSI(X) test */
33390a70 3903static irqreturn_t s2io_test_intr(int irq, void *dev_id)
8abc4d5b
SS		 3904{
3905 struct s2io_nic *sp = dev_id;
3906
3907 sp->msi_detected = 1;
3908 wake_up(&sp->msi_wait);
3909
3910 return IRQ_HANDLED;
3911}
3912
3913/* Test interrupt path by forcing a a software IRQ */
33390a70 3914static int s2io_test_msi(struct s2io_nic *sp)
8abc4d5b
SS		 3915{
3916 struct pci_dev *pdev = sp->pdev;
3917 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3918 int err;
3919 u64 val64, saved64;
3920
3921 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
d44570e4 3922 sp->name, sp);
8abc4d5b
SS		 3923 if (err) {
3924 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
d44570e4 3925 sp->dev->name, pci_name(pdev), pdev->irq);
8abc4d5b
SS		 3926 return err;
3927 }
3928
d44570e4 3929 init_waitqueue_head(&sp->msi_wait);
8abc4d5b
SS		 3930 sp->msi_detected = 0;
3931
3932 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3933 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3934 val64 |= SCHED_INT_CTRL_TIMER_EN;
3935 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3936 writeq(val64, &bar0->scheduled_int_ctrl);
3937
3938 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3939
3940 if (!sp->msi_detected) {
3941 /* MSI(X) test failed, go back to INTx mode */
2450022a 3942 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
d44570e4
JP		 3943 "using MSI(X) during test\n", sp->dev->name,
3944 pci_name(pdev));
8abc4d5b
SS		 3945
3946 err = -EOPNOTSUPP;
3947 }
3948
3949 free_irq(sp->entries[1].vector, sp);
3950
3951 writeq(saved64, &bar0->scheduled_int_ctrl);
3952
3953 return err;
3954}
18b2b7bd
SH		 3955
3956static void remove_msix_isr(struct s2io_nic *sp)
3957{
3958 int i;
3959 u16 msi_control;
3960
f61e0a35 3961 for (i = 0; i < sp->num_entries; i++) {
d44570e4 3962 if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
18b2b7bd
SH		 3963 int vector = sp->entries[i].vector;
3964 void *arg = sp->s2io_entries[i].arg;
3965 free_irq(vector, arg);
3966 }
3967 }
3968
3969 kfree(sp->entries);
3970 kfree(sp->s2io_entries);
3971 sp->entries = NULL;
3972 sp->s2io_entries = NULL;
3973
3974 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3975 msi_control &= 0xFFFE; /* Disable MSI */
3976 pci_write_config_word(sp->pdev, 0x42, msi_control);
3977
3978 pci_disable_msix(sp->pdev);
3979}
3980
3981static void remove_inta_isr(struct s2io_nic *sp)
3982{
3983 struct net_device *dev = sp->dev;
3984
3985 free_irq(sp->pdev->irq, dev);
3986}
3987
1da177e4
LT		 3988/* ********************************************************* *
3989 * Functions defined below concern the OS part of the driver *
3990 * ********************************************************* */
3991
20346722 3992/**
1da177e4
LT		 3993 * s2io_open - open entry point of the driver
3994 * @dev : pointer to the device structure.
3995 * Description:
3996 * This function is the open entry point of the driver. It mainly calls a
3997 * function to allocate Rx buffers and inserts them into the buffer
20346722 3998 * descriptors and then enables the Rx part of the NIC.
1da177e4
LT		 3999 * Return value:
4000 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4001 * file on failure.
4002 */
4003
ac1f60db 4004static int s2io_open(struct net_device *dev)
1da177e4 4005{
4cf1653a 4006 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 4007 int err = 0;
4008
20346722
K		 4009 /*
4010 * Make sure you have link off by default every time
1da177e4
LT		 4011 * Nic is initialized
4012 */
4013 netif_carrier_off(dev);
0b1f7ebe 4014 sp->last_link_state = 0;
1da177e4
LT		 4015
4016 /* Initialize H/W and enable interrupts */
c92ca04b
AR		 4017 err = s2io_card_up(sp);
4018 if (err) {
1da177e4
LT		 4019 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
4020 dev->name);
e6a8fee2 4021 goto hw_init_failed;
1da177e4
LT		 4022 }
4023
2fd37688 4024 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
1da177e4 4025 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
e6a8fee2 4026 s2io_card_down(sp);
20346722 4027 err = -ENODEV;
e6a8fee2 4028 goto hw_init_failed;
1da177e4 4029 }
3a3d5756 4030 s2io_start_all_tx_queue(sp);
1da177e4 4031 return 0;
20346722 4032
20346722 4033hw_init_failed:
eaae7f72 4034 if (sp->config.intr_type == MSI_X) {
491976b2 4035 if (sp->entries) {
cc6e7c44 4036 kfree(sp->entries);
8a4bdbaa 4037 sp->mac_control.stats_info->sw_stat.mem_freed
d44570e4 4038 += (sp->num_entries * sizeof(struct msix_entry));
491976b2
SH		 4039 }
4040 if (sp->s2io_entries) {
cc6e7c44 4041 kfree(sp->s2io_entries);
8a4bdbaa 4042 sp->mac_control.stats_info->sw_stat.mem_freed
d44570e4 4043 += (sp->num_entries * sizeof(struct s2io_msix_entry));
491976b2 4044 }
cc6e7c44 4045 }
20346722 4046 return err;
1da177e4
LT		 4047}
4048
4049/**
4050 * s2io_close -close entry point of the driver
4051 * @dev : device pointer.
4052 * Description:
4053 * This is the stop entry point of the driver. It needs to undo exactly
4054 * whatever was done by the open entry point,thus it's usually referred to
4055 * as the close function.Among other things this function mainly stops the
4056 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4057 * Return value:
4058 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4059 * file on failure.
4060 */
4061
ac1f60db 4062static int s2io_close(struct net_device *dev)
1da177e4 4063{
4cf1653a 4064 struct s2io_nic *sp = netdev_priv(dev);
faa4f796
SH		 4065 struct config_param *config = &sp->config;
4066 u64 tmp64;
4067 int offset;
cc6e7c44 4068
9f74ffde 4069 /* Return if the device is already closed *
d44570e4
JP		 4070 * Can happen when s2io_card_up failed in change_mtu *
4071 */
9f74ffde
SH		 4072 if (!is_s2io_card_up(sp))
4073 return 0;
4074
3a3d5756 4075 s2io_stop_all_tx_queue(sp);
faa4f796
SH		 4076 /* delete all populated mac entries */
4077 for (offset = 1; offset < config->max_mc_addr; offset++) {
4078 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4079 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4080 do_s2io_delete_unicast_mc(sp, tmp64);
4081 }
4082
e6a8fee2 4083 s2io_card_down(sp);
cc6e7c44 4084
1da177e4
LT		 4085 return 0;
4086}
4087
4088/**
4089 * s2io_xmit - Tx entry point of te driver
4090 * @skb : the socket buffer containing the Tx data.
4091 * @dev : device pointer.
4092 * Description :
4093 * This function is the Tx entry point of the driver. S2IO NIC supports
4094 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4095 * NOTE: when device cant queue the pkt,just the trans_start variable will
4096 * not be upadted.
4097 * Return value:
4098 * 0 on success & 1 on failure.
4099 */
4100
ac1f60db 4101static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 4102{
4cf1653a 4103 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 4104 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4105 register u64 val64;
1ee6dd77
RB		 4106 struct TxD *txdp;
4107 struct TxFIFO_element __iomem *tx_fifo;
2fda096d 4108 unsigned long flags = 0;
be3a6b02 4109 u16 vlan_tag = 0;
2fda096d 4110 struct fifo_info *fifo = NULL;
1ee6dd77 4111 struct mac_info *mac_control;
1da177e4 4112 struct config_param *config;
6cfc482b 4113 int do_spin_lock = 1;
75c30b13 4114 int offload_type;
6cfc482b 4115 int enable_per_list_interrupt = 0;
491abf25 4116 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 4117
4118 mac_control = &sp->mac_control;
4119 config = &sp->config;
4120
20346722 4121 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
491976b2
SH		 4122
4123 if (unlikely(skb->len <= 0)) {
4124 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
4125 dev_kfree_skb_any(skb);
6ed10654 4126 return NETDEV_TX_OK;
2fda096d 4127 }
491976b2 4128
92b84437 4129 if (!is_s2io_card_up(sp)) {
20346722 4130 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
1da177e4 4131 dev->name);
20346722 4132 dev_kfree_skb(skb);
6ed10654 4133 return NETDEV_TX_OK;
1da177e4
LT		 4134 }
4135
4136 queue = 0;
3a3d5756 4137 if (sp->vlgrp && vlan_tx_tag_present(skb))
be3a6b02 4138 vlan_tag = vlan_tx_tag_get(skb);
6cfc482b
SH		 4139 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4140 if (skb->protocol == htons(ETH_P_IP)) {
4141 struct iphdr *ip;
4142 struct tcphdr *th;
4143 ip = ip_hdr(skb);
4144
4145 if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4146 th = (struct tcphdr *)(((unsigned char *)ip) +
d44570e4 4147 ip->ihl*4);
6cfc482b
SH		 4148
4149 if (ip->protocol == IPPROTO_TCP) {
4150 queue_len = sp->total_tcp_fifos;
4151 queue = (ntohs(th->source) +
d44570e4
JP		 4152 ntohs(th->dest)) &
4153 sp->fifo_selector[queue_len - 1];
6cfc482b
SH		 4154 if (queue >= queue_len)
4155 queue = queue_len - 1;
4156 } else if (ip->protocol == IPPROTO_UDP) {
4157 queue_len = sp->total_udp_fifos;
4158 queue = (ntohs(th->source) +
d44570e4
JP		 4159 ntohs(th->dest)) &
4160 sp->fifo_selector[queue_len - 1];
6cfc482b
SH		 4161 if (queue >= queue_len)
4162 queue = queue_len - 1;
4163 queue += sp->udp_fifo_idx;
4164 if (skb->len > 1024)
4165 enable_per_list_interrupt = 1;
4166 do_spin_lock = 0;
4167 }
4168 }
4169 }
4170 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4171 /* get fifo number based on skb->priority value */
4172 queue = config->fifo_mapping
d44570e4 4173 [skb->priority & (MAX_TX_FIFOS - 1)];
6cfc482b 4174 fifo = &mac_control->fifos[queue];
3a3d5756 4175
6cfc482b
SH		 4176 if (do_spin_lock)
4177 spin_lock_irqsave(&fifo->tx_lock, flags);
4178 else {
4179 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4180 return NETDEV_TX_LOCKED;
4181 }
be3a6b02 4182
3a3d5756
SH		 4183 if (sp->config.multiq) {
4184 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4185 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4186 return NETDEV_TX_BUSY;
4187 }
b19fa1fa 4188 } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
3a3d5756
SH		 4189 if (netif_queue_stopped(dev)) {
4190 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4191 return NETDEV_TX_BUSY;
4192 }
4193 }
4194
d44570e4
JP		 4195 put_off = (u16)fifo->tx_curr_put_info.offset;
4196 get_off = (u16)fifo->tx_curr_get_info.offset;
4197 txdp = (struct TxD *)fifo->list_info[put_off].list_virt_addr;
20346722 4198
2fda096d 4199 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
1da177e4 4200 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4201 if (txdp->Host_Control ||
d44570e4 4202 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
776bd20f 4203 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3a3d5756 4204 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4205 dev_kfree_skb(skb);
2fda096d 4206 spin_unlock_irqrestore(&fifo->tx_lock, flags);
6ed10654 4207 return NETDEV_TX_OK;
1da177e4 4208 }
0b1f7ebe 4209
75c30b13 4210 offload_type = s2io_offload_type(skb);
75c30b13 4211 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1da177e4 4212 txdp->Control_1 |= TXD_TCP_LSO_EN;
75c30b13 4213 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
1da177e4 4214 }
84fa7933 4215 if (skb->ip_summed == CHECKSUM_PARTIAL) {
d44570e4
JP		 4216 txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4217 TXD_TX_CKO_TCP_EN |
4218 TXD_TX_CKO_UDP_EN);
1da177e4 4219 }
fed5eccd
AR		 4220 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4221 txdp->Control_1 |= TXD_LIST_OWN_XENA;
2fda096d 4222 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
6cfc482b
SH		 4223 if (enable_per_list_interrupt)
4224 if (put_off & (queue_len >> 5))
4225 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
3a3d5756 4226 if (vlan_tag) {
be3a6b02
K		 4227 txdp->Control_2 |= TXD_VLAN_ENABLE;
4228 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4229 }
4230
fed5eccd 4231 frg_len = skb->len - skb->data_len;
75c30b13 4232 if (offload_type == SKB_GSO_UDP) {
fed5eccd
AR		 4233 int ufo_size;
4234
75c30b13 4235 ufo_size = s2io_udp_mss(skb);
fed5eccd
AR		 4236 ufo_size &= ~7;
4237 txdp->Control_1 |= TXD_UFO_EN;
4238 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4239 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4240#ifdef __BIG_ENDIAN
3459feb8 4241 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
2fda096d 4242 fifo->ufo_in_band_v[put_off] =
d44570e4 4243 (__force u64)skb_shinfo(skb)->ip6_frag_id;
fed5eccd 4244#else
2fda096d 4245 fifo->ufo_in_band_v[put_off] =
d44570e4 4246 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
fed5eccd 4247#endif
2fda096d 4248 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
fed5eccd 4249 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
d44570e4
JP		 4250 fifo->ufo_in_band_v,
4251 sizeof(u64),
4252 PCI_DMA_TODEVICE);
8d8bb39b 4253 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
491abf25 4254 goto pci_map_failed;
fed5eccd 4255 txdp++;
fed5eccd 4256 }
1da177e4 4257
d44570e4
JP		 4258 txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data,
4259 frg_len, PCI_DMA_TODEVICE);
8d8bb39b 4260 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
491abf25
VP		 4261 goto pci_map_failed;
4262
d44570e4 4263 txdp->Host_Control = (unsigned long)skb;
fed5eccd 4264 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
75c30b13 4265 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4266 txdp->Control_1 |= TXD_UFO_EN;
4267
4268 frg_cnt = skb_shinfo(skb)->nr_frags;
1da177e4
LT		 4269 /* For fragmented SKB. */
4270 for (i = 0; i < frg_cnt; i++) {
4271 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0b1f7ebe
K		 4272 /* A '0' length fragment will be ignored */
4273 if (!frag->size)
4274 continue;
1da177e4 4275 txdp++;
d44570e4
JP		 4276 txdp->Buffer_Pointer = (u64)pci_map_page(sp->pdev, frag->page,
4277 frag->page_offset,
4278 frag->size,
4279 PCI_DMA_TODEVICE);
efd51b5c 4280 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
75c30b13 4281 if (offload_type == SKB_GSO_UDP)
fed5eccd 4282 txdp->Control_1 |= TXD_UFO_EN;
1da177e4
LT		 4283 }
4284 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4285
75c30b13 4286 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4287 frg_cnt++; /* as Txd0 was used for inband header */
4288
1da177e4 4289 tx_fifo = mac_control->tx_FIFO_start[queue];
2fda096d 4290 val64 = fifo->list_info[put_off].list_phy_addr;
1da177e4
LT		 4291 writeq(val64, &tx_fifo->TxDL_Pointer);
4292
4293 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4294 TX_FIFO_LAST_LIST);
75c30b13 4295 if (offload_type)
fed5eccd 4296 val64 |= TX_FIFO_SPECIAL_FUNC;
75c30b13 4297
1da177e4
LT		 4298 writeq(val64, &tx_fifo->List_Control);
4299
303bcb4b
K		 4300 mmiowb();
4301
1da177e4 4302 put_off++;
2fda096d 4303 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
863c11a9 4304 put_off = 0;
2fda096d 4305 fifo->tx_curr_put_info.offset = put_off;
1da177e4
LT		 4306
4307 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4308 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
bd1034f0 4309 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
1da177e4
LT		 4310 DBG_PRINT(TX_DBG,
4311 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4312 put_off, get_off);
3a3d5756 4313 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4314 }
491976b2 4315 mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
2fda096d 4316 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4 4317
f6f4bfa3
SH		 4318 if (sp->config.intr_type == MSI_X)
4319 tx_intr_handler(fifo);
4320
6ed10654 4321 return NETDEV_TX_OK;
491abf25
VP		 4322pci_map_failed:
4323 stats->pci_map_fail_cnt++;
3a3d5756 4324 s2io_stop_tx_queue(sp, fifo->fifo_no);
491abf25
VP		 4325 stats->mem_freed += skb->truesize;
4326 dev_kfree_skb(skb);
2fda096d 4327 spin_unlock_irqrestore(&fifo->tx_lock, flags);
6ed10654 4328 return NETDEV_TX_OK;
1da177e4
LT		 4329}
4330
25fff88e
K		 4331static void
4332s2io_alarm_handle(unsigned long data)
4333{
1ee6dd77 4334 struct s2io_nic *sp = (struct s2io_nic *)data;
8116f3cf 4335 struct net_device *dev = sp->dev;
25fff88e 4336
8116f3cf 4337 s2io_handle_errors(dev);
25fff88e
K		 4338 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4339}
4340
7d12e780 4341static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
cc6e7c44 4342{
1ee6dd77
RB		 4343 struct ring_info *ring = (struct ring_info *)dev_id;
4344 struct s2io_nic *sp = ring->nic;
f61e0a35 4345 struct XENA_dev_config __iomem *bar0 = sp->bar0;
cc6e7c44 4346
f61e0a35 4347 if (unlikely(!is_s2io_card_up(sp)))
92b84437 4348 return IRQ_HANDLED;
92b84437 4349
f61e0a35 4350 if (sp->config.napi) {
1a79d1c3
AV		 4351 u8 __iomem *addr = NULL;
4352 u8 val8 = 0;
f61e0a35 4353
1a79d1c3 4354 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
f61e0a35
SH		 4355 addr += (7 - ring->ring_no);
4356 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4357 writeb(val8, addr);
4358 val8 = readb(addr);
288379f0 4359 napi_schedule(&ring->napi);
f61e0a35
SH		 4360 } else {
4361 rx_intr_handler(ring, 0);
8d8bb39b 4362 s2io_chk_rx_buffers(sp, ring);
f61e0a35 4363 }
7d3d0439 4364
cc6e7c44
RA		 4365 return IRQ_HANDLED;
4366}
4367
7d12e780 4368static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
cc6e7c44 4369{
ac731ab6
SH		 4370 int i;
4371 struct fifo_info *fifos = (struct fifo_info *)dev_id;
4372 struct s2io_nic *sp = fifos->nic;
4373 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4374 struct config_param *config = &sp->config;
4375 u64 reason;
cc6e7c44 4376
ac731ab6
SH		 4377 if (unlikely(!is_s2io_card_up(sp)))
4378 return IRQ_NONE;
4379
4380 reason = readq(&bar0->general_int_status);
4381 if (unlikely(reason == S2IO_MINUS_ONE))
4382 /* Nothing much can be done. Get out */
92b84437 4383 return IRQ_HANDLED;
92b84437 4384
01e16faa
SH		 4385 if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4386 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
ac731ab6 4387
01e16faa
SH		 4388 if (reason & GEN_INTR_TXPIC)
4389 s2io_txpic_intr_handle(sp);
ac731ab6 4390
01e16faa
SH		 4391 if (reason & GEN_INTR_TXTRAFFIC)
4392 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
ac731ab6 4393
01e16faa
SH		 4394 for (i = 0; i < config->tx_fifo_num; i++)
4395 tx_intr_handler(&fifos[i]);
ac731ab6 4396
01e16faa
SH		 4397 writeq(sp->general_int_mask, &bar0->general_int_mask);
4398 readl(&bar0->general_int_status);
4399 return IRQ_HANDLED;
4400 }
4401 /* The interrupt was not raised by us */
4402 return IRQ_NONE;
cc6e7c44 4403}
ac731ab6 4404
1ee6dd77 4405static void s2io_txpic_intr_handle(struct s2io_nic *sp)
a371a07d 4406{
1ee6dd77 4407 struct XENA_dev_config __iomem *bar0 = sp->bar0;
a371a07d
K		 4408 u64 val64;
4409
4410 val64 = readq(&bar0->pic_int_status);
4411 if (val64 & PIC_INT_GPIO) {
4412 val64 = readq(&bar0->gpio_int_reg);
4413 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4414 (val64 & GPIO_INT_REG_LINK_UP)) {
c92ca04b
AR		 4415 /*
4416 * This is unstable state so clear both up/down
4417 * interrupt and adapter to re-evaluate the link state.
4418 */
d44570e4 4419 val64 |= GPIO_INT_REG_LINK_DOWN;
a371a07d
K		 4420 val64 |= GPIO_INT_REG_LINK_UP;
4421 writeq(val64, &bar0->gpio_int_reg);
a371a07d 4422 val64 = readq(&bar0->gpio_int_mask);
c92ca04b
AR		 4423 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4424 GPIO_INT_MASK_LINK_DOWN);
a371a07d 4425 writeq(val64, &bar0->gpio_int_mask);
d44570e4 4426 } else if (val64 & GPIO_INT_REG_LINK_UP) {
c92ca04b 4427 val64 = readq(&bar0->adapter_status);
d44570e4 4428 /* Enable Adapter */
19a60522
SS		 4429 val64 = readq(&bar0->adapter_control);
4430 val64 |= ADAPTER_CNTL_EN;
4431 writeq(val64, &bar0->adapter_control);
4432 val64 |= ADAPTER_LED_ON;
4433 writeq(val64, &bar0->adapter_control);
4434 if (!sp->device_enabled_once)
4435 sp->device_enabled_once = 1;
c92ca04b 4436
19a60522
SS		 4437 s2io_link(sp, LINK_UP);
4438 /*
4439 * unmask link down interrupt and mask link-up
4440 * intr
4441 */
4442 val64 = readq(&bar0->gpio_int_mask);
4443 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4444 val64 |= GPIO_INT_MASK_LINK_UP;
4445 writeq(val64, &bar0->gpio_int_mask);
c92ca04b 4446
d44570e4 4447 } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
c92ca04b 4448 val64 = readq(&bar0->adapter_status);
19a60522
SS		 4449 s2io_link(sp, LINK_DOWN);
4450 /* Link is down so unmaks link up interrupt */
4451 val64 = readq(&bar0->gpio_int_mask);
4452 val64 &= ~GPIO_INT_MASK_LINK_UP;
4453 val64 |= GPIO_INT_MASK_LINK_DOWN;
4454 writeq(val64, &bar0->gpio_int_mask);
ac1f90d6
SS		 4455
4456 /* turn off LED */
4457 val64 = readq(&bar0->adapter_control);
d44570e4 4458 val64 = val64 & (~ADAPTER_LED_ON);
ac1f90d6 4459 writeq(val64, &bar0->adapter_control);
a371a07d
K		 4460 }
4461 }
c92ca04b 4462 val64 = readq(&bar0->gpio_int_mask);
a371a07d
K		 4463}
4464
8116f3cf
SS		 4465/**
4466 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4467 * @value: alarm bits
4468 * @addr: address value
4469 * @cnt: counter variable
4470 * Description: Check for alarm and increment the counter
4471 * Return Value:
4472 * 1 - if alarm bit set
4473 * 0 - if alarm bit is not set
4474 */
d44570e4
JP		 4475static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4476 unsigned long long *cnt)
8116f3cf
SS		 4477{
4478 u64 val64;
4479 val64 = readq(addr);
d44570e4 4480 if (val64 & value) {
8116f3cf
SS		 4481 writeq(val64, addr);
4482 (*cnt)++;
4483 return 1;
4484 }
4485 return 0;
4486
4487}
4488
4489/**
4490 * s2io_handle_errors - Xframe error indication handler
4491 * @nic: device private variable
4492 * Description: Handle alarms such as loss of link, single or
4493 * double ECC errors, critical and serious errors.
4494 * Return Value:
4495 * NONE
4496 */
d44570e4 4497static void s2io_handle_errors(void *dev_id)
8116f3cf 4498{
d44570e4 4499 struct net_device *dev = (struct net_device *)dev_id;
4cf1653a 4500 struct s2io_nic *sp = netdev_priv(dev);
8116f3cf 4501 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d44570e4 4502 u64 temp64 = 0, val64 = 0;
8116f3cf
SS		 4503 int i = 0;
4504
4505 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4506 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4507
92b84437 4508 if (!is_s2io_card_up(sp))
8116f3cf
SS		 4509 return;
4510
4511 if (pci_channel_offline(sp->pdev))
4512 return;
4513
4514 memset(&sw_stat->ring_full_cnt, 0,
d44570e4 4515 sizeof(sw_stat->ring_full_cnt));
8116f3cf
SS		 4516
4517 /* Handling the XPAK counters update */
d44570e4 4518 if (stats->xpak_timer_count < 72000) {
8116f3cf
SS		 4519 /* waiting for an hour */
4520 stats->xpak_timer_count++;
4521 } else {
4522 s2io_updt_xpak_counter(dev);
4523 /* reset the count to zero */
4524 stats->xpak_timer_count = 0;
4525 }
4526
4527 /* Handling link status change error Intr */
4528 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4529 val64 = readq(&bar0->mac_rmac_err_reg);
4530 writeq(val64, &bar0->mac_rmac_err_reg);
4531 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4532 schedule_work(&sp->set_link_task);
4533 }
4534
4535 /* In case of a serious error, the device will be Reset. */
4536 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
d44570e4 4537 &sw_stat->serious_err_cnt))
8116f3cf
SS		 4538 goto reset;
4539
4540 /* Check for data parity error */
4541 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
d44570e4 4542 &sw_stat->parity_err_cnt))
8116f3cf
SS		 4543 goto reset;
4544
4545 /* Check for ring full counter */
4546 if (sp->device_type == XFRAME_II_DEVICE) {
4547 val64 = readq(&bar0->ring_bump_counter1);
d44570e4
JP		 4548 for (i = 0; i < 4; i++) {
4549 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
8116f3cf
SS		 4550 temp64 >>= 64 - ((i+1)*16);
4551 sw_stat->ring_full_cnt[i] += temp64;
4552 }
4553
4554 val64 = readq(&bar0->ring_bump_counter2);
d44570e4
JP		 4555 for (i = 0; i < 4; i++) {
4556 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
8116f3cf 4557 temp64 >>= 64 - ((i+1)*16);
d44570e4 4558 sw_stat->ring_full_cnt[i+4] += temp64;
8116f3cf
SS		 4559 }
4560 }
4561
4562 val64 = readq(&bar0->txdma_int_status);
4563 /*check for pfc_err*/
4564 if (val64 & TXDMA_PFC_INT) {
d44570e4
JP		 4565 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4566 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4567 PFC_PCIX_ERR,
4568 &bar0->pfc_err_reg,
4569 &sw_stat->pfc_err_cnt))
8116f3cf 4570 goto reset;
d44570e4
JP		 4571 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4572 &bar0->pfc_err_reg,
4573 &sw_stat->pfc_err_cnt);
8116f3cf
SS		 4574 }
4575
4576 /*check for tda_err*/
4577 if (val64 & TXDMA_TDA_INT) {
d44570e4
JP		 4578 if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4579 TDA_SM0_ERR_ALARM |
4580 TDA_SM1_ERR_ALARM,
4581 &bar0->tda_err_reg,
4582 &sw_stat->tda_err_cnt))
8116f3cf
SS		 4583 goto reset;
4584 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
d44570e4
JP		 4585 &bar0->tda_err_reg,
4586 &sw_stat->tda_err_cnt);
8116f3cf
SS		 4587 }
4588 /*check for pcc_err*/
4589 if (val64 & TXDMA_PCC_INT) {
d44570e4
JP		 4590 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4591 PCC_N_SERR | PCC_6_COF_OV_ERR |
4592 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4593 PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4594 PCC_TXB_ECC_DB_ERR,
4595 &bar0->pcc_err_reg,
4596 &sw_stat->pcc_err_cnt))
8116f3cf
SS		 4597 goto reset;
4598 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
d44570e4
JP		 4599 &bar0->pcc_err_reg,
4600 &sw_stat->pcc_err_cnt);
8116f3cf
SS		 4601 }
4602
4603 /*check for tti_err*/
4604 if (val64 & TXDMA_TTI_INT) {
d44570e4
JP		 4605 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4606 &bar0->tti_err_reg,
4607 &sw_stat->tti_err_cnt))
8116f3cf
SS		 4608 goto reset;
4609 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
d44570e4
JP		 4610 &bar0->tti_err_reg,
4611 &sw_stat->tti_err_cnt);
8116f3cf
SS		 4612 }
4613
4614 /*check for lso_err*/
4615 if (val64 & TXDMA_LSO_INT) {
d44570e4
JP		 4616 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4617 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4618 &bar0->lso_err_reg,
4619 &sw_stat->lso_err_cnt))
8116f3cf
SS		 4620 goto reset;
4621 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
d44570e4
JP		 4622 &bar0->lso_err_reg,
4623 &sw_stat->lso_err_cnt);
8116f3cf
SS		 4624 }
4625
4626 /*check for tpa_err*/
4627 if (val64 & TXDMA_TPA_INT) {
d44570e4
JP		 4628 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4629 &bar0->tpa_err_reg,
4630 &sw_stat->tpa_err_cnt))
8116f3cf 4631 goto reset;
d44570e4
JP		 4632 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4633 &bar0->tpa_err_reg,
4634 &sw_stat->tpa_err_cnt);
8116f3cf
SS		 4635 }
4636
4637 /*check for sm_err*/
4638 if (val64 & TXDMA_SM_INT) {
d44570e4
JP		 4639 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4640 &bar0->sm_err_reg,
4641 &sw_stat->sm_err_cnt))
8116f3cf
SS		 4642 goto reset;
4643 }
4644
4645 val64 = readq(&bar0->mac_int_status);
4646 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4647 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
d44570e4
JP		 4648 &bar0->mac_tmac_err_reg,
4649 &sw_stat->mac_tmac_err_cnt))
8116f3cf 4650 goto reset;
d44570e4
JP		 4651 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4652 TMAC_DESC_ECC_SG_ERR |
4653 TMAC_DESC_ECC_DB_ERR,
4654 &bar0->mac_tmac_err_reg,
4655 &sw_stat->mac_tmac_err_cnt);
8116f3cf
SS		 4656 }
4657
4658 val64 = readq(&bar0->xgxs_int_status);
4659 if (val64 & XGXS_INT_STATUS_TXGXS) {
4660 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
d44570e4
JP		 4661 &bar0->xgxs_txgxs_err_reg,
4662 &sw_stat->xgxs_txgxs_err_cnt))
8116f3cf
SS		 4663 goto reset;
4664 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
d44570e4
JP		 4665 &bar0->xgxs_txgxs_err_reg,
4666 &sw_stat->xgxs_txgxs_err_cnt);
8116f3cf
SS		 4667 }
4668
4669 val64 = readq(&bar0->rxdma_int_status);
4670 if (val64 & RXDMA_INT_RC_INT_M) {
d44570e4
JP		 4671 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4672 RC_FTC_ECC_DB_ERR |
4673 RC_PRCn_SM_ERR_ALARM |
4674 RC_FTC_SM_ERR_ALARM,
4675 &bar0->rc_err_reg,
4676 &sw_stat->rc_err_cnt))
8116f3cf 4677 goto reset;
d44570e4
JP		 4678 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4679 RC_FTC_ECC_SG_ERR |
4680 RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4681 &sw_stat->rc_err_cnt);
4682 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4683 PRC_PCI_AB_WR_Rn |
4684 PRC_PCI_AB_F_WR_Rn,
4685 &bar0->prc_pcix_err_reg,
4686 &sw_stat->prc_pcix_err_cnt))
8116f3cf 4687 goto reset;
d44570e4
JP		 4688 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4689 PRC_PCI_DP_WR_Rn |
4690 PRC_PCI_DP_F_WR_Rn,
4691 &bar0->prc_pcix_err_reg,
4692 &sw_stat->prc_pcix_err_cnt);
8116f3cf
SS		 4693 }
4694
4695 if (val64 & RXDMA_INT_RPA_INT_M) {
4696 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
d44570e4
JP		 4697 &bar0->rpa_err_reg,
4698 &sw_stat->rpa_err_cnt))
8116f3cf
SS		 4699 goto reset;
4700 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
d44570e4
JP		 4701 &bar0->rpa_err_reg,
4702 &sw_stat->rpa_err_cnt);
8116f3cf
SS		 4703 }
4704
4705 if (val64 & RXDMA_INT_RDA_INT_M) {
d44570e4
JP		 4706 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4707 RDA_FRM_ECC_DB_N_AERR |
4708 RDA_SM1_ERR_ALARM |
4709 RDA_SM0_ERR_ALARM |
4710 RDA_RXD_ECC_DB_SERR,
4711 &bar0->rda_err_reg,
4712 &sw_stat->rda_err_cnt))
8116f3cf 4713 goto reset;
d44570e4
JP		 4714 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4715 RDA_FRM_ECC_SG_ERR |
4716 RDA_MISC_ERR |
4717 RDA_PCIX_ERR,
4718 &bar0->rda_err_reg,
4719 &sw_stat->rda_err_cnt);
8116f3cf
SS		 4720 }
4721
4722 if (val64 & RXDMA_INT_RTI_INT_M) {
d44570e4
JP		 4723 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4724 &bar0->rti_err_reg,
4725 &sw_stat->rti_err_cnt))
8116f3cf
SS		 4726 goto reset;
4727 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
d44570e4
JP		 4728 &bar0->rti_err_reg,
4729 &sw_stat->rti_err_cnt);
8116f3cf
SS		 4730 }
4731
4732 val64 = readq(&bar0->mac_int_status);
4733 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4734 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
d44570e4
JP		 4735 &bar0->mac_rmac_err_reg,
4736 &sw_stat->mac_rmac_err_cnt))
8116f3cf 4737 goto reset;
d44570e4
JP		 4738 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4739 RMAC_SINGLE_ECC_ERR |
4740 RMAC_DOUBLE_ECC_ERR,
4741 &bar0->mac_rmac_err_reg,
4742 &sw_stat->mac_rmac_err_cnt);
8116f3cf
SS		 4743 }
4744
4745 val64 = readq(&bar0->xgxs_int_status);
4746 if (val64 & XGXS_INT_STATUS_RXGXS) {
4747 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
d44570e4
JP		 4748 &bar0->xgxs_rxgxs_err_reg,
4749 &sw_stat->xgxs_rxgxs_err_cnt))
8116f3cf
SS		 4750 goto reset;
4751 }
4752
4753 val64 = readq(&bar0->mc_int_status);
d44570e4
JP		 4754 if (val64 & MC_INT_STATUS_MC_INT) {
4755 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4756 &bar0->mc_err_reg,
4757 &sw_stat->mc_err_cnt))
8116f3cf
SS		 4758 goto reset;
4759
4760 /* Handling Ecc errors */
4761 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4762 writeq(val64, &bar0->mc_err_reg);
4763 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4764 sw_stat->double_ecc_errs++;
4765 if (sp->device_type != XFRAME_II_DEVICE) {
4766 /*
4767 * Reset XframeI only if critical error
4768 */
4769 if (val64 &
d44570e4
JP		 4770 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4771 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4772 goto reset;
4773 }
8116f3cf
SS		 4774 } else
4775 sw_stat->single_ecc_errs++;
4776 }
4777 }
4778 return;
4779
4780reset:
3a3d5756 4781 s2io_stop_all_tx_queue(sp);
8116f3cf
SS		 4782 schedule_work(&sp->rst_timer_task);
4783 sw_stat->soft_reset_cnt++;
4784 return;
4785}
4786
1da177e4
LT		 4787/**
4788 * s2io_isr - ISR handler of the device .
4789 * @irq: the irq of the device.
4790 * @dev_id: a void pointer to the dev structure of the NIC.
20346722
K		 4791 * Description: This function is the ISR handler of the device. It
4792 * identifies the reason for the interrupt and calls the relevant
4793 * service routines. As a contongency measure, this ISR allocates the
1da177e4
LT		 4794 * recv buffers, if their numbers are below the panic value which is
4795 * presently set to 25% of the original number of rcv buffers allocated.
4796 * Return value:
20346722 4797 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
1da177e4
LT		 4798 * IRQ_NONE: will be returned if interrupt is not from our device
4799 */
7d12e780 4800static irqreturn_t s2io_isr(int irq, void *dev_id)
1da177e4 4801{
d44570e4 4802 struct net_device *dev = (struct net_device *)dev_id;
4cf1653a 4803 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 4804 struct XENA_dev_config __iomem *bar0 = sp->bar0;
20346722 4805 int i;
19a60522 4806 u64 reason = 0;
1ee6dd77 4807 struct mac_info *mac_control;
1da177e4
LT		 4808 struct config_param *config;
4809
d796fdb7
LV		 4810 /* Pretend we handled any irq's from a disconnected card */
4811 if (pci_channel_offline(sp->pdev))
4812 return IRQ_NONE;
4813
596c5c97 4814 if (!is_s2io_card_up(sp))
92b84437 4815 return IRQ_NONE;
92b84437 4816
1da177e4
LT		 4817 mac_control = &sp->mac_control;
4818 config = &sp->config;
4819
20346722 4820 /*
1da177e4
LT		 4821 * Identify the cause for interrupt and call the appropriate
4822 * interrupt handler. Causes for the interrupt could be;
4823 * 1. Rx of packet.
4824 * 2. Tx complete.
4825 * 3. Link down.
1da177e4
LT		 4826 */
4827 reason = readq(&bar0->general_int_status);
4828
d44570e4
JP		 4829 if (unlikely(reason == S2IO_MINUS_ONE))
4830 return IRQ_HANDLED; /* Nothing much can be done. Get out */
5d3213cc 4831
d44570e4
JP		 4832 if (reason &
4833 (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
596c5c97
SS		 4834 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4835
4836 if (config->napi) {
4837 if (reason & GEN_INTR_RXTRAFFIC) {
288379f0 4838 napi_schedule(&sp->napi);
f61e0a35
SH		 4839 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4840 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4841 readl(&bar0->rx_traffic_int);
db874e65 4842 }
596c5c97
SS		 4843 } else {
4844 /*
4845 * rx_traffic_int reg is an R1 register, writing all 1's
4846 * will ensure that the actual interrupt causing bit
4847 * get's cleared and hence a read can be avoided.
4848 */
4849 if (reason & GEN_INTR_RXTRAFFIC)
19a60522 4850 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
596c5c97 4851
13d866a9
JP		 4852 for (i = 0; i < config->rx_ring_num; i++) {
4853 struct ring_info *ring = &mac_control->rings[i];
4854
4855 rx_intr_handler(ring, 0);
4856 }
db874e65 4857 }
596c5c97 4858
db874e65 4859 /*
596c5c97 4860 * tx_traffic_int reg is an R1 register, writing all 1's
db874e65
SS		 4861 * will ensure that the actual interrupt causing bit get's
4862 * cleared and hence a read can be avoided.
4863 */
596c5c97
SS		 4864 if (reason & GEN_INTR_TXTRAFFIC)
4865 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
19a60522 4866
596c5c97
SS		 4867 for (i = 0; i < config->tx_fifo_num; i++)
4868 tx_intr_handler(&mac_control->fifos[i]);
1da177e4 4869
596c5c97
SS		 4870 if (reason & GEN_INTR_TXPIC)
4871 s2io_txpic_intr_handle(sp);
fe113638 4872
596c5c97
SS		 4873 /*
4874 * Reallocate the buffers from the interrupt handler itself.
4875 */
4876 if (!config->napi) {
13d866a9
JP		 4877 for (i = 0; i < config->rx_ring_num; i++) {
4878 struct ring_info *ring = &mac_control->rings[i];
4879
4880 s2io_chk_rx_buffers(sp, ring);
4881 }
596c5c97
SS		 4882 }
4883 writeq(sp->general_int_mask, &bar0->general_int_mask);
4884 readl(&bar0->general_int_status);
20346722 4885
596c5c97 4886 return IRQ_HANDLED;
db874e65 4887
d44570e4 4888 } else if (!reason) {
596c5c97
SS		 4889 /* The interrupt was not raised by us */
4890 return IRQ_NONE;
4891 }
db874e65 4892
1da177e4
LT		 4893 return IRQ_HANDLED;
4894}
4895
7ba013ac
K		 4896/**
4897 * s2io_updt_stats -
4898 */
1ee6dd77 4899static void s2io_updt_stats(struct s2io_nic *sp)
7ba013ac 4900{
1ee6dd77 4901 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7ba013ac
K		 4902 u64 val64;
4903 int cnt = 0;
4904
92b84437 4905 if (is_s2io_card_up(sp)) {
7ba013ac
K		 4906 /* Apprx 30us on a 133 MHz bus */
4907 val64 = SET_UPDT_CLICKS(10) |
4908 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4909 writeq(val64, &bar0->stat_cfg);
4910 do {
4911 udelay(100);
4912 val64 = readq(&bar0->stat_cfg);
b7b5a128 4913 if (!(val64 & s2BIT(0)))
7ba013ac
K		 4914 break;
4915 cnt++;
4916 if (cnt == 5)
4917 break; /* Updt failed */
d44570e4 4918 } while (1);
8a4bdbaa 4919 }
7ba013ac
K		 4920}
4921
1da177e4 4922/**
20346722 4923 * s2io_get_stats - Updates the device statistics structure.
1da177e4
LT		 4924 * @dev : pointer to the device structure.
4925 * Description:
20346722 4926 * This function updates the device statistics structure in the s2io_nic
1da177e4
LT		 4927 * structure and returns a pointer to the same.
4928 * Return value:
4929 * pointer to the updated net_device_stats structure.
4930 */
4931
ac1f60db 4932static struct net_device_stats *s2io_get_stats(struct net_device *dev)
1da177e4 4933{
4cf1653a 4934 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 4935 struct mac_info *mac_control;
1da177e4 4936 struct config_param *config;
0425b46a 4937 int i;
1da177e4 4938
20346722 4939
1da177e4
LT		 4940 mac_control = &sp->mac_control;
4941 config = &sp->config;
4942
7ba013ac
K		 4943 /* Configure Stats for immediate updt */
4944 s2io_updt_stats(sp);
4945
dc56e634
BL		 4946 /* Using sp->stats as a staging area, because reset (due to mtu
4947 change, for example) will clear some hardware counters */
4948 dev->stats.tx_packets +=
d44570e4 4949 le32_to_cpu(mac_control->stats_info->tmac_frms) -
dc56e634 4950 sp->stats.tx_packets;
7ba013ac
K		 4951 sp->stats.tx_packets =
4952 le32_to_cpu(mac_control->stats_info->tmac_frms);
dc56e634
BL		 4953 dev->stats.tx_errors +=
4954 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms) -
4955 sp->stats.tx_errors;
20346722
K		 4956 sp->stats.tx_errors =
4957 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
dc56e634
BL		 4958 dev->stats.rx_errors +=
4959 le64_to_cpu(mac_control->stats_info->rmac_drop_frms) -
4960 sp->stats.rx_errors;
20346722 4961 sp->stats.rx_errors =
ee705dba 4962 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
dc56e634 4963 dev->stats.multicast =
d44570e4 4964 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms) -
dc56e634 4965 sp->stats.multicast;
20346722
K		 4966 sp->stats.multicast =
4967 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
dc56e634 4968 dev->stats.rx_length_errors =
d44570e4 4969 le64_to_cpu(mac_control->stats_info->rmac_long_frms) -
dc56e634 4970 sp->stats.rx_length_errors;
1da177e4 4971 sp->stats.rx_length_errors =
ee705dba 4972 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
1da177e4 4973
0425b46a 4974 /* collect per-ring rx_packets and rx_bytes */
dc56e634 4975 dev->stats.rx_packets = dev->stats.rx_bytes = 0;
0425b46a 4976 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 4977 struct ring_info *ring = &mac_control->rings[i];
4978
4979 dev->stats.rx_packets += ring->rx_packets;
4980 dev->stats.rx_bytes += ring->rx_bytes;
0425b46a
SH		 4981 }
4982
d44570e4 4983 return &dev->stats;
1da177e4
LT		 4984}
4985
4986/**
4987 * s2io_set_multicast - entry point for multicast address enable/disable.
4988 * @dev : pointer to the device structure
4989 * Description:
20346722
K		 4990 * This function is a driver entry point which gets called by the kernel
4991 * whenever multicast addresses must be enabled/disabled. This also gets
1da177e4
LT		 4992 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4993 * determine, if multicast address must be enabled or if promiscuous mode
4994 * is to be disabled etc.
4995 * Return value:
4996 * void.
4997 */
4998
4999static void s2io_set_multicast(struct net_device *dev)
5000{
5001 int i, j, prev_cnt;
5002 struct dev_mc_list *mclist;
4cf1653a 5003 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5004 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5005 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
d44570e4 5006 0xfeffffffffffULL;
faa4f796 5007 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
1da177e4 5008 void __iomem *add;
faa4f796 5009 struct config_param *config = &sp->config;
1da177e4
LT		 5010
5011 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
5012 /* Enable all Multicast addresses */
5013 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
5014 &bar0->rmac_addr_data0_mem);
5015 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
5016 &bar0->rmac_addr_data1_mem);
5017 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5018 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5019 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
1da177e4
LT		 5020 writeq(val64, &bar0->rmac_addr_cmd_mem);
5021 /* Wait till command completes */
c92ca04b 5022 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5023 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5024 S2IO_BIT_RESET);
1da177e4
LT		 5025
5026 sp->m_cast_flg = 1;
faa4f796 5027 sp->all_multi_pos = config->max_mc_addr - 1;
1da177e4
LT		 5028 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
5029 /* Disable all Multicast addresses */
5030 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5031 &bar0->rmac_addr_data0_mem);
5e25b9dd
K		 5032 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
5033 &bar0->rmac_addr_data1_mem);
1da177e4 5034 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5035 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5036 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
1da177e4
LT		 5037 writeq(val64, &bar0->rmac_addr_cmd_mem);
5038 /* Wait till command completes */
c92ca04b 5039 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5040 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5041 S2IO_BIT_RESET);
1da177e4
LT		 5042
5043 sp->m_cast_flg = 0;
5044 sp->all_multi_pos = 0;
5045 }
5046
5047 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
5048 /* Put the NIC into promiscuous mode */
5049 add = &bar0->mac_cfg;
5050 val64 = readq(&bar0->mac_cfg);
5051 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5052
5053 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 5054 writel((u32)val64, add);
1da177e4
LT		 5055 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5056 writel((u32) (val64 >> 32), (add + 4));
5057
926930b2
SS		 5058 if (vlan_tag_strip != 1) {
5059 val64 = readq(&bar0->rx_pa_cfg);
5060 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5061 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 5062 sp->vlan_strip_flag = 0;
926930b2
SS		 5063 }
5064
1da177e4
LT		 5065 val64 = readq(&bar0->mac_cfg);
5066 sp->promisc_flg = 1;
776bd20f 5067 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
1da177e4
LT		 5068 dev->name);
5069 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5070 /* Remove the NIC from promiscuous mode */
5071 add = &bar0->mac_cfg;
5072 val64 = readq(&bar0->mac_cfg);
5073 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5074
5075 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 5076 writel((u32)val64, add);
1da177e4
LT		 5077 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5078 writel((u32) (val64 >> 32), (add + 4));
5079
926930b2
SS		 5080 if (vlan_tag_strip != 0) {
5081 val64 = readq(&bar0->rx_pa_cfg);
5082 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5083 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 5084 sp->vlan_strip_flag = 1;
926930b2
SS		 5085 }
5086
1da177e4
LT		 5087 val64 = readq(&bar0->mac_cfg);
5088 sp->promisc_flg = 0;
776bd20f 5089 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
1da177e4
LT		 5090 dev->name);
5091 }
5092
5093 /* Update individual M_CAST address list */
5094 if ((!sp->m_cast_flg) && dev->mc_count) {
5095 if (dev->mc_count >
faa4f796 5096 (config->max_mc_addr - config->max_mac_addr)) {
1da177e4
LT		 5097 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
5098 dev->name);
5099 DBG_PRINT(ERR_DBG, "can be added, please enable ");
5100 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
5101 return;
5102 }
5103
5104 prev_cnt = sp->mc_addr_count;
5105 sp->mc_addr_count = dev->mc_count;
5106
5107 /* Clear out the previous list of Mc in the H/W. */
5108 for (i = 0; i < prev_cnt; i++) {
5109 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5110 &bar0->rmac_addr_data0_mem);
5111 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
d44570e4 5112 &bar0->rmac_addr_data1_mem);
1da177e4 5113 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5114 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5115 RMAC_ADDR_CMD_MEM_OFFSET
5116 (config->mc_start_offset + i);
1da177e4
LT		 5117 writeq(val64, &bar0->rmac_addr_cmd_mem);
5118
5119 /* Wait for command completes */
c92ca04b 5120 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5121 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5122 S2IO_BIT_RESET)) {
5123 DBG_PRINT(ERR_DBG, "%s: Adding ", dev->name);
1da177e4
LT		 5124 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5125 return;
5126 }
5127 }
5128
5129 /* Create the new Rx filter list and update the same in H/W. */
5130 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
5131 i++, mclist = mclist->next) {
5132 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
5133 ETH_ALEN);
a7a80d5a 5134 mac_addr = 0;
1da177e4
LT		 5135 for (j = 0; j < ETH_ALEN; j++) {
5136 mac_addr |= mclist->dmi_addr[j];
5137 mac_addr <<= 8;
5138 }
5139 mac_addr >>= 8;
5140 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5141 &bar0->rmac_addr_data0_mem);
5142 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
d44570e4 5143 &bar0->rmac_addr_data1_mem);
1da177e4 5144 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5145 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5146 RMAC_ADDR_CMD_MEM_OFFSET
5147 (i + config->mc_start_offset);
1da177e4
LT		 5148 writeq(val64, &bar0->rmac_addr_cmd_mem);
5149
5150 /* Wait for command completes */
c92ca04b 5151 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5152 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5153 S2IO_BIT_RESET)) {
5154 DBG_PRINT(ERR_DBG, "%s: Adding ", dev->name);
1da177e4
LT		 5155 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5156 return;
5157 }
5158 }
5159 }
5160}
5161
faa4f796
SH		 5162/* read from CAM unicast & multicast addresses and store it in
5163 * def_mac_addr structure
5164 */
dac499f9 5165static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
faa4f796
SH		 5166{
5167 int offset;
5168 u64 mac_addr = 0x0;
5169 struct config_param *config = &sp->config;
5170
5171 /* store unicast & multicast mac addresses */
5172 for (offset = 0; offset < config->max_mc_addr; offset++) {
5173 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5174 /* if read fails disable the entry */
5175 if (mac_addr == FAILURE)
5176 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5177 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5178 }
5179}
5180
5181/* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5182static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5183{
5184 int offset;
5185 struct config_param *config = &sp->config;
5186 /* restore unicast mac address */
5187 for (offset = 0; offset < config->max_mac_addr; offset++)
5188 do_s2io_prog_unicast(sp->dev,
d44570e4 5189 sp->def_mac_addr[offset].mac_addr);
faa4f796
SH		 5190
5191 /* restore multicast mac address */
5192 for (offset = config->mc_start_offset;
d44570e4 5193 offset < config->max_mc_addr; offset++)
faa4f796
SH		 5194 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5195}
5196
5197/* add a multicast MAC address to CAM */
5198static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5199{
5200 int i;
5201 u64 mac_addr = 0;
5202 struct config_param *config = &sp->config;
5203
5204 for (i = 0; i < ETH_ALEN; i++) {
5205 mac_addr <<= 8;
5206 mac_addr |= addr[i];
5207 }
5208 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5209 return SUCCESS;
5210
5211 /* check if the multicast mac already preset in CAM */
5212 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5213 u64 tmp64;
5214 tmp64 = do_s2io_read_unicast_mc(sp, i);
5215 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5216 break;
5217
5218 if (tmp64 == mac_addr)
5219 return SUCCESS;
5220 }
5221 if (i == config->max_mc_addr) {
5222 DBG_PRINT(ERR_DBG,
d44570e4 5223 "CAM full no space left for multicast MAC\n");
faa4f796
SH		 5224 return FAILURE;
5225 }
5226 /* Update the internal structure with this new mac address */
5227 do_s2io_copy_mac_addr(sp, i, mac_addr);
5228
d44570e4 5229 return do_s2io_add_mac(sp, mac_addr, i);
faa4f796
SH		 5230}
5231
5232/* add MAC address to CAM */
5233static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
2fd37688
SS		 5234{
5235 u64 val64;
5236 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5237
5238 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
d44570e4 5239 &bar0->rmac_addr_data0_mem);
2fd37688 5240
d44570e4 5241 val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
2fd37688
SS		 5242 RMAC_ADDR_CMD_MEM_OFFSET(off);
5243 writeq(val64, &bar0->rmac_addr_cmd_mem);
5244
5245 /* Wait till command completes */
5246 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5247 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5248 S2IO_BIT_RESET)) {
faa4f796 5249 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
2fd37688
SS		 5250 return FAILURE;
5251 }
5252 return SUCCESS;
5253}
faa4f796
SH		 5254/* deletes a specified unicast/multicast mac entry from CAM */
5255static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5256{
5257 int offset;
5258 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5259 struct config_param *config = &sp->config;
5260
5261 for (offset = 1;
d44570e4 5262 offset < config->max_mc_addr; offset++) {
faa4f796
SH		 5263 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5264 if (tmp64 == addr) {
5265 /* disable the entry by writing 0xffffffffffffULL */
5266 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5267 return FAILURE;
5268 /* store the new mac list from CAM */
5269 do_s2io_store_unicast_mc(sp);
5270 return SUCCESS;
5271 }
5272 }
5273 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
d44570e4 5274 (unsigned long long)addr);
faa4f796
SH		 5275 return FAILURE;
5276}
5277
5278/* read mac entries from CAM */
5279static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5280{
5281 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5282 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5283
5284 /* read mac addr */
d44570e4 5285 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
faa4f796
SH		 5286 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5287 writeq(val64, &bar0->rmac_addr_cmd_mem);
5288
5289 /* Wait till command completes */
5290 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5291 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5292 S2IO_BIT_RESET)) {
faa4f796
SH		 5293 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5294 return FAILURE;
5295 }
5296 tmp64 = readq(&bar0->rmac_addr_data0_mem);
d44570e4
JP		 5297
5298 return tmp64 >> 16;
faa4f796 5299}
2fd37688
SS		 5300
5301/**
5302 * s2io_set_mac_addr driver entry point
5303 */
faa4f796 5304
2fd37688
SS		 5305static int s2io_set_mac_addr(struct net_device *dev, void *p)
5306{
5307 struct sockaddr *addr = p;
5308
5309 if (!is_valid_ether_addr(addr->sa_data))
5310 return -EINVAL;
5311
5312 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5313
5314 /* store the MAC address in CAM */
d44570e4 5315 return do_s2io_prog_unicast(dev, dev->dev_addr);
2fd37688 5316}
1da177e4 5317/**
2fd37688 5318 * do_s2io_prog_unicast - Programs the Xframe mac address
1da177e4
LT		 5319 * @dev : pointer to the device structure.
5320 * @addr: a uchar pointer to the new mac address which is to be set.
20346722 5321 * Description : This procedure will program the Xframe to receive
1da177e4 5322 * frames with new Mac Address
20346722 5323 * Return value: SUCCESS on success and an appropriate (-)ve integer
1da177e4
LT		 5324 * as defined in errno.h file on failure.
5325 */
faa4f796 5326
2fd37688 5327static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
1da177e4 5328{
4cf1653a 5329 struct s2io_nic *sp = netdev_priv(dev);
2fd37688 5330 register u64 mac_addr = 0, perm_addr = 0;
1da177e4 5331 int i;
faa4f796
SH		 5332 u64 tmp64;
5333 struct config_param *config = &sp->config;
1da177e4 5334
20346722 5335 /*
d44570e4
JP		 5336 * Set the new MAC address as the new unicast filter and reflect this
5337 * change on the device address registered with the OS. It will be
5338 * at offset 0.
5339 */
1da177e4
LT		 5340 for (i = 0; i < ETH_ALEN; i++) {
5341 mac_addr <<= 8;
5342 mac_addr |= addr[i];
2fd37688
SS		 5343 perm_addr <<= 8;
5344 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
d8d70caf
SS		 5345 }
5346
2fd37688
SS		 5347 /* check if the dev_addr is different than perm_addr */
5348 if (mac_addr == perm_addr)
d8d70caf
SS		 5349 return SUCCESS;
5350
faa4f796
SH		 5351 /* check if the mac already preset in CAM */
5352 for (i = 1; i < config->max_mac_addr; i++) {
5353 tmp64 = do_s2io_read_unicast_mc(sp, i);
5354 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5355 break;
5356
5357 if (tmp64 == mac_addr) {
5358 DBG_PRINT(INFO_DBG,
d44570e4
JP		 5359 "MAC addr:0x%llx already present in CAM\n",
5360 (unsigned long long)mac_addr);
faa4f796
SH		 5361 return SUCCESS;
5362 }
5363 }
5364 if (i == config->max_mac_addr) {
5365 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5366 return FAILURE;
5367 }
d8d70caf 5368 /* Update the internal structure with this new mac address */
faa4f796 5369 do_s2io_copy_mac_addr(sp, i, mac_addr);
d44570e4
JP		 5370
5371 return do_s2io_add_mac(sp, mac_addr, i);
1da177e4
LT		 5372}
5373
5374/**
20346722 5375 * s2io_ethtool_sset - Sets different link parameters.
1da177e4
LT		 5376 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5377 * @info: pointer to the structure with parameters given by ethtool to set
5378 * link information.
5379 * Description:
20346722 5380 * The function sets different link parameters provided by the user onto
1da177e4
LT		 5381 * the NIC.
5382 * Return value:
5383 * 0 on success.
d44570e4 5384 */
1da177e4
LT		 5385
5386static int s2io_ethtool_sset(struct net_device *dev,
5387 struct ethtool_cmd *info)
5388{
4cf1653a 5389 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 5390 if ((info->autoneg == AUTONEG_ENABLE) ||
d44570e4
JP		 5391 (info->speed != SPEED_10000) ||
5392 (info->duplex != DUPLEX_FULL))
1da177e4
LT		 5393 return -EINVAL;
5394 else {
5395 s2io_close(sp->dev);
5396 s2io_open(sp->dev);
5397 }
5398
5399 return 0;
5400}
5401
5402/**
20346722 5403 * s2io_ethtol_gset - Return link specific information.
1da177e4
LT		 5404 * @sp : private member of the device structure, pointer to the
5405 * s2io_nic structure.
5406 * @info : pointer to the structure with parameters given by ethtool
5407 * to return link information.
5408 * Description:
5409 * Returns link specific information like speed, duplex etc.. to ethtool.
5410 * Return value :
5411 * return 0 on success.
5412 */
5413
5414static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5415{
4cf1653a 5416 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5417 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5418 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5419 info->port = PORT_FIBRE;
1a7eb72b
SS		 5420
5421 /* info->transceiver */
5422 info->transceiver = XCVR_EXTERNAL;
1da177e4
LT		 5423
5424 if (netif_carrier_ok(sp->dev)) {
5425 info->speed = 10000;
5426 info->duplex = DUPLEX_FULL;
5427 } else {
5428 info->speed = -1;
5429 info->duplex = -1;
5430 }
5431
5432 info->autoneg = AUTONEG_DISABLE;
5433 return 0;
5434}
5435
5436/**
20346722
K		 5437 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5438 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5439 * s2io_nic structure.
5440 * @info : pointer to the structure with parameters given by ethtool to
5441 * return driver information.
5442 * Description:
5443 * Returns driver specefic information like name, version etc.. to ethtool.
5444 * Return value:
5445 * void
5446 */
5447
5448static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5449 struct ethtool_drvinfo *info)
5450{
4cf1653a 5451 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 5452
dbc2309d
JL		 5453 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5454 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5455 strncpy(info->fw_version, "", sizeof(info->fw_version));
5456 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
1da177e4
LT		 5457 info->regdump_len = XENA_REG_SPACE;
5458 info->eedump_len = XENA_EEPROM_SPACE;
1da177e4
LT		 5459}
5460
5461/**
5462 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
20346722 5463 * @sp: private member of the device structure, which is a pointer to the
1da177e4 5464 * s2io_nic structure.
20346722 5465 * @regs : pointer to the structure with parameters given by ethtool for
1da177e4
LT		 5466 * dumping the registers.
5467 * @reg_space: The input argumnet into which all the registers are dumped.
5468 * Description:
5469 * Dumps the entire register space of xFrame NIC into the user given
5470 * buffer area.
5471 * Return value :
5472 * void .
d44570e4 5473 */
1da177e4
LT		 5474
5475static void s2io_ethtool_gregs(struct net_device *dev,
5476 struct ethtool_regs *regs, void *space)
5477{
5478 int i;
5479 u64 reg;
d44570e4 5480 u8 *reg_space = (u8 *)space;
4cf1653a 5481 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5482
5483 regs->len = XENA_REG_SPACE;
5484 regs->version = sp->pdev->subsystem_device;
5485
5486 for (i = 0; i < regs->len; i += 8) {
5487 reg = readq(sp->bar0 + i);
5488 memcpy((reg_space + i), &reg, 8);
5489 }
5490}
5491
5492/**
5493 * s2io_phy_id - timer function that alternates adapter LED.
20346722 5494 * @data : address of the private member of the device structure, which
1da177e4 5495 * is a pointer to the s2io_nic structure, provided as an u32.
20346722
K		 5496 * Description: This is actually the timer function that alternates the
5497 * adapter LED bit of the adapter control bit to set/reset every time on
5498 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
1da177e4 5499 * once every second.
d44570e4 5500 */
1da177e4
LT		 5501static void s2io_phy_id(unsigned long data)
5502{
d44570e4 5503 struct s2io_nic *sp = (struct s2io_nic *)data;
1ee6dd77 5504 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5505 u64 val64 = 0;
5506 u16 subid;
5507
5508 subid = sp->pdev->subsystem_device;
541ae68f 5509 if ((sp->device_type == XFRAME_II_DEVICE) ||
d44570e4 5510 ((subid & 0xFF) >= 0x07)) {
1da177e4
LT		 5511 val64 = readq(&bar0->gpio_control);
5512 val64 ^= GPIO_CTRL_GPIO_0;
5513 writeq(val64, &bar0->gpio_control);
5514 } else {
5515 val64 = readq(&bar0->adapter_control);
5516 val64 ^= ADAPTER_LED_ON;
5517 writeq(val64, &bar0->adapter_control);
5518 }
5519
5520 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5521}
5522
5523/**
5524 * s2io_ethtool_idnic - To physically identify the nic on the system.
5525 * @sp : private member of the device structure, which is a pointer to the
5526 * s2io_nic structure.
20346722 5527 * @id : pointer to the structure with identification parameters given by
1da177e4
LT		 5528 * ethtool.
5529 * Description: Used to physically identify the NIC on the system.
20346722 5530 * The Link LED will blink for a time specified by the user for
1da177e4 5531 * identification.
20346722 5532 * NOTE: The Link has to be Up to be able to blink the LED. Hence
1da177e4
LT		 5533 * identification is possible only if it's link is up.
5534 * Return value:
5535 * int , returns 0 on success
5536 */
5537
5538static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5539{
5540 u64 val64 = 0, last_gpio_ctrl_val;
4cf1653a 5541 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5542 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5543 u16 subid;
5544
5545 subid = sp->pdev->subsystem_device;
5546 last_gpio_ctrl_val = readq(&bar0->gpio_control);
d44570e4 5547 if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) {
1da177e4
LT		 5548 val64 = readq(&bar0->adapter_control);
5549 if (!(val64 & ADAPTER_CNTL_EN)) {
5550 printk(KERN_ERR
5551 "Adapter Link down, cannot blink LED\n");
5552 return -EFAULT;
5553 }
5554 }
5555 if (sp->id_timer.function == NULL) {
5556 init_timer(&sp->id_timer);
5557 sp->id_timer.function = s2io_phy_id;
d44570e4 5558 sp->id_timer.data = (unsigned long)sp;
1da177e4
LT		 5559 }
5560 mod_timer(&sp->id_timer, jiffies);
5561 if (data)
20346722 5562 msleep_interruptible(data * HZ);
1da177e4 5563 else
20346722 5564 msleep_interruptible(MAX_FLICKER_TIME);
1da177e4
LT		 5565 del_timer_sync(&sp->id_timer);
5566
541ae68f 5567 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
1da177e4
LT		 5568 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5569 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5570 }
5571
5572 return 0;
5573}
5574
0cec35eb 5575static void s2io_ethtool_gringparam(struct net_device *dev,
d44570e4 5576 struct ethtool_ringparam *ering)
0cec35eb 5577{
4cf1653a 5578 struct s2io_nic *sp = netdev_priv(dev);
d44570e4 5579 int i, tx_desc_count = 0, rx_desc_count = 0;
0cec35eb
SH		 5580
5581 if (sp->rxd_mode == RXD_MODE_1)
5582 ering->rx_max_pending = MAX_RX_DESC_1;
5583 else if (sp->rxd_mode == RXD_MODE_3B)
5584 ering->rx_max_pending = MAX_RX_DESC_2;
0cec35eb
SH		 5585
5586 ering->tx_max_pending = MAX_TX_DESC;
8a4bdbaa 5587 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
0cec35eb 5588 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
8a4bdbaa 5589
d44570e4 5590 DBG_PRINT(INFO_DBG, "\nmax txds : %d\n", sp->config.max_txds);
0cec35eb
SH		 5591 ering->tx_pending = tx_desc_count;
5592 rx_desc_count = 0;
8a4bdbaa 5593 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
0cec35eb 5594 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
b6627672 5595
0cec35eb
SH		 5596 ering->rx_pending = rx_desc_count;
5597
5598 ering->rx_mini_max_pending = 0;
5599 ering->rx_mini_pending = 0;
d44570e4 5600 if (sp->rxd_mode == RXD_MODE_1)
0cec35eb
SH		 5601 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5602 else if (sp->rxd_mode == RXD_MODE_3B)
5603 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5604 ering->rx_jumbo_pending = rx_desc_count;
5605}
5606
1da177e4
LT		 5607/**
5608 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
20346722
K		 5609 * @sp : private member of the device structure, which is a pointer to the
5610 * s2io_nic structure.
1da177e4
LT		 5611 * @ep : pointer to the structure with pause parameters given by ethtool.
5612 * Description:
5613 * Returns the Pause frame generation and reception capability of the NIC.
5614 * Return value:
5615 * void
5616 */
5617static void s2io_ethtool_getpause_data(struct net_device *dev,
5618 struct ethtool_pauseparam *ep)
5619{
5620 u64 val64;
4cf1653a 5621 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5622 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5623
5624 val64 = readq(&bar0->rmac_pause_cfg);
5625 if (val64 & RMAC_PAUSE_GEN_ENABLE)
f957bcf0 5626 ep->tx_pause = true;
1da177e4 5627 if (val64 & RMAC_PAUSE_RX_ENABLE)
f957bcf0
TK		 5628 ep->rx_pause = true;
5629 ep->autoneg = false;
1da177e4
LT		 5630}
5631
5632/**
5633 * s2io_ethtool_setpause_data - set/reset pause frame generation.
20346722 5634 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5635 * s2io_nic structure.
5636 * @ep : pointer to the structure with pause parameters given by ethtool.
5637 * Description:
5638 * It can be used to set or reset Pause frame generation or reception
5639 * support of the NIC.
5640 * Return value:
5641 * int, returns 0 on Success
5642 */
5643
5644static int s2io_ethtool_setpause_data(struct net_device *dev,
d44570e4 5645 struct ethtool_pauseparam *ep)
1da177e4
LT		 5646{
5647 u64 val64;
4cf1653a 5648 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5649 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5650
5651 val64 = readq(&bar0->rmac_pause_cfg);
5652 if (ep->tx_pause)
5653 val64 |= RMAC_PAUSE_GEN_ENABLE;
5654 else
5655 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5656 if (ep->rx_pause)
5657 val64 |= RMAC_PAUSE_RX_ENABLE;
5658 else
5659 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5660 writeq(val64, &bar0->rmac_pause_cfg);
5661 return 0;
5662}
5663
5664/**
5665 * read_eeprom - reads 4 bytes of data from user given offset.
20346722 5666 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5667 * s2io_nic structure.
5668 * @off : offset at which the data must be written
5669 * @data : Its an output parameter where the data read at the given
20346722 5670 * offset is stored.
1da177e4 5671 * Description:
20346722 5672 * Will read 4 bytes of data from the user given offset and return the
1da177e4
LT		 5673 * read data.
5674 * NOTE: Will allow to read only part of the EEPROM visible through the
5675 * I2C bus.
5676 * Return value:
5677 * -1 on failure and 0 on success.
5678 */
5679
5680#define S2IO_DEV_ID 5
d44570e4 5681static int read_eeprom(struct s2io_nic *sp, int off, u64 *data)
1da177e4
LT		 5682{
5683 int ret = -1;
5684 u32 exit_cnt = 0;
5685 u64 val64;
1ee6dd77 5686 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5687
ad4ebed0 5688 if (sp->device_type == XFRAME_I_DEVICE) {
d44570e4
JP		 5689 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5690 I2C_CONTROL_ADDR(off) |
5691 I2C_CONTROL_BYTE_CNT(0x3) |
5692 I2C_CONTROL_READ |
5693 I2C_CONTROL_CNTL_START;
ad4ebed0 5694 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
1da177e4 5695
ad4ebed0 5696 while (exit_cnt < 5) {
5697 val64 = readq(&bar0->i2c_control);
5698 if (I2C_CONTROL_CNTL_END(val64)) {
5699 *data = I2C_CONTROL_GET_DATA(val64);
5700 ret = 0;
5701 break;
5702 }
5703 msleep(50);
5704 exit_cnt++;
1da177e4 5705 }
1da177e4
LT		 5706 }
5707
ad4ebed0 5708 if (sp->device_type == XFRAME_II_DEVICE) {
5709 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5710 SPI_CONTROL_BYTECNT(0x3) |
ad4ebed0 5711 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5712 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5713 val64 |= SPI_CONTROL_REQ;
5714 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5715 while (exit_cnt < 5) {
5716 val64 = readq(&bar0->spi_control);
5717 if (val64 & SPI_CONTROL_NACK) {
5718 ret = 1;
5719 break;
5720 } else if (val64 & SPI_CONTROL_DONE) {
5721 *data = readq(&bar0->spi_data);
5722 *data &= 0xffffff;
5723 ret = 0;
5724 break;
5725 }
5726 msleep(50);
5727 exit_cnt++;
5728 }
5729 }
1da177e4
LT		 5730 return ret;
5731}
5732
5733/**
5734 * write_eeprom - actually writes the relevant part of the data value.
5735 * @sp : private member of the device structure, which is a pointer to the
5736 * s2io_nic structure.
5737 * @off : offset at which the data must be written
5738 * @data : The data that is to be written
20346722 5739 * @cnt : Number of bytes of the data that are actually to be written into
1da177e4
LT		 5740 * the Eeprom. (max of 3)
5741 * Description:
5742 * Actually writes the relevant part of the data value into the Eeprom
5743 * through the I2C bus.
5744 * Return value:
5745 * 0 on success, -1 on failure.
5746 */
5747
d44570e4 5748static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt)
1da177e4
LT		 5749{
5750 int exit_cnt = 0, ret = -1;
5751 u64 val64;
1ee6dd77 5752 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5753
ad4ebed0 5754 if (sp->device_type == XFRAME_I_DEVICE) {
d44570e4
JP		 5755 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5756 I2C_CONTROL_ADDR(off) |
5757 I2C_CONTROL_BYTE_CNT(cnt) |
5758 I2C_CONTROL_SET_DATA((u32)data) |
5759 I2C_CONTROL_CNTL_START;
ad4ebed0 5760 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5761
5762 while (exit_cnt < 5) {
5763 val64 = readq(&bar0->i2c_control);
5764 if (I2C_CONTROL_CNTL_END(val64)) {
5765 if (!(val64 & I2C_CONTROL_NACK))
5766 ret = 0;
5767 break;
5768 }
5769 msleep(50);
5770 exit_cnt++;
5771 }
5772 }
1da177e4 5773
ad4ebed0 5774 if (sp->device_type == XFRAME_II_DEVICE) {
5775 int write_cnt = (cnt == 8) ? 0 : cnt;
d44570e4 5776 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
ad4ebed0 5777
5778 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5779 SPI_CONTROL_BYTECNT(write_cnt) |
ad4ebed0 5780 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5781 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5782 val64 |= SPI_CONTROL_REQ;
5783 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5784 while (exit_cnt < 5) {
5785 val64 = readq(&bar0->spi_control);
5786 if (val64 & SPI_CONTROL_NACK) {
5787 ret = 1;
5788 break;
5789 } else if (val64 & SPI_CONTROL_DONE) {
1da177e4 5790 ret = 0;
ad4ebed0 5791 break;
5792 }
5793 msleep(50);
5794 exit_cnt++;
1da177e4 5795 }
1da177e4 5796 }
1da177e4
LT		 5797 return ret;
5798}
1ee6dd77 5799static void s2io_vpd_read(struct s2io_nic *nic)
9dc737a7 5800{
b41477f3
AR		 5801 u8 *vpd_data;
5802 u8 data;
d44570e4 5803 int i = 0, cnt, fail = 0;
9dc737a7
AR		 5804 int vpd_addr = 0x80;
5805
5806 if (nic->device_type == XFRAME_II_DEVICE) {
5807 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5808 vpd_addr = 0x80;
d44570e4 5809 } else {
9dc737a7
AR		 5810 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5811 vpd_addr = 0x50;
5812 }
19a60522 5813 strcpy(nic->serial_num, "NOT AVAILABLE");
9dc737a7 5814
b41477f3 5815 vpd_data = kmalloc(256, GFP_KERNEL);
c53d4945
SH		 5816 if (!vpd_data) {
5817 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
b41477f3 5818 return;
c53d4945 5819 }
491976b2 5820 nic->mac_control.stats_info->sw_stat.mem_allocated += 256;
b41477f3 5821
d44570e4 5822 for (i = 0; i < 256; i += 4) {
9dc737a7
AR		 5823 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5824 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5825 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
d44570e4 5826 for (cnt = 0; cnt < 5; cnt++) {
9dc737a7
AR		 5827 msleep(2);
5828 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5829 if (data == 0x80)
5830 break;
5831 }
5832 if (cnt >= 5) {
5833 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5834 fail = 1;
5835 break;
5836 }
5837 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5838 (u32 *)&vpd_data[i]);
5839 }
19a60522 5840
d44570e4 5841 if (!fail) {
19a60522
SS		 5842 /* read serial number of adapter */
5843 for (cnt = 0; cnt < 256; cnt++) {
d44570e4
JP		 5844 if ((vpd_data[cnt] == 'S') &&
5845 (vpd_data[cnt+1] == 'N') &&
5846 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
19a60522
SS		 5847 memset(nic->serial_num, 0, VPD_STRING_LEN);
5848 memcpy(nic->serial_num, &vpd_data[cnt + 3],
d44570e4 5849 vpd_data[cnt+2]);
19a60522
SS		 5850 break;
5851 }
5852 }
5853 }
5854
5855 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
9dc737a7
AR		 5856 memset(nic->product_name, 0, vpd_data[1]);
5857 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5858 }
b41477f3 5859 kfree(vpd_data);
491976b2 5860 nic->mac_control.stats_info->sw_stat.mem_freed += 256;
9dc737a7
AR		 5861}
5862
1da177e4
LT		 5863/**
5864 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5865 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
20346722 5866 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5867 * containing all relevant information.
5868 * @data_buf : user defined value to be written into Eeprom.
5869 * Description: Reads the values stored in the Eeprom at given offset
5870 * for a given length. Stores these values int the input argument data
5871 * buffer 'data_buf' and returns these to the caller (ethtool.)
5872 * Return value:
5873 * int 0 on success
5874 */
5875
5876static int s2io_ethtool_geeprom(struct net_device *dev,
d44570e4 5877 struct ethtool_eeprom *eeprom, u8 * data_buf)
1da177e4 5878{
ad4ebed0 5879 u32 i, valid;
5880 u64 data;
4cf1653a 5881 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5882
5883 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5884
5885 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5886 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5887
5888 for (i = 0; i < eeprom->len; i += 4) {
5889 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5890 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5891 return -EFAULT;
5892 }
5893 valid = INV(data);
5894 memcpy((data_buf + i), &valid, 4);
5895 }
5896 return 0;
5897}
5898
5899/**
5900 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5901 * @sp : private member of the device structure, which is a pointer to the
5902 * s2io_nic structure.
20346722 5903 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5904 * containing all relevant information.
5905 * @data_buf ; user defined value to be written into Eeprom.
5906 * Description:
5907 * Tries to write the user provided value in the Eeprom, at the offset
5908 * given by the user.
5909 * Return value:
5910 * 0 on success, -EFAULT on failure.
5911 */
5912
5913static int s2io_ethtool_seeprom(struct net_device *dev,
5914 struct ethtool_eeprom *eeprom,
d44570e4 5915 u8 *data_buf)
1da177e4
LT		 5916{
5917 int len = eeprom->len, cnt = 0;
ad4ebed0 5918 u64 valid = 0, data;
4cf1653a 5919 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5920
5921 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5922 DBG_PRINT(ERR_DBG,
5923 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
d44570e4 5924 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n", eeprom->magic);
1da177e4
LT		 5925 return -EFAULT;
5926 }
5927
5928 while (len) {
d44570e4
JP		 5929 data = (u32)data_buf[cnt] & 0x000000FF;
5930 if (data)
5931 valid = (u32)(data << 24);
5932 else
1da177e4
LT		 5933 valid = data;
5934
5935 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5936 DBG_PRINT(ERR_DBG,
5937 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5938 DBG_PRINT(ERR_DBG,
5939 "write into the specified offset\n");
5940 return -EFAULT;
5941 }
5942 cnt++;
5943 len--;
5944 }
5945
5946 return 0;
5947}
5948
5949/**
20346722
K		 5950 * s2io_register_test - reads and writes into all clock domains.
5951 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5952 * s2io_nic structure.
5953 * @data : variable that returns the result of each of the test conducted b
5954 * by the driver.
5955 * Description:
5956 * Read and write into all clock domains. The NIC has 3 clock domains,
5957 * see that registers in all the three regions are accessible.
5958 * Return value:
5959 * 0 on success.
5960 */
5961
d44570e4 5962static int s2io_register_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 5963{
1ee6dd77 5964 struct XENA_dev_config __iomem *bar0 = sp->bar0;
ad4ebed0 5965 u64 val64 = 0, exp_val;
1da177e4
LT		 5966 int fail = 0;
5967
20346722
K		 5968 val64 = readq(&bar0->pif_rd_swapper_fb);
5969 if (val64 != 0x123456789abcdefULL) {
1da177e4
LT		 5970 fail = 1;
5971 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5972 }
5973
5974 val64 = readq(&bar0->rmac_pause_cfg);
5975 if (val64 != 0xc000ffff00000000ULL) {
5976 fail = 1;
5977 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5978 }
5979
5980 val64 = readq(&bar0->rx_queue_cfg);
ad4ebed0 5981 if (sp->device_type == XFRAME_II_DEVICE)
5982 exp_val = 0x0404040404040404ULL;
5983 else
5984 exp_val = 0x0808080808080808ULL;
5985 if (val64 != exp_val) {
1da177e4
LT		 5986 fail = 1;
5987 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5988 }
5989
5990 val64 = readq(&bar0->xgxs_efifo_cfg);
5991 if (val64 != 0x000000001923141EULL) {
5992 fail = 1;
5993 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5994 }
5995
5996 val64 = 0x5A5A5A5A5A5A5A5AULL;
5997 writeq(val64, &bar0->xmsi_data);
5998 val64 = readq(&bar0->xmsi_data);
5999 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
6000 fail = 1;
6001 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
6002 }
6003
6004 val64 = 0xA5A5A5A5A5A5A5A5ULL;
6005 writeq(val64, &bar0->xmsi_data);
6006 val64 = readq(&bar0->xmsi_data);
6007 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
6008 fail = 1;
6009 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
6010 }
6011
6012 *data = fail;
ad4ebed0 6013 return fail;
1da177e4
LT		 6014}
6015
6016/**
20346722 6017 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
1da177e4
LT		 6018 * @sp : private member of the device structure, which is a pointer to the
6019 * s2io_nic structure.
6020 * @data:variable that returns the result of each of the test conducted by
6021 * the driver.
6022 * Description:
20346722 6023 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
1da177e4
LT		 6024 * register.
6025 * Return value:
6026 * 0 on success.
6027 */
6028
d44570e4 6029static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data)
1da177e4
LT		 6030{
6031 int fail = 0;
ad4ebed0 6032 u64 ret_data, org_4F0, org_7F0;
6033 u8 saved_4F0 = 0, saved_7F0 = 0;
6034 struct net_device *dev = sp->dev;
1da177e4
LT		 6035
6036 /* Test Write Error at offset 0 */
ad4ebed0 6037 /* Note that SPI interface allows write access to all areas
6038 * of EEPROM. Hence doing all negative testing only for Xframe I.
6039 */
6040 if (sp->device_type == XFRAME_I_DEVICE)
6041 if (!write_eeprom(sp, 0, 0, 3))
6042 fail = 1;
6043
6044 /* Save current values at offsets 0x4F0 and 0x7F0 */
6045 if (!read_eeprom(sp, 0x4F0, &org_4F0))
6046 saved_4F0 = 1;
6047 if (!read_eeprom(sp, 0x7F0, &org_7F0))
6048 saved_7F0 = 1;
1da177e4
LT		 6049
6050 /* Test Write at offset 4f0 */
ad4ebed0 6051 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
1da177e4
LT		 6052 fail = 1;
6053 if (read_eeprom(sp, 0x4F0, &ret_data))
6054 fail = 1;
6055
ad4ebed0 6056 if (ret_data != 0x012345) {
26b7625c 6057 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
d44570e4
JP		 6058 "Data written %llx Data read %llx\n",
6059 dev->name, (unsigned long long)0x12345,
6060 (unsigned long long)ret_data);
1da177e4 6061 fail = 1;
ad4ebed0 6062 }
1da177e4
LT		 6063
6064 /* Reset the EEPROM data go FFFF */
ad4ebed0 6065 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
1da177e4
LT		 6066
6067 /* Test Write Request Error at offset 0x7c */
ad4ebed0 6068 if (sp->device_type == XFRAME_I_DEVICE)
6069 if (!write_eeprom(sp, 0x07C, 0, 3))
6070 fail = 1;
1da177e4 6071
ad4ebed0 6072 /* Test Write Request at offset 0x7f0 */
6073 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
1da177e4 6074 fail = 1;
ad4ebed0 6075 if (read_eeprom(sp, 0x7F0, &ret_data))
1da177e4
LT		 6076 fail = 1;
6077
ad4ebed0 6078 if (ret_data != 0x012345) {
26b7625c 6079 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
d44570e4
JP		 6080 "Data written %llx Data read %llx\n",
6081 dev->name, (unsigned long long)0x12345,
6082 (unsigned long long)ret_data);
1da177e4 6083 fail = 1;
ad4ebed0 6084 }
1da177e4
LT		 6085
6086 /* Reset the EEPROM data go FFFF */
ad4ebed0 6087 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
1da177e4 6088
ad4ebed0 6089 if (sp->device_type == XFRAME_I_DEVICE) {
6090 /* Test Write Error at offset 0x80 */
6091 if (!write_eeprom(sp, 0x080, 0, 3))
6092 fail = 1;
1da177e4 6093
ad4ebed0 6094 /* Test Write Error at offset 0xfc */
6095 if (!write_eeprom(sp, 0x0FC, 0, 3))
6096 fail = 1;
1da177e4 6097
ad4ebed0 6098 /* Test Write Error at offset 0x100 */
6099 if (!write_eeprom(sp, 0x100, 0, 3))
6100 fail = 1;
1da177e4 6101
ad4ebed0 6102 /* Test Write Error at offset 4ec */
6103 if (!write_eeprom(sp, 0x4EC, 0, 3))
6104 fail = 1;
6105 }
6106
6107 /* Restore values at offsets 0x4F0 and 0x7F0 */
6108 if (saved_4F0)
6109 write_eeprom(sp, 0x4F0, org_4F0, 3);
6110 if (saved_7F0)
6111 write_eeprom(sp, 0x7F0, org_7F0, 3);
1da177e4
LT		 6112
6113 *data = fail;
ad4ebed0 6114 return fail;
1da177e4
LT		 6115}
6116
6117/**
6118 * s2io_bist_test - invokes the MemBist test of the card .
20346722 6119 * @sp : private member of the device structure, which is a pointer to the
1da177e4 6120 * s2io_nic structure.
20346722 6121 * @data:variable that returns the result of each of the test conducted by
1da177e4
LT		 6122 * the driver.
6123 * Description:
6124 * This invokes the MemBist test of the card. We give around
6125 * 2 secs time for the Test to complete. If it's still not complete
20346722 6126 * within this peiod, we consider that the test failed.
1da177e4
LT		 6127 * Return value:
6128 * 0 on success and -1 on failure.
6129 */
6130
d44570e4 6131static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data)
1da177e4
LT		 6132{
6133 u8 bist = 0;
6134 int cnt = 0, ret = -1;
6135
6136 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6137 bist |= PCI_BIST_START;
6138 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6139
6140 while (cnt < 20) {
6141 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6142 if (!(bist & PCI_BIST_START)) {
6143 *data = (bist & PCI_BIST_CODE_MASK);
6144 ret = 0;
6145 break;
6146 }
6147 msleep(100);
6148 cnt++;
6149 }
6150
6151 return ret;
6152}
6153
6154/**
20346722
K		 6155 * s2io-link_test - verifies the link state of the nic
6156 * @sp ; private member of the device structure, which is a pointer to the
1da177e4
LT		 6157 * s2io_nic structure.
6158 * @data: variable that returns the result of each of the test conducted by
6159 * the driver.
6160 * Description:
20346722 6161 * The function verifies the link state of the NIC and updates the input
1da177e4
LT		 6162 * argument 'data' appropriately.
6163 * Return value:
6164 * 0 on success.
6165 */
6166
d44570e4 6167static int s2io_link_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 6168{
1ee6dd77 6169 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 6170 u64 val64;
6171
6172 val64 = readq(&bar0->adapter_status);
d44570e4 6173 if (!(LINK_IS_UP(val64)))
1da177e4 6174 *data = 1;
c92ca04b
AR		 6175 else
6176 *data = 0;
1da177e4 6177
b41477f3 6178 return *data;
1da177e4
LT		 6179}
6180
6181/**
20346722
K		 6182 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6183 * @sp - private member of the device structure, which is a pointer to the
1da177e4 6184 * s2io_nic structure.
20346722 6185 * @data - variable that returns the result of each of the test
1da177e4
LT		 6186 * conducted by the driver.
6187 * Description:
20346722 6188 * This is one of the offline test that tests the read and write
1da177e4
LT		 6189 * access to the RldRam chip on the NIC.
6190 * Return value:
6191 * 0 on success.
6192 */
6193
d44570e4 6194static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 6195{
1ee6dd77 6196 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 6197 u64 val64;
ad4ebed0 6198 int cnt, iteration = 0, test_fail = 0;
1da177e4
LT		 6199
6200 val64 = readq(&bar0->adapter_control);
6201 val64 &= ~ADAPTER_ECC_EN;
6202 writeq(val64, &bar0->adapter_control);
6203
6204 val64 = readq(&bar0->mc_rldram_test_ctrl);
6205 val64 |= MC_RLDRAM_TEST_MODE;
ad4ebed0 6206 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6207
6208 val64 = readq(&bar0->mc_rldram_mrs);
6209 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6210 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6211
6212 val64 |= MC_RLDRAM_MRS_ENABLE;
6213 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6214
6215 while (iteration < 2) {
6216 val64 = 0x55555555aaaa0000ULL;
d44570e4 6217 if (iteration == 1)
1da177e4 6218 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6219 writeq(val64, &bar0->mc_rldram_test_d0);
6220
6221 val64 = 0xaaaa5a5555550000ULL;
d44570e4 6222 if (iteration == 1)
1da177e4 6223 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6224 writeq(val64, &bar0->mc_rldram_test_d1);
6225
6226 val64 = 0x55aaaaaaaa5a0000ULL;
d44570e4 6227 if (iteration == 1)
1da177e4 6228 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6229 writeq(val64, &bar0->mc_rldram_test_d2);
6230
ad4ebed0 6231 val64 = (u64) (0x0000003ffffe0100ULL);
1da177e4
LT		 6232 writeq(val64, &bar0->mc_rldram_test_add);
6233
d44570e4
JP		 6234 val64 = MC_RLDRAM_TEST_MODE |
6235 MC_RLDRAM_TEST_WRITE |
6236 MC_RLDRAM_TEST_GO;
ad4ebed0 6237 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6238
6239 for (cnt = 0; cnt < 5; cnt++) {
6240 val64 = readq(&bar0->mc_rldram_test_ctrl);
6241 if (val64 & MC_RLDRAM_TEST_DONE)
6242 break;
6243 msleep(200);
6244 }
6245
6246 if (cnt == 5)
6247 break;
6248
ad4ebed0 6249 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6250 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6251
6252 for (cnt = 0; cnt < 5; cnt++) {
6253 val64 = readq(&bar0->mc_rldram_test_ctrl);
6254 if (val64 & MC_RLDRAM_TEST_DONE)
6255 break;
6256 msleep(500);
6257 }
6258
6259 if (cnt == 5)
6260 break;
6261
6262 val64 = readq(&bar0->mc_rldram_test_ctrl);
ad4ebed0 6263 if (!(val64 & MC_RLDRAM_TEST_PASS))
6264 test_fail = 1;
1da177e4
LT		 6265
6266 iteration++;
6267 }
6268
ad4ebed0 6269 *data = test_fail;
1da177e4 6270
ad4ebed0 6271 /* Bring the adapter out of test mode */
6272 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6273
6274 return test_fail;
1da177e4
LT		 6275}
6276
6277/**
6278 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6279 * @sp : private member of the device structure, which is a pointer to the
6280 * s2io_nic structure.
6281 * @ethtest : pointer to a ethtool command specific structure that will be
6282 * returned to the user.
20346722 6283 * @data : variable that returns the result of each of the test
1da177e4
LT		 6284 * conducted by the driver.
6285 * Description:
6286 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6287 * the health of the card.
6288 * Return value:
6289 * void
6290 */
6291
6292static void s2io_ethtool_test(struct net_device *dev,
6293 struct ethtool_test *ethtest,
d44570e4 6294 uint64_t *data)
1da177e4 6295{
4cf1653a 6296 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 6297 int orig_state = netif_running(sp->dev);
6298
6299 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6300 /* Offline Tests. */
20346722 6301 if (orig_state)
1da177e4 6302 s2io_close(sp->dev);
1da177e4
LT		 6303
6304 if (s2io_register_test(sp, &data[0]))
6305 ethtest->flags |= ETH_TEST_FL_FAILED;
6306
6307 s2io_reset(sp);
1da177e4
LT		 6308
6309 if (s2io_rldram_test(sp, &data[3]))
6310 ethtest->flags |= ETH_TEST_FL_FAILED;
6311
6312 s2io_reset(sp);
1da177e4
LT		 6313
6314 if (s2io_eeprom_test(sp, &data[1]))
6315 ethtest->flags |= ETH_TEST_FL_FAILED;
6316
6317 if (s2io_bist_test(sp, &data[4]))
6318 ethtest->flags |= ETH_TEST_FL_FAILED;
6319
6320 if (orig_state)
6321 s2io_open(sp->dev);
6322
6323 data[2] = 0;
6324 } else {
6325 /* Online Tests. */
6326 if (!orig_state) {
d44570e4 6327 DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n",
1da177e4
LT		 6328 dev->name);
6329 data[0] = -1;
6330 data[1] = -1;
6331 data[2] = -1;
6332 data[3] = -1;
6333 data[4] = -1;
6334 }
6335
6336 if (s2io_link_test(sp, &data[2]))
6337 ethtest->flags |= ETH_TEST_FL_FAILED;
6338
6339 data[0] = 0;
6340 data[1] = 0;
6341 data[3] = 0;
6342 data[4] = 0;
6343 }
6344}
6345
6346static void s2io_get_ethtool_stats(struct net_device *dev,
6347 struct ethtool_stats *estats,
d44570e4 6348 u64 *tmp_stats)
1da177e4 6349{
8116f3cf 6350 int i = 0, k;
4cf1653a 6351 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 6352 struct stat_block *stat_info = sp->mac_control.stats_info;
1da177e4 6353
7ba013ac 6354 s2io_updt_stats(sp);
541ae68f
K		 6355 tmp_stats[i++] =
6356 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
6357 le32_to_cpu(stat_info->tmac_frms);
6358 tmp_stats[i++] =
6359 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
6360 le32_to_cpu(stat_info->tmac_data_octets);
1da177e4 6361 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
541ae68f
K		 6362 tmp_stats[i++] =
6363 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
6364 le32_to_cpu(stat_info->tmac_mcst_frms);
6365 tmp_stats[i++] =
6366 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
6367 le32_to_cpu(stat_info->tmac_bcst_frms);
1da177e4 6368 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
bd1034f0 6369 tmp_stats[i++] =
d44570e4
JP		 6370 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
6371 le32_to_cpu(stat_info->tmac_ttl_octets);
bd1034f0 6372 tmp_stats[i++] =
d44570e4
JP		 6373 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
6374 le32_to_cpu(stat_info->tmac_ucst_frms);
6375 tmp_stats[i++] =
6376 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
6377 le32_to_cpu(stat_info->tmac_nucst_frms);
541ae68f
K		 6378 tmp_stats[i++] =
6379 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
6380 le32_to_cpu(stat_info->tmac_any_err_frms);
d44570e4 6381 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
1da177e4 6382 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
541ae68f
K		 6383 tmp_stats[i++] =
6384 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
6385 le32_to_cpu(stat_info->tmac_vld_ip);
6386 tmp_stats[i++] =
6387 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
6388 le32_to_cpu(stat_info->tmac_drop_ip);
6389 tmp_stats[i++] =
6390 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
6391 le32_to_cpu(stat_info->tmac_icmp);
6392 tmp_stats[i++] =
6393 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
6394 le32_to_cpu(stat_info->tmac_rst_tcp);
1da177e4 6395 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
541ae68f
K		 6396 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
6397 le32_to_cpu(stat_info->tmac_udp);
6398 tmp_stats[i++] =
6399 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
6400 le32_to_cpu(stat_info->rmac_vld_frms);
6401 tmp_stats[i++] =
6402 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
6403 le32_to_cpu(stat_info->rmac_data_octets);
1da177e4
LT		 6404 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
6405 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
541ae68f
K		 6406 tmp_stats[i++] =
6407 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
6408 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
6409 tmp_stats[i++] =
6410 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
6411 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
1da177e4 6412 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
bd1034f0 6413 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
1da177e4
LT		 6414 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
6415 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
bd1034f0 6416 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
d44570e4
JP		 6417 tmp_stats[i++] =
6418 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
bd1034f0 6419 le32_to_cpu(stat_info->rmac_ttl_octets);
bd1034f0 6420 tmp_stats[i++] =
d44570e4
JP		 6421 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow) << 32
6422 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
6423 tmp_stats[i++] =
6424 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
6425 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
541ae68f
K		 6426 tmp_stats[i++] =
6427 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
6428 le32_to_cpu(stat_info->rmac_discarded_frms);
d44570e4
JP		 6429 tmp_stats[i++] =
6430 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
6431 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
6432 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
6433 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
541ae68f
K		 6434 tmp_stats[i++] =
6435 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
6436 le32_to_cpu(stat_info->rmac_usized_frms);
6437 tmp_stats[i++] =
6438 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
6439 le32_to_cpu(stat_info->rmac_osized_frms);
6440 tmp_stats[i++] =
6441 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
6442 le32_to_cpu(stat_info->rmac_frag_frms);
6443 tmp_stats[i++] =
6444 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
6445 le32_to_cpu(stat_info->rmac_jabber_frms);
bd1034f0 6446 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
d44570e4
JP		 6447 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
6448 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
6449 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
6450 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
6451 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
bd1034f0
AR		 6452 tmp_stats[i++] =
6453 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
541ae68f 6454 le32_to_cpu(stat_info->rmac_ip);
1da177e4
LT		 6455 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
6456 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
bd1034f0
AR		 6457 tmp_stats[i++] =
6458 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
541ae68f 6459 le32_to_cpu(stat_info->rmac_drop_ip);
bd1034f0
AR		 6460 tmp_stats[i++] =
6461 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
541ae68f 6462 le32_to_cpu(stat_info->rmac_icmp);
1da177e4 6463 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
bd1034f0
AR		 6464 tmp_stats[i++] =
6465 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
541ae68f
K		 6466 le32_to_cpu(stat_info->rmac_udp);
6467 tmp_stats[i++] =
6468 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
6469 le32_to_cpu(stat_info->rmac_err_drp_udp);
bd1034f0 6470 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
d44570e4
JP		 6471 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
6472 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
6473 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
6474 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
6475 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
6476 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
6477 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
6478 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
6479 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
6480 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
6481 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
6482 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
6483 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
6484 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
6485 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
6486 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
541ae68f
K		 6487 tmp_stats[i++] =
6488 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
6489 le32_to_cpu(stat_info->rmac_pause_cnt);
bd1034f0 6490 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
d44570e4 6491 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
541ae68f
K		 6492 tmp_stats[i++] =
6493 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
6494 le32_to_cpu(stat_info->rmac_accepted_ip);
1da177e4 6495 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
bd1034f0
AR		 6496 tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
6497 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
6498 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
6499 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
6500 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
6501 tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
6502 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
6503 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
6504 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
6505 tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
6506 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
6507 tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
6508 tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
6509 tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
6510 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
6511 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
6512 tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
6513 tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
fa1f0cb3
SS		 6514
6515 /* Enhanced statistics exist only for Hercules */
d44570e4 6516 if (sp->device_type == XFRAME_II_DEVICE) {
fa1f0cb3 6517 tmp_stats[i++] =
d44570e4 6518 le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
fa1f0cb3 6519 tmp_stats[i++] =
d44570e4 6520 le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
fa1f0cb3 6521 tmp_stats[i++] =
d44570e4 6522 le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
fa1f0cb3
SS		 6523 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
6524 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
6525 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
6526 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
6527 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
6528 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
6529 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
6530 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
6531 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
6532 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
6533 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
6534 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
6535 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
6536 }
6537
7ba013ac
K		 6538 tmp_stats[i++] = 0;
6539 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
6540 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
bd1034f0
AR		 6541 tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
6542 tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
6543 tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
6544 tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
8116f3cf
SS		 6545 for (k = 0; k < MAX_RX_RINGS; k++)
6546 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt[k];
bd1034f0
AR		 6547 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
6548 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
6549 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
6550 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
6551 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
6552 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
6553 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
6554 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
6555 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
6556 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
6557 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
6558 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
7d3d0439
RA		 6559 tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
6560 tmp_stats[i++] = stat_info->sw_stat.sending_both;
6561 tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
6562 tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
fe931395 6563 if (stat_info->sw_stat.num_aggregations) {
bd1034f0
AR		 6564 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
6565 int count = 0;
6aa20a22 6566 /*
bd1034f0
AR		 6567 * Since 64-bit divide does not work on all platforms,
6568 * do repeated subtraction.
6569 */
6570 while (tmp >= stat_info->sw_stat.num_aggregations) {
6571 tmp -= stat_info->sw_stat.num_aggregations;
6572 count++;
6573 }
6574 tmp_stats[i++] = count;
d44570e4 6575 } else
bd1034f0 6576 tmp_stats[i++] = 0;
c53d4945 6577 tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt;
491abf25 6578 tmp_stats[i++] = stat_info->sw_stat.pci_map_fail_cnt;
c53d4945 6579 tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt;
491976b2
SH		 6580 tmp_stats[i++] = stat_info->sw_stat.mem_allocated;
6581 tmp_stats[i++] = stat_info->sw_stat.mem_freed;
6582 tmp_stats[i++] = stat_info->sw_stat.link_up_cnt;
6583 tmp_stats[i++] = stat_info->sw_stat.link_down_cnt;
6584 tmp_stats[i++] = stat_info->sw_stat.link_up_time;
6585 tmp_stats[i++] = stat_info->sw_stat.link_down_time;
6586
6587 tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt;
6588 tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt;
6589 tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt;
6590 tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt;
6591 tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt;
6592
6593 tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt;
6594 tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt;
6595 tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt;
6596 tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt;
6597 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt;
6598 tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt;
6599 tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt;
6600 tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt;
6601 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt;
8116f3cf
SS		 6602 tmp_stats[i++] = stat_info->sw_stat.tda_err_cnt;
6603 tmp_stats[i++] = stat_info->sw_stat.pfc_err_cnt;
6604 tmp_stats[i++] = stat_info->sw_stat.pcc_err_cnt;
6605 tmp_stats[i++] = stat_info->sw_stat.tti_err_cnt;
6606 tmp_stats[i++] = stat_info->sw_stat.tpa_err_cnt;
6607 tmp_stats[i++] = stat_info->sw_stat.sm_err_cnt;
6608 tmp_stats[i++] = stat_info->sw_stat.lso_err_cnt;
6609 tmp_stats[i++] = stat_info->sw_stat.mac_tmac_err_cnt;
6610 tmp_stats[i++] = stat_info->sw_stat.mac_rmac_err_cnt;
6611 tmp_stats[i++] = stat_info->sw_stat.xgxs_txgxs_err_cnt;
6612 tmp_stats[i++] = stat_info->sw_stat.xgxs_rxgxs_err_cnt;
6613 tmp_stats[i++] = stat_info->sw_stat.rc_err_cnt;
6614 tmp_stats[i++] = stat_info->sw_stat.prc_pcix_err_cnt;
6615 tmp_stats[i++] = stat_info->sw_stat.rpa_err_cnt;
6616 tmp_stats[i++] = stat_info->sw_stat.rda_err_cnt;
6617 tmp_stats[i++] = stat_info->sw_stat.rti_err_cnt;
6618 tmp_stats[i++] = stat_info->sw_stat.mc_err_cnt;
1da177e4
LT		 6619}
6620
ac1f60db 6621static int s2io_ethtool_get_regs_len(struct net_device *dev)
1da177e4 6622{
d44570e4 6623 return XENA_REG_SPACE;
1da177e4
LT		 6624}
6625
6626
d44570e4 6627static u32 s2io_ethtool_get_rx_csum(struct net_device *dev)
1da177e4 6628{
4cf1653a 6629 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 6630
d44570e4 6631 return sp->rx_csum;
1da177e4 6632}
ac1f60db
AB		 6633
6634static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
1da177e4 6635{
4cf1653a 6636 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 6637
6638 if (data)
6639 sp->rx_csum = 1;
6640 else
6641 sp->rx_csum = 0;
6642
6643 return 0;
6644}
ac1f60db
AB		 6645
6646static int s2io_get_eeprom_len(struct net_device *dev)
1da177e4 6647{
d44570e4 6648 return XENA_EEPROM_SPACE;
1da177e4
LT		 6649}
6650
b9f2c044 6651static int s2io_get_sset_count(struct net_device *dev, int sset)
1da177e4 6652{
4cf1653a 6653 struct s2io_nic *sp = netdev_priv(dev);
b9f2c044
JG		 6654
6655 switch (sset) {
6656 case ETH_SS_TEST:
6657 return S2IO_TEST_LEN;
6658 case ETH_SS_STATS:
d44570e4 6659 switch (sp->device_type) {
b9f2c044
JG		 6660 case XFRAME_I_DEVICE:
6661 return XFRAME_I_STAT_LEN;
6662 case XFRAME_II_DEVICE:
6663 return XFRAME_II_STAT_LEN;
6664 default:
6665 return 0;
6666 }
6667 default:
6668 return -EOPNOTSUPP;
6669 }
1da177e4 6670}
ac1f60db
AB		 6671
6672static void s2io_ethtool_get_strings(struct net_device *dev,
d44570e4 6673 u32 stringset, u8 *data)
1da177e4 6674{
fa1f0cb3 6675 int stat_size = 0;
4cf1653a 6676 struct s2io_nic *sp = netdev_priv(dev);
fa1f0cb3 6677
1da177e4
LT		 6678 switch (stringset) {
6679 case ETH_SS_TEST:
6680 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6681 break;
6682 case ETH_SS_STATS:
fa1f0cb3 6683 stat_size = sizeof(ethtool_xena_stats_keys);
d44570e4
JP		 6684 memcpy(data, &ethtool_xena_stats_keys, stat_size);
6685 if (sp->device_type == XFRAME_II_DEVICE) {
fa1f0cb3 6686 memcpy(data + stat_size,
d44570e4
JP		 6687 &ethtool_enhanced_stats_keys,
6688 sizeof(ethtool_enhanced_stats_keys));
fa1f0cb3
SS		 6689 stat_size += sizeof(ethtool_enhanced_stats_keys);
6690 }
6691
6692 memcpy(data + stat_size, &ethtool_driver_stats_keys,
d44570e4 6693 sizeof(ethtool_driver_stats_keys));
1da177e4
LT		 6694 }
6695}
1da177e4 6696
ac1f60db 6697static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
1da177e4
LT		 6698{
6699 if (data)
6700 dev->features |= NETIF_F_IP_CSUM;
6701 else
6702 dev->features &= ~NETIF_F_IP_CSUM;
6703
6704 return 0;
6705}
6706
75c30b13
AR		 6707static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6708{
6709 return (dev->features & NETIF_F_TSO) != 0;
6710}
6711static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6712{
6713 if (data)
6714 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6715 else
6716 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6717
6718 return 0;
6719}
1da177e4 6720
7282d491 6721static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 6722 .get_settings = s2io_ethtool_gset,
6723 .set_settings = s2io_ethtool_sset,
6724 .get_drvinfo = s2io_ethtool_gdrvinfo,
6725 .get_regs_len = s2io_ethtool_get_regs_len,
6726 .get_regs = s2io_ethtool_gregs,
6727 .get_link = ethtool_op_get_link,
6728 .get_eeprom_len = s2io_get_eeprom_len,
6729 .get_eeprom = s2io_ethtool_geeprom,
6730 .set_eeprom = s2io_ethtool_seeprom,
0cec35eb 6731 .get_ringparam = s2io_ethtool_gringparam,
1da177e4
LT		 6732 .get_pauseparam = s2io_ethtool_getpause_data,
6733 .set_pauseparam = s2io_ethtool_setpause_data,
6734 .get_rx_csum = s2io_ethtool_get_rx_csum,
6735 .set_rx_csum = s2io_ethtool_set_rx_csum,
1da177e4 6736 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
1da177e4 6737 .set_sg = ethtool_op_set_sg,
75c30b13
AR		 6738 .get_tso = s2io_ethtool_op_get_tso,
6739 .set_tso = s2io_ethtool_op_set_tso,
fed5eccd 6740 .set_ufo = ethtool_op_set_ufo,
1da177e4
LT		 6741 .self_test = s2io_ethtool_test,
6742 .get_strings = s2io_ethtool_get_strings,
6743 .phys_id = s2io_ethtool_idnic,
b9f2c044
JG		 6744 .get_ethtool_stats = s2io_get_ethtool_stats,
6745 .get_sset_count = s2io_get_sset_count,
1da177e4
LT		 6746};
6747
6748/**
20346722 6749 * s2io_ioctl - Entry point for the Ioctl
1da177e4
LT		 6750 * @dev : Device pointer.
6751 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6752 * a proprietary structure used to pass information to the driver.
6753 * @cmd : This is used to distinguish between the different commands that
6754 * can be passed to the IOCTL functions.
6755 * Description:
20346722
K		 6756 * Currently there are no special functionality supported in IOCTL, hence
6757 * function always return EOPNOTSUPPORTED
1da177e4
LT		 6758 */
6759
ac1f60db 6760static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1da177e4
LT		 6761{
6762 return -EOPNOTSUPP;
6763}
6764
6765/**
6766 * s2io_change_mtu - entry point to change MTU size for the device.
6767 * @dev : device pointer.
6768 * @new_mtu : the new MTU size for the device.
6769 * Description: A driver entry point to change MTU size for the device.
6770 * Before changing the MTU the device must be stopped.
6771 * Return value:
6772 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6773 * file on failure.
6774 */
6775
ac1f60db 6776static int s2io_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 6777{
4cf1653a 6778 struct s2io_nic *sp = netdev_priv(dev);
9f74ffde 6779 int ret = 0;
1da177e4
LT		 6780
6781 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
d44570e4 6782 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", dev->name);
1da177e4
LT		 6783 return -EPERM;
6784 }
6785
1da177e4 6786 dev->mtu = new_mtu;
d8892c6e 6787 if (netif_running(dev)) {
3a3d5756 6788 s2io_stop_all_tx_queue(sp);
e6a8fee2 6789 s2io_card_down(sp);
9f74ffde
SH		 6790 ret = s2io_card_up(sp);
6791 if (ret) {
d8892c6e 6792 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
b39d66a8 6793 __func__);
9f74ffde 6794 return ret;
d8892c6e 6795 }
3a3d5756 6796 s2io_wake_all_tx_queue(sp);
d8892c6e 6797 } else { /* Device is down */
1ee6dd77 6798 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d8892c6e
K		 6799 u64 val64 = new_mtu;
6800
6801 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6802 }
1da177e4 6803
9f74ffde 6804 return ret;
1da177e4
LT		 6805}
6806
1da177e4
LT		 6807/**
6808 * s2io_set_link - Set the LInk status
6809 * @data: long pointer to device private structue
6810 * Description: Sets the link status for the adapter
6811 */
6812
c4028958 6813static void s2io_set_link(struct work_struct *work)
1da177e4 6814{
d44570e4
JP		 6815 struct s2io_nic *nic = container_of(work, struct s2io_nic,
6816 set_link_task);
1da177e4 6817 struct net_device *dev = nic->dev;
1ee6dd77 6818 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 6819 register u64 val64;
6820 u16 subid;
6821
22747d6b
FR		 6822 rtnl_lock();
6823
6824 if (!netif_running(dev))
6825 goto out_unlock;
6826
92b84437 6827 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
1da177e4 6828 /* The card is being reset, no point doing anything */
22747d6b 6829 goto out_unlock;
1da177e4
LT		 6830 }
6831
6832 subid = nic->pdev->subsystem_device;
a371a07d
K		 6833 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6834 /*
6835 * Allow a small delay for the NICs self initiated
6836 * cleanup to complete.
6837 */
6838 msleep(100);
6839 }
1da177e4
LT		 6840
6841 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6842 if (LINK_IS_UP(val64)) {
6843 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6844 if (verify_xena_quiescence(nic)) {
6845 val64 = readq(&bar0->adapter_control);
6846 val64 |= ADAPTER_CNTL_EN;
1da177e4 6847 writeq(val64, &bar0->adapter_control);
19a60522 6848 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
d44570e4 6849 nic->device_type, subid)) {
19a60522
SS		 6850 val64 = readq(&bar0->gpio_control);
6851 val64 |= GPIO_CTRL_GPIO_0;
6852 writeq(val64, &bar0->gpio_control);
6853 val64 = readq(&bar0->gpio_control);
6854 } else {
6855 val64 |= ADAPTER_LED_ON;
6856 writeq(val64, &bar0->adapter_control);
a371a07d 6857 }
f957bcf0 6858 nic->device_enabled_once = true;
19a60522
SS		 6859 } else {
6860 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6861 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
3a3d5756 6862 s2io_stop_all_tx_queue(nic);
1da177e4 6863 }
19a60522 6864 }
92c48799
SS		 6865 val64 = readq(&bar0->adapter_control);
6866 val64 |= ADAPTER_LED_ON;
6867 writeq(val64, &bar0->adapter_control);
6868 s2io_link(nic, LINK_UP);
19a60522
SS		 6869 } else {
6870 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6871 subid)) {
6872 val64 = readq(&bar0->gpio_control);
6873 val64 &= ~GPIO_CTRL_GPIO_0;
6874 writeq(val64, &bar0->gpio_control);
6875 val64 = readq(&bar0->gpio_control);
1da177e4 6876 }
92c48799
SS		 6877 /* turn off LED */
6878 val64 = readq(&bar0->adapter_control);
d44570e4 6879 val64 = val64 & (~ADAPTER_LED_ON);
92c48799 6880 writeq(val64, &bar0->adapter_control);
19a60522 6881 s2io_link(nic, LINK_DOWN);
1da177e4 6882 }
92b84437 6883 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
22747d6b
FR		 6884
6885out_unlock:
d8d70caf 6886 rtnl_unlock();
1da177e4
LT		 6887}
6888
1ee6dd77 6889static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
d44570e4
JP		 6890 struct buffAdd *ba,
6891 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6892 u64 *temp2, int size)
5d3213cc
AR		 6893{
6894 struct net_device *dev = sp->dev;
491abf25 6895 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
5d3213cc
AR		 6896
6897 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6d517a27 6898 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
5d3213cc
AR		 6899 /* allocate skb */
6900 if (*skb) {
6901 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6902 /*
6903 * As Rx frame are not going to be processed,
6904 * using same mapped address for the Rxd
6905 * buffer pointer
6906 */
6d517a27 6907 rxdp1->Buffer0_ptr = *temp0;
5d3213cc
AR		 6908 } else {
6909 *skb = dev_alloc_skb(size);
6910 if (!(*skb)) {
0c61ed5f 6911 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
c53d4945
SH		 6912 DBG_PRINT(INFO_DBG, "memory to allocate ");
6913 DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
d44570e4 6914 sp->mac_control.stats_info->sw_stat.
c53d4945 6915 mem_alloc_fail_cnt++;
5d3213cc
AR		 6916 return -ENOMEM ;
6917 }
8a4bdbaa 6918 sp->mac_control.stats_info->sw_stat.mem_allocated
491976b2 6919 += (*skb)->truesize;
5d3213cc
AR		 6920 /* storing the mapped addr in a temp variable
6921 * such it will be used for next rxd whose
6922 * Host Control is NULL
6923 */
6d517a27 6924 rxdp1->Buffer0_ptr = *temp0 =
d44570e4
JP		 6925 pci_map_single(sp->pdev, (*skb)->data,
6926 size - NET_IP_ALIGN,
6927 PCI_DMA_FROMDEVICE);
8d8bb39b 6928 if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
491abf25 6929 goto memalloc_failed;
5d3213cc
AR		 6930 rxdp->Host_Control = (unsigned long) (*skb);
6931 }
6932 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6d517a27 6933 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
5d3213cc
AR		 6934 /* Two buffer Mode */
6935 if (*skb) {
6d517a27
VP		 6936 rxdp3->Buffer2_ptr = *temp2;
6937 rxdp3->Buffer0_ptr = *temp0;
6938 rxdp3->Buffer1_ptr = *temp1;
5d3213cc
AR		 6939 } else {
6940 *skb = dev_alloc_skb(size);
2ceaac75 6941 if (!(*skb)) {
c53d4945
SH		 6942 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6943 DBG_PRINT(INFO_DBG, "memory to allocate ");
6944 DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
d44570e4 6945 sp->mac_control.stats_info->sw_stat.
c53d4945 6946 mem_alloc_fail_cnt++;
2ceaac75
DR		 6947 return -ENOMEM;
6948 }
8a4bdbaa 6949 sp->mac_control.stats_info->sw_stat.mem_allocated
491976b2 6950 += (*skb)->truesize;
6d517a27 6951 rxdp3->Buffer2_ptr = *temp2 =
5d3213cc
AR		 6952 pci_map_single(sp->pdev, (*skb)->data,
6953 dev->mtu + 4,
6954 PCI_DMA_FROMDEVICE);
8d8bb39b 6955 if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
491abf25 6956 goto memalloc_failed;
6d517a27 6957 rxdp3->Buffer0_ptr = *temp0 =
d44570e4
JP		 6958 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6959 PCI_DMA_FROMDEVICE);
8d8bb39b 6960 if (pci_dma_mapping_error(sp->pdev,
d44570e4
JP		 6961 rxdp3->Buffer0_ptr)) {
6962 pci_unmap_single(sp->pdev,
6963 (dma_addr_t)rxdp3->Buffer2_ptr,
6964 dev->mtu + 4,
6965 PCI_DMA_FROMDEVICE);
491abf25
VP		 6966 goto memalloc_failed;
6967 }
5d3213cc
AR		 6968 rxdp->Host_Control = (unsigned long) (*skb);
6969
6970 /* Buffer-1 will be dummy buffer not used */
6d517a27 6971 rxdp3->Buffer1_ptr = *temp1 =
5d3213cc 6972 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
d44570e4 6973 PCI_DMA_FROMDEVICE);
8d8bb39b 6974 if (pci_dma_mapping_error(sp->pdev,
d44570e4
JP		 6975 rxdp3->Buffer1_ptr)) {
6976 pci_unmap_single(sp->pdev,
6977 (dma_addr_t)rxdp3->Buffer0_ptr,
6978 BUF0_LEN, PCI_DMA_FROMDEVICE);
6979 pci_unmap_single(sp->pdev,
6980 (dma_addr_t)rxdp3->Buffer2_ptr,
6981 dev->mtu + 4,
6982 PCI_DMA_FROMDEVICE);
491abf25
VP		 6983 goto memalloc_failed;
6984 }
5d3213cc
AR		 6985 }
6986 }
6987 return 0;
d44570e4
JP		 6988
6989memalloc_failed:
6990 stats->pci_map_fail_cnt++;
6991 stats->mem_freed += (*skb)->truesize;
6992 dev_kfree_skb(*skb);
6993 return -ENOMEM;
5d3213cc 6994}
491abf25 6995
1ee6dd77
RB		 6996static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6997 int size)
5d3213cc
AR		 6998{
6999 struct net_device *dev = sp->dev;
7000 if (sp->rxd_mode == RXD_MODE_1) {
d44570e4 7001 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
5d3213cc
AR		 7002 } else if (sp->rxd_mode == RXD_MODE_3B) {
7003 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
7004 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
d44570e4 7005 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu + 4);
5d3213cc
AR		 7006 }
7007}
7008
1ee6dd77 7009static int rxd_owner_bit_reset(struct s2io_nic *sp)
5d3213cc
AR		 7010{
7011 int i, j, k, blk_cnt = 0, size;
d44570e4 7012 struct mac_info *mac_control = &sp->mac_control;
5d3213cc
AR		 7013 struct config_param *config = &sp->config;
7014 struct net_device *dev = sp->dev;
1ee6dd77 7015 struct RxD_t *rxdp = NULL;
5d3213cc 7016 struct sk_buff *skb = NULL;
1ee6dd77 7017 struct buffAdd *ba = NULL;
5d3213cc
AR		 7018 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
7019
7020 /* Calculate the size based on ring mode */
7021 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
7022 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
7023 if (sp->rxd_mode == RXD_MODE_1)
7024 size += NET_IP_ALIGN;
7025 else if (sp->rxd_mode == RXD_MODE_3B)
7026 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
5d3213cc
AR		 7027
7028 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7029 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7030 struct ring_info *ring = &mac_control->rings[i];
7031
d44570e4 7032 blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] + 1);
5d3213cc
AR		 7033
7034 for (j = 0; j < blk_cnt; j++) {
7035 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
d44570e4
JP		 7036 rxdp = ring->rx_blocks[j].rxds[k].virt_addr;
7037 if (sp->rxd_mode == RXD_MODE_3B)
13d866a9 7038 ba = &ring->ba[j][k];
d44570e4
JP		 7039 if (set_rxd_buffer_pointer(sp, rxdp, ba, &skb,
7040 (u64 *)&temp0_64,
7041 (u64 *)&temp1_64,
7042 (u64 *)&temp2_64,
7043 size) == -ENOMEM) {
ac1f90d6
SS		 7044 return 0;
7045 }
5d3213cc
AR		 7046
7047 set_rxd_buffer_size(sp, rxdp, size);
7048 wmb();
7049 /* flip the Ownership bit to Hardware */
7050 rxdp->Control_1 |= RXD_OWN_XENA;
7051 }
7052 }
7053 }
7054 return 0;
7055
7056}
7057
d44570e4 7058static int s2io_add_isr(struct s2io_nic *sp)
1da177e4 7059{
e6a8fee2 7060 int ret = 0;
c92ca04b 7061 struct net_device *dev = sp->dev;
e6a8fee2 7062 int err = 0;
1da177e4 7063
eaae7f72 7064 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7065 ret = s2io_enable_msi_x(sp);
7066 if (ret) {
7067 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
eaae7f72 7068 sp->config.intr_type = INTA;
20346722 7069 }
1da177e4 7070
d44570e4
JP		 7071 /*
7072 * Store the values of the MSIX table in
7073 * the struct s2io_nic structure
7074 */
e6a8fee2 7075 store_xmsi_data(sp);
c92ca04b 7076
e6a8fee2 7077 /* After proper initialization of H/W, register ISR */
eaae7f72 7078 if (sp->config.intr_type == MSI_X) {
ac731ab6
SH		 7079 int i, msix_rx_cnt = 0;
7080
f61e0a35
SH		 7081 for (i = 0; i < sp->num_entries; i++) {
7082 if (sp->s2io_entries[i].in_use == MSIX_FLG) {
7083 if (sp->s2io_entries[i].type ==
d44570e4 7084 MSIX_RING_TYPE) {
ac731ab6
SH		 7085 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7086 dev->name, i);
7087 err = request_irq(sp->entries[i].vector,
d44570e4
JP		 7088 s2io_msix_ring_handle,
7089 0,
7090 sp->desc[i],
7091 sp->s2io_entries[i].arg);
ac731ab6 7092 } else if (sp->s2io_entries[i].type ==
d44570e4 7093 MSIX_ALARM_TYPE) {
ac731ab6 7094 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
d44570e4 7095 dev->name, i);
ac731ab6 7096 err = request_irq(sp->entries[i].vector,
d44570e4
JP		 7097 s2io_msix_fifo_handle,
7098 0,
7099 sp->desc[i],
7100 sp->s2io_entries[i].arg);
ac731ab6 7101
fb6a825b 7102 }
ac731ab6
SH		 7103 /* if either data or addr is zero print it. */
7104 if (!(sp->msix_info[i].addr &&
d44570e4 7105 sp->msix_info[i].data)) {
ac731ab6 7106 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7107 "%s @Addr:0x%llx Data:0x%llx\n",
7108 sp->desc[i],
7109 (unsigned long long)
7110 sp->msix_info[i].addr,
7111 (unsigned long long)
7112 ntohl(sp->msix_info[i].data));
ac731ab6 7113 } else
fb6a825b 7114 msix_rx_cnt++;
ac731ab6
SH		 7115 if (err) {
7116 remove_msix_isr(sp);
7117
7118 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7119 "%s:MSI-X-%d registration "
7120 "failed\n", dev->name, i);
ac731ab6
SH		 7121
7122 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7123 "%s: Defaulting to INTA\n",
7124 dev->name);
ac731ab6
SH		 7125 sp->config.intr_type = INTA;
7126 break;
fb6a825b 7127 }
ac731ab6
SH		 7128 sp->s2io_entries[i].in_use =
7129 MSIX_REGISTERED_SUCCESS;
c92ca04b 7130 }
e6a8fee2 7131 }
18b2b7bd 7132 if (!err) {
18b2b7bd 7133 printk(KERN_INFO "MSI-X-RX %d entries enabled\n",
d44570e4 7134 --msix_rx_cnt);
ac731ab6 7135 DBG_PRINT(INFO_DBG, "MSI-X-TX entries enabled"
d44570e4 7136 " through alarm vector\n");
18b2b7bd 7137 }
e6a8fee2 7138 }
eaae7f72 7139 if (sp->config.intr_type == INTA) {
d44570e4
JP		 7140 err = request_irq((int)sp->pdev->irq, s2io_isr, IRQF_SHARED,
7141 sp->name, dev);
e6a8fee2
AR		 7142 if (err) {
7143 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7144 dev->name);
7145 return -1;
7146 }
7147 }
7148 return 0;
7149}
d44570e4
JP		 7150
7151static void s2io_rem_isr(struct s2io_nic *sp)
e6a8fee2 7152{
18b2b7bd
SH		 7153 if (sp->config.intr_type == MSI_X)
7154 remove_msix_isr(sp);
7155 else
7156 remove_inta_isr(sp);
e6a8fee2
AR		 7157}
7158
d44570e4 7159static void do_s2io_card_down(struct s2io_nic *sp, int do_io)
e6a8fee2
AR		 7160{
7161 int cnt = 0;
1ee6dd77 7162 struct XENA_dev_config __iomem *bar0 = sp->bar0;
e6a8fee2 7163 register u64 val64 = 0;
5f490c96
SH		 7164 struct config_param *config;
7165 config = &sp->config;
e6a8fee2 7166
9f74ffde
SH		 7167 if (!is_s2io_card_up(sp))
7168 return;
7169
e6a8fee2
AR		 7170 del_timer_sync(&sp->alarm_timer);
7171 /* If s2io_set_link task is executing, wait till it completes. */
d44570e4 7172 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state)))
e6a8fee2 7173 msleep(50);
92b84437 7174 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
e6a8fee2 7175
5f490c96 7176 /* Disable napi */
f61e0a35
SH		 7177 if (sp->config.napi) {
7178 int off = 0;
7179 if (config->intr_type == MSI_X) {
7180 for (; off < sp->config.rx_ring_num; off++)
7181 napi_disable(&sp->mac_control.rings[off].napi);
d44570e4 7182 }
f61e0a35
SH		 7183 else
7184 napi_disable(&sp->napi);
7185 }
5f490c96 7186
e6a8fee2 7187 /* disable Tx and Rx traffic on the NIC */
d796fdb7
LV		 7188 if (do_io)
7189 stop_nic(sp);
e6a8fee2
AR		 7190
7191 s2io_rem_isr(sp);
1da177e4 7192
01e16faa
SH		 7193 /* stop the tx queue, indicate link down */
7194 s2io_link(sp, LINK_DOWN);
7195
1da177e4 7196 /* Check if the device is Quiescent and then Reset the NIC */
d44570e4 7197 while (do_io) {
5d3213cc
AR		 7198 /* As per the HW requirement we need to replenish the
7199 * receive buffer to avoid the ring bump. Since there is
7200 * no intention of processing the Rx frame at this pointwe are
7201 * just settting the ownership bit of rxd in Each Rx
7202 * ring to HW and set the appropriate buffer size
7203 * based on the ring mode
7204 */
7205 rxd_owner_bit_reset(sp);
7206
1da177e4 7207 val64 = readq(&bar0->adapter_status);
19a60522 7208 if (verify_xena_quiescence(sp)) {
d44570e4
JP		 7209 if (verify_pcc_quiescent(sp, sp->device_enabled_once))
7210 break;
1da177e4
LT		 7211 }
7212
7213 msleep(50);
7214 cnt++;
7215 if (cnt == 10) {
d44570e4 7216 DBG_PRINT(ERR_DBG, "s2io_close:Device not Quiescent ");
1da177e4 7217 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
d44570e4 7218 (unsigned long long)val64);
1da177e4
LT		 7219 break;
7220 }
d796fdb7
LV		 7221 }
7222 if (do_io)
7223 s2io_reset(sp);
1da177e4 7224
7ba013ac 7225 /* Free all Tx buffers */
1da177e4 7226 free_tx_buffers(sp);
7ba013ac
K		 7227
7228 /* Free all Rx buffers */
1da177e4
LT		 7229 free_rx_buffers(sp);
7230
92b84437 7231 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
1da177e4
LT		 7232}
7233
d44570e4 7234static void s2io_card_down(struct s2io_nic *sp)
d796fdb7
LV		 7235{
7236 do_s2io_card_down(sp, 1);
7237}
7238
d44570e4 7239static int s2io_card_up(struct s2io_nic *sp)
1da177e4 7240{
cc6e7c44 7241 int i, ret = 0;
1ee6dd77 7242 struct mac_info *mac_control;
1da177e4 7243 struct config_param *config;
d44570e4 7244 struct net_device *dev = (struct net_device *)sp->dev;
e6a8fee2 7245 u16 interruptible;
1da177e4
LT		 7246
7247 /* Initialize the H/W I/O registers */
9f74ffde
SH		 7248 ret = init_nic(sp);
7249 if (ret != 0) {
1da177e4
LT		 7250 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7251 dev->name);
9f74ffde
SH		 7252 if (ret != -EIO)
7253 s2io_reset(sp);
7254 return ret;
1da177e4
LT		 7255 }
7256
20346722
K		 7257 /*
7258 * Initializing the Rx buffers. For now we are considering only 1
1da177e4
LT		 7259 * Rx ring and initializing buffers into 30 Rx blocks
7260 */
7261 mac_control = &sp->mac_control;
7262 config = &sp->config;
7263
7264 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7265 struct ring_info *ring = &mac_control->rings[i];
7266
7267 ring->mtu = dev->mtu;
7268 ret = fill_rx_buffers(sp, ring, 1);
0425b46a 7269 if (ret) {
1da177e4
LT		 7270 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7271 dev->name);
7272 s2io_reset(sp);
7273 free_rx_buffers(sp);
7274 return -ENOMEM;
7275 }
7276 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
13d866a9 7277 ring->rx_bufs_left);
1da177e4 7278 }
5f490c96
SH		 7279
7280 /* Initialise napi */
f61e0a35 7281 if (config->napi) {
f61e0a35
SH		 7282 if (config->intr_type == MSI_X) {
7283 for (i = 0; i < sp->config.rx_ring_num; i++)
7284 napi_enable(&sp->mac_control.rings[i].napi);
7285 } else {
7286 napi_enable(&sp->napi);
7287 }
7288 }
5f490c96 7289
19a60522
SS		 7290 /* Maintain the state prior to the open */
7291 if (sp->promisc_flg)
7292 sp->promisc_flg = 0;
7293 if (sp->m_cast_flg) {
7294 sp->m_cast_flg = 0;
d44570e4 7295 sp->all_multi_pos = 0;
19a60522 7296 }
1da177e4
LT		 7297
7298 /* Setting its receive mode */
7299 s2io_set_multicast(dev);
7300
7d3d0439 7301 if (sp->lro) {
b41477f3 7302 /* Initialize max aggregatable pkts per session based on MTU */
7d3d0439 7303 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
d44570e4 7304 /* Check if we can use (if specified) user provided value */
7d3d0439
RA		 7305 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7306 sp->lro_max_aggr_per_sess = lro_max_pkts;
7307 }
7308
1da177e4
LT		 7309 /* Enable Rx Traffic and interrupts on the NIC */
7310 if (start_nic(sp)) {
7311 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
1da177e4 7312 s2io_reset(sp);
e6a8fee2
AR		 7313 free_rx_buffers(sp);
7314 return -ENODEV;
7315 }
7316
7317 /* Add interrupt service routine */
7318 if (s2io_add_isr(sp) != 0) {
eaae7f72 7319 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7320 s2io_rem_isr(sp);
7321 s2io_reset(sp);
1da177e4
LT		 7322 free_rx_buffers(sp);
7323 return -ENODEV;
7324 }
7325
25fff88e
K		 7326 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7327
01e16faa
SH		 7328 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7329
e6a8fee2 7330 /* Enable select interrupts */
9caab458 7331 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
01e16faa
SH		 7332 if (sp->config.intr_type != INTA) {
7333 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7334 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7335 } else {
e6a8fee2 7336 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 7337 interruptible |= TX_PIC_INTR;
e6a8fee2
AR		 7338 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7339 }
7340
1da177e4
LT		 7341 return 0;
7342}
7343
20346722 7344/**
1da177e4
LT		 7345 * s2io_restart_nic - Resets the NIC.
7346 * @data : long pointer to the device private structure
7347 * Description:
7348 * This function is scheduled to be run by the s2io_tx_watchdog
20346722 7349 * function after 0.5 secs to reset the NIC. The idea is to reduce
1da177e4
LT		 7350 * the run time of the watch dog routine which is run holding a
7351 * spin lock.
7352 */
7353
c4028958 7354static void s2io_restart_nic(struct work_struct *work)
1da177e4 7355{
1ee6dd77 7356 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
c4028958 7357 struct net_device *dev = sp->dev;
1da177e4 7358
22747d6b
FR		 7359 rtnl_lock();
7360
7361 if (!netif_running(dev))
7362 goto out_unlock;
7363
e6a8fee2 7364 s2io_card_down(sp);
1da177e4 7365 if (s2io_card_up(sp)) {
d44570e4 7366 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", dev->name);
1da177e4 7367 }
3a3d5756 7368 s2io_wake_all_tx_queue(sp);
d44570e4 7369 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", dev->name);
22747d6b
FR		 7370out_unlock:
7371 rtnl_unlock();
1da177e4
LT		 7372}
7373
20346722
K		 7374/**
7375 * s2io_tx_watchdog - Watchdog for transmit side.
1da177e4
LT		 7376 * @dev : Pointer to net device structure
7377 * Description:
7378 * This function is triggered if the Tx Queue is stopped
7379 * for a pre-defined amount of time when the Interface is still up.
7380 * If the Interface is jammed in such a situation, the hardware is
7381 * reset (by s2io_close) and restarted again (by s2io_open) to
7382 * overcome any problem that might have been caused in the hardware.
7383 * Return value:
7384 * void
7385 */
7386
7387static void s2io_tx_watchdog(struct net_device *dev)
7388{
4cf1653a 7389 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 7390
7391 if (netif_carrier_ok(dev)) {
c53d4945 7392 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++;
1da177e4 7393 schedule_work(&sp->rst_timer_task);
bd1034f0 7394 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
1da177e4
LT		 7395 }
7396}
7397
7398/**
7399 * rx_osm_handler - To perform some OS related operations on SKB.
7400 * @sp: private member of the device structure,pointer to s2io_nic structure.
7401 * @skb : the socket buffer pointer.
7402 * @len : length of the packet
7403 * @cksum : FCS checksum of the frame.
7404 * @ring_no : the ring from which this RxD was extracted.
20346722 7405 * Description:
b41477f3 7406 * This function is called by the Rx interrupt serivce routine to perform
1da177e4
LT		 7407 * some OS related operations on the SKB before passing it to the upper
7408 * layers. It mainly checks if the checksum is OK, if so adds it to the
7409 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7410 * to the upper layer. If the checksum is wrong, it increments the Rx
7411 * packet error count, frees the SKB and returns error.
7412 * Return value:
7413 * SUCCESS on success and -1 on failure.
7414 */
1ee6dd77 7415static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
1da177e4 7416{
1ee6dd77 7417 struct s2io_nic *sp = ring_data->nic;
d44570e4 7418 struct net_device *dev = (struct net_device *)ring_data->dev;
20346722 7419 struct sk_buff *skb = (struct sk_buff *)
d44570e4 7420 ((unsigned long)rxdp->Host_Control);
20346722 7421 int ring_no = ring_data->ring_no;
1da177e4 7422 u16 l3_csum, l4_csum;
863c11a9 7423 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
2e6a684b 7424 struct lro *uninitialized_var(lro);
f9046eb3 7425 u8 err_mask;
da6971d8 7426
20346722 7427 skb->dev = dev;
c92ca04b 7428
863c11a9 7429 if (err) {
bd1034f0 7430 /* Check for parity error */
d44570e4 7431 if (err & 0x1)
bd1034f0 7432 sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
d44570e4 7433
f9046eb3 7434 err_mask = err >> 48;
d44570e4
JP		 7435 switch (err_mask) {
7436 case 1:
7437 sp->mac_control.stats_info->sw_stat.rx_parity_err_cnt++;
491976b2
SH		 7438 break;
7439
d44570e4
JP		 7440 case 2:
7441 sp->mac_control.stats_info->sw_stat.rx_abort_cnt++;
491976b2
SH		 7442 break;
7443
d44570e4
JP		 7444 case 3:
7445 sp->mac_control.stats_info->sw_stat.rx_parity_abort_cnt++;
491976b2
SH		 7446 break;
7447
d44570e4
JP		 7448 case 4:
7449 sp->mac_control.stats_info->sw_stat.rx_rda_fail_cnt++;
491976b2
SH		 7450 break;
7451
d44570e4
JP		 7452 case 5:
7453 sp->mac_control.stats_info->sw_stat.rx_unkn_prot_cnt++;
491976b2
SH		 7454 break;
7455
d44570e4
JP		 7456 case 6:
7457 sp->mac_control.stats_info->sw_stat.rx_fcs_err_cnt++;
491976b2 7458 break;
bd1034f0 7459
d44570e4
JP		 7460 case 7:
7461 sp->mac_control.stats_info->sw_stat.rx_buf_size_err_cnt++;
491976b2
SH		 7462 break;
7463
d44570e4
JP		 7464 case 8:
7465 sp->mac_control.stats_info->sw_stat.rx_rxd_corrupt_cnt++;
491976b2
SH		 7466 break;
7467
d44570e4
JP		 7468 case 15:
7469 sp->mac_control.stats_info->sw_stat.rx_unkn_err_cnt++;
491976b2
SH		 7470 break;
7471 }
863c11a9 7472 /*
d44570e4
JP		 7473 * Drop the packet if bad transfer code. Exception being
7474 * 0x5, which could be due to unsupported IPv6 extension header.
7475 * In this case, we let stack handle the packet.
7476 * Note that in this case, since checksum will be incorrect,
7477 * stack will validate the same.
7478 */
f9046eb3
OH		 7479 if (err_mask != 0x5) {
7480 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
d44570e4 7481 dev->name, err_mask);
dc56e634 7482 dev->stats.rx_crc_errors++;
8a4bdbaa 7483 sp->mac_control.stats_info->sw_stat.mem_freed
491976b2 7484 += skb->truesize;
863c11a9 7485 dev_kfree_skb(skb);
0425b46a 7486 ring_data->rx_bufs_left -= 1;
863c11a9
AR		 7487 rxdp->Host_Control = 0;
7488 return 0;
7489 }
20346722 7490 }
1da177e4 7491
20346722 7492 /* Updating statistics */
0425b46a 7493 ring_data->rx_packets++;
20346722 7494 rxdp->Host_Control = 0;
da6971d8
AR		 7495 if (sp->rxd_mode == RXD_MODE_1) {
7496 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
20346722 7497
0425b46a 7498 ring_data->rx_bytes += len;
da6971d8
AR		 7499 skb_put(skb, len);
7500
6d517a27 7501 } else if (sp->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 7502 int get_block = ring_data->rx_curr_get_info.block_index;
7503 int get_off = ring_data->rx_curr_get_info.offset;
7504 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7505 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7506 unsigned char *buff = skb_push(skb, buf0_len);
7507
1ee6dd77 7508 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
0425b46a 7509 ring_data->rx_bytes += buf0_len + buf2_len;
da6971d8 7510 memcpy(buff, ba->ba_0, buf0_len);
6d517a27 7511 skb_put(skb, buf2_len);
da6971d8 7512 }
20346722 7513
d44570e4
JP		 7514 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
7515 ((!ring_data->lro) ||
7516 (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
20346722
K		 7517 (sp->rx_csum)) {
7518 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
1da177e4
LT		 7519 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7520 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
20346722 7521 /*
1da177e4
LT		 7522 * NIC verifies if the Checksum of the received
7523 * frame is Ok or not and accordingly returns
7524 * a flag in the RxD.
7525 */
7526 skb->ip_summed = CHECKSUM_UNNECESSARY;
0425b46a 7527 if (ring_data->lro) {
7d3d0439
RA		 7528 u32 tcp_len;
7529 u8 *tcp;
7530 int ret = 0;
7531
0425b46a 7532 ret = s2io_club_tcp_session(ring_data,
d44570e4
JP		 7533 skb->data, &tcp,
7534 &tcp_len, &lro,
7535 rxdp, sp);
7d3d0439 7536 switch (ret) {
d44570e4
JP		 7537 case 3: /* Begin anew */
7538 lro->parent = skb;
7539 goto aggregate;
7540 case 1: /* Aggregate */
7541 lro_append_pkt(sp, lro, skb, tcp_len);
7542 goto aggregate;
7543 case 4: /* Flush session */
7544 lro_append_pkt(sp, lro, skb, tcp_len);
7545 queue_rx_frame(lro->parent,
7546 lro->vlan_tag);
7547 clear_lro_session(lro);
7548 sp->mac_control.stats_info->
7549 sw_stat.flush_max_pkts++;
7550 goto aggregate;
7551 case 2: /* Flush both */
7552 lro->parent->data_len = lro->frags_len;
7553 sp->mac_control.stats_info->
7554 sw_stat.sending_both++;
7555 queue_rx_frame(lro->parent,
7556 lro->vlan_tag);
7557 clear_lro_session(lro);
7558 goto send_up;
7559 case 0: /* sessions exceeded */
7560 case -1: /* non-TCP or not L2 aggregatable */
7561 case 5: /*
7562 * First pkt in session not
7563 * L3/L4 aggregatable
7564 */
7565 break;
7566 default:
7567 DBG_PRINT(ERR_DBG,
7568 "%s: Samadhana!!\n",
7569 __func__);
7570 BUG();
7d3d0439
RA		 7571 }
7572 }
1da177e4 7573 } else {
20346722
K		 7574 /*
7575 * Packet with erroneous checksum, let the
1da177e4
LT		 7576 * upper layers deal with it.
7577 */
7578 skb->ip_summed = CHECKSUM_NONE;
7579 }
cdb5bf02 7580 } else
1da177e4 7581 skb->ip_summed = CHECKSUM_NONE;
cdb5bf02 7582
491976b2 7583 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
7d3d0439 7584send_up:
0c8dfc83 7585 skb_record_rx_queue(skb, ring_no);
cdb5bf02 7586 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7d3d0439 7587aggregate:
0425b46a 7588 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
1da177e4
LT		 7589 return SUCCESS;
7590}
7591
7592/**
7593 * s2io_link - stops/starts the Tx queue.
7594 * @sp : private member of the device structure, which is a pointer to the
7595 * s2io_nic structure.
7596 * @link : inidicates whether link is UP/DOWN.
7597 * Description:
7598 * This function stops/starts the Tx queue depending on whether the link
20346722
K		 7599 * status of the NIC is is down or up. This is called by the Alarm
7600 * interrupt handler whenever a link change interrupt comes up.
1da177e4
LT		 7601 * Return value:
7602 * void.
7603 */
7604
d44570e4 7605static void s2io_link(struct s2io_nic *sp, int link)
1da177e4 7606{
d44570e4 7607 struct net_device *dev = (struct net_device *)sp->dev;
1da177e4
LT		 7608
7609 if (link != sp->last_link_state) {
b7c5678f 7610 init_tti(sp, link);
1da177e4
LT		 7611 if (link == LINK_DOWN) {
7612 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
3a3d5756 7613 s2io_stop_all_tx_queue(sp);
1da177e4 7614 netif_carrier_off(dev);
d44570e4
JP		 7615 if (sp->mac_control.stats_info->sw_stat.link_up_cnt)
7616 sp->mac_control.stats_info->sw_stat.
7617 link_up_time = jiffies - sp->start_time;
491976b2 7618 sp->mac_control.stats_info->sw_stat.link_down_cnt++;
1da177e4
LT		 7619 } else {
7620 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
491976b2 7621 if (sp->mac_control.stats_info->sw_stat.link_down_cnt)
d44570e4
JP		 7622 sp->mac_control.stats_info->
7623 sw_stat.link_down_time =
7624 jiffies - sp->start_time;
491976b2 7625 sp->mac_control.stats_info->sw_stat.link_up_cnt++;
1da177e4 7626 netif_carrier_on(dev);
3a3d5756 7627 s2io_wake_all_tx_queue(sp);
1da177e4
LT		 7628 }
7629 }
7630 sp->last_link_state = link;
491976b2 7631 sp->start_time = jiffies;
1da177e4
LT		 7632}
7633
20346722
K		 7634/**
7635 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7636 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 7637 * s2io_nic structure.
7638 * Description:
7639 * This function initializes a few of the PCI and PCI-X configuration registers
7640 * with recommended values.
7641 * Return value:
7642 * void
7643 */
7644
d44570e4 7645static void s2io_init_pci(struct s2io_nic *sp)
1da177e4 7646{
20346722 7647 u16 pci_cmd = 0, pcix_cmd = 0;
1da177e4
LT		 7648
7649 /* Enable Data Parity Error Recovery in PCI-X command register. */
7650 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7651 &(pcix_cmd));
1da177e4 7652 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7653 (pcix_cmd | 1));
1da177e4 7654 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7655 &(pcix_cmd));
1da177e4
LT		 7656
7657 /* Set the PErr Response bit in PCI command register. */
7658 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7659 pci_write_config_word(sp->pdev, PCI_COMMAND,
7660 (pci_cmd | PCI_COMMAND_PARITY));
7661 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
1da177e4
LT		 7662}
7663
3a3d5756 7664static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
d44570e4 7665 u8 *dev_multiq)
9dc737a7 7666{
d44570e4 7667 if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) {
2fda096d 7668 DBG_PRINT(ERR_DBG, "s2io: Requested number of tx fifos "
d44570e4 7669 "(%d) not supported\n", tx_fifo_num);
6cfc482b
SH		 7670
7671 if (tx_fifo_num < 1)
7672 tx_fifo_num = 1;
7673 else
7674 tx_fifo_num = MAX_TX_FIFOS;
7675
2fda096d
SR		 7676 DBG_PRINT(ERR_DBG, "s2io: Default to %d ", tx_fifo_num);
7677 DBG_PRINT(ERR_DBG, "tx fifos\n");
9dc737a7 7678 }
2fda096d 7679
6cfc482b 7680 if (multiq)
3a3d5756 7681 *dev_multiq = multiq;
6cfc482b
SH		 7682
7683 if (tx_steering_type && (1 == tx_fifo_num)) {
7684 if (tx_steering_type != TX_DEFAULT_STEERING)
7685 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7686 "s2io: Tx steering is not supported with "
7687 "one fifo. Disabling Tx steering.\n");
6cfc482b
SH		 7688 tx_steering_type = NO_STEERING;
7689 }
7690
7691 if ((tx_steering_type < NO_STEERING) ||
d44570e4
JP		 7692 (tx_steering_type > TX_DEFAULT_STEERING)) {
7693 DBG_PRINT(ERR_DBG,
7694 "s2io: Requested transmit steering not supported\n");
6cfc482b
SH		 7695 DBG_PRINT(ERR_DBG, "s2io: Disabling transmit steering\n");
7696 tx_steering_type = NO_STEERING;
3a3d5756
SH		 7697 }
7698
0425b46a 7699 if (rx_ring_num > MAX_RX_RINGS) {
d44570e4
JP		 7700 DBG_PRINT(ERR_DBG,
7701 "s2io: Requested number of rx rings not supported\n");
0425b46a 7702 DBG_PRINT(ERR_DBG, "s2io: Default to %d rx rings\n",
d44570e4 7703 MAX_RX_RINGS);
0425b46a 7704 rx_ring_num = MAX_RX_RINGS;
9dc737a7 7705 }
0425b46a 7706
eccb8628 7707 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
9dc737a7
AR		 7708 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
7709 "Defaulting to INTA\n");
7710 *dev_intr_type = INTA;
7711 }
596c5c97 7712
9dc737a7 7713 if ((*dev_intr_type == MSI_X) &&
d44570e4
JP		 7714 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7715 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
6aa20a22 7716 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
d44570e4 7717 "Defaulting to INTA\n");
9dc737a7
AR		 7718 *dev_intr_type = INTA;
7719 }
fb6a825b 7720
6d517a27 7721 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
9dc737a7 7722 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
6d517a27
VP		 7723 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 1-buffer mode\n");
7724 rx_ring_mode = 1;
9dc737a7
AR		 7725 }
7726 return SUCCESS;
7727}
7728
9fc93a41
SS		 7729/**
7730 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7731 * or Traffic class respectively.
b7c5678f 7732 * @nic: device private variable
9fc93a41
SS		 7733 * Description: The function configures the receive steering to
7734 * desired receive ring.
7735 * Return Value: SUCCESS on success and
7736 * '-1' on failure (endian settings incorrect).
7737 */
7738static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7739{
7740 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7741 register u64 val64 = 0;
7742
7743 if (ds_codepoint > 63)
7744 return FAILURE;
7745
7746 val64 = RTS_DS_MEM_DATA(ring);
7747 writeq(val64, &bar0->rts_ds_mem_data);
7748
7749 val64 = RTS_DS_MEM_CTRL_WE |
7750 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7751 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7752
7753 writeq(val64, &bar0->rts_ds_mem_ctrl);
7754
7755 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
d44570e4
JP		 7756 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7757 S2IO_BIT_RESET);
9fc93a41
SS		 7758}
7759
04025095
SH		 7760static const struct net_device_ops s2io_netdev_ops = {
7761 .ndo_open = s2io_open,
7762 .ndo_stop = s2io_close,
7763 .ndo_get_stats = s2io_get_stats,
7764 .ndo_start_xmit = s2io_xmit,
7765 .ndo_validate_addr = eth_validate_addr,
7766 .ndo_set_multicast_list = s2io_set_multicast,
7767 .ndo_do_ioctl = s2io_ioctl,
7768 .ndo_set_mac_address = s2io_set_mac_addr,
7769 .ndo_change_mtu = s2io_change_mtu,
7770 .ndo_vlan_rx_register = s2io_vlan_rx_register,
7771 .ndo_vlan_rx_kill_vid = s2io_vlan_rx_kill_vid,
7772 .ndo_tx_timeout = s2io_tx_watchdog,
7773#ifdef CONFIG_NET_POLL_CONTROLLER
7774 .ndo_poll_controller = s2io_netpoll,
7775#endif
7776};
7777
1da177e4 7778/**
20346722 7779 * s2io_init_nic - Initialization of the adapter .
1da177e4
LT		 7780 * @pdev : structure containing the PCI related information of the device.
7781 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7782 * Description:
7783 * The function initializes an adapter identified by the pci_dec structure.
20346722
K		 7784 * All OS related initialization including memory and device structure and
7785 * initlaization of the device private variable is done. Also the swapper
7786 * control register is initialized to enable read and write into the I/O
1da177e4
LT		 7787 * registers of the device.
7788 * Return value:
7789 * returns 0 on success and negative on failure.
7790 */
7791
7792static int __devinit
7793s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7794{
1ee6dd77 7795 struct s2io_nic *sp;
1da177e4 7796 struct net_device *dev;
1da177e4 7797 int i, j, ret;
f957bcf0 7798 int dma_flag = false;
1da177e4
LT		 7799 u32 mac_up, mac_down;
7800 u64 val64 = 0, tmp64 = 0;
1ee6dd77 7801 struct XENA_dev_config __iomem *bar0 = NULL;
1da177e4 7802 u16 subid;
1ee6dd77 7803 struct mac_info *mac_control;
1da177e4 7804 struct config_param *config;
541ae68f 7805 int mode;
cc6e7c44 7806 u8 dev_intr_type = intr_type;
3a3d5756 7807 u8 dev_multiq = 0;
1da177e4 7808
3a3d5756
SH		 7809 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7810 if (ret)
9dc737a7 7811 return ret;
1da177e4 7812
d44570e4
JP		 7813 ret = pci_enable_device(pdev);
7814 if (ret) {
1da177e4
LT		 7815 DBG_PRINT(ERR_DBG,
7816 "s2io_init_nic: pci_enable_device failed\n");
7817 return ret;
7818 }
7819
6a35528a 7820 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4 7821 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
f957bcf0 7822 dma_flag = true;
d44570e4 7823 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4 7824 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7825 "Unable to obtain 64bit DMA "
7826 "for consistent allocations\n");
1da177e4
LT		 7827 pci_disable_device(pdev);
7828 return -ENOMEM;
7829 }
284901a9 7830 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1da177e4
LT		 7831 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
7832 } else {
7833 pci_disable_device(pdev);
7834 return -ENOMEM;
7835 }
d44570e4
JP		 7836 ret = pci_request_regions(pdev, s2io_driver_name);
7837 if (ret) {
7838 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x \n",
7839 __func__, ret);
eccb8628
VP		 7840 pci_disable_device(pdev);
7841 return -ENODEV;
1da177e4 7842 }
3a3d5756 7843 if (dev_multiq)
6cfc482b 7844 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
3a3d5756 7845 else
b19fa1fa 7846 dev = alloc_etherdev(sizeof(struct s2io_nic));
1da177e4
LT		 7847 if (dev == NULL) {
7848 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7849 pci_disable_device(pdev);
7850 pci_release_regions(pdev);
7851 return -ENODEV;
7852 }
7853
7854 pci_set_master(pdev);
7855 pci_set_drvdata(pdev, dev);
1da177e4
LT		 7856 SET_NETDEV_DEV(dev, &pdev->dev);
7857
7858 /* Private member variable initialized to s2io NIC structure */
4cf1653a 7859 sp = netdev_priv(dev);
1ee6dd77 7860 memset(sp, 0, sizeof(struct s2io_nic));
1da177e4
LT		 7861 sp->dev = dev;
7862 sp->pdev = pdev;
1da177e4 7863 sp->high_dma_flag = dma_flag;
f957bcf0 7864 sp->device_enabled_once = false;
da6971d8
AR		 7865 if (rx_ring_mode == 1)
7866 sp->rxd_mode = RXD_MODE_1;
7867 if (rx_ring_mode == 2)
7868 sp->rxd_mode = RXD_MODE_3B;
da6971d8 7869
eaae7f72 7870 sp->config.intr_type = dev_intr_type;
1da177e4 7871
541ae68f 7872 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
d44570e4 7873 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
541ae68f
K		 7874 sp->device_type = XFRAME_II_DEVICE;
7875 else
7876 sp->device_type = XFRAME_I_DEVICE;
7877
43b7c451 7878 sp->lro = lro_enable;
6aa20a22 7879
1da177e4
LT		 7880 /* Initialize some PCI/PCI-X fields of the NIC. */
7881 s2io_init_pci(sp);
7882
20346722 7883 /*
1da177e4 7884 * Setting the device configuration parameters.
20346722
K		 7885 * Most of these parameters can be specified by the user during
7886 * module insertion as they are module loadable parameters. If
7887 * these parameters are not not specified during load time, they
1da177e4
LT		 7888 * are initialized with default values.
7889 */
7890 mac_control = &sp->mac_control;
7891 config = &sp->config;
7892
596c5c97 7893 config->napi = napi;
6cfc482b 7894 config->tx_steering_type = tx_steering_type;
596c5c97 7895
1da177e4 7896 /* Tx side parameters. */
6cfc482b
SH		 7897 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7898 config->tx_fifo_num = MAX_TX_FIFOS;
7899 else
7900 config->tx_fifo_num = tx_fifo_num;
7901
7902 /* Initialize the fifos used for tx steering */
7903 if (config->tx_fifo_num < 5) {
d44570e4
JP		 7904 if (config->tx_fifo_num == 1)
7905 sp->total_tcp_fifos = 1;
7906 else
7907 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7908 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7909 sp->total_udp_fifos = 1;
7910 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
6cfc482b
SH		 7911 } else {
7912 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
d44570e4 7913 FIFO_OTHER_MAX_NUM);
6cfc482b
SH		 7914 sp->udp_fifo_idx = sp->total_tcp_fifos;
7915 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7916 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7917 }
7918
3a3d5756 7919 config->multiq = dev_multiq;
6cfc482b 7920 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 7921 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7922
7923 tx_cfg->fifo_len = tx_fifo_len[i];
7924 tx_cfg->fifo_priority = i;
1da177e4
LT		 7925 }
7926
20346722
K		 7927 /* mapping the QoS priority to the configured fifos */
7928 for (i = 0; i < MAX_TX_FIFOS; i++)
3a3d5756 7929 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
20346722 7930
6cfc482b
SH		 7931 /* map the hashing selector table to the configured fifos */
7932 for (i = 0; i < config->tx_fifo_num; i++)
7933 sp->fifo_selector[i] = fifo_selector[i];
7934
7935
1da177e4
LT		 7936 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7937 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 7938 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7939
7940 tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7941 if (tx_cfg->fifo_len < 65) {
1da177e4
LT		 7942 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7943 break;
7944 }
7945 }
fed5eccd
AR		 7946 /* + 2 because one Txd for skb->data and one Txd for UFO */
7947 config->max_txds = MAX_SKB_FRAGS + 2;
1da177e4
LT		 7948
7949 /* Rx side parameters. */
1da177e4 7950 config->rx_ring_num = rx_ring_num;
0425b46a 7951 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7952 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7953 struct ring_info *ring = &mac_control->rings[i];
7954
7955 rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
7956 rx_cfg->ring_priority = i;
7957 ring->rx_bufs_left = 0;
7958 ring->rxd_mode = sp->rxd_mode;
7959 ring->rxd_count = rxd_count[sp->rxd_mode];
7960 ring->pdev = sp->pdev;
7961 ring->dev = sp->dev;
1da177e4
LT		 7962 }
7963
7964 for (i = 0; i < rx_ring_num; i++) {
13d866a9
JP		 7965 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7966
7967 rx_cfg->ring_org = RING_ORG_BUFF1;
7968 rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
1da177e4
LT		 7969 }
7970
7971 /* Setting Mac Control parameters */
7972 mac_control->rmac_pause_time = rmac_pause_time;
7973 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7974 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7975
7976
1da177e4
LT		 7977 /* initialize the shared memory used by the NIC and the host */
7978 if (init_shared_mem(sp)) {
d44570e4 7979 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", dev->name);
1da177e4
LT		 7980 ret = -ENOMEM;
7981 goto mem_alloc_failed;
7982 }
7983
275f165f 7984 sp->bar0 = pci_ioremap_bar(pdev, 0);
1da177e4 7985 if (!sp->bar0) {
19a60522 7986 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
1da177e4
LT		 7987 dev->name);
7988 ret = -ENOMEM;
7989 goto bar0_remap_failed;
7990 }
7991
275f165f 7992 sp->bar1 = pci_ioremap_bar(pdev, 2);
1da177e4 7993 if (!sp->bar1) {
19a60522 7994 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
1da177e4
LT		 7995 dev->name);
7996 ret = -ENOMEM;
7997 goto bar1_remap_failed;
7998 }
7999
8000 dev->irq = pdev->irq;
d44570e4 8001 dev->base_addr = (unsigned long)sp->bar0;
1da177e4
LT		 8002
8003 /* Initializing the BAR1 address as the start of the FIFO pointer. */
8004 for (j = 0; j < MAX_TX_FIFOS; j++) {
d44570e4
JP		 8005 mac_control->tx_FIFO_start[j] =
8006 (struct TxFIFO_element __iomem *)
8007 (sp->bar1 + (j * 0x00020000));
1da177e4
LT		 8008 }
8009
8010 /* Driver entry points */
04025095 8011 dev->netdev_ops = &s2io_netdev_ops;
1da177e4 8012 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
be3a6b02 8013 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
612eff0e 8014
1da177e4 8015 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
f957bcf0 8016 if (sp->high_dma_flag == true)
1da177e4 8017 dev->features |= NETIF_F_HIGHDMA;
1da177e4 8018 dev->features |= NETIF_F_TSO;
f83ef8c0 8019 dev->features |= NETIF_F_TSO6;
db874e65 8020 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
fed5eccd
AR		 8021 dev->features |= NETIF_F_UFO;
8022 dev->features |= NETIF_F_HW_CSUM;
8023 }
1da177e4 8024 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
c4028958
DH		 8025 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
8026 INIT_WORK(&sp->set_link_task, s2io_set_link);
1da177e4 8027
e960fc5c 8028 pci_save_state(sp->pdev);
1da177e4
LT		 8029
8030 /* Setting swapper control on the NIC, for proper reset operation */
8031 if (s2io_set_swapper(sp)) {
8032 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
8033 dev->name);
8034 ret = -EAGAIN;
8035 goto set_swap_failed;
8036 }
8037
541ae68f
K		 8038 /* Verify if the Herc works on the slot its placed into */
8039 if (sp->device_type & XFRAME_II_DEVICE) {
8040 mode = s2io_verify_pci_mode(sp);
8041 if (mode < 0) {
b39d66a8 8042 DBG_PRINT(ERR_DBG, "%s: ", __func__);
541ae68f
K		 8043 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
8044 ret = -EBADSLT;
8045 goto set_swap_failed;
8046 }
8047 }
8048
f61e0a35
SH		 8049 if (sp->config.intr_type == MSI_X) {
8050 sp->num_entries = config->rx_ring_num + 1;
8051 ret = s2io_enable_msi_x(sp);
8052
8053 if (!ret) {
8054 ret = s2io_test_msi(sp);
8055 /* rollback MSI-X, will re-enable during add_isr() */
8056 remove_msix_isr(sp);
8057 }
8058 if (ret) {
8059
8060 DBG_PRINT(ERR_DBG,
d44570e4 8061 "s2io: MSI-X requested but failed to enable\n");
f61e0a35
SH		 8062 sp->config.intr_type = INTA;
8063 }
8064 }
8065
8066 if (config->intr_type == MSI_X) {
13d866a9
JP		 8067 for (i = 0; i < config->rx_ring_num ; i++) {
8068 struct ring_info *ring = &mac_control->rings[i];
8069
8070 netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64);
8071 }
f61e0a35
SH		 8072 } else {
8073 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
8074 }
8075
541ae68f
K		 8076 /* Not needed for Herc */
8077 if (sp->device_type & XFRAME_I_DEVICE) {
8078 /*
8079 * Fix for all "FFs" MAC address problems observed on
8080 * Alpha platforms
8081 */
8082 fix_mac_address(sp);
8083 s2io_reset(sp);
8084 }
1da177e4
LT		 8085
8086 /*
1da177e4
LT		 8087 * MAC address initialization.
8088 * For now only one mac address will be read and used.
8089 */
8090 bar0 = sp->bar0;
8091 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
d44570e4 8092 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
1da177e4 8093 writeq(val64, &bar0->rmac_addr_cmd_mem);
c92ca04b 8094 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 8095 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
8096 S2IO_BIT_RESET);
1da177e4 8097 tmp64 = readq(&bar0->rmac_addr_data0_mem);
d44570e4 8098 mac_down = (u32)tmp64;
1da177e4
LT		 8099 mac_up = (u32) (tmp64 >> 32);
8100
1da177e4
LT		 8101 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8102 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8103 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8104 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8105 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8106 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8107
1da177e4
LT		 8108 /* Set the factory defined MAC address initially */
8109 dev->addr_len = ETH_ALEN;
8110 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
2fd37688 8111 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
1da177e4 8112
faa4f796
SH		 8113 /* initialize number of multicast & unicast MAC entries variables */
8114 if (sp->device_type == XFRAME_I_DEVICE) {
8115 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8116 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8117 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8118 } else if (sp->device_type == XFRAME_II_DEVICE) {
8119 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8120 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8121 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8122 }
8123
8124 /* store mac addresses from CAM to s2io_nic structure */
8125 do_s2io_store_unicast_mc(sp);
8126
f61e0a35
SH		 8127 /* Configure MSIX vector for number of rings configured plus one */
8128 if ((sp->device_type == XFRAME_II_DEVICE) &&
d44570e4 8129 (config->intr_type == MSI_X))
f61e0a35
SH		 8130 sp->num_entries = config->rx_ring_num + 1;
8131
d44570e4 8132 /* Store the values of the MSIX table in the s2io_nic structure */
c77dd43e 8133 store_xmsi_data(sp);
b41477f3
AR		 8134 /* reset Nic and bring it to known state */
8135 s2io_reset(sp);
8136
1da177e4 8137 /*
99993af6 8138 * Initialize link state flags
541ae68f 8139 * and the card state parameter
1da177e4 8140 */
92b84437 8141 sp->state = 0;
1da177e4 8142
1da177e4 8143 /* Initialize spinlocks */
13d866a9
JP		 8144 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8145 struct fifo_info *fifo = &mac_control->fifos[i];
8146
8147 spin_lock_init(&fifo->tx_lock);
8148 }
db874e65 8149
20346722
K		 8150 /*
8151 * SXE-002: Configure link and activity LED to init state
8152 * on driver load.
1da177e4
LT		 8153 */
8154 subid = sp->pdev->subsystem_device;
8155 if ((subid & 0xFF) >= 0x07) {
8156 val64 = readq(&bar0->gpio_control);
8157 val64 |= 0x0000800000000000ULL;
8158 writeq(val64, &bar0->gpio_control);
8159 val64 = 0x0411040400000000ULL;
d44570e4 8160 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 8161 val64 = readq(&bar0->gpio_control);
8162 }
8163
8164 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8165
8166 if (register_netdev(dev)) {
8167 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8168 ret = -ENODEV;
8169 goto register_failed;
8170 }
9dc737a7 8171 s2io_vpd_read(sp);
0c61ed5f 8172 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
d44570e4 8173 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name,
44c10138 8174 sp->product_name, pdev->revision);
b41477f3
AR		 8175 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8176 s2io_driver_version);
e174961c 8177 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: %pM\n", dev->name, dev->dev_addr);
19a60522 8178 DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
9dc737a7 8179 if (sp->device_type & XFRAME_II_DEVICE) {
0b1f7ebe 8180 mode = s2io_print_pci_mode(sp);
541ae68f 8181 if (mode < 0) {
9dc737a7 8182 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
541ae68f 8183 ret = -EBADSLT;
9dc737a7 8184 unregister_netdev(dev);
541ae68f
K		 8185 goto set_swap_failed;
8186 }
541ae68f 8187 }
d44570e4
JP		 8188 switch (sp->rxd_mode) {
8189 case RXD_MODE_1:
8190 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8191 dev->name);
8192 break;
8193 case RXD_MODE_3B:
8194 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8195 dev->name);
8196 break;
9dc737a7 8197 }
db874e65 8198
f61e0a35
SH		 8199 switch (sp->config.napi) {
8200 case 0:
8201 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8202 break;
8203 case 1:
db874e65 8204 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
f61e0a35
SH		 8205 break;
8206 }
3a3d5756
SH		 8207
8208 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
d44570e4 8209 sp->config.tx_fifo_num);
3a3d5756 8210
0425b46a
SH		 8211 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8212 sp->config.rx_ring_num);
8213
d44570e4
JP		 8214 switch (sp->config.intr_type) {
8215 case INTA:
8216 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8217 break;
8218 case MSI_X:
8219 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8220 break;
9dc737a7 8221 }
3a3d5756 8222 if (sp->config.multiq) {
13d866a9
JP		 8223 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8224 struct fifo_info *fifo = &mac_control->fifos[i];
8225
8226 fifo->multiq = config->multiq;
8227 }
3a3d5756 8228 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
d44570e4 8229 dev->name);
3a3d5756
SH		 8230 } else
8231 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
d44570e4 8232 dev->name);
3a3d5756 8233
6cfc482b
SH		 8234 switch (sp->config.tx_steering_type) {
8235 case NO_STEERING:
d44570e4
JP		 8236 DBG_PRINT(ERR_DBG, "%s: No steering enabled for transmit\n",
8237 dev->name);
8238 break;
6cfc482b 8239 case TX_PRIORITY_STEERING:
d44570e4
JP		 8240 DBG_PRINT(ERR_DBG,
8241 "%s: Priority steering enabled for transmit\n",
8242 dev->name);
6cfc482b
SH		 8243 break;
8244 case TX_DEFAULT_STEERING:
d44570e4
JP		 8245 DBG_PRINT(ERR_DBG,
8246 "%s: Default steering enabled for transmit\n",
8247 dev->name);
6cfc482b
SH		 8248 }
8249
7d3d0439
RA		 8250 if (sp->lro)
8251 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
9dc737a7 8252 dev->name);
db874e65 8253 if (ufo)
d44570e4
JP		 8254 DBG_PRINT(ERR_DBG,
8255 "%s: UDP Fragmentation Offload(UFO) enabled\n",
8256 dev->name);
7ba013ac 8257 /* Initialize device name */
9dc737a7 8258 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7ba013ac 8259
cd0fce03
BL		 8260 if (vlan_tag_strip)
8261 sp->vlan_strip_flag = 1;
8262 else
8263 sp->vlan_strip_flag = 0;
8264
20346722
K		 8265 /*
8266 * Make Link state as off at this point, when the Link change
8267 * interrupt comes the state will be automatically changed to
1da177e4
LT		 8268 * the right state.
8269 */
8270 netif_carrier_off(dev);
1da177e4
LT		 8271
8272 return 0;
8273
d44570e4
JP		 8274register_failed:
8275set_swap_failed:
1da177e4 8276 iounmap(sp->bar1);
d44570e4 8277bar1_remap_failed:
1da177e4 8278 iounmap(sp->bar0);
d44570e4
JP		 8279bar0_remap_failed:
8280mem_alloc_failed:
1da177e4
LT		 8281 free_shared_mem(sp);
8282 pci_disable_device(pdev);
eccb8628 8283 pci_release_regions(pdev);
1da177e4
LT		 8284 pci_set_drvdata(pdev, NULL);
8285 free_netdev(dev);
8286
8287 return ret;
8288}
8289
8290/**
20346722 8291 * s2io_rem_nic - Free the PCI device
1da177e4 8292 * @pdev: structure containing the PCI related information of the device.
20346722 8293 * Description: This function is called by the Pci subsystem to release a
1da177e4 8294 * PCI device and free up all resource held up by the device. This could
20346722 8295 * be in response to a Hot plug event or when the driver is to be removed
1da177e4
LT		 8296 * from memory.
8297 */
8298
8299static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8300{
8301 struct net_device *dev =
d44570e4 8302 (struct net_device *)pci_get_drvdata(pdev);
1ee6dd77 8303 struct s2io_nic *sp;
1da177e4
LT		 8304
8305 if (dev == NULL) {
8306 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8307 return;
8308 }
8309
22747d6b
FR		 8310 flush_scheduled_work();
8311
4cf1653a 8312 sp = netdev_priv(dev);
1da177e4
LT		 8313 unregister_netdev(dev);
8314
8315 free_shared_mem(sp);
8316 iounmap(sp->bar0);
8317 iounmap(sp->bar1);
eccb8628 8318 pci_release_regions(pdev);
1da177e4 8319 pci_set_drvdata(pdev, NULL);
1da177e4 8320 free_netdev(dev);
19a60522 8321 pci_disable_device(pdev);
1da177e4
LT		 8322}
8323
8324/**
8325 * s2io_starter - Entry point for the driver
8326 * Description: This function is the entry point for the driver. It verifies
8327 * the module loadable parameters and initializes PCI configuration space.
8328 */
8329
43b7c451 8330static int __init s2io_starter(void)
1da177e4 8331{
29917620 8332 return pci_register_driver(&s2io_driver);
1da177e4
LT		 8333}
8334
8335/**
20346722 8336 * s2io_closer - Cleanup routine for the driver
1da177e4
LT		 8337 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8338 */
8339
372cc597 8340static __exit void s2io_closer(void)
1da177e4
LT		 8341{
8342 pci_unregister_driver(&s2io_driver);
8343 DBG_PRINT(INIT_DBG, "cleanup done\n");
8344}
8345
8346module_init(s2io_starter);
8347module_exit(s2io_closer);
7d3d0439 8348
6aa20a22 8349static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
d44570e4
JP		 8350 struct tcphdr **tcp, struct RxD_t *rxdp,
8351 struct s2io_nic *sp)
7d3d0439
RA		 8352{
8353 int ip_off;
8354 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8355
8356 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
d44570e4
JP		 8357 DBG_PRINT(INIT_DBG,
8358 "%s: Non-TCP frames not supported for LRO\n",
b39d66a8 8359 __func__);
7d3d0439
RA		 8360 return -1;
8361 }
8362
cdb5bf02 8363 /* Checking for DIX type or DIX type with VLAN */
d44570e4 8364 if ((l2_type == 0) || (l2_type == 4)) {
cdb5bf02
SH		 8365 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8366 /*
8367 * If vlan stripping is disabled and the frame is VLAN tagged,
8368 * shift the offset by the VLAN header size bytes.
8369 */
cd0fce03 8370 if ((!sp->vlan_strip_flag) &&
d44570e4 8371 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
cdb5bf02
SH		 8372 ip_off += HEADER_VLAN_SIZE;
8373 } else {
7d3d0439 8374 /* LLC, SNAP etc are considered non-mergeable */
cdb5bf02 8375 return -1;
7d3d0439
RA		 8376 }
8377
8378 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8379 ip_len = (u8)((*ip)->ihl);
8380 ip_len <<= 2;
8381 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8382
8383 return 0;
8384}
8385
1ee6dd77 8386static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 8387 struct tcphdr *tcp)
8388{
d44570e4
JP		 8389 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8390 if ((lro->iph->saddr != ip->saddr) ||
8391 (lro->iph->daddr != ip->daddr) ||
8392 (lro->tcph->source != tcp->source) ||
8393 (lro->tcph->dest != tcp->dest))
7d3d0439
RA		 8394 return -1;
8395 return 0;
8396}
8397
8398static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8399{
d44570e4 8400 return ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2);
7d3d0439
RA		 8401}
8402
1ee6dd77 8403static void initiate_new_session(struct lro *lro, u8 *l2h,
d44570e4
JP		 8404 struct iphdr *ip, struct tcphdr *tcp,
8405 u32 tcp_pyld_len, u16 vlan_tag)
7d3d0439 8406{
d44570e4 8407 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8408 lro->l2h = l2h;
8409 lro->iph = ip;
8410 lro->tcph = tcp;
8411 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
c8855953 8412 lro->tcp_ack = tcp->ack_seq;
7d3d0439
RA		 8413 lro->sg_num = 1;
8414 lro->total_len = ntohs(ip->tot_len);
8415 lro->frags_len = 0;
cdb5bf02 8416 lro->vlan_tag = vlan_tag;
6aa20a22 8417 /*
d44570e4
JP		 8418 * Check if we saw TCP timestamp.
8419 * Other consistency checks have already been done.
8420 */
7d3d0439 8421 if (tcp->doff == 8) {
c8855953
SR		 8422 __be32 *ptr;
8423 ptr = (__be32 *)(tcp+1);
7d3d0439 8424 lro->saw_ts = 1;
c8855953 8425 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8426 lro->cur_tsecr = *(ptr+2);
8427 }
8428 lro->in_use = 1;
8429}
8430
1ee6dd77 8431static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7d3d0439
RA		 8432{
8433 struct iphdr *ip = lro->iph;
8434 struct tcphdr *tcp = lro->tcph;
bd4f3ae1 8435 __sum16 nchk;
1ee6dd77 8436 struct stat_block *statinfo = sp->mac_control.stats_info;
d44570e4 8437 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8438
8439 /* Update L3 header */
8440 ip->tot_len = htons(lro->total_len);
8441 ip->check = 0;
8442 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8443 ip->check = nchk;
8444
8445 /* Update L4 header */
8446 tcp->ack_seq = lro->tcp_ack;
8447 tcp->window = lro->window;
8448
8449 /* Update tsecr field if this session has timestamps enabled */
8450 if (lro->saw_ts) {
c8855953 8451 __be32 *ptr = (__be32 *)(tcp + 1);
7d3d0439
RA		 8452 *(ptr+2) = lro->cur_tsecr;
8453 }
8454
8455 /* Update counters required for calculation of
8456 * average no. of packets aggregated.
8457 */
8458 statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
8459 statinfo->sw_stat.num_aggregations++;
8460}
8461
1ee6dd77 8462static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
d44570e4 8463 struct tcphdr *tcp, u32 l4_pyld)
7d3d0439 8464{
d44570e4 8465 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8466 lro->total_len += l4_pyld;
8467 lro->frags_len += l4_pyld;
8468 lro->tcp_next_seq += l4_pyld;
8469 lro->sg_num++;
8470
8471 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8472 lro->tcp_ack = tcp->ack_seq;
8473 lro->window = tcp->window;
6aa20a22 8474
7d3d0439 8475 if (lro->saw_ts) {
c8855953 8476 __be32 *ptr;
7d3d0439 8477 /* Update tsecr and tsval from this packet */
c8855953
SR		 8478 ptr = (__be32 *)(tcp+1);
8479 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8480 lro->cur_tsecr = *(ptr + 2);
8481 }
8482}
8483
1ee6dd77 8484static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7d3d0439
RA		 8485 struct tcphdr *tcp, u32 tcp_pyld_len)
8486{
7d3d0439
RA		 8487 u8 *ptr;
8488
d44570e4 8489 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
79dc1901 8490
7d3d0439
RA		 8491 if (!tcp_pyld_len) {
8492 /* Runt frame or a pure ack */
8493 return -1;
8494 }
8495
8496 if (ip->ihl != 5) /* IP has options */
8497 return -1;
8498
75c30b13
AR		 8499 /* If we see CE codepoint in IP header, packet is not mergeable */
8500 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8501 return -1;
8502
8503 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
d44570e4
JP		 8504 if (tcp->urg || tcp->psh || tcp->rst ||
8505 tcp->syn || tcp->fin ||
8506 tcp->ece || tcp->cwr || !tcp->ack) {
7d3d0439
RA		 8507 /*
8508 * Currently recognize only the ack control word and
8509 * any other control field being set would result in
8510 * flushing the LRO session
8511 */
8512 return -1;
8513 }
8514
6aa20a22 8515 /*
7d3d0439
RA		 8516 * Allow only one TCP timestamp option. Don't aggregate if
8517 * any other options are detected.
8518 */
8519 if (tcp->doff != 5 && tcp->doff != 8)
8520 return -1;
8521
8522 if (tcp->doff == 8) {
6aa20a22 8523 ptr = (u8 *)(tcp + 1);
7d3d0439
RA		 8524 while (*ptr == TCPOPT_NOP)
8525 ptr++;
8526 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8527 return -1;
8528
8529 /* Ensure timestamp value increases monotonically */
8530 if (l_lro)
c8855953 8531 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
7d3d0439
RA		 8532 return -1;
8533
8534 /* timestamp echo reply should be non-zero */
c8855953 8535 if (*((__be32 *)(ptr+6)) == 0)
7d3d0439
RA		 8536 return -1;
8537 }
8538
8539 return 0;
8540}
8541
d44570e4
JP		 8542static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
8543 u8 **tcp, u32 *tcp_len, struct lro **lro,
8544 struct RxD_t *rxdp, struct s2io_nic *sp)
7d3d0439
RA		 8545{
8546 struct iphdr *ip;
8547 struct tcphdr *tcph;
8548 int ret = 0, i;
cdb5bf02 8549 u16 vlan_tag = 0;
7d3d0439 8550
d44570e4
JP		 8551 ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8552 rxdp, sp);
8553 if (ret)
7d3d0439 8554 return ret;
7d3d0439 8555
d44570e4
JP		 8556 DBG_PRINT(INFO_DBG, "IP Saddr: %x Daddr: %x\n", ip->saddr, ip->daddr);
8557
cdb5bf02 8558 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
7d3d0439
RA		 8559 tcph = (struct tcphdr *)*tcp;
8560 *tcp_len = get_l4_pyld_length(ip, tcph);
d44570e4 8561 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 8562 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8563 if (l_lro->in_use) {
8564 if (check_for_socket_match(l_lro, ip, tcph))
8565 continue;
8566 /* Sock pair matched */
8567 *lro = l_lro;
8568
8569 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8570 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
b39d66a8 8571 "0x%x, actual 0x%x\n", __func__,
7d3d0439
RA		 8572 (*lro)->tcp_next_seq,
8573 ntohl(tcph->seq));
8574
8575 sp->mac_control.stats_info->
d44570e4 8576 sw_stat.outof_sequence_pkts++;
7d3d0439
RA		 8577 ret = 2;
8578 break;
8579 }
8580
d44570e4
JP		 8581 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,
8582 *tcp_len))
7d3d0439
RA		 8583 ret = 1; /* Aggregate */
8584 else
8585 ret = 2; /* Flush both */
8586 break;
8587 }
8588 }
8589
8590 if (ret == 0) {
8591 /* Before searching for available LRO objects,
8592 * check if the pkt is L3/L4 aggregatable. If not
8593 * don't create new LRO session. Just send this
8594 * packet up.
8595 */
d44570e4 8596 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len))
7d3d0439 8597 return 5;
7d3d0439 8598
d44570e4 8599 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 8600 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8601 if (!(l_lro->in_use)) {
8602 *lro = l_lro;
8603 ret = 3; /* Begin anew */
8604 break;
8605 }
8606 }
8607 }
8608
8609 if (ret == 0) { /* sessions exceeded */
d44570e4 8610 DBG_PRINT(INFO_DBG, "%s:All LRO sessions already in use\n",
b39d66a8 8611 __func__);
7d3d0439
RA		 8612 *lro = NULL;
8613 return ret;
8614 }
8615
8616 switch (ret) {
d44570e4
JP		 8617 case 3:
8618 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8619 vlan_tag);
8620 break;
8621 case 2:
8622 update_L3L4_header(sp, *lro);
8623 break;
8624 case 1:
8625 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8626 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
7d3d0439 8627 update_L3L4_header(sp, *lro);
d44570e4
JP		 8628 ret = 4; /* Flush the LRO */
8629 }
8630 break;
8631 default:
8632 DBG_PRINT(ERR_DBG, "%s:Dont know, can't say!!\n", __func__);
8633 break;
7d3d0439
RA		 8634 }
8635
8636 return ret;
8637}
8638
1ee6dd77 8639static void clear_lro_session(struct lro *lro)
7d3d0439 8640{
1ee6dd77 8641 static u16 lro_struct_size = sizeof(struct lro);
7d3d0439
RA		 8642
8643 memset(lro, 0, lro_struct_size);
8644}
8645
cdb5bf02 8646static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
7d3d0439
RA		 8647{
8648 struct net_device *dev = skb->dev;
4cf1653a 8649 struct s2io_nic *sp = netdev_priv(dev);
7d3d0439
RA		 8650
8651 skb->protocol = eth_type_trans(skb, dev);
d44570e4 8652 if (sp->vlgrp && vlan_tag && (sp->vlan_strip_flag)) {
cdb5bf02
SH		 8653 /* Queueing the vlan frame to the upper layer */
8654 if (sp->config.napi)
8655 vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8656 else
8657 vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8658 } else {
8659 if (sp->config.napi)
8660 netif_receive_skb(skb);
8661 else
8662 netif_rx(skb);
8663 }
7d3d0439
RA		 8664}
8665
1ee6dd77 8666static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
d44570e4 8667 struct sk_buff *skb, u32 tcp_len)
7d3d0439 8668{
75c30b13 8669 struct sk_buff *first = lro->parent;
7d3d0439
RA		 8670
8671 first->len += tcp_len;
8672 first->data_len = lro->frags_len;
8673 skb_pull(skb, (skb->len - tcp_len));
75c30b13
AR		 8674 if (skb_shinfo(first)->frag_list)
8675 lro->last_frag->next = skb;
7d3d0439
RA		 8676 else
8677 skb_shinfo(first)->frag_list = skb;
372cc597 8678 first->truesize += skb->truesize;
75c30b13 8679 lro->last_frag = skb;
7d3d0439
RA		 8680 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
8681 return;
8682}
d796fdb7
LV		 8683
8684/**
8685 * s2io_io_error_detected - called when PCI error is detected
8686 * @pdev: Pointer to PCI device
8453d43f 8687 * @state: The current pci connection state
d796fdb7
LV		 8688 *
8689 * This function is called after a PCI bus error affecting
8690 * this device has been detected.
8691 */
8692static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
d44570e4 8693 pci_channel_state_t state)
d796fdb7
LV		 8694{
8695 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8696 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8697
8698 netif_device_detach(netdev);
8699
1e3c8bd6
DN		 8700 if (state == pci_channel_io_perm_failure)
8701 return PCI_ERS_RESULT_DISCONNECT;
8702
d796fdb7
LV		 8703 if (netif_running(netdev)) {
8704 /* Bring down the card, while avoiding PCI I/O */
8705 do_s2io_card_down(sp, 0);
d796fdb7
LV		 8706 }
8707 pci_disable_device(pdev);
8708
8709 return PCI_ERS_RESULT_NEED_RESET;
8710}
8711
8712/**
8713 * s2io_io_slot_reset - called after the pci bus has been reset.
8714 * @pdev: Pointer to PCI device
8715 *
8716 * Restart the card from scratch, as if from a cold-boot.
8717 * At this point, the card has exprienced a hard reset,
8718 * followed by fixups by BIOS, and has its config space
8719 * set up identically to what it was at cold boot.
8720 */
8721static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8722{
8723 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8724 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8725
8726 if (pci_enable_device(pdev)) {
8727 printk(KERN_ERR "s2io: "
8728 "Cannot re-enable PCI device after reset.\n");
8729 return PCI_ERS_RESULT_DISCONNECT;
8730 }
8731
8732 pci_set_master(pdev);
8733 s2io_reset(sp);
8734
8735 return PCI_ERS_RESULT_RECOVERED;
8736}
8737
8738/**
8739 * s2io_io_resume - called when traffic can start flowing again.
8740 * @pdev: Pointer to PCI device
8741 *
8742 * This callback is called when the error recovery driver tells
8743 * us that its OK to resume normal operation.
8744 */
8745static void s2io_io_resume(struct pci_dev *pdev)
8746{
8747 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8748 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8749
8750 if (netif_running(netdev)) {
8751 if (s2io_card_up(sp)) {
8752 printk(KERN_ERR "s2io: "
8753 "Can't bring device back up after reset.\n");
8754 return;
8755 }
8756
8757 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8758 s2io_card_down(sp);
8759 printk(KERN_ERR "s2io: "
8760 "Can't resetore mac addr after reset.\n");
8761 return;
8762 }
8763 }
8764
8765 netif_device_attach(netdev);
fd2ea0a7 8766 netif_tx_wake_all_queues(netdev);
d796fdb7 8767}
kernel source for telekom puls (alcatel/mediatek)