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s2io.c: Use calculated size in kmallocs
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / s2io.c
CommitLineData
1da177e4 1/************************************************************************
776bd20f 2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
0c61ed5f 3 * Copyright(c) 2002-2007 Neterion Inc.
1da177e4
LT		 4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
20346722
K		 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
1da177e4
LT		 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
20346722 21 * Francois Romieu : For pointing out all code part that were
1da177e4 22 * deprecated and also styling related comments.
20346722 23 * Grant Grundler : For helping me get rid of some Architecture
1da177e4
LT		 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
20346722 26 *
1da177e4
LT		 27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
9dc737a7 29 *
20346722
K		 30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
9dc737a7
AR		 32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
da6971d8 34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
6d517a27 35 * values are 1, 2.
1da177e4 36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
20346722 37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
1da177e4 38 * Tx descriptors that can be associated with each corresponding FIFO.
9dc737a7 39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
8abc4d5b 40 * 2(MSI_X). Default value is '2(MSI_X)'
43b7c451 41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
9dc737a7
AR		 42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
926930b2
SS		 45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
3a3d5756
SH		 53 * multiq: This parameter used to enable/disable MULTIQUEUE support.
54 * Possible values '1' for enable and '0' for disable. Default is '0'
1da177e4
LT		 55 ************************************************************************/
56
1da177e4
LT		 57#include <linux/module.h>
58#include <linux/types.h>
59#include <linux/errno.h>
60#include <linux/ioport.h>
61#include <linux/pci.h>
1e7f0bd8 62#include <linux/dma-mapping.h>
1da177e4
LT		 63#include <linux/kernel.h>
64#include <linux/netdevice.h>
65#include <linux/etherdevice.h>
40239396 66#include <linux/mdio.h>
1da177e4
LT		 67#include <linux/skbuff.h>
68#include <linux/init.h>
69#include <linux/delay.h>
70#include <linux/stddef.h>
71#include <linux/ioctl.h>
72#include <linux/timex.h>
1da177e4 73#include <linux/ethtool.h>
1da177e4 74#include <linux/workqueue.h>
be3a6b02 75#include <linux/if_vlan.h>
7d3d0439
RA		 76#include <linux/ip.h>
77#include <linux/tcp.h>
78#include <net/tcp.h>
1da177e4 79
1da177e4
LT		 80#include <asm/system.h>
81#include <asm/uaccess.h>
20346722 82#include <asm/io.h>
fe931395 83#include <asm/div64.h>
330ce0de 84#include <asm/irq.h>
1da177e4
LT		 85
86/* local include */
87#include "s2io.h"
88#include "s2io-regs.h"
89
29d0a2b0 90#define DRV_VERSION "2.0.26.25"
6c1792f4 91
1da177e4 92/* S2io Driver name & version. */
20346722 93static char s2io_driver_name[] = "Neterion";
6c1792f4 94static char s2io_driver_version[] = DRV_VERSION;
1da177e4 95
6d517a27
VP		 96static int rxd_size[2] = {32,48};
97static int rxd_count[2] = {127,85};
da6971d8 98
1ee6dd77 99static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
5e25b9dd
K		 100{
101 int ret;
102
103 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
104 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
105
106 return ret;
107}
108
20346722 109/*
1da177e4
LT		 110 * Cards with following subsystem_id have a link state indication
111 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
112 * macro below identifies these cards given the subsystem_id.
113 */
541ae68f
K		 114#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
115 (dev_type == XFRAME_I_DEVICE) ? \
116 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
117 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
1da177e4
LT		 118
119#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
120 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
1da177e4 121
92b84437
SS		 122static inline int is_s2io_card_up(const struct s2io_nic * sp)
123{
124 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
125}
126
1da177e4 127/* Ethtool related variables and Macros. */
6fce365d 128static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
1da177e4
LT		 129 "Register test\t(offline)",
130 "Eeprom test\t(offline)",
131 "Link test\t(online)",
132 "RLDRAM test\t(offline)",
133 "BIST Test\t(offline)"
134};
135
6fce365d 136static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
1da177e4
LT		 137 {"tmac_frms"},
138 {"tmac_data_octets"},
139 {"tmac_drop_frms"},
140 {"tmac_mcst_frms"},
141 {"tmac_bcst_frms"},
142 {"tmac_pause_ctrl_frms"},
bd1034f0
AR		 143 {"tmac_ttl_octets"},
144 {"tmac_ucst_frms"},
145 {"tmac_nucst_frms"},
1da177e4 146 {"tmac_any_err_frms"},
bd1034f0 147 {"tmac_ttl_less_fb_octets"},
1da177e4
LT		 148 {"tmac_vld_ip_octets"},
149 {"tmac_vld_ip"},
150 {"tmac_drop_ip"},
151 {"tmac_icmp"},
152 {"tmac_rst_tcp"},
153 {"tmac_tcp"},
154 {"tmac_udp"},
155 {"rmac_vld_frms"},
156 {"rmac_data_octets"},
157 {"rmac_fcs_err_frms"},
158 {"rmac_drop_frms"},
159 {"rmac_vld_mcst_frms"},
160 {"rmac_vld_bcst_frms"},
161 {"rmac_in_rng_len_err_frms"},
bd1034f0 162 {"rmac_out_rng_len_err_frms"},
1da177e4
LT		 163 {"rmac_long_frms"},
164 {"rmac_pause_ctrl_frms"},
bd1034f0
AR		 165 {"rmac_unsup_ctrl_frms"},
166 {"rmac_ttl_octets"},
167 {"rmac_accepted_ucst_frms"},
168 {"rmac_accepted_nucst_frms"},
1da177e4 169 {"rmac_discarded_frms"},
bd1034f0
AR		 170 {"rmac_drop_events"},
171 {"rmac_ttl_less_fb_octets"},
172 {"rmac_ttl_frms"},
1da177e4
LT		 173 {"rmac_usized_frms"},
174 {"rmac_osized_frms"},
175 {"rmac_frag_frms"},
176 {"rmac_jabber_frms"},
bd1034f0
AR		 177 {"rmac_ttl_64_frms"},
178 {"rmac_ttl_65_127_frms"},
179 {"rmac_ttl_128_255_frms"},
180 {"rmac_ttl_256_511_frms"},
181 {"rmac_ttl_512_1023_frms"},
182 {"rmac_ttl_1024_1518_frms"},
1da177e4
LT		 183 {"rmac_ip"},
184 {"rmac_ip_octets"},
185 {"rmac_hdr_err_ip"},
186 {"rmac_drop_ip"},
187 {"rmac_icmp"},
188 {"rmac_tcp"},
189 {"rmac_udp"},
190 {"rmac_err_drp_udp"},
bd1034f0
AR		 191 {"rmac_xgmii_err_sym"},
192 {"rmac_frms_q0"},
193 {"rmac_frms_q1"},
194 {"rmac_frms_q2"},
195 {"rmac_frms_q3"},
196 {"rmac_frms_q4"},
197 {"rmac_frms_q5"},
198 {"rmac_frms_q6"},
199 {"rmac_frms_q7"},
200 {"rmac_full_q0"},
201 {"rmac_full_q1"},
202 {"rmac_full_q2"},
203 {"rmac_full_q3"},
204 {"rmac_full_q4"},
205 {"rmac_full_q5"},
206 {"rmac_full_q6"},
207 {"rmac_full_q7"},
1da177e4 208 {"rmac_pause_cnt"},
bd1034f0
AR		 209 {"rmac_xgmii_data_err_cnt"},
210 {"rmac_xgmii_ctrl_err_cnt"},
1da177e4
LT		 211 {"rmac_accepted_ip"},
212 {"rmac_err_tcp"},
bd1034f0
AR		 213 {"rd_req_cnt"},
214 {"new_rd_req_cnt"},
215 {"new_rd_req_rtry_cnt"},
216 {"rd_rtry_cnt"},
217 {"wr_rtry_rd_ack_cnt"},
218 {"wr_req_cnt"},
219 {"new_wr_req_cnt"},
220 {"new_wr_req_rtry_cnt"},
221 {"wr_rtry_cnt"},
222 {"wr_disc_cnt"},
223 {"rd_rtry_wr_ack_cnt"},
224 {"txp_wr_cnt"},
225 {"txd_rd_cnt"},
226 {"txd_wr_cnt"},
227 {"rxd_rd_cnt"},
228 {"rxd_wr_cnt"},
229 {"txf_rd_cnt"},
fa1f0cb3
SS		 230 {"rxf_wr_cnt"}
231};
232
6fce365d 233static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
bd1034f0
AR		 234 {"rmac_ttl_1519_4095_frms"},
235 {"rmac_ttl_4096_8191_frms"},
236 {"rmac_ttl_8192_max_frms"},
237 {"rmac_ttl_gt_max_frms"},
238 {"rmac_osized_alt_frms"},
239 {"rmac_jabber_alt_frms"},
240 {"rmac_gt_max_alt_frms"},
241 {"rmac_vlan_frms"},
242 {"rmac_len_discard"},
243 {"rmac_fcs_discard"},
244 {"rmac_pf_discard"},
245 {"rmac_da_discard"},
246 {"rmac_red_discard"},
247 {"rmac_rts_discard"},
248 {"rmac_ingm_full_discard"},
fa1f0cb3
SS		 249 {"link_fault_cnt"}
250};
251
6fce365d 252static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
7ba013ac
K		 253 {"\n DRIVER STATISTICS"},
254 {"single_bit_ecc_errs"},
255 {"double_bit_ecc_errs"},
bd1034f0
AR		 256 {"parity_err_cnt"},
257 {"serious_err_cnt"},
258 {"soft_reset_cnt"},
259 {"fifo_full_cnt"},
8116f3cf
SS		 260 {"ring_0_full_cnt"},
261 {"ring_1_full_cnt"},
262 {"ring_2_full_cnt"},
263 {"ring_3_full_cnt"},
264 {"ring_4_full_cnt"},
265 {"ring_5_full_cnt"},
266 {"ring_6_full_cnt"},
267 {"ring_7_full_cnt"},
43b7c451
SH		 268 {"alarm_transceiver_temp_high"},
269 {"alarm_transceiver_temp_low"},
270 {"alarm_laser_bias_current_high"},
271 {"alarm_laser_bias_current_low"},
272 {"alarm_laser_output_power_high"},
273 {"alarm_laser_output_power_low"},
274 {"warn_transceiver_temp_high"},
275 {"warn_transceiver_temp_low"},
276 {"warn_laser_bias_current_high"},
277 {"warn_laser_bias_current_low"},
278 {"warn_laser_output_power_high"},
279 {"warn_laser_output_power_low"},
280 {"lro_aggregated_pkts"},
281 {"lro_flush_both_count"},
282 {"lro_out_of_sequence_pkts"},
283 {"lro_flush_due_to_max_pkts"},
284 {"lro_avg_aggr_pkts"},
285 {"mem_alloc_fail_cnt"},
286 {"pci_map_fail_cnt"},
287 {"watchdog_timer_cnt"},
288 {"mem_allocated"},
289 {"mem_freed"},
290 {"link_up_cnt"},
291 {"link_down_cnt"},
292 {"link_up_time"},
293 {"link_down_time"},
294 {"tx_tcode_buf_abort_cnt"},
295 {"tx_tcode_desc_abort_cnt"},
296 {"tx_tcode_parity_err_cnt"},
297 {"tx_tcode_link_loss_cnt"},
298 {"tx_tcode_list_proc_err_cnt"},
299 {"rx_tcode_parity_err_cnt"},
300 {"rx_tcode_abort_cnt"},
301 {"rx_tcode_parity_abort_cnt"},
302 {"rx_tcode_rda_fail_cnt"},
303 {"rx_tcode_unkn_prot_cnt"},
304 {"rx_tcode_fcs_err_cnt"},
305 {"rx_tcode_buf_size_err_cnt"},
306 {"rx_tcode_rxd_corrupt_cnt"},
307 {"rx_tcode_unkn_err_cnt"},
8116f3cf
SS		 308 {"tda_err_cnt"},
309 {"pfc_err_cnt"},
310 {"pcc_err_cnt"},
311 {"tti_err_cnt"},
312 {"tpa_err_cnt"},
313 {"sm_err_cnt"},
314 {"lso_err_cnt"},
315 {"mac_tmac_err_cnt"},
316 {"mac_rmac_err_cnt"},
317 {"xgxs_txgxs_err_cnt"},
318 {"xgxs_rxgxs_err_cnt"},
319 {"rc_err_cnt"},
320 {"prc_pcix_err_cnt"},
321 {"rpa_err_cnt"},
322 {"rda_err_cnt"},
323 {"rti_err_cnt"},
324 {"mc_err_cnt"}
1da177e4
LT		 325};
326
4c3616cd
AMR		 327#define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
328#define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
329#define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
fa1f0cb3
SS		 330
331#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
332#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
333
334#define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
335#define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
1da177e4 336
4c3616cd 337#define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
1da177e4
LT		 338#define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
339
25fff88e
K		 340#define S2IO_TIMER_CONF(timer, handle, arg, exp) \
341 init_timer(&timer); \
342 timer.function = handle; \
343 timer.data = (unsigned long) arg; \
344 mod_timer(&timer, (jiffies + exp)) \
345
2fd37688
SS		 346/* copy mac addr to def_mac_addr array */
347static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
348{
349 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
350 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
351 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
352 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
353 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
354 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
355}
04025095 356
be3a6b02
K		 357/* Add the vlan */
358static void s2io_vlan_rx_register(struct net_device *dev,
04025095 359 struct vlan_group *grp)
be3a6b02 360{
2fda096d 361 int i;
4cf1653a 362 struct s2io_nic *nic = netdev_priv(dev);
2fda096d
SR		 363 unsigned long flags[MAX_TX_FIFOS];
364 struct mac_info *mac_control = &nic->mac_control;
365 struct config_param *config = &nic->config;
366
13d866a9
JP		 367 for (i = 0; i < config->tx_fifo_num; i++) {
368 struct fifo_info *fifo = &mac_control->fifos[i];
369
370 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
371 }
be3a6b02 372
be3a6b02 373 nic->vlgrp = grp;
13d866a9
JP		 374
375 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
376 struct fifo_info *fifo = &mac_control->fifos[i];
377
378 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
379 }
be3a6b02
K		 380}
381
cdb5bf02 382/* Unregister the vlan */
04025095 383static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
cdb5bf02
SH		 384{
385 int i;
4cf1653a 386 struct s2io_nic *nic = netdev_priv(dev);
cdb5bf02
SH		 387 unsigned long flags[MAX_TX_FIFOS];
388 struct mac_info *mac_control = &nic->mac_control;
389 struct config_param *config = &nic->config;
390
13d866a9
JP		 391 for (i = 0; i < config->tx_fifo_num; i++) {
392 struct fifo_info *fifo = &mac_control->fifos[i];
393
394 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
395 }
cdb5bf02
SH		 396
397 if (nic->vlgrp)
398 vlan_group_set_device(nic->vlgrp, vid, NULL);
399
13d866a9
JP		 400 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
401 struct fifo_info *fifo = &mac_control->fifos[i];
402
403 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
404 }
cdb5bf02
SH		 405}
406
20346722 407/*
1da177e4
LT		 408 * Constants to be programmed into the Xena's registers, to configure
409 * the XAUI.
410 */
411
1da177e4 412#define END_SIGN 0x0
f71e1309 413static const u64 herc_act_dtx_cfg[] = {
541ae68f 414 /* Set address */
e960fc5c 415 0x8000051536750000ULL, 0x80000515367500E0ULL,
541ae68f 416 /* Write data */
e960fc5c 417 0x8000051536750004ULL, 0x80000515367500E4ULL,
541ae68f
K		 418 /* Set address */
419 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
420 /* Write data */
421 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
422 /* Set address */
e960fc5c 423 0x801205150D440000ULL, 0x801205150D4400E0ULL,
424 /* Write data */
425 0x801205150D440004ULL, 0x801205150D4400E4ULL,
426 /* Set address */
541ae68f
K		 427 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
428 /* Write data */
429 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
430 /* Done */
431 END_SIGN
432};
433
f71e1309 434static const u64 xena_dtx_cfg[] = {
c92ca04b 435 /* Set address */
1da177e4 436 0x8000051500000000ULL, 0x80000515000000E0ULL,
c92ca04b
AR		 437 /* Write data */
438 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
439 /* Set address */
440 0x8001051500000000ULL, 0x80010515000000E0ULL,
441 /* Write data */
442 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
443 /* Set address */
1da177e4 444 0x8002051500000000ULL, 0x80020515000000E0ULL,
c92ca04b
AR		 445 /* Write data */
446 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1da177e4
LT		 447 END_SIGN
448};
449
20346722 450/*
1da177e4
LT		 451 * Constants for Fixing the MacAddress problem seen mostly on
452 * Alpha machines.
453 */
f71e1309 454static const u64 fix_mac[] = {
1da177e4
LT		 455 0x0060000000000000ULL, 0x0060600000000000ULL,
456 0x0040600000000000ULL, 0x0000600000000000ULL,
457 0x0020600000000000ULL, 0x0060600000000000ULL,
458 0x0020600000000000ULL, 0x0060600000000000ULL,
459 0x0020600000000000ULL, 0x0060600000000000ULL,
460 0x0020600000000000ULL, 0x0060600000000000ULL,
461 0x0020600000000000ULL, 0x0060600000000000ULL,
462 0x0020600000000000ULL, 0x0060600000000000ULL,
463 0x0020600000000000ULL, 0x0060600000000000ULL,
464 0x0020600000000000ULL, 0x0060600000000000ULL,
465 0x0020600000000000ULL, 0x0060600000000000ULL,
466 0x0020600000000000ULL, 0x0060600000000000ULL,
467 0x0020600000000000ULL, 0x0000600000000000ULL,
468 0x0040600000000000ULL, 0x0060600000000000ULL,
469 END_SIGN
470};
471
b41477f3
AR		 472MODULE_LICENSE("GPL");
473MODULE_VERSION(DRV_VERSION);
474
475
1da177e4 476/* Module Loadable parameters. */
6cfc482b 477S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
b41477f3 478S2IO_PARM_INT(rx_ring_num, 1);
3a3d5756 479S2IO_PARM_INT(multiq, 0);
b41477f3
AR		 480S2IO_PARM_INT(rx_ring_mode, 1);
481S2IO_PARM_INT(use_continuous_tx_intrs, 1);
482S2IO_PARM_INT(rmac_pause_time, 0x100);
483S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
484S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
485S2IO_PARM_INT(shared_splits, 0);
486S2IO_PARM_INT(tmac_util_period, 5);
487S2IO_PARM_INT(rmac_util_period, 5);
b41477f3 488S2IO_PARM_INT(l3l4hdr_size, 128);
6cfc482b
SH		 489/* 0 is no steering, 1 is Priority steering, 2 is Default steering */
490S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
303bcb4b 491/* Frequency of Rx desc syncs expressed as power of 2 */
b41477f3 492S2IO_PARM_INT(rxsync_frequency, 3);
eccb8628 493/* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
8abc4d5b 494S2IO_PARM_INT(intr_type, 2);
7d3d0439 495/* Large receive offload feature */
43b7c451
SH		 496static unsigned int lro_enable;
497module_param_named(lro, lro_enable, uint, 0);
498
7d3d0439
RA		 499/* Max pkts to be aggregated by LRO at one time. If not specified,
500 * aggregation happens until we hit max IP pkt size(64K)
501 */
b41477f3 502S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
b41477f3 503S2IO_PARM_INT(indicate_max_pkts, 0);
db874e65
SS		 504
505S2IO_PARM_INT(napi, 1);
506S2IO_PARM_INT(ufo, 0);
926930b2 507S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
b41477f3
AR		 508
509static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
510 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
511static unsigned int rx_ring_sz[MAX_RX_RINGS] =
512 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
513static unsigned int rts_frm_len[MAX_RX_RINGS] =
514 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
515
516module_param_array(tx_fifo_len, uint, NULL, 0);
517module_param_array(rx_ring_sz, uint, NULL, 0);
518module_param_array(rts_frm_len, uint, NULL, 0);
1da177e4 519
20346722 520/*
1da177e4 521 * S2IO device table.
20346722 522 * This table lists all the devices that this driver supports.
1da177e4
LT		 523 */
524static struct pci_device_id s2io_tbl[] __devinitdata = {
525 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
526 PCI_ANY_ID, PCI_ANY_ID},
527 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
528 PCI_ANY_ID, PCI_ANY_ID},
529 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
20346722
K		 530 PCI_ANY_ID, PCI_ANY_ID},
531 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
532 PCI_ANY_ID, PCI_ANY_ID},
1da177e4
LT		 533 {0,}
534};
535
536MODULE_DEVICE_TABLE(pci, s2io_tbl);
537
d796fdb7
LV		 538static struct pci_error_handlers s2io_err_handler = {
539 .error_detected = s2io_io_error_detected,
540 .slot_reset = s2io_io_slot_reset,
541 .resume = s2io_io_resume,
542};
543
1da177e4
LT		 544static struct pci_driver s2io_driver = {
545 .name = "S2IO",
546 .id_table = s2io_tbl,
547 .probe = s2io_init_nic,
548 .remove = __devexit_p(s2io_rem_nic),
d796fdb7 549 .err_handler = &s2io_err_handler,
1da177e4
LT		 550};
551
552/* A simplifier macro used both by init and free shared_mem Fns(). */
553#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
554
3a3d5756
SH		 555/* netqueue manipulation helper functions */
556static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
557{
fd2ea0a7
DM		 558 if (!sp->config.multiq) {
559 int i;
560
3a3d5756
SH		 561 for (i = 0; i < sp->config.tx_fifo_num; i++)
562 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
3a3d5756 563 }
fd2ea0a7 564 netif_tx_stop_all_queues(sp->dev);
3a3d5756
SH		 565}
566
567static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
568{
fd2ea0a7 569 if (!sp->config.multiq)
3a3d5756
SH		 570 sp->mac_control.fifos[fifo_no].queue_state =
571 FIFO_QUEUE_STOP;
fd2ea0a7
DM		 572
573 netif_tx_stop_all_queues(sp->dev);
3a3d5756
SH		 574}
575
576static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
577{
fd2ea0a7
DM		 578 if (!sp->config.multiq) {
579 int i;
580
3a3d5756
SH		 581 for (i = 0; i < sp->config.tx_fifo_num; i++)
582 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
3a3d5756 583 }
fd2ea0a7 584 netif_tx_start_all_queues(sp->dev);
3a3d5756
SH		 585}
586
587static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
588{
fd2ea0a7 589 if (!sp->config.multiq)
3a3d5756
SH		 590 sp->mac_control.fifos[fifo_no].queue_state =
591 FIFO_QUEUE_START;
fd2ea0a7
DM		 592
593 netif_tx_start_all_queues(sp->dev);
3a3d5756
SH		 594}
595
596static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
597{
fd2ea0a7
DM		 598 if (!sp->config.multiq) {
599 int i;
600
3a3d5756
SH		 601 for (i = 0; i < sp->config.tx_fifo_num; i++)
602 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
3a3d5756 603 }
fd2ea0a7 604 netif_tx_wake_all_queues(sp->dev);
3a3d5756
SH		 605}
606
607static inline void s2io_wake_tx_queue(
608 struct fifo_info *fifo, int cnt, u8 multiq)
609{
610
3a3d5756
SH		 611 if (multiq) {
612 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
613 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
b19fa1fa 614 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
3a3d5756
SH		 615 if (netif_queue_stopped(fifo->dev)) {
616 fifo->queue_state = FIFO_QUEUE_START;
617 netif_wake_queue(fifo->dev);
618 }
619 }
620}
621
1da177e4
LT		 622/**
623 * init_shared_mem - Allocation and Initialization of Memory
624 * @nic: Device private variable.
20346722
K		 625 * Description: The function allocates all the memory areas shared
626 * between the NIC and the driver. This includes Tx descriptors,
1da177e4
LT		 627 * Rx descriptors and the statistics block.
628 */
629
630static int init_shared_mem(struct s2io_nic *nic)
631{
632 u32 size;
633 void *tmp_v_addr, *tmp_v_addr_next;
634 dma_addr_t tmp_p_addr, tmp_p_addr_next;
1ee6dd77 635 struct RxD_block *pre_rxd_blk = NULL;
372cc597 636 int i, j, blk_cnt;
1da177e4
LT		 637 int lst_size, lst_per_page;
638 struct net_device *dev = nic->dev;
8ae418cf 639 unsigned long tmp;
1ee6dd77 640 struct buffAdd *ba;
1da177e4 641
1ee6dd77 642 struct mac_info *mac_control;
1da177e4 643 struct config_param *config;
491976b2 644 unsigned long long mem_allocated = 0;
1da177e4
LT		 645
646 mac_control = &nic->mac_control;
647 config = &nic->config;
648
13d866a9 649 /* Allocation and initialization of TXDLs in FIFOs */
1da177e4
LT		 650 size = 0;
651 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 652 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
653
654 size += tx_cfg->fifo_len;
1da177e4
LT		 655 }
656 if (size > MAX_AVAILABLE_TXDS) {
b41477f3 657 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
0b1f7ebe 658 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
b41477f3 659 return -EINVAL;
1da177e4
LT		 660 }
661
2fda096d
SR		 662 size = 0;
663 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 664 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
665
666 size = tx_cfg->fifo_len;
2fda096d
SR		 667 /*
668 * Legal values are from 2 to 8192
669 */
670 if (size < 2) {
671 DBG_PRINT(ERR_DBG, "s2io: Invalid fifo len (%d)", size);
672 DBG_PRINT(ERR_DBG, "for fifo %d\n", i);
673 DBG_PRINT(ERR_DBG, "s2io: Legal values for fifo len"
674 "are 2 to 8192\n");
675 return -EINVAL;
676 }
677 }
678
1ee6dd77 679 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 680 lst_per_page = PAGE_SIZE / lst_size;
681
682 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 683 struct fifo_info *fifo = &mac_control->fifos[i];
684 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
685 int fifo_len = tx_cfg->fifo_len;
1ee6dd77 686 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
13d866a9
JP		 687
688 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
689 if (!fifo->list_info) {
0c61ed5f 690 DBG_PRINT(INFO_DBG,
1da177e4
LT		 691 "Malloc failed for list_info\n");
692 return -ENOMEM;
693 }
491976b2 694 mem_allocated += list_holder_size;
1da177e4
LT		 695 }
696 for (i = 0; i < config->tx_fifo_num; i++) {
697 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
698 lst_per_page);
13d866a9
JP		 699 struct fifo_info *fifo = &mac_control->fifos[i];
700 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
701
702 fifo->tx_curr_put_info.offset = 0;
703 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
704 fifo->tx_curr_get_info.offset = 0;
705 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
706 fifo->fifo_no = i;
707 fifo->nic = nic;
708 fifo->max_txds = MAX_SKB_FRAGS + 2;
709 fifo->dev = dev;
20346722 710
1da177e4
LT		 711 for (j = 0; j < page_num; j++) {
712 int k = 0;
713 dma_addr_t tmp_p;
714 void *tmp_v;
715 tmp_v = pci_alloc_consistent(nic->pdev,
716 PAGE_SIZE, &tmp_p);
717 if (!tmp_v) {
0c61ed5f 718 DBG_PRINT(INFO_DBG,
1da177e4 719 "pci_alloc_consistent ");
0c61ed5f 720 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
1da177e4
LT		 721 return -ENOMEM;
722 }
776bd20f 723 /* If we got a zero DMA address(can happen on
724 * certain platforms like PPC), reallocate.
725 * Store virtual address of page we don't want,
726 * to be freed later.
727 */
728 if (!tmp_p) {
729 mac_control->zerodma_virt_addr = tmp_v;
6aa20a22 730 DBG_PRINT(INIT_DBG,
776bd20f 731 "%s: Zero DMA address for TxDL. ", dev->name);
6aa20a22 732 DBG_PRINT(INIT_DBG,
6b4d617d 733 "Virtual address %p\n", tmp_v);
776bd20f 734 tmp_v = pci_alloc_consistent(nic->pdev,
735 PAGE_SIZE, &tmp_p);
736 if (!tmp_v) {
0c61ed5f 737 DBG_PRINT(INFO_DBG,
776bd20f 738 "pci_alloc_consistent ");
0c61ed5f 739 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
776bd20f 740 return -ENOMEM;
741 }
491976b2 742 mem_allocated += PAGE_SIZE;
776bd20f 743 }
1da177e4
LT		 744 while (k < lst_per_page) {
745 int l = (j * lst_per_page) + k;
13d866a9 746 if (l == tx_cfg->fifo_len)
20346722 747 break;
13d866a9 748 fifo->list_info[l].list_virt_addr =
1da177e4 749 tmp_v + (k * lst_size);
13d866a9 750 fifo->list_info[l].list_phy_addr =
1da177e4
LT		 751 tmp_p + (k * lst_size);
752 k++;
753 }
754 }
755 }
1da177e4 756
2fda096d 757 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 758 struct fifo_info *fifo = &mac_control->fifos[i];
759 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
760
761 size = tx_cfg->fifo_len;
762 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
763 if (!fifo->ufo_in_band_v)
2fda096d
SR		 764 return -ENOMEM;
765 mem_allocated += (size * sizeof(u64));
766 }
fed5eccd 767
1da177e4
LT		 768 /* Allocation and initialization of RXDs in Rings */
769 size = 0;
770 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 771 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
772 struct ring_info *ring = &mac_control->rings[i];
773
774 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
1da177e4 775 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
13d866a9 776 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ", i);
1da177e4
LT		 777 DBG_PRINT(ERR_DBG, "RxDs per Block");
778 return FAILURE;
779 }
13d866a9
JP		 780 size += rx_cfg->num_rxd;
781 ring->block_count = rx_cfg->num_rxd /
da6971d8 782 (rxd_count[nic->rxd_mode] + 1 );
13d866a9 783 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
1da177e4 784 }
da6971d8 785 if (nic->rxd_mode == RXD_MODE_1)
1ee6dd77 786 size = (size * (sizeof(struct RxD1)));
da6971d8 787 else
1ee6dd77 788 size = (size * (sizeof(struct RxD3)));
1da177e4
LT		 789
790 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 791 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
792 struct ring_info *ring = &mac_control->rings[i];
793
794 ring->rx_curr_get_info.block_index = 0;
795 ring->rx_curr_get_info.offset = 0;
796 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
797 ring->rx_curr_put_info.block_index = 0;
798 ring->rx_curr_put_info.offset = 0;
799 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
800 ring->nic = nic;
801 ring->ring_no = i;
802 ring->lro = lro_enable;
803
804 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
1da177e4
LT		 805 /* Allocating all the Rx blocks */
806 for (j = 0; j < blk_cnt; j++) {
1ee6dd77 807 struct rx_block_info *rx_blocks;
da6971d8
AR		 808 int l;
809
13d866a9 810 rx_blocks = &ring->rx_blocks[j];
da6971d8 811 size = SIZE_OF_BLOCK; //size is always page size
1da177e4
LT		 812 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
813 &tmp_p_addr);
814 if (tmp_v_addr == NULL) {
815 /*
20346722
K		 816 * In case of failure, free_shared_mem()
817 * is called, which should free any
818 * memory that was alloced till the
1da177e4
LT		 819 * failure happened.
820 */
da6971d8 821 rx_blocks->block_virt_addr = tmp_v_addr;
1da177e4
LT		 822 return -ENOMEM;
823 }
491976b2 824 mem_allocated += size;
1da177e4 825 memset(tmp_v_addr, 0, size);
4f870320
JP		 826
827 size = sizeof(struct rxd_info) *
828 rxd_count[nic->rxd_mode];
da6971d8
AR		 829 rx_blocks->block_virt_addr = tmp_v_addr;
830 rx_blocks->block_dma_addr = tmp_p_addr;
4f870320 831 rx_blocks->rxds = kmalloc(size, GFP_KERNEL);
372cc597
SS		 832 if (!rx_blocks->rxds)
833 return -ENOMEM;
4f870320 834 mem_allocated += size;
da6971d8
AR		 835 for (l=0; l<rxd_count[nic->rxd_mode];l++) {
836 rx_blocks->rxds[l].virt_addr =
837 rx_blocks->block_virt_addr +
838 (rxd_size[nic->rxd_mode] * l);
839 rx_blocks->rxds[l].dma_addr =
840 rx_blocks->block_dma_addr +
841 (rxd_size[nic->rxd_mode] * l);
842 }
1da177e4
LT		 843 }
844 /* Interlinking all Rx Blocks */
845 for (j = 0; j < blk_cnt; j++) {
13d866a9
JP		 846 int next = (j + 1) % blk_cnt;
847 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
848 tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
849 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
850 tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
1da177e4 851
1ee6dd77 852 pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
1da177e4
LT		 853 pre_rxd_blk->reserved_2_pNext_RxD_block =
854 (unsigned long) tmp_v_addr_next;
1da177e4
LT		 855 pre_rxd_blk->pNext_RxD_Blk_physical =
856 (u64) tmp_p_addr_next;
857 }
858 }
6d517a27 859 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 860 /*
861 * Allocation of Storages for buffer addresses in 2BUFF mode
862 * and the buffers as well.
863 */
864 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 865 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
866 struct ring_info *ring = &mac_control->rings[i];
867
868 blk_cnt = rx_cfg->num_rxd /
869 (rxd_count[nic->rxd_mode]+ 1);
4f870320
JP		 870 size = sizeof(struct buffAdd *) * blk_cnt;
871 ring->ba = kmalloc(size, GFP_KERNEL);
13d866a9 872 if (!ring->ba)
1da177e4 873 return -ENOMEM;
4f870320 874 mem_allocated += size;
da6971d8
AR		 875 for (j = 0; j < blk_cnt; j++) {
876 int k = 0;
4f870320
JP		 877
878 size = sizeof(struct buffAdd) *
879 (rxd_count[nic->rxd_mode] + 1);
880 ring->ba[j] = kmalloc(size, GFP_KERNEL);
13d866a9 881 if (!ring->ba[j])
1da177e4 882 return -ENOMEM;
4f870320 883 mem_allocated += size;
da6971d8 884 while (k != rxd_count[nic->rxd_mode]) {
13d866a9 885 ba = &ring->ba[j][k];
4f870320
JP		 886 size = BUF0_LEN + ALIGN_SIZE;
887 ba->ba_0_org = kmalloc(size, GFP_KERNEL);
da6971d8
AR		 888 if (!ba->ba_0_org)
889 return -ENOMEM;
4f870320 890 mem_allocated += size;
da6971d8
AR		 891 tmp = (unsigned long)ba->ba_0_org;
892 tmp += ALIGN_SIZE;
893 tmp &= ~((unsigned long) ALIGN_SIZE);
894 ba->ba_0 = (void *) tmp;
895
4f870320
JP		 896 size = BUF1_LEN + ALIGN_SIZE;
897 ba->ba_1_org = kmalloc(size, GFP_KERNEL);
da6971d8
AR		 898 if (!ba->ba_1_org)
899 return -ENOMEM;
4f870320 900 mem_allocated += size;
da6971d8
AR		 901 tmp = (unsigned long) ba->ba_1_org;
902 tmp += ALIGN_SIZE;
903 tmp &= ~((unsigned long) ALIGN_SIZE);
904 ba->ba_1 = (void *) tmp;
905 k++;
906 }
1da177e4
LT		 907 }
908 }
909 }
1da177e4
LT		 910
911 /* Allocation and initialization of Statistics block */
1ee6dd77 912 size = sizeof(struct stat_block);
1da177e4
LT		 913 mac_control->stats_mem = pci_alloc_consistent
914 (nic->pdev, size, &mac_control->stats_mem_phy);
915
916 if (!mac_control->stats_mem) {
20346722
K		 917 /*
918 * In case of failure, free_shared_mem() is called, which
919 * should free any memory that was alloced till the
1da177e4
LT		 920 * failure happened.
921 */
922 return -ENOMEM;
923 }
491976b2 924 mem_allocated += size;
1da177e4
LT		 925 mac_control->stats_mem_sz = size;
926
927 tmp_v_addr = mac_control->stats_mem;
1ee6dd77 928 mac_control->stats_info = (struct stat_block *) tmp_v_addr;
1da177e4 929 memset(tmp_v_addr, 0, size);
1da177e4
LT		 930 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
931 (unsigned long long) tmp_p_addr);
491976b2 932 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
1da177e4
LT		 933 return SUCCESS;
934}
935
20346722
K		 936/**
937 * free_shared_mem - Free the allocated Memory
1da177e4
LT		 938 * @nic: Device private variable.
939 * Description: This function is to free all memory locations allocated by
940 * the init_shared_mem() function and return it to the kernel.
941 */
942
943static void free_shared_mem(struct s2io_nic *nic)
944{
945 int i, j, blk_cnt, size;
946 void *tmp_v_addr;
947 dma_addr_t tmp_p_addr;
1ee6dd77 948 struct mac_info *mac_control;
1da177e4
LT		 949 struct config_param *config;
950 int lst_size, lst_per_page;
8910b49f 951 struct net_device *dev;
491976b2 952 int page_num = 0;
1da177e4
LT		 953
954 if (!nic)
955 return;
956
8910b49f
MG		 957 dev = nic->dev;
958
1da177e4
LT		 959 mac_control = &nic->mac_control;
960 config = &nic->config;
961
1ee6dd77 962 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 963 lst_per_page = PAGE_SIZE / lst_size;
964
965 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 966 struct fifo_info *fifo = &mac_control->fifos[i];
967 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
968
969 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
1da177e4
LT		 970 for (j = 0; j < page_num; j++) {
971 int mem_blks = (j * lst_per_page);
13d866a9
JP		 972 struct list_info_hold *fli;
973
974 if (!fifo->list_info)
6aa20a22 975 return;
13d866a9
JP		 976
977 fli = &fifo->list_info[mem_blks];
978 if (!fli->list_virt_addr)
1da177e4
LT		 979 break;
980 pci_free_consistent(nic->pdev, PAGE_SIZE,
13d866a9
JP		 981 fli->list_virt_addr,
982 fli->list_phy_addr);
8a4bdbaa 983 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 984 += PAGE_SIZE;
1da177e4 985 }
776bd20f 986 /* If we got a zero DMA address during allocation,
987 * free the page now
988 */
989 if (mac_control->zerodma_virt_addr) {
990 pci_free_consistent(nic->pdev, PAGE_SIZE,
991 mac_control->zerodma_virt_addr,
992 (dma_addr_t)0);
6aa20a22 993 DBG_PRINT(INIT_DBG,
6b4d617d
AM		 994 "%s: Freeing TxDL with zero DMA addr. ",
995 dev->name);
996 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
997 mac_control->zerodma_virt_addr);
8a4bdbaa 998 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 999 += PAGE_SIZE;
776bd20f 1000 }
13d866a9 1001 kfree(fifo->list_info);
8a4bdbaa 1002 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 1003 (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
1da177e4
LT		 1004 }
1005
1da177e4 1006 size = SIZE_OF_BLOCK;
1da177e4 1007 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1008 struct ring_info *ring = &mac_control->rings[i];
1009
1010 blk_cnt = ring->block_count;
1da177e4 1011 for (j = 0; j < blk_cnt; j++) {
13d866a9
JP		 1012 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
1013 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
1da177e4
LT		 1014 if (tmp_v_addr == NULL)
1015 break;
1016 pci_free_consistent(nic->pdev, size,
1017 tmp_v_addr, tmp_p_addr);
491976b2 1018 nic->mac_control.stats_info->sw_stat.mem_freed += size;
13d866a9 1019 kfree(ring->rx_blocks[j].rxds);
8a4bdbaa 1020 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 1021 ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
1da177e4
LT		 1022 }
1023 }
1024
6d517a27 1025 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 1026 /* Freeing buffer storage addresses in 2BUFF mode. */
1027 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1028 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1029 struct ring_info *ring = &mac_control->rings[i];
1030
1031 blk_cnt = rx_cfg->num_rxd /
1032 (rxd_count[nic->rxd_mode] + 1);
da6971d8
AR		 1033 for (j = 0; j < blk_cnt; j++) {
1034 int k = 0;
13d866a9 1035 if (!ring->ba[j])
da6971d8
AR		 1036 continue;
1037 while (k != rxd_count[nic->rxd_mode]) {
13d866a9 1038 struct buffAdd *ba = &ring->ba[j][k];
da6971d8 1039 kfree(ba->ba_0_org);
491976b2
SH		 1040 nic->mac_control.stats_info->sw_stat.\
1041 mem_freed += (BUF0_LEN + ALIGN_SIZE);
da6971d8 1042 kfree(ba->ba_1_org);
491976b2
SH		 1043 nic->mac_control.stats_info->sw_stat.\
1044 mem_freed += (BUF1_LEN + ALIGN_SIZE);
da6971d8
AR		 1045 k++;
1046 }
13d866a9 1047 kfree(ring->ba[j]);
9caab458
SS		 1048 nic->mac_control.stats_info->sw_stat.mem_freed +=
1049 (sizeof(struct buffAdd) *
1050 (rxd_count[nic->rxd_mode] + 1));
1da177e4 1051 }
13d866a9 1052 kfree(ring->ba);
8a4bdbaa 1053 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 1054 (sizeof(struct buffAdd *) * blk_cnt);
1da177e4 1055 }
1da177e4 1056 }
1da177e4 1057
2fda096d 1058 for (i = 0; i < nic->config.tx_fifo_num; i++) {
13d866a9
JP		 1059 struct fifo_info *fifo = &mac_control->fifos[i];
1060 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1061
1062 if (fifo->ufo_in_band_v) {
2fda096d 1063 nic->mac_control.stats_info->sw_stat.mem_freed
13d866a9
JP		 1064 += (tx_cfg->fifo_len * sizeof(u64));
1065 kfree(fifo->ufo_in_band_v);
2fda096d
SR		 1066 }
1067 }
1068
1da177e4 1069 if (mac_control->stats_mem) {
2fda096d
SR		 1070 nic->mac_control.stats_info->sw_stat.mem_freed +=
1071 mac_control->stats_mem_sz;
1da177e4
LT		 1072 pci_free_consistent(nic->pdev,
1073 mac_control->stats_mem_sz,
1074 mac_control->stats_mem,
1075 mac_control->stats_mem_phy);
491976b2 1076 }
1da177e4
LT		 1077}
1078
541ae68f
K		 1079/**
1080 * s2io_verify_pci_mode -
1081 */
1082
1ee6dd77 1083static int s2io_verify_pci_mode(struct s2io_nic *nic)
541ae68f 1084{
1ee6dd77 1085 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 1086 register u64 val64 = 0;
1087 int mode;
1088
1089 val64 = readq(&bar0->pci_mode);
1090 mode = (u8)GET_PCI_MODE(val64);
1091
1092 if ( val64 & PCI_MODE_UNKNOWN_MODE)
1093 return -1; /* Unknown PCI mode */
1094 return mode;
1095}
1096
c92ca04b
AR		 1097#define NEC_VENID 0x1033
1098#define NEC_DEVID 0x0125
1099static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1100{
1101 struct pci_dev *tdev = NULL;
26d36b64
AC		 1102 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1103 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
7ad62dbc 1104 if (tdev->bus == s2io_pdev->bus->parent) {
26d36b64 1105 pci_dev_put(tdev);
c92ca04b 1106 return 1;
7ad62dbc 1107 }
c92ca04b
AR		 1108 }
1109 }
1110 return 0;
1111}
541ae68f 1112
7b32a312 1113static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
541ae68f
K		 1114/**
1115 * s2io_print_pci_mode -
1116 */
1ee6dd77 1117static int s2io_print_pci_mode(struct s2io_nic *nic)
541ae68f 1118{
1ee6dd77 1119 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 1120 register u64 val64 = 0;
1121 int mode;
1122 struct config_param *config = &nic->config;
1123
1124 val64 = readq(&bar0->pci_mode);
1125 mode = (u8)GET_PCI_MODE(val64);
1126
1127 if ( val64 & PCI_MODE_UNKNOWN_MODE)
1128 return -1; /* Unknown PCI mode */
1129
c92ca04b
AR		 1130 config->bus_speed = bus_speed[mode];
1131
1132 if (s2io_on_nec_bridge(nic->pdev)) {
1133 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1134 nic->dev->name);
1135 return mode;
1136 }
1137
541ae68f
K		 1138 if (val64 & PCI_MODE_32_BITS) {
1139 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
1140 } else {
1141 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
1142 }
1143
1144 switch(mode) {
1145 case PCI_MODE_PCI_33:
1146 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
541ae68f
K		 1147 break;
1148 case PCI_MODE_PCI_66:
1149 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
541ae68f
K		 1150 break;
1151 case PCI_MODE_PCIX_M1_66:
1152 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
541ae68f
K		 1153 break;
1154 case PCI_MODE_PCIX_M1_100:
1155 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
541ae68f
K		 1156 break;
1157 case PCI_MODE_PCIX_M1_133:
1158 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
541ae68f
K		 1159 break;
1160 case PCI_MODE_PCIX_M2_66:
1161 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
541ae68f
K		 1162 break;
1163 case PCI_MODE_PCIX_M2_100:
1164 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
541ae68f
K		 1165 break;
1166 case PCI_MODE_PCIX_M2_133:
1167 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
541ae68f
K		 1168 break;
1169 default:
1170 return -1; /* Unsupported bus speed */
1171 }
1172
1173 return mode;
1174}
1175
b7c5678f
RV		 1176/**
1177 * init_tti - Initialization transmit traffic interrupt scheme
1178 * @nic: device private variable
1179 * @link: link status (UP/DOWN) used to enable/disable continuous
1180 * transmit interrupts
1181 * Description: The function configures transmit traffic interrupts
1182 * Return Value: SUCCESS on success and
1183 * '-1' on failure
1184 */
1185
0d66afe7 1186static int init_tti(struct s2io_nic *nic, int link)
b7c5678f
RV		 1187{
1188 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1189 register u64 val64 = 0;
1190 int i;
1191 struct config_param *config;
1192
1193 config = &nic->config;
1194
1195 for (i = 0; i < config->tx_fifo_num; i++) {
1196 /*
1197 * TTI Initialization. Default Tx timer gets us about
1198 * 250 interrupts per sec. Continuous interrupts are enabled
1199 * by default.
1200 */
1201 if (nic->device_type == XFRAME_II_DEVICE) {
1202 int count = (nic->config.bus_speed * 125)/2;
1203 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1204 } else
1205 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1206
1207 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1208 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1209 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1210 TTI_DATA1_MEM_TX_TIMER_AC_EN;
ac731ab6
SH		 1211 if (i == 0)
1212 if (use_continuous_tx_intrs && (link == LINK_UP))
1213 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
b7c5678f
RV		 1214 writeq(val64, &bar0->tti_data1_mem);
1215
ac731ab6
SH		 1216 if (nic->config.intr_type == MSI_X) {
1217 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1218 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1219 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1220 TTI_DATA2_MEM_TX_UFC_D(0x300);
1221 } else {
1222 if ((nic->config.tx_steering_type ==
1223 TX_DEFAULT_STEERING) &&
1224 (config->tx_fifo_num > 1) &&
1225 (i >= nic->udp_fifo_idx) &&
1226 (i < (nic->udp_fifo_idx +
1227 nic->total_udp_fifos)))
1228 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1229 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1230 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1231 TTI_DATA2_MEM_TX_UFC_D(0x120);
1232 else
1233 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1234 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1235 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1236 TTI_DATA2_MEM_TX_UFC_D(0x80);
1237 }
b7c5678f
RV		 1238
1239 writeq(val64, &bar0->tti_data2_mem);
1240
1241 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD |
1242 TTI_CMD_MEM_OFFSET(i);
1243 writeq(val64, &bar0->tti_command_mem);
1244
1245 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1246 TTI_CMD_MEM_STROBE_NEW_CMD, S2IO_BIT_RESET) != SUCCESS)
1247 return FAILURE;
1248 }
1249
1250 return SUCCESS;
1251}
1252
20346722
K		 1253/**
1254 * init_nic - Initialization of hardware
b7c5678f 1255 * @nic: device private variable
20346722
K		 1256 * Description: The function sequentially configures every block
1257 * of the H/W from their reset values.
1258 * Return Value: SUCCESS on success and
1da177e4
LT		 1259 * '-1' on failure (endian settings incorrect).
1260 */
1261
1262static int init_nic(struct s2io_nic *nic)
1263{
1ee6dd77 1264 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1265 struct net_device *dev = nic->dev;
1266 register u64 val64 = 0;
1267 void __iomem *add;
1268 u32 time;
1269 int i, j;
1ee6dd77 1270 struct mac_info *mac_control;
1da177e4 1271 struct config_param *config;
c92ca04b 1272 int dtx_cnt = 0;
1da177e4 1273 unsigned long long mem_share;
20346722 1274 int mem_size;
1da177e4
LT		 1275
1276 mac_control = &nic->mac_control;
1277 config = &nic->config;
1278
5e25b9dd 1279 /* to set the swapper controle on the card */
20346722 1280 if(s2io_set_swapper(nic)) {
1da177e4 1281 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
9f74ffde 1282 return -EIO;
1da177e4
LT		 1283 }
1284
541ae68f
K		 1285 /*
1286 * Herc requires EOI to be removed from reset before XGXS, so..
1287 */
1288 if (nic->device_type & XFRAME_II_DEVICE) {
1289 val64 = 0xA500000000ULL;
1290 writeq(val64, &bar0->sw_reset);
1291 msleep(500);
1292 val64 = readq(&bar0->sw_reset);
1293 }
1294
1da177e4
LT		 1295 /* Remove XGXS from reset state */
1296 val64 = 0;
1297 writeq(val64, &bar0->sw_reset);
1da177e4 1298 msleep(500);
20346722 1299 val64 = readq(&bar0->sw_reset);
1da177e4 1300
7962024e
SH		 1301 /* Ensure that it's safe to access registers by checking
1302 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1303 */
1304 if (nic->device_type == XFRAME_II_DEVICE) {
1305 for (i = 0; i < 50; i++) {
1306 val64 = readq(&bar0->adapter_status);
1307 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1308 break;
1309 msleep(10);
1310 }
1311 if (i == 50)
1312 return -ENODEV;
1313 }
1314
1da177e4
LT		 1315 /* Enable Receiving broadcasts */
1316 add = &bar0->mac_cfg;
1317 val64 = readq(&bar0->mac_cfg);
1318 val64 |= MAC_RMAC_BCAST_ENABLE;
1319 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1320 writel((u32) val64, add);
1321 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1322 writel((u32) (val64 >> 32), (add + 4));
1323
1324 /* Read registers in all blocks */
1325 val64 = readq(&bar0->mac_int_mask);
1326 val64 = readq(&bar0->mc_int_mask);
1327 val64 = readq(&bar0->xgxs_int_mask);
1328
1329 /* Set MTU */
1330 val64 = dev->mtu;
1331 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1332
541ae68f
K		 1333 if (nic->device_type & XFRAME_II_DEVICE) {
1334 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
303bcb4b 1335 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1da177e4 1336 &bar0->dtx_control, UF);
541ae68f
K		 1337 if (dtx_cnt & 0x1)
1338 msleep(1); /* Necessary!! */
1da177e4
LT		 1339 dtx_cnt++;
1340 }
541ae68f 1341 } else {
c92ca04b
AR		 1342 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1343 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1344 &bar0->dtx_control, UF);
1345 val64 = readq(&bar0->dtx_control);
1346 dtx_cnt++;
1da177e4
LT		 1347 }
1348 }
1349
1350 /* Tx DMA Initialization */
1351 val64 = 0;
1352 writeq(val64, &bar0->tx_fifo_partition_0);
1353 writeq(val64, &bar0->tx_fifo_partition_1);
1354 writeq(val64, &bar0->tx_fifo_partition_2);
1355 writeq(val64, &bar0->tx_fifo_partition_3);
1356
1357
1358 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 1359 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1360
1361 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1362 vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1da177e4
LT		 1363
1364 if (i == (config->tx_fifo_num - 1)) {
1365 if (i % 2 == 0)
1366 i++;
1367 }
1368
1369 switch (i) {
1370 case 1:
1371 writeq(val64, &bar0->tx_fifo_partition_0);
1372 val64 = 0;
b7c5678f 1373 j = 0;
1da177e4
LT		 1374 break;
1375 case 3:
1376 writeq(val64, &bar0->tx_fifo_partition_1);
1377 val64 = 0;
b7c5678f 1378 j = 0;
1da177e4
LT		 1379 break;
1380 case 5:
1381 writeq(val64, &bar0->tx_fifo_partition_2);
1382 val64 = 0;
b7c5678f 1383 j = 0;
1da177e4
LT		 1384 break;
1385 case 7:
1386 writeq(val64, &bar0->tx_fifo_partition_3);
b7c5678f
RV		 1387 val64 = 0;
1388 j = 0;
1389 break;
1390 default:
1391 j++;
1da177e4
LT		 1392 break;
1393 }
1394 }
1395
5e25b9dd
K		 1396 /*
1397 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1398 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1399 */
541ae68f 1400 if ((nic->device_type == XFRAME_I_DEVICE) &&
44c10138 1401 (nic->pdev->revision < 4))
5e25b9dd
K		 1402 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1403
1da177e4
LT		 1404 val64 = readq(&bar0->tx_fifo_partition_0);
1405 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1406 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1407
20346722
K		 1408 /*
1409 * Initialization of Tx_PA_CONFIG register to ignore packet
1da177e4
LT		 1410 * integrity checking.
1411 */
1412 val64 = readq(&bar0->tx_pa_cfg);
1413 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1414 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1415 writeq(val64, &bar0->tx_pa_cfg);
1416
1417 /* Rx DMA intialization. */
1418 val64 = 0;
1419 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1420 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1421
1422 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1da177e4
LT		 1423 }
1424 writeq(val64, &bar0->rx_queue_priority);
1425
20346722
K		 1426 /*
1427 * Allocating equal share of memory to all the
1da177e4
LT		 1428 * configured Rings.
1429 */
1430 val64 = 0;
541ae68f
K		 1431 if (nic->device_type & XFRAME_II_DEVICE)
1432 mem_size = 32;
1433 else
1434 mem_size = 64;
1435
1da177e4
LT		 1436 for (i = 0; i < config->rx_ring_num; i++) {
1437 switch (i) {
1438 case 0:
20346722
K		 1439 mem_share = (mem_size / config->rx_ring_num +
1440 mem_size % config->rx_ring_num);
1da177e4
LT		 1441 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1442 continue;
1443 case 1:
20346722 1444 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1445 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1446 continue;
1447 case 2:
20346722 1448 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1449 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1450 continue;
1451 case 3:
20346722 1452 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1453 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1454 continue;
1455 case 4:
20346722 1456 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1457 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1458 continue;
1459 case 5:
20346722 1460 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1461 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1462 continue;
1463 case 6:
20346722 1464 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1465 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1466 continue;
1467 case 7:
20346722 1468 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1469 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1470 continue;
1471 }
1472 }
1473 writeq(val64, &bar0->rx_queue_cfg);
1474
20346722 1475 /*
5e25b9dd 1476 * Filling Tx round robin registers
b7c5678f 1477 * as per the number of FIFOs for equal scheduling priority
1da177e4 1478 */
5e25b9dd
K		 1479 switch (config->tx_fifo_num) {
1480 case 1:
b7c5678f 1481 val64 = 0x0;
5e25b9dd
K		 1482 writeq(val64, &bar0->tx_w_round_robin_0);
1483 writeq(val64, &bar0->tx_w_round_robin_1);
1484 writeq(val64, &bar0->tx_w_round_robin_2);
1485 writeq(val64, &bar0->tx_w_round_robin_3);
1486 writeq(val64, &bar0->tx_w_round_robin_4);
1487 break;
1488 case 2:
b7c5678f 1489 val64 = 0x0001000100010001ULL;
5e25b9dd 1490 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1491 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1492 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1493 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1494 val64 = 0x0001000100000000ULL;
5e25b9dd
K		 1495 writeq(val64, &bar0->tx_w_round_robin_4);
1496 break;
1497 case 3:
b7c5678f 1498 val64 = 0x0001020001020001ULL;
5e25b9dd 1499 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1500 val64 = 0x0200010200010200ULL;
5e25b9dd 1501 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1502 val64 = 0x0102000102000102ULL;
5e25b9dd 1503 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1504 val64 = 0x0001020001020001ULL;
5e25b9dd 1505 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1506 val64 = 0x0200010200000000ULL;
5e25b9dd
K		 1507 writeq(val64, &bar0->tx_w_round_robin_4);
1508 break;
1509 case 4:
b7c5678f 1510 val64 = 0x0001020300010203ULL;
5e25b9dd 1511 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1512 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1513 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1514 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1515 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1516 writeq(val64, &bar0->tx_w_round_robin_4);
1517 break;
1518 case 5:
b7c5678f 1519 val64 = 0x0001020304000102ULL;
5e25b9dd 1520 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1521 val64 = 0x0304000102030400ULL;
5e25b9dd 1522 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1523 val64 = 0x0102030400010203ULL;
5e25b9dd 1524 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1525 val64 = 0x0400010203040001ULL;
5e25b9dd 1526 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1527 val64 = 0x0203040000000000ULL;
5e25b9dd
K		 1528 writeq(val64, &bar0->tx_w_round_robin_4);
1529 break;
1530 case 6:
b7c5678f 1531 val64 = 0x0001020304050001ULL;
5e25b9dd 1532 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1533 val64 = 0x0203040500010203ULL;
5e25b9dd 1534 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1535 val64 = 0x0405000102030405ULL;
5e25b9dd 1536 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1537 val64 = 0x0001020304050001ULL;
5e25b9dd 1538 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1539 val64 = 0x0203040500000000ULL;
5e25b9dd
K		 1540 writeq(val64, &bar0->tx_w_round_robin_4);
1541 break;
1542 case 7:
b7c5678f 1543 val64 = 0x0001020304050600ULL;
5e25b9dd 1544 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1545 val64 = 0x0102030405060001ULL;
5e25b9dd 1546 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1547 val64 = 0x0203040506000102ULL;
5e25b9dd 1548 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1549 val64 = 0x0304050600010203ULL;
5e25b9dd 1550 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1551 val64 = 0x0405060000000000ULL;
5e25b9dd
K		 1552 writeq(val64, &bar0->tx_w_round_robin_4);
1553 break;
1554 case 8:
b7c5678f 1555 val64 = 0x0001020304050607ULL;
5e25b9dd 1556 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1557 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1558 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1559 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1560 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1561 writeq(val64, &bar0->tx_w_round_robin_4);
1562 break;
1563 }
1564
b41477f3 1565 /* Enable all configured Tx FIFO partitions */
5d3213cc
AR		 1566 val64 = readq(&bar0->tx_fifo_partition_0);
1567 val64 |= (TX_FIFO_PARTITION_EN);
1568 writeq(val64, &bar0->tx_fifo_partition_0);
1569
5e25b9dd 1570 /* Filling the Rx round robin registers as per the
0425b46a
SH		 1571 * number of Rings and steering based on QoS with
1572 * equal priority.
1573 */
5e25b9dd
K		 1574 switch (config->rx_ring_num) {
1575 case 1:
0425b46a
SH		 1576 val64 = 0x0;
1577 writeq(val64, &bar0->rx_w_round_robin_0);
1578 writeq(val64, &bar0->rx_w_round_robin_1);
1579 writeq(val64, &bar0->rx_w_round_robin_2);
1580 writeq(val64, &bar0->rx_w_round_robin_3);
1581 writeq(val64, &bar0->rx_w_round_robin_4);
1582
5e25b9dd
K		 1583 val64 = 0x8080808080808080ULL;
1584 writeq(val64, &bar0->rts_qos_steering);
1585 break;
1586 case 2:
0425b46a 1587 val64 = 0x0001000100010001ULL;
5e25b9dd 1588 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1589 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1590 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1591 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1592 val64 = 0x0001000100000000ULL;
5e25b9dd
K		 1593 writeq(val64, &bar0->rx_w_round_robin_4);
1594
1595 val64 = 0x8080808040404040ULL;
1596 writeq(val64, &bar0->rts_qos_steering);
1597 break;
1598 case 3:
0425b46a 1599 val64 = 0x0001020001020001ULL;
5e25b9dd 1600 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1601 val64 = 0x0200010200010200ULL;
5e25b9dd 1602 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1603 val64 = 0x0102000102000102ULL;
5e25b9dd 1604 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1605 val64 = 0x0001020001020001ULL;
5e25b9dd 1606 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1607 val64 = 0x0200010200000000ULL;
5e25b9dd
K		 1608 writeq(val64, &bar0->rx_w_round_robin_4);
1609
1610 val64 = 0x8080804040402020ULL;
1611 writeq(val64, &bar0->rts_qos_steering);
1612 break;
1613 case 4:
0425b46a 1614 val64 = 0x0001020300010203ULL;
5e25b9dd 1615 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1616 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1617 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1618 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1619 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1620 writeq(val64, &bar0->rx_w_round_robin_4);
1621
1622 val64 = 0x8080404020201010ULL;
1623 writeq(val64, &bar0->rts_qos_steering);
1624 break;
1625 case 5:
0425b46a 1626 val64 = 0x0001020304000102ULL;
5e25b9dd 1627 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1628 val64 = 0x0304000102030400ULL;
5e25b9dd 1629 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1630 val64 = 0x0102030400010203ULL;
5e25b9dd 1631 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1632 val64 = 0x0400010203040001ULL;
5e25b9dd 1633 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1634 val64 = 0x0203040000000000ULL;
5e25b9dd
K		 1635 writeq(val64, &bar0->rx_w_round_robin_4);
1636
1637 val64 = 0x8080404020201008ULL;
1638 writeq(val64, &bar0->rts_qos_steering);
1639 break;
1640 case 6:
0425b46a 1641 val64 = 0x0001020304050001ULL;
5e25b9dd 1642 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1643 val64 = 0x0203040500010203ULL;
5e25b9dd 1644 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1645 val64 = 0x0405000102030405ULL;
5e25b9dd 1646 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1647 val64 = 0x0001020304050001ULL;
5e25b9dd 1648 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1649 val64 = 0x0203040500000000ULL;
5e25b9dd
K		 1650 writeq(val64, &bar0->rx_w_round_robin_4);
1651
1652 val64 = 0x8080404020100804ULL;
1653 writeq(val64, &bar0->rts_qos_steering);
1654 break;
1655 case 7:
0425b46a 1656 val64 = 0x0001020304050600ULL;
5e25b9dd 1657 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1658 val64 = 0x0102030405060001ULL;
5e25b9dd 1659 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1660 val64 = 0x0203040506000102ULL;
5e25b9dd 1661 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1662 val64 = 0x0304050600010203ULL;
5e25b9dd 1663 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1664 val64 = 0x0405060000000000ULL;
5e25b9dd
K		 1665 writeq(val64, &bar0->rx_w_round_robin_4);
1666
1667 val64 = 0x8080402010080402ULL;
1668 writeq(val64, &bar0->rts_qos_steering);
1669 break;
1670 case 8:
0425b46a 1671 val64 = 0x0001020304050607ULL;
5e25b9dd 1672 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1673 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1674 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1675 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1676 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1677 writeq(val64, &bar0->rx_w_round_robin_4);
1678
1679 val64 = 0x8040201008040201ULL;
1680 writeq(val64, &bar0->rts_qos_steering);
1681 break;
1682 }
1da177e4
LT		 1683
1684 /* UDP Fix */
1685 val64 = 0;
20346722 1686 for (i = 0; i < 8; i++)
1da177e4
LT		 1687 writeq(val64, &bar0->rts_frm_len_n[i]);
1688
5e25b9dd
K		 1689 /* Set the default rts frame length for the rings configured */
1690 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1691 for (i = 0 ; i < config->rx_ring_num ; i++)
1692 writeq(val64, &bar0->rts_frm_len_n[i]);
1693
1694 /* Set the frame length for the configured rings
1695 * desired by the user
1696 */
1697 for (i = 0; i < config->rx_ring_num; i++) {
1698 /* If rts_frm_len[i] == 0 then it is assumed that user not
1699 * specified frame length steering.
1700 * If the user provides the frame length then program
1701 * the rts_frm_len register for those values or else
1702 * leave it as it is.
1703 */
1704 if (rts_frm_len[i] != 0) {
1705 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1706 &bar0->rts_frm_len_n[i]);
1707 }
1708 }
8a4bdbaa 1709
9fc93a41
SS		 1710 /* Disable differentiated services steering logic */
1711 for (i = 0; i < 64; i++) {
1712 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1713 DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1714 dev->name);
1715 DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
9f74ffde 1716 return -ENODEV;
9fc93a41
SS		 1717 }
1718 }
1719
20346722 1720 /* Program statistics memory */
1da177e4 1721 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1da177e4 1722
541ae68f
K		 1723 if (nic->device_type == XFRAME_II_DEVICE) {
1724 val64 = STAT_BC(0x320);
1725 writeq(val64, &bar0->stat_byte_cnt);
1726 }
1727
20346722 1728 /*
1da177e4
LT		 1729 * Initializing the sampling rate for the device to calculate the
1730 * bandwidth utilization.
1731 */
1732 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1733 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1734 writeq(val64, &bar0->mac_link_util);
1735
20346722
K		 1736 /*
1737 * Initializing the Transmit and Receive Traffic Interrupt
1da177e4
LT		 1738 * Scheme.
1739 */
1da177e4 1740
b7c5678f
RV		 1741 /* Initialize TTI */
1742 if (SUCCESS != init_tti(nic, nic->last_link_state))
1743 return -ENODEV;
1da177e4 1744
8a4bdbaa
SS		 1745 /* RTI Initialization */
1746 if (nic->device_type == XFRAME_II_DEVICE) {
541ae68f 1747 /*
8a4bdbaa
SS		 1748 * Programmed to generate Apprx 500 Intrs per
1749 * second
1750 */
1751 int count = (nic->config.bus_speed * 125)/4;
1752 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1753 } else
1754 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1755 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1756 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1757 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1758
1759 writeq(val64, &bar0->rti_data1_mem);
1760
1761 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1762 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1763 if (nic->config.intr_type == MSI_X)
1764 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1765 RTI_DATA2_MEM_RX_UFC_D(0x40));
1766 else
1767 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1768 RTI_DATA2_MEM_RX_UFC_D(0x80));
1769 writeq(val64, &bar0->rti_data2_mem);
1da177e4 1770
8a4bdbaa
SS		 1771 for (i = 0; i < config->rx_ring_num; i++) {
1772 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1773 | RTI_CMD_MEM_OFFSET(i);
1774 writeq(val64, &bar0->rti_command_mem);
1da177e4 1775
8a4bdbaa
SS		 1776 /*
1777 * Once the operation completes, the Strobe bit of the
1778 * command register will be reset. We poll for this
1779 * particular condition. We wait for a maximum of 500ms
1780 * for the operation to complete, if it's not complete
1781 * by then we return error.
1782 */
1783 time = 0;
f957bcf0 1784 while (true) {
8a4bdbaa
SS		 1785 val64 = readq(&bar0->rti_command_mem);
1786 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1787 break;
b6e3f982 1788
8a4bdbaa
SS		 1789 if (time > 10) {
1790 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1791 dev->name);
9f74ffde 1792 return -ENODEV;
b6e3f982 1793 }
8a4bdbaa
SS		 1794 time++;
1795 msleep(50);
1da177e4 1796 }
1da177e4
LT		 1797 }
1798
20346722
K		 1799 /*
1800 * Initializing proper values as Pause threshold into all
1da177e4
LT		 1801 * the 8 Queues on Rx side.
1802 */
1803 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1804 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1805
1806 /* Disable RMAC PAD STRIPPING */
509a2671 1807 add = &bar0->mac_cfg;
1da177e4
LT		 1808 val64 = readq(&bar0->mac_cfg);
1809 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1810 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1811 writel((u32) (val64), add);
1812 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1813 writel((u32) (val64 >> 32), (add + 4));
1814 val64 = readq(&bar0->mac_cfg);
1815
7d3d0439
RA		 1816 /* Enable FCS stripping by adapter */
1817 add = &bar0->mac_cfg;
1818 val64 = readq(&bar0->mac_cfg);
1819 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1820 if (nic->device_type == XFRAME_II_DEVICE)
1821 writeq(val64, &bar0->mac_cfg);
1822 else {
1823 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1824 writel((u32) (val64), add);
1825 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1826 writel((u32) (val64 >> 32), (add + 4));
1827 }
1828
20346722
K		 1829 /*
1830 * Set the time value to be inserted in the pause frame
1da177e4
LT		 1831 * generated by xena.
1832 */
1833 val64 = readq(&bar0->rmac_pause_cfg);
1834 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1835 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1836 writeq(val64, &bar0->rmac_pause_cfg);
1837
20346722 1838 /*
1da177e4
LT		 1839 * Set the Threshold Limit for Generating the pause frame
1840 * If the amount of data in any Queue exceeds ratio of
1841 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1842 * pause frame is generated
1843 */
1844 val64 = 0;
1845 for (i = 0; i < 4; i++) {
1846 val64 |=
1847 (((u64) 0xFF00 | nic->mac_control.
1848 mc_pause_threshold_q0q3)
1849 << (i * 2 * 8));
1850 }
1851 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1852
1853 val64 = 0;
1854 for (i = 0; i < 4; i++) {
1855 val64 |=
1856 (((u64) 0xFF00 | nic->mac_control.
1857 mc_pause_threshold_q4q7)
1858 << (i * 2 * 8));
1859 }
1860 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1861
20346722
K		 1862 /*
1863 * TxDMA will stop Read request if the number of read split has
1da177e4
LT		 1864 * exceeded the limit pointed by shared_splits
1865 */
1866 val64 = readq(&bar0->pic_control);
1867 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1868 writeq(val64, &bar0->pic_control);
1869
863c11a9
AR		 1870 if (nic->config.bus_speed == 266) {
1871 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1872 writeq(0x0, &bar0->read_retry_delay);
1873 writeq(0x0, &bar0->write_retry_delay);
1874 }
1875
541ae68f
K		 1876 /*
1877 * Programming the Herc to split every write transaction
1878 * that does not start on an ADB to reduce disconnects.
1879 */
1880 if (nic->device_type == XFRAME_II_DEVICE) {
19a60522
SS		 1881 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1882 MISC_LINK_STABILITY_PRD(3);
863c11a9
AR		 1883 writeq(val64, &bar0->misc_control);
1884 val64 = readq(&bar0->pic_control2);
b7b5a128 1885 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
863c11a9 1886 writeq(val64, &bar0->pic_control2);
541ae68f 1887 }
c92ca04b
AR		 1888 if (strstr(nic->product_name, "CX4")) {
1889 val64 = TMAC_AVG_IPG(0x17);
1890 writeq(val64, &bar0->tmac_avg_ipg);
a371a07d
K		 1891 }
1892
1da177e4
LT		 1893 return SUCCESS;
1894}
a371a07d
K		 1895#define LINK_UP_DOWN_INTERRUPT 1
1896#define MAC_RMAC_ERR_TIMER 2
1897
1ee6dd77 1898static int s2io_link_fault_indication(struct s2io_nic *nic)
a371a07d
K		 1899{
1900 if (nic->device_type == XFRAME_II_DEVICE)
1901 return LINK_UP_DOWN_INTERRUPT;
1902 else
1903 return MAC_RMAC_ERR_TIMER;
1904}
8116f3cf 1905
9caab458
SS		 1906/**
1907 * do_s2io_write_bits - update alarm bits in alarm register
1908 * @value: alarm bits
1909 * @flag: interrupt status
1910 * @addr: address value
1911 * Description: update alarm bits in alarm register
1912 * Return Value:
1913 * NONE.
1914 */
1915static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1916{
1917 u64 temp64;
1918
1919 temp64 = readq(addr);
1920
1921 if(flag == ENABLE_INTRS)
1922 temp64 &= ~((u64) value);
1923 else
1924 temp64 |= ((u64) value);
1925 writeq(temp64, addr);
1926}
1da177e4 1927
43b7c451 1928static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
9caab458
SS		 1929{
1930 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1931 register u64 gen_int_mask = 0;
01e16faa 1932 u64 interruptible;
9caab458 1933
01e16faa 1934 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
9caab458
SS		 1935 if (mask & TX_DMA_INTR) {
1936
1937 gen_int_mask |= TXDMA_INT_M;
1938
1939 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1940 TXDMA_PCC_INT | TXDMA_TTI_INT |
1941 TXDMA_LSO_INT | TXDMA_TPA_INT |
1942 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1943
1944 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1945 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1946 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1947 &bar0->pfc_err_mask);
1948
1949 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1950 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1951 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1952
1953 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1954 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1955 PCC_N_SERR | PCC_6_COF_OV_ERR |
1956 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1957 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1958 PCC_TXB_ECC_SG_ERR, flag, &bar0->pcc_err_mask);
1959
1960 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1961 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1962
1963 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1964 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1965 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1966 flag, &bar0->lso_err_mask);
1967
1968 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1969 flag, &bar0->tpa_err_mask);
1970
1971 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1972
1973 }
1974
1975 if (mask & TX_MAC_INTR) {
1976 gen_int_mask |= TXMAC_INT_M;
1977 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1978 &bar0->mac_int_mask);
1979 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1980 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1981 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1982 flag, &bar0->mac_tmac_err_mask);
1983 }
1984
1985 if (mask & TX_XGXS_INTR) {
1986 gen_int_mask |= TXXGXS_INT_M;
1987 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1988 &bar0->xgxs_int_mask);
1989 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1990 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1991 flag, &bar0->xgxs_txgxs_err_mask);
1992 }
1993
1994 if (mask & RX_DMA_INTR) {
1995 gen_int_mask |= RXDMA_INT_M;
1996 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1997 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1998 flag, &bar0->rxdma_int_mask);
1999 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
2000 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
2001 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
2002 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
2003 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
2004 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
2005 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
2006 &bar0->prc_pcix_err_mask);
2007 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
2008 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
2009 &bar0->rpa_err_mask);
2010 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
2011 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
2012 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
2013 RDA_FRM_ECC_SG_ERR | RDA_MISC_ERR|RDA_PCIX_ERR,
2014 flag, &bar0->rda_err_mask);
2015 do_s2io_write_bits(RTI_SM_ERR_ALARM |
2016 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2017 flag, &bar0->rti_err_mask);
2018 }
2019
2020 if (mask & RX_MAC_INTR) {
2021 gen_int_mask |= RXMAC_INT_M;
2022 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
2023 &bar0->mac_int_mask);
01e16faa 2024 interruptible = RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
9caab458 2025 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
01e16faa
SH		 2026 RMAC_DOUBLE_ECC_ERR;
2027 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2028 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2029 do_s2io_write_bits(interruptible,
9caab458
SS		 2030 flag, &bar0->mac_rmac_err_mask);
2031 }
2032
2033 if (mask & RX_XGXS_INTR)
2034 {
2035 gen_int_mask |= RXXGXS_INT_M;
2036 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
2037 &bar0->xgxs_int_mask);
2038 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
2039 &bar0->xgxs_rxgxs_err_mask);
2040 }
2041
2042 if (mask & MC_INTR) {
2043 gen_int_mask |= MC_INT_M;
2044 do_s2io_write_bits(MC_INT_MASK_MC_INT, flag, &bar0->mc_int_mask);
2045 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
2046 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2047 &bar0->mc_err_mask);
2048 }
2049 nic->general_int_mask = gen_int_mask;
2050
2051 /* Remove this line when alarm interrupts are enabled */
2052 nic->general_int_mask = 0;
2053}
20346722
K		 2054/**
2055 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1da177e4
LT		 2056 * @nic: device private variable,
2057 * @mask: A mask indicating which Intr block must be modified and,
2058 * @flag: A flag indicating whether to enable or disable the Intrs.
2059 * Description: This function will either disable or enable the interrupts
20346722
K		 2060 * depending on the flag argument. The mask argument can be used to
2061 * enable/disable any Intr block.
1da177e4
LT		 2062 * Return Value: NONE.
2063 */
2064
2065static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2066{
1ee6dd77 2067 struct XENA_dev_config __iomem *bar0 = nic->bar0;
9caab458
SS		 2068 register u64 temp64 = 0, intr_mask = 0;
2069
2070 intr_mask = nic->general_int_mask;
1da177e4
LT		 2071
2072 /* Top level interrupt classification */
2073 /* PIC Interrupts */
9caab458 2074 if (mask & TX_PIC_INTR) {
1da177e4 2075 /* Enable PIC Intrs in the general intr mask register */
9caab458 2076 intr_mask |= TXPIC_INT_M;
1da177e4 2077 if (flag == ENABLE_INTRS) {
20346722 2078 /*
a371a07d 2079 * If Hercules adapter enable GPIO otherwise
b41477f3 2080 * disable all PCIX, Flash, MDIO, IIC and GPIO
20346722
K		 2081 * interrupts for now.
2082 * TODO
1da177e4 2083 */
a371a07d
K		 2084 if (s2io_link_fault_indication(nic) ==
2085 LINK_UP_DOWN_INTERRUPT ) {
9caab458
SS		 2086 do_s2io_write_bits(PIC_INT_GPIO, flag,
2087 &bar0->pic_int_mask);
2088 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2089 &bar0->gpio_int_mask);
2090 } else
a371a07d 2091 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4 2092 } else if (flag == DISABLE_INTRS) {
20346722
K		 2093 /*
2094 * Disable PIC Intrs in the general
2095 * intr mask register
1da177e4
LT		 2096 */
2097 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4
LT		 2098 }
2099 }
2100
1da177e4
LT		 2101 /* Tx traffic interrupts */
2102 if (mask & TX_TRAFFIC_INTR) {
9caab458 2103 intr_mask |= TXTRAFFIC_INT_M;
1da177e4 2104 if (flag == ENABLE_INTRS) {
20346722 2105 /*
1da177e4 2106 * Enable all the Tx side interrupts
20346722 2107 * writing 0 Enables all 64 TX interrupt levels
1da177e4
LT		 2108 */
2109 writeq(0x0, &bar0->tx_traffic_mask);
2110 } else if (flag == DISABLE_INTRS) {
20346722
K		 2111 /*
2112 * Disable Tx Traffic Intrs in the general intr mask
1da177e4
LT		 2113 * register.
2114 */
2115 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1da177e4
LT		 2116 }
2117 }
2118
2119 /* Rx traffic interrupts */
2120 if (mask & RX_TRAFFIC_INTR) {
9caab458 2121 intr_mask |= RXTRAFFIC_INT_M;
1da177e4 2122 if (flag == ENABLE_INTRS) {
1da177e4
LT		 2123 /* writing 0 Enables all 8 RX interrupt levels */
2124 writeq(0x0, &bar0->rx_traffic_mask);
2125 } else if (flag == DISABLE_INTRS) {
20346722
K		 2126 /*
2127 * Disable Rx Traffic Intrs in the general intr mask
1da177e4
LT		 2128 * register.
2129 */
2130 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1da177e4
LT		 2131 }
2132 }
9caab458
SS		 2133
2134 temp64 = readq(&bar0->general_int_mask);
2135 if (flag == ENABLE_INTRS)
2136 temp64 &= ~((u64) intr_mask);
2137 else
2138 temp64 = DISABLE_ALL_INTRS;
2139 writeq(temp64, &bar0->general_int_mask);
2140
2141 nic->general_int_mask = readq(&bar0->general_int_mask);
1da177e4
LT		 2142}
2143
19a60522
SS		 2144/**
2145 * verify_pcc_quiescent- Checks for PCC quiescent state
2146 * Return: 1 If PCC is quiescence
2147 * 0 If PCC is not quiescence
2148 */
1ee6dd77 2149static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
20346722 2150{
19a60522 2151 int ret = 0, herc;
1ee6dd77 2152 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522 2153 u64 val64 = readq(&bar0->adapter_status);
8a4bdbaa 2154
19a60522 2155 herc = (sp->device_type == XFRAME_II_DEVICE);
20346722 2156
f957bcf0 2157 if (flag == false) {
44c10138 2158 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
19a60522 2159 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2160 ret = 1;
19a60522
SS		 2161 } else {
2162 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2163 ret = 1;
20346722
K		 2164 }
2165 } else {
44c10138 2166 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
5e25b9dd 2167 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
19a60522 2168 ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2169 ret = 1;
5e25b9dd
K		 2170 } else {
2171 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
19a60522 2172 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2173 ret = 1;
20346722
K		 2174 }
2175 }
2176
2177 return ret;
2178}
2179/**
2180 * verify_xena_quiescence - Checks whether the H/W is ready
1da177e4 2181 * Description: Returns whether the H/W is ready to go or not. Depending
20346722 2182 * on whether adapter enable bit was written or not the comparison
1da177e4
LT		 2183 * differs and the calling function passes the input argument flag to
2184 * indicate this.
20346722 2185 * Return: 1 If xena is quiescence
1da177e4
LT		 2186 * 0 If Xena is not quiescence
2187 */
2188
1ee6dd77 2189static int verify_xena_quiescence(struct s2io_nic *sp)
1da177e4 2190{
19a60522 2191 int mode;
1ee6dd77 2192 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 2193 u64 val64 = readq(&bar0->adapter_status);
2194 mode = s2io_verify_pci_mode(sp);
1da177e4 2195
19a60522
SS		 2196 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2197 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
2198 return 0;
2199 }
2200 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2201 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
2202 return 0;
2203 }
2204 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2205 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
2206 return 0;
2207 }
2208 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2209 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
2210 return 0;
2211 }
2212 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2213 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
2214 return 0;
2215 }
2216 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2217 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
2218 return 0;
2219 }
2220 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2221 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
2222 return 0;
2223 }
2224 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2225 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
2226 return 0;
1da177e4
LT		 2227 }
2228
19a60522
SS		 2229 /*
2230 * In PCI 33 mode, the P_PLL is not used, and therefore,
2231 * the the P_PLL_LOCK bit in the adapter_status register will
2232 * not be asserted.
2233 */
2234 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2235 sp->device_type == XFRAME_II_DEVICE && mode !=
2236 PCI_MODE_PCI_33) {
2237 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
2238 return 0;
2239 }
2240 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2241 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2242 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
2243 return 0;
2244 }
2245 return 1;
1da177e4
LT		 2246}
2247
2248/**
2249 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2250 * @sp: Pointer to device specifc structure
20346722 2251 * Description :
1da177e4
LT		 2252 * New procedure to clear mac address reading problems on Alpha platforms
2253 *
2254 */
2255
1ee6dd77 2256static void fix_mac_address(struct s2io_nic * sp)
1da177e4 2257{
1ee6dd77 2258 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 2259 u64 val64;
2260 int i = 0;
2261
2262 while (fix_mac[i] != END_SIGN) {
2263 writeq(fix_mac[i++], &bar0->gpio_control);
20346722 2264 udelay(10);
1da177e4
LT		 2265 val64 = readq(&bar0->gpio_control);
2266 }
2267}
2268
2269/**
20346722 2270 * start_nic - Turns the device on
1da177e4 2271 * @nic : device private variable.
20346722
K		 2272 * Description:
2273 * This function actually turns the device on. Before this function is
2274 * called,all Registers are configured from their reset states
2275 * and shared memory is allocated but the NIC is still quiescent. On
1da177e4
LT		 2276 * calling this function, the device interrupts are cleared and the NIC is
2277 * literally switched on by writing into the adapter control register.
20346722 2278 * Return Value:
1da177e4
LT		 2279 * SUCCESS on success and -1 on failure.
2280 */
2281
2282static int start_nic(struct s2io_nic *nic)
2283{
1ee6dd77 2284 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 2285 struct net_device *dev = nic->dev;
2286 register u64 val64 = 0;
20346722 2287 u16 subid, i;
1ee6dd77 2288 struct mac_info *mac_control;
1da177e4
LT		 2289 struct config_param *config;
2290
2291 mac_control = &nic->mac_control;
2292 config = &nic->config;
2293
2294 /* PRC Initialization and configuration */
2295 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2296 struct ring_info *ring = &mac_control->rings[i];
2297
2298 writeq((u64) ring->rx_blocks[0].block_dma_addr,
1da177e4
LT		 2299 &bar0->prc_rxd0_n[i]);
2300
2301 val64 = readq(&bar0->prc_ctrl_n[i]);
da6971d8
AR		 2302 if (nic->rxd_mode == RXD_MODE_1)
2303 val64 |= PRC_CTRL_RC_ENABLED;
2304 else
2305 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
863c11a9
AR		 2306 if (nic->device_type == XFRAME_II_DEVICE)
2307 val64 |= PRC_CTRL_GROUP_READS;
2308 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2309 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1da177e4
LT		 2310 writeq(val64, &bar0->prc_ctrl_n[i]);
2311 }
2312
da6971d8
AR		 2313 if (nic->rxd_mode == RXD_MODE_3B) {
2314 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2315 val64 = readq(&bar0->rx_pa_cfg);
2316 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2317 writeq(val64, &bar0->rx_pa_cfg);
2318 }
1da177e4 2319
926930b2
SS		 2320 if (vlan_tag_strip == 0) {
2321 val64 = readq(&bar0->rx_pa_cfg);
2322 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2323 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 2324 nic->vlan_strip_flag = 0;
926930b2
SS		 2325 }
2326
20346722 2327 /*
1da177e4
LT		 2328 * Enabling MC-RLDRAM. After enabling the device, we timeout
2329 * for around 100ms, which is approximately the time required
2330 * for the device to be ready for operation.
2331 */
2332 val64 = readq(&bar0->mc_rldram_mrs);
2333 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2334 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2335 val64 = readq(&bar0->mc_rldram_mrs);
2336
20346722 2337 msleep(100); /* Delay by around 100 ms. */
1da177e4
LT		 2338
2339 /* Enabling ECC Protection. */
2340 val64 = readq(&bar0->adapter_control);
2341 val64 &= ~ADAPTER_ECC_EN;
2342 writeq(val64, &bar0->adapter_control);
2343
20346722
K		 2344 /*
2345 * Verify if the device is ready to be enabled, if so enable
1da177e4
LT		 2346 * it.
2347 */
2348 val64 = readq(&bar0->adapter_status);
19a60522 2349 if (!verify_xena_quiescence(nic)) {
1da177e4
LT		 2350 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2351 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2352 (unsigned long long) val64);
2353 return FAILURE;
2354 }
2355
20346722 2356 /*
1da177e4 2357 * With some switches, link might be already up at this point.
20346722
K		 2358 * Because of this weird behavior, when we enable laser,
2359 * we may not get link. We need to handle this. We cannot
2360 * figure out which switch is misbehaving. So we are forced to
2361 * make a global change.
1da177e4
LT		 2362 */
2363
2364 /* Enabling Laser. */
2365 val64 = readq(&bar0->adapter_control);
2366 val64 |= ADAPTER_EOI_TX_ON;
2367 writeq(val64, &bar0->adapter_control);
2368
c92ca04b
AR		 2369 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2370 /*
2371 * Dont see link state interrupts initally on some switches,
2372 * so directly scheduling the link state task here.
2373 */
2374 schedule_work(&nic->set_link_task);
2375 }
1da177e4
LT		 2376 /* SXE-002: Initialize link and activity LED */
2377 subid = nic->pdev->subsystem_device;
541ae68f
K		 2378 if (((subid & 0xFF) >= 0x07) &&
2379 (nic->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 2380 val64 = readq(&bar0->gpio_control);
2381 val64 |= 0x0000800000000000ULL;
2382 writeq(val64, &bar0->gpio_control);
2383 val64 = 0x0411040400000000ULL;
509a2671 2384 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 2385 }
2386
1da177e4
LT		 2387 return SUCCESS;
2388}
fed5eccd
AR		 2389/**
2390 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2391 */
1ee6dd77
RB		 2392static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2393 TxD *txdlp, int get_off)
fed5eccd 2394{
1ee6dd77 2395 struct s2io_nic *nic = fifo_data->nic;
fed5eccd 2396 struct sk_buff *skb;
1ee6dd77 2397 struct TxD *txds;
fed5eccd
AR		 2398 u16 j, frg_cnt;
2399
2400 txds = txdlp;
2fda096d 2401 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
fed5eccd
AR		 2402 pci_unmap_single(nic->pdev, (dma_addr_t)
2403 txds->Buffer_Pointer, sizeof(u64),
2404 PCI_DMA_TODEVICE);
2405 txds++;
2406 }
2407
2408 skb = (struct sk_buff *) ((unsigned long)
2409 txds->Host_Control);
2410 if (!skb) {
1ee6dd77 2411 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2412 return NULL;
2413 }
2414 pci_unmap_single(nic->pdev, (dma_addr_t)
2415 txds->Buffer_Pointer,
2416 skb->len - skb->data_len,
2417 PCI_DMA_TODEVICE);
2418 frg_cnt = skb_shinfo(skb)->nr_frags;
2419 if (frg_cnt) {
2420 txds++;
2421 for (j = 0; j < frg_cnt; j++, txds++) {
2422 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2423 if (!txds->Buffer_Pointer)
2424 break;
6aa20a22 2425 pci_unmap_page(nic->pdev, (dma_addr_t)
fed5eccd
AR		 2426 txds->Buffer_Pointer,
2427 frag->size, PCI_DMA_TODEVICE);
2428 }
2429 }
1ee6dd77 2430 memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2431 return(skb);
2432}
1da177e4 2433
20346722
K		 2434/**
2435 * free_tx_buffers - Free all queued Tx buffers
1da177e4 2436 * @nic : device private variable.
20346722 2437 * Description:
1da177e4 2438 * Free all queued Tx buffers.
20346722 2439 * Return Value: void
1da177e4
LT		 2440*/
2441
2442static void free_tx_buffers(struct s2io_nic *nic)
2443{
2444 struct net_device *dev = nic->dev;
2445 struct sk_buff *skb;
1ee6dd77 2446 struct TxD *txdp;
1da177e4 2447 int i, j;
1ee6dd77 2448 struct mac_info *mac_control;
1da177e4 2449 struct config_param *config;
fed5eccd 2450 int cnt = 0;
1da177e4
LT		 2451
2452 mac_control = &nic->mac_control;
2453 config = &nic->config;
2454
2455 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 2456 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2457 struct fifo_info *fifo = &mac_control->fifos[i];
2fda096d 2458 unsigned long flags;
13d866a9
JP		 2459
2460 spin_lock_irqsave(&fifo->tx_lock, flags);
2461 for (j = 0; j < tx_cfg->fifo_len; j++) {
2462 txdp = (struct TxD *)fifo->list_info[j].list_virt_addr;
fed5eccd
AR		 2463 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2464 if (skb) {
8a4bdbaa 2465 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 2466 += skb->truesize;
fed5eccd
AR		 2467 dev_kfree_skb(skb);
2468 cnt++;
1da177e4 2469 }
1da177e4
LT		 2470 }
2471 DBG_PRINT(INTR_DBG,
2472 "%s:forcibly freeing %d skbs on FIFO%d\n",
2473 dev->name, cnt, i);
13d866a9
JP		 2474 fifo->tx_curr_get_info.offset = 0;
2475 fifo->tx_curr_put_info.offset = 0;
2476 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4
LT		 2477 }
2478}
2479
20346722
K		 2480/**
2481 * stop_nic - To stop the nic
1da177e4 2482 * @nic ; device private variable.
20346722
K		 2483 * Description:
2484 * This function does exactly the opposite of what the start_nic()
1da177e4
LT		 2485 * function does. This function is called to stop the device.
2486 * Return Value:
2487 * void.
2488 */
2489
2490static void stop_nic(struct s2io_nic *nic)
2491{
1ee6dd77 2492 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 2493 register u64 val64 = 0;
5d3213cc 2494 u16 interruptible;
1ee6dd77 2495 struct mac_info *mac_control;
1da177e4
LT		 2496 struct config_param *config;
2497
2498 mac_control = &nic->mac_control;
2499 config = &nic->config;
2500
2501 /* Disable all interrupts */
9caab458 2502 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
e960fc5c 2503 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 2504 interruptible |= TX_PIC_INTR;
1da177e4
LT		 2505 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2506
5d3213cc
AR		 2507 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2508 val64 = readq(&bar0->adapter_control);
2509 val64 &= ~(ADAPTER_CNTL_EN);
2510 writeq(val64, &bar0->adapter_control);
1da177e4
LT		 2511}
2512
20346722
K		 2513/**
2514 * fill_rx_buffers - Allocates the Rx side skbs
0425b46a 2515 * @ring_info: per ring structure
3f78d885
SH		 2516 * @from_card_up: If this is true, we will map the buffer to get
2517 * the dma address for buf0 and buf1 to give it to the card.
2518 * Else we will sync the already mapped buffer to give it to the card.
20346722 2519 * Description:
1da177e4
LT		 2520 * The function allocates Rx side skbs and puts the physical
2521 * address of these buffers into the RxD buffer pointers, so that the NIC
2522 * can DMA the received frame into these locations.
2523 * The NIC supports 3 receive modes, viz
2524 * 1. single buffer,
2525 * 2. three buffer and
2526 * 3. Five buffer modes.
20346722
K		 2527 * Each mode defines how many fragments the received frame will be split
2528 * up into by the NIC. The frame is split into L3 header, L4 Header,
1da177e4
LT		 2529 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2530 * is split into 3 fragments. As of now only single buffer mode is
2531 * supported.
2532 * Return Value:
2533 * SUCCESS on success or an appropriate -ve value on failure.
2534 */
8d8bb39b
FT		 2535static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
2536 int from_card_up)
1da177e4 2537{
1da177e4 2538 struct sk_buff *skb;
1ee6dd77 2539 struct RxD_t *rxdp;
0425b46a 2540 int off, size, block_no, block_no1;
1da177e4 2541 u32 alloc_tab = 0;
20346722 2542 u32 alloc_cnt;
20346722 2543 u64 tmp;
1ee6dd77 2544 struct buffAdd *ba;
1ee6dd77 2545 struct RxD_t *first_rxdp = NULL;
363dc367 2546 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
0425b46a 2547 int rxd_index = 0;
6d517a27
VP		 2548 struct RxD1 *rxdp1;
2549 struct RxD3 *rxdp3;
0425b46a 2550 struct swStat *stats = &ring->nic->mac_control.stats_info->sw_stat;
1da177e4 2551
0425b46a 2552 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
1da177e4 2553
0425b46a 2554 block_no1 = ring->rx_curr_get_info.block_index;
1da177e4 2555 while (alloc_tab < alloc_cnt) {
0425b46a 2556 block_no = ring->rx_curr_put_info.block_index;
1da177e4 2557
0425b46a
SH		 2558 off = ring->rx_curr_put_info.offset;
2559
2560 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2561
2562 rxd_index = off + 1;
2563 if (block_no)
2564 rxd_index += (block_no * ring->rxd_count);
da6971d8 2565
7d2e3cb7 2566 if ((block_no == block_no1) &&
0425b46a
SH		 2567 (off == ring->rx_curr_get_info.offset) &&
2568 (rxdp->Host_Control)) {
da6971d8 2569 DBG_PRINT(INTR_DBG, "%s: Get and Put",
0425b46a 2570 ring->dev->name);
1da177e4
LT		 2571 DBG_PRINT(INTR_DBG, " info equated\n");
2572 goto end;
2573 }
0425b46a
SH		 2574 if (off && (off == ring->rxd_count)) {
2575 ring->rx_curr_put_info.block_index++;
2576 if (ring->rx_curr_put_info.block_index ==
2577 ring->block_count)
2578 ring->rx_curr_put_info.block_index = 0;
2579 block_no = ring->rx_curr_put_info.block_index;
2580 off = 0;
2581 ring->rx_curr_put_info.offset = off;
2582 rxdp = ring->rx_blocks[block_no].block_virt_addr;
1da177e4 2583 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
0425b46a
SH		 2584 ring->dev->name, rxdp);
2585
1da177e4 2586 }
c9fcbf47 2587
da6971d8 2588 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
0425b46a 2589 ((ring->rxd_mode == RXD_MODE_3B) &&
b7b5a128 2590 (rxdp->Control_2 & s2BIT(0)))) {
0425b46a 2591 ring->rx_curr_put_info.offset = off;
1da177e4
LT		 2592 goto end;
2593 }
da6971d8 2594 /* calculate size of skb based on ring mode */
0425b46a 2595 size = ring->mtu + HEADER_ETHERNET_II_802_3_SIZE +
da6971d8 2596 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
0425b46a 2597 if (ring->rxd_mode == RXD_MODE_1)
da6971d8 2598 size += NET_IP_ALIGN;
da6971d8 2599 else
0425b46a 2600 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
1da177e4 2601
da6971d8
AR		 2602 /* allocate skb */
2603 skb = dev_alloc_skb(size);
2604 if(!skb) {
0425b46a 2605 DBG_PRINT(INFO_DBG, "%s: Out of ", ring->dev->name);
0c61ed5f 2606 DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
303bcb4b
K		 2607 if (first_rxdp) {
2608 wmb();
2609 first_rxdp->Control_1 |= RXD_OWN_XENA;
2610 }
0425b46a 2611 stats->mem_alloc_fail_cnt++;
7d2e3cb7 2612
da6971d8
AR		 2613 return -ENOMEM ;
2614 }
0425b46a
SH		 2615 stats->mem_allocated += skb->truesize;
2616
2617 if (ring->rxd_mode == RXD_MODE_1) {
da6971d8 2618 /* 1 buffer mode - normal operation mode */
6d517a27 2619 rxdp1 = (struct RxD1*)rxdp;
1ee6dd77 2620 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2621 skb_reserve(skb, NET_IP_ALIGN);
6d517a27 2622 rxdp1->Buffer0_ptr = pci_map_single
0425b46a 2623 (ring->pdev, skb->data, size - NET_IP_ALIGN,
863c11a9 2624 PCI_DMA_FROMDEVICE);
8d8bb39b
FT		 2625 if (pci_dma_mapping_error(nic->pdev,
2626 rxdp1->Buffer0_ptr))
491abf25
VP		 2627 goto pci_map_failed;
2628
8a4bdbaa 2629 rxdp->Control_2 =
491976b2 2630 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
0425b46a
SH		 2631 rxdp->Host_Control = (unsigned long) (skb);
2632 } else if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8 2633 /*
6d517a27
VP		 2634 * 2 buffer mode -
2635 * 2 buffer mode provides 128
da6971d8 2636 * byte aligned receive buffers.
da6971d8
AR		 2637 */
2638
6d517a27 2639 rxdp3 = (struct RxD3*)rxdp;
491976b2 2640 /* save buffer pointers to avoid frequent dma mapping */
6d517a27
VP		 2641 Buffer0_ptr = rxdp3->Buffer0_ptr;
2642 Buffer1_ptr = rxdp3->Buffer1_ptr;
1ee6dd77 2643 memset(rxdp, 0, sizeof(struct RxD3));
363dc367 2644 /* restore the buffer pointers for dma sync*/
6d517a27
VP		 2645 rxdp3->Buffer0_ptr = Buffer0_ptr;
2646 rxdp3->Buffer1_ptr = Buffer1_ptr;
363dc367 2647
0425b46a 2648 ba = &ring->ba[block_no][off];
da6971d8
AR		 2649 skb_reserve(skb, BUF0_LEN);
2650 tmp = (u64)(unsigned long) skb->data;
2651 tmp += ALIGN_SIZE;
2652 tmp &= ~ALIGN_SIZE;
2653 skb->data = (void *) (unsigned long)tmp;
27a884dc 2654 skb_reset_tail_pointer(skb);
da6971d8 2655
3f78d885 2656 if (from_card_up) {
6d517a27 2657 rxdp3->Buffer0_ptr =
0425b46a
SH		 2658 pci_map_single(ring->pdev, ba->ba_0,
2659 BUF0_LEN, PCI_DMA_FROMDEVICE);
8d8bb39b
FT		 2660 if (pci_dma_mapping_error(nic->pdev,
2661 rxdp3->Buffer0_ptr))
3f78d885
SH		 2662 goto pci_map_failed;
2663 } else
0425b46a 2664 pci_dma_sync_single_for_device(ring->pdev,
6d517a27 2665 (dma_addr_t) rxdp3->Buffer0_ptr,
75c30b13 2666 BUF0_LEN, PCI_DMA_FROMDEVICE);
491abf25 2667
da6971d8 2668 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
0425b46a 2669 if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 2670 /* Two buffer mode */
2671
2672 /*
6aa20a22 2673 * Buffer2 will have L3/L4 header plus
da6971d8
AR		 2674 * L4 payload
2675 */
6d517a27 2676 rxdp3->Buffer2_ptr = pci_map_single
0425b46a 2677 (ring->pdev, skb->data, ring->mtu + 4,
da6971d8
AR		 2678 PCI_DMA_FROMDEVICE);
2679
8d8bb39b
FT		 2680 if (pci_dma_mapping_error(nic->pdev,
2681 rxdp3->Buffer2_ptr))
491abf25
VP		 2682 goto pci_map_failed;
2683
3f78d885 2684 if (from_card_up) {
0425b46a
SH		 2685 rxdp3->Buffer1_ptr =
2686 pci_map_single(ring->pdev,
75c30b13
AR		 2687 ba->ba_1, BUF1_LEN,
2688 PCI_DMA_FROMDEVICE);
0425b46a 2689
8d8bb39b
FT		 2690 if (pci_dma_mapping_error(nic->pdev,
2691 rxdp3->Buffer1_ptr)) {
3f78d885
SH		 2692 pci_unmap_single
2693 (ring->pdev,
2694 (dma_addr_t)(unsigned long)
2695 skb->data,
2696 ring->mtu + 4,
2697 PCI_DMA_FROMDEVICE);
2698 goto pci_map_failed;
2699 }
75c30b13 2700 }
da6971d8
AR		 2701 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2702 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
0425b46a 2703 (ring->mtu + 4);
da6971d8 2704 }
b7b5a128 2705 rxdp->Control_2 |= s2BIT(0);
0425b46a 2706 rxdp->Host_Control = (unsigned long) (skb);
1da177e4 2707 }
303bcb4b
K		 2708 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2709 rxdp->Control_1 |= RXD_OWN_XENA;
1da177e4 2710 off++;
0425b46a 2711 if (off == (ring->rxd_count + 1))
da6971d8 2712 off = 0;
0425b46a 2713 ring->rx_curr_put_info.offset = off;
20346722 2714
da6971d8 2715 rxdp->Control_2 |= SET_RXD_MARKER;
303bcb4b
K		 2716 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2717 if (first_rxdp) {
2718 wmb();
2719 first_rxdp->Control_1 |= RXD_OWN_XENA;
2720 }
2721 first_rxdp = rxdp;
2722 }
0425b46a 2723 ring->rx_bufs_left += 1;
1da177e4
LT		 2724 alloc_tab++;
2725 }
2726
2727 end:
303bcb4b
K		 2728 /* Transfer ownership of first descriptor to adapter just before
2729 * exiting. Before that, use memory barrier so that ownership
2730 * and other fields are seen by adapter correctly.
2731 */
2732 if (first_rxdp) {
2733 wmb();
2734 first_rxdp->Control_1 |= RXD_OWN_XENA;
2735 }
2736
1da177e4 2737 return SUCCESS;
491abf25
VP		 2738pci_map_failed:
2739 stats->pci_map_fail_cnt++;
2740 stats->mem_freed += skb->truesize;
2741 dev_kfree_skb_irq(skb);
2742 return -ENOMEM;
1da177e4
LT		 2743}
2744
da6971d8
AR		 2745static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2746{
2747 struct net_device *dev = sp->dev;
2748 int j;
2749 struct sk_buff *skb;
1ee6dd77
RB		 2750 struct RxD_t *rxdp;
2751 struct mac_info *mac_control;
2752 struct buffAdd *ba;
6d517a27
VP		 2753 struct RxD1 *rxdp1;
2754 struct RxD3 *rxdp3;
da6971d8
AR		 2755
2756 mac_control = &sp->mac_control;
2757 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2758 rxdp = mac_control->rings[ring_no].
2759 rx_blocks[blk].rxds[j].virt_addr;
2760 skb = (struct sk_buff *)
2761 ((unsigned long) rxdp->Host_Control);
2762 if (!skb) {
2763 continue;
2764 }
2765 if (sp->rxd_mode == RXD_MODE_1) {
6d517a27 2766 rxdp1 = (struct RxD1*)rxdp;
da6971d8 2767 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2768 rxdp1->Buffer0_ptr,
2769 dev->mtu +
2770 HEADER_ETHERNET_II_802_3_SIZE
2771 + HEADER_802_2_SIZE +
2772 HEADER_SNAP_SIZE,
2773 PCI_DMA_FROMDEVICE);
1ee6dd77 2774 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2775 } else if(sp->rxd_mode == RXD_MODE_3B) {
6d517a27 2776 rxdp3 = (struct RxD3*)rxdp;
da6971d8
AR		 2777 ba = &mac_control->rings[ring_no].
2778 ba[blk][j];
2779 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2780 rxdp3->Buffer0_ptr,
2781 BUF0_LEN,
da6971d8
AR		 2782 PCI_DMA_FROMDEVICE);
2783 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2784 rxdp3->Buffer1_ptr,
2785 BUF1_LEN,
da6971d8
AR		 2786 PCI_DMA_FROMDEVICE);
2787 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2788 rxdp3->Buffer2_ptr,
2789 dev->mtu + 4,
da6971d8 2790 PCI_DMA_FROMDEVICE);
1ee6dd77 2791 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8 2792 }
491976b2 2793 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
da6971d8 2794 dev_kfree_skb(skb);
0425b46a 2795 mac_control->rings[ring_no].rx_bufs_left -= 1;
da6971d8
AR		 2796 }
2797}
2798
1da177e4 2799/**
20346722 2800 * free_rx_buffers - Frees all Rx buffers
1da177e4 2801 * @sp: device private variable.
20346722 2802 * Description:
1da177e4
LT		 2803 * This function will free all Rx buffers allocated by host.
2804 * Return Value:
2805 * NONE.
2806 */
2807
2808static void free_rx_buffers(struct s2io_nic *sp)
2809{
2810 struct net_device *dev = sp->dev;
da6971d8 2811 int i, blk = 0, buf_cnt = 0;
1ee6dd77 2812 struct mac_info *mac_control;
1da177e4 2813 struct config_param *config;
1da177e4
LT		 2814
2815 mac_control = &sp->mac_control;
2816 config = &sp->config;
2817
2818 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2819 struct ring_info *ring = &mac_control->rings[i];
2820
da6971d8
AR		 2821 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2822 free_rxd_blk(sp,i,blk);
1da177e4 2823
13d866a9
JP		 2824 ring->rx_curr_put_info.block_index = 0;
2825 ring->rx_curr_get_info.block_index = 0;
2826 ring->rx_curr_put_info.offset = 0;
2827 ring->rx_curr_get_info.offset = 0;
2828 ring->rx_bufs_left = 0;
1da177e4
LT		 2829 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2830 dev->name, buf_cnt, i);
2831 }
2832}
2833
8d8bb39b 2834static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
f61e0a35 2835{
8d8bb39b 2836 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
f61e0a35
SH		 2837 DBG_PRINT(INFO_DBG, "%s:Out of memory", ring->dev->name);
2838 DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
2839 }
2840 return 0;
2841}
2842
1da177e4
LT		 2843/**
2844 * s2io_poll - Rx interrupt handler for NAPI support
bea3348e 2845 * @napi : pointer to the napi structure.
20346722 2846 * @budget : The number of packets that were budgeted to be processed
1da177e4
LT		 2847 * during one pass through the 'Poll" function.
2848 * Description:
2849 * Comes into picture only if NAPI support has been incorporated. It does
2850 * the same thing that rx_intr_handler does, but not in a interrupt context
2851 * also It will process only a given number of packets.
2852 * Return value:
2853 * 0 on success and 1 if there are No Rx packets to be processed.
2854 */
2855
f61e0a35 2856static int s2io_poll_msix(struct napi_struct *napi, int budget)
1da177e4 2857{
f61e0a35
SH		 2858 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2859 struct net_device *dev = ring->dev;
1da177e4 2860 struct config_param *config;
f61e0a35
SH		 2861 struct mac_info *mac_control;
2862 int pkts_processed = 0;
1a79d1c3
AV		 2863 u8 __iomem *addr = NULL;
2864 u8 val8 = 0;
4cf1653a 2865 struct s2io_nic *nic = netdev_priv(dev);
1ee6dd77 2866 struct XENA_dev_config __iomem *bar0 = nic->bar0;
f61e0a35 2867 int budget_org = budget;
1da177e4 2868
1da177e4 2869 config = &nic->config;
f61e0a35 2870 mac_control = &nic->mac_control;
1da177e4 2871
f61e0a35
SH		 2872 if (unlikely(!is_s2io_card_up(nic)))
2873 return 0;
1da177e4 2874
f61e0a35 2875 pkts_processed = rx_intr_handler(ring, budget);
8d8bb39b 2876 s2io_chk_rx_buffers(nic, ring);
1da177e4 2877
f61e0a35 2878 if (pkts_processed < budget_org) {
288379f0 2879 napi_complete(napi);
f61e0a35 2880 /*Re Enable MSI-Rx Vector*/
1a79d1c3 2881 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
f61e0a35
SH		 2882 addr += 7 - ring->ring_no;
2883 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2884 writeb(val8, addr);
2885 val8 = readb(addr);
1da177e4 2886 }
f61e0a35
SH		 2887 return pkts_processed;
2888}
2889static int s2io_poll_inta(struct napi_struct *napi, int budget)
2890{
2891 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
f61e0a35
SH		 2892 struct config_param *config;
2893 struct mac_info *mac_control;
2894 int pkts_processed = 0;
2895 int ring_pkts_processed, i;
2896 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2897 int budget_org = budget;
1da177e4 2898
f61e0a35
SH		 2899 config = &nic->config;
2900 mac_control = &nic->mac_control;
1da177e4 2901
f61e0a35
SH		 2902 if (unlikely(!is_s2io_card_up(nic)))
2903 return 0;
1da177e4 2904
1da177e4 2905 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9 2906 struct ring_info *ring = &mac_control->rings[i];
f61e0a35 2907 ring_pkts_processed = rx_intr_handler(ring, budget);
8d8bb39b 2908 s2io_chk_rx_buffers(nic, ring);
f61e0a35
SH		 2909 pkts_processed += ring_pkts_processed;
2910 budget -= ring_pkts_processed;
2911 if (budget <= 0)
1da177e4 2912 break;
1da177e4 2913 }
f61e0a35 2914 if (pkts_processed < budget_org) {
288379f0 2915 napi_complete(napi);
f61e0a35
SH		 2916 /* Re enable the Rx interrupts for the ring */
2917 writeq(0, &bar0->rx_traffic_mask);
2918 readl(&bar0->rx_traffic_mask);
2919 }
2920 return pkts_processed;
1da177e4 2921}
20346722 2922
b41477f3 2923#ifdef CONFIG_NET_POLL_CONTROLLER
612eff0e 2924/**
b41477f3 2925 * s2io_netpoll - netpoll event handler entry point
612eff0e
BH		 2926 * @dev : pointer to the device structure.
2927 * Description:
b41477f3
AR		 2928 * This function will be called by upper layer to check for events on the
2929 * interface in situations where interrupts are disabled. It is used for
2930 * specific in-kernel networking tasks, such as remote consoles and kernel
2931 * debugging over the network (example netdump in RedHat).
612eff0e 2932 */
612eff0e
BH		 2933static void s2io_netpoll(struct net_device *dev)
2934{
4cf1653a 2935 struct s2io_nic *nic = netdev_priv(dev);
1ee6dd77 2936 struct mac_info *mac_control;
612eff0e 2937 struct config_param *config;
1ee6dd77 2938 struct XENA_dev_config __iomem *bar0 = nic->bar0;
b41477f3 2939 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
612eff0e
BH		 2940 int i;
2941
d796fdb7
LV		 2942 if (pci_channel_offline(nic->pdev))
2943 return;
2944
612eff0e
BH		 2945 disable_irq(dev->irq);
2946
612eff0e
BH		 2947 mac_control = &nic->mac_control;
2948 config = &nic->config;
2949
612eff0e 2950 writeq(val64, &bar0->rx_traffic_int);
b41477f3
AR		 2951 writeq(val64, &bar0->tx_traffic_int);
2952
6aa20a22 2953 /* we need to free up the transmitted skbufs or else netpoll will
b41477f3
AR		 2954 * run out of skbs and will fail and eventually netpoll application such
2955 * as netdump will fail.
2956 */
2957 for (i = 0; i < config->tx_fifo_num; i++)
2958 tx_intr_handler(&mac_control->fifos[i]);
612eff0e 2959
b41477f3 2960 /* check for received packet and indicate up to network */
13d866a9
JP		 2961 for (i = 0; i < config->rx_ring_num; i++) {
2962 struct ring_info *ring = &mac_control->rings[i];
2963
2964 rx_intr_handler(ring, 0);
2965 }
612eff0e
BH		 2966
2967 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2968 struct ring_info *ring = &mac_control->rings[i];
2969
2970 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
0c61ed5f
RV		 2971 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2972 DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
612eff0e
BH		 2973 break;
2974 }
2975 }
612eff0e
BH		 2976 enable_irq(dev->irq);
2977 return;
2978}
2979#endif
2980
20346722 2981/**
1da177e4 2982 * rx_intr_handler - Rx interrupt handler
f61e0a35
SH		 2983 * @ring_info: per ring structure.
2984 * @budget: budget for napi processing.
20346722
K		 2985 * Description:
2986 * If the interrupt is because of a received frame or if the
1da177e4 2987 * receive ring contains fresh as yet un-processed frames,this function is
20346722
K		 2988 * called. It picks out the RxD at which place the last Rx processing had
2989 * stopped and sends the skb to the OSM's Rx handler and then increments
1da177e4
LT		 2990 * the offset.
2991 * Return Value:
f61e0a35 2992 * No. of napi packets processed.
1da177e4 2993 */
f61e0a35 2994static int rx_intr_handler(struct ring_info *ring_data, int budget)
1da177e4 2995{
c9fcbf47 2996 int get_block, put_block;
1ee6dd77
RB		 2997 struct rx_curr_get_info get_info, put_info;
2998 struct RxD_t *rxdp;
1da177e4 2999 struct sk_buff *skb;
f61e0a35 3000 int pkt_cnt = 0, napi_pkts = 0;
7d3d0439 3001 int i;
6d517a27
VP		 3002 struct RxD1* rxdp1;
3003 struct RxD3* rxdp3;
7d3d0439 3004
20346722
K		 3005 get_info = ring_data->rx_curr_get_info;
3006 get_block = get_info.block_index;
1ee6dd77 3007 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
20346722 3008 put_block = put_info.block_index;
da6971d8 3009 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
db874e65 3010
da6971d8 3011 while (RXD_IS_UP2DT(rxdp)) {
db874e65
SS		 3012 /*
3013 * If your are next to put index then it's
3014 * FIFO full condition
3015 */
da6971d8
AR		 3016 if ((get_block == put_block) &&
3017 (get_info.offset + 1) == put_info.offset) {
0425b46a
SH		 3018 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
3019 ring_data->dev->name);
da6971d8
AR		 3020 break;
3021 }
20346722
K		 3022 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
3023 if (skb == NULL) {
3024 DBG_PRINT(ERR_DBG, "%s: The skb is ",
0425b46a 3025 ring_data->dev->name);
20346722 3026 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
f61e0a35 3027 return 0;
1da177e4 3028 }
0425b46a 3029 if (ring_data->rxd_mode == RXD_MODE_1) {
6d517a27 3030 rxdp1 = (struct RxD1*)rxdp;
0425b46a 3031 pci_unmap_single(ring_data->pdev, (dma_addr_t)
6d517a27 3032 rxdp1->Buffer0_ptr,
0425b46a 3033 ring_data->mtu +
6d517a27
VP		 3034 HEADER_ETHERNET_II_802_3_SIZE +
3035 HEADER_802_2_SIZE +
3036 HEADER_SNAP_SIZE,
3037 PCI_DMA_FROMDEVICE);
0425b46a 3038 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
6d517a27 3039 rxdp3 = (struct RxD3*)rxdp;
0425b46a 3040 pci_dma_sync_single_for_cpu(ring_data->pdev, (dma_addr_t)
6d517a27
VP		 3041 rxdp3->Buffer0_ptr,
3042 BUF0_LEN, PCI_DMA_FROMDEVICE);
0425b46a 3043 pci_unmap_single(ring_data->pdev, (dma_addr_t)
6d517a27 3044 rxdp3->Buffer2_ptr,
0425b46a 3045 ring_data->mtu + 4,
6d517a27 3046 PCI_DMA_FROMDEVICE);
da6971d8 3047 }
863c11a9 3048 prefetch(skb->data);
20346722
K		 3049 rx_osm_handler(ring_data, rxdp);
3050 get_info.offset++;
da6971d8
AR		 3051 ring_data->rx_curr_get_info.offset = get_info.offset;
3052 rxdp = ring_data->rx_blocks[get_block].
3053 rxds[get_info.offset].virt_addr;
0425b46a 3054 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
20346722 3055 get_info.offset = 0;
da6971d8 3056 ring_data->rx_curr_get_info.offset = get_info.offset;
20346722 3057 get_block++;
da6971d8
AR		 3058 if (get_block == ring_data->block_count)
3059 get_block = 0;
3060 ring_data->rx_curr_get_info.block_index = get_block;
20346722
K		 3061 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3062 }
1da177e4 3063
f61e0a35
SH		 3064 if (ring_data->nic->config.napi) {
3065 budget--;
3066 napi_pkts++;
3067 if (!budget)
0425b46a
SH		 3068 break;
3069 }
20346722 3070 pkt_cnt++;
1da177e4
LT		 3071 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3072 break;
3073 }
0425b46a 3074 if (ring_data->lro) {
7d3d0439
RA		 3075 /* Clear all LRO sessions before exiting */
3076 for (i=0; i<MAX_LRO_SESSIONS; i++) {
0425b46a 3077 struct lro *lro = &ring_data->lro0_n[i];
7d3d0439 3078 if (lro->in_use) {
0425b46a 3079 update_L3L4_header(ring_data->nic, lro);
cdb5bf02 3080 queue_rx_frame(lro->parent, lro->vlan_tag);
7d3d0439
RA		 3081 clear_lro_session(lro);
3082 }
3083 }
3084 }
f61e0a35 3085 return(napi_pkts);
1da177e4 3086}
20346722
K		 3087
3088/**
1da177e4
LT		 3089 * tx_intr_handler - Transmit interrupt handler
3090 * @nic : device private variable
20346722
K		 3091 * Description:
3092 * If an interrupt was raised to indicate DMA complete of the
3093 * Tx packet, this function is called. It identifies the last TxD
3094 * whose buffer was freed and frees all skbs whose data have already
1da177e4
LT		 3095 * DMA'ed into the NICs internal memory.
3096 * Return Value:
3097 * NONE
3098 */
3099
1ee6dd77 3100static void tx_intr_handler(struct fifo_info *fifo_data)
1da177e4 3101{
1ee6dd77 3102 struct s2io_nic *nic = fifo_data->nic;
1ee6dd77 3103 struct tx_curr_get_info get_info, put_info;
3a3d5756 3104 struct sk_buff *skb = NULL;
1ee6dd77 3105 struct TxD *txdlp;
3a3d5756 3106 int pkt_cnt = 0;
2fda096d 3107 unsigned long flags = 0;
f9046eb3 3108 u8 err_mask;
1da177e4 3109
2fda096d
SR		 3110 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3111 return;
3112
20346722 3113 get_info = fifo_data->tx_curr_get_info;
1ee6dd77
RB		 3114 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3115 txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
20346722
K		 3116 list_virt_addr;
3117 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3118 (get_info.offset != put_info.offset) &&
3119 (txdlp->Host_Control)) {
3120 /* Check for TxD errors */
3121 if (txdlp->Control_1 & TXD_T_CODE) {
3122 unsigned long long err;
3123 err = txdlp->Control_1 & TXD_T_CODE;
bd1034f0
AR		 3124 if (err & 0x1) {
3125 nic->mac_control.stats_info->sw_stat.
3126 parity_err_cnt++;
3127 }
491976b2
SH		 3128
3129 /* update t_code statistics */
f9046eb3
OH		 3130 err_mask = err >> 48;
3131 switch(err_mask) {
491976b2
SH		 3132 case 2:
3133 nic->mac_control.stats_info->sw_stat.
3134 tx_buf_abort_cnt++;
3135 break;
3136
3137 case 3:
3138 nic->mac_control.stats_info->sw_stat.
3139 tx_desc_abort_cnt++;
3140 break;
3141
3142 case 7:
3143 nic->mac_control.stats_info->sw_stat.
3144 tx_parity_err_cnt++;
3145 break;
3146
3147 case 10:
3148 nic->mac_control.stats_info->sw_stat.
3149 tx_link_loss_cnt++;
3150 break;
3151
3152 case 15:
3153 nic->mac_control.stats_info->sw_stat.
3154 tx_list_proc_err_cnt++;
3155 break;
3156 }
20346722 3157 }
1da177e4 3158
fed5eccd 3159 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
20346722 3160 if (skb == NULL) {
2fda096d 3161 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
20346722 3162 DBG_PRINT(ERR_DBG, "%s: Null skb ",
b39d66a8 3163 __func__);
20346722
K		 3164 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
3165 return;
3166 }
3a3d5756 3167 pkt_cnt++;
20346722 3168
20346722 3169 /* Updating the statistics block */
dc56e634 3170 nic->dev->stats.tx_bytes += skb->len;
491976b2 3171 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
20346722
K		 3172 dev_kfree_skb_irq(skb);
3173
3174 get_info.offset++;
863c11a9
AR		 3175 if (get_info.offset == get_info.fifo_len + 1)
3176 get_info.offset = 0;
1ee6dd77 3177 txdlp = (struct TxD *) fifo_data->list_info
20346722
K		 3178 [get_info.offset].list_virt_addr;
3179 fifo_data->tx_curr_get_info.offset =
3180 get_info.offset;
1da177e4
LT		 3181 }
3182
3a3d5756 3183 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
2fda096d
SR		 3184
3185 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
1da177e4
LT		 3186}
3187
bd1034f0
AR		 3188/**
3189 * s2io_mdio_write - Function to write in to MDIO registers
3190 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3191 * @addr : address value
3192 * @value : data value
3193 * @dev : pointer to net_device structure
3194 * Description:
3195 * This function is used to write values to the MDIO registers
3196 * NONE
3197 */
3198static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
3199{
3200 u64 val64 = 0x0;
4cf1653a 3201 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3202 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3203
3204 //address transaction
3205 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3206 | MDIO_MMD_DEV_ADDR(mmd_type)
3207 | MDIO_MMS_PRT_ADDR(0x0);
3208 writeq(val64, &bar0->mdio_control);
3209 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3210 writeq(val64, &bar0->mdio_control);
3211 udelay(100);
3212
3213 //Data transaction
3214 val64 = 0x0;
3215 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3216 | MDIO_MMD_DEV_ADDR(mmd_type)
3217 | MDIO_MMS_PRT_ADDR(0x0)
3218 | MDIO_MDIO_DATA(value)
3219 | MDIO_OP(MDIO_OP_WRITE_TRANS);
3220 writeq(val64, &bar0->mdio_control);
3221 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3222 writeq(val64, &bar0->mdio_control);
3223 udelay(100);
3224
3225 val64 = 0x0;
3226 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3227 | MDIO_MMD_DEV_ADDR(mmd_type)
3228 | MDIO_MMS_PRT_ADDR(0x0)
3229 | MDIO_OP(MDIO_OP_READ_TRANS);
3230 writeq(val64, &bar0->mdio_control);
3231 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3232 writeq(val64, &bar0->mdio_control);
3233 udelay(100);
3234
3235}
3236
3237/**
3238 * s2io_mdio_read - Function to write in to MDIO registers
3239 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3240 * @addr : address value
3241 * @dev : pointer to net_device structure
3242 * Description:
3243 * This function is used to read values to the MDIO registers
3244 * NONE
3245 */
3246static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3247{
3248 u64 val64 = 0x0;
3249 u64 rval64 = 0x0;
4cf1653a 3250 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3251 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3252
3253 /* address transaction */
3254 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3255 | MDIO_MMD_DEV_ADDR(mmd_type)
3256 | MDIO_MMS_PRT_ADDR(0x0);
3257 writeq(val64, &bar0->mdio_control);
3258 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3259 writeq(val64, &bar0->mdio_control);
3260 udelay(100);
3261
3262 /* Data transaction */
3263 val64 = 0x0;
3264 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3265 | MDIO_MMD_DEV_ADDR(mmd_type)
3266 | MDIO_MMS_PRT_ADDR(0x0)
3267 | MDIO_OP(MDIO_OP_READ_TRANS);
3268 writeq(val64, &bar0->mdio_control);
3269 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3270 writeq(val64, &bar0->mdio_control);
3271 udelay(100);
3272
3273 /* Read the value from regs */
3274 rval64 = readq(&bar0->mdio_control);
3275 rval64 = rval64 & 0xFFFF0000;
3276 rval64 = rval64 >> 16;
3277 return rval64;
3278}
3279/**
3280 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3281 * @counter : couter value to be updated
3282 * @flag : flag to indicate the status
3283 * @type : counter type
3284 * Description:
3285 * This function is to check the status of the xpak counters value
3286 * NONE
3287 */
3288
3289static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
3290{
3291 u64 mask = 0x3;
3292 u64 val64;
3293 int i;
3294 for(i = 0; i <index; i++)
3295 mask = mask << 0x2;
3296
3297 if(flag > 0)
3298 {
3299 *counter = *counter + 1;
3300 val64 = *regs_stat & mask;
3301 val64 = val64 >> (index * 0x2);
3302 val64 = val64 + 1;
3303 if(val64 == 3)
3304 {
3305 switch(type)
3306 {
3307 case 1:
3308 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3309 "service. Excessive temperatures may "
3310 "result in premature transceiver "
3311 "failure \n");
3312 break;
3313 case 2:
3314 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3315 "service Excessive bias currents may "
3316 "indicate imminent laser diode "
3317 "failure \n");
3318 break;
3319 case 3:
3320 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3321 "service Excessive laser output "
3322 "power may saturate far-end "
3323 "receiver\n");
3324 break;
3325 default:
3326 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3327 "type \n");
3328 }
3329 val64 = 0x0;
3330 }
3331 val64 = val64 << (index * 0x2);
3332 *regs_stat = (*regs_stat & (~mask)) | (val64);
3333
3334 } else {
3335 *regs_stat = *regs_stat & (~mask);
3336 }
3337}
3338
3339/**
3340 * s2io_updt_xpak_counter - Function to update the xpak counters
3341 * @dev : pointer to net_device struct
3342 * Description:
3343 * This function is to upate the status of the xpak counters value
3344 * NONE
3345 */
3346static void s2io_updt_xpak_counter(struct net_device *dev)
3347{
3348 u16 flag = 0x0;
3349 u16 type = 0x0;
3350 u16 val16 = 0x0;
3351 u64 val64 = 0x0;
3352 u64 addr = 0x0;
3353
4cf1653a 3354 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3355 struct stat_block *stat_info = sp->mac_control.stats_info;
bd1034f0
AR		 3356
3357 /* Check the communication with the MDIO slave */
40239396 3358 addr = MDIO_CTRL1;
bd1034f0 3359 val64 = 0x0;
40239396 3360 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3361 if((val64 == 0xFFFF) || (val64 == 0x0000))
3362 {
3363 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3364 "Returned %llx\n", (unsigned long long)val64);
3365 return;
3366 }
3367
40239396
BH		 3368 /* Check for the expected value of control reg 1 */
3369 if(val64 != MDIO_CTRL1_SPEED10G)
bd1034f0
AR		 3370 {
3371 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
40239396
BH		 3372 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x%x\n",
3373 (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
bd1034f0
AR		 3374 return;
3375 }
3376
3377 /* Loading the DOM register to MDIO register */
3378 addr = 0xA100;
40239396
BH		 3379 s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3380 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3381
3382 /* Reading the Alarm flags */
3383 addr = 0xA070;
3384 val64 = 0x0;
40239396 3385 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3386
3387 flag = CHECKBIT(val64, 0x7);
3388 type = 1;
3389 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3390 &stat_info->xpak_stat.xpak_regs_stat,
3391 0x0, flag, type);
3392
3393 if(CHECKBIT(val64, 0x6))
3394 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3395
3396 flag = CHECKBIT(val64, 0x3);
3397 type = 2;
3398 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3399 &stat_info->xpak_stat.xpak_regs_stat,
3400 0x2, flag, type);
3401
3402 if(CHECKBIT(val64, 0x2))
3403 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3404
3405 flag = CHECKBIT(val64, 0x1);
3406 type = 3;
3407 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3408 &stat_info->xpak_stat.xpak_regs_stat,
3409 0x4, flag, type);
3410
3411 if(CHECKBIT(val64, 0x0))
3412 stat_info->xpak_stat.alarm_laser_output_power_low++;
3413
3414 /* Reading the Warning flags */
3415 addr = 0xA074;
3416 val64 = 0x0;
40239396 3417 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3418
3419 if(CHECKBIT(val64, 0x7))
3420 stat_info->xpak_stat.warn_transceiver_temp_high++;
3421
3422 if(CHECKBIT(val64, 0x6))
3423 stat_info->xpak_stat.warn_transceiver_temp_low++;
3424
3425 if(CHECKBIT(val64, 0x3))
3426 stat_info->xpak_stat.warn_laser_bias_current_high++;
3427
3428 if(CHECKBIT(val64, 0x2))
3429 stat_info->xpak_stat.warn_laser_bias_current_low++;
3430
3431 if(CHECKBIT(val64, 0x1))
3432 stat_info->xpak_stat.warn_laser_output_power_high++;
3433
3434 if(CHECKBIT(val64, 0x0))
3435 stat_info->xpak_stat.warn_laser_output_power_low++;
3436}
3437
20346722 3438/**
1da177e4 3439 * wait_for_cmd_complete - waits for a command to complete.
20346722 3440 * @sp : private member of the device structure, which is a pointer to the
1da177e4 3441 * s2io_nic structure.
20346722
K		 3442 * Description: Function that waits for a command to Write into RMAC
3443 * ADDR DATA registers to be completed and returns either success or
3444 * error depending on whether the command was complete or not.
1da177e4
LT		 3445 * Return value:
3446 * SUCCESS on success and FAILURE on failure.
3447 */
3448
9fc93a41
SS		 3449static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3450 int bit_state)
1da177e4 3451{
9fc93a41 3452 int ret = FAILURE, cnt = 0, delay = 1;
1da177e4
LT		 3453 u64 val64;
3454
9fc93a41
SS		 3455 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3456 return FAILURE;
3457
3458 do {
c92ca04b 3459 val64 = readq(addr);
9fc93a41
SS		 3460 if (bit_state == S2IO_BIT_RESET) {
3461 if (!(val64 & busy_bit)) {
3462 ret = SUCCESS;
3463 break;
3464 }
3465 } else {
3466 if (!(val64 & busy_bit)) {
3467 ret = SUCCESS;
3468 break;
3469 }
1da177e4 3470 }
c92ca04b
AR		 3471
3472 if(in_interrupt())
9fc93a41 3473 mdelay(delay);
c92ca04b 3474 else
9fc93a41 3475 msleep(delay);
c92ca04b 3476
9fc93a41
SS		 3477 if (++cnt >= 10)
3478 delay = 50;
3479 } while (cnt < 20);
1da177e4
LT		 3480 return ret;
3481}
19a60522
SS		 3482/*
3483 * check_pci_device_id - Checks if the device id is supported
3484 * @id : device id
3485 * Description: Function to check if the pci device id is supported by driver.
3486 * Return value: Actual device id if supported else PCI_ANY_ID
3487 */
3488static u16 check_pci_device_id(u16 id)
3489{
3490 switch (id) {
3491 case PCI_DEVICE_ID_HERC_WIN:
3492 case PCI_DEVICE_ID_HERC_UNI:
3493 return XFRAME_II_DEVICE;
3494 case PCI_DEVICE_ID_S2IO_UNI:
3495 case PCI_DEVICE_ID_S2IO_WIN:
3496 return XFRAME_I_DEVICE;
3497 default:
3498 return PCI_ANY_ID;
3499 }
3500}
1da177e4 3501
20346722
K		 3502/**
3503 * s2io_reset - Resets the card.
1da177e4
LT		 3504 * @sp : private member of the device structure.
3505 * Description: Function to Reset the card. This function then also
20346722 3506 * restores the previously saved PCI configuration space registers as
1da177e4
LT		 3507 * the card reset also resets the configuration space.
3508 * Return value:
3509 * void.
3510 */
3511
1ee6dd77 3512static void s2io_reset(struct s2io_nic * sp)
1da177e4 3513{
1ee6dd77 3514 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 3515 u64 val64;
5e25b9dd 3516 u16 subid, pci_cmd;
19a60522
SS		 3517 int i;
3518 u16 val16;
491976b2
SH		 3519 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3520 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3521
19a60522 3522 DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
b39d66a8 3523 __func__, sp->dev->name);
1da177e4 3524
0b1f7ebe 3525 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
e960fc5c 3526 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
0b1f7ebe 3527
1da177e4
LT		 3528 val64 = SW_RESET_ALL;
3529 writeq(val64, &bar0->sw_reset);
c92ca04b
AR		 3530 if (strstr(sp->product_name, "CX4")) {
3531 msleep(750);
3532 }
19a60522
SS		 3533 msleep(250);
3534 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
1da177e4 3535
19a60522
SS		 3536 /* Restore the PCI state saved during initialization. */
3537 pci_restore_state(sp->pdev);
3538 pci_read_config_word(sp->pdev, 0x2, &val16);
3539 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3540 break;
3541 msleep(200);
3542 }
1da177e4 3543
19a60522 3544 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
b39d66a8 3545 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __func__);
19a60522
SS		 3546 }
3547
3548 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3549
3550 s2io_init_pci(sp);
1da177e4 3551
20346722
K		 3552 /* Set swapper to enable I/O register access */
3553 s2io_set_swapper(sp);
3554
faa4f796
SH		 3555 /* restore mac_addr entries */
3556 do_s2io_restore_unicast_mc(sp);
3557
cc6e7c44
RA		 3558 /* Restore the MSIX table entries from local variables */
3559 restore_xmsi_data(sp);
3560
5e25b9dd 3561 /* Clear certain PCI/PCI-X fields after reset */
303bcb4b 3562 if (sp->device_type == XFRAME_II_DEVICE) {
b41477f3 3563 /* Clear "detected parity error" bit */
303bcb4b 3564 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
5e25b9dd 3565
303bcb4b
K		 3566 /* Clearing PCIX Ecc status register */
3567 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
5e25b9dd 3568
303bcb4b 3569 /* Clearing PCI_STATUS error reflected here */
b7b5a128 3570 writeq(s2BIT(62), &bar0->txpic_int_reg);
303bcb4b 3571 }
5e25b9dd 3572
20346722
K		 3573 /* Reset device statistics maintained by OS */
3574 memset(&sp->stats, 0, sizeof (struct net_device_stats));
8a4bdbaa 3575
491976b2
SH		 3576 up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3577 down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3578 up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3579 down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
363dc367 3580 reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
491976b2
SH		 3581 mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3582 mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3583 watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3584 /* save link up/down time/cnt, reset/memory/watchdog cnt */
363dc367 3585 memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
491976b2
SH		 3586 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3587 sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3588 sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3589 sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3590 sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
363dc367 3591 sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
491976b2
SH		 3592 sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3593 sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3594 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
20346722 3595
1da177e4
LT		 3596 /* SXE-002: Configure link and activity LED to turn it off */
3597 subid = sp->pdev->subsystem_device;
541ae68f
K		 3598 if (((subid & 0xFF) >= 0x07) &&
3599 (sp->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 3600 val64 = readq(&bar0->gpio_control);
3601 val64 |= 0x0000800000000000ULL;
3602 writeq(val64, &bar0->gpio_control);
3603 val64 = 0x0411040400000000ULL;
509a2671 3604 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 3605 }
3606
541ae68f
K		 3607 /*
3608 * Clear spurious ECC interrupts that would have occured on
3609 * XFRAME II cards after reset.
3610 */
3611 if (sp->device_type == XFRAME_II_DEVICE) {
3612 val64 = readq(&bar0->pcc_err_reg);
3613 writeq(val64, &bar0->pcc_err_reg);
3614 }
3615
f957bcf0 3616 sp->device_enabled_once = false;
1da177e4
LT		 3617}
3618
3619/**
20346722
K		 3620 * s2io_set_swapper - to set the swapper controle on the card
3621 * @sp : private member of the device structure,
1da177e4 3622 * pointer to the s2io_nic structure.
20346722 3623 * Description: Function to set the swapper control on the card
1da177e4
LT		 3624 * correctly depending on the 'endianness' of the system.
3625 * Return value:
3626 * SUCCESS on success and FAILURE on failure.
3627 */
3628
1ee6dd77 3629static int s2io_set_swapper(struct s2io_nic * sp)
1da177e4
LT		 3630{
3631 struct net_device *dev = sp->dev;
1ee6dd77 3632 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 3633 u64 val64, valt, valr;
3634
20346722 3635 /*
1da177e4
LT		 3636 * Set proper endian settings and verify the same by reading
3637 * the PIF Feed-back register.
3638 */
3639
3640 val64 = readq(&bar0->pif_rd_swapper_fb);
3641 if (val64 != 0x0123456789ABCDEFULL) {
3642 int i = 0;
3643 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3644 0x8100008181000081ULL, /* FE=1, SE=0 */
3645 0x4200004242000042ULL, /* FE=0, SE=1 */
3646 0}; /* FE=0, SE=0 */
3647
3648 while(i<4) {
3649 writeq(value[i], &bar0->swapper_ctrl);
3650 val64 = readq(&bar0->pif_rd_swapper_fb);
3651 if (val64 == 0x0123456789ABCDEFULL)
3652 break;
3653 i++;
3654 }
3655 if (i == 4) {
3656 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3657 dev->name);
3658 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3659 (unsigned long long) val64);
3660 return FAILURE;
3661 }
3662 valr = value[i];
3663 } else {
3664 valr = readq(&bar0->swapper_ctrl);
3665 }
3666
3667 valt = 0x0123456789ABCDEFULL;
3668 writeq(valt, &bar0->xmsi_address);
3669 val64 = readq(&bar0->xmsi_address);
3670
3671 if(val64 != valt) {
3672 int i = 0;
3673 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3674 0x0081810000818100ULL, /* FE=1, SE=0 */
3675 0x0042420000424200ULL, /* FE=0, SE=1 */
3676 0}; /* FE=0, SE=0 */
3677
3678 while(i<4) {
3679 writeq((value[i] | valr), &bar0->swapper_ctrl);
3680 writeq(valt, &bar0->xmsi_address);
3681 val64 = readq(&bar0->xmsi_address);
3682 if(val64 == valt)
3683 break;
3684 i++;
3685 }
3686 if(i == 4) {
20346722 3687 unsigned long long x = val64;
1da177e4 3688 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
20346722 3689 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
1da177e4
LT		 3690 return FAILURE;
3691 }
3692 }
3693 val64 = readq(&bar0->swapper_ctrl);
3694 val64 &= 0xFFFF000000000000ULL;
3695
3696#ifdef __BIG_ENDIAN
20346722
K		 3697 /*
3698 * The device by default set to a big endian format, so a
1da177e4
LT		 3699 * big endian driver need not set anything.
3700 */
3701 val64 |= (SWAPPER_CTRL_TXP_FE |
3702 SWAPPER_CTRL_TXP_SE |
3703 SWAPPER_CTRL_TXD_R_FE |
3704 SWAPPER_CTRL_TXD_W_FE |
3705 SWAPPER_CTRL_TXF_R_FE |
3706 SWAPPER_CTRL_RXD_R_FE |
3707 SWAPPER_CTRL_RXD_W_FE |
3708 SWAPPER_CTRL_RXF_W_FE |
3709 SWAPPER_CTRL_XMSI_FE |
1da177e4 3710 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
eaae7f72 3711 if (sp->config.intr_type == INTA)
cc6e7c44 3712 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3713 writeq(val64, &bar0->swapper_ctrl);
3714#else
20346722 3715 /*
1da177e4 3716 * Initially we enable all bits to make it accessible by the
20346722 3717 * driver, then we selectively enable only those bits that
1da177e4
LT		 3718 * we want to set.
3719 */
3720 val64 |= (SWAPPER_CTRL_TXP_FE |
3721 SWAPPER_CTRL_TXP_SE |
3722 SWAPPER_CTRL_TXD_R_FE |
3723 SWAPPER_CTRL_TXD_R_SE |
3724 SWAPPER_CTRL_TXD_W_FE |
3725 SWAPPER_CTRL_TXD_W_SE |
3726 SWAPPER_CTRL_TXF_R_FE |
3727 SWAPPER_CTRL_RXD_R_FE |
3728 SWAPPER_CTRL_RXD_R_SE |
3729 SWAPPER_CTRL_RXD_W_FE |
3730 SWAPPER_CTRL_RXD_W_SE |
3731 SWAPPER_CTRL_RXF_W_FE |
3732 SWAPPER_CTRL_XMSI_FE |
1da177e4 3733 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
eaae7f72 3734 if (sp->config.intr_type == INTA)
cc6e7c44 3735 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3736 writeq(val64, &bar0->swapper_ctrl);
3737#endif
3738 val64 = readq(&bar0->swapper_ctrl);
3739
20346722
K		 3740 /*
3741 * Verifying if endian settings are accurate by reading a
1da177e4
LT		 3742 * feedback register.
3743 */
3744 val64 = readq(&bar0->pif_rd_swapper_fb);
3745 if (val64 != 0x0123456789ABCDEFULL) {
3746 /* Endian settings are incorrect, calls for another dekko. */
3747 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3748 dev->name);
3749 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3750 (unsigned long long) val64);
3751 return FAILURE;
3752 }
3753
3754 return SUCCESS;
3755}
3756
1ee6dd77 3757static int wait_for_msix_trans(struct s2io_nic *nic, int i)
cc6e7c44 3758{
1ee6dd77 3759 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3760 u64 val64;
3761 int ret = 0, cnt = 0;
3762
3763 do {
3764 val64 = readq(&bar0->xmsi_access);
b7b5a128 3765 if (!(val64 & s2BIT(15)))
cc6e7c44
RA		 3766 break;
3767 mdelay(1);
3768 cnt++;
3769 } while(cnt < 5);
3770 if (cnt == 5) {
3771 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3772 ret = 1;
3773 }
3774
3775 return ret;
3776}
3777
1ee6dd77 3778static void restore_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3779{
1ee6dd77 3780 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44 3781 u64 val64;
f61e0a35
SH		 3782 int i, msix_index;
3783
3784
3785 if (nic->device_type == XFRAME_I_DEVICE)
3786 return;
cc6e7c44 3787
75c30b13 3788 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
f61e0a35 3789 msix_index = (i) ? ((i-1) * 8 + 1): 0;
cc6e7c44
RA		 3790 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3791 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
f61e0a35 3792 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
cc6e7c44 3793 writeq(val64, &bar0->xmsi_access);
f61e0a35 3794 if (wait_for_msix_trans(nic, msix_index)) {
b39d66a8 3795 DBG_PRINT(ERR_DBG, "failed in %s\n", __func__);
cc6e7c44
RA		 3796 continue;
3797 }
3798 }
3799}
3800
1ee6dd77 3801static void store_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3802{
1ee6dd77 3803 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44 3804 u64 val64, addr, data;
f61e0a35
SH		 3805 int i, msix_index;
3806
3807 if (nic->device_type == XFRAME_I_DEVICE)
3808 return;
cc6e7c44
RA		 3809
3810 /* Store and display */
75c30b13 3811 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
f61e0a35
SH		 3812 msix_index = (i) ? ((i-1) * 8 + 1): 0;
3813 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
cc6e7c44 3814 writeq(val64, &bar0->xmsi_access);
f61e0a35 3815 if (wait_for_msix_trans(nic, msix_index)) {
b39d66a8 3816 DBG_PRINT(ERR_DBG, "failed in %s\n", __func__);
cc6e7c44
RA		 3817 continue;
3818 }
3819 addr = readq(&bar0->xmsi_address);
3820 data = readq(&bar0->xmsi_data);
3821 if (addr && data) {
3822 nic->msix_info[i].addr = addr;
3823 nic->msix_info[i].data = data;
3824 }
3825 }
3826}
3827
1ee6dd77 3828static int s2io_enable_msi_x(struct s2io_nic *nic)
cc6e7c44 3829{
1ee6dd77 3830 struct XENA_dev_config __iomem *bar0 = nic->bar0;
ac731ab6 3831 u64 rx_mat;
cc6e7c44
RA		 3832 u16 msi_control; /* Temp variable */
3833 int ret, i, j, msix_indx = 1;
4f870320 3834 int size;
cc6e7c44 3835
4f870320
JP		 3836 size = nic->num_entries * sizeof(struct msix_entry);
3837 nic->entries = kmalloc(size, GFP_KERNEL);
bd684e43 3838 if (!nic->entries) {
491976b2 3839 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", \
b39d66a8 3840 __func__);
c53d4945 3841 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
cc6e7c44
RA		 3842 return -ENOMEM;
3843 }
4f870320 3844 nic->mac_control.stats_info->sw_stat.mem_allocated += size;
f61e0a35 3845
4f870320 3846 memset(nic->entries, 0, size);
cc6e7c44 3847
4f870320
JP		 3848 size = nic->num_entries * sizeof(struct s2io_msix_entry);
3849 nic->s2io_entries = kmalloc(size, GFP_KERNEL);
bd684e43 3850 if (!nic->s2io_entries) {
8a4bdbaa 3851 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
b39d66a8 3852 __func__);
c53d4945 3853 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
cc6e7c44 3854 kfree(nic->entries);
8a4bdbaa 3855 nic->mac_control.stats_info->sw_stat.mem_freed
f61e0a35 3856 += (nic->num_entries * sizeof(struct msix_entry));
cc6e7c44
RA		 3857 return -ENOMEM;
3858 }
4f870320
JP		 3859 nic->mac_control.stats_info->sw_stat.mem_allocated += size;
3860 memset(nic->s2io_entries, 0, size);
cc6e7c44 3861
ac731ab6
SH		 3862 nic->entries[0].entry = 0;
3863 nic->s2io_entries[0].entry = 0;
3864 nic->s2io_entries[0].in_use = MSIX_FLG;
3865 nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3866 nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3867
f61e0a35
SH		 3868 for (i = 1; i < nic->num_entries; i++) {
3869 nic->entries[i].entry = ((i - 1) * 8) + 1;
3870 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
cc6e7c44
RA		 3871 nic->s2io_entries[i].arg = NULL;
3872 nic->s2io_entries[i].in_use = 0;
3873 }
3874
8a4bdbaa 3875 rx_mat = readq(&bar0->rx_mat);
f61e0a35 3876 for (j = 0; j < nic->config.rx_ring_num; j++) {
8a4bdbaa 3877 rx_mat |= RX_MAT_SET(j, msix_indx);
f61e0a35
SH		 3878 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3879 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3880 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3881 msix_indx += 8;
cc6e7c44 3882 }
8a4bdbaa 3883 writeq(rx_mat, &bar0->rx_mat);
f61e0a35 3884 readq(&bar0->rx_mat);
cc6e7c44 3885
f61e0a35 3886 ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
c92ca04b 3887 /* We fail init if error or we get less vectors than min required */
cc6e7c44 3888 if (ret) {
073a2436 3889 DBG_PRINT(ERR_DBG, "s2io: Enabling MSI-X failed\n");
cc6e7c44 3890 kfree(nic->entries);
8a4bdbaa 3891 nic->mac_control.stats_info->sw_stat.mem_freed
f61e0a35 3892 += (nic->num_entries * sizeof(struct msix_entry));
cc6e7c44 3893 kfree(nic->s2io_entries);
8a4bdbaa 3894 nic->mac_control.stats_info->sw_stat.mem_freed
f61e0a35 3895 += (nic->num_entries * sizeof(struct s2io_msix_entry));
cc6e7c44
RA		 3896 nic->entries = NULL;
3897 nic->s2io_entries = NULL;
3898 return -ENOMEM;
3899 }
3900
3901 /*
3902 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3903 * in the herc NIC. (Temp change, needs to be removed later)
3904 */
3905 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3906 msi_control |= 0x1; /* Enable MSI */
3907 pci_write_config_word(nic->pdev, 0x42, msi_control);
3908
3909 return 0;
3910}
3911
8abc4d5b 3912/* Handle software interrupt used during MSI(X) test */
33390a70 3913static irqreturn_t s2io_test_intr(int irq, void *dev_id)
8abc4d5b
SS		 3914{
3915 struct s2io_nic *sp = dev_id;
3916
3917 sp->msi_detected = 1;
3918 wake_up(&sp->msi_wait);
3919
3920 return IRQ_HANDLED;
3921}
3922
3923/* Test interrupt path by forcing a a software IRQ */
33390a70 3924static int s2io_test_msi(struct s2io_nic *sp)
8abc4d5b
SS		 3925{
3926 struct pci_dev *pdev = sp->pdev;
3927 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3928 int err;
3929 u64 val64, saved64;
3930
3931 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3932 sp->name, sp);
3933 if (err) {
3934 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3935 sp->dev->name, pci_name(pdev), pdev->irq);
3936 return err;
3937 }
3938
3939 init_waitqueue_head (&sp->msi_wait);
3940 sp->msi_detected = 0;
3941
3942 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3943 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3944 val64 |= SCHED_INT_CTRL_TIMER_EN;
3945 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3946 writeq(val64, &bar0->scheduled_int_ctrl);
3947
3948 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3949
3950 if (!sp->msi_detected) {
3951 /* MSI(X) test failed, go back to INTx mode */
2450022a 3952 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
8abc4d5b
SS		 3953 "using MSI(X) during test\n", sp->dev->name,
3954 pci_name(pdev));
3955
3956 err = -EOPNOTSUPP;
3957 }
3958
3959 free_irq(sp->entries[1].vector, sp);
3960
3961 writeq(saved64, &bar0->scheduled_int_ctrl);
3962
3963 return err;
3964}
18b2b7bd
SH		 3965
3966static void remove_msix_isr(struct s2io_nic *sp)
3967{
3968 int i;
3969 u16 msi_control;
3970
f61e0a35 3971 for (i = 0; i < sp->num_entries; i++) {
18b2b7bd
SH		 3972 if (sp->s2io_entries[i].in_use ==
3973 MSIX_REGISTERED_SUCCESS) {
3974 int vector = sp->entries[i].vector;
3975 void *arg = sp->s2io_entries[i].arg;
3976 free_irq(vector, arg);
3977 }
3978 }
3979
3980 kfree(sp->entries);
3981 kfree(sp->s2io_entries);
3982 sp->entries = NULL;
3983 sp->s2io_entries = NULL;
3984
3985 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3986 msi_control &= 0xFFFE; /* Disable MSI */
3987 pci_write_config_word(sp->pdev, 0x42, msi_control);
3988
3989 pci_disable_msix(sp->pdev);
3990}
3991
3992static void remove_inta_isr(struct s2io_nic *sp)
3993{
3994 struct net_device *dev = sp->dev;
3995
3996 free_irq(sp->pdev->irq, dev);
3997}
3998
1da177e4
LT		 3999/* ********************************************************* *
4000 * Functions defined below concern the OS part of the driver *
4001 * ********************************************************* */
4002
20346722 4003/**
1da177e4
LT		 4004 * s2io_open - open entry point of the driver
4005 * @dev : pointer to the device structure.
4006 * Description:
4007 * This function is the open entry point of the driver. It mainly calls a
4008 * function to allocate Rx buffers and inserts them into the buffer
20346722 4009 * descriptors and then enables the Rx part of the NIC.
1da177e4
LT		 4010 * Return value:
4011 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4012 * file on failure.
4013 */
4014
ac1f60db 4015static int s2io_open(struct net_device *dev)
1da177e4 4016{
4cf1653a 4017 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 4018 int err = 0;
4019
20346722
K		 4020 /*
4021 * Make sure you have link off by default every time
1da177e4
LT		 4022 * Nic is initialized
4023 */
4024 netif_carrier_off(dev);
0b1f7ebe 4025 sp->last_link_state = 0;
1da177e4
LT		 4026
4027 /* Initialize H/W and enable interrupts */
c92ca04b
AR		 4028 err = s2io_card_up(sp);
4029 if (err) {
1da177e4
LT		 4030 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
4031 dev->name);
e6a8fee2 4032 goto hw_init_failed;
1da177e4
LT		 4033 }
4034
2fd37688 4035 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
1da177e4 4036 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
e6a8fee2 4037 s2io_card_down(sp);
20346722 4038 err = -ENODEV;
e6a8fee2 4039 goto hw_init_failed;
1da177e4 4040 }
3a3d5756 4041 s2io_start_all_tx_queue(sp);
1da177e4 4042 return 0;
20346722 4043
20346722 4044hw_init_failed:
eaae7f72 4045 if (sp->config.intr_type == MSI_X) {
491976b2 4046 if (sp->entries) {
cc6e7c44 4047 kfree(sp->entries);
8a4bdbaa 4048 sp->mac_control.stats_info->sw_stat.mem_freed
f61e0a35 4049 += (sp->num_entries * sizeof(struct msix_entry));
491976b2
SH		 4050 }
4051 if (sp->s2io_entries) {
cc6e7c44 4052 kfree(sp->s2io_entries);
8a4bdbaa 4053 sp->mac_control.stats_info->sw_stat.mem_freed
f61e0a35 4054 += (sp->num_entries * sizeof(struct s2io_msix_entry));
491976b2 4055 }
cc6e7c44 4056 }
20346722 4057 return err;
1da177e4
LT		 4058}
4059
4060/**
4061 * s2io_close -close entry point of the driver
4062 * @dev : device pointer.
4063 * Description:
4064 * This is the stop entry point of the driver. It needs to undo exactly
4065 * whatever was done by the open entry point,thus it's usually referred to
4066 * as the close function.Among other things this function mainly stops the
4067 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4068 * Return value:
4069 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4070 * file on failure.
4071 */
4072
ac1f60db 4073static int s2io_close(struct net_device *dev)
1da177e4 4074{
4cf1653a 4075 struct s2io_nic *sp = netdev_priv(dev);
faa4f796
SH		 4076 struct config_param *config = &sp->config;
4077 u64 tmp64;
4078 int offset;
cc6e7c44 4079
9f74ffde
SH		 4080 /* Return if the device is already closed *
4081 * Can happen when s2io_card_up failed in change_mtu *
4082 */
4083 if (!is_s2io_card_up(sp))
4084 return 0;
4085
3a3d5756 4086 s2io_stop_all_tx_queue(sp);
faa4f796
SH		 4087 /* delete all populated mac entries */
4088 for (offset = 1; offset < config->max_mc_addr; offset++) {
4089 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4090 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4091 do_s2io_delete_unicast_mc(sp, tmp64);
4092 }
4093
e6a8fee2 4094 s2io_card_down(sp);
cc6e7c44 4095
1da177e4
LT		 4096 return 0;
4097}
4098
4099/**
4100 * s2io_xmit - Tx entry point of te driver
4101 * @skb : the socket buffer containing the Tx data.
4102 * @dev : device pointer.
4103 * Description :
4104 * This function is the Tx entry point of the driver. S2IO NIC supports
4105 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4106 * NOTE: when device cant queue the pkt,just the trans_start variable will
4107 * not be upadted.
4108 * Return value:
4109 * 0 on success & 1 on failure.
4110 */
4111
ac1f60db 4112static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 4113{
4cf1653a 4114 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 4115 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4116 register u64 val64;
1ee6dd77
RB		 4117 struct TxD *txdp;
4118 struct TxFIFO_element __iomem *tx_fifo;
2fda096d 4119 unsigned long flags = 0;
be3a6b02 4120 u16 vlan_tag = 0;
2fda096d 4121 struct fifo_info *fifo = NULL;
1ee6dd77 4122 struct mac_info *mac_control;
1da177e4 4123 struct config_param *config;
6cfc482b 4124 int do_spin_lock = 1;
75c30b13 4125 int offload_type;
6cfc482b 4126 int enable_per_list_interrupt = 0;
491abf25 4127 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 4128
4129 mac_control = &sp->mac_control;
4130 config = &sp->config;
4131
20346722 4132 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
491976b2
SH		 4133
4134 if (unlikely(skb->len <= 0)) {
4135 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
4136 dev_kfree_skb_any(skb);
6ed10654 4137 return NETDEV_TX_OK;
2fda096d 4138 }
491976b2 4139
92b84437 4140 if (!is_s2io_card_up(sp)) {
20346722 4141 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
1da177e4 4142 dev->name);
20346722 4143 dev_kfree_skb(skb);
6ed10654 4144 return NETDEV_TX_OK;
1da177e4
LT		 4145 }
4146
4147 queue = 0;
3a3d5756 4148 if (sp->vlgrp && vlan_tx_tag_present(skb))
be3a6b02 4149 vlan_tag = vlan_tx_tag_get(skb);
6cfc482b
SH		 4150 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4151 if (skb->protocol == htons(ETH_P_IP)) {
4152 struct iphdr *ip;
4153 struct tcphdr *th;
4154 ip = ip_hdr(skb);
4155
4156 if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4157 th = (struct tcphdr *)(((unsigned char *)ip) +
4158 ip->ihl*4);
4159
4160 if (ip->protocol == IPPROTO_TCP) {
4161 queue_len = sp->total_tcp_fifos;
4162 queue = (ntohs(th->source) +
4163 ntohs(th->dest)) &
4164 sp->fifo_selector[queue_len - 1];
4165 if (queue >= queue_len)
4166 queue = queue_len - 1;
4167 } else if (ip->protocol == IPPROTO_UDP) {
4168 queue_len = sp->total_udp_fifos;
4169 queue = (ntohs(th->source) +
4170 ntohs(th->dest)) &
4171 sp->fifo_selector[queue_len - 1];
4172 if (queue >= queue_len)
4173 queue = queue_len - 1;
4174 queue += sp->udp_fifo_idx;
4175 if (skb->len > 1024)
4176 enable_per_list_interrupt = 1;
4177 do_spin_lock = 0;
4178 }
4179 }
4180 }
4181 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4182 /* get fifo number based on skb->priority value */
4183 queue = config->fifo_mapping
4184 [skb->priority & (MAX_TX_FIFOS - 1)];
4185 fifo = &mac_control->fifos[queue];
3a3d5756 4186
6cfc482b
SH		 4187 if (do_spin_lock)
4188 spin_lock_irqsave(&fifo->tx_lock, flags);
4189 else {
4190 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4191 return NETDEV_TX_LOCKED;
4192 }
be3a6b02 4193
3a3d5756
SH		 4194 if (sp->config.multiq) {
4195 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4196 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4197 return NETDEV_TX_BUSY;
4198 }
b19fa1fa 4199 } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
3a3d5756
SH		 4200 if (netif_queue_stopped(dev)) {
4201 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4202 return NETDEV_TX_BUSY;
4203 }
4204 }
4205
2fda096d
SR		 4206 put_off = (u16) fifo->tx_curr_put_info.offset;
4207 get_off = (u16) fifo->tx_curr_get_info.offset;
4208 txdp = (struct TxD *) fifo->list_info[put_off].list_virt_addr;
20346722 4209
2fda096d 4210 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
1da177e4 4211 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9
AR		 4212 if (txdp->Host_Control ||
4213 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
776bd20f 4214 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3a3d5756 4215 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4216 dev_kfree_skb(skb);
2fda096d 4217 spin_unlock_irqrestore(&fifo->tx_lock, flags);
6ed10654 4218 return NETDEV_TX_OK;
1da177e4 4219 }
0b1f7ebe 4220
75c30b13 4221 offload_type = s2io_offload_type(skb);
75c30b13 4222 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1da177e4 4223 txdp->Control_1 |= TXD_TCP_LSO_EN;
75c30b13 4224 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
1da177e4 4225 }
84fa7933 4226 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 4227 txdp->Control_2 |=
4228 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
4229 TXD_TX_CKO_UDP_EN);
4230 }
fed5eccd
AR		 4231 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4232 txdp->Control_1 |= TXD_LIST_OWN_XENA;
2fda096d 4233 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
6cfc482b
SH		 4234 if (enable_per_list_interrupt)
4235 if (put_off & (queue_len >> 5))
4236 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
3a3d5756 4237 if (vlan_tag) {
be3a6b02
K		 4238 txdp->Control_2 |= TXD_VLAN_ENABLE;
4239 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4240 }
4241
fed5eccd 4242 frg_len = skb->len - skb->data_len;
75c30b13 4243 if (offload_type == SKB_GSO_UDP) {
fed5eccd
AR		 4244 int ufo_size;
4245
75c30b13 4246 ufo_size = s2io_udp_mss(skb);
fed5eccd
AR		 4247 ufo_size &= ~7;
4248 txdp->Control_1 |= TXD_UFO_EN;
4249 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4250 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4251#ifdef __BIG_ENDIAN
3459feb8 4252 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
2fda096d 4253 fifo->ufo_in_band_v[put_off] =
3459feb8 4254 (__force u64)skb_shinfo(skb)->ip6_frag_id;
fed5eccd 4255#else
2fda096d 4256 fifo->ufo_in_band_v[put_off] =
3459feb8 4257 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
fed5eccd 4258#endif
2fda096d 4259 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
fed5eccd 4260 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
2fda096d 4261 fifo->ufo_in_band_v,
fed5eccd 4262 sizeof(u64), PCI_DMA_TODEVICE);
8d8bb39b 4263 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
491abf25 4264 goto pci_map_failed;
fed5eccd 4265 txdp++;
fed5eccd 4266 }
1da177e4 4267
fed5eccd
AR		 4268 txdp->Buffer_Pointer = pci_map_single
4269 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
8d8bb39b 4270 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
491abf25
VP		 4271 goto pci_map_failed;
4272
fed5eccd
AR		 4273 txdp->Host_Control = (unsigned long) skb;
4274 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
75c30b13 4275 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4276 txdp->Control_1 |= TXD_UFO_EN;
4277
4278 frg_cnt = skb_shinfo(skb)->nr_frags;
1da177e4
LT		 4279 /* For fragmented SKB. */
4280 for (i = 0; i < frg_cnt; i++) {
4281 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0b1f7ebe
K		 4282 /* A '0' length fragment will be ignored */
4283 if (!frag->size)
4284 continue;
1da177e4
LT		 4285 txdp++;
4286 txdp->Buffer_Pointer = (u64) pci_map_page
4287 (sp->pdev, frag->page, frag->page_offset,
4288 frag->size, PCI_DMA_TODEVICE);
efd51b5c 4289 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
75c30b13 4290 if (offload_type == SKB_GSO_UDP)
fed5eccd 4291 txdp->Control_1 |= TXD_UFO_EN;
1da177e4
LT		 4292 }
4293 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4294
75c30b13 4295 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4296 frg_cnt++; /* as Txd0 was used for inband header */
4297
1da177e4 4298 tx_fifo = mac_control->tx_FIFO_start[queue];
2fda096d 4299 val64 = fifo->list_info[put_off].list_phy_addr;
1da177e4
LT		 4300 writeq(val64, &tx_fifo->TxDL_Pointer);
4301
4302 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4303 TX_FIFO_LAST_LIST);
75c30b13 4304 if (offload_type)
fed5eccd 4305 val64 |= TX_FIFO_SPECIAL_FUNC;
75c30b13 4306
1da177e4
LT		 4307 writeq(val64, &tx_fifo->List_Control);
4308
303bcb4b
K		 4309 mmiowb();
4310
1da177e4 4311 put_off++;
2fda096d 4312 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
863c11a9 4313 put_off = 0;
2fda096d 4314 fifo->tx_curr_put_info.offset = put_off;
1da177e4
LT		 4315
4316 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4317 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
bd1034f0 4318 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
1da177e4
LT		 4319 DBG_PRINT(TX_DBG,
4320 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4321 put_off, get_off);
3a3d5756 4322 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4323 }
491976b2 4324 mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
2fda096d 4325 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4 4326
f6f4bfa3
SH		 4327 if (sp->config.intr_type == MSI_X)
4328 tx_intr_handler(fifo);
4329
6ed10654 4330 return NETDEV_TX_OK;
491abf25
VP		 4331pci_map_failed:
4332 stats->pci_map_fail_cnt++;
3a3d5756 4333 s2io_stop_tx_queue(sp, fifo->fifo_no);
491abf25
VP		 4334 stats->mem_freed += skb->truesize;
4335 dev_kfree_skb(skb);
2fda096d 4336 spin_unlock_irqrestore(&fifo->tx_lock, flags);
6ed10654 4337 return NETDEV_TX_OK;
1da177e4
LT		 4338}
4339
25fff88e
K		 4340static void
4341s2io_alarm_handle(unsigned long data)
4342{
1ee6dd77 4343 struct s2io_nic *sp = (struct s2io_nic *)data;
8116f3cf 4344 struct net_device *dev = sp->dev;
25fff88e 4345
8116f3cf 4346 s2io_handle_errors(dev);
25fff88e
K		 4347 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4348}
4349
7d12e780 4350static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
cc6e7c44 4351{
1ee6dd77
RB		 4352 struct ring_info *ring = (struct ring_info *)dev_id;
4353 struct s2io_nic *sp = ring->nic;
f61e0a35 4354 struct XENA_dev_config __iomem *bar0 = sp->bar0;
cc6e7c44 4355
f61e0a35 4356 if (unlikely(!is_s2io_card_up(sp)))
92b84437 4357 return IRQ_HANDLED;
92b84437 4358
f61e0a35 4359 if (sp->config.napi) {
1a79d1c3
AV		 4360 u8 __iomem *addr = NULL;
4361 u8 val8 = 0;
f61e0a35 4362
1a79d1c3 4363 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
f61e0a35
SH		 4364 addr += (7 - ring->ring_no);
4365 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4366 writeb(val8, addr);
4367 val8 = readb(addr);
288379f0 4368 napi_schedule(&ring->napi);
f61e0a35
SH		 4369 } else {
4370 rx_intr_handler(ring, 0);
8d8bb39b 4371 s2io_chk_rx_buffers(sp, ring);
f61e0a35 4372 }
7d3d0439 4373
cc6e7c44
RA		 4374 return IRQ_HANDLED;
4375}
4376
7d12e780 4377static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
cc6e7c44 4378{
ac731ab6
SH		 4379 int i;
4380 struct fifo_info *fifos = (struct fifo_info *)dev_id;
4381 struct s2io_nic *sp = fifos->nic;
4382 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4383 struct config_param *config = &sp->config;
4384 u64 reason;
cc6e7c44 4385
ac731ab6
SH		 4386 if (unlikely(!is_s2io_card_up(sp)))
4387 return IRQ_NONE;
4388
4389 reason = readq(&bar0->general_int_status);
4390 if (unlikely(reason == S2IO_MINUS_ONE))
4391 /* Nothing much can be done. Get out */
92b84437 4392 return IRQ_HANDLED;
92b84437 4393
01e16faa
SH		 4394 if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4395 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
ac731ab6 4396
01e16faa
SH		 4397 if (reason & GEN_INTR_TXPIC)
4398 s2io_txpic_intr_handle(sp);
ac731ab6 4399
01e16faa
SH		 4400 if (reason & GEN_INTR_TXTRAFFIC)
4401 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
ac731ab6 4402
01e16faa
SH		 4403 for (i = 0; i < config->tx_fifo_num; i++)
4404 tx_intr_handler(&fifos[i]);
ac731ab6 4405
01e16faa
SH		 4406 writeq(sp->general_int_mask, &bar0->general_int_mask);
4407 readl(&bar0->general_int_status);
4408 return IRQ_HANDLED;
4409 }
4410 /* The interrupt was not raised by us */
4411 return IRQ_NONE;
cc6e7c44 4412}
ac731ab6 4413
1ee6dd77 4414static void s2io_txpic_intr_handle(struct s2io_nic *sp)
a371a07d 4415{
1ee6dd77 4416 struct XENA_dev_config __iomem *bar0 = sp->bar0;
a371a07d
K		 4417 u64 val64;
4418
4419 val64 = readq(&bar0->pic_int_status);
4420 if (val64 & PIC_INT_GPIO) {
4421 val64 = readq(&bar0->gpio_int_reg);
4422 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4423 (val64 & GPIO_INT_REG_LINK_UP)) {
c92ca04b
AR		 4424 /*
4425 * This is unstable state so clear both up/down
4426 * interrupt and adapter to re-evaluate the link state.
4427 */
a371a07d
K		 4428 val64 |= GPIO_INT_REG_LINK_DOWN;
4429 val64 |= GPIO_INT_REG_LINK_UP;
4430 writeq(val64, &bar0->gpio_int_reg);
a371a07d 4431 val64 = readq(&bar0->gpio_int_mask);
c92ca04b
AR		 4432 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4433 GPIO_INT_MASK_LINK_DOWN);
a371a07d 4434 writeq(val64, &bar0->gpio_int_mask);
a371a07d 4435 }
c92ca04b
AR		 4436 else if (val64 & GPIO_INT_REG_LINK_UP) {
4437 val64 = readq(&bar0->adapter_status);
c92ca04b 4438 /* Enable Adapter */
19a60522
SS		 4439 val64 = readq(&bar0->adapter_control);
4440 val64 |= ADAPTER_CNTL_EN;
4441 writeq(val64, &bar0->adapter_control);
4442 val64 |= ADAPTER_LED_ON;
4443 writeq(val64, &bar0->adapter_control);
4444 if (!sp->device_enabled_once)
4445 sp->device_enabled_once = 1;
c92ca04b 4446
19a60522
SS		 4447 s2io_link(sp, LINK_UP);
4448 /*
4449 * unmask link down interrupt and mask link-up
4450 * intr
4451 */
4452 val64 = readq(&bar0->gpio_int_mask);
4453 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4454 val64 |= GPIO_INT_MASK_LINK_UP;
4455 writeq(val64, &bar0->gpio_int_mask);
c92ca04b 4456
c92ca04b
AR		 4457 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4458 val64 = readq(&bar0->adapter_status);
19a60522
SS		 4459 s2io_link(sp, LINK_DOWN);
4460 /* Link is down so unmaks link up interrupt */
4461 val64 = readq(&bar0->gpio_int_mask);
4462 val64 &= ~GPIO_INT_MASK_LINK_UP;
4463 val64 |= GPIO_INT_MASK_LINK_DOWN;
4464 writeq(val64, &bar0->gpio_int_mask);
ac1f90d6
SS		 4465
4466 /* turn off LED */
4467 val64 = readq(&bar0->adapter_control);
4468 val64 = val64 &(~ADAPTER_LED_ON);
4469 writeq(val64, &bar0->adapter_control);
a371a07d
K		 4470 }
4471 }
c92ca04b 4472 val64 = readq(&bar0->gpio_int_mask);
a371a07d
K		 4473}
4474
8116f3cf
SS		 4475/**
4476 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4477 * @value: alarm bits
4478 * @addr: address value
4479 * @cnt: counter variable
4480 * Description: Check for alarm and increment the counter
4481 * Return Value:
4482 * 1 - if alarm bit set
4483 * 0 - if alarm bit is not set
4484 */
43b7c451 4485static int do_s2io_chk_alarm_bit(u64 value, void __iomem * addr,
8116f3cf
SS		 4486 unsigned long long *cnt)
4487{
4488 u64 val64;
4489 val64 = readq(addr);
4490 if ( val64 & value ) {
4491 writeq(val64, addr);
4492 (*cnt)++;
4493 return 1;
4494 }
4495 return 0;
4496
4497}
4498
4499/**
4500 * s2io_handle_errors - Xframe error indication handler
4501 * @nic: device private variable
4502 * Description: Handle alarms such as loss of link, single or
4503 * double ECC errors, critical and serious errors.
4504 * Return Value:
4505 * NONE
4506 */
4507static void s2io_handle_errors(void * dev_id)
4508{
4509 struct net_device *dev = (struct net_device *) dev_id;
4cf1653a 4510 struct s2io_nic *sp = netdev_priv(dev);
8116f3cf
SS		 4511 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4512 u64 temp64 = 0,val64=0;
4513 int i = 0;
4514
4515 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4516 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4517
92b84437 4518 if (!is_s2io_card_up(sp))
8116f3cf
SS		 4519 return;
4520
4521 if (pci_channel_offline(sp->pdev))
4522 return;
4523
4524 memset(&sw_stat->ring_full_cnt, 0,
4525 sizeof(sw_stat->ring_full_cnt));
4526
4527 /* Handling the XPAK counters update */
4528 if(stats->xpak_timer_count < 72000) {
4529 /* waiting for an hour */
4530 stats->xpak_timer_count++;
4531 } else {
4532 s2io_updt_xpak_counter(dev);
4533 /* reset the count to zero */
4534 stats->xpak_timer_count = 0;
4535 }
4536
4537 /* Handling link status change error Intr */
4538 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4539 val64 = readq(&bar0->mac_rmac_err_reg);
4540 writeq(val64, &bar0->mac_rmac_err_reg);
4541 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4542 schedule_work(&sp->set_link_task);
4543 }
4544
4545 /* In case of a serious error, the device will be Reset. */
4546 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4547 &sw_stat->serious_err_cnt))
4548 goto reset;
4549
4550 /* Check for data parity error */
4551 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4552 &sw_stat->parity_err_cnt))
4553 goto reset;
4554
4555 /* Check for ring full counter */
4556 if (sp->device_type == XFRAME_II_DEVICE) {
4557 val64 = readq(&bar0->ring_bump_counter1);
4558 for (i=0; i<4; i++) {
4559 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4560 temp64 >>= 64 - ((i+1)*16);
4561 sw_stat->ring_full_cnt[i] += temp64;
4562 }
4563
4564 val64 = readq(&bar0->ring_bump_counter2);
4565 for (i=0; i<4; i++) {
4566 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4567 temp64 >>= 64 - ((i+1)*16);
4568 sw_stat->ring_full_cnt[i+4] += temp64;
4569 }
4570 }
4571
4572 val64 = readq(&bar0->txdma_int_status);
4573 /*check for pfc_err*/
4574 if (val64 & TXDMA_PFC_INT) {
4575 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM|
4576 PFC_MISC_0_ERR | PFC_MISC_1_ERR|
4577 PFC_PCIX_ERR, &bar0->pfc_err_reg,
4578 &sw_stat->pfc_err_cnt))
4579 goto reset;
4580 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR, &bar0->pfc_err_reg,
4581 &sw_stat->pfc_err_cnt);
4582 }
4583
4584 /*check for tda_err*/
4585 if (val64 & TXDMA_TDA_INT) {
4586 if(do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
4587 TDA_SM1_ERR_ALARM, &bar0->tda_err_reg,
4588 &sw_stat->tda_err_cnt))
4589 goto reset;
4590 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4591 &bar0->tda_err_reg, &sw_stat->tda_err_cnt);
4592 }
4593 /*check for pcc_err*/
4594 if (val64 & TXDMA_PCC_INT) {
4595 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM
4596 | PCC_N_SERR | PCC_6_COF_OV_ERR
4597 | PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR
4598 | PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR
4599 | PCC_TXB_ECC_DB_ERR, &bar0->pcc_err_reg,
4600 &sw_stat->pcc_err_cnt))
4601 goto reset;
4602 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4603 &bar0->pcc_err_reg, &sw_stat->pcc_err_cnt);
4604 }
4605
4606 /*check for tti_err*/
4607 if (val64 & TXDMA_TTI_INT) {
4608 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM, &bar0->tti_err_reg,
4609 &sw_stat->tti_err_cnt))
4610 goto reset;
4611 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4612 &bar0->tti_err_reg, &sw_stat->tti_err_cnt);
4613 }
4614
4615 /*check for lso_err*/
4616 if (val64 & TXDMA_LSO_INT) {
4617 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT
4618 | LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4619 &bar0->lso_err_reg, &sw_stat->lso_err_cnt))
4620 goto reset;
4621 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4622 &bar0->lso_err_reg, &sw_stat->lso_err_cnt);
4623 }
4624
4625 /*check for tpa_err*/
4626 if (val64 & TXDMA_TPA_INT) {
4627 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM, &bar0->tpa_err_reg,
4628 &sw_stat->tpa_err_cnt))
4629 goto reset;
4630 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP, &bar0->tpa_err_reg,
4631 &sw_stat->tpa_err_cnt);
4632 }
4633
4634 /*check for sm_err*/
4635 if (val64 & TXDMA_SM_INT) {
4636 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM, &bar0->sm_err_reg,
4637 &sw_stat->sm_err_cnt))
4638 goto reset;
4639 }
4640
4641 val64 = readq(&bar0->mac_int_status);
4642 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4643 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4644 &bar0->mac_tmac_err_reg,
4645 &sw_stat->mac_tmac_err_cnt))
4646 goto reset;
4647 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR
4648 | TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
4649 &bar0->mac_tmac_err_reg,
4650 &sw_stat->mac_tmac_err_cnt);
4651 }
4652
4653 val64 = readq(&bar0->xgxs_int_status);
4654 if (val64 & XGXS_INT_STATUS_TXGXS) {
4655 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4656 &bar0->xgxs_txgxs_err_reg,
4657 &sw_stat->xgxs_txgxs_err_cnt))
4658 goto reset;
4659 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4660 &bar0->xgxs_txgxs_err_reg,
4661 &sw_stat->xgxs_txgxs_err_cnt);
4662 }
4663
4664 val64 = readq(&bar0->rxdma_int_status);
4665 if (val64 & RXDMA_INT_RC_INT_M) {
4666 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR
4667 | RC_PRCn_SM_ERR_ALARM |RC_FTC_SM_ERR_ALARM,
4668 &bar0->rc_err_reg, &sw_stat->rc_err_cnt))
4669 goto reset;
4670 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR
4671 | RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4672 &sw_stat->rc_err_cnt);
4673 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn
4674 | PRC_PCI_AB_F_WR_Rn, &bar0->prc_pcix_err_reg,
4675 &sw_stat->prc_pcix_err_cnt))
4676 goto reset;
4677 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn | PRC_PCI_DP_WR_Rn
4678 | PRC_PCI_DP_F_WR_Rn, &bar0->prc_pcix_err_reg,
4679 &sw_stat->prc_pcix_err_cnt);
4680 }
4681
4682 if (val64 & RXDMA_INT_RPA_INT_M) {
4683 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4684 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt))
4685 goto reset;
4686 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4687 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt);
4688 }
4689
4690 if (val64 & RXDMA_INT_RDA_INT_M) {
4691 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR
4692 | RDA_FRM_ECC_DB_N_AERR | RDA_SM1_ERR_ALARM
4693 | RDA_SM0_ERR_ALARM | RDA_RXD_ECC_DB_SERR,
4694 &bar0->rda_err_reg, &sw_stat->rda_err_cnt))
4695 goto reset;
4696 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR | RDA_FRM_ECC_SG_ERR
4697 | RDA_MISC_ERR | RDA_PCIX_ERR,
4698 &bar0->rda_err_reg, &sw_stat->rda_err_cnt);
4699 }
4700
4701 if (val64 & RXDMA_INT_RTI_INT_M) {
4702 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM, &bar0->rti_err_reg,
4703 &sw_stat->rti_err_cnt))
4704 goto reset;
4705 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4706 &bar0->rti_err_reg, &sw_stat->rti_err_cnt);
4707 }
4708
4709 val64 = readq(&bar0->mac_int_status);
4710 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4711 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4712 &bar0->mac_rmac_err_reg,
4713 &sw_stat->mac_rmac_err_cnt))
4714 goto reset;
4715 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT|RMAC_SINGLE_ECC_ERR|
4716 RMAC_DOUBLE_ECC_ERR, &bar0->mac_rmac_err_reg,
4717 &sw_stat->mac_rmac_err_cnt);
4718 }
4719
4720 val64 = readq(&bar0->xgxs_int_status);
4721 if (val64 & XGXS_INT_STATUS_RXGXS) {
4722 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4723 &bar0->xgxs_rxgxs_err_reg,
4724 &sw_stat->xgxs_rxgxs_err_cnt))
4725 goto reset;
4726 }
4727
4728 val64 = readq(&bar0->mc_int_status);
4729 if(val64 & MC_INT_STATUS_MC_INT) {
4730 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR, &bar0->mc_err_reg,
4731 &sw_stat->mc_err_cnt))
4732 goto reset;
4733
4734 /* Handling Ecc errors */
4735 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4736 writeq(val64, &bar0->mc_err_reg);
4737 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4738 sw_stat->double_ecc_errs++;
4739 if (sp->device_type != XFRAME_II_DEVICE) {
4740 /*
4741 * Reset XframeI only if critical error
4742 */
4743 if (val64 &
4744 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4745 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4746 goto reset;
4747 }
4748 } else
4749 sw_stat->single_ecc_errs++;
4750 }
4751 }
4752 return;
4753
4754reset:
3a3d5756 4755 s2io_stop_all_tx_queue(sp);
8116f3cf
SS		 4756 schedule_work(&sp->rst_timer_task);
4757 sw_stat->soft_reset_cnt++;
4758 return;
4759}
4760
1da177e4
LT		 4761/**
4762 * s2io_isr - ISR handler of the device .
4763 * @irq: the irq of the device.
4764 * @dev_id: a void pointer to the dev structure of the NIC.
20346722
K		 4765 * Description: This function is the ISR handler of the device. It
4766 * identifies the reason for the interrupt and calls the relevant
4767 * service routines. As a contongency measure, this ISR allocates the
1da177e4
LT		 4768 * recv buffers, if their numbers are below the panic value which is
4769 * presently set to 25% of the original number of rcv buffers allocated.
4770 * Return value:
20346722 4771 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
1da177e4
LT		 4772 * IRQ_NONE: will be returned if interrupt is not from our device
4773 */
7d12e780 4774static irqreturn_t s2io_isr(int irq, void *dev_id)
1da177e4
LT		 4775{
4776 struct net_device *dev = (struct net_device *) dev_id;
4cf1653a 4777 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 4778 struct XENA_dev_config __iomem *bar0 = sp->bar0;
20346722 4779 int i;
19a60522 4780 u64 reason = 0;
1ee6dd77 4781 struct mac_info *mac_control;
1da177e4
LT		 4782 struct config_param *config;
4783
d796fdb7
LV		 4784 /* Pretend we handled any irq's from a disconnected card */
4785 if (pci_channel_offline(sp->pdev))
4786 return IRQ_NONE;
4787
596c5c97 4788 if (!is_s2io_card_up(sp))
92b84437 4789 return IRQ_NONE;
92b84437 4790
1da177e4
LT		 4791 mac_control = &sp->mac_control;
4792 config = &sp->config;
4793
20346722 4794 /*
1da177e4
LT		 4795 * Identify the cause for interrupt and call the appropriate
4796 * interrupt handler. Causes for the interrupt could be;
4797 * 1. Rx of packet.
4798 * 2. Tx complete.
4799 * 3. Link down.
1da177e4
LT		 4800 */
4801 reason = readq(&bar0->general_int_status);
4802
596c5c97
SS		 4803 if (unlikely(reason == S2IO_MINUS_ONE) ) {
4804 /* Nothing much can be done. Get out */
4805 return IRQ_HANDLED;
1da177e4 4806 }
5d3213cc 4807
596c5c97
SS		 4808 if (reason & (GEN_INTR_RXTRAFFIC |
4809 GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC))
4810 {
4811 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4812
4813 if (config->napi) {
4814 if (reason & GEN_INTR_RXTRAFFIC) {
288379f0 4815 napi_schedule(&sp->napi);
f61e0a35
SH		 4816 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4817 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4818 readl(&bar0->rx_traffic_int);
db874e65 4819 }
596c5c97
SS		 4820 } else {
4821 /*
4822 * rx_traffic_int reg is an R1 register, writing all 1's
4823 * will ensure that the actual interrupt causing bit
4824 * get's cleared and hence a read can be avoided.
4825 */
4826 if (reason & GEN_INTR_RXTRAFFIC)
19a60522 4827 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
596c5c97 4828
13d866a9
JP		 4829 for (i = 0; i < config->rx_ring_num; i++) {
4830 struct ring_info *ring = &mac_control->rings[i];
4831
4832 rx_intr_handler(ring, 0);
4833 }
db874e65 4834 }
596c5c97 4835
db874e65 4836 /*
596c5c97 4837 * tx_traffic_int reg is an R1 register, writing all 1's
db874e65
SS		 4838 * will ensure that the actual interrupt causing bit get's
4839 * cleared and hence a read can be avoided.
4840 */
596c5c97
SS		 4841 if (reason & GEN_INTR_TXTRAFFIC)
4842 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
19a60522 4843
596c5c97
SS		 4844 for (i = 0; i < config->tx_fifo_num; i++)
4845 tx_intr_handler(&mac_control->fifos[i]);
1da177e4 4846
596c5c97
SS		 4847 if (reason & GEN_INTR_TXPIC)
4848 s2io_txpic_intr_handle(sp);
fe113638 4849
596c5c97
SS		 4850 /*
4851 * Reallocate the buffers from the interrupt handler itself.
4852 */
4853 if (!config->napi) {
13d866a9
JP		 4854 for (i = 0; i < config->rx_ring_num; i++) {
4855 struct ring_info *ring = &mac_control->rings[i];
4856
4857 s2io_chk_rx_buffers(sp, ring);
4858 }
596c5c97
SS		 4859 }
4860 writeq(sp->general_int_mask, &bar0->general_int_mask);
4861 readl(&bar0->general_int_status);
20346722 4862
596c5c97 4863 return IRQ_HANDLED;
db874e65 4864
596c5c97
SS		 4865 }
4866 else if (!reason) {
4867 /* The interrupt was not raised by us */
4868 return IRQ_NONE;
4869 }
db874e65 4870
1da177e4
LT		 4871 return IRQ_HANDLED;
4872}
4873
7ba013ac
K		 4874/**
4875 * s2io_updt_stats -
4876 */
1ee6dd77 4877static void s2io_updt_stats(struct s2io_nic *sp)
7ba013ac 4878{
1ee6dd77 4879 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7ba013ac
K		 4880 u64 val64;
4881 int cnt = 0;
4882
92b84437 4883 if (is_s2io_card_up(sp)) {
7ba013ac
K		 4884 /* Apprx 30us on a 133 MHz bus */
4885 val64 = SET_UPDT_CLICKS(10) |
4886 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4887 writeq(val64, &bar0->stat_cfg);
4888 do {
4889 udelay(100);
4890 val64 = readq(&bar0->stat_cfg);
b7b5a128 4891 if (!(val64 & s2BIT(0)))
7ba013ac
K		 4892 break;
4893 cnt++;
4894 if (cnt == 5)
4895 break; /* Updt failed */
4896 } while(1);
8a4bdbaa 4897 }
7ba013ac
K		 4898}
4899
1da177e4 4900/**
20346722 4901 * s2io_get_stats - Updates the device statistics structure.
1da177e4
LT		 4902 * @dev : pointer to the device structure.
4903 * Description:
20346722 4904 * This function updates the device statistics structure in the s2io_nic
1da177e4
LT		 4905 * structure and returns a pointer to the same.
4906 * Return value:
4907 * pointer to the updated net_device_stats structure.
4908 */
4909
ac1f60db 4910static struct net_device_stats *s2io_get_stats(struct net_device *dev)
1da177e4 4911{
4cf1653a 4912 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 4913 struct mac_info *mac_control;
1da177e4 4914 struct config_param *config;
0425b46a 4915 int i;
1da177e4 4916
20346722 4917
1da177e4
LT		 4918 mac_control = &sp->mac_control;
4919 config = &sp->config;
4920
7ba013ac
K		 4921 /* Configure Stats for immediate updt */
4922 s2io_updt_stats(sp);
4923
dc56e634
BL		 4924 /* Using sp->stats as a staging area, because reset (due to mtu
4925 change, for example) will clear some hardware counters */
4926 dev->stats.tx_packets +=
4927 le32_to_cpu(mac_control->stats_info->tmac_frms) -
4928 sp->stats.tx_packets;
7ba013ac
K		 4929 sp->stats.tx_packets =
4930 le32_to_cpu(mac_control->stats_info->tmac_frms);
dc56e634
BL		 4931 dev->stats.tx_errors +=
4932 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms) -
4933 sp->stats.tx_errors;
20346722
K		 4934 sp->stats.tx_errors =
4935 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
dc56e634
BL		 4936 dev->stats.rx_errors +=
4937 le64_to_cpu(mac_control->stats_info->rmac_drop_frms) -
4938 sp->stats.rx_errors;
20346722 4939 sp->stats.rx_errors =
ee705dba 4940 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
dc56e634
BL		 4941 dev->stats.multicast =
4942 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms) -
4943 sp->stats.multicast;
20346722
K		 4944 sp->stats.multicast =
4945 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
dc56e634
BL		 4946 dev->stats.rx_length_errors =
4947 le64_to_cpu(mac_control->stats_info->rmac_long_frms) -
4948 sp->stats.rx_length_errors;
1da177e4 4949 sp->stats.rx_length_errors =
ee705dba 4950 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
1da177e4 4951
0425b46a 4952 /* collect per-ring rx_packets and rx_bytes */
dc56e634 4953 dev->stats.rx_packets = dev->stats.rx_bytes = 0;
0425b46a 4954 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 4955 struct ring_info *ring = &mac_control->rings[i];
4956
4957 dev->stats.rx_packets += ring->rx_packets;
4958 dev->stats.rx_bytes += ring->rx_bytes;
0425b46a
SH		 4959 }
4960
dc56e634 4961 return (&dev->stats);
1da177e4
LT		 4962}
4963
4964/**
4965 * s2io_set_multicast - entry point for multicast address enable/disable.
4966 * @dev : pointer to the device structure
4967 * Description:
20346722
K		 4968 * This function is a driver entry point which gets called by the kernel
4969 * whenever multicast addresses must be enabled/disabled. This also gets
1da177e4
LT		 4970 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4971 * determine, if multicast address must be enabled or if promiscuous mode
4972 * is to be disabled etc.
4973 * Return value:
4974 * void.
4975 */
4976
4977static void s2io_set_multicast(struct net_device *dev)
4978{
4979 int i, j, prev_cnt;
4980 struct dev_mc_list *mclist;
4cf1653a 4981 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 4982 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4983 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4984 0xfeffffffffffULL;
faa4f796 4985 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
1da177e4 4986 void __iomem *add;
faa4f796 4987 struct config_param *config = &sp->config;
1da177e4
LT		 4988
4989 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4990 /* Enable all Multicast addresses */
4991 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4992 &bar0->rmac_addr_data0_mem);
4993 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4994 &bar0->rmac_addr_data1_mem);
4995 val64 = RMAC_ADDR_CMD_MEM_WE |
4996 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
faa4f796 4997 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
1da177e4
LT		 4998 writeq(val64, &bar0->rmac_addr_cmd_mem);
4999 /* Wait till command completes */
c92ca04b 5000 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 5001 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5002 S2IO_BIT_RESET);
1da177e4
LT		 5003
5004 sp->m_cast_flg = 1;
faa4f796 5005 sp->all_multi_pos = config->max_mc_addr - 1;
1da177e4
LT		 5006 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
5007 /* Disable all Multicast addresses */
5008 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5009 &bar0->rmac_addr_data0_mem);
5e25b9dd
K		 5010 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
5011 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 5012 val64 = RMAC_ADDR_CMD_MEM_WE |
5013 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5014 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
5015 writeq(val64, &bar0->rmac_addr_cmd_mem);
5016 /* Wait till command completes */
c92ca04b 5017 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 5018 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5019 S2IO_BIT_RESET);
1da177e4
LT		 5020
5021 sp->m_cast_flg = 0;
5022 sp->all_multi_pos = 0;
5023 }
5024
5025 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
5026 /* Put the NIC into promiscuous mode */
5027 add = &bar0->mac_cfg;
5028 val64 = readq(&bar0->mac_cfg);
5029 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5030
5031 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5032 writel((u32) val64, add);
5033 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5034 writel((u32) (val64 >> 32), (add + 4));
5035
926930b2
SS		 5036 if (vlan_tag_strip != 1) {
5037 val64 = readq(&bar0->rx_pa_cfg);
5038 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5039 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 5040 sp->vlan_strip_flag = 0;
926930b2
SS		 5041 }
5042
1da177e4
LT		 5043 val64 = readq(&bar0->mac_cfg);
5044 sp->promisc_flg = 1;
776bd20f 5045 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
1da177e4
LT		 5046 dev->name);
5047 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5048 /* Remove the NIC from promiscuous mode */
5049 add = &bar0->mac_cfg;
5050 val64 = readq(&bar0->mac_cfg);
5051 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5052
5053 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5054 writel((u32) val64, add);
5055 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5056 writel((u32) (val64 >> 32), (add + 4));
5057
926930b2
SS		 5058 if (vlan_tag_strip != 0) {
5059 val64 = readq(&bar0->rx_pa_cfg);
5060 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5061 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 5062 sp->vlan_strip_flag = 1;
926930b2
SS		 5063 }
5064
1da177e4
LT		 5065 val64 = readq(&bar0->mac_cfg);
5066 sp->promisc_flg = 0;
776bd20f 5067 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
1da177e4
LT		 5068 dev->name);
5069 }
5070
5071 /* Update individual M_CAST address list */
5072 if ((!sp->m_cast_flg) && dev->mc_count) {
5073 if (dev->mc_count >
faa4f796 5074 (config->max_mc_addr - config->max_mac_addr)) {
1da177e4
LT		 5075 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
5076 dev->name);
5077 DBG_PRINT(ERR_DBG, "can be added, please enable ");
5078 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
5079 return;
5080 }
5081
5082 prev_cnt = sp->mc_addr_count;
5083 sp->mc_addr_count = dev->mc_count;
5084
5085 /* Clear out the previous list of Mc in the H/W. */
5086 for (i = 0; i < prev_cnt; i++) {
5087 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5088 &bar0->rmac_addr_data0_mem);
5089 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 5090 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 5091 val64 = RMAC_ADDR_CMD_MEM_WE |
5092 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5093 RMAC_ADDR_CMD_MEM_OFFSET
faa4f796 5094 (config->mc_start_offset + i);
1da177e4
LT		 5095 writeq(val64, &bar0->rmac_addr_cmd_mem);
5096
5097 /* Wait for command completes */
c92ca04b 5098 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 5099 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5100 S2IO_BIT_RESET)) {
1da177e4
LT		 5101 DBG_PRINT(ERR_DBG, "%s: Adding ",
5102 dev->name);
5103 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5104 return;
5105 }
5106 }
5107
5108 /* Create the new Rx filter list and update the same in H/W. */
5109 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
5110 i++, mclist = mclist->next) {
5111 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
5112 ETH_ALEN);
a7a80d5a 5113 mac_addr = 0;
1da177e4
LT		 5114 for (j = 0; j < ETH_ALEN; j++) {
5115 mac_addr |= mclist->dmi_addr[j];
5116 mac_addr <<= 8;
5117 }
5118 mac_addr >>= 8;
5119 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5120 &bar0->rmac_addr_data0_mem);
5121 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 5122 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 5123 val64 = RMAC_ADDR_CMD_MEM_WE |
5124 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5125 RMAC_ADDR_CMD_MEM_OFFSET
faa4f796 5126 (i + config->mc_start_offset);
1da177e4
LT		 5127 writeq(val64, &bar0->rmac_addr_cmd_mem);
5128
5129 /* Wait for command completes */
c92ca04b 5130 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 5131 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5132 S2IO_BIT_RESET)) {
1da177e4
LT		 5133 DBG_PRINT(ERR_DBG, "%s: Adding ",
5134 dev->name);
5135 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5136 return;
5137 }
5138 }
5139 }
5140}
5141
faa4f796
SH		 5142/* read from CAM unicast & multicast addresses and store it in
5143 * def_mac_addr structure
5144 */
dac499f9 5145static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
faa4f796
SH		 5146{
5147 int offset;
5148 u64 mac_addr = 0x0;
5149 struct config_param *config = &sp->config;
5150
5151 /* store unicast & multicast mac addresses */
5152 for (offset = 0; offset < config->max_mc_addr; offset++) {
5153 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5154 /* if read fails disable the entry */
5155 if (mac_addr == FAILURE)
5156 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5157 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5158 }
5159}
5160
5161/* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5162static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5163{
5164 int offset;
5165 struct config_param *config = &sp->config;
5166 /* restore unicast mac address */
5167 for (offset = 0; offset < config->max_mac_addr; offset++)
5168 do_s2io_prog_unicast(sp->dev,
5169 sp->def_mac_addr[offset].mac_addr);
5170
5171 /* restore multicast mac address */
5172 for (offset = config->mc_start_offset;
5173 offset < config->max_mc_addr; offset++)
5174 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5175}
5176
5177/* add a multicast MAC address to CAM */
5178static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5179{
5180 int i;
5181 u64 mac_addr = 0;
5182 struct config_param *config = &sp->config;
5183
5184 for (i = 0; i < ETH_ALEN; i++) {
5185 mac_addr <<= 8;
5186 mac_addr |= addr[i];
5187 }
5188 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5189 return SUCCESS;
5190
5191 /* check if the multicast mac already preset in CAM */
5192 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5193 u64 tmp64;
5194 tmp64 = do_s2io_read_unicast_mc(sp, i);
5195 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5196 break;
5197
5198 if (tmp64 == mac_addr)
5199 return SUCCESS;
5200 }
5201 if (i == config->max_mc_addr) {
5202 DBG_PRINT(ERR_DBG,
5203 "CAM full no space left for multicast MAC\n");
5204 return FAILURE;
5205 }
5206 /* Update the internal structure with this new mac address */
5207 do_s2io_copy_mac_addr(sp, i, mac_addr);
5208
5209 return (do_s2io_add_mac(sp, mac_addr, i));
5210}
5211
5212/* add MAC address to CAM */
5213static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
2fd37688
SS		 5214{
5215 u64 val64;
5216 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5217
5218 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5219 &bar0->rmac_addr_data0_mem);
5220
5221 val64 =
5222 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5223 RMAC_ADDR_CMD_MEM_OFFSET(off);
5224 writeq(val64, &bar0->rmac_addr_cmd_mem);
5225
5226 /* Wait till command completes */
5227 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5228 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5229 S2IO_BIT_RESET)) {
faa4f796 5230 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
2fd37688
SS		 5231 return FAILURE;
5232 }
5233 return SUCCESS;
5234}
faa4f796
SH		 5235/* deletes a specified unicast/multicast mac entry from CAM */
5236static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5237{
5238 int offset;
5239 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5240 struct config_param *config = &sp->config;
5241
5242 for (offset = 1;
5243 offset < config->max_mc_addr; offset++) {
5244 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5245 if (tmp64 == addr) {
5246 /* disable the entry by writing 0xffffffffffffULL */
5247 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5248 return FAILURE;
5249 /* store the new mac list from CAM */
5250 do_s2io_store_unicast_mc(sp);
5251 return SUCCESS;
5252 }
5253 }
5254 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5255 (unsigned long long)addr);
5256 return FAILURE;
5257}
5258
5259/* read mac entries from CAM */
5260static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5261{
5262 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5263 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5264
5265 /* read mac addr */
5266 val64 =
5267 RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5268 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5269 writeq(val64, &bar0->rmac_addr_cmd_mem);
5270
5271 /* Wait till command completes */
5272 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5273 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5274 S2IO_BIT_RESET)) {
5275 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5276 return FAILURE;
5277 }
5278 tmp64 = readq(&bar0->rmac_addr_data0_mem);
5279 return (tmp64 >> 16);
5280}
2fd37688
SS		 5281
5282/**
5283 * s2io_set_mac_addr driver entry point
5284 */
faa4f796 5285
2fd37688
SS		 5286static int s2io_set_mac_addr(struct net_device *dev, void *p)
5287{
5288 struct sockaddr *addr = p;
5289
5290 if (!is_valid_ether_addr(addr->sa_data))
5291 return -EINVAL;
5292
5293 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5294
5295 /* store the MAC address in CAM */
5296 return (do_s2io_prog_unicast(dev, dev->dev_addr));
5297}
1da177e4 5298/**
2fd37688 5299 * do_s2io_prog_unicast - Programs the Xframe mac address
1da177e4
LT		 5300 * @dev : pointer to the device structure.
5301 * @addr: a uchar pointer to the new mac address which is to be set.
20346722 5302 * Description : This procedure will program the Xframe to receive
1da177e4 5303 * frames with new Mac Address
20346722 5304 * Return value: SUCCESS on success and an appropriate (-)ve integer
1da177e4
LT		 5305 * as defined in errno.h file on failure.
5306 */
faa4f796 5307
2fd37688 5308static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
1da177e4 5309{
4cf1653a 5310 struct s2io_nic *sp = netdev_priv(dev);
2fd37688 5311 register u64 mac_addr = 0, perm_addr = 0;
1da177e4 5312 int i;
faa4f796
SH		 5313 u64 tmp64;
5314 struct config_param *config = &sp->config;
1da177e4 5315
20346722 5316 /*
2fd37688
SS		 5317 * Set the new MAC address as the new unicast filter and reflect this
5318 * change on the device address registered with the OS. It will be
5319 * at offset 0.
5320 */
1da177e4
LT		 5321 for (i = 0; i < ETH_ALEN; i++) {
5322 mac_addr <<= 8;
5323 mac_addr |= addr[i];
2fd37688
SS		 5324 perm_addr <<= 8;
5325 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
d8d70caf
SS		 5326 }
5327
2fd37688
SS		 5328 /* check if the dev_addr is different than perm_addr */
5329 if (mac_addr == perm_addr)
d8d70caf
SS		 5330 return SUCCESS;
5331
faa4f796
SH		 5332 /* check if the mac already preset in CAM */
5333 for (i = 1; i < config->max_mac_addr; i++) {
5334 tmp64 = do_s2io_read_unicast_mc(sp, i);
5335 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5336 break;
5337
5338 if (tmp64 == mac_addr) {
5339 DBG_PRINT(INFO_DBG,
5340 "MAC addr:0x%llx already present in CAM\n",
5341 (unsigned long long)mac_addr);
5342 return SUCCESS;
5343 }
5344 }
5345 if (i == config->max_mac_addr) {
5346 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5347 return FAILURE;
5348 }
d8d70caf 5349 /* Update the internal structure with this new mac address */
faa4f796
SH		 5350 do_s2io_copy_mac_addr(sp, i, mac_addr);
5351 return (do_s2io_add_mac(sp, mac_addr, i));
1da177e4
LT		 5352}
5353
5354/**
20346722 5355 * s2io_ethtool_sset - Sets different link parameters.
1da177e4
LT		 5356 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5357 * @info: pointer to the structure with parameters given by ethtool to set
5358 * link information.
5359 * Description:
20346722 5360 * The function sets different link parameters provided by the user onto
1da177e4
LT		 5361 * the NIC.
5362 * Return value:
5363 * 0 on success.
5364*/
5365
5366static int s2io_ethtool_sset(struct net_device *dev,
5367 struct ethtool_cmd *info)
5368{
4cf1653a 5369 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5370 if ((info->autoneg == AUTONEG_ENABLE) ||
5371 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
5372 return -EINVAL;
5373 else {
5374 s2io_close(sp->dev);
5375 s2io_open(sp->dev);
5376 }
5377
5378 return 0;
5379}
5380
5381/**
20346722 5382 * s2io_ethtol_gset - Return link specific information.
1da177e4
LT		 5383 * @sp : private member of the device structure, pointer to the
5384 * s2io_nic structure.
5385 * @info : pointer to the structure with parameters given by ethtool
5386 * to return link information.
5387 * Description:
5388 * Returns link specific information like speed, duplex etc.. to ethtool.
5389 * Return value :
5390 * return 0 on success.
5391 */
5392
5393static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5394{
4cf1653a 5395 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5396 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5397 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5398 info->port = PORT_FIBRE;
1a7eb72b
SS		 5399
5400 /* info->transceiver */
5401 info->transceiver = XCVR_EXTERNAL;
1da177e4
LT		 5402
5403 if (netif_carrier_ok(sp->dev)) {
5404 info->speed = 10000;
5405 info->duplex = DUPLEX_FULL;
5406 } else {
5407 info->speed = -1;
5408 info->duplex = -1;
5409 }
5410
5411 info->autoneg = AUTONEG_DISABLE;
5412 return 0;
5413}
5414
5415/**
20346722
K		 5416 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5417 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5418 * s2io_nic structure.
5419 * @info : pointer to the structure with parameters given by ethtool to
5420 * return driver information.
5421 * Description:
5422 * Returns driver specefic information like name, version etc.. to ethtool.
5423 * Return value:
5424 * void
5425 */
5426
5427static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5428 struct ethtool_drvinfo *info)
5429{
4cf1653a 5430 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 5431
dbc2309d
JL		 5432 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5433 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5434 strncpy(info->fw_version, "", sizeof(info->fw_version));
5435 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
1da177e4
LT		 5436 info->regdump_len = XENA_REG_SPACE;
5437 info->eedump_len = XENA_EEPROM_SPACE;
1da177e4
LT		 5438}
5439
5440/**
5441 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
20346722 5442 * @sp: private member of the device structure, which is a pointer to the
1da177e4 5443 * s2io_nic structure.
20346722 5444 * @regs : pointer to the structure with parameters given by ethtool for
1da177e4
LT		 5445 * dumping the registers.
5446 * @reg_space: The input argumnet into which all the registers are dumped.
5447 * Description:
5448 * Dumps the entire register space of xFrame NIC into the user given
5449 * buffer area.
5450 * Return value :
5451 * void .
5452*/
5453
5454static void s2io_ethtool_gregs(struct net_device *dev,
5455 struct ethtool_regs *regs, void *space)
5456{
5457 int i;
5458 u64 reg;
5459 u8 *reg_space = (u8 *) space;
4cf1653a 5460 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5461
5462 regs->len = XENA_REG_SPACE;
5463 regs->version = sp->pdev->subsystem_device;
5464
5465 for (i = 0; i < regs->len; i += 8) {
5466 reg = readq(sp->bar0 + i);
5467 memcpy((reg_space + i), &reg, 8);
5468 }
5469}
5470
5471/**
5472 * s2io_phy_id - timer function that alternates adapter LED.
20346722 5473 * @data : address of the private member of the device structure, which
1da177e4 5474 * is a pointer to the s2io_nic structure, provided as an u32.
20346722
K		 5475 * Description: This is actually the timer function that alternates the
5476 * adapter LED bit of the adapter control bit to set/reset every time on
5477 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
1da177e4
LT		 5478 * once every second.
5479*/
5480static void s2io_phy_id(unsigned long data)
5481{
1ee6dd77
RB		 5482 struct s2io_nic *sp = (struct s2io_nic *) data;
5483 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5484 u64 val64 = 0;
5485 u16 subid;
5486
5487 subid = sp->pdev->subsystem_device;
541ae68f
K		 5488 if ((sp->device_type == XFRAME_II_DEVICE) ||
5489 ((subid & 0xFF) >= 0x07)) {
1da177e4
LT		 5490 val64 = readq(&bar0->gpio_control);
5491 val64 ^= GPIO_CTRL_GPIO_0;
5492 writeq(val64, &bar0->gpio_control);
5493 } else {
5494 val64 = readq(&bar0->adapter_control);
5495 val64 ^= ADAPTER_LED_ON;
5496 writeq(val64, &bar0->adapter_control);
5497 }
5498
5499 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5500}
5501
5502/**
5503 * s2io_ethtool_idnic - To physically identify the nic on the system.
5504 * @sp : private member of the device structure, which is a pointer to the
5505 * s2io_nic structure.
20346722 5506 * @id : pointer to the structure with identification parameters given by
1da177e4
LT		 5507 * ethtool.
5508 * Description: Used to physically identify the NIC on the system.
20346722 5509 * The Link LED will blink for a time specified by the user for
1da177e4 5510 * identification.
20346722 5511 * NOTE: The Link has to be Up to be able to blink the LED. Hence
1da177e4
LT		 5512 * identification is possible only if it's link is up.
5513 * Return value:
5514 * int , returns 0 on success
5515 */
5516
5517static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5518{
5519 u64 val64 = 0, last_gpio_ctrl_val;
4cf1653a 5520 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5521 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5522 u16 subid;
5523
5524 subid = sp->pdev->subsystem_device;
5525 last_gpio_ctrl_val = readq(&bar0->gpio_control);
541ae68f
K		 5526 if ((sp->device_type == XFRAME_I_DEVICE) &&
5527 ((subid & 0xFF) < 0x07)) {
1da177e4
LT		 5528 val64 = readq(&bar0->adapter_control);
5529 if (!(val64 & ADAPTER_CNTL_EN)) {
5530 printk(KERN_ERR
5531 "Adapter Link down, cannot blink LED\n");
5532 return -EFAULT;
5533 }
5534 }
5535 if (sp->id_timer.function == NULL) {
5536 init_timer(&sp->id_timer);
5537 sp->id_timer.function = s2io_phy_id;
5538 sp->id_timer.data = (unsigned long) sp;
5539 }
5540 mod_timer(&sp->id_timer, jiffies);
5541 if (data)
20346722 5542 msleep_interruptible(data * HZ);
1da177e4 5543 else
20346722 5544 msleep_interruptible(MAX_FLICKER_TIME);
1da177e4
LT		 5545 del_timer_sync(&sp->id_timer);
5546
541ae68f 5547 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
1da177e4
LT		 5548 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5549 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5550 }
5551
5552 return 0;
5553}
5554
0cec35eb
SH		 5555static void s2io_ethtool_gringparam(struct net_device *dev,
5556 struct ethtool_ringparam *ering)
5557{
4cf1653a 5558 struct s2io_nic *sp = netdev_priv(dev);
0cec35eb
SH		 5559 int i,tx_desc_count=0,rx_desc_count=0;
5560
5561 if (sp->rxd_mode == RXD_MODE_1)
5562 ering->rx_max_pending = MAX_RX_DESC_1;
5563 else if (sp->rxd_mode == RXD_MODE_3B)
5564 ering->rx_max_pending = MAX_RX_DESC_2;
0cec35eb
SH		 5565
5566 ering->tx_max_pending = MAX_TX_DESC;
8a4bdbaa 5567 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
0cec35eb 5568 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
8a4bdbaa 5569
0cec35eb
SH		 5570 DBG_PRINT(INFO_DBG,"\nmax txds : %d\n",sp->config.max_txds);
5571 ering->tx_pending = tx_desc_count;
5572 rx_desc_count = 0;
8a4bdbaa 5573 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
0cec35eb 5574 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
b6627672 5575
0cec35eb
SH		 5576 ering->rx_pending = rx_desc_count;
5577
5578 ering->rx_mini_max_pending = 0;
5579 ering->rx_mini_pending = 0;
5580 if(sp->rxd_mode == RXD_MODE_1)
5581 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5582 else if (sp->rxd_mode == RXD_MODE_3B)
5583 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5584 ering->rx_jumbo_pending = rx_desc_count;
5585}
5586
1da177e4
LT		 5587/**
5588 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
20346722
K		 5589 * @sp : private member of the device structure, which is a pointer to the
5590 * s2io_nic structure.
1da177e4
LT		 5591 * @ep : pointer to the structure with pause parameters given by ethtool.
5592 * Description:
5593 * Returns the Pause frame generation and reception capability of the NIC.
5594 * Return value:
5595 * void
5596 */
5597static void s2io_ethtool_getpause_data(struct net_device *dev,
5598 struct ethtool_pauseparam *ep)
5599{
5600 u64 val64;
4cf1653a 5601 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5602 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5603
5604 val64 = readq(&bar0->rmac_pause_cfg);
5605 if (val64 & RMAC_PAUSE_GEN_ENABLE)
f957bcf0 5606 ep->tx_pause = true;
1da177e4 5607 if (val64 & RMAC_PAUSE_RX_ENABLE)
f957bcf0
TK		 5608 ep->rx_pause = true;
5609 ep->autoneg = false;
1da177e4
LT		 5610}
5611
5612/**
5613 * s2io_ethtool_setpause_data - set/reset pause frame generation.
20346722 5614 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5615 * s2io_nic structure.
5616 * @ep : pointer to the structure with pause parameters given by ethtool.
5617 * Description:
5618 * It can be used to set or reset Pause frame generation or reception
5619 * support of the NIC.
5620 * Return value:
5621 * int, returns 0 on Success
5622 */
5623
5624static int s2io_ethtool_setpause_data(struct net_device *dev,
20346722 5625 struct ethtool_pauseparam *ep)
1da177e4
LT		 5626{
5627 u64 val64;
4cf1653a 5628 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5629 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5630
5631 val64 = readq(&bar0->rmac_pause_cfg);
5632 if (ep->tx_pause)
5633 val64 |= RMAC_PAUSE_GEN_ENABLE;
5634 else
5635 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5636 if (ep->rx_pause)
5637 val64 |= RMAC_PAUSE_RX_ENABLE;
5638 else
5639 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5640 writeq(val64, &bar0->rmac_pause_cfg);
5641 return 0;
5642}
5643
5644/**
5645 * read_eeprom - reads 4 bytes of data from user given offset.
20346722 5646 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5647 * s2io_nic structure.
5648 * @off : offset at which the data must be written
5649 * @data : Its an output parameter where the data read at the given
20346722 5650 * offset is stored.
1da177e4 5651 * Description:
20346722 5652 * Will read 4 bytes of data from the user given offset and return the
1da177e4
LT		 5653 * read data.
5654 * NOTE: Will allow to read only part of the EEPROM visible through the
5655 * I2C bus.
5656 * Return value:
5657 * -1 on failure and 0 on success.
5658 */
5659
5660#define S2IO_DEV_ID 5
1ee6dd77 5661static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
1da177e4
LT		 5662{
5663 int ret = -1;
5664 u32 exit_cnt = 0;
5665 u64 val64;
1ee6dd77 5666 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5667
ad4ebed0 5668 if (sp->device_type == XFRAME_I_DEVICE) {
5669 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5670 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
5671 I2C_CONTROL_CNTL_START;
5672 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
1da177e4 5673
ad4ebed0 5674 while (exit_cnt < 5) {
5675 val64 = readq(&bar0->i2c_control);
5676 if (I2C_CONTROL_CNTL_END(val64)) {
5677 *data = I2C_CONTROL_GET_DATA(val64);
5678 ret = 0;
5679 break;
5680 }
5681 msleep(50);
5682 exit_cnt++;
1da177e4 5683 }
1da177e4
LT		 5684 }
5685
ad4ebed0 5686 if (sp->device_type == XFRAME_II_DEVICE) {
5687 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5688 SPI_CONTROL_BYTECNT(0x3) |
ad4ebed0 5689 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5690 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5691 val64 |= SPI_CONTROL_REQ;
5692 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5693 while (exit_cnt < 5) {
5694 val64 = readq(&bar0->spi_control);
5695 if (val64 & SPI_CONTROL_NACK) {
5696 ret = 1;
5697 break;
5698 } else if (val64 & SPI_CONTROL_DONE) {
5699 *data = readq(&bar0->spi_data);
5700 *data &= 0xffffff;
5701 ret = 0;
5702 break;
5703 }
5704 msleep(50);
5705 exit_cnt++;
5706 }
5707 }
1da177e4
LT		 5708 return ret;
5709}
5710
5711/**
5712 * write_eeprom - actually writes the relevant part of the data value.
5713 * @sp : private member of the device structure, which is a pointer to the
5714 * s2io_nic structure.
5715 * @off : offset at which the data must be written
5716 * @data : The data that is to be written
20346722 5717 * @cnt : Number of bytes of the data that are actually to be written into
1da177e4
LT		 5718 * the Eeprom. (max of 3)
5719 * Description:
5720 * Actually writes the relevant part of the data value into the Eeprom
5721 * through the I2C bus.
5722 * Return value:
5723 * 0 on success, -1 on failure.
5724 */
5725
1ee6dd77 5726static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
1da177e4
LT		 5727{
5728 int exit_cnt = 0, ret = -1;
5729 u64 val64;
1ee6dd77 5730 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5731
ad4ebed0 5732 if (sp->device_type == XFRAME_I_DEVICE) {
5733 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5734 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
5735 I2C_CONTROL_CNTL_START;
5736 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5737
5738 while (exit_cnt < 5) {
5739 val64 = readq(&bar0->i2c_control);
5740 if (I2C_CONTROL_CNTL_END(val64)) {
5741 if (!(val64 & I2C_CONTROL_NACK))
5742 ret = 0;
5743 break;
5744 }
5745 msleep(50);
5746 exit_cnt++;
5747 }
5748 }
1da177e4 5749
ad4ebed0 5750 if (sp->device_type == XFRAME_II_DEVICE) {
5751 int write_cnt = (cnt == 8) ? 0 : cnt;
5752 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
5753
5754 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5755 SPI_CONTROL_BYTECNT(write_cnt) |
ad4ebed0 5756 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5757 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5758 val64 |= SPI_CONTROL_REQ;
5759 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5760 while (exit_cnt < 5) {
5761 val64 = readq(&bar0->spi_control);
5762 if (val64 & SPI_CONTROL_NACK) {
5763 ret = 1;
5764 break;
5765 } else if (val64 & SPI_CONTROL_DONE) {
1da177e4 5766 ret = 0;
ad4ebed0 5767 break;
5768 }
5769 msleep(50);
5770 exit_cnt++;
1da177e4 5771 }
1da177e4 5772 }
1da177e4
LT		 5773 return ret;
5774}
1ee6dd77 5775static void s2io_vpd_read(struct s2io_nic *nic)
9dc737a7 5776{
b41477f3
AR		 5777 u8 *vpd_data;
5778 u8 data;
9dc737a7
AR		 5779 int i=0, cnt, fail = 0;
5780 int vpd_addr = 0x80;
5781
5782 if (nic->device_type == XFRAME_II_DEVICE) {
5783 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5784 vpd_addr = 0x80;
5785 }
5786 else {
5787 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5788 vpd_addr = 0x50;
5789 }
19a60522 5790 strcpy(nic->serial_num, "NOT AVAILABLE");
9dc737a7 5791
b41477f3 5792 vpd_data = kmalloc(256, GFP_KERNEL);
c53d4945
SH		 5793 if (!vpd_data) {
5794 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
b41477f3 5795 return;
c53d4945 5796 }
491976b2 5797 nic->mac_control.stats_info->sw_stat.mem_allocated += 256;
b41477f3 5798
9dc737a7
AR		 5799 for (i = 0; i < 256; i +=4 ) {
5800 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5801 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5802 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5803 for (cnt = 0; cnt <5; cnt++) {
5804 msleep(2);
5805 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5806 if (data == 0x80)
5807 break;
5808 }
5809 if (cnt >= 5) {
5810 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5811 fail = 1;
5812 break;
5813 }
5814 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5815 (u32 *)&vpd_data[i]);
5816 }
19a60522
SS		 5817
5818 if(!fail) {
5819 /* read serial number of adapter */
5820 for (cnt = 0; cnt < 256; cnt++) {
5821 if ((vpd_data[cnt] == 'S') &&
5822 (vpd_data[cnt+1] == 'N') &&
5823 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5824 memset(nic->serial_num, 0, VPD_STRING_LEN);
5825 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5826 vpd_data[cnt+2]);
5827 break;
5828 }
5829 }
5830 }
5831
5832 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
9dc737a7
AR		 5833 memset(nic->product_name, 0, vpd_data[1]);
5834 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5835 }
b41477f3 5836 kfree(vpd_data);
491976b2 5837 nic->mac_control.stats_info->sw_stat.mem_freed += 256;
9dc737a7
AR		 5838}
5839
1da177e4
LT		 5840/**
5841 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5842 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
20346722 5843 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5844 * containing all relevant information.
5845 * @data_buf : user defined value to be written into Eeprom.
5846 * Description: Reads the values stored in the Eeprom at given offset
5847 * for a given length. Stores these values int the input argument data
5848 * buffer 'data_buf' and returns these to the caller (ethtool.)
5849 * Return value:
5850 * int 0 on success
5851 */
5852
5853static int s2io_ethtool_geeprom(struct net_device *dev,
20346722 5854 struct ethtool_eeprom *eeprom, u8 * data_buf)
1da177e4 5855{
ad4ebed0 5856 u32 i, valid;
5857 u64 data;
4cf1653a 5858 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5859
5860 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5861
5862 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5863 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5864
5865 for (i = 0; i < eeprom->len; i += 4) {
5866 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5867 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5868 return -EFAULT;
5869 }
5870 valid = INV(data);
5871 memcpy((data_buf + i), &valid, 4);
5872 }
5873 return 0;
5874}
5875
5876/**
5877 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5878 * @sp : private member of the device structure, which is a pointer to the
5879 * s2io_nic structure.
20346722 5880 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5881 * containing all relevant information.
5882 * @data_buf ; user defined value to be written into Eeprom.
5883 * Description:
5884 * Tries to write the user provided value in the Eeprom, at the offset
5885 * given by the user.
5886 * Return value:
5887 * 0 on success, -EFAULT on failure.
5888 */
5889
5890static int s2io_ethtool_seeprom(struct net_device *dev,
5891 struct ethtool_eeprom *eeprom,
5892 u8 * data_buf)
5893{
5894 int len = eeprom->len, cnt = 0;
ad4ebed0 5895 u64 valid = 0, data;
4cf1653a 5896 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5897
5898 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5899 DBG_PRINT(ERR_DBG,
5900 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5901 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5902 eeprom->magic);
5903 return -EFAULT;
5904 }
5905
5906 while (len) {
5907 data = (u32) data_buf[cnt] & 0x000000FF;
5908 if (data) {
5909 valid = (u32) (data << 24);
5910 } else
5911 valid = data;
5912
5913 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5914 DBG_PRINT(ERR_DBG,
5915 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5916 DBG_PRINT(ERR_DBG,
5917 "write into the specified offset\n");
5918 return -EFAULT;
5919 }
5920 cnt++;
5921 len--;
5922 }
5923
5924 return 0;
5925}
5926
5927/**
20346722
K		 5928 * s2io_register_test - reads and writes into all clock domains.
5929 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5930 * s2io_nic structure.
5931 * @data : variable that returns the result of each of the test conducted b
5932 * by the driver.
5933 * Description:
5934 * Read and write into all clock domains. The NIC has 3 clock domains,
5935 * see that registers in all the three regions are accessible.
5936 * Return value:
5937 * 0 on success.
5938 */
5939
1ee6dd77 5940static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5941{
1ee6dd77 5942 struct XENA_dev_config __iomem *bar0 = sp->bar0;
ad4ebed0 5943 u64 val64 = 0, exp_val;
1da177e4
LT		 5944 int fail = 0;
5945
20346722
K		 5946 val64 = readq(&bar0->pif_rd_swapper_fb);
5947 if (val64 != 0x123456789abcdefULL) {
1da177e4
LT		 5948 fail = 1;
5949 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5950 }
5951
5952 val64 = readq(&bar0->rmac_pause_cfg);
5953 if (val64 != 0xc000ffff00000000ULL) {
5954 fail = 1;
5955 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5956 }
5957
5958 val64 = readq(&bar0->rx_queue_cfg);
ad4ebed0 5959 if (sp->device_type == XFRAME_II_DEVICE)
5960 exp_val = 0x0404040404040404ULL;
5961 else
5962 exp_val = 0x0808080808080808ULL;
5963 if (val64 != exp_val) {
1da177e4
LT		 5964 fail = 1;
5965 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5966 }
5967
5968 val64 = readq(&bar0->xgxs_efifo_cfg);
5969 if (val64 != 0x000000001923141EULL) {
5970 fail = 1;
5971 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5972 }
5973
5974 val64 = 0x5A5A5A5A5A5A5A5AULL;
5975 writeq(val64, &bar0->xmsi_data);
5976 val64 = readq(&bar0->xmsi_data);
5977 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5978 fail = 1;
5979 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5980 }
5981
5982 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5983 writeq(val64, &bar0->xmsi_data);
5984 val64 = readq(&bar0->xmsi_data);
5985 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5986 fail = 1;
5987 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5988 }
5989
5990 *data = fail;
ad4ebed0 5991 return fail;
1da177e4
LT		 5992}
5993
5994/**
20346722 5995 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
1da177e4
LT		 5996 * @sp : private member of the device structure, which is a pointer to the
5997 * s2io_nic structure.
5998 * @data:variable that returns the result of each of the test conducted by
5999 * the driver.
6000 * Description:
20346722 6001 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
1da177e4
LT		 6002 * register.
6003 * Return value:
6004 * 0 on success.
6005 */
6006
1ee6dd77 6007static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 6008{
6009 int fail = 0;
ad4ebed0 6010 u64 ret_data, org_4F0, org_7F0;
6011 u8 saved_4F0 = 0, saved_7F0 = 0;
6012 struct net_device *dev = sp->dev;
1da177e4
LT		 6013
6014 /* Test Write Error at offset 0 */
ad4ebed0 6015 /* Note that SPI interface allows write access to all areas
6016 * of EEPROM. Hence doing all negative testing only for Xframe I.
6017 */
6018 if (sp->device_type == XFRAME_I_DEVICE)
6019 if (!write_eeprom(sp, 0, 0, 3))
6020 fail = 1;
6021
6022 /* Save current values at offsets 0x4F0 and 0x7F0 */
6023 if (!read_eeprom(sp, 0x4F0, &org_4F0))
6024 saved_4F0 = 1;
6025 if (!read_eeprom(sp, 0x7F0, &org_7F0))
6026 saved_7F0 = 1;
1da177e4
LT		 6027
6028 /* Test Write at offset 4f0 */
ad4ebed0 6029 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
1da177e4
LT		 6030 fail = 1;
6031 if (read_eeprom(sp, 0x4F0, &ret_data))
6032 fail = 1;
6033
ad4ebed0 6034 if (ret_data != 0x012345) {
26b7625c
AM		 6035 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
6036 "Data written %llx Data read %llx\n",
6037 dev->name, (unsigned long long)0x12345,
6038 (unsigned long long)ret_data);
1da177e4 6039 fail = 1;
ad4ebed0 6040 }
1da177e4
LT		 6041
6042 /* Reset the EEPROM data go FFFF */
ad4ebed0 6043 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
1da177e4
LT		 6044
6045 /* Test Write Request Error at offset 0x7c */
ad4ebed0 6046 if (sp->device_type == XFRAME_I_DEVICE)
6047 if (!write_eeprom(sp, 0x07C, 0, 3))
6048 fail = 1;
1da177e4 6049
ad4ebed0 6050 /* Test Write Request at offset 0x7f0 */
6051 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
1da177e4 6052 fail = 1;
ad4ebed0 6053 if (read_eeprom(sp, 0x7F0, &ret_data))
1da177e4
LT		 6054 fail = 1;
6055
ad4ebed0 6056 if (ret_data != 0x012345) {
26b7625c
AM		 6057 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
6058 "Data written %llx Data read %llx\n",
6059 dev->name, (unsigned long long)0x12345,
6060 (unsigned long long)ret_data);
1da177e4 6061 fail = 1;
ad4ebed0 6062 }
1da177e4
LT		 6063
6064 /* Reset the EEPROM data go FFFF */
ad4ebed0 6065 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
1da177e4 6066
ad4ebed0 6067 if (sp->device_type == XFRAME_I_DEVICE) {
6068 /* Test Write Error at offset 0x80 */
6069 if (!write_eeprom(sp, 0x080, 0, 3))
6070 fail = 1;
1da177e4 6071
ad4ebed0 6072 /* Test Write Error at offset 0xfc */
6073 if (!write_eeprom(sp, 0x0FC, 0, 3))
6074 fail = 1;
1da177e4 6075
ad4ebed0 6076 /* Test Write Error at offset 0x100 */
6077 if (!write_eeprom(sp, 0x100, 0, 3))
6078 fail = 1;
1da177e4 6079
ad4ebed0 6080 /* Test Write Error at offset 4ec */
6081 if (!write_eeprom(sp, 0x4EC, 0, 3))
6082 fail = 1;
6083 }
6084
6085 /* Restore values at offsets 0x4F0 and 0x7F0 */
6086 if (saved_4F0)
6087 write_eeprom(sp, 0x4F0, org_4F0, 3);
6088 if (saved_7F0)
6089 write_eeprom(sp, 0x7F0, org_7F0, 3);
1da177e4
LT		 6090
6091 *data = fail;
ad4ebed0 6092 return fail;
1da177e4
LT		 6093}
6094
6095/**
6096 * s2io_bist_test - invokes the MemBist test of the card .
20346722 6097 * @sp : private member of the device structure, which is a pointer to the
1da177e4 6098 * s2io_nic structure.
20346722 6099 * @data:variable that returns the result of each of the test conducted by
1da177e4
LT		 6100 * the driver.
6101 * Description:
6102 * This invokes the MemBist test of the card. We give around
6103 * 2 secs time for the Test to complete. If it's still not complete
20346722 6104 * within this peiod, we consider that the test failed.
1da177e4
LT		 6105 * Return value:
6106 * 0 on success and -1 on failure.
6107 */
6108
1ee6dd77 6109static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 6110{
6111 u8 bist = 0;
6112 int cnt = 0, ret = -1;
6113
6114 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6115 bist |= PCI_BIST_START;
6116 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6117
6118 while (cnt < 20) {
6119 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6120 if (!(bist & PCI_BIST_START)) {
6121 *data = (bist & PCI_BIST_CODE_MASK);
6122 ret = 0;
6123 break;
6124 }
6125 msleep(100);
6126 cnt++;
6127 }
6128
6129 return ret;
6130}
6131
6132/**
20346722
K		 6133 * s2io-link_test - verifies the link state of the nic
6134 * @sp ; private member of the device structure, which is a pointer to the
1da177e4
LT		 6135 * s2io_nic structure.
6136 * @data: variable that returns the result of each of the test conducted by
6137 * the driver.
6138 * Description:
20346722 6139 * The function verifies the link state of the NIC and updates the input
1da177e4
LT		 6140 * argument 'data' appropriately.
6141 * Return value:
6142 * 0 on success.
6143 */
6144
1ee6dd77 6145static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 6146{
1ee6dd77 6147 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 6148 u64 val64;
6149
6150 val64 = readq(&bar0->adapter_status);
c92ca04b 6151 if(!(LINK_IS_UP(val64)))
1da177e4 6152 *data = 1;
c92ca04b
AR		 6153 else
6154 *data = 0;
1da177e4 6155
b41477f3 6156 return *data;
1da177e4
LT		 6157}
6158
6159/**
20346722
K		 6160 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6161 * @sp - private member of the device structure, which is a pointer to the
1da177e4 6162 * s2io_nic structure.
20346722 6163 * @data - variable that returns the result of each of the test
1da177e4
LT		 6164 * conducted by the driver.
6165 * Description:
20346722 6166 * This is one of the offline test that tests the read and write
1da177e4
LT		 6167 * access to the RldRam chip on the NIC.
6168 * Return value:
6169 * 0 on success.
6170 */
6171
1ee6dd77 6172static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 6173{
1ee6dd77 6174 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 6175 u64 val64;
ad4ebed0 6176 int cnt, iteration = 0, test_fail = 0;
1da177e4
LT		 6177
6178 val64 = readq(&bar0->adapter_control);
6179 val64 &= ~ADAPTER_ECC_EN;
6180 writeq(val64, &bar0->adapter_control);
6181
6182 val64 = readq(&bar0->mc_rldram_test_ctrl);
6183 val64 |= MC_RLDRAM_TEST_MODE;
ad4ebed0 6184 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6185
6186 val64 = readq(&bar0->mc_rldram_mrs);
6187 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6188 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6189
6190 val64 |= MC_RLDRAM_MRS_ENABLE;
6191 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6192
6193 while (iteration < 2) {
6194 val64 = 0x55555555aaaa0000ULL;
6195 if (iteration == 1) {
6196 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6197 }
6198 writeq(val64, &bar0->mc_rldram_test_d0);
6199
6200 val64 = 0xaaaa5a5555550000ULL;
6201 if (iteration == 1) {
6202 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6203 }
6204 writeq(val64, &bar0->mc_rldram_test_d1);
6205
6206 val64 = 0x55aaaaaaaa5a0000ULL;
6207 if (iteration == 1) {
6208 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6209 }
6210 writeq(val64, &bar0->mc_rldram_test_d2);
6211
ad4ebed0 6212 val64 = (u64) (0x0000003ffffe0100ULL);
1da177e4
LT		 6213 writeq(val64, &bar0->mc_rldram_test_add);
6214
ad4ebed0 6215 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
6216 MC_RLDRAM_TEST_GO;
6217 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6218
6219 for (cnt = 0; cnt < 5; cnt++) {
6220 val64 = readq(&bar0->mc_rldram_test_ctrl);
6221 if (val64 & MC_RLDRAM_TEST_DONE)
6222 break;
6223 msleep(200);
6224 }
6225
6226 if (cnt == 5)
6227 break;
6228
ad4ebed0 6229 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6230 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6231
6232 for (cnt = 0; cnt < 5; cnt++) {
6233 val64 = readq(&bar0->mc_rldram_test_ctrl);
6234 if (val64 & MC_RLDRAM_TEST_DONE)
6235 break;
6236 msleep(500);
6237 }
6238
6239 if (cnt == 5)
6240 break;
6241
6242 val64 = readq(&bar0->mc_rldram_test_ctrl);
ad4ebed0 6243 if (!(val64 & MC_RLDRAM_TEST_PASS))
6244 test_fail = 1;
1da177e4
LT		 6245
6246 iteration++;
6247 }
6248
ad4ebed0 6249 *data = test_fail;
1da177e4 6250
ad4ebed0 6251 /* Bring the adapter out of test mode */
6252 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6253
6254 return test_fail;
1da177e4
LT		 6255}
6256
6257/**
6258 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6259 * @sp : private member of the device structure, which is a pointer to the
6260 * s2io_nic structure.
6261 * @ethtest : pointer to a ethtool command specific structure that will be
6262 * returned to the user.
20346722 6263 * @data : variable that returns the result of each of the test
1da177e4
LT		 6264 * conducted by the driver.
6265 * Description:
6266 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6267 * the health of the card.
6268 * Return value:
6269 * void
6270 */
6271
6272static void s2io_ethtool_test(struct net_device *dev,
6273 struct ethtool_test *ethtest,
6274 uint64_t * data)
6275{
4cf1653a 6276 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 6277 int orig_state = netif_running(sp->dev);
6278
6279 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6280 /* Offline Tests. */
20346722 6281 if (orig_state)
1da177e4 6282 s2io_close(sp->dev);
1da177e4
LT		 6283
6284 if (s2io_register_test(sp, &data[0]))
6285 ethtest->flags |= ETH_TEST_FL_FAILED;
6286
6287 s2io_reset(sp);
1da177e4
LT		 6288
6289 if (s2io_rldram_test(sp, &data[3]))
6290 ethtest->flags |= ETH_TEST_FL_FAILED;
6291
6292 s2io_reset(sp);
1da177e4
LT		 6293
6294 if (s2io_eeprom_test(sp, &data[1]))
6295 ethtest->flags |= ETH_TEST_FL_FAILED;
6296
6297 if (s2io_bist_test(sp, &data[4]))
6298 ethtest->flags |= ETH_TEST_FL_FAILED;
6299
6300 if (orig_state)
6301 s2io_open(sp->dev);
6302
6303 data[2] = 0;
6304 } else {
6305 /* Online Tests. */
6306 if (!orig_state) {
6307 DBG_PRINT(ERR_DBG,
6308 "%s: is not up, cannot run test\n",
6309 dev->name);
6310 data[0] = -1;
6311 data[1] = -1;
6312 data[2] = -1;
6313 data[3] = -1;
6314 data[4] = -1;
6315 }
6316
6317 if (s2io_link_test(sp, &data[2]))
6318 ethtest->flags |= ETH_TEST_FL_FAILED;
6319
6320 data[0] = 0;
6321 data[1] = 0;
6322 data[3] = 0;
6323 data[4] = 0;
6324 }
6325}
6326
6327static void s2io_get_ethtool_stats(struct net_device *dev,
6328 struct ethtool_stats *estats,
6329 u64 * tmp_stats)
6330{
8116f3cf 6331 int i = 0, k;
4cf1653a 6332 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 6333 struct stat_block *stat_info = sp->mac_control.stats_info;
1da177e4 6334
7ba013ac 6335 s2io_updt_stats(sp);
541ae68f
K		 6336 tmp_stats[i++] =
6337 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
6338 le32_to_cpu(stat_info->tmac_frms);
6339 tmp_stats[i++] =
6340 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
6341 le32_to_cpu(stat_info->tmac_data_octets);
1da177e4 6342 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
541ae68f
K		 6343 tmp_stats[i++] =
6344 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
6345 le32_to_cpu(stat_info->tmac_mcst_frms);
6346 tmp_stats[i++] =
6347 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
6348 le32_to_cpu(stat_info->tmac_bcst_frms);
1da177e4 6349 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
bd1034f0
AR		 6350 tmp_stats[i++] =
6351 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
6352 le32_to_cpu(stat_info->tmac_ttl_octets);
6353 tmp_stats[i++] =
6354 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
6355 le32_to_cpu(stat_info->tmac_ucst_frms);
6356 tmp_stats[i++] =
6357 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
6358 le32_to_cpu(stat_info->tmac_nucst_frms);
541ae68f
K		 6359 tmp_stats[i++] =
6360 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
6361 le32_to_cpu(stat_info->tmac_any_err_frms);
bd1034f0 6362 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
1da177e4 6363 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
541ae68f
K		 6364 tmp_stats[i++] =
6365 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
6366 le32_to_cpu(stat_info->tmac_vld_ip);
6367 tmp_stats[i++] =
6368 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
6369 le32_to_cpu(stat_info->tmac_drop_ip);
6370 tmp_stats[i++] =
6371 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
6372 le32_to_cpu(stat_info->tmac_icmp);
6373 tmp_stats[i++] =
6374 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
6375 le32_to_cpu(stat_info->tmac_rst_tcp);
1da177e4 6376 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
541ae68f
K		 6377 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
6378 le32_to_cpu(stat_info->tmac_udp);
6379 tmp_stats[i++] =
6380 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
6381 le32_to_cpu(stat_info->rmac_vld_frms);
6382 tmp_stats[i++] =
6383 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
6384 le32_to_cpu(stat_info->rmac_data_octets);
1da177e4
LT		 6385 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
6386 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
541ae68f
K		 6387 tmp_stats[i++] =
6388 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
6389 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
6390 tmp_stats[i++] =
6391 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
6392 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
1da177e4 6393 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
bd1034f0 6394 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
1da177e4
LT		 6395 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
6396 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
bd1034f0
AR		 6397 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
6398 tmp_stats[i++] =
6399 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
6400 le32_to_cpu(stat_info->rmac_ttl_octets);
6401 tmp_stats[i++] =
6402 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
6403 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
6404 tmp_stats[i++] =
6405 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
6406 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
541ae68f
K		 6407 tmp_stats[i++] =
6408 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
6409 le32_to_cpu(stat_info->rmac_discarded_frms);
bd1034f0
AR		 6410 tmp_stats[i++] =
6411 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
6412 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
6413 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
6414 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
541ae68f
K		 6415 tmp_stats[i++] =
6416 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
6417 le32_to_cpu(stat_info->rmac_usized_frms);
6418 tmp_stats[i++] =
6419 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
6420 le32_to_cpu(stat_info->rmac_osized_frms);
6421 tmp_stats[i++] =
6422 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
6423 le32_to_cpu(stat_info->rmac_frag_frms);
6424 tmp_stats[i++] =
6425 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
6426 le32_to_cpu(stat_info->rmac_jabber_frms);
bd1034f0
AR		 6427 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
6428 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
6429 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
6430 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
6431 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
6432 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
6433 tmp_stats[i++] =
6434 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
541ae68f 6435 le32_to_cpu(stat_info->rmac_ip);
1da177e4
LT		 6436 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
6437 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
bd1034f0
AR		 6438 tmp_stats[i++] =
6439 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
541ae68f 6440 le32_to_cpu(stat_info->rmac_drop_ip);
bd1034f0
AR		 6441 tmp_stats[i++] =
6442 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
541ae68f 6443 le32_to_cpu(stat_info->rmac_icmp);
1da177e4 6444 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
bd1034f0
AR		 6445 tmp_stats[i++] =
6446 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
541ae68f
K		 6447 le32_to_cpu(stat_info->rmac_udp);
6448 tmp_stats[i++] =
6449 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
6450 le32_to_cpu(stat_info->rmac_err_drp_udp);
bd1034f0
AR		 6451 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
6452 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
6453 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
6454 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
6455 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
6456 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
6457 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
6458 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
6459 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
6460 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
6461 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
6462 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
6463 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
6464 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
6465 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
6466 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
6467 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
541ae68f
K		 6468 tmp_stats[i++] =
6469 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
6470 le32_to_cpu(stat_info->rmac_pause_cnt);
bd1034f0
AR		 6471 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
6472 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
541ae68f
K		 6473 tmp_stats[i++] =
6474 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
6475 le32_to_cpu(stat_info->rmac_accepted_ip);
1da177e4 6476 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
bd1034f0
AR		 6477 tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
6478 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
6479 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
6480 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
6481 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
6482 tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
6483 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
6484 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
6485 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
6486 tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
6487 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
6488 tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
6489 tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
6490 tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
6491 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
6492 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
6493 tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
6494 tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
fa1f0cb3
SS		 6495
6496 /* Enhanced statistics exist only for Hercules */
6497 if(sp->device_type == XFRAME_II_DEVICE) {
6498 tmp_stats[i++] =
6499 le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
6500 tmp_stats[i++] =
6501 le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
6502 tmp_stats[i++] =
6503 le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
6504 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
6505 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
6506 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
6507 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
6508 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
6509 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
6510 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
6511 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
6512 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
6513 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
6514 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
6515 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
6516 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
6517 }
6518
7ba013ac
K		 6519 tmp_stats[i++] = 0;
6520 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
6521 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
bd1034f0
AR		 6522 tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
6523 tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
6524 tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
6525 tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
8116f3cf
SS		 6526 for (k = 0; k < MAX_RX_RINGS; k++)
6527 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt[k];
bd1034f0
AR		 6528 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
6529 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
6530 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
6531 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
6532 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
6533 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
6534 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
6535 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
6536 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
6537 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
6538 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
6539 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
7d3d0439
RA		 6540 tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
6541 tmp_stats[i++] = stat_info->sw_stat.sending_both;
6542 tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
6543 tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
fe931395 6544 if (stat_info->sw_stat.num_aggregations) {
bd1034f0
AR		 6545 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
6546 int count = 0;
6aa20a22 6547 /*
bd1034f0
AR		 6548 * Since 64-bit divide does not work on all platforms,
6549 * do repeated subtraction.
6550 */
6551 while (tmp >= stat_info->sw_stat.num_aggregations) {
6552 tmp -= stat_info->sw_stat.num_aggregations;
6553 count++;
6554 }
6555 tmp_stats[i++] = count;
fe931395 6556 }
bd1034f0
AR		 6557 else
6558 tmp_stats[i++] = 0;
c53d4945 6559 tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt;
491abf25 6560 tmp_stats[i++] = stat_info->sw_stat.pci_map_fail_cnt;
c53d4945 6561 tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt;
491976b2
SH		 6562 tmp_stats[i++] = stat_info->sw_stat.mem_allocated;
6563 tmp_stats[i++] = stat_info->sw_stat.mem_freed;
6564 tmp_stats[i++] = stat_info->sw_stat.link_up_cnt;
6565 tmp_stats[i++] = stat_info->sw_stat.link_down_cnt;
6566 tmp_stats[i++] = stat_info->sw_stat.link_up_time;
6567 tmp_stats[i++] = stat_info->sw_stat.link_down_time;
6568
6569 tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt;
6570 tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt;
6571 tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt;
6572 tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt;
6573 tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt;
6574
6575 tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt;
6576 tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt;
6577 tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt;
6578 tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt;
6579 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt;
6580 tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt;
6581 tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt;
6582 tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt;
6583 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt;
8116f3cf
SS		 6584 tmp_stats[i++] = stat_info->sw_stat.tda_err_cnt;
6585 tmp_stats[i++] = stat_info->sw_stat.pfc_err_cnt;
6586 tmp_stats[i++] = stat_info->sw_stat.pcc_err_cnt;
6587 tmp_stats[i++] = stat_info->sw_stat.tti_err_cnt;
6588 tmp_stats[i++] = stat_info->sw_stat.tpa_err_cnt;
6589 tmp_stats[i++] = stat_info->sw_stat.sm_err_cnt;
6590 tmp_stats[i++] = stat_info->sw_stat.lso_err_cnt;
6591 tmp_stats[i++] = stat_info->sw_stat.mac_tmac_err_cnt;
6592 tmp_stats[i++] = stat_info->sw_stat.mac_rmac_err_cnt;
6593 tmp_stats[i++] = stat_info->sw_stat.xgxs_txgxs_err_cnt;
6594 tmp_stats[i++] = stat_info->sw_stat.xgxs_rxgxs_err_cnt;
6595 tmp_stats[i++] = stat_info->sw_stat.rc_err_cnt;
6596 tmp_stats[i++] = stat_info->sw_stat.prc_pcix_err_cnt;
6597 tmp_stats[i++] = stat_info->sw_stat.rpa_err_cnt;
6598 tmp_stats[i++] = stat_info->sw_stat.rda_err_cnt;
6599 tmp_stats[i++] = stat_info->sw_stat.rti_err_cnt;
6600 tmp_stats[i++] = stat_info->sw_stat.mc_err_cnt;
1da177e4
LT		 6601}
6602
ac1f60db 6603static int s2io_ethtool_get_regs_len(struct net_device *dev)
1da177e4
LT		 6604{
6605 return (XENA_REG_SPACE);
6606}
6607
6608
ac1f60db 6609static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
1da177e4 6610{
4cf1653a 6611 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 6612
6613 return (sp->rx_csum);
6614}
ac1f60db
AB		 6615
6616static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
1da177e4 6617{
4cf1653a 6618 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 6619
6620 if (data)
6621 sp->rx_csum = 1;
6622 else
6623 sp->rx_csum = 0;
6624
6625 return 0;
6626}
ac1f60db
AB		 6627
6628static int s2io_get_eeprom_len(struct net_device *dev)
1da177e4
LT		 6629{
6630 return (XENA_EEPROM_SPACE);
6631}
6632
b9f2c044 6633static int s2io_get_sset_count(struct net_device *dev, int sset)
1da177e4 6634{
4cf1653a 6635 struct s2io_nic *sp = netdev_priv(dev);
b9f2c044
JG		 6636
6637 switch (sset) {
6638 case ETH_SS_TEST:
6639 return S2IO_TEST_LEN;
6640 case ETH_SS_STATS:
6641 switch(sp->device_type) {
6642 case XFRAME_I_DEVICE:
6643 return XFRAME_I_STAT_LEN;
6644 case XFRAME_II_DEVICE:
6645 return XFRAME_II_STAT_LEN;
6646 default:
6647 return 0;
6648 }
6649 default:
6650 return -EOPNOTSUPP;
6651 }
1da177e4 6652}
ac1f60db
AB		 6653
6654static void s2io_ethtool_get_strings(struct net_device *dev,
6655 u32 stringset, u8 * data)
1da177e4 6656{
fa1f0cb3 6657 int stat_size = 0;
4cf1653a 6658 struct s2io_nic *sp = netdev_priv(dev);
fa1f0cb3 6659
1da177e4
LT		 6660 switch (stringset) {
6661 case ETH_SS_TEST:
6662 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6663 break;
6664 case ETH_SS_STATS:
fa1f0cb3
SS		 6665 stat_size = sizeof(ethtool_xena_stats_keys);
6666 memcpy(data, &ethtool_xena_stats_keys,stat_size);
6667 if(sp->device_type == XFRAME_II_DEVICE) {
6668 memcpy(data + stat_size,
6669 &ethtool_enhanced_stats_keys,
6670 sizeof(ethtool_enhanced_stats_keys));
6671 stat_size += sizeof(ethtool_enhanced_stats_keys);
6672 }
6673
6674 memcpy(data + stat_size, &ethtool_driver_stats_keys,
6675 sizeof(ethtool_driver_stats_keys));
1da177e4
LT		 6676 }
6677}
1da177e4 6678
ac1f60db 6679static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
1da177e4
LT		 6680{
6681 if (data)
6682 dev->features |= NETIF_F_IP_CSUM;
6683 else
6684 dev->features &= ~NETIF_F_IP_CSUM;
6685
6686 return 0;
6687}
6688
75c30b13
AR		 6689static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6690{
6691 return (dev->features & NETIF_F_TSO) != 0;
6692}
6693static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6694{
6695 if (data)
6696 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6697 else
6698 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6699
6700 return 0;
6701}
1da177e4 6702
7282d491 6703static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 6704 .get_settings = s2io_ethtool_gset,
6705 .set_settings = s2io_ethtool_sset,
6706 .get_drvinfo = s2io_ethtool_gdrvinfo,
6707 .get_regs_len = s2io_ethtool_get_regs_len,
6708 .get_regs = s2io_ethtool_gregs,
6709 .get_link = ethtool_op_get_link,
6710 .get_eeprom_len = s2io_get_eeprom_len,
6711 .get_eeprom = s2io_ethtool_geeprom,
6712 .set_eeprom = s2io_ethtool_seeprom,
0cec35eb 6713 .get_ringparam = s2io_ethtool_gringparam,
1da177e4
LT		 6714 .get_pauseparam = s2io_ethtool_getpause_data,
6715 .set_pauseparam = s2io_ethtool_setpause_data,
6716 .get_rx_csum = s2io_ethtool_get_rx_csum,
6717 .set_rx_csum = s2io_ethtool_set_rx_csum,
1da177e4 6718 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
1da177e4 6719 .set_sg = ethtool_op_set_sg,
75c30b13
AR		 6720 .get_tso = s2io_ethtool_op_get_tso,
6721 .set_tso = s2io_ethtool_op_set_tso,
fed5eccd 6722 .set_ufo = ethtool_op_set_ufo,
1da177e4
LT		 6723 .self_test = s2io_ethtool_test,
6724 .get_strings = s2io_ethtool_get_strings,
6725 .phys_id = s2io_ethtool_idnic,
b9f2c044
JG		 6726 .get_ethtool_stats = s2io_get_ethtool_stats,
6727 .get_sset_count = s2io_get_sset_count,
1da177e4
LT		 6728};
6729
6730/**
20346722 6731 * s2io_ioctl - Entry point for the Ioctl
1da177e4
LT		 6732 * @dev : Device pointer.
6733 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6734 * a proprietary structure used to pass information to the driver.
6735 * @cmd : This is used to distinguish between the different commands that
6736 * can be passed to the IOCTL functions.
6737 * Description:
20346722
K		 6738 * Currently there are no special functionality supported in IOCTL, hence
6739 * function always return EOPNOTSUPPORTED
1da177e4
LT		 6740 */
6741
ac1f60db 6742static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1da177e4
LT		 6743{
6744 return -EOPNOTSUPP;
6745}
6746
6747/**
6748 * s2io_change_mtu - entry point to change MTU size for the device.
6749 * @dev : device pointer.
6750 * @new_mtu : the new MTU size for the device.
6751 * Description: A driver entry point to change MTU size for the device.
6752 * Before changing the MTU the device must be stopped.
6753 * Return value:
6754 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6755 * file on failure.
6756 */
6757
ac1f60db 6758static int s2io_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 6759{
4cf1653a 6760 struct s2io_nic *sp = netdev_priv(dev);
9f74ffde 6761 int ret = 0;
1da177e4
LT		 6762
6763 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6764 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
6765 dev->name);
6766 return -EPERM;
6767 }
6768
1da177e4 6769 dev->mtu = new_mtu;
d8892c6e 6770 if (netif_running(dev)) {
3a3d5756 6771 s2io_stop_all_tx_queue(sp);
e6a8fee2 6772 s2io_card_down(sp);
9f74ffde
SH		 6773 ret = s2io_card_up(sp);
6774 if (ret) {
d8892c6e 6775 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
b39d66a8 6776 __func__);
9f74ffde 6777 return ret;
d8892c6e 6778 }
3a3d5756 6779 s2io_wake_all_tx_queue(sp);
d8892c6e 6780 } else { /* Device is down */
1ee6dd77 6781 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d8892c6e
K		 6782 u64 val64 = new_mtu;
6783
6784 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6785 }
1da177e4 6786
9f74ffde 6787 return ret;
1da177e4
LT		 6788}
6789
1da177e4
LT		 6790/**
6791 * s2io_set_link - Set the LInk status
6792 * @data: long pointer to device private structue
6793 * Description: Sets the link status for the adapter
6794 */
6795
c4028958 6796static void s2io_set_link(struct work_struct *work)
1da177e4 6797{
1ee6dd77 6798 struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
1da177e4 6799 struct net_device *dev = nic->dev;
1ee6dd77 6800 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 6801 register u64 val64;
6802 u16 subid;
6803
22747d6b
FR		 6804 rtnl_lock();
6805
6806 if (!netif_running(dev))
6807 goto out_unlock;
6808
92b84437 6809 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
1da177e4 6810 /* The card is being reset, no point doing anything */
22747d6b 6811 goto out_unlock;
1da177e4
LT		 6812 }
6813
6814 subid = nic->pdev->subsystem_device;
a371a07d
K		 6815 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6816 /*
6817 * Allow a small delay for the NICs self initiated
6818 * cleanup to complete.
6819 */
6820 msleep(100);
6821 }
1da177e4
LT		 6822
6823 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6824 if (LINK_IS_UP(val64)) {
6825 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6826 if (verify_xena_quiescence(nic)) {
6827 val64 = readq(&bar0->adapter_control);
6828 val64 |= ADAPTER_CNTL_EN;
1da177e4 6829 writeq(val64, &bar0->adapter_control);
19a60522
SS		 6830 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6831 nic->device_type, subid)) {
6832 val64 = readq(&bar0->gpio_control);
6833 val64 |= GPIO_CTRL_GPIO_0;
6834 writeq(val64, &bar0->gpio_control);
6835 val64 = readq(&bar0->gpio_control);
6836 } else {
6837 val64 |= ADAPTER_LED_ON;
6838 writeq(val64, &bar0->adapter_control);
a371a07d 6839 }
f957bcf0 6840 nic->device_enabled_once = true;
19a60522
SS		 6841 } else {
6842 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6843 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
3a3d5756 6844 s2io_stop_all_tx_queue(nic);
1da177e4 6845 }
19a60522 6846 }
92c48799
SS		 6847 val64 = readq(&bar0->adapter_control);
6848 val64 |= ADAPTER_LED_ON;
6849 writeq(val64, &bar0->adapter_control);
6850 s2io_link(nic, LINK_UP);
19a60522
SS		 6851 } else {
6852 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6853 subid)) {
6854 val64 = readq(&bar0->gpio_control);
6855 val64 &= ~GPIO_CTRL_GPIO_0;
6856 writeq(val64, &bar0->gpio_control);
6857 val64 = readq(&bar0->gpio_control);
1da177e4 6858 }
92c48799
SS		 6859 /* turn off LED */
6860 val64 = readq(&bar0->adapter_control);
6861 val64 = val64 &(~ADAPTER_LED_ON);
6862 writeq(val64, &bar0->adapter_control);
19a60522 6863 s2io_link(nic, LINK_DOWN);
1da177e4 6864 }
92b84437 6865 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
22747d6b
FR		 6866
6867out_unlock:
d8d70caf 6868 rtnl_unlock();
1da177e4
LT		 6869}
6870
1ee6dd77
RB		 6871static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6872 struct buffAdd *ba,
6873 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6874 u64 *temp2, int size)
5d3213cc
AR		 6875{
6876 struct net_device *dev = sp->dev;
491abf25 6877 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
5d3213cc
AR		 6878
6879 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6d517a27 6880 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
5d3213cc
AR		 6881 /* allocate skb */
6882 if (*skb) {
6883 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6884 /*
6885 * As Rx frame are not going to be processed,
6886 * using same mapped address for the Rxd
6887 * buffer pointer
6888 */
6d517a27 6889 rxdp1->Buffer0_ptr = *temp0;
5d3213cc
AR		 6890 } else {
6891 *skb = dev_alloc_skb(size);
6892 if (!(*skb)) {
0c61ed5f 6893 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
c53d4945
SH		 6894 DBG_PRINT(INFO_DBG, "memory to allocate ");
6895 DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
6896 sp->mac_control.stats_info->sw_stat. \
6897 mem_alloc_fail_cnt++;
5d3213cc
AR		 6898 return -ENOMEM ;
6899 }
8a4bdbaa 6900 sp->mac_control.stats_info->sw_stat.mem_allocated
491976b2 6901 += (*skb)->truesize;
5d3213cc
AR		 6902 /* storing the mapped addr in a temp variable
6903 * such it will be used for next rxd whose
6904 * Host Control is NULL
6905 */
6d517a27 6906 rxdp1->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6907 pci_map_single( sp->pdev, (*skb)->data,
6908 size - NET_IP_ALIGN,
6909 PCI_DMA_FROMDEVICE);
8d8bb39b 6910 if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
491abf25 6911 goto memalloc_failed;
5d3213cc
AR		 6912 rxdp->Host_Control = (unsigned long) (*skb);
6913 }
6914 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6d517a27 6915 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
5d3213cc
AR		 6916 /* Two buffer Mode */
6917 if (*skb) {
6d517a27
VP		 6918 rxdp3->Buffer2_ptr = *temp2;
6919 rxdp3->Buffer0_ptr = *temp0;
6920 rxdp3->Buffer1_ptr = *temp1;
5d3213cc
AR		 6921 } else {
6922 *skb = dev_alloc_skb(size);
2ceaac75 6923 if (!(*skb)) {
c53d4945
SH		 6924 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6925 DBG_PRINT(INFO_DBG, "memory to allocate ");
6926 DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
6927 sp->mac_control.stats_info->sw_stat. \
6928 mem_alloc_fail_cnt++;
2ceaac75
DR		 6929 return -ENOMEM;
6930 }
8a4bdbaa 6931 sp->mac_control.stats_info->sw_stat.mem_allocated
491976b2 6932 += (*skb)->truesize;
6d517a27 6933 rxdp3->Buffer2_ptr = *temp2 =
5d3213cc
AR		 6934 pci_map_single(sp->pdev, (*skb)->data,
6935 dev->mtu + 4,
6936 PCI_DMA_FROMDEVICE);
8d8bb39b 6937 if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
491abf25 6938 goto memalloc_failed;
6d517a27 6939 rxdp3->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6940 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
6941 PCI_DMA_FROMDEVICE);
8d8bb39b
FT		 6942 if (pci_dma_mapping_error(sp->pdev,
6943 rxdp3->Buffer0_ptr)) {
491abf25 6944 pci_unmap_single (sp->pdev,
3e847423 6945 (dma_addr_t)rxdp3->Buffer2_ptr,
491abf25
VP		 6946 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6947 goto memalloc_failed;
6948 }
5d3213cc
AR		 6949 rxdp->Host_Control = (unsigned long) (*skb);
6950
6951 /* Buffer-1 will be dummy buffer not used */
6d517a27 6952 rxdp3->Buffer1_ptr = *temp1 =
5d3213cc 6953 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
5d3213cc 6954 PCI_DMA_FROMDEVICE);
8d8bb39b
FT		 6955 if (pci_dma_mapping_error(sp->pdev,
6956 rxdp3->Buffer1_ptr)) {
491abf25 6957 pci_unmap_single (sp->pdev,
3e847423
AV		 6958 (dma_addr_t)rxdp3->Buffer0_ptr,
6959 BUF0_LEN, PCI_DMA_FROMDEVICE);
6960 pci_unmap_single (sp->pdev,
6961 (dma_addr_t)rxdp3->Buffer2_ptr,
491abf25
VP		 6962 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6963 goto memalloc_failed;
6964 }
5d3213cc
AR		 6965 }
6966 }
6967 return 0;
491abf25
VP		 6968 memalloc_failed:
6969 stats->pci_map_fail_cnt++;
6970 stats->mem_freed += (*skb)->truesize;
6971 dev_kfree_skb(*skb);
6972 return -ENOMEM;
5d3213cc 6973}
491abf25 6974
1ee6dd77
RB		 6975static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6976 int size)
5d3213cc
AR		 6977{
6978 struct net_device *dev = sp->dev;
6979 if (sp->rxd_mode == RXD_MODE_1) {
6980 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6981 } else if (sp->rxd_mode == RXD_MODE_3B) {
6982 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6983 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6984 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
5d3213cc
AR		 6985 }
6986}
6987
1ee6dd77 6988static int rxd_owner_bit_reset(struct s2io_nic *sp)
5d3213cc
AR		 6989{
6990 int i, j, k, blk_cnt = 0, size;
1ee6dd77 6991 struct mac_info * mac_control = &sp->mac_control;
5d3213cc
AR		 6992 struct config_param *config = &sp->config;
6993 struct net_device *dev = sp->dev;
1ee6dd77 6994 struct RxD_t *rxdp = NULL;
5d3213cc 6995 struct sk_buff *skb = NULL;
1ee6dd77 6996 struct buffAdd *ba = NULL;
5d3213cc
AR		 6997 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6998
6999 /* Calculate the size based on ring mode */
7000 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
7001 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
7002 if (sp->rxd_mode == RXD_MODE_1)
7003 size += NET_IP_ALIGN;
7004 else if (sp->rxd_mode == RXD_MODE_3B)
7005 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
5d3213cc
AR		 7006
7007 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7008 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7009 struct ring_info *ring = &mac_control->rings[i];
7010
7011 blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] +1);
5d3213cc
AR		 7012
7013 for (j = 0; j < blk_cnt; j++) {
7014 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
13d866a9 7015 rxdp = ring-> rx_blocks[j].rxds[k].virt_addr;
6d517a27 7016 if(sp->rxd_mode == RXD_MODE_3B)
13d866a9 7017 ba = &ring->ba[j][k];
ac1f90d6 7018 if (set_rxd_buffer_pointer(sp, rxdp, ba,
5d3213cc
AR		 7019 &skb,(u64 *)&temp0_64,
7020 (u64 *)&temp1_64,
ac1f90d6 7021 (u64 *)&temp2_64,
20cbe73c 7022 size) == -ENOMEM) {
ac1f90d6
SS		 7023 return 0;
7024 }
5d3213cc
AR		 7025
7026 set_rxd_buffer_size(sp, rxdp, size);
7027 wmb();
7028 /* flip the Ownership bit to Hardware */
7029 rxdp->Control_1 |= RXD_OWN_XENA;
7030 }
7031 }
7032 }
7033 return 0;
7034
7035}
7036
1ee6dd77 7037static int s2io_add_isr(struct s2io_nic * sp)
1da177e4 7038{
e6a8fee2 7039 int ret = 0;
c92ca04b 7040 struct net_device *dev = sp->dev;
e6a8fee2 7041 int err = 0;
1da177e4 7042
eaae7f72 7043 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7044 ret = s2io_enable_msi_x(sp);
7045 if (ret) {
7046 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
eaae7f72 7047 sp->config.intr_type = INTA;
20346722 7048 }
1da177e4 7049
1ee6dd77 7050 /* Store the values of the MSIX table in the struct s2io_nic structure */
e6a8fee2 7051 store_xmsi_data(sp);
c92ca04b 7052
e6a8fee2 7053 /* After proper initialization of H/W, register ISR */
eaae7f72 7054 if (sp->config.intr_type == MSI_X) {
ac731ab6
SH		 7055 int i, msix_rx_cnt = 0;
7056
f61e0a35
SH		 7057 for (i = 0; i < sp->num_entries; i++) {
7058 if (sp->s2io_entries[i].in_use == MSIX_FLG) {
7059 if (sp->s2io_entries[i].type ==
ac731ab6
SH		 7060 MSIX_RING_TYPE) {
7061 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7062 dev->name, i);
7063 err = request_irq(sp->entries[i].vector,
7064 s2io_msix_ring_handle, 0,
7065 sp->desc[i],
7066 sp->s2io_entries[i].arg);
7067 } else if (sp->s2io_entries[i].type ==
7068 MSIX_ALARM_TYPE) {
7069 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
e6a8fee2 7070 dev->name, i);
ac731ab6
SH		 7071 err = request_irq(sp->entries[i].vector,
7072 s2io_msix_fifo_handle, 0,
7073 sp->desc[i],
7074 sp->s2io_entries[i].arg);
7075
fb6a825b 7076 }
ac731ab6
SH		 7077 /* if either data or addr is zero print it. */
7078 if (!(sp->msix_info[i].addr &&
fb6a825b 7079 sp->msix_info[i].data)) {
ac731ab6
SH		 7080 DBG_PRINT(ERR_DBG,
7081 "%s @Addr:0x%llx Data:0x%llx\n",
7082 sp->desc[i],
fb6a825b
SS		 7083 (unsigned long long)
7084 sp->msix_info[i].addr,
3459feb8 7085 (unsigned long long)
ac731ab6
SH		 7086 ntohl(sp->msix_info[i].data));
7087 } else
fb6a825b 7088 msix_rx_cnt++;
ac731ab6
SH		 7089 if (err) {
7090 remove_msix_isr(sp);
7091
7092 DBG_PRINT(ERR_DBG,
7093 "%s:MSI-X-%d registration "
7094 "failed\n", dev->name, i);
7095
7096 DBG_PRINT(ERR_DBG,
7097 "%s: Defaulting to INTA\n",
7098 dev->name);
7099 sp->config.intr_type = INTA;
7100 break;
fb6a825b 7101 }
ac731ab6
SH		 7102 sp->s2io_entries[i].in_use =
7103 MSIX_REGISTERED_SUCCESS;
c92ca04b 7104 }
e6a8fee2 7105 }
18b2b7bd 7106 if (!err) {
18b2b7bd 7107 printk(KERN_INFO "MSI-X-RX %d entries enabled\n",
ac731ab6
SH		 7108 --msix_rx_cnt);
7109 DBG_PRINT(INFO_DBG, "MSI-X-TX entries enabled"
7110 " through alarm vector\n");
18b2b7bd 7111 }
e6a8fee2 7112 }
eaae7f72 7113 if (sp->config.intr_type == INTA) {
e6a8fee2
AR		 7114 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
7115 sp->name, dev);
7116 if (err) {
7117 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7118 dev->name);
7119 return -1;
7120 }
7121 }
7122 return 0;
7123}
1ee6dd77 7124static void s2io_rem_isr(struct s2io_nic * sp)
e6a8fee2 7125{
18b2b7bd
SH		 7126 if (sp->config.intr_type == MSI_X)
7127 remove_msix_isr(sp);
7128 else
7129 remove_inta_isr(sp);
e6a8fee2
AR		 7130}
7131
d796fdb7 7132static void do_s2io_card_down(struct s2io_nic * sp, int do_io)
e6a8fee2
AR		 7133{
7134 int cnt = 0;
1ee6dd77 7135 struct XENA_dev_config __iomem *bar0 = sp->bar0;
e6a8fee2 7136 register u64 val64 = 0;
5f490c96
SH		 7137 struct config_param *config;
7138 config = &sp->config;
e6a8fee2 7139
9f74ffde
SH		 7140 if (!is_s2io_card_up(sp))
7141 return;
7142
e6a8fee2
AR		 7143 del_timer_sync(&sp->alarm_timer);
7144 /* If s2io_set_link task is executing, wait till it completes. */
92b84437 7145 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state))) {
e6a8fee2
AR		 7146 msleep(50);
7147 }
92b84437 7148 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
e6a8fee2 7149
5f490c96 7150 /* Disable napi */
f61e0a35
SH		 7151 if (sp->config.napi) {
7152 int off = 0;
7153 if (config->intr_type == MSI_X) {
7154 for (; off < sp->config.rx_ring_num; off++)
7155 napi_disable(&sp->mac_control.rings[off].napi);
7156 }
7157 else
7158 napi_disable(&sp->napi);
7159 }
5f490c96 7160
e6a8fee2 7161 /* disable Tx and Rx traffic on the NIC */
d796fdb7
LV		 7162 if (do_io)
7163 stop_nic(sp);
e6a8fee2
AR		 7164
7165 s2io_rem_isr(sp);
1da177e4 7166
01e16faa
SH		 7167 /* stop the tx queue, indicate link down */
7168 s2io_link(sp, LINK_DOWN);
7169
1da177e4 7170 /* Check if the device is Quiescent and then Reset the NIC */
d796fdb7 7171 while(do_io) {
5d3213cc
AR		 7172 /* As per the HW requirement we need to replenish the
7173 * receive buffer to avoid the ring bump. Since there is
7174 * no intention of processing the Rx frame at this pointwe are
7175 * just settting the ownership bit of rxd in Each Rx
7176 * ring to HW and set the appropriate buffer size
7177 * based on the ring mode
7178 */
7179 rxd_owner_bit_reset(sp);
7180
1da177e4 7181 val64 = readq(&bar0->adapter_status);
19a60522
SS		 7182 if (verify_xena_quiescence(sp)) {
7183 if(verify_pcc_quiescent(sp, sp->device_enabled_once))
1da177e4
LT		 7184 break;
7185 }
7186
7187 msleep(50);
7188 cnt++;
7189 if (cnt == 10) {
7190 DBG_PRINT(ERR_DBG,
7191 "s2io_close:Device not Quiescent ");
7192 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
7193 (unsigned long long) val64);
7194 break;
7195 }
d796fdb7
LV		 7196 }
7197 if (do_io)
7198 s2io_reset(sp);
1da177e4 7199
7ba013ac 7200 /* Free all Tx buffers */
1da177e4 7201 free_tx_buffers(sp);
7ba013ac
K		 7202
7203 /* Free all Rx buffers */
1da177e4
LT		 7204 free_rx_buffers(sp);
7205
92b84437 7206 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
1da177e4
LT		 7207}
7208
d796fdb7
LV		 7209static void s2io_card_down(struct s2io_nic * sp)
7210{
7211 do_s2io_card_down(sp, 1);
7212}
7213
1ee6dd77 7214static int s2io_card_up(struct s2io_nic * sp)
1da177e4 7215{
cc6e7c44 7216 int i, ret = 0;
1ee6dd77 7217 struct mac_info *mac_control;
1da177e4
LT		 7218 struct config_param *config;
7219 struct net_device *dev = (struct net_device *) sp->dev;
e6a8fee2 7220 u16 interruptible;
1da177e4
LT		 7221
7222 /* Initialize the H/W I/O registers */
9f74ffde
SH		 7223 ret = init_nic(sp);
7224 if (ret != 0) {
1da177e4
LT		 7225 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7226 dev->name);
9f74ffde
SH		 7227 if (ret != -EIO)
7228 s2io_reset(sp);
7229 return ret;
1da177e4
LT		 7230 }
7231
20346722
K		 7232 /*
7233 * Initializing the Rx buffers. For now we are considering only 1
1da177e4
LT		 7234 * Rx ring and initializing buffers into 30 Rx blocks
7235 */
7236 mac_control = &sp->mac_control;
7237 config = &sp->config;
7238
7239 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7240 struct ring_info *ring = &mac_control->rings[i];
7241
7242 ring->mtu = dev->mtu;
7243 ret = fill_rx_buffers(sp, ring, 1);
0425b46a 7244 if (ret) {
1da177e4
LT		 7245 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7246 dev->name);
7247 s2io_reset(sp);
7248 free_rx_buffers(sp);
7249 return -ENOMEM;
7250 }
7251 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
13d866a9 7252 ring->rx_bufs_left);
1da177e4 7253 }
5f490c96
SH		 7254
7255 /* Initialise napi */
f61e0a35 7256 if (config->napi) {
f61e0a35
SH		 7257 if (config->intr_type == MSI_X) {
7258 for (i = 0; i < sp->config.rx_ring_num; i++)
7259 napi_enable(&sp->mac_control.rings[i].napi);
7260 } else {
7261 napi_enable(&sp->napi);
7262 }
7263 }
5f490c96 7264
19a60522
SS		 7265 /* Maintain the state prior to the open */
7266 if (sp->promisc_flg)
7267 sp->promisc_flg = 0;
7268 if (sp->m_cast_flg) {
7269 sp->m_cast_flg = 0;
7270 sp->all_multi_pos= 0;
7271 }
1da177e4
LT		 7272
7273 /* Setting its receive mode */
7274 s2io_set_multicast(dev);
7275
7d3d0439 7276 if (sp->lro) {
b41477f3 7277 /* Initialize max aggregatable pkts per session based on MTU */
7d3d0439
RA		 7278 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7279 /* Check if we can use(if specified) user provided value */
7280 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7281 sp->lro_max_aggr_per_sess = lro_max_pkts;
7282 }
7283
1da177e4
LT		 7284 /* Enable Rx Traffic and interrupts on the NIC */
7285 if (start_nic(sp)) {
7286 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
1da177e4 7287 s2io_reset(sp);
e6a8fee2
AR		 7288 free_rx_buffers(sp);
7289 return -ENODEV;
7290 }
7291
7292 /* Add interrupt service routine */
7293 if (s2io_add_isr(sp) != 0) {
eaae7f72 7294 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7295 s2io_rem_isr(sp);
7296 s2io_reset(sp);
1da177e4
LT		 7297 free_rx_buffers(sp);
7298 return -ENODEV;
7299 }
7300
25fff88e
K		 7301 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7302
01e16faa
SH		 7303 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7304
e6a8fee2 7305 /* Enable select interrupts */
9caab458 7306 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
01e16faa
SH		 7307 if (sp->config.intr_type != INTA) {
7308 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7309 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7310 } else {
e6a8fee2 7311 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 7312 interruptible |= TX_PIC_INTR;
e6a8fee2
AR		 7313 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7314 }
7315
1da177e4
LT		 7316 return 0;
7317}
7318
20346722 7319/**
1da177e4
LT		 7320 * s2io_restart_nic - Resets the NIC.
7321 * @data : long pointer to the device private structure
7322 * Description:
7323 * This function is scheduled to be run by the s2io_tx_watchdog
20346722 7324 * function after 0.5 secs to reset the NIC. The idea is to reduce
1da177e4
LT		 7325 * the run time of the watch dog routine which is run holding a
7326 * spin lock.
7327 */
7328
c4028958 7329static void s2io_restart_nic(struct work_struct *work)
1da177e4 7330{
1ee6dd77 7331 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
c4028958 7332 struct net_device *dev = sp->dev;
1da177e4 7333
22747d6b
FR		 7334 rtnl_lock();
7335
7336 if (!netif_running(dev))
7337 goto out_unlock;
7338
e6a8fee2 7339 s2io_card_down(sp);
1da177e4
LT		 7340 if (s2io_card_up(sp)) {
7341 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
7342 dev->name);
7343 }
3a3d5756 7344 s2io_wake_all_tx_queue(sp);
1da177e4
LT		 7345 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
7346 dev->name);
22747d6b
FR		 7347out_unlock:
7348 rtnl_unlock();
1da177e4
LT		 7349}
7350
20346722
K		 7351/**
7352 * s2io_tx_watchdog - Watchdog for transmit side.
1da177e4
LT		 7353 * @dev : Pointer to net device structure
7354 * Description:
7355 * This function is triggered if the Tx Queue is stopped
7356 * for a pre-defined amount of time when the Interface is still up.
7357 * If the Interface is jammed in such a situation, the hardware is
7358 * reset (by s2io_close) and restarted again (by s2io_open) to
7359 * overcome any problem that might have been caused in the hardware.
7360 * Return value:
7361 * void
7362 */
7363
7364static void s2io_tx_watchdog(struct net_device *dev)
7365{
4cf1653a 7366 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 7367
7368 if (netif_carrier_ok(dev)) {
c53d4945 7369 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++;
1da177e4 7370 schedule_work(&sp->rst_timer_task);
bd1034f0 7371 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
1da177e4
LT		 7372 }
7373}
7374
7375/**
7376 * rx_osm_handler - To perform some OS related operations on SKB.
7377 * @sp: private member of the device structure,pointer to s2io_nic structure.
7378 * @skb : the socket buffer pointer.
7379 * @len : length of the packet
7380 * @cksum : FCS checksum of the frame.
7381 * @ring_no : the ring from which this RxD was extracted.
20346722 7382 * Description:
b41477f3 7383 * This function is called by the Rx interrupt serivce routine to perform
1da177e4
LT		 7384 * some OS related operations on the SKB before passing it to the upper
7385 * layers. It mainly checks if the checksum is OK, if so adds it to the
7386 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7387 * to the upper layer. If the checksum is wrong, it increments the Rx
7388 * packet error count, frees the SKB and returns error.
7389 * Return value:
7390 * SUCCESS on success and -1 on failure.
7391 */
1ee6dd77 7392static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
1da177e4 7393{
1ee6dd77 7394 struct s2io_nic *sp = ring_data->nic;
0425b46a 7395 struct net_device *dev = (struct net_device *) ring_data->dev;
20346722
K		 7396 struct sk_buff *skb = (struct sk_buff *)
7397 ((unsigned long) rxdp->Host_Control);
7398 int ring_no = ring_data->ring_no;
1da177e4 7399 u16 l3_csum, l4_csum;
863c11a9 7400 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
2e6a684b 7401 struct lro *uninitialized_var(lro);
f9046eb3 7402 u8 err_mask;
da6971d8 7403
20346722 7404 skb->dev = dev;
c92ca04b 7405
863c11a9 7406 if (err) {
bd1034f0
AR		 7407 /* Check for parity error */
7408 if (err & 0x1) {
7409 sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
7410 }
f9046eb3
OH		 7411 err_mask = err >> 48;
7412 switch(err_mask) {
491976b2
SH		 7413 case 1:
7414 sp->mac_control.stats_info->sw_stat.
7415 rx_parity_err_cnt++;
7416 break;
7417
7418 case 2:
7419 sp->mac_control.stats_info->sw_stat.
7420 rx_abort_cnt++;
7421 break;
7422
7423 case 3:
7424 sp->mac_control.stats_info->sw_stat.
7425 rx_parity_abort_cnt++;
7426 break;
7427
7428 case 4:
7429 sp->mac_control.stats_info->sw_stat.
7430 rx_rda_fail_cnt++;
7431 break;
7432
7433 case 5:
7434 sp->mac_control.stats_info->sw_stat.
7435 rx_unkn_prot_cnt++;
7436 break;
7437
7438 case 6:
7439 sp->mac_control.stats_info->sw_stat.
7440 rx_fcs_err_cnt++;
7441 break;
bd1034f0 7442
491976b2
SH		 7443 case 7:
7444 sp->mac_control.stats_info->sw_stat.
7445 rx_buf_size_err_cnt++;
7446 break;
7447
7448 case 8:
7449 sp->mac_control.stats_info->sw_stat.
7450 rx_rxd_corrupt_cnt++;
7451 break;
7452
7453 case 15:
7454 sp->mac_control.stats_info->sw_stat.
7455 rx_unkn_err_cnt++;
7456 break;
7457 }
863c11a9
AR		 7458 /*
7459 * Drop the packet if bad transfer code. Exception being
7460 * 0x5, which could be due to unsupported IPv6 extension header.
7461 * In this case, we let stack handle the packet.
7462 * Note that in this case, since checksum will be incorrect,
7463 * stack will validate the same.
7464 */
f9046eb3
OH		 7465 if (err_mask != 0x5) {
7466 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7467 dev->name, err_mask);
dc56e634 7468 dev->stats.rx_crc_errors++;
8a4bdbaa 7469 sp->mac_control.stats_info->sw_stat.mem_freed
491976b2 7470 += skb->truesize;
863c11a9 7471 dev_kfree_skb(skb);
0425b46a 7472 ring_data->rx_bufs_left -= 1;
863c11a9
AR		 7473 rxdp->Host_Control = 0;
7474 return 0;
7475 }
20346722 7476 }
1da177e4 7477
20346722 7478 /* Updating statistics */
0425b46a 7479 ring_data->rx_packets++;
20346722 7480 rxdp->Host_Control = 0;
da6971d8
AR		 7481 if (sp->rxd_mode == RXD_MODE_1) {
7482 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
20346722 7483
0425b46a 7484 ring_data->rx_bytes += len;
da6971d8
AR		 7485 skb_put(skb, len);
7486
6d517a27 7487 } else if (sp->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 7488 int get_block = ring_data->rx_curr_get_info.block_index;
7489 int get_off = ring_data->rx_curr_get_info.offset;
7490 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7491 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7492 unsigned char *buff = skb_push(skb, buf0_len);
7493
1ee6dd77 7494 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
0425b46a 7495 ring_data->rx_bytes += buf0_len + buf2_len;
da6971d8 7496 memcpy(buff, ba->ba_0, buf0_len);
6d517a27 7497 skb_put(skb, buf2_len);
da6971d8 7498 }
20346722 7499
0425b46a
SH		 7500 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!ring_data->lro) ||
7501 (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
20346722
K		 7502 (sp->rx_csum)) {
7503 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
1da177e4
LT		 7504 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7505 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
20346722 7506 /*
1da177e4
LT		 7507 * NIC verifies if the Checksum of the received
7508 * frame is Ok or not and accordingly returns
7509 * a flag in the RxD.
7510 */
7511 skb->ip_summed = CHECKSUM_UNNECESSARY;
0425b46a 7512 if (ring_data->lro) {
7d3d0439
RA		 7513 u32 tcp_len;
7514 u8 *tcp;
7515 int ret = 0;
7516
0425b46a
SH		 7517 ret = s2io_club_tcp_session(ring_data,
7518 skb->data, &tcp, &tcp_len, &lro,
7519 rxdp, sp);
7d3d0439
RA		 7520 switch (ret) {
7521 case 3: /* Begin anew */
7522 lro->parent = skb;
7523 goto aggregate;
7524 case 1: /* Aggregate */
7525 {
7526 lro_append_pkt(sp, lro,
7527 skb, tcp_len);
7528 goto aggregate;
7529 }
7530 case 4: /* Flush session */
7531 {
7532 lro_append_pkt(sp, lro,
7533 skb, tcp_len);
cdb5bf02
SH		 7534 queue_rx_frame(lro->parent,
7535 lro->vlan_tag);
7d3d0439
RA		 7536 clear_lro_session(lro);
7537 sp->mac_control.stats_info->
7538 sw_stat.flush_max_pkts++;
7539 goto aggregate;
7540 }
7541 case 2: /* Flush both */
7542 lro->parent->data_len =
7543 lro->frags_len;
7544 sp->mac_control.stats_info->
7545 sw_stat.sending_both++;
cdb5bf02
SH		 7546 queue_rx_frame(lro->parent,
7547 lro->vlan_tag);
7d3d0439
RA		 7548 clear_lro_session(lro);
7549 goto send_up;
7550 case 0: /* sessions exceeded */
c92ca04b
AR		 7551 case -1: /* non-TCP or not
7552 * L2 aggregatable
7553 */
7d3d0439
RA		 7554 case 5: /*
7555 * First pkt in session not
7556 * L3/L4 aggregatable
7557 */
7558 break;
7559 default:
7560 DBG_PRINT(ERR_DBG,
7561 "%s: Samadhana!!\n",
b39d66a8 7562 __func__);
7d3d0439
RA		 7563 BUG();
7564 }
7565 }
1da177e4 7566 } else {
20346722
K		 7567 /*
7568 * Packet with erroneous checksum, let the
1da177e4
LT		 7569 * upper layers deal with it.
7570 */
7571 skb->ip_summed = CHECKSUM_NONE;
7572 }
cdb5bf02 7573 } else
1da177e4 7574 skb->ip_summed = CHECKSUM_NONE;
cdb5bf02 7575
491976b2 7576 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
7d3d0439 7577send_up:
0c8dfc83 7578 skb_record_rx_queue(skb, ring_no);
cdb5bf02 7579 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7d3d0439 7580aggregate:
0425b46a 7581 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
1da177e4
LT		 7582 return SUCCESS;
7583}
7584
7585/**
7586 * s2io_link - stops/starts the Tx queue.
7587 * @sp : private member of the device structure, which is a pointer to the
7588 * s2io_nic structure.
7589 * @link : inidicates whether link is UP/DOWN.
7590 * Description:
7591 * This function stops/starts the Tx queue depending on whether the link
20346722
K		 7592 * status of the NIC is is down or up. This is called by the Alarm
7593 * interrupt handler whenever a link change interrupt comes up.
1da177e4
LT		 7594 * Return value:
7595 * void.
7596 */
7597
1ee6dd77 7598static void s2io_link(struct s2io_nic * sp, int link)
1da177e4
LT		 7599{
7600 struct net_device *dev = (struct net_device *) sp->dev;
7601
7602 if (link != sp->last_link_state) {
b7c5678f 7603 init_tti(sp, link);
1da177e4
LT		 7604 if (link == LINK_DOWN) {
7605 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
3a3d5756 7606 s2io_stop_all_tx_queue(sp);
1da177e4 7607 netif_carrier_off(dev);
491976b2 7608 if(sp->mac_control.stats_info->sw_stat.link_up_cnt)
8a4bdbaa 7609 sp->mac_control.stats_info->sw_stat.link_up_time =
491976b2
SH		 7610 jiffies - sp->start_time;
7611 sp->mac_control.stats_info->sw_stat.link_down_cnt++;
1da177e4
LT		 7612 } else {
7613 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
491976b2 7614 if (sp->mac_control.stats_info->sw_stat.link_down_cnt)
8a4bdbaa 7615 sp->mac_control.stats_info->sw_stat.link_down_time =
491976b2
SH		 7616 jiffies - sp->start_time;
7617 sp->mac_control.stats_info->sw_stat.link_up_cnt++;
1da177e4 7618 netif_carrier_on(dev);
3a3d5756 7619 s2io_wake_all_tx_queue(sp);
1da177e4
LT		 7620 }
7621 }
7622 sp->last_link_state = link;
491976b2 7623 sp->start_time = jiffies;
1da177e4
LT		 7624}
7625
20346722
K		 7626/**
7627 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7628 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 7629 * s2io_nic structure.
7630 * Description:
7631 * This function initializes a few of the PCI and PCI-X configuration registers
7632 * with recommended values.
7633 * Return value:
7634 * void
7635 */
7636
1ee6dd77 7637static void s2io_init_pci(struct s2io_nic * sp)
1da177e4 7638{
20346722 7639 u16 pci_cmd = 0, pcix_cmd = 0;
1da177e4
LT		 7640
7641 /* Enable Data Parity Error Recovery in PCI-X command register. */
7642 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7643 &(pcix_cmd));
1da177e4 7644 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7645 (pcix_cmd | 1));
1da177e4 7646 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7647 &(pcix_cmd));
1da177e4
LT		 7648
7649 /* Set the PErr Response bit in PCI command register. */
7650 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7651 pci_write_config_word(sp->pdev, PCI_COMMAND,
7652 (pci_cmd | PCI_COMMAND_PARITY));
7653 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
1da177e4
LT		 7654}
7655
3a3d5756
SH		 7656static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7657 u8 *dev_multiq)
9dc737a7 7658{
2fda096d 7659 if ((tx_fifo_num > MAX_TX_FIFOS) ||
6cfc482b 7660 (tx_fifo_num < 1)) {
2fda096d
SR		 7661 DBG_PRINT(ERR_DBG, "s2io: Requested number of tx fifos "
7662 "(%d) not supported\n", tx_fifo_num);
6cfc482b
SH		 7663
7664 if (tx_fifo_num < 1)
7665 tx_fifo_num = 1;
7666 else
7667 tx_fifo_num = MAX_TX_FIFOS;
7668
2fda096d
SR		 7669 DBG_PRINT(ERR_DBG, "s2io: Default to %d ", tx_fifo_num);
7670 DBG_PRINT(ERR_DBG, "tx fifos\n");
9dc737a7 7671 }
2fda096d 7672
6cfc482b 7673 if (multiq)
3a3d5756 7674 *dev_multiq = multiq;
6cfc482b
SH		 7675
7676 if (tx_steering_type && (1 == tx_fifo_num)) {
7677 if (tx_steering_type != TX_DEFAULT_STEERING)
7678 DBG_PRINT(ERR_DBG,
7679 "s2io: Tx steering is not supported with "
7680 "one fifo. Disabling Tx steering.\n");
7681 tx_steering_type = NO_STEERING;
7682 }
7683
7684 if ((tx_steering_type < NO_STEERING) ||
7685 (tx_steering_type > TX_DEFAULT_STEERING)) {
7686 DBG_PRINT(ERR_DBG, "s2io: Requested transmit steering not "
7687 "supported\n");
7688 DBG_PRINT(ERR_DBG, "s2io: Disabling transmit steering\n");
7689 tx_steering_type = NO_STEERING;
3a3d5756
SH		 7690 }
7691
0425b46a
SH		 7692 if (rx_ring_num > MAX_RX_RINGS) {
7693 DBG_PRINT(ERR_DBG, "s2io: Requested number of rx rings not "
9dc737a7 7694 "supported\n");
0425b46a
SH		 7695 DBG_PRINT(ERR_DBG, "s2io: Default to %d rx rings\n",
7696 MAX_RX_RINGS);
7697 rx_ring_num = MAX_RX_RINGS;
9dc737a7 7698 }
0425b46a 7699
eccb8628 7700 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
9dc737a7
AR		 7701 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
7702 "Defaulting to INTA\n");
7703 *dev_intr_type = INTA;
7704 }
596c5c97 7705
9dc737a7
AR		 7706 if ((*dev_intr_type == MSI_X) &&
7707 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7708 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
6aa20a22 7709 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
9dc737a7
AR		 7710 "Defaulting to INTA\n");
7711 *dev_intr_type = INTA;
7712 }
fb6a825b 7713
6d517a27 7714 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
9dc737a7 7715 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
6d517a27
VP		 7716 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 1-buffer mode\n");
7717 rx_ring_mode = 1;
9dc737a7
AR		 7718 }
7719 return SUCCESS;
7720}
7721
9fc93a41
SS		 7722/**
7723 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7724 * or Traffic class respectively.
b7c5678f 7725 * @nic: device private variable
9fc93a41
SS		 7726 * Description: The function configures the receive steering to
7727 * desired receive ring.
7728 * Return Value: SUCCESS on success and
7729 * '-1' on failure (endian settings incorrect).
7730 */
7731static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7732{
7733 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7734 register u64 val64 = 0;
7735
7736 if (ds_codepoint > 63)
7737 return FAILURE;
7738
7739 val64 = RTS_DS_MEM_DATA(ring);
7740 writeq(val64, &bar0->rts_ds_mem_data);
7741
7742 val64 = RTS_DS_MEM_CTRL_WE |
7743 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7744 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7745
7746 writeq(val64, &bar0->rts_ds_mem_ctrl);
7747
7748 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7749 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7750 S2IO_BIT_RESET);
7751}
7752
04025095
SH		 7753static const struct net_device_ops s2io_netdev_ops = {
7754 .ndo_open = s2io_open,
7755 .ndo_stop = s2io_close,
7756 .ndo_get_stats = s2io_get_stats,
7757 .ndo_start_xmit = s2io_xmit,
7758 .ndo_validate_addr = eth_validate_addr,
7759 .ndo_set_multicast_list = s2io_set_multicast,
7760 .ndo_do_ioctl = s2io_ioctl,
7761 .ndo_set_mac_address = s2io_set_mac_addr,
7762 .ndo_change_mtu = s2io_change_mtu,
7763 .ndo_vlan_rx_register = s2io_vlan_rx_register,
7764 .ndo_vlan_rx_kill_vid = s2io_vlan_rx_kill_vid,
7765 .ndo_tx_timeout = s2io_tx_watchdog,
7766#ifdef CONFIG_NET_POLL_CONTROLLER
7767 .ndo_poll_controller = s2io_netpoll,
7768#endif
7769};
7770
1da177e4 7771/**
20346722 7772 * s2io_init_nic - Initialization of the adapter .
1da177e4
LT		 7773 * @pdev : structure containing the PCI related information of the device.
7774 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7775 * Description:
7776 * The function initializes an adapter identified by the pci_dec structure.
20346722
K		 7777 * All OS related initialization including memory and device structure and
7778 * initlaization of the device private variable is done. Also the swapper
7779 * control register is initialized to enable read and write into the I/O
1da177e4
LT		 7780 * registers of the device.
7781 * Return value:
7782 * returns 0 on success and negative on failure.
7783 */
7784
7785static int __devinit
7786s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7787{
1ee6dd77 7788 struct s2io_nic *sp;
1da177e4 7789 struct net_device *dev;
1da177e4 7790 int i, j, ret;
f957bcf0 7791 int dma_flag = false;
1da177e4
LT		 7792 u32 mac_up, mac_down;
7793 u64 val64 = 0, tmp64 = 0;
1ee6dd77 7794 struct XENA_dev_config __iomem *bar0 = NULL;
1da177e4 7795 u16 subid;
1ee6dd77 7796 struct mac_info *mac_control;
1da177e4 7797 struct config_param *config;
541ae68f 7798 int mode;
cc6e7c44 7799 u8 dev_intr_type = intr_type;
3a3d5756 7800 u8 dev_multiq = 0;
1da177e4 7801
3a3d5756
SH		 7802 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7803 if (ret)
9dc737a7 7804 return ret;
1da177e4
LT		 7805
7806 if ((ret = pci_enable_device(pdev))) {
7807 DBG_PRINT(ERR_DBG,
7808 "s2io_init_nic: pci_enable_device failed\n");
7809 return ret;
7810 }
7811
6a35528a 7812 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4 7813 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
f957bcf0 7814 dma_flag = true;
1da177e4 7815 if (pci_set_consistent_dma_mask
6a35528a 7816 (pdev, DMA_BIT_MASK(64))) {
1da177e4
LT		 7817 DBG_PRINT(ERR_DBG,
7818 "Unable to obtain 64bit DMA for \
7819 consistent allocations\n");
7820 pci_disable_device(pdev);
7821 return -ENOMEM;
7822 }
284901a9 7823 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1da177e4
LT		 7824 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
7825 } else {
7826 pci_disable_device(pdev);
7827 return -ENOMEM;
7828 }
eccb8628 7829 if ((ret = pci_request_regions(pdev, s2io_driver_name))) {
b39d66a8 7830 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x \n", __func__, ret);
eccb8628
VP		 7831 pci_disable_device(pdev);
7832 return -ENODEV;
1da177e4 7833 }
3a3d5756 7834 if (dev_multiq)
6cfc482b 7835 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
3a3d5756 7836 else
b19fa1fa 7837 dev = alloc_etherdev(sizeof(struct s2io_nic));
1da177e4
LT		 7838 if (dev == NULL) {
7839 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7840 pci_disable_device(pdev);
7841 pci_release_regions(pdev);
7842 return -ENODEV;
7843 }
7844
7845 pci_set_master(pdev);
7846 pci_set_drvdata(pdev, dev);
1da177e4
LT		 7847 SET_NETDEV_DEV(dev, &pdev->dev);
7848
7849 /* Private member variable initialized to s2io NIC structure */
4cf1653a 7850 sp = netdev_priv(dev);
1ee6dd77 7851 memset(sp, 0, sizeof(struct s2io_nic));
1da177e4
LT		 7852 sp->dev = dev;
7853 sp->pdev = pdev;
1da177e4 7854 sp->high_dma_flag = dma_flag;
f957bcf0 7855 sp->device_enabled_once = false;
da6971d8
AR		 7856 if (rx_ring_mode == 1)
7857 sp->rxd_mode = RXD_MODE_1;
7858 if (rx_ring_mode == 2)
7859 sp->rxd_mode = RXD_MODE_3B;
da6971d8 7860
eaae7f72 7861 sp->config.intr_type = dev_intr_type;
1da177e4 7862
541ae68f
K		 7863 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7864 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7865 sp->device_type = XFRAME_II_DEVICE;
7866 else
7867 sp->device_type = XFRAME_I_DEVICE;
7868
43b7c451 7869 sp->lro = lro_enable;
6aa20a22 7870
1da177e4
LT		 7871 /* Initialize some PCI/PCI-X fields of the NIC. */
7872 s2io_init_pci(sp);
7873
20346722 7874 /*
1da177e4 7875 * Setting the device configuration parameters.
20346722
K		 7876 * Most of these parameters can be specified by the user during
7877 * module insertion as they are module loadable parameters. If
7878 * these parameters are not not specified during load time, they
1da177e4
LT		 7879 * are initialized with default values.
7880 */
7881 mac_control = &sp->mac_control;
7882 config = &sp->config;
7883
596c5c97 7884 config->napi = napi;
6cfc482b 7885 config->tx_steering_type = tx_steering_type;
596c5c97 7886
1da177e4 7887 /* Tx side parameters. */
6cfc482b
SH		 7888 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7889 config->tx_fifo_num = MAX_TX_FIFOS;
7890 else
7891 config->tx_fifo_num = tx_fifo_num;
7892
7893 /* Initialize the fifos used for tx steering */
7894 if (config->tx_fifo_num < 5) {
7895 if (config->tx_fifo_num == 1)
7896 sp->total_tcp_fifos = 1;
7897 else
7898 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7899 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7900 sp->total_udp_fifos = 1;
7901 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
7902 } else {
7903 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
7904 FIFO_OTHER_MAX_NUM);
7905 sp->udp_fifo_idx = sp->total_tcp_fifos;
7906 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7907 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7908 }
7909
3a3d5756 7910 config->multiq = dev_multiq;
6cfc482b 7911 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 7912 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7913
7914 tx_cfg->fifo_len = tx_fifo_len[i];
7915 tx_cfg->fifo_priority = i;
1da177e4
LT		 7916 }
7917
20346722
K		 7918 /* mapping the QoS priority to the configured fifos */
7919 for (i = 0; i < MAX_TX_FIFOS; i++)
3a3d5756 7920 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
20346722 7921
6cfc482b
SH		 7922 /* map the hashing selector table to the configured fifos */
7923 for (i = 0; i < config->tx_fifo_num; i++)
7924 sp->fifo_selector[i] = fifo_selector[i];
7925
7926
1da177e4
LT		 7927 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7928 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 7929 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7930
7931 tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7932 if (tx_cfg->fifo_len < 65) {
1da177e4
LT		 7933 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7934 break;
7935 }
7936 }
fed5eccd
AR		 7937 /* + 2 because one Txd for skb->data and one Txd for UFO */
7938 config->max_txds = MAX_SKB_FRAGS + 2;
1da177e4
LT		 7939
7940 /* Rx side parameters. */
1da177e4 7941 config->rx_ring_num = rx_ring_num;
0425b46a 7942 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7943 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7944 struct ring_info *ring = &mac_control->rings[i];
7945
7946 rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
7947 rx_cfg->ring_priority = i;
7948 ring->rx_bufs_left = 0;
7949 ring->rxd_mode = sp->rxd_mode;
7950 ring->rxd_count = rxd_count[sp->rxd_mode];
7951 ring->pdev = sp->pdev;
7952 ring->dev = sp->dev;
1da177e4
LT		 7953 }
7954
7955 for (i = 0; i < rx_ring_num; i++) {
13d866a9
JP		 7956 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7957
7958 rx_cfg->ring_org = RING_ORG_BUFF1;
7959 rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
1da177e4
LT		 7960 }
7961
7962 /* Setting Mac Control parameters */
7963 mac_control->rmac_pause_time = rmac_pause_time;
7964 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7965 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7966
7967
1da177e4
LT		 7968 /* initialize the shared memory used by the NIC and the host */
7969 if (init_shared_mem(sp)) {
7970 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
b41477f3 7971 dev->name);
1da177e4
LT		 7972 ret = -ENOMEM;
7973 goto mem_alloc_failed;
7974 }
7975
275f165f 7976 sp->bar0 = pci_ioremap_bar(pdev, 0);
1da177e4 7977 if (!sp->bar0) {
19a60522 7978 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
1da177e4
LT		 7979 dev->name);
7980 ret = -ENOMEM;
7981 goto bar0_remap_failed;
7982 }
7983
275f165f 7984 sp->bar1 = pci_ioremap_bar(pdev, 2);
1da177e4 7985 if (!sp->bar1) {
19a60522 7986 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
1da177e4
LT		 7987 dev->name);
7988 ret = -ENOMEM;
7989 goto bar1_remap_failed;
7990 }
7991
7992 dev->irq = pdev->irq;
7993 dev->base_addr = (unsigned long) sp->bar0;
7994
7995 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7996 for (j = 0; j < MAX_TX_FIFOS; j++) {
1ee6dd77 7997 mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
1da177e4
LT		 7998 (sp->bar1 + (j * 0x00020000));
7999 }
8000
8001 /* Driver entry points */
04025095 8002 dev->netdev_ops = &s2io_netdev_ops;
1da177e4 8003 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
be3a6b02 8004 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
612eff0e 8005
1da177e4 8006 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
f957bcf0 8007 if (sp->high_dma_flag == true)
1da177e4 8008 dev->features |= NETIF_F_HIGHDMA;
1da177e4 8009 dev->features |= NETIF_F_TSO;
f83ef8c0 8010 dev->features |= NETIF_F_TSO6;
db874e65 8011 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
fed5eccd
AR		 8012 dev->features |= NETIF_F_UFO;
8013 dev->features |= NETIF_F_HW_CSUM;
8014 }
1da177e4 8015 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
c4028958
DH		 8016 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
8017 INIT_WORK(&sp->set_link_task, s2io_set_link);
1da177e4 8018
e960fc5c 8019 pci_save_state(sp->pdev);
1da177e4
LT		 8020
8021 /* Setting swapper control on the NIC, for proper reset operation */
8022 if (s2io_set_swapper(sp)) {
8023 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
8024 dev->name);
8025 ret = -EAGAIN;
8026 goto set_swap_failed;
8027 }
8028
541ae68f
K		 8029 /* Verify if the Herc works on the slot its placed into */
8030 if (sp->device_type & XFRAME_II_DEVICE) {
8031 mode = s2io_verify_pci_mode(sp);
8032 if (mode < 0) {
b39d66a8 8033 DBG_PRINT(ERR_DBG, "%s: ", __func__);
541ae68f
K		 8034 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
8035 ret = -EBADSLT;
8036 goto set_swap_failed;
8037 }
8038 }
8039
f61e0a35
SH		 8040 if (sp->config.intr_type == MSI_X) {
8041 sp->num_entries = config->rx_ring_num + 1;
8042 ret = s2io_enable_msi_x(sp);
8043
8044 if (!ret) {
8045 ret = s2io_test_msi(sp);
8046 /* rollback MSI-X, will re-enable during add_isr() */
8047 remove_msix_isr(sp);
8048 }
8049 if (ret) {
8050
8051 DBG_PRINT(ERR_DBG,
073a2436 8052 "s2io: MSI-X requested but failed to enable\n");
f61e0a35
SH		 8053 sp->config.intr_type = INTA;
8054 }
8055 }
8056
8057 if (config->intr_type == MSI_X) {
13d866a9
JP		 8058 for (i = 0; i < config->rx_ring_num ; i++) {
8059 struct ring_info *ring = &mac_control->rings[i];
8060
8061 netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64);
8062 }
f61e0a35
SH		 8063 } else {
8064 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
8065 }
8066
541ae68f
K		 8067 /* Not needed for Herc */
8068 if (sp->device_type & XFRAME_I_DEVICE) {
8069 /*
8070 * Fix for all "FFs" MAC address problems observed on
8071 * Alpha platforms
8072 */
8073 fix_mac_address(sp);
8074 s2io_reset(sp);
8075 }
1da177e4
LT		 8076
8077 /*
1da177e4
LT		 8078 * MAC address initialization.
8079 * For now only one mac address will be read and used.
8080 */
8081 bar0 = sp->bar0;
8082 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
faa4f796 8083 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
1da177e4 8084 writeq(val64, &bar0->rmac_addr_cmd_mem);
c92ca04b 8085 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41 8086 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET);
1da177e4
LT		 8087 tmp64 = readq(&bar0->rmac_addr_data0_mem);
8088 mac_down = (u32) tmp64;
8089 mac_up = (u32) (tmp64 >> 32);
8090
1da177e4
LT		 8091 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8092 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8093 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8094 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8095 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8096 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8097
1da177e4
LT		 8098 /* Set the factory defined MAC address initially */
8099 dev->addr_len = ETH_ALEN;
8100 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
2fd37688 8101 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
1da177e4 8102
faa4f796
SH		 8103 /* initialize number of multicast & unicast MAC entries variables */
8104 if (sp->device_type == XFRAME_I_DEVICE) {
8105 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8106 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8107 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8108 } else if (sp->device_type == XFRAME_II_DEVICE) {
8109 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8110 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8111 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8112 }
8113
8114 /* store mac addresses from CAM to s2io_nic structure */
8115 do_s2io_store_unicast_mc(sp);
8116
f61e0a35
SH		 8117 /* Configure MSIX vector for number of rings configured plus one */
8118 if ((sp->device_type == XFRAME_II_DEVICE) &&
8119 (config->intr_type == MSI_X))
8120 sp->num_entries = config->rx_ring_num + 1;
8121
c77dd43e
SS		 8122 /* Store the values of the MSIX table in the s2io_nic structure */
8123 store_xmsi_data(sp);
b41477f3
AR		 8124 /* reset Nic and bring it to known state */
8125 s2io_reset(sp);
8126
1da177e4 8127 /*
99993af6 8128 * Initialize link state flags
541ae68f 8129 * and the card state parameter
1da177e4 8130 */
92b84437 8131 sp->state = 0;
1da177e4 8132
1da177e4 8133 /* Initialize spinlocks */
13d866a9
JP		 8134 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8135 struct fifo_info *fifo = &mac_control->fifos[i];
8136
8137 spin_lock_init(&fifo->tx_lock);
8138 }
db874e65 8139
20346722
K		 8140 /*
8141 * SXE-002: Configure link and activity LED to init state
8142 * on driver load.
1da177e4
LT		 8143 */
8144 subid = sp->pdev->subsystem_device;
8145 if ((subid & 0xFF) >= 0x07) {
8146 val64 = readq(&bar0->gpio_control);
8147 val64 |= 0x0000800000000000ULL;
8148 writeq(val64, &bar0->gpio_control);
8149 val64 = 0x0411040400000000ULL;
8150 writeq(val64, (void __iomem *) bar0 + 0x2700);
8151 val64 = readq(&bar0->gpio_control);
8152 }
8153
8154 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8155
8156 if (register_netdev(dev)) {
8157 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8158 ret = -ENODEV;
8159 goto register_failed;
8160 }
9dc737a7 8161 s2io_vpd_read(sp);
0c61ed5f 8162 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
b41477f3 8163 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
44c10138 8164 sp->product_name, pdev->revision);
b41477f3
AR		 8165 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8166 s2io_driver_version);
e174961c 8167 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: %pM\n", dev->name, dev->dev_addr);
19a60522 8168 DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
9dc737a7 8169 if (sp->device_type & XFRAME_II_DEVICE) {
0b1f7ebe 8170 mode = s2io_print_pci_mode(sp);
541ae68f 8171 if (mode < 0) {
9dc737a7 8172 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
541ae68f 8173 ret = -EBADSLT;
9dc737a7 8174 unregister_netdev(dev);
541ae68f
K		 8175 goto set_swap_failed;
8176 }
541ae68f 8177 }
9dc737a7
AR		 8178 switch(sp->rxd_mode) {
8179 case RXD_MODE_1:
8180 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8181 dev->name);
8182 break;
8183 case RXD_MODE_3B:
8184 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8185 dev->name);
8186 break;
9dc737a7 8187 }
db874e65 8188
f61e0a35
SH		 8189 switch (sp->config.napi) {
8190 case 0:
8191 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8192 break;
8193 case 1:
db874e65 8194 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
f61e0a35
SH		 8195 break;
8196 }
3a3d5756
SH		 8197
8198 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
8199 sp->config.tx_fifo_num);
8200
0425b46a
SH		 8201 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8202 sp->config.rx_ring_num);
8203
eaae7f72 8204 switch(sp->config.intr_type) {
9dc737a7
AR		 8205 case INTA:
8206 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8207 break;
9dc737a7
AR		 8208 case MSI_X:
8209 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8210 break;
8211 }
3a3d5756 8212 if (sp->config.multiq) {
13d866a9
JP		 8213 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8214 struct fifo_info *fifo = &mac_control->fifos[i];
8215
8216 fifo->multiq = config->multiq;
8217 }
3a3d5756
SH		 8218 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
8219 dev->name);
8220 } else
8221 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
8222 dev->name);
8223
6cfc482b
SH		 8224 switch (sp->config.tx_steering_type) {
8225 case NO_STEERING:
8226 DBG_PRINT(ERR_DBG, "%s: No steering enabled for"
8227 " transmit\n", dev->name);
8228 break;
8229 case TX_PRIORITY_STEERING:
8230 DBG_PRINT(ERR_DBG, "%s: Priority steering enabled for"
8231 " transmit\n", dev->name);
8232 break;
8233 case TX_DEFAULT_STEERING:
8234 DBG_PRINT(ERR_DBG, "%s: Default steering enabled for"
8235 " transmit\n", dev->name);
8236 }
8237
7d3d0439
RA		 8238 if (sp->lro)
8239 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
9dc737a7 8240 dev->name);
db874e65
SS		 8241 if (ufo)
8242 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
8243 " enabled\n", dev->name);
7ba013ac 8244 /* Initialize device name */
9dc737a7 8245 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7ba013ac 8246
cd0fce03
BL		 8247 if (vlan_tag_strip)
8248 sp->vlan_strip_flag = 1;
8249 else
8250 sp->vlan_strip_flag = 0;
8251
20346722
K		 8252 /*
8253 * Make Link state as off at this point, when the Link change
8254 * interrupt comes the state will be automatically changed to
1da177e4
LT		 8255 * the right state.
8256 */
8257 netif_carrier_off(dev);
1da177e4
LT		 8258
8259 return 0;
8260
8261 register_failed:
8262 set_swap_failed:
8263 iounmap(sp->bar1);
8264 bar1_remap_failed:
8265 iounmap(sp->bar0);
8266 bar0_remap_failed:
8267 mem_alloc_failed:
8268 free_shared_mem(sp);
8269 pci_disable_device(pdev);
eccb8628 8270 pci_release_regions(pdev);
1da177e4
LT		 8271 pci_set_drvdata(pdev, NULL);
8272 free_netdev(dev);
8273
8274 return ret;
8275}
8276
8277/**
20346722 8278 * s2io_rem_nic - Free the PCI device
1da177e4 8279 * @pdev: structure containing the PCI related information of the device.
20346722 8280 * Description: This function is called by the Pci subsystem to release a
1da177e4 8281 * PCI device and free up all resource held up by the device. This could
20346722 8282 * be in response to a Hot plug event or when the driver is to be removed
1da177e4
LT		 8283 * from memory.
8284 */
8285
8286static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8287{
8288 struct net_device *dev =
8289 (struct net_device *) pci_get_drvdata(pdev);
1ee6dd77 8290 struct s2io_nic *sp;
1da177e4
LT		 8291
8292 if (dev == NULL) {
8293 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8294 return;
8295 }
8296
22747d6b
FR		 8297 flush_scheduled_work();
8298
4cf1653a 8299 sp = netdev_priv(dev);
1da177e4
LT		 8300 unregister_netdev(dev);
8301
8302 free_shared_mem(sp);
8303 iounmap(sp->bar0);
8304 iounmap(sp->bar1);
eccb8628 8305 pci_release_regions(pdev);
1da177e4 8306 pci_set_drvdata(pdev, NULL);
1da177e4 8307 free_netdev(dev);
19a60522 8308 pci_disable_device(pdev);
1da177e4
LT		 8309}
8310
8311/**
8312 * s2io_starter - Entry point for the driver
8313 * Description: This function is the entry point for the driver. It verifies
8314 * the module loadable parameters and initializes PCI configuration space.
8315 */
8316
43b7c451 8317static int __init s2io_starter(void)
1da177e4 8318{
29917620 8319 return pci_register_driver(&s2io_driver);
1da177e4
LT		 8320}
8321
8322/**
20346722 8323 * s2io_closer - Cleanup routine for the driver
1da177e4
LT		 8324 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8325 */
8326
372cc597 8327static __exit void s2io_closer(void)
1da177e4
LT		 8328{
8329 pci_unregister_driver(&s2io_driver);
8330 DBG_PRINT(INIT_DBG, "cleanup done\n");
8331}
8332
8333module_init(s2io_starter);
8334module_exit(s2io_closer);
7d3d0439 8335
6aa20a22 8336static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
cdb5bf02
SH		 8337 struct tcphdr **tcp, struct RxD_t *rxdp,
8338 struct s2io_nic *sp)
7d3d0439
RA		 8339{
8340 int ip_off;
8341 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8342
8343 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8344 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
b39d66a8 8345 __func__);
7d3d0439
RA		 8346 return -1;
8347 }
8348
cdb5bf02
SH		 8349 /* Checking for DIX type or DIX type with VLAN */
8350 if ((l2_type == 0)
8351 || (l2_type == 4)) {
8352 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8353 /*
8354 * If vlan stripping is disabled and the frame is VLAN tagged,
8355 * shift the offset by the VLAN header size bytes.
8356 */
cd0fce03 8357 if ((!sp->vlan_strip_flag) &&
cdb5bf02
SH		 8358 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
8359 ip_off += HEADER_VLAN_SIZE;
8360 } else {
7d3d0439 8361 /* LLC, SNAP etc are considered non-mergeable */
cdb5bf02 8362 return -1;
7d3d0439
RA		 8363 }
8364
8365 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8366 ip_len = (u8)((*ip)->ihl);
8367 ip_len <<= 2;
8368 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8369
8370 return 0;
8371}
8372
1ee6dd77 8373static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 8374 struct tcphdr *tcp)
8375{
b39d66a8 8376 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __func__);
7d3d0439
RA		 8377 if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
8378 (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
8379 return -1;
8380 return 0;
8381}
8382
8383static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8384{
8385 return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
8386}
8387
1ee6dd77 8388static void initiate_new_session(struct lro *lro, u8 *l2h,
cdb5bf02 8389 struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len, u16 vlan_tag)
7d3d0439 8390{
b39d66a8 8391 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __func__);
7d3d0439
RA		 8392 lro->l2h = l2h;
8393 lro->iph = ip;
8394 lro->tcph = tcp;
8395 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
c8855953 8396 lro->tcp_ack = tcp->ack_seq;
7d3d0439
RA		 8397 lro->sg_num = 1;
8398 lro->total_len = ntohs(ip->tot_len);
8399 lro->frags_len = 0;
cdb5bf02 8400 lro->vlan_tag = vlan_tag;
6aa20a22 8401 /*
7d3d0439
RA		 8402 * check if we saw TCP timestamp. Other consistency checks have
8403 * already been done.
8404 */
8405 if (tcp->doff == 8) {
c8855953
SR		 8406 __be32 *ptr;
8407 ptr = (__be32 *)(tcp+1);
7d3d0439 8408 lro->saw_ts = 1;
c8855953 8409 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8410 lro->cur_tsecr = *(ptr+2);
8411 }
8412 lro->in_use = 1;
8413}
8414
1ee6dd77 8415static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7d3d0439
RA		 8416{
8417 struct iphdr *ip = lro->iph;
8418 struct tcphdr *tcp = lro->tcph;
bd4f3ae1 8419 __sum16 nchk;
1ee6dd77 8420 struct stat_block *statinfo = sp->mac_control.stats_info;
b39d66a8 8421 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __func__);
7d3d0439
RA		 8422
8423 /* Update L3 header */
8424 ip->tot_len = htons(lro->total_len);
8425 ip->check = 0;
8426 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8427 ip->check = nchk;
8428
8429 /* Update L4 header */
8430 tcp->ack_seq = lro->tcp_ack;
8431 tcp->window = lro->window;
8432
8433 /* Update tsecr field if this session has timestamps enabled */
8434 if (lro->saw_ts) {
c8855953 8435 __be32 *ptr = (__be32 *)(tcp + 1);
7d3d0439
RA		 8436 *(ptr+2) = lro->cur_tsecr;
8437 }
8438
8439 /* Update counters required for calculation of
8440 * average no. of packets aggregated.
8441 */
8442 statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
8443 statinfo->sw_stat.num_aggregations++;
8444}
8445
1ee6dd77 8446static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 8447 struct tcphdr *tcp, u32 l4_pyld)
8448{
b39d66a8 8449 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __func__);
7d3d0439
RA		 8450 lro->total_len += l4_pyld;
8451 lro->frags_len += l4_pyld;
8452 lro->tcp_next_seq += l4_pyld;
8453 lro->sg_num++;
8454
8455 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8456 lro->tcp_ack = tcp->ack_seq;
8457 lro->window = tcp->window;
6aa20a22 8458
7d3d0439 8459 if (lro->saw_ts) {
c8855953 8460 __be32 *ptr;
7d3d0439 8461 /* Update tsecr and tsval from this packet */
c8855953
SR		 8462 ptr = (__be32 *)(tcp+1);
8463 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8464 lro->cur_tsecr = *(ptr + 2);
8465 }
8466}
8467
1ee6dd77 8468static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7d3d0439
RA		 8469 struct tcphdr *tcp, u32 tcp_pyld_len)
8470{
7d3d0439
RA		 8471 u8 *ptr;
8472
b39d66a8 8473 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __func__);
79dc1901 8474
7d3d0439
RA		 8475 if (!tcp_pyld_len) {
8476 /* Runt frame or a pure ack */
8477 return -1;
8478 }
8479
8480 if (ip->ihl != 5) /* IP has options */
8481 return -1;
8482
75c30b13
AR		 8483 /* If we see CE codepoint in IP header, packet is not mergeable */
8484 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8485 return -1;
8486
8487 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7d3d0439 8488 if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
75c30b13 8489 tcp->ece || tcp->cwr || !tcp->ack) {
7d3d0439
RA		 8490 /*
8491 * Currently recognize only the ack control word and
8492 * any other control field being set would result in
8493 * flushing the LRO session
8494 */
8495 return -1;
8496 }
8497
6aa20a22 8498 /*
7d3d0439
RA		 8499 * Allow only one TCP timestamp option. Don't aggregate if
8500 * any other options are detected.
8501 */
8502 if (tcp->doff != 5 && tcp->doff != 8)
8503 return -1;
8504
8505 if (tcp->doff == 8) {
6aa20a22 8506 ptr = (u8 *)(tcp + 1);
7d3d0439
RA		 8507 while (*ptr == TCPOPT_NOP)
8508 ptr++;
8509 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8510 return -1;
8511
8512 /* Ensure timestamp value increases monotonically */
8513 if (l_lro)
c8855953 8514 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
7d3d0439
RA		 8515 return -1;
8516
8517 /* timestamp echo reply should be non-zero */
c8855953 8518 if (*((__be32 *)(ptr+6)) == 0)
7d3d0439
RA		 8519 return -1;
8520 }
8521
8522 return 0;
8523}
8524
8525static int
0425b46a
SH		 8526s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer, u8 **tcp,
8527 u32 *tcp_len, struct lro **lro, struct RxD_t *rxdp,
8528 struct s2io_nic *sp)
7d3d0439
RA		 8529{
8530 struct iphdr *ip;
8531 struct tcphdr *tcph;
8532 int ret = 0, i;
cdb5bf02 8533 u16 vlan_tag = 0;
7d3d0439
RA		 8534
8535 if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
cdb5bf02 8536 rxdp, sp))) {
7d3d0439
RA		 8537 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
8538 ip->saddr, ip->daddr);
cdb5bf02 8539 } else
7d3d0439 8540 return ret;
7d3d0439 8541
cdb5bf02 8542 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
7d3d0439
RA		 8543 tcph = (struct tcphdr *)*tcp;
8544 *tcp_len = get_l4_pyld_length(ip, tcph);
8545 for (i=0; i<MAX_LRO_SESSIONS; i++) {
0425b46a 8546 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8547 if (l_lro->in_use) {
8548 if (check_for_socket_match(l_lro, ip, tcph))
8549 continue;
8550 /* Sock pair matched */
8551 *lro = l_lro;
8552
8553 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8554 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
b39d66a8 8555 "0x%x, actual 0x%x\n", __func__,
7d3d0439
RA		 8556 (*lro)->tcp_next_seq,
8557 ntohl(tcph->seq));
8558
8559 sp->mac_control.stats_info->
8560 sw_stat.outof_sequence_pkts++;
8561 ret = 2;
8562 break;
8563 }
8564
8565 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
8566 ret = 1; /* Aggregate */
8567 else
8568 ret = 2; /* Flush both */
8569 break;
8570 }
8571 }
8572
8573 if (ret == 0) {
8574 /* Before searching for available LRO objects,
8575 * check if the pkt is L3/L4 aggregatable. If not
8576 * don't create new LRO session. Just send this
8577 * packet up.
8578 */
8579 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
8580 return 5;
8581 }
8582
8583 for (i=0; i<MAX_LRO_SESSIONS; i++) {
0425b46a 8584 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8585 if (!(l_lro->in_use)) {
8586 *lro = l_lro;
8587 ret = 3; /* Begin anew */
8588 break;
8589 }
8590 }
8591 }
8592
8593 if (ret == 0) { /* sessions exceeded */
8594 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
b39d66a8 8595 __func__);
7d3d0439
RA		 8596 *lro = NULL;
8597 return ret;
8598 }
8599
8600 switch (ret) {
8601 case 3:
cdb5bf02
SH		 8602 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8603 vlan_tag);
7d3d0439
RA		 8604 break;
8605 case 2:
8606 update_L3L4_header(sp, *lro);
8607 break;
8608 case 1:
8609 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8610 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8611 update_L3L4_header(sp, *lro);
8612 ret = 4; /* Flush the LRO */
8613 }
8614 break;
8615 default:
8616 DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
b39d66a8 8617 __func__);
7d3d0439
RA		 8618 break;
8619 }
8620
8621 return ret;
8622}
8623
1ee6dd77 8624static void clear_lro_session(struct lro *lro)
7d3d0439 8625{
1ee6dd77 8626 static u16 lro_struct_size = sizeof(struct lro);
7d3d0439
RA		 8627
8628 memset(lro, 0, lro_struct_size);
8629}
8630
cdb5bf02 8631static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
7d3d0439
RA		 8632{
8633 struct net_device *dev = skb->dev;
4cf1653a 8634 struct s2io_nic *sp = netdev_priv(dev);
7d3d0439
RA		 8635
8636 skb->protocol = eth_type_trans(skb, dev);
cdb5bf02 8637 if (sp->vlgrp && vlan_tag
cd0fce03 8638 && (sp->vlan_strip_flag)) {
cdb5bf02
SH		 8639 /* Queueing the vlan frame to the upper layer */
8640 if (sp->config.napi)
8641 vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8642 else
8643 vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8644 } else {
8645 if (sp->config.napi)
8646 netif_receive_skb(skb);
8647 else
8648 netif_rx(skb);
8649 }
7d3d0439
RA		 8650}
8651
1ee6dd77
RB		 8652static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8653 struct sk_buff *skb,
7d3d0439
RA		 8654 u32 tcp_len)
8655{
75c30b13 8656 struct sk_buff *first = lro->parent;
7d3d0439
RA		 8657
8658 first->len += tcp_len;
8659 first->data_len = lro->frags_len;
8660 skb_pull(skb, (skb->len - tcp_len));
75c30b13
AR		 8661 if (skb_shinfo(first)->frag_list)
8662 lro->last_frag->next = skb;
7d3d0439
RA		 8663 else
8664 skb_shinfo(first)->frag_list = skb;
372cc597 8665 first->truesize += skb->truesize;
75c30b13 8666 lro->last_frag = skb;
7d3d0439
RA		 8667 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
8668 return;
8669}
d796fdb7
LV		 8670
8671/**
8672 * s2io_io_error_detected - called when PCI error is detected
8673 * @pdev: Pointer to PCI device
8453d43f 8674 * @state: The current pci connection state
d796fdb7
LV		 8675 *
8676 * This function is called after a PCI bus error affecting
8677 * this device has been detected.
8678 */
8679static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8680 pci_channel_state_t state)
8681{
8682 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8683 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8684
8685 netif_device_detach(netdev);
8686
1e3c8bd6
DN		 8687 if (state == pci_channel_io_perm_failure)
8688 return PCI_ERS_RESULT_DISCONNECT;
8689
d796fdb7
LV		 8690 if (netif_running(netdev)) {
8691 /* Bring down the card, while avoiding PCI I/O */
8692 do_s2io_card_down(sp, 0);
d796fdb7
LV		 8693 }
8694 pci_disable_device(pdev);
8695
8696 return PCI_ERS_RESULT_NEED_RESET;
8697}
8698
8699/**
8700 * s2io_io_slot_reset - called after the pci bus has been reset.
8701 * @pdev: Pointer to PCI device
8702 *
8703 * Restart the card from scratch, as if from a cold-boot.
8704 * At this point, the card has exprienced a hard reset,
8705 * followed by fixups by BIOS, and has its config space
8706 * set up identically to what it was at cold boot.
8707 */
8708static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8709{
8710 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8711 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8712
8713 if (pci_enable_device(pdev)) {
8714 printk(KERN_ERR "s2io: "
8715 "Cannot re-enable PCI device after reset.\n");
8716 return PCI_ERS_RESULT_DISCONNECT;
8717 }
8718
8719 pci_set_master(pdev);
8720 s2io_reset(sp);
8721
8722 return PCI_ERS_RESULT_RECOVERED;
8723}
8724
8725/**
8726 * s2io_io_resume - called when traffic can start flowing again.
8727 * @pdev: Pointer to PCI device
8728 *
8729 * This callback is called when the error recovery driver tells
8730 * us that its OK to resume normal operation.
8731 */
8732static void s2io_io_resume(struct pci_dev *pdev)
8733{
8734 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8735 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8736
8737 if (netif_running(netdev)) {
8738 if (s2io_card_up(sp)) {
8739 printk(KERN_ERR "s2io: "
8740 "Can't bring device back up after reset.\n");
8741 return;
8742 }
8743
8744 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8745 s2io_card_down(sp);
8746 printk(KERN_ERR "s2io: "
8747 "Can't resetore mac addr after reset.\n");
8748 return;
8749 }
8750 }
8751
8752 netif_device_attach(netdev);
fd2ea0a7 8753 netif_tx_wake_all_queues(netdev);
d796fdb7 8754}
kernel source for telekom puls (alcatel/mediatek)