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Merge remote branch 'origin' into secretlab/next-spi
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / s2io.c
CommitLineData
1da177e4 1/************************************************************************
776bd20f 2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
0c61ed5f 3 * Copyright(c) 2002-2007 Neterion Inc.
d44570e4 4 *
1da177e4
LT		 5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
20346722
K		 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
1da177e4
LT		 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
20346722 21 * Francois Romieu : For pointing out all code part that were
1da177e4 22 * deprecated and also styling related comments.
20346722 23 * Grant Grundler : For helping me get rid of some Architecture
1da177e4
LT		 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
20346722 26 *
1da177e4 27 * The module loadable parameters that are supported by the driver and a brief
a2a20aef 28 * explanation of all the variables.
9dc737a7 29 *
20346722
K		 30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
9dc737a7
AR		 32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
da6971d8 34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
6d517a27 35 * values are 1, 2.
1da177e4 36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
20346722 37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
1da177e4 38 * Tx descriptors that can be associated with each corresponding FIFO.
9dc737a7 39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
8abc4d5b 40 * 2(MSI_X). Default value is '2(MSI_X)'
43b7c451 41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
9dc737a7
AR		 42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
926930b2
SS		 45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
3a3d5756
SH		 53 * multiq: This parameter used to enable/disable MULTIQUEUE support.
54 * Possible values '1' for enable and '0' for disable. Default is '0'
1da177e4
LT		 55 ************************************************************************/
56
6cef2b8e
JP		 57#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
58
1da177e4
LT		 59#include <linux/module.h>
60#include <linux/types.h>
61#include <linux/errno.h>
62#include <linux/ioport.h>
63#include <linux/pci.h>
1e7f0bd8 64#include <linux/dma-mapping.h>
1da177e4
LT		 65#include <linux/kernel.h>
66#include <linux/netdevice.h>
67#include <linux/etherdevice.h>
40239396 68#include <linux/mdio.h>
1da177e4
LT		 69#include <linux/skbuff.h>
70#include <linux/init.h>
71#include <linux/delay.h>
72#include <linux/stddef.h>
73#include <linux/ioctl.h>
74#include <linux/timex.h>
1da177e4 75#include <linux/ethtool.h>
1da177e4 76#include <linux/workqueue.h>
be3a6b02 77#include <linux/if_vlan.h>
7d3d0439
RA		 78#include <linux/ip.h>
79#include <linux/tcp.h>
d44570e4
JP		 80#include <linux/uaccess.h>
81#include <linux/io.h>
5a0e3ad6 82#include <linux/slab.h>
7d3d0439 83#include <net/tcp.h>
1da177e4 84
1da177e4 85#include <asm/system.h>
fe931395 86#include <asm/div64.h>
330ce0de 87#include <asm/irq.h>
1da177e4
LT		 88
89/* local include */
90#include "s2io.h"
91#include "s2io-regs.h"
92
29d0a2b0 93#define DRV_VERSION "2.0.26.25"
6c1792f4 94
1da177e4 95/* S2io Driver name & version. */
20346722 96static char s2io_driver_name[] = "Neterion";
6c1792f4 97static char s2io_driver_version[] = DRV_VERSION;
1da177e4 98
d44570e4
JP		 99static int rxd_size[2] = {32, 48};
100static int rxd_count[2] = {127, 85};
da6971d8 101
1ee6dd77 102static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
5e25b9dd
K		 103{
104 int ret;
105
106 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
d44570e4 107 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
5e25b9dd
K		 108
109 return ret;
110}
111
20346722 112/*
1da177e4
LT		 113 * Cards with following subsystem_id have a link state indication
114 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
115 * macro below identifies these cards given the subsystem_id.
116 */
d44570e4
JP		 117#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
118 (dev_type == XFRAME_I_DEVICE) ? \
119 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
120 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
1da177e4
LT		 121
122#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
123 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
1da177e4 124
d44570e4 125static inline int is_s2io_card_up(const struct s2io_nic *sp)
92b84437
SS		 126{
127 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
128}
129
1da177e4 130/* Ethtool related variables and Macros. */
6fce365d 131static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
1da177e4
LT		 132 "Register test\t(offline)",
133 "Eeprom test\t(offline)",
134 "Link test\t(online)",
135 "RLDRAM test\t(offline)",
136 "BIST Test\t(offline)"
137};
138
6fce365d 139static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
1da177e4
LT		 140 {"tmac_frms"},
141 {"tmac_data_octets"},
142 {"tmac_drop_frms"},
143 {"tmac_mcst_frms"},
144 {"tmac_bcst_frms"},
145 {"tmac_pause_ctrl_frms"},
bd1034f0
AR		 146 {"tmac_ttl_octets"},
147 {"tmac_ucst_frms"},
148 {"tmac_nucst_frms"},
1da177e4 149 {"tmac_any_err_frms"},
bd1034f0 150 {"tmac_ttl_less_fb_octets"},
1da177e4
LT		 151 {"tmac_vld_ip_octets"},
152 {"tmac_vld_ip"},
153 {"tmac_drop_ip"},
154 {"tmac_icmp"},
155 {"tmac_rst_tcp"},
156 {"tmac_tcp"},
157 {"tmac_udp"},
158 {"rmac_vld_frms"},
159 {"rmac_data_octets"},
160 {"rmac_fcs_err_frms"},
161 {"rmac_drop_frms"},
162 {"rmac_vld_mcst_frms"},
163 {"rmac_vld_bcst_frms"},
164 {"rmac_in_rng_len_err_frms"},
bd1034f0 165 {"rmac_out_rng_len_err_frms"},
1da177e4
LT		 166 {"rmac_long_frms"},
167 {"rmac_pause_ctrl_frms"},
bd1034f0
AR		 168 {"rmac_unsup_ctrl_frms"},
169 {"rmac_ttl_octets"},
170 {"rmac_accepted_ucst_frms"},
171 {"rmac_accepted_nucst_frms"},
1da177e4 172 {"rmac_discarded_frms"},
bd1034f0
AR		 173 {"rmac_drop_events"},
174 {"rmac_ttl_less_fb_octets"},
175 {"rmac_ttl_frms"},
1da177e4
LT		 176 {"rmac_usized_frms"},
177 {"rmac_osized_frms"},
178 {"rmac_frag_frms"},
179 {"rmac_jabber_frms"},
bd1034f0
AR		 180 {"rmac_ttl_64_frms"},
181 {"rmac_ttl_65_127_frms"},
182 {"rmac_ttl_128_255_frms"},
183 {"rmac_ttl_256_511_frms"},
184 {"rmac_ttl_512_1023_frms"},
185 {"rmac_ttl_1024_1518_frms"},
1da177e4
LT		 186 {"rmac_ip"},
187 {"rmac_ip_octets"},
188 {"rmac_hdr_err_ip"},
189 {"rmac_drop_ip"},
190 {"rmac_icmp"},
191 {"rmac_tcp"},
192 {"rmac_udp"},
193 {"rmac_err_drp_udp"},
bd1034f0
AR		 194 {"rmac_xgmii_err_sym"},
195 {"rmac_frms_q0"},
196 {"rmac_frms_q1"},
197 {"rmac_frms_q2"},
198 {"rmac_frms_q3"},
199 {"rmac_frms_q4"},
200 {"rmac_frms_q5"},
201 {"rmac_frms_q6"},
202 {"rmac_frms_q7"},
203 {"rmac_full_q0"},
204 {"rmac_full_q1"},
205 {"rmac_full_q2"},
206 {"rmac_full_q3"},
207 {"rmac_full_q4"},
208 {"rmac_full_q5"},
209 {"rmac_full_q6"},
210 {"rmac_full_q7"},
1da177e4 211 {"rmac_pause_cnt"},
bd1034f0
AR		 212 {"rmac_xgmii_data_err_cnt"},
213 {"rmac_xgmii_ctrl_err_cnt"},
1da177e4
LT		 214 {"rmac_accepted_ip"},
215 {"rmac_err_tcp"},
bd1034f0
AR		 216 {"rd_req_cnt"},
217 {"new_rd_req_cnt"},
218 {"new_rd_req_rtry_cnt"},
219 {"rd_rtry_cnt"},
220 {"wr_rtry_rd_ack_cnt"},
221 {"wr_req_cnt"},
222 {"new_wr_req_cnt"},
223 {"new_wr_req_rtry_cnt"},
224 {"wr_rtry_cnt"},
225 {"wr_disc_cnt"},
226 {"rd_rtry_wr_ack_cnt"},
227 {"txp_wr_cnt"},
228 {"txd_rd_cnt"},
229 {"txd_wr_cnt"},
230 {"rxd_rd_cnt"},
231 {"rxd_wr_cnt"},
232 {"txf_rd_cnt"},
fa1f0cb3
SS		 233 {"rxf_wr_cnt"}
234};
235
6fce365d 236static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
bd1034f0
AR		 237 {"rmac_ttl_1519_4095_frms"},
238 {"rmac_ttl_4096_8191_frms"},
239 {"rmac_ttl_8192_max_frms"},
240 {"rmac_ttl_gt_max_frms"},
241 {"rmac_osized_alt_frms"},
242 {"rmac_jabber_alt_frms"},
243 {"rmac_gt_max_alt_frms"},
244 {"rmac_vlan_frms"},
245 {"rmac_len_discard"},
246 {"rmac_fcs_discard"},
247 {"rmac_pf_discard"},
248 {"rmac_da_discard"},
249 {"rmac_red_discard"},
250 {"rmac_rts_discard"},
251 {"rmac_ingm_full_discard"},
fa1f0cb3
SS		 252 {"link_fault_cnt"}
253};
254
6fce365d 255static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
7ba013ac
K		 256 {"\n DRIVER STATISTICS"},
257 {"single_bit_ecc_errs"},
258 {"double_bit_ecc_errs"},
bd1034f0
AR		 259 {"parity_err_cnt"},
260 {"serious_err_cnt"},
261 {"soft_reset_cnt"},
262 {"fifo_full_cnt"},
8116f3cf
SS		 263 {"ring_0_full_cnt"},
264 {"ring_1_full_cnt"},
265 {"ring_2_full_cnt"},
266 {"ring_3_full_cnt"},
267 {"ring_4_full_cnt"},
268 {"ring_5_full_cnt"},
269 {"ring_6_full_cnt"},
270 {"ring_7_full_cnt"},
43b7c451
SH		 271 {"alarm_transceiver_temp_high"},
272 {"alarm_transceiver_temp_low"},
273 {"alarm_laser_bias_current_high"},
274 {"alarm_laser_bias_current_low"},
275 {"alarm_laser_output_power_high"},
276 {"alarm_laser_output_power_low"},
277 {"warn_transceiver_temp_high"},
278 {"warn_transceiver_temp_low"},
279 {"warn_laser_bias_current_high"},
280 {"warn_laser_bias_current_low"},
281 {"warn_laser_output_power_high"},
282 {"warn_laser_output_power_low"},
283 {"lro_aggregated_pkts"},
284 {"lro_flush_both_count"},
285 {"lro_out_of_sequence_pkts"},
286 {"lro_flush_due_to_max_pkts"},
287 {"lro_avg_aggr_pkts"},
288 {"mem_alloc_fail_cnt"},
289 {"pci_map_fail_cnt"},
290 {"watchdog_timer_cnt"},
291 {"mem_allocated"},
292 {"mem_freed"},
293 {"link_up_cnt"},
294 {"link_down_cnt"},
295 {"link_up_time"},
296 {"link_down_time"},
297 {"tx_tcode_buf_abort_cnt"},
298 {"tx_tcode_desc_abort_cnt"},
299 {"tx_tcode_parity_err_cnt"},
300 {"tx_tcode_link_loss_cnt"},
301 {"tx_tcode_list_proc_err_cnt"},
302 {"rx_tcode_parity_err_cnt"},
303 {"rx_tcode_abort_cnt"},
304 {"rx_tcode_parity_abort_cnt"},
305 {"rx_tcode_rda_fail_cnt"},
306 {"rx_tcode_unkn_prot_cnt"},
307 {"rx_tcode_fcs_err_cnt"},
308 {"rx_tcode_buf_size_err_cnt"},
309 {"rx_tcode_rxd_corrupt_cnt"},
310 {"rx_tcode_unkn_err_cnt"},
8116f3cf
SS		 311 {"tda_err_cnt"},
312 {"pfc_err_cnt"},
313 {"pcc_err_cnt"},
314 {"tti_err_cnt"},
315 {"tpa_err_cnt"},
316 {"sm_err_cnt"},
317 {"lso_err_cnt"},
318 {"mac_tmac_err_cnt"},
319 {"mac_rmac_err_cnt"},
320 {"xgxs_txgxs_err_cnt"},
321 {"xgxs_rxgxs_err_cnt"},
322 {"rc_err_cnt"},
323 {"prc_pcix_err_cnt"},
324 {"rpa_err_cnt"},
325 {"rda_err_cnt"},
326 {"rti_err_cnt"},
327 {"mc_err_cnt"}
1da177e4
LT		 328};
329
4c3616cd
AMR		 330#define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
331#define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
332#define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
fa1f0cb3 333
d44570e4
JP		 334#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
335#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
fa1f0cb3 336
d44570e4
JP		 337#define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
338#define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
1da177e4 339
4c3616cd 340#define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
d44570e4 341#define S2IO_STRINGS_LEN (S2IO_TEST_LEN * ETH_GSTRING_LEN)
1da177e4 342
d44570e4
JP		 343#define S2IO_TIMER_CONF(timer, handle, arg, exp) \
344 init_timer(&timer); \
345 timer.function = handle; \
346 timer.data = (unsigned long)arg; \
347 mod_timer(&timer, (jiffies + exp)) \
25fff88e 348
2fd37688
SS		 349/* copy mac addr to def_mac_addr array */
350static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
351{
352 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
353 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
354 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
355 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
356 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
357 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
358}
04025095 359
be3a6b02
K		 360/* Add the vlan */
361static void s2io_vlan_rx_register(struct net_device *dev,
04025095 362 struct vlan_group *grp)
be3a6b02 363{
2fda096d 364 int i;
4cf1653a 365 struct s2io_nic *nic = netdev_priv(dev);
2fda096d 366 unsigned long flags[MAX_TX_FIFOS];
2fda096d 367 struct config_param *config = &nic->config;
ffb5df6c 368 struct mac_info *mac_control = &nic->mac_control;
2fda096d 369
13d866a9
JP		 370 for (i = 0; i < config->tx_fifo_num; i++) {
371 struct fifo_info *fifo = &mac_control->fifos[i];
372
373 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
374 }
be3a6b02 375
be3a6b02 376 nic->vlgrp = grp;
13d866a9
JP		 377
378 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
379 struct fifo_info *fifo = &mac_control->fifos[i];
380
381 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
382 }
be3a6b02
K		 383}
384
cdb5bf02 385/* Unregister the vlan */
04025095 386static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
cdb5bf02
SH		 387{
388 int i;
4cf1653a 389 struct s2io_nic *nic = netdev_priv(dev);
cdb5bf02 390 unsigned long flags[MAX_TX_FIFOS];
cdb5bf02 391 struct config_param *config = &nic->config;
ffb5df6c 392 struct mac_info *mac_control = &nic->mac_control;
cdb5bf02 393
13d866a9
JP		 394 for (i = 0; i < config->tx_fifo_num; i++) {
395 struct fifo_info *fifo = &mac_control->fifos[i];
396
397 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
398 }
cdb5bf02
SH		 399
400 if (nic->vlgrp)
401 vlan_group_set_device(nic->vlgrp, vid, NULL);
402
13d866a9
JP		 403 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
404 struct fifo_info *fifo = &mac_control->fifos[i];
405
406 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
407 }
cdb5bf02
SH		 408}
409
20346722 410/*
1da177e4
LT		 411 * Constants to be programmed into the Xena's registers, to configure
412 * the XAUI.
413 */
414
1da177e4 415#define END_SIGN 0x0
f71e1309 416static const u64 herc_act_dtx_cfg[] = {
541ae68f 417 /* Set address */
e960fc5c 418 0x8000051536750000ULL, 0x80000515367500E0ULL,
541ae68f 419 /* Write data */
e960fc5c 420 0x8000051536750004ULL, 0x80000515367500E4ULL,
541ae68f
K		 421 /* Set address */
422 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
423 /* Write data */
424 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
425 /* Set address */
e960fc5c 426 0x801205150D440000ULL, 0x801205150D4400E0ULL,
427 /* Write data */
428 0x801205150D440004ULL, 0x801205150D4400E4ULL,
429 /* Set address */
541ae68f
K		 430 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
431 /* Write data */
432 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
433 /* Done */
434 END_SIGN
435};
436
f71e1309 437static const u64 xena_dtx_cfg[] = {
c92ca04b 438 /* Set address */
1da177e4 439 0x8000051500000000ULL, 0x80000515000000E0ULL,
c92ca04b
AR		 440 /* Write data */
441 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
442 /* Set address */
443 0x8001051500000000ULL, 0x80010515000000E0ULL,
444 /* Write data */
445 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
446 /* Set address */
1da177e4 447 0x8002051500000000ULL, 0x80020515000000E0ULL,
c92ca04b
AR		 448 /* Write data */
449 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1da177e4
LT		 450 END_SIGN
451};
452
20346722 453/*
1da177e4
LT		 454 * Constants for Fixing the MacAddress problem seen mostly on
455 * Alpha machines.
456 */
f71e1309 457static const u64 fix_mac[] = {
1da177e4
LT		 458 0x0060000000000000ULL, 0x0060600000000000ULL,
459 0x0040600000000000ULL, 0x0000600000000000ULL,
460 0x0020600000000000ULL, 0x0060600000000000ULL,
461 0x0020600000000000ULL, 0x0060600000000000ULL,
462 0x0020600000000000ULL, 0x0060600000000000ULL,
463 0x0020600000000000ULL, 0x0060600000000000ULL,
464 0x0020600000000000ULL, 0x0060600000000000ULL,
465 0x0020600000000000ULL, 0x0060600000000000ULL,
466 0x0020600000000000ULL, 0x0060600000000000ULL,
467 0x0020600000000000ULL, 0x0060600000000000ULL,
468 0x0020600000000000ULL, 0x0060600000000000ULL,
469 0x0020600000000000ULL, 0x0060600000000000ULL,
470 0x0020600000000000ULL, 0x0000600000000000ULL,
471 0x0040600000000000ULL, 0x0060600000000000ULL,
472 END_SIGN
473};
474
b41477f3
AR		 475MODULE_LICENSE("GPL");
476MODULE_VERSION(DRV_VERSION);
477
478
1da177e4 479/* Module Loadable parameters. */
6cfc482b 480S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
b41477f3 481S2IO_PARM_INT(rx_ring_num, 1);
3a3d5756 482S2IO_PARM_INT(multiq, 0);
b41477f3
AR		 483S2IO_PARM_INT(rx_ring_mode, 1);
484S2IO_PARM_INT(use_continuous_tx_intrs, 1);
485S2IO_PARM_INT(rmac_pause_time, 0x100);
486S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
487S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
488S2IO_PARM_INT(shared_splits, 0);
489S2IO_PARM_INT(tmac_util_period, 5);
490S2IO_PARM_INT(rmac_util_period, 5);
b41477f3 491S2IO_PARM_INT(l3l4hdr_size, 128);
6cfc482b
SH		 492/* 0 is no steering, 1 is Priority steering, 2 is Default steering */
493S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
303bcb4b 494/* Frequency of Rx desc syncs expressed as power of 2 */
b41477f3 495S2IO_PARM_INT(rxsync_frequency, 3);
eccb8628 496/* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
8abc4d5b 497S2IO_PARM_INT(intr_type, 2);
7d3d0439 498/* Large receive offload feature */
43b7c451
SH		 499static unsigned int lro_enable;
500module_param_named(lro, lro_enable, uint, 0);
501
7d3d0439
RA		 502/* Max pkts to be aggregated by LRO at one time. If not specified,
503 * aggregation happens until we hit max IP pkt size(64K)
504 */
b41477f3 505S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
b41477f3 506S2IO_PARM_INT(indicate_max_pkts, 0);
db874e65
SS		 507
508S2IO_PARM_INT(napi, 1);
509S2IO_PARM_INT(ufo, 0);
926930b2 510S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
b41477f3
AR		 511
512static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
d44570e4 513{DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
b41477f3 514static unsigned int rx_ring_sz[MAX_RX_RINGS] =
d44570e4 515{[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
b41477f3 516static unsigned int rts_frm_len[MAX_RX_RINGS] =
d44570e4 517{[0 ...(MAX_RX_RINGS - 1)] = 0 };
b41477f3
AR		 518
519module_param_array(tx_fifo_len, uint, NULL, 0);
520module_param_array(rx_ring_sz, uint, NULL, 0);
521module_param_array(rts_frm_len, uint, NULL, 0);
1da177e4 522
20346722 523/*
1da177e4 524 * S2IO device table.
20346722 525 * This table lists all the devices that this driver supports.
1da177e4 526 */
a3aa1884 527static DEFINE_PCI_DEVICE_TABLE(s2io_tbl) = {
1da177e4
LT		 528 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
529 PCI_ANY_ID, PCI_ANY_ID},
530 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
531 PCI_ANY_ID, PCI_ANY_ID},
532 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
d44570e4
JP		 533 PCI_ANY_ID, PCI_ANY_ID},
534 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
535 PCI_ANY_ID, PCI_ANY_ID},
1da177e4
LT		 536 {0,}
537};
538
539MODULE_DEVICE_TABLE(pci, s2io_tbl);
540
d796fdb7
LV		 541static struct pci_error_handlers s2io_err_handler = {
542 .error_detected = s2io_io_error_detected,
543 .slot_reset = s2io_io_slot_reset,
544 .resume = s2io_io_resume,
545};
546
1da177e4 547static struct pci_driver s2io_driver = {
d44570e4
JP		 548 .name = "S2IO",
549 .id_table = s2io_tbl,
550 .probe = s2io_init_nic,
551 .remove = __devexit_p(s2io_rem_nic),
552 .err_handler = &s2io_err_handler,
1da177e4
LT		 553};
554
555/* A simplifier macro used both by init and free shared_mem Fns(). */
556#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
557
3a3d5756
SH		 558/* netqueue manipulation helper functions */
559static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
560{
fd2ea0a7
DM		 561 if (!sp->config.multiq) {
562 int i;
563
3a3d5756
SH		 564 for (i = 0; i < sp->config.tx_fifo_num; i++)
565 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
3a3d5756 566 }
fd2ea0a7 567 netif_tx_stop_all_queues(sp->dev);
3a3d5756
SH		 568}
569
570static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
571{
fd2ea0a7 572 if (!sp->config.multiq)
3a3d5756
SH		 573 sp->mac_control.fifos[fifo_no].queue_state =
574 FIFO_QUEUE_STOP;
fd2ea0a7
DM		 575
576 netif_tx_stop_all_queues(sp->dev);
3a3d5756
SH		 577}
578
579static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
580{
fd2ea0a7
DM		 581 if (!sp->config.multiq) {
582 int i;
583
3a3d5756
SH		 584 for (i = 0; i < sp->config.tx_fifo_num; i++)
585 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
3a3d5756 586 }
fd2ea0a7 587 netif_tx_start_all_queues(sp->dev);
3a3d5756
SH		 588}
589
590static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
591{
fd2ea0a7 592 if (!sp->config.multiq)
3a3d5756
SH		 593 sp->mac_control.fifos[fifo_no].queue_state =
594 FIFO_QUEUE_START;
fd2ea0a7
DM		 595
596 netif_tx_start_all_queues(sp->dev);
3a3d5756
SH		 597}
598
599static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
600{
fd2ea0a7
DM		 601 if (!sp->config.multiq) {
602 int i;
603
3a3d5756
SH		 604 for (i = 0; i < sp->config.tx_fifo_num; i++)
605 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
3a3d5756 606 }
fd2ea0a7 607 netif_tx_wake_all_queues(sp->dev);
3a3d5756
SH		 608}
609
610static inline void s2io_wake_tx_queue(
611 struct fifo_info *fifo, int cnt, u8 multiq)
612{
613
3a3d5756
SH		 614 if (multiq) {
615 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
616 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
b19fa1fa 617 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
3a3d5756
SH		 618 if (netif_queue_stopped(fifo->dev)) {
619 fifo->queue_state = FIFO_QUEUE_START;
620 netif_wake_queue(fifo->dev);
621 }
622 }
623}
624
1da177e4
LT		 625/**
626 * init_shared_mem - Allocation and Initialization of Memory
627 * @nic: Device private variable.
20346722
K		 628 * Description: The function allocates all the memory areas shared
629 * between the NIC and the driver. This includes Tx descriptors,
1da177e4
LT		 630 * Rx descriptors and the statistics block.
631 */
632
633static int init_shared_mem(struct s2io_nic *nic)
634{
635 u32 size;
636 void *tmp_v_addr, *tmp_v_addr_next;
637 dma_addr_t tmp_p_addr, tmp_p_addr_next;
1ee6dd77 638 struct RxD_block *pre_rxd_blk = NULL;
372cc597 639 int i, j, blk_cnt;
1da177e4
LT		 640 int lst_size, lst_per_page;
641 struct net_device *dev = nic->dev;
8ae418cf 642 unsigned long tmp;
1ee6dd77 643 struct buffAdd *ba;
ffb5df6c
JP		 644 struct config_param *config = &nic->config;
645 struct mac_info *mac_control = &nic->mac_control;
491976b2 646 unsigned long long mem_allocated = 0;
1da177e4 647
13d866a9 648 /* Allocation and initialization of TXDLs in FIFOs */
1da177e4
LT		 649 size = 0;
650 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 651 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
652
653 size += tx_cfg->fifo_len;
1da177e4
LT		 654 }
655 if (size > MAX_AVAILABLE_TXDS) {
9e39f7c5
JP		 656 DBG_PRINT(ERR_DBG,
657 "Too many TxDs requested: %d, max supported: %d\n",
658 size, MAX_AVAILABLE_TXDS);
b41477f3 659 return -EINVAL;
1da177e4
LT		 660 }
661
2fda096d
SR		 662 size = 0;
663 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 664 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
665
666 size = tx_cfg->fifo_len;
2fda096d
SR		 667 /*
668 * Legal values are from 2 to 8192
669 */
670 if (size < 2) {
9e39f7c5
JP		 671 DBG_PRINT(ERR_DBG, "Fifo %d: Invalid length (%d) - "
672 "Valid lengths are 2 through 8192\n",
673 i, size);
2fda096d
SR		 674 return -EINVAL;
675 }
676 }
677
1ee6dd77 678 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 679 lst_per_page = PAGE_SIZE / lst_size;
680
681 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 682 struct fifo_info *fifo = &mac_control->fifos[i];
683 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
684 int fifo_len = tx_cfg->fifo_len;
1ee6dd77 685 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
13d866a9
JP		 686
687 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
688 if (!fifo->list_info) {
d44570e4 689 DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
1da177e4
LT		 690 return -ENOMEM;
691 }
491976b2 692 mem_allocated += list_holder_size;
1da177e4
LT		 693 }
694 for (i = 0; i < config->tx_fifo_num; i++) {
695 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
696 lst_per_page);
13d866a9
JP		 697 struct fifo_info *fifo = &mac_control->fifos[i];
698 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
699
700 fifo->tx_curr_put_info.offset = 0;
701 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
702 fifo->tx_curr_get_info.offset = 0;
703 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
704 fifo->fifo_no = i;
705 fifo->nic = nic;
706 fifo->max_txds = MAX_SKB_FRAGS + 2;
707 fifo->dev = dev;
20346722 708
1da177e4
LT		 709 for (j = 0; j < page_num; j++) {
710 int k = 0;
711 dma_addr_t tmp_p;
712 void *tmp_v;
713 tmp_v = pci_alloc_consistent(nic->pdev,
714 PAGE_SIZE, &tmp_p);
715 if (!tmp_v) {
9e39f7c5
JP		 716 DBG_PRINT(INFO_DBG,
717 "pci_alloc_consistent failed for TxDL\n");
1da177e4
LT		 718 return -ENOMEM;
719 }
776bd20f 720 /* If we got a zero DMA address(can happen on
721 * certain platforms like PPC), reallocate.
722 * Store virtual address of page we don't want,
723 * to be freed later.
724 */
725 if (!tmp_p) {
726 mac_control->zerodma_virt_addr = tmp_v;
6aa20a22 727 DBG_PRINT(INIT_DBG,
9e39f7c5
JP		 728 "%s: Zero DMA address for TxDL. "
729 "Virtual address %p\n",
730 dev->name, tmp_v);
776bd20f 731 tmp_v = pci_alloc_consistent(nic->pdev,
d44570e4 732 PAGE_SIZE, &tmp_p);
776bd20f 733 if (!tmp_v) {
0c61ed5f 734 DBG_PRINT(INFO_DBG,
9e39f7c5 735 "pci_alloc_consistent failed for TxDL\n");
776bd20f 736 return -ENOMEM;
737 }
491976b2 738 mem_allocated += PAGE_SIZE;
776bd20f 739 }
1da177e4
LT		 740 while (k < lst_per_page) {
741 int l = (j * lst_per_page) + k;
13d866a9 742 if (l == tx_cfg->fifo_len)
20346722 743 break;
13d866a9 744 fifo->list_info[l].list_virt_addr =
d44570e4 745 tmp_v + (k * lst_size);
13d866a9 746 fifo->list_info[l].list_phy_addr =
d44570e4 747 tmp_p + (k * lst_size);
1da177e4
LT		 748 k++;
749 }
750 }
751 }
1da177e4 752
2fda096d 753 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 754 struct fifo_info *fifo = &mac_control->fifos[i];
755 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
756
757 size = tx_cfg->fifo_len;
758 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
759 if (!fifo->ufo_in_band_v)
2fda096d
SR		 760 return -ENOMEM;
761 mem_allocated += (size * sizeof(u64));
762 }
fed5eccd 763
1da177e4
LT		 764 /* Allocation and initialization of RXDs in Rings */
765 size = 0;
766 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 767 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
768 struct ring_info *ring = &mac_control->rings[i];
769
770 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
9e39f7c5
JP		 771 DBG_PRINT(ERR_DBG, "%s: Ring%d RxD count is not a "
772 "multiple of RxDs per Block\n",
773 dev->name, i);
1da177e4
LT		 774 return FAILURE;
775 }
13d866a9
JP		 776 size += rx_cfg->num_rxd;
777 ring->block_count = rx_cfg->num_rxd /
d44570e4 778 (rxd_count[nic->rxd_mode] + 1);
13d866a9 779 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
1da177e4 780 }
da6971d8 781 if (nic->rxd_mode == RXD_MODE_1)
1ee6dd77 782 size = (size * (sizeof(struct RxD1)));
da6971d8 783 else
1ee6dd77 784 size = (size * (sizeof(struct RxD3)));
1da177e4
LT		 785
786 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 787 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
788 struct ring_info *ring = &mac_control->rings[i];
789
790 ring->rx_curr_get_info.block_index = 0;
791 ring->rx_curr_get_info.offset = 0;
792 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
793 ring->rx_curr_put_info.block_index = 0;
794 ring->rx_curr_put_info.offset = 0;
795 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
796 ring->nic = nic;
797 ring->ring_no = i;
798 ring->lro = lro_enable;
799
800 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
1da177e4
LT		 801 /* Allocating all the Rx blocks */
802 for (j = 0; j < blk_cnt; j++) {
1ee6dd77 803 struct rx_block_info *rx_blocks;
da6971d8
AR		 804 int l;
805
13d866a9 806 rx_blocks = &ring->rx_blocks[j];
d44570e4 807 size = SIZE_OF_BLOCK; /* size is always page size */
1da177e4
LT		 808 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
809 &tmp_p_addr);
810 if (tmp_v_addr == NULL) {
811 /*
20346722
K		 812 * In case of failure, free_shared_mem()
813 * is called, which should free any
814 * memory that was alloced till the
1da177e4
LT		 815 * failure happened.
816 */
da6971d8 817 rx_blocks->block_virt_addr = tmp_v_addr;
1da177e4
LT		 818 return -ENOMEM;
819 }
491976b2 820 mem_allocated += size;
1da177e4 821 memset(tmp_v_addr, 0, size);
4f870320
JP		 822
823 size = sizeof(struct rxd_info) *
824 rxd_count[nic->rxd_mode];
da6971d8
AR		 825 rx_blocks->block_virt_addr = tmp_v_addr;
826 rx_blocks->block_dma_addr = tmp_p_addr;
4f870320 827 rx_blocks->rxds = kmalloc(size, GFP_KERNEL);
372cc597
SS		 828 if (!rx_blocks->rxds)
829 return -ENOMEM;
4f870320 830 mem_allocated += size;
d44570e4 831 for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
da6971d8
AR		 832 rx_blocks->rxds[l].virt_addr =
833 rx_blocks->block_virt_addr +
834 (rxd_size[nic->rxd_mode] * l);
835 rx_blocks->rxds[l].dma_addr =
836 rx_blocks->block_dma_addr +
837 (rxd_size[nic->rxd_mode] * l);
838 }
1da177e4
LT		 839 }
840 /* Interlinking all Rx Blocks */
841 for (j = 0; j < blk_cnt; j++) {
13d866a9
JP		 842 int next = (j + 1) % blk_cnt;
843 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
844 tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
845 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
846 tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
1da177e4 847
d44570e4 848 pre_rxd_blk = (struct RxD_block *)tmp_v_addr;
1da177e4 849 pre_rxd_blk->reserved_2_pNext_RxD_block =
d44570e4 850 (unsigned long)tmp_v_addr_next;
1da177e4 851 pre_rxd_blk->pNext_RxD_Blk_physical =
d44570e4 852 (u64)tmp_p_addr_next;
1da177e4
LT		 853 }
854 }
6d517a27 855 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 856 /*
857 * Allocation of Storages for buffer addresses in 2BUFF mode
858 * and the buffers as well.
859 */
860 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 861 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
862 struct ring_info *ring = &mac_control->rings[i];
863
864 blk_cnt = rx_cfg->num_rxd /
d44570e4 865 (rxd_count[nic->rxd_mode] + 1);
4f870320
JP		 866 size = sizeof(struct buffAdd *) * blk_cnt;
867 ring->ba = kmalloc(size, GFP_KERNEL);
13d866a9 868 if (!ring->ba)
1da177e4 869 return -ENOMEM;
4f870320 870 mem_allocated += size;
da6971d8
AR		 871 for (j = 0; j < blk_cnt; j++) {
872 int k = 0;
4f870320
JP		 873
874 size = sizeof(struct buffAdd) *
875 (rxd_count[nic->rxd_mode] + 1);
876 ring->ba[j] = kmalloc(size, GFP_KERNEL);
13d866a9 877 if (!ring->ba[j])
1da177e4 878 return -ENOMEM;
4f870320 879 mem_allocated += size;
da6971d8 880 while (k != rxd_count[nic->rxd_mode]) {
13d866a9 881 ba = &ring->ba[j][k];
4f870320
JP		 882 size = BUF0_LEN + ALIGN_SIZE;
883 ba->ba_0_org = kmalloc(size, GFP_KERNEL);
da6971d8
AR		 884 if (!ba->ba_0_org)
885 return -ENOMEM;
4f870320 886 mem_allocated += size;
da6971d8
AR		 887 tmp = (unsigned long)ba->ba_0_org;
888 tmp += ALIGN_SIZE;
d44570e4
JP		 889 tmp &= ~((unsigned long)ALIGN_SIZE);
890 ba->ba_0 = (void *)tmp;
da6971d8 891
4f870320
JP		 892 size = BUF1_LEN + ALIGN_SIZE;
893 ba->ba_1_org = kmalloc(size, GFP_KERNEL);
da6971d8
AR		 894 if (!ba->ba_1_org)
895 return -ENOMEM;
4f870320 896 mem_allocated += size;
d44570e4 897 tmp = (unsigned long)ba->ba_1_org;
da6971d8 898 tmp += ALIGN_SIZE;
d44570e4
JP		 899 tmp &= ~((unsigned long)ALIGN_SIZE);
900 ba->ba_1 = (void *)tmp;
da6971d8
AR		 901 k++;
902 }
1da177e4
LT		 903 }
904 }
905 }
1da177e4
LT		 906
907 /* Allocation and initialization of Statistics block */
1ee6dd77 908 size = sizeof(struct stat_block);
d44570e4
JP		 909 mac_control->stats_mem =
910 pci_alloc_consistent(nic->pdev, size,
911 &mac_control->stats_mem_phy);
1da177e4
LT		 912
913 if (!mac_control->stats_mem) {
20346722
K		 914 /*
915 * In case of failure, free_shared_mem() is called, which
916 * should free any memory that was alloced till the
1da177e4
LT		 917 * failure happened.
918 */
919 return -ENOMEM;
920 }
491976b2 921 mem_allocated += size;
1da177e4
LT		 922 mac_control->stats_mem_sz = size;
923
924 tmp_v_addr = mac_control->stats_mem;
d44570e4 925 mac_control->stats_info = (struct stat_block *)tmp_v_addr;
1da177e4 926 memset(tmp_v_addr, 0, size);
3a22813a
BL		 927 DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n",
928 dev_name(&nic->pdev->dev), (unsigned long long)tmp_p_addr);
491976b2 929 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
1da177e4
LT		 930 return SUCCESS;
931}
932
20346722
K		 933/**
934 * free_shared_mem - Free the allocated Memory
1da177e4
LT		 935 * @nic: Device private variable.
936 * Description: This function is to free all memory locations allocated by
937 * the init_shared_mem() function and return it to the kernel.
938 */
939
940static void free_shared_mem(struct s2io_nic *nic)
941{
942 int i, j, blk_cnt, size;
943 void *tmp_v_addr;
944 dma_addr_t tmp_p_addr;
1da177e4 945 int lst_size, lst_per_page;
8910b49f 946 struct net_device *dev;
491976b2 947 int page_num = 0;
ffb5df6c
JP		 948 struct config_param *config;
949 struct mac_info *mac_control;
950 struct stat_block *stats;
951 struct swStat *swstats;
1da177e4
LT		 952
953 if (!nic)
954 return;
955
8910b49f
MG		 956 dev = nic->dev;
957
1da177e4 958 config = &nic->config;
ffb5df6c
JP		 959 mac_control = &nic->mac_control;
960 stats = mac_control->stats_info;
961 swstats = &stats->sw_stat;
1da177e4 962
d44570e4 963 lst_size = sizeof(struct TxD) * config->max_txds;
1da177e4
LT		 964 lst_per_page = PAGE_SIZE / lst_size;
965
966 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 967 struct fifo_info *fifo = &mac_control->fifos[i];
968 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
969
970 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
1da177e4
LT		 971 for (j = 0; j < page_num; j++) {
972 int mem_blks = (j * lst_per_page);
13d866a9
JP		 973 struct list_info_hold *fli;
974
975 if (!fifo->list_info)
6aa20a22 976 return;
13d866a9
JP		 977
978 fli = &fifo->list_info[mem_blks];
979 if (!fli->list_virt_addr)
1da177e4
LT		 980 break;
981 pci_free_consistent(nic->pdev, PAGE_SIZE,
13d866a9
JP		 982 fli->list_virt_addr,
983 fli->list_phy_addr);
ffb5df6c 984 swstats->mem_freed += PAGE_SIZE;
1da177e4 985 }
776bd20f 986 /* If we got a zero DMA address during allocation,
987 * free the page now
988 */
989 if (mac_control->zerodma_virt_addr) {
990 pci_free_consistent(nic->pdev, PAGE_SIZE,
991 mac_control->zerodma_virt_addr,
992 (dma_addr_t)0);
6aa20a22 993 DBG_PRINT(INIT_DBG,
9e39f7c5
JP		 994 "%s: Freeing TxDL with zero DMA address. "
995 "Virtual address %p\n",
996 dev->name, mac_control->zerodma_virt_addr);
ffb5df6c 997 swstats->mem_freed += PAGE_SIZE;
776bd20f 998 }
13d866a9 999 kfree(fifo->list_info);
82c2d023 1000 swstats->mem_freed += tx_cfg->fifo_len *
d44570e4 1001 sizeof(struct list_info_hold);
1da177e4
LT		 1002 }
1003
1da177e4 1004 size = SIZE_OF_BLOCK;
1da177e4 1005 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1006 struct ring_info *ring = &mac_control->rings[i];
1007
1008 blk_cnt = ring->block_count;
1da177e4 1009 for (j = 0; j < blk_cnt; j++) {
13d866a9
JP		 1010 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
1011 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
1da177e4
LT		 1012 if (tmp_v_addr == NULL)
1013 break;
1014 pci_free_consistent(nic->pdev, size,
1015 tmp_v_addr, tmp_p_addr);
ffb5df6c 1016 swstats->mem_freed += size;
13d866a9 1017 kfree(ring->rx_blocks[j].rxds);
ffb5df6c
JP		 1018 swstats->mem_freed += sizeof(struct rxd_info) *
1019 rxd_count[nic->rxd_mode];
1da177e4
LT		 1020 }
1021 }
1022
6d517a27 1023 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 1024 /* Freeing buffer storage addresses in 2BUFF mode. */
1025 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1026 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1027 struct ring_info *ring = &mac_control->rings[i];
1028
1029 blk_cnt = rx_cfg->num_rxd /
1030 (rxd_count[nic->rxd_mode] + 1);
da6971d8
AR		 1031 for (j = 0; j < blk_cnt; j++) {
1032 int k = 0;
13d866a9 1033 if (!ring->ba[j])
da6971d8
AR		 1034 continue;
1035 while (k != rxd_count[nic->rxd_mode]) {
13d866a9 1036 struct buffAdd *ba = &ring->ba[j][k];
da6971d8 1037 kfree(ba->ba_0_org);
ffb5df6c
JP		 1038 swstats->mem_freed +=
1039 BUF0_LEN + ALIGN_SIZE;
da6971d8 1040 kfree(ba->ba_1_org);
ffb5df6c
JP		 1041 swstats->mem_freed +=
1042 BUF1_LEN + ALIGN_SIZE;
da6971d8
AR		 1043 k++;
1044 }
13d866a9 1045 kfree(ring->ba[j]);
ffb5df6c
JP		 1046 swstats->mem_freed += sizeof(struct buffAdd) *
1047 (rxd_count[nic->rxd_mode] + 1);
1da177e4 1048 }
13d866a9 1049 kfree(ring->ba);
ffb5df6c
JP		 1050 swstats->mem_freed += sizeof(struct buffAdd *) *
1051 blk_cnt;
1da177e4 1052 }
1da177e4 1053 }
1da177e4 1054
2fda096d 1055 for (i = 0; i < nic->config.tx_fifo_num; i++) {
13d866a9
JP		 1056 struct fifo_info *fifo = &mac_control->fifos[i];
1057 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1058
1059 if (fifo->ufo_in_band_v) {
ffb5df6c
JP		 1060 swstats->mem_freed += tx_cfg->fifo_len *
1061 sizeof(u64);
13d866a9 1062 kfree(fifo->ufo_in_band_v);
2fda096d
SR		 1063 }
1064 }
1065
1da177e4 1066 if (mac_control->stats_mem) {
ffb5df6c 1067 swstats->mem_freed += mac_control->stats_mem_sz;
1da177e4
LT		 1068 pci_free_consistent(nic->pdev,
1069 mac_control->stats_mem_sz,
1070 mac_control->stats_mem,
1071 mac_control->stats_mem_phy);
491976b2 1072 }
1da177e4
LT		 1073}
1074
541ae68f
K		 1075/**
1076 * s2io_verify_pci_mode -
1077 */
1078
1ee6dd77 1079static int s2io_verify_pci_mode(struct s2io_nic *nic)
541ae68f 1080{
1ee6dd77 1081 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 1082 register u64 val64 = 0;
1083 int mode;
1084
1085 val64 = readq(&bar0->pci_mode);
1086 mode = (u8)GET_PCI_MODE(val64);
1087
d44570e4 1088 if (val64 & PCI_MODE_UNKNOWN_MODE)
541ae68f
K		 1089 return -1; /* Unknown PCI mode */
1090 return mode;
1091}
1092
c92ca04b
AR		 1093#define NEC_VENID 0x1033
1094#define NEC_DEVID 0x0125
1095static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1096{
1097 struct pci_dev *tdev = NULL;
26d36b64
AC		 1098 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1099 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
7ad62dbc 1100 if (tdev->bus == s2io_pdev->bus->parent) {
26d36b64 1101 pci_dev_put(tdev);
c92ca04b 1102 return 1;
7ad62dbc 1103 }
c92ca04b
AR		 1104 }
1105 }
1106 return 0;
1107}
541ae68f 1108
7b32a312 1109static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
541ae68f
K		 1110/**
1111 * s2io_print_pci_mode -
1112 */
1ee6dd77 1113static int s2io_print_pci_mode(struct s2io_nic *nic)
541ae68f 1114{
1ee6dd77 1115 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 1116 register u64 val64 = 0;
1117 int mode;
1118 struct config_param *config = &nic->config;
9e39f7c5 1119 const char *pcimode;
541ae68f
K		 1120
1121 val64 = readq(&bar0->pci_mode);
1122 mode = (u8)GET_PCI_MODE(val64);
1123
d44570e4 1124 if (val64 & PCI_MODE_UNKNOWN_MODE)
541ae68f
K		 1125 return -1; /* Unknown PCI mode */
1126
c92ca04b
AR		 1127 config->bus_speed = bus_speed[mode];
1128
1129 if (s2io_on_nec_bridge(nic->pdev)) {
1130 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
d44570e4 1131 nic->dev->name);
c92ca04b
AR		 1132 return mode;
1133 }
1134
d44570e4
JP		 1135 switch (mode) {
1136 case PCI_MODE_PCI_33:
9e39f7c5 1137 pcimode = "33MHz PCI bus";
d44570e4
JP		 1138 break;
1139 case PCI_MODE_PCI_66:
9e39f7c5 1140 pcimode = "66MHz PCI bus";
d44570e4
JP		 1141 break;
1142 case PCI_MODE_PCIX_M1_66:
9e39f7c5 1143 pcimode = "66MHz PCIX(M1) bus";
d44570e4
JP		 1144 break;
1145 case PCI_MODE_PCIX_M1_100:
9e39f7c5 1146 pcimode = "100MHz PCIX(M1) bus";
d44570e4
JP		 1147 break;
1148 case PCI_MODE_PCIX_M1_133:
9e39f7c5 1149 pcimode = "133MHz PCIX(M1) bus";
d44570e4
JP		 1150 break;
1151 case PCI_MODE_PCIX_M2_66:
9e39f7c5 1152 pcimode = "133MHz PCIX(M2) bus";
d44570e4
JP		 1153 break;
1154 case PCI_MODE_PCIX_M2_100:
9e39f7c5 1155 pcimode = "200MHz PCIX(M2) bus";
d44570e4
JP		 1156 break;
1157 case PCI_MODE_PCIX_M2_133:
9e39f7c5 1158 pcimode = "266MHz PCIX(M2) bus";
d44570e4
JP		 1159 break;
1160 default:
9e39f7c5
JP		 1161 pcimode = "unsupported bus!";
1162 mode = -1;
541ae68f
K		 1163 }
1164
9e39f7c5
JP		 1165 DBG_PRINT(ERR_DBG, "%s: Device is on %d bit %s\n",
1166 nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode);
1167
541ae68f
K		 1168 return mode;
1169}
1170
b7c5678f
RV		 1171/**
1172 * init_tti - Initialization transmit traffic interrupt scheme
1173 * @nic: device private variable
1174 * @link: link status (UP/DOWN) used to enable/disable continuous
1175 * transmit interrupts
1176 * Description: The function configures transmit traffic interrupts
1177 * Return Value: SUCCESS on success and
1178 * '-1' on failure
1179 */
1180
0d66afe7 1181static int init_tti(struct s2io_nic *nic, int link)
b7c5678f
RV		 1182{
1183 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1184 register u64 val64 = 0;
1185 int i;
ffb5df6c 1186 struct config_param *config = &nic->config;
b7c5678f
RV		 1187
1188 for (i = 0; i < config->tx_fifo_num; i++) {
1189 /*
1190 * TTI Initialization. Default Tx timer gets us about
1191 * 250 interrupts per sec. Continuous interrupts are enabled
1192 * by default.
1193 */
1194 if (nic->device_type == XFRAME_II_DEVICE) {
1195 int count = (nic->config.bus_speed * 125)/2;
1196 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1197 } else
1198 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1199
1200 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
d44570e4
JP		 1201 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1202 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1203 TTI_DATA1_MEM_TX_TIMER_AC_EN;
ac731ab6
SH		 1204 if (i == 0)
1205 if (use_continuous_tx_intrs && (link == LINK_UP))
1206 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
b7c5678f
RV		 1207 writeq(val64, &bar0->tti_data1_mem);
1208
ac731ab6
SH		 1209 if (nic->config.intr_type == MSI_X) {
1210 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1211 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1212 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1213 TTI_DATA2_MEM_TX_UFC_D(0x300);
1214 } else {
1215 if ((nic->config.tx_steering_type ==
d44570e4
JP		 1216 TX_DEFAULT_STEERING) &&
1217 (config->tx_fifo_num > 1) &&
1218 (i >= nic->udp_fifo_idx) &&
1219 (i < (nic->udp_fifo_idx +
1220 nic->total_udp_fifos)))
ac731ab6
SH		 1221 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1222 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1223 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1224 TTI_DATA2_MEM_TX_UFC_D(0x120);
1225 else
1226 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1227 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1228 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1229 TTI_DATA2_MEM_TX_UFC_D(0x80);
1230 }
b7c5678f
RV		 1231
1232 writeq(val64, &bar0->tti_data2_mem);
1233
d44570e4
JP		 1234 val64 = TTI_CMD_MEM_WE |
1235 TTI_CMD_MEM_STROBE_NEW_CMD |
1236 TTI_CMD_MEM_OFFSET(i);
b7c5678f
RV		 1237 writeq(val64, &bar0->tti_command_mem);
1238
1239 if (wait_for_cmd_complete(&bar0->tti_command_mem,
d44570e4
JP		 1240 TTI_CMD_MEM_STROBE_NEW_CMD,
1241 S2IO_BIT_RESET) != SUCCESS)
b7c5678f
RV		 1242 return FAILURE;
1243 }
1244
1245 return SUCCESS;
1246}
1247
20346722
K		 1248/**
1249 * init_nic - Initialization of hardware
b7c5678f 1250 * @nic: device private variable
20346722
K		 1251 * Description: The function sequentially configures every block
1252 * of the H/W from their reset values.
1253 * Return Value: SUCCESS on success and
1da177e4
LT		 1254 * '-1' on failure (endian settings incorrect).
1255 */
1256
1257static int init_nic(struct s2io_nic *nic)
1258{
1ee6dd77 1259 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1260 struct net_device *dev = nic->dev;
1261 register u64 val64 = 0;
1262 void __iomem *add;
1263 u32 time;
1264 int i, j;
c92ca04b 1265 int dtx_cnt = 0;
1da177e4 1266 unsigned long long mem_share;
20346722 1267 int mem_size;
ffb5df6c
JP		 1268 struct config_param *config = &nic->config;
1269 struct mac_info *mac_control = &nic->mac_control;
1da177e4 1270
5e25b9dd 1271 /* to set the swapper controle on the card */
d44570e4
JP		 1272 if (s2io_set_swapper(nic)) {
1273 DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
9f74ffde 1274 return -EIO;
1da177e4
LT		 1275 }
1276
541ae68f
K		 1277 /*
1278 * Herc requires EOI to be removed from reset before XGXS, so..
1279 */
1280 if (nic->device_type & XFRAME_II_DEVICE) {
1281 val64 = 0xA500000000ULL;
1282 writeq(val64, &bar0->sw_reset);
1283 msleep(500);
1284 val64 = readq(&bar0->sw_reset);
1285 }
1286
1da177e4
LT		 1287 /* Remove XGXS from reset state */
1288 val64 = 0;
1289 writeq(val64, &bar0->sw_reset);
1da177e4 1290 msleep(500);
20346722 1291 val64 = readq(&bar0->sw_reset);
1da177e4 1292
7962024e
SH		 1293 /* Ensure that it's safe to access registers by checking
1294 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1295 */
1296 if (nic->device_type == XFRAME_II_DEVICE) {
1297 for (i = 0; i < 50; i++) {
1298 val64 = readq(&bar0->adapter_status);
1299 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1300 break;
1301 msleep(10);
1302 }
1303 if (i == 50)
1304 return -ENODEV;
1305 }
1306
1da177e4
LT		 1307 /* Enable Receiving broadcasts */
1308 add = &bar0->mac_cfg;
1309 val64 = readq(&bar0->mac_cfg);
1310 val64 |= MAC_RMAC_BCAST_ENABLE;
1311 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 1312 writel((u32)val64, add);
1da177e4
LT		 1313 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1314 writel((u32) (val64 >> 32), (add + 4));
1315
1316 /* Read registers in all blocks */
1317 val64 = readq(&bar0->mac_int_mask);
1318 val64 = readq(&bar0->mc_int_mask);
1319 val64 = readq(&bar0->xgxs_int_mask);
1320
1321 /* Set MTU */
1322 val64 = dev->mtu;
1323 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1324
541ae68f
K		 1325 if (nic->device_type & XFRAME_II_DEVICE) {
1326 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
303bcb4b 1327 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1da177e4 1328 &bar0->dtx_control, UF);
541ae68f
K		 1329 if (dtx_cnt & 0x1)
1330 msleep(1); /* Necessary!! */
1da177e4
LT		 1331 dtx_cnt++;
1332 }
541ae68f 1333 } else {
c92ca04b
AR		 1334 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1335 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1336 &bar0->dtx_control, UF);
1337 val64 = readq(&bar0->dtx_control);
1338 dtx_cnt++;
1da177e4
LT		 1339 }
1340 }
1341
1342 /* Tx DMA Initialization */
1343 val64 = 0;
1344 writeq(val64, &bar0->tx_fifo_partition_0);
1345 writeq(val64, &bar0->tx_fifo_partition_1);
1346 writeq(val64, &bar0->tx_fifo_partition_2);
1347 writeq(val64, &bar0->tx_fifo_partition_3);
1348
1da177e4 1349 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 1350 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1351
1352 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1353 vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1da177e4
LT		 1354
1355 if (i == (config->tx_fifo_num - 1)) {
1356 if (i % 2 == 0)
1357 i++;
1358 }
1359
1360 switch (i) {
1361 case 1:
1362 writeq(val64, &bar0->tx_fifo_partition_0);
1363 val64 = 0;
b7c5678f 1364 j = 0;
1da177e4
LT		 1365 break;
1366 case 3:
1367 writeq(val64, &bar0->tx_fifo_partition_1);
1368 val64 = 0;
b7c5678f 1369 j = 0;
1da177e4
LT		 1370 break;
1371 case 5:
1372 writeq(val64, &bar0->tx_fifo_partition_2);
1373 val64 = 0;
b7c5678f 1374 j = 0;
1da177e4
LT		 1375 break;
1376 case 7:
1377 writeq(val64, &bar0->tx_fifo_partition_3);
b7c5678f
RV		 1378 val64 = 0;
1379 j = 0;
1380 break;
1381 default:
1382 j++;
1da177e4
LT		 1383 break;
1384 }
1385 }
1386
5e25b9dd
K		 1387 /*
1388 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1389 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1390 */
d44570e4 1391 if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
5e25b9dd
K		 1392 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1393
1da177e4
LT		 1394 val64 = readq(&bar0->tx_fifo_partition_0);
1395 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
d44570e4 1396 &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1da177e4 1397
20346722
K		 1398 /*
1399 * Initialization of Tx_PA_CONFIG register to ignore packet
1da177e4
LT		 1400 * integrity checking.
1401 */
1402 val64 = readq(&bar0->tx_pa_cfg);
d44570e4
JP		 1403 val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1404 TX_PA_CFG_IGNORE_SNAP_OUI |
1405 TX_PA_CFG_IGNORE_LLC_CTRL |
1406 TX_PA_CFG_IGNORE_L2_ERR;
1da177e4
LT		 1407 writeq(val64, &bar0->tx_pa_cfg);
1408
1409 /* Rx DMA intialization. */
1410 val64 = 0;
1411 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1412 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1413
1414 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1da177e4
LT		 1415 }
1416 writeq(val64, &bar0->rx_queue_priority);
1417
20346722
K		 1418 /*
1419 * Allocating equal share of memory to all the
1da177e4
LT		 1420 * configured Rings.
1421 */
1422 val64 = 0;
541ae68f
K		 1423 if (nic->device_type & XFRAME_II_DEVICE)
1424 mem_size = 32;
1425 else
1426 mem_size = 64;
1427
1da177e4
LT		 1428 for (i = 0; i < config->rx_ring_num; i++) {
1429 switch (i) {
1430 case 0:
20346722
K		 1431 mem_share = (mem_size / config->rx_ring_num +
1432 mem_size % config->rx_ring_num);
1da177e4
LT		 1433 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1434 continue;
1435 case 1:
20346722 1436 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1437 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1438 continue;
1439 case 2:
20346722 1440 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1441 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1442 continue;
1443 case 3:
20346722 1444 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1445 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1446 continue;
1447 case 4:
20346722 1448 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1449 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1450 continue;
1451 case 5:
20346722 1452 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1453 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1454 continue;
1455 case 6:
20346722 1456 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1457 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1458 continue;
1459 case 7:
20346722 1460 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1461 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1462 continue;
1463 }
1464 }
1465 writeq(val64, &bar0->rx_queue_cfg);
1466
20346722 1467 /*
5e25b9dd 1468 * Filling Tx round robin registers
b7c5678f 1469 * as per the number of FIFOs for equal scheduling priority
1da177e4 1470 */
5e25b9dd
K		 1471 switch (config->tx_fifo_num) {
1472 case 1:
b7c5678f 1473 val64 = 0x0;
5e25b9dd
K		 1474 writeq(val64, &bar0->tx_w_round_robin_0);
1475 writeq(val64, &bar0->tx_w_round_robin_1);
1476 writeq(val64, &bar0->tx_w_round_robin_2);
1477 writeq(val64, &bar0->tx_w_round_robin_3);
1478 writeq(val64, &bar0->tx_w_round_robin_4);
1479 break;
1480 case 2:
b7c5678f 1481 val64 = 0x0001000100010001ULL;
5e25b9dd 1482 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1483 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1484 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1485 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1486 val64 = 0x0001000100000000ULL;
5e25b9dd
K		 1487 writeq(val64, &bar0->tx_w_round_robin_4);
1488 break;
1489 case 3:
b7c5678f 1490 val64 = 0x0001020001020001ULL;
5e25b9dd 1491 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1492 val64 = 0x0200010200010200ULL;
5e25b9dd 1493 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1494 val64 = 0x0102000102000102ULL;
5e25b9dd 1495 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1496 val64 = 0x0001020001020001ULL;
5e25b9dd 1497 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1498 val64 = 0x0200010200000000ULL;
5e25b9dd
K		 1499 writeq(val64, &bar0->tx_w_round_robin_4);
1500 break;
1501 case 4:
b7c5678f 1502 val64 = 0x0001020300010203ULL;
5e25b9dd 1503 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1504 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1505 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1506 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1507 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1508 writeq(val64, &bar0->tx_w_round_robin_4);
1509 break;
1510 case 5:
b7c5678f 1511 val64 = 0x0001020304000102ULL;
5e25b9dd 1512 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1513 val64 = 0x0304000102030400ULL;
5e25b9dd 1514 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1515 val64 = 0x0102030400010203ULL;
5e25b9dd 1516 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1517 val64 = 0x0400010203040001ULL;
5e25b9dd 1518 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1519 val64 = 0x0203040000000000ULL;
5e25b9dd
K		 1520 writeq(val64, &bar0->tx_w_round_robin_4);
1521 break;
1522 case 6:
b7c5678f 1523 val64 = 0x0001020304050001ULL;
5e25b9dd 1524 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1525 val64 = 0x0203040500010203ULL;
5e25b9dd 1526 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1527 val64 = 0x0405000102030405ULL;
5e25b9dd 1528 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1529 val64 = 0x0001020304050001ULL;
5e25b9dd 1530 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1531 val64 = 0x0203040500000000ULL;
5e25b9dd
K		 1532 writeq(val64, &bar0->tx_w_round_robin_4);
1533 break;
1534 case 7:
b7c5678f 1535 val64 = 0x0001020304050600ULL;
5e25b9dd 1536 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1537 val64 = 0x0102030405060001ULL;
5e25b9dd 1538 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1539 val64 = 0x0203040506000102ULL;
5e25b9dd 1540 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1541 val64 = 0x0304050600010203ULL;
5e25b9dd 1542 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1543 val64 = 0x0405060000000000ULL;
5e25b9dd
K		 1544 writeq(val64, &bar0->tx_w_round_robin_4);
1545 break;
1546 case 8:
b7c5678f 1547 val64 = 0x0001020304050607ULL;
5e25b9dd 1548 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1549 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1550 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1551 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1552 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1553 writeq(val64, &bar0->tx_w_round_robin_4);
1554 break;
1555 }
1556
b41477f3 1557 /* Enable all configured Tx FIFO partitions */
5d3213cc
AR		 1558 val64 = readq(&bar0->tx_fifo_partition_0);
1559 val64 |= (TX_FIFO_PARTITION_EN);
1560 writeq(val64, &bar0->tx_fifo_partition_0);
1561
5e25b9dd 1562 /* Filling the Rx round robin registers as per the
0425b46a
SH		 1563 * number of Rings and steering based on QoS with
1564 * equal priority.
1565 */
5e25b9dd
K		 1566 switch (config->rx_ring_num) {
1567 case 1:
0425b46a
SH		 1568 val64 = 0x0;
1569 writeq(val64, &bar0->rx_w_round_robin_0);
1570 writeq(val64, &bar0->rx_w_round_robin_1);
1571 writeq(val64, &bar0->rx_w_round_robin_2);
1572 writeq(val64, &bar0->rx_w_round_robin_3);
1573 writeq(val64, &bar0->rx_w_round_robin_4);
1574
5e25b9dd
K		 1575 val64 = 0x8080808080808080ULL;
1576 writeq(val64, &bar0->rts_qos_steering);
1577 break;
1578 case 2:
0425b46a 1579 val64 = 0x0001000100010001ULL;
5e25b9dd 1580 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1581 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1582 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1583 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1584 val64 = 0x0001000100000000ULL;
5e25b9dd
K		 1585 writeq(val64, &bar0->rx_w_round_robin_4);
1586
1587 val64 = 0x8080808040404040ULL;
1588 writeq(val64, &bar0->rts_qos_steering);
1589 break;
1590 case 3:
0425b46a 1591 val64 = 0x0001020001020001ULL;
5e25b9dd 1592 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1593 val64 = 0x0200010200010200ULL;
5e25b9dd 1594 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1595 val64 = 0x0102000102000102ULL;
5e25b9dd 1596 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1597 val64 = 0x0001020001020001ULL;
5e25b9dd 1598 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1599 val64 = 0x0200010200000000ULL;
5e25b9dd
K		 1600 writeq(val64, &bar0->rx_w_round_robin_4);
1601
1602 val64 = 0x8080804040402020ULL;
1603 writeq(val64, &bar0->rts_qos_steering);
1604 break;
1605 case 4:
0425b46a 1606 val64 = 0x0001020300010203ULL;
5e25b9dd 1607 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1608 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1609 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1610 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1611 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1612 writeq(val64, &bar0->rx_w_round_robin_4);
1613
1614 val64 = 0x8080404020201010ULL;
1615 writeq(val64, &bar0->rts_qos_steering);
1616 break;
1617 case 5:
0425b46a 1618 val64 = 0x0001020304000102ULL;
5e25b9dd 1619 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1620 val64 = 0x0304000102030400ULL;
5e25b9dd 1621 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1622 val64 = 0x0102030400010203ULL;
5e25b9dd 1623 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1624 val64 = 0x0400010203040001ULL;
5e25b9dd 1625 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1626 val64 = 0x0203040000000000ULL;
5e25b9dd
K		 1627 writeq(val64, &bar0->rx_w_round_robin_4);
1628
1629 val64 = 0x8080404020201008ULL;
1630 writeq(val64, &bar0->rts_qos_steering);
1631 break;
1632 case 6:
0425b46a 1633 val64 = 0x0001020304050001ULL;
5e25b9dd 1634 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1635 val64 = 0x0203040500010203ULL;
5e25b9dd 1636 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1637 val64 = 0x0405000102030405ULL;
5e25b9dd 1638 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1639 val64 = 0x0001020304050001ULL;
5e25b9dd 1640 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1641 val64 = 0x0203040500000000ULL;
5e25b9dd
K		 1642 writeq(val64, &bar0->rx_w_round_robin_4);
1643
1644 val64 = 0x8080404020100804ULL;
1645 writeq(val64, &bar0->rts_qos_steering);
1646 break;
1647 case 7:
0425b46a 1648 val64 = 0x0001020304050600ULL;
5e25b9dd 1649 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1650 val64 = 0x0102030405060001ULL;
5e25b9dd 1651 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1652 val64 = 0x0203040506000102ULL;
5e25b9dd 1653 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1654 val64 = 0x0304050600010203ULL;
5e25b9dd 1655 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1656 val64 = 0x0405060000000000ULL;
5e25b9dd
K		 1657 writeq(val64, &bar0->rx_w_round_robin_4);
1658
1659 val64 = 0x8080402010080402ULL;
1660 writeq(val64, &bar0->rts_qos_steering);
1661 break;
1662 case 8:
0425b46a 1663 val64 = 0x0001020304050607ULL;
5e25b9dd 1664 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1665 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1666 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1667 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1668 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1669 writeq(val64, &bar0->rx_w_round_robin_4);
1670
1671 val64 = 0x8040201008040201ULL;
1672 writeq(val64, &bar0->rts_qos_steering);
1673 break;
1674 }
1da177e4
LT		 1675
1676 /* UDP Fix */
1677 val64 = 0;
20346722 1678 for (i = 0; i < 8; i++)
1da177e4
LT		 1679 writeq(val64, &bar0->rts_frm_len_n[i]);
1680
5e25b9dd
K		 1681 /* Set the default rts frame length for the rings configured */
1682 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1683 for (i = 0 ; i < config->rx_ring_num ; i++)
1684 writeq(val64, &bar0->rts_frm_len_n[i]);
1685
1686 /* Set the frame length for the configured rings
1687 * desired by the user
1688 */
1689 for (i = 0; i < config->rx_ring_num; i++) {
1690 /* If rts_frm_len[i] == 0 then it is assumed that user not
1691 * specified frame length steering.
1692 * If the user provides the frame length then program
1693 * the rts_frm_len register for those values or else
1694 * leave it as it is.
1695 */
1696 if (rts_frm_len[i] != 0) {
1697 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
d44570e4 1698 &bar0->rts_frm_len_n[i]);
5e25b9dd
K		 1699 }
1700 }
8a4bdbaa 1701
9fc93a41
SS		 1702 /* Disable differentiated services steering logic */
1703 for (i = 0; i < 64; i++) {
1704 if (rts_ds_steer(nic, i, 0) == FAILURE) {
9e39f7c5
JP		 1705 DBG_PRINT(ERR_DBG,
1706 "%s: rts_ds_steer failed on codepoint %d\n",
1707 dev->name, i);
9f74ffde 1708 return -ENODEV;
9fc93a41
SS		 1709 }
1710 }
1711
20346722 1712 /* Program statistics memory */
1da177e4 1713 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1da177e4 1714
541ae68f
K		 1715 if (nic->device_type == XFRAME_II_DEVICE) {
1716 val64 = STAT_BC(0x320);
1717 writeq(val64, &bar0->stat_byte_cnt);
1718 }
1719
20346722 1720 /*
1da177e4
LT		 1721 * Initializing the sampling rate for the device to calculate the
1722 * bandwidth utilization.
1723 */
1724 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
d44570e4 1725 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1da177e4
LT		 1726 writeq(val64, &bar0->mac_link_util);
1727
20346722
K		 1728 /*
1729 * Initializing the Transmit and Receive Traffic Interrupt
1da177e4
LT		 1730 * Scheme.
1731 */
1da177e4 1732
b7c5678f
RV		 1733 /* Initialize TTI */
1734 if (SUCCESS != init_tti(nic, nic->last_link_state))
1735 return -ENODEV;
1da177e4 1736
8a4bdbaa
SS		 1737 /* RTI Initialization */
1738 if (nic->device_type == XFRAME_II_DEVICE) {
541ae68f 1739 /*
8a4bdbaa
SS		 1740 * Programmed to generate Apprx 500 Intrs per
1741 * second
1742 */
1743 int count = (nic->config.bus_speed * 125)/4;
1744 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1745 } else
1746 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1747 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
d44570e4
JP		 1748 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1749 RTI_DATA1_MEM_RX_URNG_C(0x30) |
1750 RTI_DATA1_MEM_RX_TIMER_AC_EN;
8a4bdbaa
SS		 1751
1752 writeq(val64, &bar0->rti_data1_mem);
1753
1754 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1755 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1756 if (nic->config.intr_type == MSI_X)
d44570e4
JP		 1757 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1758 RTI_DATA2_MEM_RX_UFC_D(0x40));
8a4bdbaa 1759 else
d44570e4
JP		 1760 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1761 RTI_DATA2_MEM_RX_UFC_D(0x80));
8a4bdbaa 1762 writeq(val64, &bar0->rti_data2_mem);
1da177e4 1763
8a4bdbaa 1764 for (i = 0; i < config->rx_ring_num; i++) {
d44570e4
JP		 1765 val64 = RTI_CMD_MEM_WE |
1766 RTI_CMD_MEM_STROBE_NEW_CMD |
1767 RTI_CMD_MEM_OFFSET(i);
8a4bdbaa 1768 writeq(val64, &bar0->rti_command_mem);
1da177e4 1769
8a4bdbaa
SS		 1770 /*
1771 * Once the operation completes, the Strobe bit of the
1772 * command register will be reset. We poll for this
1773 * particular condition. We wait for a maximum of 500ms
1774 * for the operation to complete, if it's not complete
1775 * by then we return error.
1776 */
1777 time = 0;
f957bcf0 1778 while (true) {
8a4bdbaa
SS		 1779 val64 = readq(&bar0->rti_command_mem);
1780 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1781 break;
b6e3f982 1782
8a4bdbaa 1783 if (time > 10) {
9e39f7c5 1784 DBG_PRINT(ERR_DBG, "%s: RTI init failed\n",
8a4bdbaa 1785 dev->name);
9f74ffde 1786 return -ENODEV;
b6e3f982 1787 }
8a4bdbaa
SS		 1788 time++;
1789 msleep(50);
1da177e4 1790 }
1da177e4
LT		 1791 }
1792
20346722
K		 1793 /*
1794 * Initializing proper values as Pause threshold into all
1da177e4
LT		 1795 * the 8 Queues on Rx side.
1796 */
1797 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1798 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1799
1800 /* Disable RMAC PAD STRIPPING */
509a2671 1801 add = &bar0->mac_cfg;
1da177e4
LT		 1802 val64 = readq(&bar0->mac_cfg);
1803 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1804 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1805 writel((u32) (val64), add);
1806 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1807 writel((u32) (val64 >> 32), (add + 4));
1808 val64 = readq(&bar0->mac_cfg);
1809
7d3d0439
RA		 1810 /* Enable FCS stripping by adapter */
1811 add = &bar0->mac_cfg;
1812 val64 = readq(&bar0->mac_cfg);
1813 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1814 if (nic->device_type == XFRAME_II_DEVICE)
1815 writeq(val64, &bar0->mac_cfg);
1816 else {
1817 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1818 writel((u32) (val64), add);
1819 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1820 writel((u32) (val64 >> 32), (add + 4));
1821 }
1822
20346722
K		 1823 /*
1824 * Set the time value to be inserted in the pause frame
1da177e4
LT		 1825 * generated by xena.
1826 */
1827 val64 = readq(&bar0->rmac_pause_cfg);
1828 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1829 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1830 writeq(val64, &bar0->rmac_pause_cfg);
1831
20346722 1832 /*
1da177e4
LT		 1833 * Set the Threshold Limit for Generating the pause frame
1834 * If the amount of data in any Queue exceeds ratio of
1835 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1836 * pause frame is generated
1837 */
1838 val64 = 0;
1839 for (i = 0; i < 4; i++) {
d44570e4
JP		 1840 val64 |= (((u64)0xFF00 |
1841 nic->mac_control.mc_pause_threshold_q0q3)
1842 << (i * 2 * 8));
1da177e4
LT		 1843 }
1844 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1845
1846 val64 = 0;
1847 for (i = 0; i < 4; i++) {
d44570e4
JP		 1848 val64 |= (((u64)0xFF00 |
1849 nic->mac_control.mc_pause_threshold_q4q7)
1850 << (i * 2 * 8));
1da177e4
LT		 1851 }
1852 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1853
20346722
K		 1854 /*
1855 * TxDMA will stop Read request if the number of read split has
1da177e4
LT		 1856 * exceeded the limit pointed by shared_splits
1857 */
1858 val64 = readq(&bar0->pic_control);
1859 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1860 writeq(val64, &bar0->pic_control);
1861
863c11a9
AR		 1862 if (nic->config.bus_speed == 266) {
1863 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1864 writeq(0x0, &bar0->read_retry_delay);
1865 writeq(0x0, &bar0->write_retry_delay);
1866 }
1867
541ae68f
K		 1868 /*
1869 * Programming the Herc to split every write transaction
1870 * that does not start on an ADB to reduce disconnects.
1871 */
1872 if (nic->device_type == XFRAME_II_DEVICE) {
19a60522
SS		 1873 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1874 MISC_LINK_STABILITY_PRD(3);
863c11a9
AR		 1875 writeq(val64, &bar0->misc_control);
1876 val64 = readq(&bar0->pic_control2);
b7b5a128 1877 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
863c11a9 1878 writeq(val64, &bar0->pic_control2);
541ae68f 1879 }
c92ca04b
AR		 1880 if (strstr(nic->product_name, "CX4")) {
1881 val64 = TMAC_AVG_IPG(0x17);
1882 writeq(val64, &bar0->tmac_avg_ipg);
a371a07d
K		 1883 }
1884
1da177e4
LT		 1885 return SUCCESS;
1886}
a371a07d
K		 1887#define LINK_UP_DOWN_INTERRUPT 1
1888#define MAC_RMAC_ERR_TIMER 2
1889
1ee6dd77 1890static int s2io_link_fault_indication(struct s2io_nic *nic)
a371a07d
K		 1891{
1892 if (nic->device_type == XFRAME_II_DEVICE)
1893 return LINK_UP_DOWN_INTERRUPT;
1894 else
1895 return MAC_RMAC_ERR_TIMER;
1896}
8116f3cf 1897
9caab458
SS		 1898/**
1899 * do_s2io_write_bits - update alarm bits in alarm register
1900 * @value: alarm bits
1901 * @flag: interrupt status
1902 * @addr: address value
1903 * Description: update alarm bits in alarm register
1904 * Return Value:
1905 * NONE.
1906 */
1907static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1908{
1909 u64 temp64;
1910
1911 temp64 = readq(addr);
1912
d44570e4
JP		 1913 if (flag == ENABLE_INTRS)
1914 temp64 &= ~((u64)value);
9caab458 1915 else
d44570e4 1916 temp64 |= ((u64)value);
9caab458
SS		 1917 writeq(temp64, addr);
1918}
1da177e4 1919
43b7c451 1920static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
9caab458
SS		 1921{
1922 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1923 register u64 gen_int_mask = 0;
01e16faa 1924 u64 interruptible;
9caab458 1925
01e16faa 1926 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
9caab458 1927 if (mask & TX_DMA_INTR) {
9caab458
SS		 1928 gen_int_mask |= TXDMA_INT_M;
1929
1930 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
d44570e4
JP		 1931 TXDMA_PCC_INT | TXDMA_TTI_INT |
1932 TXDMA_LSO_INT | TXDMA_TPA_INT |
1933 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
9caab458
SS		 1934
1935 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
d44570e4
JP		 1936 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1937 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1938 &bar0->pfc_err_mask);
9caab458
SS		 1939
1940 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
d44570e4
JP		 1941 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1942 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
9caab458
SS		 1943
1944 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
d44570e4
JP		 1945 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1946 PCC_N_SERR | PCC_6_COF_OV_ERR |
1947 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1948 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1949 PCC_TXB_ECC_SG_ERR,
1950 flag, &bar0->pcc_err_mask);
9caab458
SS		 1951
1952 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
d44570e4 1953 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
9caab458
SS		 1954
1955 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
d44570e4
JP		 1956 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1957 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1958 flag, &bar0->lso_err_mask);
9caab458
SS		 1959
1960 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
d44570e4 1961 flag, &bar0->tpa_err_mask);
9caab458
SS		 1962
1963 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
9caab458
SS		 1964 }
1965
1966 if (mask & TX_MAC_INTR) {
1967 gen_int_mask |= TXMAC_INT_M;
1968 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
d44570e4 1969 &bar0->mac_int_mask);
9caab458 1970 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
d44570e4
JP		 1971 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1972 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1973 flag, &bar0->mac_tmac_err_mask);
9caab458
SS		 1974 }
1975
1976 if (mask & TX_XGXS_INTR) {
1977 gen_int_mask |= TXXGXS_INT_M;
1978 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
d44570e4 1979 &bar0->xgxs_int_mask);
9caab458 1980 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
d44570e4
JP		 1981 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1982 flag, &bar0->xgxs_txgxs_err_mask);
9caab458
SS		 1983 }
1984
1985 if (mask & RX_DMA_INTR) {
1986 gen_int_mask |= RXDMA_INT_M;
1987 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
d44570e4
JP		 1988 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1989 flag, &bar0->rxdma_int_mask);
9caab458 1990 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
d44570e4
JP		 1991 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1992 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1993 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
9caab458 1994 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
d44570e4
JP		 1995 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1996 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1997 &bar0->prc_pcix_err_mask);
9caab458 1998 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
d44570e4
JP		 1999 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
2000 &bar0->rpa_err_mask);
9caab458 2001 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
d44570e4
JP		 2002 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
2003 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
2004 RDA_FRM_ECC_SG_ERR |
2005 RDA_MISC_ERR|RDA_PCIX_ERR,
2006 flag, &bar0->rda_err_mask);
9caab458 2007 do_s2io_write_bits(RTI_SM_ERR_ALARM |
d44570e4
JP		 2008 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2009 flag, &bar0->rti_err_mask);
9caab458
SS		 2010 }
2011
2012 if (mask & RX_MAC_INTR) {
2013 gen_int_mask |= RXMAC_INT_M;
2014 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
d44570e4
JP		 2015 &bar0->mac_int_mask);
2016 interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2017 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2018 RMAC_DOUBLE_ECC_ERR);
01e16faa
SH		 2019 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2020 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2021 do_s2io_write_bits(interruptible,
d44570e4 2022 flag, &bar0->mac_rmac_err_mask);
9caab458
SS		 2023 }
2024
d44570e4 2025 if (mask & RX_XGXS_INTR) {
9caab458
SS		 2026 gen_int_mask |= RXXGXS_INT_M;
2027 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
d44570e4 2028 &bar0->xgxs_int_mask);
9caab458 2029 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
d44570e4 2030 &bar0->xgxs_rxgxs_err_mask);
9caab458
SS		 2031 }
2032
2033 if (mask & MC_INTR) {
2034 gen_int_mask |= MC_INT_M;
d44570e4
JP		 2035 do_s2io_write_bits(MC_INT_MASK_MC_INT,
2036 flag, &bar0->mc_int_mask);
9caab458 2037 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
d44570e4
JP		 2038 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2039 &bar0->mc_err_mask);
9caab458
SS		 2040 }
2041 nic->general_int_mask = gen_int_mask;
2042
2043 /* Remove this line when alarm interrupts are enabled */
2044 nic->general_int_mask = 0;
2045}
d44570e4 2046
20346722
K		 2047/**
2048 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1da177e4
LT		 2049 * @nic: device private variable,
2050 * @mask: A mask indicating which Intr block must be modified and,
2051 * @flag: A flag indicating whether to enable or disable the Intrs.
2052 * Description: This function will either disable or enable the interrupts
20346722
K		 2053 * depending on the flag argument. The mask argument can be used to
2054 * enable/disable any Intr block.
1da177e4
LT		 2055 * Return Value: NONE.
2056 */
2057
2058static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2059{
1ee6dd77 2060 struct XENA_dev_config __iomem *bar0 = nic->bar0;
9caab458
SS		 2061 register u64 temp64 = 0, intr_mask = 0;
2062
2063 intr_mask = nic->general_int_mask;
1da177e4
LT		 2064
2065 /* Top level interrupt classification */
2066 /* PIC Interrupts */
9caab458 2067 if (mask & TX_PIC_INTR) {
1da177e4 2068 /* Enable PIC Intrs in the general intr mask register */
9caab458 2069 intr_mask |= TXPIC_INT_M;
1da177e4 2070 if (flag == ENABLE_INTRS) {
20346722 2071 /*
a371a07d 2072 * If Hercules adapter enable GPIO otherwise
b41477f3 2073 * disable all PCIX, Flash, MDIO, IIC and GPIO
20346722
K		 2074 * interrupts for now.
2075 * TODO
1da177e4 2076 */
a371a07d 2077 if (s2io_link_fault_indication(nic) ==
d44570e4 2078 LINK_UP_DOWN_INTERRUPT) {
9caab458 2079 do_s2io_write_bits(PIC_INT_GPIO, flag,
d44570e4 2080 &bar0->pic_int_mask);
9caab458 2081 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
d44570e4 2082 &bar0->gpio_int_mask);
9caab458 2083 } else
a371a07d 2084 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4 2085 } else if (flag == DISABLE_INTRS) {
20346722
K		 2086 /*
2087 * Disable PIC Intrs in the general
2088 * intr mask register
1da177e4
LT		 2089 */
2090 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4
LT		 2091 }
2092 }
2093
1da177e4
LT		 2094 /* Tx traffic interrupts */
2095 if (mask & TX_TRAFFIC_INTR) {
9caab458 2096 intr_mask |= TXTRAFFIC_INT_M;
1da177e4 2097 if (flag == ENABLE_INTRS) {
20346722 2098 /*
1da177e4 2099 * Enable all the Tx side interrupts
20346722 2100 * writing 0 Enables all 64 TX interrupt levels
1da177e4
LT		 2101 */
2102 writeq(0x0, &bar0->tx_traffic_mask);
2103 } else if (flag == DISABLE_INTRS) {
20346722
K		 2104 /*
2105 * Disable Tx Traffic Intrs in the general intr mask
1da177e4
LT		 2106 * register.
2107 */
2108 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1da177e4
LT		 2109 }
2110 }
2111
2112 /* Rx traffic interrupts */
2113 if (mask & RX_TRAFFIC_INTR) {
9caab458 2114 intr_mask |= RXTRAFFIC_INT_M;
1da177e4 2115 if (flag == ENABLE_INTRS) {
1da177e4
LT		 2116 /* writing 0 Enables all 8 RX interrupt levels */
2117 writeq(0x0, &bar0->rx_traffic_mask);
2118 } else if (flag == DISABLE_INTRS) {
20346722
K		 2119 /*
2120 * Disable Rx Traffic Intrs in the general intr mask
1da177e4
LT		 2121 * register.
2122 */
2123 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1da177e4
LT		 2124 }
2125 }
9caab458
SS		 2126
2127 temp64 = readq(&bar0->general_int_mask);
2128 if (flag == ENABLE_INTRS)
d44570e4 2129 temp64 &= ~((u64)intr_mask);
9caab458
SS		 2130 else
2131 temp64 = DISABLE_ALL_INTRS;
2132 writeq(temp64, &bar0->general_int_mask);
2133
2134 nic->general_int_mask = readq(&bar0->general_int_mask);
1da177e4
LT		 2135}
2136
19a60522
SS		 2137/**
2138 * verify_pcc_quiescent- Checks for PCC quiescent state
2139 * Return: 1 If PCC is quiescence
2140 * 0 If PCC is not quiescence
2141 */
1ee6dd77 2142static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
20346722 2143{
19a60522 2144 int ret = 0, herc;
1ee6dd77 2145 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522 2146 u64 val64 = readq(&bar0->adapter_status);
8a4bdbaa 2147
19a60522 2148 herc = (sp->device_type == XFRAME_II_DEVICE);
20346722 2149
f957bcf0 2150 if (flag == false) {
44c10138 2151 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
19a60522 2152 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2153 ret = 1;
19a60522
SS		 2154 } else {
2155 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2156 ret = 1;
20346722
K		 2157 }
2158 } else {
44c10138 2159 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
5e25b9dd 2160 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
19a60522 2161 ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2162 ret = 1;
5e25b9dd
K		 2163 } else {
2164 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
19a60522 2165 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2166 ret = 1;
20346722
K		 2167 }
2168 }
2169
2170 return ret;
2171}
2172/**
2173 * verify_xena_quiescence - Checks whether the H/W is ready
1da177e4 2174 * Description: Returns whether the H/W is ready to go or not. Depending
20346722 2175 * on whether adapter enable bit was written or not the comparison
1da177e4
LT		 2176 * differs and the calling function passes the input argument flag to
2177 * indicate this.
20346722 2178 * Return: 1 If xena is quiescence
1da177e4
LT		 2179 * 0 If Xena is not quiescence
2180 */
2181
1ee6dd77 2182static int verify_xena_quiescence(struct s2io_nic *sp)
1da177e4 2183{
19a60522 2184 int mode;
1ee6dd77 2185 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 2186 u64 val64 = readq(&bar0->adapter_status);
2187 mode = s2io_verify_pci_mode(sp);
1da177e4 2188
19a60522 2189 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
9e39f7c5 2190 DBG_PRINT(ERR_DBG, "TDMA is not ready!\n");
19a60522
SS		 2191 return 0;
2192 }
2193 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
9e39f7c5 2194 DBG_PRINT(ERR_DBG, "RDMA is not ready!\n");
19a60522
SS		 2195 return 0;
2196 }
2197 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
9e39f7c5 2198 DBG_PRINT(ERR_DBG, "PFC is not ready!\n");
19a60522
SS		 2199 return 0;
2200 }
2201 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
9e39f7c5 2202 DBG_PRINT(ERR_DBG, "TMAC BUF is not empty!\n");
19a60522
SS		 2203 return 0;
2204 }
2205 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
9e39f7c5 2206 DBG_PRINT(ERR_DBG, "PIC is not QUIESCENT!\n");
19a60522
SS		 2207 return 0;
2208 }
2209 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
9e39f7c5 2210 DBG_PRINT(ERR_DBG, "MC_DRAM is not ready!\n");
19a60522
SS		 2211 return 0;
2212 }
2213 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
9e39f7c5 2214 DBG_PRINT(ERR_DBG, "MC_QUEUES is not ready!\n");
19a60522
SS		 2215 return 0;
2216 }
2217 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
9e39f7c5 2218 DBG_PRINT(ERR_DBG, "M_PLL is not locked!\n");
19a60522 2219 return 0;
1da177e4
LT		 2220 }
2221
19a60522
SS		 2222 /*
2223 * In PCI 33 mode, the P_PLL is not used, and therefore,
2224 * the the P_PLL_LOCK bit in the adapter_status register will
2225 * not be asserted.
2226 */
2227 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
d44570e4
JP		 2228 sp->device_type == XFRAME_II_DEVICE &&
2229 mode != PCI_MODE_PCI_33) {
9e39f7c5 2230 DBG_PRINT(ERR_DBG, "P_PLL is not locked!\n");
19a60522
SS		 2231 return 0;
2232 }
2233 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
d44570e4 2234 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
9e39f7c5 2235 DBG_PRINT(ERR_DBG, "RC_PRC is not QUIESCENT!\n");
19a60522
SS		 2236 return 0;
2237 }
2238 return 1;
1da177e4
LT		 2239}
2240
2241/**
2242 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2243 * @sp: Pointer to device specifc structure
20346722 2244 * Description :
1da177e4
LT		 2245 * New procedure to clear mac address reading problems on Alpha platforms
2246 *
2247 */
2248
d44570e4 2249static void fix_mac_address(struct s2io_nic *sp)
1da177e4 2250{
1ee6dd77 2251 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 2252 u64 val64;
2253 int i = 0;
2254
2255 while (fix_mac[i] != END_SIGN) {
2256 writeq(fix_mac[i++], &bar0->gpio_control);
20346722 2257 udelay(10);
1da177e4
LT		 2258 val64 = readq(&bar0->gpio_control);
2259 }
2260}
2261
2262/**
20346722 2263 * start_nic - Turns the device on
1da177e4 2264 * @nic : device private variable.
20346722
K		 2265 * Description:
2266 * This function actually turns the device on. Before this function is
2267 * called,all Registers are configured from their reset states
2268 * and shared memory is allocated but the NIC is still quiescent. On
1da177e4
LT		 2269 * calling this function, the device interrupts are cleared and the NIC is
2270 * literally switched on by writing into the adapter control register.
20346722 2271 * Return Value:
1da177e4
LT		 2272 * SUCCESS on success and -1 on failure.
2273 */
2274
2275static int start_nic(struct s2io_nic *nic)
2276{
1ee6dd77 2277 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 2278 struct net_device *dev = nic->dev;
2279 register u64 val64 = 0;
20346722 2280 u16 subid, i;
ffb5df6c
JP		 2281 struct config_param *config = &nic->config;
2282 struct mac_info *mac_control = &nic->mac_control;
1da177e4
LT		 2283
2284 /* PRC Initialization and configuration */
2285 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2286 struct ring_info *ring = &mac_control->rings[i];
2287
d44570e4 2288 writeq((u64)ring->rx_blocks[0].block_dma_addr,
1da177e4
LT		 2289 &bar0->prc_rxd0_n[i]);
2290
2291 val64 = readq(&bar0->prc_ctrl_n[i]);
da6971d8
AR		 2292 if (nic->rxd_mode == RXD_MODE_1)
2293 val64 |= PRC_CTRL_RC_ENABLED;
2294 else
2295 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
863c11a9
AR		 2296 if (nic->device_type == XFRAME_II_DEVICE)
2297 val64 |= PRC_CTRL_GROUP_READS;
2298 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2299 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1da177e4
LT		 2300 writeq(val64, &bar0->prc_ctrl_n[i]);
2301 }
2302
da6971d8
AR		 2303 if (nic->rxd_mode == RXD_MODE_3B) {
2304 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2305 val64 = readq(&bar0->rx_pa_cfg);
2306 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2307 writeq(val64, &bar0->rx_pa_cfg);
2308 }
1da177e4 2309
926930b2
SS		 2310 if (vlan_tag_strip == 0) {
2311 val64 = readq(&bar0->rx_pa_cfg);
2312 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2313 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 2314 nic->vlan_strip_flag = 0;
926930b2
SS		 2315 }
2316
20346722 2317 /*
1da177e4
LT		 2318 * Enabling MC-RLDRAM. After enabling the device, we timeout
2319 * for around 100ms, which is approximately the time required
2320 * for the device to be ready for operation.
2321 */
2322 val64 = readq(&bar0->mc_rldram_mrs);
2323 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2324 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2325 val64 = readq(&bar0->mc_rldram_mrs);
2326
20346722 2327 msleep(100); /* Delay by around 100 ms. */
1da177e4
LT		 2328
2329 /* Enabling ECC Protection. */
2330 val64 = readq(&bar0->adapter_control);
2331 val64 &= ~ADAPTER_ECC_EN;
2332 writeq(val64, &bar0->adapter_control);
2333
20346722
K		 2334 /*
2335 * Verify if the device is ready to be enabled, if so enable
1da177e4
LT		 2336 * it.
2337 */
2338 val64 = readq(&bar0->adapter_status);
19a60522 2339 if (!verify_xena_quiescence(nic)) {
9e39f7c5
JP		 2340 DBG_PRINT(ERR_DBG, "%s: device is not ready, "
2341 "Adapter status reads: 0x%llx\n",
2342 dev->name, (unsigned long long)val64);
1da177e4
LT		 2343 return FAILURE;
2344 }
2345
20346722 2346 /*
1da177e4 2347 * With some switches, link might be already up at this point.
20346722
K		 2348 * Because of this weird behavior, when we enable laser,
2349 * we may not get link. We need to handle this. We cannot
2350 * figure out which switch is misbehaving. So we are forced to
2351 * make a global change.
1da177e4
LT		 2352 */
2353
2354 /* Enabling Laser. */
2355 val64 = readq(&bar0->adapter_control);
2356 val64 |= ADAPTER_EOI_TX_ON;
2357 writeq(val64, &bar0->adapter_control);
2358
c92ca04b
AR		 2359 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2360 /*
2361 * Dont see link state interrupts initally on some switches,
2362 * so directly scheduling the link state task here.
2363 */
2364 schedule_work(&nic->set_link_task);
2365 }
1da177e4
LT		 2366 /* SXE-002: Initialize link and activity LED */
2367 subid = nic->pdev->subsystem_device;
541ae68f
K		 2368 if (((subid & 0xFF) >= 0x07) &&
2369 (nic->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 2370 val64 = readq(&bar0->gpio_control);
2371 val64 |= 0x0000800000000000ULL;
2372 writeq(val64, &bar0->gpio_control);
2373 val64 = 0x0411040400000000ULL;
509a2671 2374 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 2375 }
2376
1da177e4
LT		 2377 return SUCCESS;
2378}
fed5eccd
AR		 2379/**
2380 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2381 */
d44570e4
JP		 2382static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2383 struct TxD *txdlp, int get_off)
fed5eccd 2384{
1ee6dd77 2385 struct s2io_nic *nic = fifo_data->nic;
fed5eccd 2386 struct sk_buff *skb;
1ee6dd77 2387 struct TxD *txds;
fed5eccd
AR		 2388 u16 j, frg_cnt;
2389
2390 txds = txdlp;
2fda096d 2391 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
d44570e4
JP		 2392 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2393 sizeof(u64), PCI_DMA_TODEVICE);
fed5eccd
AR		 2394 txds++;
2395 }
2396
d44570e4 2397 skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
fed5eccd 2398 if (!skb) {
1ee6dd77 2399 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2400 return NULL;
2401 }
d44570e4 2402 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
e743d313 2403 skb_headlen(skb), PCI_DMA_TODEVICE);
fed5eccd
AR		 2404 frg_cnt = skb_shinfo(skb)->nr_frags;
2405 if (frg_cnt) {
2406 txds++;
2407 for (j = 0; j < frg_cnt; j++, txds++) {
2408 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2409 if (!txds->Buffer_Pointer)
2410 break;
d44570e4
JP		 2411 pci_unmap_page(nic->pdev,
2412 (dma_addr_t)txds->Buffer_Pointer,
fed5eccd
AR		 2413 frag->size, PCI_DMA_TODEVICE);
2414 }
2415 }
d44570e4
JP		 2416 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2417 return skb;
fed5eccd 2418}
1da177e4 2419
20346722
K		 2420/**
2421 * free_tx_buffers - Free all queued Tx buffers
1da177e4 2422 * @nic : device private variable.
20346722 2423 * Description:
1da177e4 2424 * Free all queued Tx buffers.
20346722 2425 * Return Value: void
d44570e4 2426 */
1da177e4
LT		 2427
2428static void free_tx_buffers(struct s2io_nic *nic)
2429{
2430 struct net_device *dev = nic->dev;
2431 struct sk_buff *skb;
1ee6dd77 2432 struct TxD *txdp;
1da177e4 2433 int i, j;
fed5eccd 2434 int cnt = 0;
ffb5df6c
JP		 2435 struct config_param *config = &nic->config;
2436 struct mac_info *mac_control = &nic->mac_control;
2437 struct stat_block *stats = mac_control->stats_info;
2438 struct swStat *swstats = &stats->sw_stat;
1da177e4
LT		 2439
2440 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 2441 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2442 struct fifo_info *fifo = &mac_control->fifos[i];
2fda096d 2443 unsigned long flags;
13d866a9
JP		 2444
2445 spin_lock_irqsave(&fifo->tx_lock, flags);
2446 for (j = 0; j < tx_cfg->fifo_len; j++) {
2447 txdp = (struct TxD *)fifo->list_info[j].list_virt_addr;
fed5eccd
AR		 2448 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2449 if (skb) {
ffb5df6c 2450 swstats->mem_freed += skb->truesize;
fed5eccd
AR		 2451 dev_kfree_skb(skb);
2452 cnt++;
1da177e4 2453 }
1da177e4
LT		 2454 }
2455 DBG_PRINT(INTR_DBG,
9e39f7c5 2456 "%s: forcibly freeing %d skbs on FIFO%d\n",
1da177e4 2457 dev->name, cnt, i);
13d866a9
JP		 2458 fifo->tx_curr_get_info.offset = 0;
2459 fifo->tx_curr_put_info.offset = 0;
2460 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4
LT		 2461 }
2462}
2463
20346722
K		 2464/**
2465 * stop_nic - To stop the nic
1da177e4 2466 * @nic ; device private variable.
20346722
K		 2467 * Description:
2468 * This function does exactly the opposite of what the start_nic()
1da177e4
LT		 2469 * function does. This function is called to stop the device.
2470 * Return Value:
2471 * void.
2472 */
2473
2474static void stop_nic(struct s2io_nic *nic)
2475{
1ee6dd77 2476 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 2477 register u64 val64 = 0;
5d3213cc 2478 u16 interruptible;
1da177e4
LT		 2479
2480 /* Disable all interrupts */
9caab458 2481 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
e960fc5c 2482 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 2483 interruptible |= TX_PIC_INTR;
1da177e4
LT		 2484 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2485
5d3213cc
AR		 2486 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2487 val64 = readq(&bar0->adapter_control);
2488 val64 &= ~(ADAPTER_CNTL_EN);
2489 writeq(val64, &bar0->adapter_control);
1da177e4
LT		 2490}
2491
20346722
K		 2492/**
2493 * fill_rx_buffers - Allocates the Rx side skbs
0425b46a 2494 * @ring_info: per ring structure
3f78d885
SH		 2495 * @from_card_up: If this is true, we will map the buffer to get
2496 * the dma address for buf0 and buf1 to give it to the card.
2497 * Else we will sync the already mapped buffer to give it to the card.
20346722 2498 * Description:
1da177e4
LT		 2499 * The function allocates Rx side skbs and puts the physical
2500 * address of these buffers into the RxD buffer pointers, so that the NIC
2501 * can DMA the received frame into these locations.
2502 * The NIC supports 3 receive modes, viz
2503 * 1. single buffer,
2504 * 2. three buffer and
2505 * 3. Five buffer modes.
20346722
K		 2506 * Each mode defines how many fragments the received frame will be split
2507 * up into by the NIC. The frame is split into L3 header, L4 Header,
1da177e4
LT		 2508 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2509 * is split into 3 fragments. As of now only single buffer mode is
2510 * supported.
2511 * Return Value:
2512 * SUCCESS on success or an appropriate -ve value on failure.
2513 */
8d8bb39b 2514static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
d44570e4 2515 int from_card_up)
1da177e4 2516{
1da177e4 2517 struct sk_buff *skb;
1ee6dd77 2518 struct RxD_t *rxdp;
0425b46a 2519 int off, size, block_no, block_no1;
1da177e4 2520 u32 alloc_tab = 0;
20346722 2521 u32 alloc_cnt;
20346722 2522 u64 tmp;
1ee6dd77 2523 struct buffAdd *ba;
1ee6dd77 2524 struct RxD_t *first_rxdp = NULL;
363dc367 2525 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
0425b46a 2526 int rxd_index = 0;
6d517a27
VP		 2527 struct RxD1 *rxdp1;
2528 struct RxD3 *rxdp3;
ffb5df6c 2529 struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat;
1da177e4 2530
0425b46a 2531 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
1da177e4 2532
0425b46a 2533 block_no1 = ring->rx_curr_get_info.block_index;
1da177e4 2534 while (alloc_tab < alloc_cnt) {
0425b46a 2535 block_no = ring->rx_curr_put_info.block_index;
1da177e4 2536
0425b46a
SH		 2537 off = ring->rx_curr_put_info.offset;
2538
2539 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2540
2541 rxd_index = off + 1;
2542 if (block_no)
2543 rxd_index += (block_no * ring->rxd_count);
da6971d8 2544
7d2e3cb7 2545 if ((block_no == block_no1) &&
d44570e4
JP		 2546 (off == ring->rx_curr_get_info.offset) &&
2547 (rxdp->Host_Control)) {
9e39f7c5
JP		 2548 DBG_PRINT(INTR_DBG, "%s: Get and Put info equated\n",
2549 ring->dev->name);
1da177e4
LT		 2550 goto end;
2551 }
0425b46a
SH		 2552 if (off && (off == ring->rxd_count)) {
2553 ring->rx_curr_put_info.block_index++;
2554 if (ring->rx_curr_put_info.block_index ==
d44570e4 2555 ring->block_count)
0425b46a
SH		 2556 ring->rx_curr_put_info.block_index = 0;
2557 block_no = ring->rx_curr_put_info.block_index;
2558 off = 0;
2559 ring->rx_curr_put_info.offset = off;
2560 rxdp = ring->rx_blocks[block_no].block_virt_addr;
1da177e4 2561 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
0425b46a
SH		 2562 ring->dev->name, rxdp);
2563
1da177e4 2564 }
c9fcbf47 2565
da6971d8 2566 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
d44570e4
JP		 2567 ((ring->rxd_mode == RXD_MODE_3B) &&
2568 (rxdp->Control_2 & s2BIT(0)))) {
0425b46a 2569 ring->rx_curr_put_info.offset = off;
1da177e4
LT		 2570 goto end;
2571 }
da6971d8 2572 /* calculate size of skb based on ring mode */
d44570e4
JP		 2573 size = ring->mtu +
2574 HEADER_ETHERNET_II_802_3_SIZE +
2575 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
0425b46a 2576 if (ring->rxd_mode == RXD_MODE_1)
da6971d8 2577 size += NET_IP_ALIGN;
da6971d8 2578 else
0425b46a 2579 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
1da177e4 2580
da6971d8
AR		 2581 /* allocate skb */
2582 skb = dev_alloc_skb(size);
d44570e4 2583 if (!skb) {
9e39f7c5
JP		 2584 DBG_PRINT(INFO_DBG, "%s: Could not allocate skb\n",
2585 ring->dev->name);
303bcb4b
K		 2586 if (first_rxdp) {
2587 wmb();
2588 first_rxdp->Control_1 |= RXD_OWN_XENA;
2589 }
ffb5df6c 2590 swstats->mem_alloc_fail_cnt++;
7d2e3cb7 2591
da6971d8
AR		 2592 return -ENOMEM ;
2593 }
ffb5df6c 2594 swstats->mem_allocated += skb->truesize;
0425b46a
SH		 2595
2596 if (ring->rxd_mode == RXD_MODE_1) {
da6971d8 2597 /* 1 buffer mode - normal operation mode */
d44570e4 2598 rxdp1 = (struct RxD1 *)rxdp;
1ee6dd77 2599 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2600 skb_reserve(skb, NET_IP_ALIGN);
d44570e4
JP		 2601 rxdp1->Buffer0_ptr =
2602 pci_map_single(ring->pdev, skb->data,
2603 size - NET_IP_ALIGN,
2604 PCI_DMA_FROMDEVICE);
8d8bb39b 2605 if (pci_dma_mapping_error(nic->pdev,
d44570e4 2606 rxdp1->Buffer0_ptr))
491abf25
VP		 2607 goto pci_map_failed;
2608
8a4bdbaa 2609 rxdp->Control_2 =
491976b2 2610 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
d44570e4 2611 rxdp->Host_Control = (unsigned long)skb;
0425b46a 2612 } else if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8 2613 /*
6d517a27
VP		 2614 * 2 buffer mode -
2615 * 2 buffer mode provides 128
da6971d8 2616 * byte aligned receive buffers.
da6971d8
AR		 2617 */
2618
d44570e4 2619 rxdp3 = (struct RxD3 *)rxdp;
491976b2 2620 /* save buffer pointers to avoid frequent dma mapping */
6d517a27
VP		 2621 Buffer0_ptr = rxdp3->Buffer0_ptr;
2622 Buffer1_ptr = rxdp3->Buffer1_ptr;
1ee6dd77 2623 memset(rxdp, 0, sizeof(struct RxD3));
363dc367 2624 /* restore the buffer pointers for dma sync*/
6d517a27
VP		 2625 rxdp3->Buffer0_ptr = Buffer0_ptr;
2626 rxdp3->Buffer1_ptr = Buffer1_ptr;
363dc367 2627
0425b46a 2628 ba = &ring->ba[block_no][off];
da6971d8 2629 skb_reserve(skb, BUF0_LEN);
d44570e4 2630 tmp = (u64)(unsigned long)skb->data;
da6971d8
AR		 2631 tmp += ALIGN_SIZE;
2632 tmp &= ~ALIGN_SIZE;
2633 skb->data = (void *) (unsigned long)tmp;
27a884dc 2634 skb_reset_tail_pointer(skb);
da6971d8 2635
3f78d885 2636 if (from_card_up) {
6d517a27 2637 rxdp3->Buffer0_ptr =
d44570e4
JP		 2638 pci_map_single(ring->pdev, ba->ba_0,
2639 BUF0_LEN,
2640 PCI_DMA_FROMDEVICE);
2641 if (pci_dma_mapping_error(nic->pdev,
2642 rxdp3->Buffer0_ptr))
3f78d885
SH		 2643 goto pci_map_failed;
2644 } else
0425b46a 2645 pci_dma_sync_single_for_device(ring->pdev,
d44570e4
JP		 2646 (dma_addr_t)rxdp3->Buffer0_ptr,
2647 BUF0_LEN,
2648 PCI_DMA_FROMDEVICE);
491abf25 2649
da6971d8 2650 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
0425b46a 2651 if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 2652 /* Two buffer mode */
2653
2654 /*
6aa20a22 2655 * Buffer2 will have L3/L4 header plus
da6971d8
AR		 2656 * L4 payload
2657 */
d44570e4
JP		 2658 rxdp3->Buffer2_ptr = pci_map_single(ring->pdev,
2659 skb->data,
2660 ring->mtu + 4,
2661 PCI_DMA_FROMDEVICE);
da6971d8 2662
8d8bb39b 2663 if (pci_dma_mapping_error(nic->pdev,
d44570e4 2664 rxdp3->Buffer2_ptr))
491abf25
VP		 2665 goto pci_map_failed;
2666
3f78d885 2667 if (from_card_up) {
0425b46a
SH		 2668 rxdp3->Buffer1_ptr =
2669 pci_map_single(ring->pdev,
d44570e4
JP		 2670 ba->ba_1,
2671 BUF1_LEN,
2672 PCI_DMA_FROMDEVICE);
0425b46a 2673
8d8bb39b 2674 if (pci_dma_mapping_error(nic->pdev,
d44570e4
JP		 2675 rxdp3->Buffer1_ptr)) {
2676 pci_unmap_single(ring->pdev,
2677 (dma_addr_t)(unsigned long)
2678 skb->data,
2679 ring->mtu + 4,
2680 PCI_DMA_FROMDEVICE);
3f78d885
SH		 2681 goto pci_map_failed;
2682 }
75c30b13 2683 }
da6971d8
AR		 2684 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2685 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
d44570e4 2686 (ring->mtu + 4);
da6971d8 2687 }
b7b5a128 2688 rxdp->Control_2 |= s2BIT(0);
0425b46a 2689 rxdp->Host_Control = (unsigned long) (skb);
1da177e4 2690 }
303bcb4b
K		 2691 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2692 rxdp->Control_1 |= RXD_OWN_XENA;
1da177e4 2693 off++;
0425b46a 2694 if (off == (ring->rxd_count + 1))
da6971d8 2695 off = 0;
0425b46a 2696 ring->rx_curr_put_info.offset = off;
20346722 2697
da6971d8 2698 rxdp->Control_2 |= SET_RXD_MARKER;
303bcb4b
K		 2699 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2700 if (first_rxdp) {
2701 wmb();
2702 first_rxdp->Control_1 |= RXD_OWN_XENA;
2703 }
2704 first_rxdp = rxdp;
2705 }
0425b46a 2706 ring->rx_bufs_left += 1;
1da177e4
LT		 2707 alloc_tab++;
2708 }
2709
d44570e4 2710end:
303bcb4b
K		 2711 /* Transfer ownership of first descriptor to adapter just before
2712 * exiting. Before that, use memory barrier so that ownership
2713 * and other fields are seen by adapter correctly.
2714 */
2715 if (first_rxdp) {
2716 wmb();
2717 first_rxdp->Control_1 |= RXD_OWN_XENA;
2718 }
2719
1da177e4 2720 return SUCCESS;
d44570e4 2721
491abf25 2722pci_map_failed:
ffb5df6c
JP		 2723 swstats->pci_map_fail_cnt++;
2724 swstats->mem_freed += skb->truesize;
491abf25
VP		 2725 dev_kfree_skb_irq(skb);
2726 return -ENOMEM;
1da177e4
LT		 2727}
2728
da6971d8
AR		 2729static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2730{
2731 struct net_device *dev = sp->dev;
2732 int j;
2733 struct sk_buff *skb;
1ee6dd77 2734 struct RxD_t *rxdp;
1ee6dd77 2735 struct buffAdd *ba;
6d517a27
VP		 2736 struct RxD1 *rxdp1;
2737 struct RxD3 *rxdp3;
ffb5df6c
JP		 2738 struct mac_info *mac_control = &sp->mac_control;
2739 struct stat_block *stats = mac_control->stats_info;
2740 struct swStat *swstats = &stats->sw_stat;
da6971d8 2741
da6971d8
AR		 2742 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2743 rxdp = mac_control->rings[ring_no].
d44570e4
JP		 2744 rx_blocks[blk].rxds[j].virt_addr;
2745 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2746 if (!skb)
da6971d8 2747 continue;
da6971d8 2748 if (sp->rxd_mode == RXD_MODE_1) {
d44570e4
JP		 2749 rxdp1 = (struct RxD1 *)rxdp;
2750 pci_unmap_single(sp->pdev,
2751 (dma_addr_t)rxdp1->Buffer0_ptr,
2752 dev->mtu +
2753 HEADER_ETHERNET_II_802_3_SIZE +
2754 HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2755 PCI_DMA_FROMDEVICE);
1ee6dd77 2756 memset(rxdp, 0, sizeof(struct RxD1));
d44570e4
JP		 2757 } else if (sp->rxd_mode == RXD_MODE_3B) {
2758 rxdp3 = (struct RxD3 *)rxdp;
2759 ba = &mac_control->rings[ring_no].ba[blk][j];
2760 pci_unmap_single(sp->pdev,
2761 (dma_addr_t)rxdp3->Buffer0_ptr,
2762 BUF0_LEN,
2763 PCI_DMA_FROMDEVICE);
2764 pci_unmap_single(sp->pdev,
2765 (dma_addr_t)rxdp3->Buffer1_ptr,
2766 BUF1_LEN,
2767 PCI_DMA_FROMDEVICE);
2768 pci_unmap_single(sp->pdev,
2769 (dma_addr_t)rxdp3->Buffer2_ptr,
2770 dev->mtu + 4,
2771 PCI_DMA_FROMDEVICE);
1ee6dd77 2772 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8 2773 }
ffb5df6c 2774 swstats->mem_freed += skb->truesize;
da6971d8 2775 dev_kfree_skb(skb);
0425b46a 2776 mac_control->rings[ring_no].rx_bufs_left -= 1;
da6971d8
AR		 2777 }
2778}
2779
1da177e4 2780/**
20346722 2781 * free_rx_buffers - Frees all Rx buffers
1da177e4 2782 * @sp: device private variable.
20346722 2783 * Description:
1da177e4
LT		 2784 * This function will free all Rx buffers allocated by host.
2785 * Return Value:
2786 * NONE.
2787 */
2788
2789static void free_rx_buffers(struct s2io_nic *sp)
2790{
2791 struct net_device *dev = sp->dev;
da6971d8 2792 int i, blk = 0, buf_cnt = 0;
ffb5df6c
JP		 2793 struct config_param *config = &sp->config;
2794 struct mac_info *mac_control = &sp->mac_control;
1da177e4
LT		 2795
2796 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2797 struct ring_info *ring = &mac_control->rings[i];
2798
da6971d8 2799 for (blk = 0; blk < rx_ring_sz[i]; blk++)
d44570e4 2800 free_rxd_blk(sp, i, blk);
1da177e4 2801
13d866a9
JP		 2802 ring->rx_curr_put_info.block_index = 0;
2803 ring->rx_curr_get_info.block_index = 0;
2804 ring->rx_curr_put_info.offset = 0;
2805 ring->rx_curr_get_info.offset = 0;
2806 ring->rx_bufs_left = 0;
9e39f7c5 2807 DBG_PRINT(INIT_DBG, "%s: Freed 0x%x Rx Buffers on ring%d\n",
1da177e4
LT		 2808 dev->name, buf_cnt, i);
2809 }
2810}
2811
8d8bb39b 2812static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
f61e0a35 2813{
8d8bb39b 2814 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
9e39f7c5
JP		 2815 DBG_PRINT(INFO_DBG, "%s: Out of memory in Rx Intr!!\n",
2816 ring->dev->name);
f61e0a35
SH		 2817 }
2818 return 0;
2819}
2820
1da177e4
LT		 2821/**
2822 * s2io_poll - Rx interrupt handler for NAPI support
bea3348e 2823 * @napi : pointer to the napi structure.
20346722 2824 * @budget : The number of packets that were budgeted to be processed
1da177e4
LT		 2825 * during one pass through the 'Poll" function.
2826 * Description:
2827 * Comes into picture only if NAPI support has been incorporated. It does
2828 * the same thing that rx_intr_handler does, but not in a interrupt context
2829 * also It will process only a given number of packets.
2830 * Return value:
2831 * 0 on success and 1 if there are No Rx packets to be processed.
2832 */
2833
f61e0a35 2834static int s2io_poll_msix(struct napi_struct *napi, int budget)
1da177e4 2835{
f61e0a35
SH		 2836 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2837 struct net_device *dev = ring->dev;
f61e0a35 2838 int pkts_processed = 0;
1a79d1c3
AV		 2839 u8 __iomem *addr = NULL;
2840 u8 val8 = 0;
4cf1653a 2841 struct s2io_nic *nic = netdev_priv(dev);
1ee6dd77 2842 struct XENA_dev_config __iomem *bar0 = nic->bar0;
f61e0a35 2843 int budget_org = budget;
1da177e4 2844
f61e0a35
SH		 2845 if (unlikely(!is_s2io_card_up(nic)))
2846 return 0;
1da177e4 2847
f61e0a35 2848 pkts_processed = rx_intr_handler(ring, budget);
8d8bb39b 2849 s2io_chk_rx_buffers(nic, ring);
1da177e4 2850
f61e0a35 2851 if (pkts_processed < budget_org) {
288379f0 2852 napi_complete(napi);
f61e0a35 2853 /*Re Enable MSI-Rx Vector*/
1a79d1c3 2854 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
f61e0a35
SH		 2855 addr += 7 - ring->ring_no;
2856 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2857 writeb(val8, addr);
2858 val8 = readb(addr);
1da177e4 2859 }
f61e0a35
SH		 2860 return pkts_processed;
2861}
d44570e4 2862
f61e0a35
SH		 2863static int s2io_poll_inta(struct napi_struct *napi, int budget)
2864{
2865 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
f61e0a35
SH		 2866 int pkts_processed = 0;
2867 int ring_pkts_processed, i;
2868 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2869 int budget_org = budget;
ffb5df6c
JP		 2870 struct config_param *config = &nic->config;
2871 struct mac_info *mac_control = &nic->mac_control;
1da177e4 2872
f61e0a35
SH		 2873 if (unlikely(!is_s2io_card_up(nic)))
2874 return 0;
1da177e4 2875
1da177e4 2876 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9 2877 struct ring_info *ring = &mac_control->rings[i];
f61e0a35 2878 ring_pkts_processed = rx_intr_handler(ring, budget);
8d8bb39b 2879 s2io_chk_rx_buffers(nic, ring);
f61e0a35
SH		 2880 pkts_processed += ring_pkts_processed;
2881 budget -= ring_pkts_processed;
2882 if (budget <= 0)
1da177e4 2883 break;
1da177e4 2884 }
f61e0a35 2885 if (pkts_processed < budget_org) {
288379f0 2886 napi_complete(napi);
f61e0a35
SH		 2887 /* Re enable the Rx interrupts for the ring */
2888 writeq(0, &bar0->rx_traffic_mask);
2889 readl(&bar0->rx_traffic_mask);
2890 }
2891 return pkts_processed;
1da177e4 2892}
20346722 2893
b41477f3 2894#ifdef CONFIG_NET_POLL_CONTROLLER
612eff0e 2895/**
b41477f3 2896 * s2io_netpoll - netpoll event handler entry point
612eff0e
BH		 2897 * @dev : pointer to the device structure.
2898 * Description:
b41477f3
AR		 2899 * This function will be called by upper layer to check for events on the
2900 * interface in situations where interrupts are disabled. It is used for
2901 * specific in-kernel networking tasks, such as remote consoles and kernel
2902 * debugging over the network (example netdump in RedHat).
612eff0e 2903 */
612eff0e
BH		 2904static void s2io_netpoll(struct net_device *dev)
2905{
4cf1653a 2906 struct s2io_nic *nic = netdev_priv(dev);
1ee6dd77 2907 struct XENA_dev_config __iomem *bar0 = nic->bar0;
b41477f3 2908 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
612eff0e 2909 int i;
ffb5df6c
JP		 2910 struct config_param *config = &nic->config;
2911 struct mac_info *mac_control = &nic->mac_control;
612eff0e 2912
d796fdb7
LV		 2913 if (pci_channel_offline(nic->pdev))
2914 return;
2915
612eff0e
BH		 2916 disable_irq(dev->irq);
2917
612eff0e 2918 writeq(val64, &bar0->rx_traffic_int);
b41477f3
AR		 2919 writeq(val64, &bar0->tx_traffic_int);
2920
6aa20a22 2921 /* we need to free up the transmitted skbufs or else netpoll will
b41477f3
AR		 2922 * run out of skbs and will fail and eventually netpoll application such
2923 * as netdump will fail.
2924 */
2925 for (i = 0; i < config->tx_fifo_num; i++)
2926 tx_intr_handler(&mac_control->fifos[i]);
612eff0e 2927
b41477f3 2928 /* check for received packet and indicate up to network */
13d866a9
JP		 2929 for (i = 0; i < config->rx_ring_num; i++) {
2930 struct ring_info *ring = &mac_control->rings[i];
2931
2932 rx_intr_handler(ring, 0);
2933 }
612eff0e
BH		 2934
2935 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2936 struct ring_info *ring = &mac_control->rings[i];
2937
2938 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
9e39f7c5
JP		 2939 DBG_PRINT(INFO_DBG,
2940 "%s: Out of memory in Rx Netpoll!!\n",
2941 dev->name);
612eff0e
BH		 2942 break;
2943 }
2944 }
612eff0e 2945 enable_irq(dev->irq);
612eff0e
BH		 2946}
2947#endif
2948
20346722 2949/**
1da177e4 2950 * rx_intr_handler - Rx interrupt handler
f61e0a35
SH		 2951 * @ring_info: per ring structure.
2952 * @budget: budget for napi processing.
20346722
K		 2953 * Description:
2954 * If the interrupt is because of a received frame or if the
1da177e4 2955 * receive ring contains fresh as yet un-processed frames,this function is
20346722
K		 2956 * called. It picks out the RxD at which place the last Rx processing had
2957 * stopped and sends the skb to the OSM's Rx handler and then increments
1da177e4
LT		 2958 * the offset.
2959 * Return Value:
f61e0a35 2960 * No. of napi packets processed.
1da177e4 2961 */
f61e0a35 2962static int rx_intr_handler(struct ring_info *ring_data, int budget)
1da177e4 2963{
c9fcbf47 2964 int get_block, put_block;
1ee6dd77
RB		 2965 struct rx_curr_get_info get_info, put_info;
2966 struct RxD_t *rxdp;
1da177e4 2967 struct sk_buff *skb;
f61e0a35 2968 int pkt_cnt = 0, napi_pkts = 0;
7d3d0439 2969 int i;
d44570e4
JP		 2970 struct RxD1 *rxdp1;
2971 struct RxD3 *rxdp3;
7d3d0439 2972
20346722
K		 2973 get_info = ring_data->rx_curr_get_info;
2974 get_block = get_info.block_index;
1ee6dd77 2975 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
20346722 2976 put_block = put_info.block_index;
da6971d8 2977 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
db874e65 2978
da6971d8 2979 while (RXD_IS_UP2DT(rxdp)) {
db874e65
SS		 2980 /*
2981 * If your are next to put index then it's
2982 * FIFO full condition
2983 */
da6971d8
AR		 2984 if ((get_block == put_block) &&
2985 (get_info.offset + 1) == put_info.offset) {
0425b46a 2986 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
d44570e4 2987 ring_data->dev->name);
da6971d8
AR		 2988 break;
2989 }
d44570e4 2990 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
20346722 2991 if (skb == NULL) {
9e39f7c5 2992 DBG_PRINT(ERR_DBG, "%s: NULL skb in Rx Intr\n",
0425b46a 2993 ring_data->dev->name);
f61e0a35 2994 return 0;
1da177e4 2995 }
0425b46a 2996 if (ring_data->rxd_mode == RXD_MODE_1) {
d44570e4 2997 rxdp1 = (struct RxD1 *)rxdp;
0425b46a 2998 pci_unmap_single(ring_data->pdev, (dma_addr_t)
d44570e4
JP		 2999 rxdp1->Buffer0_ptr,
3000 ring_data->mtu +
3001 HEADER_ETHERNET_II_802_3_SIZE +
3002 HEADER_802_2_SIZE +
3003 HEADER_SNAP_SIZE,
3004 PCI_DMA_FROMDEVICE);
0425b46a 3005 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
d44570e4
JP		 3006 rxdp3 = (struct RxD3 *)rxdp;
3007 pci_dma_sync_single_for_cpu(ring_data->pdev,
3008 (dma_addr_t)rxdp3->Buffer0_ptr,
3009 BUF0_LEN,
3010 PCI_DMA_FROMDEVICE);
3011 pci_unmap_single(ring_data->pdev,
3012 (dma_addr_t)rxdp3->Buffer2_ptr,
3013 ring_data->mtu + 4,
3014 PCI_DMA_FROMDEVICE);
da6971d8 3015 }
863c11a9 3016 prefetch(skb->data);
20346722
K		 3017 rx_osm_handler(ring_data, rxdp);
3018 get_info.offset++;
da6971d8
AR		 3019 ring_data->rx_curr_get_info.offset = get_info.offset;
3020 rxdp = ring_data->rx_blocks[get_block].
d44570e4 3021 rxds[get_info.offset].virt_addr;
0425b46a 3022 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
20346722 3023 get_info.offset = 0;
da6971d8 3024 ring_data->rx_curr_get_info.offset = get_info.offset;
20346722 3025 get_block++;
da6971d8
AR		 3026 if (get_block == ring_data->block_count)
3027 get_block = 0;
3028 ring_data->rx_curr_get_info.block_index = get_block;
20346722
K		 3029 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3030 }
1da177e4 3031
f61e0a35
SH		 3032 if (ring_data->nic->config.napi) {
3033 budget--;
3034 napi_pkts++;
3035 if (!budget)
0425b46a
SH		 3036 break;
3037 }
20346722 3038 pkt_cnt++;
1da177e4
LT		 3039 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3040 break;
3041 }
0425b46a 3042 if (ring_data->lro) {
7d3d0439 3043 /* Clear all LRO sessions before exiting */
d44570e4 3044 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 3045 struct lro *lro = &ring_data->lro0_n[i];
7d3d0439 3046 if (lro->in_use) {
0425b46a 3047 update_L3L4_header(ring_data->nic, lro);
cdb5bf02 3048 queue_rx_frame(lro->parent, lro->vlan_tag);
7d3d0439
RA		 3049 clear_lro_session(lro);
3050 }
3051 }
3052 }
d44570e4 3053 return napi_pkts;
1da177e4 3054}
20346722
K		 3055
3056/**
1da177e4
LT		 3057 * tx_intr_handler - Transmit interrupt handler
3058 * @nic : device private variable
20346722
K		 3059 * Description:
3060 * If an interrupt was raised to indicate DMA complete of the
3061 * Tx packet, this function is called. It identifies the last TxD
3062 * whose buffer was freed and frees all skbs whose data have already
1da177e4
LT		 3063 * DMA'ed into the NICs internal memory.
3064 * Return Value:
3065 * NONE
3066 */
3067
1ee6dd77 3068static void tx_intr_handler(struct fifo_info *fifo_data)
1da177e4 3069{
1ee6dd77 3070 struct s2io_nic *nic = fifo_data->nic;
1ee6dd77 3071 struct tx_curr_get_info get_info, put_info;
3a3d5756 3072 struct sk_buff *skb = NULL;
1ee6dd77 3073 struct TxD *txdlp;
3a3d5756 3074 int pkt_cnt = 0;
2fda096d 3075 unsigned long flags = 0;
f9046eb3 3076 u8 err_mask;
ffb5df6c
JP		 3077 struct stat_block *stats = nic->mac_control.stats_info;
3078 struct swStat *swstats = &stats->sw_stat;
1da177e4 3079
2fda096d 3080 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
d44570e4 3081 return;
2fda096d 3082
20346722 3083 get_info = fifo_data->tx_curr_get_info;
1ee6dd77 3084 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
d44570e4
JP		 3085 txdlp = (struct TxD *)
3086 fifo_data->list_info[get_info.offset].list_virt_addr;
20346722
K		 3087 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3088 (get_info.offset != put_info.offset) &&
3089 (txdlp->Host_Control)) {
3090 /* Check for TxD errors */
3091 if (txdlp->Control_1 & TXD_T_CODE) {
3092 unsigned long long err;
3093 err = txdlp->Control_1 & TXD_T_CODE;
bd1034f0 3094 if (err & 0x1) {
ffb5df6c 3095 swstats->parity_err_cnt++;
bd1034f0 3096 }
491976b2
SH		 3097
3098 /* update t_code statistics */
f9046eb3 3099 err_mask = err >> 48;
d44570e4
JP		 3100 switch (err_mask) {
3101 case 2:
ffb5df6c 3102 swstats->tx_buf_abort_cnt++;
491976b2
SH		 3103 break;
3104
d44570e4 3105 case 3:
ffb5df6c 3106 swstats->tx_desc_abort_cnt++;
491976b2
SH		 3107 break;
3108
d44570e4 3109 case 7:
ffb5df6c 3110 swstats->tx_parity_err_cnt++;
491976b2
SH		 3111 break;
3112
d44570e4 3113 case 10:
ffb5df6c 3114 swstats->tx_link_loss_cnt++;
491976b2
SH		 3115 break;
3116
d44570e4 3117 case 15:
ffb5df6c 3118 swstats->tx_list_proc_err_cnt++;
491976b2 3119 break;
d44570e4 3120 }
20346722 3121 }
1da177e4 3122
fed5eccd 3123 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
20346722 3124 if (skb == NULL) {
2fda096d 3125 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
9e39f7c5
JP		 3126 DBG_PRINT(ERR_DBG, "%s: NULL skb in Tx Free Intr\n",
3127 __func__);
20346722
K		 3128 return;
3129 }
3a3d5756 3130 pkt_cnt++;
20346722 3131
20346722 3132 /* Updating the statistics block */
dc56e634 3133 nic->dev->stats.tx_bytes += skb->len;
ffb5df6c 3134 swstats->mem_freed += skb->truesize;
20346722
K		 3135 dev_kfree_skb_irq(skb);
3136
3137 get_info.offset++;
863c11a9
AR		 3138 if (get_info.offset == get_info.fifo_len + 1)
3139 get_info.offset = 0;
d44570e4
JP		 3140 txdlp = (struct TxD *)
3141 fifo_data->list_info[get_info.offset].list_virt_addr;
3142 fifo_data->tx_curr_get_info.offset = get_info.offset;
1da177e4
LT		 3143 }
3144
3a3d5756 3145 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
2fda096d
SR		 3146
3147 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
1da177e4
LT		 3148}
3149
bd1034f0
AR		 3150/**
3151 * s2io_mdio_write - Function to write in to MDIO registers
3152 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3153 * @addr : address value
3154 * @value : data value
3155 * @dev : pointer to net_device structure
3156 * Description:
3157 * This function is used to write values to the MDIO registers
3158 * NONE
3159 */
d44570e4
JP		 3160static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3161 struct net_device *dev)
bd1034f0 3162{
d44570e4 3163 u64 val64;
4cf1653a 3164 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3165 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0 3166
d44570e4
JP		 3167 /* address transaction */
3168 val64 = MDIO_MMD_INDX_ADDR(addr) |
3169 MDIO_MMD_DEV_ADDR(mmd_type) |
3170 MDIO_MMS_PRT_ADDR(0x0);
bd1034f0
AR		 3171 writeq(val64, &bar0->mdio_control);
3172 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3173 writeq(val64, &bar0->mdio_control);
3174 udelay(100);
3175
d44570e4
JP		 3176 /* Data transaction */
3177 val64 = MDIO_MMD_INDX_ADDR(addr) |
3178 MDIO_MMD_DEV_ADDR(mmd_type) |
3179 MDIO_MMS_PRT_ADDR(0x0) |
3180 MDIO_MDIO_DATA(value) |
3181 MDIO_OP(MDIO_OP_WRITE_TRANS);
bd1034f0
AR		 3182 writeq(val64, &bar0->mdio_control);
3183 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3184 writeq(val64, &bar0->mdio_control);
3185 udelay(100);
3186
d44570e4
JP		 3187 val64 = MDIO_MMD_INDX_ADDR(addr) |
3188 MDIO_MMD_DEV_ADDR(mmd_type) |
3189 MDIO_MMS_PRT_ADDR(0x0) |
3190 MDIO_OP(MDIO_OP_READ_TRANS);
bd1034f0
AR		 3191 writeq(val64, &bar0->mdio_control);
3192 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3193 writeq(val64, &bar0->mdio_control);
3194 udelay(100);
bd1034f0
AR		 3195}
3196
3197/**
3198 * s2io_mdio_read - Function to write in to MDIO registers
3199 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3200 * @addr : address value
3201 * @dev : pointer to net_device structure
3202 * Description:
3203 * This function is used to read values to the MDIO registers
3204 * NONE
3205 */
3206static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3207{
3208 u64 val64 = 0x0;
3209 u64 rval64 = 0x0;
4cf1653a 3210 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3211 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3212
3213 /* address transaction */
d44570e4
JP		 3214 val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3215 | MDIO_MMD_DEV_ADDR(mmd_type)
3216 | MDIO_MMS_PRT_ADDR(0x0));
bd1034f0
AR		 3217 writeq(val64, &bar0->mdio_control);
3218 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3219 writeq(val64, &bar0->mdio_control);
3220 udelay(100);
3221
3222 /* Data transaction */
d44570e4
JP		 3223 val64 = MDIO_MMD_INDX_ADDR(addr) |
3224 MDIO_MMD_DEV_ADDR(mmd_type) |
3225 MDIO_MMS_PRT_ADDR(0x0) |
3226 MDIO_OP(MDIO_OP_READ_TRANS);
bd1034f0
AR		 3227 writeq(val64, &bar0->mdio_control);
3228 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3229 writeq(val64, &bar0->mdio_control);
3230 udelay(100);
3231
3232 /* Read the value from regs */
3233 rval64 = readq(&bar0->mdio_control);
3234 rval64 = rval64 & 0xFFFF0000;
3235 rval64 = rval64 >> 16;
3236 return rval64;
3237}
d44570e4 3238
bd1034f0
AR		 3239/**
3240 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
fbfecd37 3241 * @counter : counter value to be updated
bd1034f0
AR		 3242 * @flag : flag to indicate the status
3243 * @type : counter type
3244 * Description:
3245 * This function is to check the status of the xpak counters value
3246 * NONE
3247 */
3248
d44570e4
JP		 3249static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3250 u16 flag, u16 type)
bd1034f0
AR		 3251{
3252 u64 mask = 0x3;
3253 u64 val64;
3254 int i;
d44570e4 3255 for (i = 0; i < index; i++)
bd1034f0
AR		 3256 mask = mask << 0x2;
3257
d44570e4 3258 if (flag > 0) {
bd1034f0
AR		 3259 *counter = *counter + 1;
3260 val64 = *regs_stat & mask;
3261 val64 = val64 >> (index * 0x2);
3262 val64 = val64 + 1;
d44570e4
JP		 3263 if (val64 == 3) {
3264 switch (type) {
bd1034f0 3265 case 1:
9e39f7c5
JP		 3266 DBG_PRINT(ERR_DBG,
3267 "Take Xframe NIC out of service.\n");
3268 DBG_PRINT(ERR_DBG,
3269"Excessive temperatures may result in premature transceiver failure.\n");
d44570e4 3270 break;
bd1034f0 3271 case 2:
9e39f7c5
JP		 3272 DBG_PRINT(ERR_DBG,
3273 "Take Xframe NIC out of service.\n");
3274 DBG_PRINT(ERR_DBG,
3275"Excessive bias currents may indicate imminent laser diode failure.\n");
d44570e4 3276 break;
bd1034f0 3277 case 3:
9e39f7c5
JP		 3278 DBG_PRINT(ERR_DBG,
3279 "Take Xframe NIC out of service.\n");
3280 DBG_PRINT(ERR_DBG,
3281"Excessive laser output power may saturate far-end receiver.\n");
d44570e4 3282 break;
bd1034f0 3283 default:
d44570e4
JP		 3284 DBG_PRINT(ERR_DBG,
3285 "Incorrect XPAK Alarm type\n");
bd1034f0
AR		 3286 }
3287 val64 = 0x0;
3288 }
3289 val64 = val64 << (index * 0x2);
3290 *regs_stat = (*regs_stat & (~mask)) | (val64);
3291
3292 } else {
3293 *regs_stat = *regs_stat & (~mask);
3294 }
3295}
3296
3297/**
3298 * s2io_updt_xpak_counter - Function to update the xpak counters
3299 * @dev : pointer to net_device struct
3300 * Description:
3301 * This function is to upate the status of the xpak counters value
3302 * NONE
3303 */
3304static void s2io_updt_xpak_counter(struct net_device *dev)
3305{
3306 u16 flag = 0x0;
3307 u16 type = 0x0;
3308 u16 val16 = 0x0;
3309 u64 val64 = 0x0;
3310 u64 addr = 0x0;
3311
4cf1653a 3312 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c
JP		 3313 struct stat_block *stats = sp->mac_control.stats_info;
3314 struct xpakStat *xstats = &stats->xpak_stat;
bd1034f0
AR		 3315
3316 /* Check the communication with the MDIO slave */
40239396 3317 addr = MDIO_CTRL1;
bd1034f0 3318 val64 = 0x0;
40239396 3319 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
d44570e4 3320 if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
9e39f7c5
JP		 3321 DBG_PRINT(ERR_DBG,
3322 "ERR: MDIO slave access failed - Returned %llx\n",
3323 (unsigned long long)val64);
bd1034f0
AR		 3324 return;
3325 }
3326
40239396 3327 /* Check for the expected value of control reg 1 */
d44570e4 3328 if (val64 != MDIO_CTRL1_SPEED10G) {
9e39f7c5
JP		 3329 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - "
3330 "Returned: %llx- Expected: 0x%x\n",
40239396 3331 (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
bd1034f0
AR		 3332 return;
3333 }
3334
3335 /* Loading the DOM register to MDIO register */
3336 addr = 0xA100;
40239396
BH		 3337 s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3338 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3339
3340 /* Reading the Alarm flags */
3341 addr = 0xA070;
3342 val64 = 0x0;
40239396 3343 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3344
3345 flag = CHECKBIT(val64, 0x7);
3346 type = 1;
ffb5df6c
JP		 3347 s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high,
3348 &xstats->xpak_regs_stat,
d44570e4 3349 0x0, flag, type);
bd1034f0 3350
d44570e4 3351 if (CHECKBIT(val64, 0x6))
ffb5df6c 3352 xstats->alarm_transceiver_temp_low++;
bd1034f0
AR		 3353
3354 flag = CHECKBIT(val64, 0x3);
3355 type = 2;
ffb5df6c
JP		 3356 s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high,
3357 &xstats->xpak_regs_stat,
d44570e4 3358 0x2, flag, type);
bd1034f0 3359
d44570e4 3360 if (CHECKBIT(val64, 0x2))
ffb5df6c 3361 xstats->alarm_laser_bias_current_low++;
bd1034f0
AR		 3362
3363 flag = CHECKBIT(val64, 0x1);
3364 type = 3;
ffb5df6c
JP		 3365 s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high,
3366 &xstats->xpak_regs_stat,
d44570e4 3367 0x4, flag, type);
bd1034f0 3368
d44570e4 3369 if (CHECKBIT(val64, 0x0))
ffb5df6c 3370 xstats->alarm_laser_output_power_low++;
bd1034f0
AR		 3371
3372 /* Reading the Warning flags */
3373 addr = 0xA074;
3374 val64 = 0x0;
40239396 3375 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0 3376
d44570e4 3377 if (CHECKBIT(val64, 0x7))
ffb5df6c 3378 xstats->warn_transceiver_temp_high++;
bd1034f0 3379
d44570e4 3380 if (CHECKBIT(val64, 0x6))
ffb5df6c 3381 xstats->warn_transceiver_temp_low++;
bd1034f0 3382
d44570e4 3383 if (CHECKBIT(val64, 0x3))
ffb5df6c 3384 xstats->warn_laser_bias_current_high++;
bd1034f0 3385
d44570e4 3386 if (CHECKBIT(val64, 0x2))
ffb5df6c 3387 xstats->warn_laser_bias_current_low++;
bd1034f0 3388
d44570e4 3389 if (CHECKBIT(val64, 0x1))
ffb5df6c 3390 xstats->warn_laser_output_power_high++;
bd1034f0 3391
d44570e4 3392 if (CHECKBIT(val64, 0x0))
ffb5df6c 3393 xstats->warn_laser_output_power_low++;
bd1034f0
AR		 3394}
3395
20346722 3396/**
1da177e4 3397 * wait_for_cmd_complete - waits for a command to complete.
20346722 3398 * @sp : private member of the device structure, which is a pointer to the
1da177e4 3399 * s2io_nic structure.
20346722
K		 3400 * Description: Function that waits for a command to Write into RMAC
3401 * ADDR DATA registers to be completed and returns either success or
3402 * error depending on whether the command was complete or not.
1da177e4
LT		 3403 * Return value:
3404 * SUCCESS on success and FAILURE on failure.
3405 */
3406
9fc93a41 3407static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
d44570e4 3408 int bit_state)
1da177e4 3409{
9fc93a41 3410 int ret = FAILURE, cnt = 0, delay = 1;
1da177e4
LT		 3411 u64 val64;
3412
9fc93a41
SS		 3413 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3414 return FAILURE;
3415
3416 do {
c92ca04b 3417 val64 = readq(addr);
9fc93a41
SS		 3418 if (bit_state == S2IO_BIT_RESET) {
3419 if (!(val64 & busy_bit)) {
3420 ret = SUCCESS;
3421 break;
3422 }
3423 } else {
2d146eb1 3424 if (val64 & busy_bit) {
9fc93a41
SS		 3425 ret = SUCCESS;
3426 break;
3427 }
1da177e4 3428 }
c92ca04b 3429
d44570e4 3430 if (in_interrupt())
9fc93a41 3431 mdelay(delay);
c92ca04b 3432 else
9fc93a41 3433 msleep(delay);
c92ca04b 3434
9fc93a41
SS		 3435 if (++cnt >= 10)
3436 delay = 50;
3437 } while (cnt < 20);
1da177e4
LT		 3438 return ret;
3439}
19a60522
SS		 3440/*
3441 * check_pci_device_id - Checks if the device id is supported
3442 * @id : device id
3443 * Description: Function to check if the pci device id is supported by driver.
3444 * Return value: Actual device id if supported else PCI_ANY_ID
3445 */
3446static u16 check_pci_device_id(u16 id)
3447{
3448 switch (id) {
3449 case PCI_DEVICE_ID_HERC_WIN:
3450 case PCI_DEVICE_ID_HERC_UNI:
3451 return XFRAME_II_DEVICE;
3452 case PCI_DEVICE_ID_S2IO_UNI:
3453 case PCI_DEVICE_ID_S2IO_WIN:
3454 return XFRAME_I_DEVICE;
3455 default:
3456 return PCI_ANY_ID;
3457 }
3458}
1da177e4 3459
20346722
K		 3460/**
3461 * s2io_reset - Resets the card.
1da177e4
LT		 3462 * @sp : private member of the device structure.
3463 * Description: Function to Reset the card. This function then also
20346722 3464 * restores the previously saved PCI configuration space registers as
1da177e4
LT		 3465 * the card reset also resets the configuration space.
3466 * Return value:
3467 * void.
3468 */
3469
d44570e4 3470static void s2io_reset(struct s2io_nic *sp)
1da177e4 3471{
1ee6dd77 3472 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 3473 u64 val64;
5e25b9dd 3474 u16 subid, pci_cmd;
19a60522
SS		 3475 int i;
3476 u16 val16;
491976b2
SH		 3477 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3478 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
ffb5df6c
JP		 3479 struct stat_block *stats;
3480 struct swStat *swstats;
491976b2 3481
9e39f7c5 3482 DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n",
3a22813a 3483 __func__, pci_name(sp->pdev));
1da177e4 3484
0b1f7ebe 3485 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
e960fc5c 3486 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
0b1f7ebe 3487
1da177e4
LT		 3488 val64 = SW_RESET_ALL;
3489 writeq(val64, &bar0->sw_reset);
d44570e4 3490 if (strstr(sp->product_name, "CX4"))
c92ca04b 3491 msleep(750);
19a60522
SS		 3492 msleep(250);
3493 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
1da177e4 3494
19a60522
SS		 3495 /* Restore the PCI state saved during initialization. */
3496 pci_restore_state(sp->pdev);
b8a623bf 3497 pci_save_state(sp->pdev);
19a60522
SS		 3498 pci_read_config_word(sp->pdev, 0x2, &val16);
3499 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3500 break;
3501 msleep(200);
3502 }
1da177e4 3503
d44570e4
JP		 3504 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3505 DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
19a60522
SS		 3506
3507 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3508
3509 s2io_init_pci(sp);
1da177e4 3510
20346722
K		 3511 /* Set swapper to enable I/O register access */
3512 s2io_set_swapper(sp);
3513
faa4f796
SH		 3514 /* restore mac_addr entries */
3515 do_s2io_restore_unicast_mc(sp);
3516
cc6e7c44
RA		 3517 /* Restore the MSIX table entries from local variables */
3518 restore_xmsi_data(sp);
3519
5e25b9dd 3520 /* Clear certain PCI/PCI-X fields after reset */
303bcb4b 3521 if (sp->device_type == XFRAME_II_DEVICE) {
b41477f3 3522 /* Clear "detected parity error" bit */
303bcb4b 3523 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
5e25b9dd 3524
303bcb4b
K		 3525 /* Clearing PCIX Ecc status register */
3526 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
5e25b9dd 3527
303bcb4b 3528 /* Clearing PCI_STATUS error reflected here */
b7b5a128 3529 writeq(s2BIT(62), &bar0->txpic_int_reg);
303bcb4b 3530 }
5e25b9dd 3531
20346722 3532 /* Reset device statistics maintained by OS */
d44570e4 3533 memset(&sp->stats, 0, sizeof(struct net_device_stats));
8a4bdbaa 3534
ffb5df6c
JP		 3535 stats = sp->mac_control.stats_info;
3536 swstats = &stats->sw_stat;
3537
491976b2 3538 /* save link up/down time/cnt, reset/memory/watchdog cnt */
ffb5df6c
JP		 3539 up_cnt = swstats->link_up_cnt;
3540 down_cnt = swstats->link_down_cnt;
3541 up_time = swstats->link_up_time;
3542 down_time = swstats->link_down_time;
3543 reset_cnt = swstats->soft_reset_cnt;
3544 mem_alloc_cnt = swstats->mem_allocated;
3545 mem_free_cnt = swstats->mem_freed;
3546 watchdog_cnt = swstats->watchdog_timer_cnt;
3547
3548 memset(stats, 0, sizeof(struct stat_block));
3549
491976b2 3550 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
ffb5df6c
JP		 3551 swstats->link_up_cnt = up_cnt;
3552 swstats->link_down_cnt = down_cnt;
3553 swstats->link_up_time = up_time;
3554 swstats->link_down_time = down_time;
3555 swstats->soft_reset_cnt = reset_cnt;
3556 swstats->mem_allocated = mem_alloc_cnt;
3557 swstats->mem_freed = mem_free_cnt;
3558 swstats->watchdog_timer_cnt = watchdog_cnt;
20346722 3559
1da177e4
LT		 3560 /* SXE-002: Configure link and activity LED to turn it off */
3561 subid = sp->pdev->subsystem_device;
541ae68f
K		 3562 if (((subid & 0xFF) >= 0x07) &&
3563 (sp->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 3564 val64 = readq(&bar0->gpio_control);
3565 val64 |= 0x0000800000000000ULL;
3566 writeq(val64, &bar0->gpio_control);
3567 val64 = 0x0411040400000000ULL;
509a2671 3568 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 3569 }
3570
541ae68f
K		 3571 /*
3572 * Clear spurious ECC interrupts that would have occured on
3573 * XFRAME II cards after reset.
3574 */
3575 if (sp->device_type == XFRAME_II_DEVICE) {
3576 val64 = readq(&bar0->pcc_err_reg);
3577 writeq(val64, &bar0->pcc_err_reg);
3578 }
3579
f957bcf0 3580 sp->device_enabled_once = false;
1da177e4
LT		 3581}
3582
3583/**
20346722
K		 3584 * s2io_set_swapper - to set the swapper controle on the card
3585 * @sp : private member of the device structure,
1da177e4 3586 * pointer to the s2io_nic structure.
20346722 3587 * Description: Function to set the swapper control on the card
1da177e4
LT		 3588 * correctly depending on the 'endianness' of the system.
3589 * Return value:
3590 * SUCCESS on success and FAILURE on failure.
3591 */
3592
d44570e4 3593static int s2io_set_swapper(struct s2io_nic *sp)
1da177e4
LT		 3594{
3595 struct net_device *dev = sp->dev;
1ee6dd77 3596 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 3597 u64 val64, valt, valr;
3598
20346722 3599 /*
1da177e4
LT		 3600 * Set proper endian settings and verify the same by reading
3601 * the PIF Feed-back register.
3602 */
3603
3604 val64 = readq(&bar0->pif_rd_swapper_fb);
3605 if (val64 != 0x0123456789ABCDEFULL) {
3606 int i = 0;
3607 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3608 0x8100008181000081ULL, /* FE=1, SE=0 */
3609 0x4200004242000042ULL, /* FE=0, SE=1 */
3610 0}; /* FE=0, SE=0 */
3611
d44570e4 3612 while (i < 4) {
1da177e4
LT		 3613 writeq(value[i], &bar0->swapper_ctrl);
3614 val64 = readq(&bar0->pif_rd_swapper_fb);
3615 if (val64 == 0x0123456789ABCDEFULL)
3616 break;
3617 i++;
3618 }
3619 if (i == 4) {
9e39f7c5
JP		 3620 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, "
3621 "feedback read %llx\n",
3622 dev->name, (unsigned long long)val64);
1da177e4
LT		 3623 return FAILURE;
3624 }
3625 valr = value[i];
3626 } else {
3627 valr = readq(&bar0->swapper_ctrl);
3628 }
3629
3630 valt = 0x0123456789ABCDEFULL;
3631 writeq(valt, &bar0->xmsi_address);
3632 val64 = readq(&bar0->xmsi_address);
3633
d44570e4 3634 if (val64 != valt) {
1da177e4
LT		 3635 int i = 0;
3636 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3637 0x0081810000818100ULL, /* FE=1, SE=0 */
3638 0x0042420000424200ULL, /* FE=0, SE=1 */
3639 0}; /* FE=0, SE=0 */
3640
d44570e4 3641 while (i < 4) {
1da177e4
LT		 3642 writeq((value[i] | valr), &bar0->swapper_ctrl);
3643 writeq(valt, &bar0->xmsi_address);
3644 val64 = readq(&bar0->xmsi_address);
d44570e4 3645 if (val64 == valt)
1da177e4
LT		 3646 break;
3647 i++;
3648 }
d44570e4 3649 if (i == 4) {
20346722 3650 unsigned long long x = val64;
9e39f7c5
JP		 3651 DBG_PRINT(ERR_DBG,
3652 "Write failed, Xmsi_addr reads:0x%llx\n", x);
1da177e4
LT		 3653 return FAILURE;
3654 }
3655 }
3656 val64 = readq(&bar0->swapper_ctrl);
3657 val64 &= 0xFFFF000000000000ULL;
3658
d44570e4 3659#ifdef __BIG_ENDIAN
20346722
K		 3660 /*
3661 * The device by default set to a big endian format, so a
1da177e4
LT		 3662 * big endian driver need not set anything.
3663 */
3664 val64 |= (SWAPPER_CTRL_TXP_FE |
d44570e4
JP		 3665 SWAPPER_CTRL_TXP_SE |
3666 SWAPPER_CTRL_TXD_R_FE |
3667 SWAPPER_CTRL_TXD_W_FE |
3668 SWAPPER_CTRL_TXF_R_FE |
3669 SWAPPER_CTRL_RXD_R_FE |
3670 SWAPPER_CTRL_RXD_W_FE |
3671 SWAPPER_CTRL_RXF_W_FE |
3672 SWAPPER_CTRL_XMSI_FE |
3673 SWAPPER_CTRL_STATS_FE |
3674 SWAPPER_CTRL_STATS_SE);
eaae7f72 3675 if (sp->config.intr_type == INTA)
cc6e7c44 3676 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3677 writeq(val64, &bar0->swapper_ctrl);
3678#else
20346722 3679 /*
1da177e4 3680 * Initially we enable all bits to make it accessible by the
20346722 3681 * driver, then we selectively enable only those bits that
1da177e4
LT		 3682 * we want to set.
3683 */
3684 val64 |= (SWAPPER_CTRL_TXP_FE |
d44570e4
JP		 3685 SWAPPER_CTRL_TXP_SE |
3686 SWAPPER_CTRL_TXD_R_FE |
3687 SWAPPER_CTRL_TXD_R_SE |
3688 SWAPPER_CTRL_TXD_W_FE |
3689 SWAPPER_CTRL_TXD_W_SE |
3690 SWAPPER_CTRL_TXF_R_FE |
3691 SWAPPER_CTRL_RXD_R_FE |
3692 SWAPPER_CTRL_RXD_R_SE |
3693 SWAPPER_CTRL_RXD_W_FE |
3694 SWAPPER_CTRL_RXD_W_SE |
3695 SWAPPER_CTRL_RXF_W_FE |
3696 SWAPPER_CTRL_XMSI_FE |
3697 SWAPPER_CTRL_STATS_FE |
3698 SWAPPER_CTRL_STATS_SE);
eaae7f72 3699 if (sp->config.intr_type == INTA)
cc6e7c44 3700 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3701 writeq(val64, &bar0->swapper_ctrl);
3702#endif
3703 val64 = readq(&bar0->swapper_ctrl);
3704
20346722
K		 3705 /*
3706 * Verifying if endian settings are accurate by reading a
1da177e4
LT		 3707 * feedback register.
3708 */
3709 val64 = readq(&bar0->pif_rd_swapper_fb);
3710 if (val64 != 0x0123456789ABCDEFULL) {
3711 /* Endian settings are incorrect, calls for another dekko. */
9e39f7c5
JP		 3712 DBG_PRINT(ERR_DBG,
3713 "%s: Endian settings are wrong, feedback read %llx\n",
3714 dev->name, (unsigned long long)val64);
1da177e4
LT		 3715 return FAILURE;
3716 }
3717
3718 return SUCCESS;
3719}
3720
1ee6dd77 3721static int wait_for_msix_trans(struct s2io_nic *nic, int i)
cc6e7c44 3722{
1ee6dd77 3723 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3724 u64 val64;
3725 int ret = 0, cnt = 0;
3726
3727 do {
3728 val64 = readq(&bar0->xmsi_access);
b7b5a128 3729 if (!(val64 & s2BIT(15)))
cc6e7c44
RA		 3730 break;
3731 mdelay(1);
3732 cnt++;
d44570e4 3733 } while (cnt < 5);
cc6e7c44
RA		 3734 if (cnt == 5) {
3735 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3736 ret = 1;
3737 }
3738
3739 return ret;
3740}
3741
1ee6dd77 3742static void restore_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3743{
1ee6dd77 3744 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44 3745 u64 val64;
f61e0a35
SH		 3746 int i, msix_index;
3747
f61e0a35
SH		 3748 if (nic->device_type == XFRAME_I_DEVICE)
3749 return;
cc6e7c44 3750
d44570e4
JP		 3751 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3752 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
cc6e7c44
RA		 3753 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3754 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
f61e0a35 3755 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
cc6e7c44 3756 writeq(val64, &bar0->xmsi_access);
f61e0a35 3757 if (wait_for_msix_trans(nic, msix_index)) {
9e39f7c5
JP		 3758 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3759 __func__, msix_index);
cc6e7c44
RA		 3760 continue;
3761 }
3762 }
3763}
3764
1ee6dd77 3765static void store_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3766{
1ee6dd77 3767 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44 3768 u64 val64, addr, data;
f61e0a35
SH		 3769 int i, msix_index;
3770
3771 if (nic->device_type == XFRAME_I_DEVICE)
3772 return;
cc6e7c44
RA		 3773
3774 /* Store and display */
d44570e4
JP		 3775 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3776 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
f61e0a35 3777 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
cc6e7c44 3778 writeq(val64, &bar0->xmsi_access);
f61e0a35 3779 if (wait_for_msix_trans(nic, msix_index)) {
9e39f7c5
JP		 3780 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3781 __func__, msix_index);
cc6e7c44
RA		 3782 continue;
3783 }
3784 addr = readq(&bar0->xmsi_address);
3785 data = readq(&bar0->xmsi_data);
3786 if (addr && data) {
3787 nic->msix_info[i].addr = addr;
3788 nic->msix_info[i].data = data;
3789 }
3790 }
3791}
3792
1ee6dd77 3793static int s2io_enable_msi_x(struct s2io_nic *nic)
cc6e7c44 3794{
1ee6dd77 3795 struct XENA_dev_config __iomem *bar0 = nic->bar0;
ac731ab6 3796 u64 rx_mat;
cc6e7c44
RA		 3797 u16 msi_control; /* Temp variable */
3798 int ret, i, j, msix_indx = 1;
4f870320 3799 int size;
ffb5df6c
JP		 3800 struct stat_block *stats = nic->mac_control.stats_info;
3801 struct swStat *swstats = &stats->sw_stat;
cc6e7c44 3802
4f870320 3803 size = nic->num_entries * sizeof(struct msix_entry);
44364a03 3804 nic->entries = kzalloc(size, GFP_KERNEL);
bd684e43 3805 if (!nic->entries) {
d44570e4
JP		 3806 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3807 __func__);
ffb5df6c 3808 swstats->mem_alloc_fail_cnt++;
cc6e7c44
RA		 3809 return -ENOMEM;
3810 }
ffb5df6c 3811 swstats->mem_allocated += size;
f61e0a35 3812
4f870320 3813 size = nic->num_entries * sizeof(struct s2io_msix_entry);
44364a03 3814 nic->s2io_entries = kzalloc(size, GFP_KERNEL);
bd684e43 3815 if (!nic->s2io_entries) {
8a4bdbaa 3816 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
d44570e4 3817 __func__);
ffb5df6c 3818 swstats->mem_alloc_fail_cnt++;
cc6e7c44 3819 kfree(nic->entries);
ffb5df6c 3820 swstats->mem_freed
f61e0a35 3821 += (nic->num_entries * sizeof(struct msix_entry));
cc6e7c44
RA		 3822 return -ENOMEM;
3823 }
ffb5df6c 3824 swstats->mem_allocated += size;
cc6e7c44 3825
ac731ab6
SH		 3826 nic->entries[0].entry = 0;
3827 nic->s2io_entries[0].entry = 0;
3828 nic->s2io_entries[0].in_use = MSIX_FLG;
3829 nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3830 nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3831
f61e0a35
SH		 3832 for (i = 1; i < nic->num_entries; i++) {
3833 nic->entries[i].entry = ((i - 1) * 8) + 1;
3834 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
cc6e7c44
RA		 3835 nic->s2io_entries[i].arg = NULL;
3836 nic->s2io_entries[i].in_use = 0;
3837 }
3838
8a4bdbaa 3839 rx_mat = readq(&bar0->rx_mat);
f61e0a35 3840 for (j = 0; j < nic->config.rx_ring_num; j++) {
8a4bdbaa 3841 rx_mat |= RX_MAT_SET(j, msix_indx);
f61e0a35
SH		 3842 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3843 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3844 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3845 msix_indx += 8;
cc6e7c44 3846 }
8a4bdbaa 3847 writeq(rx_mat, &bar0->rx_mat);
f61e0a35 3848 readq(&bar0->rx_mat);
cc6e7c44 3849
f61e0a35 3850 ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
c92ca04b 3851 /* We fail init if error or we get less vectors than min required */
cc6e7c44 3852 if (ret) {
9e39f7c5 3853 DBG_PRINT(ERR_DBG, "Enabling MSI-X failed\n");
cc6e7c44 3854 kfree(nic->entries);
ffb5df6c
JP		 3855 swstats->mem_freed += nic->num_entries *
3856 sizeof(struct msix_entry);
cc6e7c44 3857 kfree(nic->s2io_entries);
ffb5df6c
JP		 3858 swstats->mem_freed += nic->num_entries *
3859 sizeof(struct s2io_msix_entry);
cc6e7c44
RA		 3860 nic->entries = NULL;
3861 nic->s2io_entries = NULL;
3862 return -ENOMEM;
3863 }
3864
3865 /*
3866 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3867 * in the herc NIC. (Temp change, needs to be removed later)
3868 */
3869 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3870 msi_control |= 0x1; /* Enable MSI */
3871 pci_write_config_word(nic->pdev, 0x42, msi_control);
3872
3873 return 0;
3874}
3875
8abc4d5b 3876/* Handle software interrupt used during MSI(X) test */
33390a70 3877static irqreturn_t s2io_test_intr(int irq, void *dev_id)
8abc4d5b
SS		 3878{
3879 struct s2io_nic *sp = dev_id;
3880
3881 sp->msi_detected = 1;
3882 wake_up(&sp->msi_wait);
3883
3884 return IRQ_HANDLED;
3885}
3886
3887/* Test interrupt path by forcing a a software IRQ */
33390a70 3888static int s2io_test_msi(struct s2io_nic *sp)
8abc4d5b
SS		 3889{
3890 struct pci_dev *pdev = sp->pdev;
3891 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3892 int err;
3893 u64 val64, saved64;
3894
3895 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
d44570e4 3896 sp->name, sp);
8abc4d5b
SS		 3897 if (err) {
3898 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
d44570e4 3899 sp->dev->name, pci_name(pdev), pdev->irq);
8abc4d5b
SS		 3900 return err;
3901 }
3902
d44570e4 3903 init_waitqueue_head(&sp->msi_wait);
8abc4d5b
SS		 3904 sp->msi_detected = 0;
3905
3906 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3907 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3908 val64 |= SCHED_INT_CTRL_TIMER_EN;
3909 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3910 writeq(val64, &bar0->scheduled_int_ctrl);
3911
3912 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3913
3914 if (!sp->msi_detected) {
3915 /* MSI(X) test failed, go back to INTx mode */
2450022a 3916 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
9e39f7c5
JP		 3917 "using MSI(X) during test\n",
3918 sp->dev->name, pci_name(pdev));
8abc4d5b
SS		 3919
3920 err = -EOPNOTSUPP;
3921 }
3922
3923 free_irq(sp->entries[1].vector, sp);
3924
3925 writeq(saved64, &bar0->scheduled_int_ctrl);
3926
3927 return err;
3928}
18b2b7bd
SH		 3929
3930static void remove_msix_isr(struct s2io_nic *sp)
3931{
3932 int i;
3933 u16 msi_control;
3934
f61e0a35 3935 for (i = 0; i < sp->num_entries; i++) {
d44570e4 3936 if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
18b2b7bd
SH		 3937 int vector = sp->entries[i].vector;
3938 void *arg = sp->s2io_entries[i].arg;
3939 free_irq(vector, arg);
3940 }
3941 }
3942
3943 kfree(sp->entries);
3944 kfree(sp->s2io_entries);
3945 sp->entries = NULL;
3946 sp->s2io_entries = NULL;
3947
3948 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3949 msi_control &= 0xFFFE; /* Disable MSI */
3950 pci_write_config_word(sp->pdev, 0x42, msi_control);
3951
3952 pci_disable_msix(sp->pdev);
3953}
3954
3955static void remove_inta_isr(struct s2io_nic *sp)
3956{
3957 struct net_device *dev = sp->dev;
3958
3959 free_irq(sp->pdev->irq, dev);
3960}
3961
1da177e4
LT		 3962/* ********************************************************* *
3963 * Functions defined below concern the OS part of the driver *
3964 * ********************************************************* */
3965
20346722 3966/**
1da177e4
LT		 3967 * s2io_open - open entry point of the driver
3968 * @dev : pointer to the device structure.
3969 * Description:
3970 * This function is the open entry point of the driver. It mainly calls a
3971 * function to allocate Rx buffers and inserts them into the buffer
20346722 3972 * descriptors and then enables the Rx part of the NIC.
1da177e4
LT		 3973 * Return value:
3974 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3975 * file on failure.
3976 */
3977
ac1f60db 3978static int s2io_open(struct net_device *dev)
1da177e4 3979{
4cf1653a 3980 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c 3981 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 3982 int err = 0;
3983
20346722
K		 3984 /*
3985 * Make sure you have link off by default every time
1da177e4
LT		 3986 * Nic is initialized
3987 */
3988 netif_carrier_off(dev);
0b1f7ebe 3989 sp->last_link_state = 0;
1da177e4
LT		 3990
3991 /* Initialize H/W and enable interrupts */
c92ca04b
AR		 3992 err = s2io_card_up(sp);
3993 if (err) {
1da177e4
LT		 3994 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3995 dev->name);
e6a8fee2 3996 goto hw_init_failed;
1da177e4
LT		 3997 }
3998
2fd37688 3999 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
1da177e4 4000 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
e6a8fee2 4001 s2io_card_down(sp);
20346722 4002 err = -ENODEV;
e6a8fee2 4003 goto hw_init_failed;
1da177e4 4004 }
3a3d5756 4005 s2io_start_all_tx_queue(sp);
1da177e4 4006 return 0;
20346722 4007
20346722 4008hw_init_failed:
eaae7f72 4009 if (sp->config.intr_type == MSI_X) {
491976b2 4010 if (sp->entries) {
cc6e7c44 4011 kfree(sp->entries);
ffb5df6c
JP		 4012 swstats->mem_freed += sp->num_entries *
4013 sizeof(struct msix_entry);
491976b2
SH		 4014 }
4015 if (sp->s2io_entries) {
cc6e7c44 4016 kfree(sp->s2io_entries);
ffb5df6c
JP		 4017 swstats->mem_freed += sp->num_entries *
4018 sizeof(struct s2io_msix_entry);
491976b2 4019 }
cc6e7c44 4020 }
20346722 4021 return err;
1da177e4
LT		 4022}
4023
4024/**
4025 * s2io_close -close entry point of the driver
4026 * @dev : device pointer.
4027 * Description:
4028 * This is the stop entry point of the driver. It needs to undo exactly
4029 * whatever was done by the open entry point,thus it's usually referred to
4030 * as the close function.Among other things this function mainly stops the
4031 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4032 * Return value:
4033 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4034 * file on failure.
4035 */
4036
ac1f60db 4037static int s2io_close(struct net_device *dev)
1da177e4 4038{
4cf1653a 4039 struct s2io_nic *sp = netdev_priv(dev);
faa4f796
SH		 4040 struct config_param *config = &sp->config;
4041 u64 tmp64;
4042 int offset;
cc6e7c44 4043
9f74ffde 4044 /* Return if the device is already closed *
d44570e4
JP		 4045 * Can happen when s2io_card_up failed in change_mtu *
4046 */
9f74ffde
SH		 4047 if (!is_s2io_card_up(sp))
4048 return 0;
4049
3a3d5756 4050 s2io_stop_all_tx_queue(sp);
faa4f796
SH		 4051 /* delete all populated mac entries */
4052 for (offset = 1; offset < config->max_mc_addr; offset++) {
4053 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4054 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4055 do_s2io_delete_unicast_mc(sp, tmp64);
4056 }
4057
e6a8fee2 4058 s2io_card_down(sp);
cc6e7c44 4059
1da177e4
LT		 4060 return 0;
4061}
4062
4063/**
4064 * s2io_xmit - Tx entry point of te driver
4065 * @skb : the socket buffer containing the Tx data.
4066 * @dev : device pointer.
4067 * Description :
4068 * This function is the Tx entry point of the driver. S2IO NIC supports
4069 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4070 * NOTE: when device cant queue the pkt,just the trans_start variable will
4071 * not be upadted.
4072 * Return value:
4073 * 0 on success & 1 on failure.
4074 */
4075
61357325 4076static netdev_tx_t s2io_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 4077{
4cf1653a 4078 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 4079 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4080 register u64 val64;
1ee6dd77
RB		 4081 struct TxD *txdp;
4082 struct TxFIFO_element __iomem *tx_fifo;
2fda096d 4083 unsigned long flags = 0;
be3a6b02 4084 u16 vlan_tag = 0;
2fda096d 4085 struct fifo_info *fifo = NULL;
6cfc482b 4086 int do_spin_lock = 1;
75c30b13 4087 int offload_type;
6cfc482b 4088 int enable_per_list_interrupt = 0;
ffb5df6c
JP		 4089 struct config_param *config = &sp->config;
4090 struct mac_info *mac_control = &sp->mac_control;
4091 struct stat_block *stats = mac_control->stats_info;
4092 struct swStat *swstats = &stats->sw_stat;
1da177e4 4093
20346722 4094 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
491976b2
SH		 4095
4096 if (unlikely(skb->len <= 0)) {
9e39f7c5 4097 DBG_PRINT(TX_DBG, "%s: Buffer has no data..\n", dev->name);
491976b2 4098 dev_kfree_skb_any(skb);
6ed10654 4099 return NETDEV_TX_OK;
2fda096d 4100 }
491976b2 4101
92b84437 4102 if (!is_s2io_card_up(sp)) {
20346722 4103 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
1da177e4 4104 dev->name);
20346722 4105 dev_kfree_skb(skb);
6ed10654 4106 return NETDEV_TX_OK;
1da177e4
LT		 4107 }
4108
4109 queue = 0;
3a3d5756 4110 if (sp->vlgrp && vlan_tx_tag_present(skb))
be3a6b02 4111 vlan_tag = vlan_tx_tag_get(skb);
6cfc482b
SH		 4112 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4113 if (skb->protocol == htons(ETH_P_IP)) {
4114 struct iphdr *ip;
4115 struct tcphdr *th;
4116 ip = ip_hdr(skb);
4117
4118 if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4119 th = (struct tcphdr *)(((unsigned char *)ip) +
d44570e4 4120 ip->ihl*4);
6cfc482b
SH		 4121
4122 if (ip->protocol == IPPROTO_TCP) {
4123 queue_len = sp->total_tcp_fifos;
4124 queue = (ntohs(th->source) +
d44570e4
JP		 4125 ntohs(th->dest)) &
4126 sp->fifo_selector[queue_len - 1];
6cfc482b
SH		 4127 if (queue >= queue_len)
4128 queue = queue_len - 1;
4129 } else if (ip->protocol == IPPROTO_UDP) {
4130 queue_len = sp->total_udp_fifos;
4131 queue = (ntohs(th->source) +
d44570e4
JP		 4132 ntohs(th->dest)) &
4133 sp->fifo_selector[queue_len - 1];
6cfc482b
SH		 4134 if (queue >= queue_len)
4135 queue = queue_len - 1;
4136 queue += sp->udp_fifo_idx;
4137 if (skb->len > 1024)
4138 enable_per_list_interrupt = 1;
4139 do_spin_lock = 0;
4140 }
4141 }
4142 }
4143 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4144 /* get fifo number based on skb->priority value */
4145 queue = config->fifo_mapping
d44570e4 4146 [skb->priority & (MAX_TX_FIFOS - 1)];
6cfc482b 4147 fifo = &mac_control->fifos[queue];
3a3d5756 4148
6cfc482b
SH		 4149 if (do_spin_lock)
4150 spin_lock_irqsave(&fifo->tx_lock, flags);
4151 else {
4152 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4153 return NETDEV_TX_LOCKED;
4154 }
be3a6b02 4155
3a3d5756
SH		 4156 if (sp->config.multiq) {
4157 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4158 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4159 return NETDEV_TX_BUSY;
4160 }
b19fa1fa 4161 } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
3a3d5756
SH		 4162 if (netif_queue_stopped(dev)) {
4163 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4164 return NETDEV_TX_BUSY;
4165 }
4166 }
4167
d44570e4
JP		 4168 put_off = (u16)fifo->tx_curr_put_info.offset;
4169 get_off = (u16)fifo->tx_curr_get_info.offset;
4170 txdp = (struct TxD *)fifo->list_info[put_off].list_virt_addr;
20346722 4171
2fda096d 4172 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
1da177e4 4173 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4174 if (txdp->Host_Control ||
d44570e4 4175 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
776bd20f 4176 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3a3d5756 4177 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4178 dev_kfree_skb(skb);
2fda096d 4179 spin_unlock_irqrestore(&fifo->tx_lock, flags);
6ed10654 4180 return NETDEV_TX_OK;
1da177e4 4181 }
0b1f7ebe 4182
75c30b13 4183 offload_type = s2io_offload_type(skb);
75c30b13 4184 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1da177e4 4185 txdp->Control_1 |= TXD_TCP_LSO_EN;
75c30b13 4186 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
1da177e4 4187 }
84fa7933 4188 if (skb->ip_summed == CHECKSUM_PARTIAL) {
d44570e4
JP		 4189 txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4190 TXD_TX_CKO_TCP_EN |
4191 TXD_TX_CKO_UDP_EN);
1da177e4 4192 }
fed5eccd
AR		 4193 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4194 txdp->Control_1 |= TXD_LIST_OWN_XENA;
2fda096d 4195 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
6cfc482b
SH		 4196 if (enable_per_list_interrupt)
4197 if (put_off & (queue_len >> 5))
4198 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
3a3d5756 4199 if (vlan_tag) {
be3a6b02
K		 4200 txdp->Control_2 |= TXD_VLAN_ENABLE;
4201 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4202 }
4203
e743d313 4204 frg_len = skb_headlen(skb);
75c30b13 4205 if (offload_type == SKB_GSO_UDP) {
fed5eccd
AR		 4206 int ufo_size;
4207
75c30b13 4208 ufo_size = s2io_udp_mss(skb);
fed5eccd
AR		 4209 ufo_size &= ~7;
4210 txdp->Control_1 |= TXD_UFO_EN;
4211 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4212 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4213#ifdef __BIG_ENDIAN
3459feb8 4214 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
2fda096d 4215 fifo->ufo_in_band_v[put_off] =
d44570e4 4216 (__force u64)skb_shinfo(skb)->ip6_frag_id;
fed5eccd 4217#else
2fda096d 4218 fifo->ufo_in_band_v[put_off] =
d44570e4 4219 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
fed5eccd 4220#endif
2fda096d 4221 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
fed5eccd 4222 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
d44570e4
JP		 4223 fifo->ufo_in_band_v,
4224 sizeof(u64),
4225 PCI_DMA_TODEVICE);
8d8bb39b 4226 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
491abf25 4227 goto pci_map_failed;
fed5eccd 4228 txdp++;
fed5eccd 4229 }
1da177e4 4230
d44570e4
JP		 4231 txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data,
4232 frg_len, PCI_DMA_TODEVICE);
8d8bb39b 4233 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
491abf25
VP		 4234 goto pci_map_failed;
4235
d44570e4 4236 txdp->Host_Control = (unsigned long)skb;
fed5eccd 4237 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
75c30b13 4238 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4239 txdp->Control_1 |= TXD_UFO_EN;
4240
4241 frg_cnt = skb_shinfo(skb)->nr_frags;
1da177e4
LT		 4242 /* For fragmented SKB. */
4243 for (i = 0; i < frg_cnt; i++) {
4244 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0b1f7ebe
K		 4245 /* A '0' length fragment will be ignored */
4246 if (!frag->size)
4247 continue;
1da177e4 4248 txdp++;
d44570e4
JP		 4249 txdp->Buffer_Pointer = (u64)pci_map_page(sp->pdev, frag->page,
4250 frag->page_offset,
4251 frag->size,
4252 PCI_DMA_TODEVICE);
efd51b5c 4253 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
75c30b13 4254 if (offload_type == SKB_GSO_UDP)
fed5eccd 4255 txdp->Control_1 |= TXD_UFO_EN;
1da177e4
LT		 4256 }
4257 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4258
75c30b13 4259 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4260 frg_cnt++; /* as Txd0 was used for inband header */
4261
1da177e4 4262 tx_fifo = mac_control->tx_FIFO_start[queue];
2fda096d 4263 val64 = fifo->list_info[put_off].list_phy_addr;
1da177e4
LT		 4264 writeq(val64, &tx_fifo->TxDL_Pointer);
4265
4266 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4267 TX_FIFO_LAST_LIST);
75c30b13 4268 if (offload_type)
fed5eccd 4269 val64 |= TX_FIFO_SPECIAL_FUNC;
75c30b13 4270
1da177e4
LT		 4271 writeq(val64, &tx_fifo->List_Control);
4272
303bcb4b
K		 4273 mmiowb();
4274
1da177e4 4275 put_off++;
2fda096d 4276 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
863c11a9 4277 put_off = 0;
2fda096d 4278 fifo->tx_curr_put_info.offset = put_off;
1da177e4
LT		 4279
4280 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4281 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
ffb5df6c 4282 swstats->fifo_full_cnt++;
1da177e4
LT		 4283 DBG_PRINT(TX_DBG,
4284 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4285 put_off, get_off);
3a3d5756 4286 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4287 }
ffb5df6c 4288 swstats->mem_allocated += skb->truesize;
2fda096d 4289 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4 4290
f6f4bfa3
SH		 4291 if (sp->config.intr_type == MSI_X)
4292 tx_intr_handler(fifo);
4293
6ed10654 4294 return NETDEV_TX_OK;
ffb5df6c 4295
491abf25 4296pci_map_failed:
ffb5df6c 4297 swstats->pci_map_fail_cnt++;
3a3d5756 4298 s2io_stop_tx_queue(sp, fifo->fifo_no);
ffb5df6c 4299 swstats->mem_freed += skb->truesize;
491abf25 4300 dev_kfree_skb(skb);
2fda096d 4301 spin_unlock_irqrestore(&fifo->tx_lock, flags);
6ed10654 4302 return NETDEV_TX_OK;
1da177e4
LT		 4303}
4304
25fff88e
K		 4305static void
4306s2io_alarm_handle(unsigned long data)
4307{
1ee6dd77 4308 struct s2io_nic *sp = (struct s2io_nic *)data;
8116f3cf 4309 struct net_device *dev = sp->dev;
25fff88e 4310
8116f3cf 4311 s2io_handle_errors(dev);
25fff88e
K		 4312 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4313}
4314
7d12e780 4315static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
cc6e7c44 4316{
1ee6dd77
RB		 4317 struct ring_info *ring = (struct ring_info *)dev_id;
4318 struct s2io_nic *sp = ring->nic;
f61e0a35 4319 struct XENA_dev_config __iomem *bar0 = sp->bar0;
cc6e7c44 4320
f61e0a35 4321 if (unlikely(!is_s2io_card_up(sp)))
92b84437 4322 return IRQ_HANDLED;
92b84437 4323
f61e0a35 4324 if (sp->config.napi) {
1a79d1c3
AV		 4325 u8 __iomem *addr = NULL;
4326 u8 val8 = 0;
f61e0a35 4327
1a79d1c3 4328 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
f61e0a35
SH		 4329 addr += (7 - ring->ring_no);
4330 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4331 writeb(val8, addr);
4332 val8 = readb(addr);
288379f0 4333 napi_schedule(&ring->napi);
f61e0a35
SH		 4334 } else {
4335 rx_intr_handler(ring, 0);
8d8bb39b 4336 s2io_chk_rx_buffers(sp, ring);
f61e0a35 4337 }
7d3d0439 4338
cc6e7c44
RA		 4339 return IRQ_HANDLED;
4340}
4341
7d12e780 4342static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
cc6e7c44 4343{
ac731ab6
SH		 4344 int i;
4345 struct fifo_info *fifos = (struct fifo_info *)dev_id;
4346 struct s2io_nic *sp = fifos->nic;
4347 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4348 struct config_param *config = &sp->config;
4349 u64 reason;
cc6e7c44 4350
ac731ab6
SH		 4351 if (unlikely(!is_s2io_card_up(sp)))
4352 return IRQ_NONE;
4353
4354 reason = readq(&bar0->general_int_status);
4355 if (unlikely(reason == S2IO_MINUS_ONE))
4356 /* Nothing much can be done. Get out */
92b84437 4357 return IRQ_HANDLED;
92b84437 4358
01e16faa
SH		 4359 if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4360 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
ac731ab6 4361
01e16faa
SH		 4362 if (reason & GEN_INTR_TXPIC)
4363 s2io_txpic_intr_handle(sp);
ac731ab6 4364
01e16faa
SH		 4365 if (reason & GEN_INTR_TXTRAFFIC)
4366 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
ac731ab6 4367
01e16faa
SH		 4368 for (i = 0; i < config->tx_fifo_num; i++)
4369 tx_intr_handler(&fifos[i]);
ac731ab6 4370
01e16faa
SH		 4371 writeq(sp->general_int_mask, &bar0->general_int_mask);
4372 readl(&bar0->general_int_status);
4373 return IRQ_HANDLED;
4374 }
4375 /* The interrupt was not raised by us */
4376 return IRQ_NONE;
cc6e7c44 4377}
ac731ab6 4378
1ee6dd77 4379static void s2io_txpic_intr_handle(struct s2io_nic *sp)
a371a07d 4380{
1ee6dd77 4381 struct XENA_dev_config __iomem *bar0 = sp->bar0;
a371a07d
K		 4382 u64 val64;
4383
4384 val64 = readq(&bar0->pic_int_status);
4385 if (val64 & PIC_INT_GPIO) {
4386 val64 = readq(&bar0->gpio_int_reg);
4387 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4388 (val64 & GPIO_INT_REG_LINK_UP)) {
c92ca04b
AR		 4389 /*
4390 * This is unstable state so clear both up/down
4391 * interrupt and adapter to re-evaluate the link state.
4392 */
d44570e4 4393 val64 |= GPIO_INT_REG_LINK_DOWN;
a371a07d
K		 4394 val64 |= GPIO_INT_REG_LINK_UP;
4395 writeq(val64, &bar0->gpio_int_reg);
a371a07d 4396 val64 = readq(&bar0->gpio_int_mask);
c92ca04b
AR		 4397 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4398 GPIO_INT_MASK_LINK_DOWN);
a371a07d 4399 writeq(val64, &bar0->gpio_int_mask);
d44570e4 4400 } else if (val64 & GPIO_INT_REG_LINK_UP) {
c92ca04b 4401 val64 = readq(&bar0->adapter_status);
d44570e4 4402 /* Enable Adapter */
19a60522
SS		 4403 val64 = readq(&bar0->adapter_control);
4404 val64 |= ADAPTER_CNTL_EN;
4405 writeq(val64, &bar0->adapter_control);
4406 val64 |= ADAPTER_LED_ON;
4407 writeq(val64, &bar0->adapter_control);
4408 if (!sp->device_enabled_once)
4409 sp->device_enabled_once = 1;
c92ca04b 4410
19a60522
SS		 4411 s2io_link(sp, LINK_UP);
4412 /*
4413 * unmask link down interrupt and mask link-up
4414 * intr
4415 */
4416 val64 = readq(&bar0->gpio_int_mask);
4417 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4418 val64 |= GPIO_INT_MASK_LINK_UP;
4419 writeq(val64, &bar0->gpio_int_mask);
c92ca04b 4420
d44570e4 4421 } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
c92ca04b 4422 val64 = readq(&bar0->adapter_status);
19a60522
SS		 4423 s2io_link(sp, LINK_DOWN);
4424 /* Link is down so unmaks link up interrupt */
4425 val64 = readq(&bar0->gpio_int_mask);
4426 val64 &= ~GPIO_INT_MASK_LINK_UP;
4427 val64 |= GPIO_INT_MASK_LINK_DOWN;
4428 writeq(val64, &bar0->gpio_int_mask);
ac1f90d6
SS		 4429
4430 /* turn off LED */
4431 val64 = readq(&bar0->adapter_control);
d44570e4 4432 val64 = val64 & (~ADAPTER_LED_ON);
ac1f90d6 4433 writeq(val64, &bar0->adapter_control);
a371a07d
K		 4434 }
4435 }
c92ca04b 4436 val64 = readq(&bar0->gpio_int_mask);
a371a07d
K		 4437}
4438
8116f3cf
SS		 4439/**
4440 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4441 * @value: alarm bits
4442 * @addr: address value
4443 * @cnt: counter variable
4444 * Description: Check for alarm and increment the counter
4445 * Return Value:
4446 * 1 - if alarm bit set
4447 * 0 - if alarm bit is not set
4448 */
d44570e4
JP		 4449static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4450 unsigned long long *cnt)
8116f3cf
SS		 4451{
4452 u64 val64;
4453 val64 = readq(addr);
d44570e4 4454 if (val64 & value) {
8116f3cf
SS		 4455 writeq(val64, addr);
4456 (*cnt)++;
4457 return 1;
4458 }
4459 return 0;
4460
4461}
4462
4463/**
4464 * s2io_handle_errors - Xframe error indication handler
4465 * @nic: device private variable
4466 * Description: Handle alarms such as loss of link, single or
4467 * double ECC errors, critical and serious errors.
4468 * Return Value:
4469 * NONE
4470 */
d44570e4 4471static void s2io_handle_errors(void *dev_id)
8116f3cf 4472{
d44570e4 4473 struct net_device *dev = (struct net_device *)dev_id;
4cf1653a 4474 struct s2io_nic *sp = netdev_priv(dev);
8116f3cf 4475 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d44570e4 4476 u64 temp64 = 0, val64 = 0;
8116f3cf
SS		 4477 int i = 0;
4478
4479 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4480 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4481
92b84437 4482 if (!is_s2io_card_up(sp))
8116f3cf
SS		 4483 return;
4484
4485 if (pci_channel_offline(sp->pdev))
4486 return;
4487
4488 memset(&sw_stat->ring_full_cnt, 0,
d44570e4 4489 sizeof(sw_stat->ring_full_cnt));
8116f3cf
SS		 4490
4491 /* Handling the XPAK counters update */
d44570e4 4492 if (stats->xpak_timer_count < 72000) {
8116f3cf
SS		 4493 /* waiting for an hour */
4494 stats->xpak_timer_count++;
4495 } else {
4496 s2io_updt_xpak_counter(dev);
4497 /* reset the count to zero */
4498 stats->xpak_timer_count = 0;
4499 }
4500
4501 /* Handling link status change error Intr */
4502 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4503 val64 = readq(&bar0->mac_rmac_err_reg);
4504 writeq(val64, &bar0->mac_rmac_err_reg);
4505 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4506 schedule_work(&sp->set_link_task);
4507 }
4508
4509 /* In case of a serious error, the device will be Reset. */
4510 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
d44570e4 4511 &sw_stat->serious_err_cnt))
8116f3cf
SS		 4512 goto reset;
4513
4514 /* Check for data parity error */
4515 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
d44570e4 4516 &sw_stat->parity_err_cnt))
8116f3cf
SS		 4517 goto reset;
4518
4519 /* Check for ring full counter */
4520 if (sp->device_type == XFRAME_II_DEVICE) {
4521 val64 = readq(&bar0->ring_bump_counter1);
d44570e4
JP		 4522 for (i = 0; i < 4; i++) {
4523 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
8116f3cf
SS		 4524 temp64 >>= 64 - ((i+1)*16);
4525 sw_stat->ring_full_cnt[i] += temp64;
4526 }
4527
4528 val64 = readq(&bar0->ring_bump_counter2);
d44570e4
JP		 4529 for (i = 0; i < 4; i++) {
4530 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
8116f3cf 4531 temp64 >>= 64 - ((i+1)*16);
d44570e4 4532 sw_stat->ring_full_cnt[i+4] += temp64;
8116f3cf
SS		 4533 }
4534 }
4535
4536 val64 = readq(&bar0->txdma_int_status);
4537 /*check for pfc_err*/
4538 if (val64 & TXDMA_PFC_INT) {
d44570e4
JP		 4539 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4540 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4541 PFC_PCIX_ERR,
4542 &bar0->pfc_err_reg,
4543 &sw_stat->pfc_err_cnt))
8116f3cf 4544 goto reset;
d44570e4
JP		 4545 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4546 &bar0->pfc_err_reg,
4547 &sw_stat->pfc_err_cnt);
8116f3cf
SS		 4548 }
4549
4550 /*check for tda_err*/
4551 if (val64 & TXDMA_TDA_INT) {
d44570e4
JP		 4552 if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4553 TDA_SM0_ERR_ALARM |
4554 TDA_SM1_ERR_ALARM,
4555 &bar0->tda_err_reg,
4556 &sw_stat->tda_err_cnt))
8116f3cf
SS		 4557 goto reset;
4558 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
d44570e4
JP		 4559 &bar0->tda_err_reg,
4560 &sw_stat->tda_err_cnt);
8116f3cf
SS		 4561 }
4562 /*check for pcc_err*/
4563 if (val64 & TXDMA_PCC_INT) {
d44570e4
JP		 4564 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4565 PCC_N_SERR | PCC_6_COF_OV_ERR |
4566 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4567 PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4568 PCC_TXB_ECC_DB_ERR,
4569 &bar0->pcc_err_reg,
4570 &sw_stat->pcc_err_cnt))
8116f3cf
SS		 4571 goto reset;
4572 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
d44570e4
JP		 4573 &bar0->pcc_err_reg,
4574 &sw_stat->pcc_err_cnt);
8116f3cf
SS		 4575 }
4576
4577 /*check for tti_err*/
4578 if (val64 & TXDMA_TTI_INT) {
d44570e4
JP		 4579 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4580 &bar0->tti_err_reg,
4581 &sw_stat->tti_err_cnt))
8116f3cf
SS		 4582 goto reset;
4583 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
d44570e4
JP		 4584 &bar0->tti_err_reg,
4585 &sw_stat->tti_err_cnt);
8116f3cf
SS		 4586 }
4587
4588 /*check for lso_err*/
4589 if (val64 & TXDMA_LSO_INT) {
d44570e4
JP		 4590 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4591 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4592 &bar0->lso_err_reg,
4593 &sw_stat->lso_err_cnt))
8116f3cf
SS		 4594 goto reset;
4595 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
d44570e4
JP		 4596 &bar0->lso_err_reg,
4597 &sw_stat->lso_err_cnt);
8116f3cf
SS		 4598 }
4599
4600 /*check for tpa_err*/
4601 if (val64 & TXDMA_TPA_INT) {
d44570e4
JP		 4602 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4603 &bar0->tpa_err_reg,
4604 &sw_stat->tpa_err_cnt))
8116f3cf 4605 goto reset;
d44570e4
JP		 4606 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4607 &bar0->tpa_err_reg,
4608 &sw_stat->tpa_err_cnt);
8116f3cf
SS		 4609 }
4610
4611 /*check for sm_err*/
4612 if (val64 & TXDMA_SM_INT) {
d44570e4
JP		 4613 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4614 &bar0->sm_err_reg,
4615 &sw_stat->sm_err_cnt))
8116f3cf
SS		 4616 goto reset;
4617 }
4618
4619 val64 = readq(&bar0->mac_int_status);
4620 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4621 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
d44570e4
JP		 4622 &bar0->mac_tmac_err_reg,
4623 &sw_stat->mac_tmac_err_cnt))
8116f3cf 4624 goto reset;
d44570e4
JP		 4625 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4626 TMAC_DESC_ECC_SG_ERR |
4627 TMAC_DESC_ECC_DB_ERR,
4628 &bar0->mac_tmac_err_reg,
4629 &sw_stat->mac_tmac_err_cnt);
8116f3cf
SS		 4630 }
4631
4632 val64 = readq(&bar0->xgxs_int_status);
4633 if (val64 & XGXS_INT_STATUS_TXGXS) {
4634 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
d44570e4
JP		 4635 &bar0->xgxs_txgxs_err_reg,
4636 &sw_stat->xgxs_txgxs_err_cnt))
8116f3cf
SS		 4637 goto reset;
4638 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
d44570e4
JP		 4639 &bar0->xgxs_txgxs_err_reg,
4640 &sw_stat->xgxs_txgxs_err_cnt);
8116f3cf
SS		 4641 }
4642
4643 val64 = readq(&bar0->rxdma_int_status);
4644 if (val64 & RXDMA_INT_RC_INT_M) {
d44570e4
JP		 4645 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4646 RC_FTC_ECC_DB_ERR |
4647 RC_PRCn_SM_ERR_ALARM |
4648 RC_FTC_SM_ERR_ALARM,
4649 &bar0->rc_err_reg,
4650 &sw_stat->rc_err_cnt))
8116f3cf 4651 goto reset;
d44570e4
JP		 4652 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4653 RC_FTC_ECC_SG_ERR |
4654 RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4655 &sw_stat->rc_err_cnt);
4656 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4657 PRC_PCI_AB_WR_Rn |
4658 PRC_PCI_AB_F_WR_Rn,
4659 &bar0->prc_pcix_err_reg,
4660 &sw_stat->prc_pcix_err_cnt))
8116f3cf 4661 goto reset;
d44570e4
JP		 4662 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4663 PRC_PCI_DP_WR_Rn |
4664 PRC_PCI_DP_F_WR_Rn,
4665 &bar0->prc_pcix_err_reg,
4666 &sw_stat->prc_pcix_err_cnt);
8116f3cf
SS		 4667 }
4668
4669 if (val64 & RXDMA_INT_RPA_INT_M) {
4670 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
d44570e4
JP		 4671 &bar0->rpa_err_reg,
4672 &sw_stat->rpa_err_cnt))
8116f3cf
SS		 4673 goto reset;
4674 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
d44570e4
JP		 4675 &bar0->rpa_err_reg,
4676 &sw_stat->rpa_err_cnt);
8116f3cf
SS		 4677 }
4678
4679 if (val64 & RXDMA_INT_RDA_INT_M) {
d44570e4
JP		 4680 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4681 RDA_FRM_ECC_DB_N_AERR |
4682 RDA_SM1_ERR_ALARM |
4683 RDA_SM0_ERR_ALARM |
4684 RDA_RXD_ECC_DB_SERR,
4685 &bar0->rda_err_reg,
4686 &sw_stat->rda_err_cnt))
8116f3cf 4687 goto reset;
d44570e4
JP		 4688 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4689 RDA_FRM_ECC_SG_ERR |
4690 RDA_MISC_ERR |
4691 RDA_PCIX_ERR,
4692 &bar0->rda_err_reg,
4693 &sw_stat->rda_err_cnt);
8116f3cf
SS		 4694 }
4695
4696 if (val64 & RXDMA_INT_RTI_INT_M) {
d44570e4
JP		 4697 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4698 &bar0->rti_err_reg,
4699 &sw_stat->rti_err_cnt))
8116f3cf
SS		 4700 goto reset;
4701 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
d44570e4
JP		 4702 &bar0->rti_err_reg,
4703 &sw_stat->rti_err_cnt);
8116f3cf
SS		 4704 }
4705
4706 val64 = readq(&bar0->mac_int_status);
4707 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4708 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
d44570e4
JP		 4709 &bar0->mac_rmac_err_reg,
4710 &sw_stat->mac_rmac_err_cnt))
8116f3cf 4711 goto reset;
d44570e4
JP		 4712 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4713 RMAC_SINGLE_ECC_ERR |
4714 RMAC_DOUBLE_ECC_ERR,
4715 &bar0->mac_rmac_err_reg,
4716 &sw_stat->mac_rmac_err_cnt);
8116f3cf
SS		 4717 }
4718
4719 val64 = readq(&bar0->xgxs_int_status);
4720 if (val64 & XGXS_INT_STATUS_RXGXS) {
4721 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
d44570e4
JP		 4722 &bar0->xgxs_rxgxs_err_reg,
4723 &sw_stat->xgxs_rxgxs_err_cnt))
8116f3cf
SS		 4724 goto reset;
4725 }
4726
4727 val64 = readq(&bar0->mc_int_status);
d44570e4
JP		 4728 if (val64 & MC_INT_STATUS_MC_INT) {
4729 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4730 &bar0->mc_err_reg,
4731 &sw_stat->mc_err_cnt))
8116f3cf
SS		 4732 goto reset;
4733
4734 /* Handling Ecc errors */
4735 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4736 writeq(val64, &bar0->mc_err_reg);
4737 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4738 sw_stat->double_ecc_errs++;
4739 if (sp->device_type != XFRAME_II_DEVICE) {
4740 /*
4741 * Reset XframeI only if critical error
4742 */
4743 if (val64 &
d44570e4
JP		 4744 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4745 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4746 goto reset;
4747 }
8116f3cf
SS		 4748 } else
4749 sw_stat->single_ecc_errs++;
4750 }
4751 }
4752 return;
4753
4754reset:
3a3d5756 4755 s2io_stop_all_tx_queue(sp);
8116f3cf
SS		 4756 schedule_work(&sp->rst_timer_task);
4757 sw_stat->soft_reset_cnt++;
8116f3cf
SS		 4758}
4759
1da177e4
LT		 4760/**
4761 * s2io_isr - ISR handler of the device .
4762 * @irq: the irq of the device.
4763 * @dev_id: a void pointer to the dev structure of the NIC.
20346722
K		 4764 * Description: This function is the ISR handler of the device. It
4765 * identifies the reason for the interrupt and calls the relevant
4766 * service routines. As a contongency measure, this ISR allocates the
1da177e4
LT		 4767 * recv buffers, if their numbers are below the panic value which is
4768 * presently set to 25% of the original number of rcv buffers allocated.
4769 * Return value:
20346722 4770 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
1da177e4
LT		 4771 * IRQ_NONE: will be returned if interrupt is not from our device
4772 */
7d12e780 4773static irqreturn_t s2io_isr(int irq, void *dev_id)
1da177e4 4774{
d44570e4 4775 struct net_device *dev = (struct net_device *)dev_id;
4cf1653a 4776 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 4777 struct XENA_dev_config __iomem *bar0 = sp->bar0;
20346722 4778 int i;
19a60522 4779 u64 reason = 0;
1ee6dd77 4780 struct mac_info *mac_control;
1da177e4
LT		 4781 struct config_param *config;
4782
d796fdb7
LV		 4783 /* Pretend we handled any irq's from a disconnected card */
4784 if (pci_channel_offline(sp->pdev))
4785 return IRQ_NONE;
4786
596c5c97 4787 if (!is_s2io_card_up(sp))
92b84437 4788 return IRQ_NONE;
92b84437 4789
1da177e4 4790 config = &sp->config;
ffb5df6c 4791 mac_control = &sp->mac_control;
1da177e4 4792
20346722 4793 /*
1da177e4
LT		 4794 * Identify the cause for interrupt and call the appropriate
4795 * interrupt handler. Causes for the interrupt could be;
4796 * 1. Rx of packet.
4797 * 2. Tx complete.
4798 * 3. Link down.
1da177e4
LT		 4799 */
4800 reason = readq(&bar0->general_int_status);
4801
d44570e4
JP		 4802 if (unlikely(reason == S2IO_MINUS_ONE))
4803 return IRQ_HANDLED; /* Nothing much can be done. Get out */
5d3213cc 4804
d44570e4
JP		 4805 if (reason &
4806 (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
596c5c97
SS		 4807 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4808
4809 if (config->napi) {
4810 if (reason & GEN_INTR_RXTRAFFIC) {
288379f0 4811 napi_schedule(&sp->napi);
f61e0a35
SH		 4812 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4813 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4814 readl(&bar0->rx_traffic_int);
db874e65 4815 }
596c5c97
SS		 4816 } else {
4817 /*
4818 * rx_traffic_int reg is an R1 register, writing all 1's
4819 * will ensure that the actual interrupt causing bit
4820 * get's cleared and hence a read can be avoided.
4821 */
4822 if (reason & GEN_INTR_RXTRAFFIC)
19a60522 4823 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
596c5c97 4824
13d866a9
JP		 4825 for (i = 0; i < config->rx_ring_num; i++) {
4826 struct ring_info *ring = &mac_control->rings[i];
4827
4828 rx_intr_handler(ring, 0);
4829 }
db874e65 4830 }
596c5c97 4831
db874e65 4832 /*
596c5c97 4833 * tx_traffic_int reg is an R1 register, writing all 1's
db874e65
SS		 4834 * will ensure that the actual interrupt causing bit get's
4835 * cleared and hence a read can be avoided.
4836 */
596c5c97
SS		 4837 if (reason & GEN_INTR_TXTRAFFIC)
4838 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
19a60522 4839
596c5c97
SS		 4840 for (i = 0; i < config->tx_fifo_num; i++)
4841 tx_intr_handler(&mac_control->fifos[i]);
1da177e4 4842
596c5c97
SS		 4843 if (reason & GEN_INTR_TXPIC)
4844 s2io_txpic_intr_handle(sp);
fe113638 4845
596c5c97
SS		 4846 /*
4847 * Reallocate the buffers from the interrupt handler itself.
4848 */
4849 if (!config->napi) {
13d866a9
JP		 4850 for (i = 0; i < config->rx_ring_num; i++) {
4851 struct ring_info *ring = &mac_control->rings[i];
4852
4853 s2io_chk_rx_buffers(sp, ring);
4854 }
596c5c97
SS		 4855 }
4856 writeq(sp->general_int_mask, &bar0->general_int_mask);
4857 readl(&bar0->general_int_status);
20346722 4858
596c5c97 4859 return IRQ_HANDLED;
db874e65 4860
d44570e4 4861 } else if (!reason) {
596c5c97
SS		 4862 /* The interrupt was not raised by us */
4863 return IRQ_NONE;
4864 }
db874e65 4865
1da177e4
LT		 4866 return IRQ_HANDLED;
4867}
4868
7ba013ac
K		 4869/**
4870 * s2io_updt_stats -
4871 */
1ee6dd77 4872static void s2io_updt_stats(struct s2io_nic *sp)
7ba013ac 4873{
1ee6dd77 4874 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7ba013ac
K		 4875 u64 val64;
4876 int cnt = 0;
4877
92b84437 4878 if (is_s2io_card_up(sp)) {
7ba013ac
K		 4879 /* Apprx 30us on a 133 MHz bus */
4880 val64 = SET_UPDT_CLICKS(10) |
4881 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4882 writeq(val64, &bar0->stat_cfg);
4883 do {
4884 udelay(100);
4885 val64 = readq(&bar0->stat_cfg);
b7b5a128 4886 if (!(val64 & s2BIT(0)))
7ba013ac
K		 4887 break;
4888 cnt++;
4889 if (cnt == 5)
4890 break; /* Updt failed */
d44570e4 4891 } while (1);
8a4bdbaa 4892 }
7ba013ac
K		 4893}
4894
1da177e4 4895/**
20346722 4896 * s2io_get_stats - Updates the device statistics structure.
1da177e4
LT		 4897 * @dev : pointer to the device structure.
4898 * Description:
20346722 4899 * This function updates the device statistics structure in the s2io_nic
1da177e4
LT		 4900 * structure and returns a pointer to the same.
4901 * Return value:
4902 * pointer to the updated net_device_stats structure.
4903 */
4904
ac1f60db 4905static struct net_device_stats *s2io_get_stats(struct net_device *dev)
1da177e4 4906{
4cf1653a 4907 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c
JP		 4908 struct config_param *config = &sp->config;
4909 struct mac_info *mac_control = &sp->mac_control;
4910 struct stat_block *stats = mac_control->stats_info;
0425b46a 4911 int i;
1da177e4 4912
7ba013ac
K		 4913 /* Configure Stats for immediate updt */
4914 s2io_updt_stats(sp);
4915
dc56e634
BL		 4916 /* Using sp->stats as a staging area, because reset (due to mtu
4917 change, for example) will clear some hardware counters */
ffb5df6c 4918 dev->stats.tx_packets += le32_to_cpu(stats->tmac_frms) -
dc56e634 4919 sp->stats.tx_packets;
ffb5df6c
JP		 4920 sp->stats.tx_packets = le32_to_cpu(stats->tmac_frms);
4921
4922 dev->stats.tx_errors += le32_to_cpu(stats->tmac_any_err_frms) -
dc56e634 4923 sp->stats.tx_errors;
ffb5df6c
JP		 4924 sp->stats.tx_errors = le32_to_cpu(stats->tmac_any_err_frms);
4925
4926 dev->stats.rx_errors += le64_to_cpu(stats->rmac_drop_frms) -
dc56e634 4927 sp->stats.rx_errors;
ffb5df6c
JP		 4928 sp->stats.rx_errors = le64_to_cpu(stats->rmac_drop_frms);
4929
4930 dev->stats.multicast = le32_to_cpu(stats->rmac_vld_mcst_frms) -
dc56e634 4931 sp->stats.multicast;
ffb5df6c
JP		 4932 sp->stats.multicast = le32_to_cpu(stats->rmac_vld_mcst_frms);
4933
4934 dev->stats.rx_length_errors = le64_to_cpu(stats->rmac_long_frms) -
dc56e634 4935 sp->stats.rx_length_errors;
ffb5df6c 4936 sp->stats.rx_length_errors = le64_to_cpu(stats->rmac_long_frms);
1da177e4 4937
0425b46a 4938 /* collect per-ring rx_packets and rx_bytes */
dc56e634 4939 dev->stats.rx_packets = dev->stats.rx_bytes = 0;
0425b46a 4940 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 4941 struct ring_info *ring = &mac_control->rings[i];
4942
4943 dev->stats.rx_packets += ring->rx_packets;
4944 dev->stats.rx_bytes += ring->rx_bytes;
0425b46a
SH		 4945 }
4946
d44570e4 4947 return &dev->stats;
1da177e4
LT		 4948}
4949
4950/**
4951 * s2io_set_multicast - entry point for multicast address enable/disable.
4952 * @dev : pointer to the device structure
4953 * Description:
20346722
K		 4954 * This function is a driver entry point which gets called by the kernel
4955 * whenever multicast addresses must be enabled/disabled. This also gets
1da177e4
LT		 4956 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4957 * determine, if multicast address must be enabled or if promiscuous mode
4958 * is to be disabled etc.
4959 * Return value:
4960 * void.
4961 */
4962
4963static void s2io_set_multicast(struct net_device *dev)
4964{
4965 int i, j, prev_cnt;
22bedad3 4966 struct netdev_hw_addr *ha;
4cf1653a 4967 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 4968 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 4969 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
d44570e4 4970 0xfeffffffffffULL;
faa4f796 4971 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
1da177e4 4972 void __iomem *add;
faa4f796 4973 struct config_param *config = &sp->config;
1da177e4
LT		 4974
4975 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4976 /* Enable all Multicast addresses */
4977 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4978 &bar0->rmac_addr_data0_mem);
4979 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4980 &bar0->rmac_addr_data1_mem);
4981 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 4982 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4983 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
1da177e4
LT		 4984 writeq(val64, &bar0->rmac_addr_cmd_mem);
4985 /* Wait till command completes */
c92ca04b 4986 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 4987 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4988 S2IO_BIT_RESET);
1da177e4
LT		 4989
4990 sp->m_cast_flg = 1;
faa4f796 4991 sp->all_multi_pos = config->max_mc_addr - 1;
1da177e4
LT		 4992 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4993 /* Disable all Multicast addresses */
4994 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4995 &bar0->rmac_addr_data0_mem);
5e25b9dd
K		 4996 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4997 &bar0->rmac_addr_data1_mem);
1da177e4 4998 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 4999 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5000 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
1da177e4
LT		 5001 writeq(val64, &bar0->rmac_addr_cmd_mem);
5002 /* Wait till command completes */
c92ca04b 5003 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5004 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5005 S2IO_BIT_RESET);
1da177e4
LT		 5006
5007 sp->m_cast_flg = 0;
5008 sp->all_multi_pos = 0;
5009 }
5010
5011 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
5012 /* Put the NIC into promiscuous mode */
5013 add = &bar0->mac_cfg;
5014 val64 = readq(&bar0->mac_cfg);
5015 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5016
5017 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 5018 writel((u32)val64, add);
1da177e4
LT		 5019 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5020 writel((u32) (val64 >> 32), (add + 4));
5021
926930b2
SS		 5022 if (vlan_tag_strip != 1) {
5023 val64 = readq(&bar0->rx_pa_cfg);
5024 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5025 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 5026 sp->vlan_strip_flag = 0;
926930b2
SS		 5027 }
5028
1da177e4
LT		 5029 val64 = readq(&bar0->mac_cfg);
5030 sp->promisc_flg = 1;
776bd20f 5031 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
1da177e4
LT		 5032 dev->name);
5033 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5034 /* Remove the NIC from promiscuous mode */
5035 add = &bar0->mac_cfg;
5036 val64 = readq(&bar0->mac_cfg);
5037 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5038
5039 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 5040 writel((u32)val64, add);
1da177e4
LT		 5041 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5042 writel((u32) (val64 >> 32), (add + 4));
5043
926930b2
SS		 5044 if (vlan_tag_strip != 0) {
5045 val64 = readq(&bar0->rx_pa_cfg);
5046 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5047 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 5048 sp->vlan_strip_flag = 1;
926930b2
SS		 5049 }
5050
1da177e4
LT		 5051 val64 = readq(&bar0->mac_cfg);
5052 sp->promisc_flg = 0;
9e39f7c5 5053 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name);
1da177e4
LT		 5054 }
5055
5056 /* Update individual M_CAST address list */
4cd24eaf
JP		 5057 if ((!sp->m_cast_flg) && netdev_mc_count(dev)) {
5058 if (netdev_mc_count(dev) >
faa4f796 5059 (config->max_mc_addr - config->max_mac_addr)) {
9e39f7c5
JP		 5060 DBG_PRINT(ERR_DBG,
5061 "%s: No more Rx filters can be added - "
5062 "please enable ALL_MULTI instead\n",
1da177e4 5063 dev->name);
1da177e4
LT		 5064 return;
5065 }
5066
5067 prev_cnt = sp->mc_addr_count;
4cd24eaf 5068 sp->mc_addr_count = netdev_mc_count(dev);
1da177e4
LT		 5069
5070 /* Clear out the previous list of Mc in the H/W. */
5071 for (i = 0; i < prev_cnt; i++) {
5072 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5073 &bar0->rmac_addr_data0_mem);
5074 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
d44570e4 5075 &bar0->rmac_addr_data1_mem);
1da177e4 5076 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5077 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5078 RMAC_ADDR_CMD_MEM_OFFSET
5079 (config->mc_start_offset + i);
1da177e4
LT		 5080 writeq(val64, &bar0->rmac_addr_cmd_mem);
5081
5082 /* Wait for command completes */
c92ca04b 5083 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5084 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5085 S2IO_BIT_RESET)) {
9e39f7c5
JP		 5086 DBG_PRINT(ERR_DBG,
5087 "%s: Adding Multicasts failed\n",
5088 dev->name);
1da177e4
LT		 5089 return;
5090 }
5091 }
5092
5093 /* Create the new Rx filter list and update the same in H/W. */
5508590c 5094 i = 0;
22bedad3
JP		 5095 netdev_for_each_mc_addr(ha, dev) {
5096 memcpy(sp->usr_addrs[i].addr, ha->addr,
1da177e4 5097 ETH_ALEN);
a7a80d5a 5098 mac_addr = 0;
1da177e4 5099 for (j = 0; j < ETH_ALEN; j++) {
22bedad3 5100 mac_addr |= ha->addr[j];
1da177e4
LT		 5101 mac_addr <<= 8;
5102 }
5103 mac_addr >>= 8;
5104 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5105 &bar0->rmac_addr_data0_mem);
5106 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
d44570e4 5107 &bar0->rmac_addr_data1_mem);
1da177e4 5108 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5109 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5110 RMAC_ADDR_CMD_MEM_OFFSET
5111 (i + config->mc_start_offset);
1da177e4
LT		 5112 writeq(val64, &bar0->rmac_addr_cmd_mem);
5113
5114 /* Wait for command completes */
c92ca04b 5115 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5116 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5117 S2IO_BIT_RESET)) {
9e39f7c5
JP		 5118 DBG_PRINT(ERR_DBG,
5119 "%s: Adding Multicasts failed\n",
5120 dev->name);
1da177e4
LT		 5121 return;
5122 }
5508590c 5123 i++;
1da177e4
LT		 5124 }
5125 }
5126}
5127
faa4f796
SH		 5128/* read from CAM unicast & multicast addresses and store it in
5129 * def_mac_addr structure
5130 */
dac499f9 5131static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
faa4f796
SH		 5132{
5133 int offset;
5134 u64 mac_addr = 0x0;
5135 struct config_param *config = &sp->config;
5136
5137 /* store unicast & multicast mac addresses */
5138 for (offset = 0; offset < config->max_mc_addr; offset++) {
5139 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5140 /* if read fails disable the entry */
5141 if (mac_addr == FAILURE)
5142 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5143 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5144 }
5145}
5146
5147/* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5148static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5149{
5150 int offset;
5151 struct config_param *config = &sp->config;
5152 /* restore unicast mac address */
5153 for (offset = 0; offset < config->max_mac_addr; offset++)
5154 do_s2io_prog_unicast(sp->dev,
d44570e4 5155 sp->def_mac_addr[offset].mac_addr);
faa4f796
SH		 5156
5157 /* restore multicast mac address */
5158 for (offset = config->mc_start_offset;
d44570e4 5159 offset < config->max_mc_addr; offset++)
faa4f796
SH		 5160 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5161}
5162
5163/* add a multicast MAC address to CAM */
5164static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5165{
5166 int i;
5167 u64 mac_addr = 0;
5168 struct config_param *config = &sp->config;
5169
5170 for (i = 0; i < ETH_ALEN; i++) {
5171 mac_addr <<= 8;
5172 mac_addr |= addr[i];
5173 }
5174 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5175 return SUCCESS;
5176
5177 /* check if the multicast mac already preset in CAM */
5178 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5179 u64 tmp64;
5180 tmp64 = do_s2io_read_unicast_mc(sp, i);
5181 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5182 break;
5183
5184 if (tmp64 == mac_addr)
5185 return SUCCESS;
5186 }
5187 if (i == config->max_mc_addr) {
5188 DBG_PRINT(ERR_DBG,
d44570e4 5189 "CAM full no space left for multicast MAC\n");
faa4f796
SH		 5190 return FAILURE;
5191 }
5192 /* Update the internal structure with this new mac address */
5193 do_s2io_copy_mac_addr(sp, i, mac_addr);
5194
d44570e4 5195 return do_s2io_add_mac(sp, mac_addr, i);
faa4f796
SH		 5196}
5197
5198/* add MAC address to CAM */
5199static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
2fd37688
SS		 5200{
5201 u64 val64;
5202 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5203
5204 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
d44570e4 5205 &bar0->rmac_addr_data0_mem);
2fd37688 5206
d44570e4 5207 val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
2fd37688
SS		 5208 RMAC_ADDR_CMD_MEM_OFFSET(off);
5209 writeq(val64, &bar0->rmac_addr_cmd_mem);
5210
5211 /* Wait till command completes */
5212 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5213 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5214 S2IO_BIT_RESET)) {
faa4f796 5215 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
2fd37688
SS		 5216 return FAILURE;
5217 }
5218 return SUCCESS;
5219}
faa4f796
SH		 5220/* deletes a specified unicast/multicast mac entry from CAM */
5221static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5222{
5223 int offset;
5224 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5225 struct config_param *config = &sp->config;
5226
5227 for (offset = 1;
d44570e4 5228 offset < config->max_mc_addr; offset++) {
faa4f796
SH		 5229 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5230 if (tmp64 == addr) {
5231 /* disable the entry by writing 0xffffffffffffULL */
5232 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5233 return FAILURE;
5234 /* store the new mac list from CAM */
5235 do_s2io_store_unicast_mc(sp);
5236 return SUCCESS;
5237 }
5238 }
5239 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
d44570e4 5240 (unsigned long long)addr);
faa4f796
SH		 5241 return FAILURE;
5242}
5243
5244/* read mac entries from CAM */
5245static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5246{
5247 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5248 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5249
5250 /* read mac addr */
d44570e4 5251 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
faa4f796
SH		 5252 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5253 writeq(val64, &bar0->rmac_addr_cmd_mem);
5254
5255 /* Wait till command completes */
5256 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5257 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5258 S2IO_BIT_RESET)) {
faa4f796
SH		 5259 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5260 return FAILURE;
5261 }
5262 tmp64 = readq(&bar0->rmac_addr_data0_mem);
d44570e4
JP		 5263
5264 return tmp64 >> 16;
faa4f796 5265}
2fd37688
SS		 5266
5267/**
5268 * s2io_set_mac_addr driver entry point
5269 */
faa4f796 5270
2fd37688
SS		 5271static int s2io_set_mac_addr(struct net_device *dev, void *p)
5272{
5273 struct sockaddr *addr = p;
5274
5275 if (!is_valid_ether_addr(addr->sa_data))
5276 return -EINVAL;
5277
5278 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5279
5280 /* store the MAC address in CAM */
d44570e4 5281 return do_s2io_prog_unicast(dev, dev->dev_addr);
2fd37688 5282}
1da177e4 5283/**
2fd37688 5284 * do_s2io_prog_unicast - Programs the Xframe mac address
1da177e4
LT		 5285 * @dev : pointer to the device structure.
5286 * @addr: a uchar pointer to the new mac address which is to be set.
20346722 5287 * Description : This procedure will program the Xframe to receive
1da177e4 5288 * frames with new Mac Address
20346722 5289 * Return value: SUCCESS on success and an appropriate (-)ve integer
1da177e4
LT		 5290 * as defined in errno.h file on failure.
5291 */
faa4f796 5292
2fd37688 5293static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
1da177e4 5294{
4cf1653a 5295 struct s2io_nic *sp = netdev_priv(dev);
2fd37688 5296 register u64 mac_addr = 0, perm_addr = 0;
1da177e4 5297 int i;
faa4f796
SH		 5298 u64 tmp64;
5299 struct config_param *config = &sp->config;
1da177e4 5300
20346722 5301 /*
d44570e4
JP		 5302 * Set the new MAC address as the new unicast filter and reflect this
5303 * change on the device address registered with the OS. It will be
5304 * at offset 0.
5305 */
1da177e4
LT		 5306 for (i = 0; i < ETH_ALEN; i++) {
5307 mac_addr <<= 8;
5308 mac_addr |= addr[i];
2fd37688
SS		 5309 perm_addr <<= 8;
5310 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
d8d70caf
SS		 5311 }
5312
2fd37688
SS		 5313 /* check if the dev_addr is different than perm_addr */
5314 if (mac_addr == perm_addr)
d8d70caf
SS		 5315 return SUCCESS;
5316
faa4f796
SH		 5317 /* check if the mac already preset in CAM */
5318 for (i = 1; i < config->max_mac_addr; i++) {
5319 tmp64 = do_s2io_read_unicast_mc(sp, i);
5320 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5321 break;
5322
5323 if (tmp64 == mac_addr) {
5324 DBG_PRINT(INFO_DBG,
d44570e4
JP		 5325 "MAC addr:0x%llx already present in CAM\n",
5326 (unsigned long long)mac_addr);
faa4f796
SH		 5327 return SUCCESS;
5328 }
5329 }
5330 if (i == config->max_mac_addr) {
5331 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5332 return FAILURE;
5333 }
d8d70caf 5334 /* Update the internal structure with this new mac address */
faa4f796 5335 do_s2io_copy_mac_addr(sp, i, mac_addr);
d44570e4
JP		 5336
5337 return do_s2io_add_mac(sp, mac_addr, i);
1da177e4
LT		 5338}
5339
5340/**
20346722 5341 * s2io_ethtool_sset - Sets different link parameters.
1da177e4
LT		 5342 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5343 * @info: pointer to the structure with parameters given by ethtool to set
5344 * link information.
5345 * Description:
20346722 5346 * The function sets different link parameters provided by the user onto
1da177e4
LT		 5347 * the NIC.
5348 * Return value:
5349 * 0 on success.
d44570e4 5350 */
1da177e4
LT		 5351
5352static int s2io_ethtool_sset(struct net_device *dev,
5353 struct ethtool_cmd *info)
5354{
4cf1653a 5355 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 5356 if ((info->autoneg == AUTONEG_ENABLE) ||
d44570e4
JP		 5357 (info->speed != SPEED_10000) ||
5358 (info->duplex != DUPLEX_FULL))
1da177e4
LT		 5359 return -EINVAL;
5360 else {
5361 s2io_close(sp->dev);
5362 s2io_open(sp->dev);
5363 }
5364
5365 return 0;
5366}
5367
5368/**
20346722 5369 * s2io_ethtol_gset - Return link specific information.
1da177e4
LT		 5370 * @sp : private member of the device structure, pointer to the
5371 * s2io_nic structure.
5372 * @info : pointer to the structure with parameters given by ethtool
5373 * to return link information.
5374 * Description:
5375 * Returns link specific information like speed, duplex etc.. to ethtool.
5376 * Return value :
5377 * return 0 on success.
5378 */
5379
5380static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5381{
4cf1653a 5382 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5383 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5384 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5385 info->port = PORT_FIBRE;
1a7eb72b
SS		 5386
5387 /* info->transceiver */
5388 info->transceiver = XCVR_EXTERNAL;
1da177e4
LT		 5389
5390 if (netif_carrier_ok(sp->dev)) {
5391 info->speed = 10000;
5392 info->duplex = DUPLEX_FULL;
5393 } else {
5394 info->speed = -1;
5395 info->duplex = -1;
5396 }
5397
5398 info->autoneg = AUTONEG_DISABLE;
5399 return 0;
5400}
5401
5402/**
20346722
K		 5403 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5404 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5405 * s2io_nic structure.
5406 * @info : pointer to the structure with parameters given by ethtool to
5407 * return driver information.
5408 * Description:
5409 * Returns driver specefic information like name, version etc.. to ethtool.
5410 * Return value:
5411 * void
5412 */
5413
5414static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5415 struct ethtool_drvinfo *info)
5416{
4cf1653a 5417 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 5418
dbc2309d
JL		 5419 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5420 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5421 strncpy(info->fw_version, "", sizeof(info->fw_version));
5422 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
1da177e4
LT		 5423 info->regdump_len = XENA_REG_SPACE;
5424 info->eedump_len = XENA_EEPROM_SPACE;
1da177e4
LT		 5425}
5426
5427/**
5428 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
20346722 5429 * @sp: private member of the device structure, which is a pointer to the
1da177e4 5430 * s2io_nic structure.
20346722 5431 * @regs : pointer to the structure with parameters given by ethtool for
1da177e4
LT		 5432 * dumping the registers.
5433 * @reg_space: The input argumnet into which all the registers are dumped.
5434 * Description:
5435 * Dumps the entire register space of xFrame NIC into the user given
5436 * buffer area.
5437 * Return value :
5438 * void .
d44570e4 5439 */
1da177e4
LT		 5440
5441static void s2io_ethtool_gregs(struct net_device *dev,
5442 struct ethtool_regs *regs, void *space)
5443{
5444 int i;
5445 u64 reg;
d44570e4 5446 u8 *reg_space = (u8 *)space;
4cf1653a 5447 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5448
5449 regs->len = XENA_REG_SPACE;
5450 regs->version = sp->pdev->subsystem_device;
5451
5452 for (i = 0; i < regs->len; i += 8) {
5453 reg = readq(sp->bar0 + i);
5454 memcpy((reg_space + i), &reg, 8);
5455 }
5456}
5457
5458/**
5459 * s2io_phy_id - timer function that alternates adapter LED.
20346722 5460 * @data : address of the private member of the device structure, which
1da177e4 5461 * is a pointer to the s2io_nic structure, provided as an u32.
20346722
K		 5462 * Description: This is actually the timer function that alternates the
5463 * adapter LED bit of the adapter control bit to set/reset every time on
5464 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
1da177e4 5465 * once every second.
d44570e4 5466 */
1da177e4
LT		 5467static void s2io_phy_id(unsigned long data)
5468{
d44570e4 5469 struct s2io_nic *sp = (struct s2io_nic *)data;
1ee6dd77 5470 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5471 u64 val64 = 0;
5472 u16 subid;
5473
5474 subid = sp->pdev->subsystem_device;
541ae68f 5475 if ((sp->device_type == XFRAME_II_DEVICE) ||
d44570e4 5476 ((subid & 0xFF) >= 0x07)) {
1da177e4
LT		 5477 val64 = readq(&bar0->gpio_control);
5478 val64 ^= GPIO_CTRL_GPIO_0;
5479 writeq(val64, &bar0->gpio_control);
5480 } else {
5481 val64 = readq(&bar0->adapter_control);
5482 val64 ^= ADAPTER_LED_ON;
5483 writeq(val64, &bar0->adapter_control);
5484 }
5485
5486 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5487}
5488
5489/**
5490 * s2io_ethtool_idnic - To physically identify the nic on the system.
5491 * @sp : private member of the device structure, which is a pointer to the
5492 * s2io_nic structure.
20346722 5493 * @id : pointer to the structure with identification parameters given by
1da177e4
LT		 5494 * ethtool.
5495 * Description: Used to physically identify the NIC on the system.
20346722 5496 * The Link LED will blink for a time specified by the user for
1da177e4 5497 * identification.
20346722 5498 * NOTE: The Link has to be Up to be able to blink the LED. Hence
1da177e4
LT		 5499 * identification is possible only if it's link is up.
5500 * Return value:
5501 * int , returns 0 on success
5502 */
5503
5504static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5505{
5506 u64 val64 = 0, last_gpio_ctrl_val;
4cf1653a 5507 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5508 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5509 u16 subid;
5510
5511 subid = sp->pdev->subsystem_device;
5512 last_gpio_ctrl_val = readq(&bar0->gpio_control);
d44570e4 5513 if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) {
1da177e4
LT		 5514 val64 = readq(&bar0->adapter_control);
5515 if (!(val64 & ADAPTER_CNTL_EN)) {
6cef2b8e 5516 pr_err("Adapter Link down, cannot blink LED\n");
1da177e4
LT		 5517 return -EFAULT;
5518 }
5519 }
5520 if (sp->id_timer.function == NULL) {
5521 init_timer(&sp->id_timer);
5522 sp->id_timer.function = s2io_phy_id;
d44570e4 5523 sp->id_timer.data = (unsigned long)sp;
1da177e4
LT		 5524 }
5525 mod_timer(&sp->id_timer, jiffies);
5526 if (data)
20346722 5527 msleep_interruptible(data * HZ);
1da177e4 5528 else
20346722 5529 msleep_interruptible(MAX_FLICKER_TIME);
1da177e4
LT		 5530 del_timer_sync(&sp->id_timer);
5531
541ae68f 5532 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
1da177e4
LT		 5533 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5534 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5535 }
5536
5537 return 0;
5538}
5539
0cec35eb 5540static void s2io_ethtool_gringparam(struct net_device *dev,
d44570e4 5541 struct ethtool_ringparam *ering)
0cec35eb 5542{
4cf1653a 5543 struct s2io_nic *sp = netdev_priv(dev);
d44570e4 5544 int i, tx_desc_count = 0, rx_desc_count = 0;
0cec35eb
SH		 5545
5546 if (sp->rxd_mode == RXD_MODE_1)
5547 ering->rx_max_pending = MAX_RX_DESC_1;
5548 else if (sp->rxd_mode == RXD_MODE_3B)
5549 ering->rx_max_pending = MAX_RX_DESC_2;
0cec35eb
SH		 5550
5551 ering->tx_max_pending = MAX_TX_DESC;
8a4bdbaa 5552 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
0cec35eb 5553 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
8a4bdbaa 5554
9e39f7c5 5555 DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds);
0cec35eb
SH		 5556 ering->tx_pending = tx_desc_count;
5557 rx_desc_count = 0;
8a4bdbaa 5558 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
0cec35eb 5559 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
b6627672 5560
0cec35eb
SH		 5561 ering->rx_pending = rx_desc_count;
5562
5563 ering->rx_mini_max_pending = 0;
5564 ering->rx_mini_pending = 0;
d44570e4 5565 if (sp->rxd_mode == RXD_MODE_1)
0cec35eb
SH		 5566 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5567 else if (sp->rxd_mode == RXD_MODE_3B)
5568 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5569 ering->rx_jumbo_pending = rx_desc_count;
5570}
5571
1da177e4
LT		 5572/**
5573 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
20346722
K		 5574 * @sp : private member of the device structure, which is a pointer to the
5575 * s2io_nic structure.
1da177e4
LT		 5576 * @ep : pointer to the structure with pause parameters given by ethtool.
5577 * Description:
5578 * Returns the Pause frame generation and reception capability of the NIC.
5579 * Return value:
5580 * void
5581 */
5582static void s2io_ethtool_getpause_data(struct net_device *dev,
5583 struct ethtool_pauseparam *ep)
5584{
5585 u64 val64;
4cf1653a 5586 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5587 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5588
5589 val64 = readq(&bar0->rmac_pause_cfg);
5590 if (val64 & RMAC_PAUSE_GEN_ENABLE)
f957bcf0 5591 ep->tx_pause = true;
1da177e4 5592 if (val64 & RMAC_PAUSE_RX_ENABLE)
f957bcf0
TK		 5593 ep->rx_pause = true;
5594 ep->autoneg = false;
1da177e4
LT		 5595}
5596
5597/**
5598 * s2io_ethtool_setpause_data - set/reset pause frame generation.
20346722 5599 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5600 * s2io_nic structure.
5601 * @ep : pointer to the structure with pause parameters given by ethtool.
5602 * Description:
5603 * It can be used to set or reset Pause frame generation or reception
5604 * support of the NIC.
5605 * Return value:
5606 * int, returns 0 on Success
5607 */
5608
5609static int s2io_ethtool_setpause_data(struct net_device *dev,
d44570e4 5610 struct ethtool_pauseparam *ep)
1da177e4
LT		 5611{
5612 u64 val64;
4cf1653a 5613 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5614 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5615
5616 val64 = readq(&bar0->rmac_pause_cfg);
5617 if (ep->tx_pause)
5618 val64 |= RMAC_PAUSE_GEN_ENABLE;
5619 else
5620 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5621 if (ep->rx_pause)
5622 val64 |= RMAC_PAUSE_RX_ENABLE;
5623 else
5624 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5625 writeq(val64, &bar0->rmac_pause_cfg);
5626 return 0;
5627}
5628
5629/**
5630 * read_eeprom - reads 4 bytes of data from user given offset.
20346722 5631 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5632 * s2io_nic structure.
5633 * @off : offset at which the data must be written
5634 * @data : Its an output parameter where the data read at the given
20346722 5635 * offset is stored.
1da177e4 5636 * Description:
20346722 5637 * Will read 4 bytes of data from the user given offset and return the
1da177e4
LT		 5638 * read data.
5639 * NOTE: Will allow to read only part of the EEPROM visible through the
5640 * I2C bus.
5641 * Return value:
5642 * -1 on failure and 0 on success.
5643 */
5644
5645#define S2IO_DEV_ID 5
d44570e4 5646static int read_eeprom(struct s2io_nic *sp, int off, u64 *data)
1da177e4
LT		 5647{
5648 int ret = -1;
5649 u32 exit_cnt = 0;
5650 u64 val64;
1ee6dd77 5651 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5652
ad4ebed0 5653 if (sp->device_type == XFRAME_I_DEVICE) {
d44570e4
JP		 5654 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5655 I2C_CONTROL_ADDR(off) |
5656 I2C_CONTROL_BYTE_CNT(0x3) |
5657 I2C_CONTROL_READ |
5658 I2C_CONTROL_CNTL_START;
ad4ebed0 5659 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
1da177e4 5660
ad4ebed0 5661 while (exit_cnt < 5) {
5662 val64 = readq(&bar0->i2c_control);
5663 if (I2C_CONTROL_CNTL_END(val64)) {
5664 *data = I2C_CONTROL_GET_DATA(val64);
5665 ret = 0;
5666 break;
5667 }
5668 msleep(50);
5669 exit_cnt++;
1da177e4 5670 }
1da177e4
LT		 5671 }
5672
ad4ebed0 5673 if (sp->device_type == XFRAME_II_DEVICE) {
5674 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5675 SPI_CONTROL_BYTECNT(0x3) |
ad4ebed0 5676 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5677 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5678 val64 |= SPI_CONTROL_REQ;
5679 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5680 while (exit_cnt < 5) {
5681 val64 = readq(&bar0->spi_control);
5682 if (val64 & SPI_CONTROL_NACK) {
5683 ret = 1;
5684 break;
5685 } else if (val64 & SPI_CONTROL_DONE) {
5686 *data = readq(&bar0->spi_data);
5687 *data &= 0xffffff;
5688 ret = 0;
5689 break;
5690 }
5691 msleep(50);
5692 exit_cnt++;
5693 }
5694 }
1da177e4
LT		 5695 return ret;
5696}
5697
5698/**
5699 * write_eeprom - actually writes the relevant part of the data value.
5700 * @sp : private member of the device structure, which is a pointer to the
5701 * s2io_nic structure.
5702 * @off : offset at which the data must be written
5703 * @data : The data that is to be written
20346722 5704 * @cnt : Number of bytes of the data that are actually to be written into
1da177e4
LT		 5705 * the Eeprom. (max of 3)
5706 * Description:
5707 * Actually writes the relevant part of the data value into the Eeprom
5708 * through the I2C bus.
5709 * Return value:
5710 * 0 on success, -1 on failure.
5711 */
5712
d44570e4 5713static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt)
1da177e4
LT		 5714{
5715 int exit_cnt = 0, ret = -1;
5716 u64 val64;
1ee6dd77 5717 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5718
ad4ebed0 5719 if (sp->device_type == XFRAME_I_DEVICE) {
d44570e4
JP		 5720 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5721 I2C_CONTROL_ADDR(off) |
5722 I2C_CONTROL_BYTE_CNT(cnt) |
5723 I2C_CONTROL_SET_DATA((u32)data) |
5724 I2C_CONTROL_CNTL_START;
ad4ebed0 5725 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5726
5727 while (exit_cnt < 5) {
5728 val64 = readq(&bar0->i2c_control);
5729 if (I2C_CONTROL_CNTL_END(val64)) {
5730 if (!(val64 & I2C_CONTROL_NACK))
5731 ret = 0;
5732 break;
5733 }
5734 msleep(50);
5735 exit_cnt++;
5736 }
5737 }
1da177e4 5738
ad4ebed0 5739 if (sp->device_type == XFRAME_II_DEVICE) {
5740 int write_cnt = (cnt == 8) ? 0 : cnt;
d44570e4 5741 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
ad4ebed0 5742
5743 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5744 SPI_CONTROL_BYTECNT(write_cnt) |
ad4ebed0 5745 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5746 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5747 val64 |= SPI_CONTROL_REQ;
5748 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5749 while (exit_cnt < 5) {
5750 val64 = readq(&bar0->spi_control);
5751 if (val64 & SPI_CONTROL_NACK) {
5752 ret = 1;
5753 break;
5754 } else if (val64 & SPI_CONTROL_DONE) {
1da177e4 5755 ret = 0;
ad4ebed0 5756 break;
5757 }
5758 msleep(50);
5759 exit_cnt++;
1da177e4 5760 }
1da177e4 5761 }
1da177e4
LT		 5762 return ret;
5763}
1ee6dd77 5764static void s2io_vpd_read(struct s2io_nic *nic)
9dc737a7 5765{
b41477f3
AR		 5766 u8 *vpd_data;
5767 u8 data;
d44570e4 5768 int i = 0, cnt, fail = 0;
9dc737a7 5769 int vpd_addr = 0x80;
ffb5df6c 5770 struct swStat *swstats = &nic->mac_control.stats_info->sw_stat;
9dc737a7
AR		 5771
5772 if (nic->device_type == XFRAME_II_DEVICE) {
5773 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5774 vpd_addr = 0x80;
d44570e4 5775 } else {
9dc737a7
AR		 5776 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5777 vpd_addr = 0x50;
5778 }
19a60522 5779 strcpy(nic->serial_num, "NOT AVAILABLE");
9dc737a7 5780
b41477f3 5781 vpd_data = kmalloc(256, GFP_KERNEL);
c53d4945 5782 if (!vpd_data) {
ffb5df6c 5783 swstats->mem_alloc_fail_cnt++;
b41477f3 5784 return;
c53d4945 5785 }
ffb5df6c 5786 swstats->mem_allocated += 256;
b41477f3 5787
d44570e4 5788 for (i = 0; i < 256; i += 4) {
9dc737a7
AR		 5789 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5790 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5791 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
d44570e4 5792 for (cnt = 0; cnt < 5; cnt++) {
9dc737a7
AR		 5793 msleep(2);
5794 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5795 if (data == 0x80)
5796 break;
5797 }
5798 if (cnt >= 5) {
5799 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5800 fail = 1;
5801 break;
5802 }
5803 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5804 (u32 *)&vpd_data[i]);
5805 }
19a60522 5806
d44570e4 5807 if (!fail) {
19a60522
SS		 5808 /* read serial number of adapter */
5809 for (cnt = 0; cnt < 256; cnt++) {
d44570e4
JP		 5810 if ((vpd_data[cnt] == 'S') &&
5811 (vpd_data[cnt+1] == 'N') &&
5812 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
19a60522
SS		 5813 memset(nic->serial_num, 0, VPD_STRING_LEN);
5814 memcpy(nic->serial_num, &vpd_data[cnt + 3],
d44570e4 5815 vpd_data[cnt+2]);
19a60522
SS		 5816 break;
5817 }
5818 }
5819 }
5820
876e956f 5821 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN))
9dc737a7 5822 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
b41477f3 5823 kfree(vpd_data);
ffb5df6c 5824 swstats->mem_freed += 256;
9dc737a7
AR		 5825}
5826
1da177e4
LT		 5827/**
5828 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5829 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
20346722 5830 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5831 * containing all relevant information.
5832 * @data_buf : user defined value to be written into Eeprom.
5833 * Description: Reads the values stored in the Eeprom at given offset
5834 * for a given length. Stores these values int the input argument data
5835 * buffer 'data_buf' and returns these to the caller (ethtool.)
5836 * Return value:
5837 * int 0 on success
5838 */
5839
5840static int s2io_ethtool_geeprom(struct net_device *dev,
d44570e4 5841 struct ethtool_eeprom *eeprom, u8 * data_buf)
1da177e4 5842{
ad4ebed0 5843 u32 i, valid;
5844 u64 data;
4cf1653a 5845 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5846
5847 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5848
5849 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5850 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5851
5852 for (i = 0; i < eeprom->len; i += 4) {
5853 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5854 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5855 return -EFAULT;
5856 }
5857 valid = INV(data);
5858 memcpy((data_buf + i), &valid, 4);
5859 }
5860 return 0;
5861}
5862
5863/**
5864 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5865 * @sp : private member of the device structure, which is a pointer to the
5866 * s2io_nic structure.
20346722 5867 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5868 * containing all relevant information.
5869 * @data_buf ; user defined value to be written into Eeprom.
5870 * Description:
5871 * Tries to write the user provided value in the Eeprom, at the offset
5872 * given by the user.
5873 * Return value:
5874 * 0 on success, -EFAULT on failure.
5875 */
5876
5877static int s2io_ethtool_seeprom(struct net_device *dev,
5878 struct ethtool_eeprom *eeprom,
d44570e4 5879 u8 *data_buf)
1da177e4
LT		 5880{
5881 int len = eeprom->len, cnt = 0;
ad4ebed0 5882 u64 valid = 0, data;
4cf1653a 5883 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5884
5885 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5886 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 5887 "ETHTOOL_WRITE_EEPROM Err: "
5888 "Magic value is wrong, it is 0x%x should be 0x%x\n",
5889 (sp->pdev->vendor | (sp->pdev->device << 16)),
5890 eeprom->magic);
1da177e4
LT		 5891 return -EFAULT;
5892 }
5893
5894 while (len) {
d44570e4
JP		 5895 data = (u32)data_buf[cnt] & 0x000000FF;
5896 if (data)
5897 valid = (u32)(data << 24);
5898 else
1da177e4
LT		 5899 valid = data;
5900
5901 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5902 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 5903 "ETHTOOL_WRITE_EEPROM Err: "
5904 "Cannot write into the specified offset\n");
1da177e4
LT		 5905 return -EFAULT;
5906 }
5907 cnt++;
5908 len--;
5909 }
5910
5911 return 0;
5912}
5913
5914/**
20346722
K		 5915 * s2io_register_test - reads and writes into all clock domains.
5916 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5917 * s2io_nic structure.
5918 * @data : variable that returns the result of each of the test conducted b
5919 * by the driver.
5920 * Description:
5921 * Read and write into all clock domains. The NIC has 3 clock domains,
5922 * see that registers in all the three regions are accessible.
5923 * Return value:
5924 * 0 on success.
5925 */
5926
d44570e4 5927static int s2io_register_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 5928{
1ee6dd77 5929 struct XENA_dev_config __iomem *bar0 = sp->bar0;
ad4ebed0 5930 u64 val64 = 0, exp_val;
1da177e4
LT		 5931 int fail = 0;
5932
20346722
K		 5933 val64 = readq(&bar0->pif_rd_swapper_fb);
5934 if (val64 != 0x123456789abcdefULL) {
1da177e4 5935 fail = 1;
9e39f7c5 5936 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 1);
1da177e4
LT		 5937 }
5938
5939 val64 = readq(&bar0->rmac_pause_cfg);
5940 if (val64 != 0xc000ffff00000000ULL) {
5941 fail = 1;
9e39f7c5 5942 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 2);
1da177e4
LT		 5943 }
5944
5945 val64 = readq(&bar0->rx_queue_cfg);
ad4ebed0 5946 if (sp->device_type == XFRAME_II_DEVICE)
5947 exp_val = 0x0404040404040404ULL;
5948 else
5949 exp_val = 0x0808080808080808ULL;
5950 if (val64 != exp_val) {
1da177e4 5951 fail = 1;
9e39f7c5 5952 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 3);
1da177e4
LT		 5953 }
5954
5955 val64 = readq(&bar0->xgxs_efifo_cfg);
5956 if (val64 != 0x000000001923141EULL) {
5957 fail = 1;
9e39f7c5 5958 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 4);
1da177e4
LT		 5959 }
5960
5961 val64 = 0x5A5A5A5A5A5A5A5AULL;
5962 writeq(val64, &bar0->xmsi_data);
5963 val64 = readq(&bar0->xmsi_data);
5964 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5965 fail = 1;
9e39f7c5 5966 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 1);
1da177e4
LT		 5967 }
5968
5969 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5970 writeq(val64, &bar0->xmsi_data);
5971 val64 = readq(&bar0->xmsi_data);
5972 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5973 fail = 1;
9e39f7c5 5974 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 2);
1da177e4
LT		 5975 }
5976
5977 *data = fail;
ad4ebed0 5978 return fail;
1da177e4
LT		 5979}
5980
5981/**
20346722 5982 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
1da177e4
LT		 5983 * @sp : private member of the device structure, which is a pointer to the
5984 * s2io_nic structure.
5985 * @data:variable that returns the result of each of the test conducted by
5986 * the driver.
5987 * Description:
20346722 5988 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
1da177e4
LT		 5989 * register.
5990 * Return value:
5991 * 0 on success.
5992 */
5993
d44570e4 5994static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data)
1da177e4
LT		 5995{
5996 int fail = 0;
ad4ebed0 5997 u64 ret_data, org_4F0, org_7F0;
5998 u8 saved_4F0 = 0, saved_7F0 = 0;
5999 struct net_device *dev = sp->dev;
1da177e4
LT		 6000
6001 /* Test Write Error at offset 0 */
ad4ebed0 6002 /* Note that SPI interface allows write access to all areas
6003 * of EEPROM. Hence doing all negative testing only for Xframe I.
6004 */
6005 if (sp->device_type == XFRAME_I_DEVICE)
6006 if (!write_eeprom(sp, 0, 0, 3))
6007 fail = 1;
6008
6009 /* Save current values at offsets 0x4F0 and 0x7F0 */
6010 if (!read_eeprom(sp, 0x4F0, &org_4F0))
6011 saved_4F0 = 1;
6012 if (!read_eeprom(sp, 0x7F0, &org_7F0))
6013 saved_7F0 = 1;
1da177e4
LT		 6014
6015 /* Test Write at offset 4f0 */
ad4ebed0 6016 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
1da177e4
LT		 6017 fail = 1;
6018 if (read_eeprom(sp, 0x4F0, &ret_data))
6019 fail = 1;
6020
ad4ebed0 6021 if (ret_data != 0x012345) {
26b7625c 6022 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
d44570e4
JP		 6023 "Data written %llx Data read %llx\n",
6024 dev->name, (unsigned long long)0x12345,
6025 (unsigned long long)ret_data);
1da177e4 6026 fail = 1;
ad4ebed0 6027 }
1da177e4
LT		 6028
6029 /* Reset the EEPROM data go FFFF */
ad4ebed0 6030 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
1da177e4
LT		 6031
6032 /* Test Write Request Error at offset 0x7c */
ad4ebed0 6033 if (sp->device_type == XFRAME_I_DEVICE)
6034 if (!write_eeprom(sp, 0x07C, 0, 3))
6035 fail = 1;
1da177e4 6036
ad4ebed0 6037 /* Test Write Request at offset 0x7f0 */
6038 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
1da177e4 6039 fail = 1;
ad4ebed0 6040 if (read_eeprom(sp, 0x7F0, &ret_data))
1da177e4
LT		 6041 fail = 1;
6042
ad4ebed0 6043 if (ret_data != 0x012345) {
26b7625c 6044 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
d44570e4
JP		 6045 "Data written %llx Data read %llx\n",
6046 dev->name, (unsigned long long)0x12345,
6047 (unsigned long long)ret_data);
1da177e4 6048 fail = 1;
ad4ebed0 6049 }
1da177e4
LT		 6050
6051 /* Reset the EEPROM data go FFFF */
ad4ebed0 6052 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
1da177e4 6053
ad4ebed0 6054 if (sp->device_type == XFRAME_I_DEVICE) {
6055 /* Test Write Error at offset 0x80 */
6056 if (!write_eeprom(sp, 0x080, 0, 3))
6057 fail = 1;
1da177e4 6058
ad4ebed0 6059 /* Test Write Error at offset 0xfc */
6060 if (!write_eeprom(sp, 0x0FC, 0, 3))
6061 fail = 1;
1da177e4 6062
ad4ebed0 6063 /* Test Write Error at offset 0x100 */
6064 if (!write_eeprom(sp, 0x100, 0, 3))
6065 fail = 1;
1da177e4 6066
ad4ebed0 6067 /* Test Write Error at offset 4ec */
6068 if (!write_eeprom(sp, 0x4EC, 0, 3))
6069 fail = 1;
6070 }
6071
6072 /* Restore values at offsets 0x4F0 and 0x7F0 */
6073 if (saved_4F0)
6074 write_eeprom(sp, 0x4F0, org_4F0, 3);
6075 if (saved_7F0)
6076 write_eeprom(sp, 0x7F0, org_7F0, 3);
1da177e4
LT		 6077
6078 *data = fail;
ad4ebed0 6079 return fail;
1da177e4
LT		 6080}
6081
6082/**
6083 * s2io_bist_test - invokes the MemBist test of the card .
20346722 6084 * @sp : private member of the device structure, which is a pointer to the
1da177e4 6085 * s2io_nic structure.
20346722 6086 * @data:variable that returns the result of each of the test conducted by
1da177e4
LT		 6087 * the driver.
6088 * Description:
6089 * This invokes the MemBist test of the card. We give around
6090 * 2 secs time for the Test to complete. If it's still not complete
20346722 6091 * within this peiod, we consider that the test failed.
1da177e4
LT		 6092 * Return value:
6093 * 0 on success and -1 on failure.
6094 */
6095
d44570e4 6096static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data)
1da177e4
LT		 6097{
6098 u8 bist = 0;
6099 int cnt = 0, ret = -1;
6100
6101 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6102 bist |= PCI_BIST_START;
6103 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6104
6105 while (cnt < 20) {
6106 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6107 if (!(bist & PCI_BIST_START)) {
6108 *data = (bist & PCI_BIST_CODE_MASK);
6109 ret = 0;
6110 break;
6111 }
6112 msleep(100);
6113 cnt++;
6114 }
6115
6116 return ret;
6117}
6118
6119/**
20346722
K		 6120 * s2io-link_test - verifies the link state of the nic
6121 * @sp ; private member of the device structure, which is a pointer to the
1da177e4
LT		 6122 * s2io_nic structure.
6123 * @data: variable that returns the result of each of the test conducted by
6124 * the driver.
6125 * Description:
20346722 6126 * The function verifies the link state of the NIC and updates the input
1da177e4
LT		 6127 * argument 'data' appropriately.
6128 * Return value:
6129 * 0 on success.
6130 */
6131
d44570e4 6132static int s2io_link_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 6133{
1ee6dd77 6134 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 6135 u64 val64;
6136
6137 val64 = readq(&bar0->adapter_status);
d44570e4 6138 if (!(LINK_IS_UP(val64)))
1da177e4 6139 *data = 1;
c92ca04b
AR		 6140 else
6141 *data = 0;
1da177e4 6142
b41477f3 6143 return *data;
1da177e4
LT		 6144}
6145
6146/**
20346722
K		 6147 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6148 * @sp - private member of the device structure, which is a pointer to the
1da177e4 6149 * s2io_nic structure.
20346722 6150 * @data - variable that returns the result of each of the test
1da177e4
LT		 6151 * conducted by the driver.
6152 * Description:
20346722 6153 * This is one of the offline test that tests the read and write
1da177e4
LT		 6154 * access to the RldRam chip on the NIC.
6155 * Return value:
6156 * 0 on success.
6157 */
6158
d44570e4 6159static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 6160{
1ee6dd77 6161 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 6162 u64 val64;
ad4ebed0 6163 int cnt, iteration = 0, test_fail = 0;
1da177e4
LT		 6164
6165 val64 = readq(&bar0->adapter_control);
6166 val64 &= ~ADAPTER_ECC_EN;
6167 writeq(val64, &bar0->adapter_control);
6168
6169 val64 = readq(&bar0->mc_rldram_test_ctrl);
6170 val64 |= MC_RLDRAM_TEST_MODE;
ad4ebed0 6171 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6172
6173 val64 = readq(&bar0->mc_rldram_mrs);
6174 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6175 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6176
6177 val64 |= MC_RLDRAM_MRS_ENABLE;
6178 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6179
6180 while (iteration < 2) {
6181 val64 = 0x55555555aaaa0000ULL;
d44570e4 6182 if (iteration == 1)
1da177e4 6183 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6184 writeq(val64, &bar0->mc_rldram_test_d0);
6185
6186 val64 = 0xaaaa5a5555550000ULL;
d44570e4 6187 if (iteration == 1)
1da177e4 6188 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6189 writeq(val64, &bar0->mc_rldram_test_d1);
6190
6191 val64 = 0x55aaaaaaaa5a0000ULL;
d44570e4 6192 if (iteration == 1)
1da177e4 6193 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6194 writeq(val64, &bar0->mc_rldram_test_d2);
6195
ad4ebed0 6196 val64 = (u64) (0x0000003ffffe0100ULL);
1da177e4
LT		 6197 writeq(val64, &bar0->mc_rldram_test_add);
6198
d44570e4
JP		 6199 val64 = MC_RLDRAM_TEST_MODE |
6200 MC_RLDRAM_TEST_WRITE |
6201 MC_RLDRAM_TEST_GO;
ad4ebed0 6202 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6203
6204 for (cnt = 0; cnt < 5; cnt++) {
6205 val64 = readq(&bar0->mc_rldram_test_ctrl);
6206 if (val64 & MC_RLDRAM_TEST_DONE)
6207 break;
6208 msleep(200);
6209 }
6210
6211 if (cnt == 5)
6212 break;
6213
ad4ebed0 6214 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6215 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6216
6217 for (cnt = 0; cnt < 5; cnt++) {
6218 val64 = readq(&bar0->mc_rldram_test_ctrl);
6219 if (val64 & MC_RLDRAM_TEST_DONE)
6220 break;
6221 msleep(500);
6222 }
6223
6224 if (cnt == 5)
6225 break;
6226
6227 val64 = readq(&bar0->mc_rldram_test_ctrl);
ad4ebed0 6228 if (!(val64 & MC_RLDRAM_TEST_PASS))
6229 test_fail = 1;
1da177e4
LT		 6230
6231 iteration++;
6232 }
6233
ad4ebed0 6234 *data = test_fail;
1da177e4 6235
ad4ebed0 6236 /* Bring the adapter out of test mode */
6237 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6238
6239 return test_fail;
1da177e4
LT		 6240}
6241
6242/**
6243 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6244 * @sp : private member of the device structure, which is a pointer to the
6245 * s2io_nic structure.
6246 * @ethtest : pointer to a ethtool command specific structure that will be
6247 * returned to the user.
20346722 6248 * @data : variable that returns the result of each of the test
1da177e4
LT		 6249 * conducted by the driver.
6250 * Description:
6251 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6252 * the health of the card.
6253 * Return value:
6254 * void
6255 */
6256
6257static void s2io_ethtool_test(struct net_device *dev,
6258 struct ethtool_test *ethtest,
d44570e4 6259 uint64_t *data)
1da177e4 6260{
4cf1653a 6261 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 6262 int orig_state = netif_running(sp->dev);
6263
6264 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6265 /* Offline Tests. */
20346722 6266 if (orig_state)
1da177e4 6267 s2io_close(sp->dev);
1da177e4
LT		 6268
6269 if (s2io_register_test(sp, &data[0]))
6270 ethtest->flags |= ETH_TEST_FL_FAILED;
6271
6272 s2io_reset(sp);
1da177e4
LT		 6273
6274 if (s2io_rldram_test(sp, &data[3]))
6275 ethtest->flags |= ETH_TEST_FL_FAILED;
6276
6277 s2io_reset(sp);
1da177e4
LT		 6278
6279 if (s2io_eeprom_test(sp, &data[1]))
6280 ethtest->flags |= ETH_TEST_FL_FAILED;
6281
6282 if (s2io_bist_test(sp, &data[4]))
6283 ethtest->flags |= ETH_TEST_FL_FAILED;
6284
6285 if (orig_state)
6286 s2io_open(sp->dev);
6287
6288 data[2] = 0;
6289 } else {
6290 /* Online Tests. */
6291 if (!orig_state) {
d44570e4 6292 DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n",
1da177e4
LT		 6293 dev->name);
6294 data[0] = -1;
6295 data[1] = -1;
6296 data[2] = -1;
6297 data[3] = -1;
6298 data[4] = -1;
6299 }
6300
6301 if (s2io_link_test(sp, &data[2]))
6302 ethtest->flags |= ETH_TEST_FL_FAILED;
6303
6304 data[0] = 0;
6305 data[1] = 0;
6306 data[3] = 0;
6307 data[4] = 0;
6308 }
6309}
6310
6311static void s2io_get_ethtool_stats(struct net_device *dev,
6312 struct ethtool_stats *estats,
d44570e4 6313 u64 *tmp_stats)
1da177e4 6314{
8116f3cf 6315 int i = 0, k;
4cf1653a 6316 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c
JP		 6317 struct stat_block *stats = sp->mac_control.stats_info;
6318 struct swStat *swstats = &stats->sw_stat;
6319 struct xpakStat *xstats = &stats->xpak_stat;
1da177e4 6320
7ba013ac 6321 s2io_updt_stats(sp);
541ae68f 6322 tmp_stats[i++] =
ffb5df6c
JP		 6323 (u64)le32_to_cpu(stats->tmac_frms_oflow) << 32 |
6324 le32_to_cpu(stats->tmac_frms);
541ae68f 6325 tmp_stats[i++] =
ffb5df6c
JP		 6326 (u64)le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
6327 le32_to_cpu(stats->tmac_data_octets);
6328 tmp_stats[i++] = le64_to_cpu(stats->tmac_drop_frms);
541ae68f 6329 tmp_stats[i++] =
ffb5df6c
JP		 6330 (u64)le32_to_cpu(stats->tmac_mcst_frms_oflow) << 32 |
6331 le32_to_cpu(stats->tmac_mcst_frms);
541ae68f 6332 tmp_stats[i++] =
ffb5df6c
JP		 6333 (u64)le32_to_cpu(stats->tmac_bcst_frms_oflow) << 32 |
6334 le32_to_cpu(stats->tmac_bcst_frms);
6335 tmp_stats[i++] = le64_to_cpu(stats->tmac_pause_ctrl_frms);
bd1034f0 6336 tmp_stats[i++] =
ffb5df6c
JP		 6337 (u64)le32_to_cpu(stats->tmac_ttl_octets_oflow) << 32 |
6338 le32_to_cpu(stats->tmac_ttl_octets);
bd1034f0 6339 tmp_stats[i++] =
ffb5df6c
JP		 6340 (u64)le32_to_cpu(stats->tmac_ucst_frms_oflow) << 32 |
6341 le32_to_cpu(stats->tmac_ucst_frms);
d44570e4 6342 tmp_stats[i++] =
ffb5df6c
JP		 6343 (u64)le32_to_cpu(stats->tmac_nucst_frms_oflow) << 32 |
6344 le32_to_cpu(stats->tmac_nucst_frms);
541ae68f 6345 tmp_stats[i++] =
ffb5df6c
JP		 6346 (u64)le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
6347 le32_to_cpu(stats->tmac_any_err_frms);
6348 tmp_stats[i++] = le64_to_cpu(stats->tmac_ttl_less_fb_octets);
6349 tmp_stats[i++] = le64_to_cpu(stats->tmac_vld_ip_octets);
541ae68f 6350 tmp_stats[i++] =
ffb5df6c
JP		 6351 (u64)le32_to_cpu(stats->tmac_vld_ip_oflow) << 32 |
6352 le32_to_cpu(stats->tmac_vld_ip);
541ae68f 6353 tmp_stats[i++] =
ffb5df6c
JP		 6354 (u64)le32_to_cpu(stats->tmac_drop_ip_oflow) << 32 |
6355 le32_to_cpu(stats->tmac_drop_ip);
541ae68f 6356 tmp_stats[i++] =
ffb5df6c
JP		 6357 (u64)le32_to_cpu(stats->tmac_icmp_oflow) << 32 |
6358 le32_to_cpu(stats->tmac_icmp);
541ae68f 6359 tmp_stats[i++] =
ffb5df6c
JP		 6360 (u64)le32_to_cpu(stats->tmac_rst_tcp_oflow) << 32 |
6361 le32_to_cpu(stats->tmac_rst_tcp);
6362 tmp_stats[i++] = le64_to_cpu(stats->tmac_tcp);
6363 tmp_stats[i++] = (u64)le32_to_cpu(stats->tmac_udp_oflow) << 32 |
6364 le32_to_cpu(stats->tmac_udp);
541ae68f 6365 tmp_stats[i++] =
ffb5df6c
JP		 6366 (u64)le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
6367 le32_to_cpu(stats->rmac_vld_frms);
541ae68f 6368 tmp_stats[i++] =
ffb5df6c
JP		 6369 (u64)le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
6370 le32_to_cpu(stats->rmac_data_octets);
6371 tmp_stats[i++] = le64_to_cpu(stats->rmac_fcs_err_frms);
6372 tmp_stats[i++] = le64_to_cpu(stats->rmac_drop_frms);
541ae68f 6373 tmp_stats[i++] =
ffb5df6c
JP		 6374 (u64)le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
6375 le32_to_cpu(stats->rmac_vld_mcst_frms);
541ae68f 6376 tmp_stats[i++] =
ffb5df6c
JP		 6377 (u64)le32_to_cpu(stats->rmac_vld_bcst_frms_oflow) << 32 |
6378 le32_to_cpu(stats->rmac_vld_bcst_frms);
6379 tmp_stats[i++] = le32_to_cpu(stats->rmac_in_rng_len_err_frms);
6380 tmp_stats[i++] = le32_to_cpu(stats->rmac_out_rng_len_err_frms);
6381 tmp_stats[i++] = le64_to_cpu(stats->rmac_long_frms);
6382 tmp_stats[i++] = le64_to_cpu(stats->rmac_pause_ctrl_frms);
6383 tmp_stats[i++] = le64_to_cpu(stats->rmac_unsup_ctrl_frms);
d44570e4 6384 tmp_stats[i++] =
ffb5df6c
JP		 6385 (u64)le32_to_cpu(stats->rmac_ttl_octets_oflow) << 32 |
6386 le32_to_cpu(stats->rmac_ttl_octets);
bd1034f0 6387 tmp_stats[i++] =
ffb5df6c
JP		 6388 (u64)le32_to_cpu(stats->rmac_accepted_ucst_frms_oflow) << 32
6389 | le32_to_cpu(stats->rmac_accepted_ucst_frms);
d44570e4 6390 tmp_stats[i++] =
ffb5df6c
JP		 6391 (u64)le32_to_cpu(stats->rmac_accepted_nucst_frms_oflow)
6392 << 32 | le32_to_cpu(stats->rmac_accepted_nucst_frms);
541ae68f 6393 tmp_stats[i++] =
ffb5df6c
JP		 6394 (u64)le32_to_cpu(stats->rmac_discarded_frms_oflow) << 32 |
6395 le32_to_cpu(stats->rmac_discarded_frms);
d44570e4 6396 tmp_stats[i++] =
ffb5df6c
JP		 6397 (u64)le32_to_cpu(stats->rmac_drop_events_oflow)
6398 << 32 | le32_to_cpu(stats->rmac_drop_events);
6399 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_less_fb_octets);
6400 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_frms);
541ae68f 6401 tmp_stats[i++] =
ffb5df6c
JP		 6402 (u64)le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
6403 le32_to_cpu(stats->rmac_usized_frms);
541ae68f 6404 tmp_stats[i++] =
ffb5df6c
JP		 6405 (u64)le32_to_cpu(stats->rmac_osized_frms_oflow) << 32 |
6406 le32_to_cpu(stats->rmac_osized_frms);
541ae68f 6407 tmp_stats[i++] =
ffb5df6c
JP		 6408 (u64)le32_to_cpu(stats->rmac_frag_frms_oflow) << 32 |
6409 le32_to_cpu(stats->rmac_frag_frms);
541ae68f 6410 tmp_stats[i++] =
ffb5df6c
JP		 6411 (u64)le32_to_cpu(stats->rmac_jabber_frms_oflow) << 32 |
6412 le32_to_cpu(stats->rmac_jabber_frms);
6413 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_64_frms);
6414 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_65_127_frms);
6415 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_128_255_frms);
6416 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_256_511_frms);
6417 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_512_1023_frms);
6418 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_1024_1518_frms);
bd1034f0 6419 tmp_stats[i++] =
ffb5df6c
JP		 6420 (u64)le32_to_cpu(stats->rmac_ip_oflow) << 32 |
6421 le32_to_cpu(stats->rmac_ip);
6422 tmp_stats[i++] = le64_to_cpu(stats->rmac_ip_octets);
6423 tmp_stats[i++] = le32_to_cpu(stats->rmac_hdr_err_ip);
bd1034f0 6424 tmp_stats[i++] =
ffb5df6c
JP		 6425 (u64)le32_to_cpu(stats->rmac_drop_ip_oflow) << 32 |
6426 le32_to_cpu(stats->rmac_drop_ip);
bd1034f0 6427 tmp_stats[i++] =
ffb5df6c
JP		 6428 (u64)le32_to_cpu(stats->rmac_icmp_oflow) << 32 |
6429 le32_to_cpu(stats->rmac_icmp);
6430 tmp_stats[i++] = le64_to_cpu(stats->rmac_tcp);
bd1034f0 6431 tmp_stats[i++] =
ffb5df6c
JP		 6432 (u64)le32_to_cpu(stats->rmac_udp_oflow) << 32 |
6433 le32_to_cpu(stats->rmac_udp);
541ae68f 6434 tmp_stats[i++] =
ffb5df6c
JP		 6435 (u64)le32_to_cpu(stats->rmac_err_drp_udp_oflow) << 32 |
6436 le32_to_cpu(stats->rmac_err_drp_udp);
6437 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_err_sym);
6438 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q0);
6439 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q1);
6440 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q2);
6441 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q3);
6442 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q4);
6443 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q5);
6444 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q6);
6445 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q7);
6446 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q0);
6447 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q1);
6448 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q2);
6449 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q3);
6450 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q4);
6451 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q5);
6452 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q6);
6453 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q7);
541ae68f 6454 tmp_stats[i++] =
ffb5df6c
JP		 6455 (u64)le32_to_cpu(stats->rmac_pause_cnt_oflow) << 32 |
6456 le32_to_cpu(stats->rmac_pause_cnt);
6457 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_data_err_cnt);
6458 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_ctrl_err_cnt);
541ae68f 6459 tmp_stats[i++] =
ffb5df6c
JP		 6460 (u64)le32_to_cpu(stats->rmac_accepted_ip_oflow) << 32 |
6461 le32_to_cpu(stats->rmac_accepted_ip);
6462 tmp_stats[i++] = le32_to_cpu(stats->rmac_err_tcp);
6463 tmp_stats[i++] = le32_to_cpu(stats->rd_req_cnt);
6464 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_cnt);
6465 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_rtry_cnt);
6466 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_cnt);
6467 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_rd_ack_cnt);
6468 tmp_stats[i++] = le32_to_cpu(stats->wr_req_cnt);
6469 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_cnt);
6470 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_rtry_cnt);
6471 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_cnt);
6472 tmp_stats[i++] = le32_to_cpu(stats->wr_disc_cnt);
6473 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_wr_ack_cnt);
6474 tmp_stats[i++] = le32_to_cpu(stats->txp_wr_cnt);
6475 tmp_stats[i++] = le32_to_cpu(stats->txd_rd_cnt);
6476 tmp_stats[i++] = le32_to_cpu(stats->txd_wr_cnt);
6477 tmp_stats[i++] = le32_to_cpu(stats->rxd_rd_cnt);
6478 tmp_stats[i++] = le32_to_cpu(stats->rxd_wr_cnt);
6479 tmp_stats[i++] = le32_to_cpu(stats->txf_rd_cnt);
6480 tmp_stats[i++] = le32_to_cpu(stats->rxf_wr_cnt);
fa1f0cb3
SS		 6481
6482 /* Enhanced statistics exist only for Hercules */
d44570e4 6483 if (sp->device_type == XFRAME_II_DEVICE) {
fa1f0cb3 6484 tmp_stats[i++] =
ffb5df6c 6485 le64_to_cpu(stats->rmac_ttl_1519_4095_frms);
fa1f0cb3 6486 tmp_stats[i++] =
ffb5df6c 6487 le64_to_cpu(stats->rmac_ttl_4096_8191_frms);
fa1f0cb3 6488 tmp_stats[i++] =
ffb5df6c
JP		 6489 le64_to_cpu(stats->rmac_ttl_8192_max_frms);
6490 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_gt_max_frms);
6491 tmp_stats[i++] = le64_to_cpu(stats->rmac_osized_alt_frms);
6492 tmp_stats[i++] = le64_to_cpu(stats->rmac_jabber_alt_frms);
6493 tmp_stats[i++] = le64_to_cpu(stats->rmac_gt_max_alt_frms);
6494 tmp_stats[i++] = le64_to_cpu(stats->rmac_vlan_frms);
6495 tmp_stats[i++] = le32_to_cpu(stats->rmac_len_discard);
6496 tmp_stats[i++] = le32_to_cpu(stats->rmac_fcs_discard);
6497 tmp_stats[i++] = le32_to_cpu(stats->rmac_pf_discard);
6498 tmp_stats[i++] = le32_to_cpu(stats->rmac_da_discard);
6499 tmp_stats[i++] = le32_to_cpu(stats->rmac_red_discard);
6500 tmp_stats[i++] = le32_to_cpu(stats->rmac_rts_discard);
6501 tmp_stats[i++] = le32_to_cpu(stats->rmac_ingm_full_discard);
6502 tmp_stats[i++] = le32_to_cpu(stats->link_fault_cnt);
fa1f0cb3
SS		 6503 }
6504
7ba013ac 6505 tmp_stats[i++] = 0;
ffb5df6c
JP		 6506 tmp_stats[i++] = swstats->single_ecc_errs;
6507 tmp_stats[i++] = swstats->double_ecc_errs;
6508 tmp_stats[i++] = swstats->parity_err_cnt;
6509 tmp_stats[i++] = swstats->serious_err_cnt;
6510 tmp_stats[i++] = swstats->soft_reset_cnt;
6511 tmp_stats[i++] = swstats->fifo_full_cnt;
8116f3cf 6512 for (k = 0; k < MAX_RX_RINGS; k++)
ffb5df6c
JP		 6513 tmp_stats[i++] = swstats->ring_full_cnt[k];
6514 tmp_stats[i++] = xstats->alarm_transceiver_temp_high;
6515 tmp_stats[i++] = xstats->alarm_transceiver_temp_low;
6516 tmp_stats[i++] = xstats->alarm_laser_bias_current_high;
6517 tmp_stats[i++] = xstats->alarm_laser_bias_current_low;
6518 tmp_stats[i++] = xstats->alarm_laser_output_power_high;
6519 tmp_stats[i++] = xstats->alarm_laser_output_power_low;
6520 tmp_stats[i++] = xstats->warn_transceiver_temp_high;
6521 tmp_stats[i++] = xstats->warn_transceiver_temp_low;
6522 tmp_stats[i++] = xstats->warn_laser_bias_current_high;
6523 tmp_stats[i++] = xstats->warn_laser_bias_current_low;
6524 tmp_stats[i++] = xstats->warn_laser_output_power_high;
6525 tmp_stats[i++] = xstats->warn_laser_output_power_low;
6526 tmp_stats[i++] = swstats->clubbed_frms_cnt;
6527 tmp_stats[i++] = swstats->sending_both;
6528 tmp_stats[i++] = swstats->outof_sequence_pkts;
6529 tmp_stats[i++] = swstats->flush_max_pkts;
6530 if (swstats->num_aggregations) {
6531 u64 tmp = swstats->sum_avg_pkts_aggregated;
bd1034f0 6532 int count = 0;
6aa20a22 6533 /*
bd1034f0
AR		 6534 * Since 64-bit divide does not work on all platforms,
6535 * do repeated subtraction.
6536 */
ffb5df6c
JP		 6537 while (tmp >= swstats->num_aggregations) {
6538 tmp -= swstats->num_aggregations;
bd1034f0
AR		 6539 count++;
6540 }
6541 tmp_stats[i++] = count;
d44570e4 6542 } else
bd1034f0 6543 tmp_stats[i++] = 0;
ffb5df6c
JP		 6544 tmp_stats[i++] = swstats->mem_alloc_fail_cnt;
6545 tmp_stats[i++] = swstats->pci_map_fail_cnt;
6546 tmp_stats[i++] = swstats->watchdog_timer_cnt;
6547 tmp_stats[i++] = swstats->mem_allocated;
6548 tmp_stats[i++] = swstats->mem_freed;
6549 tmp_stats[i++] = swstats->link_up_cnt;
6550 tmp_stats[i++] = swstats->link_down_cnt;
6551 tmp_stats[i++] = swstats->link_up_time;
6552 tmp_stats[i++] = swstats->link_down_time;
6553
6554 tmp_stats[i++] = swstats->tx_buf_abort_cnt;
6555 tmp_stats[i++] = swstats->tx_desc_abort_cnt;
6556 tmp_stats[i++] = swstats->tx_parity_err_cnt;
6557 tmp_stats[i++] = swstats->tx_link_loss_cnt;
6558 tmp_stats[i++] = swstats->tx_list_proc_err_cnt;
6559
6560 tmp_stats[i++] = swstats->rx_parity_err_cnt;
6561 tmp_stats[i++] = swstats->rx_abort_cnt;
6562 tmp_stats[i++] = swstats->rx_parity_abort_cnt;
6563 tmp_stats[i++] = swstats->rx_rda_fail_cnt;
6564 tmp_stats[i++] = swstats->rx_unkn_prot_cnt;
6565 tmp_stats[i++] = swstats->rx_fcs_err_cnt;
6566 tmp_stats[i++] = swstats->rx_buf_size_err_cnt;
6567 tmp_stats[i++] = swstats->rx_rxd_corrupt_cnt;
6568 tmp_stats[i++] = swstats->rx_unkn_err_cnt;
6569 tmp_stats[i++] = swstats->tda_err_cnt;
6570 tmp_stats[i++] = swstats->pfc_err_cnt;
6571 tmp_stats[i++] = swstats->pcc_err_cnt;
6572 tmp_stats[i++] = swstats->tti_err_cnt;
6573 tmp_stats[i++] = swstats->tpa_err_cnt;
6574 tmp_stats[i++] = swstats->sm_err_cnt;
6575 tmp_stats[i++] = swstats->lso_err_cnt;
6576 tmp_stats[i++] = swstats->mac_tmac_err_cnt;
6577 tmp_stats[i++] = swstats->mac_rmac_err_cnt;
6578 tmp_stats[i++] = swstats->xgxs_txgxs_err_cnt;
6579 tmp_stats[i++] = swstats->xgxs_rxgxs_err_cnt;
6580 tmp_stats[i++] = swstats->rc_err_cnt;
6581 tmp_stats[i++] = swstats->prc_pcix_err_cnt;
6582 tmp_stats[i++] = swstats->rpa_err_cnt;
6583 tmp_stats[i++] = swstats->rda_err_cnt;
6584 tmp_stats[i++] = swstats->rti_err_cnt;
6585 tmp_stats[i++] = swstats->mc_err_cnt;
1da177e4
LT		 6586}
6587
ac1f60db 6588static int s2io_ethtool_get_regs_len(struct net_device *dev)
1da177e4 6589{
d44570e4 6590 return XENA_REG_SPACE;
1da177e4
LT		 6591}
6592
6593
d44570e4 6594static u32 s2io_ethtool_get_rx_csum(struct net_device *dev)
1da177e4 6595{
4cf1653a 6596 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 6597
d44570e4 6598 return sp->rx_csum;
1da177e4 6599}
ac1f60db
AB		 6600
6601static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
1da177e4 6602{
4cf1653a 6603 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 6604
6605 if (data)
6606 sp->rx_csum = 1;
6607 else
6608 sp->rx_csum = 0;
6609
6610 return 0;
6611}
ac1f60db
AB		 6612
6613static int s2io_get_eeprom_len(struct net_device *dev)
1da177e4 6614{
d44570e4 6615 return XENA_EEPROM_SPACE;
1da177e4
LT		 6616}
6617
b9f2c044 6618static int s2io_get_sset_count(struct net_device *dev, int sset)
1da177e4 6619{
4cf1653a 6620 struct s2io_nic *sp = netdev_priv(dev);
b9f2c044
JG		 6621
6622 switch (sset) {
6623 case ETH_SS_TEST:
6624 return S2IO_TEST_LEN;
6625 case ETH_SS_STATS:
d44570e4 6626 switch (sp->device_type) {
b9f2c044
JG		 6627 case XFRAME_I_DEVICE:
6628 return XFRAME_I_STAT_LEN;
6629 case XFRAME_II_DEVICE:
6630 return XFRAME_II_STAT_LEN;
6631 default:
6632 return 0;
6633 }
6634 default:
6635 return -EOPNOTSUPP;
6636 }
1da177e4 6637}
ac1f60db
AB		 6638
6639static void s2io_ethtool_get_strings(struct net_device *dev,
d44570e4 6640 u32 stringset, u8 *data)
1da177e4 6641{
fa1f0cb3 6642 int stat_size = 0;
4cf1653a 6643 struct s2io_nic *sp = netdev_priv(dev);
fa1f0cb3 6644
1da177e4
LT		 6645 switch (stringset) {
6646 case ETH_SS_TEST:
6647 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6648 break;
6649 case ETH_SS_STATS:
fa1f0cb3 6650 stat_size = sizeof(ethtool_xena_stats_keys);
d44570e4
JP		 6651 memcpy(data, &ethtool_xena_stats_keys, stat_size);
6652 if (sp->device_type == XFRAME_II_DEVICE) {
fa1f0cb3 6653 memcpy(data + stat_size,
d44570e4
JP		 6654 &ethtool_enhanced_stats_keys,
6655 sizeof(ethtool_enhanced_stats_keys));
fa1f0cb3
SS		 6656 stat_size += sizeof(ethtool_enhanced_stats_keys);
6657 }
6658
6659 memcpy(data + stat_size, &ethtool_driver_stats_keys,
d44570e4 6660 sizeof(ethtool_driver_stats_keys));
1da177e4
LT		 6661 }
6662}
1da177e4 6663
ac1f60db 6664static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
1da177e4
LT		 6665{
6666 if (data)
6667 dev->features |= NETIF_F_IP_CSUM;
6668 else
6669 dev->features &= ~NETIF_F_IP_CSUM;
6670
6671 return 0;
6672}
6673
75c30b13
AR		 6674static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6675{
6676 return (dev->features & NETIF_F_TSO) != 0;
6677}
6678static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6679{
6680 if (data)
6681 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6682 else
6683 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6684
6685 return 0;
6686}
1da177e4 6687
7282d491 6688static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 6689 .get_settings = s2io_ethtool_gset,
6690 .set_settings = s2io_ethtool_sset,
6691 .get_drvinfo = s2io_ethtool_gdrvinfo,
6692 .get_regs_len = s2io_ethtool_get_regs_len,
6693 .get_regs = s2io_ethtool_gregs,
6694 .get_link = ethtool_op_get_link,
6695 .get_eeprom_len = s2io_get_eeprom_len,
6696 .get_eeprom = s2io_ethtool_geeprom,
6697 .set_eeprom = s2io_ethtool_seeprom,
0cec35eb 6698 .get_ringparam = s2io_ethtool_gringparam,
1da177e4
LT		 6699 .get_pauseparam = s2io_ethtool_getpause_data,
6700 .set_pauseparam = s2io_ethtool_setpause_data,
6701 .get_rx_csum = s2io_ethtool_get_rx_csum,
6702 .set_rx_csum = s2io_ethtool_set_rx_csum,
1da177e4 6703 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
1da177e4 6704 .set_sg = ethtool_op_set_sg,
75c30b13
AR		 6705 .get_tso = s2io_ethtool_op_get_tso,
6706 .set_tso = s2io_ethtool_op_set_tso,
fed5eccd 6707 .set_ufo = ethtool_op_set_ufo,
1da177e4
LT		 6708 .self_test = s2io_ethtool_test,
6709 .get_strings = s2io_ethtool_get_strings,
6710 .phys_id = s2io_ethtool_idnic,
b9f2c044
JG		 6711 .get_ethtool_stats = s2io_get_ethtool_stats,
6712 .get_sset_count = s2io_get_sset_count,
1da177e4
LT		 6713};
6714
6715/**
20346722 6716 * s2io_ioctl - Entry point for the Ioctl
1da177e4
LT		 6717 * @dev : Device pointer.
6718 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6719 * a proprietary structure used to pass information to the driver.
6720 * @cmd : This is used to distinguish between the different commands that
6721 * can be passed to the IOCTL functions.
6722 * Description:
20346722
K		 6723 * Currently there are no special functionality supported in IOCTL, hence
6724 * function always return EOPNOTSUPPORTED
1da177e4
LT		 6725 */
6726
ac1f60db 6727static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1da177e4
LT		 6728{
6729 return -EOPNOTSUPP;
6730}
6731
6732/**
6733 * s2io_change_mtu - entry point to change MTU size for the device.
6734 * @dev : device pointer.
6735 * @new_mtu : the new MTU size for the device.
6736 * Description: A driver entry point to change MTU size for the device.
6737 * Before changing the MTU the device must be stopped.
6738 * Return value:
6739 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6740 * file on failure.
6741 */
6742
ac1f60db 6743static int s2io_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 6744{
4cf1653a 6745 struct s2io_nic *sp = netdev_priv(dev);
9f74ffde 6746 int ret = 0;
1da177e4
LT		 6747
6748 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
d44570e4 6749 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", dev->name);
1da177e4
LT		 6750 return -EPERM;
6751 }
6752
1da177e4 6753 dev->mtu = new_mtu;
d8892c6e 6754 if (netif_running(dev)) {
3a3d5756 6755 s2io_stop_all_tx_queue(sp);
e6a8fee2 6756 s2io_card_down(sp);
9f74ffde
SH		 6757 ret = s2io_card_up(sp);
6758 if (ret) {
d8892c6e 6759 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
b39d66a8 6760 __func__);
9f74ffde 6761 return ret;
d8892c6e 6762 }
3a3d5756 6763 s2io_wake_all_tx_queue(sp);
d8892c6e 6764 } else { /* Device is down */
1ee6dd77 6765 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d8892c6e
K		 6766 u64 val64 = new_mtu;
6767
6768 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6769 }
1da177e4 6770
9f74ffde 6771 return ret;
1da177e4
LT		 6772}
6773
1da177e4
LT		 6774/**
6775 * s2io_set_link - Set the LInk status
6776 * @data: long pointer to device private structue
6777 * Description: Sets the link status for the adapter
6778 */
6779
c4028958 6780static void s2io_set_link(struct work_struct *work)
1da177e4 6781{
d44570e4
JP		 6782 struct s2io_nic *nic = container_of(work, struct s2io_nic,
6783 set_link_task);
1da177e4 6784 struct net_device *dev = nic->dev;
1ee6dd77 6785 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 6786 register u64 val64;
6787 u16 subid;
6788
22747d6b
FR		 6789 rtnl_lock();
6790
6791 if (!netif_running(dev))
6792 goto out_unlock;
6793
92b84437 6794 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
1da177e4 6795 /* The card is being reset, no point doing anything */
22747d6b 6796 goto out_unlock;
1da177e4
LT		 6797 }
6798
6799 subid = nic->pdev->subsystem_device;
a371a07d
K		 6800 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6801 /*
6802 * Allow a small delay for the NICs self initiated
6803 * cleanup to complete.
6804 */
6805 msleep(100);
6806 }
1da177e4
LT		 6807
6808 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6809 if (LINK_IS_UP(val64)) {
6810 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6811 if (verify_xena_quiescence(nic)) {
6812 val64 = readq(&bar0->adapter_control);
6813 val64 |= ADAPTER_CNTL_EN;
1da177e4 6814 writeq(val64, &bar0->adapter_control);
19a60522 6815 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
d44570e4 6816 nic->device_type, subid)) {
19a60522
SS		 6817 val64 = readq(&bar0->gpio_control);
6818 val64 |= GPIO_CTRL_GPIO_0;
6819 writeq(val64, &bar0->gpio_control);
6820 val64 = readq(&bar0->gpio_control);
6821 } else {
6822 val64 |= ADAPTER_LED_ON;
6823 writeq(val64, &bar0->adapter_control);
a371a07d 6824 }
f957bcf0 6825 nic->device_enabled_once = true;
19a60522 6826 } else {
9e39f7c5
JP		 6827 DBG_PRINT(ERR_DBG,
6828 "%s: Error: device is not Quiescent\n",
6829 dev->name);
3a3d5756 6830 s2io_stop_all_tx_queue(nic);
1da177e4 6831 }
19a60522 6832 }
92c48799
SS		 6833 val64 = readq(&bar0->adapter_control);
6834 val64 |= ADAPTER_LED_ON;
6835 writeq(val64, &bar0->adapter_control);
6836 s2io_link(nic, LINK_UP);
19a60522
SS		 6837 } else {
6838 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6839 subid)) {
6840 val64 = readq(&bar0->gpio_control);
6841 val64 &= ~GPIO_CTRL_GPIO_0;
6842 writeq(val64, &bar0->gpio_control);
6843 val64 = readq(&bar0->gpio_control);
1da177e4 6844 }
92c48799
SS		 6845 /* turn off LED */
6846 val64 = readq(&bar0->adapter_control);
d44570e4 6847 val64 = val64 & (~ADAPTER_LED_ON);
92c48799 6848 writeq(val64, &bar0->adapter_control);
19a60522 6849 s2io_link(nic, LINK_DOWN);
1da177e4 6850 }
92b84437 6851 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
22747d6b
FR		 6852
6853out_unlock:
d8d70caf 6854 rtnl_unlock();
1da177e4
LT		 6855}
6856
1ee6dd77 6857static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
d44570e4
JP		 6858 struct buffAdd *ba,
6859 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6860 u64 *temp2, int size)
5d3213cc
AR		 6861{
6862 struct net_device *dev = sp->dev;
491abf25 6863 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
5d3213cc
AR		 6864
6865 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6d517a27 6866 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
5d3213cc
AR		 6867 /* allocate skb */
6868 if (*skb) {
6869 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6870 /*
6871 * As Rx frame are not going to be processed,
6872 * using same mapped address for the Rxd
6873 * buffer pointer
6874 */
6d517a27 6875 rxdp1->Buffer0_ptr = *temp0;
5d3213cc
AR		 6876 } else {
6877 *skb = dev_alloc_skb(size);
6878 if (!(*skb)) {
9e39f7c5
JP		 6879 DBG_PRINT(INFO_DBG,
6880 "%s: Out of memory to allocate %s\n",
6881 dev->name, "1 buf mode SKBs");
ffb5df6c 6882 stats->mem_alloc_fail_cnt++;
5d3213cc
AR		 6883 return -ENOMEM ;
6884 }
ffb5df6c 6885 stats->mem_allocated += (*skb)->truesize;
5d3213cc
AR		 6886 /* storing the mapped addr in a temp variable
6887 * such it will be used for next rxd whose
6888 * Host Control is NULL
6889 */
6d517a27 6890 rxdp1->Buffer0_ptr = *temp0 =
d44570e4
JP		 6891 pci_map_single(sp->pdev, (*skb)->data,
6892 size - NET_IP_ALIGN,
6893 PCI_DMA_FROMDEVICE);
8d8bb39b 6894 if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
491abf25 6895 goto memalloc_failed;
5d3213cc
AR		 6896 rxdp->Host_Control = (unsigned long) (*skb);
6897 }
6898 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6d517a27 6899 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
5d3213cc
AR		 6900 /* Two buffer Mode */
6901 if (*skb) {
6d517a27
VP		 6902 rxdp3->Buffer2_ptr = *temp2;
6903 rxdp3->Buffer0_ptr = *temp0;
6904 rxdp3->Buffer1_ptr = *temp1;
5d3213cc
AR		 6905 } else {
6906 *skb = dev_alloc_skb(size);
2ceaac75 6907 if (!(*skb)) {
9e39f7c5
JP		 6908 DBG_PRINT(INFO_DBG,
6909 "%s: Out of memory to allocate %s\n",
6910 dev->name,
6911 "2 buf mode SKBs");
ffb5df6c 6912 stats->mem_alloc_fail_cnt++;
2ceaac75
DR		 6913 return -ENOMEM;
6914 }
ffb5df6c 6915 stats->mem_allocated += (*skb)->truesize;
6d517a27 6916 rxdp3->Buffer2_ptr = *temp2 =
5d3213cc
AR		 6917 pci_map_single(sp->pdev, (*skb)->data,
6918 dev->mtu + 4,
6919 PCI_DMA_FROMDEVICE);
8d8bb39b 6920 if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
491abf25 6921 goto memalloc_failed;
6d517a27 6922 rxdp3->Buffer0_ptr = *temp0 =
d44570e4
JP		 6923 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6924 PCI_DMA_FROMDEVICE);
8d8bb39b 6925 if (pci_dma_mapping_error(sp->pdev,
d44570e4
JP		 6926 rxdp3->Buffer0_ptr)) {
6927 pci_unmap_single(sp->pdev,
6928 (dma_addr_t)rxdp3->Buffer2_ptr,
6929 dev->mtu + 4,
6930 PCI_DMA_FROMDEVICE);
491abf25
VP		 6931 goto memalloc_failed;
6932 }
5d3213cc
AR		 6933 rxdp->Host_Control = (unsigned long) (*skb);
6934
6935 /* Buffer-1 will be dummy buffer not used */
6d517a27 6936 rxdp3->Buffer1_ptr = *temp1 =
5d3213cc 6937 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
d44570e4 6938 PCI_DMA_FROMDEVICE);
8d8bb39b 6939 if (pci_dma_mapping_error(sp->pdev,
d44570e4
JP		 6940 rxdp3->Buffer1_ptr)) {
6941 pci_unmap_single(sp->pdev,
6942 (dma_addr_t)rxdp3->Buffer0_ptr,
6943 BUF0_LEN, PCI_DMA_FROMDEVICE);
6944 pci_unmap_single(sp->pdev,
6945 (dma_addr_t)rxdp3->Buffer2_ptr,
6946 dev->mtu + 4,
6947 PCI_DMA_FROMDEVICE);
491abf25
VP		 6948 goto memalloc_failed;
6949 }
5d3213cc
AR		 6950 }
6951 }
6952 return 0;
d44570e4
JP		 6953
6954memalloc_failed:
6955 stats->pci_map_fail_cnt++;
6956 stats->mem_freed += (*skb)->truesize;
6957 dev_kfree_skb(*skb);
6958 return -ENOMEM;
5d3213cc 6959}
491abf25 6960
1ee6dd77
RB		 6961static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6962 int size)
5d3213cc
AR		 6963{
6964 struct net_device *dev = sp->dev;
6965 if (sp->rxd_mode == RXD_MODE_1) {
d44570e4 6966 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
5d3213cc
AR		 6967 } else if (sp->rxd_mode == RXD_MODE_3B) {
6968 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6969 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
d44570e4 6970 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu + 4);
5d3213cc
AR		 6971 }
6972}
6973
1ee6dd77 6974static int rxd_owner_bit_reset(struct s2io_nic *sp)
5d3213cc
AR		 6975{
6976 int i, j, k, blk_cnt = 0, size;
5d3213cc 6977 struct config_param *config = &sp->config;
ffb5df6c 6978 struct mac_info *mac_control = &sp->mac_control;
5d3213cc 6979 struct net_device *dev = sp->dev;
1ee6dd77 6980 struct RxD_t *rxdp = NULL;
5d3213cc 6981 struct sk_buff *skb = NULL;
1ee6dd77 6982 struct buffAdd *ba = NULL;
5d3213cc
AR		 6983 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6984
6985 /* Calculate the size based on ring mode */
6986 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6987 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6988 if (sp->rxd_mode == RXD_MODE_1)
6989 size += NET_IP_ALIGN;
6990 else if (sp->rxd_mode == RXD_MODE_3B)
6991 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
5d3213cc
AR		 6992
6993 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 6994 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
6995 struct ring_info *ring = &mac_control->rings[i];
6996
d44570e4 6997 blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] + 1);
5d3213cc
AR		 6998
6999 for (j = 0; j < blk_cnt; j++) {
7000 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
d44570e4
JP		 7001 rxdp = ring->rx_blocks[j].rxds[k].virt_addr;
7002 if (sp->rxd_mode == RXD_MODE_3B)
13d866a9 7003 ba = &ring->ba[j][k];
d44570e4
JP		 7004 if (set_rxd_buffer_pointer(sp, rxdp, ba, &skb,
7005 (u64 *)&temp0_64,
7006 (u64 *)&temp1_64,
7007 (u64 *)&temp2_64,
7008 size) == -ENOMEM) {
ac1f90d6
SS		 7009 return 0;
7010 }
5d3213cc
AR		 7011
7012 set_rxd_buffer_size(sp, rxdp, size);
7013 wmb();
7014 /* flip the Ownership bit to Hardware */
7015 rxdp->Control_1 |= RXD_OWN_XENA;
7016 }
7017 }
7018 }
7019 return 0;
7020
7021}
7022
d44570e4 7023static int s2io_add_isr(struct s2io_nic *sp)
1da177e4 7024{
e6a8fee2 7025 int ret = 0;
c92ca04b 7026 struct net_device *dev = sp->dev;
e6a8fee2 7027 int err = 0;
1da177e4 7028
eaae7f72 7029 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7030 ret = s2io_enable_msi_x(sp);
7031 if (ret) {
7032 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
eaae7f72 7033 sp->config.intr_type = INTA;
20346722 7034 }
1da177e4 7035
d44570e4
JP		 7036 /*
7037 * Store the values of the MSIX table in
7038 * the struct s2io_nic structure
7039 */
e6a8fee2 7040 store_xmsi_data(sp);
c92ca04b 7041
e6a8fee2 7042 /* After proper initialization of H/W, register ISR */
eaae7f72 7043 if (sp->config.intr_type == MSI_X) {
ac731ab6
SH		 7044 int i, msix_rx_cnt = 0;
7045
f61e0a35
SH		 7046 for (i = 0; i < sp->num_entries; i++) {
7047 if (sp->s2io_entries[i].in_use == MSIX_FLG) {
7048 if (sp->s2io_entries[i].type ==
d44570e4 7049 MSIX_RING_TYPE) {
ac731ab6
SH		 7050 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7051 dev->name, i);
7052 err = request_irq(sp->entries[i].vector,
d44570e4
JP		 7053 s2io_msix_ring_handle,
7054 0,
7055 sp->desc[i],
7056 sp->s2io_entries[i].arg);
ac731ab6 7057 } else if (sp->s2io_entries[i].type ==
d44570e4 7058 MSIX_ALARM_TYPE) {
ac731ab6 7059 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
d44570e4 7060 dev->name, i);
ac731ab6 7061 err = request_irq(sp->entries[i].vector,
d44570e4
JP		 7062 s2io_msix_fifo_handle,
7063 0,
7064 sp->desc[i],
7065 sp->s2io_entries[i].arg);
ac731ab6 7066
fb6a825b 7067 }
ac731ab6
SH		 7068 /* if either data or addr is zero print it. */
7069 if (!(sp->msix_info[i].addr &&
d44570e4 7070 sp->msix_info[i].data)) {
ac731ab6 7071 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7072 "%s @Addr:0x%llx Data:0x%llx\n",
7073 sp->desc[i],
7074 (unsigned long long)
7075 sp->msix_info[i].addr,
7076 (unsigned long long)
7077 ntohl(sp->msix_info[i].data));
ac731ab6 7078 } else
fb6a825b 7079 msix_rx_cnt++;
ac731ab6
SH		 7080 if (err) {
7081 remove_msix_isr(sp);
7082
7083 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7084 "%s:MSI-X-%d registration "
7085 "failed\n", dev->name, i);
ac731ab6
SH		 7086
7087 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7088 "%s: Defaulting to INTA\n",
7089 dev->name);
ac731ab6
SH		 7090 sp->config.intr_type = INTA;
7091 break;
fb6a825b 7092 }
ac731ab6
SH		 7093 sp->s2io_entries[i].in_use =
7094 MSIX_REGISTERED_SUCCESS;
c92ca04b 7095 }
e6a8fee2 7096 }
18b2b7bd 7097 if (!err) {
6cef2b8e 7098 pr_info("MSI-X-RX %d entries enabled\n", --msix_rx_cnt);
9e39f7c5
JP		 7099 DBG_PRINT(INFO_DBG,
7100 "MSI-X-TX entries enabled through alarm vector\n");
18b2b7bd 7101 }
e6a8fee2 7102 }
eaae7f72 7103 if (sp->config.intr_type == INTA) {
d44570e4
JP		 7104 err = request_irq((int)sp->pdev->irq, s2io_isr, IRQF_SHARED,
7105 sp->name, dev);
e6a8fee2
AR		 7106 if (err) {
7107 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7108 dev->name);
7109 return -1;
7110 }
7111 }
7112 return 0;
7113}
d44570e4
JP		 7114
7115static void s2io_rem_isr(struct s2io_nic *sp)
e6a8fee2 7116{
18b2b7bd
SH		 7117 if (sp->config.intr_type == MSI_X)
7118 remove_msix_isr(sp);
7119 else
7120 remove_inta_isr(sp);
e6a8fee2
AR		 7121}
7122
d44570e4 7123static void do_s2io_card_down(struct s2io_nic *sp, int do_io)
e6a8fee2
AR		 7124{
7125 int cnt = 0;
1ee6dd77 7126 struct XENA_dev_config __iomem *bar0 = sp->bar0;
e6a8fee2 7127 register u64 val64 = 0;
5f490c96
SH		 7128 struct config_param *config;
7129 config = &sp->config;
e6a8fee2 7130
9f74ffde
SH		 7131 if (!is_s2io_card_up(sp))
7132 return;
7133
e6a8fee2
AR		 7134 del_timer_sync(&sp->alarm_timer);
7135 /* If s2io_set_link task is executing, wait till it completes. */
d44570e4 7136 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state)))
e6a8fee2 7137 msleep(50);
92b84437 7138 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
e6a8fee2 7139
5f490c96 7140 /* Disable napi */
f61e0a35
SH		 7141 if (sp->config.napi) {
7142 int off = 0;
7143 if (config->intr_type == MSI_X) {
7144 for (; off < sp->config.rx_ring_num; off++)
7145 napi_disable(&sp->mac_control.rings[off].napi);
d44570e4 7146 }
f61e0a35
SH		 7147 else
7148 napi_disable(&sp->napi);
7149 }
5f490c96 7150
e6a8fee2 7151 /* disable Tx and Rx traffic on the NIC */
d796fdb7
LV		 7152 if (do_io)
7153 stop_nic(sp);
e6a8fee2
AR		 7154
7155 s2io_rem_isr(sp);
1da177e4 7156
01e16faa
SH		 7157 /* stop the tx queue, indicate link down */
7158 s2io_link(sp, LINK_DOWN);
7159
1da177e4 7160 /* Check if the device is Quiescent and then Reset the NIC */
d44570e4 7161 while (do_io) {
5d3213cc
AR		 7162 /* As per the HW requirement we need to replenish the
7163 * receive buffer to avoid the ring bump. Since there is
7164 * no intention of processing the Rx frame at this pointwe are
7165 * just settting the ownership bit of rxd in Each Rx
7166 * ring to HW and set the appropriate buffer size
7167 * based on the ring mode
7168 */
7169 rxd_owner_bit_reset(sp);
7170
1da177e4 7171 val64 = readq(&bar0->adapter_status);
19a60522 7172 if (verify_xena_quiescence(sp)) {
d44570e4
JP		 7173 if (verify_pcc_quiescent(sp, sp->device_enabled_once))
7174 break;
1da177e4
LT		 7175 }
7176
7177 msleep(50);
7178 cnt++;
7179 if (cnt == 10) {
9e39f7c5
JP		 7180 DBG_PRINT(ERR_DBG, "Device not Quiescent - "
7181 "adapter status reads 0x%llx\n",
d44570e4 7182 (unsigned long long)val64);
1da177e4
LT		 7183 break;
7184 }
d796fdb7
LV		 7185 }
7186 if (do_io)
7187 s2io_reset(sp);
1da177e4 7188
7ba013ac 7189 /* Free all Tx buffers */
1da177e4 7190 free_tx_buffers(sp);
7ba013ac
K		 7191
7192 /* Free all Rx buffers */
1da177e4
LT		 7193 free_rx_buffers(sp);
7194
92b84437 7195 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
1da177e4
LT		 7196}
7197
d44570e4 7198static void s2io_card_down(struct s2io_nic *sp)
d796fdb7
LV		 7199{
7200 do_s2io_card_down(sp, 1);
7201}
7202
d44570e4 7203static int s2io_card_up(struct s2io_nic *sp)
1da177e4 7204{
cc6e7c44 7205 int i, ret = 0;
1da177e4 7206 struct config_param *config;
ffb5df6c 7207 struct mac_info *mac_control;
d44570e4 7208 struct net_device *dev = (struct net_device *)sp->dev;
e6a8fee2 7209 u16 interruptible;
1da177e4
LT		 7210
7211 /* Initialize the H/W I/O registers */
9f74ffde
SH		 7212 ret = init_nic(sp);
7213 if (ret != 0) {
1da177e4
LT		 7214 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7215 dev->name);
9f74ffde
SH		 7216 if (ret != -EIO)
7217 s2io_reset(sp);
7218 return ret;
1da177e4
LT		 7219 }
7220
20346722
K		 7221 /*
7222 * Initializing the Rx buffers. For now we are considering only 1
1da177e4
LT		 7223 * Rx ring and initializing buffers into 30 Rx blocks
7224 */
1da177e4 7225 config = &sp->config;
ffb5df6c 7226 mac_control = &sp->mac_control;
1da177e4
LT		 7227
7228 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7229 struct ring_info *ring = &mac_control->rings[i];
7230
7231 ring->mtu = dev->mtu;
7232 ret = fill_rx_buffers(sp, ring, 1);
0425b46a 7233 if (ret) {
1da177e4
LT		 7234 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7235 dev->name);
7236 s2io_reset(sp);
7237 free_rx_buffers(sp);
7238 return -ENOMEM;
7239 }
7240 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
13d866a9 7241 ring->rx_bufs_left);
1da177e4 7242 }
5f490c96
SH		 7243
7244 /* Initialise napi */
f61e0a35 7245 if (config->napi) {
f61e0a35
SH		 7246 if (config->intr_type == MSI_X) {
7247 for (i = 0; i < sp->config.rx_ring_num; i++)
7248 napi_enable(&sp->mac_control.rings[i].napi);
7249 } else {
7250 napi_enable(&sp->napi);
7251 }
7252 }
5f490c96 7253
19a60522
SS		 7254 /* Maintain the state prior to the open */
7255 if (sp->promisc_flg)
7256 sp->promisc_flg = 0;
7257 if (sp->m_cast_flg) {
7258 sp->m_cast_flg = 0;
d44570e4 7259 sp->all_multi_pos = 0;
19a60522 7260 }
1da177e4
LT		 7261
7262 /* Setting its receive mode */
7263 s2io_set_multicast(dev);
7264
7d3d0439 7265 if (sp->lro) {
b41477f3 7266 /* Initialize max aggregatable pkts per session based on MTU */
7d3d0439 7267 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
d44570e4 7268 /* Check if we can use (if specified) user provided value */
7d3d0439
RA		 7269 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7270 sp->lro_max_aggr_per_sess = lro_max_pkts;
7271 }
7272
1da177e4
LT		 7273 /* Enable Rx Traffic and interrupts on the NIC */
7274 if (start_nic(sp)) {
7275 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
1da177e4 7276 s2io_reset(sp);
e6a8fee2
AR		 7277 free_rx_buffers(sp);
7278 return -ENODEV;
7279 }
7280
7281 /* Add interrupt service routine */
7282 if (s2io_add_isr(sp) != 0) {
eaae7f72 7283 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7284 s2io_rem_isr(sp);
7285 s2io_reset(sp);
1da177e4
LT		 7286 free_rx_buffers(sp);
7287 return -ENODEV;
7288 }
7289
25fff88e
K		 7290 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7291
01e16faa
SH		 7292 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7293
e6a8fee2 7294 /* Enable select interrupts */
9caab458 7295 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
01e16faa
SH		 7296 if (sp->config.intr_type != INTA) {
7297 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7298 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7299 } else {
e6a8fee2 7300 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 7301 interruptible |= TX_PIC_INTR;
e6a8fee2
AR		 7302 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7303 }
7304
1da177e4
LT		 7305 return 0;
7306}
7307
20346722 7308/**
1da177e4
LT		 7309 * s2io_restart_nic - Resets the NIC.
7310 * @data : long pointer to the device private structure
7311 * Description:
7312 * This function is scheduled to be run by the s2io_tx_watchdog
20346722 7313 * function after 0.5 secs to reset the NIC. The idea is to reduce
1da177e4
LT		 7314 * the run time of the watch dog routine which is run holding a
7315 * spin lock.
7316 */
7317
c4028958 7318static void s2io_restart_nic(struct work_struct *work)
1da177e4 7319{
1ee6dd77 7320 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
c4028958 7321 struct net_device *dev = sp->dev;
1da177e4 7322
22747d6b
FR		 7323 rtnl_lock();
7324
7325 if (!netif_running(dev))
7326 goto out_unlock;
7327
e6a8fee2 7328 s2io_card_down(sp);
1da177e4 7329 if (s2io_card_up(sp)) {
d44570e4 7330 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", dev->name);
1da177e4 7331 }
3a3d5756 7332 s2io_wake_all_tx_queue(sp);
d44570e4 7333 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", dev->name);
22747d6b
FR		 7334out_unlock:
7335 rtnl_unlock();
1da177e4
LT		 7336}
7337
20346722
K		 7338/**
7339 * s2io_tx_watchdog - Watchdog for transmit side.
1da177e4
LT		 7340 * @dev : Pointer to net device structure
7341 * Description:
7342 * This function is triggered if the Tx Queue is stopped
7343 * for a pre-defined amount of time when the Interface is still up.
7344 * If the Interface is jammed in such a situation, the hardware is
7345 * reset (by s2io_close) and restarted again (by s2io_open) to
7346 * overcome any problem that might have been caused in the hardware.
7347 * Return value:
7348 * void
7349 */
7350
7351static void s2io_tx_watchdog(struct net_device *dev)
7352{
4cf1653a 7353 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c 7354 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 7355
7356 if (netif_carrier_ok(dev)) {
ffb5df6c 7357 swstats->watchdog_timer_cnt++;
1da177e4 7358 schedule_work(&sp->rst_timer_task);
ffb5df6c 7359 swstats->soft_reset_cnt++;
1da177e4
LT		 7360 }
7361}
7362
7363/**
7364 * rx_osm_handler - To perform some OS related operations on SKB.
7365 * @sp: private member of the device structure,pointer to s2io_nic structure.
7366 * @skb : the socket buffer pointer.
7367 * @len : length of the packet
7368 * @cksum : FCS checksum of the frame.
7369 * @ring_no : the ring from which this RxD was extracted.
20346722 7370 * Description:
b41477f3 7371 * This function is called by the Rx interrupt serivce routine to perform
1da177e4
LT		 7372 * some OS related operations on the SKB before passing it to the upper
7373 * layers. It mainly checks if the checksum is OK, if so adds it to the
7374 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7375 * to the upper layer. If the checksum is wrong, it increments the Rx
7376 * packet error count, frees the SKB and returns error.
7377 * Return value:
7378 * SUCCESS on success and -1 on failure.
7379 */
1ee6dd77 7380static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
1da177e4 7381{
1ee6dd77 7382 struct s2io_nic *sp = ring_data->nic;
d44570e4 7383 struct net_device *dev = (struct net_device *)ring_data->dev;
20346722 7384 struct sk_buff *skb = (struct sk_buff *)
d44570e4 7385 ((unsigned long)rxdp->Host_Control);
20346722 7386 int ring_no = ring_data->ring_no;
1da177e4 7387 u16 l3_csum, l4_csum;
863c11a9 7388 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
2e6a684b 7389 struct lro *uninitialized_var(lro);
f9046eb3 7390 u8 err_mask;
ffb5df6c 7391 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
da6971d8 7392
20346722 7393 skb->dev = dev;
c92ca04b 7394
863c11a9 7395 if (err) {
bd1034f0 7396 /* Check for parity error */
d44570e4 7397 if (err & 0x1)
ffb5df6c 7398 swstats->parity_err_cnt++;
d44570e4 7399
f9046eb3 7400 err_mask = err >> 48;
d44570e4
JP		 7401 switch (err_mask) {
7402 case 1:
ffb5df6c 7403 swstats->rx_parity_err_cnt++;
491976b2
SH		 7404 break;
7405
d44570e4 7406 case 2:
ffb5df6c 7407 swstats->rx_abort_cnt++;
491976b2
SH		 7408 break;
7409
d44570e4 7410 case 3:
ffb5df6c 7411 swstats->rx_parity_abort_cnt++;
491976b2
SH		 7412 break;
7413
d44570e4 7414 case 4:
ffb5df6c 7415 swstats->rx_rda_fail_cnt++;
491976b2
SH		 7416 break;
7417
d44570e4 7418 case 5:
ffb5df6c 7419 swstats->rx_unkn_prot_cnt++;
491976b2
SH		 7420 break;
7421
d44570e4 7422 case 6:
ffb5df6c 7423 swstats->rx_fcs_err_cnt++;
491976b2 7424 break;
bd1034f0 7425
d44570e4 7426 case 7:
ffb5df6c 7427 swstats->rx_buf_size_err_cnt++;
491976b2
SH		 7428 break;
7429
d44570e4 7430 case 8:
ffb5df6c 7431 swstats->rx_rxd_corrupt_cnt++;
491976b2
SH		 7432 break;
7433
d44570e4 7434 case 15:
ffb5df6c 7435 swstats->rx_unkn_err_cnt++;
491976b2
SH		 7436 break;
7437 }
863c11a9 7438 /*
d44570e4
JP		 7439 * Drop the packet if bad transfer code. Exception being
7440 * 0x5, which could be due to unsupported IPv6 extension header.
7441 * In this case, we let stack handle the packet.
7442 * Note that in this case, since checksum will be incorrect,
7443 * stack will validate the same.
7444 */
f9046eb3
OH		 7445 if (err_mask != 0x5) {
7446 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
d44570e4 7447 dev->name, err_mask);
dc56e634 7448 dev->stats.rx_crc_errors++;
ffb5df6c 7449 swstats->mem_freed
491976b2 7450 += skb->truesize;
863c11a9 7451 dev_kfree_skb(skb);
0425b46a 7452 ring_data->rx_bufs_left -= 1;
863c11a9
AR		 7453 rxdp->Host_Control = 0;
7454 return 0;
7455 }
20346722 7456 }
1da177e4 7457
20346722 7458 /* Updating statistics */
0425b46a 7459 ring_data->rx_packets++;
20346722 7460 rxdp->Host_Control = 0;
da6971d8
AR		 7461 if (sp->rxd_mode == RXD_MODE_1) {
7462 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
20346722 7463
0425b46a 7464 ring_data->rx_bytes += len;
da6971d8
AR		 7465 skb_put(skb, len);
7466
6d517a27 7467 } else if (sp->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 7468 int get_block = ring_data->rx_curr_get_info.block_index;
7469 int get_off = ring_data->rx_curr_get_info.offset;
7470 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7471 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7472 unsigned char *buff = skb_push(skb, buf0_len);
7473
1ee6dd77 7474 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
0425b46a 7475 ring_data->rx_bytes += buf0_len + buf2_len;
da6971d8 7476 memcpy(buff, ba->ba_0, buf0_len);
6d517a27 7477 skb_put(skb, buf2_len);
da6971d8 7478 }
20346722 7479
d44570e4
JP		 7480 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
7481 ((!ring_data->lro) ||
7482 (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
20346722
K		 7483 (sp->rx_csum)) {
7484 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
1da177e4
LT		 7485 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7486 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
20346722 7487 /*
1da177e4
LT		 7488 * NIC verifies if the Checksum of the received
7489 * frame is Ok or not and accordingly returns
7490 * a flag in the RxD.
7491 */
7492 skb->ip_summed = CHECKSUM_UNNECESSARY;
0425b46a 7493 if (ring_data->lro) {
7d3d0439
RA		 7494 u32 tcp_len;
7495 u8 *tcp;
7496 int ret = 0;
7497
0425b46a 7498 ret = s2io_club_tcp_session(ring_data,
d44570e4
JP		 7499 skb->data, &tcp,
7500 &tcp_len, &lro,
7501 rxdp, sp);
7d3d0439 7502 switch (ret) {
d44570e4
JP		 7503 case 3: /* Begin anew */
7504 lro->parent = skb;
7505 goto aggregate;
7506 case 1: /* Aggregate */
7507 lro_append_pkt(sp, lro, skb, tcp_len);
7508 goto aggregate;
7509 case 4: /* Flush session */
7510 lro_append_pkt(sp, lro, skb, tcp_len);
7511 queue_rx_frame(lro->parent,
7512 lro->vlan_tag);
7513 clear_lro_session(lro);
ffb5df6c 7514 swstats->flush_max_pkts++;
d44570e4
JP		 7515 goto aggregate;
7516 case 2: /* Flush both */
7517 lro->parent->data_len = lro->frags_len;
ffb5df6c 7518 swstats->sending_both++;
d44570e4
JP		 7519 queue_rx_frame(lro->parent,
7520 lro->vlan_tag);
7521 clear_lro_session(lro);
7522 goto send_up;
7523 case 0: /* sessions exceeded */
7524 case -1: /* non-TCP or not L2 aggregatable */
7525 case 5: /*
7526 * First pkt in session not
7527 * L3/L4 aggregatable
7528 */
7529 break;
7530 default:
7531 DBG_PRINT(ERR_DBG,
7532 "%s: Samadhana!!\n",
7533 __func__);
7534 BUG();
7d3d0439
RA		 7535 }
7536 }
1da177e4 7537 } else {
20346722
K		 7538 /*
7539 * Packet with erroneous checksum, let the
1da177e4
LT		 7540 * upper layers deal with it.
7541 */
7542 skb->ip_summed = CHECKSUM_NONE;
7543 }
cdb5bf02 7544 } else
1da177e4 7545 skb->ip_summed = CHECKSUM_NONE;
cdb5bf02 7546
ffb5df6c 7547 swstats->mem_freed += skb->truesize;
7d3d0439 7548send_up:
0c8dfc83 7549 skb_record_rx_queue(skb, ring_no);
cdb5bf02 7550 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7d3d0439 7551aggregate:
0425b46a 7552 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
1da177e4
LT		 7553 return SUCCESS;
7554}
7555
7556/**
7557 * s2io_link - stops/starts the Tx queue.
7558 * @sp : private member of the device structure, which is a pointer to the
7559 * s2io_nic structure.
7560 * @link : inidicates whether link is UP/DOWN.
7561 * Description:
7562 * This function stops/starts the Tx queue depending on whether the link
20346722
K		 7563 * status of the NIC is is down or up. This is called by the Alarm
7564 * interrupt handler whenever a link change interrupt comes up.
1da177e4
LT		 7565 * Return value:
7566 * void.
7567 */
7568
d44570e4 7569static void s2io_link(struct s2io_nic *sp, int link)
1da177e4 7570{
d44570e4 7571 struct net_device *dev = (struct net_device *)sp->dev;
ffb5df6c 7572 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 7573
7574 if (link != sp->last_link_state) {
b7c5678f 7575 init_tti(sp, link);
1da177e4
LT		 7576 if (link == LINK_DOWN) {
7577 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
3a3d5756 7578 s2io_stop_all_tx_queue(sp);
1da177e4 7579 netif_carrier_off(dev);
ffb5df6c
JP		 7580 if (swstats->link_up_cnt)
7581 swstats->link_up_time =
7582 jiffies - sp->start_time;
7583 swstats->link_down_cnt++;
1da177e4
LT		 7584 } else {
7585 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
ffb5df6c
JP		 7586 if (swstats->link_down_cnt)
7587 swstats->link_down_time =
d44570e4 7588 jiffies - sp->start_time;
ffb5df6c 7589 swstats->link_up_cnt++;
1da177e4 7590 netif_carrier_on(dev);
3a3d5756 7591 s2io_wake_all_tx_queue(sp);
1da177e4
LT		 7592 }
7593 }
7594 sp->last_link_state = link;
491976b2 7595 sp->start_time = jiffies;
1da177e4
LT		 7596}
7597
20346722
K		 7598/**
7599 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7600 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 7601 * s2io_nic structure.
7602 * Description:
7603 * This function initializes a few of the PCI and PCI-X configuration registers
7604 * with recommended values.
7605 * Return value:
7606 * void
7607 */
7608
d44570e4 7609static void s2io_init_pci(struct s2io_nic *sp)
1da177e4 7610{
20346722 7611 u16 pci_cmd = 0, pcix_cmd = 0;
1da177e4
LT		 7612
7613 /* Enable Data Parity Error Recovery in PCI-X command register. */
7614 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7615 &(pcix_cmd));
1da177e4 7616 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7617 (pcix_cmd | 1));
1da177e4 7618 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7619 &(pcix_cmd));
1da177e4
LT		 7620
7621 /* Set the PErr Response bit in PCI command register. */
7622 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7623 pci_write_config_word(sp->pdev, PCI_COMMAND,
7624 (pci_cmd | PCI_COMMAND_PARITY));
7625 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
1da177e4
LT		 7626}
7627
3a3d5756 7628static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
d44570e4 7629 u8 *dev_multiq)
9dc737a7 7630{
d44570e4 7631 if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) {
9e39f7c5 7632 DBG_PRINT(ERR_DBG, "Requested number of tx fifos "
d44570e4 7633 "(%d) not supported\n", tx_fifo_num);
6cfc482b
SH		 7634
7635 if (tx_fifo_num < 1)
7636 tx_fifo_num = 1;
7637 else
7638 tx_fifo_num = MAX_TX_FIFOS;
7639
9e39f7c5 7640 DBG_PRINT(ERR_DBG, "Default to %d tx fifos\n", tx_fifo_num);
9dc737a7 7641 }
2fda096d 7642
6cfc482b 7643 if (multiq)
3a3d5756 7644 *dev_multiq = multiq;
6cfc482b
SH		 7645
7646 if (tx_steering_type && (1 == tx_fifo_num)) {
7647 if (tx_steering_type != TX_DEFAULT_STEERING)
7648 DBG_PRINT(ERR_DBG,
9e39f7c5 7649 "Tx steering is not supported with "
d44570e4 7650 "one fifo. Disabling Tx steering.\n");
6cfc482b
SH		 7651 tx_steering_type = NO_STEERING;
7652 }
7653
7654 if ((tx_steering_type < NO_STEERING) ||
d44570e4
JP		 7655 (tx_steering_type > TX_DEFAULT_STEERING)) {
7656 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 7657 "Requested transmit steering not supported\n");
7658 DBG_PRINT(ERR_DBG, "Disabling transmit steering\n");
6cfc482b 7659 tx_steering_type = NO_STEERING;
3a3d5756
SH		 7660 }
7661
0425b46a 7662 if (rx_ring_num > MAX_RX_RINGS) {
d44570e4 7663 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 7664 "Requested number of rx rings not supported\n");
7665 DBG_PRINT(ERR_DBG, "Default to %d rx rings\n",
d44570e4 7666 MAX_RX_RINGS);
0425b46a 7667 rx_ring_num = MAX_RX_RINGS;
9dc737a7 7668 }
0425b46a 7669
eccb8628 7670 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
9e39f7c5 7671 DBG_PRINT(ERR_DBG, "Wrong intr_type requested. "
9dc737a7
AR		 7672 "Defaulting to INTA\n");
7673 *dev_intr_type = INTA;
7674 }
596c5c97 7675
9dc737a7 7676 if ((*dev_intr_type == MSI_X) &&
d44570e4
JP		 7677 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7678 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
9e39f7c5 7679 DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. "
d44570e4 7680 "Defaulting to INTA\n");
9dc737a7
AR		 7681 *dev_intr_type = INTA;
7682 }
fb6a825b 7683
6d517a27 7684 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
9e39f7c5
JP		 7685 DBG_PRINT(ERR_DBG, "Requested ring mode not supported\n");
7686 DBG_PRINT(ERR_DBG, "Defaulting to 1-buffer mode\n");
6d517a27 7687 rx_ring_mode = 1;
9dc737a7
AR		 7688 }
7689 return SUCCESS;
7690}
7691
9fc93a41
SS		 7692/**
7693 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7694 * or Traffic class respectively.
b7c5678f 7695 * @nic: device private variable
9fc93a41
SS		 7696 * Description: The function configures the receive steering to
7697 * desired receive ring.
7698 * Return Value: SUCCESS on success and
7699 * '-1' on failure (endian settings incorrect).
7700 */
7701static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7702{
7703 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7704 register u64 val64 = 0;
7705
7706 if (ds_codepoint > 63)
7707 return FAILURE;
7708
7709 val64 = RTS_DS_MEM_DATA(ring);
7710 writeq(val64, &bar0->rts_ds_mem_data);
7711
7712 val64 = RTS_DS_MEM_CTRL_WE |
7713 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7714 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7715
7716 writeq(val64, &bar0->rts_ds_mem_ctrl);
7717
7718 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
d44570e4
JP		 7719 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7720 S2IO_BIT_RESET);
9fc93a41
SS		 7721}
7722
04025095
SH		 7723static const struct net_device_ops s2io_netdev_ops = {
7724 .ndo_open = s2io_open,
7725 .ndo_stop = s2io_close,
7726 .ndo_get_stats = s2io_get_stats,
7727 .ndo_start_xmit = s2io_xmit,
7728 .ndo_validate_addr = eth_validate_addr,
7729 .ndo_set_multicast_list = s2io_set_multicast,
7730 .ndo_do_ioctl = s2io_ioctl,
7731 .ndo_set_mac_address = s2io_set_mac_addr,
7732 .ndo_change_mtu = s2io_change_mtu,
7733 .ndo_vlan_rx_register = s2io_vlan_rx_register,
7734 .ndo_vlan_rx_kill_vid = s2io_vlan_rx_kill_vid,
7735 .ndo_tx_timeout = s2io_tx_watchdog,
7736#ifdef CONFIG_NET_POLL_CONTROLLER
7737 .ndo_poll_controller = s2io_netpoll,
7738#endif
7739};
7740
1da177e4 7741/**
20346722 7742 * s2io_init_nic - Initialization of the adapter .
1da177e4
LT		 7743 * @pdev : structure containing the PCI related information of the device.
7744 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7745 * Description:
7746 * The function initializes an adapter identified by the pci_dec structure.
20346722
K		 7747 * All OS related initialization including memory and device structure and
7748 * initlaization of the device private variable is done. Also the swapper
7749 * control register is initialized to enable read and write into the I/O
1da177e4
LT		 7750 * registers of the device.
7751 * Return value:
7752 * returns 0 on success and negative on failure.
7753 */
7754
7755static int __devinit
7756s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7757{
1ee6dd77 7758 struct s2io_nic *sp;
1da177e4 7759 struct net_device *dev;
1da177e4 7760 int i, j, ret;
f957bcf0 7761 int dma_flag = false;
1da177e4
LT		 7762 u32 mac_up, mac_down;
7763 u64 val64 = 0, tmp64 = 0;
1ee6dd77 7764 struct XENA_dev_config __iomem *bar0 = NULL;
1da177e4 7765 u16 subid;
1da177e4 7766 struct config_param *config;
ffb5df6c 7767 struct mac_info *mac_control;
541ae68f 7768 int mode;
cc6e7c44 7769 u8 dev_intr_type = intr_type;
3a3d5756 7770 u8 dev_multiq = 0;
1da177e4 7771
3a3d5756
SH		 7772 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7773 if (ret)
9dc737a7 7774 return ret;
1da177e4 7775
d44570e4
JP		 7776 ret = pci_enable_device(pdev);
7777 if (ret) {
1da177e4 7778 DBG_PRINT(ERR_DBG,
9e39f7c5 7779 "%s: pci_enable_device failed\n", __func__);
1da177e4
LT		 7780 return ret;
7781 }
7782
6a35528a 7783 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
9e39f7c5 7784 DBG_PRINT(INIT_DBG, "%s: Using 64bit DMA\n", __func__);
f957bcf0 7785 dma_flag = true;
d44570e4 7786 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4 7787 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7788 "Unable to obtain 64bit DMA "
7789 "for consistent allocations\n");
1da177e4
LT		 7790 pci_disable_device(pdev);
7791 return -ENOMEM;
7792 }
284901a9 7793 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
9e39f7c5 7794 DBG_PRINT(INIT_DBG, "%s: Using 32bit DMA\n", __func__);
1da177e4
LT		 7795 } else {
7796 pci_disable_device(pdev);
7797 return -ENOMEM;
7798 }
d44570e4
JP		 7799 ret = pci_request_regions(pdev, s2io_driver_name);
7800 if (ret) {
9e39f7c5 7801 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x\n",
d44570e4 7802 __func__, ret);
eccb8628
VP		 7803 pci_disable_device(pdev);
7804 return -ENODEV;
1da177e4 7805 }
3a3d5756 7806 if (dev_multiq)
6cfc482b 7807 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
3a3d5756 7808 else
b19fa1fa 7809 dev = alloc_etherdev(sizeof(struct s2io_nic));
1da177e4
LT		 7810 if (dev == NULL) {
7811 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7812 pci_disable_device(pdev);
7813 pci_release_regions(pdev);
7814 return -ENODEV;
7815 }
7816
7817 pci_set_master(pdev);
7818 pci_set_drvdata(pdev, dev);
1da177e4
LT		 7819 SET_NETDEV_DEV(dev, &pdev->dev);
7820
7821 /* Private member variable initialized to s2io NIC structure */
4cf1653a 7822 sp = netdev_priv(dev);
1ee6dd77 7823 memset(sp, 0, sizeof(struct s2io_nic));
1da177e4
LT		 7824 sp->dev = dev;
7825 sp->pdev = pdev;
1da177e4 7826 sp->high_dma_flag = dma_flag;
f957bcf0 7827 sp->device_enabled_once = false;
da6971d8
AR		 7828 if (rx_ring_mode == 1)
7829 sp->rxd_mode = RXD_MODE_1;
7830 if (rx_ring_mode == 2)
7831 sp->rxd_mode = RXD_MODE_3B;
da6971d8 7832
eaae7f72 7833 sp->config.intr_type = dev_intr_type;
1da177e4 7834
541ae68f 7835 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
d44570e4 7836 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
541ae68f
K		 7837 sp->device_type = XFRAME_II_DEVICE;
7838 else
7839 sp->device_type = XFRAME_I_DEVICE;
7840
43b7c451 7841 sp->lro = lro_enable;
6aa20a22 7842
1da177e4
LT		 7843 /* Initialize some PCI/PCI-X fields of the NIC. */
7844 s2io_init_pci(sp);
7845
20346722 7846 /*
1da177e4 7847 * Setting the device configuration parameters.
20346722
K		 7848 * Most of these parameters can be specified by the user during
7849 * module insertion as they are module loadable parameters. If
7850 * these parameters are not not specified during load time, they
1da177e4
LT		 7851 * are initialized with default values.
7852 */
1da177e4 7853 config = &sp->config;
ffb5df6c 7854 mac_control = &sp->mac_control;
1da177e4 7855
596c5c97 7856 config->napi = napi;
6cfc482b 7857 config->tx_steering_type = tx_steering_type;
596c5c97 7858
1da177e4 7859 /* Tx side parameters. */
6cfc482b
SH		 7860 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7861 config->tx_fifo_num = MAX_TX_FIFOS;
7862 else
7863 config->tx_fifo_num = tx_fifo_num;
7864
7865 /* Initialize the fifos used for tx steering */
7866 if (config->tx_fifo_num < 5) {
d44570e4
JP		 7867 if (config->tx_fifo_num == 1)
7868 sp->total_tcp_fifos = 1;
7869 else
7870 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7871 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7872 sp->total_udp_fifos = 1;
7873 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
6cfc482b
SH		 7874 } else {
7875 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
d44570e4 7876 FIFO_OTHER_MAX_NUM);
6cfc482b
SH		 7877 sp->udp_fifo_idx = sp->total_tcp_fifos;
7878 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7879 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7880 }
7881
3a3d5756 7882 config->multiq = dev_multiq;
6cfc482b 7883 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 7884 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7885
7886 tx_cfg->fifo_len = tx_fifo_len[i];
7887 tx_cfg->fifo_priority = i;
1da177e4
LT		 7888 }
7889
20346722
K		 7890 /* mapping the QoS priority to the configured fifos */
7891 for (i = 0; i < MAX_TX_FIFOS; i++)
3a3d5756 7892 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
20346722 7893
6cfc482b
SH		 7894 /* map the hashing selector table to the configured fifos */
7895 for (i = 0; i < config->tx_fifo_num; i++)
7896 sp->fifo_selector[i] = fifo_selector[i];
7897
7898
1da177e4
LT		 7899 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7900 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 7901 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7902
7903 tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7904 if (tx_cfg->fifo_len < 65) {
1da177e4
LT		 7905 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7906 break;
7907 }
7908 }
fed5eccd
AR		 7909 /* + 2 because one Txd for skb->data and one Txd for UFO */
7910 config->max_txds = MAX_SKB_FRAGS + 2;
1da177e4
LT		 7911
7912 /* Rx side parameters. */
1da177e4 7913 config->rx_ring_num = rx_ring_num;
0425b46a 7914 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7915 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7916 struct ring_info *ring = &mac_control->rings[i];
7917
7918 rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
7919 rx_cfg->ring_priority = i;
7920 ring->rx_bufs_left = 0;
7921 ring->rxd_mode = sp->rxd_mode;
7922 ring->rxd_count = rxd_count[sp->rxd_mode];
7923 ring->pdev = sp->pdev;
7924 ring->dev = sp->dev;
1da177e4
LT		 7925 }
7926
7927 for (i = 0; i < rx_ring_num; i++) {
13d866a9
JP		 7928 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7929
7930 rx_cfg->ring_org = RING_ORG_BUFF1;
7931 rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
1da177e4
LT		 7932 }
7933
7934 /* Setting Mac Control parameters */
7935 mac_control->rmac_pause_time = rmac_pause_time;
7936 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7937 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7938
7939
1da177e4
LT		 7940 /* initialize the shared memory used by the NIC and the host */
7941 if (init_shared_mem(sp)) {
d44570e4 7942 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", dev->name);
1da177e4
LT		 7943 ret = -ENOMEM;
7944 goto mem_alloc_failed;
7945 }
7946
275f165f 7947 sp->bar0 = pci_ioremap_bar(pdev, 0);
1da177e4 7948 if (!sp->bar0) {
19a60522 7949 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
1da177e4
LT		 7950 dev->name);
7951 ret = -ENOMEM;
7952 goto bar0_remap_failed;
7953 }
7954
275f165f 7955 sp->bar1 = pci_ioremap_bar(pdev, 2);
1da177e4 7956 if (!sp->bar1) {
19a60522 7957 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
1da177e4
LT		 7958 dev->name);
7959 ret = -ENOMEM;
7960 goto bar1_remap_failed;
7961 }
7962
7963 dev->irq = pdev->irq;
d44570e4 7964 dev->base_addr = (unsigned long)sp->bar0;
1da177e4
LT		 7965
7966 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7967 for (j = 0; j < MAX_TX_FIFOS; j++) {
d44570e4
JP		 7968 mac_control->tx_FIFO_start[j] =
7969 (struct TxFIFO_element __iomem *)
7970 (sp->bar1 + (j * 0x00020000));
1da177e4
LT		 7971 }
7972
7973 /* Driver entry points */
04025095 7974 dev->netdev_ops = &s2io_netdev_ops;
1da177e4 7975 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
be3a6b02 7976 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
612eff0e 7977
1da177e4 7978 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
f957bcf0 7979 if (sp->high_dma_flag == true)
1da177e4 7980 dev->features |= NETIF_F_HIGHDMA;
1da177e4 7981 dev->features |= NETIF_F_TSO;
f83ef8c0 7982 dev->features |= NETIF_F_TSO6;
db874e65 7983 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
fed5eccd
AR		 7984 dev->features |= NETIF_F_UFO;
7985 dev->features |= NETIF_F_HW_CSUM;
7986 }
1da177e4 7987 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
c4028958
DH		 7988 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7989 INIT_WORK(&sp->set_link_task, s2io_set_link);
1da177e4 7990
e960fc5c 7991 pci_save_state(sp->pdev);
1da177e4
LT		 7992
7993 /* Setting swapper control on the NIC, for proper reset operation */
7994 if (s2io_set_swapper(sp)) {
9e39f7c5 7995 DBG_PRINT(ERR_DBG, "%s: swapper settings are wrong\n",
1da177e4
LT		 7996 dev->name);
7997 ret = -EAGAIN;
7998 goto set_swap_failed;
7999 }
8000
541ae68f
K		 8001 /* Verify if the Herc works on the slot its placed into */
8002 if (sp->device_type & XFRAME_II_DEVICE) {
8003 mode = s2io_verify_pci_mode(sp);
8004 if (mode < 0) {
9e39f7c5
JP		 8005 DBG_PRINT(ERR_DBG, "%s: Unsupported PCI bus mode\n",
8006 __func__);
541ae68f
K		 8007 ret = -EBADSLT;
8008 goto set_swap_failed;
8009 }
8010 }
8011
f61e0a35
SH		 8012 if (sp->config.intr_type == MSI_X) {
8013 sp->num_entries = config->rx_ring_num + 1;
8014 ret = s2io_enable_msi_x(sp);
8015
8016 if (!ret) {
8017 ret = s2io_test_msi(sp);
8018 /* rollback MSI-X, will re-enable during add_isr() */
8019 remove_msix_isr(sp);
8020 }
8021 if (ret) {
8022
8023 DBG_PRINT(ERR_DBG,
9e39f7c5 8024 "MSI-X requested but failed to enable\n");
f61e0a35
SH		 8025 sp->config.intr_type = INTA;
8026 }
8027 }
8028
8029 if (config->intr_type == MSI_X) {
13d866a9
JP		 8030 for (i = 0; i < config->rx_ring_num ; i++) {
8031 struct ring_info *ring = &mac_control->rings[i];
8032
8033 netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64);
8034 }
f61e0a35
SH		 8035 } else {
8036 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
8037 }
8038
541ae68f
K		 8039 /* Not needed for Herc */
8040 if (sp->device_type & XFRAME_I_DEVICE) {
8041 /*
8042 * Fix for all "FFs" MAC address problems observed on
8043 * Alpha platforms
8044 */
8045 fix_mac_address(sp);
8046 s2io_reset(sp);
8047 }
1da177e4
LT		 8048
8049 /*
1da177e4
LT		 8050 * MAC address initialization.
8051 * For now only one mac address will be read and used.
8052 */
8053 bar0 = sp->bar0;
8054 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
d44570e4 8055 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
1da177e4 8056 writeq(val64, &bar0->rmac_addr_cmd_mem);
c92ca04b 8057 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 8058 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
8059 S2IO_BIT_RESET);
1da177e4 8060 tmp64 = readq(&bar0->rmac_addr_data0_mem);
d44570e4 8061 mac_down = (u32)tmp64;
1da177e4
LT		 8062 mac_up = (u32) (tmp64 >> 32);
8063
1da177e4
LT		 8064 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8065 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8066 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8067 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8068 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8069 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8070
1da177e4
LT		 8071 /* Set the factory defined MAC address initially */
8072 dev->addr_len = ETH_ALEN;
8073 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
2fd37688 8074 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
1da177e4 8075
faa4f796
SH		 8076 /* initialize number of multicast & unicast MAC entries variables */
8077 if (sp->device_type == XFRAME_I_DEVICE) {
8078 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8079 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8080 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8081 } else if (sp->device_type == XFRAME_II_DEVICE) {
8082 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8083 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8084 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8085 }
8086
8087 /* store mac addresses from CAM to s2io_nic structure */
8088 do_s2io_store_unicast_mc(sp);
8089
f61e0a35
SH		 8090 /* Configure MSIX vector for number of rings configured plus one */
8091 if ((sp->device_type == XFRAME_II_DEVICE) &&
d44570e4 8092 (config->intr_type == MSI_X))
f61e0a35
SH		 8093 sp->num_entries = config->rx_ring_num + 1;
8094
d44570e4 8095 /* Store the values of the MSIX table in the s2io_nic structure */
c77dd43e 8096 store_xmsi_data(sp);
b41477f3
AR		 8097 /* reset Nic and bring it to known state */
8098 s2io_reset(sp);
8099
1da177e4 8100 /*
99993af6 8101 * Initialize link state flags
541ae68f 8102 * and the card state parameter
1da177e4 8103 */
92b84437 8104 sp->state = 0;
1da177e4 8105
1da177e4 8106 /* Initialize spinlocks */
13d866a9
JP		 8107 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8108 struct fifo_info *fifo = &mac_control->fifos[i];
8109
8110 spin_lock_init(&fifo->tx_lock);
8111 }
db874e65 8112
20346722
K		 8113 /*
8114 * SXE-002: Configure link and activity LED to init state
8115 * on driver load.
1da177e4
LT		 8116 */
8117 subid = sp->pdev->subsystem_device;
8118 if ((subid & 0xFF) >= 0x07) {
8119 val64 = readq(&bar0->gpio_control);
8120 val64 |= 0x0000800000000000ULL;
8121 writeq(val64, &bar0->gpio_control);
8122 val64 = 0x0411040400000000ULL;
d44570e4 8123 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 8124 val64 = readq(&bar0->gpio_control);
8125 }
8126
8127 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8128
8129 if (register_netdev(dev)) {
8130 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8131 ret = -ENODEV;
8132 goto register_failed;
8133 }
9dc737a7 8134 s2io_vpd_read(sp);
0c61ed5f 8135 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
d44570e4 8136 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name,
44c10138 8137 sp->product_name, pdev->revision);
b41477f3
AR		 8138 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8139 s2io_driver_version);
9e39f7c5
JP		 8140 DBG_PRINT(ERR_DBG, "%s: MAC Address: %pM\n", dev->name, dev->dev_addr);
8141 DBG_PRINT(ERR_DBG, "Serial number: %s\n", sp->serial_num);
9dc737a7 8142 if (sp->device_type & XFRAME_II_DEVICE) {
0b1f7ebe 8143 mode = s2io_print_pci_mode(sp);
541ae68f 8144 if (mode < 0) {
541ae68f 8145 ret = -EBADSLT;
9dc737a7 8146 unregister_netdev(dev);
541ae68f
K		 8147 goto set_swap_failed;
8148 }
541ae68f 8149 }
d44570e4
JP		 8150 switch (sp->rxd_mode) {
8151 case RXD_MODE_1:
8152 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8153 dev->name);
8154 break;
8155 case RXD_MODE_3B:
8156 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8157 dev->name);
8158 break;
9dc737a7 8159 }
db874e65 8160
f61e0a35
SH		 8161 switch (sp->config.napi) {
8162 case 0:
8163 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8164 break;
8165 case 1:
db874e65 8166 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
f61e0a35
SH		 8167 break;
8168 }
3a3d5756
SH		 8169
8170 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
d44570e4 8171 sp->config.tx_fifo_num);
3a3d5756 8172
0425b46a
SH		 8173 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8174 sp->config.rx_ring_num);
8175
d44570e4
JP		 8176 switch (sp->config.intr_type) {
8177 case INTA:
8178 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8179 break;
8180 case MSI_X:
8181 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8182 break;
9dc737a7 8183 }
3a3d5756 8184 if (sp->config.multiq) {
13d866a9
JP		 8185 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8186 struct fifo_info *fifo = &mac_control->fifos[i];
8187
8188 fifo->multiq = config->multiq;
8189 }
3a3d5756 8190 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
d44570e4 8191 dev->name);
3a3d5756
SH		 8192 } else
8193 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
d44570e4 8194 dev->name);
3a3d5756 8195
6cfc482b
SH		 8196 switch (sp->config.tx_steering_type) {
8197 case NO_STEERING:
d44570e4
JP		 8198 DBG_PRINT(ERR_DBG, "%s: No steering enabled for transmit\n",
8199 dev->name);
8200 break;
6cfc482b 8201 case TX_PRIORITY_STEERING:
d44570e4
JP		 8202 DBG_PRINT(ERR_DBG,
8203 "%s: Priority steering enabled for transmit\n",
8204 dev->name);
6cfc482b
SH		 8205 break;
8206 case TX_DEFAULT_STEERING:
d44570e4
JP		 8207 DBG_PRINT(ERR_DBG,
8208 "%s: Default steering enabled for transmit\n",
8209 dev->name);
6cfc482b
SH		 8210 }
8211
7d3d0439
RA		 8212 if (sp->lro)
8213 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
9dc737a7 8214 dev->name);
db874e65 8215 if (ufo)
d44570e4
JP		 8216 DBG_PRINT(ERR_DBG,
8217 "%s: UDP Fragmentation Offload(UFO) enabled\n",
8218 dev->name);
7ba013ac 8219 /* Initialize device name */
9dc737a7 8220 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7ba013ac 8221
cd0fce03
BL		 8222 if (vlan_tag_strip)
8223 sp->vlan_strip_flag = 1;
8224 else
8225 sp->vlan_strip_flag = 0;
8226
20346722
K		 8227 /*
8228 * Make Link state as off at this point, when the Link change
8229 * interrupt comes the state will be automatically changed to
1da177e4
LT		 8230 * the right state.
8231 */
8232 netif_carrier_off(dev);
1da177e4
LT		 8233
8234 return 0;
8235
d44570e4
JP		 8236register_failed:
8237set_swap_failed:
1da177e4 8238 iounmap(sp->bar1);
d44570e4 8239bar1_remap_failed:
1da177e4 8240 iounmap(sp->bar0);
d44570e4
JP		 8241bar0_remap_failed:
8242mem_alloc_failed:
1da177e4
LT		 8243 free_shared_mem(sp);
8244 pci_disable_device(pdev);
eccb8628 8245 pci_release_regions(pdev);
1da177e4
LT		 8246 pci_set_drvdata(pdev, NULL);
8247 free_netdev(dev);
8248
8249 return ret;
8250}
8251
8252/**
20346722 8253 * s2io_rem_nic - Free the PCI device
1da177e4 8254 * @pdev: structure containing the PCI related information of the device.
20346722 8255 * Description: This function is called by the Pci subsystem to release a
1da177e4 8256 * PCI device and free up all resource held up by the device. This could
20346722 8257 * be in response to a Hot plug event or when the driver is to be removed
1da177e4
LT		 8258 * from memory.
8259 */
8260
8261static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8262{
8263 struct net_device *dev =
d44570e4 8264 (struct net_device *)pci_get_drvdata(pdev);
1ee6dd77 8265 struct s2io_nic *sp;
1da177e4
LT		 8266
8267 if (dev == NULL) {
8268 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8269 return;
8270 }
8271
22747d6b
FR		 8272 flush_scheduled_work();
8273
4cf1653a 8274 sp = netdev_priv(dev);
1da177e4
LT		 8275 unregister_netdev(dev);
8276
8277 free_shared_mem(sp);
8278 iounmap(sp->bar0);
8279 iounmap(sp->bar1);
eccb8628 8280 pci_release_regions(pdev);
1da177e4 8281 pci_set_drvdata(pdev, NULL);
1da177e4 8282 free_netdev(dev);
19a60522 8283 pci_disable_device(pdev);
1da177e4
LT		 8284}
8285
8286/**
8287 * s2io_starter - Entry point for the driver
8288 * Description: This function is the entry point for the driver. It verifies
8289 * the module loadable parameters and initializes PCI configuration space.
8290 */
8291
43b7c451 8292static int __init s2io_starter(void)
1da177e4 8293{
29917620 8294 return pci_register_driver(&s2io_driver);
1da177e4
LT		 8295}
8296
8297/**
20346722 8298 * s2io_closer - Cleanup routine for the driver
1da177e4
LT		 8299 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8300 */
8301
372cc597 8302static __exit void s2io_closer(void)
1da177e4
LT		 8303{
8304 pci_unregister_driver(&s2io_driver);
8305 DBG_PRINT(INIT_DBG, "cleanup done\n");
8306}
8307
8308module_init(s2io_starter);
8309module_exit(s2io_closer);
7d3d0439 8310
6aa20a22 8311static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
d44570e4
JP		 8312 struct tcphdr **tcp, struct RxD_t *rxdp,
8313 struct s2io_nic *sp)
7d3d0439
RA		 8314{
8315 int ip_off;
8316 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8317
8318 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
d44570e4
JP		 8319 DBG_PRINT(INIT_DBG,
8320 "%s: Non-TCP frames not supported for LRO\n",
b39d66a8 8321 __func__);
7d3d0439
RA		 8322 return -1;
8323 }
8324
cdb5bf02 8325 /* Checking for DIX type or DIX type with VLAN */
d44570e4 8326 if ((l2_type == 0) || (l2_type == 4)) {
cdb5bf02
SH		 8327 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8328 /*
8329 * If vlan stripping is disabled and the frame is VLAN tagged,
8330 * shift the offset by the VLAN header size bytes.
8331 */
cd0fce03 8332 if ((!sp->vlan_strip_flag) &&
d44570e4 8333 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
cdb5bf02
SH		 8334 ip_off += HEADER_VLAN_SIZE;
8335 } else {
7d3d0439 8336 /* LLC, SNAP etc are considered non-mergeable */
cdb5bf02 8337 return -1;
7d3d0439
RA		 8338 }
8339
8340 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8341 ip_len = (u8)((*ip)->ihl);
8342 ip_len <<= 2;
8343 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8344
8345 return 0;
8346}
8347
1ee6dd77 8348static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 8349 struct tcphdr *tcp)
8350{
d44570e4
JP		 8351 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8352 if ((lro->iph->saddr != ip->saddr) ||
8353 (lro->iph->daddr != ip->daddr) ||
8354 (lro->tcph->source != tcp->source) ||
8355 (lro->tcph->dest != tcp->dest))
7d3d0439
RA		 8356 return -1;
8357 return 0;
8358}
8359
8360static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8361{
d44570e4 8362 return ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2);
7d3d0439
RA		 8363}
8364
1ee6dd77 8365static void initiate_new_session(struct lro *lro, u8 *l2h,
d44570e4
JP		 8366 struct iphdr *ip, struct tcphdr *tcp,
8367 u32 tcp_pyld_len, u16 vlan_tag)
7d3d0439 8368{
d44570e4 8369 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8370 lro->l2h = l2h;
8371 lro->iph = ip;
8372 lro->tcph = tcp;
8373 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
c8855953 8374 lro->tcp_ack = tcp->ack_seq;
7d3d0439
RA		 8375 lro->sg_num = 1;
8376 lro->total_len = ntohs(ip->tot_len);
8377 lro->frags_len = 0;
cdb5bf02 8378 lro->vlan_tag = vlan_tag;
6aa20a22 8379 /*
d44570e4
JP		 8380 * Check if we saw TCP timestamp.
8381 * Other consistency checks have already been done.
8382 */
7d3d0439 8383 if (tcp->doff == 8) {
c8855953
SR		 8384 __be32 *ptr;
8385 ptr = (__be32 *)(tcp+1);
7d3d0439 8386 lro->saw_ts = 1;
c8855953 8387 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8388 lro->cur_tsecr = *(ptr+2);
8389 }
8390 lro->in_use = 1;
8391}
8392
1ee6dd77 8393static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7d3d0439
RA		 8394{
8395 struct iphdr *ip = lro->iph;
8396 struct tcphdr *tcp = lro->tcph;
bd4f3ae1 8397 __sum16 nchk;
ffb5df6c
JP		 8398 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8399
d44570e4 8400 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8401
8402 /* Update L3 header */
8403 ip->tot_len = htons(lro->total_len);
8404 ip->check = 0;
8405 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8406 ip->check = nchk;
8407
8408 /* Update L4 header */
8409 tcp->ack_seq = lro->tcp_ack;
8410 tcp->window = lro->window;
8411
8412 /* Update tsecr field if this session has timestamps enabled */
8413 if (lro->saw_ts) {
c8855953 8414 __be32 *ptr = (__be32 *)(tcp + 1);
7d3d0439
RA		 8415 *(ptr+2) = lro->cur_tsecr;
8416 }
8417
8418 /* Update counters required for calculation of
8419 * average no. of packets aggregated.
8420 */
ffb5df6c
JP		 8421 swstats->sum_avg_pkts_aggregated += lro->sg_num;
8422 swstats->num_aggregations++;
7d3d0439
RA		 8423}
8424
1ee6dd77 8425static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
d44570e4 8426 struct tcphdr *tcp, u32 l4_pyld)
7d3d0439 8427{
d44570e4 8428 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8429 lro->total_len += l4_pyld;
8430 lro->frags_len += l4_pyld;
8431 lro->tcp_next_seq += l4_pyld;
8432 lro->sg_num++;
8433
8434 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8435 lro->tcp_ack = tcp->ack_seq;
8436 lro->window = tcp->window;
6aa20a22 8437
7d3d0439 8438 if (lro->saw_ts) {
c8855953 8439 __be32 *ptr;
7d3d0439 8440 /* Update tsecr and tsval from this packet */
c8855953
SR		 8441 ptr = (__be32 *)(tcp+1);
8442 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8443 lro->cur_tsecr = *(ptr + 2);
8444 }
8445}
8446
1ee6dd77 8447static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7d3d0439
RA		 8448 struct tcphdr *tcp, u32 tcp_pyld_len)
8449{
7d3d0439
RA		 8450 u8 *ptr;
8451
d44570e4 8452 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
79dc1901 8453
7d3d0439
RA		 8454 if (!tcp_pyld_len) {
8455 /* Runt frame or a pure ack */
8456 return -1;
8457 }
8458
8459 if (ip->ihl != 5) /* IP has options */
8460 return -1;
8461
75c30b13
AR		 8462 /* If we see CE codepoint in IP header, packet is not mergeable */
8463 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8464 return -1;
8465
8466 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
d44570e4
JP		 8467 if (tcp->urg || tcp->psh || tcp->rst ||
8468 tcp->syn || tcp->fin ||
8469 tcp->ece || tcp->cwr || !tcp->ack) {
7d3d0439
RA		 8470 /*
8471 * Currently recognize only the ack control word and
8472 * any other control field being set would result in
8473 * flushing the LRO session
8474 */
8475 return -1;
8476 }
8477
6aa20a22 8478 /*
7d3d0439
RA		 8479 * Allow only one TCP timestamp option. Don't aggregate if
8480 * any other options are detected.
8481 */
8482 if (tcp->doff != 5 && tcp->doff != 8)
8483 return -1;
8484
8485 if (tcp->doff == 8) {
6aa20a22 8486 ptr = (u8 *)(tcp + 1);
7d3d0439
RA		 8487 while (*ptr == TCPOPT_NOP)
8488 ptr++;
8489 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8490 return -1;
8491
8492 /* Ensure timestamp value increases monotonically */
8493 if (l_lro)
c8855953 8494 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
7d3d0439
RA		 8495 return -1;
8496
8497 /* timestamp echo reply should be non-zero */
c8855953 8498 if (*((__be32 *)(ptr+6)) == 0)
7d3d0439
RA		 8499 return -1;
8500 }
8501
8502 return 0;
8503}
8504
d44570e4
JP		 8505static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
8506 u8 **tcp, u32 *tcp_len, struct lro **lro,
8507 struct RxD_t *rxdp, struct s2io_nic *sp)
7d3d0439
RA		 8508{
8509 struct iphdr *ip;
8510 struct tcphdr *tcph;
8511 int ret = 0, i;
cdb5bf02 8512 u16 vlan_tag = 0;
ffb5df6c 8513 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7d3d0439 8514
d44570e4
JP		 8515 ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8516 rxdp, sp);
8517 if (ret)
7d3d0439 8518 return ret;
7d3d0439 8519
d44570e4
JP		 8520 DBG_PRINT(INFO_DBG, "IP Saddr: %x Daddr: %x\n", ip->saddr, ip->daddr);
8521
cdb5bf02 8522 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
7d3d0439
RA		 8523 tcph = (struct tcphdr *)*tcp;
8524 *tcp_len = get_l4_pyld_length(ip, tcph);
d44570e4 8525 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 8526 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8527 if (l_lro->in_use) {
8528 if (check_for_socket_match(l_lro, ip, tcph))
8529 continue;
8530 /* Sock pair matched */
8531 *lro = l_lro;
8532
8533 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
9e39f7c5
JP		 8534 DBG_PRINT(INFO_DBG, "%s: Out of sequence. "
8535 "expected 0x%x, actual 0x%x\n",
8536 __func__,
7d3d0439
RA		 8537 (*lro)->tcp_next_seq,
8538 ntohl(tcph->seq));
8539
ffb5df6c 8540 swstats->outof_sequence_pkts++;
7d3d0439
RA		 8541 ret = 2;
8542 break;
8543 }
8544
d44570e4
JP		 8545 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,
8546 *tcp_len))
7d3d0439
RA		 8547 ret = 1; /* Aggregate */
8548 else
8549 ret = 2; /* Flush both */
8550 break;
8551 }
8552 }
8553
8554 if (ret == 0) {
8555 /* Before searching for available LRO objects,
8556 * check if the pkt is L3/L4 aggregatable. If not
8557 * don't create new LRO session. Just send this
8558 * packet up.
8559 */
d44570e4 8560 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len))
7d3d0439 8561 return 5;
7d3d0439 8562
d44570e4 8563 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 8564 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8565 if (!(l_lro->in_use)) {
8566 *lro = l_lro;
8567 ret = 3; /* Begin anew */
8568 break;
8569 }
8570 }
8571 }
8572
8573 if (ret == 0) { /* sessions exceeded */
9e39f7c5 8574 DBG_PRINT(INFO_DBG, "%s: All LRO sessions already in use\n",
b39d66a8 8575 __func__);
7d3d0439
RA		 8576 *lro = NULL;
8577 return ret;
8578 }
8579
8580 switch (ret) {
d44570e4
JP		 8581 case 3:
8582 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8583 vlan_tag);
8584 break;
8585 case 2:
8586 update_L3L4_header(sp, *lro);
8587 break;
8588 case 1:
8589 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8590 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
7d3d0439 8591 update_L3L4_header(sp, *lro);
d44570e4
JP		 8592 ret = 4; /* Flush the LRO */
8593 }
8594 break;
8595 default:
9e39f7c5 8596 DBG_PRINT(ERR_DBG, "%s: Don't know, can't say!!\n", __func__);
d44570e4 8597 break;
7d3d0439
RA		 8598 }
8599
8600 return ret;
8601}
8602
1ee6dd77 8603static void clear_lro_session(struct lro *lro)
7d3d0439 8604{
1ee6dd77 8605 static u16 lro_struct_size = sizeof(struct lro);
7d3d0439
RA		 8606
8607 memset(lro, 0, lro_struct_size);
8608}
8609
cdb5bf02 8610static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
7d3d0439
RA		 8611{
8612 struct net_device *dev = skb->dev;
4cf1653a 8613 struct s2io_nic *sp = netdev_priv(dev);
7d3d0439
RA		 8614
8615 skb->protocol = eth_type_trans(skb, dev);
d44570e4 8616 if (sp->vlgrp && vlan_tag && (sp->vlan_strip_flag)) {
cdb5bf02
SH		 8617 /* Queueing the vlan frame to the upper layer */
8618 if (sp->config.napi)
8619 vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8620 else
8621 vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8622 } else {
8623 if (sp->config.napi)
8624 netif_receive_skb(skb);
8625 else
8626 netif_rx(skb);
8627 }
7d3d0439
RA		 8628}
8629
1ee6dd77 8630static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
d44570e4 8631 struct sk_buff *skb, u32 tcp_len)
7d3d0439 8632{
75c30b13 8633 struct sk_buff *first = lro->parent;
ffb5df6c 8634 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7d3d0439
RA		 8635
8636 first->len += tcp_len;
8637 first->data_len = lro->frags_len;
8638 skb_pull(skb, (skb->len - tcp_len));
75c30b13
AR		 8639 if (skb_shinfo(first)->frag_list)
8640 lro->last_frag->next = skb;
7d3d0439
RA		 8641 else
8642 skb_shinfo(first)->frag_list = skb;
372cc597 8643 first->truesize += skb->truesize;
75c30b13 8644 lro->last_frag = skb;
ffb5df6c 8645 swstats->clubbed_frms_cnt++;
7d3d0439 8646}
d796fdb7
LV		 8647
8648/**
8649 * s2io_io_error_detected - called when PCI error is detected
8650 * @pdev: Pointer to PCI device
8453d43f 8651 * @state: The current pci connection state
d796fdb7
LV		 8652 *
8653 * This function is called after a PCI bus error affecting
8654 * this device has been detected.
8655 */
8656static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
d44570e4 8657 pci_channel_state_t state)
d796fdb7
LV		 8658{
8659 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8660 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8661
8662 netif_device_detach(netdev);
8663
1e3c8bd6
DN		 8664 if (state == pci_channel_io_perm_failure)
8665 return PCI_ERS_RESULT_DISCONNECT;
8666
d796fdb7
LV		 8667 if (netif_running(netdev)) {
8668 /* Bring down the card, while avoiding PCI I/O */
8669 do_s2io_card_down(sp, 0);
d796fdb7
LV		 8670 }
8671 pci_disable_device(pdev);
8672
8673 return PCI_ERS_RESULT_NEED_RESET;
8674}
8675
8676/**
8677 * s2io_io_slot_reset - called after the pci bus has been reset.
8678 * @pdev: Pointer to PCI device
8679 *
8680 * Restart the card from scratch, as if from a cold-boot.
8681 * At this point, the card has exprienced a hard reset,
8682 * followed by fixups by BIOS, and has its config space
8683 * set up identically to what it was at cold boot.
8684 */
8685static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8686{
8687 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8688 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8689
8690 if (pci_enable_device(pdev)) {
6cef2b8e 8691 pr_err("Cannot re-enable PCI device after reset.\n");
d796fdb7
LV		 8692 return PCI_ERS_RESULT_DISCONNECT;
8693 }
8694
8695 pci_set_master(pdev);
8696 s2io_reset(sp);
8697
8698 return PCI_ERS_RESULT_RECOVERED;
8699}
8700
8701/**
8702 * s2io_io_resume - called when traffic can start flowing again.
8703 * @pdev: Pointer to PCI device
8704 *
8705 * This callback is called when the error recovery driver tells
8706 * us that its OK to resume normal operation.
8707 */
8708static void s2io_io_resume(struct pci_dev *pdev)
8709{
8710 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8711 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8712
8713 if (netif_running(netdev)) {
8714 if (s2io_card_up(sp)) {
6cef2b8e 8715 pr_err("Can't bring device back up after reset.\n");
d796fdb7
LV		 8716 return;
8717 }
8718
8719 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8720 s2io_card_down(sp);
6cef2b8e 8721 pr_err("Can't restore mac addr after reset.\n");
d796fdb7
LV		 8722 return;
8723 }
8724 }
8725
8726 netif_device_attach(netdev);
fd2ea0a7 8727 netif_tx_wake_all_queues(netdev);
d796fdb7 8728}
kernel source for telekom puls (alcatel/mediatek)