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r8169: fix crash when large packets are received
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
865c652d 31#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 32#define MODULENAME "r8169"
33#define PFX MODULENAME ": "
34
35#ifdef RTL8169_DEBUG
36#define assert(expr) \
5b0384f4
FR		 37 if (!(expr)) { \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 39 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 40 }
06fa7358
JP		 41#define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 43#else
44#define assert(expr) do {} while (0)
45#define dprintk(fmt, args...) do {} while (0)
46#endif /* RTL8169_DEBUG */
47
b57b7e5a 48#define R8169_MSG_DEFAULT \
f0e837d9 49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 50
1da177e4
LT		 51#define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
1da177e4 54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 55static const int max_interrupt_work = 20;
1da177e4
LT		 56
57/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 59static const int multicast_filter_limit = 32;
1da177e4
LT		 60
61/* MAC address length */
62#define MAC_ADDR_LEN 6
63
9c14ceaf 64#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 65#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 68#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 69#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
70#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
71
72#define R8169_REGS_SIZE 256
73#define R8169_NAPI_WEIGHT 64
74#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
75#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
76#define RX_BUF_SIZE 1536 /* Rx Buffer size */
77#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
78#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
79
80#define RTL8169_TX_TIMEOUT (6*HZ)
81#define RTL8169_PHY_TIMEOUT (10*HZ)
82
ea8dbdd1 83#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
84#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 85#define RTL_EEPROM_SIG_ADDR 0x0000
86
1da177e4
LT		 87/* write/read MMIO register */
88#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
89#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
90#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
91#define RTL_R8(reg) readb (ioaddr + (reg))
92#define RTL_R16(reg) readw (ioaddr + (reg))
93#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
94
95enum mac_version {
ba6eb6ee
FR		 96 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
97 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
98 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
99 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
100 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 101 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 102 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
103 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
104 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
105 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 106 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 107 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
108 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
109 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
110 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
111 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
112 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
113 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
114 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 115 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 116 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0 117 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
7f3e3d3a 118 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
5b538df9
FR		 119 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
120 RTL_GIGA_MAC_VER_25 = 0x19 // 8168D
1da177e4
LT		 121};
122
1da177e4
LT		 123#define _R(NAME,MAC,MASK) \
124 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
125
3c6bee1d 126static const struct {
1da177e4
LT		 127 const char *name;
128 u8 mac_version;
129 u32 RxConfigMask; /* Clears the bits supported by this chip */
130} rtl_chip_info[] = {
ba6eb6ee
FR		 131 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
132 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
133 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
134 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
135 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 137 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
138 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
140 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 141 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
143 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
144 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 145 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
146 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
147 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
148 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
149 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
197ff761 150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
6fb07058 151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
ef3386f0 152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
7f3e3d3a 153 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
5b538df9
FR		 154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
155 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880) // PCI-E
1da177e4
LT		 156};
157#undef _R
158
bcf0bf90
FR		 159enum cfg_version {
160 RTL_CFG_0 = 0x00,
161 RTL_CFG_1,
162 RTL_CFG_2
163};
164
07ce4064
FR		 165static void rtl_hw_start_8169(struct net_device *);
166static void rtl_hw_start_8168(struct net_device *);
167static void rtl_hw_start_8101(struct net_device *);
168
1da177e4 169static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 170 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 171 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 172 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
175 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 176 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 177 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
178 { PCI_VENDOR_ID_LINKSYS, 0x1032,
179 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 180 { 0x0001, 0x8168,
181 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 182 {0,},
183};
184
185MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
186
187static int rx_copybreak = 200;
188static int use_dac;
b57b7e5a
SH		 189static struct {
190 u32 msg_enable;
191} debug = { -1 };
1da177e4 192
07d3f51f
FR		 193enum rtl_registers {
194 MAC0 = 0, /* Ethernet hardware address. */
773d2021 195 MAC4 = 4,
07d3f51f
FR		 196 MAR0 = 8, /* Multicast filter. */
197 CounterAddrLow = 0x10,
198 CounterAddrHigh = 0x14,
199 TxDescStartAddrLow = 0x20,
200 TxDescStartAddrHigh = 0x24,
201 TxHDescStartAddrLow = 0x28,
202 TxHDescStartAddrHigh = 0x2c,
203 FLASH = 0x30,
204 ERSR = 0x36,
205 ChipCmd = 0x37,
206 TxPoll = 0x38,
207 IntrMask = 0x3c,
208 IntrStatus = 0x3e,
209 TxConfig = 0x40,
210 RxConfig = 0x44,
211 RxMissed = 0x4c,
212 Cfg9346 = 0x50,
213 Config0 = 0x51,
214 Config1 = 0x52,
215 Config2 = 0x53,
216 Config3 = 0x54,
217 Config4 = 0x55,
218 Config5 = 0x56,
219 MultiIntr = 0x5c,
220 PHYAR = 0x60,
07d3f51f
FR		 221 PHYstatus = 0x6c,
222 RxMaxSize = 0xda,
223 CPlusCmd = 0xe0,
224 IntrMitigate = 0xe2,
225 RxDescAddrLow = 0xe4,
226 RxDescAddrHigh = 0xe8,
227 EarlyTxThres = 0xec,
228 FuncEvent = 0xf0,
229 FuncEventMask = 0xf4,
230 FuncPresetState = 0xf8,
231 FuncForceEvent = 0xfc,
1da177e4
LT		 232};
233
f162a5d1
FR		 234enum rtl8110_registers {
235 TBICSR = 0x64,
236 TBI_ANAR = 0x68,
237 TBI_LPAR = 0x6a,
238};
239
240enum rtl8168_8101_registers {
241 CSIDR = 0x64,
242 CSIAR = 0x68,
243#define CSIAR_FLAG 0x80000000
244#define CSIAR_WRITE_CMD 0x80000000
245#define CSIAR_BYTE_ENABLE 0x0f
246#define CSIAR_BYTE_ENABLE_SHIFT 12
247#define CSIAR_ADDR_MASK 0x0fff
248
249 EPHYAR = 0x80,
250#define EPHYAR_FLAG 0x80000000
251#define EPHYAR_WRITE_CMD 0x80000000
252#define EPHYAR_REG_MASK 0x1f
253#define EPHYAR_REG_SHIFT 16
254#define EPHYAR_DATA_MASK 0xffff
255 DBG_REG = 0xd1,
256#define FIX_NAK_1 (1 << 4)
257#define FIX_NAK_2 (1 << 3)
258};
259
07d3f51f 260enum rtl_register_content {
1da177e4 261 /* InterruptStatusBits */
07d3f51f
FR		 262 SYSErr = 0x8000,
263 PCSTimeout = 0x4000,
264 SWInt = 0x0100,
265 TxDescUnavail = 0x0080,
266 RxFIFOOver = 0x0040,
267 LinkChg = 0x0020,
268 RxOverflow = 0x0010,
269 TxErr = 0x0008,
270 TxOK = 0x0004,
271 RxErr = 0x0002,
272 RxOK = 0x0001,
1da177e4
LT		 273
274 /* RxStatusDesc */
9dccf611
FR		 275 RxFOVF = (1 << 23),
276 RxRWT = (1 << 22),
277 RxRES = (1 << 21),
278 RxRUNT = (1 << 20),
279 RxCRC = (1 << 19),
1da177e4
LT		 280
281 /* ChipCmdBits */
07d3f51f
FR		 282 CmdReset = 0x10,
283 CmdRxEnb = 0x08,
284 CmdTxEnb = 0x04,
285 RxBufEmpty = 0x01,
1da177e4 286
275391a4
FR		 287 /* TXPoll register p.5 */
288 HPQ = 0x80, /* Poll cmd on the high prio queue */
289 NPQ = 0x40, /* Poll cmd on the low prio queue */
290 FSWInt = 0x01, /* Forced software interrupt */
291
1da177e4 292 /* Cfg9346Bits */
07d3f51f
FR		 293 Cfg9346_Lock = 0x00,
294 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 295
296 /* rx_mode_bits */
07d3f51f
FR		 297 AcceptErr = 0x20,
298 AcceptRunt = 0x10,
299 AcceptBroadcast = 0x08,
300 AcceptMulticast = 0x04,
301 AcceptMyPhys = 0x02,
302 AcceptAllPhys = 0x01,
1da177e4
LT		 303
304 /* RxConfigBits */
07d3f51f
FR		 305 RxCfgFIFOShift = 13,
306 RxCfgDMAShift = 8,
1da177e4
LT		 307
308 /* TxConfigBits */
309 TxInterFrameGapShift = 24,
310 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
311
5d06a99f 312 /* Config1 register p.24 */
f162a5d1
FR		 313 LEDS1 = (1 << 7),
314 LEDS0 = (1 << 6),
fbac58fc 315 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 316 Speed_down = (1 << 4),
317 MEMMAP = (1 << 3),
318 IOMAP = (1 << 2),
319 VPD = (1 << 1),
5d06a99f
FR		 320 PMEnable = (1 << 0), /* Power Management Enable */
321
6dccd16b
FR		 322 /* Config2 register p. 25 */
323 PCI_Clock_66MHz = 0x01,
324 PCI_Clock_33MHz = 0x00,
325
61a4dcc2
FR		 326 /* Config3 register p.25 */
327 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
328 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 329 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 330
5d06a99f 331 /* Config5 register p.27 */
61a4dcc2
FR		 332 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
333 MWF = (1 << 5), /* Accept Multicast wakeup frame */
334 UWF = (1 << 4), /* Accept Unicast wakeup frame */
335 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 336 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
337
1da177e4
LT		 338 /* TBICSR p.28 */
339 TBIReset = 0x80000000,
340 TBILoopback = 0x40000000,
341 TBINwEnable = 0x20000000,
342 TBINwRestart = 0x10000000,
343 TBILinkOk = 0x02000000,
344 TBINwComplete = 0x01000000,
345
346 /* CPlusCmd p.31 */
f162a5d1
FR		 347 EnableBist = (1 << 15), // 8168 8101
348 Mac_dbgo_oe = (1 << 14), // 8168 8101
349 Normal_mode = (1 << 13), // unused
350 Force_half_dup = (1 << 12), // 8168 8101
351 Force_rxflow_en = (1 << 11), // 8168 8101
352 Force_txflow_en = (1 << 10), // 8168 8101
353 Cxpl_dbg_sel = (1 << 9), // 8168 8101
354 ASF = (1 << 8), // 8168 8101
355 PktCntrDisable = (1 << 7), // 8168 8101
356 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 357 RxVlan = (1 << 6),
358 RxChkSum = (1 << 5),
359 PCIDAC = (1 << 4),
360 PCIMulRW = (1 << 3),
0e485150
FR		 361 INTT_0 = 0x0000, // 8168
362 INTT_1 = 0x0001, // 8168
363 INTT_2 = 0x0002, // 8168
364 INTT_3 = 0x0003, // 8168
1da177e4
LT		 365
366 /* rtl8169_PHYstatus */
07d3f51f
FR		 367 TBI_Enable = 0x80,
368 TxFlowCtrl = 0x40,
369 RxFlowCtrl = 0x20,
370 _1000bpsF = 0x10,
371 _100bps = 0x08,
372 _10bps = 0x04,
373 LinkStatus = 0x02,
374 FullDup = 0x01,
1da177e4 375
1da177e4 376 /* _TBICSRBit */
07d3f51f 377 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 378
379 /* DumpCounterCommand */
07d3f51f 380 CounterDump = 0x8,
1da177e4
LT		 381};
382
07d3f51f 383enum desc_status_bit {
1da177e4
LT		 384 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
385 RingEnd = (1 << 30), /* End of descriptor ring */
386 FirstFrag = (1 << 29), /* First segment of a packet */
387 LastFrag = (1 << 28), /* Final segment of a packet */
388
389 /* Tx private */
390 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
391 MSSShift = 16, /* MSS value position */
392 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
393 IPCS = (1 << 18), /* Calculate IP checksum */
394 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
395 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
396 TxVlanTag = (1 << 17), /* Add VLAN tag */
397
398 /* Rx private */
399 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
400 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
401
402#define RxProtoUDP (PID1)
403#define RxProtoTCP (PID0)
404#define RxProtoIP (PID1 | PID0)
405#define RxProtoMask RxProtoIP
406
407 IPFail = (1 << 16), /* IP checksum failed */
408 UDPFail = (1 << 15), /* UDP/IP checksum failed */
409 TCPFail = (1 << 14), /* TCP/IP checksum failed */
410 RxVlanTag = (1 << 16), /* VLAN tag available */
411};
412
413#define RsvdMask 0x3fffc000
414
415struct TxDesc {
6cccd6e7
REB		 416 __le32 opts1;
417 __le32 opts2;
418 __le64 addr;
1da177e4
LT		 419};
420
421struct RxDesc {
6cccd6e7
REB		 422 __le32 opts1;
423 __le32 opts2;
424 __le64 addr;
1da177e4
LT		 425};
426
427struct ring_info {
428 struct sk_buff *skb;
429 u32 len;
430 u8 __pad[sizeof(void *) - sizeof(u32)];
431};
432
f23e7fda 433enum features {
ccdffb9a
FR		 434 RTL_FEATURE_WOL = (1 << 0),
435 RTL_FEATURE_MSI = (1 << 1),
436 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 437};
438
355423d0
IV		 439struct rtl8169_counters {
440 __le64 tx_packets;
441 __le64 rx_packets;
442 __le64 tx_errors;
443 __le32 rx_errors;
444 __le16 rx_missed;
445 __le16 align_errors;
446 __le32 tx_one_collision;
447 __le32 tx_multi_collision;
448 __le64 rx_unicast;
449 __le64 rx_broadcast;
450 __le32 rx_multicast;
451 __le16 tx_aborted;
452 __le16 tx_underun;
453};
454
1da177e4
LT		 455struct rtl8169_private {
456 void __iomem *mmio_addr; /* memory map physical address */
457 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 458 struct net_device *dev;
bea3348e 459 struct napi_struct napi;
1da177e4 460 spinlock_t lock; /* spin lock flag */
b57b7e5a 461 u32 msg_enable;
1da177e4
LT		 462 int chipset;
463 int mac_version;
1da177e4
LT		 464 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
465 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
466 u32 dirty_rx;
467 u32 dirty_tx;
468 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
469 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
470 dma_addr_t TxPhyAddr;
471 dma_addr_t RxPhyAddr;
472 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
473 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 474 unsigned align;
1da177e4
LT		 475 unsigned rx_buf_sz;
476 struct timer_list timer;
477 u16 cp_cmd;
0e485150
FR		 478 u16 intr_event;
479 u16 napi_event;
1da177e4
LT		 480 u16 intr_mask;
481 int phy_auto_nego_reg;
482 int phy_1000_ctrl_reg;
483#ifdef CONFIG_R8169_VLAN
484 struct vlan_group *vlgrp;
485#endif
486 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 487 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
1da177e4 488 void (*phy_reset_enable)(void __iomem *);
07ce4064 489 void (*hw_start)(struct net_device *);
1da177e4
LT		 490 unsigned int (*phy_reset_pending)(void __iomem *);
491 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 492 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 493 int pcie_cap;
c4028958 494 struct delayed_work task;
f23e7fda 495 unsigned features;
ccdffb9a
FR		 496
497 struct mii_if_info mii;
355423d0 498 struct rtl8169_counters counters;
1da177e4
LT		 499};
500
979b6c13 501MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 502MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 503module_param(rx_copybreak, int, 0);
1b7efd58 504MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 505module_param(use_dac, int, 0);
506MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 507module_param_named(debug, debug.msg_enable, int, 0);
508MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 509MODULE_LICENSE("GPL");
510MODULE_VERSION(RTL8169_VERSION);
511
512static int rtl8169_open(struct net_device *dev);
513static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 514static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 515static int rtl8169_init_ring(struct net_device *dev);
07ce4064 516static void rtl_hw_start(struct net_device *dev);
1da177e4 517static int rtl8169_close(struct net_device *dev);
07ce4064 518static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 519static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 520static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 521static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 522 void __iomem *, u32 budget);
4dcb7d33 523static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 524static void rtl8169_down(struct net_device *dev);
99f252b0 525static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 526static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 527
1da177e4 528static const unsigned int rtl8169_rx_config =
5b0384f4 529 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 530
07d3f51f 531static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 532{
533 int i;
534
a6baf3af 535 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 536
2371408c 537 for (i = 20; i > 0; i--) {
07d3f51f
FR		 538 /*
539 * Check if the RTL8169 has completed writing to the specified
540 * MII register.
541 */
5b0384f4 542 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 543 break;
2371408c 544 udelay(25);
1da177e4
LT		 545 }
546}
547
07d3f51f 548static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 549{
550 int i, value = -1;
551
a6baf3af 552 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 553
2371408c 554 for (i = 20; i > 0; i--) {
07d3f51f
FR		 555 /*
556 * Check if the RTL8169 has completed retrieving data from
557 * the specified MII register.
558 */
1da177e4 559 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 560 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 561 break;
562 }
2371408c 563 udelay(25);
1da177e4
LT		 564 }
565 return value;
566}
567
dacf8154
FR		 568static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
569{
570 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
571}
572
ccdffb9a
FR		 573static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
574 int val)
575{
576 struct rtl8169_private *tp = netdev_priv(dev);
577 void __iomem *ioaddr = tp->mmio_addr;
578
579 mdio_write(ioaddr, location, val);
580}
581
582static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
583{
584 struct rtl8169_private *tp = netdev_priv(dev);
585 void __iomem *ioaddr = tp->mmio_addr;
586
587 return mdio_read(ioaddr, location);
588}
589
dacf8154
FR		 590static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
591{
592 unsigned int i;
593
594 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
595 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
596
597 for (i = 0; i < 100; i++) {
598 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
599 break;
600 udelay(10);
601 }
602}
603
604static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
605{
606 u16 value = 0xffff;
607 unsigned int i;
608
609 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
610
611 for (i = 0; i < 100; i++) {
612 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
613 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
614 break;
615 }
616 udelay(10);
617 }
618
619 return value;
620}
621
622static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
623{
624 unsigned int i;
625
626 RTL_W32(CSIDR, value);
627 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
628 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
629
630 for (i = 0; i < 100; i++) {
631 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
632 break;
633 udelay(10);
634 }
635}
636
637static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
638{
639 u32 value = ~0x00;
640 unsigned int i;
641
642 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
643 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
644
645 for (i = 0; i < 100; i++) {
646 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
647 value = RTL_R32(CSIDR);
648 break;
649 }
650 udelay(10);
651 }
652
653 return value;
654}
655
1da177e4
LT		 656static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
657{
658 RTL_W16(IntrMask, 0x0000);
659
660 RTL_W16(IntrStatus, 0xffff);
661}
662
663static void rtl8169_asic_down(void __iomem *ioaddr)
664{
665 RTL_W8(ChipCmd, 0x00);
666 rtl8169_irq_mask_and_ack(ioaddr);
667 RTL_R16(CPlusCmd);
668}
669
670static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
671{
672 return RTL_R32(TBICSR) & TBIReset;
673}
674
675static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
676{
64e4bfb4 677 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 678}
679
680static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
681{
682 return RTL_R32(TBICSR) & TBILinkOk;
683}
684
685static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
686{
687 return RTL_R8(PHYstatus) & LinkStatus;
688}
689
690static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
691{
692 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
693}
694
695static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
696{
697 unsigned int val;
698
9e0db8ef
FR		 699 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
700 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 701}
702
703static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 704 struct rtl8169_private *tp,
705 void __iomem *ioaddr)
1da177e4
LT		 706{
707 unsigned long flags;
708
709 spin_lock_irqsave(&tp->lock, flags);
710 if (tp->link_ok(ioaddr)) {
711 netif_carrier_on(dev);
b57b7e5a
SH		 712 if (netif_msg_ifup(tp))
713 printk(KERN_INFO PFX "%s: link up\n", dev->name);
714 } else {
715 if (netif_msg_ifdown(tp))
716 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 717 netif_carrier_off(dev);
b57b7e5a 718 }
1da177e4
LT		 719 spin_unlock_irqrestore(&tp->lock, flags);
720}
721
61a4dcc2
FR		 722static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
723{
724 struct rtl8169_private *tp = netdev_priv(dev);
725 void __iomem *ioaddr = tp->mmio_addr;
726 u8 options;
727
728 wol->wolopts = 0;
729
730#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
731 wol->supported = WAKE_ANY;
732
733 spin_lock_irq(&tp->lock);
734
735 options = RTL_R8(Config1);
736 if (!(options & PMEnable))
737 goto out_unlock;
738
739 options = RTL_R8(Config3);
740 if (options & LinkUp)
741 wol->wolopts |= WAKE_PHY;
742 if (options & MagicPacket)
743 wol->wolopts |= WAKE_MAGIC;
744
745 options = RTL_R8(Config5);
746 if (options & UWF)
747 wol->wolopts |= WAKE_UCAST;
748 if (options & BWF)
5b0384f4 749 wol->wolopts |= WAKE_BCAST;
61a4dcc2 750 if (options & MWF)
5b0384f4 751 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 752
753out_unlock:
754 spin_unlock_irq(&tp->lock);
755}
756
757static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
758{
759 struct rtl8169_private *tp = netdev_priv(dev);
760 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 761 unsigned int i;
61a4dcc2
FR		 762 static struct {
763 u32 opt;
764 u16 reg;
765 u8 mask;
766 } cfg[] = {
767 { WAKE_ANY, Config1, PMEnable },
768 { WAKE_PHY, Config3, LinkUp },
769 { WAKE_MAGIC, Config3, MagicPacket },
770 { WAKE_UCAST, Config5, UWF },
771 { WAKE_BCAST, Config5, BWF },
772 { WAKE_MCAST, Config5, MWF },
773 { WAKE_ANY, Config5, LanWake }
774 };
775
776 spin_lock_irq(&tp->lock);
777
778 RTL_W8(Cfg9346, Cfg9346_Unlock);
779
780 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
781 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
782 if (wol->wolopts & cfg[i].opt)
783 options |= cfg[i].mask;
784 RTL_W8(cfg[i].reg, options);
785 }
786
787 RTL_W8(Cfg9346, Cfg9346_Lock);
788
f23e7fda
FR		 789 if (wol->wolopts)
790 tp->features |= RTL_FEATURE_WOL;
791 else
792 tp->features &= ~RTL_FEATURE_WOL;
8b76ab39 793 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
61a4dcc2
FR		 794
795 spin_unlock_irq(&tp->lock);
796
797 return 0;
798}
799
1da177e4
LT		 800static void rtl8169_get_drvinfo(struct net_device *dev,
801 struct ethtool_drvinfo *info)
802{
803 struct rtl8169_private *tp = netdev_priv(dev);
804
805 strcpy(info->driver, MODULENAME);
806 strcpy(info->version, RTL8169_VERSION);
807 strcpy(info->bus_info, pci_name(tp->pci_dev));
808}
809
810static int rtl8169_get_regs_len(struct net_device *dev)
811{
812 return R8169_REGS_SIZE;
813}
814
815static int rtl8169_set_speed_tbi(struct net_device *dev,
816 u8 autoneg, u16 speed, u8 duplex)
817{
818 struct rtl8169_private *tp = netdev_priv(dev);
819 void __iomem *ioaddr = tp->mmio_addr;
820 int ret = 0;
821 u32 reg;
822
823 reg = RTL_R32(TBICSR);
824 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
825 (duplex == DUPLEX_FULL)) {
826 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
827 } else if (autoneg == AUTONEG_ENABLE)
828 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
829 else {
b57b7e5a
SH		 830 if (netif_msg_link(tp)) {
831 printk(KERN_WARNING "%s: "
832 "incorrect speed setting refused in TBI mode\n",
833 dev->name);
834 }
1da177e4
LT		 835 ret = -EOPNOTSUPP;
836 }
837
838 return ret;
839}
840
841static int rtl8169_set_speed_xmii(struct net_device *dev,
842 u8 autoneg, u16 speed, u8 duplex)
843{
844 struct rtl8169_private *tp = netdev_priv(dev);
845 void __iomem *ioaddr = tp->mmio_addr;
846 int auto_nego, giga_ctrl;
847
64e4bfb4
FR		 848 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
849 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
850 ADVERTISE_100HALF | ADVERTISE_100FULL);
851 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
852 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 853
854 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 855 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
856 ADVERTISE_100HALF | ADVERTISE_100FULL);
857 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 858 } else {
859 if (speed == SPEED_10)
64e4bfb4 860 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 861 else if (speed == SPEED_100)
64e4bfb4 862 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 863 else if (speed == SPEED_1000)
64e4bfb4 864 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 865
866 if (duplex == DUPLEX_HALF)
64e4bfb4 867 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 868
869 if (duplex == DUPLEX_FULL)
64e4bfb4 870 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 871
872 /* This tweak comes straight from Realtek's driver. */
873 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
e3cf0cc0
FR		 874 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
875 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
64e4bfb4 876 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 877 }
878 }
879
2857ffb7
FR		 880 /* The 8100e/8101e/8102e do Fast Ethernet only. */
881 if ((tp->mac_version == RTL_GIGA_MAC_VER_07) ||
882 (tp->mac_version == RTL_GIGA_MAC_VER_08) ||
883 (tp->mac_version == RTL_GIGA_MAC_VER_09) ||
884 (tp->mac_version == RTL_GIGA_MAC_VER_10) ||
885 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
bcf0bf90 886 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
e3cf0cc0
FR		 887 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
888 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
64e4bfb4 889 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 890 netif_msg_link(tp)) {
891 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
892 dev->name);
893 }
64e4bfb4 894 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 895 }
896
623a1593
FR		 897 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
898
a2de6b89
FR		 899 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
900 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
901 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
902 /*
903 * Wake up the PHY.
904 * Vendor specific (0x1f) and reserved (0x0e) MII registers.
905 */
2584fbc3
RS		 906 mdio_write(ioaddr, 0x1f, 0x0000);
907 mdio_write(ioaddr, 0x0e, 0x0000);
908 }
909
1da177e4
LT		 910 tp->phy_auto_nego_reg = auto_nego;
911 tp->phy_1000_ctrl_reg = giga_ctrl;
912
64e4bfb4
FR		 913 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
914 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
915 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 916 return 0;
917}
918
919static int rtl8169_set_speed(struct net_device *dev,
920 u8 autoneg, u16 speed, u8 duplex)
921{
922 struct rtl8169_private *tp = netdev_priv(dev);
923 int ret;
924
925 ret = tp->set_speed(dev, autoneg, speed, duplex);
926
64e4bfb4 927 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 928 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
929
930 return ret;
931}
932
933static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
934{
935 struct rtl8169_private *tp = netdev_priv(dev);
936 unsigned long flags;
937 int ret;
938
939 spin_lock_irqsave(&tp->lock, flags);
940 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
941 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 942
1da177e4
LT		 943 return ret;
944}
945
946static u32 rtl8169_get_rx_csum(struct net_device *dev)
947{
948 struct rtl8169_private *tp = netdev_priv(dev);
949
950 return tp->cp_cmd & RxChkSum;
951}
952
953static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
954{
955 struct rtl8169_private *tp = netdev_priv(dev);
956 void __iomem *ioaddr = tp->mmio_addr;
957 unsigned long flags;
958
959 spin_lock_irqsave(&tp->lock, flags);
960
961 if (data)
962 tp->cp_cmd |= RxChkSum;
963 else
964 tp->cp_cmd &= ~RxChkSum;
965
966 RTL_W16(CPlusCmd, tp->cp_cmd);
967 RTL_R16(CPlusCmd);
968
969 spin_unlock_irqrestore(&tp->lock, flags);
970
971 return 0;
972}
973
974#ifdef CONFIG_R8169_VLAN
975
976static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
977 struct sk_buff *skb)
978{
979 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
980 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
981}
982
983static void rtl8169_vlan_rx_register(struct net_device *dev,
984 struct vlan_group *grp)
985{
986 struct rtl8169_private *tp = netdev_priv(dev);
987 void __iomem *ioaddr = tp->mmio_addr;
988 unsigned long flags;
989
990 spin_lock_irqsave(&tp->lock, flags);
991 tp->vlgrp = grp;
992 if (tp->vlgrp)
993 tp->cp_cmd |= RxVlan;
994 else
995 tp->cp_cmd &= ~RxVlan;
996 RTL_W16(CPlusCmd, tp->cp_cmd);
997 RTL_R16(CPlusCmd);
998 spin_unlock_irqrestore(&tp->lock, flags);
999}
1000
1da177e4
LT		 1001static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1002 struct sk_buff *skb)
1003{
1004 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 1005 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 1006 int ret;
1007
865c652d
FR		 1008 if (vlgrp && (opts2 & RxVlanTag)) {
1009 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 1010 ret = 0;
1011 } else
1012 ret = -1;
1013 desc->opts2 = 0;
1014 return ret;
1015}
1016
1017#else /* !CONFIG_R8169_VLAN */
1018
1019static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1020 struct sk_buff *skb)
1021{
1022 return 0;
1023}
1024
1025static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1026 struct sk_buff *skb)
1027{
1028 return -1;
1029}
1030
1031#endif
1032
ccdffb9a 1033static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1034{
1035 struct rtl8169_private *tp = netdev_priv(dev);
1036 void __iomem *ioaddr = tp->mmio_addr;
1037 u32 status;
1038
1039 cmd->supported =
1040 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1041 cmd->port = PORT_FIBRE;
1042 cmd->transceiver = XCVR_INTERNAL;
1043
1044 status = RTL_R32(TBICSR);
1045 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1046 cmd->autoneg = !!(status & TBINwEnable);
1047
1048 cmd->speed = SPEED_1000;
1049 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1050
1051 return 0;
1da177e4
LT		 1052}
1053
ccdffb9a 1054static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1055{
1056 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1057
1058 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1059}
1060
1061static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1062{
1063 struct rtl8169_private *tp = netdev_priv(dev);
1064 unsigned long flags;
ccdffb9a 1065 int rc;
1da177e4
LT		 1066
1067 spin_lock_irqsave(&tp->lock, flags);
1068
ccdffb9a 1069 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1070
1071 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1072 return rc;
1da177e4
LT		 1073}
1074
1075static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1076 void *p)
1077{
5b0384f4
FR		 1078 struct rtl8169_private *tp = netdev_priv(dev);
1079 unsigned long flags;
1da177e4 1080
5b0384f4
FR		 1081 if (regs->len > R8169_REGS_SIZE)
1082 regs->len = R8169_REGS_SIZE;
1da177e4 1083
5b0384f4
FR		 1084 spin_lock_irqsave(&tp->lock, flags);
1085 memcpy_fromio(p, tp->mmio_addr, regs->len);
1086 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1087}
1088
b57b7e5a
SH		 1089static u32 rtl8169_get_msglevel(struct net_device *dev)
1090{
1091 struct rtl8169_private *tp = netdev_priv(dev);
1092
1093 return tp->msg_enable;
1094}
1095
1096static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1097{
1098 struct rtl8169_private *tp = netdev_priv(dev);
1099
1100 tp->msg_enable = value;
1101}
1102
d4a3a0fc
SH		 1103static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1104 "tx_packets",
1105 "rx_packets",
1106 "tx_errors",
1107 "rx_errors",
1108 "rx_missed",
1109 "align_errors",
1110 "tx_single_collisions",
1111 "tx_multi_collisions",
1112 "unicast",
1113 "broadcast",
1114 "multicast",
1115 "tx_aborted",
1116 "tx_underrun",
1117};
1118
b9f2c044 1119static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1120{
b9f2c044
JG		 1121 switch (sset) {
1122 case ETH_SS_STATS:
1123 return ARRAY_SIZE(rtl8169_gstrings);
1124 default:
1125 return -EOPNOTSUPP;
1126 }
d4a3a0fc
SH		 1127}
1128
355423d0 1129static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1130{
1131 struct rtl8169_private *tp = netdev_priv(dev);
1132 void __iomem *ioaddr = tp->mmio_addr;
1133 struct rtl8169_counters *counters;
1134 dma_addr_t paddr;
1135 u32 cmd;
355423d0 1136 int wait = 1000;
d4a3a0fc 1137
355423d0
IV		 1138 /*
1139 * Some chips are unable to dump tally counters when the receiver
1140 * is disabled.
1141 */
1142 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1143 return;
d4a3a0fc
SH		 1144
1145 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1146 if (!counters)
1147 return;
1148
1149 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1150 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1151 RTL_W32(CounterAddrLow, cmd);
1152 RTL_W32(CounterAddrLow, cmd | CounterDump);
1153
355423d0
IV		 1154 while (wait--) {
1155 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1156 /* copy updated counters */
1157 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1158 break;
355423d0
IV		 1159 }
1160 udelay(10);
d4a3a0fc
SH		 1161 }
1162
1163 RTL_W32(CounterAddrLow, 0);
1164 RTL_W32(CounterAddrHigh, 0);
1165
d4a3a0fc
SH		 1166 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1167}
1168
355423d0
IV		 1169static void rtl8169_get_ethtool_stats(struct net_device *dev,
1170 struct ethtool_stats *stats, u64 *data)
1171{
1172 struct rtl8169_private *tp = netdev_priv(dev);
1173
1174 ASSERT_RTNL();
1175
1176 rtl8169_update_counters(dev);
1177
1178 data[0] = le64_to_cpu(tp->counters.tx_packets);
1179 data[1] = le64_to_cpu(tp->counters.rx_packets);
1180 data[2] = le64_to_cpu(tp->counters.tx_errors);
1181 data[3] = le32_to_cpu(tp->counters.rx_errors);
1182 data[4] = le16_to_cpu(tp->counters.rx_missed);
1183 data[5] = le16_to_cpu(tp->counters.align_errors);
1184 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1185 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1186 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1187 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1188 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1189 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1190 data[12] = le16_to_cpu(tp->counters.tx_underun);
1191}
1192
d4a3a0fc
SH		 1193static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1194{
1195 switch(stringset) {
1196 case ETH_SS_STATS:
1197 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1198 break;
1199 }
1200}
1201
7282d491 1202static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1203 .get_drvinfo = rtl8169_get_drvinfo,
1204 .get_regs_len = rtl8169_get_regs_len,
1205 .get_link = ethtool_op_get_link,
1206 .get_settings = rtl8169_get_settings,
1207 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1208 .get_msglevel = rtl8169_get_msglevel,
1209 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1210 .get_rx_csum = rtl8169_get_rx_csum,
1211 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1212 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1213 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1214 .set_tso = ethtool_op_set_tso,
1215 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1216 .get_wol = rtl8169_get_wol,
1217 .set_wol = rtl8169_set_wol,
d4a3a0fc 1218 .get_strings = rtl8169_get_strings,
b9f2c044 1219 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1220 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1221};
1222
07d3f51f
FR		 1223static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1224 int bitnum, int bitval)
1da177e4
LT		 1225{
1226 int val;
1227
1228 val = mdio_read(ioaddr, reg);
1229 val = (bitval == 1) ?
1230 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1231 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1232}
1233
07d3f51f
FR		 1234static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1235 void __iomem *ioaddr)
1da177e4 1236{
0e485150
FR		 1237 /*
1238 * The driver currently handles the 8168Bf and the 8168Be identically
1239 * but they can be identified more specifically through the test below
1240 * if needed:
1241 *
1242 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1243 *
1244 * Same thing for the 8101Eb and the 8101Ec:
1245 *
1246 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1247 */
1da177e4
LT		 1248 const struct {
1249 u32 mask;
e3cf0cc0 1250 u32 val;
1da177e4
LT		 1251 int mac_version;
1252 } mac_info[] = {
5b538df9
FR		 1253 /* 8168D family. */
1254 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_25 },
1255
ef808d50 1256 /* 8168C family. */
7f3e3d3a 1257 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1258 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1259 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1260 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1261 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1262 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1263 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1264 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1265 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1266
1267 /* 8168B family. */
1268 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1269 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1270 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1271 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1272
1273 /* 8101 family. */
2857ffb7
FR		 1274 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1275 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1276 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1277 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1278 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1279 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1280 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1281 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1282 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1283 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1284 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1285 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1286 /* FIXME: where did these entries come from ? -- FR */
1287 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1288 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1289
1290 /* 8110 family. */
1291 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1292 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1293 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1294 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1295 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1296 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1297
1298 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1299 }, *p = mac_info;
1300 u32 reg;
1301
e3cf0cc0
FR		 1302 reg = RTL_R32(TxConfig);
1303 while ((reg & p->mask) != p->val)
1da177e4
LT		 1304 p++;
1305 tp->mac_version = p->mac_version;
e3cf0cc0
FR		 1306
1307 if (p->mask == 0x00000000) {
1308 struct pci_dev *pdev = tp->pci_dev;
1309
1310 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1311 }
1da177e4
LT		 1312}
1313
1314static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1315{
bcf0bf90 1316 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1317}
1318
867763c1
FR		 1319struct phy_reg {
1320 u16 reg;
1321 u16 val;
1322};
1323
1324static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1325{
1326 while (len-- > 0) {
1327 mdio_write(ioaddr, regs->reg, regs->val);
1328 regs++;
1329 }
1330}
1331
5615d9f1 1332static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1333{
1da177e4
LT		 1334 struct {
1335 u16 regs[5]; /* Beware of bit-sign propagation */
1336 } phy_magic[5] = { {
1337 { 0x0000, //w 4 15 12 0
1338 0x00a1, //w 3 15 0 00a1
1339 0x0008, //w 2 15 0 0008
1340 0x1020, //w 1 15 0 1020
1341 0x1000 } },{ //w 0 15 0 1000
1342 { 0x7000, //w 4 15 12 7
1343 0xff41, //w 3 15 0 ff41
1344 0xde60, //w 2 15 0 de60
1345 0x0140, //w 1 15 0 0140
1346 0x0077 } },{ //w 0 15 0 0077
1347 { 0xa000, //w 4 15 12 a
1348 0xdf01, //w 3 15 0 df01
1349 0xdf20, //w 2 15 0 df20
1350 0xff95, //w 1 15 0 ff95
1351 0xfa00 } },{ //w 0 15 0 fa00
1352 { 0xb000, //w 4 15 12 b
1353 0xff41, //w 3 15 0 ff41
1354 0xde20, //w 2 15 0 de20
1355 0x0140, //w 1 15 0 0140
1356 0x00bb } },{ //w 0 15 0 00bb
1357 { 0xf000, //w 4 15 12 f
1358 0xdf01, //w 3 15 0 df01
1359 0xdf20, //w 2 15 0 df20
1360 0xff95, //w 1 15 0 ff95
1361 0xbf00 } //w 0 15 0 bf00
1362 }
1363 }, *p = phy_magic;
07d3f51f 1364 unsigned int i;
1da177e4 1365
a441d7b6
FR		 1366 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1367 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1368 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1da177e4
LT		 1369 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1370
1371 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1372 int val, pos = 4;
1373
1374 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1375 mdio_write(ioaddr, pos, val);
1376 while (--pos >= 0)
1377 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1378 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1379 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1380 }
a441d7b6 1381 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1da177e4
LT		 1382}
1383
5615d9f1
FR		 1384static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1385{
a441d7b6
FR		 1386 struct phy_reg phy_reg_init[] = {
1387 { 0x1f, 0x0002 },
1388 { 0x01, 0x90d0 },
1389 { 0x1f, 0x0000 }
1390 };
1391
1392 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1393}
1394
236b8082
FR		 1395static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1396{
1397 struct phy_reg phy_reg_init[] = {
1398 { 0x10, 0xf41b },
1399 { 0x1f, 0x0000 }
1400 };
1401
1402 mdio_write(ioaddr, 0x1f, 0x0001);
1403 mdio_patch(ioaddr, 0x16, 1 << 0);
1404
1405 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1406}
1407
1408static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1409{
1410 struct phy_reg phy_reg_init[] = {
1411 { 0x1f, 0x0001 },
1412 { 0x10, 0xf41b },
1413 { 0x1f, 0x0000 }
1414 };
1415
1416 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1417}
1418
ef3386f0 1419static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
867763c1
FR		 1420{
1421 struct phy_reg phy_reg_init[] = {
1422 { 0x1f, 0x0000 },
1423 { 0x1d, 0x0f00 },
1424 { 0x1f, 0x0002 },
1425 { 0x0c, 0x1ec8 },
1426 { 0x1f, 0x0000 }
1427 };
1428
1429 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1430}
1431
ef3386f0
FR		 1432static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1433{
1434 struct phy_reg phy_reg_init[] = {
1435 { 0x1f, 0x0001 },
1436 { 0x1d, 0x3d98 },
1437 { 0x1f, 0x0000 }
1438 };
1439
1440 mdio_write(ioaddr, 0x1f, 0x0000);
1441 mdio_patch(ioaddr, 0x14, 1 << 5);
1442 mdio_patch(ioaddr, 0x0d, 1 << 5);
1443
1444 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1445}
1446
219a1e9d 1447static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
867763c1
FR		 1448{
1449 struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1450 { 0x1f, 0x0001 },
1451 { 0x12, 0x2300 },
867763c1
FR		 1452 { 0x1f, 0x0002 },
1453 { 0x00, 0x88d4 },
1454 { 0x01, 0x82b1 },
1455 { 0x03, 0x7002 },
1456 { 0x08, 0x9e30 },
1457 { 0x09, 0x01f0 },
1458 { 0x0a, 0x5500 },
1459 { 0x0c, 0x00c8 },
1460 { 0x1f, 0x0003 },
1461 { 0x12, 0xc096 },
1462 { 0x16, 0x000a },
f50d4275
FR		 1463 { 0x1f, 0x0000 },
1464 { 0x1f, 0x0000 },
1465 { 0x09, 0x2000 },
1466 { 0x09, 0x0000 }
867763c1
FR		 1467 };
1468
1469 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1470
1471 mdio_patch(ioaddr, 0x14, 1 << 5);
1472 mdio_patch(ioaddr, 0x0d, 1 << 5);
1473 mdio_write(ioaddr, 0x1f, 0x0000);
867763c1
FR		 1474}
1475
219a1e9d 1476static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
7da97ec9
FR		 1477{
1478 struct phy_reg phy_reg_init[] = {
f50d4275 1479 { 0x1f, 0x0001 },
7da97ec9 1480 { 0x12, 0x2300 },
f50d4275
FR		 1481 { 0x03, 0x802f },
1482 { 0x02, 0x4f02 },
1483 { 0x01, 0x0409 },
1484 { 0x00, 0xf099 },
1485 { 0x04, 0x9800 },
1486 { 0x04, 0x9000 },
1487 { 0x1d, 0x3d98 },
7da97ec9
FR		 1488 { 0x1f, 0x0002 },
1489 { 0x0c, 0x7eb8 },
f50d4275
FR		 1490 { 0x06, 0x0761 },
1491 { 0x1f, 0x0003 },
1492 { 0x16, 0x0f0a },
7da97ec9
FR		 1493 { 0x1f, 0x0000 }
1494 };
1495
1496 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1497
1498 mdio_patch(ioaddr, 0x16, 1 << 0);
1499 mdio_patch(ioaddr, 0x14, 1 << 5);
1500 mdio_patch(ioaddr, 0x0d, 1 << 5);
1501 mdio_write(ioaddr, 0x1f, 0x0000);
7da97ec9
FR		 1502}
1503
197ff761
FR		 1504static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1505{
1506 struct phy_reg phy_reg_init[] = {
1507 { 0x1f, 0x0001 },
1508 { 0x12, 0x2300 },
1509 { 0x1d, 0x3d98 },
1510 { 0x1f, 0x0002 },
1511 { 0x0c, 0x7eb8 },
1512 { 0x06, 0x5461 },
1513 { 0x1f, 0x0003 },
1514 { 0x16, 0x0f0a },
1515 { 0x1f, 0x0000 }
1516 };
1517
1518 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1519
1520 mdio_patch(ioaddr, 0x16, 1 << 0);
1521 mdio_patch(ioaddr, 0x14, 1 << 5);
1522 mdio_patch(ioaddr, 0x0d, 1 << 5);
1523 mdio_write(ioaddr, 0x1f, 0x0000);
1524}
1525
6fb07058
FR		 1526static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1527{
1528 rtl8168c_3_hw_phy_config(ioaddr);
1529}
1530
5b538df9
FR		 1531static void rtl8168d_hw_phy_config(void __iomem *ioaddr)
1532{
1533 struct phy_reg phy_reg_init_0[] = {
1534 { 0x1f, 0x0001 },
1535 { 0x09, 0x2770 },
1536 { 0x08, 0x04d0 },
1537 { 0x0b, 0xad15 },
1538 { 0x0c, 0x5bf0 },
1539 { 0x1c, 0xf101 },
1540 { 0x1f, 0x0003 },
1541 { 0x14, 0x94d7 },
1542 { 0x12, 0xf4d6 },
1543 { 0x09, 0xca0f },
1544 { 0x1f, 0x0002 },
1545 { 0x0b, 0x0b10 },
1546 { 0x0c, 0xd1f7 },
1547 { 0x1f, 0x0002 },
1548 { 0x06, 0x5461 },
1549 { 0x1f, 0x0002 },
1550 { 0x05, 0x6662 },
1551 { 0x1f, 0x0000 },
1552 { 0x14, 0x0060 },
1553 { 0x1f, 0x0000 },
1554 { 0x0d, 0xf8a0 },
1555 { 0x1f, 0x0005 },
1556 { 0x05, 0xffc2 }
1557 };
1558
1559 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
1560
1561 if (mdio_read(ioaddr, 0x06) == 0xc400) {
1562 struct phy_reg phy_reg_init_1[] = {
1563 { 0x1f, 0x0005 },
1564 { 0x01, 0x0300 },
1565 { 0x1f, 0x0000 },
1566 { 0x11, 0x401c },
1567 { 0x16, 0x4100 },
1568 { 0x1f, 0x0005 },
1569 { 0x07, 0x0010 },
1570 { 0x05, 0x83dc },
1571 { 0x06, 0x087d },
1572 { 0x05, 0x8300 },
1573 { 0x06, 0x0101 },
1574 { 0x06, 0x05f8 },
1575 { 0x06, 0xf9fa },
1576 { 0x06, 0xfbef },
1577 { 0x06, 0x79e2 },
1578 { 0x06, 0x835f },
1579 { 0x06, 0xe0f8 },
1580 { 0x06, 0x9ae1 },
1581 { 0x06, 0xf89b },
1582 { 0x06, 0xef31 },
1583 { 0x06, 0x3b65 },
1584 { 0x06, 0xaa07 },
1585 { 0x06, 0x81e4 },
1586 { 0x06, 0xf89a },
1587 { 0x06, 0xe5f8 },
1588 { 0x06, 0x9baf },
1589 { 0x06, 0x06ae },
1590 { 0x05, 0x83dc },
1591 { 0x06, 0x8300 },
1592 };
1593
1594 rtl_phy_write(ioaddr, phy_reg_init_1,
1595 ARRAY_SIZE(phy_reg_init_1));
1596 }
1597
1598 mdio_write(ioaddr, 0x1f, 0x0000);
1599}
1600
2857ffb7
FR		 1601static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1602{
1603 struct phy_reg phy_reg_init[] = {
1604 { 0x1f, 0x0003 },
1605 { 0x08, 0x441d },
1606 { 0x01, 0x9100 },
1607 { 0x1f, 0x0000 }
1608 };
1609
1610 mdio_write(ioaddr, 0x1f, 0x0000);
1611 mdio_patch(ioaddr, 0x11, 1 << 12);
1612 mdio_patch(ioaddr, 0x19, 1 << 13);
1613
1614 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1615}
1616
5615d9f1
FR		 1617static void rtl_hw_phy_config(struct net_device *dev)
1618{
1619 struct rtl8169_private *tp = netdev_priv(dev);
1620 void __iomem *ioaddr = tp->mmio_addr;
1621
1622 rtl8169_print_mac_version(tp);
1623
1624 switch (tp->mac_version) {
1625 case RTL_GIGA_MAC_VER_01:
1626 break;
1627 case RTL_GIGA_MAC_VER_02:
1628 case RTL_GIGA_MAC_VER_03:
1629 rtl8169s_hw_phy_config(ioaddr);
1630 break;
1631 case RTL_GIGA_MAC_VER_04:
1632 rtl8169sb_hw_phy_config(ioaddr);
1633 break;
2857ffb7
FR		 1634 case RTL_GIGA_MAC_VER_07:
1635 case RTL_GIGA_MAC_VER_08:
1636 case RTL_GIGA_MAC_VER_09:
1637 rtl8102e_hw_phy_config(ioaddr);
1638 break;
236b8082
FR		 1639 case RTL_GIGA_MAC_VER_11:
1640 rtl8168bb_hw_phy_config(ioaddr);
1641 break;
1642 case RTL_GIGA_MAC_VER_12:
1643 rtl8168bef_hw_phy_config(ioaddr);
1644 break;
1645 case RTL_GIGA_MAC_VER_17:
1646 rtl8168bef_hw_phy_config(ioaddr);
1647 break;
867763c1 1648 case RTL_GIGA_MAC_VER_18:
ef3386f0 1649 rtl8168cp_1_hw_phy_config(ioaddr);
867763c1
FR		 1650 break;
1651 case RTL_GIGA_MAC_VER_19:
219a1e9d 1652 rtl8168c_1_hw_phy_config(ioaddr);
867763c1 1653 break;
7da97ec9 1654 case RTL_GIGA_MAC_VER_20:
219a1e9d 1655 rtl8168c_2_hw_phy_config(ioaddr);
7da97ec9 1656 break;
197ff761
FR		 1657 case RTL_GIGA_MAC_VER_21:
1658 rtl8168c_3_hw_phy_config(ioaddr);
1659 break;
6fb07058
FR		 1660 case RTL_GIGA_MAC_VER_22:
1661 rtl8168c_4_hw_phy_config(ioaddr);
1662 break;
ef3386f0 1663 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 1664 case RTL_GIGA_MAC_VER_24:
ef3386f0
FR		 1665 rtl8168cp_2_hw_phy_config(ioaddr);
1666 break;
5b538df9
FR		 1667 case RTL_GIGA_MAC_VER_25:
1668 rtl8168d_hw_phy_config(ioaddr);
1669 break;
ef3386f0 1670
5615d9f1
FR		 1671 default:
1672 break;
1673 }
1674}
1675
1da177e4
LT		 1676static void rtl8169_phy_timer(unsigned long __opaque)
1677{
1678 struct net_device *dev = (struct net_device *)__opaque;
1679 struct rtl8169_private *tp = netdev_priv(dev);
1680 struct timer_list *timer = &tp->timer;
1681 void __iomem *ioaddr = tp->mmio_addr;
1682 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1683
bcf0bf90 1684 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 1685
64e4bfb4 1686 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1687 return;
1688
1689 spin_lock_irq(&tp->lock);
1690
1691 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1692 /*
1da177e4
LT		 1693 * A busy loop could burn quite a few cycles on nowadays CPU.
1694 * Let's delay the execution of the timer for a few ticks.
1695 */
1696 timeout = HZ/10;
1697 goto out_mod_timer;
1698 }
1699
1700 if (tp->link_ok(ioaddr))
1701 goto out_unlock;
1702
b57b7e5a
SH		 1703 if (netif_msg_link(tp))
1704 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1705
1706 tp->phy_reset_enable(ioaddr);
1707
1708out_mod_timer:
1709 mod_timer(timer, jiffies + timeout);
1710out_unlock:
1711 spin_unlock_irq(&tp->lock);
1712}
1713
1714static inline void rtl8169_delete_timer(struct net_device *dev)
1715{
1716 struct rtl8169_private *tp = netdev_priv(dev);
1717 struct timer_list *timer = &tp->timer;
1718
e179bb7b 1719 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1720 return;
1721
1722 del_timer_sync(timer);
1723}
1724
1725static inline void rtl8169_request_timer(struct net_device *dev)
1726{
1727 struct rtl8169_private *tp = netdev_priv(dev);
1728 struct timer_list *timer = &tp->timer;
1729
e179bb7b 1730 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1731 return;
1732
2efa53f3 1733 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1734}
1735
1736#ifdef CONFIG_NET_POLL_CONTROLLER
1737/*
1738 * Polling 'interrupt' - used by things like netconsole to send skbs
1739 * without having to re-enable interrupts. It's not called while
1740 * the interrupt routine is executing.
1741 */
1742static void rtl8169_netpoll(struct net_device *dev)
1743{
1744 struct rtl8169_private *tp = netdev_priv(dev);
1745 struct pci_dev *pdev = tp->pci_dev;
1746
1747 disable_irq(pdev->irq);
7d12e780 1748 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1749 enable_irq(pdev->irq);
1750}
1751#endif
1752
1753static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1754 void __iomem *ioaddr)
1755{
1756 iounmap(ioaddr);
1757 pci_release_regions(pdev);
1758 pci_disable_device(pdev);
1759 free_netdev(dev);
1760}
1761
bf793295
FR		 1762static void rtl8169_phy_reset(struct net_device *dev,
1763 struct rtl8169_private *tp)
1764{
1765 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1766 unsigned int i;
bf793295
FR		 1767
1768 tp->phy_reset_enable(ioaddr);
1769 for (i = 0; i < 100; i++) {
1770 if (!tp->phy_reset_pending(ioaddr))
1771 return;
1772 msleep(1);
1773 }
1774 if (netif_msg_link(tp))
1775 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1776}
1777
4ff96fa6
FR		 1778static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1779{
1780 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 1781
5615d9f1 1782 rtl_hw_phy_config(dev);
4ff96fa6 1783
77332894
MS		 1784 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1785 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1786 RTL_W8(0x82, 0x01);
1787 }
4ff96fa6 1788
6dccd16b
FR		 1789 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1790
1791 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1792 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1793
bcf0bf90 1794 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1795 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1796 RTL_W8(0x82, 0x01);
1797 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1798 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1799 }
1800
bf793295
FR		 1801 rtl8169_phy_reset(dev, tp);
1802
901dda2b
FR		 1803 /*
1804 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1805 * only 8101. Don't panic.
1806 */
1807 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6
FR		 1808
1809 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1810 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1811}
1812
773d2021
FR		 1813static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1814{
1815 void __iomem *ioaddr = tp->mmio_addr;
1816 u32 high;
1817 u32 low;
1818
1819 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1820 high = addr[4] | (addr[5] << 8);
1821
1822 spin_lock_irq(&tp->lock);
1823
1824 RTL_W8(Cfg9346, Cfg9346_Unlock);
1825 RTL_W32(MAC0, low);
1826 RTL_W32(MAC4, high);
1827 RTL_W8(Cfg9346, Cfg9346_Lock);
1828
1829 spin_unlock_irq(&tp->lock);
1830}
1831
1832static int rtl_set_mac_address(struct net_device *dev, void *p)
1833{
1834 struct rtl8169_private *tp = netdev_priv(dev);
1835 struct sockaddr *addr = p;
1836
1837 if (!is_valid_ether_addr(addr->sa_data))
1838 return -EADDRNOTAVAIL;
1839
1840 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1841
1842 rtl_rar_set(tp, dev->dev_addr);
1843
1844 return 0;
1845}
1846
5f787a1a
FR		 1847static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1848{
1849 struct rtl8169_private *tp = netdev_priv(dev);
1850 struct mii_ioctl_data *data = if_mii(ifr);
1851
8b4ab28d
FR		 1852 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
1853}
5f787a1a 1854
8b4ab28d
FR		 1855static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
1856{
5f787a1a
FR		 1857 switch (cmd) {
1858 case SIOCGMIIPHY:
1859 data->phy_id = 32; /* Internal PHY */
1860 return 0;
1861
1862 case SIOCGMIIREG:
1863 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1864 return 0;
1865
1866 case SIOCSMIIREG:
1867 if (!capable(CAP_NET_ADMIN))
1868 return -EPERM;
1869 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1870 return 0;
1871 }
1872 return -EOPNOTSUPP;
1873}
1874
8b4ab28d
FR		 1875static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
1876{
1877 return -EOPNOTSUPP;
1878}
1879
0e485150
FR		 1880static const struct rtl_cfg_info {
1881 void (*hw_start)(struct net_device *);
1882 unsigned int region;
1883 unsigned int align;
1884 u16 intr_event;
1885 u16 napi_event;
ccdffb9a 1886 unsigned features;
0e485150
FR		 1887} rtl_cfg_infos [] = {
1888 [RTL_CFG_0] = {
1889 .hw_start = rtl_hw_start_8169,
1890 .region = 1,
e9f63f30 1891 .align = 0,
0e485150
FR		 1892 .intr_event = SYSErr | LinkChg | RxOverflow |
1893 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 1894 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1895 .features = RTL_FEATURE_GMII
0e485150
FR		 1896 },
1897 [RTL_CFG_1] = {
1898 .hw_start = rtl_hw_start_8168,
1899 .region = 2,
1900 .align = 8,
1901 .intr_event = SYSErr | LinkChg | RxOverflow |
1902 TxErr | TxOK | RxOK | RxErr,
fbac58fc 1903 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1904 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI
0e485150
FR		 1905 },
1906 [RTL_CFG_2] = {
1907 .hw_start = rtl_hw_start_8101,
1908 .region = 2,
1909 .align = 8,
1910 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1911 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 1912 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1913 .features = RTL_FEATURE_MSI
0e485150
FR		 1914 }
1915};
1916
fbac58fc
FR		 1917/* Cfg9346_Unlock assumed. */
1918static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1919 const struct rtl_cfg_info *cfg)
1920{
1921 unsigned msi = 0;
1922 u8 cfg2;
1923
1924 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 1925 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 1926 if (pci_enable_msi(pdev)) {
1927 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1928 } else {
1929 cfg2 |= MSIEnable;
1930 msi = RTL_FEATURE_MSI;
1931 }
1932 }
1933 RTL_W8(Config2, cfg2);
1934 return msi;
1935}
1936
1937static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1938{
1939 if (tp->features & RTL_FEATURE_MSI) {
1940 pci_disable_msi(pdev);
1941 tp->features &= ~RTL_FEATURE_MSI;
1942 }
1943}
1944
8b4ab28d
FR		 1945static const struct net_device_ops rtl8169_netdev_ops = {
1946 .ndo_open = rtl8169_open,
1947 .ndo_stop = rtl8169_close,
1948 .ndo_get_stats = rtl8169_get_stats,
00829823 1949 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 1950 .ndo_tx_timeout = rtl8169_tx_timeout,
1951 .ndo_validate_addr = eth_validate_addr,
1952 .ndo_change_mtu = rtl8169_change_mtu,
1953 .ndo_set_mac_address = rtl_set_mac_address,
1954 .ndo_do_ioctl = rtl8169_ioctl,
1955 .ndo_set_multicast_list = rtl_set_rx_mode,
1956#ifdef CONFIG_R8169_VLAN
1957 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
1958#endif
1959#ifdef CONFIG_NET_POLL_CONTROLLER
1960 .ndo_poll_controller = rtl8169_netpoll,
1961#endif
1962
1963};
1964
1da177e4 1965static int __devinit
4ff96fa6 1966rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1967{
0e485150
FR		 1968 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1969 const unsigned int region = cfg->region;
1da177e4 1970 struct rtl8169_private *tp;
ccdffb9a 1971 struct mii_if_info *mii;
4ff96fa6
FR		 1972 struct net_device *dev;
1973 void __iomem *ioaddr;
07d3f51f
FR		 1974 unsigned int i;
1975 int rc;
1da177e4 1976
4ff96fa6
FR		 1977 if (netif_msg_drv(&debug)) {
1978 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1979 MODULENAME, RTL8169_VERSION);
1980 }
1da177e4 1981
1da177e4 1982 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 1983 if (!dev) {
b57b7e5a 1984 if (netif_msg_drv(&debug))
9b91cf9d 1985 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 1986 rc = -ENOMEM;
1987 goto out;
1da177e4
LT		 1988 }
1989
1da177e4 1990 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 1991 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 1992 tp = netdev_priv(dev);
c4028958 1993 tp->dev = dev;
21e197f2 1994 tp->pci_dev = pdev;
b57b7e5a 1995 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 1996
ccdffb9a
FR		 1997 mii = &tp->mii;
1998 mii->dev = dev;
1999 mii->mdio_read = rtl_mdio_read;
2000 mii->mdio_write = rtl_mdio_write;
2001 mii->phy_id_mask = 0x1f;
2002 mii->reg_num_mask = 0x1f;
2003 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
2004
1da177e4
LT		 2005 /* enable device (incl. PCI PM wakeup and hotplug setup) */
2006 rc = pci_enable_device(pdev);
b57b7e5a 2007 if (rc < 0) {
2e8a538d 2008 if (netif_msg_probe(tp))
9b91cf9d 2009 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 2010 goto err_out_free_dev_1;
1da177e4
LT		 2011 }
2012
2013 rc = pci_set_mwi(pdev);
2014 if (rc < 0)
4ff96fa6 2015 goto err_out_disable_2;
1da177e4 2016
1da177e4 2017 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 2018 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 2019 if (netif_msg_probe(tp)) {
9b91cf9d 2020 dev_err(&pdev->dev,
bcf0bf90
FR		 2021 "region #%d not an MMIO resource, aborting\n",
2022 region);
4ff96fa6 2023 }
1da177e4 2024 rc = -ENODEV;
4ff96fa6 2025 goto err_out_mwi_3;
1da177e4 2026 }
4ff96fa6 2027
1da177e4 2028 /* check for weird/broken PCI region reporting */
bcf0bf90 2029 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 2030 if (netif_msg_probe(tp)) {
9b91cf9d 2031 dev_err(&pdev->dev,
4ff96fa6
FR		 2032 "Invalid PCI region size(s), aborting\n");
2033 }
1da177e4 2034 rc = -ENODEV;
4ff96fa6 2035 goto err_out_mwi_3;
1da177e4
LT		 2036 }
2037
2038 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 2039 if (rc < 0) {
2e8a538d 2040 if (netif_msg_probe(tp))
9b91cf9d 2041 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 2042 goto err_out_mwi_3;
1da177e4
LT		 2043 }
2044
2045 tp->cp_cmd = PCIMulRW | RxChkSum;
2046
2047 if ((sizeof(dma_addr_t) > 4) &&
6a35528a 2048 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 2049 tp->cp_cmd |= PCIDAC;
2050 dev->features |= NETIF_F_HIGHDMA;
2051 } else {
284901a9 2052 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 2053 if (rc < 0) {
4ff96fa6 2054 if (netif_msg_probe(tp)) {
9b91cf9d 2055 dev_err(&pdev->dev,
4ff96fa6
FR		 2056 "DMA configuration failed.\n");
2057 }
2058 goto err_out_free_res_4;
1da177e4
LT		 2059 }
2060 }
2061
2062 pci_set_master(pdev);
2063
2064 /* ioremap MMIO region */
bcf0bf90 2065 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 2066 if (!ioaddr) {
b57b7e5a 2067 if (netif_msg_probe(tp))
9b91cf9d 2068 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 2069 rc = -EIO;
4ff96fa6 2070 goto err_out_free_res_4;
1da177e4
LT		 2071 }
2072
9c14ceaf
FR		 2073 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2074 if (!tp->pcie_cap && netif_msg_probe(tp))
2075 dev_info(&pdev->dev, "no PCI Express capability\n");
2076
d78ad8cb 2077 RTL_W16(IntrMask, 0x0000);
1da177e4
LT		 2078
2079 /* Soft reset the chip. */
2080 RTL_W8(ChipCmd, CmdReset);
2081
2082 /* Check that the chip has finished the reset. */
07d3f51f 2083 for (i = 0; i < 100; i++) {
1da177e4
LT		 2084 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2085 break;
b518fa8e 2086 msleep_interruptible(1);
1da177e4
LT		 2087 }
2088
d78ad8cb
KW		 2089 RTL_W16(IntrStatus, 0xffff);
2090
1da177e4
LT		 2091 /* Identify chip attached to board */
2092 rtl8169_get_mac_version(tp, ioaddr);
1da177e4
LT		 2093
2094 rtl8169_print_mac_version(tp);
1da177e4 2095
cee60c37 2096 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 2097 if (tp->mac_version == rtl_chip_info[i].mac_version)
2098 break;
2099 }
cee60c37 2100 if (i == ARRAY_SIZE(rtl_chip_info)) {
1da177e4 2101 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 2102 if (netif_msg_probe(tp)) {
2e8a538d 2103 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 2104 "unknown chip version, assuming %s\n",
2105 rtl_chip_info[0].name);
b57b7e5a 2106 }
cee60c37 2107 i = 0;
1da177e4
LT		 2108 }
2109 tp->chipset = i;
2110
5d06a99f
FR		 2111 RTL_W8(Cfg9346, Cfg9346_Unlock);
2112 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2113 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 2114 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2115 tp->features |= RTL_FEATURE_WOL;
2116 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2117 tp->features |= RTL_FEATURE_WOL;
fbac58fc 2118 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 2119 RTL_W8(Cfg9346, Cfg9346_Lock);
2120
66ec5d4f
FR		 2121 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2122 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 2123 tp->set_speed = rtl8169_set_speed_tbi;
2124 tp->get_settings = rtl8169_gset_tbi;
2125 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2126 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2127 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 2128 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4 2129
64e4bfb4 2130 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 2131 } else {
2132 tp->set_speed = rtl8169_set_speed_xmii;
2133 tp->get_settings = rtl8169_gset_xmii;
2134 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2135 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2136 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 2137 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 2138 }
2139
df58ef51
FR		 2140 spin_lock_init(&tp->lock);
2141
738e1e69
PV		 2142 tp->mmio_addr = ioaddr;
2143
7bf6bf48 2144 /* Get MAC address */
1da177e4
LT		 2145 for (i = 0; i < MAC_ADDR_LEN; i++)
2146 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 2147 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 2148
1da177e4 2149 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 2150 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2151 dev->irq = pdev->irq;
2152 dev->base_addr = (unsigned long) ioaddr;
1da177e4 2153
bea3348e 2154 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 2155
2156#ifdef CONFIG_R8169_VLAN
2157 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 2158#endif
2159
2160 tp->intr_mask = 0xffff;
0e485150
FR		 2161 tp->align = cfg->align;
2162 tp->hw_start = cfg->hw_start;
2163 tp->intr_event = cfg->intr_event;
2164 tp->napi_event = cfg->napi_event;
1da177e4 2165
2efa53f3
FR		 2166 init_timer(&tp->timer);
2167 tp->timer.data = (unsigned long) dev;
2168 tp->timer.function = rtl8169_phy_timer;
2169
1da177e4 2170 rc = register_netdev(dev);
4ff96fa6 2171 if (rc < 0)
fbac58fc 2172 goto err_out_msi_5;
1da177e4
LT		 2173
2174 pci_set_drvdata(pdev, dev);
2175
b57b7e5a 2176 if (netif_msg_probe(tp)) {
96b9709c
FR		 2177 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
2178
b57b7e5a
SH		 2179 printk(KERN_INFO "%s: %s at 0x%lx, "
2180 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
96b9709c 2181 "XID %08x IRQ %d\n",
b57b7e5a 2182 dev->name,
bcf0bf90 2183 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 2184 dev->base_addr,
2185 dev->dev_addr[0], dev->dev_addr[1],
2186 dev->dev_addr[2], dev->dev_addr[3],
96b9709c 2187 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
b57b7e5a 2188 }
1da177e4 2189
4ff96fa6 2190 rtl8169_init_phy(dev, tp);
8b76ab39 2191 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 2192
4ff96fa6
FR		 2193out:
2194 return rc;
1da177e4 2195
fbac58fc
FR		 2196err_out_msi_5:
2197 rtl_disable_msi(pdev, tp);
4ff96fa6
FR		 2198 iounmap(ioaddr);
2199err_out_free_res_4:
2200 pci_release_regions(pdev);
2201err_out_mwi_3:
2202 pci_clear_mwi(pdev);
2203err_out_disable_2:
2204 pci_disable_device(pdev);
2205err_out_free_dev_1:
2206 free_netdev(dev);
2207 goto out;
1da177e4
LT		 2208}
2209
07d3f51f 2210static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 2211{
2212 struct net_device *dev = pci_get_drvdata(pdev);
2213 struct rtl8169_private *tp = netdev_priv(dev);
2214
eb2a021c
FR		 2215 flush_scheduled_work();
2216
1da177e4 2217 unregister_netdev(dev);
fbac58fc 2218 rtl_disable_msi(pdev, tp);
1da177e4
LT		 2219 rtl8169_release_board(pdev, dev, tp->mmio_addr);
2220 pci_set_drvdata(pdev, NULL);
2221}
2222
1da177e4
LT		 2223static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2224 struct net_device *dev)
2225{
2226 unsigned int mtu = dev->mtu;
2227
2228 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2229}
2230
2231static int rtl8169_open(struct net_device *dev)
2232{
2233 struct rtl8169_private *tp = netdev_priv(dev);
2234 struct pci_dev *pdev = tp->pci_dev;
99f252b0 2235 int retval = -ENOMEM;
1da177e4 2236
1da177e4 2237
99f252b0 2238 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 2239
2240 /*
2241 * Rx and Tx desscriptors needs 256 bytes alignment.
2242 * pci_alloc_consistent provides more.
2243 */
2244 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2245 &tp->TxPhyAddr);
2246 if (!tp->TxDescArray)
99f252b0 2247 goto out;
1da177e4
LT		 2248
2249 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2250 &tp->RxPhyAddr);
2251 if (!tp->RxDescArray)
99f252b0 2252 goto err_free_tx_0;
1da177e4
LT		 2253
2254 retval = rtl8169_init_ring(dev);
2255 if (retval < 0)
99f252b0 2256 goto err_free_rx_1;
1da177e4 2257
c4028958 2258 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 2259
99f252b0
FR		 2260 smp_mb();
2261
fbac58fc
FR		 2262 retval = request_irq(dev->irq, rtl8169_interrupt,
2263 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 2264 dev->name, dev);
2265 if (retval < 0)
2266 goto err_release_ring_2;
2267
bea3348e 2268 napi_enable(&tp->napi);
bea3348e 2269
07ce4064 2270 rtl_hw_start(dev);
1da177e4
LT		 2271
2272 rtl8169_request_timer(dev);
2273
2274 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2275out:
2276 return retval;
2277
99f252b0
FR		 2278err_release_ring_2:
2279 rtl8169_rx_clear(tp);
2280err_free_rx_1:
1da177e4
LT		 2281 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2282 tp->RxPhyAddr);
99f252b0 2283err_free_tx_0:
1da177e4
LT		 2284 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2285 tp->TxPhyAddr);
1da177e4
LT		 2286 goto out;
2287}
2288
2289static void rtl8169_hw_reset(void __iomem *ioaddr)
2290{
2291 /* Disable interrupts */
2292 rtl8169_irq_mask_and_ack(ioaddr);
2293
2294 /* Reset the chipset */
2295 RTL_W8(ChipCmd, CmdReset);
2296
2297 /* PCI commit */
2298 RTL_R8(ChipCmd);
2299}
2300
7f796d83 2301static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 2302{
2303 void __iomem *ioaddr = tp->mmio_addr;
2304 u32 cfg = rtl8169_rx_config;
2305
2306 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2307 RTL_W32(RxConfig, cfg);
2308
2309 /* Set DMA burst size and Interframe Gap Time */
2310 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2311 (InterFrameGap << TxInterFrameGapShift));
2312}
2313
07ce4064 2314static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 2315{
2316 struct rtl8169_private *tp = netdev_priv(dev);
2317 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 2318 unsigned int i;
1da177e4
LT		 2319
2320 /* Soft reset the chip. */
2321 RTL_W8(ChipCmd, CmdReset);
2322
2323 /* Check that the chip has finished the reset. */
07d3f51f 2324 for (i = 0; i < 100; i++) {
1da177e4
LT		 2325 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2326 break;
b518fa8e 2327 msleep_interruptible(1);
1da177e4
LT		 2328 }
2329
07ce4064
FR		 2330 tp->hw_start(dev);
2331
07ce4064
FR		 2332 netif_start_queue(dev);
2333}
2334
2335
7f796d83
FR		 2336static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2337 void __iomem *ioaddr)
2338{
2339 /*
2340 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2341 * register to be written before TxDescAddrLow to work.
2342 * Switching from MMIO to I/O access fixes the issue as well.
2343 */
2344 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 2345 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 2346 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 2347 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 2348}
2349
2350static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2351{
2352 u16 cmd;
2353
2354 cmd = RTL_R16(CPlusCmd);
2355 RTL_W16(CPlusCmd, cmd);
2356 return cmd;
2357}
2358
fdd7b4c3 2359static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 2360{
2361 /* Low hurts. Let's disable the filtering. */
fdd7b4c3 2362 RTL_W16(RxMaxSize, rx_buf_sz);
7f796d83
FR		 2363}
2364
6dccd16b
FR		 2365static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2366{
2367 struct {
2368 u32 mac_version;
2369 u32 clk;
2370 u32 val;
2371 } cfg2_info [] = {
2372 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2373 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2374 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2375 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2376 }, *p = cfg2_info;
2377 unsigned int i;
2378 u32 clk;
2379
2380 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 2381 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 2382 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2383 RTL_W32(0x7c, p->val);
2384 break;
2385 }
2386 }
2387}
2388
07ce4064
FR		 2389static void rtl_hw_start_8169(struct net_device *dev)
2390{
2391 struct rtl8169_private *tp = netdev_priv(dev);
2392 void __iomem *ioaddr = tp->mmio_addr;
2393 struct pci_dev *pdev = tp->pci_dev;
07ce4064 2394
9cb427b6
FR		 2395 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2396 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2397 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2398 }
2399
1da177e4 2400 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 2401 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2402 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2403 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2404 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2405 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2406
1da177e4
LT		 2407 RTL_W8(EarlyTxThres, EarlyTxThld);
2408
fdd7b4c3 2409 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
1da177e4 2410
c946b304
FR		 2411 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2412 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2413 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2414 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2415 rtl_set_rx_tx_config_registers(tp);
1da177e4 2416
7f796d83 2417 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 2418
bcf0bf90
FR		 2419 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2420 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 2421 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 2422 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 2423 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 2424 }
2425
bcf0bf90
FR		 2426 RTL_W16(CPlusCmd, tp->cp_cmd);
2427
6dccd16b
FR		 2428 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2429
1da177e4
LT		 2430 /*
2431 * Undocumented corner. Supposedly:
2432 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2433 */
2434 RTL_W16(IntrMitigate, 0x0000);
2435
7f796d83 2436 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 2437
c946b304
FR		 2438 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2439 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2440 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2441 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2442 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2443 rtl_set_rx_tx_config_registers(tp);
2444 }
2445
1da177e4 2446 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 2447
2448 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2449 RTL_R8(IntrMask);
1da177e4
LT		 2450
2451 RTL_W32(RxMissed, 0);
2452
07ce4064 2453 rtl_set_rx_mode(dev);
1da177e4
LT		 2454
2455 /* no early-rx interrupts */
2456 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 2457
2458 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 2459 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2460}
1da177e4 2461
9c14ceaf 2462static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 2463{
9c14ceaf
FR		 2464 struct net_device *dev = pci_get_drvdata(pdev);
2465 struct rtl8169_private *tp = netdev_priv(dev);
2466 int cap = tp->pcie_cap;
2467
2468 if (cap) {
2469 u16 ctl;
458a9f61 2470
9c14ceaf
FR		 2471 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2472 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2473 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2474 }
458a9f61
FR		 2475}
2476
dacf8154
FR		 2477static void rtl_csi_access_enable(void __iomem *ioaddr)
2478{
2479 u32 csi;
2480
2481 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2482 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2483}
2484
2485struct ephy_info {
2486 unsigned int offset;
2487 u16 mask;
2488 u16 bits;
2489};
2490
2491static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2492{
2493 u16 w;
2494
2495 while (len-- > 0) {
2496 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2497 rtl_ephy_write(ioaddr, e->offset, w);
2498 e++;
2499 }
2500}
2501
b726e493
FR		 2502static void rtl_disable_clock_request(struct pci_dev *pdev)
2503{
2504 struct net_device *dev = pci_get_drvdata(pdev);
2505 struct rtl8169_private *tp = netdev_priv(dev);
2506 int cap = tp->pcie_cap;
2507
2508 if (cap) {
2509 u16 ctl;
2510
2511 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
2512 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
2513 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
2514 }
2515}
2516
2517#define R8168_CPCMD_QUIRK_MASK (\
2518 EnableBist | \
2519 Mac_dbgo_oe | \
2520 Force_half_dup | \
2521 Force_rxflow_en | \
2522 Force_txflow_en | \
2523 Cxpl_dbg_sel | \
2524 ASF | \
2525 PktCntrDisable | \
2526 Mac_dbgo_sel)
2527
219a1e9d
FR		 2528static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
2529{
b726e493
FR		 2530 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2531
2532 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2533
2e68ae44
FR		 2534 rtl_tx_performance_tweak(pdev,
2535 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 2536}
2537
2538static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
2539{
2540 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493
FR		 2541
2542 RTL_W8(EarlyTxThres, EarlyTxThld);
2543
2544 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 2545}
2546
2547static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2548{
b726e493
FR		 2549 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
2550
2551 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2552
219a1e9d 2553 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 2554
2555 rtl_disable_clock_request(pdev);
2556
2557 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 2558}
2559
ef3386f0 2560static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 2561{
b726e493
FR		 2562 static struct ephy_info e_info_8168cp[] = {
2563 { 0x01, 0, 0x0001 },
2564 { 0x02, 0x0800, 0x1000 },
2565 { 0x03, 0, 0x0042 },
2566 { 0x06, 0x0080, 0x0000 },
2567 { 0x07, 0, 0x2000 }
2568 };
2569
2570 rtl_csi_access_enable(ioaddr);
2571
2572 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
2573
219a1e9d
FR		 2574 __rtl_hw_start_8168cp(ioaddr, pdev);
2575}
2576
ef3386f0
FR		 2577static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
2578{
2579 rtl_csi_access_enable(ioaddr);
2580
2581 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2582
2583 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2584
2585 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2586}
2587
7f3e3d3a
FR		 2588static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
2589{
2590 rtl_csi_access_enable(ioaddr);
2591
2592 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2593
2594 /* Magic. */
2595 RTL_W8(DBG_REG, 0x20);
2596
2597 RTL_W8(EarlyTxThres, EarlyTxThld);
2598
2599 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2600
2601 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2602}
2603
219a1e9d
FR		 2604static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
2605{
b726e493
FR		 2606 static struct ephy_info e_info_8168c_1[] = {
2607 { 0x02, 0x0800, 0x1000 },
2608 { 0x03, 0, 0x0002 },
2609 { 0x06, 0x0080, 0x0000 }
2610 };
2611
2612 rtl_csi_access_enable(ioaddr);
2613
2614 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2615
2616 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
2617
219a1e9d
FR		 2618 __rtl_hw_start_8168cp(ioaddr, pdev);
2619}
2620
2621static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
2622{
b726e493
FR		 2623 static struct ephy_info e_info_8168c_2[] = {
2624 { 0x01, 0, 0x0001 },
2625 { 0x03, 0x0400, 0x0220 }
2626 };
2627
2628 rtl_csi_access_enable(ioaddr);
2629
2630 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
2631
219a1e9d
FR		 2632 __rtl_hw_start_8168cp(ioaddr, pdev);
2633}
2634
197ff761
FR		 2635static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
2636{
2637 rtl_hw_start_8168c_2(ioaddr, pdev);
2638}
2639
6fb07058
FR		 2640static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
2641{
2642 rtl_csi_access_enable(ioaddr);
2643
2644 __rtl_hw_start_8168cp(ioaddr, pdev);
2645}
2646
5b538df9
FR		 2647static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
2648{
2649 rtl_csi_access_enable(ioaddr);
2650
2651 rtl_disable_clock_request(pdev);
2652
2653 RTL_W8(EarlyTxThres, EarlyTxThld);
2654
2655 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2656
2657 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2658}
2659
07ce4064
FR		 2660static void rtl_hw_start_8168(struct net_device *dev)
2661{
2dd99530
FR		 2662 struct rtl8169_private *tp = netdev_priv(dev);
2663 void __iomem *ioaddr = tp->mmio_addr;
0e485150 2664 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 2665
2666 RTL_W8(Cfg9346, Cfg9346_Unlock);
2667
2668 RTL_W8(EarlyTxThres, EarlyTxThld);
2669
fdd7b4c3 2670 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
2dd99530 2671
0e485150 2672 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 2673
2674 RTL_W16(CPlusCmd, tp->cp_cmd);
2675
0e485150 2676 RTL_W16(IntrMitigate, 0x5151);
2dd99530 2677
0e485150
FR		 2678 /* Work around for RxFIFO overflow. */
2679 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2680 tp->intr_event |= RxFIFOOver | PCSTimeout;
2681 tp->intr_event &= ~RxOverflow;
2682 }
2683
2684 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 2685
b8363901
FR		 2686 rtl_set_rx_mode(dev);
2687
2688 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2689 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 2690
2691 RTL_R8(IntrMask);
2692
219a1e9d
FR		 2693 switch (tp->mac_version) {
2694 case RTL_GIGA_MAC_VER_11:
2695 rtl_hw_start_8168bb(ioaddr, pdev);
2696 break;
2697
2698 case RTL_GIGA_MAC_VER_12:
2699 case RTL_GIGA_MAC_VER_17:
2700 rtl_hw_start_8168bef(ioaddr, pdev);
2701 break;
2702
2703 case RTL_GIGA_MAC_VER_18:
ef3386f0 2704 rtl_hw_start_8168cp_1(ioaddr, pdev);
219a1e9d
FR		 2705 break;
2706
2707 case RTL_GIGA_MAC_VER_19:
2708 rtl_hw_start_8168c_1(ioaddr, pdev);
2709 break;
2710
2711 case RTL_GIGA_MAC_VER_20:
2712 rtl_hw_start_8168c_2(ioaddr, pdev);
2713 break;
2714
197ff761
FR		 2715 case RTL_GIGA_MAC_VER_21:
2716 rtl_hw_start_8168c_3(ioaddr, pdev);
2717 break;
2718
6fb07058
FR		 2719 case RTL_GIGA_MAC_VER_22:
2720 rtl_hw_start_8168c_4(ioaddr, pdev);
2721 break;
2722
ef3386f0
FR		 2723 case RTL_GIGA_MAC_VER_23:
2724 rtl_hw_start_8168cp_2(ioaddr, pdev);
2725 break;
2726
7f3e3d3a
FR		 2727 case RTL_GIGA_MAC_VER_24:
2728 rtl_hw_start_8168cp_3(ioaddr, pdev);
2729 break;
2730
5b538df9
FR		 2731 case RTL_GIGA_MAC_VER_25:
2732 rtl_hw_start_8168d(ioaddr, pdev);
2733 break;
2734
219a1e9d
FR		 2735 default:
2736 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
2737 dev->name, tp->mac_version);
2738 break;
2739 }
2dd99530 2740
0e485150
FR		 2741 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2742
b8363901
FR		 2743 RTL_W8(Cfg9346, Cfg9346_Lock);
2744
2dd99530 2745 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 2746
0e485150 2747 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2748}
1da177e4 2749
2857ffb7
FR		 2750#define R810X_CPCMD_QUIRK_MASK (\
2751 EnableBist | \
2752 Mac_dbgo_oe | \
2753 Force_half_dup | \
2754 Force_half_dup | \
2755 Force_txflow_en | \
2756 Cxpl_dbg_sel | \
2757 ASF | \
2758 PktCntrDisable | \
2759 PCIDAC | \
2760 PCIMulRW)
2761
2762static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2763{
2764 static struct ephy_info e_info_8102e_1[] = {
2765 { 0x01, 0, 0x6e65 },
2766 { 0x02, 0, 0x091f },
2767 { 0x03, 0, 0xc2f9 },
2768 { 0x06, 0, 0xafb5 },
2769 { 0x07, 0, 0x0e00 },
2770 { 0x19, 0, 0xec80 },
2771 { 0x01, 0, 0x2e65 },
2772 { 0x01, 0, 0x6e65 }
2773 };
2774 u8 cfg1;
2775
2776 rtl_csi_access_enable(ioaddr);
2777
2778 RTL_W8(DBG_REG, FIX_NAK_1);
2779
2780 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2781
2782 RTL_W8(Config1,
2783 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2784 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2785
2786 cfg1 = RTL_R8(Config1);
2787 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2788 RTL_W8(Config1, cfg1 & ~LEDS0);
2789
2790 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2791
2792 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2793}
2794
2795static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2796{
2797 rtl_csi_access_enable(ioaddr);
2798
2799 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2800
2801 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2802 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2803
2804 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2805}
2806
2807static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2808{
2809 rtl_hw_start_8102e_2(ioaddr, pdev);
2810
2811 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2812}
2813
07ce4064
FR		 2814static void rtl_hw_start_8101(struct net_device *dev)
2815{
cdf1a608
FR		 2816 struct rtl8169_private *tp = netdev_priv(dev);
2817 void __iomem *ioaddr = tp->mmio_addr;
2818 struct pci_dev *pdev = tp->pci_dev;
2819
e3cf0cc0
FR		 2820 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2821 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 2822 int cap = tp->pcie_cap;
2823
2824 if (cap) {
2825 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2826 PCI_EXP_DEVCTL_NOSNOOP_EN);
2827 }
cdf1a608
FR		 2828 }
2829
2857ffb7
FR		 2830 switch (tp->mac_version) {
2831 case RTL_GIGA_MAC_VER_07:
2832 rtl_hw_start_8102e_1(ioaddr, pdev);
2833 break;
2834
2835 case RTL_GIGA_MAC_VER_08:
2836 rtl_hw_start_8102e_3(ioaddr, pdev);
2837 break;
2838
2839 case RTL_GIGA_MAC_VER_09:
2840 rtl_hw_start_8102e_2(ioaddr, pdev);
2841 break;
cdf1a608
FR		 2842 }
2843
2844 RTL_W8(Cfg9346, Cfg9346_Unlock);
2845
2846 RTL_W8(EarlyTxThres, EarlyTxThld);
2847
fdd7b4c3 2848 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
cdf1a608
FR		 2849
2850 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2851
2852 RTL_W16(CPlusCmd, tp->cp_cmd);
2853
2854 RTL_W16(IntrMitigate, 0x0000);
2855
2856 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2857
2858 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2859 rtl_set_rx_tx_config_registers(tp);
2860
2861 RTL_W8(Cfg9346, Cfg9346_Lock);
2862
2863 RTL_R8(IntrMask);
2864
cdf1a608
FR		 2865 rtl_set_rx_mode(dev);
2866
0e485150
FR		 2867 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2868
cdf1a608 2869 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 2870
0e485150 2871 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2872}
2873
2874static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2875{
2876 struct rtl8169_private *tp = netdev_priv(dev);
2877 int ret = 0;
2878
2879 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2880 return -EINVAL;
2881
2882 dev->mtu = new_mtu;
2883
2884 if (!netif_running(dev))
2885 goto out;
2886
2887 rtl8169_down(dev);
2888
2889 rtl8169_set_rxbufsize(tp, dev);
2890
2891 ret = rtl8169_init_ring(dev);
2892 if (ret < 0)
2893 goto out;
2894
bea3348e 2895 napi_enable(&tp->napi);
1da177e4 2896
07ce4064 2897 rtl_hw_start(dev);
1da177e4
LT		 2898
2899 rtl8169_request_timer(dev);
2900
2901out:
2902 return ret;
2903}
2904
2905static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2906{
95e0918d 2907 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 2908 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2909}
2910
2911static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2912 struct sk_buff **sk_buff, struct RxDesc *desc)
2913{
2914 struct pci_dev *pdev = tp->pci_dev;
2915
2916 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2917 PCI_DMA_FROMDEVICE);
2918 dev_kfree_skb(*sk_buff);
2919 *sk_buff = NULL;
2920 rtl8169_make_unusable_by_asic(desc);
2921}
2922
2923static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2924{
2925 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2926
2927 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2928}
2929
2930static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2931 u32 rx_buf_sz)
2932{
2933 desc->addr = cpu_to_le64(mapping);
2934 wmb();
2935 rtl8169_mark_to_asic(desc, rx_buf_sz);
2936}
2937
15d31758
SH		 2938static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2939 struct net_device *dev,
2940 struct RxDesc *desc, int rx_buf_sz,
2941 unsigned int align)
1da177e4
LT		 2942{
2943 struct sk_buff *skb;
2944 dma_addr_t mapping;
e9f63f30 2945 unsigned int pad;
1da177e4 2946
e9f63f30
FR		 2947 pad = align ? align : NET_IP_ALIGN;
2948
2949 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 2950 if (!skb)
2951 goto err_out;
2952
e9f63f30 2953 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 2954
689be439 2955 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 2956 PCI_DMA_FROMDEVICE);
2957
2958 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 2959out:
15d31758 2960 return skb;
1da177e4
LT		 2961
2962err_out:
1da177e4
LT		 2963 rtl8169_make_unusable_by_asic(desc);
2964 goto out;
2965}
2966
2967static void rtl8169_rx_clear(struct rtl8169_private *tp)
2968{
07d3f51f 2969 unsigned int i;
1da177e4
LT		 2970
2971 for (i = 0; i < NUM_RX_DESC; i++) {
2972 if (tp->Rx_skbuff[i]) {
2973 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2974 tp->RxDescArray + i);
2975 }
2976 }
2977}
2978
2979static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2980 u32 start, u32 end)
2981{
2982 u32 cur;
5b0384f4 2983
4ae47c2d 2984 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 2985 struct sk_buff *skb;
2986 unsigned int i = cur % NUM_RX_DESC;
1da177e4 2987
4ae47c2d
FR		 2988 WARN_ON((s32)(end - cur) < 0);
2989
1da177e4
LT		 2990 if (tp->Rx_skbuff[i])
2991 continue;
bcf0bf90 2992
15d31758
SH		 2993 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2994 tp->RxDescArray + i,
2995 tp->rx_buf_sz, tp->align);
2996 if (!skb)
1da177e4 2997 break;
15d31758
SH		 2998
2999 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 3000 }
3001 return cur - start;
3002}
3003
3004static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
3005{
3006 desc->opts1 |= cpu_to_le32(RingEnd);
3007}
3008
3009static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3010{
3011 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3012}
3013
3014static int rtl8169_init_ring(struct net_device *dev)
3015{
3016 struct rtl8169_private *tp = netdev_priv(dev);
3017
3018 rtl8169_init_ring_indexes(tp);
3019
3020 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
3021 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
3022
3023 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
3024 goto err_out;
3025
3026 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3027
3028 return 0;
3029
3030err_out:
3031 rtl8169_rx_clear(tp);
3032 return -ENOMEM;
3033}
3034
3035static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
3036 struct TxDesc *desc)
3037{
3038 unsigned int len = tx_skb->len;
3039
3040 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
3041 desc->opts1 = 0x00;
3042 desc->opts2 = 0x00;
3043 desc->addr = 0x00;
3044 tx_skb->len = 0;
3045}
3046
3047static void rtl8169_tx_clear(struct rtl8169_private *tp)
3048{
3049 unsigned int i;
3050
3051 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
3052 unsigned int entry = i % NUM_TX_DESC;
3053 struct ring_info *tx_skb = tp->tx_skb + entry;
3054 unsigned int len = tx_skb->len;
3055
3056 if (len) {
3057 struct sk_buff *skb = tx_skb->skb;
3058
3059 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
3060 tp->TxDescArray + entry);
3061 if (skb) {
3062 dev_kfree_skb(skb);
3063 tx_skb->skb = NULL;
3064 }
cebf8cc7 3065 tp->dev->stats.tx_dropped++;
1da177e4
LT		 3066 }
3067 }
3068 tp->cur_tx = tp->dirty_tx = 0;
3069}
3070
c4028958 3071static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 3072{
3073 struct rtl8169_private *tp = netdev_priv(dev);
3074
c4028958 3075 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 3076 schedule_delayed_work(&tp->task, 4);
3077}
3078
3079static void rtl8169_wait_for_quiescence(struct net_device *dev)
3080{
3081 struct rtl8169_private *tp = netdev_priv(dev);
3082 void __iomem *ioaddr = tp->mmio_addr;
3083
3084 synchronize_irq(dev->irq);
3085
3086 /* Wait for any pending NAPI task to complete */
bea3348e 3087 napi_disable(&tp->napi);
1da177e4
LT		 3088
3089 rtl8169_irq_mask_and_ack(ioaddr);
3090
d1d08d12
DM		 3091 tp->intr_mask = 0xffff;
3092 RTL_W16(IntrMask, tp->intr_event);
bea3348e 3093 napi_enable(&tp->napi);
1da177e4
LT		 3094}
3095
c4028958 3096static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 3097{
c4028958
DH		 3098 struct rtl8169_private *tp =
3099 container_of(work, struct rtl8169_private, task.work);
3100 struct net_device *dev = tp->dev;
1da177e4
LT		 3101 int ret;
3102
eb2a021c
FR		 3103 rtnl_lock();
3104
3105 if (!netif_running(dev))
3106 goto out_unlock;
3107
3108 rtl8169_wait_for_quiescence(dev);
3109 rtl8169_close(dev);
1da177e4
LT		 3110
3111 ret = rtl8169_open(dev);
3112 if (unlikely(ret < 0)) {
07d3f51f 3113 if (net_ratelimit() && netif_msg_drv(tp)) {
53edbecd 3114 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
07d3f51f 3115 " Rescheduling.\n", dev->name, ret);
1da177e4
LT		 3116 }
3117 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3118 }
eb2a021c
FR		 3119
3120out_unlock:
3121 rtnl_unlock();
1da177e4
LT		 3122}
3123
c4028958 3124static void rtl8169_reset_task(struct work_struct *work)
1da177e4 3125{
c4028958
DH		 3126 struct rtl8169_private *tp =
3127 container_of(work, struct rtl8169_private, task.work);
3128 struct net_device *dev = tp->dev;
1da177e4 3129
eb2a021c
FR		 3130 rtnl_lock();
3131
1da177e4 3132 if (!netif_running(dev))
eb2a021c 3133 goto out_unlock;
1da177e4
LT		 3134
3135 rtl8169_wait_for_quiescence(dev);
3136
bea3348e 3137 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 3138 rtl8169_tx_clear(tp);
3139
3140 if (tp->dirty_rx == tp->cur_rx) {
3141 rtl8169_init_ring_indexes(tp);
07ce4064 3142 rtl_hw_start(dev);
1da177e4 3143 netif_wake_queue(dev);
cebf8cc7 3144 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 3145 } else {
07d3f51f 3146 if (net_ratelimit() && netif_msg_intr(tp)) {
53edbecd 3147 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
07d3f51f 3148 dev->name);
1da177e4
LT		 3149 }
3150 rtl8169_schedule_work(dev, rtl8169_reset_task);
3151 }
eb2a021c
FR		 3152
3153out_unlock:
3154 rtnl_unlock();
1da177e4
LT		 3155}
3156
3157static void rtl8169_tx_timeout(struct net_device *dev)
3158{
3159 struct rtl8169_private *tp = netdev_priv(dev);
3160
3161 rtl8169_hw_reset(tp->mmio_addr);
3162
3163 /* Let's wait a bit while any (async) irq lands on */
3164 rtl8169_schedule_work(dev, rtl8169_reset_task);
3165}
3166
3167static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3168 u32 opts1)
3169{
3170 struct skb_shared_info *info = skb_shinfo(skb);
3171 unsigned int cur_frag, entry;
a6343afb 3172 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 3173
3174 entry = tp->cur_tx;
3175 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3176 skb_frag_t *frag = info->frags + cur_frag;
3177 dma_addr_t mapping;
3178 u32 status, len;
3179 void *addr;
3180
3181 entry = (entry + 1) % NUM_TX_DESC;
3182
3183 txd = tp->TxDescArray + entry;
3184 len = frag->size;
3185 addr = ((void *) page_address(frag->page)) + frag->page_offset;
3186 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
3187
3188 /* anti gcc 2.95.3 bugware (sic) */
3189 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3190
3191 txd->opts1 = cpu_to_le32(status);
3192 txd->addr = cpu_to_le64(mapping);
3193
3194 tp->tx_skb[entry].len = len;
3195 }
3196
3197 if (cur_frag) {
3198 tp->tx_skb[entry].skb = skb;
3199 txd->opts1 |= cpu_to_le32(LastFrag);
3200 }
3201
3202 return cur_frag;
3203}
3204
3205static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
3206{
3207 if (dev->features & NETIF_F_TSO) {
7967168c 3208 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 3209
3210 if (mss)
3211 return LargeSend | ((mss & MSSMask) << MSSShift);
3212 }
84fa7933 3213 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 3214 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 3215
3216 if (ip->protocol == IPPROTO_TCP)
3217 return IPCS | TCPCS;
3218 else if (ip->protocol == IPPROTO_UDP)
3219 return IPCS | UDPCS;
3220 WARN_ON(1); /* we need a WARN() */
3221 }
3222 return 0;
3223}
3224
3225static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
3226{
3227 struct rtl8169_private *tp = netdev_priv(dev);
3228 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
3229 struct TxDesc *txd = tp->TxDescArray + entry;
3230 void __iomem *ioaddr = tp->mmio_addr;
3231 dma_addr_t mapping;
3232 u32 status, len;
3233 u32 opts1;
188f4af0 3234 int ret = NETDEV_TX_OK;
5b0384f4 3235
1da177e4 3236 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 3237 if (netif_msg_drv(tp)) {
3238 printk(KERN_ERR
3239 "%s: BUG! Tx Ring full when queue awake!\n",
3240 dev->name);
3241 }
1da177e4
LT		 3242 goto err_stop;
3243 }
3244
3245 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3246 goto err_stop;
3247
3248 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
3249
3250 frags = rtl8169_xmit_frags(tp, skb, opts1);
3251 if (frags) {
3252 len = skb_headlen(skb);
3253 opts1 |= FirstFrag;
3254 } else {
3255 len = skb->len;
1da177e4
LT		 3256 opts1 |= FirstFrag | LastFrag;
3257 tp->tx_skb[entry].skb = skb;
3258 }
3259
3260 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
3261
3262 tp->tx_skb[entry].len = len;
3263 txd->addr = cpu_to_le64(mapping);
3264 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
3265
3266 wmb();
3267
3268 /* anti gcc 2.95.3 bugware (sic) */
3269 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3270 txd->opts1 = cpu_to_le32(status);
3271
3272 dev->trans_start = jiffies;
3273
3274 tp->cur_tx += frags + 1;
3275
3276 smp_wmb();
3277
275391a4 3278 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 3279
3280 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
3281 netif_stop_queue(dev);
3282 smp_rmb();
3283 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
3284 netif_wake_queue(dev);
3285 }
3286
3287out:
3288 return ret;
3289
3290err_stop:
3291 netif_stop_queue(dev);
188f4af0 3292 ret = NETDEV_TX_BUSY;
cebf8cc7 3293 dev->stats.tx_dropped++;
1da177e4
LT		 3294 goto out;
3295}
3296
3297static void rtl8169_pcierr_interrupt(struct net_device *dev)
3298{
3299 struct rtl8169_private *tp = netdev_priv(dev);
3300 struct pci_dev *pdev = tp->pci_dev;
3301 void __iomem *ioaddr = tp->mmio_addr;
3302 u16 pci_status, pci_cmd;
3303
3304 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3305 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3306
b57b7e5a
SH		 3307 if (netif_msg_intr(tp)) {
3308 printk(KERN_ERR
3309 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3310 dev->name, pci_cmd, pci_status);
3311 }
1da177e4
LT		 3312
3313 /*
3314 * The recovery sequence below admits a very elaborated explanation:
3315 * - it seems to work;
d03902b8
FR		 3316 * - I did not see what else could be done;
3317 * - it makes iop3xx happy.
1da177e4
LT		 3318 *
3319 * Feel free to adjust to your needs.
3320 */
a27993f3 3321 if (pdev->broken_parity_status)
d03902b8
FR		 3322 pci_cmd &= ~PCI_COMMAND_PARITY;
3323 else
3324 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3325
3326 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 3327
3328 pci_write_config_word(pdev, PCI_STATUS,
3329 pci_status & (PCI_STATUS_DETECTED_PARITY |
3330 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3331 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3332
3333 /* The infamous DAC f*ckup only happens at boot time */
3334 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 3335 if (netif_msg_intr(tp))
3336 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 3337 tp->cp_cmd &= ~PCIDAC;
3338 RTL_W16(CPlusCmd, tp->cp_cmd);
3339 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 3340 }
3341
3342 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 3343
3344 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 3345}
3346
07d3f51f
FR		 3347static void rtl8169_tx_interrupt(struct net_device *dev,
3348 struct rtl8169_private *tp,
3349 void __iomem *ioaddr)
1da177e4
LT		 3350{
3351 unsigned int dirty_tx, tx_left;
3352
1da177e4
LT		 3353 dirty_tx = tp->dirty_tx;
3354 smp_rmb();
3355 tx_left = tp->cur_tx - dirty_tx;
3356
3357 while (tx_left > 0) {
3358 unsigned int entry = dirty_tx % NUM_TX_DESC;
3359 struct ring_info *tx_skb = tp->tx_skb + entry;
3360 u32 len = tx_skb->len;
3361 u32 status;
3362
3363 rmb();
3364 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3365 if (status & DescOwn)
3366 break;
3367
cebf8cc7
FR		 3368 dev->stats.tx_bytes += len;
3369 dev->stats.tx_packets++;
1da177e4
LT		 3370
3371 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3372
3373 if (status & LastFrag) {
3374 dev_kfree_skb_irq(tx_skb->skb);
3375 tx_skb->skb = NULL;
3376 }
3377 dirty_tx++;
3378 tx_left--;
3379 }
3380
3381 if (tp->dirty_tx != dirty_tx) {
3382 tp->dirty_tx = dirty_tx;
3383 smp_wmb();
3384 if (netif_queue_stopped(dev) &&
3385 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3386 netif_wake_queue(dev);
3387 }
d78ae2dc
FR		 3388 /*
3389 * 8168 hack: TxPoll requests are lost when the Tx packets are
3390 * too close. Let's kick an extra TxPoll request when a burst
3391 * of start_xmit activity is detected (if it is not detected,
3392 * it is slow enough). -- FR
3393 */
3394 smp_rmb();
3395 if (tp->cur_tx != dirty_tx)
3396 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 3397 }
3398}
3399
126fa4b9
FR		 3400static inline int rtl8169_fragmented_frame(u32 status)
3401{
3402 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3403}
3404
1da177e4
LT		 3405static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3406{
3407 u32 opts1 = le32_to_cpu(desc->opts1);
3408 u32 status = opts1 & RxProtoMask;
3409
3410 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3411 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3412 ((status == RxProtoIP) && !(opts1 & IPFail)))
3413 skb->ip_summed = CHECKSUM_UNNECESSARY;
3414 else
3415 skb->ip_summed = CHECKSUM_NONE;
3416}
3417
07d3f51f
FR		 3418static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3419 struct rtl8169_private *tp, int pkt_size,
3420 dma_addr_t addr)
1da177e4 3421{
b449655f
SH		 3422 struct sk_buff *skb;
3423 bool done = false;
1da177e4 3424
b449655f
SH		 3425 if (pkt_size >= rx_copybreak)
3426 goto out;
1da177e4 3427
07d3f51f 3428 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
b449655f
SH		 3429 if (!skb)
3430 goto out;
3431
07d3f51f
FR		 3432 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3433 PCI_DMA_FROMDEVICE);
86402234 3434 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 3435 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3436 *sk_buff = skb;
3437 done = true;
3438out:
3439 return done;
1da177e4
LT		 3440}
3441
07d3f51f
FR		 3442static int rtl8169_rx_interrupt(struct net_device *dev,
3443 struct rtl8169_private *tp,
bea3348e 3444 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 3445{
3446 unsigned int cur_rx, rx_left;
3447 unsigned int delta, count;
3448
1da177e4
LT		 3449 cur_rx = tp->cur_rx;
3450 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 3451 rx_left = min(rx_left, budget);
1da177e4 3452
4dcb7d33 3453 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 3454 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 3455 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 3456 u32 status;
3457
3458 rmb();
126fa4b9 3459 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 3460
3461 if (status & DescOwn)
3462 break;
4dcb7d33 3463 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 3464 if (netif_msg_rx_err(tp)) {
3465 printk(KERN_INFO
3466 "%s: Rx ERROR. status = %08x\n",
3467 dev->name, status);
3468 }
cebf8cc7 3469 dev->stats.rx_errors++;
1da177e4 3470 if (status & (RxRWT | RxRUNT))
cebf8cc7 3471 dev->stats.rx_length_errors++;
1da177e4 3472 if (status & RxCRC)
cebf8cc7 3473 dev->stats.rx_crc_errors++;
9dccf611
FR		 3474 if (status & RxFOVF) {
3475 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 3476 dev->stats.rx_fifo_errors++;
9dccf611 3477 }
126fa4b9 3478 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 3479 } else {
1da177e4 3480 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 3481 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 3482 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 3483 struct pci_dev *pdev = tp->pci_dev;
1da177e4 3484
126fa4b9
FR		 3485 /*
3486 * The driver does not support incoming fragmented
3487 * frames. They are seen as a symptom of over-mtu
3488 * sized frames.
3489 */
3490 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 3491 dev->stats.rx_dropped++;
3492 dev->stats.rx_length_errors++;
126fa4b9 3493 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 3494 continue;
126fa4b9
FR		 3495 }
3496
1da177e4 3497 rtl8169_rx_csum(skb, desc);
bcf0bf90 3498
07d3f51f 3499 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 3500 pci_dma_sync_single_for_device(pdev, addr,
3501 pkt_size, PCI_DMA_FROMDEVICE);
3502 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3503 } else {
a866bbf6 3504 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
b449655f 3505 PCI_DMA_FROMDEVICE);
1da177e4
LT		 3506 tp->Rx_skbuff[entry] = NULL;
3507 }
3508
1da177e4
LT		 3509 skb_put(skb, pkt_size);
3510 skb->protocol = eth_type_trans(skb, dev);
3511
3512 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
865c652d 3513 netif_receive_skb(skb);
1da177e4 3514
cebf8cc7
FR		 3515 dev->stats.rx_bytes += pkt_size;
3516 dev->stats.rx_packets++;
1da177e4 3517 }
6dccd16b
FR		 3518
3519 /* Work around for AMD plateform. */
95e0918d 3520 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 3521 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3522 desc->opts2 = 0;
3523 cur_rx++;
3524 }
1da177e4
LT		 3525 }
3526
3527 count = cur_rx - tp->cur_rx;
3528 tp->cur_rx = cur_rx;
3529
3530 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 3531 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 3532 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3533 tp->dirty_rx += delta;
3534
3535 /*
3536 * FIXME: until there is periodic timer to try and refill the ring,
3537 * a temporary shortage may definitely kill the Rx process.
3538 * - disable the asic to try and avoid an overflow and kick it again
3539 * after refill ?
3540 * - how do others driver handle this condition (Uh oh...).
3541 */
b57b7e5a 3542 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 3543 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3544
3545 return count;
3546}
3547
07d3f51f 3548static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 3549{
07d3f51f 3550 struct net_device *dev = dev_instance;
1da177e4 3551 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 3552 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3553 int handled = 0;
865c652d 3554 int status;
1da177e4 3555
f11a377b
DD		 3556 /* loop handling interrupts until we have no new ones or
3557 * we hit a invalid/hotplug case.
3558 */
865c652d 3559 status = RTL_R16(IntrStatus);
f11a377b
DD		 3560 while (status && status != 0xffff) {
3561 handled = 1;
1da177e4 3562
f11a377b
DD		 3563 /* Handle all of the error cases first. These will reset
3564 * the chip, so just exit the loop.
3565 */
3566 if (unlikely(!netif_running(dev))) {
3567 rtl8169_asic_down(ioaddr);
3568 break;
3569 }
1da177e4 3570
f11a377b
DD		 3571 /* Work around for rx fifo overflow */
3572 if (unlikely(status & RxFIFOOver) &&
3573 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3574 netif_stop_queue(dev);
3575 rtl8169_tx_timeout(dev);
3576 break;
3577 }
1da177e4 3578
f11a377b
DD		 3579 if (unlikely(status & SYSErr)) {
3580 rtl8169_pcierr_interrupt(dev);
3581 break;
3582 }
1da177e4 3583
f11a377b
DD		 3584 if (status & LinkChg)
3585 rtl8169_check_link_status(dev, tp, ioaddr);
0e485150 3586
f11a377b
DD		 3587 /* We need to see the lastest version of tp->intr_mask to
3588 * avoid ignoring an MSI interrupt and having to wait for
3589 * another event which may never come.
3590 */
3591 smp_rmb();
3592 if (status & tp->intr_mask & tp->napi_event) {
3593 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3594 tp->intr_mask = ~tp->napi_event;
3595
3596 if (likely(napi_schedule_prep(&tp->napi)))
3597 __napi_schedule(&tp->napi);
3598 else if (netif_msg_intr(tp)) {
3599 printk(KERN_INFO "%s: interrupt %04x in poll\n",
3600 dev->name, status);
3601 }
3602 }
1da177e4 3603
f11a377b
DD		 3604 /* We only get a new MSI interrupt when all active irq
3605 * sources on the chip have been acknowledged. So, ack
3606 * everything we've seen and check if new sources have become
3607 * active to avoid blocking all interrupts from the chip.
3608 */
3609 RTL_W16(IntrStatus,
3610 (status & RxFIFOOver) ? (status | RxOverflow) : status);
3611 status = RTL_R16(IntrStatus);
865c652d 3612 }
1da177e4 3613
1da177e4
LT		 3614 return IRQ_RETVAL(handled);
3615}
3616
bea3348e 3617static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 3618{
bea3348e
SH		 3619 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3620 struct net_device *dev = tp->dev;
1da177e4 3621 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 3622 int work_done;
1da177e4 3623
bea3348e 3624 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 3625 rtl8169_tx_interrupt(dev, tp, ioaddr);
3626
bea3348e 3627 if (work_done < budget) {
288379f0 3628 napi_complete(napi);
f11a377b
DD		 3629
3630 /* We need for force the visibility of tp->intr_mask
3631 * for other CPUs, as we can loose an MSI interrupt
3632 * and potentially wait for a retransmit timeout if we don't.
3633 * The posted write to IntrMask is safe, as it will
3634 * eventually make it to the chip and we won't loose anything
3635 * until it does.
1da177e4 3636 */
f11a377b 3637 tp->intr_mask = 0xffff;
1da177e4 3638 smp_wmb();
0e485150 3639 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3640 }
3641
bea3348e 3642 return work_done;
1da177e4 3643}
1da177e4 3644
523a6094
FR		 3645static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
3646{
3647 struct rtl8169_private *tp = netdev_priv(dev);
3648
3649 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3650 return;
3651
3652 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3653 RTL_W32(RxMissed, 0);
3654}
3655
1da177e4
LT		 3656static void rtl8169_down(struct net_device *dev)
3657{
3658 struct rtl8169_private *tp = netdev_priv(dev);
3659 void __iomem *ioaddr = tp->mmio_addr;
733b736c 3660 unsigned int intrmask;
1da177e4
LT		 3661
3662 rtl8169_delete_timer(dev);
3663
3664 netif_stop_queue(dev);
3665
93dd79e8 3666 napi_disable(&tp->napi);
93dd79e8 3667
1da177e4
LT		 3668core_down:
3669 spin_lock_irq(&tp->lock);
3670
3671 rtl8169_asic_down(ioaddr);
3672
523a6094 3673 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 3674
3675 spin_unlock_irq(&tp->lock);
3676
3677 synchronize_irq(dev->irq);
3678
1da177e4 3679 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 3680 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 3681
3682 /*
3683 * And now for the 50k$ question: are IRQ disabled or not ?
3684 *
3685 * Two paths lead here:
3686 * 1) dev->close
3687 * -> netif_running() is available to sync the current code and the
3688 * IRQ handler. See rtl8169_interrupt for details.
3689 * 2) dev->change_mtu
3690 * -> rtl8169_poll can not be issued again and re-enable the
3691 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 3692 *
3693 * No loop if hotpluged or major error (0xffff).
1da177e4 3694 */
733b736c
AP		 3695 intrmask = RTL_R16(IntrMask);
3696 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 3697 goto core_down;
3698
3699 rtl8169_tx_clear(tp);
3700
3701 rtl8169_rx_clear(tp);
3702}
3703
3704static int rtl8169_close(struct net_device *dev)
3705{
3706 struct rtl8169_private *tp = netdev_priv(dev);
3707 struct pci_dev *pdev = tp->pci_dev;
3708
355423d0
IV		 3709 /* update counters before going down */
3710 rtl8169_update_counters(dev);
3711
1da177e4
LT		 3712 rtl8169_down(dev);
3713
3714 free_irq(dev->irq, dev);
3715
1da177e4
LT		 3716 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3717 tp->RxPhyAddr);
3718 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3719 tp->TxPhyAddr);
3720 tp->TxDescArray = NULL;
3721 tp->RxDescArray = NULL;
3722
3723 return 0;
3724}
3725
07ce4064 3726static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 3727{
3728 struct rtl8169_private *tp = netdev_priv(dev);
3729 void __iomem *ioaddr = tp->mmio_addr;
3730 unsigned long flags;
3731 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 3732 int rx_mode;
1da177e4
LT		 3733 u32 tmp = 0;
3734
3735 if (dev->flags & IFF_PROMISC) {
3736 /* Unconditionally log net taps. */
b57b7e5a
SH		 3737 if (netif_msg_link(tp)) {
3738 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3739 dev->name);
3740 }
1da177e4
LT		 3741 rx_mode =
3742 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3743 AcceptAllPhys;
3744 mc_filter[1] = mc_filter[0] = 0xffffffff;
3745 } else if ((dev->mc_count > multicast_filter_limit)
3746 || (dev->flags & IFF_ALLMULTI)) {
3747 /* Too many to filter perfectly -- accept all multicasts. */
3748 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3749 mc_filter[1] = mc_filter[0] = 0xffffffff;
3750 } else {
3751 struct dev_mc_list *mclist;
07d3f51f
FR		 3752 unsigned int i;
3753
1da177e4
LT		 3754 rx_mode = AcceptBroadcast | AcceptMyPhys;
3755 mc_filter[1] = mc_filter[0] = 0;
3756 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3757 i++, mclist = mclist->next) {
3758 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3759 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3760 rx_mode |= AcceptMulticast;
3761 }
3762 }
3763
3764 spin_lock_irqsave(&tp->lock, flags);
3765
3766 tmp = rtl8169_rx_config | rx_mode |
3767 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3768
f887cce8 3769 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 3770 u32 data = mc_filter[0];
3771
3772 mc_filter[0] = swab32(mc_filter[1]);
3773 mc_filter[1] = swab32(data);
bcf0bf90
FR		 3774 }
3775
1da177e4
LT		 3776 RTL_W32(MAR0 + 0, mc_filter[0]);
3777 RTL_W32(MAR0 + 4, mc_filter[1]);
3778
57a9f236
FR		 3779 RTL_W32(RxConfig, tmp);
3780
1da177e4
LT		 3781 spin_unlock_irqrestore(&tp->lock, flags);
3782}
3783
3784/**
3785 * rtl8169_get_stats - Get rtl8169 read/write statistics
3786 * @dev: The Ethernet Device to get statistics for
3787 *
3788 * Get TX/RX statistics for rtl8169
3789 */
3790static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3791{
3792 struct rtl8169_private *tp = netdev_priv(dev);
3793 void __iomem *ioaddr = tp->mmio_addr;
3794 unsigned long flags;
3795
3796 if (netif_running(dev)) {
3797 spin_lock_irqsave(&tp->lock, flags);
523a6094 3798 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 3799 spin_unlock_irqrestore(&tp->lock, flags);
3800 }
5b0384f4 3801
cebf8cc7 3802 return &dev->stats;
1da177e4
LT		 3803}
3804
5d06a99f
FR		 3805#ifdef CONFIG_PM
3806
3807static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3808{
3809 struct net_device *dev = pci_get_drvdata(pdev);
3810 struct rtl8169_private *tp = netdev_priv(dev);
3811 void __iomem *ioaddr = tp->mmio_addr;
3812
3813 if (!netif_running(dev))
1371fa6d 3814 goto out_pci_suspend;
5d06a99f
FR		 3815
3816 netif_device_detach(dev);
3817 netif_stop_queue(dev);
3818
3819 spin_lock_irq(&tp->lock);
3820
3821 rtl8169_asic_down(ioaddr);
3822
523a6094 3823 rtl8169_rx_missed(dev, ioaddr);
5d06a99f
FR		 3824
3825 spin_unlock_irq(&tp->lock);
3826
1371fa6d 3827out_pci_suspend:
5d06a99f 3828 pci_save_state(pdev);
f23e7fda
FR		 3829 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3830 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
5d06a99f 3831 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1371fa6d 3832
5d06a99f
FR		 3833 return 0;
3834}
3835
3836static int rtl8169_resume(struct pci_dev *pdev)
3837{
3838 struct net_device *dev = pci_get_drvdata(pdev);
3839
1371fa6d
FR		 3840 pci_set_power_state(pdev, PCI_D0);
3841 pci_restore_state(pdev);
3842 pci_enable_wake(pdev, PCI_D0, 0);
3843
5d06a99f
FR		 3844 if (!netif_running(dev))
3845 goto out;
3846
3847 netif_device_attach(dev);
3848
5d06a99f
FR		 3849 rtl8169_schedule_work(dev, rtl8169_reset_task);
3850out:
3851 return 0;
3852}
3853
1765f95d
FR		 3854static void rtl_shutdown(struct pci_dev *pdev)
3855{
3856 rtl8169_suspend(pdev, PMSG_SUSPEND);
3857}
3858
5d06a99f
FR		 3859#endif /* CONFIG_PM */
3860
1da177e4
LT		 3861static struct pci_driver rtl8169_pci_driver = {
3862 .name = MODULENAME,
3863 .id_table = rtl8169_pci_tbl,
3864 .probe = rtl8169_init_one,
3865 .remove = __devexit_p(rtl8169_remove_one),
3866#ifdef CONFIG_PM
3867 .suspend = rtl8169_suspend,
3868 .resume = rtl8169_resume,
1765f95d 3869 .shutdown = rtl_shutdown,
1da177e4
LT		 3870#endif
3871};
3872
07d3f51f 3873static int __init rtl8169_init_module(void)
1da177e4 3874{
29917620 3875 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 3876}
3877
07d3f51f 3878static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 3879{
3880 pci_unregister_driver(&rtl8169_pci_driver);
3881}
3882
3883module_init(rtl8169_init_module);
3884module_exit(rtl8169_cleanup_module);
kernel source for telekom puls (alcatel/mediatek)