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r8169: add a new 8168c flavor (bis)
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
865c652d 31#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 32#define MODULENAME "r8169"
33#define PFX MODULENAME ": "
34
35#ifdef RTL8169_DEBUG
36#define assert(expr) \
5b0384f4
FR		 37 if (!(expr)) { \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 39 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 40 }
06fa7358
JP		 41#define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 43#else
44#define assert(expr) do {} while (0)
45#define dprintk(fmt, args...) do {} while (0)
46#endif /* RTL8169_DEBUG */
47
b57b7e5a 48#define R8169_MSG_DEFAULT \
f0e837d9 49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 50
1da177e4
LT		 51#define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
1da177e4 54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 55static const int max_interrupt_work = 20;
1da177e4
LT		 56
57/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 59static const int multicast_filter_limit = 32;
1da177e4
LT		 60
61/* MAC address length */
62#define MAC_ADDR_LEN 6
63
9c14ceaf 64#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 65#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 68#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 69#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
70#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
72
73#define R8169_REGS_SIZE 256
74#define R8169_NAPI_WEIGHT 64
75#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77#define RX_BUF_SIZE 1536 /* Rx Buffer size */
78#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
80
81#define RTL8169_TX_TIMEOUT (6*HZ)
82#define RTL8169_PHY_TIMEOUT (10*HZ)
83
84/* write/read MMIO register */
85#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88#define RTL_R8(reg) readb (ioaddr + (reg))
89#define RTL_R16(reg) readw (ioaddr + (reg))
90#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
91
92enum mac_version {
ba6eb6ee
FR		 93 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
94 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
95 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
96 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
97 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 98 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 99 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
100 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
101 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
102 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 103 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 104 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
105 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
106 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
107 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
108 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
109 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
110 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
111 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 112 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058
FR		 113 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
114 RTL_GIGA_MAC_VER_22 = 0x16 // 8168C
1da177e4
LT		 115};
116
1da177e4
LT		 117#define _R(NAME,MAC,MASK) \
118 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
119
3c6bee1d 120static const struct {
1da177e4
LT		 121 const char *name;
122 u8 mac_version;
123 u32 RxConfigMask; /* Clears the bits supported by this chip */
124} rtl_chip_info[] = {
ba6eb6ee
FR		 125 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
126 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
127 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
128 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
129 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 130 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 131 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
132 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
133 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
134 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 135 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
136 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
137 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
138 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 139 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
140 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
141 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
142 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
143 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
197ff761 144 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
6fb07058
FR		 145 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
146 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880) // PCI-E
1da177e4
LT		 147};
148#undef _R
149
bcf0bf90
FR		 150enum cfg_version {
151 RTL_CFG_0 = 0x00,
152 RTL_CFG_1,
153 RTL_CFG_2
154};
155
07ce4064
FR		 156static void rtl_hw_start_8169(struct net_device *);
157static void rtl_hw_start_8168(struct net_device *);
158static void rtl_hw_start_8101(struct net_device *);
159
1da177e4 160static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 161 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 162 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 163 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 164 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 165 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
166 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 167 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 168 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
169 { PCI_VENDOR_ID_LINKSYS, 0x1032,
170 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 171 { 0x0001, 0x8168,
172 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 173 {0,},
174};
175
176MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
177
178static int rx_copybreak = 200;
179static int use_dac;
b57b7e5a
SH		 180static struct {
181 u32 msg_enable;
182} debug = { -1 };
1da177e4 183
07d3f51f
FR		 184enum rtl_registers {
185 MAC0 = 0, /* Ethernet hardware address. */
773d2021 186 MAC4 = 4,
07d3f51f
FR		 187 MAR0 = 8, /* Multicast filter. */
188 CounterAddrLow = 0x10,
189 CounterAddrHigh = 0x14,
190 TxDescStartAddrLow = 0x20,
191 TxDescStartAddrHigh = 0x24,
192 TxHDescStartAddrLow = 0x28,
193 TxHDescStartAddrHigh = 0x2c,
194 FLASH = 0x30,
195 ERSR = 0x36,
196 ChipCmd = 0x37,
197 TxPoll = 0x38,
198 IntrMask = 0x3c,
199 IntrStatus = 0x3e,
200 TxConfig = 0x40,
201 RxConfig = 0x44,
202 RxMissed = 0x4c,
203 Cfg9346 = 0x50,
204 Config0 = 0x51,
205 Config1 = 0x52,
206 Config2 = 0x53,
207 Config3 = 0x54,
208 Config4 = 0x55,
209 Config5 = 0x56,
210 MultiIntr = 0x5c,
211 PHYAR = 0x60,
07d3f51f
FR		 212 PHYstatus = 0x6c,
213 RxMaxSize = 0xda,
214 CPlusCmd = 0xe0,
215 IntrMitigate = 0xe2,
216 RxDescAddrLow = 0xe4,
217 RxDescAddrHigh = 0xe8,
218 EarlyTxThres = 0xec,
219 FuncEvent = 0xf0,
220 FuncEventMask = 0xf4,
221 FuncPresetState = 0xf8,
222 FuncForceEvent = 0xfc,
1da177e4
LT		 223};
224
f162a5d1
FR		 225enum rtl8110_registers {
226 TBICSR = 0x64,
227 TBI_ANAR = 0x68,
228 TBI_LPAR = 0x6a,
229};
230
231enum rtl8168_8101_registers {
232 CSIDR = 0x64,
233 CSIAR = 0x68,
234#define CSIAR_FLAG 0x80000000
235#define CSIAR_WRITE_CMD 0x80000000
236#define CSIAR_BYTE_ENABLE 0x0f
237#define CSIAR_BYTE_ENABLE_SHIFT 12
238#define CSIAR_ADDR_MASK 0x0fff
239
240 EPHYAR = 0x80,
241#define EPHYAR_FLAG 0x80000000
242#define EPHYAR_WRITE_CMD 0x80000000
243#define EPHYAR_REG_MASK 0x1f
244#define EPHYAR_REG_SHIFT 16
245#define EPHYAR_DATA_MASK 0xffff
246 DBG_REG = 0xd1,
247#define FIX_NAK_1 (1 << 4)
248#define FIX_NAK_2 (1 << 3)
249};
250
07d3f51f 251enum rtl_register_content {
1da177e4 252 /* InterruptStatusBits */
07d3f51f
FR		 253 SYSErr = 0x8000,
254 PCSTimeout = 0x4000,
255 SWInt = 0x0100,
256 TxDescUnavail = 0x0080,
257 RxFIFOOver = 0x0040,
258 LinkChg = 0x0020,
259 RxOverflow = 0x0010,
260 TxErr = 0x0008,
261 TxOK = 0x0004,
262 RxErr = 0x0002,
263 RxOK = 0x0001,
1da177e4
LT		 264
265 /* RxStatusDesc */
9dccf611
FR		 266 RxFOVF = (1 << 23),
267 RxRWT = (1 << 22),
268 RxRES = (1 << 21),
269 RxRUNT = (1 << 20),
270 RxCRC = (1 << 19),
1da177e4
LT		 271
272 /* ChipCmdBits */
07d3f51f
FR		 273 CmdReset = 0x10,
274 CmdRxEnb = 0x08,
275 CmdTxEnb = 0x04,
276 RxBufEmpty = 0x01,
1da177e4 277
275391a4
FR		 278 /* TXPoll register p.5 */
279 HPQ = 0x80, /* Poll cmd on the high prio queue */
280 NPQ = 0x40, /* Poll cmd on the low prio queue */
281 FSWInt = 0x01, /* Forced software interrupt */
282
1da177e4 283 /* Cfg9346Bits */
07d3f51f
FR		 284 Cfg9346_Lock = 0x00,
285 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 286
287 /* rx_mode_bits */
07d3f51f
FR		 288 AcceptErr = 0x20,
289 AcceptRunt = 0x10,
290 AcceptBroadcast = 0x08,
291 AcceptMulticast = 0x04,
292 AcceptMyPhys = 0x02,
293 AcceptAllPhys = 0x01,
1da177e4
LT		 294
295 /* RxConfigBits */
07d3f51f
FR		 296 RxCfgFIFOShift = 13,
297 RxCfgDMAShift = 8,
1da177e4
LT		 298
299 /* TxConfigBits */
300 TxInterFrameGapShift = 24,
301 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
302
5d06a99f 303 /* Config1 register p.24 */
f162a5d1
FR		 304 LEDS1 = (1 << 7),
305 LEDS0 = (1 << 6),
fbac58fc 306 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 307 Speed_down = (1 << 4),
308 MEMMAP = (1 << 3),
309 IOMAP = (1 << 2),
310 VPD = (1 << 1),
5d06a99f
FR		 311 PMEnable = (1 << 0), /* Power Management Enable */
312
6dccd16b
FR		 313 /* Config2 register p. 25 */
314 PCI_Clock_66MHz = 0x01,
315 PCI_Clock_33MHz = 0x00,
316
61a4dcc2
FR		 317 /* Config3 register p.25 */
318 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
319 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 320 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 321
5d06a99f 322 /* Config5 register p.27 */
61a4dcc2
FR		 323 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
324 MWF = (1 << 5), /* Accept Multicast wakeup frame */
325 UWF = (1 << 4), /* Accept Unicast wakeup frame */
326 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 327 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
328
1da177e4
LT		 329 /* TBICSR p.28 */
330 TBIReset = 0x80000000,
331 TBILoopback = 0x40000000,
332 TBINwEnable = 0x20000000,
333 TBINwRestart = 0x10000000,
334 TBILinkOk = 0x02000000,
335 TBINwComplete = 0x01000000,
336
337 /* CPlusCmd p.31 */
f162a5d1
FR		 338 EnableBist = (1 << 15), // 8168 8101
339 Mac_dbgo_oe = (1 << 14), // 8168 8101
340 Normal_mode = (1 << 13), // unused
341 Force_half_dup = (1 << 12), // 8168 8101
342 Force_rxflow_en = (1 << 11), // 8168 8101
343 Force_txflow_en = (1 << 10), // 8168 8101
344 Cxpl_dbg_sel = (1 << 9), // 8168 8101
345 ASF = (1 << 8), // 8168 8101
346 PktCntrDisable = (1 << 7), // 8168 8101
347 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 348 RxVlan = (1 << 6),
349 RxChkSum = (1 << 5),
350 PCIDAC = (1 << 4),
351 PCIMulRW = (1 << 3),
0e485150
FR		 352 INTT_0 = 0x0000, // 8168
353 INTT_1 = 0x0001, // 8168
354 INTT_2 = 0x0002, // 8168
355 INTT_3 = 0x0003, // 8168
1da177e4
LT		 356
357 /* rtl8169_PHYstatus */
07d3f51f
FR		 358 TBI_Enable = 0x80,
359 TxFlowCtrl = 0x40,
360 RxFlowCtrl = 0x20,
361 _1000bpsF = 0x10,
362 _100bps = 0x08,
363 _10bps = 0x04,
364 LinkStatus = 0x02,
365 FullDup = 0x01,
1da177e4 366
1da177e4 367 /* _TBICSRBit */
07d3f51f 368 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 369
370 /* DumpCounterCommand */
07d3f51f 371 CounterDump = 0x8,
1da177e4
LT		 372};
373
07d3f51f 374enum desc_status_bit {
1da177e4
LT		 375 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
376 RingEnd = (1 << 30), /* End of descriptor ring */
377 FirstFrag = (1 << 29), /* First segment of a packet */
378 LastFrag = (1 << 28), /* Final segment of a packet */
379
380 /* Tx private */
381 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
382 MSSShift = 16, /* MSS value position */
383 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
384 IPCS = (1 << 18), /* Calculate IP checksum */
385 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
386 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
387 TxVlanTag = (1 << 17), /* Add VLAN tag */
388
389 /* Rx private */
390 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
391 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
392
393#define RxProtoUDP (PID1)
394#define RxProtoTCP (PID0)
395#define RxProtoIP (PID1 | PID0)
396#define RxProtoMask RxProtoIP
397
398 IPFail = (1 << 16), /* IP checksum failed */
399 UDPFail = (1 << 15), /* UDP/IP checksum failed */
400 TCPFail = (1 << 14), /* TCP/IP checksum failed */
401 RxVlanTag = (1 << 16), /* VLAN tag available */
402};
403
404#define RsvdMask 0x3fffc000
405
406struct TxDesc {
6cccd6e7
REB		 407 __le32 opts1;
408 __le32 opts2;
409 __le64 addr;
1da177e4
LT		 410};
411
412struct RxDesc {
6cccd6e7
REB		 413 __le32 opts1;
414 __le32 opts2;
415 __le64 addr;
1da177e4
LT		 416};
417
418struct ring_info {
419 struct sk_buff *skb;
420 u32 len;
421 u8 __pad[sizeof(void *) - sizeof(u32)];
422};
423
f23e7fda 424enum features {
ccdffb9a
FR		 425 RTL_FEATURE_WOL = (1 << 0),
426 RTL_FEATURE_MSI = (1 << 1),
427 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 428};
429
1da177e4
LT		 430struct rtl8169_private {
431 void __iomem *mmio_addr; /* memory map physical address */
432 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 433 struct net_device *dev;
bea3348e 434 struct napi_struct napi;
1da177e4 435 spinlock_t lock; /* spin lock flag */
b57b7e5a 436 u32 msg_enable;
1da177e4
LT		 437 int chipset;
438 int mac_version;
1da177e4
LT		 439 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
440 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
441 u32 dirty_rx;
442 u32 dirty_tx;
443 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
444 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
445 dma_addr_t TxPhyAddr;
446 dma_addr_t RxPhyAddr;
447 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
448 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 449 unsigned align;
1da177e4
LT		 450 unsigned rx_buf_sz;
451 struct timer_list timer;
452 u16 cp_cmd;
0e485150
FR		 453 u16 intr_event;
454 u16 napi_event;
1da177e4
LT		 455 u16 intr_mask;
456 int phy_auto_nego_reg;
457 int phy_1000_ctrl_reg;
458#ifdef CONFIG_R8169_VLAN
459 struct vlan_group *vlgrp;
460#endif
461 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 462 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
1da177e4 463 void (*phy_reset_enable)(void __iomem *);
07ce4064 464 void (*hw_start)(struct net_device *);
1da177e4
LT		 465 unsigned int (*phy_reset_pending)(void __iomem *);
466 unsigned int (*link_ok)(void __iomem *);
9c14ceaf 467 int pcie_cap;
c4028958 468 struct delayed_work task;
f23e7fda 469 unsigned features;
ccdffb9a
FR		 470
471 struct mii_if_info mii;
1da177e4
LT		 472};
473
979b6c13 474MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 475MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 476module_param(rx_copybreak, int, 0);
1b7efd58 477MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 478module_param(use_dac, int, 0);
479MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 480module_param_named(debug, debug.msg_enable, int, 0);
481MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 482MODULE_LICENSE("GPL");
483MODULE_VERSION(RTL8169_VERSION);
484
485static int rtl8169_open(struct net_device *dev);
486static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 487static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 488static int rtl8169_init_ring(struct net_device *dev);
07ce4064 489static void rtl_hw_start(struct net_device *dev);
1da177e4 490static int rtl8169_close(struct net_device *dev);
07ce4064 491static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 492static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 493static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 494static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 495 void __iomem *, u32 budget);
4dcb7d33 496static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 497static void rtl8169_down(struct net_device *dev);
99f252b0 498static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 499static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 500
1da177e4 501static const unsigned int rtl8169_rx_config =
5b0384f4 502 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 503
07d3f51f 504static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 505{
506 int i;
507
a6baf3af 508 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 509
2371408c 510 for (i = 20; i > 0; i--) {
07d3f51f
FR		 511 /*
512 * Check if the RTL8169 has completed writing to the specified
513 * MII register.
514 */
5b0384f4 515 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 516 break;
2371408c 517 udelay(25);
1da177e4
LT		 518 }
519}
520
07d3f51f 521static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 522{
523 int i, value = -1;
524
a6baf3af 525 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 526
2371408c 527 for (i = 20; i > 0; i--) {
07d3f51f
FR		 528 /*
529 * Check if the RTL8169 has completed retrieving data from
530 * the specified MII register.
531 */
1da177e4 532 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 533 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 534 break;
535 }
2371408c 536 udelay(25);
1da177e4
LT		 537 }
538 return value;
539}
540
dacf8154
FR		 541static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
542{
543 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
544}
545
ccdffb9a
FR		 546static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
547 int val)
548{
549 struct rtl8169_private *tp = netdev_priv(dev);
550 void __iomem *ioaddr = tp->mmio_addr;
551
552 mdio_write(ioaddr, location, val);
553}
554
555static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
556{
557 struct rtl8169_private *tp = netdev_priv(dev);
558 void __iomem *ioaddr = tp->mmio_addr;
559
560 return mdio_read(ioaddr, location);
561}
562
dacf8154
FR		 563static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
564{
565 unsigned int i;
566
567 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
568 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
569
570 for (i = 0; i < 100; i++) {
571 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
572 break;
573 udelay(10);
574 }
575}
576
577static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
578{
579 u16 value = 0xffff;
580 unsigned int i;
581
582 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
583
584 for (i = 0; i < 100; i++) {
585 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
586 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
587 break;
588 }
589 udelay(10);
590 }
591
592 return value;
593}
594
595static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
596{
597 unsigned int i;
598
599 RTL_W32(CSIDR, value);
600 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
601 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
602
603 for (i = 0; i < 100; i++) {
604 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
605 break;
606 udelay(10);
607 }
608}
609
610static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
611{
612 u32 value = ~0x00;
613 unsigned int i;
614
615 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
616 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
617
618 for (i = 0; i < 100; i++) {
619 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
620 value = RTL_R32(CSIDR);
621 break;
622 }
623 udelay(10);
624 }
625
626 return value;
627}
628
1da177e4
LT		 629static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
630{
631 RTL_W16(IntrMask, 0x0000);
632
633 RTL_W16(IntrStatus, 0xffff);
634}
635
636static void rtl8169_asic_down(void __iomem *ioaddr)
637{
638 RTL_W8(ChipCmd, 0x00);
639 rtl8169_irq_mask_and_ack(ioaddr);
640 RTL_R16(CPlusCmd);
641}
642
643static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
644{
645 return RTL_R32(TBICSR) & TBIReset;
646}
647
648static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
649{
64e4bfb4 650 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 651}
652
653static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
654{
655 return RTL_R32(TBICSR) & TBILinkOk;
656}
657
658static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
659{
660 return RTL_R8(PHYstatus) & LinkStatus;
661}
662
663static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
664{
665 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
666}
667
668static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
669{
670 unsigned int val;
671
9e0db8ef
FR		 672 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
673 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 674}
675
676static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 677 struct rtl8169_private *tp,
678 void __iomem *ioaddr)
1da177e4
LT		 679{
680 unsigned long flags;
681
682 spin_lock_irqsave(&tp->lock, flags);
683 if (tp->link_ok(ioaddr)) {
684 netif_carrier_on(dev);
b57b7e5a
SH		 685 if (netif_msg_ifup(tp))
686 printk(KERN_INFO PFX "%s: link up\n", dev->name);
687 } else {
688 if (netif_msg_ifdown(tp))
689 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 690 netif_carrier_off(dev);
b57b7e5a 691 }
1da177e4
LT		 692 spin_unlock_irqrestore(&tp->lock, flags);
693}
694
61a4dcc2
FR		 695static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
696{
697 struct rtl8169_private *tp = netdev_priv(dev);
698 void __iomem *ioaddr = tp->mmio_addr;
699 u8 options;
700
701 wol->wolopts = 0;
702
703#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
704 wol->supported = WAKE_ANY;
705
706 spin_lock_irq(&tp->lock);
707
708 options = RTL_R8(Config1);
709 if (!(options & PMEnable))
710 goto out_unlock;
711
712 options = RTL_R8(Config3);
713 if (options & LinkUp)
714 wol->wolopts |= WAKE_PHY;
715 if (options & MagicPacket)
716 wol->wolopts |= WAKE_MAGIC;
717
718 options = RTL_R8(Config5);
719 if (options & UWF)
720 wol->wolopts |= WAKE_UCAST;
721 if (options & BWF)
5b0384f4 722 wol->wolopts |= WAKE_BCAST;
61a4dcc2 723 if (options & MWF)
5b0384f4 724 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 725
726out_unlock:
727 spin_unlock_irq(&tp->lock);
728}
729
730static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
731{
732 struct rtl8169_private *tp = netdev_priv(dev);
733 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 734 unsigned int i;
61a4dcc2
FR		 735 static struct {
736 u32 opt;
737 u16 reg;
738 u8 mask;
739 } cfg[] = {
740 { WAKE_ANY, Config1, PMEnable },
741 { WAKE_PHY, Config3, LinkUp },
742 { WAKE_MAGIC, Config3, MagicPacket },
743 { WAKE_UCAST, Config5, UWF },
744 { WAKE_BCAST, Config5, BWF },
745 { WAKE_MCAST, Config5, MWF },
746 { WAKE_ANY, Config5, LanWake }
747 };
748
749 spin_lock_irq(&tp->lock);
750
751 RTL_W8(Cfg9346, Cfg9346_Unlock);
752
753 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
754 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
755 if (wol->wolopts & cfg[i].opt)
756 options |= cfg[i].mask;
757 RTL_W8(cfg[i].reg, options);
758 }
759
760 RTL_W8(Cfg9346, Cfg9346_Lock);
761
f23e7fda
FR		 762 if (wol->wolopts)
763 tp->features |= RTL_FEATURE_WOL;
764 else
765 tp->features &= ~RTL_FEATURE_WOL;
8b76ab39 766 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
61a4dcc2
FR		 767
768 spin_unlock_irq(&tp->lock);
769
770 return 0;
771}
772
1da177e4
LT		 773static void rtl8169_get_drvinfo(struct net_device *dev,
774 struct ethtool_drvinfo *info)
775{
776 struct rtl8169_private *tp = netdev_priv(dev);
777
778 strcpy(info->driver, MODULENAME);
779 strcpy(info->version, RTL8169_VERSION);
780 strcpy(info->bus_info, pci_name(tp->pci_dev));
781}
782
783static int rtl8169_get_regs_len(struct net_device *dev)
784{
785 return R8169_REGS_SIZE;
786}
787
788static int rtl8169_set_speed_tbi(struct net_device *dev,
789 u8 autoneg, u16 speed, u8 duplex)
790{
791 struct rtl8169_private *tp = netdev_priv(dev);
792 void __iomem *ioaddr = tp->mmio_addr;
793 int ret = 0;
794 u32 reg;
795
796 reg = RTL_R32(TBICSR);
797 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
798 (duplex == DUPLEX_FULL)) {
799 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
800 } else if (autoneg == AUTONEG_ENABLE)
801 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
802 else {
b57b7e5a
SH		 803 if (netif_msg_link(tp)) {
804 printk(KERN_WARNING "%s: "
805 "incorrect speed setting refused in TBI mode\n",
806 dev->name);
807 }
1da177e4
LT		 808 ret = -EOPNOTSUPP;
809 }
810
811 return ret;
812}
813
814static int rtl8169_set_speed_xmii(struct net_device *dev,
815 u8 autoneg, u16 speed, u8 duplex)
816{
817 struct rtl8169_private *tp = netdev_priv(dev);
818 void __iomem *ioaddr = tp->mmio_addr;
819 int auto_nego, giga_ctrl;
820
64e4bfb4
FR		 821 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
822 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
823 ADVERTISE_100HALF | ADVERTISE_100FULL);
824 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
825 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 826
827 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 828 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
829 ADVERTISE_100HALF | ADVERTISE_100FULL);
830 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 831 } else {
832 if (speed == SPEED_10)
64e4bfb4 833 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 834 else if (speed == SPEED_100)
64e4bfb4 835 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 836 else if (speed == SPEED_1000)
64e4bfb4 837 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 838
839 if (duplex == DUPLEX_HALF)
64e4bfb4 840 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 841
842 if (duplex == DUPLEX_FULL)
64e4bfb4 843 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 844
845 /* This tweak comes straight from Realtek's driver. */
846 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
e3cf0cc0
FR		 847 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
848 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
64e4bfb4 849 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 850 }
851 }
852
2857ffb7
FR		 853 /* The 8100e/8101e/8102e do Fast Ethernet only. */
854 if ((tp->mac_version == RTL_GIGA_MAC_VER_07) ||
855 (tp->mac_version == RTL_GIGA_MAC_VER_08) ||
856 (tp->mac_version == RTL_GIGA_MAC_VER_09) ||
857 (tp->mac_version == RTL_GIGA_MAC_VER_10) ||
858 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
bcf0bf90 859 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
e3cf0cc0
FR		 860 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
861 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
64e4bfb4 862 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 863 netif_msg_link(tp)) {
864 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
865 dev->name);
866 }
64e4bfb4 867 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 868 }
869
623a1593
FR		 870 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
871
a2de6b89
FR		 872 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
873 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
874 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
875 /*
876 * Wake up the PHY.
877 * Vendor specific (0x1f) and reserved (0x0e) MII registers.
878 */
2584fbc3
RS		 879 mdio_write(ioaddr, 0x1f, 0x0000);
880 mdio_write(ioaddr, 0x0e, 0x0000);
881 }
882
1da177e4
LT		 883 tp->phy_auto_nego_reg = auto_nego;
884 tp->phy_1000_ctrl_reg = giga_ctrl;
885
64e4bfb4
FR		 886 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
887 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
888 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 889 return 0;
890}
891
892static int rtl8169_set_speed(struct net_device *dev,
893 u8 autoneg, u16 speed, u8 duplex)
894{
895 struct rtl8169_private *tp = netdev_priv(dev);
896 int ret;
897
898 ret = tp->set_speed(dev, autoneg, speed, duplex);
899
64e4bfb4 900 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 901 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
902
903 return ret;
904}
905
906static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
907{
908 struct rtl8169_private *tp = netdev_priv(dev);
909 unsigned long flags;
910 int ret;
911
912 spin_lock_irqsave(&tp->lock, flags);
913 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
914 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 915
1da177e4
LT		 916 return ret;
917}
918
919static u32 rtl8169_get_rx_csum(struct net_device *dev)
920{
921 struct rtl8169_private *tp = netdev_priv(dev);
922
923 return tp->cp_cmd & RxChkSum;
924}
925
926static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
927{
928 struct rtl8169_private *tp = netdev_priv(dev);
929 void __iomem *ioaddr = tp->mmio_addr;
930 unsigned long flags;
931
932 spin_lock_irqsave(&tp->lock, flags);
933
934 if (data)
935 tp->cp_cmd |= RxChkSum;
936 else
937 tp->cp_cmd &= ~RxChkSum;
938
939 RTL_W16(CPlusCmd, tp->cp_cmd);
940 RTL_R16(CPlusCmd);
941
942 spin_unlock_irqrestore(&tp->lock, flags);
943
944 return 0;
945}
946
947#ifdef CONFIG_R8169_VLAN
948
949static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
950 struct sk_buff *skb)
951{
952 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
953 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
954}
955
956static void rtl8169_vlan_rx_register(struct net_device *dev,
957 struct vlan_group *grp)
958{
959 struct rtl8169_private *tp = netdev_priv(dev);
960 void __iomem *ioaddr = tp->mmio_addr;
961 unsigned long flags;
962
963 spin_lock_irqsave(&tp->lock, flags);
964 tp->vlgrp = grp;
965 if (tp->vlgrp)
966 tp->cp_cmd |= RxVlan;
967 else
968 tp->cp_cmd &= ~RxVlan;
969 RTL_W16(CPlusCmd, tp->cp_cmd);
970 RTL_R16(CPlusCmd);
971 spin_unlock_irqrestore(&tp->lock, flags);
972}
973
1da177e4
LT		 974static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
975 struct sk_buff *skb)
976{
977 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 978 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 979 int ret;
980
865c652d
FR		 981 if (vlgrp && (opts2 & RxVlanTag)) {
982 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 983 ret = 0;
984 } else
985 ret = -1;
986 desc->opts2 = 0;
987 return ret;
988}
989
990#else /* !CONFIG_R8169_VLAN */
991
992static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
993 struct sk_buff *skb)
994{
995 return 0;
996}
997
998static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
999 struct sk_buff *skb)
1000{
1001 return -1;
1002}
1003
1004#endif
1005
ccdffb9a 1006static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1007{
1008 struct rtl8169_private *tp = netdev_priv(dev);
1009 void __iomem *ioaddr = tp->mmio_addr;
1010 u32 status;
1011
1012 cmd->supported =
1013 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1014 cmd->port = PORT_FIBRE;
1015 cmd->transceiver = XCVR_INTERNAL;
1016
1017 status = RTL_R32(TBICSR);
1018 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1019 cmd->autoneg = !!(status & TBINwEnable);
1020
1021 cmd->speed = SPEED_1000;
1022 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1023
1024 return 0;
1da177e4
LT		 1025}
1026
ccdffb9a 1027static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1028{
1029 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1030
1031 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1032}
1033
1034static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1035{
1036 struct rtl8169_private *tp = netdev_priv(dev);
1037 unsigned long flags;
ccdffb9a 1038 int rc;
1da177e4
LT		 1039
1040 spin_lock_irqsave(&tp->lock, flags);
1041
ccdffb9a 1042 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1043
1044 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1045 return rc;
1da177e4
LT		 1046}
1047
1048static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1049 void *p)
1050{
5b0384f4
FR		 1051 struct rtl8169_private *tp = netdev_priv(dev);
1052 unsigned long flags;
1da177e4 1053
5b0384f4
FR		 1054 if (regs->len > R8169_REGS_SIZE)
1055 regs->len = R8169_REGS_SIZE;
1da177e4 1056
5b0384f4
FR		 1057 spin_lock_irqsave(&tp->lock, flags);
1058 memcpy_fromio(p, tp->mmio_addr, regs->len);
1059 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1060}
1061
b57b7e5a
SH		 1062static u32 rtl8169_get_msglevel(struct net_device *dev)
1063{
1064 struct rtl8169_private *tp = netdev_priv(dev);
1065
1066 return tp->msg_enable;
1067}
1068
1069static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1070{
1071 struct rtl8169_private *tp = netdev_priv(dev);
1072
1073 tp->msg_enable = value;
1074}
1075
d4a3a0fc
SH		 1076static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1077 "tx_packets",
1078 "rx_packets",
1079 "tx_errors",
1080 "rx_errors",
1081 "rx_missed",
1082 "align_errors",
1083 "tx_single_collisions",
1084 "tx_multi_collisions",
1085 "unicast",
1086 "broadcast",
1087 "multicast",
1088 "tx_aborted",
1089 "tx_underrun",
1090};
1091
1092struct rtl8169_counters {
b1eab701
AV		 1093 __le64 tx_packets;
1094 __le64 rx_packets;
1095 __le64 tx_errors;
1096 __le32 rx_errors;
1097 __le16 rx_missed;
1098 __le16 align_errors;
1099 __le32 tx_one_collision;
1100 __le32 tx_multi_collision;
1101 __le64 rx_unicast;
1102 __le64 rx_broadcast;
1103 __le32 rx_multicast;
1104 __le16 tx_aborted;
1105 __le16 tx_underun;
d4a3a0fc
SH		 1106};
1107
b9f2c044 1108static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1109{
b9f2c044
JG		 1110 switch (sset) {
1111 case ETH_SS_STATS:
1112 return ARRAY_SIZE(rtl8169_gstrings);
1113 default:
1114 return -EOPNOTSUPP;
1115 }
d4a3a0fc
SH		 1116}
1117
1118static void rtl8169_get_ethtool_stats(struct net_device *dev,
1119 struct ethtool_stats *stats, u64 *data)
1120{
1121 struct rtl8169_private *tp = netdev_priv(dev);
1122 void __iomem *ioaddr = tp->mmio_addr;
1123 struct rtl8169_counters *counters;
1124 dma_addr_t paddr;
1125 u32 cmd;
1126
1127 ASSERT_RTNL();
1128
1129 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1130 if (!counters)
1131 return;
1132
1133 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1134 cmd = (u64)paddr & DMA_32BIT_MASK;
1135 RTL_W32(CounterAddrLow, cmd);
1136 RTL_W32(CounterAddrLow, cmd | CounterDump);
1137
1138 while (RTL_R32(CounterAddrLow) & CounterDump) {
1139 if (msleep_interruptible(1))
1140 break;
1141 }
1142
1143 RTL_W32(CounterAddrLow, 0);
1144 RTL_W32(CounterAddrHigh, 0);
1145
5b0384f4 1146 data[0] = le64_to_cpu(counters->tx_packets);
d4a3a0fc
SH		 1147 data[1] = le64_to_cpu(counters->rx_packets);
1148 data[2] = le64_to_cpu(counters->tx_errors);
1149 data[3] = le32_to_cpu(counters->rx_errors);
1150 data[4] = le16_to_cpu(counters->rx_missed);
1151 data[5] = le16_to_cpu(counters->align_errors);
1152 data[6] = le32_to_cpu(counters->tx_one_collision);
1153 data[7] = le32_to_cpu(counters->tx_multi_collision);
1154 data[8] = le64_to_cpu(counters->rx_unicast);
1155 data[9] = le64_to_cpu(counters->rx_broadcast);
1156 data[10] = le32_to_cpu(counters->rx_multicast);
1157 data[11] = le16_to_cpu(counters->tx_aborted);
1158 data[12] = le16_to_cpu(counters->tx_underun);
1159
1160 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1161}
1162
1163static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1164{
1165 switch(stringset) {
1166 case ETH_SS_STATS:
1167 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1168 break;
1169 }
1170}
1171
7282d491 1172static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1173 .get_drvinfo = rtl8169_get_drvinfo,
1174 .get_regs_len = rtl8169_get_regs_len,
1175 .get_link = ethtool_op_get_link,
1176 .get_settings = rtl8169_get_settings,
1177 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1178 .get_msglevel = rtl8169_get_msglevel,
1179 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1180 .get_rx_csum = rtl8169_get_rx_csum,
1181 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1182 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1183 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1184 .set_tso = ethtool_op_set_tso,
1185 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1186 .get_wol = rtl8169_get_wol,
1187 .set_wol = rtl8169_set_wol,
d4a3a0fc 1188 .get_strings = rtl8169_get_strings,
b9f2c044 1189 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1190 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1191};
1192
07d3f51f
FR		 1193static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1194 int bitnum, int bitval)
1da177e4
LT		 1195{
1196 int val;
1197
1198 val = mdio_read(ioaddr, reg);
1199 val = (bitval == 1) ?
1200 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1201 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1202}
1203
07d3f51f
FR		 1204static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1205 void __iomem *ioaddr)
1da177e4 1206{
0e485150
FR		 1207 /*
1208 * The driver currently handles the 8168Bf and the 8168Be identically
1209 * but they can be identified more specifically through the test below
1210 * if needed:
1211 *
1212 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1213 *
1214 * Same thing for the 8101Eb and the 8101Ec:
1215 *
1216 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1217 */
1da177e4
LT		 1218 const struct {
1219 u32 mask;
e3cf0cc0 1220 u32 val;
1da177e4
LT		 1221 int mac_version;
1222 } mac_info[] = {
e3cf0cc0
FR		 1223 /* 8168B family. */
1224 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1225 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1226 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1227 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1228 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1229 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 },
1230
1231 /* 8168B family. */
1232 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1233 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1234 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1235 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1236
1237 /* 8101 family. */
2857ffb7
FR		 1238 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1239 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1240 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1241 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1242 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1243 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1244 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1245 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1246 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1247 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1248 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1249 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1250 /* FIXME: where did these entries come from ? -- FR */
1251 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1252 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1253
1254 /* 8110 family. */
1255 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1256 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1257 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1258 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1259 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1260 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1261
1262 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1263 }, *p = mac_info;
1264 u32 reg;
1265
e3cf0cc0
FR		 1266 reg = RTL_R32(TxConfig);
1267 while ((reg & p->mask) != p->val)
1da177e4
LT		 1268 p++;
1269 tp->mac_version = p->mac_version;
e3cf0cc0
FR		 1270
1271 if (p->mask == 0x00000000) {
1272 struct pci_dev *pdev = tp->pci_dev;
1273
1274 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1275 }
1da177e4
LT		 1276}
1277
1278static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1279{
bcf0bf90 1280 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1281}
1282
867763c1
FR		 1283struct phy_reg {
1284 u16 reg;
1285 u16 val;
1286};
1287
1288static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1289{
1290 while (len-- > 0) {
1291 mdio_write(ioaddr, regs->reg, regs->val);
1292 regs++;
1293 }
1294}
1295
5615d9f1 1296static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1297{
1da177e4
LT		 1298 struct {
1299 u16 regs[5]; /* Beware of bit-sign propagation */
1300 } phy_magic[5] = { {
1301 { 0x0000, //w 4 15 12 0
1302 0x00a1, //w 3 15 0 00a1
1303 0x0008, //w 2 15 0 0008
1304 0x1020, //w 1 15 0 1020
1305 0x1000 } },{ //w 0 15 0 1000
1306 { 0x7000, //w 4 15 12 7
1307 0xff41, //w 3 15 0 ff41
1308 0xde60, //w 2 15 0 de60
1309 0x0140, //w 1 15 0 0140
1310 0x0077 } },{ //w 0 15 0 0077
1311 { 0xa000, //w 4 15 12 a
1312 0xdf01, //w 3 15 0 df01
1313 0xdf20, //w 2 15 0 df20
1314 0xff95, //w 1 15 0 ff95
1315 0xfa00 } },{ //w 0 15 0 fa00
1316 { 0xb000, //w 4 15 12 b
1317 0xff41, //w 3 15 0 ff41
1318 0xde20, //w 2 15 0 de20
1319 0x0140, //w 1 15 0 0140
1320 0x00bb } },{ //w 0 15 0 00bb
1321 { 0xf000, //w 4 15 12 f
1322 0xdf01, //w 3 15 0 df01
1323 0xdf20, //w 2 15 0 df20
1324 0xff95, //w 1 15 0 ff95
1325 0xbf00 } //w 0 15 0 bf00
1326 }
1327 }, *p = phy_magic;
07d3f51f 1328 unsigned int i;
1da177e4 1329
a441d7b6
FR		 1330 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1331 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1332 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1da177e4
LT		 1333 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1334
1335 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1336 int val, pos = 4;
1337
1338 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1339 mdio_write(ioaddr, pos, val);
1340 while (--pos >= 0)
1341 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1342 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1343 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1344 }
a441d7b6 1345 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1da177e4
LT		 1346}
1347
5615d9f1
FR		 1348static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1349{
a441d7b6
FR		 1350 struct phy_reg phy_reg_init[] = {
1351 { 0x1f, 0x0002 },
1352 { 0x01, 0x90d0 },
1353 { 0x1f, 0x0000 }
1354 };
1355
1356 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1357}
1358
236b8082
FR		 1359static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1360{
1361 struct phy_reg phy_reg_init[] = {
1362 { 0x10, 0xf41b },
1363 { 0x1f, 0x0000 }
1364 };
1365
1366 mdio_write(ioaddr, 0x1f, 0x0001);
1367 mdio_patch(ioaddr, 0x16, 1 << 0);
1368
1369 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1370}
1371
1372static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1373{
1374 struct phy_reg phy_reg_init[] = {
1375 { 0x1f, 0x0001 },
1376 { 0x10, 0xf41b },
1377 { 0x1f, 0x0000 }
1378 };
1379
1380 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1381}
1382
867763c1
FR		 1383static void rtl8168cp_hw_phy_config(void __iomem *ioaddr)
1384{
1385 struct phy_reg phy_reg_init[] = {
1386 { 0x1f, 0x0000 },
1387 { 0x1d, 0x0f00 },
1388 { 0x1f, 0x0002 },
1389 { 0x0c, 0x1ec8 },
1390 { 0x1f, 0x0000 }
1391 };
1392
1393 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1394}
1395
219a1e9d 1396static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
867763c1
FR		 1397{
1398 struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1399 { 0x1f, 0x0001 },
1400 { 0x12, 0x2300 },
867763c1
FR		 1401 { 0x1f, 0x0002 },
1402 { 0x00, 0x88d4 },
1403 { 0x01, 0x82b1 },
1404 { 0x03, 0x7002 },
1405 { 0x08, 0x9e30 },
1406 { 0x09, 0x01f0 },
1407 { 0x0a, 0x5500 },
1408 { 0x0c, 0x00c8 },
1409 { 0x1f, 0x0003 },
1410 { 0x12, 0xc096 },
1411 { 0x16, 0x000a },
f50d4275
FR		 1412 { 0x1f, 0x0000 },
1413 { 0x1f, 0x0000 },
1414 { 0x09, 0x2000 },
1415 { 0x09, 0x0000 }
867763c1
FR		 1416 };
1417
1418 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1419
1420 mdio_patch(ioaddr, 0x14, 1 << 5);
1421 mdio_patch(ioaddr, 0x0d, 1 << 5);
1422 mdio_write(ioaddr, 0x1f, 0x0000);
867763c1
FR		 1423}
1424
219a1e9d 1425static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
7da97ec9
FR		 1426{
1427 struct phy_reg phy_reg_init[] = {
f50d4275 1428 { 0x1f, 0x0001 },
7da97ec9 1429 { 0x12, 0x2300 },
f50d4275
FR		 1430 { 0x03, 0x802f },
1431 { 0x02, 0x4f02 },
1432 { 0x01, 0x0409 },
1433 { 0x00, 0xf099 },
1434 { 0x04, 0x9800 },
1435 { 0x04, 0x9000 },
1436 { 0x1d, 0x3d98 },
7da97ec9
FR		 1437 { 0x1f, 0x0002 },
1438 { 0x0c, 0x7eb8 },
f50d4275
FR		 1439 { 0x06, 0x0761 },
1440 { 0x1f, 0x0003 },
1441 { 0x16, 0x0f0a },
7da97ec9
FR		 1442 { 0x1f, 0x0000 }
1443 };
1444
1445 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1446
1447 mdio_patch(ioaddr, 0x16, 1 << 0);
1448 mdio_patch(ioaddr, 0x14, 1 << 5);
1449 mdio_patch(ioaddr, 0x0d, 1 << 5);
1450 mdio_write(ioaddr, 0x1f, 0x0000);
7da97ec9
FR		 1451}
1452
197ff761
FR		 1453static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1454{
1455 struct phy_reg phy_reg_init[] = {
1456 { 0x1f, 0x0001 },
1457 { 0x12, 0x2300 },
1458 { 0x1d, 0x3d98 },
1459 { 0x1f, 0x0002 },
1460 { 0x0c, 0x7eb8 },
1461 { 0x06, 0x5461 },
1462 { 0x1f, 0x0003 },
1463 { 0x16, 0x0f0a },
1464 { 0x1f, 0x0000 }
1465 };
1466
1467 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1468
1469 mdio_patch(ioaddr, 0x16, 1 << 0);
1470 mdio_patch(ioaddr, 0x14, 1 << 5);
1471 mdio_patch(ioaddr, 0x0d, 1 << 5);
1472 mdio_write(ioaddr, 0x1f, 0x0000);
1473}
1474
6fb07058
FR		 1475static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1476{
1477 rtl8168c_3_hw_phy_config(ioaddr);
1478}
1479
2857ffb7
FR		 1480static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1481{
1482 struct phy_reg phy_reg_init[] = {
1483 { 0x1f, 0x0003 },
1484 { 0x08, 0x441d },
1485 { 0x01, 0x9100 },
1486 { 0x1f, 0x0000 }
1487 };
1488
1489 mdio_write(ioaddr, 0x1f, 0x0000);
1490 mdio_patch(ioaddr, 0x11, 1 << 12);
1491 mdio_patch(ioaddr, 0x19, 1 << 13);
1492
1493 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1494}
1495
5615d9f1
FR		 1496static void rtl_hw_phy_config(struct net_device *dev)
1497{
1498 struct rtl8169_private *tp = netdev_priv(dev);
1499 void __iomem *ioaddr = tp->mmio_addr;
1500
1501 rtl8169_print_mac_version(tp);
1502
1503 switch (tp->mac_version) {
1504 case RTL_GIGA_MAC_VER_01:
1505 break;
1506 case RTL_GIGA_MAC_VER_02:
1507 case RTL_GIGA_MAC_VER_03:
1508 rtl8169s_hw_phy_config(ioaddr);
1509 break;
1510 case RTL_GIGA_MAC_VER_04:
1511 rtl8169sb_hw_phy_config(ioaddr);
1512 break;
2857ffb7
FR		 1513 case RTL_GIGA_MAC_VER_07:
1514 case RTL_GIGA_MAC_VER_08:
1515 case RTL_GIGA_MAC_VER_09:
1516 rtl8102e_hw_phy_config(ioaddr);
1517 break;
236b8082
FR		 1518 case RTL_GIGA_MAC_VER_11:
1519 rtl8168bb_hw_phy_config(ioaddr);
1520 break;
1521 case RTL_GIGA_MAC_VER_12:
1522 rtl8168bef_hw_phy_config(ioaddr);
1523 break;
1524 case RTL_GIGA_MAC_VER_17:
1525 rtl8168bef_hw_phy_config(ioaddr);
1526 break;
867763c1
FR		 1527 case RTL_GIGA_MAC_VER_18:
1528 rtl8168cp_hw_phy_config(ioaddr);
1529 break;
1530 case RTL_GIGA_MAC_VER_19:
219a1e9d 1531 rtl8168c_1_hw_phy_config(ioaddr);
867763c1 1532 break;
7da97ec9 1533 case RTL_GIGA_MAC_VER_20:
219a1e9d 1534 rtl8168c_2_hw_phy_config(ioaddr);
7da97ec9 1535 break;
197ff761
FR		 1536 case RTL_GIGA_MAC_VER_21:
1537 rtl8168c_3_hw_phy_config(ioaddr);
1538 break;
6fb07058
FR		 1539 case RTL_GIGA_MAC_VER_22:
1540 rtl8168c_4_hw_phy_config(ioaddr);
1541 break;
5615d9f1
FR		 1542 default:
1543 break;
1544 }
1545}
1546
1da177e4
LT		 1547static void rtl8169_phy_timer(unsigned long __opaque)
1548{
1549 struct net_device *dev = (struct net_device *)__opaque;
1550 struct rtl8169_private *tp = netdev_priv(dev);
1551 struct timer_list *timer = &tp->timer;
1552 void __iomem *ioaddr = tp->mmio_addr;
1553 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1554
bcf0bf90 1555 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 1556
64e4bfb4 1557 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1558 return;
1559
1560 spin_lock_irq(&tp->lock);
1561
1562 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1563 /*
1da177e4
LT		 1564 * A busy loop could burn quite a few cycles on nowadays CPU.
1565 * Let's delay the execution of the timer for a few ticks.
1566 */
1567 timeout = HZ/10;
1568 goto out_mod_timer;
1569 }
1570
1571 if (tp->link_ok(ioaddr))
1572 goto out_unlock;
1573
b57b7e5a
SH		 1574 if (netif_msg_link(tp))
1575 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1576
1577 tp->phy_reset_enable(ioaddr);
1578
1579out_mod_timer:
1580 mod_timer(timer, jiffies + timeout);
1581out_unlock:
1582 spin_unlock_irq(&tp->lock);
1583}
1584
1585static inline void rtl8169_delete_timer(struct net_device *dev)
1586{
1587 struct rtl8169_private *tp = netdev_priv(dev);
1588 struct timer_list *timer = &tp->timer;
1589
e179bb7b 1590 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1591 return;
1592
1593 del_timer_sync(timer);
1594}
1595
1596static inline void rtl8169_request_timer(struct net_device *dev)
1597{
1598 struct rtl8169_private *tp = netdev_priv(dev);
1599 struct timer_list *timer = &tp->timer;
1600
e179bb7b 1601 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1602 return;
1603
2efa53f3 1604 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1605}
1606
1607#ifdef CONFIG_NET_POLL_CONTROLLER
1608/*
1609 * Polling 'interrupt' - used by things like netconsole to send skbs
1610 * without having to re-enable interrupts. It's not called while
1611 * the interrupt routine is executing.
1612 */
1613static void rtl8169_netpoll(struct net_device *dev)
1614{
1615 struct rtl8169_private *tp = netdev_priv(dev);
1616 struct pci_dev *pdev = tp->pci_dev;
1617
1618 disable_irq(pdev->irq);
7d12e780 1619 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1620 enable_irq(pdev->irq);
1621}
1622#endif
1623
1624static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1625 void __iomem *ioaddr)
1626{
1627 iounmap(ioaddr);
1628 pci_release_regions(pdev);
1629 pci_disable_device(pdev);
1630 free_netdev(dev);
1631}
1632
bf793295
FR		 1633static void rtl8169_phy_reset(struct net_device *dev,
1634 struct rtl8169_private *tp)
1635{
1636 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1637 unsigned int i;
bf793295
FR		 1638
1639 tp->phy_reset_enable(ioaddr);
1640 for (i = 0; i < 100; i++) {
1641 if (!tp->phy_reset_pending(ioaddr))
1642 return;
1643 msleep(1);
1644 }
1645 if (netif_msg_link(tp))
1646 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1647}
1648
4ff96fa6
FR		 1649static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1650{
1651 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 1652
5615d9f1 1653 rtl_hw_phy_config(dev);
4ff96fa6 1654
77332894
MS		 1655 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1656 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1657 RTL_W8(0x82, 0x01);
1658 }
4ff96fa6 1659
6dccd16b
FR		 1660 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1661
1662 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1663 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1664
bcf0bf90 1665 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1666 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1667 RTL_W8(0x82, 0x01);
1668 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1669 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1670 }
1671
bf793295
FR		 1672 rtl8169_phy_reset(dev, tp);
1673
901dda2b
FR		 1674 /*
1675 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1676 * only 8101. Don't panic.
1677 */
1678 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6
FR		 1679
1680 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1681 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1682}
1683
773d2021
FR		 1684static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1685{
1686 void __iomem *ioaddr = tp->mmio_addr;
1687 u32 high;
1688 u32 low;
1689
1690 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1691 high = addr[4] | (addr[5] << 8);
1692
1693 spin_lock_irq(&tp->lock);
1694
1695 RTL_W8(Cfg9346, Cfg9346_Unlock);
1696 RTL_W32(MAC0, low);
1697 RTL_W32(MAC4, high);
1698 RTL_W8(Cfg9346, Cfg9346_Lock);
1699
1700 spin_unlock_irq(&tp->lock);
1701}
1702
1703static int rtl_set_mac_address(struct net_device *dev, void *p)
1704{
1705 struct rtl8169_private *tp = netdev_priv(dev);
1706 struct sockaddr *addr = p;
1707
1708 if (!is_valid_ether_addr(addr->sa_data))
1709 return -EADDRNOTAVAIL;
1710
1711 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1712
1713 rtl_rar_set(tp, dev->dev_addr);
1714
1715 return 0;
1716}
1717
5f787a1a
FR		 1718static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1719{
1720 struct rtl8169_private *tp = netdev_priv(dev);
1721 struct mii_ioctl_data *data = if_mii(ifr);
1722
1723 if (!netif_running(dev))
1724 return -ENODEV;
1725
1726 switch (cmd) {
1727 case SIOCGMIIPHY:
1728 data->phy_id = 32; /* Internal PHY */
1729 return 0;
1730
1731 case SIOCGMIIREG:
1732 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1733 return 0;
1734
1735 case SIOCSMIIREG:
1736 if (!capable(CAP_NET_ADMIN))
1737 return -EPERM;
1738 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1739 return 0;
1740 }
1741 return -EOPNOTSUPP;
1742}
1743
0e485150
FR		 1744static const struct rtl_cfg_info {
1745 void (*hw_start)(struct net_device *);
1746 unsigned int region;
1747 unsigned int align;
1748 u16 intr_event;
1749 u16 napi_event;
ccdffb9a 1750 unsigned features;
0e485150
FR		 1751} rtl_cfg_infos [] = {
1752 [RTL_CFG_0] = {
1753 .hw_start = rtl_hw_start_8169,
1754 .region = 1,
e9f63f30 1755 .align = 0,
0e485150
FR		 1756 .intr_event = SYSErr | LinkChg | RxOverflow |
1757 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 1758 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1759 .features = RTL_FEATURE_GMII
0e485150
FR		 1760 },
1761 [RTL_CFG_1] = {
1762 .hw_start = rtl_hw_start_8168,
1763 .region = 2,
1764 .align = 8,
1765 .intr_event = SYSErr | LinkChg | RxOverflow |
1766 TxErr | TxOK | RxOK | RxErr,
fbac58fc 1767 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1768 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI
0e485150
FR		 1769 },
1770 [RTL_CFG_2] = {
1771 .hw_start = rtl_hw_start_8101,
1772 .region = 2,
1773 .align = 8,
1774 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1775 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 1776 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1777 .features = RTL_FEATURE_MSI
0e485150
FR		 1778 }
1779};
1780
fbac58fc
FR		 1781/* Cfg9346_Unlock assumed. */
1782static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1783 const struct rtl_cfg_info *cfg)
1784{
1785 unsigned msi = 0;
1786 u8 cfg2;
1787
1788 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 1789 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 1790 if (pci_enable_msi(pdev)) {
1791 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1792 } else {
1793 cfg2 |= MSIEnable;
1794 msi = RTL_FEATURE_MSI;
1795 }
1796 }
1797 RTL_W8(Config2, cfg2);
1798 return msi;
1799}
1800
1801static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1802{
1803 if (tp->features & RTL_FEATURE_MSI) {
1804 pci_disable_msi(pdev);
1805 tp->features &= ~RTL_FEATURE_MSI;
1806 }
1807}
1808
7bf6bf48
IV		 1809static int rtl_eeprom_read(struct pci_dev *pdev, int cap, int addr, __le32 *val)
1810{
1811 int ret, count = 100;
1812 u16 status = 0;
1813 u32 value;
1814
1815 ret = pci_write_config_word(pdev, cap + PCI_VPD_ADDR, addr);
1816 if (ret < 0)
1817 return ret;
1818
1819 do {
1820 udelay(10);
1821 ret = pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &status);
1822 if (ret < 0)
1823 return ret;
1824 } while (!(status & PCI_VPD_ADDR_F) && --count);
1825
1826 if (!(status & PCI_VPD_ADDR_F))
1827 return -ETIMEDOUT;
1828
1829 ret = pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &value);
1830 if (ret < 0)
1831 return ret;
1832
1833 *val = cpu_to_le32(value);
1834
1835 return 0;
1836}
1837
1838static void rtl_init_mac_address(struct rtl8169_private *tp,
1839 void __iomem *ioaddr)
1840{
1841 struct pci_dev *pdev = tp->pci_dev;
1842 u8 cfg1;
1843 int vpd_cap;
1844 u8 mac[8];
1845 DECLARE_MAC_BUF(buf);
1846
1847 cfg1 = RTL_R8(Config1);
1848 if (!(cfg1 & VPD)) {
1849 dprintk("VPD access not enabled, enabling\n");
1850 RTL_W8(Cfg9346, Cfg9346_Unlock);
1851 RTL_W8(Config1, cfg1 | VPD);
1852 RTL_W8(Cfg9346, Cfg9346_Lock);
1853 }
1854
1855 vpd_cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
1856 if (!vpd_cap)
1857 return;
1858
1859 /* MAC address is stored in EEPROM at offset 0x0e
1860 * Realtek says: "The VPD address does not have to be a DWORD-aligned
1861 * address as defined in the PCI 2.2 Specifications, but the VPD data
1862 * is always consecutive 4-byte data starting from the VPD address
1863 * specified."
1864 */
1865 if (rtl_eeprom_read(pdev, vpd_cap, 0x000e, (__le32*)&mac[0]) < 0 ||
1866 rtl_eeprom_read(pdev, vpd_cap, 0x0012, (__le32*)&mac[4]) < 0) {
1867 dprintk("Reading MAC address from EEPROM failed\n");
1868 return;
1869 }
1870
1871 dprintk("MAC address found in EEPROM: %s\n", print_mac(buf, mac));
1872
1873 /* Write MAC address */
1874 rtl_rar_set(tp, mac);
1875}
1876
1da177e4 1877static int __devinit
4ff96fa6 1878rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1879{
0e485150
FR		 1880 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1881 const unsigned int region = cfg->region;
1da177e4 1882 struct rtl8169_private *tp;
ccdffb9a 1883 struct mii_if_info *mii;
4ff96fa6
FR		 1884 struct net_device *dev;
1885 void __iomem *ioaddr;
07d3f51f
FR		 1886 unsigned int i;
1887 int rc;
1da177e4 1888
4ff96fa6
FR		 1889 if (netif_msg_drv(&debug)) {
1890 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1891 MODULENAME, RTL8169_VERSION);
1892 }
1da177e4 1893
1da177e4 1894 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 1895 if (!dev) {
b57b7e5a 1896 if (netif_msg_drv(&debug))
9b91cf9d 1897 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 1898 rc = -ENOMEM;
1899 goto out;
1da177e4
LT		 1900 }
1901
1da177e4
LT		 1902 SET_NETDEV_DEV(dev, &pdev->dev);
1903 tp = netdev_priv(dev);
c4028958 1904 tp->dev = dev;
21e197f2 1905 tp->pci_dev = pdev;
b57b7e5a 1906 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 1907
ccdffb9a
FR		 1908 mii = &tp->mii;
1909 mii->dev = dev;
1910 mii->mdio_read = rtl_mdio_read;
1911 mii->mdio_write = rtl_mdio_write;
1912 mii->phy_id_mask = 0x1f;
1913 mii->reg_num_mask = 0x1f;
1914 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
1915
1da177e4
LT		 1916 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1917 rc = pci_enable_device(pdev);
b57b7e5a 1918 if (rc < 0) {
2e8a538d 1919 if (netif_msg_probe(tp))
9b91cf9d 1920 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 1921 goto err_out_free_dev_1;
1da177e4
LT		 1922 }
1923
1924 rc = pci_set_mwi(pdev);
1925 if (rc < 0)
4ff96fa6 1926 goto err_out_disable_2;
1da177e4 1927
1da177e4 1928 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 1929 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 1930 if (netif_msg_probe(tp)) {
9b91cf9d 1931 dev_err(&pdev->dev,
bcf0bf90
FR		 1932 "region #%d not an MMIO resource, aborting\n",
1933 region);
4ff96fa6 1934 }
1da177e4 1935 rc = -ENODEV;
4ff96fa6 1936 goto err_out_mwi_3;
1da177e4 1937 }
4ff96fa6 1938
1da177e4 1939 /* check for weird/broken PCI region reporting */
bcf0bf90 1940 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 1941 if (netif_msg_probe(tp)) {
9b91cf9d 1942 dev_err(&pdev->dev,
4ff96fa6
FR		 1943 "Invalid PCI region size(s), aborting\n");
1944 }
1da177e4 1945 rc = -ENODEV;
4ff96fa6 1946 goto err_out_mwi_3;
1da177e4
LT		 1947 }
1948
1949 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 1950 if (rc < 0) {
2e8a538d 1951 if (netif_msg_probe(tp))
9b91cf9d 1952 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 1953 goto err_out_mwi_3;
1da177e4
LT		 1954 }
1955
1956 tp->cp_cmd = PCIMulRW | RxChkSum;
1957
1958 if ((sizeof(dma_addr_t) > 4) &&
1959 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1960 tp->cp_cmd |= PCIDAC;
1961 dev->features |= NETIF_F_HIGHDMA;
1962 } else {
1963 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1964 if (rc < 0) {
4ff96fa6 1965 if (netif_msg_probe(tp)) {
9b91cf9d 1966 dev_err(&pdev->dev,
4ff96fa6
FR		 1967 "DMA configuration failed.\n");
1968 }
1969 goto err_out_free_res_4;
1da177e4
LT		 1970 }
1971 }
1972
1973 pci_set_master(pdev);
1974
1975 /* ioremap MMIO region */
bcf0bf90 1976 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 1977 if (!ioaddr) {
b57b7e5a 1978 if (netif_msg_probe(tp))
9b91cf9d 1979 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 1980 rc = -EIO;
4ff96fa6 1981 goto err_out_free_res_4;
1da177e4
LT		 1982 }
1983
9c14ceaf
FR		 1984 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1985 if (!tp->pcie_cap && netif_msg_probe(tp))
1986 dev_info(&pdev->dev, "no PCI Express capability\n");
1987
1da177e4
LT		 1988 /* Unneeded ? Don't mess with Mrs. Murphy. */
1989 rtl8169_irq_mask_and_ack(ioaddr);
1990
1991 /* Soft reset the chip. */
1992 RTL_W8(ChipCmd, CmdReset);
1993
1994 /* Check that the chip has finished the reset. */
07d3f51f 1995 for (i = 0; i < 100; i++) {
1da177e4
LT		 1996 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1997 break;
b518fa8e 1998 msleep_interruptible(1);
1da177e4
LT		 1999 }
2000
2001 /* Identify chip attached to board */
2002 rtl8169_get_mac_version(tp, ioaddr);
1da177e4
LT		 2003
2004 rtl8169_print_mac_version(tp);
1da177e4 2005
cee60c37 2006 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 2007 if (tp->mac_version == rtl_chip_info[i].mac_version)
2008 break;
2009 }
cee60c37 2010 if (i == ARRAY_SIZE(rtl_chip_info)) {
1da177e4 2011 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 2012 if (netif_msg_probe(tp)) {
2e8a538d 2013 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 2014 "unknown chip version, assuming %s\n",
2015 rtl_chip_info[0].name);
b57b7e5a 2016 }
cee60c37 2017 i = 0;
1da177e4
LT		 2018 }
2019 tp->chipset = i;
2020
5d06a99f
FR		 2021 RTL_W8(Cfg9346, Cfg9346_Unlock);
2022 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2023 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 2024 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2025 tp->features |= RTL_FEATURE_WOL;
2026 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2027 tp->features |= RTL_FEATURE_WOL;
fbac58fc 2028 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 2029 RTL_W8(Cfg9346, Cfg9346_Lock);
2030
66ec5d4f
FR		 2031 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2032 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 2033 tp->set_speed = rtl8169_set_speed_tbi;
2034 tp->get_settings = rtl8169_gset_tbi;
2035 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2036 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2037 tp->link_ok = rtl8169_tbi_link_ok;
2038
64e4bfb4 2039 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 2040 } else {
2041 tp->set_speed = rtl8169_set_speed_xmii;
2042 tp->get_settings = rtl8169_gset_xmii;
2043 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2044 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2045 tp->link_ok = rtl8169_xmii_link_ok;
5f787a1a
FR		 2046
2047 dev->do_ioctl = rtl8169_ioctl;
1da177e4
LT		 2048 }
2049
df58ef51
FR		 2050 spin_lock_init(&tp->lock);
2051
7bf6bf48
IV		 2052 rtl_init_mac_address(tp, ioaddr);
2053
2054 /* Get MAC address */
1da177e4
LT		 2055 for (i = 0; i < MAC_ADDR_LEN; i++)
2056 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 2057 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 2058
2059 dev->open = rtl8169_open;
2060 dev->hard_start_xmit = rtl8169_start_xmit;
2061 dev->get_stats = rtl8169_get_stats;
2062 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
2063 dev->stop = rtl8169_close;
2064 dev->tx_timeout = rtl8169_tx_timeout;
07ce4064 2065 dev->set_multicast_list = rtl_set_rx_mode;
1da177e4
LT		 2066 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2067 dev->irq = pdev->irq;
2068 dev->base_addr = (unsigned long) ioaddr;
2069 dev->change_mtu = rtl8169_change_mtu;
773d2021 2070 dev->set_mac_address = rtl_set_mac_address;
1da177e4 2071
bea3348e 2072 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 2073
2074#ifdef CONFIG_R8169_VLAN
2075 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2076 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1da177e4
LT		 2077#endif
2078
2079#ifdef CONFIG_NET_POLL_CONTROLLER
2080 dev->poll_controller = rtl8169_netpoll;
2081#endif
2082
2083 tp->intr_mask = 0xffff;
1da177e4 2084 tp->mmio_addr = ioaddr;
0e485150
FR		 2085 tp->align = cfg->align;
2086 tp->hw_start = cfg->hw_start;
2087 tp->intr_event = cfg->intr_event;
2088 tp->napi_event = cfg->napi_event;
1da177e4 2089
2efa53f3
FR		 2090 init_timer(&tp->timer);
2091 tp->timer.data = (unsigned long) dev;
2092 tp->timer.function = rtl8169_phy_timer;
2093
1da177e4 2094 rc = register_netdev(dev);
4ff96fa6 2095 if (rc < 0)
fbac58fc 2096 goto err_out_msi_5;
1da177e4
LT		 2097
2098 pci_set_drvdata(pdev, dev);
2099
b57b7e5a 2100 if (netif_msg_probe(tp)) {
96b9709c
FR		 2101 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
2102
b57b7e5a
SH		 2103 printk(KERN_INFO "%s: %s at 0x%lx, "
2104 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
96b9709c 2105 "XID %08x IRQ %d\n",
b57b7e5a 2106 dev->name,
bcf0bf90 2107 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 2108 dev->base_addr,
2109 dev->dev_addr[0], dev->dev_addr[1],
2110 dev->dev_addr[2], dev->dev_addr[3],
96b9709c 2111 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
b57b7e5a 2112 }
1da177e4 2113
4ff96fa6 2114 rtl8169_init_phy(dev, tp);
8b76ab39 2115 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 2116
4ff96fa6
FR		 2117out:
2118 return rc;
1da177e4 2119
fbac58fc
FR		 2120err_out_msi_5:
2121 rtl_disable_msi(pdev, tp);
4ff96fa6
FR		 2122 iounmap(ioaddr);
2123err_out_free_res_4:
2124 pci_release_regions(pdev);
2125err_out_mwi_3:
2126 pci_clear_mwi(pdev);
2127err_out_disable_2:
2128 pci_disable_device(pdev);
2129err_out_free_dev_1:
2130 free_netdev(dev);
2131 goto out;
1da177e4
LT		 2132}
2133
07d3f51f 2134static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 2135{
2136 struct net_device *dev = pci_get_drvdata(pdev);
2137 struct rtl8169_private *tp = netdev_priv(dev);
2138
eb2a021c
FR		 2139 flush_scheduled_work();
2140
1da177e4 2141 unregister_netdev(dev);
fbac58fc 2142 rtl_disable_msi(pdev, tp);
1da177e4
LT		 2143 rtl8169_release_board(pdev, dev, tp->mmio_addr);
2144 pci_set_drvdata(pdev, NULL);
2145}
2146
1da177e4
LT		 2147static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2148 struct net_device *dev)
2149{
2150 unsigned int mtu = dev->mtu;
2151
2152 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2153}
2154
2155static int rtl8169_open(struct net_device *dev)
2156{
2157 struct rtl8169_private *tp = netdev_priv(dev);
2158 struct pci_dev *pdev = tp->pci_dev;
99f252b0 2159 int retval = -ENOMEM;
1da177e4 2160
1da177e4 2161
99f252b0 2162 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 2163
2164 /*
2165 * Rx and Tx desscriptors needs 256 bytes alignment.
2166 * pci_alloc_consistent provides more.
2167 */
2168 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2169 &tp->TxPhyAddr);
2170 if (!tp->TxDescArray)
99f252b0 2171 goto out;
1da177e4
LT		 2172
2173 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2174 &tp->RxPhyAddr);
2175 if (!tp->RxDescArray)
99f252b0 2176 goto err_free_tx_0;
1da177e4
LT		 2177
2178 retval = rtl8169_init_ring(dev);
2179 if (retval < 0)
99f252b0 2180 goto err_free_rx_1;
1da177e4 2181
c4028958 2182 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 2183
99f252b0
FR		 2184 smp_mb();
2185
fbac58fc
FR		 2186 retval = request_irq(dev->irq, rtl8169_interrupt,
2187 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 2188 dev->name, dev);
2189 if (retval < 0)
2190 goto err_release_ring_2;
2191
bea3348e 2192 napi_enable(&tp->napi);
bea3348e 2193
07ce4064 2194 rtl_hw_start(dev);
1da177e4
LT		 2195
2196 rtl8169_request_timer(dev);
2197
2198 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2199out:
2200 return retval;
2201
99f252b0
FR		 2202err_release_ring_2:
2203 rtl8169_rx_clear(tp);
2204err_free_rx_1:
1da177e4
LT		 2205 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2206 tp->RxPhyAddr);
99f252b0 2207err_free_tx_0:
1da177e4
LT		 2208 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2209 tp->TxPhyAddr);
1da177e4
LT		 2210 goto out;
2211}
2212
2213static void rtl8169_hw_reset(void __iomem *ioaddr)
2214{
2215 /* Disable interrupts */
2216 rtl8169_irq_mask_and_ack(ioaddr);
2217
2218 /* Reset the chipset */
2219 RTL_W8(ChipCmd, CmdReset);
2220
2221 /* PCI commit */
2222 RTL_R8(ChipCmd);
2223}
2224
7f796d83 2225static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 2226{
2227 void __iomem *ioaddr = tp->mmio_addr;
2228 u32 cfg = rtl8169_rx_config;
2229
2230 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2231 RTL_W32(RxConfig, cfg);
2232
2233 /* Set DMA burst size and Interframe Gap Time */
2234 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2235 (InterFrameGap << TxInterFrameGapShift));
2236}
2237
07ce4064 2238static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 2239{
2240 struct rtl8169_private *tp = netdev_priv(dev);
2241 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 2242 unsigned int i;
1da177e4
LT		 2243
2244 /* Soft reset the chip. */
2245 RTL_W8(ChipCmd, CmdReset);
2246
2247 /* Check that the chip has finished the reset. */
07d3f51f 2248 for (i = 0; i < 100; i++) {
1da177e4
LT		 2249 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2250 break;
b518fa8e 2251 msleep_interruptible(1);
1da177e4
LT		 2252 }
2253
07ce4064
FR		 2254 tp->hw_start(dev);
2255
07ce4064
FR		 2256 netif_start_queue(dev);
2257}
2258
2259
7f796d83
FR		 2260static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2261 void __iomem *ioaddr)
2262{
2263 /*
2264 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2265 * register to be written before TxDescAddrLow to work.
2266 * Switching from MMIO to I/O access fixes the issue as well.
2267 */
2268 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2269 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
2270 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2271 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
2272}
2273
2274static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2275{
2276 u16 cmd;
2277
2278 cmd = RTL_R16(CPlusCmd);
2279 RTL_W16(CPlusCmd, cmd);
2280 return cmd;
2281}
2282
2283static void rtl_set_rx_max_size(void __iomem *ioaddr)
2284{
2285 /* Low hurts. Let's disable the filtering. */
2286 RTL_W16(RxMaxSize, 16383);
2287}
2288
6dccd16b
FR		 2289static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2290{
2291 struct {
2292 u32 mac_version;
2293 u32 clk;
2294 u32 val;
2295 } cfg2_info [] = {
2296 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2297 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2298 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2299 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2300 }, *p = cfg2_info;
2301 unsigned int i;
2302 u32 clk;
2303
2304 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 2305 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 2306 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2307 RTL_W32(0x7c, p->val);
2308 break;
2309 }
2310 }
2311}
2312
07ce4064
FR		 2313static void rtl_hw_start_8169(struct net_device *dev)
2314{
2315 struct rtl8169_private *tp = netdev_priv(dev);
2316 void __iomem *ioaddr = tp->mmio_addr;
2317 struct pci_dev *pdev = tp->pci_dev;
07ce4064 2318
9cb427b6
FR		 2319 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2320 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2321 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2322 }
2323
1da177e4 2324 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 2325 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2326 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2327 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2328 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2329 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2330
1da177e4
LT		 2331 RTL_W8(EarlyTxThres, EarlyTxThld);
2332
7f796d83 2333 rtl_set_rx_max_size(ioaddr);
1da177e4 2334
c946b304
FR		 2335 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2336 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2337 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2338 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2339 rtl_set_rx_tx_config_registers(tp);
1da177e4 2340
7f796d83 2341 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 2342
bcf0bf90
FR		 2343 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2344 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 2345 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 2346 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 2347 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 2348 }
2349
bcf0bf90
FR		 2350 RTL_W16(CPlusCmd, tp->cp_cmd);
2351
6dccd16b
FR		 2352 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2353
1da177e4
LT		 2354 /*
2355 * Undocumented corner. Supposedly:
2356 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2357 */
2358 RTL_W16(IntrMitigate, 0x0000);
2359
7f796d83 2360 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 2361
c946b304
FR		 2362 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2363 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2364 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2365 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2366 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2367 rtl_set_rx_tx_config_registers(tp);
2368 }
2369
1da177e4 2370 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 2371
2372 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2373 RTL_R8(IntrMask);
1da177e4
LT		 2374
2375 RTL_W32(RxMissed, 0);
2376
07ce4064 2377 rtl_set_rx_mode(dev);
1da177e4
LT		 2378
2379 /* no early-rx interrupts */
2380 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 2381
2382 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 2383 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2384}
1da177e4 2385
9c14ceaf 2386static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 2387{
9c14ceaf
FR		 2388 struct net_device *dev = pci_get_drvdata(pdev);
2389 struct rtl8169_private *tp = netdev_priv(dev);
2390 int cap = tp->pcie_cap;
2391
2392 if (cap) {
2393 u16 ctl;
458a9f61 2394
9c14ceaf
FR		 2395 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2396 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2397 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2398 }
458a9f61
FR		 2399}
2400
dacf8154
FR		 2401static void rtl_csi_access_enable(void __iomem *ioaddr)
2402{
2403 u32 csi;
2404
2405 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2406 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2407}
2408
2409struct ephy_info {
2410 unsigned int offset;
2411 u16 mask;
2412 u16 bits;
2413};
2414
2415static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2416{
2417 u16 w;
2418
2419 while (len-- > 0) {
2420 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2421 rtl_ephy_write(ioaddr, e->offset, w);
2422 e++;
2423 }
2424}
2425
b726e493
FR		 2426static void rtl_disable_clock_request(struct pci_dev *pdev)
2427{
2428 struct net_device *dev = pci_get_drvdata(pdev);
2429 struct rtl8169_private *tp = netdev_priv(dev);
2430 int cap = tp->pcie_cap;
2431
2432 if (cap) {
2433 u16 ctl;
2434
2435 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
2436 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
2437 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
2438 }
2439}
2440
2441#define R8168_CPCMD_QUIRK_MASK (\
2442 EnableBist | \
2443 Mac_dbgo_oe | \
2444 Force_half_dup | \
2445 Force_rxflow_en | \
2446 Force_txflow_en | \
2447 Cxpl_dbg_sel | \
2448 ASF | \
2449 PktCntrDisable | \
2450 Mac_dbgo_sel)
2451
219a1e9d
FR		 2452static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
2453{
b726e493
FR		 2454 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2455
2456 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2457
2e68ae44
FR		 2458 rtl_tx_performance_tweak(pdev,
2459 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 2460}
2461
2462static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
2463{
2464 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493
FR		 2465
2466 RTL_W8(EarlyTxThres, EarlyTxThld);
2467
2468 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 2469}
2470
2471static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2472{
b726e493
FR		 2473 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
2474
2475 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2476
219a1e9d 2477 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 2478
2479 rtl_disable_clock_request(pdev);
2480
2481 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 2482}
2483
2484static void rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2485{
b726e493
FR		 2486 static struct ephy_info e_info_8168cp[] = {
2487 { 0x01, 0, 0x0001 },
2488 { 0x02, 0x0800, 0x1000 },
2489 { 0x03, 0, 0x0042 },
2490 { 0x06, 0x0080, 0x0000 },
2491 { 0x07, 0, 0x2000 }
2492 };
2493
2494 rtl_csi_access_enable(ioaddr);
2495
2496 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
2497
219a1e9d
FR		 2498 __rtl_hw_start_8168cp(ioaddr, pdev);
2499}
2500
2501static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
2502{
b726e493
FR		 2503 static struct ephy_info e_info_8168c_1[] = {
2504 { 0x02, 0x0800, 0x1000 },
2505 { 0x03, 0, 0x0002 },
2506 { 0x06, 0x0080, 0x0000 }
2507 };
2508
2509 rtl_csi_access_enable(ioaddr);
2510
2511 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2512
2513 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
2514
219a1e9d
FR		 2515 __rtl_hw_start_8168cp(ioaddr, pdev);
2516}
2517
2518static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
2519{
b726e493
FR		 2520 static struct ephy_info e_info_8168c_2[] = {
2521 { 0x01, 0, 0x0001 },
2522 { 0x03, 0x0400, 0x0220 }
2523 };
2524
2525 rtl_csi_access_enable(ioaddr);
2526
2527 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
2528
219a1e9d
FR		 2529 __rtl_hw_start_8168cp(ioaddr, pdev);
2530}
2531
197ff761
FR		 2532static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
2533{
2534 rtl_hw_start_8168c_2(ioaddr, pdev);
2535}
2536
6fb07058
FR		 2537static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
2538{
2539 rtl_csi_access_enable(ioaddr);
2540
2541 __rtl_hw_start_8168cp(ioaddr, pdev);
2542}
2543
07ce4064
FR		 2544static void rtl_hw_start_8168(struct net_device *dev)
2545{
2dd99530
FR		 2546 struct rtl8169_private *tp = netdev_priv(dev);
2547 void __iomem *ioaddr = tp->mmio_addr;
0e485150 2548 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 2549
2550 RTL_W8(Cfg9346, Cfg9346_Unlock);
2551
2552 RTL_W8(EarlyTxThres, EarlyTxThld);
2553
2554 rtl_set_rx_max_size(ioaddr);
2555
0e485150 2556 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 2557
2558 RTL_W16(CPlusCmd, tp->cp_cmd);
2559
0e485150 2560 RTL_W16(IntrMitigate, 0x5151);
2dd99530 2561
0e485150
FR		 2562 /* Work around for RxFIFO overflow. */
2563 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2564 tp->intr_event |= RxFIFOOver | PCSTimeout;
2565 tp->intr_event &= ~RxOverflow;
2566 }
2567
2568 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 2569
b8363901
FR		 2570 rtl_set_rx_mode(dev);
2571
2572 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2573 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 2574
2575 RTL_R8(IntrMask);
2576
219a1e9d
FR		 2577 switch (tp->mac_version) {
2578 case RTL_GIGA_MAC_VER_11:
2579 rtl_hw_start_8168bb(ioaddr, pdev);
2580 break;
2581
2582 case RTL_GIGA_MAC_VER_12:
2583 case RTL_GIGA_MAC_VER_17:
2584 rtl_hw_start_8168bef(ioaddr, pdev);
2585 break;
2586
2587 case RTL_GIGA_MAC_VER_18:
2588 rtl_hw_start_8168cp(ioaddr, pdev);
2589 break;
2590
2591 case RTL_GIGA_MAC_VER_19:
2592 rtl_hw_start_8168c_1(ioaddr, pdev);
2593 break;
2594
2595 case RTL_GIGA_MAC_VER_20:
2596 rtl_hw_start_8168c_2(ioaddr, pdev);
2597 break;
2598
197ff761
FR		 2599 case RTL_GIGA_MAC_VER_21:
2600 rtl_hw_start_8168c_3(ioaddr, pdev);
2601 break;
2602
6fb07058
FR		 2603 case RTL_GIGA_MAC_VER_22:
2604 rtl_hw_start_8168c_4(ioaddr, pdev);
2605 break;
2606
219a1e9d
FR		 2607 default:
2608 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
2609 dev->name, tp->mac_version);
2610 break;
2611 }
2dd99530 2612
0e485150
FR		 2613 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2614
b8363901
FR		 2615 RTL_W8(Cfg9346, Cfg9346_Lock);
2616
2dd99530 2617 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 2618
0e485150 2619 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2620}
1da177e4 2621
2857ffb7
FR		 2622#define R810X_CPCMD_QUIRK_MASK (\
2623 EnableBist | \
2624 Mac_dbgo_oe | \
2625 Force_half_dup | \
2626 Force_half_dup | \
2627 Force_txflow_en | \
2628 Cxpl_dbg_sel | \
2629 ASF | \
2630 PktCntrDisable | \
2631 PCIDAC | \
2632 PCIMulRW)
2633
2634static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2635{
2636 static struct ephy_info e_info_8102e_1[] = {
2637 { 0x01, 0, 0x6e65 },
2638 { 0x02, 0, 0x091f },
2639 { 0x03, 0, 0xc2f9 },
2640 { 0x06, 0, 0xafb5 },
2641 { 0x07, 0, 0x0e00 },
2642 { 0x19, 0, 0xec80 },
2643 { 0x01, 0, 0x2e65 },
2644 { 0x01, 0, 0x6e65 }
2645 };
2646 u8 cfg1;
2647
2648 rtl_csi_access_enable(ioaddr);
2649
2650 RTL_W8(DBG_REG, FIX_NAK_1);
2651
2652 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2653
2654 RTL_W8(Config1,
2655 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2656 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2657
2658 cfg1 = RTL_R8(Config1);
2659 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2660 RTL_W8(Config1, cfg1 & ~LEDS0);
2661
2662 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2663
2664 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2665}
2666
2667static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2668{
2669 rtl_csi_access_enable(ioaddr);
2670
2671 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2672
2673 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2674 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2675
2676 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2677}
2678
2679static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2680{
2681 rtl_hw_start_8102e_2(ioaddr, pdev);
2682
2683 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2684}
2685
07ce4064
FR		 2686static void rtl_hw_start_8101(struct net_device *dev)
2687{
cdf1a608
FR		 2688 struct rtl8169_private *tp = netdev_priv(dev);
2689 void __iomem *ioaddr = tp->mmio_addr;
2690 struct pci_dev *pdev = tp->pci_dev;
2691
e3cf0cc0
FR		 2692 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2693 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 2694 int cap = tp->pcie_cap;
2695
2696 if (cap) {
2697 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2698 PCI_EXP_DEVCTL_NOSNOOP_EN);
2699 }
cdf1a608
FR		 2700 }
2701
2857ffb7
FR		 2702 switch (tp->mac_version) {
2703 case RTL_GIGA_MAC_VER_07:
2704 rtl_hw_start_8102e_1(ioaddr, pdev);
2705 break;
2706
2707 case RTL_GIGA_MAC_VER_08:
2708 rtl_hw_start_8102e_3(ioaddr, pdev);
2709 break;
2710
2711 case RTL_GIGA_MAC_VER_09:
2712 rtl_hw_start_8102e_2(ioaddr, pdev);
2713 break;
cdf1a608
FR		 2714 }
2715
2716 RTL_W8(Cfg9346, Cfg9346_Unlock);
2717
2718 RTL_W8(EarlyTxThres, EarlyTxThld);
2719
2720 rtl_set_rx_max_size(ioaddr);
2721
2722 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2723
2724 RTL_W16(CPlusCmd, tp->cp_cmd);
2725
2726 RTL_W16(IntrMitigate, 0x0000);
2727
2728 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2729
2730 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2731 rtl_set_rx_tx_config_registers(tp);
2732
2733 RTL_W8(Cfg9346, Cfg9346_Lock);
2734
2735 RTL_R8(IntrMask);
2736
cdf1a608
FR		 2737 rtl_set_rx_mode(dev);
2738
0e485150
FR		 2739 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2740
cdf1a608 2741 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 2742
0e485150 2743 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2744}
2745
2746static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2747{
2748 struct rtl8169_private *tp = netdev_priv(dev);
2749 int ret = 0;
2750
2751 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2752 return -EINVAL;
2753
2754 dev->mtu = new_mtu;
2755
2756 if (!netif_running(dev))
2757 goto out;
2758
2759 rtl8169_down(dev);
2760
2761 rtl8169_set_rxbufsize(tp, dev);
2762
2763 ret = rtl8169_init_ring(dev);
2764 if (ret < 0)
2765 goto out;
2766
bea3348e 2767 napi_enable(&tp->napi);
1da177e4 2768
07ce4064 2769 rtl_hw_start(dev);
1da177e4
LT		 2770
2771 rtl8169_request_timer(dev);
2772
2773out:
2774 return ret;
2775}
2776
2777static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2778{
95e0918d 2779 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 2780 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2781}
2782
2783static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2784 struct sk_buff **sk_buff, struct RxDesc *desc)
2785{
2786 struct pci_dev *pdev = tp->pci_dev;
2787
2788 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2789 PCI_DMA_FROMDEVICE);
2790 dev_kfree_skb(*sk_buff);
2791 *sk_buff = NULL;
2792 rtl8169_make_unusable_by_asic(desc);
2793}
2794
2795static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2796{
2797 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2798
2799 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2800}
2801
2802static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2803 u32 rx_buf_sz)
2804{
2805 desc->addr = cpu_to_le64(mapping);
2806 wmb();
2807 rtl8169_mark_to_asic(desc, rx_buf_sz);
2808}
2809
15d31758
SH		 2810static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2811 struct net_device *dev,
2812 struct RxDesc *desc, int rx_buf_sz,
2813 unsigned int align)
1da177e4
LT		 2814{
2815 struct sk_buff *skb;
2816 dma_addr_t mapping;
e9f63f30 2817 unsigned int pad;
1da177e4 2818
e9f63f30
FR		 2819 pad = align ? align : NET_IP_ALIGN;
2820
2821 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 2822 if (!skb)
2823 goto err_out;
2824
e9f63f30 2825 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 2826
689be439 2827 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 2828 PCI_DMA_FROMDEVICE);
2829
2830 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 2831out:
15d31758 2832 return skb;
1da177e4
LT		 2833
2834err_out:
1da177e4
LT		 2835 rtl8169_make_unusable_by_asic(desc);
2836 goto out;
2837}
2838
2839static void rtl8169_rx_clear(struct rtl8169_private *tp)
2840{
07d3f51f 2841 unsigned int i;
1da177e4
LT		 2842
2843 for (i = 0; i < NUM_RX_DESC; i++) {
2844 if (tp->Rx_skbuff[i]) {
2845 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2846 tp->RxDescArray + i);
2847 }
2848 }
2849}
2850
2851static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2852 u32 start, u32 end)
2853{
2854 u32 cur;
5b0384f4 2855
4ae47c2d 2856 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 2857 struct sk_buff *skb;
2858 unsigned int i = cur % NUM_RX_DESC;
1da177e4 2859
4ae47c2d
FR		 2860 WARN_ON((s32)(end - cur) < 0);
2861
1da177e4
LT		 2862 if (tp->Rx_skbuff[i])
2863 continue;
bcf0bf90 2864
15d31758
SH		 2865 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2866 tp->RxDescArray + i,
2867 tp->rx_buf_sz, tp->align);
2868 if (!skb)
1da177e4 2869 break;
15d31758
SH		 2870
2871 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 2872 }
2873 return cur - start;
2874}
2875
2876static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2877{
2878 desc->opts1 |= cpu_to_le32(RingEnd);
2879}
2880
2881static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2882{
2883 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2884}
2885
2886static int rtl8169_init_ring(struct net_device *dev)
2887{
2888 struct rtl8169_private *tp = netdev_priv(dev);
2889
2890 rtl8169_init_ring_indexes(tp);
2891
2892 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2893 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2894
2895 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2896 goto err_out;
2897
2898 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2899
2900 return 0;
2901
2902err_out:
2903 rtl8169_rx_clear(tp);
2904 return -ENOMEM;
2905}
2906
2907static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2908 struct TxDesc *desc)
2909{
2910 unsigned int len = tx_skb->len;
2911
2912 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2913 desc->opts1 = 0x00;
2914 desc->opts2 = 0x00;
2915 desc->addr = 0x00;
2916 tx_skb->len = 0;
2917}
2918
2919static void rtl8169_tx_clear(struct rtl8169_private *tp)
2920{
2921 unsigned int i;
2922
2923 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2924 unsigned int entry = i % NUM_TX_DESC;
2925 struct ring_info *tx_skb = tp->tx_skb + entry;
2926 unsigned int len = tx_skb->len;
2927
2928 if (len) {
2929 struct sk_buff *skb = tx_skb->skb;
2930
2931 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2932 tp->TxDescArray + entry);
2933 if (skb) {
2934 dev_kfree_skb(skb);
2935 tx_skb->skb = NULL;
2936 }
cebf8cc7 2937 tp->dev->stats.tx_dropped++;
1da177e4
LT		 2938 }
2939 }
2940 tp->cur_tx = tp->dirty_tx = 0;
2941}
2942
c4028958 2943static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 2944{
2945 struct rtl8169_private *tp = netdev_priv(dev);
2946
c4028958 2947 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 2948 schedule_delayed_work(&tp->task, 4);
2949}
2950
2951static void rtl8169_wait_for_quiescence(struct net_device *dev)
2952{
2953 struct rtl8169_private *tp = netdev_priv(dev);
2954 void __iomem *ioaddr = tp->mmio_addr;
2955
2956 synchronize_irq(dev->irq);
2957
2958 /* Wait for any pending NAPI task to complete */
bea3348e 2959 napi_disable(&tp->napi);
1da177e4
LT		 2960
2961 rtl8169_irq_mask_and_ack(ioaddr);
2962
d1d08d12
DM		 2963 tp->intr_mask = 0xffff;
2964 RTL_W16(IntrMask, tp->intr_event);
bea3348e 2965 napi_enable(&tp->napi);
1da177e4
LT		 2966}
2967
c4028958 2968static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 2969{
c4028958
DH		 2970 struct rtl8169_private *tp =
2971 container_of(work, struct rtl8169_private, task.work);
2972 struct net_device *dev = tp->dev;
1da177e4
LT		 2973 int ret;
2974
eb2a021c
FR		 2975 rtnl_lock();
2976
2977 if (!netif_running(dev))
2978 goto out_unlock;
2979
2980 rtl8169_wait_for_quiescence(dev);
2981 rtl8169_close(dev);
1da177e4
LT		 2982
2983 ret = rtl8169_open(dev);
2984 if (unlikely(ret < 0)) {
07d3f51f 2985 if (net_ratelimit() && netif_msg_drv(tp)) {
53edbecd 2986 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
07d3f51f 2987 " Rescheduling.\n", dev->name, ret);
1da177e4
LT		 2988 }
2989 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2990 }
eb2a021c
FR		 2991
2992out_unlock:
2993 rtnl_unlock();
1da177e4
LT		 2994}
2995
c4028958 2996static void rtl8169_reset_task(struct work_struct *work)
1da177e4 2997{
c4028958
DH		 2998 struct rtl8169_private *tp =
2999 container_of(work, struct rtl8169_private, task.work);
3000 struct net_device *dev = tp->dev;
1da177e4 3001
eb2a021c
FR		 3002 rtnl_lock();
3003
1da177e4 3004 if (!netif_running(dev))
eb2a021c 3005 goto out_unlock;
1da177e4
LT		 3006
3007 rtl8169_wait_for_quiescence(dev);
3008
bea3348e 3009 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 3010 rtl8169_tx_clear(tp);
3011
3012 if (tp->dirty_rx == tp->cur_rx) {
3013 rtl8169_init_ring_indexes(tp);
07ce4064 3014 rtl_hw_start(dev);
1da177e4 3015 netif_wake_queue(dev);
cebf8cc7 3016 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 3017 } else {
07d3f51f 3018 if (net_ratelimit() && netif_msg_intr(tp)) {
53edbecd 3019 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
07d3f51f 3020 dev->name);
1da177e4
LT		 3021 }
3022 rtl8169_schedule_work(dev, rtl8169_reset_task);
3023 }
eb2a021c
FR		 3024
3025out_unlock:
3026 rtnl_unlock();
1da177e4
LT		 3027}
3028
3029static void rtl8169_tx_timeout(struct net_device *dev)
3030{
3031 struct rtl8169_private *tp = netdev_priv(dev);
3032
3033 rtl8169_hw_reset(tp->mmio_addr);
3034
3035 /* Let's wait a bit while any (async) irq lands on */
3036 rtl8169_schedule_work(dev, rtl8169_reset_task);
3037}
3038
3039static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3040 u32 opts1)
3041{
3042 struct skb_shared_info *info = skb_shinfo(skb);
3043 unsigned int cur_frag, entry;
a6343afb 3044 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 3045
3046 entry = tp->cur_tx;
3047 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3048 skb_frag_t *frag = info->frags + cur_frag;
3049 dma_addr_t mapping;
3050 u32 status, len;
3051 void *addr;
3052
3053 entry = (entry + 1) % NUM_TX_DESC;
3054
3055 txd = tp->TxDescArray + entry;
3056 len = frag->size;
3057 addr = ((void *) page_address(frag->page)) + frag->page_offset;
3058 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
3059
3060 /* anti gcc 2.95.3 bugware (sic) */
3061 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3062
3063 txd->opts1 = cpu_to_le32(status);
3064 txd->addr = cpu_to_le64(mapping);
3065
3066 tp->tx_skb[entry].len = len;
3067 }
3068
3069 if (cur_frag) {
3070 tp->tx_skb[entry].skb = skb;
3071 txd->opts1 |= cpu_to_le32(LastFrag);
3072 }
3073
3074 return cur_frag;
3075}
3076
3077static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
3078{
3079 if (dev->features & NETIF_F_TSO) {
7967168c 3080 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 3081
3082 if (mss)
3083 return LargeSend | ((mss & MSSMask) << MSSShift);
3084 }
84fa7933 3085 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 3086 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 3087
3088 if (ip->protocol == IPPROTO_TCP)
3089 return IPCS | TCPCS;
3090 else if (ip->protocol == IPPROTO_UDP)
3091 return IPCS | UDPCS;
3092 WARN_ON(1); /* we need a WARN() */
3093 }
3094 return 0;
3095}
3096
3097static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
3098{
3099 struct rtl8169_private *tp = netdev_priv(dev);
3100 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
3101 struct TxDesc *txd = tp->TxDescArray + entry;
3102 void __iomem *ioaddr = tp->mmio_addr;
3103 dma_addr_t mapping;
3104 u32 status, len;
3105 u32 opts1;
188f4af0 3106 int ret = NETDEV_TX_OK;
5b0384f4 3107
1da177e4 3108 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 3109 if (netif_msg_drv(tp)) {
3110 printk(KERN_ERR
3111 "%s: BUG! Tx Ring full when queue awake!\n",
3112 dev->name);
3113 }
1da177e4
LT		 3114 goto err_stop;
3115 }
3116
3117 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3118 goto err_stop;
3119
3120 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
3121
3122 frags = rtl8169_xmit_frags(tp, skb, opts1);
3123 if (frags) {
3124 len = skb_headlen(skb);
3125 opts1 |= FirstFrag;
3126 } else {
3127 len = skb->len;
3128
3129 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 3130 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 3131 goto err_update_stats;
3132 len = ETH_ZLEN;
3133 }
3134
3135 opts1 |= FirstFrag | LastFrag;
3136 tp->tx_skb[entry].skb = skb;
3137 }
3138
3139 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
3140
3141 tp->tx_skb[entry].len = len;
3142 txd->addr = cpu_to_le64(mapping);
3143 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
3144
3145 wmb();
3146
3147 /* anti gcc 2.95.3 bugware (sic) */
3148 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3149 txd->opts1 = cpu_to_le32(status);
3150
3151 dev->trans_start = jiffies;
3152
3153 tp->cur_tx += frags + 1;
3154
3155 smp_wmb();
3156
275391a4 3157 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 3158
3159 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
3160 netif_stop_queue(dev);
3161 smp_rmb();
3162 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
3163 netif_wake_queue(dev);
3164 }
3165
3166out:
3167 return ret;
3168
3169err_stop:
3170 netif_stop_queue(dev);
188f4af0 3171 ret = NETDEV_TX_BUSY;
1da177e4 3172err_update_stats:
cebf8cc7 3173 dev->stats.tx_dropped++;
1da177e4
LT		 3174 goto out;
3175}
3176
3177static void rtl8169_pcierr_interrupt(struct net_device *dev)
3178{
3179 struct rtl8169_private *tp = netdev_priv(dev);
3180 struct pci_dev *pdev = tp->pci_dev;
3181 void __iomem *ioaddr = tp->mmio_addr;
3182 u16 pci_status, pci_cmd;
3183
3184 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3185 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3186
b57b7e5a
SH		 3187 if (netif_msg_intr(tp)) {
3188 printk(KERN_ERR
3189 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3190 dev->name, pci_cmd, pci_status);
3191 }
1da177e4
LT		 3192
3193 /*
3194 * The recovery sequence below admits a very elaborated explanation:
3195 * - it seems to work;
d03902b8
FR		 3196 * - I did not see what else could be done;
3197 * - it makes iop3xx happy.
1da177e4
LT		 3198 *
3199 * Feel free to adjust to your needs.
3200 */
a27993f3 3201 if (pdev->broken_parity_status)
d03902b8
FR		 3202 pci_cmd &= ~PCI_COMMAND_PARITY;
3203 else
3204 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3205
3206 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 3207
3208 pci_write_config_word(pdev, PCI_STATUS,
3209 pci_status & (PCI_STATUS_DETECTED_PARITY |
3210 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3211 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3212
3213 /* The infamous DAC f*ckup only happens at boot time */
3214 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 3215 if (netif_msg_intr(tp))
3216 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 3217 tp->cp_cmd &= ~PCIDAC;
3218 RTL_W16(CPlusCmd, tp->cp_cmd);
3219 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 3220 }
3221
3222 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 3223
3224 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 3225}
3226
07d3f51f
FR		 3227static void rtl8169_tx_interrupt(struct net_device *dev,
3228 struct rtl8169_private *tp,
3229 void __iomem *ioaddr)
1da177e4
LT		 3230{
3231 unsigned int dirty_tx, tx_left;
3232
1da177e4
LT		 3233 dirty_tx = tp->dirty_tx;
3234 smp_rmb();
3235 tx_left = tp->cur_tx - dirty_tx;
3236
3237 while (tx_left > 0) {
3238 unsigned int entry = dirty_tx % NUM_TX_DESC;
3239 struct ring_info *tx_skb = tp->tx_skb + entry;
3240 u32 len = tx_skb->len;
3241 u32 status;
3242
3243 rmb();
3244 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3245 if (status & DescOwn)
3246 break;
3247
cebf8cc7
FR		 3248 dev->stats.tx_bytes += len;
3249 dev->stats.tx_packets++;
1da177e4
LT		 3250
3251 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3252
3253 if (status & LastFrag) {
3254 dev_kfree_skb_irq(tx_skb->skb);
3255 tx_skb->skb = NULL;
3256 }
3257 dirty_tx++;
3258 tx_left--;
3259 }
3260
3261 if (tp->dirty_tx != dirty_tx) {
3262 tp->dirty_tx = dirty_tx;
3263 smp_wmb();
3264 if (netif_queue_stopped(dev) &&
3265 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3266 netif_wake_queue(dev);
3267 }
d78ae2dc
FR		 3268 /*
3269 * 8168 hack: TxPoll requests are lost when the Tx packets are
3270 * too close. Let's kick an extra TxPoll request when a burst
3271 * of start_xmit activity is detected (if it is not detected,
3272 * it is slow enough). -- FR
3273 */
3274 smp_rmb();
3275 if (tp->cur_tx != dirty_tx)
3276 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 3277 }
3278}
3279
126fa4b9
FR		 3280static inline int rtl8169_fragmented_frame(u32 status)
3281{
3282 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3283}
3284
1da177e4
LT		 3285static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3286{
3287 u32 opts1 = le32_to_cpu(desc->opts1);
3288 u32 status = opts1 & RxProtoMask;
3289
3290 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3291 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3292 ((status == RxProtoIP) && !(opts1 & IPFail)))
3293 skb->ip_summed = CHECKSUM_UNNECESSARY;
3294 else
3295 skb->ip_summed = CHECKSUM_NONE;
3296}
3297
07d3f51f
FR		 3298static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3299 struct rtl8169_private *tp, int pkt_size,
3300 dma_addr_t addr)
1da177e4 3301{
b449655f
SH		 3302 struct sk_buff *skb;
3303 bool done = false;
1da177e4 3304
b449655f
SH		 3305 if (pkt_size >= rx_copybreak)
3306 goto out;
1da177e4 3307
07d3f51f 3308 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
b449655f
SH		 3309 if (!skb)
3310 goto out;
3311
07d3f51f
FR		 3312 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3313 PCI_DMA_FROMDEVICE);
86402234 3314 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 3315 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3316 *sk_buff = skb;
3317 done = true;
3318out:
3319 return done;
1da177e4
LT		 3320}
3321
07d3f51f
FR		 3322static int rtl8169_rx_interrupt(struct net_device *dev,
3323 struct rtl8169_private *tp,
bea3348e 3324 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 3325{
3326 unsigned int cur_rx, rx_left;
3327 unsigned int delta, count;
3328
1da177e4
LT		 3329 cur_rx = tp->cur_rx;
3330 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 3331 rx_left = min(rx_left, budget);
1da177e4 3332
4dcb7d33 3333 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 3334 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 3335 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 3336 u32 status;
3337
3338 rmb();
126fa4b9 3339 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 3340
3341 if (status & DescOwn)
3342 break;
4dcb7d33 3343 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 3344 if (netif_msg_rx_err(tp)) {
3345 printk(KERN_INFO
3346 "%s: Rx ERROR. status = %08x\n",
3347 dev->name, status);
3348 }
cebf8cc7 3349 dev->stats.rx_errors++;
1da177e4 3350 if (status & (RxRWT | RxRUNT))
cebf8cc7 3351 dev->stats.rx_length_errors++;
1da177e4 3352 if (status & RxCRC)
cebf8cc7 3353 dev->stats.rx_crc_errors++;
9dccf611
FR		 3354 if (status & RxFOVF) {
3355 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 3356 dev->stats.rx_fifo_errors++;
9dccf611 3357 }
126fa4b9 3358 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 3359 } else {
1da177e4 3360 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 3361 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 3362 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 3363 struct pci_dev *pdev = tp->pci_dev;
1da177e4 3364
126fa4b9
FR		 3365 /*
3366 * The driver does not support incoming fragmented
3367 * frames. They are seen as a symptom of over-mtu
3368 * sized frames.
3369 */
3370 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 3371 dev->stats.rx_dropped++;
3372 dev->stats.rx_length_errors++;
126fa4b9 3373 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 3374 continue;
126fa4b9
FR		 3375 }
3376
1da177e4 3377 rtl8169_rx_csum(skb, desc);
bcf0bf90 3378
07d3f51f 3379 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 3380 pci_dma_sync_single_for_device(pdev, addr,
3381 pkt_size, PCI_DMA_FROMDEVICE);
3382 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3383 } else {
a866bbf6 3384 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
b449655f 3385 PCI_DMA_FROMDEVICE);
1da177e4
LT		 3386 tp->Rx_skbuff[entry] = NULL;
3387 }
3388
1da177e4
LT		 3389 skb_put(skb, pkt_size);
3390 skb->protocol = eth_type_trans(skb, dev);
3391
3392 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
865c652d 3393 netif_receive_skb(skb);
1da177e4
LT		 3394
3395 dev->last_rx = jiffies;
cebf8cc7
FR		 3396 dev->stats.rx_bytes += pkt_size;
3397 dev->stats.rx_packets++;
1da177e4 3398 }
6dccd16b
FR		 3399
3400 /* Work around for AMD plateform. */
95e0918d 3401 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 3402 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3403 desc->opts2 = 0;
3404 cur_rx++;
3405 }
1da177e4
LT		 3406 }
3407
3408 count = cur_rx - tp->cur_rx;
3409 tp->cur_rx = cur_rx;
3410
3411 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 3412 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 3413 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3414 tp->dirty_rx += delta;
3415
3416 /*
3417 * FIXME: until there is periodic timer to try and refill the ring,
3418 * a temporary shortage may definitely kill the Rx process.
3419 * - disable the asic to try and avoid an overflow and kick it again
3420 * after refill ?
3421 * - how do others driver handle this condition (Uh oh...).
3422 */
b57b7e5a 3423 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 3424 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3425
3426 return count;
3427}
3428
07d3f51f 3429static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 3430{
07d3f51f 3431 struct net_device *dev = dev_instance;
1da177e4 3432 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 3433 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3434 int handled = 0;
865c652d 3435 int status;
1da177e4 3436
865c652d 3437 status = RTL_R16(IntrStatus);
1da177e4 3438
865c652d
FR		 3439 /* hotplug/major error/no more work/shared irq */
3440 if ((status == 0xffff) || !status)
3441 goto out;
1da177e4 3442
865c652d 3443 handled = 1;
1da177e4 3444
865c652d
FR		 3445 if (unlikely(!netif_running(dev))) {
3446 rtl8169_asic_down(ioaddr);
3447 goto out;
3448 }
1da177e4 3449
865c652d
FR		 3450 status &= tp->intr_mask;
3451 RTL_W16(IntrStatus,
3452 (status & RxFIFOOver) ? (status | RxOverflow) : status);
1da177e4 3453
865c652d
FR		 3454 if (!(status & tp->intr_event))
3455 goto out;
0e485150 3456
865c652d
FR		 3457 /* Work around for rx fifo overflow */
3458 if (unlikely(status & RxFIFOOver) &&
3459 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3460 netif_stop_queue(dev);
3461 rtl8169_tx_timeout(dev);
3462 goto out;
3463 }
1da177e4 3464
865c652d
FR		 3465 if (unlikely(status & SYSErr)) {
3466 rtl8169_pcierr_interrupt(dev);
3467 goto out;
3468 }
1da177e4 3469
865c652d
FR		 3470 if (status & LinkChg)
3471 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4 3472
865c652d
FR		 3473 if (status & tp->napi_event) {
3474 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3475 tp->intr_mask = ~tp->napi_event;
313b0305 3476
bea3348e
SH		 3477 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
3478 __netif_rx_schedule(dev, &tp->napi);
865c652d
FR		 3479 else if (netif_msg_intr(tp)) {
3480 printk(KERN_INFO "%s: interrupt %04x in poll\n",
3481 dev->name, status);
b57b7e5a 3482 }
1da177e4
LT		 3483 }
3484out:
3485 return IRQ_RETVAL(handled);
3486}
3487
bea3348e 3488static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 3489{
bea3348e
SH		 3490 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3491 struct net_device *dev = tp->dev;
1da177e4 3492 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 3493 int work_done;
1da177e4 3494
bea3348e 3495 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 3496 rtl8169_tx_interrupt(dev, tp, ioaddr);
3497
bea3348e
SH		 3498 if (work_done < budget) {
3499 netif_rx_complete(dev, napi);
1da177e4
LT		 3500 tp->intr_mask = 0xffff;
3501 /*
3502 * 20040426: the barrier is not strictly required but the
3503 * behavior of the irq handler could be less predictable
3504 * without it. Btw, the lack of flush for the posted pci
3505 * write is safe - FR
3506 */
3507 smp_wmb();
0e485150 3508 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3509 }
3510
bea3348e 3511 return work_done;
1da177e4 3512}
1da177e4 3513
523a6094
FR		 3514static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
3515{
3516 struct rtl8169_private *tp = netdev_priv(dev);
3517
3518 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3519 return;
3520
3521 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3522 RTL_W32(RxMissed, 0);
3523}
3524
1da177e4
LT		 3525static void rtl8169_down(struct net_device *dev)
3526{
3527 struct rtl8169_private *tp = netdev_priv(dev);
3528 void __iomem *ioaddr = tp->mmio_addr;
733b736c 3529 unsigned int intrmask;
1da177e4
LT		 3530
3531 rtl8169_delete_timer(dev);
3532
3533 netif_stop_queue(dev);
3534
93dd79e8 3535 napi_disable(&tp->napi);
93dd79e8 3536
1da177e4
LT		 3537core_down:
3538 spin_lock_irq(&tp->lock);
3539
3540 rtl8169_asic_down(ioaddr);
3541
523a6094 3542 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 3543
3544 spin_unlock_irq(&tp->lock);
3545
3546 synchronize_irq(dev->irq);
3547
1da177e4 3548 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 3549 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 3550
3551 /*
3552 * And now for the 50k$ question: are IRQ disabled or not ?
3553 *
3554 * Two paths lead here:
3555 * 1) dev->close
3556 * -> netif_running() is available to sync the current code and the
3557 * IRQ handler. See rtl8169_interrupt for details.
3558 * 2) dev->change_mtu
3559 * -> rtl8169_poll can not be issued again and re-enable the
3560 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 3561 *
3562 * No loop if hotpluged or major error (0xffff).
1da177e4 3563 */
733b736c
AP		 3564 intrmask = RTL_R16(IntrMask);
3565 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 3566 goto core_down;
3567
3568 rtl8169_tx_clear(tp);
3569
3570 rtl8169_rx_clear(tp);
3571}
3572
3573static int rtl8169_close(struct net_device *dev)
3574{
3575 struct rtl8169_private *tp = netdev_priv(dev);
3576 struct pci_dev *pdev = tp->pci_dev;
3577
3578 rtl8169_down(dev);
3579
3580 free_irq(dev->irq, dev);
3581
1da177e4
LT		 3582 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3583 tp->RxPhyAddr);
3584 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3585 tp->TxPhyAddr);
3586 tp->TxDescArray = NULL;
3587 tp->RxDescArray = NULL;
3588
3589 return 0;
3590}
3591
07ce4064 3592static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 3593{
3594 struct rtl8169_private *tp = netdev_priv(dev);
3595 void __iomem *ioaddr = tp->mmio_addr;
3596 unsigned long flags;
3597 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 3598 int rx_mode;
1da177e4
LT		 3599 u32 tmp = 0;
3600
3601 if (dev->flags & IFF_PROMISC) {
3602 /* Unconditionally log net taps. */
b57b7e5a
SH		 3603 if (netif_msg_link(tp)) {
3604 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3605 dev->name);
3606 }
1da177e4
LT		 3607 rx_mode =
3608 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3609 AcceptAllPhys;
3610 mc_filter[1] = mc_filter[0] = 0xffffffff;
3611 } else if ((dev->mc_count > multicast_filter_limit)
3612 || (dev->flags & IFF_ALLMULTI)) {
3613 /* Too many to filter perfectly -- accept all multicasts. */
3614 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3615 mc_filter[1] = mc_filter[0] = 0xffffffff;
3616 } else {
3617 struct dev_mc_list *mclist;
07d3f51f
FR		 3618 unsigned int i;
3619
1da177e4
LT		 3620 rx_mode = AcceptBroadcast | AcceptMyPhys;
3621 mc_filter[1] = mc_filter[0] = 0;
3622 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3623 i++, mclist = mclist->next) {
3624 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3625 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3626 rx_mode |= AcceptMulticast;
3627 }
3628 }
3629
3630 spin_lock_irqsave(&tp->lock, flags);
3631
3632 tmp = rtl8169_rx_config | rx_mode |
3633 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3634
f887cce8 3635 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 3636 u32 data = mc_filter[0];
3637
3638 mc_filter[0] = swab32(mc_filter[1]);
3639 mc_filter[1] = swab32(data);
bcf0bf90
FR		 3640 }
3641
1da177e4
LT		 3642 RTL_W32(MAR0 + 0, mc_filter[0]);
3643 RTL_W32(MAR0 + 4, mc_filter[1]);
3644
57a9f236
FR		 3645 RTL_W32(RxConfig, tmp);
3646
1da177e4
LT		 3647 spin_unlock_irqrestore(&tp->lock, flags);
3648}
3649
3650/**
3651 * rtl8169_get_stats - Get rtl8169 read/write statistics
3652 * @dev: The Ethernet Device to get statistics for
3653 *
3654 * Get TX/RX statistics for rtl8169
3655 */
3656static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3657{
3658 struct rtl8169_private *tp = netdev_priv(dev);
3659 void __iomem *ioaddr = tp->mmio_addr;
3660 unsigned long flags;
3661
3662 if (netif_running(dev)) {
3663 spin_lock_irqsave(&tp->lock, flags);
523a6094 3664 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 3665 spin_unlock_irqrestore(&tp->lock, flags);
3666 }
5b0384f4 3667
cebf8cc7 3668 return &dev->stats;
1da177e4
LT		 3669}
3670
5d06a99f
FR		 3671#ifdef CONFIG_PM
3672
3673static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3674{
3675 struct net_device *dev = pci_get_drvdata(pdev);
3676 struct rtl8169_private *tp = netdev_priv(dev);
3677 void __iomem *ioaddr = tp->mmio_addr;
3678
3679 if (!netif_running(dev))
1371fa6d 3680 goto out_pci_suspend;
5d06a99f
FR		 3681
3682 netif_device_detach(dev);
3683 netif_stop_queue(dev);
3684
3685 spin_lock_irq(&tp->lock);
3686
3687 rtl8169_asic_down(ioaddr);
3688
523a6094 3689 rtl8169_rx_missed(dev, ioaddr);
5d06a99f
FR		 3690
3691 spin_unlock_irq(&tp->lock);
3692
1371fa6d 3693out_pci_suspend:
5d06a99f 3694 pci_save_state(pdev);
f23e7fda
FR		 3695 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3696 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
5d06a99f 3697 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1371fa6d 3698
5d06a99f
FR		 3699 return 0;
3700}
3701
3702static int rtl8169_resume(struct pci_dev *pdev)
3703{
3704 struct net_device *dev = pci_get_drvdata(pdev);
3705
1371fa6d
FR		 3706 pci_set_power_state(pdev, PCI_D0);
3707 pci_restore_state(pdev);
3708 pci_enable_wake(pdev, PCI_D0, 0);
3709
5d06a99f
FR		 3710 if (!netif_running(dev))
3711 goto out;
3712
3713 netif_device_attach(dev);
3714
5d06a99f
FR		 3715 rtl8169_schedule_work(dev, rtl8169_reset_task);
3716out:
3717 return 0;
3718}
3719
3720#endif /* CONFIG_PM */
3721
1da177e4
LT		 3722static struct pci_driver rtl8169_pci_driver = {
3723 .name = MODULENAME,
3724 .id_table = rtl8169_pci_tbl,
3725 .probe = rtl8169_init_one,
3726 .remove = __devexit_p(rtl8169_remove_one),
3727#ifdef CONFIG_PM
3728 .suspend = rtl8169_suspend,
3729 .resume = rtl8169_resume,
3730#endif
3731};
3732
07d3f51f 3733static int __init rtl8169_init_module(void)
1da177e4 3734{
29917620 3735 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 3736}
3737
07d3f51f 3738static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 3739{
3740 pci_unregister_driver(&rtl8169_pci_driver);
3741}
3742
3743module_init(rtl8169_init_module);
3744module_exit(rtl8169_cleanup_module);
kernel source for telekom puls (alcatel/mediatek)