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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
865c652d 31#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 32#define MODULENAME "r8169"
33#define PFX MODULENAME ": "
34
35#ifdef RTL8169_DEBUG
36#define assert(expr) \
5b0384f4
FR		 37 if (!(expr)) { \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 39 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 40 }
06fa7358
JP		 41#define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 43#else
44#define assert(expr) do {} while (0)
45#define dprintk(fmt, args...) do {} while (0)
46#endif /* RTL8169_DEBUG */
47
b57b7e5a 48#define R8169_MSG_DEFAULT \
f0e837d9 49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 50
1da177e4
LT		 51#define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
1da177e4
LT		 54/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
55 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 56static const int multicast_filter_limit = 32;
1da177e4
LT		 57
58/* MAC address length */
59#define MAC_ADDR_LEN 6
60
9c14ceaf 61#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 62#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
63#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
64#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 65#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 66#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
67#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
68
69#define R8169_REGS_SIZE 256
70#define R8169_NAPI_WEIGHT 64
71#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
72#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
73#define RX_BUF_SIZE 1536 /* Rx Buffer size */
74#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
75#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
76
77#define RTL8169_TX_TIMEOUT (6*HZ)
78#define RTL8169_PHY_TIMEOUT (10*HZ)
79
ea8dbdd1 80#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
81#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 82#define RTL_EEPROM_SIG_ADDR 0x0000
83
1da177e4
LT		 84/* write/read MMIO register */
85#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88#define RTL_R8(reg) readb (ioaddr + (reg))
89#define RTL_R16(reg) readw (ioaddr + (reg))
90#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
91
92enum mac_version {
f21b75e9 93 RTL_GIGA_MAC_NONE = 0x00,
ba6eb6ee
FR		 94 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
95 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
96 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
97 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
98 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 99 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 100 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
101 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
102 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
103 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 104 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 105 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
106 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
107 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
108 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
109 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
110 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
111 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
112 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 113 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 114 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0 115 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
7f3e3d3a 116 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
5b538df9 117 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
daf9df6d 118 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
119 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
120 RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP
1da177e4
LT		 121};
122
1da177e4
LT		 123#define _R(NAME,MAC,MASK) \
124 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
125
3c6bee1d 126static const struct {
1da177e4
LT		 127 const char *name;
128 u8 mac_version;
129 u32 RxConfigMask; /* Clears the bits supported by this chip */
130} rtl_chip_info[] = {
ba6eb6ee
FR		 131 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
132 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
133 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
134 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
135 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 137 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
138 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
140 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 141 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
143 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
144 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 145 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
146 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
147 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
148 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
149 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
197ff761 150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
6fb07058 151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
ef3386f0 152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
7f3e3d3a 153 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
5b538df9 154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
daf9df6d 155 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
157 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E
1da177e4
LT		 158};
159#undef _R
160
bcf0bf90
FR		 161enum cfg_version {
162 RTL_CFG_0 = 0x00,
163 RTL_CFG_1,
164 RTL_CFG_2
165};
166
07ce4064
FR		 167static void rtl_hw_start_8169(struct net_device *);
168static void rtl_hw_start_8168(struct net_device *);
169static void rtl_hw_start_8101(struct net_device *);
170
a3aa1884 171static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 172 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
177 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 178 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 179 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
180 { PCI_VENDOR_ID_LINKSYS, 0x1032,
181 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 182 { 0x0001, 0x8168,
183 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 184 {0,},
185};
186
187MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
188
c0cd884a
NH		 189/*
190 * we set our copybreak very high so that we don't have
191 * to allocate 16k frames all the time (see note in
192 * rtl8169_open()
193 */
194static int rx_copybreak = 16383;
4300e8c7 195static int use_dac;
b57b7e5a
SH		 196static struct {
197 u32 msg_enable;
198} debug = { -1 };
1da177e4 199
07d3f51f
FR		 200enum rtl_registers {
201 MAC0 = 0, /* Ethernet hardware address. */
773d2021 202 MAC4 = 4,
07d3f51f
FR		 203 MAR0 = 8, /* Multicast filter. */
204 CounterAddrLow = 0x10,
205 CounterAddrHigh = 0x14,
206 TxDescStartAddrLow = 0x20,
207 TxDescStartAddrHigh = 0x24,
208 TxHDescStartAddrLow = 0x28,
209 TxHDescStartAddrHigh = 0x2c,
210 FLASH = 0x30,
211 ERSR = 0x36,
212 ChipCmd = 0x37,
213 TxPoll = 0x38,
214 IntrMask = 0x3c,
215 IntrStatus = 0x3e,
216 TxConfig = 0x40,
217 RxConfig = 0x44,
218 RxMissed = 0x4c,
219 Cfg9346 = 0x50,
220 Config0 = 0x51,
221 Config1 = 0x52,
222 Config2 = 0x53,
223 Config3 = 0x54,
224 Config4 = 0x55,
225 Config5 = 0x56,
226 MultiIntr = 0x5c,
227 PHYAR = 0x60,
07d3f51f
FR		 228 PHYstatus = 0x6c,
229 RxMaxSize = 0xda,
230 CPlusCmd = 0xe0,
231 IntrMitigate = 0xe2,
232 RxDescAddrLow = 0xe4,
233 RxDescAddrHigh = 0xe8,
234 EarlyTxThres = 0xec,
235 FuncEvent = 0xf0,
236 FuncEventMask = 0xf4,
237 FuncPresetState = 0xf8,
238 FuncForceEvent = 0xfc,
1da177e4
LT		 239};
240
f162a5d1
FR		 241enum rtl8110_registers {
242 TBICSR = 0x64,
243 TBI_ANAR = 0x68,
244 TBI_LPAR = 0x6a,
245};
246
247enum rtl8168_8101_registers {
248 CSIDR = 0x64,
249 CSIAR = 0x68,
250#define CSIAR_FLAG 0x80000000
251#define CSIAR_WRITE_CMD 0x80000000
252#define CSIAR_BYTE_ENABLE 0x0f
253#define CSIAR_BYTE_ENABLE_SHIFT 12
254#define CSIAR_ADDR_MASK 0x0fff
255
256 EPHYAR = 0x80,
257#define EPHYAR_FLAG 0x80000000
258#define EPHYAR_WRITE_CMD 0x80000000
259#define EPHYAR_REG_MASK 0x1f
260#define EPHYAR_REG_SHIFT 16
261#define EPHYAR_DATA_MASK 0xffff
262 DBG_REG = 0xd1,
263#define FIX_NAK_1 (1 << 4)
264#define FIX_NAK_2 (1 << 3)
daf9df6d 265 EFUSEAR = 0xdc,
266#define EFUSEAR_FLAG 0x80000000
267#define EFUSEAR_WRITE_CMD 0x80000000
268#define EFUSEAR_READ_CMD 0x00000000
269#define EFUSEAR_REG_MASK 0x03ff
270#define EFUSEAR_REG_SHIFT 8
271#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 272};
273
07d3f51f 274enum rtl_register_content {
1da177e4 275 /* InterruptStatusBits */
07d3f51f
FR		 276 SYSErr = 0x8000,
277 PCSTimeout = 0x4000,
278 SWInt = 0x0100,
279 TxDescUnavail = 0x0080,
280 RxFIFOOver = 0x0040,
281 LinkChg = 0x0020,
282 RxOverflow = 0x0010,
283 TxErr = 0x0008,
284 TxOK = 0x0004,
285 RxErr = 0x0002,
286 RxOK = 0x0001,
1da177e4
LT		 287
288 /* RxStatusDesc */
9dccf611
FR		 289 RxFOVF = (1 << 23),
290 RxRWT = (1 << 22),
291 RxRES = (1 << 21),
292 RxRUNT = (1 << 20),
293 RxCRC = (1 << 19),
1da177e4
LT		 294
295 /* ChipCmdBits */
07d3f51f
FR		 296 CmdReset = 0x10,
297 CmdRxEnb = 0x08,
298 CmdTxEnb = 0x04,
299 RxBufEmpty = 0x01,
1da177e4 300
275391a4
FR		 301 /* TXPoll register p.5 */
302 HPQ = 0x80, /* Poll cmd on the high prio queue */
303 NPQ = 0x40, /* Poll cmd on the low prio queue */
304 FSWInt = 0x01, /* Forced software interrupt */
305
1da177e4 306 /* Cfg9346Bits */
07d3f51f
FR		 307 Cfg9346_Lock = 0x00,
308 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 309
310 /* rx_mode_bits */
07d3f51f
FR		 311 AcceptErr = 0x20,
312 AcceptRunt = 0x10,
313 AcceptBroadcast = 0x08,
314 AcceptMulticast = 0x04,
315 AcceptMyPhys = 0x02,
316 AcceptAllPhys = 0x01,
1da177e4
LT		 317
318 /* RxConfigBits */
07d3f51f
FR		 319 RxCfgFIFOShift = 13,
320 RxCfgDMAShift = 8,
1da177e4
LT		 321
322 /* TxConfigBits */
323 TxInterFrameGapShift = 24,
324 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
325
5d06a99f 326 /* Config1 register p.24 */
f162a5d1
FR		 327 LEDS1 = (1 << 7),
328 LEDS0 = (1 << 6),
fbac58fc 329 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 330 Speed_down = (1 << 4),
331 MEMMAP = (1 << 3),
332 IOMAP = (1 << 2),
333 VPD = (1 << 1),
5d06a99f
FR		 334 PMEnable = (1 << 0), /* Power Management Enable */
335
6dccd16b
FR		 336 /* Config2 register p. 25 */
337 PCI_Clock_66MHz = 0x01,
338 PCI_Clock_33MHz = 0x00,
339
61a4dcc2
FR		 340 /* Config3 register p.25 */
341 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
342 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 343 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 344
5d06a99f 345 /* Config5 register p.27 */
61a4dcc2
FR		 346 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
347 MWF = (1 << 5), /* Accept Multicast wakeup frame */
348 UWF = (1 << 4), /* Accept Unicast wakeup frame */
349 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 350 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
351
1da177e4
LT		 352 /* TBICSR p.28 */
353 TBIReset = 0x80000000,
354 TBILoopback = 0x40000000,
355 TBINwEnable = 0x20000000,
356 TBINwRestart = 0x10000000,
357 TBILinkOk = 0x02000000,
358 TBINwComplete = 0x01000000,
359
360 /* CPlusCmd p.31 */
f162a5d1
FR		 361 EnableBist = (1 << 15), // 8168 8101
362 Mac_dbgo_oe = (1 << 14), // 8168 8101
363 Normal_mode = (1 << 13), // unused
364 Force_half_dup = (1 << 12), // 8168 8101
365 Force_rxflow_en = (1 << 11), // 8168 8101
366 Force_txflow_en = (1 << 10), // 8168 8101
367 Cxpl_dbg_sel = (1 << 9), // 8168 8101
368 ASF = (1 << 8), // 8168 8101
369 PktCntrDisable = (1 << 7), // 8168 8101
370 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 371 RxVlan = (1 << 6),
372 RxChkSum = (1 << 5),
373 PCIDAC = (1 << 4),
374 PCIMulRW = (1 << 3),
0e485150
FR		 375 INTT_0 = 0x0000, // 8168
376 INTT_1 = 0x0001, // 8168
377 INTT_2 = 0x0002, // 8168
378 INTT_3 = 0x0003, // 8168
1da177e4
LT		 379
380 /* rtl8169_PHYstatus */
07d3f51f
FR		 381 TBI_Enable = 0x80,
382 TxFlowCtrl = 0x40,
383 RxFlowCtrl = 0x20,
384 _1000bpsF = 0x10,
385 _100bps = 0x08,
386 _10bps = 0x04,
387 LinkStatus = 0x02,
388 FullDup = 0x01,
1da177e4 389
1da177e4 390 /* _TBICSRBit */
07d3f51f 391 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 392
393 /* DumpCounterCommand */
07d3f51f 394 CounterDump = 0x8,
1da177e4
LT		 395};
396
07d3f51f 397enum desc_status_bit {
1da177e4
LT		 398 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
399 RingEnd = (1 << 30), /* End of descriptor ring */
400 FirstFrag = (1 << 29), /* First segment of a packet */
401 LastFrag = (1 << 28), /* Final segment of a packet */
402
403 /* Tx private */
404 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
405 MSSShift = 16, /* MSS value position */
406 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
407 IPCS = (1 << 18), /* Calculate IP checksum */
408 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
409 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
410 TxVlanTag = (1 << 17), /* Add VLAN tag */
411
412 /* Rx private */
413 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
414 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
415
416#define RxProtoUDP (PID1)
417#define RxProtoTCP (PID0)
418#define RxProtoIP (PID1 | PID0)
419#define RxProtoMask RxProtoIP
420
421 IPFail = (1 << 16), /* IP checksum failed */
422 UDPFail = (1 << 15), /* UDP/IP checksum failed */
423 TCPFail = (1 << 14), /* TCP/IP checksum failed */
424 RxVlanTag = (1 << 16), /* VLAN tag available */
425};
426
427#define RsvdMask 0x3fffc000
428
429struct TxDesc {
6cccd6e7
REB		 430 __le32 opts1;
431 __le32 opts2;
432 __le64 addr;
1da177e4
LT		 433};
434
435struct RxDesc {
6cccd6e7
REB		 436 __le32 opts1;
437 __le32 opts2;
438 __le64 addr;
1da177e4
LT		 439};
440
441struct ring_info {
442 struct sk_buff *skb;
443 u32 len;
444 u8 __pad[sizeof(void *) - sizeof(u32)];
445};
446
f23e7fda 447enum features {
ccdffb9a
FR		 448 RTL_FEATURE_WOL = (1 << 0),
449 RTL_FEATURE_MSI = (1 << 1),
450 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 451};
452
355423d0
IV		 453struct rtl8169_counters {
454 __le64 tx_packets;
455 __le64 rx_packets;
456 __le64 tx_errors;
457 __le32 rx_errors;
458 __le16 rx_missed;
459 __le16 align_errors;
460 __le32 tx_one_collision;
461 __le32 tx_multi_collision;
462 __le64 rx_unicast;
463 __le64 rx_broadcast;
464 __le32 rx_multicast;
465 __le16 tx_aborted;
466 __le16 tx_underun;
467};
468
1da177e4
LT		 469struct rtl8169_private {
470 void __iomem *mmio_addr; /* memory map physical address */
471 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 472 struct net_device *dev;
bea3348e 473 struct napi_struct napi;
1da177e4 474 spinlock_t lock; /* spin lock flag */
b57b7e5a 475 u32 msg_enable;
1da177e4
LT		 476 int chipset;
477 int mac_version;
1da177e4
LT		 478 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
479 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
480 u32 dirty_rx;
481 u32 dirty_tx;
482 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
483 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
484 dma_addr_t TxPhyAddr;
485 dma_addr_t RxPhyAddr;
486 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
487 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 488 unsigned align;
1da177e4
LT		 489 unsigned rx_buf_sz;
490 struct timer_list timer;
491 u16 cp_cmd;
0e485150
FR		 492 u16 intr_event;
493 u16 napi_event;
1da177e4 494 u16 intr_mask;
1da177e4
LT		 495 int phy_1000_ctrl_reg;
496#ifdef CONFIG_R8169_VLAN
497 struct vlan_group *vlgrp;
498#endif
499 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 500 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
1da177e4 501 void (*phy_reset_enable)(void __iomem *);
07ce4064 502 void (*hw_start)(struct net_device *);
1da177e4
LT		 503 unsigned int (*phy_reset_pending)(void __iomem *);
504 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 505 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 506 int pcie_cap;
c4028958 507 struct delayed_work task;
f23e7fda 508 unsigned features;
ccdffb9a
FR		 509
510 struct mii_if_info mii;
355423d0 511 struct rtl8169_counters counters;
1da177e4
LT		 512};
513
979b6c13 514MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 515MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 516module_param(rx_copybreak, int, 0);
1b7efd58 517MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4 518module_param(use_dac, int, 0);
4300e8c7 519MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 520module_param_named(debug, debug.msg_enable, int, 0);
521MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 522MODULE_LICENSE("GPL");
523MODULE_VERSION(RTL8169_VERSION);
524
525static int rtl8169_open(struct net_device *dev);
61357325
SH		 526static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
527 struct net_device *dev);
7d12e780 528static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 529static int rtl8169_init_ring(struct net_device *dev);
07ce4064 530static void rtl_hw_start(struct net_device *dev);
1da177e4 531static int rtl8169_close(struct net_device *dev);
07ce4064 532static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 533static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 534static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 535static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 536 void __iomem *, u32 budget);
4dcb7d33 537static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 538static void rtl8169_down(struct net_device *dev);
99f252b0 539static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 540static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 541
1da177e4 542static const unsigned int rtl8169_rx_config =
5b0384f4 543 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 544
07d3f51f 545static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 546{
547 int i;
548
a6baf3af 549 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 550
2371408c 551 for (i = 20; i > 0; i--) {
07d3f51f
FR		 552 /*
553 * Check if the RTL8169 has completed writing to the specified
554 * MII register.
555 */
5b0384f4 556 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 557 break;
2371408c 558 udelay(25);
1da177e4
LT		 559 }
560}
561
07d3f51f 562static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 563{
564 int i, value = -1;
565
a6baf3af 566 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 567
2371408c 568 for (i = 20; i > 0; i--) {
07d3f51f
FR		 569 /*
570 * Check if the RTL8169 has completed retrieving data from
571 * the specified MII register.
572 */
1da177e4 573 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 574 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 575 break;
576 }
2371408c 577 udelay(25);
1da177e4
LT		 578 }
579 return value;
580}
581
dacf8154
FR		 582static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
583{
584 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
585}
586
daf9df6d 587static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m)
588{
589 int val;
590
591 val = mdio_read(ioaddr, reg_addr);
592 mdio_write(ioaddr, reg_addr, (val | p) & ~m);
593}
594
ccdffb9a
FR		 595static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
596 int val)
597{
598 struct rtl8169_private *tp = netdev_priv(dev);
599 void __iomem *ioaddr = tp->mmio_addr;
600
601 mdio_write(ioaddr, location, val);
602}
603
604static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
605{
606 struct rtl8169_private *tp = netdev_priv(dev);
607 void __iomem *ioaddr = tp->mmio_addr;
608
609 return mdio_read(ioaddr, location);
610}
611
dacf8154
FR		 612static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
613{
614 unsigned int i;
615
616 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
617 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
618
619 for (i = 0; i < 100; i++) {
620 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
621 break;
622 udelay(10);
623 }
624}
625
626static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
627{
628 u16 value = 0xffff;
629 unsigned int i;
630
631 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
632
633 for (i = 0; i < 100; i++) {
634 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
635 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
636 break;
637 }
638 udelay(10);
639 }
640
641 return value;
642}
643
644static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
645{
646 unsigned int i;
647
648 RTL_W32(CSIDR, value);
649 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
650 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
651
652 for (i = 0; i < 100; i++) {
653 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
654 break;
655 udelay(10);
656 }
657}
658
659static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
660{
661 u32 value = ~0x00;
662 unsigned int i;
663
664 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
665 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
666
667 for (i = 0; i < 100; i++) {
668 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
669 value = RTL_R32(CSIDR);
670 break;
671 }
672 udelay(10);
673 }
674
675 return value;
676}
677
daf9df6d 678static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
679{
680 u8 value = 0xff;
681 unsigned int i;
682
683 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
684
685 for (i = 0; i < 300; i++) {
686 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
687 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
688 break;
689 }
690 udelay(100);
691 }
692
693 return value;
694}
695
1da177e4
LT		 696static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
697{
698 RTL_W16(IntrMask, 0x0000);
699
700 RTL_W16(IntrStatus, 0xffff);
701}
702
703static void rtl8169_asic_down(void __iomem *ioaddr)
704{
705 RTL_W8(ChipCmd, 0x00);
706 rtl8169_irq_mask_and_ack(ioaddr);
707 RTL_R16(CPlusCmd);
708}
709
710static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
711{
712 return RTL_R32(TBICSR) & TBIReset;
713}
714
715static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
716{
64e4bfb4 717 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 718}
719
720static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
721{
722 return RTL_R32(TBICSR) & TBILinkOk;
723}
724
725static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
726{
727 return RTL_R8(PHYstatus) & LinkStatus;
728}
729
730static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
731{
732 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
733}
734
735static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
736{
737 unsigned int val;
738
9e0db8ef
FR		 739 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
740 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 741}
742
743static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 744 struct rtl8169_private *tp,
745 void __iomem *ioaddr)
1da177e4
LT		 746{
747 unsigned long flags;
748
749 spin_lock_irqsave(&tp->lock, flags);
750 if (tp->link_ok(ioaddr)) {
751 netif_carrier_on(dev);
bf82c189 752 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 753 } else {
1da177e4 754 netif_carrier_off(dev);
bf82c189 755 netif_info(tp, ifdown, dev, "link down\n");
b57b7e5a 756 }
1da177e4
LT		 757 spin_unlock_irqrestore(&tp->lock, flags);
758}
759
61a4dcc2
FR		 760static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
761{
762 struct rtl8169_private *tp = netdev_priv(dev);
763 void __iomem *ioaddr = tp->mmio_addr;
764 u8 options;
765
766 wol->wolopts = 0;
767
768#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
769 wol->supported = WAKE_ANY;
770
771 spin_lock_irq(&tp->lock);
772
773 options = RTL_R8(Config1);
774 if (!(options & PMEnable))
775 goto out_unlock;
776
777 options = RTL_R8(Config3);
778 if (options & LinkUp)
779 wol->wolopts |= WAKE_PHY;
780 if (options & MagicPacket)
781 wol->wolopts |= WAKE_MAGIC;
782
783 options = RTL_R8(Config5);
784 if (options & UWF)
785 wol->wolopts |= WAKE_UCAST;
786 if (options & BWF)
5b0384f4 787 wol->wolopts |= WAKE_BCAST;
61a4dcc2 788 if (options & MWF)
5b0384f4 789 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 790
791out_unlock:
792 spin_unlock_irq(&tp->lock);
793}
794
795static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
796{
797 struct rtl8169_private *tp = netdev_priv(dev);
798 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 799 unsigned int i;
350f7596 800 static const struct {
61a4dcc2
FR		 801 u32 opt;
802 u16 reg;
803 u8 mask;
804 } cfg[] = {
805 { WAKE_ANY, Config1, PMEnable },
806 { WAKE_PHY, Config3, LinkUp },
807 { WAKE_MAGIC, Config3, MagicPacket },
808 { WAKE_UCAST, Config5, UWF },
809 { WAKE_BCAST, Config5, BWF },
810 { WAKE_MCAST, Config5, MWF },
811 { WAKE_ANY, Config5, LanWake }
812 };
813
814 spin_lock_irq(&tp->lock);
815
816 RTL_W8(Cfg9346, Cfg9346_Unlock);
817
818 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
819 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
820 if (wol->wolopts & cfg[i].opt)
821 options |= cfg[i].mask;
822 RTL_W8(cfg[i].reg, options);
823 }
824
825 RTL_W8(Cfg9346, Cfg9346_Lock);
826
f23e7fda
FR		 827 if (wol->wolopts)
828 tp->features |= RTL_FEATURE_WOL;
829 else
830 tp->features &= ~RTL_FEATURE_WOL;
8b76ab39 831 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
61a4dcc2
FR		 832
833 spin_unlock_irq(&tp->lock);
834
835 return 0;
836}
837
1da177e4
LT		 838static void rtl8169_get_drvinfo(struct net_device *dev,
839 struct ethtool_drvinfo *info)
840{
841 struct rtl8169_private *tp = netdev_priv(dev);
842
843 strcpy(info->driver, MODULENAME);
844 strcpy(info->version, RTL8169_VERSION);
845 strcpy(info->bus_info, pci_name(tp->pci_dev));
846}
847
848static int rtl8169_get_regs_len(struct net_device *dev)
849{
850 return R8169_REGS_SIZE;
851}
852
853static int rtl8169_set_speed_tbi(struct net_device *dev,
854 u8 autoneg, u16 speed, u8 duplex)
855{
856 struct rtl8169_private *tp = netdev_priv(dev);
857 void __iomem *ioaddr = tp->mmio_addr;
858 int ret = 0;
859 u32 reg;
860
861 reg = RTL_R32(TBICSR);
862 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
863 (duplex == DUPLEX_FULL)) {
864 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
865 } else if (autoneg == AUTONEG_ENABLE)
866 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
867 else {
bf82c189
JP		 868 netif_warn(tp, link, dev,
869 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 870 ret = -EOPNOTSUPP;
871 }
872
873 return ret;
874}
875
876static int rtl8169_set_speed_xmii(struct net_device *dev,
877 u8 autoneg, u16 speed, u8 duplex)
878{
879 struct rtl8169_private *tp = netdev_priv(dev);
880 void __iomem *ioaddr = tp->mmio_addr;
3577aa1b 881 int giga_ctrl, bmcr;
1da177e4
LT		 882
883 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 884 int auto_nego;
885
886 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
64e4bfb4
FR		 887 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
888 ADVERTISE_100HALF | ADVERTISE_100FULL);
3577aa1b 889 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 890
3577aa1b 891 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
892 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 893
3577aa1b 894 /* The 8100e/8101e/8102e do Fast Ethernet only. */
895 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
896 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
897 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
898 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
899 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
900 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
901 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
902 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
903 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
bf82c189
JP		 904 } else {
905 netif_info(tp, link, dev,
906 "PHY does not support 1000Mbps\n");
bcf0bf90 907 }
1da177e4 908
3577aa1b 909 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
910
911 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
912 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
913 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
914 /*
915 * Wake up the PHY.
916 * Vendor specific (0x1f) and reserved (0x0e) MII
917 * registers.
918 */
919 mdio_write(ioaddr, 0x1f, 0x0000);
920 mdio_write(ioaddr, 0x0e, 0x0000);
921 }
922
923 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
924 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
925 } else {
926 giga_ctrl = 0;
927
928 if (speed == SPEED_10)
929 bmcr = 0;
930 else if (speed == SPEED_100)
931 bmcr = BMCR_SPEED100;
932 else
933 return -EINVAL;
934
935 if (duplex == DUPLEX_FULL)
936 bmcr |= BMCR_FULLDPLX;
623a1593 937
2584fbc3 938 mdio_write(ioaddr, 0x1f, 0x0000);
2584fbc3
RS		 939 }
940
1da177e4
LT		 941 tp->phy_1000_ctrl_reg = giga_ctrl;
942
3577aa1b 943 mdio_write(ioaddr, MII_BMCR, bmcr);
944
945 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
946 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
947 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
948 mdio_write(ioaddr, 0x17, 0x2138);
949 mdio_write(ioaddr, 0x0e, 0x0260);
950 } else {
951 mdio_write(ioaddr, 0x17, 0x2108);
952 mdio_write(ioaddr, 0x0e, 0x0000);
953 }
954 }
955
1da177e4
LT		 956 return 0;
957}
958
959static int rtl8169_set_speed(struct net_device *dev,
960 u8 autoneg, u16 speed, u8 duplex)
961{
962 struct rtl8169_private *tp = netdev_priv(dev);
963 int ret;
964
965 ret = tp->set_speed(dev, autoneg, speed, duplex);
966
64e4bfb4 967 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 968 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
969
970 return ret;
971}
972
973static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
974{
975 struct rtl8169_private *tp = netdev_priv(dev);
976 unsigned long flags;
977 int ret;
978
979 spin_lock_irqsave(&tp->lock, flags);
980 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
981 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 982
1da177e4
LT		 983 return ret;
984}
985
986static u32 rtl8169_get_rx_csum(struct net_device *dev)
987{
988 struct rtl8169_private *tp = netdev_priv(dev);
989
990 return tp->cp_cmd & RxChkSum;
991}
992
993static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
994{
995 struct rtl8169_private *tp = netdev_priv(dev);
996 void __iomem *ioaddr = tp->mmio_addr;
997 unsigned long flags;
998
999 spin_lock_irqsave(&tp->lock, flags);
1000
1001 if (data)
1002 tp->cp_cmd |= RxChkSum;
1003 else
1004 tp->cp_cmd &= ~RxChkSum;
1005
1006 RTL_W16(CPlusCmd, tp->cp_cmd);
1007 RTL_R16(CPlusCmd);
1008
1009 spin_unlock_irqrestore(&tp->lock, flags);
1010
1011 return 0;
1012}
1013
1014#ifdef CONFIG_R8169_VLAN
1015
1016static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1017 struct sk_buff *skb)
1018{
1019 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
1020 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1021}
1022
1023static void rtl8169_vlan_rx_register(struct net_device *dev,
1024 struct vlan_group *grp)
1025{
1026 struct rtl8169_private *tp = netdev_priv(dev);
1027 void __iomem *ioaddr = tp->mmio_addr;
1028 unsigned long flags;
1029
1030 spin_lock_irqsave(&tp->lock, flags);
1031 tp->vlgrp = grp;
05af2142
SW		 1032 /*
1033 * Do not disable RxVlan on 8110SCd.
1034 */
1035 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1da177e4
LT		 1036 tp->cp_cmd |= RxVlan;
1037 else
1038 tp->cp_cmd &= ~RxVlan;
1039 RTL_W16(CPlusCmd, tp->cp_cmd);
1040 RTL_R16(CPlusCmd);
1041 spin_unlock_irqrestore(&tp->lock, flags);
1042}
1043
1da177e4 1044static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
6c3b9d34 1045 struct sk_buff *skb, int polling)
1da177e4
LT		 1046{
1047 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 1048 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 1049 int ret;
1050
865c652d 1051 if (vlgrp && (opts2 & RxVlanTag)) {
6c3b9d34 1052 __vlan_hwaccel_rx(skb, vlgrp, swab16(opts2 & 0xffff), polling);
1da177e4
LT		 1053 ret = 0;
1054 } else
1055 ret = -1;
1056 desc->opts2 = 0;
1057 return ret;
1058}
1059
1060#else /* !CONFIG_R8169_VLAN */
1061
1062static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1063 struct sk_buff *skb)
1064{
1065 return 0;
1066}
1067
1068static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
6c3b9d34 1069 struct sk_buff *skb, int polling)
1da177e4
LT		 1070{
1071 return -1;
1072}
1073
1074#endif
1075
ccdffb9a 1076static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1077{
1078 struct rtl8169_private *tp = netdev_priv(dev);
1079 void __iomem *ioaddr = tp->mmio_addr;
1080 u32 status;
1081
1082 cmd->supported =
1083 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1084 cmd->port = PORT_FIBRE;
1085 cmd->transceiver = XCVR_INTERNAL;
1086
1087 status = RTL_R32(TBICSR);
1088 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1089 cmd->autoneg = !!(status & TBINwEnable);
1090
1091 cmd->speed = SPEED_1000;
1092 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1093
1094 return 0;
1da177e4
LT		 1095}
1096
ccdffb9a 1097static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1098{
1099 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1100
1101 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1102}
1103
1104static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1105{
1106 struct rtl8169_private *tp = netdev_priv(dev);
1107 unsigned long flags;
ccdffb9a 1108 int rc;
1da177e4
LT		 1109
1110 spin_lock_irqsave(&tp->lock, flags);
1111
ccdffb9a 1112 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1113
1114 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1115 return rc;
1da177e4
LT		 1116}
1117
1118static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1119 void *p)
1120{
5b0384f4
FR		 1121 struct rtl8169_private *tp = netdev_priv(dev);
1122 unsigned long flags;
1da177e4 1123
5b0384f4
FR		 1124 if (regs->len > R8169_REGS_SIZE)
1125 regs->len = R8169_REGS_SIZE;
1da177e4 1126
5b0384f4
FR		 1127 spin_lock_irqsave(&tp->lock, flags);
1128 memcpy_fromio(p, tp->mmio_addr, regs->len);
1129 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1130}
1131
b57b7e5a
SH		 1132static u32 rtl8169_get_msglevel(struct net_device *dev)
1133{
1134 struct rtl8169_private *tp = netdev_priv(dev);
1135
1136 return tp->msg_enable;
1137}
1138
1139static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1140{
1141 struct rtl8169_private *tp = netdev_priv(dev);
1142
1143 tp->msg_enable = value;
1144}
1145
d4a3a0fc
SH		 1146static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1147 "tx_packets",
1148 "rx_packets",
1149 "tx_errors",
1150 "rx_errors",
1151 "rx_missed",
1152 "align_errors",
1153 "tx_single_collisions",
1154 "tx_multi_collisions",
1155 "unicast",
1156 "broadcast",
1157 "multicast",
1158 "tx_aborted",
1159 "tx_underrun",
1160};
1161
b9f2c044 1162static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1163{
b9f2c044
JG		 1164 switch (sset) {
1165 case ETH_SS_STATS:
1166 return ARRAY_SIZE(rtl8169_gstrings);
1167 default:
1168 return -EOPNOTSUPP;
1169 }
d4a3a0fc
SH		 1170}
1171
355423d0 1172static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1173{
1174 struct rtl8169_private *tp = netdev_priv(dev);
1175 void __iomem *ioaddr = tp->mmio_addr;
1176 struct rtl8169_counters *counters;
1177 dma_addr_t paddr;
1178 u32 cmd;
355423d0 1179 int wait = 1000;
d4a3a0fc 1180
355423d0
IV		 1181 /*
1182 * Some chips are unable to dump tally counters when the receiver
1183 * is disabled.
1184 */
1185 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1186 return;
d4a3a0fc
SH		 1187
1188 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1189 if (!counters)
1190 return;
1191
1192 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1193 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1194 RTL_W32(CounterAddrLow, cmd);
1195 RTL_W32(CounterAddrLow, cmd | CounterDump);
1196
355423d0
IV		 1197 while (wait--) {
1198 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1199 /* copy updated counters */
1200 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1201 break;
355423d0
IV		 1202 }
1203 udelay(10);
d4a3a0fc
SH		 1204 }
1205
1206 RTL_W32(CounterAddrLow, 0);
1207 RTL_W32(CounterAddrHigh, 0);
1208
d4a3a0fc
SH		 1209 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1210}
1211
355423d0
IV		 1212static void rtl8169_get_ethtool_stats(struct net_device *dev,
1213 struct ethtool_stats *stats, u64 *data)
1214{
1215 struct rtl8169_private *tp = netdev_priv(dev);
1216
1217 ASSERT_RTNL();
1218
1219 rtl8169_update_counters(dev);
1220
1221 data[0] = le64_to_cpu(tp->counters.tx_packets);
1222 data[1] = le64_to_cpu(tp->counters.rx_packets);
1223 data[2] = le64_to_cpu(tp->counters.tx_errors);
1224 data[3] = le32_to_cpu(tp->counters.rx_errors);
1225 data[4] = le16_to_cpu(tp->counters.rx_missed);
1226 data[5] = le16_to_cpu(tp->counters.align_errors);
1227 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1228 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1229 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1230 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1231 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1232 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1233 data[12] = le16_to_cpu(tp->counters.tx_underun);
1234}
1235
d4a3a0fc
SH		 1236static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1237{
1238 switch(stringset) {
1239 case ETH_SS_STATS:
1240 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1241 break;
1242 }
1243}
1244
7282d491 1245static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1246 .get_drvinfo = rtl8169_get_drvinfo,
1247 .get_regs_len = rtl8169_get_regs_len,
1248 .get_link = ethtool_op_get_link,
1249 .get_settings = rtl8169_get_settings,
1250 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1251 .get_msglevel = rtl8169_get_msglevel,
1252 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1253 .get_rx_csum = rtl8169_get_rx_csum,
1254 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1255 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1256 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1257 .set_tso = ethtool_op_set_tso,
1258 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1259 .get_wol = rtl8169_get_wol,
1260 .set_wol = rtl8169_set_wol,
d4a3a0fc 1261 .get_strings = rtl8169_get_strings,
b9f2c044 1262 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1263 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1264};
1265
07d3f51f
FR		 1266static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1267 void __iomem *ioaddr)
1da177e4 1268{
0e485150
FR		 1269 /*
1270 * The driver currently handles the 8168Bf and the 8168Be identically
1271 * but they can be identified more specifically through the test below
1272 * if needed:
1273 *
1274 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1275 *
1276 * Same thing for the 8101Eb and the 8101Ec:
1277 *
1278 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1279 */
350f7596 1280 static const struct {
1da177e4 1281 u32 mask;
e3cf0cc0 1282 u32 val;
1da177e4
LT		 1283 int mac_version;
1284 } mac_info[] = {
5b538df9 1285 /* 8168D family. */
daf9df6d 1286 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1287 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1288 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1289 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1290
ef808d50 1291 /* 8168C family. */
7f3e3d3a 1292 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1293 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1294 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1295 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1296 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1297 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1298 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1299 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1300 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1301
1302 /* 8168B family. */
1303 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1304 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1305 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1306 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1307
1308 /* 8101 family. */
2857ffb7
FR		 1309 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1310 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1311 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1312 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1313 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1314 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1315 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1316 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1317 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1318 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1319 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1320 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1321 /* FIXME: where did these entries come from ? -- FR */
1322 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1323 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1324
1325 /* 8110 family. */
1326 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1327 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1328 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1329 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1330 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1331 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1332
f21b75e9
JD		 1333 /* Catch-all */
1334 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1da177e4
LT		 1335 }, *p = mac_info;
1336 u32 reg;
1337
e3cf0cc0
FR		 1338 reg = RTL_R32(TxConfig);
1339 while ((reg & p->mask) != p->val)
1da177e4
LT		 1340 p++;
1341 tp->mac_version = p->mac_version;
1342}
1343
1344static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1345{
bcf0bf90 1346 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1347}
1348
867763c1
FR		 1349struct phy_reg {
1350 u16 reg;
1351 u16 val;
1352};
1353
350f7596 1354static void rtl_phy_write(void __iomem *ioaddr, const struct phy_reg *regs, int len)
867763c1
FR		 1355{
1356 while (len-- > 0) {
1357 mdio_write(ioaddr, regs->reg, regs->val);
1358 regs++;
1359 }
1360}
1361
5615d9f1 1362static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1363{
350f7596 1364 static const struct phy_reg phy_reg_init[] = {
0b9b571d 1365 { 0x1f, 0x0001 },
1366 { 0x06, 0x006e },
1367 { 0x08, 0x0708 },
1368 { 0x15, 0x4000 },
1369 { 0x18, 0x65c7 },
1da177e4 1370
0b9b571d 1371 { 0x1f, 0x0001 },
1372 { 0x03, 0x00a1 },
1373 { 0x02, 0x0008 },
1374 { 0x01, 0x0120 },
1375 { 0x00, 0x1000 },
1376 { 0x04, 0x0800 },
1377 { 0x04, 0x0000 },
1da177e4 1378
0b9b571d 1379 { 0x03, 0xff41 },
1380 { 0x02, 0xdf60 },
1381 { 0x01, 0x0140 },
1382 { 0x00, 0x0077 },
1383 { 0x04, 0x7800 },
1384 { 0x04, 0x7000 },
1385
1386 { 0x03, 0x802f },
1387 { 0x02, 0x4f02 },
1388 { 0x01, 0x0409 },
1389 { 0x00, 0xf0f9 },
1390 { 0x04, 0x9800 },
1391 { 0x04, 0x9000 },
1392
1393 { 0x03, 0xdf01 },
1394 { 0x02, 0xdf20 },
1395 { 0x01, 0xff95 },
1396 { 0x00, 0xba00 },
1397 { 0x04, 0xa800 },
1398 { 0x04, 0xa000 },
1399
1400 { 0x03, 0xff41 },
1401 { 0x02, 0xdf20 },
1402 { 0x01, 0x0140 },
1403 { 0x00, 0x00bb },
1404 { 0x04, 0xb800 },
1405 { 0x04, 0xb000 },
1406
1407 { 0x03, 0xdf41 },
1408 { 0x02, 0xdc60 },
1409 { 0x01, 0x6340 },
1410 { 0x00, 0x007d },
1411 { 0x04, 0xd800 },
1412 { 0x04, 0xd000 },
1413
1414 { 0x03, 0xdf01 },
1415 { 0x02, 0xdf20 },
1416 { 0x01, 0x100a },
1417 { 0x00, 0xa0ff },
1418 { 0x04, 0xf800 },
1419 { 0x04, 0xf000 },
1420
1421 { 0x1f, 0x0000 },
1422 { 0x0b, 0x0000 },
1423 { 0x00, 0x9200 }
1424 };
1da177e4 1425
0b9b571d 1426 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 1427}
1428
5615d9f1
FR		 1429static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1430{
350f7596 1431 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 1432 { 0x1f, 0x0002 },
1433 { 0x01, 0x90d0 },
1434 { 0x1f, 0x0000 }
1435 };
1436
1437 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1438}
1439
2e955856 1440static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
1441 void __iomem *ioaddr)
1442{
1443 struct pci_dev *pdev = tp->pci_dev;
1444 u16 vendor_id, device_id;
1445
1446 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1447 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1448
1449 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1450 return;
1451
1452 mdio_write(ioaddr, 0x1f, 0x0001);
1453 mdio_write(ioaddr, 0x10, 0xf01b);
1454 mdio_write(ioaddr, 0x1f, 0x0000);
1455}
1456
1457static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
1458 void __iomem *ioaddr)
1459{
350f7596 1460 static const struct phy_reg phy_reg_init[] = {
2e955856 1461 { 0x1f, 0x0001 },
1462 { 0x04, 0x0000 },
1463 { 0x03, 0x00a1 },
1464 { 0x02, 0x0008 },
1465 { 0x01, 0x0120 },
1466 { 0x00, 0x1000 },
1467 { 0x04, 0x0800 },
1468 { 0x04, 0x9000 },
1469 { 0x03, 0x802f },
1470 { 0x02, 0x4f02 },
1471 { 0x01, 0x0409 },
1472 { 0x00, 0xf099 },
1473 { 0x04, 0x9800 },
1474 { 0x04, 0xa000 },
1475 { 0x03, 0xdf01 },
1476 { 0x02, 0xdf20 },
1477 { 0x01, 0xff95 },
1478 { 0x00, 0xba00 },
1479 { 0x04, 0xa800 },
1480 { 0x04, 0xf000 },
1481 { 0x03, 0xdf01 },
1482 { 0x02, 0xdf20 },
1483 { 0x01, 0x101a },
1484 { 0x00, 0xa0ff },
1485 { 0x04, 0xf800 },
1486 { 0x04, 0x0000 },
1487 { 0x1f, 0x0000 },
1488
1489 { 0x1f, 0x0001 },
1490 { 0x10, 0xf41b },
1491 { 0x14, 0xfb54 },
1492 { 0x18, 0xf5c7 },
1493 { 0x1f, 0x0000 },
1494
1495 { 0x1f, 0x0001 },
1496 { 0x17, 0x0cc0 },
1497 { 0x1f, 0x0000 }
1498 };
1499
1500 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1501
1502 rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
1503}
1504
8c7006aa 1505static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
1506{
350f7596 1507 static const struct phy_reg phy_reg_init[] = {
8c7006aa 1508 { 0x1f, 0x0001 },
1509 { 0x04, 0x0000 },
1510 { 0x03, 0x00a1 },
1511 { 0x02, 0x0008 },
1512 { 0x01, 0x0120 },
1513 { 0x00, 0x1000 },
1514 { 0x04, 0x0800 },
1515 { 0x04, 0x9000 },
1516 { 0x03, 0x802f },
1517 { 0x02, 0x4f02 },
1518 { 0x01, 0x0409 },
1519 { 0x00, 0xf099 },
1520 { 0x04, 0x9800 },
1521 { 0x04, 0xa000 },
1522 { 0x03, 0xdf01 },
1523 { 0x02, 0xdf20 },
1524 { 0x01, 0xff95 },
1525 { 0x00, 0xba00 },
1526 { 0x04, 0xa800 },
1527 { 0x04, 0xf000 },
1528 { 0x03, 0xdf01 },
1529 { 0x02, 0xdf20 },
1530 { 0x01, 0x101a },
1531 { 0x00, 0xa0ff },
1532 { 0x04, 0xf800 },
1533 { 0x04, 0x0000 },
1534 { 0x1f, 0x0000 },
1535
1536 { 0x1f, 0x0001 },
1537 { 0x0b, 0x8480 },
1538 { 0x1f, 0x0000 },
1539
1540 { 0x1f, 0x0001 },
1541 { 0x18, 0x67c7 },
1542 { 0x04, 0x2000 },
1543 { 0x03, 0x002f },
1544 { 0x02, 0x4360 },
1545 { 0x01, 0x0109 },
1546 { 0x00, 0x3022 },
1547 { 0x04, 0x2800 },
1548 { 0x1f, 0x0000 },
1549
1550 { 0x1f, 0x0001 },
1551 { 0x17, 0x0cc0 },
1552 { 0x1f, 0x0000 }
1553 };
1554
1555 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1556}
1557
236b8082
FR		 1558static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1559{
350f7596 1560 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 1561 { 0x10, 0xf41b },
1562 { 0x1f, 0x0000 }
1563 };
1564
1565 mdio_write(ioaddr, 0x1f, 0x0001);
1566 mdio_patch(ioaddr, 0x16, 1 << 0);
1567
1568 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1569}
1570
1571static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1572{
350f7596 1573 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 1574 { 0x1f, 0x0001 },
1575 { 0x10, 0xf41b },
1576 { 0x1f, 0x0000 }
1577 };
1578
1579 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1580}
1581
ef3386f0 1582static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
867763c1 1583{
350f7596 1584 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 1585 { 0x1f, 0x0000 },
1586 { 0x1d, 0x0f00 },
1587 { 0x1f, 0x0002 },
1588 { 0x0c, 0x1ec8 },
1589 { 0x1f, 0x0000 }
1590 };
1591
1592 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1593}
1594
ef3386f0
FR		 1595static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1596{
350f7596 1597 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 1598 { 0x1f, 0x0001 },
1599 { 0x1d, 0x3d98 },
1600 { 0x1f, 0x0000 }
1601 };
1602
1603 mdio_write(ioaddr, 0x1f, 0x0000);
1604 mdio_patch(ioaddr, 0x14, 1 << 5);
1605 mdio_patch(ioaddr, 0x0d, 1 << 5);
1606
1607 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1608}
1609
219a1e9d 1610static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
867763c1 1611{
350f7596 1612 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1613 { 0x1f, 0x0001 },
1614 { 0x12, 0x2300 },
867763c1
FR		 1615 { 0x1f, 0x0002 },
1616 { 0x00, 0x88d4 },
1617 { 0x01, 0x82b1 },
1618 { 0x03, 0x7002 },
1619 { 0x08, 0x9e30 },
1620 { 0x09, 0x01f0 },
1621 { 0x0a, 0x5500 },
1622 { 0x0c, 0x00c8 },
1623 { 0x1f, 0x0003 },
1624 { 0x12, 0xc096 },
1625 { 0x16, 0x000a },
f50d4275
FR		 1626 { 0x1f, 0x0000 },
1627 { 0x1f, 0x0000 },
1628 { 0x09, 0x2000 },
1629 { 0x09, 0x0000 }
867763c1
FR		 1630 };
1631
1632 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1633
1634 mdio_patch(ioaddr, 0x14, 1 << 5);
1635 mdio_patch(ioaddr, 0x0d, 1 << 5);
1636 mdio_write(ioaddr, 0x1f, 0x0000);
867763c1
FR		 1637}
1638
219a1e9d 1639static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
7da97ec9 1640{
350f7596 1641 static const struct phy_reg phy_reg_init[] = {
f50d4275 1642 { 0x1f, 0x0001 },
7da97ec9 1643 { 0x12, 0x2300 },
f50d4275
FR		 1644 { 0x03, 0x802f },
1645 { 0x02, 0x4f02 },
1646 { 0x01, 0x0409 },
1647 { 0x00, 0xf099 },
1648 { 0x04, 0x9800 },
1649 { 0x04, 0x9000 },
1650 { 0x1d, 0x3d98 },
7da97ec9
FR		 1651 { 0x1f, 0x0002 },
1652 { 0x0c, 0x7eb8 },
f50d4275
FR		 1653 { 0x06, 0x0761 },
1654 { 0x1f, 0x0003 },
1655 { 0x16, 0x0f0a },
7da97ec9
FR		 1656 { 0x1f, 0x0000 }
1657 };
1658
1659 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1660
1661 mdio_patch(ioaddr, 0x16, 1 << 0);
1662 mdio_patch(ioaddr, 0x14, 1 << 5);
1663 mdio_patch(ioaddr, 0x0d, 1 << 5);
1664 mdio_write(ioaddr, 0x1f, 0x0000);
7da97ec9
FR		 1665}
1666
197ff761
FR		 1667static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1668{
350f7596 1669 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 1670 { 0x1f, 0x0001 },
1671 { 0x12, 0x2300 },
1672 { 0x1d, 0x3d98 },
1673 { 0x1f, 0x0002 },
1674 { 0x0c, 0x7eb8 },
1675 { 0x06, 0x5461 },
1676 { 0x1f, 0x0003 },
1677 { 0x16, 0x0f0a },
1678 { 0x1f, 0x0000 }
1679 };
1680
1681 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1682
1683 mdio_patch(ioaddr, 0x16, 1 << 0);
1684 mdio_patch(ioaddr, 0x14, 1 << 5);
1685 mdio_patch(ioaddr, 0x0d, 1 << 5);
1686 mdio_write(ioaddr, 0x1f, 0x0000);
1687}
1688
6fb07058
FR		 1689static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1690{
1691 rtl8168c_3_hw_phy_config(ioaddr);
1692}
1693
daf9df6d 1694static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
5b538df9 1695{
350f7596 1696 static const struct phy_reg phy_reg_init_0[] = {
5b538df9 1697 { 0x1f, 0x0001 },
daf9df6d 1698 { 0x06, 0x4064 },
1699 { 0x07, 0x2863 },
1700 { 0x08, 0x059c },
1701 { 0x09, 0x26b4 },
1702 { 0x0a, 0x6a19 },
1703 { 0x0b, 0xdcc8 },
1704 { 0x10, 0xf06d },
1705 { 0x14, 0x7f68 },
1706 { 0x18, 0x7fd9 },
1707 { 0x1c, 0xf0ff },
1708 { 0x1d, 0x3d9c },
5b538df9 1709 { 0x1f, 0x0003 },
daf9df6d 1710 { 0x12, 0xf49f },
1711 { 0x13, 0x070b },
1712 { 0x1a, 0x05ad },
1713 { 0x14, 0x94c0 }
1714 };
350f7596 1715 static const struct phy_reg phy_reg_init_1[] = {
5b538df9 1716 { 0x1f, 0x0002 },
daf9df6d 1717 { 0x06, 0x5561 },
1718 { 0x1f, 0x0005 },
1719 { 0x05, 0x8332 },
1720 { 0x06, 0x5561 }
1721 };
350f7596 1722 static const struct phy_reg phy_reg_init_2[] = {
daf9df6d 1723 { 0x1f, 0x0005 },
1724 { 0x05, 0xffc2 },
1725 { 0x1f, 0x0005 },
1726 { 0x05, 0x8000 },
1727 { 0x06, 0xf8f9 },
1728 { 0x06, 0xfaef },
1729 { 0x06, 0x59ee },
1730 { 0x06, 0xf8ea },
1731 { 0x06, 0x00ee },
1732 { 0x06, 0xf8eb },
1733 { 0x06, 0x00e0 },
1734 { 0x06, 0xf87c },
1735 { 0x06, 0xe1f8 },
1736 { 0x06, 0x7d59 },
1737 { 0x06, 0x0fef },
1738 { 0x06, 0x0139 },
1739 { 0x06, 0x029e },
1740 { 0x06, 0x06ef },
1741 { 0x06, 0x1039 },
1742 { 0x06, 0x089f },
1743 { 0x06, 0x2aee },
1744 { 0x06, 0xf8ea },
1745 { 0x06, 0x00ee },
1746 { 0x06, 0xf8eb },
1747 { 0x06, 0x01e0 },
1748 { 0x06, 0xf87c },
1749 { 0x06, 0xe1f8 },
1750 { 0x06, 0x7d58 },
1751 { 0x06, 0x409e },
1752 { 0x06, 0x0f39 },
1753 { 0x06, 0x46aa },
1754 { 0x06, 0x0bbf },
1755 { 0x06, 0x8290 },
1756 { 0x06, 0xd682 },
1757 { 0x06, 0x9802 },
1758 { 0x06, 0x014f },
1759 { 0x06, 0xae09 },
1760 { 0x06, 0xbf82 },
1761 { 0x06, 0x98d6 },
1762 { 0x06, 0x82a0 },
1763 { 0x06, 0x0201 },
1764 { 0x06, 0x4fef },
1765 { 0x06, 0x95fe },
1766 { 0x06, 0xfdfc },
1767 { 0x06, 0x05f8 },
1768 { 0x06, 0xf9fa },
1769 { 0x06, 0xeef8 },
1770 { 0x06, 0xea00 },
1771 { 0x06, 0xeef8 },
1772 { 0x06, 0xeb00 },
1773 { 0x06, 0xe2f8 },
1774 { 0x06, 0x7ce3 },
1775 { 0x06, 0xf87d },
1776 { 0x06, 0xa511 },
1777 { 0x06, 0x1112 },
1778 { 0x06, 0xd240 },
1779 { 0x06, 0xd644 },
1780 { 0x06, 0x4402 },
1781 { 0x06, 0x8217 },
1782 { 0x06, 0xd2a0 },
1783 { 0x06, 0xd6aa },
1784 { 0x06, 0xaa02 },
1785 { 0x06, 0x8217 },
1786 { 0x06, 0xae0f },
1787 { 0x06, 0xa544 },
1788 { 0x06, 0x4402 },
1789 { 0x06, 0xae4d },
1790 { 0x06, 0xa5aa },
1791 { 0x06, 0xaa02 },
1792 { 0x06, 0xae47 },
1793 { 0x06, 0xaf82 },
1794 { 0x06, 0x13ee },
1795 { 0x06, 0x834e },
1796 { 0x06, 0x00ee },
1797 { 0x06, 0x834d },
1798 { 0x06, 0x0fee },
1799 { 0x06, 0x834c },
1800 { 0x06, 0x0fee },
1801 { 0x06, 0x834f },
1802 { 0x06, 0x00ee },
1803 { 0x06, 0x8351 },
1804 { 0x06, 0x00ee },
1805 { 0x06, 0x834a },
1806 { 0x06, 0xffee },
1807 { 0x06, 0x834b },
1808 { 0x06, 0xffe0 },
1809 { 0x06, 0x8330 },
1810 { 0x06, 0xe183 },
1811 { 0x06, 0x3158 },
1812 { 0x06, 0xfee4 },
1813 { 0x06, 0xf88a },
1814 { 0x06, 0xe5f8 },
1815 { 0x06, 0x8be0 },
1816 { 0x06, 0x8332 },
1817 { 0x06, 0xe183 },
1818 { 0x06, 0x3359 },
1819 { 0x06, 0x0fe2 },
1820 { 0x06, 0x834d },
1821 { 0x06, 0x0c24 },
1822 { 0x06, 0x5af0 },
1823 { 0x06, 0x1e12 },
1824 { 0x06, 0xe4f8 },
1825 { 0x06, 0x8ce5 },
1826 { 0x06, 0xf88d },
1827 { 0x06, 0xaf82 },
1828 { 0x06, 0x13e0 },
1829 { 0x06, 0x834f },
1830 { 0x06, 0x10e4 },
1831 { 0x06, 0x834f },
1832 { 0x06, 0xe083 },
1833 { 0x06, 0x4e78 },
1834 { 0x06, 0x009f },
1835 { 0x06, 0x0ae0 },
1836 { 0x06, 0x834f },
1837 { 0x06, 0xa010 },
1838 { 0x06, 0xa5ee },
1839 { 0x06, 0x834e },
1840 { 0x06, 0x01e0 },
1841 { 0x06, 0x834e },
1842 { 0x06, 0x7805 },
1843 { 0x06, 0x9e9a },
1844 { 0x06, 0xe083 },
1845 { 0x06, 0x4e78 },
1846 { 0x06, 0x049e },
1847 { 0x06, 0x10e0 },
1848 { 0x06, 0x834e },
1849 { 0x06, 0x7803 },
1850 { 0x06, 0x9e0f },
1851 { 0x06, 0xe083 },
1852 { 0x06, 0x4e78 },
1853 { 0x06, 0x019e },
1854 { 0x06, 0x05ae },
1855 { 0x06, 0x0caf },
1856 { 0x06, 0x81f8 },
1857 { 0x06, 0xaf81 },
1858 { 0x06, 0xa3af },
1859 { 0x06, 0x81dc },
1860 { 0x06, 0xaf82 },
1861 { 0x06, 0x13ee },
1862 { 0x06, 0x8348 },
1863 { 0x06, 0x00ee },
1864 { 0x06, 0x8349 },
1865 { 0x06, 0x00e0 },
1866 { 0x06, 0x8351 },
1867 { 0x06, 0x10e4 },
1868 { 0x06, 0x8351 },
1869 { 0x06, 0x5801 },
1870 { 0x06, 0x9fea },
1871 { 0x06, 0xd000 },
1872 { 0x06, 0xd180 },
1873 { 0x06, 0x1f66 },
1874 { 0x06, 0xe2f8 },
1875 { 0x06, 0xeae3 },
1876 { 0x06, 0xf8eb },
1877 { 0x06, 0x5af8 },
1878 { 0x06, 0x1e20 },
1879 { 0x06, 0xe6f8 },
1880 { 0x06, 0xeae5 },
1881 { 0x06, 0xf8eb },
1882 { 0x06, 0xd302 },
1883 { 0x06, 0xb3fe },
1884 { 0x06, 0xe2f8 },
1885 { 0x06, 0x7cef },
1886 { 0x06, 0x325b },
1887 { 0x06, 0x80e3 },
1888 { 0x06, 0xf87d },
1889 { 0x06, 0x9e03 },
1890 { 0x06, 0x7dff },
1891 { 0x06, 0xff0d },
1892 { 0x06, 0x581c },
1893 { 0x06, 0x551a },
1894 { 0x06, 0x6511 },
1895 { 0x06, 0xa190 },
1896 { 0x06, 0xd3e2 },
1897 { 0x06, 0x8348 },
1898 { 0x06, 0xe383 },
1899 { 0x06, 0x491b },
1900 { 0x06, 0x56ab },
1901 { 0x06, 0x08ef },
1902 { 0x06, 0x56e6 },
1903 { 0x06, 0x8348 },
1904 { 0x06, 0xe783 },
1905 { 0x06, 0x4910 },
1906 { 0x06, 0xd180 },
1907 { 0x06, 0x1f66 },
1908 { 0x06, 0xa004 },
1909 { 0x06, 0xb9e2 },
1910 { 0x06, 0x8348 },
1911 { 0x06, 0xe383 },
1912 { 0x06, 0x49ef },
1913 { 0x06, 0x65e2 },
1914 { 0x06, 0x834a },
1915 { 0x06, 0xe383 },
1916 { 0x06, 0x4b1b },
1917 { 0x06, 0x56aa },
1918 { 0x06, 0x0eef },
1919 { 0x06, 0x56e6 },
1920 { 0x06, 0x834a },
1921 { 0x06, 0xe783 },
1922 { 0x06, 0x4be2 },
1923 { 0x06, 0x834d },
1924 { 0x06, 0xe683 },
1925 { 0x06, 0x4ce0 },
1926 { 0x06, 0x834d },
1927 { 0x06, 0xa000 },
1928 { 0x06, 0x0caf },
1929 { 0x06, 0x81dc },
1930 { 0x06, 0xe083 },
1931 { 0x06, 0x4d10 },
1932 { 0x06, 0xe483 },
1933 { 0x06, 0x4dae },
1934 { 0x06, 0x0480 },
1935 { 0x06, 0xe483 },
1936 { 0x06, 0x4de0 },
1937 { 0x06, 0x834e },
1938 { 0x06, 0x7803 },
1939 { 0x06, 0x9e0b },
1940 { 0x06, 0xe083 },
1941 { 0x06, 0x4e78 },
1942 { 0x06, 0x049e },
1943 { 0x06, 0x04ee },
1944 { 0x06, 0x834e },
1945 { 0x06, 0x02e0 },
1946 { 0x06, 0x8332 },
1947 { 0x06, 0xe183 },
1948 { 0x06, 0x3359 },
1949 { 0x06, 0x0fe2 },
1950 { 0x06, 0x834d },
1951 { 0x06, 0x0c24 },
1952 { 0x06, 0x5af0 },
1953 { 0x06, 0x1e12 },
1954 { 0x06, 0xe4f8 },
1955 { 0x06, 0x8ce5 },
1956 { 0x06, 0xf88d },
1957 { 0x06, 0xe083 },
1958 { 0x06, 0x30e1 },
1959 { 0x06, 0x8331 },
1960 { 0x06, 0x6801 },
1961 { 0x06, 0xe4f8 },
1962 { 0x06, 0x8ae5 },
1963 { 0x06, 0xf88b },
1964 { 0x06, 0xae37 },
1965 { 0x06, 0xee83 },
1966 { 0x06, 0x4e03 },
1967 { 0x06, 0xe083 },
1968 { 0x06, 0x4ce1 },
1969 { 0x06, 0x834d },
1970 { 0x06, 0x1b01 },
1971 { 0x06, 0x9e04 },
1972 { 0x06, 0xaaa1 },
1973 { 0x06, 0xaea8 },
1974 { 0x06, 0xee83 },
1975 { 0x06, 0x4e04 },
1976 { 0x06, 0xee83 },
1977 { 0x06, 0x4f00 },
1978 { 0x06, 0xaeab },
1979 { 0x06, 0xe083 },
1980 { 0x06, 0x4f78 },
1981 { 0x06, 0x039f },
1982 { 0x06, 0x14ee },
1983 { 0x06, 0x834e },
1984 { 0x06, 0x05d2 },
1985 { 0x06, 0x40d6 },
1986 { 0x06, 0x5554 },
1987 { 0x06, 0x0282 },
1988 { 0x06, 0x17d2 },
1989 { 0x06, 0xa0d6 },
1990 { 0x06, 0xba00 },
1991 { 0x06, 0x0282 },
1992 { 0x06, 0x17fe },
1993 { 0x06, 0xfdfc },
1994 { 0x06, 0x05f8 },
1995 { 0x06, 0xe0f8 },
1996 { 0x06, 0x60e1 },
1997 { 0x06, 0xf861 },
1998 { 0x06, 0x6802 },
1999 { 0x06, 0xe4f8 },
2000 { 0x06, 0x60e5 },
2001 { 0x06, 0xf861 },
2002 { 0x06, 0xe0f8 },
2003 { 0x06, 0x48e1 },
2004 { 0x06, 0xf849 },
2005 { 0x06, 0x580f },
2006 { 0x06, 0x1e02 },
2007 { 0x06, 0xe4f8 },
2008 { 0x06, 0x48e5 },
2009 { 0x06, 0xf849 },
2010 { 0x06, 0xd000 },
2011 { 0x06, 0x0282 },
2012 { 0x06, 0x5bbf },
2013 { 0x06, 0x8350 },
2014 { 0x06, 0xef46 },
2015 { 0x06, 0xdc19 },
2016 { 0x06, 0xddd0 },
2017 { 0x06, 0x0102 },
2018 { 0x06, 0x825b },
2019 { 0x06, 0x0282 },
2020 { 0x06, 0x77e0 },
2021 { 0x06, 0xf860 },
2022 { 0x06, 0xe1f8 },
2023 { 0x06, 0x6158 },
2024 { 0x06, 0xfde4 },
2025 { 0x06, 0xf860 },
2026 { 0x06, 0xe5f8 },
2027 { 0x06, 0x61fc },
2028 { 0x06, 0x04f9 },
2029 { 0x06, 0xfafb },
2030 { 0x06, 0xc6bf },
2031 { 0x06, 0xf840 },
2032 { 0x06, 0xbe83 },
2033 { 0x06, 0x50a0 },
2034 { 0x06, 0x0101 },
2035 { 0x06, 0x071b },
2036 { 0x06, 0x89cf },
2037 { 0x06, 0xd208 },
2038 { 0x06, 0xebdb },
2039 { 0x06, 0x19b2 },
2040 { 0x06, 0xfbff },
2041 { 0x06, 0xfefd },
2042 { 0x06, 0x04f8 },
2043 { 0x06, 0xe0f8 },
2044 { 0x06, 0x48e1 },
2045 { 0x06, 0xf849 },
2046 { 0x06, 0x6808 },
2047 { 0x06, 0xe4f8 },
2048 { 0x06, 0x48e5 },
2049 { 0x06, 0xf849 },
2050 { 0x06, 0x58f7 },
2051 { 0x06, 0xe4f8 },
2052 { 0x06, 0x48e5 },
2053 { 0x06, 0xf849 },
2054 { 0x06, 0xfc04 },
2055 { 0x06, 0x4d20 },
2056 { 0x06, 0x0002 },
2057 { 0x06, 0x4e22 },
2058 { 0x06, 0x0002 },
2059 { 0x06, 0x4ddf },
2060 { 0x06, 0xff01 },
2061 { 0x06, 0x4edd },
2062 { 0x06, 0xff01 },
2063 { 0x05, 0x83d4 },
2064 { 0x06, 0x8000 },
2065 { 0x05, 0x83d8 },
2066 { 0x06, 0x8051 },
2067 { 0x02, 0x6010 },
2068 { 0x03, 0xdc00 },
2069 { 0x05, 0xfff6 },
2070 { 0x06, 0x00fc },
5b538df9 2071 { 0x1f, 0x0000 },
daf9df6d 2072
5b538df9 2073 { 0x1f, 0x0000 },
daf9df6d 2074 { 0x0d, 0xf880 },
2075 { 0x1f, 0x0000 }
2076 };
2077
2078 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2079
2080 mdio_write(ioaddr, 0x1f, 0x0002);
2081 mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
2082 mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);
2083
2084 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2085
2086 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2087 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2088 { 0x1f, 0x0002 },
2089 { 0x05, 0x669a },
2090 { 0x1f, 0x0005 },
2091 { 0x05, 0x8330 },
2092 { 0x06, 0x669a },
2093 { 0x1f, 0x0002 }
2094 };
2095 int val;
2096
2097 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2098
2099 val = mdio_read(ioaddr, 0x0d);
2100
2101 if ((val & 0x00ff) != 0x006c) {
350f7596 2102 static const u32 set[] = {
daf9df6d 2103 0x0065, 0x0066, 0x0067, 0x0068,
2104 0x0069, 0x006a, 0x006b, 0x006c
2105 };
2106 int i;
2107
2108 mdio_write(ioaddr, 0x1f, 0x0002);
2109
2110 val &= 0xff00;
2111 for (i = 0; i < ARRAY_SIZE(set); i++)
2112 mdio_write(ioaddr, 0x0d, val | set[i]);
2113 }
2114 } else {
350f7596 2115 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2116 { 0x1f, 0x0002 },
2117 { 0x05, 0x6662 },
2118 { 0x1f, 0x0005 },
2119 { 0x05, 0x8330 },
2120 { 0x06, 0x6662 }
2121 };
2122
2123 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2124 }
2125
2126 mdio_write(ioaddr, 0x1f, 0x0002);
2127 mdio_patch(ioaddr, 0x0d, 0x0300);
2128 mdio_patch(ioaddr, 0x0f, 0x0010);
2129
2130 mdio_write(ioaddr, 0x1f, 0x0002);
2131 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2132 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2133
2134 rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2));
2135}
2136
2137static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
2138{
350f7596 2139 static const struct phy_reg phy_reg_init_0[] = {
daf9df6d 2140 { 0x1f, 0x0001 },
2141 { 0x06, 0x4064 },
2142 { 0x07, 0x2863 },
2143 { 0x08, 0x059c },
2144 { 0x09, 0x26b4 },
2145 { 0x0a, 0x6a19 },
2146 { 0x0b, 0xdcc8 },
2147 { 0x10, 0xf06d },
2148 { 0x14, 0x7f68 },
2149 { 0x18, 0x7fd9 },
2150 { 0x1c, 0xf0ff },
2151 { 0x1d, 0x3d9c },
2152 { 0x1f, 0x0003 },
2153 { 0x12, 0xf49f },
2154 { 0x13, 0x070b },
2155 { 0x1a, 0x05ad },
2156 { 0x14, 0x94c0 },
2157
2158 { 0x1f, 0x0002 },
2159 { 0x06, 0x5561 },
2160 { 0x1f, 0x0005 },
2161 { 0x05, 0x8332 },
2162 { 0x06, 0x5561 }
2163 };
350f7596 2164 static const struct phy_reg phy_reg_init_1[] = {
daf9df6d 2165 { 0x1f, 0x0005 },
2166 { 0x05, 0xffc2 },
5b538df9 2167 { 0x1f, 0x0005 },
daf9df6d 2168 { 0x05, 0x8000 },
2169 { 0x06, 0xf8f9 },
2170 { 0x06, 0xfaee },
2171 { 0x06, 0xf8ea },
2172 { 0x06, 0x00ee },
2173 { 0x06, 0xf8eb },
2174 { 0x06, 0x00e2 },
2175 { 0x06, 0xf87c },
2176 { 0x06, 0xe3f8 },
2177 { 0x06, 0x7da5 },
2178 { 0x06, 0x1111 },
2179 { 0x06, 0x12d2 },
2180 { 0x06, 0x40d6 },
2181 { 0x06, 0x4444 },
2182 { 0x06, 0x0281 },
2183 { 0x06, 0xc6d2 },
2184 { 0x06, 0xa0d6 },
2185 { 0x06, 0xaaaa },
2186 { 0x06, 0x0281 },
2187 { 0x06, 0xc6ae },
2188 { 0x06, 0x0fa5 },
2189 { 0x06, 0x4444 },
2190 { 0x06, 0x02ae },
2191 { 0x06, 0x4da5 },
2192 { 0x06, 0xaaaa },
2193 { 0x06, 0x02ae },
2194 { 0x06, 0x47af },
2195 { 0x06, 0x81c2 },
2196 { 0x06, 0xee83 },
2197 { 0x06, 0x4e00 },
2198 { 0x06, 0xee83 },
2199 { 0x06, 0x4d0f },
2200 { 0x06, 0xee83 },
2201 { 0x06, 0x4c0f },
2202 { 0x06, 0xee83 },
2203 { 0x06, 0x4f00 },
2204 { 0x06, 0xee83 },
2205 { 0x06, 0x5100 },
2206 { 0x06, 0xee83 },
2207 { 0x06, 0x4aff },
2208 { 0x06, 0xee83 },
2209 { 0x06, 0x4bff },
2210 { 0x06, 0xe083 },
2211 { 0x06, 0x30e1 },
2212 { 0x06, 0x8331 },
2213 { 0x06, 0x58fe },
2214 { 0x06, 0xe4f8 },
2215 { 0x06, 0x8ae5 },
2216 { 0x06, 0xf88b },
2217 { 0x06, 0xe083 },
2218 { 0x06, 0x32e1 },
2219 { 0x06, 0x8333 },
2220 { 0x06, 0x590f },
2221 { 0x06, 0xe283 },
2222 { 0x06, 0x4d0c },
2223 { 0x06, 0x245a },
2224 { 0x06, 0xf01e },
2225 { 0x06, 0x12e4 },
2226 { 0x06, 0xf88c },
2227 { 0x06, 0xe5f8 },
2228 { 0x06, 0x8daf },
2229 { 0x06, 0x81c2 },
2230 { 0x06, 0xe083 },
2231 { 0x06, 0x4f10 },
2232 { 0x06, 0xe483 },
2233 { 0x06, 0x4fe0 },
2234 { 0x06, 0x834e },
2235 { 0x06, 0x7800 },
2236 { 0x06, 0x9f0a },
2237 { 0x06, 0xe083 },
2238 { 0x06, 0x4fa0 },
2239 { 0x06, 0x10a5 },
2240 { 0x06, 0xee83 },
2241 { 0x06, 0x4e01 },
2242 { 0x06, 0xe083 },
2243 { 0x06, 0x4e78 },
2244 { 0x06, 0x059e },
2245 { 0x06, 0x9ae0 },
2246 { 0x06, 0x834e },
2247 { 0x06, 0x7804 },
2248 { 0x06, 0x9e10 },
2249 { 0x06, 0xe083 },
2250 { 0x06, 0x4e78 },
2251 { 0x06, 0x039e },
2252 { 0x06, 0x0fe0 },
2253 { 0x06, 0x834e },
2254 { 0x06, 0x7801 },
2255 { 0x06, 0x9e05 },
2256 { 0x06, 0xae0c },
2257 { 0x06, 0xaf81 },
2258 { 0x06, 0xa7af },
2259 { 0x06, 0x8152 },
2260 { 0x06, 0xaf81 },
2261 { 0x06, 0x8baf },
2262 { 0x06, 0x81c2 },
2263 { 0x06, 0xee83 },
2264 { 0x06, 0x4800 },
2265 { 0x06, 0xee83 },
2266 { 0x06, 0x4900 },
2267 { 0x06, 0xe083 },
2268 { 0x06, 0x5110 },
2269 { 0x06, 0xe483 },
2270 { 0x06, 0x5158 },
2271 { 0x06, 0x019f },
2272 { 0x06, 0xead0 },
2273 { 0x06, 0x00d1 },
2274 { 0x06, 0x801f },
2275 { 0x06, 0x66e2 },
2276 { 0x06, 0xf8ea },
2277 { 0x06, 0xe3f8 },
2278 { 0x06, 0xeb5a },
2279 { 0x06, 0xf81e },
2280 { 0x06, 0x20e6 },
2281 { 0x06, 0xf8ea },
2282 { 0x06, 0xe5f8 },
2283 { 0x06, 0xebd3 },
2284 { 0x06, 0x02b3 },
2285 { 0x06, 0xfee2 },
2286 { 0x06, 0xf87c },
2287 { 0x06, 0xef32 },
2288 { 0x06, 0x5b80 },
2289 { 0x06, 0xe3f8 },
2290 { 0x06, 0x7d9e },
2291 { 0x06, 0x037d },
2292 { 0x06, 0xffff },
2293 { 0x06, 0x0d58 },
2294 { 0x06, 0x1c55 },
2295 { 0x06, 0x1a65 },
2296 { 0x06, 0x11a1 },
2297 { 0x06, 0x90d3 },
2298 { 0x06, 0xe283 },
2299 { 0x06, 0x48e3 },
2300 { 0x06, 0x8349 },
2301 { 0x06, 0x1b56 },
2302 { 0x06, 0xab08 },
2303 { 0x06, 0xef56 },
2304 { 0x06, 0xe683 },
2305 { 0x06, 0x48e7 },
2306 { 0x06, 0x8349 },
2307 { 0x06, 0x10d1 },
2308 { 0x06, 0x801f },
2309 { 0x06, 0x66a0 },
2310 { 0x06, 0x04b9 },
2311 { 0x06, 0xe283 },
2312 { 0x06, 0x48e3 },
2313 { 0x06, 0x8349 },
2314 { 0x06, 0xef65 },
2315 { 0x06, 0xe283 },
2316 { 0x06, 0x4ae3 },
2317 { 0x06, 0x834b },
2318 { 0x06, 0x1b56 },
2319 { 0x06, 0xaa0e },
2320 { 0x06, 0xef56 },
2321 { 0x06, 0xe683 },
2322 { 0x06, 0x4ae7 },
2323 { 0x06, 0x834b },
2324 { 0x06, 0xe283 },
2325 { 0x06, 0x4de6 },
2326 { 0x06, 0x834c },
2327 { 0x06, 0xe083 },
2328 { 0x06, 0x4da0 },
2329 { 0x06, 0x000c },
2330 { 0x06, 0xaf81 },
2331 { 0x06, 0x8be0 },
2332 { 0x06, 0x834d },
2333 { 0x06, 0x10e4 },
2334 { 0x06, 0x834d },
2335 { 0x06, 0xae04 },
2336 { 0x06, 0x80e4 },
2337 { 0x06, 0x834d },
2338 { 0x06, 0xe083 },
2339 { 0x06, 0x4e78 },
2340 { 0x06, 0x039e },
2341 { 0x06, 0x0be0 },
2342 { 0x06, 0x834e },
2343 { 0x06, 0x7804 },
2344 { 0x06, 0x9e04 },
2345 { 0x06, 0xee83 },
2346 { 0x06, 0x4e02 },
2347 { 0x06, 0xe083 },
2348 { 0x06, 0x32e1 },
2349 { 0x06, 0x8333 },
2350 { 0x06, 0x590f },
2351 { 0x06, 0xe283 },
2352 { 0x06, 0x4d0c },
2353 { 0x06, 0x245a },
2354 { 0x06, 0xf01e },
2355 { 0x06, 0x12e4 },
2356 { 0x06, 0xf88c },
2357 { 0x06, 0xe5f8 },
2358 { 0x06, 0x8de0 },
2359 { 0x06, 0x8330 },
2360 { 0x06, 0xe183 },
2361 { 0x06, 0x3168 },
2362 { 0x06, 0x01e4 },
2363 { 0x06, 0xf88a },
2364 { 0x06, 0xe5f8 },
2365 { 0x06, 0x8bae },
2366 { 0x06, 0x37ee },
2367 { 0x06, 0x834e },
2368 { 0x06, 0x03e0 },
2369 { 0x06, 0x834c },
2370 { 0x06, 0xe183 },
2371 { 0x06, 0x4d1b },
2372 { 0x06, 0x019e },
2373 { 0x06, 0x04aa },
2374 { 0x06, 0xa1ae },
2375 { 0x06, 0xa8ee },
2376 { 0x06, 0x834e },
2377 { 0x06, 0x04ee },
2378 { 0x06, 0x834f },
2379 { 0x06, 0x00ae },
2380 { 0x06, 0xabe0 },
2381 { 0x06, 0x834f },
2382 { 0x06, 0x7803 },
2383 { 0x06, 0x9f14 },
2384 { 0x06, 0xee83 },
2385 { 0x06, 0x4e05 },
2386 { 0x06, 0xd240 },
2387 { 0x06, 0xd655 },
2388 { 0x06, 0x5402 },
2389 { 0x06, 0x81c6 },
2390 { 0x06, 0xd2a0 },
2391 { 0x06, 0xd6ba },
2392 { 0x06, 0x0002 },
2393 { 0x06, 0x81c6 },
2394 { 0x06, 0xfefd },
2395 { 0x06, 0xfc05 },
2396 { 0x06, 0xf8e0 },
2397 { 0x06, 0xf860 },
2398 { 0x06, 0xe1f8 },
2399 { 0x06, 0x6168 },
2400 { 0x06, 0x02e4 },
2401 { 0x06, 0xf860 },
2402 { 0x06, 0xe5f8 },
2403 { 0x06, 0x61e0 },
2404 { 0x06, 0xf848 },
2405 { 0x06, 0xe1f8 },
2406 { 0x06, 0x4958 },
2407 { 0x06, 0x0f1e },
2408 { 0x06, 0x02e4 },
2409 { 0x06, 0xf848 },
2410 { 0x06, 0xe5f8 },
2411 { 0x06, 0x49d0 },
2412 { 0x06, 0x0002 },
2413 { 0x06, 0x820a },
2414 { 0x06, 0xbf83 },
2415 { 0x06, 0x50ef },
2416 { 0x06, 0x46dc },
2417 { 0x06, 0x19dd },
2418 { 0x06, 0xd001 },
2419 { 0x06, 0x0282 },
2420 { 0x06, 0x0a02 },
2421 { 0x06, 0x8226 },
2422 { 0x06, 0xe0f8 },
2423 { 0x06, 0x60e1 },
2424 { 0x06, 0xf861 },
2425 { 0x06, 0x58fd },
2426 { 0x06, 0xe4f8 },
2427 { 0x06, 0x60e5 },
2428 { 0x06, 0xf861 },
2429 { 0x06, 0xfc04 },
2430 { 0x06, 0xf9fa },
2431 { 0x06, 0xfbc6 },
2432 { 0x06, 0xbff8 },
2433 { 0x06, 0x40be },
2434 { 0x06, 0x8350 },
2435 { 0x06, 0xa001 },
2436 { 0x06, 0x0107 },
2437 { 0x06, 0x1b89 },
2438 { 0x06, 0xcfd2 },
2439 { 0x06, 0x08eb },
2440 { 0x06, 0xdb19 },
2441 { 0x06, 0xb2fb },
2442 { 0x06, 0xfffe },
2443 { 0x06, 0xfd04 },
2444 { 0x06, 0xf8e0 },
2445 { 0x06, 0xf848 },
2446 { 0x06, 0xe1f8 },
2447 { 0x06, 0x4968 },
2448 { 0x06, 0x08e4 },
2449 { 0x06, 0xf848 },
2450 { 0x06, 0xe5f8 },
2451 { 0x06, 0x4958 },
2452 { 0x06, 0xf7e4 },
2453 { 0x06, 0xf848 },
2454 { 0x06, 0xe5f8 },
2455 { 0x06, 0x49fc },
2456 { 0x06, 0x044d },
2457 { 0x06, 0x2000 },
2458 { 0x06, 0x024e },
2459 { 0x06, 0x2200 },
2460 { 0x06, 0x024d },
2461 { 0x06, 0xdfff },
2462 { 0x06, 0x014e },
2463 { 0x06, 0xddff },
2464 { 0x06, 0x0100 },
2465 { 0x05, 0x83d8 },
2466 { 0x06, 0x8000 },
2467 { 0x03, 0xdc00 },
2468 { 0x05, 0xfff6 },
2469 { 0x06, 0x00fc },
2470 { 0x1f, 0x0000 },
2471
2472 { 0x1f, 0x0000 },
2473 { 0x0d, 0xf880 },
2474 { 0x1f, 0x0000 }
5b538df9
FR		 2475 };
2476
2477 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2478
daf9df6d 2479 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2480 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2481 { 0x1f, 0x0002 },
2482 { 0x05, 0x669a },
5b538df9 2483 { 0x1f, 0x0005 },
daf9df6d 2484 { 0x05, 0x8330 },
2485 { 0x06, 0x669a },
2486
2487 { 0x1f, 0x0002 }
2488 };
2489 int val;
2490
2491 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2492
2493 val = mdio_read(ioaddr, 0x0d);
2494 if ((val & 0x00ff) != 0x006c) {
2495 u32 set[] = {
2496 0x0065, 0x0066, 0x0067, 0x0068,
2497 0x0069, 0x006a, 0x006b, 0x006c
2498 };
2499 int i;
2500
2501 mdio_write(ioaddr, 0x1f, 0x0002);
2502
2503 val &= 0xff00;
2504 for (i = 0; i < ARRAY_SIZE(set); i++)
2505 mdio_write(ioaddr, 0x0d, val | set[i]);
2506 }
2507 } else {
350f7596 2508 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2509 { 0x1f, 0x0002 },
2510 { 0x05, 0x2642 },
5b538df9 2511 { 0x1f, 0x0005 },
daf9df6d 2512 { 0x05, 0x8330 },
2513 { 0x06, 0x2642 }
5b538df9
FR		 2514 };
2515
daf9df6d 2516 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2517 }
2518
daf9df6d 2519 mdio_write(ioaddr, 0x1f, 0x0002);
2520 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2521 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2522
2523 mdio_write(ioaddr, 0x1f, 0x0001);
2524 mdio_write(ioaddr, 0x17, 0x0cc0);
2525
2526 mdio_write(ioaddr, 0x1f, 0x0002);
2527 mdio_patch(ioaddr, 0x0f, 0x0017);
2528
2529 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2530}
2531
2532static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
2533{
350f7596 2534 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2535 { 0x1f, 0x0002 },
2536 { 0x10, 0x0008 },
2537 { 0x0d, 0x006c },
2538
2539 { 0x1f, 0x0000 },
2540 { 0x0d, 0xf880 },
2541
2542 { 0x1f, 0x0001 },
2543 { 0x17, 0x0cc0 },
2544
2545 { 0x1f, 0x0001 },
2546 { 0x0b, 0xa4d8 },
2547 { 0x09, 0x281c },
2548 { 0x07, 0x2883 },
2549 { 0x0a, 0x6b35 },
2550 { 0x1d, 0x3da4 },
2551 { 0x1c, 0xeffd },
2552 { 0x14, 0x7f52 },
2553 { 0x18, 0x7fc6 },
2554 { 0x08, 0x0601 },
2555 { 0x06, 0x4063 },
2556 { 0x10, 0xf074 },
2557 { 0x1f, 0x0003 },
2558 { 0x13, 0x0789 },
2559 { 0x12, 0xf4bd },
2560 { 0x1a, 0x04fd },
2561 { 0x14, 0x84b0 },
2562 { 0x1f, 0x0000 },
2563 { 0x00, 0x9200 },
2564
2565 { 0x1f, 0x0005 },
2566 { 0x01, 0x0340 },
2567 { 0x1f, 0x0001 },
2568 { 0x04, 0x4000 },
2569 { 0x03, 0x1d21 },
2570 { 0x02, 0x0c32 },
2571 { 0x01, 0x0200 },
2572 { 0x00, 0x5554 },
2573 { 0x04, 0x4800 },
2574 { 0x04, 0x4000 },
2575 { 0x04, 0xf000 },
2576 { 0x03, 0xdf01 },
2577 { 0x02, 0xdf20 },
2578 { 0x01, 0x101a },
2579 { 0x00, 0xa0ff },
2580 { 0x04, 0xf800 },
2581 { 0x04, 0xf000 },
2582 { 0x1f, 0x0000 },
2583
2584 { 0x1f, 0x0007 },
2585 { 0x1e, 0x0023 },
2586 { 0x16, 0x0000 },
2587 { 0x1f, 0x0000 }
2588 };
2589
2590 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2591}
2592
2857ffb7
FR		 2593static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
2594{
350f7596 2595 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2596 { 0x1f, 0x0003 },
2597 { 0x08, 0x441d },
2598 { 0x01, 0x9100 },
2599 { 0x1f, 0x0000 }
2600 };
2601
2602 mdio_write(ioaddr, 0x1f, 0x0000);
2603 mdio_patch(ioaddr, 0x11, 1 << 12);
2604 mdio_patch(ioaddr, 0x19, 1 << 13);
85910a8e 2605 mdio_patch(ioaddr, 0x10, 1 << 15);
2857ffb7
FR		 2606
2607 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2608}
2609
5615d9f1
FR		 2610static void rtl_hw_phy_config(struct net_device *dev)
2611{
2612 struct rtl8169_private *tp = netdev_priv(dev);
2613 void __iomem *ioaddr = tp->mmio_addr;
2614
2615 rtl8169_print_mac_version(tp);
2616
2617 switch (tp->mac_version) {
2618 case RTL_GIGA_MAC_VER_01:
2619 break;
2620 case RTL_GIGA_MAC_VER_02:
2621 case RTL_GIGA_MAC_VER_03:
2622 rtl8169s_hw_phy_config(ioaddr);
2623 break;
2624 case RTL_GIGA_MAC_VER_04:
2625 rtl8169sb_hw_phy_config(ioaddr);
2626 break;
2e955856 2627 case RTL_GIGA_MAC_VER_05:
2628 rtl8169scd_hw_phy_config(tp, ioaddr);
2629 break;
8c7006aa 2630 case RTL_GIGA_MAC_VER_06:
2631 rtl8169sce_hw_phy_config(ioaddr);
2632 break;
2857ffb7
FR		 2633 case RTL_GIGA_MAC_VER_07:
2634 case RTL_GIGA_MAC_VER_08:
2635 case RTL_GIGA_MAC_VER_09:
2636 rtl8102e_hw_phy_config(ioaddr);
2637 break;
236b8082
FR		 2638 case RTL_GIGA_MAC_VER_11:
2639 rtl8168bb_hw_phy_config(ioaddr);
2640 break;
2641 case RTL_GIGA_MAC_VER_12:
2642 rtl8168bef_hw_phy_config(ioaddr);
2643 break;
2644 case RTL_GIGA_MAC_VER_17:
2645 rtl8168bef_hw_phy_config(ioaddr);
2646 break;
867763c1 2647 case RTL_GIGA_MAC_VER_18:
ef3386f0 2648 rtl8168cp_1_hw_phy_config(ioaddr);
867763c1
FR		 2649 break;
2650 case RTL_GIGA_MAC_VER_19:
219a1e9d 2651 rtl8168c_1_hw_phy_config(ioaddr);
867763c1 2652 break;
7da97ec9 2653 case RTL_GIGA_MAC_VER_20:
219a1e9d 2654 rtl8168c_2_hw_phy_config(ioaddr);
7da97ec9 2655 break;
197ff761
FR		 2656 case RTL_GIGA_MAC_VER_21:
2657 rtl8168c_3_hw_phy_config(ioaddr);
2658 break;
6fb07058
FR		 2659 case RTL_GIGA_MAC_VER_22:
2660 rtl8168c_4_hw_phy_config(ioaddr);
2661 break;
ef3386f0 2662 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2663 case RTL_GIGA_MAC_VER_24:
ef3386f0
FR		 2664 rtl8168cp_2_hw_phy_config(ioaddr);
2665 break;
5b538df9 2666 case RTL_GIGA_MAC_VER_25:
daf9df6d 2667 rtl8168d_1_hw_phy_config(ioaddr);
2668 break;
2669 case RTL_GIGA_MAC_VER_26:
2670 rtl8168d_2_hw_phy_config(ioaddr);
2671 break;
2672 case RTL_GIGA_MAC_VER_27:
2673 rtl8168d_3_hw_phy_config(ioaddr);
5b538df9 2674 break;
ef3386f0 2675
5615d9f1
FR		 2676 default:
2677 break;
2678 }
2679}
2680
1da177e4
LT		 2681static void rtl8169_phy_timer(unsigned long __opaque)
2682{
2683 struct net_device *dev = (struct net_device *)__opaque;
2684 struct rtl8169_private *tp = netdev_priv(dev);
2685 struct timer_list *timer = &tp->timer;
2686 void __iomem *ioaddr = tp->mmio_addr;
2687 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2688
bcf0bf90 2689 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 2690
64e4bfb4 2691 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 2692 return;
2693
2694 spin_lock_irq(&tp->lock);
2695
2696 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 2697 /*
1da177e4
LT		 2698 * A busy loop could burn quite a few cycles on nowadays CPU.
2699 * Let's delay the execution of the timer for a few ticks.
2700 */
2701 timeout = HZ/10;
2702 goto out_mod_timer;
2703 }
2704
2705 if (tp->link_ok(ioaddr))
2706 goto out_unlock;
2707
bf82c189 2708 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4
LT		 2709
2710 tp->phy_reset_enable(ioaddr);
2711
2712out_mod_timer:
2713 mod_timer(timer, jiffies + timeout);
2714out_unlock:
2715 spin_unlock_irq(&tp->lock);
2716}
2717
2718static inline void rtl8169_delete_timer(struct net_device *dev)
2719{
2720 struct rtl8169_private *tp = netdev_priv(dev);
2721 struct timer_list *timer = &tp->timer;
2722
e179bb7b 2723 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2724 return;
2725
2726 del_timer_sync(timer);
2727}
2728
2729static inline void rtl8169_request_timer(struct net_device *dev)
2730{
2731 struct rtl8169_private *tp = netdev_priv(dev);
2732 struct timer_list *timer = &tp->timer;
2733
e179bb7b 2734 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2735 return;
2736
2efa53f3 2737 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 2738}
2739
2740#ifdef CONFIG_NET_POLL_CONTROLLER
2741/*
2742 * Polling 'interrupt' - used by things like netconsole to send skbs
2743 * without having to re-enable interrupts. It's not called while
2744 * the interrupt routine is executing.
2745 */
2746static void rtl8169_netpoll(struct net_device *dev)
2747{
2748 struct rtl8169_private *tp = netdev_priv(dev);
2749 struct pci_dev *pdev = tp->pci_dev;
2750
2751 disable_irq(pdev->irq);
7d12e780 2752 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 2753 enable_irq(pdev->irq);
2754}
2755#endif
2756
2757static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2758 void __iomem *ioaddr)
2759{
2760 iounmap(ioaddr);
2761 pci_release_regions(pdev);
87aeec76 2762 pci_clear_mwi(pdev);
1da177e4
LT		 2763 pci_disable_device(pdev);
2764 free_netdev(dev);
2765}
2766
bf793295
FR		 2767static void rtl8169_phy_reset(struct net_device *dev,
2768 struct rtl8169_private *tp)
2769{
2770 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 2771 unsigned int i;
bf793295
FR		 2772
2773 tp->phy_reset_enable(ioaddr);
2774 for (i = 0; i < 100; i++) {
2775 if (!tp->phy_reset_pending(ioaddr))
2776 return;
2777 msleep(1);
2778 }
bf82c189 2779 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 2780}
2781
4ff96fa6
FR		 2782static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2783{
2784 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 2785
5615d9f1 2786 rtl_hw_phy_config(dev);
4ff96fa6 2787
77332894
MS		 2788 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2789 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2790 RTL_W8(0x82, 0x01);
2791 }
4ff96fa6 2792
6dccd16b
FR		 2793 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2794
2795 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2796 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 2797
bcf0bf90 2798 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 2799 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2800 RTL_W8(0x82, 0x01);
2801 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2802 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
2803 }
2804
bf793295
FR		 2805 rtl8169_phy_reset(dev, tp);
2806
901dda2b
FR		 2807 /*
2808 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2809 * only 8101. Don't panic.
2810 */
2811 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6 2812
bf82c189
JP		 2813 if (RTL_R8(PHYstatus) & TBI_Enable)
2814 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 2815}
2816
773d2021
FR		 2817static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2818{
2819 void __iomem *ioaddr = tp->mmio_addr;
2820 u32 high;
2821 u32 low;
2822
2823 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2824 high = addr[4] | (addr[5] << 8);
2825
2826 spin_lock_irq(&tp->lock);
2827
2828 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 2829
773d2021 2830 RTL_W32(MAC4, high);
908ba2bf 2831 RTL_R32(MAC4);
2832
78f1cd02 2833 RTL_W32(MAC0, low);
908ba2bf 2834 RTL_R32(MAC0);
2835
773d2021
FR		 2836 RTL_W8(Cfg9346, Cfg9346_Lock);
2837
2838 spin_unlock_irq(&tp->lock);
2839}
2840
2841static int rtl_set_mac_address(struct net_device *dev, void *p)
2842{
2843 struct rtl8169_private *tp = netdev_priv(dev);
2844 struct sockaddr *addr = p;
2845
2846 if (!is_valid_ether_addr(addr->sa_data))
2847 return -EADDRNOTAVAIL;
2848
2849 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2850
2851 rtl_rar_set(tp, dev->dev_addr);
2852
2853 return 0;
2854}
2855
5f787a1a
FR		 2856static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2857{
2858 struct rtl8169_private *tp = netdev_priv(dev);
2859 struct mii_ioctl_data *data = if_mii(ifr);
2860
8b4ab28d
FR		 2861 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2862}
5f787a1a 2863
8b4ab28d
FR		 2864static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2865{
5f787a1a
FR		 2866 switch (cmd) {
2867 case SIOCGMIIPHY:
2868 data->phy_id = 32; /* Internal PHY */
2869 return 0;
2870
2871 case SIOCGMIIREG:
2872 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
2873 return 0;
2874
2875 case SIOCSMIIREG:
5f787a1a
FR		 2876 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
2877 return 0;
2878 }
2879 return -EOPNOTSUPP;
2880}
2881
8b4ab28d
FR		 2882static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2883{
2884 return -EOPNOTSUPP;
2885}
2886
0e485150
FR		 2887static const struct rtl_cfg_info {
2888 void (*hw_start)(struct net_device *);
2889 unsigned int region;
2890 unsigned int align;
2891 u16 intr_event;
2892 u16 napi_event;
ccdffb9a 2893 unsigned features;
f21b75e9 2894 u8 default_ver;
0e485150
FR		 2895} rtl_cfg_infos [] = {
2896 [RTL_CFG_0] = {
2897 .hw_start = rtl_hw_start_8169,
2898 .region = 1,
e9f63f30 2899 .align = 0,
0e485150
FR		 2900 .intr_event = SYSErr | LinkChg | RxOverflow |
2901 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2902 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2903 .features = RTL_FEATURE_GMII,
2904 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 2905 },
2906 [RTL_CFG_1] = {
2907 .hw_start = rtl_hw_start_8168,
2908 .region = 2,
2909 .align = 8,
2910 .intr_event = SYSErr | LinkChg | RxOverflow |
2911 TxErr | TxOK | RxOK | RxErr,
fbac58fc 2912 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2913 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2914 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 2915 },
2916 [RTL_CFG_2] = {
2917 .hw_start = rtl_hw_start_8101,
2918 .region = 2,
2919 .align = 8,
2920 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2921 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2922 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2923 .features = RTL_FEATURE_MSI,
2924 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 2925 }
2926};
2927
fbac58fc
FR		 2928/* Cfg9346_Unlock assumed. */
2929static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2930 const struct rtl_cfg_info *cfg)
2931{
2932 unsigned msi = 0;
2933 u8 cfg2;
2934
2935 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 2936 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 2937 if (pci_enable_msi(pdev)) {
2938 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2939 } else {
2940 cfg2 |= MSIEnable;
2941 msi = RTL_FEATURE_MSI;
2942 }
2943 }
2944 RTL_W8(Config2, cfg2);
2945 return msi;
2946}
2947
2948static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2949{
2950 if (tp->features & RTL_FEATURE_MSI) {
2951 pci_disable_msi(pdev);
2952 tp->features &= ~RTL_FEATURE_MSI;
2953 }
2954}
2955
8b4ab28d
FR		 2956static const struct net_device_ops rtl8169_netdev_ops = {
2957 .ndo_open = rtl8169_open,
2958 .ndo_stop = rtl8169_close,
2959 .ndo_get_stats = rtl8169_get_stats,
00829823 2960 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 2961 .ndo_tx_timeout = rtl8169_tx_timeout,
2962 .ndo_validate_addr = eth_validate_addr,
2963 .ndo_change_mtu = rtl8169_change_mtu,
2964 .ndo_set_mac_address = rtl_set_mac_address,
2965 .ndo_do_ioctl = rtl8169_ioctl,
2966 .ndo_set_multicast_list = rtl_set_rx_mode,
2967#ifdef CONFIG_R8169_VLAN
2968 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2969#endif
2970#ifdef CONFIG_NET_POLL_CONTROLLER
2971 .ndo_poll_controller = rtl8169_netpoll,
2972#endif
2973
2974};
2975
1da177e4 2976static int __devinit
4ff96fa6 2977rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 2978{
0e485150
FR		 2979 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2980 const unsigned int region = cfg->region;
1da177e4 2981 struct rtl8169_private *tp;
ccdffb9a 2982 struct mii_if_info *mii;
4ff96fa6
FR		 2983 struct net_device *dev;
2984 void __iomem *ioaddr;
07d3f51f
FR		 2985 unsigned int i;
2986 int rc;
1da177e4 2987
4ff96fa6
FR		 2988 if (netif_msg_drv(&debug)) {
2989 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2990 MODULENAME, RTL8169_VERSION);
2991 }
1da177e4 2992
1da177e4 2993 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 2994 if (!dev) {
b57b7e5a 2995 if (netif_msg_drv(&debug))
9b91cf9d 2996 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 2997 rc = -ENOMEM;
2998 goto out;
1da177e4
LT		 2999 }
3000
1da177e4 3001 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 3002 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 3003 tp = netdev_priv(dev);
c4028958 3004 tp->dev = dev;
21e197f2 3005 tp->pci_dev = pdev;
b57b7e5a 3006 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 3007
ccdffb9a
FR		 3008 mii = &tp->mii;
3009 mii->dev = dev;
3010 mii->mdio_read = rtl_mdio_read;
3011 mii->mdio_write = rtl_mdio_write;
3012 mii->phy_id_mask = 0x1f;
3013 mii->reg_num_mask = 0x1f;
3014 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3015
1da177e4
LT		 3016 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3017 rc = pci_enable_device(pdev);
b57b7e5a 3018 if (rc < 0) {
bf82c189 3019 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 3020 goto err_out_free_dev_1;
1da177e4
LT		 3021 }
3022
87aeec76 3023 if (pci_set_mwi(pdev) < 0)
3024 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 3025
1da177e4 3026 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3027 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3028 netif_err(tp, probe, dev,
3029 "region #%d not an MMIO resource, aborting\n",
3030 region);
1da177e4 3031 rc = -ENODEV;
87aeec76 3032 goto err_out_mwi_2;
1da177e4 3033 }
4ff96fa6 3034
1da177e4 3035 /* check for weird/broken PCI region reporting */
bcf0bf90 3036 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 3037 netif_err(tp, probe, dev,
3038 "Invalid PCI region size(s), aborting\n");
1da177e4 3039 rc = -ENODEV;
87aeec76 3040 goto err_out_mwi_2;
1da177e4
LT		 3041 }
3042
3043 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3044 if (rc < 0) {
bf82c189 3045 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 3046 goto err_out_mwi_2;
1da177e4
LT		 3047 }
3048
3049 tp->cp_cmd = PCIMulRW | RxChkSum;
3050
3051 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 3052 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 3053 tp->cp_cmd |= PCIDAC;
3054 dev->features |= NETIF_F_HIGHDMA;
3055 } else {
284901a9 3056 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3057 if (rc < 0) {
bf82c189 3058 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 3059 goto err_out_free_res_3;
1da177e4
LT		 3060 }
3061 }
3062
1da177e4 3063 /* ioremap MMIO region */
bcf0bf90 3064 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3065 if (!ioaddr) {
bf82c189 3066 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 3067 rc = -EIO;
87aeec76 3068 goto err_out_free_res_3;
1da177e4
LT		 3069 }
3070
4300e8c7
DM		 3071 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3072 if (!tp->pcie_cap)
3073 netif_info(tp, probe, dev, "no PCI Express capability\n");
3074
d78ad8cb 3075 RTL_W16(IntrMask, 0x0000);
1da177e4
LT		 3076
3077 /* Soft reset the chip. */
3078 RTL_W8(ChipCmd, CmdReset);
3079
3080 /* Check that the chip has finished the reset. */
07d3f51f 3081 for (i = 0; i < 100; i++) {
1da177e4
LT		 3082 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3083 break;
b518fa8e 3084 msleep_interruptible(1);
1da177e4
LT		 3085 }
3086
d78ad8cb
KW		 3087 RTL_W16(IntrStatus, 0xffff);
3088
ca52efd5 3089 pci_set_master(pdev);
3090
1da177e4
LT		 3091 /* Identify chip attached to board */
3092 rtl8169_get_mac_version(tp, ioaddr);
1da177e4 3093
f21b75e9
JD		 3094 /* Use appropriate default if unknown */
3095 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
bf82c189
JP		 3096 netif_notice(tp, probe, dev,
3097 "unknown MAC, using family default\n");
f21b75e9
JD		 3098 tp->mac_version = cfg->default_ver;
3099 }
3100
1da177e4 3101 rtl8169_print_mac_version(tp);
1da177e4 3102
cee60c37 3103 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 3104 if (tp->mac_version == rtl_chip_info[i].mac_version)
3105 break;
3106 }
cee60c37 3107 if (i == ARRAY_SIZE(rtl_chip_info)) {
f21b75e9
JD		 3108 dev_err(&pdev->dev,
3109 "driver bug, MAC version not found in rtl_chip_info\n");
87aeec76 3110 goto err_out_msi_4;
1da177e4
LT		 3111 }
3112 tp->chipset = i;
3113
5d06a99f
FR		 3114 RTL_W8(Cfg9346, Cfg9346_Unlock);
3115 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3116 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3117 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3118 tp->features |= RTL_FEATURE_WOL;
3119 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3120 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3121 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3122 RTL_W8(Cfg9346, Cfg9346_Lock);
3123
66ec5d4f
FR		 3124 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3125 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3126 tp->set_speed = rtl8169_set_speed_tbi;
3127 tp->get_settings = rtl8169_gset_tbi;
3128 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3129 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3130 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3131 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4 3132
64e4bfb4 3133 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 3134 } else {
3135 tp->set_speed = rtl8169_set_speed_xmii;
3136 tp->get_settings = rtl8169_gset_xmii;
3137 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3138 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3139 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3140 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3141 }
3142
df58ef51
FR		 3143 spin_lock_init(&tp->lock);
3144
738e1e69
PV		 3145 tp->mmio_addr = ioaddr;
3146
7bf6bf48 3147 /* Get MAC address */
1da177e4
LT		 3148 for (i = 0; i < MAC_ADDR_LEN; i++)
3149 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3150 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3151
1da177e4 3152 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3153 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3154 dev->irq = pdev->irq;
3155 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3156
bea3348e 3157 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 3158
3159#ifdef CONFIG_R8169_VLAN
3160 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 3161#endif
3162
3163 tp->intr_mask = 0xffff;
0e485150
FR		 3164 tp->align = cfg->align;
3165 tp->hw_start = cfg->hw_start;
3166 tp->intr_event = cfg->intr_event;
3167 tp->napi_event = cfg->napi_event;
1da177e4 3168
2efa53f3
FR		 3169 init_timer(&tp->timer);
3170 tp->timer.data = (unsigned long) dev;
3171 tp->timer.function = rtl8169_phy_timer;
3172
1da177e4 3173 rc = register_netdev(dev);
4ff96fa6 3174 if (rc < 0)
87aeec76 3175 goto err_out_msi_4;
1da177e4
LT		 3176
3177 pci_set_drvdata(pdev, dev);
3178
bf82c189
JP		 3179 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3180 rtl_chip_info[tp->chipset].name,
3181 dev->base_addr, dev->dev_addr,
3182 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3183
4ff96fa6 3184 rtl8169_init_phy(dev, tp);
05af2142
SW		 3185
3186 /*
3187 * Pretend we are using VLANs; This bypasses a nasty bug where
3188 * Interrupts stop flowing on high load on 8110SCd controllers.
3189 */
3190 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3191 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3192
8b76ab39 3193 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3194
4ff96fa6
FR		 3195out:
3196 return rc;
1da177e4 3197
87aeec76 3198err_out_msi_4:
fbac58fc 3199 rtl_disable_msi(pdev, tp);
4ff96fa6 3200 iounmap(ioaddr);
87aeec76 3201err_out_free_res_3:
4ff96fa6 3202 pci_release_regions(pdev);
87aeec76 3203err_out_mwi_2:
4ff96fa6 3204 pci_clear_mwi(pdev);
4ff96fa6
FR		 3205 pci_disable_device(pdev);
3206err_out_free_dev_1:
3207 free_netdev(dev);
3208 goto out;
1da177e4
LT		 3209}
3210
07d3f51f 3211static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3212{
3213 struct net_device *dev = pci_get_drvdata(pdev);
3214 struct rtl8169_private *tp = netdev_priv(dev);
3215
eb2a021c
FR		 3216 flush_scheduled_work();
3217
1da177e4 3218 unregister_netdev(dev);
cc098dc7
IV		 3219
3220 /* restore original MAC address */
3221 rtl_rar_set(tp, dev->perm_addr);
3222
fbac58fc 3223 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3224 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3225 pci_set_drvdata(pdev, NULL);
3226}
3227
1da177e4 3228static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
c0cd884a 3229 unsigned int mtu)
1da177e4 3230{
c0cd884a
NH		 3231 unsigned int max_frame = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3232
3233 if (max_frame != 16383)
93f4d91d
NH		 3234 printk(KERN_WARNING PFX "WARNING! Changing of MTU on this "
3235 "NIC may lead to frame reception errors!\n");
1da177e4 3236
8812304c 3237 tp->rx_buf_sz = (max_frame > RX_BUF_SIZE) ? max_frame : RX_BUF_SIZE;
1da177e4
LT		 3238}
3239
3240static int rtl8169_open(struct net_device *dev)
3241{
3242 struct rtl8169_private *tp = netdev_priv(dev);
3243 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3244 int retval = -ENOMEM;
1da177e4 3245
1da177e4 3246
c0cd884a
NH		 3247 /*
3248 * Note that we use a magic value here, its wierd I know
3249 * its done because, some subset of rtl8169 hardware suffers from
3250 * a problem in which frames received that are longer than
3251 * the size set in RxMaxSize register return garbage sizes
3252 * when received. To avoid this we need to turn off filtering,
3253 * which is done by setting a value of 16383 in the RxMaxSize register
3254 * and allocating 16k frames to handle the largest possible rx value
3255 * thats what the magic math below does.
3256 */
3257 rtl8169_set_rxbufsize(tp, 16383 - VLAN_ETH_HLEN - ETH_FCS_LEN);
1da177e4
LT		 3258
3259 /*
3260 * Rx and Tx desscriptors needs 256 bytes alignment.
3261 * pci_alloc_consistent provides more.
3262 */
3263 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
3264 &tp->TxPhyAddr);
3265 if (!tp->TxDescArray)
99f252b0 3266 goto out;
1da177e4
LT		 3267
3268 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
3269 &tp->RxPhyAddr);
3270 if (!tp->RxDescArray)
99f252b0 3271 goto err_free_tx_0;
1da177e4
LT		 3272
3273 retval = rtl8169_init_ring(dev);
3274 if (retval < 0)
99f252b0 3275 goto err_free_rx_1;
1da177e4 3276
c4028958 3277 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3278
99f252b0
FR		 3279 smp_mb();
3280
fbac58fc
FR		 3281 retval = request_irq(dev->irq, rtl8169_interrupt,
3282 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3283 dev->name, dev);
3284 if (retval < 0)
3285 goto err_release_ring_2;
3286
bea3348e 3287 napi_enable(&tp->napi);
bea3348e 3288
07ce4064 3289 rtl_hw_start(dev);
1da177e4
LT		 3290
3291 rtl8169_request_timer(dev);
3292
3293 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3294out:
3295 return retval;
3296
99f252b0
FR		 3297err_release_ring_2:
3298 rtl8169_rx_clear(tp);
3299err_free_rx_1:
1da177e4
LT		 3300 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3301 tp->RxPhyAddr);
99f252b0 3302err_free_tx_0:
1da177e4
LT		 3303 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3304 tp->TxPhyAddr);
1da177e4
LT		 3305 goto out;
3306}
3307
3308static void rtl8169_hw_reset(void __iomem *ioaddr)
3309{
3310 /* Disable interrupts */
3311 rtl8169_irq_mask_and_ack(ioaddr);
3312
3313 /* Reset the chipset */
3314 RTL_W8(ChipCmd, CmdReset);
3315
3316 /* PCI commit */
3317 RTL_R8(ChipCmd);
3318}
3319
7f796d83 3320static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3321{
3322 void __iomem *ioaddr = tp->mmio_addr;
3323 u32 cfg = rtl8169_rx_config;
3324
3325 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3326 RTL_W32(RxConfig, cfg);
3327
3328 /* Set DMA burst size and Interframe Gap Time */
3329 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3330 (InterFrameGap << TxInterFrameGapShift));
3331}
3332
07ce4064 3333static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3334{
3335 struct rtl8169_private *tp = netdev_priv(dev);
3336 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 3337 unsigned int i;
1da177e4
LT		 3338
3339 /* Soft reset the chip. */
3340 RTL_W8(ChipCmd, CmdReset);
3341
3342 /* Check that the chip has finished the reset. */
07d3f51f 3343 for (i = 0; i < 100; i++) {
1da177e4
LT		 3344 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3345 break;
b518fa8e 3346 msleep_interruptible(1);
1da177e4
LT		 3347 }
3348
07ce4064
FR		 3349 tp->hw_start(dev);
3350
07ce4064
FR		 3351 netif_start_queue(dev);
3352}
3353
3354
7f796d83
FR		 3355static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3356 void __iomem *ioaddr)
3357{
3358 /*
3359 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3360 * register to be written before TxDescAddrLow to work.
3361 * Switching from MMIO to I/O access fixes the issue as well.
3362 */
3363 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 3364 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 3365 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 3366 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 3367}
3368
3369static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3370{
3371 u16 cmd;
3372
3373 cmd = RTL_R16(CPlusCmd);
3374 RTL_W16(CPlusCmd, cmd);
3375 return cmd;
3376}
3377
fdd7b4c3 3378static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 3379{
3380 /* Low hurts. Let's disable the filtering. */
207d6e87 3381 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 3382}
3383
6dccd16b
FR		 3384static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3385{
350f7596 3386 static const struct {
6dccd16b
FR		 3387 u32 mac_version;
3388 u32 clk;
3389 u32 val;
3390 } cfg2_info [] = {
3391 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3392 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3393 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3394 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3395 }, *p = cfg2_info;
3396 unsigned int i;
3397 u32 clk;
3398
3399 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 3400 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 3401 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3402 RTL_W32(0x7c, p->val);
3403 break;
3404 }
3405 }
3406}
3407
07ce4064
FR		 3408static void rtl_hw_start_8169(struct net_device *dev)
3409{
3410 struct rtl8169_private *tp = netdev_priv(dev);
3411 void __iomem *ioaddr = tp->mmio_addr;
3412 struct pci_dev *pdev = tp->pci_dev;
07ce4064 3413
9cb427b6
FR		 3414 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3415 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3416 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3417 }
3418
1da177e4 3419 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 3420 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3421 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3422 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3423 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3424 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3425
1da177e4
LT		 3426 RTL_W8(EarlyTxThres, EarlyTxThld);
3427
fdd7b4c3 3428 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
1da177e4 3429
c946b304
FR		 3430 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3431 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3432 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3433 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3434 rtl_set_rx_tx_config_registers(tp);
1da177e4 3435
7f796d83 3436 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 3437
bcf0bf90
FR		 3438 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3439 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 3440 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 3441 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 3442 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 3443 }
3444
bcf0bf90
FR		 3445 RTL_W16(CPlusCmd, tp->cp_cmd);
3446
6dccd16b
FR		 3447 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3448
1da177e4
LT		 3449 /*
3450 * Undocumented corner. Supposedly:
3451 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3452 */
3453 RTL_W16(IntrMitigate, 0x0000);
3454
7f796d83 3455 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 3456
c946b304
FR		 3457 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3458 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3459 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3460 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3461 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3462 rtl_set_rx_tx_config_registers(tp);
3463 }
3464
1da177e4 3465 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 3466
3467 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3468 RTL_R8(IntrMask);
1da177e4
LT		 3469
3470 RTL_W32(RxMissed, 0);
3471
07ce4064 3472 rtl_set_rx_mode(dev);
1da177e4
LT		 3473
3474 /* no early-rx interrupts */
3475 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 3476
3477 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 3478 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3479}
1da177e4 3480
9c14ceaf 3481static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 3482{
9c14ceaf
FR		 3483 struct net_device *dev = pci_get_drvdata(pdev);
3484 struct rtl8169_private *tp = netdev_priv(dev);
3485 int cap = tp->pcie_cap;
3486
3487 if (cap) {
3488 u16 ctl;
458a9f61 3489
9c14ceaf
FR		 3490 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3491 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3492 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3493 }
458a9f61
FR		 3494}
3495
dacf8154
FR		 3496static void rtl_csi_access_enable(void __iomem *ioaddr)
3497{
3498 u32 csi;
3499
3500 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3501 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
3502}
3503
3504struct ephy_info {
3505 unsigned int offset;
3506 u16 mask;
3507 u16 bits;
3508};
3509
350f7596 3510static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 3511{
3512 u16 w;
3513
3514 while (len-- > 0) {
3515 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3516 rtl_ephy_write(ioaddr, e->offset, w);
3517 e++;
3518 }
3519}
3520
b726e493
FR		 3521static void rtl_disable_clock_request(struct pci_dev *pdev)
3522{
3523 struct net_device *dev = pci_get_drvdata(pdev);
3524 struct rtl8169_private *tp = netdev_priv(dev);
3525 int cap = tp->pcie_cap;
3526
3527 if (cap) {
3528 u16 ctl;
3529
3530 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3531 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3532 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3533 }
3534}
3535
3536#define R8168_CPCMD_QUIRK_MASK (\
3537 EnableBist | \
3538 Mac_dbgo_oe | \
3539 Force_half_dup | \
3540 Force_rxflow_en | \
3541 Force_txflow_en | \
3542 Cxpl_dbg_sel | \
3543 ASF | \
3544 PktCntrDisable | \
3545 Mac_dbgo_sel)
3546
219a1e9d
FR		 3547static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3548{
b726e493
FR		 3549 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3550
3551 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3552
2e68ae44
FR		 3553 rtl_tx_performance_tweak(pdev,
3554 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 3555}
3556
3557static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3558{
3559 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493
FR		 3560
3561 RTL_W8(EarlyTxThres, EarlyTxThld);
3562
3563 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 3564}
3565
3566static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3567{
b726e493
FR		 3568 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3569
3570 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3571
219a1e9d 3572 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 3573
3574 rtl_disable_clock_request(pdev);
3575
3576 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 3577}
3578
ef3386f0 3579static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 3580{
350f7596 3581 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 3582 { 0x01, 0, 0x0001 },
3583 { 0x02, 0x0800, 0x1000 },
3584 { 0x03, 0, 0x0042 },
3585 { 0x06, 0x0080, 0x0000 },
3586 { 0x07, 0, 0x2000 }
3587 };
3588
3589 rtl_csi_access_enable(ioaddr);
3590
3591 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3592
219a1e9d
FR		 3593 __rtl_hw_start_8168cp(ioaddr, pdev);
3594}
3595
ef3386f0
FR		 3596static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3597{
3598 rtl_csi_access_enable(ioaddr);
3599
3600 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3601
3602 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3603
3604 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3605}
3606
7f3e3d3a
FR		 3607static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3608{
3609 rtl_csi_access_enable(ioaddr);
3610
3611 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3612
3613 /* Magic. */
3614 RTL_W8(DBG_REG, 0x20);
3615
3616 RTL_W8(EarlyTxThres, EarlyTxThld);
3617
3618 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3619
3620 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3621}
3622
219a1e9d
FR		 3623static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3624{
350f7596 3625 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 3626 { 0x02, 0x0800, 0x1000 },
3627 { 0x03, 0, 0x0002 },
3628 { 0x06, 0x0080, 0x0000 }
3629 };
3630
3631 rtl_csi_access_enable(ioaddr);
3632
3633 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3634
3635 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3636
219a1e9d
FR		 3637 __rtl_hw_start_8168cp(ioaddr, pdev);
3638}
3639
3640static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3641{
350f7596 3642 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 3643 { 0x01, 0, 0x0001 },
3644 { 0x03, 0x0400, 0x0220 }
3645 };
3646
3647 rtl_csi_access_enable(ioaddr);
3648
3649 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3650
219a1e9d
FR		 3651 __rtl_hw_start_8168cp(ioaddr, pdev);
3652}
3653
197ff761
FR		 3654static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3655{
3656 rtl_hw_start_8168c_2(ioaddr, pdev);
3657}
3658
6fb07058
FR		 3659static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3660{
3661 rtl_csi_access_enable(ioaddr);
3662
3663 __rtl_hw_start_8168cp(ioaddr, pdev);
3664}
3665
5b538df9
FR		 3666static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3667{
3668 rtl_csi_access_enable(ioaddr);
3669
3670 rtl_disable_clock_request(pdev);
3671
3672 RTL_W8(EarlyTxThres, EarlyTxThld);
3673
3674 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3675
3676 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3677}
3678
07ce4064
FR		 3679static void rtl_hw_start_8168(struct net_device *dev)
3680{
2dd99530
FR		 3681 struct rtl8169_private *tp = netdev_priv(dev);
3682 void __iomem *ioaddr = tp->mmio_addr;
0e485150 3683 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 3684
3685 RTL_W8(Cfg9346, Cfg9346_Unlock);
3686
3687 RTL_W8(EarlyTxThres, EarlyTxThld);
3688
fdd7b4c3 3689 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
2dd99530 3690
0e485150 3691 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 3692
3693 RTL_W16(CPlusCmd, tp->cp_cmd);
3694
0e485150 3695 RTL_W16(IntrMitigate, 0x5151);
2dd99530 3696
0e485150
FR		 3697 /* Work around for RxFIFO overflow. */
3698 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3699 tp->intr_event |= RxFIFOOver | PCSTimeout;
3700 tp->intr_event &= ~RxOverflow;
3701 }
3702
3703 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 3704
b8363901
FR		 3705 rtl_set_rx_mode(dev);
3706
3707 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3708 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 3709
3710 RTL_R8(IntrMask);
3711
219a1e9d
FR		 3712 switch (tp->mac_version) {
3713 case RTL_GIGA_MAC_VER_11:
3714 rtl_hw_start_8168bb(ioaddr, pdev);
3715 break;
3716
3717 case RTL_GIGA_MAC_VER_12:
3718 case RTL_GIGA_MAC_VER_17:
3719 rtl_hw_start_8168bef(ioaddr, pdev);
3720 break;
3721
3722 case RTL_GIGA_MAC_VER_18:
ef3386f0 3723 rtl_hw_start_8168cp_1(ioaddr, pdev);
219a1e9d
FR		 3724 break;
3725
3726 case RTL_GIGA_MAC_VER_19:
3727 rtl_hw_start_8168c_1(ioaddr, pdev);
3728 break;
3729
3730 case RTL_GIGA_MAC_VER_20:
3731 rtl_hw_start_8168c_2(ioaddr, pdev);
3732 break;
3733
197ff761
FR		 3734 case RTL_GIGA_MAC_VER_21:
3735 rtl_hw_start_8168c_3(ioaddr, pdev);
3736 break;
3737
6fb07058
FR		 3738 case RTL_GIGA_MAC_VER_22:
3739 rtl_hw_start_8168c_4(ioaddr, pdev);
3740 break;
3741
ef3386f0
FR		 3742 case RTL_GIGA_MAC_VER_23:
3743 rtl_hw_start_8168cp_2(ioaddr, pdev);
3744 break;
3745
7f3e3d3a
FR		 3746 case RTL_GIGA_MAC_VER_24:
3747 rtl_hw_start_8168cp_3(ioaddr, pdev);
3748 break;
3749
5b538df9 3750 case RTL_GIGA_MAC_VER_25:
daf9df6d 3751 case RTL_GIGA_MAC_VER_26:
3752 case RTL_GIGA_MAC_VER_27:
5b538df9
FR		 3753 rtl_hw_start_8168d(ioaddr, pdev);
3754 break;
3755
219a1e9d
FR		 3756 default:
3757 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3758 dev->name, tp->mac_version);
3759 break;
3760 }
2dd99530 3761
0e485150
FR		 3762 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3763
b8363901
FR		 3764 RTL_W8(Cfg9346, Cfg9346_Lock);
3765
2dd99530 3766 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 3767
0e485150 3768 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3769}
1da177e4 3770
2857ffb7
FR		 3771#define R810X_CPCMD_QUIRK_MASK (\
3772 EnableBist | \
3773 Mac_dbgo_oe | \
3774 Force_half_dup | \
5edcc537 3775 Force_rxflow_en | \
2857ffb7
FR		 3776 Force_txflow_en | \
3777 Cxpl_dbg_sel | \
3778 ASF | \
3779 PktCntrDisable | \
3780 PCIDAC | \
3781 PCIMulRW)
3782
3783static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3784{
350f7596 3785 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 3786 { 0x01, 0, 0x6e65 },
3787 { 0x02, 0, 0x091f },
3788 { 0x03, 0, 0xc2f9 },
3789 { 0x06, 0, 0xafb5 },
3790 { 0x07, 0, 0x0e00 },
3791 { 0x19, 0, 0xec80 },
3792 { 0x01, 0, 0x2e65 },
3793 { 0x01, 0, 0x6e65 }
3794 };
3795 u8 cfg1;
3796
3797 rtl_csi_access_enable(ioaddr);
3798
3799 RTL_W8(DBG_REG, FIX_NAK_1);
3800
3801 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3802
3803 RTL_W8(Config1,
3804 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3805 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3806
3807 cfg1 = RTL_R8(Config1);
3808 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3809 RTL_W8(Config1, cfg1 & ~LEDS0);
3810
3811 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3812
3813 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3814}
3815
3816static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3817{
3818 rtl_csi_access_enable(ioaddr);
3819
3820 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3821
3822 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3823 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3824
3825 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3826}
3827
3828static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3829{
3830 rtl_hw_start_8102e_2(ioaddr, pdev);
3831
3832 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3833}
3834
07ce4064
FR		 3835static void rtl_hw_start_8101(struct net_device *dev)
3836{
cdf1a608
FR		 3837 struct rtl8169_private *tp = netdev_priv(dev);
3838 void __iomem *ioaddr = tp->mmio_addr;
3839 struct pci_dev *pdev = tp->pci_dev;
3840
e3cf0cc0
FR		 3841 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3842 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 3843 int cap = tp->pcie_cap;
3844
3845 if (cap) {
3846 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3847 PCI_EXP_DEVCTL_NOSNOOP_EN);
3848 }
cdf1a608
FR		 3849 }
3850
2857ffb7
FR		 3851 switch (tp->mac_version) {
3852 case RTL_GIGA_MAC_VER_07:
3853 rtl_hw_start_8102e_1(ioaddr, pdev);
3854 break;
3855
3856 case RTL_GIGA_MAC_VER_08:
3857 rtl_hw_start_8102e_3(ioaddr, pdev);
3858 break;
3859
3860 case RTL_GIGA_MAC_VER_09:
3861 rtl_hw_start_8102e_2(ioaddr, pdev);
3862 break;
cdf1a608
FR		 3863 }
3864
3865 RTL_W8(Cfg9346, Cfg9346_Unlock);
3866
3867 RTL_W8(EarlyTxThres, EarlyTxThld);
3868
fdd7b4c3 3869 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
cdf1a608
FR		 3870
3871 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3872
3873 RTL_W16(CPlusCmd, tp->cp_cmd);
3874
3875 RTL_W16(IntrMitigate, 0x0000);
3876
3877 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3878
3879 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3880 rtl_set_rx_tx_config_registers(tp);
3881
3882 RTL_W8(Cfg9346, Cfg9346_Lock);
3883
3884 RTL_R8(IntrMask);
3885
cdf1a608
FR		 3886 rtl_set_rx_mode(dev);
3887
0e485150
FR		 3888 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3889
cdf1a608 3890 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 3891
0e485150 3892 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3893}
3894
3895static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3896{
3897 struct rtl8169_private *tp = netdev_priv(dev);
3898 int ret = 0;
3899
3900 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3901 return -EINVAL;
3902
3903 dev->mtu = new_mtu;
3904
3905 if (!netif_running(dev))
3906 goto out;
3907
3908 rtl8169_down(dev);
3909
c0cd884a 3910 rtl8169_set_rxbufsize(tp, dev->mtu);
1da177e4
LT		 3911
3912 ret = rtl8169_init_ring(dev);
3913 if (ret < 0)
3914 goto out;
3915
bea3348e 3916 napi_enable(&tp->napi);
1da177e4 3917
07ce4064 3918 rtl_hw_start(dev);
1da177e4
LT		 3919
3920 rtl8169_request_timer(dev);
3921
3922out:
3923 return ret;
3924}
3925
3926static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3927{
95e0918d 3928 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 3929 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3930}
3931
3932static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
3933 struct sk_buff **sk_buff, struct RxDesc *desc)
3934{
3935 struct pci_dev *pdev = tp->pci_dev;
3936
3937 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
3938 PCI_DMA_FROMDEVICE);
3939 dev_kfree_skb(*sk_buff);
3940 *sk_buff = NULL;
3941 rtl8169_make_unusable_by_asic(desc);
3942}
3943
3944static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3945{
3946 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3947
3948 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3949}
3950
3951static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3952 u32 rx_buf_sz)
3953{
3954 desc->addr = cpu_to_le64(mapping);
3955 wmb();
3956 rtl8169_mark_to_asic(desc, rx_buf_sz);
3957}
3958
15d31758
SH		 3959static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
3960 struct net_device *dev,
3961 struct RxDesc *desc, int rx_buf_sz,
3962 unsigned int align)
1da177e4
LT		 3963{
3964 struct sk_buff *skb;
3965 dma_addr_t mapping;
e9f63f30 3966 unsigned int pad;
1da177e4 3967
e9f63f30
FR		 3968 pad = align ? align : NET_IP_ALIGN;
3969
3970 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 3971 if (!skb)
3972 goto err_out;
3973
e9f63f30 3974 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 3975
689be439 3976 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 3977 PCI_DMA_FROMDEVICE);
3978
3979 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 3980out:
15d31758 3981 return skb;
1da177e4
LT		 3982
3983err_out:
1da177e4
LT		 3984 rtl8169_make_unusable_by_asic(desc);
3985 goto out;
3986}
3987
3988static void rtl8169_rx_clear(struct rtl8169_private *tp)
3989{
07d3f51f 3990 unsigned int i;
1da177e4
LT		 3991
3992 for (i = 0; i < NUM_RX_DESC; i++) {
3993 if (tp->Rx_skbuff[i]) {
3994 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
3995 tp->RxDescArray + i);
3996 }
3997 }
3998}
3999
4000static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
4001 u32 start, u32 end)
4002{
4003 u32 cur;
5b0384f4 4004
4ae47c2d 4005 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 4006 struct sk_buff *skb;
4007 unsigned int i = cur % NUM_RX_DESC;
1da177e4 4008
4ae47c2d
FR		 4009 WARN_ON((s32)(end - cur) < 0);
4010
1da177e4
LT		 4011 if (tp->Rx_skbuff[i])
4012 continue;
bcf0bf90 4013
15d31758
SH		 4014 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
4015 tp->RxDescArray + i,
4016 tp->rx_buf_sz, tp->align);
4017 if (!skb)
1da177e4 4018 break;
15d31758
SH		 4019
4020 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 4021 }
4022 return cur - start;
4023}
4024
4025static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4026{
4027 desc->opts1 |= cpu_to_le32(RingEnd);
4028}
4029
4030static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4031{
4032 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4033}
4034
4035static int rtl8169_init_ring(struct net_device *dev)
4036{
4037 struct rtl8169_private *tp = netdev_priv(dev);
4038
4039 rtl8169_init_ring_indexes(tp);
4040
4041 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4042 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
4043
4044 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
4045 goto err_out;
4046
4047 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4048
4049 return 0;
4050
4051err_out:
4052 rtl8169_rx_clear(tp);
4053 return -ENOMEM;
4054}
4055
4056static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
4057 struct TxDesc *desc)
4058{
4059 unsigned int len = tx_skb->len;
4060
4061 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
4062 desc->opts1 = 0x00;
4063 desc->opts2 = 0x00;
4064 desc->addr = 0x00;
4065 tx_skb->len = 0;
4066}
4067
4068static void rtl8169_tx_clear(struct rtl8169_private *tp)
4069{
4070 unsigned int i;
4071
4072 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
4073 unsigned int entry = i % NUM_TX_DESC;
4074 struct ring_info *tx_skb = tp->tx_skb + entry;
4075 unsigned int len = tx_skb->len;
4076
4077 if (len) {
4078 struct sk_buff *skb = tx_skb->skb;
4079
4080 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
4081 tp->TxDescArray + entry);
4082 if (skb) {
4083 dev_kfree_skb(skb);
4084 tx_skb->skb = NULL;
4085 }
cebf8cc7 4086 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4087 }
4088 }
4089 tp->cur_tx = tp->dirty_tx = 0;
4090}
4091
c4028958 4092static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4093{
4094 struct rtl8169_private *tp = netdev_priv(dev);
4095
c4028958 4096 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4097 schedule_delayed_work(&tp->task, 4);
4098}
4099
4100static void rtl8169_wait_for_quiescence(struct net_device *dev)
4101{
4102 struct rtl8169_private *tp = netdev_priv(dev);
4103 void __iomem *ioaddr = tp->mmio_addr;
4104
4105 synchronize_irq(dev->irq);
4106
4107 /* Wait for any pending NAPI task to complete */
bea3348e 4108 napi_disable(&tp->napi);
1da177e4
LT		 4109
4110 rtl8169_irq_mask_and_ack(ioaddr);
4111
d1d08d12
DM		 4112 tp->intr_mask = 0xffff;
4113 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4114 napi_enable(&tp->napi);
1da177e4
LT		 4115}
4116
c4028958 4117static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4118{
c4028958
DH		 4119 struct rtl8169_private *tp =
4120 container_of(work, struct rtl8169_private, task.work);
4121 struct net_device *dev = tp->dev;
1da177e4
LT		 4122 int ret;
4123
eb2a021c
FR		 4124 rtnl_lock();
4125
4126 if (!netif_running(dev))
4127 goto out_unlock;
4128
4129 rtl8169_wait_for_quiescence(dev);
4130 rtl8169_close(dev);
1da177e4
LT		 4131
4132 ret = rtl8169_open(dev);
4133 if (unlikely(ret < 0)) {
bf82c189
JP		 4134 if (net_ratelimit())
4135 netif_err(tp, drv, dev,
4136 "reinit failure (status = %d). Rescheduling\n",
4137 ret);
1da177e4
LT		 4138 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4139 }
eb2a021c
FR		 4140
4141out_unlock:
4142 rtnl_unlock();
1da177e4
LT		 4143}
4144
c4028958 4145static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4146{
c4028958
DH		 4147 struct rtl8169_private *tp =
4148 container_of(work, struct rtl8169_private, task.work);
4149 struct net_device *dev = tp->dev;
1da177e4 4150
eb2a021c
FR		 4151 rtnl_lock();
4152
1da177e4 4153 if (!netif_running(dev))
eb2a021c 4154 goto out_unlock;
1da177e4
LT		 4155
4156 rtl8169_wait_for_quiescence(dev);
4157
bea3348e 4158 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 4159 rtl8169_tx_clear(tp);
4160
4161 if (tp->dirty_rx == tp->cur_rx) {
4162 rtl8169_init_ring_indexes(tp);
07ce4064 4163 rtl_hw_start(dev);
1da177e4 4164 netif_wake_queue(dev);
cebf8cc7 4165 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 4166 } else {
bf82c189
JP		 4167 if (net_ratelimit())
4168 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
1da177e4
LT		 4169 rtl8169_schedule_work(dev, rtl8169_reset_task);
4170 }
eb2a021c
FR		 4171
4172out_unlock:
4173 rtnl_unlock();
1da177e4
LT		 4174}
4175
4176static void rtl8169_tx_timeout(struct net_device *dev)
4177{
4178 struct rtl8169_private *tp = netdev_priv(dev);
4179
4180 rtl8169_hw_reset(tp->mmio_addr);
4181
4182 /* Let's wait a bit while any (async) irq lands on */
4183 rtl8169_schedule_work(dev, rtl8169_reset_task);
4184}
4185
4186static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4187 u32 opts1)
4188{
4189 struct skb_shared_info *info = skb_shinfo(skb);
4190 unsigned int cur_frag, entry;
a6343afb 4191 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 4192
4193 entry = tp->cur_tx;
4194 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4195 skb_frag_t *frag = info->frags + cur_frag;
4196 dma_addr_t mapping;
4197 u32 status, len;
4198 void *addr;
4199
4200 entry = (entry + 1) % NUM_TX_DESC;
4201
4202 txd = tp->TxDescArray + entry;
4203 len = frag->size;
4204 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4205 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
4206
4207 /* anti gcc 2.95.3 bugware (sic) */
4208 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4209
4210 txd->opts1 = cpu_to_le32(status);
4211 txd->addr = cpu_to_le64(mapping);
4212
4213 tp->tx_skb[entry].len = len;
4214 }
4215
4216 if (cur_frag) {
4217 tp->tx_skb[entry].skb = skb;
4218 txd->opts1 |= cpu_to_le32(LastFrag);
4219 }
4220
4221 return cur_frag;
4222}
4223
4224static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4225{
4226 if (dev->features & NETIF_F_TSO) {
7967168c 4227 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 4228
4229 if (mss)
4230 return LargeSend | ((mss & MSSMask) << MSSShift);
4231 }
84fa7933 4232 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 4233 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 4234
4235 if (ip->protocol == IPPROTO_TCP)
4236 return IPCS | TCPCS;
4237 else if (ip->protocol == IPPROTO_UDP)
4238 return IPCS | UDPCS;
4239 WARN_ON(1); /* we need a WARN() */
4240 }
4241 return 0;
4242}
4243
61357325
SH		 4244static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4245 struct net_device *dev)
1da177e4
LT		 4246{
4247 struct rtl8169_private *tp = netdev_priv(dev);
4248 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
4249 struct TxDesc *txd = tp->TxDescArray + entry;
4250 void __iomem *ioaddr = tp->mmio_addr;
4251 dma_addr_t mapping;
4252 u32 status, len;
4253 u32 opts1;
5b0384f4 4254
1da177e4 4255 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 4256 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
1da177e4
LT		 4257 goto err_stop;
4258 }
4259
4260 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4261 goto err_stop;
4262
4263 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4264
4265 frags = rtl8169_xmit_frags(tp, skb, opts1);
4266 if (frags) {
4267 len = skb_headlen(skb);
4268 opts1 |= FirstFrag;
4269 } else {
4270 len = skb->len;
1da177e4
LT		 4271 opts1 |= FirstFrag | LastFrag;
4272 tp->tx_skb[entry].skb = skb;
4273 }
4274
4275 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
4276
4277 tp->tx_skb[entry].len = len;
4278 txd->addr = cpu_to_le64(mapping);
4279 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4280
4281 wmb();
4282
4283 /* anti gcc 2.95.3 bugware (sic) */
4284 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4285 txd->opts1 = cpu_to_le32(status);
4286
1da177e4
LT		 4287 tp->cur_tx += frags + 1;
4288
4c020a96 4289 wmb();
1da177e4 4290
275391a4 4291 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 4292
4293 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4294 netif_stop_queue(dev);
4295 smp_rmb();
4296 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4297 netif_wake_queue(dev);
4298 }
4299
61357325 4300 return NETDEV_TX_OK;
1da177e4
LT		 4301
4302err_stop:
4303 netif_stop_queue(dev);
cebf8cc7 4304 dev->stats.tx_dropped++;
61357325 4305 return NETDEV_TX_BUSY;
1da177e4
LT		 4306}
4307
4308static void rtl8169_pcierr_interrupt(struct net_device *dev)
4309{
4310 struct rtl8169_private *tp = netdev_priv(dev);
4311 struct pci_dev *pdev = tp->pci_dev;
4312 void __iomem *ioaddr = tp->mmio_addr;
4313 u16 pci_status, pci_cmd;
4314
4315 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4316 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4317
bf82c189
JP		 4318 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4319 pci_cmd, pci_status);
1da177e4
LT		 4320
4321 /*
4322 * The recovery sequence below admits a very elaborated explanation:
4323 * - it seems to work;
d03902b8
FR		 4324 * - I did not see what else could be done;
4325 * - it makes iop3xx happy.
1da177e4
LT		 4326 *
4327 * Feel free to adjust to your needs.
4328 */
a27993f3 4329 if (pdev->broken_parity_status)
d03902b8
FR		 4330 pci_cmd &= ~PCI_COMMAND_PARITY;
4331 else
4332 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4333
4334 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 4335
4336 pci_write_config_word(pdev, PCI_STATUS,
4337 pci_status & (PCI_STATUS_DETECTED_PARITY |
4338 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4339 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4340
4341 /* The infamous DAC f*ckup only happens at boot time */
4342 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
bf82c189 4343 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 4344 tp->cp_cmd &= ~PCIDAC;
4345 RTL_W16(CPlusCmd, tp->cp_cmd);
4346 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 4347 }
4348
4349 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 4350
4351 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 4352}
4353
07d3f51f
FR		 4354static void rtl8169_tx_interrupt(struct net_device *dev,
4355 struct rtl8169_private *tp,
4356 void __iomem *ioaddr)
1da177e4
LT		 4357{
4358 unsigned int dirty_tx, tx_left;
4359
1da177e4
LT		 4360 dirty_tx = tp->dirty_tx;
4361 smp_rmb();
4362 tx_left = tp->cur_tx - dirty_tx;
4363
4364 while (tx_left > 0) {
4365 unsigned int entry = dirty_tx % NUM_TX_DESC;
4366 struct ring_info *tx_skb = tp->tx_skb + entry;
4367 u32 len = tx_skb->len;
4368 u32 status;
4369
4370 rmb();
4371 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4372 if (status & DescOwn)
4373 break;
4374
cebf8cc7
FR		 4375 dev->stats.tx_bytes += len;
4376 dev->stats.tx_packets++;
1da177e4
LT		 4377
4378 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
4379
4380 if (status & LastFrag) {
87433bfc 4381 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 4382 tx_skb->skb = NULL;
4383 }
4384 dirty_tx++;
4385 tx_left--;
4386 }
4387
4388 if (tp->dirty_tx != dirty_tx) {
4389 tp->dirty_tx = dirty_tx;
4390 smp_wmb();
4391 if (netif_queue_stopped(dev) &&
4392 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4393 netif_wake_queue(dev);
4394 }
d78ae2dc
FR		 4395 /*
4396 * 8168 hack: TxPoll requests are lost when the Tx packets are
4397 * too close. Let's kick an extra TxPoll request when a burst
4398 * of start_xmit activity is detected (if it is not detected,
4399 * it is slow enough). -- FR
4400 */
4401 smp_rmb();
4402 if (tp->cur_tx != dirty_tx)
4403 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4404 }
4405}
4406
126fa4b9
FR		 4407static inline int rtl8169_fragmented_frame(u32 status)
4408{
4409 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4410}
4411
1da177e4
LT		 4412static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
4413{
4414 u32 opts1 = le32_to_cpu(desc->opts1);
4415 u32 status = opts1 & RxProtoMask;
4416
4417 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4418 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
4419 ((status == RxProtoIP) && !(opts1 & IPFail)))
4420 skb->ip_summed = CHECKSUM_UNNECESSARY;
4421 else
4422 skb->ip_summed = CHECKSUM_NONE;
4423}
4424
07d3f51f
FR		 4425static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
4426 struct rtl8169_private *tp, int pkt_size,
4427 dma_addr_t addr)
1da177e4 4428{
b449655f
SH		 4429 struct sk_buff *skb;
4430 bool done = false;
1da177e4 4431
b449655f
SH		 4432 if (pkt_size >= rx_copybreak)
4433 goto out;
1da177e4 4434
89d71a66 4435 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
b449655f
SH		 4436 if (!skb)
4437 goto out;
4438
07d3f51f
FR		 4439 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
4440 PCI_DMA_FROMDEVICE);
b449655f
SH		 4441 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
4442 *sk_buff = skb;
4443 done = true;
4444out:
4445 return done;
1da177e4
LT		 4446}
4447
6c3b9d34
ED		 4448/*
4449 * Warning : rtl8169_rx_interrupt() might be called :
4450 * 1) from NAPI (softirq) context
4451 * (polling = 1 : we should call netif_receive_skb())
4452 * 2) from process context (rtl8169_reset_task())
4453 * (polling = 0 : we must call netif_rx() instead)
4454 */
07d3f51f
FR		 4455static int rtl8169_rx_interrupt(struct net_device *dev,
4456 struct rtl8169_private *tp,
bea3348e 4457 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 4458{
4459 unsigned int cur_rx, rx_left;
4460 unsigned int delta, count;
6c3b9d34 4461 int polling = (budget != ~(u32)0) ? 1 : 0;
1da177e4 4462
1da177e4
LT		 4463 cur_rx = tp->cur_rx;
4464 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 4465 rx_left = min(rx_left, budget);
1da177e4 4466
4dcb7d33 4467 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 4468 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 4469 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 4470 u32 status;
4471
4472 rmb();
126fa4b9 4473 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 4474
4475 if (status & DescOwn)
4476 break;
4dcb7d33 4477 if (unlikely(status & RxRES)) {
bf82c189
JP		 4478 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4479 status);
cebf8cc7 4480 dev->stats.rx_errors++;
1da177e4 4481 if (status & (RxRWT | RxRUNT))
cebf8cc7 4482 dev->stats.rx_length_errors++;
1da177e4 4483 if (status & RxCRC)
cebf8cc7 4484 dev->stats.rx_crc_errors++;
9dccf611
FR		 4485 if (status & RxFOVF) {
4486 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 4487 dev->stats.rx_fifo_errors++;
9dccf611 4488 }
126fa4b9 4489 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 4490 } else {
1da177e4 4491 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 4492 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 4493 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 4494 struct pci_dev *pdev = tp->pci_dev;
1da177e4 4495
126fa4b9
FR		 4496 /*
4497 * The driver does not support incoming fragmented
4498 * frames. They are seen as a symptom of over-mtu
4499 * sized frames.
4500 */
4501 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 4502 dev->stats.rx_dropped++;
4503 dev->stats.rx_length_errors++;
126fa4b9 4504 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 4505 continue;
126fa4b9
FR		 4506 }
4507
1da177e4 4508 rtl8169_rx_csum(skb, desc);
bcf0bf90 4509
07d3f51f 4510 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 4511 pci_dma_sync_single_for_device(pdev, addr,
4512 pkt_size, PCI_DMA_FROMDEVICE);
4513 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4514 } else {
a866bbf6 4515 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
b449655f 4516 PCI_DMA_FROMDEVICE);
1da177e4
LT		 4517 tp->Rx_skbuff[entry] = NULL;
4518 }
4519
1da177e4
LT		 4520 skb_put(skb, pkt_size);
4521 skb->protocol = eth_type_trans(skb, dev);
4522
6c3b9d34
ED		 4523 if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4524 if (likely(polling))
4525 netif_receive_skb(skb);
4526 else
4527 netif_rx(skb);
4528 }
1da177e4 4529
cebf8cc7
FR		 4530 dev->stats.rx_bytes += pkt_size;
4531 dev->stats.rx_packets++;
1da177e4 4532 }
6dccd16b
FR		 4533
4534 /* Work around for AMD plateform. */
95e0918d 4535 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 4536 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4537 desc->opts2 = 0;
4538 cur_rx++;
4539 }
1da177e4
LT		 4540 }
4541
4542 count = cur_rx - tp->cur_rx;
4543 tp->cur_rx = cur_rx;
4544
4545 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
bf82c189
JP		 4546 if (!delta && count)
4547 netif_info(tp, intr, dev, "no Rx buffer allocated\n");
1da177e4
LT		 4548 tp->dirty_rx += delta;
4549
4550 /*
4551 * FIXME: until there is periodic timer to try and refill the ring,
4552 * a temporary shortage may definitely kill the Rx process.
4553 * - disable the asic to try and avoid an overflow and kick it again
4554 * after refill ?
4555 * - how do others driver handle this condition (Uh oh...).
4556 */
bf82c189
JP		 4557 if (tp->dirty_rx + NUM_RX_DESC == tp->cur_rx)
4558 netif_emerg(tp, intr, dev, "Rx buffers exhausted\n");
1da177e4
LT		 4559
4560 return count;
4561}
4562
07d3f51f 4563static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 4564{
07d3f51f 4565 struct net_device *dev = dev_instance;
1da177e4 4566 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4567 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 4568 int handled = 0;
865c652d 4569 int status;
1da177e4 4570
f11a377b
DD		 4571 /* loop handling interrupts until we have no new ones or
4572 * we hit a invalid/hotplug case.
4573 */
865c652d 4574 status = RTL_R16(IntrStatus);
f11a377b
DD		 4575 while (status && status != 0xffff) {
4576 handled = 1;
1da177e4 4577
f11a377b
DD		 4578 /* Handle all of the error cases first. These will reset
4579 * the chip, so just exit the loop.
4580 */
4581 if (unlikely(!netif_running(dev))) {
4582 rtl8169_asic_down(ioaddr);
4583 break;
4584 }
1da177e4 4585
f11a377b
DD		 4586 /* Work around for rx fifo overflow */
4587 if (unlikely(status & RxFIFOOver) &&
4588 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4589 netif_stop_queue(dev);
4590 rtl8169_tx_timeout(dev);
4591 break;
4592 }
1da177e4 4593
f11a377b
DD		 4594 if (unlikely(status & SYSErr)) {
4595 rtl8169_pcierr_interrupt(dev);
4596 break;
4597 }
1da177e4 4598
f11a377b
DD		 4599 if (status & LinkChg)
4600 rtl8169_check_link_status(dev, tp, ioaddr);
0e485150 4601
f11a377b
DD		 4602 /* We need to see the lastest version of tp->intr_mask to
4603 * avoid ignoring an MSI interrupt and having to wait for
4604 * another event which may never come.
4605 */
4606 smp_rmb();
4607 if (status & tp->intr_mask & tp->napi_event) {
4608 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4609 tp->intr_mask = ~tp->napi_event;
4610
4611 if (likely(napi_schedule_prep(&tp->napi)))
4612 __napi_schedule(&tp->napi);
bf82c189
JP		 4613 else
4614 netif_info(tp, intr, dev,
4615 "interrupt %04x in poll\n", status);
f11a377b 4616 }
1da177e4 4617
f11a377b
DD		 4618 /* We only get a new MSI interrupt when all active irq
4619 * sources on the chip have been acknowledged. So, ack
4620 * everything we've seen and check if new sources have become
4621 * active to avoid blocking all interrupts from the chip.
4622 */
4623 RTL_W16(IntrStatus,
4624 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4625 status = RTL_R16(IntrStatus);
865c652d 4626 }
1da177e4 4627
1da177e4
LT		 4628 return IRQ_RETVAL(handled);
4629}
4630
bea3348e 4631static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 4632{
bea3348e
SH		 4633 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4634 struct net_device *dev = tp->dev;
1da177e4 4635 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 4636 int work_done;
1da177e4 4637
bea3348e 4638 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 4639 rtl8169_tx_interrupt(dev, tp, ioaddr);
4640
bea3348e 4641 if (work_done < budget) {
288379f0 4642 napi_complete(napi);
f11a377b
DD		 4643
4644 /* We need for force the visibility of tp->intr_mask
4645 * for other CPUs, as we can loose an MSI interrupt
4646 * and potentially wait for a retransmit timeout if we don't.
4647 * The posted write to IntrMask is safe, as it will
4648 * eventually make it to the chip and we won't loose anything
4649 * until it does.
1da177e4 4650 */
f11a377b 4651 tp->intr_mask = 0xffff;
4c020a96 4652 wmb();
0e485150 4653 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4654 }
4655
bea3348e 4656 return work_done;
1da177e4 4657}
1da177e4 4658
523a6094
FR		 4659static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4660{
4661 struct rtl8169_private *tp = netdev_priv(dev);
4662
4663 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4664 return;
4665
4666 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4667 RTL_W32(RxMissed, 0);
4668}
4669
1da177e4
LT		 4670static void rtl8169_down(struct net_device *dev)
4671{
4672 struct rtl8169_private *tp = netdev_priv(dev);
4673 void __iomem *ioaddr = tp->mmio_addr;
733b736c 4674 unsigned int intrmask;
1da177e4
LT		 4675
4676 rtl8169_delete_timer(dev);
4677
4678 netif_stop_queue(dev);
4679
93dd79e8 4680 napi_disable(&tp->napi);
93dd79e8 4681
1da177e4
LT		 4682core_down:
4683 spin_lock_irq(&tp->lock);
4684
4685 rtl8169_asic_down(ioaddr);
4686
523a6094 4687 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4688
4689 spin_unlock_irq(&tp->lock);
4690
4691 synchronize_irq(dev->irq);
4692
1da177e4 4693 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 4694 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 4695
4696 /*
4697 * And now for the 50k$ question: are IRQ disabled or not ?
4698 *
4699 * Two paths lead here:
4700 * 1) dev->close
4701 * -> netif_running() is available to sync the current code and the
4702 * IRQ handler. See rtl8169_interrupt for details.
4703 * 2) dev->change_mtu
4704 * -> rtl8169_poll can not be issued again and re-enable the
4705 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 4706 *
4707 * No loop if hotpluged or major error (0xffff).
1da177e4 4708 */
733b736c
AP		 4709 intrmask = RTL_R16(IntrMask);
4710 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 4711 goto core_down;
4712
4713 rtl8169_tx_clear(tp);
4714
4715 rtl8169_rx_clear(tp);
4716}
4717
4718static int rtl8169_close(struct net_device *dev)
4719{
4720 struct rtl8169_private *tp = netdev_priv(dev);
4721 struct pci_dev *pdev = tp->pci_dev;
4722
355423d0
IV		 4723 /* update counters before going down */
4724 rtl8169_update_counters(dev);
4725
1da177e4
LT		 4726 rtl8169_down(dev);
4727
4728 free_irq(dev->irq, dev);
4729
1da177e4
LT		 4730 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
4731 tp->RxPhyAddr);
4732 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
4733 tp->TxPhyAddr);
4734 tp->TxDescArray = NULL;
4735 tp->RxDescArray = NULL;
4736
4737 return 0;
4738}
4739
07ce4064 4740static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 4741{
4742 struct rtl8169_private *tp = netdev_priv(dev);
4743 void __iomem *ioaddr = tp->mmio_addr;
4744 unsigned long flags;
4745 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 4746 int rx_mode;
1da177e4
LT		 4747 u32 tmp = 0;
4748
4749 if (dev->flags & IFF_PROMISC) {
4750 /* Unconditionally log net taps. */
bf82c189 4751 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 4752 rx_mode =
4753 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4754 AcceptAllPhys;
4755 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 4756 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 4757 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 4758 /* Too many to filter perfectly -- accept all multicasts. */
4759 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4760 mc_filter[1] = mc_filter[0] = 0xffffffff;
4761 } else {
4762 struct dev_mc_list *mclist;
07d3f51f 4763
1da177e4
LT		 4764 rx_mode = AcceptBroadcast | AcceptMyPhys;
4765 mc_filter[1] = mc_filter[0] = 0;
f9dcbcc9 4766 netdev_for_each_mc_addr(mclist, dev) {
1da177e4
LT		 4767 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
4768 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4769 rx_mode |= AcceptMulticast;
4770 }
4771 }
4772
4773 spin_lock_irqsave(&tp->lock, flags);
4774
4775 tmp = rtl8169_rx_config | rx_mode |
4776 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4777
f887cce8 4778 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 4779 u32 data = mc_filter[0];
4780
4781 mc_filter[0] = swab32(mc_filter[1]);
4782 mc_filter[1] = swab32(data);
bcf0bf90
FR		 4783 }
4784
1da177e4 4785 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 4786 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 4787
57a9f236
FR		 4788 RTL_W32(RxConfig, tmp);
4789
1da177e4
LT		 4790 spin_unlock_irqrestore(&tp->lock, flags);
4791}
4792
4793/**
4794 * rtl8169_get_stats - Get rtl8169 read/write statistics
4795 * @dev: The Ethernet Device to get statistics for
4796 *
4797 * Get TX/RX statistics for rtl8169
4798 */
4799static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4800{
4801 struct rtl8169_private *tp = netdev_priv(dev);
4802 void __iomem *ioaddr = tp->mmio_addr;
4803 unsigned long flags;
4804
4805 if (netif_running(dev)) {
4806 spin_lock_irqsave(&tp->lock, flags);
523a6094 4807 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4808 spin_unlock_irqrestore(&tp->lock, flags);
4809 }
5b0384f4 4810
cebf8cc7 4811 return &dev->stats;
1da177e4
LT		 4812}
4813
861ab440 4814static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 4815{
5d06a99f 4816 if (!netif_running(dev))
861ab440 4817 return;
5d06a99f
FR		 4818
4819 netif_device_detach(dev);
4820 netif_stop_queue(dev);
861ab440
RW		 4821}
4822
4823#ifdef CONFIG_PM
4824
4825static int rtl8169_suspend(struct device *device)
4826{
4827 struct pci_dev *pdev = to_pci_dev(device);
4828 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 4829
861ab440 4830 rtl8169_net_suspend(dev);
1371fa6d 4831
5d06a99f
FR		 4832 return 0;
4833}
4834
861ab440 4835static int rtl8169_resume(struct device *device)
5d06a99f 4836{
861ab440 4837 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f
FR		 4838 struct net_device *dev = pci_get_drvdata(pdev);
4839
4840 if (!netif_running(dev))
4841 goto out;
4842
4843 netif_device_attach(dev);
4844
5d06a99f
FR		 4845 rtl8169_schedule_work(dev, rtl8169_reset_task);
4846out:
4847 return 0;
4848}
4849
47145210 4850static const struct dev_pm_ops rtl8169_pm_ops = {
861ab440
RW		 4851 .suspend = rtl8169_suspend,
4852 .resume = rtl8169_resume,
4853 .freeze = rtl8169_suspend,
4854 .thaw = rtl8169_resume,
4855 .poweroff = rtl8169_suspend,
4856 .restore = rtl8169_resume,
4857};
4858
4859#define RTL8169_PM_OPS (&rtl8169_pm_ops)
4860
4861#else /* !CONFIG_PM */
4862
4863#define RTL8169_PM_OPS NULL
4864
4865#endif /* !CONFIG_PM */
4866
1765f95d
FR		 4867static void rtl_shutdown(struct pci_dev *pdev)
4868{
861ab440 4869 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 4870 struct rtl8169_private *tp = netdev_priv(dev);
4871 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 4872
4873 rtl8169_net_suspend(dev);
1765f95d 4874
cc098dc7
IV		 4875 /* restore original MAC address */
4876 rtl_rar_set(tp, dev->perm_addr);
4877
4bb3f522 4878 spin_lock_irq(&tp->lock);
4879
4880 rtl8169_asic_down(ioaddr);
4881
4882 spin_unlock_irq(&tp->lock);
4883
861ab440 4884 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 4885 /* WoL fails with some 8168 when the receiver is disabled. */
4886 if (tp->features & RTL_FEATURE_WOL) {
4887 pci_clear_master(pdev);
4888
4889 RTL_W8(ChipCmd, CmdRxEnb);
4890 /* PCI commit */
4891 RTL_R8(ChipCmd);
4892 }
4893
861ab440
RW		 4894 pci_wake_from_d3(pdev, true);
4895 pci_set_power_state(pdev, PCI_D3hot);
4896 }
4897}
5d06a99f 4898
1da177e4
LT		 4899static struct pci_driver rtl8169_pci_driver = {
4900 .name = MODULENAME,
4901 .id_table = rtl8169_pci_tbl,
4902 .probe = rtl8169_init_one,
4903 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 4904 .shutdown = rtl_shutdown,
861ab440 4905 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 4906};
4907
07d3f51f 4908static int __init rtl8169_init_module(void)
1da177e4 4909{
29917620 4910 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 4911}
4912
07d3f51f 4913static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 4914{
4915 pci_unregister_driver(&rtl8169_pci_driver);
4916}
4917
4918module_init(rtl8169_init_module);
4919module_exit(rtl8169_cleanup_module);
kernel source for telekom puls (alcatel/mediatek)