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qlge: Get rid of split addresses in hardware control blocks.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / qlge / qlge_main.c
CommitLineData
c4e84bde
RM		 1/*
2 * QLogic qlge NIC HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 * See LICENSE.qlge for copyright and licensing details.
5 * Author: Linux qlge network device driver by
6 * Ron Mercer <ron.mercer@qlogic.com>
7 */
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/types.h>
11#include <linux/module.h>
12#include <linux/list.h>
13#include <linux/pci.h>
14#include <linux/dma-mapping.h>
15#include <linux/pagemap.h>
16#include <linux/sched.h>
17#include <linux/slab.h>
18#include <linux/dmapool.h>
19#include <linux/mempool.h>
20#include <linux/spinlock.h>
21#include <linux/kthread.h>
22#include <linux/interrupt.h>
23#include <linux/errno.h>
24#include <linux/ioport.h>
25#include <linux/in.h>
26#include <linux/ip.h>
27#include <linux/ipv6.h>
28#include <net/ipv6.h>
29#include <linux/tcp.h>
30#include <linux/udp.h>
31#include <linux/if_arp.h>
32#include <linux/if_ether.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/skbuff.h>
37#include <linux/rtnetlink.h>
38#include <linux/if_vlan.h>
c4e84bde
RM		 39#include <linux/delay.h>
40#include <linux/mm.h>
41#include <linux/vmalloc.h>
b7c6bfb7 42#include <net/ip6_checksum.h>
c4e84bde
RM		 43
44#include "qlge.h"
45
46char qlge_driver_name[] = DRV_NAME;
47const char qlge_driver_version[] = DRV_VERSION;
48
49MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
50MODULE_DESCRIPTION(DRV_STRING " ");
51MODULE_LICENSE("GPL");
52MODULE_VERSION(DRV_VERSION);
53
54static const u32 default_msg =
55 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
56/* NETIF_MSG_TIMER | */
57 NETIF_MSG_IFDOWN |
58 NETIF_MSG_IFUP |
59 NETIF_MSG_RX_ERR |
60 NETIF_MSG_TX_ERR |
61 NETIF_MSG_TX_QUEUED |
62 NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS |
63/* NETIF_MSG_PKTDATA | */
64 NETIF_MSG_HW | NETIF_MSG_WOL | 0;
65
66static int debug = 0x00007fff; /* defaults above */
67module_param(debug, int, 0);
68MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
69
70#define MSIX_IRQ 0
71#define MSI_IRQ 1
72#define LEG_IRQ 2
73static int irq_type = MSIX_IRQ;
74module_param(irq_type, int, MSIX_IRQ);
75MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
76
77static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
78 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID)},
79 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID1)},
80 /* required last entry */
81 {0,}
82};
83
84MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
85
86/* This hardware semaphore causes exclusive access to
87 * resources shared between the NIC driver, MPI firmware,
88 * FCOE firmware and the FC driver.
89 */
90static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
91{
92 u32 sem_bits = 0;
93
94 switch (sem_mask) {
95 case SEM_XGMAC0_MASK:
96 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
97 break;
98 case SEM_XGMAC1_MASK:
99 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
100 break;
101 case SEM_ICB_MASK:
102 sem_bits = SEM_SET << SEM_ICB_SHIFT;
103 break;
104 case SEM_MAC_ADDR_MASK:
105 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
106 break;
107 case SEM_FLASH_MASK:
108 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
109 break;
110 case SEM_PROBE_MASK:
111 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
112 break;
113 case SEM_RT_IDX_MASK:
114 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
115 break;
116 case SEM_PROC_REG_MASK:
117 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
118 break;
119 default:
120 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
121 return -EINVAL;
122 }
123
124 ql_write32(qdev, SEM, sem_bits | sem_mask);
125 return !(ql_read32(qdev, SEM) & sem_bits);
126}
127
128int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
129{
130 unsigned int seconds = 3;
131 do {
132 if (!ql_sem_trylock(qdev, sem_mask))
133 return 0;
134 ssleep(1);
135 } while (--seconds);
136 return -ETIMEDOUT;
137}
138
139void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
140{
141 ql_write32(qdev, SEM, sem_mask);
142 ql_read32(qdev, SEM); /* flush */
143}
144
145/* This function waits for a specific bit to come ready
146 * in a given register. It is used mostly by the initialize
147 * process, but is also used in kernel thread API such as
148 * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
149 */
150int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
151{
152 u32 temp;
153 int count = UDELAY_COUNT;
154
155 while (count) {
156 temp = ql_read32(qdev, reg);
157
158 /* check for errors */
159 if (temp & err_bit) {
160 QPRINTK(qdev, PROBE, ALERT,
161 "register 0x%.08x access error, value = 0x%.08x!.\n",
162 reg, temp);
163 return -EIO;
164 } else if (temp & bit)
165 return 0;
166 udelay(UDELAY_DELAY);
167 count--;
168 }
169 QPRINTK(qdev, PROBE, ALERT,
170 "Timed out waiting for reg %x to come ready.\n", reg);
171 return -ETIMEDOUT;
172}
173
174/* The CFG register is used to download TX and RX control blocks
175 * to the chip. This function waits for an operation to complete.
176 */
177static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
178{
179 int count = UDELAY_COUNT;
180 u32 temp;
181
182 while (count) {
183 temp = ql_read32(qdev, CFG);
184 if (temp & CFG_LE)
185 return -EIO;
186 if (!(temp & bit))
187 return 0;
188 udelay(UDELAY_DELAY);
189 count--;
190 }
191 return -ETIMEDOUT;
192}
193
194
195/* Used to issue init control blocks to hw. Maps control block,
196 * sets address, triggers download, waits for completion.
197 */
198int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
199 u16 q_id)
200{
201 u64 map;
202 int status = 0;
203 int direction;
204 u32 mask;
205 u32 value;
206
207 direction =
208 (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
209 PCI_DMA_FROMDEVICE;
210
211 map = pci_map_single(qdev->pdev, ptr, size, direction);
212 if (pci_dma_mapping_error(qdev->pdev, map)) {
213 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
214 return -ENOMEM;
215 }
216
217 status = ql_wait_cfg(qdev, bit);
218 if (status) {
219 QPRINTK(qdev, IFUP, ERR,
220 "Timed out waiting for CFG to come ready.\n");
221 goto exit;
222 }
223
224 status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
225 if (status)
226 goto exit;
227 ql_write32(qdev, ICB_L, (u32) map);
228 ql_write32(qdev, ICB_H, (u32) (map >> 32));
229 ql_sem_unlock(qdev, SEM_ICB_MASK); /* does flush too */
230
231 mask = CFG_Q_MASK | (bit << 16);
232 value = bit | (q_id << CFG_Q_SHIFT);
233 ql_write32(qdev, CFG, (mask | value));
234
235 /*
236 * Wait for the bit to clear after signaling hw.
237 */
238 status = ql_wait_cfg(qdev, bit);
239exit:
240 pci_unmap_single(qdev->pdev, map, size, direction);
241 return status;
242}
243
244/* Get a specific MAC address from the CAM. Used for debug and reg dump. */
245int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
246 u32 *value)
247{
248 u32 offset = 0;
249 int status;
250
251 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
252 if (status)
253 return status;
254 switch (type) {
255 case MAC_ADDR_TYPE_MULTI_MAC:
256 case MAC_ADDR_TYPE_CAM_MAC:
257 {
258 status =
259 ql_wait_reg_rdy(qdev,
939678f8 260 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 261 if (status)
262 goto exit;
263 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
264 (index << MAC_ADDR_IDX_SHIFT) | /* index */
265 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
266 status =
267 ql_wait_reg_rdy(qdev,
939678f8 268 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
c4e84bde
RM		 269 if (status)
270 goto exit;
271 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
272 status =
273 ql_wait_reg_rdy(qdev,
939678f8 274 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 275 if (status)
276 goto exit;
277 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
278 (index << MAC_ADDR_IDX_SHIFT) | /* index */
279 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
280 status =
281 ql_wait_reg_rdy(qdev,
939678f8 282 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
c4e84bde
RM		 283 if (status)
284 goto exit;
285 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
286 if (type == MAC_ADDR_TYPE_CAM_MAC) {
287 status =
288 ql_wait_reg_rdy(qdev,
939678f8 289 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 290 if (status)
291 goto exit;
292 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
293 (index << MAC_ADDR_IDX_SHIFT) | /* index */
294 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
295 status =
296 ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
939678f8 297 MAC_ADDR_MR, 0);
c4e84bde
RM		 298 if (status)
299 goto exit;
300 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
301 }
302 break;
303 }
304 case MAC_ADDR_TYPE_VLAN:
305 case MAC_ADDR_TYPE_MULTI_FLTR:
306 default:
307 QPRINTK(qdev, IFUP, CRIT,
308 "Address type %d not yet supported.\n", type);
309 status = -EPERM;
310 }
311exit:
312 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
313 return status;
314}
315
316/* Set up a MAC, multicast or VLAN address for the
317 * inbound frame matching.
318 */
319static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
320 u16 index)
321{
322 u32 offset = 0;
323 int status = 0;
324
325 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
326 if (status)
327 return status;
328 switch (type) {
329 case MAC_ADDR_TYPE_MULTI_MAC:
330 case MAC_ADDR_TYPE_CAM_MAC:
331 {
332 u32 cam_output;
333 u32 upper = (addr[0] << 8) | addr[1];
334 u32 lower =
335 (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
336 (addr[5]);
337
338 QPRINTK(qdev, IFUP, INFO,
7c510e4b 339 "Adding %s address %pM"
c4e84bde
RM		 340 " at index %d in the CAM.\n",
341 ((type ==
342 MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
7c510e4b 343 "UNICAST"), addr, index);
c4e84bde
RM		 344
345 status =
346 ql_wait_reg_rdy(qdev,
939678f8 347 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 348 if (status)
349 goto exit;
350 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
351 (index << MAC_ADDR_IDX_SHIFT) | /* index */
352 type); /* type */
353 ql_write32(qdev, MAC_ADDR_DATA, lower);
354 status =
355 ql_wait_reg_rdy(qdev,
939678f8 356 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 357 if (status)
358 goto exit;
359 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
360 (index << MAC_ADDR_IDX_SHIFT) | /* index */
361 type); /* type */
362 ql_write32(qdev, MAC_ADDR_DATA, upper);
363 status =
364 ql_wait_reg_rdy(qdev,
939678f8 365 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 366 if (status)
367 goto exit;
368 ql_write32(qdev, MAC_ADDR_IDX, (offset) | /* offset */
369 (index << MAC_ADDR_IDX_SHIFT) | /* index */
370 type); /* type */
371 /* This field should also include the queue id
372 and possibly the function id. Right now we hardcode
373 the route field to NIC core.
374 */
375 if (type == MAC_ADDR_TYPE_CAM_MAC) {
376 cam_output = (CAM_OUT_ROUTE_NIC |
377 (qdev->
378 func << CAM_OUT_FUNC_SHIFT) |
379 (qdev->
380 rss_ring_first_cq_id <<
381 CAM_OUT_CQ_ID_SHIFT));
382 if (qdev->vlgrp)
383 cam_output |= CAM_OUT_RV;
384 /* route to NIC core */
385 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
386 }
387 break;
388 }
389 case MAC_ADDR_TYPE_VLAN:
390 {
391 u32 enable_bit = *((u32 *) &addr[0]);
392 /* For VLAN, the addr actually holds a bit that
393 * either enables or disables the vlan id we are
394 * addressing. It's either MAC_ADDR_E on or off.
395 * That's bit-27 we're talking about.
396 */
397 QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
398 (enable_bit ? "Adding" : "Removing"),
399 index, (enable_bit ? "to" : "from"));
400
401 status =
402 ql_wait_reg_rdy(qdev,
939678f8 403 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
c4e84bde
RM		 404 if (status)
405 goto exit;
406 ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
407 (index << MAC_ADDR_IDX_SHIFT) | /* index */
408 type | /* type */
409 enable_bit); /* enable/disable */
410 break;
411 }
412 case MAC_ADDR_TYPE_MULTI_FLTR:
413 default:
414 QPRINTK(qdev, IFUP, CRIT,
415 "Address type %d not yet supported.\n", type);
416 status = -EPERM;
417 }
418exit:
419 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
420 return status;
421}
422
423/* Get a specific frame routing value from the CAM.
424 * Used for debug and reg dump.
425 */
426int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
427{
428 int status = 0;
429
430 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
431 if (status)
432 goto exit;
433
939678f8 434 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
c4e84bde
RM		 435 if (status)
436 goto exit;
437
438 ql_write32(qdev, RT_IDX,
439 RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
939678f8 440 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
c4e84bde
RM		 441 if (status)
442 goto exit;
443 *value = ql_read32(qdev, RT_DATA);
444exit:
445 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
446 return status;
447}
448
449/* The NIC function for this chip has 16 routing indexes. Each one can be used
450 * to route different frame types to various inbound queues. We send broadcast/
451 * multicast/error frames to the default queue for slow handling,
452 * and CAM hit/RSS frames to the fast handling queues.
453 */
454static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
455 int enable)
456{
457 int status;
458 u32 value = 0;
459
460 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
461 if (status)
462 return status;
463
464 QPRINTK(qdev, IFUP, DEBUG,
465 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
466 (enable ? "Adding" : "Removing"),
467 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
468 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
469 ((index ==
470 RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
471 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
472 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
473 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
474 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
475 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
476 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
477 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
478 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
479 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
480 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
481 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
482 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
483 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
484 (enable ? "to" : "from"));
485
486 switch (mask) {
487 case RT_IDX_CAM_HIT:
488 {
489 value = RT_IDX_DST_CAM_Q | /* dest */
490 RT_IDX_TYPE_NICQ | /* type */
491 (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
492 break;
493 }
494 case RT_IDX_VALID: /* Promiscuous Mode frames. */
495 {
496 value = RT_IDX_DST_DFLT_Q | /* dest */
497 RT_IDX_TYPE_NICQ | /* type */
498 (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
499 break;
500 }
501 case RT_IDX_ERR: /* Pass up MAC,IP,TCP/UDP error frames. */
502 {
503 value = RT_IDX_DST_DFLT_Q | /* dest */
504 RT_IDX_TYPE_NICQ | /* type */
505 (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
506 break;
507 }
508 case RT_IDX_BCAST: /* Pass up Broadcast frames to default Q. */
509 {
510 value = RT_IDX_DST_DFLT_Q | /* dest */
511 RT_IDX_TYPE_NICQ | /* type */
512 (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
513 break;
514 }
515 case RT_IDX_MCAST: /* Pass up All Multicast frames. */
516 {
517 value = RT_IDX_DST_CAM_Q | /* dest */
518 RT_IDX_TYPE_NICQ | /* type */
519 (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
520 break;
521 }
522 case RT_IDX_MCAST_MATCH: /* Pass up matched Multicast frames. */
523 {
524 value = RT_IDX_DST_CAM_Q | /* dest */
525 RT_IDX_TYPE_NICQ | /* type */
526 (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
527 break;
528 }
529 case RT_IDX_RSS_MATCH: /* Pass up matched RSS frames. */
530 {
531 value = RT_IDX_DST_RSS | /* dest */
532 RT_IDX_TYPE_NICQ | /* type */
533 (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
534 break;
535 }
536 case 0: /* Clear the E-bit on an entry. */
537 {
538 value = RT_IDX_DST_DFLT_Q | /* dest */
539 RT_IDX_TYPE_NICQ | /* type */
540 (index << RT_IDX_IDX_SHIFT);/* index */
541 break;
542 }
543 default:
544 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
545 mask);
546 status = -EPERM;
547 goto exit;
548 }
549
550 if (value) {
551 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
552 if (status)
553 goto exit;
554 value |= (enable ? RT_IDX_E : 0);
555 ql_write32(qdev, RT_IDX, value);
556 ql_write32(qdev, RT_DATA, enable ? mask : 0);
557 }
558exit:
559 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
560 return status;
561}
562
563static void ql_enable_interrupts(struct ql_adapter *qdev)
564{
565 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
566}
567
568static void ql_disable_interrupts(struct ql_adapter *qdev)
569{
570 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
571}
572
573/* If we're running with multiple MSI-X vectors then we enable on the fly.
574 * Otherwise, we may have multiple outstanding workers and don't want to
575 * enable until the last one finishes. In this case, the irq_cnt gets
576 * incremented everytime we queue a worker and decremented everytime
577 * a worker finishes. Once it hits zero we enable the interrupt.
578 */
bb0d215c 579u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
c4e84bde 580{
bb0d215c
RM		 581 u32 var = 0;
582 unsigned long hw_flags = 0;
583 struct intr_context *ctx = qdev->intr_context + intr;
584
585 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
586 /* Always enable if we're MSIX multi interrupts and
587 * it's not the default (zeroeth) interrupt.
588 */
c4e84bde 589 ql_write32(qdev, INTR_EN,
bb0d215c
RM		 590 ctx->intr_en_mask);
591 var = ql_read32(qdev, STS);
592 return var;
c4e84bde 593 }
bb0d215c
RM		 594
595 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
596 if (atomic_dec_and_test(&ctx->irq_cnt)) {
597 ql_write32(qdev, INTR_EN,
598 ctx->intr_en_mask);
599 var = ql_read32(qdev, STS);
600 }
601 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
602 return var;
c4e84bde
RM		 603}
604
605static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
606{
607 u32 var = 0;
bb0d215c
RM		 608 unsigned long hw_flags;
609 struct intr_context *ctx;
c4e84bde 610
bb0d215c
RM		 611 /* HW disables for us if we're MSIX multi interrupts and
612 * it's not the default (zeroeth) interrupt.
613 */
614 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
615 return 0;
616
617 ctx = qdev->intr_context + intr;
618 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
619 if (!atomic_read(&ctx->irq_cnt)) {
c4e84bde 620 ql_write32(qdev, INTR_EN,
bb0d215c 621 ctx->intr_dis_mask);
c4e84bde
RM		 622 var = ql_read32(qdev, STS);
623 }
bb0d215c
RM		 624 atomic_inc(&ctx->irq_cnt);
625 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
c4e84bde
RM		 626 return var;
627}
628
629static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
630{
631 int i;
632 for (i = 0; i < qdev->intr_count; i++) {
633 /* The enable call does a atomic_dec_and_test
634 * and enables only if the result is zero.
635 * So we precharge it here.
636 */
bb0d215c
RM		 637 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
638 i == 0))
639 atomic_set(&qdev->intr_context[i].irq_cnt, 1);
c4e84bde
RM		 640 ql_enable_completion_interrupt(qdev, i);
641 }
642
643}
644
8668ae92 645static int ql_read_flash_word(struct ql_adapter *qdev, int offset, u32 *data)
c4e84bde
RM		 646{
647 int status = 0;
648 /* wait for reg to come ready */
649 status = ql_wait_reg_rdy(qdev,
650 FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
651 if (status)
652 goto exit;
653 /* set up for reg read */
654 ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
655 /* wait for reg to come ready */
656 status = ql_wait_reg_rdy(qdev,
657 FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
658 if (status)
659 goto exit;
660 /* get the data */
661 *data = ql_read32(qdev, FLASH_DATA);
662exit:
663 return status;
664}
665
666static int ql_get_flash_params(struct ql_adapter *qdev)
667{
668 int i;
669 int status;
670 u32 *p = (u32 *)&qdev->flash;
671
672 if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
673 return -ETIMEDOUT;
674
675 for (i = 0; i < sizeof(qdev->flash) / sizeof(u32); i++, p++) {
676 status = ql_read_flash_word(qdev, i, p);
677 if (status) {
678 QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
679 goto exit;
680 }
681
682 }
683exit:
684 ql_sem_unlock(qdev, SEM_FLASH_MASK);
685 return status;
686}
687
688/* xgmac register are located behind the xgmac_addr and xgmac_data
689 * register pair. Each read/write requires us to wait for the ready
690 * bit before reading/writing the data.
691 */
692static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
693{
694 int status;
695 /* wait for reg to come ready */
696 status = ql_wait_reg_rdy(qdev,
697 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
698 if (status)
699 return status;
700 /* write the data to the data reg */
701 ql_write32(qdev, XGMAC_DATA, data);
702 /* trigger the write */
703 ql_write32(qdev, XGMAC_ADDR, reg);
704 return status;
705}
706
707/* xgmac register are located behind the xgmac_addr and xgmac_data
708 * register pair. Each read/write requires us to wait for the ready
709 * bit before reading/writing the data.
710 */
711int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
712{
713 int status = 0;
714 /* wait for reg to come ready */
715 status = ql_wait_reg_rdy(qdev,
716 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
717 if (status)
718 goto exit;
719 /* set up for reg read */
720 ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
721 /* wait for reg to come ready */
722 status = ql_wait_reg_rdy(qdev,
723 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
724 if (status)
725 goto exit;
726 /* get the data */
727 *data = ql_read32(qdev, XGMAC_DATA);
728exit:
729 return status;
730}
731
732/* This is used for reading the 64-bit statistics regs. */
733int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
734{
735 int status = 0;
736 u32 hi = 0;
737 u32 lo = 0;
738
739 status = ql_read_xgmac_reg(qdev, reg, &lo);
740 if (status)
741 goto exit;
742
743 status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
744 if (status)
745 goto exit;
746
747 *data = (u64) lo | ((u64) hi << 32);
748
749exit:
750 return status;
751}
752
753/* Take the MAC Core out of reset.
754 * Enable statistics counting.
755 * Take the transmitter/receiver out of reset.
756 * This functionality may be done in the MPI firmware at a
757 * later date.
758 */
759static int ql_port_initialize(struct ql_adapter *qdev)
760{
761 int status = 0;
762 u32 data;
763
764 if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
765 /* Another function has the semaphore, so
766 * wait for the port init bit to come ready.
767 */
768 QPRINTK(qdev, LINK, INFO,
769 "Another function has the semaphore, so wait for the port init bit to come ready.\n");
770 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
771 if (status) {
772 QPRINTK(qdev, LINK, CRIT,
773 "Port initialize timed out.\n");
774 }
775 return status;
776 }
777
778 QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
779 /* Set the core reset. */
780 status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
781 if (status)
782 goto end;
783 data |= GLOBAL_CFG_RESET;
784 status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
785 if (status)
786 goto end;
787
788 /* Clear the core reset and turn on jumbo for receiver. */
789 data &= ~GLOBAL_CFG_RESET; /* Clear core reset. */
790 data |= GLOBAL_CFG_JUMBO; /* Turn on jumbo. */
791 data |= GLOBAL_CFG_TX_STAT_EN;
792 data |= GLOBAL_CFG_RX_STAT_EN;
793 status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
794 if (status)
795 goto end;
796
797 /* Enable transmitter, and clear it's reset. */
798 status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
799 if (status)
800 goto end;
801 data &= ~TX_CFG_RESET; /* Clear the TX MAC reset. */
802 data |= TX_CFG_EN; /* Enable the transmitter. */
803 status = ql_write_xgmac_reg(qdev, TX_CFG, data);
804 if (status)
805 goto end;
806
807 /* Enable receiver and clear it's reset. */
808 status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
809 if (status)
810 goto end;
811 data &= ~RX_CFG_RESET; /* Clear the RX MAC reset. */
812 data |= RX_CFG_EN; /* Enable the receiver. */
813 status = ql_write_xgmac_reg(qdev, RX_CFG, data);
814 if (status)
815 goto end;
816
817 /* Turn on jumbo. */
818 status =
819 ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
820 if (status)
821 goto end;
822 status =
823 ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
824 if (status)
825 goto end;
826
827 /* Signal to the world that the port is enabled. */
828 ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
829end:
830 ql_sem_unlock(qdev, qdev->xg_sem_mask);
831 return status;
832}
833
834/* Get the next large buffer. */
8668ae92 835static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
c4e84bde
RM		 836{
837 struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
838 rx_ring->lbq_curr_idx++;
839 if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
840 rx_ring->lbq_curr_idx = 0;
841 rx_ring->lbq_free_cnt++;
842 return lbq_desc;
843}
844
845/* Get the next small buffer. */
8668ae92 846static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
c4e84bde
RM		 847{
848 struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
849 rx_ring->sbq_curr_idx++;
850 if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
851 rx_ring->sbq_curr_idx = 0;
852 rx_ring->sbq_free_cnt++;
853 return sbq_desc;
854}
855
856/* Update an rx ring index. */
857static void ql_update_cq(struct rx_ring *rx_ring)
858{
859 rx_ring->cnsmr_idx++;
860 rx_ring->curr_entry++;
861 if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
862 rx_ring->cnsmr_idx = 0;
863 rx_ring->curr_entry = rx_ring->cq_base;
864 }
865}
866
867static void ql_write_cq_idx(struct rx_ring *rx_ring)
868{
869 ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
870}
871
872/* Process (refill) a large buffer queue. */
873static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
874{
875 int clean_idx = rx_ring->lbq_clean_idx;
876 struct bq_desc *lbq_desc;
c4e84bde
RM		 877 u64 map;
878 int i;
879
880 while (rx_ring->lbq_free_cnt > 16) {
881 for (i = 0; i < 16; i++) {
882 QPRINTK(qdev, RX_STATUS, DEBUG,
883 "lbq: try cleaning clean_idx = %d.\n",
884 clean_idx);
885 lbq_desc = &rx_ring->lbq[clean_idx];
c4e84bde
RM		 886 if (lbq_desc->p.lbq_page == NULL) {
887 QPRINTK(qdev, RX_STATUS, DEBUG,
888 "lbq: getting new page for index %d.\n",
889 lbq_desc->index);
890 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
891 if (lbq_desc->p.lbq_page == NULL) {
892 QPRINTK(qdev, RX_STATUS, ERR,
893 "Couldn't get a page.\n");
894 return;
895 }
896 map = pci_map_page(qdev->pdev,
897 lbq_desc->p.lbq_page,
898 0, PAGE_SIZE,
899 PCI_DMA_FROMDEVICE);
900 if (pci_dma_mapping_error(qdev->pdev, map)) {
901 QPRINTK(qdev, RX_STATUS, ERR,
902 "PCI mapping failed.\n");
903 return;
904 }
905 pci_unmap_addr_set(lbq_desc, mapaddr, map);
906 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
2c9a0d41 907 *lbq_desc->addr = cpu_to_le64(map);
c4e84bde
RM		 908 }
909 clean_idx++;
910 if (clean_idx == rx_ring->lbq_len)
911 clean_idx = 0;
912 }
913
914 rx_ring->lbq_clean_idx = clean_idx;
915 rx_ring->lbq_prod_idx += 16;
916 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
917 rx_ring->lbq_prod_idx = 0;
918 QPRINTK(qdev, RX_STATUS, DEBUG,
919 "lbq: updating prod idx = %d.\n",
920 rx_ring->lbq_prod_idx);
921 ql_write_db_reg(rx_ring->lbq_prod_idx,
922 rx_ring->lbq_prod_idx_db_reg);
923 rx_ring->lbq_free_cnt -= 16;
924 }
925}
926
927/* Process (refill) a small buffer queue. */
928static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
929{
930 int clean_idx = rx_ring->sbq_clean_idx;
931 struct bq_desc *sbq_desc;
c4e84bde
RM		 932 u64 map;
933 int i;
934
935 while (rx_ring->sbq_free_cnt > 16) {
936 for (i = 0; i < 16; i++) {
937 sbq_desc = &rx_ring->sbq[clean_idx];
938 QPRINTK(qdev, RX_STATUS, DEBUG,
939 "sbq: try cleaning clean_idx = %d.\n",
940 clean_idx);
c4e84bde
RM		 941 if (sbq_desc->p.skb == NULL) {
942 QPRINTK(qdev, RX_STATUS, DEBUG,
943 "sbq: getting new skb for index %d.\n",
944 sbq_desc->index);
945 sbq_desc->p.skb =
946 netdev_alloc_skb(qdev->ndev,
947 rx_ring->sbq_buf_size);
948 if (sbq_desc->p.skb == NULL) {
949 QPRINTK(qdev, PROBE, ERR,
950 "Couldn't get an skb.\n");
951 rx_ring->sbq_clean_idx = clean_idx;
952 return;
953 }
954 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
955 map = pci_map_single(qdev->pdev,
956 sbq_desc->p.skb->data,
957 rx_ring->sbq_buf_size /
958 2, PCI_DMA_FROMDEVICE);
c907a35a
RM		 959 if (pci_dma_mapping_error(qdev->pdev, map)) {
960 QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
961 rx_ring->sbq_clean_idx = clean_idx;
962 return;
963 }
c4e84bde
RM		 964 pci_unmap_addr_set(sbq_desc, mapaddr, map);
965 pci_unmap_len_set(sbq_desc, maplen,
966 rx_ring->sbq_buf_size / 2);
2c9a0d41 967 *sbq_desc->addr = cpu_to_le64(map);
c4e84bde
RM		 968 }
969
970 clean_idx++;
971 if (clean_idx == rx_ring->sbq_len)
972 clean_idx = 0;
973 }
974 rx_ring->sbq_clean_idx = clean_idx;
975 rx_ring->sbq_prod_idx += 16;
976 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
977 rx_ring->sbq_prod_idx = 0;
978 QPRINTK(qdev, RX_STATUS, DEBUG,
979 "sbq: updating prod idx = %d.\n",
980 rx_ring->sbq_prod_idx);
981 ql_write_db_reg(rx_ring->sbq_prod_idx,
982 rx_ring->sbq_prod_idx_db_reg);
983
984 rx_ring->sbq_free_cnt -= 16;
985 }
986}
987
988static void ql_update_buffer_queues(struct ql_adapter *qdev,
989 struct rx_ring *rx_ring)
990{
991 ql_update_sbq(qdev, rx_ring);
992 ql_update_lbq(qdev, rx_ring);
993}
994
995/* Unmaps tx buffers. Can be called from send() if a pci mapping
996 * fails at some stage, or from the interrupt when a tx completes.
997 */
998static void ql_unmap_send(struct ql_adapter *qdev,
999 struct tx_ring_desc *tx_ring_desc, int mapped)
1000{
1001 int i;
1002 for (i = 0; i < mapped; i++) {
1003 if (i == 0 || (i == 7 && mapped > 7)) {
1004 /*
1005 * Unmap the skb->data area, or the
1006 * external sglist (AKA the Outbound
1007 * Address List (OAL)).
1008 * If its the zeroeth element, then it's
1009 * the skb->data area. If it's the 7th
1010 * element and there is more than 6 frags,
1011 * then its an OAL.
1012 */
1013 if (i == 7) {
1014 QPRINTK(qdev, TX_DONE, DEBUG,
1015 "unmapping OAL area.\n");
1016 }
1017 pci_unmap_single(qdev->pdev,
1018 pci_unmap_addr(&tx_ring_desc->map[i],
1019 mapaddr),
1020 pci_unmap_len(&tx_ring_desc->map[i],
1021 maplen),
1022 PCI_DMA_TODEVICE);
1023 } else {
1024 QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1025 i);
1026 pci_unmap_page(qdev->pdev,
1027 pci_unmap_addr(&tx_ring_desc->map[i],
1028 mapaddr),
1029 pci_unmap_len(&tx_ring_desc->map[i],
1030 maplen), PCI_DMA_TODEVICE);
1031 }
1032 }
1033
1034}
1035
1036/* Map the buffers for this transmit. This will return
1037 * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1038 */
1039static int ql_map_send(struct ql_adapter *qdev,
1040 struct ob_mac_iocb_req *mac_iocb_ptr,
1041 struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1042{
1043 int len = skb_headlen(skb);
1044 dma_addr_t map;
1045 int frag_idx, err, map_idx = 0;
1046 struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1047 int frag_cnt = skb_shinfo(skb)->nr_frags;
1048
1049 if (frag_cnt) {
1050 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1051 }
1052 /*
1053 * Map the skb buffer first.
1054 */
1055 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1056
1057 err = pci_dma_mapping_error(qdev->pdev, map);
1058 if (err) {
1059 QPRINTK(qdev, TX_QUEUED, ERR,
1060 "PCI mapping failed with error: %d\n", err);
1061
1062 return NETDEV_TX_BUSY;
1063 }
1064
1065 tbd->len = cpu_to_le32(len);
1066 tbd->addr = cpu_to_le64(map);
1067 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1068 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1069 map_idx++;
1070
1071 /*
1072 * This loop fills the remainder of the 8 address descriptors
1073 * in the IOCB. If there are more than 7 fragments, then the
1074 * eighth address desc will point to an external list (OAL).
1075 * When this happens, the remainder of the frags will be stored
1076 * in this list.
1077 */
1078 for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1079 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1080 tbd++;
1081 if (frag_idx == 6 && frag_cnt > 7) {
1082 /* Let's tack on an sglist.
1083 * Our control block will now
1084 * look like this:
1085 * iocb->seg[0] = skb->data
1086 * iocb->seg[1] = frag[0]
1087 * iocb->seg[2] = frag[1]
1088 * iocb->seg[3] = frag[2]
1089 * iocb->seg[4] = frag[3]
1090 * iocb->seg[5] = frag[4]
1091 * iocb->seg[6] = frag[5]
1092 * iocb->seg[7] = ptr to OAL (external sglist)
1093 * oal->seg[0] = frag[6]
1094 * oal->seg[1] = frag[7]
1095 * oal->seg[2] = frag[8]
1096 * oal->seg[3] = frag[9]
1097 * oal->seg[4] = frag[10]
1098 * etc...
1099 */
1100 /* Tack on the OAL in the eighth segment of IOCB. */
1101 map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1102 sizeof(struct oal),
1103 PCI_DMA_TODEVICE);
1104 err = pci_dma_mapping_error(qdev->pdev, map);
1105 if (err) {
1106 QPRINTK(qdev, TX_QUEUED, ERR,
1107 "PCI mapping outbound address list with error: %d\n",
1108 err);
1109 goto map_error;
1110 }
1111
1112 tbd->addr = cpu_to_le64(map);
1113 /*
1114 * The length is the number of fragments
1115 * that remain to be mapped times the length
1116 * of our sglist (OAL).
1117 */
1118 tbd->len =
1119 cpu_to_le32((sizeof(struct tx_buf_desc) *
1120 (frag_cnt - frag_idx)) | TX_DESC_C);
1121 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1122 map);
1123 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1124 sizeof(struct oal));
1125 tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1126 map_idx++;
1127 }
1128
1129 map =
1130 pci_map_page(qdev->pdev, frag->page,
1131 frag->page_offset, frag->size,
1132 PCI_DMA_TODEVICE);
1133
1134 err = pci_dma_mapping_error(qdev->pdev, map);
1135 if (err) {
1136 QPRINTK(qdev, TX_QUEUED, ERR,
1137 "PCI mapping frags failed with error: %d.\n",
1138 err);
1139 goto map_error;
1140 }
1141
1142 tbd->addr = cpu_to_le64(map);
1143 tbd->len = cpu_to_le32(frag->size);
1144 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1145 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1146 frag->size);
1147
1148 }
1149 /* Save the number of segments we've mapped. */
1150 tx_ring_desc->map_cnt = map_idx;
1151 /* Terminate the last segment. */
1152 tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1153 return NETDEV_TX_OK;
1154
1155map_error:
1156 /*
1157 * If the first frag mapping failed, then i will be zero.
1158 * This causes the unmap of the skb->data area. Otherwise
1159 * we pass in the number of frags that mapped successfully
1160 * so they can be umapped.
1161 */
1162 ql_unmap_send(qdev, tx_ring_desc, map_idx);
1163 return NETDEV_TX_BUSY;
1164}
1165
8668ae92 1166static void ql_realign_skb(struct sk_buff *skb, int len)
c4e84bde
RM		 1167{
1168 void *temp_addr = skb->data;
1169
1170 /* Undo the skb_reserve(skb,32) we did before
1171 * giving to hardware, and realign data on
1172 * a 2-byte boundary.
1173 */
1174 skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1175 skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1176 skb_copy_to_linear_data(skb, temp_addr,
1177 (unsigned int)len);
1178}
1179
1180/*
1181 * This function builds an skb for the given inbound
1182 * completion. It will be rewritten for readability in the near
1183 * future, but for not it works well.
1184 */
1185static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1186 struct rx_ring *rx_ring,
1187 struct ib_mac_iocb_rsp *ib_mac_rsp)
1188{
1189 struct bq_desc *lbq_desc;
1190 struct bq_desc *sbq_desc;
1191 struct sk_buff *skb = NULL;
1192 u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1193 u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1194
1195 /*
1196 * Handle the header buffer if present.
1197 */
1198 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1199 ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1200 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1201 /*
1202 * Headers fit nicely into a small buffer.
1203 */
1204 sbq_desc = ql_get_curr_sbuf(rx_ring);
1205 pci_unmap_single(qdev->pdev,
1206 pci_unmap_addr(sbq_desc, mapaddr),
1207 pci_unmap_len(sbq_desc, maplen),
1208 PCI_DMA_FROMDEVICE);
1209 skb = sbq_desc->p.skb;
1210 ql_realign_skb(skb, hdr_len);
1211 skb_put(skb, hdr_len);
1212 sbq_desc->p.skb = NULL;
1213 }
1214
1215 /*
1216 * Handle the data buffer(s).
1217 */
1218 if (unlikely(!length)) { /* Is there data too? */
1219 QPRINTK(qdev, RX_STATUS, DEBUG,
1220 "No Data buffer in this packet.\n");
1221 return skb;
1222 }
1223
1224 if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1225 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1226 QPRINTK(qdev, RX_STATUS, DEBUG,
1227 "Headers in small, data of %d bytes in small, combine them.\n", length);
1228 /*
1229 * Data is less than small buffer size so it's
1230 * stuffed in a small buffer.
1231 * For this case we append the data
1232 * from the "data" small buffer to the "header" small
1233 * buffer.
1234 */
1235 sbq_desc = ql_get_curr_sbuf(rx_ring);
1236 pci_dma_sync_single_for_cpu(qdev->pdev,
1237 pci_unmap_addr
1238 (sbq_desc, mapaddr),
1239 pci_unmap_len
1240 (sbq_desc, maplen),
1241 PCI_DMA_FROMDEVICE);
1242 memcpy(skb_put(skb, length),
1243 sbq_desc->p.skb->data, length);
1244 pci_dma_sync_single_for_device(qdev->pdev,
1245 pci_unmap_addr
1246 (sbq_desc,
1247 mapaddr),
1248 pci_unmap_len
1249 (sbq_desc,
1250 maplen),
1251 PCI_DMA_FROMDEVICE);
1252 } else {
1253 QPRINTK(qdev, RX_STATUS, DEBUG,
1254 "%d bytes in a single small buffer.\n", length);
1255 sbq_desc = ql_get_curr_sbuf(rx_ring);
1256 skb = sbq_desc->p.skb;
1257 ql_realign_skb(skb, length);
1258 skb_put(skb, length);
1259 pci_unmap_single(qdev->pdev,
1260 pci_unmap_addr(sbq_desc,
1261 mapaddr),
1262 pci_unmap_len(sbq_desc,
1263 maplen),
1264 PCI_DMA_FROMDEVICE);
1265 sbq_desc->p.skb = NULL;
1266 }
1267 } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1268 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1269 QPRINTK(qdev, RX_STATUS, DEBUG,
1270 "Header in small, %d bytes in large. Chain large to small!\n", length);
1271 /*
1272 * The data is in a single large buffer. We
1273 * chain it to the header buffer's skb and let
1274 * it rip.
1275 */
1276 lbq_desc = ql_get_curr_lbuf(rx_ring);
1277 pci_unmap_page(qdev->pdev,
1278 pci_unmap_addr(lbq_desc,
1279 mapaddr),
1280 pci_unmap_len(lbq_desc, maplen),
1281 PCI_DMA_FROMDEVICE);
1282 QPRINTK(qdev, RX_STATUS, DEBUG,
1283 "Chaining page to skb.\n");
1284 skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1285 0, length);
1286 skb->len += length;
1287 skb->data_len += length;
1288 skb->truesize += length;
1289 lbq_desc->p.lbq_page = NULL;
1290 } else {
1291 /*
1292 * The headers and data are in a single large buffer. We
1293 * copy it to a new skb and let it go. This can happen with
1294 * jumbo mtu on a non-TCP/UDP frame.
1295 */
1296 lbq_desc = ql_get_curr_lbuf(rx_ring);
1297 skb = netdev_alloc_skb(qdev->ndev, length);
1298 if (skb == NULL) {
1299 QPRINTK(qdev, PROBE, DEBUG,
1300 "No skb available, drop the packet.\n");
1301 return NULL;
1302 }
4055c7d4
RM		 1303 pci_unmap_page(qdev->pdev,
1304 pci_unmap_addr(lbq_desc,
1305 mapaddr),
1306 pci_unmap_len(lbq_desc, maplen),
1307 PCI_DMA_FROMDEVICE);
c4e84bde
RM		 1308 skb_reserve(skb, NET_IP_ALIGN);
1309 QPRINTK(qdev, RX_STATUS, DEBUG,
1310 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1311 skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1312 0, length);
1313 skb->len += length;
1314 skb->data_len += length;
1315 skb->truesize += length;
1316 length -= length;
1317 lbq_desc->p.lbq_page = NULL;
1318 __pskb_pull_tail(skb,
1319 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1320 VLAN_ETH_HLEN : ETH_HLEN);
1321 }
1322 } else {
1323 /*
1324 * The data is in a chain of large buffers
1325 * pointed to by a small buffer. We loop
1326 * thru and chain them to the our small header
1327 * buffer's skb.
1328 * frags: There are 18 max frags and our small
1329 * buffer will hold 32 of them. The thing is,
1330 * we'll use 3 max for our 9000 byte jumbo
1331 * frames. If the MTU goes up we could
1332 * eventually be in trouble.
1333 */
1334 int size, offset, i = 0;
2c9a0d41 1335 __le64 *bq, bq_array[8];
c4e84bde
RM		 1336 sbq_desc = ql_get_curr_sbuf(rx_ring);
1337 pci_unmap_single(qdev->pdev,
1338 pci_unmap_addr(sbq_desc, mapaddr),
1339 pci_unmap_len(sbq_desc, maplen),
1340 PCI_DMA_FROMDEVICE);
1341 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1342 /*
1343 * This is an non TCP/UDP IP frame, so
1344 * the headers aren't split into a small
1345 * buffer. We have to use the small buffer
1346 * that contains our sg list as our skb to
1347 * send upstairs. Copy the sg list here to
1348 * a local buffer and use it to find the
1349 * pages to chain.
1350 */
1351 QPRINTK(qdev, RX_STATUS, DEBUG,
1352 "%d bytes of headers & data in chain of large.\n", length);
1353 skb = sbq_desc->p.skb;
1354 bq = &bq_array[0];
1355 memcpy(bq, skb->data, sizeof(bq_array));
1356 sbq_desc->p.skb = NULL;
1357 skb_reserve(skb, NET_IP_ALIGN);
1358 } else {
1359 QPRINTK(qdev, RX_STATUS, DEBUG,
1360 "Headers in small, %d bytes of data in chain of large.\n", length);
2c9a0d41 1361 bq = (__le64 *)sbq_desc->p.skb->data;
c4e84bde
RM		 1362 }
1363 while (length > 0) {
1364 lbq_desc = ql_get_curr_lbuf(rx_ring);
c4e84bde
RM		 1365 pci_unmap_page(qdev->pdev,
1366 pci_unmap_addr(lbq_desc,
1367 mapaddr),
1368 pci_unmap_len(lbq_desc,
1369 maplen),
1370 PCI_DMA_FROMDEVICE);
1371 size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1372 offset = 0;
1373
1374 QPRINTK(qdev, RX_STATUS, DEBUG,
1375 "Adding page %d to skb for %d bytes.\n",
1376 i, size);
1377 skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1378 offset, size);
1379 skb->len += size;
1380 skb->data_len += size;
1381 skb->truesize += size;
1382 length -= size;
1383 lbq_desc->p.lbq_page = NULL;
1384 bq++;
1385 i++;
1386 }
1387 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1388 VLAN_ETH_HLEN : ETH_HLEN);
1389 }
1390 return skb;
1391}
1392
1393/* Process an inbound completion from an rx ring. */
1394static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1395 struct rx_ring *rx_ring,
1396 struct ib_mac_iocb_rsp *ib_mac_rsp)
1397{
1398 struct net_device *ndev = qdev->ndev;
1399 struct sk_buff *skb = NULL;
1400
1401 QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1402
1403 skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1404 if (unlikely(!skb)) {
1405 QPRINTK(qdev, RX_STATUS, DEBUG,
1406 "No skb available, drop packet.\n");
1407 return;
1408 }
1409
1410 prefetch(skb->data);
1411 skb->dev = ndev;
1412 if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1413 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1414 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1415 IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1416 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1417 IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1418 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1419 IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1420 }
1421 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1422 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1423 }
1424 if (ib_mac_rsp->flags1 & (IB_MAC_IOCB_RSP_IE | IB_MAC_IOCB_RSP_TE)) {
1425 QPRINTK(qdev, RX_STATUS, ERR,
1426 "Bad checksum for this %s packet.\n",
1427 ((ib_mac_rsp->
1428 flags2 & IB_MAC_IOCB_RSP_T) ? "TCP" : "UDP"));
1429 skb->ip_summed = CHECKSUM_NONE;
1430 } else if (qdev->rx_csum &&
1431 ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) ||
1432 ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1433 !(ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_NU)))) {
1434 QPRINTK(qdev, RX_STATUS, DEBUG, "RX checksum done!\n");
1435 skb->ip_summed = CHECKSUM_UNNECESSARY;
1436 }
1437 qdev->stats.rx_packets++;
1438 qdev->stats.rx_bytes += skb->len;
1439 skb->protocol = eth_type_trans(skb, ndev);
1440 if (qdev->vlgrp && (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V)) {
1441 QPRINTK(qdev, RX_STATUS, DEBUG,
1442 "Passing a VLAN packet upstream.\n");
1443 vlan_hwaccel_rx(skb, qdev->vlgrp,
1444 le16_to_cpu(ib_mac_rsp->vlan_id));
1445 } else {
1446 QPRINTK(qdev, RX_STATUS, DEBUG,
1447 "Passing a normal packet upstream.\n");
1448 netif_rx(skb);
1449 }
c4e84bde
RM		 1450}
1451
1452/* Process an outbound completion from an rx ring. */
1453static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1454 struct ob_mac_iocb_rsp *mac_rsp)
1455{
1456 struct tx_ring *tx_ring;
1457 struct tx_ring_desc *tx_ring_desc;
1458
1459 QL_DUMP_OB_MAC_RSP(mac_rsp);
1460 tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1461 tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1462 ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1463 qdev->stats.tx_bytes += tx_ring_desc->map_cnt;
1464 qdev->stats.tx_packets++;
1465 dev_kfree_skb(tx_ring_desc->skb);
1466 tx_ring_desc->skb = NULL;
1467
1468 if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1469 OB_MAC_IOCB_RSP_S |
1470 OB_MAC_IOCB_RSP_L |
1471 OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1472 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1473 QPRINTK(qdev, TX_DONE, WARNING,
1474 "Total descriptor length did not match transfer length.\n");
1475 }
1476 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1477 QPRINTK(qdev, TX_DONE, WARNING,
1478 "Frame too short to be legal, not sent.\n");
1479 }
1480 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1481 QPRINTK(qdev, TX_DONE, WARNING,
1482 "Frame too long, but sent anyway.\n");
1483 }
1484 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1485 QPRINTK(qdev, TX_DONE, WARNING,
1486 "PCI backplane error. Frame not sent.\n");
1487 }
1488 }
1489 atomic_inc(&tx_ring->tx_count);
1490}
1491
1492/* Fire up a handler to reset the MPI processor. */
1493void ql_queue_fw_error(struct ql_adapter *qdev)
1494{
1495 netif_stop_queue(qdev->ndev);
1496 netif_carrier_off(qdev->ndev);
1497 queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1498}
1499
1500void ql_queue_asic_error(struct ql_adapter *qdev)
1501{
1502 netif_stop_queue(qdev->ndev);
1503 netif_carrier_off(qdev->ndev);
1504 ql_disable_interrupts(qdev);
1505 queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1506}
1507
1508static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1509 struct ib_ae_iocb_rsp *ib_ae_rsp)
1510{
1511 switch (ib_ae_rsp->event) {
1512 case MGMT_ERR_EVENT:
1513 QPRINTK(qdev, RX_ERR, ERR,
1514 "Management Processor Fatal Error.\n");
1515 ql_queue_fw_error(qdev);
1516 return;
1517
1518 case CAM_LOOKUP_ERR_EVENT:
1519 QPRINTK(qdev, LINK, ERR,
1520 "Multiple CAM hits lookup occurred.\n");
1521 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1522 ql_queue_asic_error(qdev);
1523 return;
1524
1525 case SOFT_ECC_ERROR_EVENT:
1526 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1527 ql_queue_asic_error(qdev);
1528 break;
1529
1530 case PCI_ERR_ANON_BUF_RD:
1531 QPRINTK(qdev, RX_ERR, ERR,
1532 "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1533 ib_ae_rsp->q_id);
1534 ql_queue_asic_error(qdev);
1535 break;
1536
1537 default:
1538 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1539 ib_ae_rsp->event);
1540 ql_queue_asic_error(qdev);
1541 break;
1542 }
1543}
1544
1545static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1546{
1547 struct ql_adapter *qdev = rx_ring->qdev;
ba7cd3ba 1548 u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
c4e84bde
RM		 1549 struct ob_mac_iocb_rsp *net_rsp = NULL;
1550 int count = 0;
1551
1552 /* While there are entries in the completion queue. */
1553 while (prod != rx_ring->cnsmr_idx) {
1554
1555 QPRINTK(qdev, RX_STATUS, DEBUG,
1556 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1557 prod, rx_ring->cnsmr_idx);
1558
1559 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1560 rmb();
1561 switch (net_rsp->opcode) {
1562
1563 case OPCODE_OB_MAC_TSO_IOCB:
1564 case OPCODE_OB_MAC_IOCB:
1565 ql_process_mac_tx_intr(qdev, net_rsp);
1566 break;
1567 default:
1568 QPRINTK(qdev, RX_STATUS, DEBUG,
1569 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1570 net_rsp->opcode);
1571 }
1572 count++;
1573 ql_update_cq(rx_ring);
ba7cd3ba 1574 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
c4e84bde
RM		 1575 }
1576 ql_write_cq_idx(rx_ring);
1577 if (netif_queue_stopped(qdev->ndev) && net_rsp != NULL) {
1578 struct tx_ring *tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1579 if (atomic_read(&tx_ring->queue_stopped) &&
1580 (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1581 /*
1582 * The queue got stopped because the tx_ring was full.
1583 * Wake it up, because it's now at least 25% empty.
1584 */
1585 netif_wake_queue(qdev->ndev);
1586 }
1587
1588 return count;
1589}
1590
1591static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1592{
1593 struct ql_adapter *qdev = rx_ring->qdev;
ba7cd3ba 1594 u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
c4e84bde
RM		 1595 struct ql_net_rsp_iocb *net_rsp;
1596 int count = 0;
1597
1598 /* While there are entries in the completion queue. */
1599 while (prod != rx_ring->cnsmr_idx) {
1600
1601 QPRINTK(qdev, RX_STATUS, DEBUG,
1602 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1603 prod, rx_ring->cnsmr_idx);
1604
1605 net_rsp = rx_ring->curr_entry;
1606 rmb();
1607 switch (net_rsp->opcode) {
1608 case OPCODE_IB_MAC_IOCB:
1609 ql_process_mac_rx_intr(qdev, rx_ring,
1610 (struct ib_mac_iocb_rsp *)
1611 net_rsp);
1612 break;
1613
1614 case OPCODE_IB_AE_IOCB:
1615 ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1616 net_rsp);
1617 break;
1618 default:
1619 {
1620 QPRINTK(qdev, RX_STATUS, DEBUG,
1621 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1622 net_rsp->opcode);
1623 }
1624 }
1625 count++;
1626 ql_update_cq(rx_ring);
ba7cd3ba 1627 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
c4e84bde
RM		 1628 if (count == budget)
1629 break;
1630 }
1631 ql_update_buffer_queues(qdev, rx_ring);
1632 ql_write_cq_idx(rx_ring);
1633 return count;
1634}
1635
1636static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1637{
1638 struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1639 struct ql_adapter *qdev = rx_ring->qdev;
1640 int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1641
1642 QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1643 rx_ring->cq_id);
1644
1645 if (work_done < budget) {
908a7a16 1646 __netif_rx_complete(napi);
c4e84bde
RM		 1647 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1648 }
1649 return work_done;
1650}
1651
1652static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1653{
1654 struct ql_adapter *qdev = netdev_priv(ndev);
1655
1656 qdev->vlgrp = grp;
1657 if (grp) {
1658 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1659 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1660 NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1661 } else {
1662 QPRINTK(qdev, IFUP, DEBUG,
1663 "Turning off VLAN in NIC_RCV_CFG.\n");
1664 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1665 }
1666}
1667
1668static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1669{
1670 struct ql_adapter *qdev = netdev_priv(ndev);
1671 u32 enable_bit = MAC_ADDR_E;
1672
1673 spin_lock(&qdev->hw_lock);
1674 if (ql_set_mac_addr_reg
1675 (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1676 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1677 }
1678 spin_unlock(&qdev->hw_lock);
1679}
1680
1681static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1682{
1683 struct ql_adapter *qdev = netdev_priv(ndev);
1684 u32 enable_bit = 0;
1685
1686 spin_lock(&qdev->hw_lock);
1687 if (ql_set_mac_addr_reg
1688 (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1689 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1690 }
1691 spin_unlock(&qdev->hw_lock);
1692
1693}
1694
1695/* Worker thread to process a given rx_ring that is dedicated
1696 * to outbound completions.
1697 */
1698static void ql_tx_clean(struct work_struct *work)
1699{
1700 struct rx_ring *rx_ring =
1701 container_of(work, struct rx_ring, rx_work.work);
1702 ql_clean_outbound_rx_ring(rx_ring);
1703 ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1704
1705}
1706
1707/* Worker thread to process a given rx_ring that is dedicated
1708 * to inbound completions.
1709 */
1710static void ql_rx_clean(struct work_struct *work)
1711{
1712 struct rx_ring *rx_ring =
1713 container_of(work, struct rx_ring, rx_work.work);
1714 ql_clean_inbound_rx_ring(rx_ring, 64);
1715 ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1716}
1717
1718/* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1719static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1720{
1721 struct rx_ring *rx_ring = dev_id;
1722 queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1723 &rx_ring->rx_work, 0);
1724 return IRQ_HANDLED;
1725}
1726
1727/* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1728static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1729{
1730 struct rx_ring *rx_ring = dev_id;
908a7a16 1731 netif_rx_schedule(&rx_ring->napi);
c4e84bde
RM		 1732 return IRQ_HANDLED;
1733}
1734
c4e84bde
RM		 1735/* This handles a fatal error, MPI activity, and the default
1736 * rx_ring in an MSI-X multiple vector environment.
1737 * In MSI/Legacy environment it also process the rest of
1738 * the rx_rings.
1739 */
1740static irqreturn_t qlge_isr(int irq, void *dev_id)
1741{
1742 struct rx_ring *rx_ring = dev_id;
1743 struct ql_adapter *qdev = rx_ring->qdev;
1744 struct intr_context *intr_context = &qdev->intr_context[0];
1745 u32 var;
1746 int i;
1747 int work_done = 0;
1748
bb0d215c
RM		 1749 spin_lock(&qdev->hw_lock);
1750 if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1751 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1752 spin_unlock(&qdev->hw_lock);
1753 return IRQ_NONE;
c4e84bde 1754 }
bb0d215c 1755 spin_unlock(&qdev->hw_lock);
c4e84bde 1756
bb0d215c 1757 var = ql_disable_completion_interrupt(qdev, intr_context->intr);
c4e84bde
RM		 1758
1759 /*
1760 * Check for fatal error.
1761 */
1762 if (var & STS_FE) {
1763 ql_queue_asic_error(qdev);
1764 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1765 var = ql_read32(qdev, ERR_STS);
1766 QPRINTK(qdev, INTR, ERR,
1767 "Resetting chip. Error Status Register = 0x%x\n", var);
1768 return IRQ_HANDLED;
1769 }
1770
1771 /*
1772 * Check MPI processor activity.
1773 */
1774 if (var & STS_PI) {
1775 /*
1776 * We've got an async event or mailbox completion.
1777 * Handle it and clear the source of the interrupt.
1778 */
1779 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
1780 ql_disable_completion_interrupt(qdev, intr_context->intr);
1781 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
1782 &qdev->mpi_work, 0);
1783 work_done++;
1784 }
1785
1786 /*
1787 * Check the default queue and wake handler if active.
1788 */
1789 rx_ring = &qdev->rx_ring[0];
ba7cd3ba 1790 if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
c4e84bde
RM		 1791 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
1792 ql_disable_completion_interrupt(qdev, intr_context->intr);
1793 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
1794 &rx_ring->rx_work, 0);
1795 work_done++;
1796 }
1797
1798 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
1799 /*
1800 * Start the DPC for each active queue.
1801 */
1802 for (i = 1; i < qdev->rx_ring_count; i++) {
1803 rx_ring = &qdev->rx_ring[i];
ba7cd3ba 1804 if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
c4e84bde
RM		 1805 rx_ring->cnsmr_idx) {
1806 QPRINTK(qdev, INTR, INFO,
1807 "Waking handler for rx_ring[%d].\n", i);
1808 ql_disable_completion_interrupt(qdev,
1809 intr_context->
1810 intr);
1811 if (i < qdev->rss_ring_first_cq_id)
1812 queue_delayed_work_on(rx_ring->cpu,
1813 qdev->q_workqueue,
1814 &rx_ring->rx_work,
1815 0);
1816 else
908a7a16 1817 netif_rx_schedule(&rx_ring->napi);
c4e84bde
RM		 1818 work_done++;
1819 }
1820 }
1821 }
bb0d215c 1822 ql_enable_completion_interrupt(qdev, intr_context->intr);
c4e84bde
RM		 1823 return work_done ? IRQ_HANDLED : IRQ_NONE;
1824}
1825
1826static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1827{
1828
1829 if (skb_is_gso(skb)) {
1830 int err;
1831 if (skb_header_cloned(skb)) {
1832 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1833 if (err)
1834 return err;
1835 }
1836
1837 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1838 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
1839 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1840 mac_iocb_ptr->total_hdrs_len =
1841 cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
1842 mac_iocb_ptr->net_trans_offset =
1843 cpu_to_le16(skb_network_offset(skb) |
1844 skb_transport_offset(skb)
1845 << OB_MAC_TRANSPORT_HDR_SHIFT);
1846 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
1847 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
1848 if (likely(skb->protocol == htons(ETH_P_IP))) {
1849 struct iphdr *iph = ip_hdr(skb);
1850 iph->check = 0;
1851 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1852 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1853 iph->daddr, 0,
1854 IPPROTO_TCP,
1855 0);
1856 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1857 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
1858 tcp_hdr(skb)->check =
1859 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1860 &ipv6_hdr(skb)->daddr,
1861 0, IPPROTO_TCP, 0);
1862 }
1863 return 1;
1864 }
1865 return 0;
1866}
1867
1868static void ql_hw_csum_setup(struct sk_buff *skb,
1869 struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1870{
1871 int len;
1872 struct iphdr *iph = ip_hdr(skb);
fd2df4f7 1873 __sum16 *check;
c4e84bde
RM		 1874 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1875 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1876 mac_iocb_ptr->net_trans_offset =
1877 cpu_to_le16(skb_network_offset(skb) |
1878 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
1879
1880 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1881 len = (ntohs(iph->tot_len) - (iph->ihl << 2));
1882 if (likely(iph->protocol == IPPROTO_TCP)) {
1883 check = &(tcp_hdr(skb)->check);
1884 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
1885 mac_iocb_ptr->total_hdrs_len =
1886 cpu_to_le16(skb_transport_offset(skb) +
1887 (tcp_hdr(skb)->doff << 2));
1888 } else {
1889 check = &(udp_hdr(skb)->check);
1890 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
1891 mac_iocb_ptr->total_hdrs_len =
1892 cpu_to_le16(skb_transport_offset(skb) +
1893 sizeof(struct udphdr));
1894 }
1895 *check = ~csum_tcpudp_magic(iph->saddr,
1896 iph->daddr, len, iph->protocol, 0);
1897}
1898
1899static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
1900{
1901 struct tx_ring_desc *tx_ring_desc;
1902 struct ob_mac_iocb_req *mac_iocb_ptr;
1903 struct ql_adapter *qdev = netdev_priv(ndev);
1904 int tso;
1905 struct tx_ring *tx_ring;
1906 u32 tx_ring_idx = (u32) QL_TXQ_IDX(qdev, skb);
1907
1908 tx_ring = &qdev->tx_ring[tx_ring_idx];
1909
1910 if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
1911 QPRINTK(qdev, TX_QUEUED, INFO,
1912 "%s: shutting down tx queue %d du to lack of resources.\n",
1913 __func__, tx_ring_idx);
1914 netif_stop_queue(ndev);
1915 atomic_inc(&tx_ring->queue_stopped);
1916 return NETDEV_TX_BUSY;
1917 }
1918 tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
1919 mac_iocb_ptr = tx_ring_desc->queue_entry;
1920 memset((void *)mac_iocb_ptr, 0, sizeof(mac_iocb_ptr));
1921 if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) != NETDEV_TX_OK) {
1922 QPRINTK(qdev, TX_QUEUED, ERR, "Could not map the segments.\n");
1923 return NETDEV_TX_BUSY;
1924 }
1925
1926 mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
1927 mac_iocb_ptr->tid = tx_ring_desc->index;
1928 /* We use the upper 32-bits to store the tx queue for this IO.
1929 * When we get the completion we can use it to establish the context.
1930 */
1931 mac_iocb_ptr->txq_idx = tx_ring_idx;
1932 tx_ring_desc->skb = skb;
1933
1934 mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
1935
1936 if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
1937 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
1938 vlan_tx_tag_get(skb));
1939 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
1940 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
1941 }
1942 tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1943 if (tso < 0) {
1944 dev_kfree_skb_any(skb);
1945 return NETDEV_TX_OK;
1946 } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
1947 ql_hw_csum_setup(skb,
1948 (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1949 }
1950 QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
1951 tx_ring->prod_idx++;
1952 if (tx_ring->prod_idx == tx_ring->wq_len)
1953 tx_ring->prod_idx = 0;
1954 wmb();
1955
1956 ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
1957 ndev->trans_start = jiffies;
1958 QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
1959 tx_ring->prod_idx, skb->len);
1960
1961 atomic_dec(&tx_ring->tx_count);
1962 return NETDEV_TX_OK;
1963}
1964
1965static void ql_free_shadow_space(struct ql_adapter *qdev)
1966{
1967 if (qdev->rx_ring_shadow_reg_area) {
1968 pci_free_consistent(qdev->pdev,
1969 PAGE_SIZE,
1970 qdev->rx_ring_shadow_reg_area,
1971 qdev->rx_ring_shadow_reg_dma);
1972 qdev->rx_ring_shadow_reg_area = NULL;
1973 }
1974 if (qdev->tx_ring_shadow_reg_area) {
1975 pci_free_consistent(qdev->pdev,
1976 PAGE_SIZE,
1977 qdev->tx_ring_shadow_reg_area,
1978 qdev->tx_ring_shadow_reg_dma);
1979 qdev->tx_ring_shadow_reg_area = NULL;
1980 }
1981}
1982
1983static int ql_alloc_shadow_space(struct ql_adapter *qdev)
1984{
1985 qdev->rx_ring_shadow_reg_area =
1986 pci_alloc_consistent(qdev->pdev,
1987 PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
1988 if (qdev->rx_ring_shadow_reg_area == NULL) {
1989 QPRINTK(qdev, IFUP, ERR,
1990 "Allocation of RX shadow space failed.\n");
1991 return -ENOMEM;
1992 }
1993 qdev->tx_ring_shadow_reg_area =
1994 pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
1995 &qdev->tx_ring_shadow_reg_dma);
1996 if (qdev->tx_ring_shadow_reg_area == NULL) {
1997 QPRINTK(qdev, IFUP, ERR,
1998 "Allocation of TX shadow space failed.\n");
1999 goto err_wqp_sh_area;
2000 }
2001 return 0;
2002
2003err_wqp_sh_area:
2004 pci_free_consistent(qdev->pdev,
2005 PAGE_SIZE,
2006 qdev->rx_ring_shadow_reg_area,
2007 qdev->rx_ring_shadow_reg_dma);
2008 return -ENOMEM;
2009}
2010
2011static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2012{
2013 struct tx_ring_desc *tx_ring_desc;
2014 int i;
2015 struct ob_mac_iocb_req *mac_iocb_ptr;
2016
2017 mac_iocb_ptr = tx_ring->wq_base;
2018 tx_ring_desc = tx_ring->q;
2019 for (i = 0; i < tx_ring->wq_len; i++) {
2020 tx_ring_desc->index = i;
2021 tx_ring_desc->skb = NULL;
2022 tx_ring_desc->queue_entry = mac_iocb_ptr;
2023 mac_iocb_ptr++;
2024 tx_ring_desc++;
2025 }
2026 atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2027 atomic_set(&tx_ring->queue_stopped, 0);
2028}
2029
2030static void ql_free_tx_resources(struct ql_adapter *qdev,
2031 struct tx_ring *tx_ring)
2032{
2033 if (tx_ring->wq_base) {
2034 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2035 tx_ring->wq_base, tx_ring->wq_base_dma);
2036 tx_ring->wq_base = NULL;
2037 }
2038 kfree(tx_ring->q);
2039 tx_ring->q = NULL;
2040}
2041
2042static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2043 struct tx_ring *tx_ring)
2044{
2045 tx_ring->wq_base =
2046 pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2047 &tx_ring->wq_base_dma);
2048
2049 if ((tx_ring->wq_base == NULL)
2050 || tx_ring->wq_base_dma & (tx_ring->wq_size - 1)) {
2051 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2052 return -ENOMEM;
2053 }
2054 tx_ring->q =
2055 kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2056 if (tx_ring->q == NULL)
2057 goto err;
2058
2059 return 0;
2060err:
2061 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2062 tx_ring->wq_base, tx_ring->wq_base_dma);
2063 return -ENOMEM;
2064}
2065
8668ae92 2066static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
c4e84bde
RM		 2067{
2068 int i;
2069 struct bq_desc *lbq_desc;
2070
2071 for (i = 0; i < rx_ring->lbq_len; i++) {
2072 lbq_desc = &rx_ring->lbq[i];
2073 if (lbq_desc->p.lbq_page) {
2074 pci_unmap_page(qdev->pdev,
2075 pci_unmap_addr(lbq_desc, mapaddr),
2076 pci_unmap_len(lbq_desc, maplen),
2077 PCI_DMA_FROMDEVICE);
2078
2079 put_page(lbq_desc->p.lbq_page);
2080 lbq_desc->p.lbq_page = NULL;
2081 }
c4e84bde
RM		 2082 }
2083}
2084
2085/*
2086 * Allocate and map a page for each element of the lbq.
2087 */
2088static int ql_alloc_lbq_buffers(struct ql_adapter *qdev,
2089 struct rx_ring *rx_ring)
2090{
2091 int i;
2092 struct bq_desc *lbq_desc;
2093 u64 map;
2c9a0d41 2094 __le64 *bq = rx_ring->lbq_base;
c4e84bde
RM		 2095
2096 for (i = 0; i < rx_ring->lbq_len; i++) {
2097 lbq_desc = &rx_ring->lbq[i];
2098 memset(lbq_desc, 0, sizeof(lbq_desc));
2c9a0d41 2099 lbq_desc->addr = bq;
c4e84bde
RM		 2100 lbq_desc->index = i;
2101 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
2102 if (unlikely(!lbq_desc->p.lbq_page)) {
2103 QPRINTK(qdev, IFUP, ERR, "failed alloc_page().\n");
2104 goto mem_error;
2105 } else {
2106 map = pci_map_page(qdev->pdev,
2107 lbq_desc->p.lbq_page,
2108 0, PAGE_SIZE, PCI_DMA_FROMDEVICE);
2109 if (pci_dma_mapping_error(qdev->pdev, map)) {
2110 QPRINTK(qdev, IFUP, ERR,
2111 "PCI mapping failed.\n");
2112 goto mem_error;
2113 }
2114 pci_unmap_addr_set(lbq_desc, mapaddr, map);
2115 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
2c9a0d41 2116 *lbq_desc->addr = cpu_to_le64(map);
c4e84bde
RM		 2117 }
2118 bq++;
2119 }
2120 return 0;
2121mem_error:
2122 ql_free_lbq_buffers(qdev, rx_ring);
2123 return -ENOMEM;
2124}
2125
8668ae92 2126static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
c4e84bde
RM		 2127{
2128 int i;
2129 struct bq_desc *sbq_desc;
2130
2131 for (i = 0; i < rx_ring->sbq_len; i++) {
2132 sbq_desc = &rx_ring->sbq[i];
2133 if (sbq_desc == NULL) {
2134 QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2135 return;
2136 }
2137 if (sbq_desc->p.skb) {
2138 pci_unmap_single(qdev->pdev,
2139 pci_unmap_addr(sbq_desc, mapaddr),
2140 pci_unmap_len(sbq_desc, maplen),
2141 PCI_DMA_FROMDEVICE);
2142 dev_kfree_skb(sbq_desc->p.skb);
2143 sbq_desc->p.skb = NULL;
2144 }
c4e84bde
RM		 2145 }
2146}
2147
2148/* Allocate and map an skb for each element of the sbq. */
2149static int ql_alloc_sbq_buffers(struct ql_adapter *qdev,
2150 struct rx_ring *rx_ring)
2151{
2152 int i;
2153 struct bq_desc *sbq_desc;
2154 struct sk_buff *skb;
2155 u64 map;
2c9a0d41 2156 __le64 *bq = rx_ring->sbq_base;
c4e84bde
RM		 2157
2158 for (i = 0; i < rx_ring->sbq_len; i++) {
2159 sbq_desc = &rx_ring->sbq[i];
2160 memset(sbq_desc, 0, sizeof(sbq_desc));
2161 sbq_desc->index = i;
2c9a0d41 2162 sbq_desc->addr = bq;
c4e84bde
RM		 2163 skb = netdev_alloc_skb(qdev->ndev, rx_ring->sbq_buf_size);
2164 if (unlikely(!skb)) {
2165 /* Better luck next round */
2166 QPRINTK(qdev, IFUP, ERR,
2167 "small buff alloc failed for %d bytes at index %d.\n",
2168 rx_ring->sbq_buf_size, i);
2169 goto mem_err;
2170 }
2171 skb_reserve(skb, QLGE_SB_PAD);
2172 sbq_desc->p.skb = skb;
2173 /*
2174 * Map only half the buffer. Because the
2175 * other half may get some data copied to it
2176 * when the completion arrives.
2177 */
2178 map = pci_map_single(qdev->pdev,
2179 skb->data,
2180 rx_ring->sbq_buf_size / 2,
2181 PCI_DMA_FROMDEVICE);
2182 if (pci_dma_mapping_error(qdev->pdev, map)) {
2183 QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
2184 goto mem_err;
2185 }
2186 pci_unmap_addr_set(sbq_desc, mapaddr, map);
2187 pci_unmap_len_set(sbq_desc, maplen, rx_ring->sbq_buf_size / 2);
2c9a0d41 2188 *sbq_desc->addr = cpu_to_le64(map);
c4e84bde
RM		 2189 bq++;
2190 }
2191 return 0;
2192mem_err:
2193 ql_free_sbq_buffers(qdev, rx_ring);
2194 return -ENOMEM;
2195}
2196
2197static void ql_free_rx_resources(struct ql_adapter *qdev,
2198 struct rx_ring *rx_ring)
2199{
2200 if (rx_ring->sbq_len)
2201 ql_free_sbq_buffers(qdev, rx_ring);
2202 if (rx_ring->lbq_len)
2203 ql_free_lbq_buffers(qdev, rx_ring);
2204
2205 /* Free the small buffer queue. */
2206 if (rx_ring->sbq_base) {
2207 pci_free_consistent(qdev->pdev,
2208 rx_ring->sbq_size,
2209 rx_ring->sbq_base, rx_ring->sbq_base_dma);
2210 rx_ring->sbq_base = NULL;
2211 }
2212
2213 /* Free the small buffer queue control blocks. */
2214 kfree(rx_ring->sbq);
2215 rx_ring->sbq = NULL;
2216
2217 /* Free the large buffer queue. */
2218 if (rx_ring->lbq_base) {
2219 pci_free_consistent(qdev->pdev,
2220 rx_ring->lbq_size,
2221 rx_ring->lbq_base, rx_ring->lbq_base_dma);
2222 rx_ring->lbq_base = NULL;
2223 }
2224
2225 /* Free the large buffer queue control blocks. */
2226 kfree(rx_ring->lbq);
2227 rx_ring->lbq = NULL;
2228
2229 /* Free the rx queue. */
2230 if (rx_ring->cq_base) {
2231 pci_free_consistent(qdev->pdev,
2232 rx_ring->cq_size,
2233 rx_ring->cq_base, rx_ring->cq_base_dma);
2234 rx_ring->cq_base = NULL;
2235 }
2236}
2237
2238/* Allocate queues and buffers for this completions queue based
2239 * on the values in the parameter structure. */
2240static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2241 struct rx_ring *rx_ring)
2242{
2243
2244 /*
2245 * Allocate the completion queue for this rx_ring.
2246 */
2247 rx_ring->cq_base =
2248 pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2249 &rx_ring->cq_base_dma);
2250
2251 if (rx_ring->cq_base == NULL) {
2252 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2253 return -ENOMEM;
2254 }
2255
2256 if (rx_ring->sbq_len) {
2257 /*
2258 * Allocate small buffer queue.
2259 */
2260 rx_ring->sbq_base =
2261 pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2262 &rx_ring->sbq_base_dma);
2263
2264 if (rx_ring->sbq_base == NULL) {
2265 QPRINTK(qdev, IFUP, ERR,
2266 "Small buffer queue allocation failed.\n");
2267 goto err_mem;
2268 }
2269
2270 /*
2271 * Allocate small buffer queue control blocks.
2272 */
2273 rx_ring->sbq =
2274 kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2275 GFP_KERNEL);
2276 if (rx_ring->sbq == NULL) {
2277 QPRINTK(qdev, IFUP, ERR,
2278 "Small buffer queue control block allocation failed.\n");
2279 goto err_mem;
2280 }
2281
2282 if (ql_alloc_sbq_buffers(qdev, rx_ring)) {
2283 QPRINTK(qdev, IFUP, ERR,
2284 "Small buffer allocation failed.\n");
2285 goto err_mem;
2286 }
2287 }
2288
2289 if (rx_ring->lbq_len) {
2290 /*
2291 * Allocate large buffer queue.
2292 */
2293 rx_ring->lbq_base =
2294 pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2295 &rx_ring->lbq_base_dma);
2296
2297 if (rx_ring->lbq_base == NULL) {
2298 QPRINTK(qdev, IFUP, ERR,
2299 "Large buffer queue allocation failed.\n");
2300 goto err_mem;
2301 }
2302 /*
2303 * Allocate large buffer queue control blocks.
2304 */
2305 rx_ring->lbq =
2306 kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2307 GFP_KERNEL);
2308 if (rx_ring->lbq == NULL) {
2309 QPRINTK(qdev, IFUP, ERR,
2310 "Large buffer queue control block allocation failed.\n");
2311 goto err_mem;
2312 }
2313
2314 /*
2315 * Allocate the buffers.
2316 */
2317 if (ql_alloc_lbq_buffers(qdev, rx_ring)) {
2318 QPRINTK(qdev, IFUP, ERR,
2319 "Large buffer allocation failed.\n");
2320 goto err_mem;
2321 }
2322 }
2323
2324 return 0;
2325
2326err_mem:
2327 ql_free_rx_resources(qdev, rx_ring);
2328 return -ENOMEM;
2329}
2330
2331static void ql_tx_ring_clean(struct ql_adapter *qdev)
2332{
2333 struct tx_ring *tx_ring;
2334 struct tx_ring_desc *tx_ring_desc;
2335 int i, j;
2336
2337 /*
2338 * Loop through all queues and free
2339 * any resources.
2340 */
2341 for (j = 0; j < qdev->tx_ring_count; j++) {
2342 tx_ring = &qdev->tx_ring[j];
2343 for (i = 0; i < tx_ring->wq_len; i++) {
2344 tx_ring_desc = &tx_ring->q[i];
2345 if (tx_ring_desc && tx_ring_desc->skb) {
2346 QPRINTK(qdev, IFDOWN, ERR,
2347 "Freeing lost SKB %p, from queue %d, index %d.\n",
2348 tx_ring_desc->skb, j,
2349 tx_ring_desc->index);
2350 ql_unmap_send(qdev, tx_ring_desc,
2351 tx_ring_desc->map_cnt);
2352 dev_kfree_skb(tx_ring_desc->skb);
2353 tx_ring_desc->skb = NULL;
2354 }
2355 }
2356 }
2357}
2358
2359static void ql_free_ring_cb(struct ql_adapter *qdev)
2360{
2361 kfree(qdev->ring_mem);
2362}
2363
2364static int ql_alloc_ring_cb(struct ql_adapter *qdev)
2365{
2366 /* Allocate space for tx/rx ring control blocks. */
2367 qdev->ring_mem_size =
2368 (qdev->tx_ring_count * sizeof(struct tx_ring)) +
2369 (qdev->rx_ring_count * sizeof(struct rx_ring));
2370 qdev->ring_mem = kmalloc(qdev->ring_mem_size, GFP_KERNEL);
2371 if (qdev->ring_mem == NULL) {
2372 return -ENOMEM;
2373 } else {
2374 qdev->rx_ring = qdev->ring_mem;
2375 qdev->tx_ring = qdev->ring_mem +
2376 (qdev->rx_ring_count * sizeof(struct rx_ring));
2377 }
2378 return 0;
2379}
2380
2381static void ql_free_mem_resources(struct ql_adapter *qdev)
2382{
2383 int i;
2384
2385 for (i = 0; i < qdev->tx_ring_count; i++)
2386 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2387 for (i = 0; i < qdev->rx_ring_count; i++)
2388 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2389 ql_free_shadow_space(qdev);
2390}
2391
2392static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2393{
2394 int i;
2395
2396 /* Allocate space for our shadow registers and such. */
2397 if (ql_alloc_shadow_space(qdev))
2398 return -ENOMEM;
2399
2400 for (i = 0; i < qdev->rx_ring_count; i++) {
2401 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2402 QPRINTK(qdev, IFUP, ERR,
2403 "RX resource allocation failed.\n");
2404 goto err_mem;
2405 }
2406 }
2407 /* Allocate tx queue resources */
2408 for (i = 0; i < qdev->tx_ring_count; i++) {
2409 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2410 QPRINTK(qdev, IFUP, ERR,
2411 "TX resource allocation failed.\n");
2412 goto err_mem;
2413 }
2414 }
2415 return 0;
2416
2417err_mem:
2418 ql_free_mem_resources(qdev);
2419 return -ENOMEM;
2420}
2421
2422/* Set up the rx ring control block and pass it to the chip.
2423 * The control block is defined as
2424 * "Completion Queue Initialization Control Block", or cqicb.
2425 */
2426static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2427{
2428 struct cqicb *cqicb = &rx_ring->cqicb;
2429 void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2430 (rx_ring->cq_id * sizeof(u64) * 4);
2431 u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2432 (rx_ring->cq_id * sizeof(u64) * 4);
2433 void __iomem *doorbell_area =
2434 qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2435 int err = 0;
2436 u16 bq_len;
2437
2438 /* Set up the shadow registers for this ring. */
2439 rx_ring->prod_idx_sh_reg = shadow_reg;
2440 rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2441 shadow_reg += sizeof(u64);
2442 shadow_reg_dma += sizeof(u64);
2443 rx_ring->lbq_base_indirect = shadow_reg;
2444 rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2445 shadow_reg += sizeof(u64);
2446 shadow_reg_dma += sizeof(u64);
2447 rx_ring->sbq_base_indirect = shadow_reg;
2448 rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2449
2450 /* PCI doorbell mem area + 0x00 for consumer index register */
8668ae92 2451 rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
c4e84bde
RM		 2452 rx_ring->cnsmr_idx = 0;
2453 rx_ring->curr_entry = rx_ring->cq_base;
2454
2455 /* PCI doorbell mem area + 0x04 for valid register */
2456 rx_ring->valid_db_reg = doorbell_area + 0x04;
2457
2458 /* PCI doorbell mem area + 0x18 for large buffer consumer */
8668ae92 2459 rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
c4e84bde
RM		 2460
2461 /* PCI doorbell mem area + 0x1c */
8668ae92 2462 rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
c4e84bde
RM		 2463
2464 memset((void *)cqicb, 0, sizeof(struct cqicb));
2465 cqicb->msix_vect = rx_ring->irq;
2466
459caf5a
RM		 2467 bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
2468 cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
c4e84bde 2469
97345524 2470 cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
c4e84bde 2471
97345524 2472 cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
c4e84bde
RM		 2473
2474 /*
2475 * Set up the control block load flags.
2476 */
2477 cqicb->flags = FLAGS_LC | /* Load queue base address */
2478 FLAGS_LV | /* Load MSI-X vector */
2479 FLAGS_LI; /* Load irq delay values */
2480 if (rx_ring->lbq_len) {
2481 cqicb->flags |= FLAGS_LL; /* Load lbq values */
2482 *((u64 *) rx_ring->lbq_base_indirect) = rx_ring->lbq_base_dma;
97345524
RM		 2483 cqicb->lbq_addr =
2484 cpu_to_le64(rx_ring->lbq_base_indirect_dma);
459caf5a
RM		 2485 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
2486 (u16) rx_ring->lbq_buf_size;
2487 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
2488 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
2489 (u16) rx_ring->lbq_len;
c4e84bde
RM		 2490 cqicb->lbq_len = cpu_to_le16(bq_len);
2491 rx_ring->lbq_prod_idx = rx_ring->lbq_len - 16;
2492 rx_ring->lbq_curr_idx = 0;
2493 rx_ring->lbq_clean_idx = rx_ring->lbq_prod_idx;
2494 rx_ring->lbq_free_cnt = 16;
2495 }
2496 if (rx_ring->sbq_len) {
2497 cqicb->flags |= FLAGS_LS; /* Load sbq values */
2498 *((u64 *) rx_ring->sbq_base_indirect) = rx_ring->sbq_base_dma;
97345524
RM		 2499 cqicb->sbq_addr =
2500 cpu_to_le64(rx_ring->sbq_base_indirect_dma);
c4e84bde
RM		 2501 cqicb->sbq_buf_size =
2502 cpu_to_le16(((rx_ring->sbq_buf_size / 2) + 8) & 0xfffffff8);
459caf5a
RM		 2503 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
2504 (u16) rx_ring->sbq_len;
c4e84bde
RM		 2505 cqicb->sbq_len = cpu_to_le16(bq_len);
2506 rx_ring->sbq_prod_idx = rx_ring->sbq_len - 16;
2507 rx_ring->sbq_curr_idx = 0;
2508 rx_ring->sbq_clean_idx = rx_ring->sbq_prod_idx;
2509 rx_ring->sbq_free_cnt = 16;
2510 }
2511 switch (rx_ring->type) {
2512 case TX_Q:
2513 /* If there's only one interrupt, then we use
2514 * worker threads to process the outbound
2515 * completion handling rx_rings. We do this so
2516 * they can be run on multiple CPUs. There is
2517 * room to play with this more where we would only
2518 * run in a worker if there are more than x number
2519 * of outbound completions on the queue and more
2520 * than one queue active. Some threshold that
2521 * would indicate a benefit in spite of the cost
2522 * of a context switch.
2523 * If there's more than one interrupt, then the
2524 * outbound completions are processed in the ISR.
2525 */
2526 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2527 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2528 else {
2529 /* With all debug warnings on we see a WARN_ON message
2530 * when we free the skb in the interrupt context.
2531 */
2532 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2533 }
2534 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2535 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2536 break;
2537 case DEFAULT_Q:
2538 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2539 cqicb->irq_delay = 0;
2540 cqicb->pkt_delay = 0;
2541 break;
2542 case RX_Q:
2543 /* Inbound completion handling rx_rings run in
2544 * separate NAPI contexts.
2545 */
2546 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2547 64);
2548 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2549 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2550 break;
2551 default:
2552 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2553 rx_ring->type);
2554 }
2555 QPRINTK(qdev, IFUP, INFO, "Initializing rx work queue.\n");
2556 err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2557 CFG_LCQ, rx_ring->cq_id);
2558 if (err) {
2559 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2560 return err;
2561 }
2562 QPRINTK(qdev, IFUP, INFO, "Successfully loaded CQICB.\n");
2563 /*
2564 * Advance the producer index for the buffer queues.
2565 */
2566 wmb();
2567 if (rx_ring->lbq_len)
2568 ql_write_db_reg(rx_ring->lbq_prod_idx,
2569 rx_ring->lbq_prod_idx_db_reg);
2570 if (rx_ring->sbq_len)
2571 ql_write_db_reg(rx_ring->sbq_prod_idx,
2572 rx_ring->sbq_prod_idx_db_reg);
2573 return err;
2574}
2575
2576static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2577{
2578 struct wqicb *wqicb = (struct wqicb *)tx_ring;
2579 void __iomem *doorbell_area =
2580 qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2581 void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2582 (tx_ring->wq_id * sizeof(u64));
2583 u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2584 (tx_ring->wq_id * sizeof(u64));
2585 int err = 0;
2586
2587 /*
2588 * Assign doorbell registers for this tx_ring.
2589 */
2590 /* TX PCI doorbell mem area for tx producer index */
8668ae92 2591 tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
c4e84bde
RM		 2592 tx_ring->prod_idx = 0;
2593 /* TX PCI doorbell mem area + 0x04 */
2594 tx_ring->valid_db_reg = doorbell_area + 0x04;
2595
2596 /*
2597 * Assign shadow registers for this tx_ring.
2598 */
2599 tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2600 tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2601
2602 wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2603 wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2604 Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2605 wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2606 wqicb->rid = 0;
97345524 2607 wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
c4e84bde 2608
97345524 2609 wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
c4e84bde
RM		 2610
2611 ql_init_tx_ring(qdev, tx_ring);
2612
2613 err = ql_write_cfg(qdev, wqicb, sizeof(wqicb), CFG_LRQ,
2614 (u16) tx_ring->wq_id);
2615 if (err) {
2616 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2617 return err;
2618 }
2619 QPRINTK(qdev, IFUP, INFO, "Successfully loaded WQICB.\n");
2620 return err;
2621}
2622
2623static void ql_disable_msix(struct ql_adapter *qdev)
2624{
2625 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2626 pci_disable_msix(qdev->pdev);
2627 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2628 kfree(qdev->msi_x_entry);
2629 qdev->msi_x_entry = NULL;
2630 } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2631 pci_disable_msi(qdev->pdev);
2632 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2633 }
2634}
2635
2636static void ql_enable_msix(struct ql_adapter *qdev)
2637{
2638 int i;
2639
2640 qdev->intr_count = 1;
2641 /* Get the MSIX vectors. */
2642 if (irq_type == MSIX_IRQ) {
2643 /* Try to alloc space for the msix struct,
2644 * if it fails then go to MSI/legacy.
2645 */
2646 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2647 sizeof(struct msix_entry),
2648 GFP_KERNEL);
2649 if (!qdev->msi_x_entry) {
2650 irq_type = MSI_IRQ;
2651 goto msi;
2652 }
2653
2654 for (i = 0; i < qdev->rx_ring_count; i++)
2655 qdev->msi_x_entry[i].entry = i;
2656
2657 if (!pci_enable_msix
2658 (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2659 set_bit(QL_MSIX_ENABLED, &qdev->flags);
2660 qdev->intr_count = qdev->rx_ring_count;
2661 QPRINTK(qdev, IFUP, INFO,
2662 "MSI-X Enabled, got %d vectors.\n",
2663 qdev->intr_count);
2664 return;
2665 } else {
2666 kfree(qdev->msi_x_entry);
2667 qdev->msi_x_entry = NULL;
2668 QPRINTK(qdev, IFUP, WARNING,
2669 "MSI-X Enable failed, trying MSI.\n");
2670 irq_type = MSI_IRQ;
2671 }
2672 }
2673msi:
2674 if (irq_type == MSI_IRQ) {
2675 if (!pci_enable_msi(qdev->pdev)) {
2676 set_bit(QL_MSI_ENABLED, &qdev->flags);
2677 QPRINTK(qdev, IFUP, INFO,
2678 "Running with MSI interrupts.\n");
2679 return;
2680 }
2681 }
2682 irq_type = LEG_IRQ;
c4e84bde
RM		 2683 QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2684}
2685
2686/*
2687 * Here we build the intr_context structures based on
2688 * our rx_ring count and intr vector count.
2689 * The intr_context structure is used to hook each vector
2690 * to possibly different handlers.
2691 */
2692static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2693{
2694 int i = 0;
2695 struct intr_context *intr_context = &qdev->intr_context[0];
2696
2697 ql_enable_msix(qdev);
2698
2699 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2700 /* Each rx_ring has it's
2701 * own intr_context since we have separate
2702 * vectors for each queue.
2703 * This only true when MSI-X is enabled.
2704 */
2705 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2706 qdev->rx_ring[i].irq = i;
2707 intr_context->intr = i;
2708 intr_context->qdev = qdev;
2709 /*
2710 * We set up each vectors enable/disable/read bits so
2711 * there's no bit/mask calculations in the critical path.
2712 */
2713 intr_context->intr_en_mask =
2714 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2715 INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2716 | i;
2717 intr_context->intr_dis_mask =
2718 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2719 INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2720 INTR_EN_IHD | i;
2721 intr_context->intr_read_mask =
2722 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2723 INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2724 i;
2725
2726 if (i == 0) {
2727 /*
2728 * Default queue handles bcast/mcast plus
2729 * async events. Needs buffers.
2730 */
2731 intr_context->handler = qlge_isr;
2732 sprintf(intr_context->name, "%s-default-queue",
2733 qdev->ndev->name);
2734 } else if (i < qdev->rss_ring_first_cq_id) {
2735 /*
2736 * Outbound queue is for outbound completions only.
2737 */
2738 intr_context->handler = qlge_msix_tx_isr;
c224969e 2739 sprintf(intr_context->name, "%s-tx-%d",
c4e84bde
RM		 2740 qdev->ndev->name, i);
2741 } else {
2742 /*
2743 * Inbound queues handle unicast frames only.
2744 */
2745 intr_context->handler = qlge_msix_rx_isr;
c224969e 2746 sprintf(intr_context->name, "%s-rx-%d",
c4e84bde
RM		 2747 qdev->ndev->name, i);
2748 }
2749 }
2750 } else {
2751 /*
2752 * All rx_rings use the same intr_context since
2753 * there is only one vector.
2754 */
2755 intr_context->intr = 0;
2756 intr_context->qdev = qdev;
2757 /*
2758 * We set up each vectors enable/disable/read bits so
2759 * there's no bit/mask calculations in the critical path.
2760 */
2761 intr_context->intr_en_mask =
2762 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2763 intr_context->intr_dis_mask =
2764 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2765 INTR_EN_TYPE_DISABLE;
2766 intr_context->intr_read_mask =
2767 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2768 /*
2769 * Single interrupt means one handler for all rings.
2770 */
2771 intr_context->handler = qlge_isr;
2772 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2773 for (i = 0; i < qdev->rx_ring_count; i++)
2774 qdev->rx_ring[i].irq = 0;
2775 }
2776}
2777
2778static void ql_free_irq(struct ql_adapter *qdev)
2779{
2780 int i;
2781 struct intr_context *intr_context = &qdev->intr_context[0];
2782
2783 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2784 if (intr_context->hooked) {
2785 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2786 free_irq(qdev->msi_x_entry[i].vector,
2787 &qdev->rx_ring[i]);
2788 QPRINTK(qdev, IFDOWN, ERR,
2789 "freeing msix interrupt %d.\n", i);
2790 } else {
2791 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
2792 QPRINTK(qdev, IFDOWN, ERR,
2793 "freeing msi interrupt %d.\n", i);
2794 }
2795 }
2796 }
2797 ql_disable_msix(qdev);
2798}
2799
2800static int ql_request_irq(struct ql_adapter *qdev)
2801{
2802 int i;
2803 int status = 0;
2804 struct pci_dev *pdev = qdev->pdev;
2805 struct intr_context *intr_context = &qdev->intr_context[0];
2806
2807 ql_resolve_queues_to_irqs(qdev);
2808
2809 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2810 atomic_set(&intr_context->irq_cnt, 0);
2811 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2812 status = request_irq(qdev->msi_x_entry[i].vector,
2813 intr_context->handler,
2814 0,
2815 intr_context->name,
2816 &qdev->rx_ring[i]);
2817 if (status) {
2818 QPRINTK(qdev, IFUP, ERR,
2819 "Failed request for MSIX interrupt %d.\n",
2820 i);
2821 goto err_irq;
2822 } else {
2823 QPRINTK(qdev, IFUP, INFO,
2824 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2825 i,
2826 qdev->rx_ring[i].type ==
2827 DEFAULT_Q ? "DEFAULT_Q" : "",
2828 qdev->rx_ring[i].type ==
2829 TX_Q ? "TX_Q" : "",
2830 qdev->rx_ring[i].type ==
2831 RX_Q ? "RX_Q" : "", intr_context->name);
2832 }
2833 } else {
2834 QPRINTK(qdev, IFUP, DEBUG,
2835 "trying msi or legacy interrupts.\n");
2836 QPRINTK(qdev, IFUP, DEBUG,
2837 "%s: irq = %d.\n", __func__, pdev->irq);
2838 QPRINTK(qdev, IFUP, DEBUG,
2839 "%s: context->name = %s.\n", __func__,
2840 intr_context->name);
2841 QPRINTK(qdev, IFUP, DEBUG,
2842 "%s: dev_id = 0x%p.\n", __func__,
2843 &qdev->rx_ring[0]);
2844 status =
2845 request_irq(pdev->irq, qlge_isr,
2846 test_bit(QL_MSI_ENABLED,
2847 &qdev->
2848 flags) ? 0 : IRQF_SHARED,
2849 intr_context->name, &qdev->rx_ring[0]);
2850 if (status)
2851 goto err_irq;
2852
2853 QPRINTK(qdev, IFUP, ERR,
2854 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2855 i,
2856 qdev->rx_ring[0].type ==
2857 DEFAULT_Q ? "DEFAULT_Q" : "",
2858 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
2859 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
2860 intr_context->name);
2861 }
2862 intr_context->hooked = 1;
2863 }
2864 return status;
2865err_irq:
2866 QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
2867 ql_free_irq(qdev);
2868 return status;
2869}
2870
2871static int ql_start_rss(struct ql_adapter *qdev)
2872{
2873 struct ricb *ricb = &qdev->ricb;
2874 int status = 0;
2875 int i;
2876 u8 *hash_id = (u8 *) ricb->hash_cq_id;
2877
2878 memset((void *)ricb, 0, sizeof(ricb));
2879
2880 ricb->base_cq = qdev->rss_ring_first_cq_id | RSS_L4K;
2881 ricb->flags =
2882 (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
2883 RSS_RT6);
2884 ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
2885
2886 /*
2887 * Fill out the Indirection Table.
2888 */
2889 for (i = 0; i < 32; i++)
2890 hash_id[i] = i & 1;
2891
2892 /*
2893 * Random values for the IPv6 and IPv4 Hash Keys.
2894 */
2895 get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
2896 get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
2897
2898 QPRINTK(qdev, IFUP, INFO, "Initializing RSS.\n");
2899
2900 status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
2901 if (status) {
2902 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
2903 return status;
2904 }
2905 QPRINTK(qdev, IFUP, INFO, "Successfully loaded RICB.\n");
2906 return status;
2907}
2908
2909/* Initialize the frame-to-queue routing. */
2910static int ql_route_initialize(struct ql_adapter *qdev)
2911{
2912 int status = 0;
2913 int i;
2914
2915 /* Clear all the entries in the routing table. */
2916 for (i = 0; i < 16; i++) {
2917 status = ql_set_routing_reg(qdev, i, 0, 0);
2918 if (status) {
2919 QPRINTK(qdev, IFUP, ERR,
2920 "Failed to init routing register for CAM packets.\n");
2921 return status;
2922 }
2923 }
2924
2925 status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
2926 if (status) {
2927 QPRINTK(qdev, IFUP, ERR,
2928 "Failed to init routing register for error packets.\n");
2929 return status;
2930 }
2931 status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
2932 if (status) {
2933 QPRINTK(qdev, IFUP, ERR,
2934 "Failed to init routing register for broadcast packets.\n");
2935 return status;
2936 }
2937 /* If we have more than one inbound queue, then turn on RSS in the
2938 * routing block.
2939 */
2940 if (qdev->rss_ring_count > 1) {
2941 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
2942 RT_IDX_RSS_MATCH, 1);
2943 if (status) {
2944 QPRINTK(qdev, IFUP, ERR,
2945 "Failed to init routing register for MATCH RSS packets.\n");
2946 return status;
2947 }
2948 }
2949
2950 status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
2951 RT_IDX_CAM_HIT, 1);
2952 if (status) {
2953 QPRINTK(qdev, IFUP, ERR,
2954 "Failed to init routing register for CAM packets.\n");
2955 return status;
2956 }
2957 return status;
2958}
2959
2960static int ql_adapter_initialize(struct ql_adapter *qdev)
2961{
2962 u32 value, mask;
2963 int i;
2964 int status = 0;
2965
2966 /*
2967 * Set up the System register to halt on errors.
2968 */
2969 value = SYS_EFE | SYS_FAE;
2970 mask = value << 16;
2971 ql_write32(qdev, SYS, mask | value);
2972
2973 /* Set the default queue. */
2974 value = NIC_RCV_CFG_DFQ;
2975 mask = NIC_RCV_CFG_DFQ_MASK;
2976 ql_write32(qdev, NIC_RCV_CFG, (mask | value));
2977
2978 /* Set the MPI interrupt to enabled. */
2979 ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
2980
2981 /* Enable the function, set pagesize, enable error checking. */
2982 value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
2983 FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
2984
2985 /* Set/clear header splitting. */
2986 mask = FSC_VM_PAGESIZE_MASK |
2987 FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
2988 ql_write32(qdev, FSC, mask | value);
2989
2990 ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
2991 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
2992
2993 /* Start up the rx queues. */
2994 for (i = 0; i < qdev->rx_ring_count; i++) {
2995 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
2996 if (status) {
2997 QPRINTK(qdev, IFUP, ERR,
2998 "Failed to start rx ring[%d].\n", i);
2999 return status;
3000 }
3001 }
3002
3003 /* If there is more than one inbound completion queue
3004 * then download a RICB to configure RSS.
3005 */
3006 if (qdev->rss_ring_count > 1) {
3007 status = ql_start_rss(qdev);
3008 if (status) {
3009 QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
3010 return status;
3011 }
3012 }
3013
3014 /* Start up the tx queues. */
3015 for (i = 0; i < qdev->tx_ring_count; i++) {
3016 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3017 if (status) {
3018 QPRINTK(qdev, IFUP, ERR,
3019 "Failed to start tx ring[%d].\n", i);
3020 return status;
3021 }
3022 }
3023
3024 status = ql_port_initialize(qdev);
3025 if (status) {
3026 QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3027 return status;
3028 }
3029
3030 status = ql_set_mac_addr_reg(qdev, (u8 *) qdev->ndev->perm_addr,
3031 MAC_ADDR_TYPE_CAM_MAC, qdev->func);
3032 if (status) {
3033 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
3034 return status;
3035 }
3036
3037 status = ql_route_initialize(qdev);
3038 if (status) {
3039 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
3040 return status;
3041 }
3042
3043 /* Start NAPI for the RSS queues. */
3044 for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
3045 QPRINTK(qdev, IFUP, INFO, "Enabling NAPI for rx_ring[%d].\n",
3046 i);
3047 napi_enable(&qdev->rx_ring[i].napi);
3048 }
3049
3050 return status;
3051}
3052
3053/* Issue soft reset to chip. */
3054static int ql_adapter_reset(struct ql_adapter *qdev)
3055{
3056 u32 value;
3057 int max_wait_time;
3058 int status = 0;
3059 int resetCnt = 0;
3060
3061#define MAX_RESET_CNT 1
3062issueReset:
3063 resetCnt++;
3064 QPRINTK(qdev, IFDOWN, DEBUG, "Issue soft reset to chip.\n");
3065 ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3066 /* Wait for reset to complete. */
3067 max_wait_time = 3;
3068 QPRINTK(qdev, IFDOWN, DEBUG, "Wait %d seconds for reset to complete.\n",
3069 max_wait_time);
3070 do {
3071 value = ql_read32(qdev, RST_FO);
3072 if ((value & RST_FO_FR) == 0)
3073 break;
3074
3075 ssleep(1);
3076 } while ((--max_wait_time));
3077 if (value & RST_FO_FR) {
3078 QPRINTK(qdev, IFDOWN, ERR,
3079 "Stuck in SoftReset: FSC_SR:0x%08x\n", value);
3080 if (resetCnt < MAX_RESET_CNT)
3081 goto issueReset;
3082 }
3083 if (max_wait_time == 0) {
3084 status = -ETIMEDOUT;
3085 QPRINTK(qdev, IFDOWN, ERR,
3086 "ETIMEOUT!!! errored out of resetting the chip!\n");
3087 }
3088
3089 return status;
3090}
3091
3092static void ql_display_dev_info(struct net_device *ndev)
3093{
3094 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3095
3096 QPRINTK(qdev, PROBE, INFO,
3097 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3098 "XG Roll = %d, XG Rev = %d.\n",
3099 qdev->func,
3100 qdev->chip_rev_id & 0x0000000f,
3101 qdev->chip_rev_id >> 4 & 0x0000000f,
3102 qdev->chip_rev_id >> 8 & 0x0000000f,
3103 qdev->chip_rev_id >> 12 & 0x0000000f);
7c510e4b 3104 QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
c4e84bde
RM		 3105}
3106
3107static int ql_adapter_down(struct ql_adapter *qdev)
3108{
3109 struct net_device *ndev = qdev->ndev;
3110 int i, status = 0;
3111 struct rx_ring *rx_ring;
3112
3113 netif_stop_queue(ndev);
3114 netif_carrier_off(ndev);
3115
3116 cancel_delayed_work_sync(&qdev->asic_reset_work);
3117 cancel_delayed_work_sync(&qdev->mpi_reset_work);
3118 cancel_delayed_work_sync(&qdev->mpi_work);
3119
3120 /* The default queue at index 0 is always processed in
3121 * a workqueue.
3122 */
3123 cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3124
3125 /* The rest of the rx_rings are processed in
3126 * a workqueue only if it's a single interrupt
3127 * environment (MSI/Legacy).
3128 */
c062076c 3129 for (i = 1; i < qdev->rx_ring_count; i++) {
c4e84bde
RM		 3130 rx_ring = &qdev->rx_ring[i];
3131 /* Only the RSS rings use NAPI on multi irq
3132 * environment. Outbound completion processing
3133 * is done in interrupt context.
3134 */
3135 if (i >= qdev->rss_ring_first_cq_id) {
3136 napi_disable(&rx_ring->napi);
3137 } else {
3138 cancel_delayed_work_sync(&rx_ring->rx_work);
3139 }
3140 }
3141
3142 clear_bit(QL_ADAPTER_UP, &qdev->flags);
3143
3144 ql_disable_interrupts(qdev);
3145
3146 ql_tx_ring_clean(qdev);
3147
3148 spin_lock(&qdev->hw_lock);
3149 status = ql_adapter_reset(qdev);
3150 if (status)
3151 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3152 qdev->func);
3153 spin_unlock(&qdev->hw_lock);
3154 return status;
3155}
3156
3157static int ql_adapter_up(struct ql_adapter *qdev)
3158{
3159 int err = 0;
3160
3161 spin_lock(&qdev->hw_lock);
3162 err = ql_adapter_initialize(qdev);
3163 if (err) {
3164 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3165 spin_unlock(&qdev->hw_lock);
3166 goto err_init;
3167 }
3168 spin_unlock(&qdev->hw_lock);
3169 set_bit(QL_ADAPTER_UP, &qdev->flags);
3170 ql_enable_interrupts(qdev);
3171 ql_enable_all_completion_interrupts(qdev);
3172 if ((ql_read32(qdev, STS) & qdev->port_init)) {
3173 netif_carrier_on(qdev->ndev);
3174 netif_start_queue(qdev->ndev);
3175 }
3176
3177 return 0;
3178err_init:
3179 ql_adapter_reset(qdev);
3180 return err;
3181}
3182
3183static int ql_cycle_adapter(struct ql_adapter *qdev)
3184{
3185 int status;
3186
3187 status = ql_adapter_down(qdev);
3188 if (status)
3189 goto error;
3190
3191 status = ql_adapter_up(qdev);
3192 if (status)
3193 goto error;
3194
3195 return status;
3196error:
3197 QPRINTK(qdev, IFUP, ALERT,
3198 "Driver up/down cycle failed, closing device\n");
3199 rtnl_lock();
3200 dev_close(qdev->ndev);
3201 rtnl_unlock();
3202 return status;
3203}
3204
3205static void ql_release_adapter_resources(struct ql_adapter *qdev)
3206{
3207 ql_free_mem_resources(qdev);
3208 ql_free_irq(qdev);
3209}
3210
3211static int ql_get_adapter_resources(struct ql_adapter *qdev)
3212{
3213 int status = 0;
3214
3215 if (ql_alloc_mem_resources(qdev)) {
3216 QPRINTK(qdev, IFUP, ERR, "Unable to allocate memory.\n");
3217 return -ENOMEM;
3218 }
3219 status = ql_request_irq(qdev);
3220 if (status)
3221 goto err_irq;
3222 return status;
3223err_irq:
3224 ql_free_mem_resources(qdev);
3225 return status;
3226}
3227
3228static int qlge_close(struct net_device *ndev)
3229{
3230 struct ql_adapter *qdev = netdev_priv(ndev);
3231
3232 /*
3233 * Wait for device to recover from a reset.
3234 * (Rarely happens, but possible.)
3235 */
3236 while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3237 msleep(1);
3238 ql_adapter_down(qdev);
3239 ql_release_adapter_resources(qdev);
3240 ql_free_ring_cb(qdev);
3241 return 0;
3242}
3243
3244static int ql_configure_rings(struct ql_adapter *qdev)
3245{
3246 int i;
3247 struct rx_ring *rx_ring;
3248 struct tx_ring *tx_ring;
3249 int cpu_cnt = num_online_cpus();
3250
3251 /*
3252 * For each processor present we allocate one
3253 * rx_ring for outbound completions, and one
3254 * rx_ring for inbound completions. Plus there is
3255 * always the one default queue. For the CPU
3256 * counts we end up with the following rx_rings:
3257 * rx_ring count =
3258 * one default queue +
3259 * (CPU count * outbound completion rx_ring) +
3260 * (CPU count * inbound (RSS) completion rx_ring)
3261 * To keep it simple we limit the total number of
3262 * queues to < 32, so we truncate CPU to 8.
3263 * This limitation can be removed when requested.
3264 */
3265
3266 if (cpu_cnt > 8)
3267 cpu_cnt = 8;
3268
3269 /*
3270 * rx_ring[0] is always the default queue.
3271 */
3272 /* Allocate outbound completion ring for each CPU. */
3273 qdev->tx_ring_count = cpu_cnt;
3274 /* Allocate inbound completion (RSS) ring for each CPU. */
3275 qdev->rss_ring_count = cpu_cnt;
3276 /* cq_id for the first inbound ring handler. */
3277 qdev->rss_ring_first_cq_id = cpu_cnt + 1;
3278 /*
3279 * qdev->rx_ring_count:
3280 * Total number of rx_rings. This includes the one
3281 * default queue, a number of outbound completion
3282 * handler rx_rings, and the number of inbound
3283 * completion handler rx_rings.
3284 */
3285 qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1;
3286
3287 if (ql_alloc_ring_cb(qdev))
3288 return -ENOMEM;
3289
3290 for (i = 0; i < qdev->tx_ring_count; i++) {
3291 tx_ring = &qdev->tx_ring[i];
3292 memset((void *)tx_ring, 0, sizeof(tx_ring));
3293 tx_ring->qdev = qdev;
3294 tx_ring->wq_id = i;
3295 tx_ring->wq_len = qdev->tx_ring_size;
3296 tx_ring->wq_size =
3297 tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3298
3299 /*
3300 * The completion queue ID for the tx rings start
3301 * immediately after the default Q ID, which is zero.
3302 */
3303 tx_ring->cq_id = i + 1;
3304 }
3305
3306 for (i = 0; i < qdev->rx_ring_count; i++) {
3307 rx_ring = &qdev->rx_ring[i];
3308 memset((void *)rx_ring, 0, sizeof(rx_ring));
3309 rx_ring->qdev = qdev;
3310 rx_ring->cq_id = i;
3311 rx_ring->cpu = i % cpu_cnt; /* CPU to run handler on. */
3312 if (i == 0) { /* Default queue at index 0. */
3313 /*
3314 * Default queue handles bcast/mcast plus
3315 * async events. Needs buffers.
3316 */
3317 rx_ring->cq_len = qdev->rx_ring_size;
3318 rx_ring->cq_size =
3319 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3320 rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3321 rx_ring->lbq_size =
2c9a0d41 3322 rx_ring->lbq_len * sizeof(__le64);
c4e84bde
RM		 3323 rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3324 rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3325 rx_ring->sbq_size =
2c9a0d41 3326 rx_ring->sbq_len * sizeof(__le64);
c4e84bde
RM		 3327 rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3328 rx_ring->type = DEFAULT_Q;
3329 } else if (i < qdev->rss_ring_first_cq_id) {
3330 /*
3331 * Outbound queue handles outbound completions only.
3332 */
3333 /* outbound cq is same size as tx_ring it services. */
3334 rx_ring->cq_len = qdev->tx_ring_size;
3335 rx_ring->cq_size =
3336 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3337 rx_ring->lbq_len = 0;
3338 rx_ring->lbq_size = 0;
3339 rx_ring->lbq_buf_size = 0;
3340 rx_ring->sbq_len = 0;
3341 rx_ring->sbq_size = 0;
3342 rx_ring->sbq_buf_size = 0;
3343 rx_ring->type = TX_Q;
3344 } else { /* Inbound completions (RSS) queues */
3345 /*
3346 * Inbound queues handle unicast frames only.
3347 */
3348 rx_ring->cq_len = qdev->rx_ring_size;
3349 rx_ring->cq_size =
3350 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3351 rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3352 rx_ring->lbq_size =
2c9a0d41 3353 rx_ring->lbq_len * sizeof(__le64);
c4e84bde
RM		 3354 rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3355 rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3356 rx_ring->sbq_size =
2c9a0d41 3357 rx_ring->sbq_len * sizeof(__le64);
c4e84bde
RM		 3358 rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3359 rx_ring->type = RX_Q;
3360 }
3361 }
3362 return 0;
3363}
3364
3365static int qlge_open(struct net_device *ndev)
3366{
3367 int err = 0;
3368 struct ql_adapter *qdev = netdev_priv(ndev);
3369
3370 err = ql_configure_rings(qdev);
3371 if (err)
3372 return err;
3373
3374 err = ql_get_adapter_resources(qdev);
3375 if (err)
3376 goto error_up;
3377
3378 err = ql_adapter_up(qdev);
3379 if (err)
3380 goto error_up;
3381
3382 return err;
3383
3384error_up:
3385 ql_release_adapter_resources(qdev);
3386 ql_free_ring_cb(qdev);
3387 return err;
3388}
3389
3390static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3391{
3392 struct ql_adapter *qdev = netdev_priv(ndev);
3393
3394 if (ndev->mtu == 1500 && new_mtu == 9000) {
3395 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3396 } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3397 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3398 } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3399 (ndev->mtu == 9000 && new_mtu == 9000)) {
3400 return 0;
3401 } else
3402 return -EINVAL;
3403 ndev->mtu = new_mtu;
3404 return 0;
3405}
3406
3407static struct net_device_stats *qlge_get_stats(struct net_device
3408 *ndev)
3409{
3410 struct ql_adapter *qdev = netdev_priv(ndev);
3411 return &qdev->stats;
3412}
3413
3414static void qlge_set_multicast_list(struct net_device *ndev)
3415{
3416 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3417 struct dev_mc_list *mc_ptr;
3418 int i;
3419
3420 spin_lock(&qdev->hw_lock);
3421 /*
3422 * Set or clear promiscuous mode if a
3423 * transition is taking place.
3424 */
3425 if (ndev->flags & IFF_PROMISC) {
3426 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3427 if (ql_set_routing_reg
3428 (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3429 QPRINTK(qdev, HW, ERR,
3430 "Failed to set promiscous mode.\n");
3431 } else {
3432 set_bit(QL_PROMISCUOUS, &qdev->flags);
3433 }
3434 }
3435 } else {
3436 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3437 if (ql_set_routing_reg
3438 (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3439 QPRINTK(qdev, HW, ERR,
3440 "Failed to clear promiscous mode.\n");
3441 } else {
3442 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3443 }
3444 }
3445 }
3446
3447 /*
3448 * Set or clear all multicast mode if a
3449 * transition is taking place.
3450 */
3451 if ((ndev->flags & IFF_ALLMULTI) ||
3452 (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3453 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3454 if (ql_set_routing_reg
3455 (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3456 QPRINTK(qdev, HW, ERR,
3457 "Failed to set all-multi mode.\n");
3458 } else {
3459 set_bit(QL_ALLMULTI, &qdev->flags);
3460 }
3461 }
3462 } else {
3463 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3464 if (ql_set_routing_reg
3465 (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3466 QPRINTK(qdev, HW, ERR,
3467 "Failed to clear all-multi mode.\n");
3468 } else {
3469 clear_bit(QL_ALLMULTI, &qdev->flags);
3470 }
3471 }
3472 }
3473
3474 if (ndev->mc_count) {
3475 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3476 i++, mc_ptr = mc_ptr->next)
3477 if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3478 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3479 QPRINTK(qdev, HW, ERR,
3480 "Failed to loadmulticast address.\n");
3481 goto exit;
3482 }
3483 if (ql_set_routing_reg
3484 (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3485 QPRINTK(qdev, HW, ERR,
3486 "Failed to set multicast match mode.\n");
3487 } else {
3488 set_bit(QL_ALLMULTI, &qdev->flags);
3489 }
3490 }
3491exit:
3492 spin_unlock(&qdev->hw_lock);
3493}
3494
3495static int qlge_set_mac_address(struct net_device *ndev, void *p)
3496{
3497 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3498 struct sockaddr *addr = p;
8668ae92 3499 int ret = 0;
c4e84bde
RM		 3500
3501 if (netif_running(ndev))
3502 return -EBUSY;
3503
3504 if (!is_valid_ether_addr(addr->sa_data))
3505 return -EADDRNOTAVAIL;
3506 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3507
3508 spin_lock(&qdev->hw_lock);
3509 if (ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3510 MAC_ADDR_TYPE_CAM_MAC, qdev->func)) {/* Unicast */
3511 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
8668ae92 3512 ret = -1;
c4e84bde
RM		 3513 }
3514 spin_unlock(&qdev->hw_lock);
3515
8668ae92 3516 return ret;
c4e84bde
RM		 3517}
3518
3519static void qlge_tx_timeout(struct net_device *ndev)
3520{
3521 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3522 queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
3523}
3524
3525static void ql_asic_reset_work(struct work_struct *work)
3526{
3527 struct ql_adapter *qdev =
3528 container_of(work, struct ql_adapter, asic_reset_work.work);
3529 ql_cycle_adapter(qdev);
3530}
3531
3532static void ql_get_board_info(struct ql_adapter *qdev)
3533{
3534 qdev->func =
3535 (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3536 if (qdev->func) {
3537 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3538 qdev->port_link_up = STS_PL1;
3539 qdev->port_init = STS_PI1;
3540 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3541 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3542 } else {
3543 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3544 qdev->port_link_up = STS_PL0;
3545 qdev->port_init = STS_PI0;
3546 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3547 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3548 }
3549 qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3550}
3551
3552static void ql_release_all(struct pci_dev *pdev)
3553{
3554 struct net_device *ndev = pci_get_drvdata(pdev);
3555 struct ql_adapter *qdev = netdev_priv(ndev);
3556
3557 if (qdev->workqueue) {
3558 destroy_workqueue(qdev->workqueue);
3559 qdev->workqueue = NULL;
3560 }
3561 if (qdev->q_workqueue) {
3562 destroy_workqueue(qdev->q_workqueue);
3563 qdev->q_workqueue = NULL;
3564 }
3565 if (qdev->reg_base)
8668ae92 3566 iounmap(qdev->reg_base);
c4e84bde
RM		 3567 if (qdev->doorbell_area)
3568 iounmap(qdev->doorbell_area);
3569 pci_release_regions(pdev);
3570 pci_set_drvdata(pdev, NULL);
3571}
3572
3573static int __devinit ql_init_device(struct pci_dev *pdev,
3574 struct net_device *ndev, int cards_found)
3575{
3576 struct ql_adapter *qdev = netdev_priv(ndev);
3577 int pos, err = 0;
3578 u16 val16;
3579
3580 memset((void *)qdev, 0, sizeof(qdev));
3581 err = pci_enable_device(pdev);
3582 if (err) {
3583 dev_err(&pdev->dev, "PCI device enable failed.\n");
3584 return err;
3585 }
3586
3587 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3588 if (pos <= 0) {
3589 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3590 "aborting.\n");
3591 goto err_out;
3592 } else {
3593 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3594 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3595 val16 |= (PCI_EXP_DEVCTL_CERE |
3596 PCI_EXP_DEVCTL_NFERE |
3597 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3598 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3599 }
3600
3601 err = pci_request_regions(pdev, DRV_NAME);
3602 if (err) {
3603 dev_err(&pdev->dev, "PCI region request failed.\n");
3604 goto err_out;
3605 }
3606
3607 pci_set_master(pdev);
3608 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3609 set_bit(QL_DMA64, &qdev->flags);
3610 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3611 } else {
3612 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3613 if (!err)
3614 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3615 }
3616
3617 if (err) {
3618 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3619 goto err_out;
3620 }
3621
3622 pci_set_drvdata(pdev, ndev);
3623 qdev->reg_base =
3624 ioremap_nocache(pci_resource_start(pdev, 1),
3625 pci_resource_len(pdev, 1));
3626 if (!qdev->reg_base) {
3627 dev_err(&pdev->dev, "Register mapping failed.\n");
3628 err = -ENOMEM;
3629 goto err_out;
3630 }
3631
3632 qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3633 qdev->doorbell_area =
3634 ioremap_nocache(pci_resource_start(pdev, 3),
3635 pci_resource_len(pdev, 3));
3636 if (!qdev->doorbell_area) {
3637 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3638 err = -ENOMEM;
3639 goto err_out;
3640 }
3641
3642 ql_get_board_info(qdev);
3643 qdev->ndev = ndev;
3644 qdev->pdev = pdev;
3645 qdev->msg_enable = netif_msg_init(debug, default_msg);
3646 spin_lock_init(&qdev->hw_lock);
3647 spin_lock_init(&qdev->stats_lock);
3648
3649 /* make sure the EEPROM is good */
3650 err = ql_get_flash_params(qdev);
3651 if (err) {
3652 dev_err(&pdev->dev, "Invalid FLASH.\n");
3653 goto err_out;
3654 }
3655
3656 if (!is_valid_ether_addr(qdev->flash.mac_addr))
3657 goto err_out;
3658
3659 memcpy(ndev->dev_addr, qdev->flash.mac_addr, ndev->addr_len);
3660 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3661
3662 /* Set up the default ring sizes. */
3663 qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3664 qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3665
3666 /* Set up the coalescing parameters. */
3667 qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3668 qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3669 qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3670 qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3671
3672 /*
3673 * Set up the operating parameters.
3674 */
3675 qdev->rx_csum = 1;
3676
3677 qdev->q_workqueue = create_workqueue(ndev->name);
3678 qdev->workqueue = create_singlethread_workqueue(ndev->name);
3679 INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3680 INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3681 INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3682
3683 if (!cards_found) {
3684 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3685 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3686 DRV_NAME, DRV_VERSION);
3687 }
3688 return 0;
3689err_out:
3690 ql_release_all(pdev);
3691 pci_disable_device(pdev);
3692 return err;
3693}
3694
25ed7849
SH		 3695
3696static const struct net_device_ops qlge_netdev_ops = {
3697 .ndo_open = qlge_open,
3698 .ndo_stop = qlge_close,
3699 .ndo_start_xmit = qlge_send,
3700 .ndo_change_mtu = qlge_change_mtu,
3701 .ndo_get_stats = qlge_get_stats,
3702 .ndo_set_multicast_list = qlge_set_multicast_list,
3703 .ndo_set_mac_address = qlge_set_mac_address,
3704 .ndo_validate_addr = eth_validate_addr,
3705 .ndo_tx_timeout = qlge_tx_timeout,
3706 .ndo_vlan_rx_register = ql_vlan_rx_register,
3707 .ndo_vlan_rx_add_vid = ql_vlan_rx_add_vid,
3708 .ndo_vlan_rx_kill_vid = ql_vlan_rx_kill_vid,
3709};
3710
c4e84bde
RM		 3711static int __devinit qlge_probe(struct pci_dev *pdev,
3712 const struct pci_device_id *pci_entry)
3713{
3714 struct net_device *ndev = NULL;
3715 struct ql_adapter *qdev = NULL;
3716 static int cards_found = 0;
3717 int err = 0;
3718
3719 ndev = alloc_etherdev(sizeof(struct ql_adapter));
3720 if (!ndev)
3721 return -ENOMEM;
3722
3723 err = ql_init_device(pdev, ndev, cards_found);
3724 if (err < 0) {
3725 free_netdev(ndev);
3726 return err;
3727 }
3728
3729 qdev = netdev_priv(ndev);
3730 SET_NETDEV_DEV(ndev, &pdev->dev);
3731 ndev->features = (0
3732 | NETIF_F_IP_CSUM
3733 | NETIF_F_SG
3734 | NETIF_F_TSO
3735 | NETIF_F_TSO6
3736 | NETIF_F_TSO_ECN
3737 | NETIF_F_HW_VLAN_TX
3738 | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3739
3740 if (test_bit(QL_DMA64, &qdev->flags))
3741 ndev->features |= NETIF_F_HIGHDMA;
3742
3743 /*
3744 * Set up net_device structure.
3745 */
3746 ndev->tx_queue_len = qdev->tx_ring_size;
3747 ndev->irq = pdev->irq;
25ed7849
SH		 3748
3749 ndev->netdev_ops = &qlge_netdev_ops;
c4e84bde 3750 SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
c4e84bde 3751 ndev->watchdog_timeo = 10 * HZ;
25ed7849 3752
c4e84bde
RM		 3753 err = register_netdev(ndev);
3754 if (err) {
3755 dev_err(&pdev->dev, "net device registration failed.\n");
3756 ql_release_all(pdev);
3757 pci_disable_device(pdev);
3758 return err;
3759 }
3760 netif_carrier_off(ndev);
3761 netif_stop_queue(ndev);
3762 ql_display_dev_info(ndev);
3763 cards_found++;
3764 return 0;
3765}
3766
3767static void __devexit qlge_remove(struct pci_dev *pdev)
3768{
3769 struct net_device *ndev = pci_get_drvdata(pdev);
3770 unregister_netdev(ndev);
3771 ql_release_all(pdev);
3772 pci_disable_device(pdev);
3773 free_netdev(ndev);
3774}
3775
3776/*
3777 * This callback is called by the PCI subsystem whenever
3778 * a PCI bus error is detected.
3779 */
3780static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
3781 enum pci_channel_state state)
3782{
3783 struct net_device *ndev = pci_get_drvdata(pdev);
3784 struct ql_adapter *qdev = netdev_priv(ndev);
3785
3786 if (netif_running(ndev))
3787 ql_adapter_down(qdev);
3788
3789 pci_disable_device(pdev);
3790
3791 /* Request a slot reset. */
3792 return PCI_ERS_RESULT_NEED_RESET;
3793}
3794
3795/*
3796 * This callback is called after the PCI buss has been reset.
3797 * Basically, this tries to restart the card from scratch.
3798 * This is a shortened version of the device probe/discovery code,
3799 * it resembles the first-half of the () routine.
3800 */
3801static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
3802{
3803 struct net_device *ndev = pci_get_drvdata(pdev);
3804 struct ql_adapter *qdev = netdev_priv(ndev);
3805
3806 if (pci_enable_device(pdev)) {
3807 QPRINTK(qdev, IFUP, ERR,
3808 "Cannot re-enable PCI device after reset.\n");
3809 return PCI_ERS_RESULT_DISCONNECT;
3810 }
3811
3812 pci_set_master(pdev);
3813
3814 netif_carrier_off(ndev);
3815 netif_stop_queue(ndev);
3816 ql_adapter_reset(qdev);
3817
3818 /* Make sure the EEPROM is good */
3819 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3820
3821 if (!is_valid_ether_addr(ndev->perm_addr)) {
3822 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
3823 return PCI_ERS_RESULT_DISCONNECT;
3824 }
3825
3826 return PCI_ERS_RESULT_RECOVERED;
3827}
3828
3829static void qlge_io_resume(struct pci_dev *pdev)
3830{
3831 struct net_device *ndev = pci_get_drvdata(pdev);
3832 struct ql_adapter *qdev = netdev_priv(ndev);
3833
3834 pci_set_master(pdev);
3835
3836 if (netif_running(ndev)) {
3837 if (ql_adapter_up(qdev)) {
3838 QPRINTK(qdev, IFUP, ERR,
3839 "Device initialization failed after reset.\n");
3840 return;
3841 }
3842 }
3843
3844 netif_device_attach(ndev);
3845}
3846
3847static struct pci_error_handlers qlge_err_handler = {
3848 .error_detected = qlge_io_error_detected,
3849 .slot_reset = qlge_io_slot_reset,
3850 .resume = qlge_io_resume,
3851};
3852
3853static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
3854{
3855 struct net_device *ndev = pci_get_drvdata(pdev);
3856 struct ql_adapter *qdev = netdev_priv(ndev);
3857 int err;
3858
3859 netif_device_detach(ndev);
3860
3861 if (netif_running(ndev)) {
3862 err = ql_adapter_down(qdev);
3863 if (!err)
3864 return err;
3865 }
3866
3867 err = pci_save_state(pdev);
3868 if (err)
3869 return err;
3870
3871 pci_disable_device(pdev);
3872
3873 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3874
3875 return 0;
3876}
3877
04da2cf9 3878#ifdef CONFIG_PM
c4e84bde
RM		 3879static int qlge_resume(struct pci_dev *pdev)
3880{
3881 struct net_device *ndev = pci_get_drvdata(pdev);
3882 struct ql_adapter *qdev = netdev_priv(ndev);
3883 int err;
3884
3885 pci_set_power_state(pdev, PCI_D0);
3886 pci_restore_state(pdev);
3887 err = pci_enable_device(pdev);
3888 if (err) {
3889 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
3890 return err;
3891 }
3892 pci_set_master(pdev);
3893
3894 pci_enable_wake(pdev, PCI_D3hot, 0);
3895 pci_enable_wake(pdev, PCI_D3cold, 0);
3896
3897 if (netif_running(ndev)) {
3898 err = ql_adapter_up(qdev);
3899 if (err)
3900 return err;
3901 }
3902
3903 netif_device_attach(ndev);
3904
3905 return 0;
3906}
04da2cf9 3907#endif /* CONFIG_PM */
c4e84bde
RM		 3908
3909static void qlge_shutdown(struct pci_dev *pdev)
3910{
3911 qlge_suspend(pdev, PMSG_SUSPEND);
3912}
3913
3914static struct pci_driver qlge_driver = {
3915 .name = DRV_NAME,
3916 .id_table = qlge_pci_tbl,
3917 .probe = qlge_probe,
3918 .remove = __devexit_p(qlge_remove),
3919#ifdef CONFIG_PM
3920 .suspend = qlge_suspend,
3921 .resume = qlge_resume,
3922#endif
3923 .shutdown = qlge_shutdown,
3924 .err_handler = &qlge_err_handler
3925};
3926
3927static int __init qlge_init_module(void)
3928{
3929 return pci_register_driver(&qlge_driver);
3930}
3931
3932static void __exit qlge_exit(void)
3933{
3934 pci_unregister_driver(&qlge_driver);
3935}
3936
3937module_init(qlge_init_module);
3938module_exit(qlge_exit);
kernel source for telekom puls (alcatel/mediatek)