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qlge: bugfix: Fix ring length setting for rx ring, large/small
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / qlge / qlge_main.c
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c4e84bde
RM		 1/*
2 * QLogic qlge NIC HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 * See LICENSE.qlge for copyright and licensing details.
5 * Author: Linux qlge network device driver by
6 * Ron Mercer <ron.mercer@qlogic.com>
7 */
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/types.h>
11#include <linux/module.h>
12#include <linux/list.h>
13#include <linux/pci.h>
14#include <linux/dma-mapping.h>
15#include <linux/pagemap.h>
16#include <linux/sched.h>
17#include <linux/slab.h>
18#include <linux/dmapool.h>
19#include <linux/mempool.h>
20#include <linux/spinlock.h>
21#include <linux/kthread.h>
22#include <linux/interrupt.h>
23#include <linux/errno.h>
24#include <linux/ioport.h>
25#include <linux/in.h>
26#include <linux/ip.h>
27#include <linux/ipv6.h>
28#include <net/ipv6.h>
29#include <linux/tcp.h>
30#include <linux/udp.h>
31#include <linux/if_arp.h>
32#include <linux/if_ether.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/skbuff.h>
37#include <linux/rtnetlink.h>
38#include <linux/if_vlan.h>
c4e84bde
RM		 39#include <linux/delay.h>
40#include <linux/mm.h>
41#include <linux/vmalloc.h>
b7c6bfb7 42#include <net/ip6_checksum.h>
c4e84bde
RM		 43
44#include "qlge.h"
45
46char qlge_driver_name[] = DRV_NAME;
47const char qlge_driver_version[] = DRV_VERSION;
48
49MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
50MODULE_DESCRIPTION(DRV_STRING " ");
51MODULE_LICENSE("GPL");
52MODULE_VERSION(DRV_VERSION);
53
54static const u32 default_msg =
55 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
56/* NETIF_MSG_TIMER | */
57 NETIF_MSG_IFDOWN |
58 NETIF_MSG_IFUP |
59 NETIF_MSG_RX_ERR |
60 NETIF_MSG_TX_ERR |
61 NETIF_MSG_TX_QUEUED |
62 NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS |
63/* NETIF_MSG_PKTDATA | */
64 NETIF_MSG_HW | NETIF_MSG_WOL | 0;
65
66static int debug = 0x00007fff; /* defaults above */
67module_param(debug, int, 0);
68MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
69
70#define MSIX_IRQ 0
71#define MSI_IRQ 1
72#define LEG_IRQ 2
73static int irq_type = MSIX_IRQ;
74module_param(irq_type, int, MSIX_IRQ);
75MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
76
77static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
78 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID)},
79 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID1)},
80 /* required last entry */
81 {0,}
82};
83
84MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
85
86/* This hardware semaphore causes exclusive access to
87 * resources shared between the NIC driver, MPI firmware,
88 * FCOE firmware and the FC driver.
89 */
90static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
91{
92 u32 sem_bits = 0;
93
94 switch (sem_mask) {
95 case SEM_XGMAC0_MASK:
96 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
97 break;
98 case SEM_XGMAC1_MASK:
99 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
100 break;
101 case SEM_ICB_MASK:
102 sem_bits = SEM_SET << SEM_ICB_SHIFT;
103 break;
104 case SEM_MAC_ADDR_MASK:
105 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
106 break;
107 case SEM_FLASH_MASK:
108 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
109 break;
110 case SEM_PROBE_MASK:
111 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
112 break;
113 case SEM_RT_IDX_MASK:
114 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
115 break;
116 case SEM_PROC_REG_MASK:
117 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
118 break;
119 default:
120 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
121 return -EINVAL;
122 }
123
124 ql_write32(qdev, SEM, sem_bits | sem_mask);
125 return !(ql_read32(qdev, SEM) & sem_bits);
126}
127
128int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
129{
130 unsigned int seconds = 3;
131 do {
132 if (!ql_sem_trylock(qdev, sem_mask))
133 return 0;
134 ssleep(1);
135 } while (--seconds);
136 return -ETIMEDOUT;
137}
138
139void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
140{
141 ql_write32(qdev, SEM, sem_mask);
142 ql_read32(qdev, SEM); /* flush */
143}
144
145/* This function waits for a specific bit to come ready
146 * in a given register. It is used mostly by the initialize
147 * process, but is also used in kernel thread API such as
148 * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
149 */
150int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
151{
152 u32 temp;
153 int count = UDELAY_COUNT;
154
155 while (count) {
156 temp = ql_read32(qdev, reg);
157
158 /* check for errors */
159 if (temp & err_bit) {
160 QPRINTK(qdev, PROBE, ALERT,
161 "register 0x%.08x access error, value = 0x%.08x!.\n",
162 reg, temp);
163 return -EIO;
164 } else if (temp & bit)
165 return 0;
166 udelay(UDELAY_DELAY);
167 count--;
168 }
169 QPRINTK(qdev, PROBE, ALERT,
170 "Timed out waiting for reg %x to come ready.\n", reg);
171 return -ETIMEDOUT;
172}
173
174/* The CFG register is used to download TX and RX control blocks
175 * to the chip. This function waits for an operation to complete.
176 */
177static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
178{
179 int count = UDELAY_COUNT;
180 u32 temp;
181
182 while (count) {
183 temp = ql_read32(qdev, CFG);
184 if (temp & CFG_LE)
185 return -EIO;
186 if (!(temp & bit))
187 return 0;
188 udelay(UDELAY_DELAY);
189 count--;
190 }
191 return -ETIMEDOUT;
192}
193
194
195/* Used to issue init control blocks to hw. Maps control block,
196 * sets address, triggers download, waits for completion.
197 */
198int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
199 u16 q_id)
200{
201 u64 map;
202 int status = 0;
203 int direction;
204 u32 mask;
205 u32 value;
206
207 direction =
208 (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
209 PCI_DMA_FROMDEVICE;
210
211 map = pci_map_single(qdev->pdev, ptr, size, direction);
212 if (pci_dma_mapping_error(qdev->pdev, map)) {
213 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
214 return -ENOMEM;
215 }
216
217 status = ql_wait_cfg(qdev, bit);
218 if (status) {
219 QPRINTK(qdev, IFUP, ERR,
220 "Timed out waiting for CFG to come ready.\n");
221 goto exit;
222 }
223
224 status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
225 if (status)
226 goto exit;
227 ql_write32(qdev, ICB_L, (u32) map);
228 ql_write32(qdev, ICB_H, (u32) (map >> 32));
229 ql_sem_unlock(qdev, SEM_ICB_MASK); /* does flush too */
230
231 mask = CFG_Q_MASK | (bit << 16);
232 value = bit | (q_id << CFG_Q_SHIFT);
233 ql_write32(qdev, CFG, (mask | value));
234
235 /*
236 * Wait for the bit to clear after signaling hw.
237 */
238 status = ql_wait_cfg(qdev, bit);
239exit:
240 pci_unmap_single(qdev->pdev, map, size, direction);
241 return status;
242}
243
244/* Get a specific MAC address from the CAM. Used for debug and reg dump. */
245int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
246 u32 *value)
247{
248 u32 offset = 0;
249 int status;
250
251 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
252 if (status)
253 return status;
254 switch (type) {
255 case MAC_ADDR_TYPE_MULTI_MAC:
256 case MAC_ADDR_TYPE_CAM_MAC:
257 {
258 status =
259 ql_wait_reg_rdy(qdev,
260 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
261 if (status)
262 goto exit;
263 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
264 (index << MAC_ADDR_IDX_SHIFT) | /* index */
265 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
266 status =
267 ql_wait_reg_rdy(qdev,
268 MAC_ADDR_IDX, MAC_ADDR_MR, MAC_ADDR_E);
269 if (status)
270 goto exit;
271 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
272 status =
273 ql_wait_reg_rdy(qdev,
274 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
275 if (status)
276 goto exit;
277 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
278 (index << MAC_ADDR_IDX_SHIFT) | /* index */
279 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
280 status =
281 ql_wait_reg_rdy(qdev,
282 MAC_ADDR_IDX, MAC_ADDR_MR, MAC_ADDR_E);
283 if (status)
284 goto exit;
285 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
286 if (type == MAC_ADDR_TYPE_CAM_MAC) {
287 status =
288 ql_wait_reg_rdy(qdev,
289 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
290 if (status)
291 goto exit;
292 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
293 (index << MAC_ADDR_IDX_SHIFT) | /* index */
294 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
295 status =
296 ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
297 MAC_ADDR_MR, MAC_ADDR_E);
298 if (status)
299 goto exit;
300 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
301 }
302 break;
303 }
304 case MAC_ADDR_TYPE_VLAN:
305 case MAC_ADDR_TYPE_MULTI_FLTR:
306 default:
307 QPRINTK(qdev, IFUP, CRIT,
308 "Address type %d not yet supported.\n", type);
309 status = -EPERM;
310 }
311exit:
312 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
313 return status;
314}
315
316/* Set up a MAC, multicast or VLAN address for the
317 * inbound frame matching.
318 */
319static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
320 u16 index)
321{
322 u32 offset = 0;
323 int status = 0;
324
325 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
326 if (status)
327 return status;
328 switch (type) {
329 case MAC_ADDR_TYPE_MULTI_MAC:
330 case MAC_ADDR_TYPE_CAM_MAC:
331 {
332 u32 cam_output;
333 u32 upper = (addr[0] << 8) | addr[1];
334 u32 lower =
335 (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
336 (addr[5]);
337
338 QPRINTK(qdev, IFUP, INFO,
7c510e4b 339 "Adding %s address %pM"
c4e84bde
RM		 340 " at index %d in the CAM.\n",
341 ((type ==
342 MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
7c510e4b 343 "UNICAST"), addr, index);
c4e84bde
RM		 344
345 status =
346 ql_wait_reg_rdy(qdev,
347 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
348 if (status)
349 goto exit;
350 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
351 (index << MAC_ADDR_IDX_SHIFT) | /* index */
352 type); /* type */
353 ql_write32(qdev, MAC_ADDR_DATA, lower);
354 status =
355 ql_wait_reg_rdy(qdev,
356 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
357 if (status)
358 goto exit;
359 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
360 (index << MAC_ADDR_IDX_SHIFT) | /* index */
361 type); /* type */
362 ql_write32(qdev, MAC_ADDR_DATA, upper);
363 status =
364 ql_wait_reg_rdy(qdev,
365 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
366 if (status)
367 goto exit;
368 ql_write32(qdev, MAC_ADDR_IDX, (offset) | /* offset */
369 (index << MAC_ADDR_IDX_SHIFT) | /* index */
370 type); /* type */
371 /* This field should also include the queue id
372 and possibly the function id. Right now we hardcode
373 the route field to NIC core.
374 */
375 if (type == MAC_ADDR_TYPE_CAM_MAC) {
376 cam_output = (CAM_OUT_ROUTE_NIC |
377 (qdev->
378 func << CAM_OUT_FUNC_SHIFT) |
379 (qdev->
380 rss_ring_first_cq_id <<
381 CAM_OUT_CQ_ID_SHIFT));
382 if (qdev->vlgrp)
383 cam_output |= CAM_OUT_RV;
384 /* route to NIC core */
385 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
386 }
387 break;
388 }
389 case MAC_ADDR_TYPE_VLAN:
390 {
391 u32 enable_bit = *((u32 *) &addr[0]);
392 /* For VLAN, the addr actually holds a bit that
393 * either enables or disables the vlan id we are
394 * addressing. It's either MAC_ADDR_E on or off.
395 * That's bit-27 we're talking about.
396 */
397 QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
398 (enable_bit ? "Adding" : "Removing"),
399 index, (enable_bit ? "to" : "from"));
400
401 status =
402 ql_wait_reg_rdy(qdev,
403 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
404 if (status)
405 goto exit;
406 ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
407 (index << MAC_ADDR_IDX_SHIFT) | /* index */
408 type | /* type */
409 enable_bit); /* enable/disable */
410 break;
411 }
412 case MAC_ADDR_TYPE_MULTI_FLTR:
413 default:
414 QPRINTK(qdev, IFUP, CRIT,
415 "Address type %d not yet supported.\n", type);
416 status = -EPERM;
417 }
418exit:
419 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
420 return status;
421}
422
423/* Get a specific frame routing value from the CAM.
424 * Used for debug and reg dump.
425 */
426int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
427{
428 int status = 0;
429
430 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
431 if (status)
432 goto exit;
433
434 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, RT_IDX_E);
435 if (status)
436 goto exit;
437
438 ql_write32(qdev, RT_IDX,
439 RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
440 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, RT_IDX_E);
441 if (status)
442 goto exit;
443 *value = ql_read32(qdev, RT_DATA);
444exit:
445 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
446 return status;
447}
448
449/* The NIC function for this chip has 16 routing indexes. Each one can be used
450 * to route different frame types to various inbound queues. We send broadcast/
451 * multicast/error frames to the default queue for slow handling,
452 * and CAM hit/RSS frames to the fast handling queues.
453 */
454static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
455 int enable)
456{
457 int status;
458 u32 value = 0;
459
460 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
461 if (status)
462 return status;
463
464 QPRINTK(qdev, IFUP, DEBUG,
465 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
466 (enable ? "Adding" : "Removing"),
467 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
468 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
469 ((index ==
470 RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
471 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
472 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
473 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
474 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
475 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
476 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
477 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
478 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
479 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
480 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
481 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
482 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
483 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
484 (enable ? "to" : "from"));
485
486 switch (mask) {
487 case RT_IDX_CAM_HIT:
488 {
489 value = RT_IDX_DST_CAM_Q | /* dest */
490 RT_IDX_TYPE_NICQ | /* type */
491 (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
492 break;
493 }
494 case RT_IDX_VALID: /* Promiscuous Mode frames. */
495 {
496 value = RT_IDX_DST_DFLT_Q | /* dest */
497 RT_IDX_TYPE_NICQ | /* type */
498 (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
499 break;
500 }
501 case RT_IDX_ERR: /* Pass up MAC,IP,TCP/UDP error frames. */
502 {
503 value = RT_IDX_DST_DFLT_Q | /* dest */
504 RT_IDX_TYPE_NICQ | /* type */
505 (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
506 break;
507 }
508 case RT_IDX_BCAST: /* Pass up Broadcast frames to default Q. */
509 {
510 value = RT_IDX_DST_DFLT_Q | /* dest */
511 RT_IDX_TYPE_NICQ | /* type */
512 (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
513 break;
514 }
515 case RT_IDX_MCAST: /* Pass up All Multicast frames. */
516 {
517 value = RT_IDX_DST_CAM_Q | /* dest */
518 RT_IDX_TYPE_NICQ | /* type */
519 (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
520 break;
521 }
522 case RT_IDX_MCAST_MATCH: /* Pass up matched Multicast frames. */
523 {
524 value = RT_IDX_DST_CAM_Q | /* dest */
525 RT_IDX_TYPE_NICQ | /* type */
526 (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
527 break;
528 }
529 case RT_IDX_RSS_MATCH: /* Pass up matched RSS frames. */
530 {
531 value = RT_IDX_DST_RSS | /* dest */
532 RT_IDX_TYPE_NICQ | /* type */
533 (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
534 break;
535 }
536 case 0: /* Clear the E-bit on an entry. */
537 {
538 value = RT_IDX_DST_DFLT_Q | /* dest */
539 RT_IDX_TYPE_NICQ | /* type */
540 (index << RT_IDX_IDX_SHIFT);/* index */
541 break;
542 }
543 default:
544 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
545 mask);
546 status = -EPERM;
547 goto exit;
548 }
549
550 if (value) {
551 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
552 if (status)
553 goto exit;
554 value |= (enable ? RT_IDX_E : 0);
555 ql_write32(qdev, RT_IDX, value);
556 ql_write32(qdev, RT_DATA, enable ? mask : 0);
557 }
558exit:
559 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
560 return status;
561}
562
563static void ql_enable_interrupts(struct ql_adapter *qdev)
564{
565 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
566}
567
568static void ql_disable_interrupts(struct ql_adapter *qdev)
569{
570 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
571}
572
573/* If we're running with multiple MSI-X vectors then we enable on the fly.
574 * Otherwise, we may have multiple outstanding workers and don't want to
575 * enable until the last one finishes. In this case, the irq_cnt gets
576 * incremented everytime we queue a worker and decremented everytime
577 * a worker finishes. Once it hits zero we enable the interrupt.
578 */
bb0d215c 579u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
c4e84bde 580{
bb0d215c
RM		 581 u32 var = 0;
582 unsigned long hw_flags = 0;
583 struct intr_context *ctx = qdev->intr_context + intr;
584
585 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
586 /* Always enable if we're MSIX multi interrupts and
587 * it's not the default (zeroeth) interrupt.
588 */
c4e84bde 589 ql_write32(qdev, INTR_EN,
bb0d215c
RM		 590 ctx->intr_en_mask);
591 var = ql_read32(qdev, STS);
592 return var;
c4e84bde 593 }
bb0d215c
RM		 594
595 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
596 if (atomic_dec_and_test(&ctx->irq_cnt)) {
597 ql_write32(qdev, INTR_EN,
598 ctx->intr_en_mask);
599 var = ql_read32(qdev, STS);
600 }
601 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
602 return var;
c4e84bde
RM		 603}
604
605static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
606{
607 u32 var = 0;
bb0d215c
RM		 608 unsigned long hw_flags;
609 struct intr_context *ctx;
c4e84bde 610
bb0d215c
RM		 611 /* HW disables for us if we're MSIX multi interrupts and
612 * it's not the default (zeroeth) interrupt.
613 */
614 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
615 return 0;
616
617 ctx = qdev->intr_context + intr;
618 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
619 if (!atomic_read(&ctx->irq_cnt)) {
c4e84bde 620 ql_write32(qdev, INTR_EN,
bb0d215c 621 ctx->intr_dis_mask);
c4e84bde
RM		 622 var = ql_read32(qdev, STS);
623 }
bb0d215c
RM		 624 atomic_inc(&ctx->irq_cnt);
625 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
c4e84bde
RM		 626 return var;
627}
628
629static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
630{
631 int i;
632 for (i = 0; i < qdev->intr_count; i++) {
633 /* The enable call does a atomic_dec_and_test
634 * and enables only if the result is zero.
635 * So we precharge it here.
636 */
bb0d215c
RM		 637 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
638 i == 0))
639 atomic_set(&qdev->intr_context[i].irq_cnt, 1);
c4e84bde
RM		 640 ql_enable_completion_interrupt(qdev, i);
641 }
642
643}
644
8668ae92 645static int ql_read_flash_word(struct ql_adapter *qdev, int offset, u32 *data)
c4e84bde
RM		 646{
647 int status = 0;
648 /* wait for reg to come ready */
649 status = ql_wait_reg_rdy(qdev,
650 FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
651 if (status)
652 goto exit;
653 /* set up for reg read */
654 ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
655 /* wait for reg to come ready */
656 status = ql_wait_reg_rdy(qdev,
657 FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
658 if (status)
659 goto exit;
660 /* get the data */
661 *data = ql_read32(qdev, FLASH_DATA);
662exit:
663 return status;
664}
665
666static int ql_get_flash_params(struct ql_adapter *qdev)
667{
668 int i;
669 int status;
670 u32 *p = (u32 *)&qdev->flash;
671
672 if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
673 return -ETIMEDOUT;
674
675 for (i = 0; i < sizeof(qdev->flash) / sizeof(u32); i++, p++) {
676 status = ql_read_flash_word(qdev, i, p);
677 if (status) {
678 QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
679 goto exit;
680 }
681
682 }
683exit:
684 ql_sem_unlock(qdev, SEM_FLASH_MASK);
685 return status;
686}
687
688/* xgmac register are located behind the xgmac_addr and xgmac_data
689 * register pair. Each read/write requires us to wait for the ready
690 * bit before reading/writing the data.
691 */
692static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
693{
694 int status;
695 /* wait for reg to come ready */
696 status = ql_wait_reg_rdy(qdev,
697 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
698 if (status)
699 return status;
700 /* write the data to the data reg */
701 ql_write32(qdev, XGMAC_DATA, data);
702 /* trigger the write */
703 ql_write32(qdev, XGMAC_ADDR, reg);
704 return status;
705}
706
707/* xgmac register are located behind the xgmac_addr and xgmac_data
708 * register pair. Each read/write requires us to wait for the ready
709 * bit before reading/writing the data.
710 */
711int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
712{
713 int status = 0;
714 /* wait for reg to come ready */
715 status = ql_wait_reg_rdy(qdev,
716 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
717 if (status)
718 goto exit;
719 /* set up for reg read */
720 ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
721 /* wait for reg to come ready */
722 status = ql_wait_reg_rdy(qdev,
723 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
724 if (status)
725 goto exit;
726 /* get the data */
727 *data = ql_read32(qdev, XGMAC_DATA);
728exit:
729 return status;
730}
731
732/* This is used for reading the 64-bit statistics regs. */
733int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
734{
735 int status = 0;
736 u32 hi = 0;
737 u32 lo = 0;
738
739 status = ql_read_xgmac_reg(qdev, reg, &lo);
740 if (status)
741 goto exit;
742
743 status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
744 if (status)
745 goto exit;
746
747 *data = (u64) lo | ((u64) hi << 32);
748
749exit:
750 return status;
751}
752
753/* Take the MAC Core out of reset.
754 * Enable statistics counting.
755 * Take the transmitter/receiver out of reset.
756 * This functionality may be done in the MPI firmware at a
757 * later date.
758 */
759static int ql_port_initialize(struct ql_adapter *qdev)
760{
761 int status = 0;
762 u32 data;
763
764 if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
765 /* Another function has the semaphore, so
766 * wait for the port init bit to come ready.
767 */
768 QPRINTK(qdev, LINK, INFO,
769 "Another function has the semaphore, so wait for the port init bit to come ready.\n");
770 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
771 if (status) {
772 QPRINTK(qdev, LINK, CRIT,
773 "Port initialize timed out.\n");
774 }
775 return status;
776 }
777
778 QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
779 /* Set the core reset. */
780 status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
781 if (status)
782 goto end;
783 data |= GLOBAL_CFG_RESET;
784 status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
785 if (status)
786 goto end;
787
788 /* Clear the core reset and turn on jumbo for receiver. */
789 data &= ~GLOBAL_CFG_RESET; /* Clear core reset. */
790 data |= GLOBAL_CFG_JUMBO; /* Turn on jumbo. */
791 data |= GLOBAL_CFG_TX_STAT_EN;
792 data |= GLOBAL_CFG_RX_STAT_EN;
793 status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
794 if (status)
795 goto end;
796
797 /* Enable transmitter, and clear it's reset. */
798 status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
799 if (status)
800 goto end;
801 data &= ~TX_CFG_RESET; /* Clear the TX MAC reset. */
802 data |= TX_CFG_EN; /* Enable the transmitter. */
803 status = ql_write_xgmac_reg(qdev, TX_CFG, data);
804 if (status)
805 goto end;
806
807 /* Enable receiver and clear it's reset. */
808 status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
809 if (status)
810 goto end;
811 data &= ~RX_CFG_RESET; /* Clear the RX MAC reset. */
812 data |= RX_CFG_EN; /* Enable the receiver. */
813 status = ql_write_xgmac_reg(qdev, RX_CFG, data);
814 if (status)
815 goto end;
816
817 /* Turn on jumbo. */
818 status =
819 ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
820 if (status)
821 goto end;
822 status =
823 ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
824 if (status)
825 goto end;
826
827 /* Signal to the world that the port is enabled. */
828 ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
829end:
830 ql_sem_unlock(qdev, qdev->xg_sem_mask);
831 return status;
832}
833
834/* Get the next large buffer. */
8668ae92 835static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
c4e84bde
RM		 836{
837 struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
838 rx_ring->lbq_curr_idx++;
839 if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
840 rx_ring->lbq_curr_idx = 0;
841 rx_ring->lbq_free_cnt++;
842 return lbq_desc;
843}
844
845/* Get the next small buffer. */
8668ae92 846static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
c4e84bde
RM		 847{
848 struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
849 rx_ring->sbq_curr_idx++;
850 if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
851 rx_ring->sbq_curr_idx = 0;
852 rx_ring->sbq_free_cnt++;
853 return sbq_desc;
854}
855
856/* Update an rx ring index. */
857static void ql_update_cq(struct rx_ring *rx_ring)
858{
859 rx_ring->cnsmr_idx++;
860 rx_ring->curr_entry++;
861 if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
862 rx_ring->cnsmr_idx = 0;
863 rx_ring->curr_entry = rx_ring->cq_base;
864 }
865}
866
867static void ql_write_cq_idx(struct rx_ring *rx_ring)
868{
869 ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
870}
871
872/* Process (refill) a large buffer queue. */
873static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
874{
875 int clean_idx = rx_ring->lbq_clean_idx;
876 struct bq_desc *lbq_desc;
877 struct bq_element *bq;
878 u64 map;
879 int i;
880
881 while (rx_ring->lbq_free_cnt > 16) {
882 for (i = 0; i < 16; i++) {
883 QPRINTK(qdev, RX_STATUS, DEBUG,
884 "lbq: try cleaning clean_idx = %d.\n",
885 clean_idx);
886 lbq_desc = &rx_ring->lbq[clean_idx];
887 bq = lbq_desc->bq;
888 if (lbq_desc->p.lbq_page == NULL) {
889 QPRINTK(qdev, RX_STATUS, DEBUG,
890 "lbq: getting new page for index %d.\n",
891 lbq_desc->index);
892 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
893 if (lbq_desc->p.lbq_page == NULL) {
894 QPRINTK(qdev, RX_STATUS, ERR,
895 "Couldn't get a page.\n");
896 return;
897 }
898 map = pci_map_page(qdev->pdev,
899 lbq_desc->p.lbq_page,
900 0, PAGE_SIZE,
901 PCI_DMA_FROMDEVICE);
902 if (pci_dma_mapping_error(qdev->pdev, map)) {
903 QPRINTK(qdev, RX_STATUS, ERR,
904 "PCI mapping failed.\n");
905 return;
906 }
907 pci_unmap_addr_set(lbq_desc, mapaddr, map);
908 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
909 bq->addr_lo = /*lbq_desc->addr_lo = */
910 cpu_to_le32(map);
911 bq->addr_hi = /*lbq_desc->addr_hi = */
912 cpu_to_le32(map >> 32);
913 }
914 clean_idx++;
915 if (clean_idx == rx_ring->lbq_len)
916 clean_idx = 0;
917 }
918
919 rx_ring->lbq_clean_idx = clean_idx;
920 rx_ring->lbq_prod_idx += 16;
921 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
922 rx_ring->lbq_prod_idx = 0;
923 QPRINTK(qdev, RX_STATUS, DEBUG,
924 "lbq: updating prod idx = %d.\n",
925 rx_ring->lbq_prod_idx);
926 ql_write_db_reg(rx_ring->lbq_prod_idx,
927 rx_ring->lbq_prod_idx_db_reg);
928 rx_ring->lbq_free_cnt -= 16;
929 }
930}
931
932/* Process (refill) a small buffer queue. */
933static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
934{
935 int clean_idx = rx_ring->sbq_clean_idx;
936 struct bq_desc *sbq_desc;
937 struct bq_element *bq;
938 u64 map;
939 int i;
940
941 while (rx_ring->sbq_free_cnt > 16) {
942 for (i = 0; i < 16; i++) {
943 sbq_desc = &rx_ring->sbq[clean_idx];
944 QPRINTK(qdev, RX_STATUS, DEBUG,
945 "sbq: try cleaning clean_idx = %d.\n",
946 clean_idx);
947 bq = sbq_desc->bq;
948 if (sbq_desc->p.skb == NULL) {
949 QPRINTK(qdev, RX_STATUS, DEBUG,
950 "sbq: getting new skb for index %d.\n",
951 sbq_desc->index);
952 sbq_desc->p.skb =
953 netdev_alloc_skb(qdev->ndev,
954 rx_ring->sbq_buf_size);
955 if (sbq_desc->p.skb == NULL) {
956 QPRINTK(qdev, PROBE, ERR,
957 "Couldn't get an skb.\n");
958 rx_ring->sbq_clean_idx = clean_idx;
959 return;
960 }
961 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
962 map = pci_map_single(qdev->pdev,
963 sbq_desc->p.skb->data,
964 rx_ring->sbq_buf_size /
965 2, PCI_DMA_FROMDEVICE);
c907a35a
RM		 966 if (pci_dma_mapping_error(qdev->pdev, map)) {
967 QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
968 rx_ring->sbq_clean_idx = clean_idx;
969 return;
970 }
c4e84bde
RM		 971 pci_unmap_addr_set(sbq_desc, mapaddr, map);
972 pci_unmap_len_set(sbq_desc, maplen,
973 rx_ring->sbq_buf_size / 2);
974 bq->addr_lo = cpu_to_le32(map);
975 bq->addr_hi = cpu_to_le32(map >> 32);
976 }
977
978 clean_idx++;
979 if (clean_idx == rx_ring->sbq_len)
980 clean_idx = 0;
981 }
982 rx_ring->sbq_clean_idx = clean_idx;
983 rx_ring->sbq_prod_idx += 16;
984 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
985 rx_ring->sbq_prod_idx = 0;
986 QPRINTK(qdev, RX_STATUS, DEBUG,
987 "sbq: updating prod idx = %d.\n",
988 rx_ring->sbq_prod_idx);
989 ql_write_db_reg(rx_ring->sbq_prod_idx,
990 rx_ring->sbq_prod_idx_db_reg);
991
992 rx_ring->sbq_free_cnt -= 16;
993 }
994}
995
996static void ql_update_buffer_queues(struct ql_adapter *qdev,
997 struct rx_ring *rx_ring)
998{
999 ql_update_sbq(qdev, rx_ring);
1000 ql_update_lbq(qdev, rx_ring);
1001}
1002
1003/* Unmaps tx buffers. Can be called from send() if a pci mapping
1004 * fails at some stage, or from the interrupt when a tx completes.
1005 */
1006static void ql_unmap_send(struct ql_adapter *qdev,
1007 struct tx_ring_desc *tx_ring_desc, int mapped)
1008{
1009 int i;
1010 for (i = 0; i < mapped; i++) {
1011 if (i == 0 || (i == 7 && mapped > 7)) {
1012 /*
1013 * Unmap the skb->data area, or the
1014 * external sglist (AKA the Outbound
1015 * Address List (OAL)).
1016 * If its the zeroeth element, then it's
1017 * the skb->data area. If it's the 7th
1018 * element and there is more than 6 frags,
1019 * then its an OAL.
1020 */
1021 if (i == 7) {
1022 QPRINTK(qdev, TX_DONE, DEBUG,
1023 "unmapping OAL area.\n");
1024 }
1025 pci_unmap_single(qdev->pdev,
1026 pci_unmap_addr(&tx_ring_desc->map[i],
1027 mapaddr),
1028 pci_unmap_len(&tx_ring_desc->map[i],
1029 maplen),
1030 PCI_DMA_TODEVICE);
1031 } else {
1032 QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1033 i);
1034 pci_unmap_page(qdev->pdev,
1035 pci_unmap_addr(&tx_ring_desc->map[i],
1036 mapaddr),
1037 pci_unmap_len(&tx_ring_desc->map[i],
1038 maplen), PCI_DMA_TODEVICE);
1039 }
1040 }
1041
1042}
1043
1044/* Map the buffers for this transmit. This will return
1045 * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1046 */
1047static int ql_map_send(struct ql_adapter *qdev,
1048 struct ob_mac_iocb_req *mac_iocb_ptr,
1049 struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1050{
1051 int len = skb_headlen(skb);
1052 dma_addr_t map;
1053 int frag_idx, err, map_idx = 0;
1054 struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1055 int frag_cnt = skb_shinfo(skb)->nr_frags;
1056
1057 if (frag_cnt) {
1058 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1059 }
1060 /*
1061 * Map the skb buffer first.
1062 */
1063 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1064
1065 err = pci_dma_mapping_error(qdev->pdev, map);
1066 if (err) {
1067 QPRINTK(qdev, TX_QUEUED, ERR,
1068 "PCI mapping failed with error: %d\n", err);
1069
1070 return NETDEV_TX_BUSY;
1071 }
1072
1073 tbd->len = cpu_to_le32(len);
1074 tbd->addr = cpu_to_le64(map);
1075 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1076 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1077 map_idx++;
1078
1079 /*
1080 * This loop fills the remainder of the 8 address descriptors
1081 * in the IOCB. If there are more than 7 fragments, then the
1082 * eighth address desc will point to an external list (OAL).
1083 * When this happens, the remainder of the frags will be stored
1084 * in this list.
1085 */
1086 for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1087 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1088 tbd++;
1089 if (frag_idx == 6 && frag_cnt > 7) {
1090 /* Let's tack on an sglist.
1091 * Our control block will now
1092 * look like this:
1093 * iocb->seg[0] = skb->data
1094 * iocb->seg[1] = frag[0]
1095 * iocb->seg[2] = frag[1]
1096 * iocb->seg[3] = frag[2]
1097 * iocb->seg[4] = frag[3]
1098 * iocb->seg[5] = frag[4]
1099 * iocb->seg[6] = frag[5]
1100 * iocb->seg[7] = ptr to OAL (external sglist)
1101 * oal->seg[0] = frag[6]
1102 * oal->seg[1] = frag[7]
1103 * oal->seg[2] = frag[8]
1104 * oal->seg[3] = frag[9]
1105 * oal->seg[4] = frag[10]
1106 * etc...
1107 */
1108 /* Tack on the OAL in the eighth segment of IOCB. */
1109 map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1110 sizeof(struct oal),
1111 PCI_DMA_TODEVICE);
1112 err = pci_dma_mapping_error(qdev->pdev, map);
1113 if (err) {
1114 QPRINTK(qdev, TX_QUEUED, ERR,
1115 "PCI mapping outbound address list with error: %d\n",
1116 err);
1117 goto map_error;
1118 }
1119
1120 tbd->addr = cpu_to_le64(map);
1121 /*
1122 * The length is the number of fragments
1123 * that remain to be mapped times the length
1124 * of our sglist (OAL).
1125 */
1126 tbd->len =
1127 cpu_to_le32((sizeof(struct tx_buf_desc) *
1128 (frag_cnt - frag_idx)) | TX_DESC_C);
1129 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1130 map);
1131 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1132 sizeof(struct oal));
1133 tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1134 map_idx++;
1135 }
1136
1137 map =
1138 pci_map_page(qdev->pdev, frag->page,
1139 frag->page_offset, frag->size,
1140 PCI_DMA_TODEVICE);
1141
1142 err = pci_dma_mapping_error(qdev->pdev, map);
1143 if (err) {
1144 QPRINTK(qdev, TX_QUEUED, ERR,
1145 "PCI mapping frags failed with error: %d.\n",
1146 err);
1147 goto map_error;
1148 }
1149
1150 tbd->addr = cpu_to_le64(map);
1151 tbd->len = cpu_to_le32(frag->size);
1152 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1153 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1154 frag->size);
1155
1156 }
1157 /* Save the number of segments we've mapped. */
1158 tx_ring_desc->map_cnt = map_idx;
1159 /* Terminate the last segment. */
1160 tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1161 return NETDEV_TX_OK;
1162
1163map_error:
1164 /*
1165 * If the first frag mapping failed, then i will be zero.
1166 * This causes the unmap of the skb->data area. Otherwise
1167 * we pass in the number of frags that mapped successfully
1168 * so they can be umapped.
1169 */
1170 ql_unmap_send(qdev, tx_ring_desc, map_idx);
1171 return NETDEV_TX_BUSY;
1172}
1173
8668ae92 1174static void ql_realign_skb(struct sk_buff *skb, int len)
c4e84bde
RM		 1175{
1176 void *temp_addr = skb->data;
1177
1178 /* Undo the skb_reserve(skb,32) we did before
1179 * giving to hardware, and realign data on
1180 * a 2-byte boundary.
1181 */
1182 skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1183 skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1184 skb_copy_to_linear_data(skb, temp_addr,
1185 (unsigned int)len);
1186}
1187
1188/*
1189 * This function builds an skb for the given inbound
1190 * completion. It will be rewritten for readability in the near
1191 * future, but for not it works well.
1192 */
1193static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1194 struct rx_ring *rx_ring,
1195 struct ib_mac_iocb_rsp *ib_mac_rsp)
1196{
1197 struct bq_desc *lbq_desc;
1198 struct bq_desc *sbq_desc;
1199 struct sk_buff *skb = NULL;
1200 u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1201 u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1202
1203 /*
1204 * Handle the header buffer if present.
1205 */
1206 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1207 ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1208 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1209 /*
1210 * Headers fit nicely into a small buffer.
1211 */
1212 sbq_desc = ql_get_curr_sbuf(rx_ring);
1213 pci_unmap_single(qdev->pdev,
1214 pci_unmap_addr(sbq_desc, mapaddr),
1215 pci_unmap_len(sbq_desc, maplen),
1216 PCI_DMA_FROMDEVICE);
1217 skb = sbq_desc->p.skb;
1218 ql_realign_skb(skb, hdr_len);
1219 skb_put(skb, hdr_len);
1220 sbq_desc->p.skb = NULL;
1221 }
1222
1223 /*
1224 * Handle the data buffer(s).
1225 */
1226 if (unlikely(!length)) { /* Is there data too? */
1227 QPRINTK(qdev, RX_STATUS, DEBUG,
1228 "No Data buffer in this packet.\n");
1229 return skb;
1230 }
1231
1232 if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1233 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1234 QPRINTK(qdev, RX_STATUS, DEBUG,
1235 "Headers in small, data of %d bytes in small, combine them.\n", length);
1236 /*
1237 * Data is less than small buffer size so it's
1238 * stuffed in a small buffer.
1239 * For this case we append the data
1240 * from the "data" small buffer to the "header" small
1241 * buffer.
1242 */
1243 sbq_desc = ql_get_curr_sbuf(rx_ring);
1244 pci_dma_sync_single_for_cpu(qdev->pdev,
1245 pci_unmap_addr
1246 (sbq_desc, mapaddr),
1247 pci_unmap_len
1248 (sbq_desc, maplen),
1249 PCI_DMA_FROMDEVICE);
1250 memcpy(skb_put(skb, length),
1251 sbq_desc->p.skb->data, length);
1252 pci_dma_sync_single_for_device(qdev->pdev,
1253 pci_unmap_addr
1254 (sbq_desc,
1255 mapaddr),
1256 pci_unmap_len
1257 (sbq_desc,
1258 maplen),
1259 PCI_DMA_FROMDEVICE);
1260 } else {
1261 QPRINTK(qdev, RX_STATUS, DEBUG,
1262 "%d bytes in a single small buffer.\n", length);
1263 sbq_desc = ql_get_curr_sbuf(rx_ring);
1264 skb = sbq_desc->p.skb;
1265 ql_realign_skb(skb, length);
1266 skb_put(skb, length);
1267 pci_unmap_single(qdev->pdev,
1268 pci_unmap_addr(sbq_desc,
1269 mapaddr),
1270 pci_unmap_len(sbq_desc,
1271 maplen),
1272 PCI_DMA_FROMDEVICE);
1273 sbq_desc->p.skb = NULL;
1274 }
1275 } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1276 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1277 QPRINTK(qdev, RX_STATUS, DEBUG,
1278 "Header in small, %d bytes in large. Chain large to small!\n", length);
1279 /*
1280 * The data is in a single large buffer. We
1281 * chain it to the header buffer's skb and let
1282 * it rip.
1283 */
1284 lbq_desc = ql_get_curr_lbuf(rx_ring);
1285 pci_unmap_page(qdev->pdev,
1286 pci_unmap_addr(lbq_desc,
1287 mapaddr),
1288 pci_unmap_len(lbq_desc, maplen),
1289 PCI_DMA_FROMDEVICE);
1290 QPRINTK(qdev, RX_STATUS, DEBUG,
1291 "Chaining page to skb.\n");
1292 skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1293 0, length);
1294 skb->len += length;
1295 skb->data_len += length;
1296 skb->truesize += length;
1297 lbq_desc->p.lbq_page = NULL;
1298 } else {
1299 /*
1300 * The headers and data are in a single large buffer. We
1301 * copy it to a new skb and let it go. This can happen with
1302 * jumbo mtu on a non-TCP/UDP frame.
1303 */
1304 lbq_desc = ql_get_curr_lbuf(rx_ring);
1305 skb = netdev_alloc_skb(qdev->ndev, length);
1306 if (skb == NULL) {
1307 QPRINTK(qdev, PROBE, DEBUG,
1308 "No skb available, drop the packet.\n");
1309 return NULL;
1310 }
4055c7d4
RM		 1311 pci_unmap_page(qdev->pdev,
1312 pci_unmap_addr(lbq_desc,
1313 mapaddr),
1314 pci_unmap_len(lbq_desc, maplen),
1315 PCI_DMA_FROMDEVICE);
c4e84bde
RM		 1316 skb_reserve(skb, NET_IP_ALIGN);
1317 QPRINTK(qdev, RX_STATUS, DEBUG,
1318 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1319 skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1320 0, length);
1321 skb->len += length;
1322 skb->data_len += length;
1323 skb->truesize += length;
1324 length -= length;
1325 lbq_desc->p.lbq_page = NULL;
1326 __pskb_pull_tail(skb,
1327 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1328 VLAN_ETH_HLEN : ETH_HLEN);
1329 }
1330 } else {
1331 /*
1332 * The data is in a chain of large buffers
1333 * pointed to by a small buffer. We loop
1334 * thru and chain them to the our small header
1335 * buffer's skb.
1336 * frags: There are 18 max frags and our small
1337 * buffer will hold 32 of them. The thing is,
1338 * we'll use 3 max for our 9000 byte jumbo
1339 * frames. If the MTU goes up we could
1340 * eventually be in trouble.
1341 */
1342 int size, offset, i = 0;
1343 struct bq_element *bq, bq_array[8];
1344 sbq_desc = ql_get_curr_sbuf(rx_ring);
1345 pci_unmap_single(qdev->pdev,
1346 pci_unmap_addr(sbq_desc, mapaddr),
1347 pci_unmap_len(sbq_desc, maplen),
1348 PCI_DMA_FROMDEVICE);
1349 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1350 /*
1351 * This is an non TCP/UDP IP frame, so
1352 * the headers aren't split into a small
1353 * buffer. We have to use the small buffer
1354 * that contains our sg list as our skb to
1355 * send upstairs. Copy the sg list here to
1356 * a local buffer and use it to find the
1357 * pages to chain.
1358 */
1359 QPRINTK(qdev, RX_STATUS, DEBUG,
1360 "%d bytes of headers & data in chain of large.\n", length);
1361 skb = sbq_desc->p.skb;
1362 bq = &bq_array[0];
1363 memcpy(bq, skb->data, sizeof(bq_array));
1364 sbq_desc->p.skb = NULL;
1365 skb_reserve(skb, NET_IP_ALIGN);
1366 } else {
1367 QPRINTK(qdev, RX_STATUS, DEBUG,
1368 "Headers in small, %d bytes of data in chain of large.\n", length);
1369 bq = (struct bq_element *)sbq_desc->p.skb->data;
1370 }
1371 while (length > 0) {
1372 lbq_desc = ql_get_curr_lbuf(rx_ring);
1373 if ((bq->addr_lo & ~BQ_MASK) != lbq_desc->bq->addr_lo) {
1374 QPRINTK(qdev, RX_STATUS, ERR,
1375 "Panic!!! bad large buffer address, expected 0x%.08x, got 0x%.08x.\n",
1376 lbq_desc->bq->addr_lo, bq->addr_lo);
1377 return NULL;
1378 }
1379 pci_unmap_page(qdev->pdev,
1380 pci_unmap_addr(lbq_desc,
1381 mapaddr),
1382 pci_unmap_len(lbq_desc,
1383 maplen),
1384 PCI_DMA_FROMDEVICE);
1385 size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1386 offset = 0;
1387
1388 QPRINTK(qdev, RX_STATUS, DEBUG,
1389 "Adding page %d to skb for %d bytes.\n",
1390 i, size);
1391 skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1392 offset, size);
1393 skb->len += size;
1394 skb->data_len += size;
1395 skb->truesize += size;
1396 length -= size;
1397 lbq_desc->p.lbq_page = NULL;
1398 bq++;
1399 i++;
1400 }
1401 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1402 VLAN_ETH_HLEN : ETH_HLEN);
1403 }
1404 return skb;
1405}
1406
1407/* Process an inbound completion from an rx ring. */
1408static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1409 struct rx_ring *rx_ring,
1410 struct ib_mac_iocb_rsp *ib_mac_rsp)
1411{
1412 struct net_device *ndev = qdev->ndev;
1413 struct sk_buff *skb = NULL;
1414
1415 QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1416
1417 skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1418 if (unlikely(!skb)) {
1419 QPRINTK(qdev, RX_STATUS, DEBUG,
1420 "No skb available, drop packet.\n");
1421 return;
1422 }
1423
1424 prefetch(skb->data);
1425 skb->dev = ndev;
1426 if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1427 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1428 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1429 IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1430 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1431 IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1432 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1433 IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1434 }
1435 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1436 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1437 }
1438 if (ib_mac_rsp->flags1 & (IB_MAC_IOCB_RSP_IE | IB_MAC_IOCB_RSP_TE)) {
1439 QPRINTK(qdev, RX_STATUS, ERR,
1440 "Bad checksum for this %s packet.\n",
1441 ((ib_mac_rsp->
1442 flags2 & IB_MAC_IOCB_RSP_T) ? "TCP" : "UDP"));
1443 skb->ip_summed = CHECKSUM_NONE;
1444 } else if (qdev->rx_csum &&
1445 ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) ||
1446 ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1447 !(ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_NU)))) {
1448 QPRINTK(qdev, RX_STATUS, DEBUG, "RX checksum done!\n");
1449 skb->ip_summed = CHECKSUM_UNNECESSARY;
1450 }
1451 qdev->stats.rx_packets++;
1452 qdev->stats.rx_bytes += skb->len;
1453 skb->protocol = eth_type_trans(skb, ndev);
1454 if (qdev->vlgrp && (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V)) {
1455 QPRINTK(qdev, RX_STATUS, DEBUG,
1456 "Passing a VLAN packet upstream.\n");
1457 vlan_hwaccel_rx(skb, qdev->vlgrp,
1458 le16_to_cpu(ib_mac_rsp->vlan_id));
1459 } else {
1460 QPRINTK(qdev, RX_STATUS, DEBUG,
1461 "Passing a normal packet upstream.\n");
1462 netif_rx(skb);
1463 }
c4e84bde
RM		 1464}
1465
1466/* Process an outbound completion from an rx ring. */
1467static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1468 struct ob_mac_iocb_rsp *mac_rsp)
1469{
1470 struct tx_ring *tx_ring;
1471 struct tx_ring_desc *tx_ring_desc;
1472
1473 QL_DUMP_OB_MAC_RSP(mac_rsp);
1474 tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1475 tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1476 ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1477 qdev->stats.tx_bytes += tx_ring_desc->map_cnt;
1478 qdev->stats.tx_packets++;
1479 dev_kfree_skb(tx_ring_desc->skb);
1480 tx_ring_desc->skb = NULL;
1481
1482 if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1483 OB_MAC_IOCB_RSP_S |
1484 OB_MAC_IOCB_RSP_L |
1485 OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1486 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1487 QPRINTK(qdev, TX_DONE, WARNING,
1488 "Total descriptor length did not match transfer length.\n");
1489 }
1490 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1491 QPRINTK(qdev, TX_DONE, WARNING,
1492 "Frame too short to be legal, not sent.\n");
1493 }
1494 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1495 QPRINTK(qdev, TX_DONE, WARNING,
1496 "Frame too long, but sent anyway.\n");
1497 }
1498 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1499 QPRINTK(qdev, TX_DONE, WARNING,
1500 "PCI backplane error. Frame not sent.\n");
1501 }
1502 }
1503 atomic_inc(&tx_ring->tx_count);
1504}
1505
1506/* Fire up a handler to reset the MPI processor. */
1507void ql_queue_fw_error(struct ql_adapter *qdev)
1508{
1509 netif_stop_queue(qdev->ndev);
1510 netif_carrier_off(qdev->ndev);
1511 queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1512}
1513
1514void ql_queue_asic_error(struct ql_adapter *qdev)
1515{
1516 netif_stop_queue(qdev->ndev);
1517 netif_carrier_off(qdev->ndev);
1518 ql_disable_interrupts(qdev);
1519 queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1520}
1521
1522static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1523 struct ib_ae_iocb_rsp *ib_ae_rsp)
1524{
1525 switch (ib_ae_rsp->event) {
1526 case MGMT_ERR_EVENT:
1527 QPRINTK(qdev, RX_ERR, ERR,
1528 "Management Processor Fatal Error.\n");
1529 ql_queue_fw_error(qdev);
1530 return;
1531
1532 case CAM_LOOKUP_ERR_EVENT:
1533 QPRINTK(qdev, LINK, ERR,
1534 "Multiple CAM hits lookup occurred.\n");
1535 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1536 ql_queue_asic_error(qdev);
1537 return;
1538
1539 case SOFT_ECC_ERROR_EVENT:
1540 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1541 ql_queue_asic_error(qdev);
1542 break;
1543
1544 case PCI_ERR_ANON_BUF_RD:
1545 QPRINTK(qdev, RX_ERR, ERR,
1546 "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1547 ib_ae_rsp->q_id);
1548 ql_queue_asic_error(qdev);
1549 break;
1550
1551 default:
1552 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1553 ib_ae_rsp->event);
1554 ql_queue_asic_error(qdev);
1555 break;
1556 }
1557}
1558
1559static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1560{
1561 struct ql_adapter *qdev = rx_ring->qdev;
2b72c784 1562 u32 prod = le32_to_cpu(*rx_ring->prod_idx_sh_reg);
c4e84bde
RM		 1563 struct ob_mac_iocb_rsp *net_rsp = NULL;
1564 int count = 0;
1565
1566 /* While there are entries in the completion queue. */
1567 while (prod != rx_ring->cnsmr_idx) {
1568
1569 QPRINTK(qdev, RX_STATUS, DEBUG,
1570 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1571 prod, rx_ring->cnsmr_idx);
1572
1573 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1574 rmb();
1575 switch (net_rsp->opcode) {
1576
1577 case OPCODE_OB_MAC_TSO_IOCB:
1578 case OPCODE_OB_MAC_IOCB:
1579 ql_process_mac_tx_intr(qdev, net_rsp);
1580 break;
1581 default:
1582 QPRINTK(qdev, RX_STATUS, DEBUG,
1583 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1584 net_rsp->opcode);
1585 }
1586 count++;
1587 ql_update_cq(rx_ring);
2b72c784 1588 prod = le32_to_cpu(*rx_ring->prod_idx_sh_reg);
c4e84bde
RM		 1589 }
1590 ql_write_cq_idx(rx_ring);
1591 if (netif_queue_stopped(qdev->ndev) && net_rsp != NULL) {
1592 struct tx_ring *tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1593 if (atomic_read(&tx_ring->queue_stopped) &&
1594 (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1595 /*
1596 * The queue got stopped because the tx_ring was full.
1597 * Wake it up, because it's now at least 25% empty.
1598 */
1599 netif_wake_queue(qdev->ndev);
1600 }
1601
1602 return count;
1603}
1604
1605static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1606{
1607 struct ql_adapter *qdev = rx_ring->qdev;
2b72c784 1608 u32 prod = le32_to_cpu(*rx_ring->prod_idx_sh_reg);
c4e84bde
RM		 1609 struct ql_net_rsp_iocb *net_rsp;
1610 int count = 0;
1611
1612 /* While there are entries in the completion queue. */
1613 while (prod != rx_ring->cnsmr_idx) {
1614
1615 QPRINTK(qdev, RX_STATUS, DEBUG,
1616 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1617 prod, rx_ring->cnsmr_idx);
1618
1619 net_rsp = rx_ring->curr_entry;
1620 rmb();
1621 switch (net_rsp->opcode) {
1622 case OPCODE_IB_MAC_IOCB:
1623 ql_process_mac_rx_intr(qdev, rx_ring,
1624 (struct ib_mac_iocb_rsp *)
1625 net_rsp);
1626 break;
1627
1628 case OPCODE_IB_AE_IOCB:
1629 ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1630 net_rsp);
1631 break;
1632 default:
1633 {
1634 QPRINTK(qdev, RX_STATUS, DEBUG,
1635 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1636 net_rsp->opcode);
1637 }
1638 }
1639 count++;
1640 ql_update_cq(rx_ring);
2b72c784 1641 prod = le32_to_cpu(*rx_ring->prod_idx_sh_reg);
c4e84bde
RM		 1642 if (count == budget)
1643 break;
1644 }
1645 ql_update_buffer_queues(qdev, rx_ring);
1646 ql_write_cq_idx(rx_ring);
1647 return count;
1648}
1649
1650static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1651{
1652 struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1653 struct ql_adapter *qdev = rx_ring->qdev;
1654 int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1655
1656 QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1657 rx_ring->cq_id);
1658
1659 if (work_done < budget) {
908a7a16 1660 __netif_rx_complete(napi);
c4e84bde
RM		 1661 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1662 }
1663 return work_done;
1664}
1665
1666static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1667{
1668 struct ql_adapter *qdev = netdev_priv(ndev);
1669
1670 qdev->vlgrp = grp;
1671 if (grp) {
1672 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1673 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1674 NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1675 } else {
1676 QPRINTK(qdev, IFUP, DEBUG,
1677 "Turning off VLAN in NIC_RCV_CFG.\n");
1678 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1679 }
1680}
1681
1682static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1683{
1684 struct ql_adapter *qdev = netdev_priv(ndev);
1685 u32 enable_bit = MAC_ADDR_E;
1686
1687 spin_lock(&qdev->hw_lock);
1688 if (ql_set_mac_addr_reg
1689 (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1690 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1691 }
1692 spin_unlock(&qdev->hw_lock);
1693}
1694
1695static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1696{
1697 struct ql_adapter *qdev = netdev_priv(ndev);
1698 u32 enable_bit = 0;
1699
1700 spin_lock(&qdev->hw_lock);
1701 if (ql_set_mac_addr_reg
1702 (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1703 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1704 }
1705 spin_unlock(&qdev->hw_lock);
1706
1707}
1708
1709/* Worker thread to process a given rx_ring that is dedicated
1710 * to outbound completions.
1711 */
1712static void ql_tx_clean(struct work_struct *work)
1713{
1714 struct rx_ring *rx_ring =
1715 container_of(work, struct rx_ring, rx_work.work);
1716 ql_clean_outbound_rx_ring(rx_ring);
1717 ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1718
1719}
1720
1721/* Worker thread to process a given rx_ring that is dedicated
1722 * to inbound completions.
1723 */
1724static void ql_rx_clean(struct work_struct *work)
1725{
1726 struct rx_ring *rx_ring =
1727 container_of(work, struct rx_ring, rx_work.work);
1728 ql_clean_inbound_rx_ring(rx_ring, 64);
1729 ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1730}
1731
1732/* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1733static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1734{
1735 struct rx_ring *rx_ring = dev_id;
1736 queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1737 &rx_ring->rx_work, 0);
1738 return IRQ_HANDLED;
1739}
1740
1741/* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1742static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1743{
1744 struct rx_ring *rx_ring = dev_id;
908a7a16 1745 netif_rx_schedule(&rx_ring->napi);
c4e84bde
RM		 1746 return IRQ_HANDLED;
1747}
1748
c4e84bde
RM		 1749/* This handles a fatal error, MPI activity, and the default
1750 * rx_ring in an MSI-X multiple vector environment.
1751 * In MSI/Legacy environment it also process the rest of
1752 * the rx_rings.
1753 */
1754static irqreturn_t qlge_isr(int irq, void *dev_id)
1755{
1756 struct rx_ring *rx_ring = dev_id;
1757 struct ql_adapter *qdev = rx_ring->qdev;
1758 struct intr_context *intr_context = &qdev->intr_context[0];
1759 u32 var;
1760 int i;
1761 int work_done = 0;
1762
bb0d215c
RM		 1763 spin_lock(&qdev->hw_lock);
1764 if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1765 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1766 spin_unlock(&qdev->hw_lock);
1767 return IRQ_NONE;
c4e84bde 1768 }
bb0d215c 1769 spin_unlock(&qdev->hw_lock);
c4e84bde 1770
bb0d215c 1771 var = ql_disable_completion_interrupt(qdev, intr_context->intr);
c4e84bde
RM		 1772
1773 /*
1774 * Check for fatal error.
1775 */
1776 if (var & STS_FE) {
1777 ql_queue_asic_error(qdev);
1778 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1779 var = ql_read32(qdev, ERR_STS);
1780 QPRINTK(qdev, INTR, ERR,
1781 "Resetting chip. Error Status Register = 0x%x\n", var);
1782 return IRQ_HANDLED;
1783 }
1784
1785 /*
1786 * Check MPI processor activity.
1787 */
1788 if (var & STS_PI) {
1789 /*
1790 * We've got an async event or mailbox completion.
1791 * Handle it and clear the source of the interrupt.
1792 */
1793 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
1794 ql_disable_completion_interrupt(qdev, intr_context->intr);
1795 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
1796 &qdev->mpi_work, 0);
1797 work_done++;
1798 }
1799
1800 /*
1801 * Check the default queue and wake handler if active.
1802 */
1803 rx_ring = &qdev->rx_ring[0];
2b72c784 1804 if (le32_to_cpu(*rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
c4e84bde
RM		 1805 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
1806 ql_disable_completion_interrupt(qdev, intr_context->intr);
1807 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
1808 &rx_ring->rx_work, 0);
1809 work_done++;
1810 }
1811
1812 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
1813 /*
1814 * Start the DPC for each active queue.
1815 */
1816 for (i = 1; i < qdev->rx_ring_count; i++) {
1817 rx_ring = &qdev->rx_ring[i];
2b72c784 1818 if (le32_to_cpu(*rx_ring->prod_idx_sh_reg) !=
c4e84bde
RM		 1819 rx_ring->cnsmr_idx) {
1820 QPRINTK(qdev, INTR, INFO,
1821 "Waking handler for rx_ring[%d].\n", i);
1822 ql_disable_completion_interrupt(qdev,
1823 intr_context->
1824 intr);
1825 if (i < qdev->rss_ring_first_cq_id)
1826 queue_delayed_work_on(rx_ring->cpu,
1827 qdev->q_workqueue,
1828 &rx_ring->rx_work,
1829 0);
1830 else
908a7a16 1831 netif_rx_schedule(&rx_ring->napi);
c4e84bde
RM		 1832 work_done++;
1833 }
1834 }
1835 }
bb0d215c 1836 ql_enable_completion_interrupt(qdev, intr_context->intr);
c4e84bde
RM		 1837 return work_done ? IRQ_HANDLED : IRQ_NONE;
1838}
1839
1840static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1841{
1842
1843 if (skb_is_gso(skb)) {
1844 int err;
1845 if (skb_header_cloned(skb)) {
1846 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1847 if (err)
1848 return err;
1849 }
1850
1851 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1852 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
1853 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1854 mac_iocb_ptr->total_hdrs_len =
1855 cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
1856 mac_iocb_ptr->net_trans_offset =
1857 cpu_to_le16(skb_network_offset(skb) |
1858 skb_transport_offset(skb)
1859 << OB_MAC_TRANSPORT_HDR_SHIFT);
1860 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
1861 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
1862 if (likely(skb->protocol == htons(ETH_P_IP))) {
1863 struct iphdr *iph = ip_hdr(skb);
1864 iph->check = 0;
1865 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1866 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1867 iph->daddr, 0,
1868 IPPROTO_TCP,
1869 0);
1870 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1871 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
1872 tcp_hdr(skb)->check =
1873 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1874 &ipv6_hdr(skb)->daddr,
1875 0, IPPROTO_TCP, 0);
1876 }
1877 return 1;
1878 }
1879 return 0;
1880}
1881
1882static void ql_hw_csum_setup(struct sk_buff *skb,
1883 struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1884{
1885 int len;
1886 struct iphdr *iph = ip_hdr(skb);
1887 u16 *check;
1888 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1889 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1890 mac_iocb_ptr->net_trans_offset =
1891 cpu_to_le16(skb_network_offset(skb) |
1892 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
1893
1894 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1895 len = (ntohs(iph->tot_len) - (iph->ihl << 2));
1896 if (likely(iph->protocol == IPPROTO_TCP)) {
1897 check = &(tcp_hdr(skb)->check);
1898 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
1899 mac_iocb_ptr->total_hdrs_len =
1900 cpu_to_le16(skb_transport_offset(skb) +
1901 (tcp_hdr(skb)->doff << 2));
1902 } else {
1903 check = &(udp_hdr(skb)->check);
1904 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
1905 mac_iocb_ptr->total_hdrs_len =
1906 cpu_to_le16(skb_transport_offset(skb) +
1907 sizeof(struct udphdr));
1908 }
1909 *check = ~csum_tcpudp_magic(iph->saddr,
1910 iph->daddr, len, iph->protocol, 0);
1911}
1912
1913static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
1914{
1915 struct tx_ring_desc *tx_ring_desc;
1916 struct ob_mac_iocb_req *mac_iocb_ptr;
1917 struct ql_adapter *qdev = netdev_priv(ndev);
1918 int tso;
1919 struct tx_ring *tx_ring;
1920 u32 tx_ring_idx = (u32) QL_TXQ_IDX(qdev, skb);
1921
1922 tx_ring = &qdev->tx_ring[tx_ring_idx];
1923
1924 if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
1925 QPRINTK(qdev, TX_QUEUED, INFO,
1926 "%s: shutting down tx queue %d du to lack of resources.\n",
1927 __func__, tx_ring_idx);
1928 netif_stop_queue(ndev);
1929 atomic_inc(&tx_ring->queue_stopped);
1930 return NETDEV_TX_BUSY;
1931 }
1932 tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
1933 mac_iocb_ptr = tx_ring_desc->queue_entry;
1934 memset((void *)mac_iocb_ptr, 0, sizeof(mac_iocb_ptr));
1935 if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) != NETDEV_TX_OK) {
1936 QPRINTK(qdev, TX_QUEUED, ERR, "Could not map the segments.\n");
1937 return NETDEV_TX_BUSY;
1938 }
1939
1940 mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
1941 mac_iocb_ptr->tid = tx_ring_desc->index;
1942 /* We use the upper 32-bits to store the tx queue for this IO.
1943 * When we get the completion we can use it to establish the context.
1944 */
1945 mac_iocb_ptr->txq_idx = tx_ring_idx;
1946 tx_ring_desc->skb = skb;
1947
1948 mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
1949
1950 if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
1951 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
1952 vlan_tx_tag_get(skb));
1953 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
1954 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
1955 }
1956 tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1957 if (tso < 0) {
1958 dev_kfree_skb_any(skb);
1959 return NETDEV_TX_OK;
1960 } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
1961 ql_hw_csum_setup(skb,
1962 (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1963 }
1964 QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
1965 tx_ring->prod_idx++;
1966 if (tx_ring->prod_idx == tx_ring->wq_len)
1967 tx_ring->prod_idx = 0;
1968 wmb();
1969
1970 ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
1971 ndev->trans_start = jiffies;
1972 QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
1973 tx_ring->prod_idx, skb->len);
1974
1975 atomic_dec(&tx_ring->tx_count);
1976 return NETDEV_TX_OK;
1977}
1978
1979static void ql_free_shadow_space(struct ql_adapter *qdev)
1980{
1981 if (qdev->rx_ring_shadow_reg_area) {
1982 pci_free_consistent(qdev->pdev,
1983 PAGE_SIZE,
1984 qdev->rx_ring_shadow_reg_area,
1985 qdev->rx_ring_shadow_reg_dma);
1986 qdev->rx_ring_shadow_reg_area = NULL;
1987 }
1988 if (qdev->tx_ring_shadow_reg_area) {
1989 pci_free_consistent(qdev->pdev,
1990 PAGE_SIZE,
1991 qdev->tx_ring_shadow_reg_area,
1992 qdev->tx_ring_shadow_reg_dma);
1993 qdev->tx_ring_shadow_reg_area = NULL;
1994 }
1995}
1996
1997static int ql_alloc_shadow_space(struct ql_adapter *qdev)
1998{
1999 qdev->rx_ring_shadow_reg_area =
2000 pci_alloc_consistent(qdev->pdev,
2001 PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
2002 if (qdev->rx_ring_shadow_reg_area == NULL) {
2003 QPRINTK(qdev, IFUP, ERR,
2004 "Allocation of RX shadow space failed.\n");
2005 return -ENOMEM;
2006 }
2007 qdev->tx_ring_shadow_reg_area =
2008 pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2009 &qdev->tx_ring_shadow_reg_dma);
2010 if (qdev->tx_ring_shadow_reg_area == NULL) {
2011 QPRINTK(qdev, IFUP, ERR,
2012 "Allocation of TX shadow space failed.\n");
2013 goto err_wqp_sh_area;
2014 }
2015 return 0;
2016
2017err_wqp_sh_area:
2018 pci_free_consistent(qdev->pdev,
2019 PAGE_SIZE,
2020 qdev->rx_ring_shadow_reg_area,
2021 qdev->rx_ring_shadow_reg_dma);
2022 return -ENOMEM;
2023}
2024
2025static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2026{
2027 struct tx_ring_desc *tx_ring_desc;
2028 int i;
2029 struct ob_mac_iocb_req *mac_iocb_ptr;
2030
2031 mac_iocb_ptr = tx_ring->wq_base;
2032 tx_ring_desc = tx_ring->q;
2033 for (i = 0; i < tx_ring->wq_len; i++) {
2034 tx_ring_desc->index = i;
2035 tx_ring_desc->skb = NULL;
2036 tx_ring_desc->queue_entry = mac_iocb_ptr;
2037 mac_iocb_ptr++;
2038 tx_ring_desc++;
2039 }
2040 atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2041 atomic_set(&tx_ring->queue_stopped, 0);
2042}
2043
2044static void ql_free_tx_resources(struct ql_adapter *qdev,
2045 struct tx_ring *tx_ring)
2046{
2047 if (tx_ring->wq_base) {
2048 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2049 tx_ring->wq_base, tx_ring->wq_base_dma);
2050 tx_ring->wq_base = NULL;
2051 }
2052 kfree(tx_ring->q);
2053 tx_ring->q = NULL;
2054}
2055
2056static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2057 struct tx_ring *tx_ring)
2058{
2059 tx_ring->wq_base =
2060 pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2061 &tx_ring->wq_base_dma);
2062
2063 if ((tx_ring->wq_base == NULL)
2064 || tx_ring->wq_base_dma & (tx_ring->wq_size - 1)) {
2065 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2066 return -ENOMEM;
2067 }
2068 tx_ring->q =
2069 kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2070 if (tx_ring->q == NULL)
2071 goto err;
2072
2073 return 0;
2074err:
2075 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2076 tx_ring->wq_base, tx_ring->wq_base_dma);
2077 return -ENOMEM;
2078}
2079
8668ae92 2080static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
c4e84bde
RM		 2081{
2082 int i;
2083 struct bq_desc *lbq_desc;
2084
2085 for (i = 0; i < rx_ring->lbq_len; i++) {
2086 lbq_desc = &rx_ring->lbq[i];
2087 if (lbq_desc->p.lbq_page) {
2088 pci_unmap_page(qdev->pdev,
2089 pci_unmap_addr(lbq_desc, mapaddr),
2090 pci_unmap_len(lbq_desc, maplen),
2091 PCI_DMA_FROMDEVICE);
2092
2093 put_page(lbq_desc->p.lbq_page);
2094 lbq_desc->p.lbq_page = NULL;
2095 }
2096 lbq_desc->bq->addr_lo = 0;
2097 lbq_desc->bq->addr_hi = 0;
2098 }
2099}
2100
2101/*
2102 * Allocate and map a page for each element of the lbq.
2103 */
2104static int ql_alloc_lbq_buffers(struct ql_adapter *qdev,
2105 struct rx_ring *rx_ring)
2106{
2107 int i;
2108 struct bq_desc *lbq_desc;
2109 u64 map;
2110 struct bq_element *bq = rx_ring->lbq_base;
2111
2112 for (i = 0; i < rx_ring->lbq_len; i++) {
2113 lbq_desc = &rx_ring->lbq[i];
2114 memset(lbq_desc, 0, sizeof(lbq_desc));
2115 lbq_desc->bq = bq;
2116 lbq_desc->index = i;
2117 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
2118 if (unlikely(!lbq_desc->p.lbq_page)) {
2119 QPRINTK(qdev, IFUP, ERR, "failed alloc_page().\n");
2120 goto mem_error;
2121 } else {
2122 map = pci_map_page(qdev->pdev,
2123 lbq_desc->p.lbq_page,
2124 0, PAGE_SIZE, PCI_DMA_FROMDEVICE);
2125 if (pci_dma_mapping_error(qdev->pdev, map)) {
2126 QPRINTK(qdev, IFUP, ERR,
2127 "PCI mapping failed.\n");
2128 goto mem_error;
2129 }
2130 pci_unmap_addr_set(lbq_desc, mapaddr, map);
2131 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
2132 bq->addr_lo = cpu_to_le32(map);
2133 bq->addr_hi = cpu_to_le32(map >> 32);
2134 }
2135 bq++;
2136 }
2137 return 0;
2138mem_error:
2139 ql_free_lbq_buffers(qdev, rx_ring);
2140 return -ENOMEM;
2141}
2142
8668ae92 2143static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
c4e84bde
RM		 2144{
2145 int i;
2146 struct bq_desc *sbq_desc;
2147
2148 for (i = 0; i < rx_ring->sbq_len; i++) {
2149 sbq_desc = &rx_ring->sbq[i];
2150 if (sbq_desc == NULL) {
2151 QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2152 return;
2153 }
2154 if (sbq_desc->p.skb) {
2155 pci_unmap_single(qdev->pdev,
2156 pci_unmap_addr(sbq_desc, mapaddr),
2157 pci_unmap_len(sbq_desc, maplen),
2158 PCI_DMA_FROMDEVICE);
2159 dev_kfree_skb(sbq_desc->p.skb);
2160 sbq_desc->p.skb = NULL;
2161 }
2162 if (sbq_desc->bq == NULL) {
2163 QPRINTK(qdev, IFUP, ERR, "sbq_desc->bq %d is NULL.\n",
2164 i);
2165 return;
2166 }
2167 sbq_desc->bq->addr_lo = 0;
2168 sbq_desc->bq->addr_hi = 0;
2169 }
2170}
2171
2172/* Allocate and map an skb for each element of the sbq. */
2173static int ql_alloc_sbq_buffers(struct ql_adapter *qdev,
2174 struct rx_ring *rx_ring)
2175{
2176 int i;
2177 struct bq_desc *sbq_desc;
2178 struct sk_buff *skb;
2179 u64 map;
2180 struct bq_element *bq = rx_ring->sbq_base;
2181
2182 for (i = 0; i < rx_ring->sbq_len; i++) {
2183 sbq_desc = &rx_ring->sbq[i];
2184 memset(sbq_desc, 0, sizeof(sbq_desc));
2185 sbq_desc->index = i;
2186 sbq_desc->bq = bq;
2187 skb = netdev_alloc_skb(qdev->ndev, rx_ring->sbq_buf_size);
2188 if (unlikely(!skb)) {
2189 /* Better luck next round */
2190 QPRINTK(qdev, IFUP, ERR,
2191 "small buff alloc failed for %d bytes at index %d.\n",
2192 rx_ring->sbq_buf_size, i);
2193 goto mem_err;
2194 }
2195 skb_reserve(skb, QLGE_SB_PAD);
2196 sbq_desc->p.skb = skb;
2197 /*
2198 * Map only half the buffer. Because the
2199 * other half may get some data copied to it
2200 * when the completion arrives.
2201 */
2202 map = pci_map_single(qdev->pdev,
2203 skb->data,
2204 rx_ring->sbq_buf_size / 2,
2205 PCI_DMA_FROMDEVICE);
2206 if (pci_dma_mapping_error(qdev->pdev, map)) {
2207 QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
2208 goto mem_err;
2209 }
2210 pci_unmap_addr_set(sbq_desc, mapaddr, map);
2211 pci_unmap_len_set(sbq_desc, maplen, rx_ring->sbq_buf_size / 2);
2212 bq->addr_lo = /*sbq_desc->addr_lo = */
2213 cpu_to_le32(map);
2214 bq->addr_hi = /*sbq_desc->addr_hi = */
2215 cpu_to_le32(map >> 32);
2216 bq++;
2217 }
2218 return 0;
2219mem_err:
2220 ql_free_sbq_buffers(qdev, rx_ring);
2221 return -ENOMEM;
2222}
2223
2224static void ql_free_rx_resources(struct ql_adapter *qdev,
2225 struct rx_ring *rx_ring)
2226{
2227 if (rx_ring->sbq_len)
2228 ql_free_sbq_buffers(qdev, rx_ring);
2229 if (rx_ring->lbq_len)
2230 ql_free_lbq_buffers(qdev, rx_ring);
2231
2232 /* Free the small buffer queue. */
2233 if (rx_ring->sbq_base) {
2234 pci_free_consistent(qdev->pdev,
2235 rx_ring->sbq_size,
2236 rx_ring->sbq_base, rx_ring->sbq_base_dma);
2237 rx_ring->sbq_base = NULL;
2238 }
2239
2240 /* Free the small buffer queue control blocks. */
2241 kfree(rx_ring->sbq);
2242 rx_ring->sbq = NULL;
2243
2244 /* Free the large buffer queue. */
2245 if (rx_ring->lbq_base) {
2246 pci_free_consistent(qdev->pdev,
2247 rx_ring->lbq_size,
2248 rx_ring->lbq_base, rx_ring->lbq_base_dma);
2249 rx_ring->lbq_base = NULL;
2250 }
2251
2252 /* Free the large buffer queue control blocks. */
2253 kfree(rx_ring->lbq);
2254 rx_ring->lbq = NULL;
2255
2256 /* Free the rx queue. */
2257 if (rx_ring->cq_base) {
2258 pci_free_consistent(qdev->pdev,
2259 rx_ring->cq_size,
2260 rx_ring->cq_base, rx_ring->cq_base_dma);
2261 rx_ring->cq_base = NULL;
2262 }
2263}
2264
2265/* Allocate queues and buffers for this completions queue based
2266 * on the values in the parameter structure. */
2267static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2268 struct rx_ring *rx_ring)
2269{
2270
2271 /*
2272 * Allocate the completion queue for this rx_ring.
2273 */
2274 rx_ring->cq_base =
2275 pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2276 &rx_ring->cq_base_dma);
2277
2278 if (rx_ring->cq_base == NULL) {
2279 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2280 return -ENOMEM;
2281 }
2282
2283 if (rx_ring->sbq_len) {
2284 /*
2285 * Allocate small buffer queue.
2286 */
2287 rx_ring->sbq_base =
2288 pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2289 &rx_ring->sbq_base_dma);
2290
2291 if (rx_ring->sbq_base == NULL) {
2292 QPRINTK(qdev, IFUP, ERR,
2293 "Small buffer queue allocation failed.\n");
2294 goto err_mem;
2295 }
2296
2297 /*
2298 * Allocate small buffer queue control blocks.
2299 */
2300 rx_ring->sbq =
2301 kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2302 GFP_KERNEL);
2303 if (rx_ring->sbq == NULL) {
2304 QPRINTK(qdev, IFUP, ERR,
2305 "Small buffer queue control block allocation failed.\n");
2306 goto err_mem;
2307 }
2308
2309 if (ql_alloc_sbq_buffers(qdev, rx_ring)) {
2310 QPRINTK(qdev, IFUP, ERR,
2311 "Small buffer allocation failed.\n");
2312 goto err_mem;
2313 }
2314 }
2315
2316 if (rx_ring->lbq_len) {
2317 /*
2318 * Allocate large buffer queue.
2319 */
2320 rx_ring->lbq_base =
2321 pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2322 &rx_ring->lbq_base_dma);
2323
2324 if (rx_ring->lbq_base == NULL) {
2325 QPRINTK(qdev, IFUP, ERR,
2326 "Large buffer queue allocation failed.\n");
2327 goto err_mem;
2328 }
2329 /*
2330 * Allocate large buffer queue control blocks.
2331 */
2332 rx_ring->lbq =
2333 kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2334 GFP_KERNEL);
2335 if (rx_ring->lbq == NULL) {
2336 QPRINTK(qdev, IFUP, ERR,
2337 "Large buffer queue control block allocation failed.\n");
2338 goto err_mem;
2339 }
2340
2341 /*
2342 * Allocate the buffers.
2343 */
2344 if (ql_alloc_lbq_buffers(qdev, rx_ring)) {
2345 QPRINTK(qdev, IFUP, ERR,
2346 "Large buffer allocation failed.\n");
2347 goto err_mem;
2348 }
2349 }
2350
2351 return 0;
2352
2353err_mem:
2354 ql_free_rx_resources(qdev, rx_ring);
2355 return -ENOMEM;
2356}
2357
2358static void ql_tx_ring_clean(struct ql_adapter *qdev)
2359{
2360 struct tx_ring *tx_ring;
2361 struct tx_ring_desc *tx_ring_desc;
2362 int i, j;
2363
2364 /*
2365 * Loop through all queues and free
2366 * any resources.
2367 */
2368 for (j = 0; j < qdev->tx_ring_count; j++) {
2369 tx_ring = &qdev->tx_ring[j];
2370 for (i = 0; i < tx_ring->wq_len; i++) {
2371 tx_ring_desc = &tx_ring->q[i];
2372 if (tx_ring_desc && tx_ring_desc->skb) {
2373 QPRINTK(qdev, IFDOWN, ERR,
2374 "Freeing lost SKB %p, from queue %d, index %d.\n",
2375 tx_ring_desc->skb, j,
2376 tx_ring_desc->index);
2377 ql_unmap_send(qdev, tx_ring_desc,
2378 tx_ring_desc->map_cnt);
2379 dev_kfree_skb(tx_ring_desc->skb);
2380 tx_ring_desc->skb = NULL;
2381 }
2382 }
2383 }
2384}
2385
2386static void ql_free_ring_cb(struct ql_adapter *qdev)
2387{
2388 kfree(qdev->ring_mem);
2389}
2390
2391static int ql_alloc_ring_cb(struct ql_adapter *qdev)
2392{
2393 /* Allocate space for tx/rx ring control blocks. */
2394 qdev->ring_mem_size =
2395 (qdev->tx_ring_count * sizeof(struct tx_ring)) +
2396 (qdev->rx_ring_count * sizeof(struct rx_ring));
2397 qdev->ring_mem = kmalloc(qdev->ring_mem_size, GFP_KERNEL);
2398 if (qdev->ring_mem == NULL) {
2399 return -ENOMEM;
2400 } else {
2401 qdev->rx_ring = qdev->ring_mem;
2402 qdev->tx_ring = qdev->ring_mem +
2403 (qdev->rx_ring_count * sizeof(struct rx_ring));
2404 }
2405 return 0;
2406}
2407
2408static void ql_free_mem_resources(struct ql_adapter *qdev)
2409{
2410 int i;
2411
2412 for (i = 0; i < qdev->tx_ring_count; i++)
2413 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2414 for (i = 0; i < qdev->rx_ring_count; i++)
2415 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2416 ql_free_shadow_space(qdev);
2417}
2418
2419static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2420{
2421 int i;
2422
2423 /* Allocate space for our shadow registers and such. */
2424 if (ql_alloc_shadow_space(qdev))
2425 return -ENOMEM;
2426
2427 for (i = 0; i < qdev->rx_ring_count; i++) {
2428 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2429 QPRINTK(qdev, IFUP, ERR,
2430 "RX resource allocation failed.\n");
2431 goto err_mem;
2432 }
2433 }
2434 /* Allocate tx queue resources */
2435 for (i = 0; i < qdev->tx_ring_count; i++) {
2436 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2437 QPRINTK(qdev, IFUP, ERR,
2438 "TX resource allocation failed.\n");
2439 goto err_mem;
2440 }
2441 }
2442 return 0;
2443
2444err_mem:
2445 ql_free_mem_resources(qdev);
2446 return -ENOMEM;
2447}
2448
2449/* Set up the rx ring control block and pass it to the chip.
2450 * The control block is defined as
2451 * "Completion Queue Initialization Control Block", or cqicb.
2452 */
2453static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2454{
2455 struct cqicb *cqicb = &rx_ring->cqicb;
2456 void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2457 (rx_ring->cq_id * sizeof(u64) * 4);
2458 u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2459 (rx_ring->cq_id * sizeof(u64) * 4);
2460 void __iomem *doorbell_area =
2461 qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2462 int err = 0;
2463 u16 bq_len;
2464
2465 /* Set up the shadow registers for this ring. */
2466 rx_ring->prod_idx_sh_reg = shadow_reg;
2467 rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2468 shadow_reg += sizeof(u64);
2469 shadow_reg_dma += sizeof(u64);
2470 rx_ring->lbq_base_indirect = shadow_reg;
2471 rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2472 shadow_reg += sizeof(u64);
2473 shadow_reg_dma += sizeof(u64);
2474 rx_ring->sbq_base_indirect = shadow_reg;
2475 rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2476
2477 /* PCI doorbell mem area + 0x00 for consumer index register */
8668ae92 2478 rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
c4e84bde
RM		 2479 rx_ring->cnsmr_idx = 0;
2480 rx_ring->curr_entry = rx_ring->cq_base;
2481
2482 /* PCI doorbell mem area + 0x04 for valid register */
2483 rx_ring->valid_db_reg = doorbell_area + 0x04;
2484
2485 /* PCI doorbell mem area + 0x18 for large buffer consumer */
8668ae92 2486 rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
c4e84bde
RM		 2487
2488 /* PCI doorbell mem area + 0x1c */
8668ae92 2489 rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
c4e84bde
RM		 2490
2491 memset((void *)cqicb, 0, sizeof(struct cqicb));
2492 cqicb->msix_vect = rx_ring->irq;
2493
459caf5a
RM		 2494 bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
2495 cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
c4e84bde
RM		 2496
2497 cqicb->addr_lo = cpu_to_le32(rx_ring->cq_base_dma);
2498 cqicb->addr_hi = cpu_to_le32((u64) rx_ring->cq_base_dma >> 32);
2499
2500 cqicb->prod_idx_addr_lo = cpu_to_le32(rx_ring->prod_idx_sh_reg_dma);
2501 cqicb->prod_idx_addr_hi =
2502 cpu_to_le32((u64) rx_ring->prod_idx_sh_reg_dma >> 32);
2503
2504 /*
2505 * Set up the control block load flags.
2506 */
2507 cqicb->flags = FLAGS_LC | /* Load queue base address */
2508 FLAGS_LV | /* Load MSI-X vector */
2509 FLAGS_LI; /* Load irq delay values */
2510 if (rx_ring->lbq_len) {
2511 cqicb->flags |= FLAGS_LL; /* Load lbq values */
2512 *((u64 *) rx_ring->lbq_base_indirect) = rx_ring->lbq_base_dma;
2513 cqicb->lbq_addr_lo =
2514 cpu_to_le32(rx_ring->lbq_base_indirect_dma);
2515 cqicb->lbq_addr_hi =
2516 cpu_to_le32((u64) rx_ring->lbq_base_indirect_dma >> 32);
459caf5a
RM		 2517 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
2518 (u16) rx_ring->lbq_buf_size;
2519 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
2520 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
2521 (u16) rx_ring->lbq_len;
c4e84bde
RM		 2522 cqicb->lbq_len = cpu_to_le16(bq_len);
2523 rx_ring->lbq_prod_idx = rx_ring->lbq_len - 16;
2524 rx_ring->lbq_curr_idx = 0;
2525 rx_ring->lbq_clean_idx = rx_ring->lbq_prod_idx;
2526 rx_ring->lbq_free_cnt = 16;
2527 }
2528 if (rx_ring->sbq_len) {
2529 cqicb->flags |= FLAGS_LS; /* Load sbq values */
2530 *((u64 *) rx_ring->sbq_base_indirect) = rx_ring->sbq_base_dma;
2531 cqicb->sbq_addr_lo =
2532 cpu_to_le32(rx_ring->sbq_base_indirect_dma);
2533 cqicb->sbq_addr_hi =
2534 cpu_to_le32((u64) rx_ring->sbq_base_indirect_dma >> 32);
2535 cqicb->sbq_buf_size =
2536 cpu_to_le16(((rx_ring->sbq_buf_size / 2) + 8) & 0xfffffff8);
459caf5a
RM		 2537 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
2538 (u16) rx_ring->sbq_len;
c4e84bde
RM		 2539 cqicb->sbq_len = cpu_to_le16(bq_len);
2540 rx_ring->sbq_prod_idx = rx_ring->sbq_len - 16;
2541 rx_ring->sbq_curr_idx = 0;
2542 rx_ring->sbq_clean_idx = rx_ring->sbq_prod_idx;
2543 rx_ring->sbq_free_cnt = 16;
2544 }
2545 switch (rx_ring->type) {
2546 case TX_Q:
2547 /* If there's only one interrupt, then we use
2548 * worker threads to process the outbound
2549 * completion handling rx_rings. We do this so
2550 * they can be run on multiple CPUs. There is
2551 * room to play with this more where we would only
2552 * run in a worker if there are more than x number
2553 * of outbound completions on the queue and more
2554 * than one queue active. Some threshold that
2555 * would indicate a benefit in spite of the cost
2556 * of a context switch.
2557 * If there's more than one interrupt, then the
2558 * outbound completions are processed in the ISR.
2559 */
2560 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2561 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2562 else {
2563 /* With all debug warnings on we see a WARN_ON message
2564 * when we free the skb in the interrupt context.
2565 */
2566 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2567 }
2568 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2569 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2570 break;
2571 case DEFAULT_Q:
2572 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2573 cqicb->irq_delay = 0;
2574 cqicb->pkt_delay = 0;
2575 break;
2576 case RX_Q:
2577 /* Inbound completion handling rx_rings run in
2578 * separate NAPI contexts.
2579 */
2580 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2581 64);
2582 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2583 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2584 break;
2585 default:
2586 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2587 rx_ring->type);
2588 }
2589 QPRINTK(qdev, IFUP, INFO, "Initializing rx work queue.\n");
2590 err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2591 CFG_LCQ, rx_ring->cq_id);
2592 if (err) {
2593 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2594 return err;
2595 }
2596 QPRINTK(qdev, IFUP, INFO, "Successfully loaded CQICB.\n");
2597 /*
2598 * Advance the producer index for the buffer queues.
2599 */
2600 wmb();
2601 if (rx_ring->lbq_len)
2602 ql_write_db_reg(rx_ring->lbq_prod_idx,
2603 rx_ring->lbq_prod_idx_db_reg);
2604 if (rx_ring->sbq_len)
2605 ql_write_db_reg(rx_ring->sbq_prod_idx,
2606 rx_ring->sbq_prod_idx_db_reg);
2607 return err;
2608}
2609
2610static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2611{
2612 struct wqicb *wqicb = (struct wqicb *)tx_ring;
2613 void __iomem *doorbell_area =
2614 qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2615 void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2616 (tx_ring->wq_id * sizeof(u64));
2617 u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2618 (tx_ring->wq_id * sizeof(u64));
2619 int err = 0;
2620
2621 /*
2622 * Assign doorbell registers for this tx_ring.
2623 */
2624 /* TX PCI doorbell mem area for tx producer index */
8668ae92 2625 tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
c4e84bde
RM		 2626 tx_ring->prod_idx = 0;
2627 /* TX PCI doorbell mem area + 0x04 */
2628 tx_ring->valid_db_reg = doorbell_area + 0x04;
2629
2630 /*
2631 * Assign shadow registers for this tx_ring.
2632 */
2633 tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2634 tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2635
2636 wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2637 wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2638 Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2639 wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2640 wqicb->rid = 0;
2641 wqicb->addr_lo = cpu_to_le32(tx_ring->wq_base_dma);
2642 wqicb->addr_hi = cpu_to_le32((u64) tx_ring->wq_base_dma >> 32);
2643
2644 wqicb->cnsmr_idx_addr_lo = cpu_to_le32(tx_ring->cnsmr_idx_sh_reg_dma);
2645 wqicb->cnsmr_idx_addr_hi =
2646 cpu_to_le32((u64) tx_ring->cnsmr_idx_sh_reg_dma >> 32);
2647
2648 ql_init_tx_ring(qdev, tx_ring);
2649
2650 err = ql_write_cfg(qdev, wqicb, sizeof(wqicb), CFG_LRQ,
2651 (u16) tx_ring->wq_id);
2652 if (err) {
2653 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2654 return err;
2655 }
2656 QPRINTK(qdev, IFUP, INFO, "Successfully loaded WQICB.\n");
2657 return err;
2658}
2659
2660static void ql_disable_msix(struct ql_adapter *qdev)
2661{
2662 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2663 pci_disable_msix(qdev->pdev);
2664 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2665 kfree(qdev->msi_x_entry);
2666 qdev->msi_x_entry = NULL;
2667 } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2668 pci_disable_msi(qdev->pdev);
2669 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2670 }
2671}
2672
2673static void ql_enable_msix(struct ql_adapter *qdev)
2674{
2675 int i;
2676
2677 qdev->intr_count = 1;
2678 /* Get the MSIX vectors. */
2679 if (irq_type == MSIX_IRQ) {
2680 /* Try to alloc space for the msix struct,
2681 * if it fails then go to MSI/legacy.
2682 */
2683 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2684 sizeof(struct msix_entry),
2685 GFP_KERNEL);
2686 if (!qdev->msi_x_entry) {
2687 irq_type = MSI_IRQ;
2688 goto msi;
2689 }
2690
2691 for (i = 0; i < qdev->rx_ring_count; i++)
2692 qdev->msi_x_entry[i].entry = i;
2693
2694 if (!pci_enable_msix
2695 (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2696 set_bit(QL_MSIX_ENABLED, &qdev->flags);
2697 qdev->intr_count = qdev->rx_ring_count;
2698 QPRINTK(qdev, IFUP, INFO,
2699 "MSI-X Enabled, got %d vectors.\n",
2700 qdev->intr_count);
2701 return;
2702 } else {
2703 kfree(qdev->msi_x_entry);
2704 qdev->msi_x_entry = NULL;
2705 QPRINTK(qdev, IFUP, WARNING,
2706 "MSI-X Enable failed, trying MSI.\n");
2707 irq_type = MSI_IRQ;
2708 }
2709 }
2710msi:
2711 if (irq_type == MSI_IRQ) {
2712 if (!pci_enable_msi(qdev->pdev)) {
2713 set_bit(QL_MSI_ENABLED, &qdev->flags);
2714 QPRINTK(qdev, IFUP, INFO,
2715 "Running with MSI interrupts.\n");
2716 return;
2717 }
2718 }
2719 irq_type = LEG_IRQ;
c4e84bde
RM		 2720 QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2721}
2722
2723/*
2724 * Here we build the intr_context structures based on
2725 * our rx_ring count and intr vector count.
2726 * The intr_context structure is used to hook each vector
2727 * to possibly different handlers.
2728 */
2729static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2730{
2731 int i = 0;
2732 struct intr_context *intr_context = &qdev->intr_context[0];
2733
2734 ql_enable_msix(qdev);
2735
2736 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2737 /* Each rx_ring has it's
2738 * own intr_context since we have separate
2739 * vectors for each queue.
2740 * This only true when MSI-X is enabled.
2741 */
2742 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2743 qdev->rx_ring[i].irq = i;
2744 intr_context->intr = i;
2745 intr_context->qdev = qdev;
2746 /*
2747 * We set up each vectors enable/disable/read bits so
2748 * there's no bit/mask calculations in the critical path.
2749 */
2750 intr_context->intr_en_mask =
2751 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2752 INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2753 | i;
2754 intr_context->intr_dis_mask =
2755 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2756 INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2757 INTR_EN_IHD | i;
2758 intr_context->intr_read_mask =
2759 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2760 INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2761 i;
2762
2763 if (i == 0) {
2764 /*
2765 * Default queue handles bcast/mcast plus
2766 * async events. Needs buffers.
2767 */
2768 intr_context->handler = qlge_isr;
2769 sprintf(intr_context->name, "%s-default-queue",
2770 qdev->ndev->name);
2771 } else if (i < qdev->rss_ring_first_cq_id) {
2772 /*
2773 * Outbound queue is for outbound completions only.
2774 */
2775 intr_context->handler = qlge_msix_tx_isr;
2776 sprintf(intr_context->name, "%s-txq-%d",
2777 qdev->ndev->name, i);
2778 } else {
2779 /*
2780 * Inbound queues handle unicast frames only.
2781 */
2782 intr_context->handler = qlge_msix_rx_isr;
2783 sprintf(intr_context->name, "%s-rxq-%d",
2784 qdev->ndev->name, i);
2785 }
2786 }
2787 } else {
2788 /*
2789 * All rx_rings use the same intr_context since
2790 * there is only one vector.
2791 */
2792 intr_context->intr = 0;
2793 intr_context->qdev = qdev;
2794 /*
2795 * We set up each vectors enable/disable/read bits so
2796 * there's no bit/mask calculations in the critical path.
2797 */
2798 intr_context->intr_en_mask =
2799 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2800 intr_context->intr_dis_mask =
2801 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2802 INTR_EN_TYPE_DISABLE;
2803 intr_context->intr_read_mask =
2804 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2805 /*
2806 * Single interrupt means one handler for all rings.
2807 */
2808 intr_context->handler = qlge_isr;
2809 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2810 for (i = 0; i < qdev->rx_ring_count; i++)
2811 qdev->rx_ring[i].irq = 0;
2812 }
2813}
2814
2815static void ql_free_irq(struct ql_adapter *qdev)
2816{
2817 int i;
2818 struct intr_context *intr_context = &qdev->intr_context[0];
2819
2820 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2821 if (intr_context->hooked) {
2822 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2823 free_irq(qdev->msi_x_entry[i].vector,
2824 &qdev->rx_ring[i]);
2825 QPRINTK(qdev, IFDOWN, ERR,
2826 "freeing msix interrupt %d.\n", i);
2827 } else {
2828 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
2829 QPRINTK(qdev, IFDOWN, ERR,
2830 "freeing msi interrupt %d.\n", i);
2831 }
2832 }
2833 }
2834 ql_disable_msix(qdev);
2835}
2836
2837static int ql_request_irq(struct ql_adapter *qdev)
2838{
2839 int i;
2840 int status = 0;
2841 struct pci_dev *pdev = qdev->pdev;
2842 struct intr_context *intr_context = &qdev->intr_context[0];
2843
2844 ql_resolve_queues_to_irqs(qdev);
2845
2846 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2847 atomic_set(&intr_context->irq_cnt, 0);
2848 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2849 status = request_irq(qdev->msi_x_entry[i].vector,
2850 intr_context->handler,
2851 0,
2852 intr_context->name,
2853 &qdev->rx_ring[i]);
2854 if (status) {
2855 QPRINTK(qdev, IFUP, ERR,
2856 "Failed request for MSIX interrupt %d.\n",
2857 i);
2858 goto err_irq;
2859 } else {
2860 QPRINTK(qdev, IFUP, INFO,
2861 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2862 i,
2863 qdev->rx_ring[i].type ==
2864 DEFAULT_Q ? "DEFAULT_Q" : "",
2865 qdev->rx_ring[i].type ==
2866 TX_Q ? "TX_Q" : "",
2867 qdev->rx_ring[i].type ==
2868 RX_Q ? "RX_Q" : "", intr_context->name);
2869 }
2870 } else {
2871 QPRINTK(qdev, IFUP, DEBUG,
2872 "trying msi or legacy interrupts.\n");
2873 QPRINTK(qdev, IFUP, DEBUG,
2874 "%s: irq = %d.\n", __func__, pdev->irq);
2875 QPRINTK(qdev, IFUP, DEBUG,
2876 "%s: context->name = %s.\n", __func__,
2877 intr_context->name);
2878 QPRINTK(qdev, IFUP, DEBUG,
2879 "%s: dev_id = 0x%p.\n", __func__,
2880 &qdev->rx_ring[0]);
2881 status =
2882 request_irq(pdev->irq, qlge_isr,
2883 test_bit(QL_MSI_ENABLED,
2884 &qdev->
2885 flags) ? 0 : IRQF_SHARED,
2886 intr_context->name, &qdev->rx_ring[0]);
2887 if (status)
2888 goto err_irq;
2889
2890 QPRINTK(qdev, IFUP, ERR,
2891 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2892 i,
2893 qdev->rx_ring[0].type ==
2894 DEFAULT_Q ? "DEFAULT_Q" : "",
2895 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
2896 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
2897 intr_context->name);
2898 }
2899 intr_context->hooked = 1;
2900 }
2901 return status;
2902err_irq:
2903 QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
2904 ql_free_irq(qdev);
2905 return status;
2906}
2907
2908static int ql_start_rss(struct ql_adapter *qdev)
2909{
2910 struct ricb *ricb = &qdev->ricb;
2911 int status = 0;
2912 int i;
2913 u8 *hash_id = (u8 *) ricb->hash_cq_id;
2914
2915 memset((void *)ricb, 0, sizeof(ricb));
2916
2917 ricb->base_cq = qdev->rss_ring_first_cq_id | RSS_L4K;
2918 ricb->flags =
2919 (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
2920 RSS_RT6);
2921 ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
2922
2923 /*
2924 * Fill out the Indirection Table.
2925 */
2926 for (i = 0; i < 32; i++)
2927 hash_id[i] = i & 1;
2928
2929 /*
2930 * Random values for the IPv6 and IPv4 Hash Keys.
2931 */
2932 get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
2933 get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
2934
2935 QPRINTK(qdev, IFUP, INFO, "Initializing RSS.\n");
2936
2937 status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
2938 if (status) {
2939 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
2940 return status;
2941 }
2942 QPRINTK(qdev, IFUP, INFO, "Successfully loaded RICB.\n");
2943 return status;
2944}
2945
2946/* Initialize the frame-to-queue routing. */
2947static int ql_route_initialize(struct ql_adapter *qdev)
2948{
2949 int status = 0;
2950 int i;
2951
2952 /* Clear all the entries in the routing table. */
2953 for (i = 0; i < 16; i++) {
2954 status = ql_set_routing_reg(qdev, i, 0, 0);
2955 if (status) {
2956 QPRINTK(qdev, IFUP, ERR,
2957 "Failed to init routing register for CAM packets.\n");
2958 return status;
2959 }
2960 }
2961
2962 status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
2963 if (status) {
2964 QPRINTK(qdev, IFUP, ERR,
2965 "Failed to init routing register for error packets.\n");
2966 return status;
2967 }
2968 status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
2969 if (status) {
2970 QPRINTK(qdev, IFUP, ERR,
2971 "Failed to init routing register for broadcast packets.\n");
2972 return status;
2973 }
2974 /* If we have more than one inbound queue, then turn on RSS in the
2975 * routing block.
2976 */
2977 if (qdev->rss_ring_count > 1) {
2978 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
2979 RT_IDX_RSS_MATCH, 1);
2980 if (status) {
2981 QPRINTK(qdev, IFUP, ERR,
2982 "Failed to init routing register for MATCH RSS packets.\n");
2983 return status;
2984 }
2985 }
2986
2987 status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
2988 RT_IDX_CAM_HIT, 1);
2989 if (status) {
2990 QPRINTK(qdev, IFUP, ERR,
2991 "Failed to init routing register for CAM packets.\n");
2992 return status;
2993 }
2994 return status;
2995}
2996
2997static int ql_adapter_initialize(struct ql_adapter *qdev)
2998{
2999 u32 value, mask;
3000 int i;
3001 int status = 0;
3002
3003 /*
3004 * Set up the System register to halt on errors.
3005 */
3006 value = SYS_EFE | SYS_FAE;
3007 mask = value << 16;
3008 ql_write32(qdev, SYS, mask | value);
3009
3010 /* Set the default queue. */
3011 value = NIC_RCV_CFG_DFQ;
3012 mask = NIC_RCV_CFG_DFQ_MASK;
3013 ql_write32(qdev, NIC_RCV_CFG, (mask | value));
3014
3015 /* Set the MPI interrupt to enabled. */
3016 ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
3017
3018 /* Enable the function, set pagesize, enable error checking. */
3019 value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
3020 FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
3021
3022 /* Set/clear header splitting. */
3023 mask = FSC_VM_PAGESIZE_MASK |
3024 FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3025 ql_write32(qdev, FSC, mask | value);
3026
3027 ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
3028 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
3029
3030 /* Start up the rx queues. */
3031 for (i = 0; i < qdev->rx_ring_count; i++) {
3032 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3033 if (status) {
3034 QPRINTK(qdev, IFUP, ERR,
3035 "Failed to start rx ring[%d].\n", i);
3036 return status;
3037 }
3038 }
3039
3040 /* If there is more than one inbound completion queue
3041 * then download a RICB to configure RSS.
3042 */
3043 if (qdev->rss_ring_count > 1) {
3044 status = ql_start_rss(qdev);
3045 if (status) {
3046 QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
3047 return status;
3048 }
3049 }
3050
3051 /* Start up the tx queues. */
3052 for (i = 0; i < qdev->tx_ring_count; i++) {
3053 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3054 if (status) {
3055 QPRINTK(qdev, IFUP, ERR,
3056 "Failed to start tx ring[%d].\n", i);
3057 return status;
3058 }
3059 }
3060
3061 status = ql_port_initialize(qdev);
3062 if (status) {
3063 QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3064 return status;
3065 }
3066
3067 status = ql_set_mac_addr_reg(qdev, (u8 *) qdev->ndev->perm_addr,
3068 MAC_ADDR_TYPE_CAM_MAC, qdev->func);
3069 if (status) {
3070 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
3071 return status;
3072 }
3073
3074 status = ql_route_initialize(qdev);
3075 if (status) {
3076 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
3077 return status;
3078 }
3079
3080 /* Start NAPI for the RSS queues. */
3081 for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
3082 QPRINTK(qdev, IFUP, INFO, "Enabling NAPI for rx_ring[%d].\n",
3083 i);
3084 napi_enable(&qdev->rx_ring[i].napi);
3085 }
3086
3087 return status;
3088}
3089
3090/* Issue soft reset to chip. */
3091static int ql_adapter_reset(struct ql_adapter *qdev)
3092{
3093 u32 value;
3094 int max_wait_time;
3095 int status = 0;
3096 int resetCnt = 0;
3097
3098#define MAX_RESET_CNT 1
3099issueReset:
3100 resetCnt++;
3101 QPRINTK(qdev, IFDOWN, DEBUG, "Issue soft reset to chip.\n");
3102 ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3103 /* Wait for reset to complete. */
3104 max_wait_time = 3;
3105 QPRINTK(qdev, IFDOWN, DEBUG, "Wait %d seconds for reset to complete.\n",
3106 max_wait_time);
3107 do {
3108 value = ql_read32(qdev, RST_FO);
3109 if ((value & RST_FO_FR) == 0)
3110 break;
3111
3112 ssleep(1);
3113 } while ((--max_wait_time));
3114 if (value & RST_FO_FR) {
3115 QPRINTK(qdev, IFDOWN, ERR,
3116 "Stuck in SoftReset: FSC_SR:0x%08x\n", value);
3117 if (resetCnt < MAX_RESET_CNT)
3118 goto issueReset;
3119 }
3120 if (max_wait_time == 0) {
3121 status = -ETIMEDOUT;
3122 QPRINTK(qdev, IFDOWN, ERR,
3123 "ETIMEOUT!!! errored out of resetting the chip!\n");
3124 }
3125
3126 return status;
3127}
3128
3129static void ql_display_dev_info(struct net_device *ndev)
3130{
3131 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3132
3133 QPRINTK(qdev, PROBE, INFO,
3134 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3135 "XG Roll = %d, XG Rev = %d.\n",
3136 qdev->func,
3137 qdev->chip_rev_id & 0x0000000f,
3138 qdev->chip_rev_id >> 4 & 0x0000000f,
3139 qdev->chip_rev_id >> 8 & 0x0000000f,
3140 qdev->chip_rev_id >> 12 & 0x0000000f);
7c510e4b 3141 QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
c4e84bde
RM		 3142}
3143
3144static int ql_adapter_down(struct ql_adapter *qdev)
3145{
3146 struct net_device *ndev = qdev->ndev;
3147 int i, status = 0;
3148 struct rx_ring *rx_ring;
3149
3150 netif_stop_queue(ndev);
3151 netif_carrier_off(ndev);
3152
3153 cancel_delayed_work_sync(&qdev->asic_reset_work);
3154 cancel_delayed_work_sync(&qdev->mpi_reset_work);
3155 cancel_delayed_work_sync(&qdev->mpi_work);
3156
3157 /* The default queue at index 0 is always processed in
3158 * a workqueue.
3159 */
3160 cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3161
3162 /* The rest of the rx_rings are processed in
3163 * a workqueue only if it's a single interrupt
3164 * environment (MSI/Legacy).
3165 */
c062076c 3166 for (i = 1; i < qdev->rx_ring_count; i++) {
c4e84bde
RM		 3167 rx_ring = &qdev->rx_ring[i];
3168 /* Only the RSS rings use NAPI on multi irq
3169 * environment. Outbound completion processing
3170 * is done in interrupt context.
3171 */
3172 if (i >= qdev->rss_ring_first_cq_id) {
3173 napi_disable(&rx_ring->napi);
3174 } else {
3175 cancel_delayed_work_sync(&rx_ring->rx_work);
3176 }
3177 }
3178
3179 clear_bit(QL_ADAPTER_UP, &qdev->flags);
3180
3181 ql_disable_interrupts(qdev);
3182
3183 ql_tx_ring_clean(qdev);
3184
3185 spin_lock(&qdev->hw_lock);
3186 status = ql_adapter_reset(qdev);
3187 if (status)
3188 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3189 qdev->func);
3190 spin_unlock(&qdev->hw_lock);
3191 return status;
3192}
3193
3194static int ql_adapter_up(struct ql_adapter *qdev)
3195{
3196 int err = 0;
3197
3198 spin_lock(&qdev->hw_lock);
3199 err = ql_adapter_initialize(qdev);
3200 if (err) {
3201 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3202 spin_unlock(&qdev->hw_lock);
3203 goto err_init;
3204 }
3205 spin_unlock(&qdev->hw_lock);
3206 set_bit(QL_ADAPTER_UP, &qdev->flags);
3207 ql_enable_interrupts(qdev);
3208 ql_enable_all_completion_interrupts(qdev);
3209 if ((ql_read32(qdev, STS) & qdev->port_init)) {
3210 netif_carrier_on(qdev->ndev);
3211 netif_start_queue(qdev->ndev);
3212 }
3213
3214 return 0;
3215err_init:
3216 ql_adapter_reset(qdev);
3217 return err;
3218}
3219
3220static int ql_cycle_adapter(struct ql_adapter *qdev)
3221{
3222 int status;
3223
3224 status = ql_adapter_down(qdev);
3225 if (status)
3226 goto error;
3227
3228 status = ql_adapter_up(qdev);
3229 if (status)
3230 goto error;
3231
3232 return status;
3233error:
3234 QPRINTK(qdev, IFUP, ALERT,
3235 "Driver up/down cycle failed, closing device\n");
3236 rtnl_lock();
3237 dev_close(qdev->ndev);
3238 rtnl_unlock();
3239 return status;
3240}
3241
3242static void ql_release_adapter_resources(struct ql_adapter *qdev)
3243{
3244 ql_free_mem_resources(qdev);
3245 ql_free_irq(qdev);
3246}
3247
3248static int ql_get_adapter_resources(struct ql_adapter *qdev)
3249{
3250 int status = 0;
3251
3252 if (ql_alloc_mem_resources(qdev)) {
3253 QPRINTK(qdev, IFUP, ERR, "Unable to allocate memory.\n");
3254 return -ENOMEM;
3255 }
3256 status = ql_request_irq(qdev);
3257 if (status)
3258 goto err_irq;
3259 return status;
3260err_irq:
3261 ql_free_mem_resources(qdev);
3262 return status;
3263}
3264
3265static int qlge_close(struct net_device *ndev)
3266{
3267 struct ql_adapter *qdev = netdev_priv(ndev);
3268
3269 /*
3270 * Wait for device to recover from a reset.
3271 * (Rarely happens, but possible.)
3272 */
3273 while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3274 msleep(1);
3275 ql_adapter_down(qdev);
3276 ql_release_adapter_resources(qdev);
3277 ql_free_ring_cb(qdev);
3278 return 0;
3279}
3280
3281static int ql_configure_rings(struct ql_adapter *qdev)
3282{
3283 int i;
3284 struct rx_ring *rx_ring;
3285 struct tx_ring *tx_ring;
3286 int cpu_cnt = num_online_cpus();
3287
3288 /*
3289 * For each processor present we allocate one
3290 * rx_ring for outbound completions, and one
3291 * rx_ring for inbound completions. Plus there is
3292 * always the one default queue. For the CPU
3293 * counts we end up with the following rx_rings:
3294 * rx_ring count =
3295 * one default queue +
3296 * (CPU count * outbound completion rx_ring) +
3297 * (CPU count * inbound (RSS) completion rx_ring)
3298 * To keep it simple we limit the total number of
3299 * queues to < 32, so we truncate CPU to 8.
3300 * This limitation can be removed when requested.
3301 */
3302
3303 if (cpu_cnt > 8)
3304 cpu_cnt = 8;
3305
3306 /*
3307 * rx_ring[0] is always the default queue.
3308 */
3309 /* Allocate outbound completion ring for each CPU. */
3310 qdev->tx_ring_count = cpu_cnt;
3311 /* Allocate inbound completion (RSS) ring for each CPU. */
3312 qdev->rss_ring_count = cpu_cnt;
3313 /* cq_id for the first inbound ring handler. */
3314 qdev->rss_ring_first_cq_id = cpu_cnt + 1;
3315 /*
3316 * qdev->rx_ring_count:
3317 * Total number of rx_rings. This includes the one
3318 * default queue, a number of outbound completion
3319 * handler rx_rings, and the number of inbound
3320 * completion handler rx_rings.
3321 */
3322 qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1;
3323
3324 if (ql_alloc_ring_cb(qdev))
3325 return -ENOMEM;
3326
3327 for (i = 0; i < qdev->tx_ring_count; i++) {
3328 tx_ring = &qdev->tx_ring[i];
3329 memset((void *)tx_ring, 0, sizeof(tx_ring));
3330 tx_ring->qdev = qdev;
3331 tx_ring->wq_id = i;
3332 tx_ring->wq_len = qdev->tx_ring_size;
3333 tx_ring->wq_size =
3334 tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3335
3336 /*
3337 * The completion queue ID for the tx rings start
3338 * immediately after the default Q ID, which is zero.
3339 */
3340 tx_ring->cq_id = i + 1;
3341 }
3342
3343 for (i = 0; i < qdev->rx_ring_count; i++) {
3344 rx_ring = &qdev->rx_ring[i];
3345 memset((void *)rx_ring, 0, sizeof(rx_ring));
3346 rx_ring->qdev = qdev;
3347 rx_ring->cq_id = i;
3348 rx_ring->cpu = i % cpu_cnt; /* CPU to run handler on. */
3349 if (i == 0) { /* Default queue at index 0. */
3350 /*
3351 * Default queue handles bcast/mcast plus
3352 * async events. Needs buffers.
3353 */
3354 rx_ring->cq_len = qdev->rx_ring_size;
3355 rx_ring->cq_size =
3356 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3357 rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3358 rx_ring->lbq_size =
3359 rx_ring->lbq_len * sizeof(struct bq_element);
3360 rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3361 rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3362 rx_ring->sbq_size =
3363 rx_ring->sbq_len * sizeof(struct bq_element);
3364 rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3365 rx_ring->type = DEFAULT_Q;
3366 } else if (i < qdev->rss_ring_first_cq_id) {
3367 /*
3368 * Outbound queue handles outbound completions only.
3369 */
3370 /* outbound cq is same size as tx_ring it services. */
3371 rx_ring->cq_len = qdev->tx_ring_size;
3372 rx_ring->cq_size =
3373 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3374 rx_ring->lbq_len = 0;
3375 rx_ring->lbq_size = 0;
3376 rx_ring->lbq_buf_size = 0;
3377 rx_ring->sbq_len = 0;
3378 rx_ring->sbq_size = 0;
3379 rx_ring->sbq_buf_size = 0;
3380 rx_ring->type = TX_Q;
3381 } else { /* Inbound completions (RSS) queues */
3382 /*
3383 * Inbound queues handle unicast frames only.
3384 */
3385 rx_ring->cq_len = qdev->rx_ring_size;
3386 rx_ring->cq_size =
3387 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3388 rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3389 rx_ring->lbq_size =
3390 rx_ring->lbq_len * sizeof(struct bq_element);
3391 rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3392 rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3393 rx_ring->sbq_size =
3394 rx_ring->sbq_len * sizeof(struct bq_element);
3395 rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3396 rx_ring->type = RX_Q;
3397 }
3398 }
3399 return 0;
3400}
3401
3402static int qlge_open(struct net_device *ndev)
3403{
3404 int err = 0;
3405 struct ql_adapter *qdev = netdev_priv(ndev);
3406
3407 err = ql_configure_rings(qdev);
3408 if (err)
3409 return err;
3410
3411 err = ql_get_adapter_resources(qdev);
3412 if (err)
3413 goto error_up;
3414
3415 err = ql_adapter_up(qdev);
3416 if (err)
3417 goto error_up;
3418
3419 return err;
3420
3421error_up:
3422 ql_release_adapter_resources(qdev);
3423 ql_free_ring_cb(qdev);
3424 return err;
3425}
3426
3427static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3428{
3429 struct ql_adapter *qdev = netdev_priv(ndev);
3430
3431 if (ndev->mtu == 1500 && new_mtu == 9000) {
3432 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3433 } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3434 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3435 } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3436 (ndev->mtu == 9000 && new_mtu == 9000)) {
3437 return 0;
3438 } else
3439 return -EINVAL;
3440 ndev->mtu = new_mtu;
3441 return 0;
3442}
3443
3444static struct net_device_stats *qlge_get_stats(struct net_device
3445 *ndev)
3446{
3447 struct ql_adapter *qdev = netdev_priv(ndev);
3448 return &qdev->stats;
3449}
3450
3451static void qlge_set_multicast_list(struct net_device *ndev)
3452{
3453 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3454 struct dev_mc_list *mc_ptr;
3455 int i;
3456
3457 spin_lock(&qdev->hw_lock);
3458 /*
3459 * Set or clear promiscuous mode if a
3460 * transition is taking place.
3461 */
3462 if (ndev->flags & IFF_PROMISC) {
3463 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3464 if (ql_set_routing_reg
3465 (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3466 QPRINTK(qdev, HW, ERR,
3467 "Failed to set promiscous mode.\n");
3468 } else {
3469 set_bit(QL_PROMISCUOUS, &qdev->flags);
3470 }
3471 }
3472 } else {
3473 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3474 if (ql_set_routing_reg
3475 (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3476 QPRINTK(qdev, HW, ERR,
3477 "Failed to clear promiscous mode.\n");
3478 } else {
3479 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3480 }
3481 }
3482 }
3483
3484 /*
3485 * Set or clear all multicast mode if a
3486 * transition is taking place.
3487 */
3488 if ((ndev->flags & IFF_ALLMULTI) ||
3489 (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3490 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3491 if (ql_set_routing_reg
3492 (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3493 QPRINTK(qdev, HW, ERR,
3494 "Failed to set all-multi mode.\n");
3495 } else {
3496 set_bit(QL_ALLMULTI, &qdev->flags);
3497 }
3498 }
3499 } else {
3500 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3501 if (ql_set_routing_reg
3502 (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3503 QPRINTK(qdev, HW, ERR,
3504 "Failed to clear all-multi mode.\n");
3505 } else {
3506 clear_bit(QL_ALLMULTI, &qdev->flags);
3507 }
3508 }
3509 }
3510
3511 if (ndev->mc_count) {
3512 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3513 i++, mc_ptr = mc_ptr->next)
3514 if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3515 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3516 QPRINTK(qdev, HW, ERR,
3517 "Failed to loadmulticast address.\n");
3518 goto exit;
3519 }
3520 if (ql_set_routing_reg
3521 (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3522 QPRINTK(qdev, HW, ERR,
3523 "Failed to set multicast match mode.\n");
3524 } else {
3525 set_bit(QL_ALLMULTI, &qdev->flags);
3526 }
3527 }
3528exit:
3529 spin_unlock(&qdev->hw_lock);
3530}
3531
3532static int qlge_set_mac_address(struct net_device *ndev, void *p)
3533{
3534 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3535 struct sockaddr *addr = p;
8668ae92 3536 int ret = 0;
c4e84bde
RM		 3537
3538 if (netif_running(ndev))
3539 return -EBUSY;
3540
3541 if (!is_valid_ether_addr(addr->sa_data))
3542 return -EADDRNOTAVAIL;
3543 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3544
3545 spin_lock(&qdev->hw_lock);
3546 if (ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3547 MAC_ADDR_TYPE_CAM_MAC, qdev->func)) {/* Unicast */
3548 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
8668ae92 3549 ret = -1;
c4e84bde
RM		 3550 }
3551 spin_unlock(&qdev->hw_lock);
3552
8668ae92 3553 return ret;
c4e84bde
RM		 3554}
3555
3556static void qlge_tx_timeout(struct net_device *ndev)
3557{
3558 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3559 queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
3560}
3561
3562static void ql_asic_reset_work(struct work_struct *work)
3563{
3564 struct ql_adapter *qdev =
3565 container_of(work, struct ql_adapter, asic_reset_work.work);
3566 ql_cycle_adapter(qdev);
3567}
3568
3569static void ql_get_board_info(struct ql_adapter *qdev)
3570{
3571 qdev->func =
3572 (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3573 if (qdev->func) {
3574 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3575 qdev->port_link_up = STS_PL1;
3576 qdev->port_init = STS_PI1;
3577 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3578 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3579 } else {
3580 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3581 qdev->port_link_up = STS_PL0;
3582 qdev->port_init = STS_PI0;
3583 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3584 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3585 }
3586 qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3587}
3588
3589static void ql_release_all(struct pci_dev *pdev)
3590{
3591 struct net_device *ndev = pci_get_drvdata(pdev);
3592 struct ql_adapter *qdev = netdev_priv(ndev);
3593
3594 if (qdev->workqueue) {
3595 destroy_workqueue(qdev->workqueue);
3596 qdev->workqueue = NULL;
3597 }
3598 if (qdev->q_workqueue) {
3599 destroy_workqueue(qdev->q_workqueue);
3600 qdev->q_workqueue = NULL;
3601 }
3602 if (qdev->reg_base)
8668ae92 3603 iounmap(qdev->reg_base);
c4e84bde
RM		 3604 if (qdev->doorbell_area)
3605 iounmap(qdev->doorbell_area);
3606 pci_release_regions(pdev);
3607 pci_set_drvdata(pdev, NULL);
3608}
3609
3610static int __devinit ql_init_device(struct pci_dev *pdev,
3611 struct net_device *ndev, int cards_found)
3612{
3613 struct ql_adapter *qdev = netdev_priv(ndev);
3614 int pos, err = 0;
3615 u16 val16;
3616
3617 memset((void *)qdev, 0, sizeof(qdev));
3618 err = pci_enable_device(pdev);
3619 if (err) {
3620 dev_err(&pdev->dev, "PCI device enable failed.\n");
3621 return err;
3622 }
3623
3624 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3625 if (pos <= 0) {
3626 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3627 "aborting.\n");
3628 goto err_out;
3629 } else {
3630 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3631 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3632 val16 |= (PCI_EXP_DEVCTL_CERE |
3633 PCI_EXP_DEVCTL_NFERE |
3634 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3635 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3636 }
3637
3638 err = pci_request_regions(pdev, DRV_NAME);
3639 if (err) {
3640 dev_err(&pdev->dev, "PCI region request failed.\n");
3641 goto err_out;
3642 }
3643
3644 pci_set_master(pdev);
3645 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3646 set_bit(QL_DMA64, &qdev->flags);
3647 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3648 } else {
3649 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3650 if (!err)
3651 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3652 }
3653
3654 if (err) {
3655 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3656 goto err_out;
3657 }
3658
3659 pci_set_drvdata(pdev, ndev);
3660 qdev->reg_base =
3661 ioremap_nocache(pci_resource_start(pdev, 1),
3662 pci_resource_len(pdev, 1));
3663 if (!qdev->reg_base) {
3664 dev_err(&pdev->dev, "Register mapping failed.\n");
3665 err = -ENOMEM;
3666 goto err_out;
3667 }
3668
3669 qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3670 qdev->doorbell_area =
3671 ioremap_nocache(pci_resource_start(pdev, 3),
3672 pci_resource_len(pdev, 3));
3673 if (!qdev->doorbell_area) {
3674 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3675 err = -ENOMEM;
3676 goto err_out;
3677 }
3678
3679 ql_get_board_info(qdev);
3680 qdev->ndev = ndev;
3681 qdev->pdev = pdev;
3682 qdev->msg_enable = netif_msg_init(debug, default_msg);
3683 spin_lock_init(&qdev->hw_lock);
3684 spin_lock_init(&qdev->stats_lock);
3685
3686 /* make sure the EEPROM is good */
3687 err = ql_get_flash_params(qdev);
3688 if (err) {
3689 dev_err(&pdev->dev, "Invalid FLASH.\n");
3690 goto err_out;
3691 }
3692
3693 if (!is_valid_ether_addr(qdev->flash.mac_addr))
3694 goto err_out;
3695
3696 memcpy(ndev->dev_addr, qdev->flash.mac_addr, ndev->addr_len);
3697 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3698
3699 /* Set up the default ring sizes. */
3700 qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3701 qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3702
3703 /* Set up the coalescing parameters. */
3704 qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3705 qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3706 qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3707 qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3708
3709 /*
3710 * Set up the operating parameters.
3711 */
3712 qdev->rx_csum = 1;
3713
3714 qdev->q_workqueue = create_workqueue(ndev->name);
3715 qdev->workqueue = create_singlethread_workqueue(ndev->name);
3716 INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3717 INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3718 INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3719
3720 if (!cards_found) {
3721 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3722 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3723 DRV_NAME, DRV_VERSION);
3724 }
3725 return 0;
3726err_out:
3727 ql_release_all(pdev);
3728 pci_disable_device(pdev);
3729 return err;
3730}
3731
25ed7849
SH		 3732
3733static const struct net_device_ops qlge_netdev_ops = {
3734 .ndo_open = qlge_open,
3735 .ndo_stop = qlge_close,
3736 .ndo_start_xmit = qlge_send,
3737 .ndo_change_mtu = qlge_change_mtu,
3738 .ndo_get_stats = qlge_get_stats,
3739 .ndo_set_multicast_list = qlge_set_multicast_list,
3740 .ndo_set_mac_address = qlge_set_mac_address,
3741 .ndo_validate_addr = eth_validate_addr,
3742 .ndo_tx_timeout = qlge_tx_timeout,
3743 .ndo_vlan_rx_register = ql_vlan_rx_register,
3744 .ndo_vlan_rx_add_vid = ql_vlan_rx_add_vid,
3745 .ndo_vlan_rx_kill_vid = ql_vlan_rx_kill_vid,
3746};
3747
c4e84bde
RM		 3748static int __devinit qlge_probe(struct pci_dev *pdev,
3749 const struct pci_device_id *pci_entry)
3750{
3751 struct net_device *ndev = NULL;
3752 struct ql_adapter *qdev = NULL;
3753 static int cards_found = 0;
3754 int err = 0;
3755
3756 ndev = alloc_etherdev(sizeof(struct ql_adapter));
3757 if (!ndev)
3758 return -ENOMEM;
3759
3760 err = ql_init_device(pdev, ndev, cards_found);
3761 if (err < 0) {
3762 free_netdev(ndev);
3763 return err;
3764 }
3765
3766 qdev = netdev_priv(ndev);
3767 SET_NETDEV_DEV(ndev, &pdev->dev);
3768 ndev->features = (0
3769 | NETIF_F_IP_CSUM
3770 | NETIF_F_SG
3771 | NETIF_F_TSO
3772 | NETIF_F_TSO6
3773 | NETIF_F_TSO_ECN
3774 | NETIF_F_HW_VLAN_TX
3775 | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3776
3777 if (test_bit(QL_DMA64, &qdev->flags))
3778 ndev->features |= NETIF_F_HIGHDMA;
3779
3780 /*
3781 * Set up net_device structure.
3782 */
3783 ndev->tx_queue_len = qdev->tx_ring_size;
3784 ndev->irq = pdev->irq;
25ed7849
SH		 3785
3786 ndev->netdev_ops = &qlge_netdev_ops;
c4e84bde 3787 SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
c4e84bde 3788 ndev->watchdog_timeo = 10 * HZ;
25ed7849 3789
c4e84bde
RM		 3790 err = register_netdev(ndev);
3791 if (err) {
3792 dev_err(&pdev->dev, "net device registration failed.\n");
3793 ql_release_all(pdev);
3794 pci_disable_device(pdev);
3795 return err;
3796 }
3797 netif_carrier_off(ndev);
3798 netif_stop_queue(ndev);
3799 ql_display_dev_info(ndev);
3800 cards_found++;
3801 return 0;
3802}
3803
3804static void __devexit qlge_remove(struct pci_dev *pdev)
3805{
3806 struct net_device *ndev = pci_get_drvdata(pdev);
3807 unregister_netdev(ndev);
3808 ql_release_all(pdev);
3809 pci_disable_device(pdev);
3810 free_netdev(ndev);
3811}
3812
3813/*
3814 * This callback is called by the PCI subsystem whenever
3815 * a PCI bus error is detected.
3816 */
3817static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
3818 enum pci_channel_state state)
3819{
3820 struct net_device *ndev = pci_get_drvdata(pdev);
3821 struct ql_adapter *qdev = netdev_priv(ndev);
3822
3823 if (netif_running(ndev))
3824 ql_adapter_down(qdev);
3825
3826 pci_disable_device(pdev);
3827
3828 /* Request a slot reset. */
3829 return PCI_ERS_RESULT_NEED_RESET;
3830}
3831
3832/*
3833 * This callback is called after the PCI buss has been reset.
3834 * Basically, this tries to restart the card from scratch.
3835 * This is a shortened version of the device probe/discovery code,
3836 * it resembles the first-half of the () routine.
3837 */
3838static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
3839{
3840 struct net_device *ndev = pci_get_drvdata(pdev);
3841 struct ql_adapter *qdev = netdev_priv(ndev);
3842
3843 if (pci_enable_device(pdev)) {
3844 QPRINTK(qdev, IFUP, ERR,
3845 "Cannot re-enable PCI device after reset.\n");
3846 return PCI_ERS_RESULT_DISCONNECT;
3847 }
3848
3849 pci_set_master(pdev);
3850
3851 netif_carrier_off(ndev);
3852 netif_stop_queue(ndev);
3853 ql_adapter_reset(qdev);
3854
3855 /* Make sure the EEPROM is good */
3856 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3857
3858 if (!is_valid_ether_addr(ndev->perm_addr)) {
3859 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
3860 return PCI_ERS_RESULT_DISCONNECT;
3861 }
3862
3863 return PCI_ERS_RESULT_RECOVERED;
3864}
3865
3866static void qlge_io_resume(struct pci_dev *pdev)
3867{
3868 struct net_device *ndev = pci_get_drvdata(pdev);
3869 struct ql_adapter *qdev = netdev_priv(ndev);
3870
3871 pci_set_master(pdev);
3872
3873 if (netif_running(ndev)) {
3874 if (ql_adapter_up(qdev)) {
3875 QPRINTK(qdev, IFUP, ERR,
3876 "Device initialization failed after reset.\n");
3877 return;
3878 }
3879 }
3880
3881 netif_device_attach(ndev);
3882}
3883
3884static struct pci_error_handlers qlge_err_handler = {
3885 .error_detected = qlge_io_error_detected,
3886 .slot_reset = qlge_io_slot_reset,
3887 .resume = qlge_io_resume,
3888};
3889
3890static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
3891{
3892 struct net_device *ndev = pci_get_drvdata(pdev);
3893 struct ql_adapter *qdev = netdev_priv(ndev);
3894 int err;
3895
3896 netif_device_detach(ndev);
3897
3898 if (netif_running(ndev)) {
3899 err = ql_adapter_down(qdev);
3900 if (!err)
3901 return err;
3902 }
3903
3904 err = pci_save_state(pdev);
3905 if (err)
3906 return err;
3907
3908 pci_disable_device(pdev);
3909
3910 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3911
3912 return 0;
3913}
3914
04da2cf9 3915#ifdef CONFIG_PM
c4e84bde
RM		 3916static int qlge_resume(struct pci_dev *pdev)
3917{
3918 struct net_device *ndev = pci_get_drvdata(pdev);
3919 struct ql_adapter *qdev = netdev_priv(ndev);
3920 int err;
3921
3922 pci_set_power_state(pdev, PCI_D0);
3923 pci_restore_state(pdev);
3924 err = pci_enable_device(pdev);
3925 if (err) {
3926 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
3927 return err;
3928 }
3929 pci_set_master(pdev);
3930
3931 pci_enable_wake(pdev, PCI_D3hot, 0);
3932 pci_enable_wake(pdev, PCI_D3cold, 0);
3933
3934 if (netif_running(ndev)) {
3935 err = ql_adapter_up(qdev);
3936 if (err)
3937 return err;
3938 }
3939
3940 netif_device_attach(ndev);
3941
3942 return 0;
3943}
04da2cf9 3944#endif /* CONFIG_PM */
c4e84bde
RM		 3945
3946static void qlge_shutdown(struct pci_dev *pdev)
3947{
3948 qlge_suspend(pdev, PMSG_SUSPEND);
3949}
3950
3951static struct pci_driver qlge_driver = {
3952 .name = DRV_NAME,
3953 .id_table = qlge_pci_tbl,
3954 .probe = qlge_probe,
3955 .remove = __devexit_p(qlge_remove),
3956#ifdef CONFIG_PM
3957 .suspend = qlge_suspend,
3958 .resume = qlge_resume,
3959#endif
3960 .shutdown = qlge_shutdown,
3961 .err_handler = &qlge_err_handler
3962};
3963
3964static int __init qlge_init_module(void)
3965{
3966 return pci_register_driver(&qlge_driver);
3967}
3968
3969static void __exit qlge_exit(void)
3970{
3971 pci_unregister_driver(&qlge_driver);
3972}
3973
3974module_init(qlge_init_module);
3975module_exit(qlge_exit);
kernel source for telekom puls (alcatel/mediatek)