[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / phy / icplus.c

/*
 * Driver for ICPlus PHYs
 *
 * Copyright (c) 2007 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/unistd.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/spinlock.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/phy.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>

MODULE_DESCRIPTION("ICPlus IP175C/IP101A/IP101G/IC1001 PHY drivers");
MODULE_AUTHOR("Michael Barkowski");
MODULE_LICENSE("GPL");

/* IP101A/G - IP1001 */
#define IP10XX_SPEC_CTRL_STATUS		16	/* Spec. Control Register */
#define IP1001_RXPHASE_SEL		(1<<0)	/* Add delay on RX_CLK */
#define IP1001_TXPHASE_SEL		(1<<1)	/* Add delay on TX_CLK */
#define IP1001_SPEC_CTRL_STATUS_2	20	/* IP1001 Spec. Control Reg 2 */
#define IP1001_APS_ON			11	/* IP1001 APS Mode  bit */
#define IP101A_G_APS_ON			2	/* IP101A/G APS Mode bit */
#define IP101A_G_IRQ_CONF_STATUS	0x11	/* Conf Info IRQ & Status Reg */
#define	IP101A_G_IRQ_PIN_USED		(1<<15) /* INTR pin used */
#define	IP101A_G_IRQ_DEFAULT		IP101A_G_IRQ_PIN_USED

static int ip175c_config_init(struct phy_device *phydev)
{
	int err, i;
	static int full_reset_performed = 0;

	if (full_reset_performed == 0) {

		/* master reset */
		err = mdiobus_write(phydev->bus, 30, 0, 0x175c);
		if (err < 0)
			return err;

		/* ensure no bus delays overlap reset period */
		err = mdiobus_read(phydev->bus, 30, 0);

		/* data sheet specifies reset period is 2 msec */
		mdelay(2);

		/* enable IP175C mode */
		err = mdiobus_write(phydev->bus, 29, 31, 0x175c);
		if (err < 0)
			return err;

		/* Set MII0 speed and duplex (in PHY mode) */
		err = mdiobus_write(phydev->bus, 29, 22, 0x420);
		if (err < 0)
			return err;

		/* reset switch ports */
		for (i = 0; i < 5; i++) {
			err = mdiobus_write(phydev->bus, i,
					    MII_BMCR, BMCR_RESET);
			if (err < 0)
				return err;
		}

		for (i = 0; i < 5; i++)
			err = mdiobus_read(phydev->bus, i, MII_BMCR);

		mdelay(2);

		full_reset_performed = 1;
	}

	if (phydev->addr != 4) {
		phydev->state = PHY_RUNNING;
		phydev->speed = SPEED_100;
		phydev->duplex = DUPLEX_FULL;
		phydev->link = 1;
		netif_carrier_on(phydev->attached_dev);
	}

	return 0;
}

static int ip1xx_reset(struct phy_device *phydev)
{
	int bmcr;

	/* Software Reset PHY */
	bmcr = phy_read(phydev, MII_BMCR);
	if (bmcr < 0)
		return bmcr;
	bmcr |= BMCR_RESET;
	bmcr = phy_write(phydev, MII_BMCR, bmcr);
	if (bmcr < 0)
		return bmcr;

	do {
		bmcr = phy_read(phydev, MII_BMCR);
		if (bmcr < 0)
			return bmcr;
	} while (bmcr & BMCR_RESET);

	return 0;
}

static int ip1001_config_init(struct phy_device *phydev)
{
	int c;

	c = ip1xx_reset(phydev);
	if (c < 0)
		return c;

	/* Enable Auto Power Saving mode */
	c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2);
	if (c < 0)
		return c;
	c |= IP1001_APS_ON;
	c = phy_write(phydev, IP1001_SPEC_CTRL_STATUS_2, c);
	if (c < 0)
		return c;

	if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {

		c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
		if (c < 0)
			return c;

		c &= ~(IP1001_RXPHASE_SEL | IP1001_TXPHASE_SEL);

		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
			c |= (IP1001_RXPHASE_SEL | IP1001_TXPHASE_SEL);
		else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
			c |= IP1001_RXPHASE_SEL;
		else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
			c |= IP1001_TXPHASE_SEL;

		c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
		if (c < 0)
			return c;
	}

	return 0;
}

static int ip101a_g_config_init(struct phy_device *phydev)
{
	int c;

	c = ip1xx_reset(phydev);
	if (c < 0)
		return c;

	/* INTR pin used: speed/link/duplex will cause an interrupt */
	c = phy_write(phydev, IP101A_G_IRQ_CONF_STATUS, IP101A_G_IRQ_DEFAULT);
	if (c < 0)
		return c;

	/* Enable Auto Power Saving mode */
	c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
	c |= IP101A_G_APS_ON;

	return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
}

static int ip175c_read_status(struct phy_device *phydev)
{
	if (phydev->addr == 4) /* WAN port */
		genphy_read_status(phydev);
	else
		/* Don't need to read status for switch ports */
		phydev->irq = PHY_IGNORE_INTERRUPT;

	return 0;
}

static int ip175c_config_aneg(struct phy_device *phydev)
{
	if (phydev->addr == 4) /* WAN port */
		genphy_config_aneg(phydev);

	return 0;
}

static int ip101a_g_ack_interrupt(struct phy_device *phydev)
{
	int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS);
	if (err < 0)
		return err;

	return 0;
}

static struct phy_driver icplus_driver[] = {
{
	.phy_id		= 0x02430d80,
	.name		= "ICPlus IP175C",
	.phy_id_mask	= 0x0ffffff0,
	.features	= PHY_BASIC_FEATURES,
	.config_init	= &ip175c_config_init,
	.config_aneg	= &ip175c_config_aneg,
	.read_status	= &ip175c_read_status,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= 0x02430d90,
	.name		= "ICPlus IP1001",
	.phy_id_mask	= 0x0ffffff0,
	.features	= PHY_GBIT_FEATURES | SUPPORTED_Pause |
			  SUPPORTED_Asym_Pause,
	.config_init	= &ip1001_config_init,
	.config_aneg	= &genphy_config_aneg,
	.read_status	= &genphy_read_status,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= 0x02430c54,
	.name		= "ICPlus IP101A/G",
	.phy_id_mask	= 0x0ffffff0,
	.features	= PHY_BASIC_FEATURES | SUPPORTED_Pause |
			  SUPPORTED_Asym_Pause,
	.flags		= PHY_HAS_INTERRUPT,
	.ack_interrupt	= ip101a_g_ack_interrupt,
	.config_init	= &ip101a_g_config_init,
	.config_aneg	= &genphy_config_aneg,
	.read_status	= &genphy_read_status,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE,},
} };

static int __init icplus_init(void)
{
	return phy_drivers_register(icplus_driver,
		ARRAY_SIZE(icplus_driver));
}

static void __exit icplus_exit(void)
{
	phy_drivers_unregister(icplus_driver,
		ARRAY_SIZE(icplus_driver));
}

module_init(icplus_init);
module_exit(icplus_exit);

static struct mdio_device_id __maybe_unused icplus_tbl[] = {
	{ 0x02430d80, 0x0ffffff0 },
	{ 0x02430d90, 0x0ffffff0 },
	{ 0x02430c54, 0x0ffffff0 },
	{ }
};

MODULE_DEVICE_TABLE(mdio, icplus_tbl);
Commit	Line	Data
0cefeeba MB	1	/*
	2	* Driver for ICPlus PHYs
	3	*
	4	* Copyright (c) 2007 Freescale Semiconductor, Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*
	11	*/
	12	#include <linux/kernel.h>
	13	#include <linux/string.h>
	14	#include <linux/errno.h>
	15	#include <linux/unistd.h>
0cefeeba MB	16	#include <linux/interrupt.h>
	17	#include <linux/init.h>
	18	#include <linux/delay.h>
	19	#include <linux/netdevice.h>
	20	#include <linux/etherdevice.h>
	21	#include <linux/skbuff.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/mm.h>
	24	#include <linux/module.h>
	25	#include <linux/mii.h>
	26	#include <linux/ethtool.h>
	27	#include <linux/phy.h>
	28
	29	#include <asm/io.h>
	30	#include <asm/irq.h>
	31	#include <asm/uaccess.h>
	32
e3e09f26	33	MODULE_DESCRIPTION("ICPlus IP175C/IP101A/IP101G/IC1001 PHY drivers");
0cefeeba MB	34	MODULE_AUTHOR("Michael Barkowski");
	35	MODULE_LICENSE("GPL");
	36
e3e09f26 GC	37	/* IP101A/G - IP1001 */
e3e09f26 GC	38	#define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */
b4a49631 SM	39	#define IP1001_RXPHASE_SEL (1<<0) /* Add delay on RX_CLK */
b4a49631 SM	40	#define IP1001_TXPHASE_SEL (1<<1) /* Add delay on TX_CLK */
e3e09f26	41	#define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */
e3e09f26 GC	42	#define IP1001_APS_ON 11 /* IP1001 APS Mode bit */
e3e09f26 GC	43	#define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */
996f7393	44	#define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */
9ec0db71 GC	45	#define IP101A_G_IRQ_PIN_USED (1<<15) /* INTR pin used */
9ec0db71 GC	46	#define IP101A_G_IRQ_DEFAULT IP101A_G_IRQ_PIN_USED
9c9b1f24	47
0cefeeba MB	48	static int ip175c_config_init(struct phy_device *phydev)
	49	{
	50	int err, i;
	51	static int full_reset_performed = 0;
	52
	53	if (full_reset_performed == 0) {
	54
	55	/* master reset */
76231e02	56	err = mdiobus_write(phydev->bus, 30, 0, 0x175c);
0cefeeba MB	57	if (err < 0)
	58	return err;
	59
	60	/* ensure no bus delays overlap reset period */
76231e02	61	err = mdiobus_read(phydev->bus, 30, 0);
0cefeeba MB	62
	63	/* data sheet specifies reset period is 2 msec */
	64	mdelay(2);
	65
	66	/* enable IP175C mode */
76231e02	67	err = mdiobus_write(phydev->bus, 29, 31, 0x175c);
0cefeeba MB	68	if (err < 0)
	69	return err;
	70
	71	/* Set MII0 speed and duplex (in PHY mode) */
76231e02	72	err = mdiobus_write(phydev->bus, 29, 22, 0x420);
0cefeeba MB	73	if (err < 0)
	74	return err;
	75
	76	/* reset switch ports */
	77	for (i = 0; i < 5; i++) {
76231e02 DD	78	err = mdiobus_write(phydev->bus, i,
76231e02 DD	79	MII_BMCR, BMCR_RESET);
0cefeeba MB	80	if (err < 0)
	81	return err;
	82	}
	83
	84	for (i = 0; i < 5; i++)
76231e02	85	err = mdiobus_read(phydev->bus, i, MII_BMCR);
0cefeeba MB	86
	87	mdelay(2);
	88
	89	full_reset_performed = 1;
	90	}
	91
	92	if (phydev->addr != 4) {
	93	phydev->state = PHY_RUNNING;
	94	phydev->speed = SPEED_100;
	95	phydev->duplex = DUPLEX_FULL;
	96	phydev->link = 1;
	97	netif_carrier_on(phydev->attached_dev);
	98	}
	99
	100	return 0;
	101	}
	102
9c9b1f24	103	static int ip1xx_reset(struct phy_device *phydev)
377ecca9	104	{
b8e3995a	105	int bmcr;
377ecca9 GC	106
377ecca9 GC	107	/* Software Reset PHY */
9c9b1f24	108	bmcr = phy_read(phydev, MII_BMCR);
b8e3995a DM	109	if (bmcr < 0)
b8e3995a DM	110	return bmcr;
9c9b1f24	111	bmcr \|= BMCR_RESET;
b8e3995a DM	112	bmcr = phy_write(phydev, MII_BMCR, bmcr);
	113	if (bmcr < 0)
	114	return bmcr;
377ecca9 GC	115
377ecca9 GC	116	do {
9c9b1f24	117	bmcr = phy_read(phydev, MII_BMCR);
b8e3995a DM	118	if (bmcr < 0)
b8e3995a DM	119	return bmcr;
9c9b1f24 GC	120	} while (bmcr & BMCR_RESET);
9c9b1f24 GC	121
b8e3995a	122	return 0;
9c9b1f24 GC	123	}
	124
	125	static int ip1001_config_init(struct phy_device *phydev)
	126	{
	127	int c;
	128
	129	c = ip1xx_reset(phydev);
	130	if (c < 0)
	131	return c;
	132
	133	/* Enable Auto Power Saving mode */
	134	c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2);
b8e3995a DM	135	if (c < 0)
b8e3995a DM	136	return c;
9c9b1f24	137	c \|= IP1001_APS_ON;
b8e3995a	138	c = phy_write(phydev, IP1001_SPEC_CTRL_STATUS_2, c);
9c9b1f24 GC	139	if (c < 0)
9c9b1f24 GC	140	return c;
377ecca9	141
b4a49631 SM	142	if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) \|\|
	143	(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) \|\|
	144	(phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) \|\|
	145	(phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
	146
a4886d52	147	c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
b8e3995a DM	148	if (c < 0)
	149	return c;
	150
b4a49631 SM	151	c &= ~(IP1001_RXPHASE_SEL \| IP1001_TXPHASE_SEL);
	152
	153	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
	154	c \|= (IP1001_RXPHASE_SEL \| IP1001_TXPHASE_SEL);
	155	else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
	156	c \|= IP1001_RXPHASE_SEL;
	157	else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
	158	c \|= IP1001_TXPHASE_SEL;
	159
a4886d52	160	c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
b8e3995a DM	161	if (c < 0)
b8e3995a DM	162	return c;
a4886d52	163	}
9c9b1f24	164
b8e3995a	165	return 0;
9c9b1f24 GC	166	}
9c9b1f24 GC	167
e3e09f26	168	static int ip101a_g_config_init(struct phy_device *phydev)
9c9b1f24 GC	169	{
9c9b1f24 GC	170	int c;
377ecca9	171
9c9b1f24 GC	172	c = ip1xx_reset(phydev);
	173	if (c < 0)
	174	return c;
	175
014f2ffd GC	176	/* INTR pin used: speed/link/duplex will cause an interrupt */
	177	c = phy_write(phydev, IP101A_G_IRQ_CONF_STATUS, IP101A_G_IRQ_DEFAULT);
	178	if (c < 0)
	179	return c;
	180
9c9b1f24 GC	181	/* Enable Auto Power Saving mode */
9c9b1f24 GC	182	c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
e3e09f26	183	c \|= IP101A_G_APS_ON;
b3300146 SK	184
b3300146 SK	185	return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
377ecca9 GC	186	}
377ecca9 GC	187
0cefeeba MB	188	static int ip175c_read_status(struct phy_device *phydev)
	189	{
	190	if (phydev->addr == 4) /* WAN port */
	191	genphy_read_status(phydev);
	192	else
	193	/* Don't need to read status for switch ports */
	194	phydev->irq = PHY_IGNORE_INTERRUPT;
	195
	196	return 0;
	197	}
	198
	199	static int ip175c_config_aneg(struct phy_device *phydev)
	200	{
	201	if (phydev->addr == 4) /* WAN port */
	202	genphy_config_aneg(phydev);
	203
	204	return 0;
	205	}
	206
996f7393 GC	207	static int ip101a_g_ack_interrupt(struct phy_device *phydev)
	208	{
	209	int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS);
	210	if (err < 0)
	211	return err;
	212
	213	return 0;
	214	}
	215
d5bf9071 CH	216	static struct phy_driver icplus_driver[] = {
d5bf9071 CH	217	{
0cefeeba MB	218	.phy_id = 0x02430d80,
	219	.name = "ICPlus IP175C",
	220	.phy_id_mask = 0x0ffffff0,
	221	.features = PHY_BASIC_FEATURES,
	222	.config_init = &ip175c_config_init,
	223	.config_aneg = &ip175c_config_aneg,
	224	.read_status = &ip175c_read_status,
dab10863 GC	225	.suspend = genphy_suspend,
dab10863 GC	226	.resume = genphy_resume,
0cefeeba	227	.driver = { .owner = THIS_MODULE,},
d5bf9071	228	}, {
377ecca9 GC	229	.phy_id = 0x02430d90,
	230	.name = "ICPlus IP1001",
	231	.phy_id_mask = 0x0ffffff0,
	232	.features = PHY_GBIT_FEATURES \| SUPPORTED_Pause \|
	233	SUPPORTED_Asym_Pause,
	234	.config_init = &ip1001_config_init,
	235	.config_aneg = &genphy_config_aneg,
	236	.read_status = &genphy_read_status,
	237	.suspend = genphy_suspend,
	238	.resume = genphy_resume,
	239	.driver = { .owner = THIS_MODULE,},
d5bf9071	240	}, {
9c9b1f24	241	.phy_id = 0x02430c54,
e3e09f26	242	.name = "ICPlus IP101A/G",
9c9b1f24 GC	243	.phy_id_mask = 0x0ffffff0,
	244	.features = PHY_BASIC_FEATURES \| SUPPORTED_Pause \|
	245	SUPPORTED_Asym_Pause,
e3e09f26	246	.flags = PHY_HAS_INTERRUPT,
996f7393	247	.ack_interrupt = ip101a_g_ack_interrupt,
e3e09f26	248	.config_init = &ip101a_g_config_init,
9c9b1f24 GC	249	.config_aneg = &genphy_config_aneg,
	250	.read_status = &genphy_read_status,
	251	.suspend = genphy_suspend,
	252	.resume = genphy_resume,
	253	.driver = { .owner = THIS_MODULE,},
d5bf9071	254	} };
9c9b1f24	255
377ecca9	256	static int __init icplus_init(void)
0cefeeba	257	{
d5bf9071 CH	258	return phy_drivers_register(icplus_driver,
d5bf9071 CH	259	ARRAY_SIZE(icplus_driver));
0cefeeba MB	260	}
0cefeeba MB	261
377ecca9	262	static void __exit icplus_exit(void)
0cefeeba	263	{
d5bf9071 CH	264	phy_drivers_unregister(icplus_driver,
d5bf9071 CH	265	ARRAY_SIZE(icplus_driver));
0cefeeba MB	266	}
0cefeeba MB	267
377ecca9 GC	268	module_init(icplus_init);
377ecca9 GC	269	module_exit(icplus_exit);
4e4f10f6	270
cf93c945	271	static struct mdio_device_id __maybe_unused icplus_tbl[] = {
4e4f10f6	272	{ 0x02430d80, 0x0ffffff0 },
377ecca9	273	{ 0x02430d90, 0x0ffffff0 },
e3e09f26	274	{ 0x02430c54, 0x0ffffff0 },
4e4f10f6 DW	275	{ }
	276	};
	277
	278	MODULE_DEVICE_TABLE(mdio, icplus_tbl);