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09bb9aa0 MB |
1 | /* |
2 | * Driver for Broadcom 63xx SOCs integrated PHYs | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | */ | |
a1cba561 | 9 | #include "bcm-phy-lib.h" |
09bb9aa0 MB |
10 | #include <linux/module.h> |
11 | #include <linux/phy.h> | |
12 | ||
13 | #define MII_BCM63XX_IR 0x1a /* interrupt register */ | |
14 | #define MII_BCM63XX_IR_EN 0x4000 /* global interrupt enable */ | |
15 | #define MII_BCM63XX_IR_DUPLEX 0x0800 /* duplex changed */ | |
16 | #define MII_BCM63XX_IR_SPEED 0x0400 /* speed changed */ | |
17 | #define MII_BCM63XX_IR_LINK 0x0200 /* link changed */ | |
18 | #define MII_BCM63XX_IR_GMASK 0x0100 /* global interrupt mask */ | |
19 | ||
20 | MODULE_DESCRIPTION("Broadcom 63xx internal PHY driver"); | |
21 | MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>"); | |
22 | MODULE_LICENSE("GPL"); | |
23 | ||
cd33b3e0 DGC |
24 | static int bcm63xx_config_intr(struct phy_device *phydev) |
25 | { | |
26 | int reg, err; | |
27 | ||
28 | reg = phy_read(phydev, MII_BCM63XX_IR); | |
29 | if (reg < 0) | |
30 | return reg; | |
31 | ||
32 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) | |
33 | reg &= ~MII_BCM63XX_IR_GMASK; | |
34 | else | |
35 | reg |= MII_BCM63XX_IR_GMASK; | |
36 | ||
37 | err = phy_write(phydev, MII_BCM63XX_IR, reg); | |
38 | return err; | |
39 | } | |
40 | ||
09bb9aa0 MB |
41 | static int bcm63xx_config_init(struct phy_device *phydev) |
42 | { | |
43 | int reg, err; | |
44 | ||
45 | reg = phy_read(phydev, MII_BCM63XX_IR); | |
46 | if (reg < 0) | |
47 | return reg; | |
48 | ||
49 | /* Mask interrupts globally. */ | |
50 | reg |= MII_BCM63XX_IR_GMASK; | |
51 | err = phy_write(phydev, MII_BCM63XX_IR, reg); | |
52 | if (err < 0) | |
53 | return err; | |
54 | ||
55 | /* Unmask events we are interested in */ | |
56 | reg = ~(MII_BCM63XX_IR_DUPLEX | | |
57 | MII_BCM63XX_IR_SPEED | | |
58 | MII_BCM63XX_IR_LINK) | | |
59 | MII_BCM63XX_IR_EN; | |
a25cc43e | 60 | return phy_write(phydev, MII_BCM63XX_IR, reg); |
09bb9aa0 MB |
61 | } |
62 | ||
d5bf9071 CH |
63 | static struct phy_driver bcm63xx_driver[] = { |
64 | { | |
09bb9aa0 MB |
65 | .phy_id = 0x00406000, |
66 | .phy_id_mask = 0xfffffc00, | |
67 | .name = "Broadcom BCM63XX (1)", | |
68 | /* ASYM_PAUSE bit is marked RO in datasheet, so don't cheat */ | |
69 | .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), | |
50ab731e | 70 | .flags = PHY_HAS_INTERRUPT | PHY_IS_INTERNAL, |
09bb9aa0 MB |
71 | .config_init = bcm63xx_config_init, |
72 | .config_aneg = genphy_config_aneg, | |
73 | .read_status = genphy_read_status, | |
a1cba561 | 74 | .ack_interrupt = bcm_phy_ack_intr, |
cd33b3e0 | 75 | .config_intr = bcm63xx_config_intr, |
d5bf9071 CH |
76 | }, { |
77 | /* same phy as above, with just a different OUI */ | |
09bb9aa0 MB |
78 | .phy_id = 0x002bdc00, |
79 | .phy_id_mask = 0xfffffc00, | |
80 | .name = "Broadcom BCM63XX (2)", | |
81 | .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), | |
50ab731e | 82 | .flags = PHY_HAS_INTERRUPT | PHY_IS_INTERNAL, |
09bb9aa0 MB |
83 | .config_init = bcm63xx_config_init, |
84 | .config_aneg = genphy_config_aneg, | |
85 | .read_status = genphy_read_status, | |
a1cba561 | 86 | .ack_interrupt = bcm_phy_ack_intr, |
cd33b3e0 | 87 | .config_intr = bcm63xx_config_intr, |
d5bf9071 | 88 | } }; |
09bb9aa0 | 89 | |
50fd7150 | 90 | module_phy_driver(bcm63xx_driver); |
4e4f10f6 | 91 | |
cf93c945 | 92 | static struct mdio_device_id __maybe_unused bcm63xx_tbl[] = { |
4e4f10f6 DW |
93 | { 0x00406000, 0xfffffc00 }, |
94 | { 0x002bdc00, 0xfffffc00 }, | |
95 | { } | |
96 | }; | |
97 | ||
0de8655a | 98 | MODULE_DEVICE_TABLE(mdio, bcm63xx_tbl); |