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vortex_up should initialize "err"
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / pcnet32.c
CommitLineData
1da177e4
LT		 1/* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2/*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15/**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
23
24#define DRV_NAME "pcnet32"
7de745e5 25#ifdef CONFIG_PCNET32_NAPI
917270c6 26#define DRV_VERSION "1.34-NAPI"
7de745e5 27#else
917270c6 28#define DRV_VERSION "1.34"
7de745e5 29#endif
917270c6 30#define DRV_RELDATE "14.Aug.2007"
1da177e4
LT		 31#define PFX DRV_NAME ": "
32
4a5e8e29
JG		 33static const char *const version =
34 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
1da177e4
LT		 35
36#include <linux/module.h>
37#include <linux/kernel.h>
38#include <linux/string.h>
39#include <linux/errno.h>
40#include <linux/ioport.h>
41#include <linux/slab.h>
42#include <linux/interrupt.h>
43#include <linux/pci.h>
44#include <linux/delay.h>
45#include <linux/init.h>
46#include <linux/ethtool.h>
47#include <linux/mii.h>
48#include <linux/crc32.h>
49#include <linux/netdevice.h>
50#include <linux/etherdevice.h>
51#include <linux/skbuff.h>
52#include <linux/spinlock.h>
53#include <linux/moduleparam.h>
54#include <linux/bitops.h>
55
56#include <asm/dma.h>
57#include <asm/io.h>
58#include <asm/uaccess.h>
59#include <asm/irq.h>
60
61/*
62 * PCI device identifiers for "new style" Linux PCI Device Drivers
63 */
64static struct pci_device_id pcnet32_pci_tbl[] = {
f2622a2b
DF		 65 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
66 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
4a5e8e29
JG		 67
68 /*
69 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
70 * the incorrect vendor id.
71 */
f2622a2b
DF		 72 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
73 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
4a5e8e29
JG		 74
75 { } /* terminate list */
1da177e4
LT		 76};
77
4a5e8e29 78MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
1da177e4
LT		 79
80static int cards_found;
81
82/*
83 * VLB I/O addresses
84 */
85static unsigned int pcnet32_portlist[] __initdata =
4a5e8e29 86 { 0x300, 0x320, 0x340, 0x360, 0 };
1da177e4
LT		 87
88static int pcnet32_debug = 0;
4a5e8e29
JG		 89static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
90static int pcnet32vlb; /* check for VLB cards ? */
1da177e4
LT		 91
92static struct net_device *pcnet32_dev;
93
94static int max_interrupt_work = 2;
95static int rx_copybreak = 200;
96
97#define PCNET32_PORT_AUI 0x00
98#define PCNET32_PORT_10BT 0x01
99#define PCNET32_PORT_GPSI 0x02
100#define PCNET32_PORT_MII 0x03
101
102#define PCNET32_PORT_PORTSEL 0x03
103#define PCNET32_PORT_ASEL 0x04
104#define PCNET32_PORT_100 0x40
105#define PCNET32_PORT_FD 0x80
106
107#define PCNET32_DMA_MASK 0xffffffff
108
109#define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
110#define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
111
112/*
113 * table to translate option values from tulip
114 * to internal options
115 */
f71e1309 116static const unsigned char options_mapping[] = {
4a5e8e29
JG		 117 PCNET32_PORT_ASEL, /* 0 Auto-select */
118 PCNET32_PORT_AUI, /* 1 BNC/AUI */
119 PCNET32_PORT_AUI, /* 2 AUI/BNC */
120 PCNET32_PORT_ASEL, /* 3 not supported */
121 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
122 PCNET32_PORT_ASEL, /* 5 not supported */
123 PCNET32_PORT_ASEL, /* 6 not supported */
124 PCNET32_PORT_ASEL, /* 7 not supported */
125 PCNET32_PORT_ASEL, /* 8 not supported */
126 PCNET32_PORT_MII, /* 9 MII 10baseT */
127 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
128 PCNET32_PORT_MII, /* 11 MII (autosel) */
129 PCNET32_PORT_10BT, /* 12 10BaseT */
130 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
131 /* 14 MII 100BaseTx-FD */
132 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
133 PCNET32_PORT_ASEL /* 15 not supported */
1da177e4
LT		 134};
135
136static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
4a5e8e29 137 "Loopback test (offline)"
1da177e4 138};
4a5e8e29 139
1da177e4
LT		 140#define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
141
ac62ef04 142#define PCNET32_NUM_REGS 136
1da177e4 143
4a5e8e29 144#define MAX_UNITS 8 /* More are supported, limit only on options */
1da177e4
LT		 145static int options[MAX_UNITS];
146static int full_duplex[MAX_UNITS];
147static int homepna[MAX_UNITS];
148
149/*
150 * Theory of Operation
151 *
152 * This driver uses the same software structure as the normal lance
153 * driver. So look for a verbose description in lance.c. The differences
154 * to the normal lance driver is the use of the 32bit mode of PCnet32
155 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
156 * 16MB limitation and we don't need bounce buffers.
157 */
158
1da177e4
LT		 159/*
160 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
161 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
162 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
163 */
164#ifndef PCNET32_LOG_TX_BUFFERS
eabf0415
HWL		 165#define PCNET32_LOG_TX_BUFFERS 4
166#define PCNET32_LOG_RX_BUFFERS 5
167#define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
168#define PCNET32_LOG_MAX_RX_BUFFERS 9
1da177e4
LT		 169#endif
170
171#define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
eabf0415 172#define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
1da177e4
LT		 173
174#define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
eabf0415 175#define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
1da177e4
LT		 176
177#define PKT_BUF_SZ 1544
178
179/* Offsets from base I/O address. */
180#define PCNET32_WIO_RDP 0x10
181#define PCNET32_WIO_RAP 0x12
182#define PCNET32_WIO_RESET 0x14
183#define PCNET32_WIO_BDP 0x16
184
185#define PCNET32_DWIO_RDP 0x10
186#define PCNET32_DWIO_RAP 0x14
187#define PCNET32_DWIO_RESET 0x18
188#define PCNET32_DWIO_BDP 0x1C
189
190#define PCNET32_TOTAL_SIZE 0x20
191
06c87850
DF		 192#define CSR0 0
193#define CSR0_INIT 0x1
194#define CSR0_START 0x2
195#define CSR0_STOP 0x4
196#define CSR0_TXPOLL 0x8
197#define CSR0_INTEN 0x40
198#define CSR0_IDON 0x0100
199#define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
200#define PCNET32_INIT_LOW 1
201#define PCNET32_INIT_HIGH 2
202#define CSR3 3
203#define CSR4 4
204#define CSR5 5
205#define CSR5_SUSPEND 0x0001
206#define CSR15 15
207#define PCNET32_MC_FILTER 8
208
8d916266
DF		 209#define PCNET32_79C970A 0x2621
210
1da177e4
LT		 211/* The PCNET32 Rx and Tx ring descriptors. */
212struct pcnet32_rx_head {
3e33545b
AV		 213 __le32 base;
214 __le16 buf_length; /* two`s complement of length */
215 __le16 status;
216 __le32 msg_length;
217 __le32 reserved;
1da177e4
LT		 218};
219
220struct pcnet32_tx_head {
3e33545b
AV		 221 __le32 base;
222 __le16 length; /* two`s complement of length */
223 __le16 status;
224 __le32 misc;
225 __le32 reserved;
1da177e4
LT		 226};
227
228/* The PCNET32 32-Bit initialization block, described in databook. */
229struct pcnet32_init_block {
3e33545b
AV		 230 __le16 mode;
231 __le16 tlen_rlen;
0b5bf225 232 u8 phys_addr[6];
3e33545b
AV		 233 __le16 reserved;
234 __le32 filter[2];
4a5e8e29 235 /* Receive and transmit ring base, along with extra bits. */
3e33545b
AV		 236 __le32 rx_ring;
237 __le32 tx_ring;
1da177e4
LT		 238};
239
240/* PCnet32 access functions */
241struct pcnet32_access {
4a5e8e29
JG		 242 u16 (*read_csr) (unsigned long, int);
243 void (*write_csr) (unsigned long, int, u16);
244 u16 (*read_bcr) (unsigned long, int);
245 void (*write_bcr) (unsigned long, int, u16);
246 u16 (*read_rap) (unsigned long);
247 void (*write_rap) (unsigned long, u16);
248 void (*reset) (unsigned long);
1da177e4
LT		 249};
250
251/*
76209926
HWL		 252 * The first field of pcnet32_private is read by the ethernet device
253 * so the structure should be allocated using pci_alloc_consistent().
1da177e4
LT		 254 */
255struct pcnet32_private {
6ecb7667 256 struct pcnet32_init_block *init_block;
4a5e8e29 257 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
0b5bf225
JG		 258 struct pcnet32_rx_head *rx_ring;
259 struct pcnet32_tx_head *tx_ring;
6ecb7667
DF		 260 dma_addr_t init_dma_addr;/* DMA address of beginning of the init block,
261 returned by pci_alloc_consistent */
0b5bf225
JG		 262 struct pci_dev *pci_dev;
263 const char *name;
4a5e8e29 264 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
0b5bf225
JG		 265 struct sk_buff **tx_skbuff;
266 struct sk_buff **rx_skbuff;
267 dma_addr_t *tx_dma_addr;
268 dma_addr_t *rx_dma_addr;
269 struct pcnet32_access a;
270 spinlock_t lock; /* Guard lock */
271 unsigned int cur_rx, cur_tx; /* The next free ring entry */
272 unsigned int rx_ring_size; /* current rx ring size */
273 unsigned int tx_ring_size; /* current tx ring size */
274 unsigned int rx_mod_mask; /* rx ring modular mask */
275 unsigned int tx_mod_mask; /* tx ring modular mask */
276 unsigned short rx_len_bits;
277 unsigned short tx_len_bits;
278 dma_addr_t rx_ring_dma_addr;
279 dma_addr_t tx_ring_dma_addr;
280 unsigned int dirty_rx, /* ring entries to be freed. */
281 dirty_tx;
282
bea3348e
SH		 283 struct net_device *dev;
284 struct napi_struct napi;
0b5bf225
JG		 285 struct net_device_stats stats;
286 char tx_full;
287 char phycount; /* number of phys found */
288 int options;
289 unsigned int shared_irq:1, /* shared irq possible */
290 dxsuflo:1, /* disable transmit stop on uflo */
291 mii:1; /* mii port available */
292 struct net_device *next;
293 struct mii_if_info mii_if;
294 struct timer_list watchdog_timer;
295 struct timer_list blink_timer;
296 u32 msg_enable; /* debug message level */
4a5e8e29
JG		 297
298 /* each bit indicates an available PHY */
0b5bf225 299 u32 phymask;
8d916266 300 unsigned short chip_version; /* which variant this is */
1da177e4
LT		 301};
302
4a5e8e29
JG		 303static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
304static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
305static int pcnet32_open(struct net_device *);
306static int pcnet32_init_ring(struct net_device *);
307static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
4a5e8e29 308static void pcnet32_tx_timeout(struct net_device *dev);
7d12e780 309static irqreturn_t pcnet32_interrupt(int, void *);
4a5e8e29 310static int pcnet32_close(struct net_device *);
1da177e4
LT		 311static struct net_device_stats *pcnet32_get_stats(struct net_device *);
312static void pcnet32_load_multicast(struct net_device *dev);
313static void pcnet32_set_multicast_list(struct net_device *);
4a5e8e29 314static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
1da177e4
LT		 315static void pcnet32_watchdog(struct net_device *);
316static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
4a5e8e29
JG		 317static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
318 int val);
1da177e4
LT		 319static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
320static void pcnet32_ethtool_test(struct net_device *dev,
4a5e8e29
JG		 321 struct ethtool_test *eth_test, u64 * data);
322static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
1da177e4
LT		 323static int pcnet32_phys_id(struct net_device *dev, u32 data);
324static void pcnet32_led_blink_callback(struct net_device *dev);
325static int pcnet32_get_regs_len(struct net_device *dev);
326static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4a5e8e29 327 void *ptr);
1bcd3153 328static void pcnet32_purge_tx_ring(struct net_device *dev);
a88c844c 329static int pcnet32_alloc_ring(struct net_device *dev, char *name);
eabf0415 330static void pcnet32_free_ring(struct net_device *dev);
ac62ef04 331static void pcnet32_check_media(struct net_device *dev, int verbose);
eabf0415 332
4a5e8e29 333static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
1da177e4 334{
4a5e8e29
JG		 335 outw(index, addr + PCNET32_WIO_RAP);
336 return inw(addr + PCNET32_WIO_RDP);
1da177e4
LT		 337}
338
4a5e8e29 339static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
1da177e4 340{
4a5e8e29
JG		 341 outw(index, addr + PCNET32_WIO_RAP);
342 outw(val, addr + PCNET32_WIO_RDP);
1da177e4
LT		 343}
344
4a5e8e29 345static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
1da177e4 346{
4a5e8e29
JG		 347 outw(index, addr + PCNET32_WIO_RAP);
348 return inw(addr + PCNET32_WIO_BDP);
1da177e4
LT		 349}
350
4a5e8e29 351static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
1da177e4 352{
4a5e8e29
JG		 353 outw(index, addr + PCNET32_WIO_RAP);
354 outw(val, addr + PCNET32_WIO_BDP);
1da177e4
LT		 355}
356
4a5e8e29 357static u16 pcnet32_wio_read_rap(unsigned long addr)
1da177e4 358{
4a5e8e29 359 return inw(addr + PCNET32_WIO_RAP);
1da177e4
LT		 360}
361
4a5e8e29 362static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
1da177e4 363{
4a5e8e29 364 outw(val, addr + PCNET32_WIO_RAP);
1da177e4
LT		 365}
366
4a5e8e29 367static void pcnet32_wio_reset(unsigned long addr)
1da177e4 368{
4a5e8e29 369 inw(addr + PCNET32_WIO_RESET);
1da177e4
LT		 370}
371
4a5e8e29 372static int pcnet32_wio_check(unsigned long addr)
1da177e4 373{
4a5e8e29
JG		 374 outw(88, addr + PCNET32_WIO_RAP);
375 return (inw(addr + PCNET32_WIO_RAP) == 88);
1da177e4
LT		 376}
377
378static struct pcnet32_access pcnet32_wio = {
4a5e8e29
JG		 379 .read_csr = pcnet32_wio_read_csr,
380 .write_csr = pcnet32_wio_write_csr,
381 .read_bcr = pcnet32_wio_read_bcr,
382 .write_bcr = pcnet32_wio_write_bcr,
383 .read_rap = pcnet32_wio_read_rap,
384 .write_rap = pcnet32_wio_write_rap,
385 .reset = pcnet32_wio_reset
1da177e4
LT		 386};
387
4a5e8e29 388static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
1da177e4 389{
4a5e8e29
JG		 390 outl(index, addr + PCNET32_DWIO_RAP);
391 return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
1da177e4
LT		 392}
393
4a5e8e29 394static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
1da177e4 395{
4a5e8e29
JG		 396 outl(index, addr + PCNET32_DWIO_RAP);
397 outl(val, addr + PCNET32_DWIO_RDP);
1da177e4
LT		 398}
399
4a5e8e29 400static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
1da177e4 401{
4a5e8e29
JG		 402 outl(index, addr + PCNET32_DWIO_RAP);
403 return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
1da177e4
LT		 404}
405
4a5e8e29 406static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
1da177e4 407{
4a5e8e29
JG		 408 outl(index, addr + PCNET32_DWIO_RAP);
409 outl(val, addr + PCNET32_DWIO_BDP);
1da177e4
LT		 410}
411
4a5e8e29 412static u16 pcnet32_dwio_read_rap(unsigned long addr)
1da177e4 413{
4a5e8e29 414 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
1da177e4
LT		 415}
416
4a5e8e29 417static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
1da177e4 418{
4a5e8e29 419 outl(val, addr + PCNET32_DWIO_RAP);
1da177e4
LT		 420}
421
4a5e8e29 422static void pcnet32_dwio_reset(unsigned long addr)
1da177e4 423{
4a5e8e29 424 inl(addr + PCNET32_DWIO_RESET);
1da177e4
LT		 425}
426
4a5e8e29 427static int pcnet32_dwio_check(unsigned long addr)
1da177e4 428{
4a5e8e29
JG		 429 outl(88, addr + PCNET32_DWIO_RAP);
430 return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
1da177e4
LT		 431}
432
433static struct pcnet32_access pcnet32_dwio = {
4a5e8e29
JG		 434 .read_csr = pcnet32_dwio_read_csr,
435 .write_csr = pcnet32_dwio_write_csr,
436 .read_bcr = pcnet32_dwio_read_bcr,
437 .write_bcr = pcnet32_dwio_write_bcr,
438 .read_rap = pcnet32_dwio_read_rap,
439 .write_rap = pcnet32_dwio_write_rap,
440 .reset = pcnet32_dwio_reset
1da177e4
LT		 441};
442
06c87850
DF		 443static void pcnet32_netif_stop(struct net_device *dev)
444{
6ad6c756 445#ifdef CONFIG_PCNET32_NAPI
bea3348e 446 struct pcnet32_private *lp = netdev_priv(dev);
6ad6c756 447#endif
06c87850 448 dev->trans_start = jiffies;
bea3348e
SH		 449#ifdef CONFIG_PCNET32_NAPI
450 napi_disable(&lp->napi);
451#endif
06c87850
DF		 452 netif_tx_disable(dev);
453}
454
455static void pcnet32_netif_start(struct net_device *dev)
456{
6ad6c756 457#ifdef CONFIG_PCNET32_NAPI
bea3348e 458 struct pcnet32_private *lp = netdev_priv(dev);
6ad6c756 459#endif
06c87850 460 netif_wake_queue(dev);
bea3348e
SH		 461#ifdef CONFIG_PCNET32_NAPI
462 napi_enable(&lp->napi);
463#endif
06c87850
DF		 464}
465
466/*
467 * Allocate space for the new sized tx ring.
468 * Free old resources
469 * Save new resources.
470 * Any failure keeps old resources.
471 * Must be called with lp->lock held.
472 */
473static void pcnet32_realloc_tx_ring(struct net_device *dev,
474 struct pcnet32_private *lp,
475 unsigned int size)
476{
477 dma_addr_t new_ring_dma_addr;
478 dma_addr_t *new_dma_addr_list;
479 struct pcnet32_tx_head *new_tx_ring;
480 struct sk_buff **new_skb_list;
481
482 pcnet32_purge_tx_ring(dev);
483
484 new_tx_ring = pci_alloc_consistent(lp->pci_dev,
485 sizeof(struct pcnet32_tx_head) *
486 (1 << size),
487 &new_ring_dma_addr);
488 if (new_tx_ring == NULL) {
489 if (netif_msg_drv(lp))
490 printk("\n" KERN_ERR
491 "%s: Consistent memory allocation failed.\n",
492 dev->name);
493 return;
494 }
495 memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
496
497 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
498 GFP_ATOMIC);
499 if (!new_dma_addr_list) {
500 if (netif_msg_drv(lp))
501 printk("\n" KERN_ERR
502 "%s: Memory allocation failed.\n", dev->name);
503 goto free_new_tx_ring;
504 }
505
506 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
507 GFP_ATOMIC);
508 if (!new_skb_list) {
509 if (netif_msg_drv(lp))
510 printk("\n" KERN_ERR
511 "%s: Memory allocation failed.\n", dev->name);
512 goto free_new_lists;
513 }
514
515 kfree(lp->tx_skbuff);
516 kfree(lp->tx_dma_addr);
517 pci_free_consistent(lp->pci_dev,
518 sizeof(struct pcnet32_tx_head) *
519 lp->tx_ring_size, lp->tx_ring,
520 lp->tx_ring_dma_addr);
521
522 lp->tx_ring_size = (1 << size);
523 lp->tx_mod_mask = lp->tx_ring_size - 1;
524 lp->tx_len_bits = (size << 12);
525 lp->tx_ring = new_tx_ring;
526 lp->tx_ring_dma_addr = new_ring_dma_addr;
527 lp->tx_dma_addr = new_dma_addr_list;
528 lp->tx_skbuff = new_skb_list;
529 return;
530
531 free_new_lists:
532 kfree(new_dma_addr_list);
533 free_new_tx_ring:
534 pci_free_consistent(lp->pci_dev,
535 sizeof(struct pcnet32_tx_head) *
536 (1 << size),
537 new_tx_ring,
538 new_ring_dma_addr);
539 return;
540}
541
542/*
543 * Allocate space for the new sized rx ring.
544 * Re-use old receive buffers.
545 * alloc extra buffers
546 * free unneeded buffers
547 * free unneeded buffers
548 * Save new resources.
549 * Any failure keeps old resources.
550 * Must be called with lp->lock held.
551 */
552static void pcnet32_realloc_rx_ring(struct net_device *dev,
553 struct pcnet32_private *lp,
554 unsigned int size)
555{
556 dma_addr_t new_ring_dma_addr;
557 dma_addr_t *new_dma_addr_list;
558 struct pcnet32_rx_head *new_rx_ring;
559 struct sk_buff **new_skb_list;
560 int new, overlap;
561
562 new_rx_ring = pci_alloc_consistent(lp->pci_dev,
563 sizeof(struct pcnet32_rx_head) *
564 (1 << size),
565 &new_ring_dma_addr);
566 if (new_rx_ring == NULL) {
567 if (netif_msg_drv(lp))
568 printk("\n" KERN_ERR
569 "%s: Consistent memory allocation failed.\n",
570 dev->name);
571 return;
572 }
573 memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
574
575 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
576 GFP_ATOMIC);
577 if (!new_dma_addr_list) {
578 if (netif_msg_drv(lp))
579 printk("\n" KERN_ERR
580 "%s: Memory allocation failed.\n", dev->name);
581 goto free_new_rx_ring;
582 }
583
584 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
585 GFP_ATOMIC);
586 if (!new_skb_list) {
587 if (netif_msg_drv(lp))
588 printk("\n" KERN_ERR
589 "%s: Memory allocation failed.\n", dev->name);
590 goto free_new_lists;
591 }
592
593 /* first copy the current receive buffers */
594 overlap = min(size, lp->rx_ring_size);
595 for (new = 0; new < overlap; new++) {
596 new_rx_ring[new] = lp->rx_ring[new];
597 new_dma_addr_list[new] = lp->rx_dma_addr[new];
598 new_skb_list[new] = lp->rx_skbuff[new];
599 }
600 /* now allocate any new buffers needed */
601 for (; new < size; new++ ) {
602 struct sk_buff *rx_skbuff;
603 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SZ);
604 if (!(rx_skbuff = new_skb_list[new])) {
605 /* keep the original lists and buffers */
606 if (netif_msg_drv(lp))
607 printk(KERN_ERR
608 "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
609 dev->name);
610 goto free_all_new;
611 }
612 skb_reserve(rx_skbuff, 2);
613
614 new_dma_addr_list[new] =
615 pci_map_single(lp->pci_dev, rx_skbuff->data,
616 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
3e33545b
AV		 617 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);
618 new_rx_ring[new].buf_length = cpu_to_le16(2 - PKT_BUF_SZ);
619 new_rx_ring[new].status = cpu_to_le16(0x8000);
06c87850
DF		 620 }
621 /* and free any unneeded buffers */
622 for (; new < lp->rx_ring_size; new++) {
623 if (lp->rx_skbuff[new]) {
624 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
625 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
626 dev_kfree_skb(lp->rx_skbuff[new]);
627 }
628 }
629
630 kfree(lp->rx_skbuff);
631 kfree(lp->rx_dma_addr);
632 pci_free_consistent(lp->pci_dev,
633 sizeof(struct pcnet32_rx_head) *
634 lp->rx_ring_size, lp->rx_ring,
635 lp->rx_ring_dma_addr);
636
637 lp->rx_ring_size = (1 << size);
638 lp->rx_mod_mask = lp->rx_ring_size - 1;
639 lp->rx_len_bits = (size << 4);
640 lp->rx_ring = new_rx_ring;
641 lp->rx_ring_dma_addr = new_ring_dma_addr;
642 lp->rx_dma_addr = new_dma_addr_list;
643 lp->rx_skbuff = new_skb_list;
644 return;
645
646 free_all_new:
647 for (; --new >= lp->rx_ring_size; ) {
648 if (new_skb_list[new]) {
649 pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
650 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
651 dev_kfree_skb(new_skb_list[new]);
652 }
653 }
654 kfree(new_skb_list);
655 free_new_lists:
656 kfree(new_dma_addr_list);
657 free_new_rx_ring:
658 pci_free_consistent(lp->pci_dev,
659 sizeof(struct pcnet32_rx_head) *
660 (1 << size),
661 new_rx_ring,
662 new_ring_dma_addr);
663 return;
664}
665
ac5bfe40
DF		 666static void pcnet32_purge_rx_ring(struct net_device *dev)
667{
1e56a4b4 668 struct pcnet32_private *lp = netdev_priv(dev);
ac5bfe40
DF		 669 int i;
670
671 /* free all allocated skbuffs */
672 for (i = 0; i < lp->rx_ring_size; i++) {
673 lp->rx_ring[i].status = 0; /* CPU owns buffer */
674 wmb(); /* Make sure adapter sees owner change */
675 if (lp->rx_skbuff[i]) {
676 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
677 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
678 dev_kfree_skb_any(lp->rx_skbuff[i]);
679 }
680 lp->rx_skbuff[i] = NULL;
681 lp->rx_dma_addr[i] = 0;
682 }
683}
684
1da177e4
LT		 685#ifdef CONFIG_NET_POLL_CONTROLLER
686static void pcnet32_poll_controller(struct net_device *dev)
687{
4a5e8e29 688 disable_irq(dev->irq);
7d12e780 689 pcnet32_interrupt(0, dev);
4a5e8e29 690 enable_irq(dev->irq);
1da177e4
LT		 691}
692#endif
693
1da177e4
LT		 694static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
695{
1e56a4b4 696 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 697 unsigned long flags;
698 int r = -EOPNOTSUPP;
1da177e4 699
4a5e8e29
JG		 700 if (lp->mii) {
701 spin_lock_irqsave(&lp->lock, flags);
702 mii_ethtool_gset(&lp->mii_if, cmd);
703 spin_unlock_irqrestore(&lp->lock, flags);
704 r = 0;
705 }
706 return r;
1da177e4
LT		 707}
708
709static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
710{
1e56a4b4 711 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 712 unsigned long flags;
713 int r = -EOPNOTSUPP;
1da177e4 714
4a5e8e29
JG		 715 if (lp->mii) {
716 spin_lock_irqsave(&lp->lock, flags);
717 r = mii_ethtool_sset(&lp->mii_if, cmd);
718 spin_unlock_irqrestore(&lp->lock, flags);
719 }
720 return r;
1da177e4
LT		 721}
722
4a5e8e29
JG		 723static void pcnet32_get_drvinfo(struct net_device *dev,
724 struct ethtool_drvinfo *info)
1da177e4 725{
1e56a4b4 726 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 727
728 strcpy(info->driver, DRV_NAME);
729 strcpy(info->version, DRV_VERSION);
730 if (lp->pci_dev)
731 strcpy(info->bus_info, pci_name(lp->pci_dev));
732 else
733 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
1da177e4
LT		 734}
735
736static u32 pcnet32_get_link(struct net_device *dev)
737{
1e56a4b4 738 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 739 unsigned long flags;
740 int r;
1da177e4 741
4a5e8e29
JG		 742 spin_lock_irqsave(&lp->lock, flags);
743 if (lp->mii) {
744 r = mii_link_ok(&lp->mii_if);
8d916266 745 } else if (lp->chip_version >= PCNET32_79C970A) {
4a5e8e29
JG		 746 ulong ioaddr = dev->base_addr; /* card base I/O address */
747 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
8d916266
DF		 748 } else { /* can not detect link on really old chips */
749 r = 1;
4a5e8e29
JG		 750 }
751 spin_unlock_irqrestore(&lp->lock, flags);
752
753 return r;
1da177e4
LT		 754}
755
756static u32 pcnet32_get_msglevel(struct net_device *dev)
757{
1e56a4b4 758 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 759 return lp->msg_enable;
1da177e4
LT		 760}
761
762static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
763{
1e56a4b4 764 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 765 lp->msg_enable = value;
1da177e4
LT		 766}
767
768static int pcnet32_nway_reset(struct net_device *dev)
769{
1e56a4b4 770 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 771 unsigned long flags;
772 int r = -EOPNOTSUPP;
1da177e4 773
4a5e8e29
JG		 774 if (lp->mii) {
775 spin_lock_irqsave(&lp->lock, flags);
776 r = mii_nway_restart(&lp->mii_if);
777 spin_unlock_irqrestore(&lp->lock, flags);
778 }
779 return r;
1da177e4
LT		 780}
781
4a5e8e29
JG		 782static void pcnet32_get_ringparam(struct net_device *dev,
783 struct ethtool_ringparam *ering)
1da177e4 784{
1e56a4b4 785 struct pcnet32_private *lp = netdev_priv(dev);
1da177e4 786
6dcd60c2
DF		 787 ering->tx_max_pending = TX_MAX_RING_SIZE;
788 ering->tx_pending = lp->tx_ring_size;
789 ering->rx_max_pending = RX_MAX_RING_SIZE;
790 ering->rx_pending = lp->rx_ring_size;
eabf0415
HWL		 791}
792
4a5e8e29
JG		 793static int pcnet32_set_ringparam(struct net_device *dev,
794 struct ethtool_ringparam *ering)
eabf0415 795{
1e56a4b4 796 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 797 unsigned long flags;
06c87850
DF		 798 unsigned int size;
799 ulong ioaddr = dev->base_addr;
4a5e8e29
JG		 800 int i;
801
802 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
803 return -EINVAL;
804
805 if (netif_running(dev))
06c87850 806 pcnet32_netif_stop(dev);
4a5e8e29
JG		 807
808 spin_lock_irqsave(&lp->lock, flags);
06c87850
DF		 809 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
810
811 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
4a5e8e29
JG		 812
813 /* set the minimum ring size to 4, to allow the loopback test to work
814 * unchanged.
815 */
816 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
06c87850 817 if (size <= (1 << i))
4a5e8e29
JG		 818 break;
819 }
06c87850
DF		 820 if ((1 << i) != lp->tx_ring_size)
821 pcnet32_realloc_tx_ring(dev, lp, i);
b368a3fb 822
06c87850 823 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
4a5e8e29 824 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
06c87850 825 if (size <= (1 << i))
4a5e8e29
JG		 826 break;
827 }
06c87850
DF		 828 if ((1 << i) != lp->rx_ring_size)
829 pcnet32_realloc_rx_ring(dev, lp, i);
b368a3fb 830
bea3348e 831 lp->napi.weight = lp->rx_ring_size / 2;
06c87850
DF		 832
833 if (netif_running(dev)) {
834 pcnet32_netif_start(dev);
835 pcnet32_restart(dev, CSR0_NORMAL);
4a5e8e29 836 }
eabf0415 837
4a5e8e29 838 spin_unlock_irqrestore(&lp->lock, flags);
eabf0415 839
06c87850
DF		 840 if (netif_msg_drv(lp))
841 printk(KERN_INFO
4a5e8e29
JG		 842 "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name,
843 lp->rx_ring_size, lp->tx_ring_size);
eabf0415 844
4a5e8e29 845 return 0;
1da177e4
LT		 846}
847
4a5e8e29
JG		 848static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
849 u8 * data)
1da177e4 850{
4a5e8e29 851 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
1da177e4
LT		 852}
853
b9f2c044 854static int pcnet32_get_sset_count(struct net_device *dev, int sset)
1da177e4 855{
b9f2c044
JG		 856 switch (sset) {
857 case ETH_SS_TEST:
858 return PCNET32_TEST_LEN;
859 default:
860 return -EOPNOTSUPP;
861 }
1da177e4
LT		 862}
863
864static void pcnet32_ethtool_test(struct net_device *dev,
4a5e8e29 865 struct ethtool_test *test, u64 * data)
1da177e4 866{
1e56a4b4 867 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 868 int rc;
869
870 if (test->flags == ETH_TEST_FL_OFFLINE) {
871 rc = pcnet32_loopback_test(dev, data);
872 if (rc) {
873 if (netif_msg_hw(lp))
874 printk(KERN_DEBUG "%s: Loopback test failed.\n",
875 dev->name);
876 test->flags |= ETH_TEST_FL_FAILED;
877 } else if (netif_msg_hw(lp))
878 printk(KERN_DEBUG "%s: Loopback test passed.\n",
879 dev->name);
1da177e4 880 } else if (netif_msg_hw(lp))
4a5e8e29
JG		 881 printk(KERN_DEBUG
882 "%s: No tests to run (specify 'Offline' on ethtool).",
883 dev->name);
884} /* end pcnet32_ethtool_test */
1da177e4 885
4a5e8e29 886static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
1da177e4 887{
1e56a4b4 888 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 889 struct pcnet32_access *a = &lp->a; /* access to registers */
890 ulong ioaddr = dev->base_addr; /* card base I/O address */
891 struct sk_buff *skb; /* sk buff */
892 int x, i; /* counters */
893 int numbuffs = 4; /* number of TX/RX buffers and descs */
894 u16 status = 0x8300; /* TX ring status */
3e33545b 895 __le16 teststatus; /* test of ring status */
4a5e8e29
JG		 896 int rc; /* return code */
897 int size; /* size of packets */
898 unsigned char *packet; /* source packet data */
899 static const int data_len = 60; /* length of source packets */
900 unsigned long flags;
901 unsigned long ticks;
902
4a5e8e29
JG		 903 rc = 1; /* default to fail */
904
905 if (netif_running(dev))
7de745e5
DF		 906#ifdef CONFIG_PCNET32_NAPI
907 pcnet32_netif_stop(dev);
908#else
4a5e8e29 909 pcnet32_close(dev);
7de745e5 910#endif
4a5e8e29
JG		 911
912 spin_lock_irqsave(&lp->lock, flags);
ac5bfe40
DF		 913 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
914
915 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
4a5e8e29
JG		 916
917 /* Reset the PCNET32 */
918 lp->a.reset(ioaddr);
b368a3fb 919 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
4a5e8e29
JG		 920
921 /* switch pcnet32 to 32bit mode */
922 lp->a.write_bcr(ioaddr, 20, 2);
923
4a5e8e29
JG		 924 /* purge & init rings but don't actually restart */
925 pcnet32_restart(dev, 0x0000);
926
ac5bfe40 927 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
4a5e8e29
JG		 928
929 /* Initialize Transmit buffers. */
930 size = data_len + 15;
931 for (x = 0; x < numbuffs; x++) {
932 if (!(skb = dev_alloc_skb(size))) {
933 if (netif_msg_hw(lp))
934 printk(KERN_DEBUG
935 "%s: Cannot allocate skb at line: %d!\n",
936 dev->name, __LINE__);
937 goto clean_up;
938 } else {
939 packet = skb->data;
940 skb_put(skb, size); /* create space for data */
941 lp->tx_skbuff[x] = skb;
3e33545b 942 lp->tx_ring[x].length = cpu_to_le16(-skb->len);
4a5e8e29
JG		 943 lp->tx_ring[x].misc = 0;
944
945 /* put DA and SA into the skb */
946 for (i = 0; i < 6; i++)
947 *packet++ = dev->dev_addr[i];
948 for (i = 0; i < 6; i++)
949 *packet++ = dev->dev_addr[i];
950 /* type */
951 *packet++ = 0x08;
952 *packet++ = 0x06;
953 /* packet number */
954 *packet++ = x;
955 /* fill packet with data */
956 for (i = 0; i < data_len; i++)
957 *packet++ = i;
958
959 lp->tx_dma_addr[x] =
960 pci_map_single(lp->pci_dev, skb->data, skb->len,
961 PCI_DMA_TODEVICE);
3e33545b 962 lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);
4a5e8e29 963 wmb(); /* Make sure owner changes after all others are visible */
3e33545b 964 lp->tx_ring[x].status = cpu_to_le16(status);
4a5e8e29 965 }
1da177e4 966 }
1da177e4 967
ac5bfe40
DF		 968 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */
969 a->write_bcr(ioaddr, 32, x | 0x0002);
4a5e8e29 970
ac5bfe40
DF		 971 /* set int loopback in CSR15 */
972 x = a->read_csr(ioaddr, CSR15) & 0xfffc;
973 lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
4a5e8e29 974
3e33545b 975 teststatus = cpu_to_le16(0x8000);
ac5bfe40 976 lp->a.write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
4a5e8e29
JG		 977
978 /* Check status of descriptors */
979 for (x = 0; x < numbuffs; x++) {
980 ticks = 0;
981 rmb();
982 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
983 spin_unlock_irqrestore(&lp->lock, flags);
ac5bfe40 984 msleep(1);
4a5e8e29
JG		 985 spin_lock_irqsave(&lp->lock, flags);
986 rmb();
987 ticks++;
988 }
989 if (ticks == 200) {
990 if (netif_msg_hw(lp))
991 printk("%s: Desc %d failed to reset!\n",
992 dev->name, x);
993 break;
994 }
995 }
996
ac5bfe40 997 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
4a5e8e29
JG		 998 wmb();
999 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
1000 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
1001
1002 for (x = 0; x < numbuffs; x++) {
1003 printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
1004 skb = lp->rx_skbuff[x];
1005 for (i = 0; i < size; i++) {
1006 printk("%02x ", *(skb->data + i));
1007 }
1008 printk("\n");
1009 }
1010 }
1da177e4 1011
4a5e8e29
JG		 1012 x = 0;
1013 rc = 0;
1014 while (x < numbuffs && !rc) {
1015 skb = lp->rx_skbuff[x];
1016 packet = lp->tx_skbuff[x]->data;
1017 for (i = 0; i < size; i++) {
1018 if (*(skb->data + i) != packet[i]) {
1019 if (netif_msg_hw(lp))
1020 printk(KERN_DEBUG
1021 "%s: Error in compare! %2x - %02x %02x\n",
1022 dev->name, i, *(skb->data + i),
1023 packet[i]);
1024 rc = 1;
1025 break;
1026 }
1027 }
1028 x++;
1029 }
1da177e4 1030
4a5e8e29 1031 clean_up:
ac5bfe40 1032 *data1 = rc;
4a5e8e29 1033 pcnet32_purge_tx_ring(dev);
1da177e4 1034
ac5bfe40
DF		 1035 x = a->read_csr(ioaddr, CSR15);
1036 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
1da177e4 1037
ac5bfe40
DF		 1038 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
1039 a->write_bcr(ioaddr, 32, (x & ~0x0002));
4a5e8e29 1040
7de745e5
DF		 1041#ifdef CONFIG_PCNET32_NAPI
1042 if (netif_running(dev)) {
1043 pcnet32_netif_start(dev);
1044 pcnet32_restart(dev, CSR0_NORMAL);
1045 } else {
1046 pcnet32_purge_rx_ring(dev);
1047 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1048 }
1049 spin_unlock_irqrestore(&lp->lock, flags);
1050#else
4a5e8e29 1051 if (netif_running(dev)) {
ac5bfe40 1052 spin_unlock_irqrestore(&lp->lock, flags);
4a5e8e29
JG		 1053 pcnet32_open(dev);
1054 } else {
ac5bfe40 1055 pcnet32_purge_rx_ring(dev);
4a5e8e29 1056 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
ac5bfe40 1057 spin_unlock_irqrestore(&lp->lock, flags);
4a5e8e29 1058 }
7de745e5 1059#endif
4a5e8e29
JG		 1060
1061 return (rc);
1062} /* end pcnet32_loopback_test */
1da177e4
LT		 1063
1064static void pcnet32_led_blink_callback(struct net_device *dev)
1065{
1e56a4b4 1066 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 1067 struct pcnet32_access *a = &lp->a;
1068 ulong ioaddr = dev->base_addr;
1069 unsigned long flags;
1070 int i;
1071
1072 spin_lock_irqsave(&lp->lock, flags);
1073 for (i = 4; i < 8; i++) {
1074 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1075 }
1076 spin_unlock_irqrestore(&lp->lock, flags);
1077
1078 mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
1da177e4
LT		 1079}
1080
1081static int pcnet32_phys_id(struct net_device *dev, u32 data)
1082{
1e56a4b4 1083 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 1084 struct pcnet32_access *a = &lp->a;
1085 ulong ioaddr = dev->base_addr;
1086 unsigned long flags;
1087 int i, regs[4];
1088
1089 if (!lp->blink_timer.function) {
1090 init_timer(&lp->blink_timer);
1091 lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
1092 lp->blink_timer.data = (unsigned long)dev;
1093 }
1094
1095 /* Save the current value of the bcrs */
1096 spin_lock_irqsave(&lp->lock, flags);
1097 for (i = 4; i < 8; i++) {
1098 regs[i - 4] = a->read_bcr(ioaddr, i);
1099 }
1100 spin_unlock_irqrestore(&lp->lock, flags);
1101
1102 mod_timer(&lp->blink_timer, jiffies);
1103 set_current_state(TASK_INTERRUPTIBLE);
1104
3e33545b 1105 /* AV: the limit here makes no sense whatsoever */
4a5e8e29
JG		 1106 if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
1107 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
1108
1109 msleep_interruptible(data * 1000);
1110 del_timer_sync(&lp->blink_timer);
1111
1112 /* Restore the original value of the bcrs */
1113 spin_lock_irqsave(&lp->lock, flags);
1114 for (i = 4; i < 8; i++) {
1115 a->write_bcr(ioaddr, i, regs[i - 4]);
1116 }
1117 spin_unlock_irqrestore(&lp->lock, flags);
1118
1119 return 0;
1da177e4
LT		 1120}
1121
df27f4a6
DF		 1122/*
1123 * lp->lock must be held.
1124 */
1125static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1126 int can_sleep)
1127{
1128 int csr5;
1e56a4b4 1129 struct pcnet32_private *lp = netdev_priv(dev);
df27f4a6
DF		 1130 struct pcnet32_access *a = &lp->a;
1131 ulong ioaddr = dev->base_addr;
1132 int ticks;
1133
8d916266
DF		 1134 /* really old chips have to be stopped. */
1135 if (lp->chip_version < PCNET32_79C970A)
1136 return 0;
1137
df27f4a6
DF		 1138 /* set SUSPEND (SPND) - CSR5 bit 0 */
1139 csr5 = a->read_csr(ioaddr, CSR5);
1140 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1141
1142 /* poll waiting for bit to be set */
1143 ticks = 0;
1144 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1145 spin_unlock_irqrestore(&lp->lock, *flags);
1146 if (can_sleep)
1147 msleep(1);
1148 else
1149 mdelay(1);
1150 spin_lock_irqsave(&lp->lock, *flags);
1151 ticks++;
1152 if (ticks > 200) {
1153 if (netif_msg_hw(lp))
1154 printk(KERN_DEBUG
1155 "%s: Error getting into suspend!\n",
1156 dev->name);
1157 return 0;
1158 }
1159 }
1160 return 1;
1161}
1162
3904c324
DF		 1163/*
1164 * process one receive descriptor entry
1165 */
1166
1167static void pcnet32_rx_entry(struct net_device *dev,
1168 struct pcnet32_private *lp,
1169 struct pcnet32_rx_head *rxp,
1170 int entry)
1171{
1172 int status = (short)le16_to_cpu(rxp->status) >> 8;
1173 int rx_in_place = 0;
1174 struct sk_buff *skb;
1175 short pkt_len;
1176
1177 if (status != 0x03) { /* There was an error. */
1178 /*
1179 * There is a tricky error noted by John Murphy,
1180 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1181 * buffers it's possible for a jabber packet to use two
1182 * buffers, with only the last correctly noting the error.
1183 */
1184 if (status & 0x01) /* Only count a general error at the */
1185 lp->stats.rx_errors++; /* end of a packet. */
1186 if (status & 0x20)
1187 lp->stats.rx_frame_errors++;
1188 if (status & 0x10)
1189 lp->stats.rx_over_errors++;
1190 if (status & 0x08)
1191 lp->stats.rx_crc_errors++;
1192 if (status & 0x04)
1193 lp->stats.rx_fifo_errors++;
1194 return;
1195 }
1196
1197 pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1198
1199 /* Discard oversize frames. */
1200 if (unlikely(pkt_len > PKT_BUF_SZ - 2)) {
1201 if (netif_msg_drv(lp))
1202 printk(KERN_ERR "%s: Impossible packet size %d!\n",
1203 dev->name, pkt_len);
1204 lp->stats.rx_errors++;
1205 return;
1206 }
1207 if (pkt_len < 60) {
1208 if (netif_msg_rx_err(lp))
1209 printk(KERN_ERR "%s: Runt packet!\n", dev->name);
1210 lp->stats.rx_errors++;
1211 return;
1212 }
1213
1214 if (pkt_len > rx_copybreak) {
1215 struct sk_buff *newskb;
1216
1217 if ((newskb = dev_alloc_skb(PKT_BUF_SZ))) {
1218 skb_reserve(newskb, 2);
1219 skb = lp->rx_skbuff[entry];
1220 pci_unmap_single(lp->pci_dev,
1221 lp->rx_dma_addr[entry],
1222 PKT_BUF_SZ - 2,
1223 PCI_DMA_FROMDEVICE);
1224 skb_put(skb, pkt_len);
1225 lp->rx_skbuff[entry] = newskb;
3904c324
DF		 1226 lp->rx_dma_addr[entry] =
1227 pci_map_single(lp->pci_dev,
1228 newskb->data,
1229 PKT_BUF_SZ - 2,
1230 PCI_DMA_FROMDEVICE);
3e33545b 1231 rxp->base = cpu_to_le32(lp->rx_dma_addr[entry]);
3904c324
DF		 1232 rx_in_place = 1;
1233 } else
1234 skb = NULL;
1235 } else {
1236 skb = dev_alloc_skb(pkt_len + 2);
1237 }
1238
1239 if (skb == NULL) {
1240 if (netif_msg_drv(lp))
1241 printk(KERN_ERR
1242 "%s: Memory squeeze, dropping packet.\n",
1243 dev->name);
1244 lp->stats.rx_dropped++;
1245 return;
1246 }
1247 skb->dev = dev;
1248 if (!rx_in_place) {
1249 skb_reserve(skb, 2); /* 16 byte align */
1250 skb_put(skb, pkt_len); /* Make room */
1251 pci_dma_sync_single_for_cpu(lp->pci_dev,
1252 lp->rx_dma_addr[entry],
b2cbbd8e 1253 pkt_len,
3904c324 1254 PCI_DMA_FROMDEVICE);
8c7b7faa 1255 skb_copy_to_linear_data(skb,
3904c324 1256 (unsigned char *)(lp->rx_skbuff[entry]->data),
8c7b7faa 1257 pkt_len);
3904c324
DF		 1258 pci_dma_sync_single_for_device(lp->pci_dev,
1259 lp->rx_dma_addr[entry],
b2cbbd8e 1260 pkt_len,
3904c324
DF		 1261 PCI_DMA_FROMDEVICE);
1262 }
1263 lp->stats.rx_bytes += skb->len;
1264 skb->protocol = eth_type_trans(skb, dev);
7de745e5
DF		 1265#ifdef CONFIG_PCNET32_NAPI
1266 netif_receive_skb(skb);
1267#else
3904c324 1268 netif_rx(skb);
7de745e5 1269#endif
3904c324
DF		 1270 dev->last_rx = jiffies;
1271 lp->stats.rx_packets++;
1272 return;
1273}
1274
bea3348e 1275static int pcnet32_rx(struct net_device *dev, int budget)
9691edd2 1276{
1e56a4b4 1277 struct pcnet32_private *lp = netdev_priv(dev);
9691edd2 1278 int entry = lp->cur_rx & lp->rx_mod_mask;
3904c324
DF		 1279 struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1280 int npackets = 0;
9691edd2
DF		 1281
1282 /* If we own the next entry, it's a new packet. Send it up. */
bea3348e 1283 while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {
3904c324
DF		 1284 pcnet32_rx_entry(dev, lp, rxp, entry);
1285 npackets += 1;
9691edd2 1286 /*
3904c324
DF		 1287 * The docs say that the buffer length isn't touched, but Andrew
1288 * Boyd of QNX reports that some revs of the 79C965 clear it.
9691edd2 1289 */
3e33545b 1290 rxp->buf_length = cpu_to_le16(2 - PKT_BUF_SZ);
3904c324 1291 wmb(); /* Make sure owner changes after others are visible */
3e33545b 1292 rxp->status = cpu_to_le16(0x8000);
9691edd2 1293 entry = (++lp->cur_rx) & lp->rx_mod_mask;
3904c324 1294 rxp = &lp->rx_ring[entry];
9691edd2
DF		 1295 }
1296
7de745e5 1297 return npackets;
9691edd2
DF		 1298}
1299
7de745e5 1300static int pcnet32_tx(struct net_device *dev)
9691edd2 1301{
1e56a4b4 1302 struct pcnet32_private *lp = netdev_priv(dev);
9691edd2
DF		 1303 unsigned int dirty_tx = lp->dirty_tx;
1304 int delta;
1305 int must_restart = 0;
1306
1307 while (dirty_tx != lp->cur_tx) {
1308 int entry = dirty_tx & lp->tx_mod_mask;
1309 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1310
1311 if (status < 0)
1312 break; /* It still hasn't been Txed */
1313
1314 lp->tx_ring[entry].base = 0;
1315
1316 if (status & 0x4000) {
3904c324 1317 /* There was a major error, log it. */
9691edd2
DF		 1318 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1319 lp->stats.tx_errors++;
1320 if (netif_msg_tx_err(lp))
1321 printk(KERN_ERR
1322 "%s: Tx error status=%04x err_status=%08x\n",
1323 dev->name, status,
1324 err_status);
1325 if (err_status & 0x04000000)
1326 lp->stats.tx_aborted_errors++;
1327 if (err_status & 0x08000000)
1328 lp->stats.tx_carrier_errors++;
1329 if (err_status & 0x10000000)
1330 lp->stats.tx_window_errors++;
1331#ifndef DO_DXSUFLO
1332 if (err_status & 0x40000000) {
1333 lp->stats.tx_fifo_errors++;
1334 /* Ackk! On FIFO errors the Tx unit is turned off! */
1335 /* Remove this verbosity later! */
1336 if (netif_msg_tx_err(lp))
1337 printk(KERN_ERR
7de745e5
DF		 1338 "%s: Tx FIFO error!\n",
1339 dev->name);
9691edd2
DF		 1340 must_restart = 1;
1341 }
1342#else
1343 if (err_status & 0x40000000) {
1344 lp->stats.tx_fifo_errors++;
1345 if (!lp->dxsuflo) { /* If controller doesn't recover ... */
1346 /* Ackk! On FIFO errors the Tx unit is turned off! */
1347 /* Remove this verbosity later! */
3904c324 1348 if (netif_msg_tx_err(lp))
9691edd2 1349 printk(KERN_ERR
7de745e5
DF		 1350 "%s: Tx FIFO error!\n",
1351 dev->name);
9691edd2
DF		 1352 must_restart = 1;
1353 }
1354 }
1355#endif
1356 } else {
1357 if (status & 0x1800)
1358 lp->stats.collisions++;
1359 lp->stats.tx_packets++;
1360 }
1361
1362 /* We must free the original skb */
1363 if (lp->tx_skbuff[entry]) {
1364 pci_unmap_single(lp->pci_dev,
1365 lp->tx_dma_addr[entry],
1366 lp->tx_skbuff[entry]->
1367 len, PCI_DMA_TODEVICE);
3904c324 1368 dev_kfree_skb_any(lp->tx_skbuff[entry]);
9691edd2
DF		 1369 lp->tx_skbuff[entry] = NULL;
1370 lp->tx_dma_addr[entry] = 0;
1371 }
1372 dirty_tx++;
1373 }
1374
3904c324 1375 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
9691edd2
DF		 1376 if (delta > lp->tx_ring_size) {
1377 if (netif_msg_drv(lp))
1378 printk(KERN_ERR
1379 "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1380 dev->name, dirty_tx, lp->cur_tx,
1381 lp->tx_full);
1382 dirty_tx += lp->tx_ring_size;
1383 delta -= lp->tx_ring_size;
1384 }
1385
1386 if (lp->tx_full &&
1387 netif_queue_stopped(dev) &&
1388 delta < lp->tx_ring_size - 2) {
1389 /* The ring is no longer full, clear tbusy. */
1390 lp->tx_full = 0;
1391 netif_wake_queue(dev);
1392 }
1393 lp->dirty_tx = dirty_tx;
1394
1395 return must_restart;
1396}
1397
7de745e5 1398#ifdef CONFIG_PCNET32_NAPI
bea3348e 1399static int pcnet32_poll(struct napi_struct *napi, int budget)
7de745e5 1400{
bea3348e
SH		 1401 struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
1402 struct net_device *dev = lp->dev;
7de745e5
DF		 1403 unsigned long ioaddr = dev->base_addr;
1404 unsigned long flags;
bea3348e 1405 int work_done;
7de745e5
DF		 1406 u16 val;
1407
bea3348e 1408 work_done = pcnet32_rx(dev, budget);
7de745e5
DF		 1409
1410 spin_lock_irqsave(&lp->lock, flags);
1411 if (pcnet32_tx(dev)) {
1412 /* reset the chip to clear the error condition, then restart */
1413 lp->a.reset(ioaddr);
1414 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
1415 pcnet32_restart(dev, CSR0_START);
1416 netif_wake_queue(dev);
1417 }
1418 spin_unlock_irqrestore(&lp->lock, flags);
1419
bea3348e
SH		 1420 if (work_done < budget) {
1421 spin_lock_irqsave(&lp->lock, flags);
7de745e5 1422
bea3348e 1423 __netif_rx_complete(dev, napi);
7de745e5 1424
bea3348e
SH		 1425 /* clear interrupt masks */
1426 val = lp->a.read_csr(ioaddr, CSR3);
1427 val &= 0x00ff;
1428 lp->a.write_csr(ioaddr, CSR3, val);
7de745e5 1429
bea3348e
SH		 1430 /* Set interrupt enable. */
1431 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
1432 mmiowb();
1433 spin_unlock_irqrestore(&lp->lock, flags);
1434 }
1435 return work_done;
7de745e5
DF		 1436}
1437#endif
1438
ac62ef04
DF		 1439#define PCNET32_REGS_PER_PHY 32
1440#define PCNET32_MAX_PHYS 32
1da177e4
LT		 1441static int pcnet32_get_regs_len(struct net_device *dev)
1442{
1e56a4b4 1443 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 1444 int j = lp->phycount * PCNET32_REGS_PER_PHY;
ac62ef04 1445
4a5e8e29 1446 return ((PCNET32_NUM_REGS + j) * sizeof(u16));
1da177e4
LT		 1447}
1448
1449static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4a5e8e29 1450 void *ptr)
1da177e4 1451{
4a5e8e29
JG		 1452 int i, csr0;
1453 u16 *buff = ptr;
1e56a4b4 1454 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 1455 struct pcnet32_access *a = &lp->a;
1456 ulong ioaddr = dev->base_addr;
4a5e8e29
JG		 1457 unsigned long flags;
1458
1459 spin_lock_irqsave(&lp->lock, flags);
1460
df27f4a6
DF		 1461 csr0 = a->read_csr(ioaddr, CSR0);
1462 if (!(csr0 & CSR0_STOP)) /* If not stopped */
1463 pcnet32_suspend(dev, &flags, 1);
1da177e4 1464
4a5e8e29
JG		 1465 /* read address PROM */
1466 for (i = 0; i < 16; i += 2)
1467 *buff++ = inw(ioaddr + i);
1468
1469 /* read control and status registers */
1470 for (i = 0; i < 90; i++) {
1471 *buff++ = a->read_csr(ioaddr, i);
1472 }
1473
1474 *buff++ = a->read_csr(ioaddr, 112);
1475 *buff++ = a->read_csr(ioaddr, 114);
1da177e4 1476
4a5e8e29
JG		 1477 /* read bus configuration registers */
1478 for (i = 0; i < 30; i++) {
1479 *buff++ = a->read_bcr(ioaddr, i);
1480 }
1481 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
1482 for (i = 31; i < 36; i++) {
1483 *buff++ = a->read_bcr(ioaddr, i);
1484 }
1485
1486 /* read mii phy registers */
1487 if (lp->mii) {
1488 int j;
1489 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1490 if (lp->phymask & (1 << j)) {
1491 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1492 lp->a.write_bcr(ioaddr, 33,
1493 (j << 5) | i);
1494 *buff++ = lp->a.read_bcr(ioaddr, 34);
1495 }
1496 }
1497 }
1498 }
1499
df27f4a6
DF		 1500 if (!(csr0 & CSR0_STOP)) { /* If not stopped */
1501 int csr5;
1502
4a5e8e29 1503 /* clear SUSPEND (SPND) - CSR5 bit 0 */
df27f4a6
DF		 1504 csr5 = a->read_csr(ioaddr, CSR5);
1505 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
4a5e8e29
JG		 1506 }
1507
1508 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4
LT		 1509}
1510
7282d491 1511static const struct ethtool_ops pcnet32_ethtool_ops = {
4a5e8e29
JG		 1512 .get_settings = pcnet32_get_settings,
1513 .set_settings = pcnet32_set_settings,
1514 .get_drvinfo = pcnet32_get_drvinfo,
1515 .get_msglevel = pcnet32_get_msglevel,
1516 .set_msglevel = pcnet32_set_msglevel,
1517 .nway_reset = pcnet32_nway_reset,
1518 .get_link = pcnet32_get_link,
1519 .get_ringparam = pcnet32_get_ringparam,
1520 .set_ringparam = pcnet32_set_ringparam,
4a5e8e29 1521 .get_strings = pcnet32_get_strings,
4a5e8e29
JG		 1522 .self_test = pcnet32_ethtool_test,
1523 .phys_id = pcnet32_phys_id,
1524 .get_regs_len = pcnet32_get_regs_len,
1525 .get_regs = pcnet32_get_regs,
b9f2c044 1526 .get_sset_count = pcnet32_get_sset_count,
1da177e4
LT		 1527};
1528
1529/* only probes for non-PCI devices, the rest are handled by
1530 * pci_register_driver via pcnet32_probe_pci */
1531
dcaf9769 1532static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1da177e4 1533{
4a5e8e29
JG		 1534 unsigned int *port, ioaddr;
1535
1536 /* search for PCnet32 VLB cards at known addresses */
1537 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1538 if (request_region
1539 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1540 /* check if there is really a pcnet chip on that ioaddr */
1541 if ((inb(ioaddr + 14) == 0x57)
1542 && (inb(ioaddr + 15) == 0x57)) {
1543 pcnet32_probe1(ioaddr, 0, NULL);
1544 } else {
1545 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1546 }
1547 }
1548 }
1da177e4
LT		 1549}
1550
1da177e4
LT		 1551static int __devinit
1552pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1553{
4a5e8e29
JG		 1554 unsigned long ioaddr;
1555 int err;
1556
1557 err = pci_enable_device(pdev);
1558 if (err < 0) {
1559 if (pcnet32_debug & NETIF_MSG_PROBE)
1560 printk(KERN_ERR PFX
1561 "failed to enable device -- err=%d\n", err);
1562 return err;
1563 }
1564 pci_set_master(pdev);
1565
1566 ioaddr = pci_resource_start(pdev, 0);
1567 if (!ioaddr) {
1568 if (pcnet32_debug & NETIF_MSG_PROBE)
1569 printk(KERN_ERR PFX
1570 "card has no PCI IO resources, aborting\n");
1571 return -ENODEV;
1572 }
1da177e4 1573
4a5e8e29
JG		 1574 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1575 if (pcnet32_debug & NETIF_MSG_PROBE)
1576 printk(KERN_ERR PFX
1577 "architecture does not support 32bit PCI busmaster DMA\n");
1578 return -ENODEV;
1579 }
1580 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") ==
1581 NULL) {
1582 if (pcnet32_debug & NETIF_MSG_PROBE)
1583 printk(KERN_ERR PFX
1584 "io address range already allocated\n");
1585 return -EBUSY;
1586 }
1da177e4 1587
4a5e8e29
JG		 1588 err = pcnet32_probe1(ioaddr, 1, pdev);
1589 if (err < 0) {
1590 pci_disable_device(pdev);
1591 }
1592 return err;
1da177e4
LT		 1593}
1594
1da177e4
LT		 1595/* pcnet32_probe1
1596 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1597 * pdev will be NULL when called from pcnet32_probe_vlbus.
1598 */
1599static int __devinit
1600pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1601{
4a5e8e29 1602 struct pcnet32_private *lp;
4a5e8e29
JG		 1603 int i, media;
1604 int fdx, mii, fset, dxsuflo;
1605 int chip_version;
1606 char *chipname;
1607 struct net_device *dev;
1608 struct pcnet32_access *a = NULL;
1609 u8 promaddr[6];
1610 int ret = -ENODEV;
1611
1612 /* reset the chip */
1613 pcnet32_wio_reset(ioaddr);
1614
1615 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1616 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1617 a = &pcnet32_wio;
1618 } else {
1619 pcnet32_dwio_reset(ioaddr);
1620 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
1621 && pcnet32_dwio_check(ioaddr)) {
1622 a = &pcnet32_dwio;
1623 } else
1624 goto err_release_region;
1625 }
1626
1627 chip_version =
1628 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1629 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1630 printk(KERN_INFO " PCnet chip version is %#x.\n",
1631 chip_version);
1632 if ((chip_version & 0xfff) != 0x003) {
1633 if (pcnet32_debug & NETIF_MSG_PROBE)
1634 printk(KERN_INFO PFX "Unsupported chip version.\n");
1635 goto err_release_region;
1636 }
1637
1638 /* initialize variables */
1639 fdx = mii = fset = dxsuflo = 0;
1640 chip_version = (chip_version >> 12) & 0xffff;
1641
1642 switch (chip_version) {
1643 case 0x2420:
1644 chipname = "PCnet/PCI 79C970"; /* PCI */
1645 break;
1646 case 0x2430:
1647 if (shared)
1648 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1649 else
1650 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1651 break;
1652 case 0x2621:
1653 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1654 fdx = 1;
1655 break;
1656 case 0x2623:
1657 chipname = "PCnet/FAST 79C971"; /* PCI */
1658 fdx = 1;
1659 mii = 1;
1660 fset = 1;
1661 break;
1662 case 0x2624:
1663 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1664 fdx = 1;
1665 mii = 1;
1666 fset = 1;
1667 break;
1668 case 0x2625:
1669 chipname = "PCnet/FAST III 79C973"; /* PCI */
1670 fdx = 1;
1671 mii = 1;
1672 break;
1673 case 0x2626:
1674 chipname = "PCnet/Home 79C978"; /* PCI */
1675 fdx = 1;
1676 /*
1677 * This is based on specs published at www.amd.com. This section
1678 * assumes that a card with a 79C978 wants to go into standard
1679 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1680 * and the module option homepna=1 can select this instead.
1681 */
1682 media = a->read_bcr(ioaddr, 49);
1683 media &= ~3; /* default to 10Mb ethernet */
1684 if (cards_found < MAX_UNITS && homepna[cards_found])
1685 media |= 1; /* switch to home wiring mode */
1686 if (pcnet32_debug & NETIF_MSG_PROBE)
1687 printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
1688 (media & 1) ? "1" : "10");
1689 a->write_bcr(ioaddr, 49, media);
1690 break;
1691 case 0x2627:
1692 chipname = "PCnet/FAST III 79C975"; /* PCI */
1693 fdx = 1;
1694 mii = 1;
1695 break;
1696 case 0x2628:
1697 chipname = "PCnet/PRO 79C976";
1698 fdx = 1;
1699 mii = 1;
1700 break;
1701 default:
1702 if (pcnet32_debug & NETIF_MSG_PROBE)
1703 printk(KERN_INFO PFX
1704 "PCnet version %#x, no PCnet32 chip.\n",
1705 chip_version);
1706 goto err_release_region;
1707 }
1708
1da177e4 1709 /*
4a5e8e29
JG		 1710 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1711 * starting until the packet is loaded. Strike one for reliability, lose
1712 * one for latency - although on PCI this isnt a big loss. Older chips
1713 * have FIFO's smaller than a packet, so you can't do this.
1714 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1da177e4 1715 */
4a5e8e29
JG		 1716
1717 if (fset) {
1718 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1719 a->write_csr(ioaddr, 80,
1720 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1721 dxsuflo = 1;
1722 }
1723
6ecb7667 1724 dev = alloc_etherdev(sizeof(*lp));
4a5e8e29
JG		 1725 if (!dev) {
1726 if (pcnet32_debug & NETIF_MSG_PROBE)
1727 printk(KERN_ERR PFX "Memory allocation failed.\n");
1728 ret = -ENOMEM;
1729 goto err_release_region;
1730 }
1731 SET_NETDEV_DEV(dev, &pdev->dev);
1732
1da177e4 1733 if (pcnet32_debug & NETIF_MSG_PROBE)
4a5e8e29
JG		 1734 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1735
1736 /* In most chips, after a chip reset, the ethernet address is read from the
1737 * station address PROM at the base address and programmed into the
1738 * "Physical Address Registers" CSR12-14.
1739 * As a precautionary measure, we read the PROM values and complain if
bc0e1fc9
LV		 1740 * they disagree with the CSRs. If they miscompare, and the PROM addr
1741 * is valid, then the PROM addr is used.
4a5e8e29
JG		 1742 */
1743 for (i = 0; i < 3; i++) {
1744 unsigned int val;
1745 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1746 /* There may be endianness issues here. */
1747 dev->dev_addr[2 * i] = val & 0x0ff;
1748 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1749 }
1750
1751 /* read PROM address and compare with CSR address */
1da177e4 1752 for (i = 0; i < 6; i++)
4a5e8e29
JG		 1753 promaddr[i] = inb(ioaddr + i);
1754
1755 if (memcmp(promaddr, dev->dev_addr, 6)
1756 || !is_valid_ether_addr(dev->dev_addr)) {
1757 if (is_valid_ether_addr(promaddr)) {
1758 if (pcnet32_debug & NETIF_MSG_PROBE) {
1759 printk(" warning: CSR address invalid,\n");
1760 printk(KERN_INFO
1761 " using instead PROM address of");
1762 }
1763 memcpy(dev->dev_addr, promaddr, 6);
1764 }
1765 }
1766 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1767
1768 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1769 if (!is_valid_ether_addr(dev->perm_addr))
1770 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
1771
1772 if (pcnet32_debug & NETIF_MSG_PROBE) {
1773 for (i = 0; i < 6; i++)
1774 printk(" %2.2x", dev->dev_addr[i]);
1775
1776 /* Version 0x2623 and 0x2624 */
1777 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1778 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
1779 printk("\n" KERN_INFO " tx_start_pt(0x%04x):", i);
1780 switch (i >> 10) {
1781 case 0:
1782 printk(" 20 bytes,");
1783 break;
1784 case 1:
1785 printk(" 64 bytes,");
1786 break;
1787 case 2:
1788 printk(" 128 bytes,");
1789 break;
1790 case 3:
1791 printk("~220 bytes,");
1792 break;
1793 }
1794 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
1795 printk(" BCR18(%x):", i & 0xffff);
1796 if (i & (1 << 5))
1797 printk("BurstWrEn ");
1798 if (i & (1 << 6))
1799 printk("BurstRdEn ");
1800 if (i & (1 << 7))
1801 printk("DWordIO ");
1802 if (i & (1 << 11))
1803 printk("NoUFlow ");
1804 i = a->read_bcr(ioaddr, 25);
1805 printk("\n" KERN_INFO " SRAMSIZE=0x%04x,", i << 8);
1806 i = a->read_bcr(ioaddr, 26);
1807 printk(" SRAM_BND=0x%04x,", i << 8);
1808 i = a->read_bcr(ioaddr, 27);
1809 if (i & (1 << 14))
1810 printk("LowLatRx");
1811 }
1812 }
1813
1814 dev->base_addr = ioaddr;
1e56a4b4 1815 lp = netdev_priv(dev);
4a5e8e29 1816 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
6ecb7667
DF		 1817 if ((lp->init_block =
1818 pci_alloc_consistent(pdev, sizeof(*lp->init_block), &lp->init_dma_addr)) == NULL) {
4a5e8e29
JG		 1819 if (pcnet32_debug & NETIF_MSG_PROBE)
1820 printk(KERN_ERR PFX
1821 "Consistent memory allocation failed.\n");
1822 ret = -ENOMEM;
1823 goto err_free_netdev;
1824 }
4a5e8e29
JG		 1825 lp->pci_dev = pdev;
1826
bea3348e
SH		 1827 lp->dev = dev;
1828
4a5e8e29
JG		 1829 spin_lock_init(&lp->lock);
1830
4a5e8e29 1831 SET_NETDEV_DEV(dev, &pdev->dev);
4a5e8e29
JG		 1832 lp->name = chipname;
1833 lp->shared_irq = shared;
1834 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
1835 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
1836 lp->tx_mod_mask = lp->tx_ring_size - 1;
1837 lp->rx_mod_mask = lp->rx_ring_size - 1;
1838 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1839 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1840 lp->mii_if.full_duplex = fdx;
1841 lp->mii_if.phy_id_mask = 0x1f;
1842 lp->mii_if.reg_num_mask = 0x1f;
1843 lp->dxsuflo = dxsuflo;
1844 lp->mii = mii;
8d916266 1845 lp->chip_version = chip_version;
4a5e8e29
JG		 1846 lp->msg_enable = pcnet32_debug;
1847 if ((cards_found >= MAX_UNITS)
1848 || (options[cards_found] > sizeof(options_mapping)))
1849 lp->options = PCNET32_PORT_ASEL;
1850 else
1851 lp->options = options_mapping[options[cards_found]];
1852 lp->mii_if.dev = dev;
1853 lp->mii_if.mdio_read = mdio_read;
1854 lp->mii_if.mdio_write = mdio_write;
1855
feff348f
DF		 1856 /* napi.weight is used in both the napi and non-napi cases */
1857 lp->napi.weight = lp->rx_ring_size / 2;
1858
bea3348e
SH		 1859#ifdef CONFIG_PCNET32_NAPI
1860 netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
1861#endif
1862
4a5e8e29
JG		 1863 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1864 ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1865 lp->options |= PCNET32_PORT_FD;
1866
1867 if (!a) {
1868 if (pcnet32_debug & NETIF_MSG_PROBE)
1869 printk(KERN_ERR PFX "No access methods\n");
1870 ret = -ENODEV;
1871 goto err_free_consistent;
1872 }
1873 lp->a = *a;
1874
1875 /* prior to register_netdev, dev->name is not yet correct */
1876 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1877 ret = -ENOMEM;
1878 goto err_free_ring;
1879 }
1880 /* detect special T1/E1 WAN card by checking for MAC address */
1881 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
1da177e4 1882 && dev->dev_addr[2] == 0x75)
4a5e8e29 1883 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1da177e4 1884
3e33545b 1885 lp->init_block->mode = cpu_to_le16(0x0003); /* Disable Rx and Tx. */
6ecb7667 1886 lp->init_block->tlen_rlen =
3e33545b 1887 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
4a5e8e29 1888 for (i = 0; i < 6; i++)
6ecb7667
DF		 1889 lp->init_block->phys_addr[i] = dev->dev_addr[i];
1890 lp->init_block->filter[0] = 0x00000000;
1891 lp->init_block->filter[1] = 0x00000000;
3e33545b
AV		 1892 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
1893 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
4a5e8e29
JG		 1894
1895 /* switch pcnet32 to 32bit mode */
1896 a->write_bcr(ioaddr, 20, 2);
1897
6ecb7667
DF		 1898 a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
1899 a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
4a5e8e29
JG		 1900
1901 if (pdev) { /* use the IRQ provided by PCI */
1902 dev->irq = pdev->irq;
1903 if (pcnet32_debug & NETIF_MSG_PROBE)
1904 printk(" assigned IRQ %d.\n", dev->irq);
1905 } else {
1906 unsigned long irq_mask = probe_irq_on();
1907
1908 /*
1909 * To auto-IRQ we enable the initialization-done and DMA error
1910 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1911 * boards will work.
1912 */
1913 /* Trigger an initialization just for the interrupt. */
b368a3fb 1914 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
4a5e8e29
JG		 1915 mdelay(1);
1916
1917 dev->irq = probe_irq_off(irq_mask);
1918 if (!dev->irq) {
1919 if (pcnet32_debug & NETIF_MSG_PROBE)
1920 printk(", failed to detect IRQ line.\n");
1921 ret = -ENODEV;
1922 goto err_free_ring;
1923 }
1924 if (pcnet32_debug & NETIF_MSG_PROBE)
1925 printk(", probed IRQ %d.\n", dev->irq);
1926 }
1da177e4 1927
4a5e8e29
JG		 1928 /* Set the mii phy_id so that we can query the link state */
1929 if (lp->mii) {
1930 /* lp->phycount and lp->phymask are set to 0 by memset above */
1931
1932 lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1933 /* scan for PHYs */
1934 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1935 unsigned short id1, id2;
1936
1937 id1 = mdio_read(dev, i, MII_PHYSID1);
1938 if (id1 == 0xffff)
1939 continue;
1940 id2 = mdio_read(dev, i, MII_PHYSID2);
1941 if (id2 == 0xffff)
1942 continue;
1943 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1944 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1945 lp->phycount++;
1946 lp->phymask |= (1 << i);
1947 lp->mii_if.phy_id = i;
1948 if (pcnet32_debug & NETIF_MSG_PROBE)
1949 printk(KERN_INFO PFX
1950 "Found PHY %04x:%04x at address %d.\n",
1951 id1, id2, i);
1952 }
1953 lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1954 if (lp->phycount > 1) {
1955 lp->options |= PCNET32_PORT_MII;
1956 }
1da177e4 1957 }
4a5e8e29
JG		 1958
1959 init_timer(&lp->watchdog_timer);
1960 lp->watchdog_timer.data = (unsigned long)dev;
1961 lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1962
1963 /* The PCNET32-specific entries in the device structure. */
1964 dev->open = &pcnet32_open;
1965 dev->hard_start_xmit = &pcnet32_start_xmit;
1966 dev->stop = &pcnet32_close;
1967 dev->get_stats = &pcnet32_get_stats;
1968 dev->set_multicast_list = &pcnet32_set_multicast_list;
1969 dev->do_ioctl = &pcnet32_ioctl;
1970 dev->ethtool_ops = &pcnet32_ethtool_ops;
1971 dev->tx_timeout = pcnet32_tx_timeout;
1972 dev->watchdog_timeo = (5 * HZ);
1da177e4
LT		 1973
1974#ifdef CONFIG_NET_POLL_CONTROLLER
4a5e8e29 1975 dev->poll_controller = pcnet32_poll_controller;
1da177e4
LT		 1976#endif
1977
4a5e8e29
JG		 1978 /* Fill in the generic fields of the device structure. */
1979 if (register_netdev(dev))
1980 goto err_free_ring;
1981
1982 if (pdev) {
1983 pci_set_drvdata(pdev, dev);
1984 } else {
1985 lp->next = pcnet32_dev;
1986 pcnet32_dev = dev;
1987 }
1988
1989 if (pcnet32_debug & NETIF_MSG_PROBE)
1990 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1991 cards_found++;
1992
1993 /* enable LED writes */
1994 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1da177e4 1995
4a5e8e29
JG		 1996 return 0;
1997
1998 err_free_ring:
1999 pcnet32_free_ring(dev);
2000 err_free_consistent:
6ecb7667
DF		 2001 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
2002 lp->init_block, lp->init_dma_addr);
4a5e8e29
JG		 2003 err_free_netdev:
2004 free_netdev(dev);
2005 err_release_region:
2006 release_region(ioaddr, PCNET32_TOTAL_SIZE);
2007 return ret;
2008}
1da177e4 2009
a88c844c
DF		 2010/* if any allocation fails, caller must also call pcnet32_free_ring */
2011static int pcnet32_alloc_ring(struct net_device *dev, char *name)
eabf0415 2012{
1e56a4b4 2013 struct pcnet32_private *lp = netdev_priv(dev);
eabf0415 2014
4a5e8e29
JG		 2015 lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
2016 sizeof(struct pcnet32_tx_head) *
2017 lp->tx_ring_size,
2018 &lp->tx_ring_dma_addr);
2019 if (lp->tx_ring == NULL) {
12fa30f3 2020 if (netif_msg_drv(lp))
4a5e8e29
JG		 2021 printk("\n" KERN_ERR PFX
2022 "%s: Consistent memory allocation failed.\n",
2023 name);
2024 return -ENOMEM;
2025 }
eabf0415 2026
4a5e8e29
JG		 2027 lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
2028 sizeof(struct pcnet32_rx_head) *
2029 lp->rx_ring_size,
2030 &lp->rx_ring_dma_addr);
2031 if (lp->rx_ring == NULL) {
12fa30f3 2032 if (netif_msg_drv(lp))
4a5e8e29
JG		 2033 printk("\n" KERN_ERR PFX
2034 "%s: Consistent memory allocation failed.\n",
2035 name);
2036 return -ENOMEM;
2037 }
eabf0415 2038
12fa30f3 2039 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
4a5e8e29
JG		 2040 GFP_ATOMIC);
2041 if (!lp->tx_dma_addr) {
12fa30f3 2042 if (netif_msg_drv(lp))
4a5e8e29
JG		 2043 printk("\n" KERN_ERR PFX
2044 "%s: Memory allocation failed.\n", name);
2045 return -ENOMEM;
2046 }
4a5e8e29 2047
12fa30f3 2048 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
4a5e8e29
JG		 2049 GFP_ATOMIC);
2050 if (!lp->rx_dma_addr) {
12fa30f3 2051 if (netif_msg_drv(lp))
4a5e8e29
JG		 2052 printk("\n" KERN_ERR PFX
2053 "%s: Memory allocation failed.\n", name);
2054 return -ENOMEM;
2055 }
4a5e8e29 2056
12fa30f3 2057 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
4a5e8e29
JG		 2058 GFP_ATOMIC);
2059 if (!lp->tx_skbuff) {
12fa30f3 2060 if (netif_msg_drv(lp))
4a5e8e29
JG		 2061 printk("\n" KERN_ERR PFX
2062 "%s: Memory allocation failed.\n", name);
2063 return -ENOMEM;
2064 }
4a5e8e29 2065
12fa30f3 2066 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
4a5e8e29
JG		 2067 GFP_ATOMIC);
2068 if (!lp->rx_skbuff) {
12fa30f3 2069 if (netif_msg_drv(lp))
4a5e8e29
JG		 2070 printk("\n" KERN_ERR PFX
2071 "%s: Memory allocation failed.\n", name);
2072 return -ENOMEM;
2073 }
4a5e8e29
JG		 2074
2075 return 0;
2076}
eabf0415
HWL		 2077
2078static void pcnet32_free_ring(struct net_device *dev)
2079{
1e56a4b4 2080 struct pcnet32_private *lp = netdev_priv(dev);
eabf0415 2081
4a5e8e29
JG		 2082 kfree(lp->tx_skbuff);
2083 lp->tx_skbuff = NULL;
eabf0415 2084
4a5e8e29
JG		 2085 kfree(lp->rx_skbuff);
2086 lp->rx_skbuff = NULL;
eabf0415 2087
4a5e8e29
JG		 2088 kfree(lp->tx_dma_addr);
2089 lp->tx_dma_addr = NULL;
eabf0415 2090
4a5e8e29
JG		 2091 kfree(lp->rx_dma_addr);
2092 lp->rx_dma_addr = NULL;
eabf0415 2093
4a5e8e29
JG		 2094 if (lp->tx_ring) {
2095 pci_free_consistent(lp->pci_dev,
2096 sizeof(struct pcnet32_tx_head) *
2097 lp->tx_ring_size, lp->tx_ring,
2098 lp->tx_ring_dma_addr);
2099 lp->tx_ring = NULL;
2100 }
eabf0415 2101
4a5e8e29
JG		 2102 if (lp->rx_ring) {
2103 pci_free_consistent(lp->pci_dev,
2104 sizeof(struct pcnet32_rx_head) *
2105 lp->rx_ring_size, lp->rx_ring,
2106 lp->rx_ring_dma_addr);
2107 lp->rx_ring = NULL;
2108 }
eabf0415
HWL		 2109}
2110
4a5e8e29 2111static int pcnet32_open(struct net_device *dev)
1da177e4 2112{
1e56a4b4 2113 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2114 unsigned long ioaddr = dev->base_addr;
2115 u16 val;
2116 int i;
2117 int rc;
2118 unsigned long flags;
2119
2120 if (request_irq(dev->irq, &pcnet32_interrupt,
1fb9df5d 2121 lp->shared_irq ? IRQF_SHARED : 0, dev->name,
4a5e8e29
JG		 2122 (void *)dev)) {
2123 return -EAGAIN;
2124 }
2125
2126 spin_lock_irqsave(&lp->lock, flags);
2127 /* Check for a valid station address */
2128 if (!is_valid_ether_addr(dev->dev_addr)) {
2129 rc = -EINVAL;
2130 goto err_free_irq;
2131 }
2132
2133 /* Reset the PCNET32 */
2134 lp->a.reset(ioaddr);
2135
2136 /* switch pcnet32 to 32bit mode */
2137 lp->a.write_bcr(ioaddr, 20, 2);
2138
2139 if (netif_msg_ifup(lp))
2140 printk(KERN_DEBUG
2141 "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
2142 dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr),
2143 (u32) (lp->rx_ring_dma_addr),
6ecb7667 2144 (u32) (lp->init_dma_addr));
4a5e8e29
JG		 2145
2146 /* set/reset autoselect bit */
2147 val = lp->a.read_bcr(ioaddr, 2) & ~2;
2148 if (lp->options & PCNET32_PORT_ASEL)
1da177e4 2149 val |= 2;
4a5e8e29
JG		 2150 lp->a.write_bcr(ioaddr, 2, val);
2151
2152 /* handle full duplex setting */
2153 if (lp->mii_if.full_duplex) {
2154 val = lp->a.read_bcr(ioaddr, 9) & ~3;
2155 if (lp->options & PCNET32_PORT_FD) {
2156 val |= 1;
2157 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2158 val |= 2;
2159 } else if (lp->options & PCNET32_PORT_ASEL) {
2160 /* workaround of xSeries250, turn on for 79C975 only */
8d916266 2161 if (lp->chip_version == 0x2627)
4a5e8e29
JG		 2162 val |= 3;
2163 }
2164 lp->a.write_bcr(ioaddr, 9, val);
2165 }
2166
2167 /* set/reset GPSI bit in test register */
2168 val = lp->a.read_csr(ioaddr, 124) & ~0x10;
2169 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2170 val |= 0x10;
2171 lp->a.write_csr(ioaddr, 124, val);
2172
2173 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2174 if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2964bbd7
DF		 2175 (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2176 lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
ac62ef04 2177 if (lp->options & PCNET32_PORT_ASEL) {
4a5e8e29
JG		 2178 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2179 if (netif_msg_link(lp))
2180 printk(KERN_DEBUG
2181 "%s: Setting 100Mb-Full Duplex.\n",
2182 dev->name);
2183 }
2184 }
2185 if (lp->phycount < 2) {
2186 /*
2187 * 24 Jun 2004 according AMD, in order to change the PHY,
2188 * DANAS (or DISPM for 79C976) must be set; then select the speed,
2189 * duplex, and/or enable auto negotiation, and clear DANAS
2190 */
2191 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2192 lp->a.write_bcr(ioaddr, 32,
2193 lp->a.read_bcr(ioaddr, 32) | 0x0080);
2194 /* disable Auto Negotiation, set 10Mpbs, HD */
2195 val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
2196 if (lp->options & PCNET32_PORT_FD)
2197 val |= 0x10;
2198 if (lp->options & PCNET32_PORT_100)
2199 val |= 0x08;
2200 lp->a.write_bcr(ioaddr, 32, val);
2201 } else {
2202 if (lp->options & PCNET32_PORT_ASEL) {
2203 lp->a.write_bcr(ioaddr, 32,
2204 lp->a.read_bcr(ioaddr,
2205 32) | 0x0080);
2206 /* enable auto negotiate, setup, disable fd */
2207 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
2208 val |= 0x20;
2209 lp->a.write_bcr(ioaddr, 32, val);
2210 }
2211 }
2212 } else {
2213 int first_phy = -1;
2214 u16 bmcr;
2215 u32 bcr9;
2216 struct ethtool_cmd ecmd;
2217
2218 /*
2219 * There is really no good other way to handle multiple PHYs
2220 * other than turning off all automatics
2221 */
2222 val = lp->a.read_bcr(ioaddr, 2);
2223 lp->a.write_bcr(ioaddr, 2, val & ~2);
2224 val = lp->a.read_bcr(ioaddr, 32);
2225 lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
2226
2227 if (!(lp->options & PCNET32_PORT_ASEL)) {
2228 /* setup ecmd */
2229 ecmd.port = PORT_MII;
2230 ecmd.transceiver = XCVR_INTERNAL;
2231 ecmd.autoneg = AUTONEG_DISABLE;
2232 ecmd.speed =
2233 lp->
2234 options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
2235 bcr9 = lp->a.read_bcr(ioaddr, 9);
2236
2237 if (lp->options & PCNET32_PORT_FD) {
2238 ecmd.duplex = DUPLEX_FULL;
2239 bcr9 |= (1 << 0);
2240 } else {
2241 ecmd.duplex = DUPLEX_HALF;
2242 bcr9 |= ~(1 << 0);
2243 }
2244 lp->a.write_bcr(ioaddr, 9, bcr9);
ac62ef04 2245 }
4a5e8e29
JG		 2246
2247 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2248 if (lp->phymask & (1 << i)) {
2249 /* isolate all but the first PHY */
2250 bmcr = mdio_read(dev, i, MII_BMCR);
2251 if (first_phy == -1) {
2252 first_phy = i;
2253 mdio_write(dev, i, MII_BMCR,
2254 bmcr & ~BMCR_ISOLATE);
2255 } else {
2256 mdio_write(dev, i, MII_BMCR,
2257 bmcr | BMCR_ISOLATE);
2258 }
2259 /* use mii_ethtool_sset to setup PHY */
2260 lp->mii_if.phy_id = i;
2261 ecmd.phy_address = i;
2262 if (lp->options & PCNET32_PORT_ASEL) {
2263 mii_ethtool_gset(&lp->mii_if, &ecmd);
2264 ecmd.autoneg = AUTONEG_ENABLE;
2265 }
2266 mii_ethtool_sset(&lp->mii_if, &ecmd);
2267 }
2268 }
2269 lp->mii_if.phy_id = first_phy;
2270 if (netif_msg_link(lp))
2271 printk(KERN_INFO "%s: Using PHY number %d.\n",
2272 dev->name, first_phy);
2273 }
1da177e4
LT		 2274
2275#ifdef DO_DXSUFLO
4a5e8e29 2276 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
b368a3fb 2277 val = lp->a.read_csr(ioaddr, CSR3);
4a5e8e29 2278 val |= 0x40;
b368a3fb 2279 lp->a.write_csr(ioaddr, CSR3, val);
4a5e8e29 2280 }
1da177e4
LT		 2281#endif
2282
6ecb7667 2283 lp->init_block->mode =
3e33545b 2284 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
4a5e8e29
JG		 2285 pcnet32_load_multicast(dev);
2286
2287 if (pcnet32_init_ring(dev)) {
2288 rc = -ENOMEM;
2289 goto err_free_ring;
2290 }
2291
bea3348e
SH		 2292#ifdef CONFIG_PCNET32_NAPI
2293 napi_enable(&lp->napi);
2294#endif
2295
4a5e8e29 2296 /* Re-initialize the PCNET32, and start it when done. */
6ecb7667
DF		 2297 lp->a.write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
2298 lp->a.write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
4a5e8e29 2299
b368a3fb
DF		 2300 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2301 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
4a5e8e29
JG		 2302
2303 netif_start_queue(dev);
2304
8d916266
DF		 2305 if (lp->chip_version >= PCNET32_79C970A) {
2306 /* Print the link status and start the watchdog */
2307 pcnet32_check_media(dev, 1);
2308 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2309 }
4a5e8e29
JG		 2310
2311 i = 0;
2312 while (i++ < 100)
b368a3fb 2313 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
4a5e8e29
JG		 2314 break;
2315 /*
2316 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2317 * reports that doing so triggers a bug in the '974.
2318 */
b368a3fb 2319 lp->a.write_csr(ioaddr, CSR0, CSR0_NORMAL);
4a5e8e29
JG		 2320
2321 if (netif_msg_ifup(lp))
2322 printk(KERN_DEBUG
2323 "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
2324 dev->name, i,
6ecb7667 2325 (u32) (lp->init_dma_addr),
b368a3fb 2326 lp->a.read_csr(ioaddr, CSR0));
4a5e8e29
JG		 2327
2328 spin_unlock_irqrestore(&lp->lock, flags);
2329
2330 return 0; /* Always succeed */
2331
2332 err_free_ring:
2333 /* free any allocated skbuffs */
ac5bfe40 2334 pcnet32_purge_rx_ring(dev);
4a5e8e29 2335
4a5e8e29
JG		 2336 /*
2337 * Switch back to 16bit mode to avoid problems with dumb
2338 * DOS packet driver after a warm reboot
2339 */
2340 lp->a.write_bcr(ioaddr, 20, 4);
2341
2342 err_free_irq:
2343 spin_unlock_irqrestore(&lp->lock, flags);
2344 free_irq(dev->irq, dev);
2345 return rc;
1da177e4
LT		 2346}
2347
2348/*
2349 * The LANCE has been halted for one reason or another (busmaster memory
2350 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2351 * etc.). Modern LANCE variants always reload their ring-buffer
2352 * configuration when restarted, so we must reinitialize our ring
2353 * context before restarting. As part of this reinitialization,
2354 * find all packets still on the Tx ring and pretend that they had been
2355 * sent (in effect, drop the packets on the floor) - the higher-level
2356 * protocols will time out and retransmit. It'd be better to shuffle
2357 * these skbs to a temp list and then actually re-Tx them after
2358 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2359 */
2360
4a5e8e29 2361static void pcnet32_purge_tx_ring(struct net_device *dev)
1da177e4 2362{
1e56a4b4 2363 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2364 int i;
1da177e4 2365
4a5e8e29
JG		 2366 for (i = 0; i < lp->tx_ring_size; i++) {
2367 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2368 wmb(); /* Make sure adapter sees owner change */
2369 if (lp->tx_skbuff[i]) {
2370 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2371 lp->tx_skbuff[i]->len,
2372 PCI_DMA_TODEVICE);
2373 dev_kfree_skb_any(lp->tx_skbuff[i]);
2374 }
2375 lp->tx_skbuff[i] = NULL;
2376 lp->tx_dma_addr[i] = 0;
2377 }
2378}
1da177e4
LT		 2379
2380/* Initialize the PCNET32 Rx and Tx rings. */
4a5e8e29 2381static int pcnet32_init_ring(struct net_device *dev)
1da177e4 2382{
1e56a4b4 2383 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2384 int i;
2385
2386 lp->tx_full = 0;
2387 lp->cur_rx = lp->cur_tx = 0;
2388 lp->dirty_rx = lp->dirty_tx = 0;
2389
2390 for (i = 0; i < lp->rx_ring_size; i++) {
2391 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2392 if (rx_skbuff == NULL) {
2393 if (!
2394 (rx_skbuff = lp->rx_skbuff[i] =
2395 dev_alloc_skb(PKT_BUF_SZ))) {
2396 /* there is not much, we can do at this point */
b368a3fb 2397 if (netif_msg_drv(lp))
4a5e8e29
JG		 2398 printk(KERN_ERR
2399 "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
2400 dev->name);
2401 return -1;
2402 }
2403 skb_reserve(rx_skbuff, 2);
2404 }
2405
2406 rmb();
2407 if (lp->rx_dma_addr[i] == 0)
2408 lp->rx_dma_addr[i] =
2409 pci_map_single(lp->pci_dev, rx_skbuff->data,
2410 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
3e33545b
AV		 2411 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);
2412 lp->rx_ring[i].buf_length = cpu_to_le16(2 - PKT_BUF_SZ);
4a5e8e29 2413 wmb(); /* Make sure owner changes after all others are visible */
3e33545b 2414 lp->rx_ring[i].status = cpu_to_le16(0x8000);
4a5e8e29
JG		 2415 }
2416 /* The Tx buffer address is filled in as needed, but we do need to clear
2417 * the upper ownership bit. */
2418 for (i = 0; i < lp->tx_ring_size; i++) {
2419 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2420 wmb(); /* Make sure adapter sees owner change */
2421 lp->tx_ring[i].base = 0;
2422 lp->tx_dma_addr[i] = 0;
2423 }
2424
6ecb7667 2425 lp->init_block->tlen_rlen =
3e33545b 2426 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
4a5e8e29 2427 for (i = 0; i < 6; i++)
6ecb7667 2428 lp->init_block->phys_addr[i] = dev->dev_addr[i];
3e33545b
AV		 2429 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
2430 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
4a5e8e29
JG		 2431 wmb(); /* Make sure all changes are visible */
2432 return 0;
1da177e4
LT		 2433}
2434
2435/* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2436 * then flush the pending transmit operations, re-initialize the ring,
2437 * and tell the chip to initialize.
2438 */
4a5e8e29 2439static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
1da177e4 2440{
1e56a4b4 2441 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2442 unsigned long ioaddr = dev->base_addr;
2443 int i;
1da177e4 2444
4a5e8e29
JG		 2445 /* wait for stop */
2446 for (i = 0; i < 100; i++)
b368a3fb 2447 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_STOP)
4a5e8e29 2448 break;
1da177e4 2449
4a5e8e29
JG		 2450 if (i >= 100 && netif_msg_drv(lp))
2451 printk(KERN_ERR
2452 "%s: pcnet32_restart timed out waiting for stop.\n",
2453 dev->name);
1da177e4 2454
4a5e8e29
JG		 2455 pcnet32_purge_tx_ring(dev);
2456 if (pcnet32_init_ring(dev))
2457 return;
1da177e4 2458
4a5e8e29 2459 /* ReInit Ring */
b368a3fb 2460 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
4a5e8e29
JG		 2461 i = 0;
2462 while (i++ < 1000)
b368a3fb 2463 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
4a5e8e29 2464 break;
1da177e4 2465
b368a3fb 2466 lp->a.write_csr(ioaddr, CSR0, csr0_bits);
1da177e4
LT		 2467}
2468
4a5e8e29 2469static void pcnet32_tx_timeout(struct net_device *dev)
1da177e4 2470{
1e56a4b4 2471 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2472 unsigned long ioaddr = dev->base_addr, flags;
2473
2474 spin_lock_irqsave(&lp->lock, flags);
2475 /* Transmitter timeout, serious problems. */
2476 if (pcnet32_debug & NETIF_MSG_DRV)
2477 printk(KERN_ERR
2478 "%s: transmit timed out, status %4.4x, resetting.\n",
b368a3fb
DF		 2479 dev->name, lp->a.read_csr(ioaddr, CSR0));
2480 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
4a5e8e29
JG		 2481 lp->stats.tx_errors++;
2482 if (netif_msg_tx_err(lp)) {
2483 int i;
2484 printk(KERN_DEBUG
2485 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2486 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2487 lp->cur_rx);
2488 for (i = 0; i < lp->rx_ring_size; i++)
2489 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2490 le32_to_cpu(lp->rx_ring[i].base),
2491 (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2492 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2493 le16_to_cpu(lp->rx_ring[i].status));
2494 for (i = 0; i < lp->tx_ring_size; i++)
2495 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2496 le32_to_cpu(lp->tx_ring[i].base),
2497 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2498 le32_to_cpu(lp->tx_ring[i].misc),
2499 le16_to_cpu(lp->tx_ring[i].status));
2500 printk("\n");
2501 }
b368a3fb 2502 pcnet32_restart(dev, CSR0_NORMAL);
1da177e4 2503
4a5e8e29
JG		 2504 dev->trans_start = jiffies;
2505 netif_wake_queue(dev);
1da177e4 2506
4a5e8e29
JG		 2507 spin_unlock_irqrestore(&lp->lock, flags);
2508}
2509
2510static int pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 2511{
1e56a4b4 2512 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2513 unsigned long ioaddr = dev->base_addr;
2514 u16 status;
2515 int entry;
2516 unsigned long flags;
1da177e4 2517
4a5e8e29 2518 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2519
4a5e8e29
JG		 2520 if (netif_msg_tx_queued(lp)) {
2521 printk(KERN_DEBUG
2522 "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
b368a3fb 2523 dev->name, lp->a.read_csr(ioaddr, CSR0));
4a5e8e29 2524 }
1da177e4 2525
4a5e8e29
JG		 2526 /* Default status -- will not enable Successful-TxDone
2527 * interrupt when that option is available to us.
2528 */
2529 status = 0x8300;
1da177e4 2530
4a5e8e29 2531 /* Fill in a Tx ring entry */
1da177e4 2532
4a5e8e29
JG		 2533 /* Mask to ring buffer boundary. */
2534 entry = lp->cur_tx & lp->tx_mod_mask;
1da177e4 2535
4a5e8e29
JG		 2536 /* Caution: the write order is important here, set the status
2537 * with the "ownership" bits last. */
1da177e4 2538
3e33545b 2539 lp->tx_ring[entry].length = cpu_to_le16(-skb->len);
1da177e4 2540
4a5e8e29 2541 lp->tx_ring[entry].misc = 0x00000000;
1da177e4 2542
4a5e8e29
JG		 2543 lp->tx_skbuff[entry] = skb;
2544 lp->tx_dma_addr[entry] =
2545 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
3e33545b 2546 lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);
4a5e8e29 2547 wmb(); /* Make sure owner changes after all others are visible */
3e33545b 2548 lp->tx_ring[entry].status = cpu_to_le16(status);
1da177e4 2549
4a5e8e29
JG		 2550 lp->cur_tx++;
2551 lp->stats.tx_bytes += skb->len;
1da177e4 2552
4a5e8e29 2553 /* Trigger an immediate send poll. */
b368a3fb 2554 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
1da177e4 2555
4a5e8e29 2556 dev->trans_start = jiffies;
1da177e4 2557
4a5e8e29
JG		 2558 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2559 lp->tx_full = 1;
2560 netif_stop_queue(dev);
2561 }
2562 spin_unlock_irqrestore(&lp->lock, flags);
2563 return 0;
1da177e4
LT		 2564}
2565
2566/* The PCNET32 interrupt handler. */
2567static irqreturn_t
7d12e780 2568pcnet32_interrupt(int irq, void *dev_id)
1da177e4 2569{
4a5e8e29
JG		 2570 struct net_device *dev = dev_id;
2571 struct pcnet32_private *lp;
2572 unsigned long ioaddr;
5c99346a 2573 u16 csr0;
4a5e8e29 2574 int boguscnt = max_interrupt_work;
4a5e8e29 2575
4a5e8e29 2576 ioaddr = dev->base_addr;
1e56a4b4 2577 lp = netdev_priv(dev);
1da177e4 2578
4a5e8e29
JG		 2579 spin_lock(&lp->lock);
2580
3904c324
DF		 2581 csr0 = lp->a.read_csr(ioaddr, CSR0);
2582 while ((csr0 & 0x8f00) && --boguscnt >= 0) {
4a5e8e29
JG		 2583 if (csr0 == 0xffff) {
2584 break; /* PCMCIA remove happened */
2585 }
2586 /* Acknowledge all of the current interrupt sources ASAP. */
3904c324 2587 lp->a.write_csr(ioaddr, CSR0, csr0 & ~0x004f);
4a5e8e29 2588
4a5e8e29
JG		 2589 if (netif_msg_intr(lp))
2590 printk(KERN_DEBUG
2591 "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
3904c324 2592 dev->name, csr0, lp->a.read_csr(ioaddr, CSR0));
4a5e8e29 2593
4a5e8e29
JG		 2594 /* Log misc errors. */
2595 if (csr0 & 0x4000)
2596 lp->stats.tx_errors++; /* Tx babble. */
2597 if (csr0 & 0x1000) {
2598 /*
3904c324
DF		 2599 * This happens when our receive ring is full. This
2600 * shouldn't be a problem as we will see normal rx
2601 * interrupts for the frames in the receive ring. But
2602 * there are some PCI chipsets (I can reproduce this
2603 * on SP3G with Intel saturn chipset) which have
2604 * sometimes problems and will fill up the receive
2605 * ring with error descriptors. In this situation we
2606 * don't get a rx interrupt, but a missed frame
7de745e5 2607 * interrupt sooner or later.
4a5e8e29 2608 */
4a5e8e29
JG		 2609 lp->stats.rx_errors++; /* Missed a Rx frame. */
2610 }
2611 if (csr0 & 0x0800) {
2612 if (netif_msg_drv(lp))
2613 printk(KERN_ERR
2614 "%s: Bus master arbitration failure, status %4.4x.\n",
2615 dev->name, csr0);
2616 /* unlike for the lance, there is no restart needed */
1da177e4 2617 }
7de745e5 2618#ifdef CONFIG_PCNET32_NAPI
bea3348e 2619 if (netif_rx_schedule_prep(dev, &lp->napi)) {
7de745e5
DF		 2620 u16 val;
2621 /* set interrupt masks */
2622 val = lp->a.read_csr(ioaddr, CSR3);
2623 val |= 0x5f00;
2624 lp->a.write_csr(ioaddr, CSR3, val);
2625 mmiowb();
bea3348e 2626 __netif_rx_schedule(dev, &lp->napi);
7de745e5
DF		 2627 break;
2628 }
2629#else
bea3348e 2630 pcnet32_rx(dev, lp->napi.weight);
7de745e5 2631 if (pcnet32_tx(dev)) {
4a5e8e29
JG		 2632 /* reset the chip to clear the error condition, then restart */
2633 lp->a.reset(ioaddr);
7de745e5 2634 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
b368a3fb 2635 pcnet32_restart(dev, CSR0_START);
4a5e8e29 2636 netif_wake_queue(dev);
1da177e4 2637 }
7de745e5 2638#endif
3904c324 2639 csr0 = lp->a.read_csr(ioaddr, CSR0);
4a5e8e29
JG		 2640 }
2641
7de745e5 2642#ifndef CONFIG_PCNET32_NAPI
4a5e8e29 2643 /* Set interrupt enable. */
b368a3fb 2644 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
7de745e5 2645#endif
4a5e8e29
JG		 2646
2647 if (netif_msg_intr(lp))
2648 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
b368a3fb 2649 dev->name, lp->a.read_csr(ioaddr, CSR0));
4a5e8e29
JG		 2650
2651 spin_unlock(&lp->lock);
2652
2653 return IRQ_HANDLED;
1da177e4
LT		 2654}
2655
4a5e8e29 2656static int pcnet32_close(struct net_device *dev)
1da177e4 2657{
4a5e8e29 2658 unsigned long ioaddr = dev->base_addr;
1e56a4b4 2659 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2660 unsigned long flags;
1da177e4 2661
4a5e8e29 2662 del_timer_sync(&lp->watchdog_timer);
1da177e4 2663
4a5e8e29 2664 netif_stop_queue(dev);
bea3348e
SH		 2665#ifdef CONFIG_PCNET32_NAPI
2666 napi_disable(&lp->napi);
2667#endif
1da177e4 2668
4a5e8e29 2669 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2670
4a5e8e29 2671 lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
1da177e4 2672
4a5e8e29
JG		 2673 if (netif_msg_ifdown(lp))
2674 printk(KERN_DEBUG
2675 "%s: Shutting down ethercard, status was %2.2x.\n",
b368a3fb 2676 dev->name, lp->a.read_csr(ioaddr, CSR0));
1da177e4 2677
4a5e8e29 2678 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
b368a3fb 2679 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
1da177e4 2680
4a5e8e29
JG		 2681 /*
2682 * Switch back to 16bit mode to avoid problems with dumb
2683 * DOS packet driver after a warm reboot
2684 */
2685 lp->a.write_bcr(ioaddr, 20, 4);
1da177e4 2686
4a5e8e29 2687 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2688
4a5e8e29 2689 free_irq(dev->irq, dev);
1da177e4 2690
4a5e8e29 2691 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2692
ac5bfe40
DF		 2693 pcnet32_purge_rx_ring(dev);
2694 pcnet32_purge_tx_ring(dev);
1da177e4 2695
4a5e8e29 2696 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2697
4a5e8e29 2698 return 0;
1da177e4
LT		 2699}
2700
4a5e8e29 2701static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
1da177e4 2702{
1e56a4b4 2703 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2704 unsigned long ioaddr = dev->base_addr;
4a5e8e29
JG		 2705 unsigned long flags;
2706
2707 spin_lock_irqsave(&lp->lock, flags);
4a5e8e29 2708 lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
4a5e8e29
JG		 2709 spin_unlock_irqrestore(&lp->lock, flags);
2710
2711 return &lp->stats;
1da177e4
LT		 2712}
2713
2714/* taken from the sunlance driver, which it took from the depca driver */
4a5e8e29 2715static void pcnet32_load_multicast(struct net_device *dev)
1da177e4 2716{
1e56a4b4 2717 struct pcnet32_private *lp = netdev_priv(dev);
6ecb7667 2718 volatile struct pcnet32_init_block *ib = lp->init_block;
3e33545b 2719 volatile __le16 *mcast_table = (__le16 *)ib->filter;
4a5e8e29 2720 struct dev_mc_list *dmi = dev->mc_list;
df27f4a6 2721 unsigned long ioaddr = dev->base_addr;
4a5e8e29
JG		 2722 char *addrs;
2723 int i;
2724 u32 crc;
2725
2726 /* set all multicast bits */
2727 if (dev->flags & IFF_ALLMULTI) {
3e33545b
AV		 2728 ib->filter[0] = cpu_to_le32(~0U);
2729 ib->filter[1] = cpu_to_le32(~0U);
df27f4a6
DF		 2730 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2731 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2732 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2733 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
4a5e8e29
JG		 2734 return;
2735 }
2736 /* clear the multicast filter */
2737 ib->filter[0] = 0;
2738 ib->filter[1] = 0;
2739
2740 /* Add addresses */
2741 for (i = 0; i < dev->mc_count; i++) {
2742 addrs = dmi->dmi_addr;
2743 dmi = dmi->next;
2744
2745 /* multicast address? */
2746 if (!(*addrs & 1))
2747 continue;
2748
2749 crc = ether_crc_le(6, addrs);
2750 crc = crc >> 26;
3e33545b 2751 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
4a5e8e29 2752 }
df27f4a6
DF		 2753 for (i = 0; i < 4; i++)
2754 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
2755 le16_to_cpu(mcast_table[i]));
1da177e4 2756 return;
1da177e4
LT		 2757}
2758
1da177e4
LT		 2759/*
2760 * Set or clear the multicast filter for this adaptor.
2761 */
2762static void pcnet32_set_multicast_list(struct net_device *dev)
2763{
4a5e8e29 2764 unsigned long ioaddr = dev->base_addr, flags;
1e56a4b4 2765 struct pcnet32_private *lp = netdev_priv(dev);
df27f4a6 2766 int csr15, suspended;
4a5e8e29
JG		 2767
2768 spin_lock_irqsave(&lp->lock, flags);
df27f4a6
DF		 2769 suspended = pcnet32_suspend(dev, &flags, 0);
2770 csr15 = lp->a.read_csr(ioaddr, CSR15);
4a5e8e29
JG		 2771 if (dev->flags & IFF_PROMISC) {
2772 /* Log any net taps. */
2773 if (netif_msg_hw(lp))
2774 printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
2775 dev->name);
6ecb7667 2776 lp->init_block->mode =
3e33545b 2777 cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
4a5e8e29 2778 7);
df27f4a6 2779 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
4a5e8e29 2780 } else {
6ecb7667 2781 lp->init_block->mode =
3e33545b 2782 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
df27f4a6 2783 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
4a5e8e29
JG		 2784 pcnet32_load_multicast(dev);
2785 }
2786
df27f4a6
DF		 2787 if (suspended) {
2788 int csr5;
2789 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2790 csr5 = lp->a.read_csr(ioaddr, CSR5);
2791 lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
b368a3fb 2792 } else {
df27f4a6
DF		 2793 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2794 pcnet32_restart(dev, CSR0_NORMAL);
2795 netif_wake_queue(dev);
2796 }
4a5e8e29
JG		 2797
2798 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4
LT		 2799}
2800
2801/* This routine assumes that the lp->lock is held */
2802static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2803{
1e56a4b4 2804 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2805 unsigned long ioaddr = dev->base_addr;
2806 u16 val_out;
1da177e4 2807
4a5e8e29
JG		 2808 if (!lp->mii)
2809 return 0;
1da177e4 2810
4a5e8e29
JG		 2811 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2812 val_out = lp->a.read_bcr(ioaddr, 34);
1da177e4 2813
4a5e8e29 2814 return val_out;
1da177e4
LT		 2815}
2816
2817/* This routine assumes that the lp->lock is held */
2818static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2819{
1e56a4b4 2820 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2821 unsigned long ioaddr = dev->base_addr;
1da177e4 2822
4a5e8e29
JG		 2823 if (!lp->mii)
2824 return;
1da177e4 2825
4a5e8e29
JG		 2826 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2827 lp->a.write_bcr(ioaddr, 34, val);
1da177e4
LT		 2828}
2829
2830static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2831{
1e56a4b4 2832 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2833 int rc;
2834 unsigned long flags;
1da177e4 2835
4a5e8e29
JG		 2836 /* SIOC[GS]MIIxxx ioctls */
2837 if (lp->mii) {
2838 spin_lock_irqsave(&lp->lock, flags);
2839 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2840 spin_unlock_irqrestore(&lp->lock, flags);
2841 } else {
2842 rc = -EOPNOTSUPP;
2843 }
1da177e4 2844
4a5e8e29 2845 return rc;
1da177e4
LT		 2846}
2847
ac62ef04
DF		 2848static int pcnet32_check_otherphy(struct net_device *dev)
2849{
1e56a4b4 2850 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2851 struct mii_if_info mii = lp->mii_if;
2852 u16 bmcr;
2853 int i;
ac62ef04 2854
4a5e8e29
JG		 2855 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2856 if (i == lp->mii_if.phy_id)
2857 continue; /* skip active phy */
2858 if (lp->phymask & (1 << i)) {
2859 mii.phy_id = i;
2860 if (mii_link_ok(&mii)) {
2861 /* found PHY with active link */
2862 if (netif_msg_link(lp))
2863 printk(KERN_INFO
2864 "%s: Using PHY number %d.\n",
2865 dev->name, i);
2866
2867 /* isolate inactive phy */
2868 bmcr =
2869 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2870 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2871 bmcr | BMCR_ISOLATE);
2872
2873 /* de-isolate new phy */
2874 bmcr = mdio_read(dev, i, MII_BMCR);
2875 mdio_write(dev, i, MII_BMCR,
2876 bmcr & ~BMCR_ISOLATE);
2877
2878 /* set new phy address */
2879 lp->mii_if.phy_id = i;
2880 return 1;
2881 }
2882 }
ac62ef04 2883 }
4a5e8e29 2884 return 0;
ac62ef04
DF		 2885}
2886
2887/*
2888 * Show the status of the media. Similar to mii_check_media however it
2889 * correctly shows the link speed for all (tested) pcnet32 variants.
2890 * Devices with no mii just report link state without speed.
2891 *
2892 * Caller is assumed to hold and release the lp->lock.
2893 */
2894
2895static void pcnet32_check_media(struct net_device *dev, int verbose)
2896{
1e56a4b4 2897 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2898 int curr_link;
2899 int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2900 u32 bcr9;
2901
ac62ef04 2902 if (lp->mii) {
4a5e8e29 2903 curr_link = mii_link_ok(&lp->mii_if);
ac62ef04 2904 } else {
4a5e8e29
JG		 2905 ulong ioaddr = dev->base_addr; /* card base I/O address */
2906 curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
2907 }
2908 if (!curr_link) {
2909 if (prev_link || verbose) {
2910 netif_carrier_off(dev);
2911 if (netif_msg_link(lp))
2912 printk(KERN_INFO "%s: link down\n", dev->name);
2913 }
2914 if (lp->phycount > 1) {
2915 curr_link = pcnet32_check_otherphy(dev);
2916 prev_link = 0;
2917 }
2918 } else if (verbose || !prev_link) {
2919 netif_carrier_on(dev);
2920 if (lp->mii) {
2921 if (netif_msg_link(lp)) {
2922 struct ethtool_cmd ecmd;
2923 mii_ethtool_gset(&lp->mii_if, &ecmd);
2924 printk(KERN_INFO
2925 "%s: link up, %sMbps, %s-duplex\n",
2926 dev->name,
2927 (ecmd.speed == SPEED_100) ? "100" : "10",
2928 (ecmd.duplex ==
2929 DUPLEX_FULL) ? "full" : "half");
2930 }
2931 bcr9 = lp->a.read_bcr(dev->base_addr, 9);
2932 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2933 if (lp->mii_if.full_duplex)
2934 bcr9 |= (1 << 0);
2935 else
2936 bcr9 &= ~(1 << 0);
2937 lp->a.write_bcr(dev->base_addr, 9, bcr9);
2938 }
2939 } else {
2940 if (netif_msg_link(lp))
2941 printk(KERN_INFO "%s: link up\n", dev->name);
2942 }
ac62ef04 2943 }
ac62ef04
DF		 2944}
2945
2946/*
2947 * Check for loss of link and link establishment.
2948 * Can not use mii_check_media because it does nothing if mode is forced.
2949 */
2950
1da177e4
LT		 2951static void pcnet32_watchdog(struct net_device *dev)
2952{
1e56a4b4 2953 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2954 unsigned long flags;
1da177e4 2955
4a5e8e29
JG		 2956 /* Print the link status if it has changed */
2957 spin_lock_irqsave(&lp->lock, flags);
2958 pcnet32_check_media(dev, 0);
2959 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2960
4a5e8e29 2961 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
1da177e4
LT		 2962}
2963
917270c6
DF		 2964static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state)
2965{
2966 struct net_device *dev = pci_get_drvdata(pdev);
2967
2968 if (netif_running(dev)) {
2969 netif_device_detach(dev);
2970 pcnet32_close(dev);
2971 }
2972 pci_save_state(pdev);
2973 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2974 return 0;
2975}
2976
2977static int pcnet32_pm_resume(struct pci_dev *pdev)
2978{
2979 struct net_device *dev = pci_get_drvdata(pdev);
2980
2981 pci_set_power_state(pdev, PCI_D0);
2982 pci_restore_state(pdev);
2983
2984 if (netif_running(dev)) {
2985 pcnet32_open(dev);
2986 netif_device_attach(dev);
2987 }
2988 return 0;
2989}
2990
1da177e4
LT		 2991static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2992{
4a5e8e29
JG		 2993 struct net_device *dev = pci_get_drvdata(pdev);
2994
2995 if (dev) {
1e56a4b4 2996 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2997
2998 unregister_netdev(dev);
2999 pcnet32_free_ring(dev);
3000 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
6ecb7667
DF		 3001 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
3002 lp->init_block, lp->init_dma_addr);
4a5e8e29
JG		 3003 free_netdev(dev);
3004 pci_disable_device(pdev);
3005 pci_set_drvdata(pdev, NULL);
3006 }
1da177e4
LT		 3007}
3008
3009static struct pci_driver pcnet32_driver = {
4a5e8e29
JG		 3010 .name = DRV_NAME,
3011 .probe = pcnet32_probe_pci,
3012 .remove = __devexit_p(pcnet32_remove_one),
3013 .id_table = pcnet32_pci_tbl,
917270c6
DF		 3014 .suspend = pcnet32_pm_suspend,
3015 .resume = pcnet32_pm_resume,
1da177e4
LT		 3016};
3017
3018/* An additional parameter that may be passed in... */
3019static int debug = -1;
3020static int tx_start_pt = -1;
3021static int pcnet32_have_pci;
3022
3023module_param(debug, int, 0);
3024MODULE_PARM_DESC(debug, DRV_NAME " debug level");
3025module_param(max_interrupt_work, int, 0);
4a5e8e29
JG		 3026MODULE_PARM_DESC(max_interrupt_work,
3027 DRV_NAME " maximum events handled per interrupt");
1da177e4 3028module_param(rx_copybreak, int, 0);
4a5e8e29
JG		 3029MODULE_PARM_DESC(rx_copybreak,
3030 DRV_NAME " copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 3031module_param(tx_start_pt, int, 0);
3032MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
3033module_param(pcnet32vlb, int, 0);
3034MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
3035module_param_array(options, int, NULL, 0);
3036MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
3037module_param_array(full_duplex, int, NULL, 0);
3038MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
3039/* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
3040module_param_array(homepna, int, NULL, 0);
4a5e8e29
JG		 3041MODULE_PARM_DESC(homepna,
3042 DRV_NAME
3043 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
1da177e4
LT		 3044
3045MODULE_AUTHOR("Thomas Bogendoerfer");
3046MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
3047MODULE_LICENSE("GPL");
3048
3049#define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
3050
3051static int __init pcnet32_init_module(void)
3052{
4a5e8e29 3053 printk(KERN_INFO "%s", version);
1da177e4 3054
4a5e8e29 3055 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
1da177e4 3056
4a5e8e29
JG		 3057 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
3058 tx_start = tx_start_pt;
1da177e4 3059
4a5e8e29 3060 /* find the PCI devices */
29917620 3061 if (!pci_register_driver(&pcnet32_driver))
4a5e8e29 3062 pcnet32_have_pci = 1;
1da177e4 3063
4a5e8e29
JG		 3064 /* should we find any remaining VLbus devices ? */
3065 if (pcnet32vlb)
dcaf9769 3066 pcnet32_probe_vlbus(pcnet32_portlist);
1da177e4 3067
4a5e8e29
JG		 3068 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
3069 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
1da177e4 3070
4a5e8e29 3071 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
1da177e4
LT		 3072}
3073
3074static void __exit pcnet32_cleanup_module(void)
3075{
4a5e8e29
JG		 3076 struct net_device *next_dev;
3077
3078 while (pcnet32_dev) {
1e56a4b4 3079 struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
4a5e8e29
JG		 3080 next_dev = lp->next;
3081 unregister_netdev(pcnet32_dev);
3082 pcnet32_free_ring(pcnet32_dev);
3083 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
6ecb7667
DF		 3084 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
3085 lp->init_block, lp->init_dma_addr);
4a5e8e29
JG		 3086 free_netdev(pcnet32_dev);
3087 pcnet32_dev = next_dev;
3088 }
1da177e4 3089
4a5e8e29
JG		 3090 if (pcnet32_have_pci)
3091 pci_unregister_driver(&pcnet32_driver);
1da177e4
LT		 3092}
3093
3094module_init(pcnet32_init_module);
3095module_exit(pcnet32_cleanup_module);
3096
3097/*
3098 * Local variables:
3099 * c-indent-level: 4
3100 * tab-width: 8
3101 * End:
3102 */
kernel source for telekom puls (alcatel/mediatek)