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Merge branch 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / drivers / net / pcmcia / nmclan_cs.c
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1da177e4
LT		 1/* ----------------------------------------------------------------------------
2Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN.
3 nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao
4
5 The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media
6 Access Controller for Ethernet (MACE). It is essentially the Am2150
7 PCMCIA Ethernet card contained in the Am2150 Demo Kit.
8
9Written by Roger C. Pao <rpao@paonet.org>
10 Copyright 1995 Roger C. Pao
11 Linux 2.5 cleanups Copyright Red Hat 2003
12
13 This software may be used and distributed according to the terms of
14 the GNU General Public License.
15
16Ported to Linux 1.3.* network driver environment by
17 Matti Aarnio <mea@utu.fi>
18
19References
20
21 Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993
22 Am79C940 (MACE) Data Sheet, 1994
23 Am79C90 (C-LANCE) Data Sheet, 1994
24 Linux PCMCIA Programmer's Guide v1.17
25 /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8
26
27 Eric Mears, New Media Corporation
28 Tom Pollard, New Media Corporation
29 Dean Siasoyco, New Media Corporation
30 Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com>
31 Donald Becker <becker@scyld.com>
32 David Hinds <dahinds@users.sourceforge.net>
33
34 The Linux client driver is based on the 3c589_cs.c client driver by
35 David Hinds.
36
37 The Linux network driver outline is based on the 3c589_cs.c driver,
38 the 8390.c driver, and the example skeleton.c kernel code, which are
39 by Donald Becker.
40
41 The Am2150 network driver hardware interface code is based on the
42 OS/9000 driver for the New Media Ethernet LAN by Eric Mears.
43
44 Special thanks for testing and help in debugging this driver goes
45 to Ken Lesniak.
46
47-------------------------------------------------------------------------------
48Driver Notes and Issues
49-------------------------------------------------------------------------------
50
511. Developed on a Dell 320SLi
52 PCMCIA Card Services 2.6.2
53 Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386
54
552. rc.pcmcia may require loading pcmcia_core with io_speed=300:
56 'insmod pcmcia_core.o io_speed=300'.
57 This will avoid problems with fast systems which causes rx_framecnt
58 to return random values.
59
603. If hot extraction does not work for you, use 'ifconfig eth0 down'
61 before extraction.
62
634. There is a bad slow-down problem in this driver.
64
655. Future: Multicast processing. In the meantime, do _not_ compile your
66 kernel with multicast ip enabled.
67
68-------------------------------------------------------------------------------
69History
70-------------------------------------------------------------------------------
71Log: nmclan_cs.c,v
113aa838 72 * 2.5.75-ac1 2003/07/11 Alan Cox <alan@lxorguk.ukuu.org.uk>
1da177e4
LT		 73 * Fixed hang on card eject as we probe it
74 * Cleaned up to use new style locking.
75 *
76 * Revision 0.16 1995/07/01 06:42:17 rpao
77 * Bug fix: nmclan_reset() called CardServices incorrectly.
78 *
79 * Revision 0.15 1995/05/24 08:09:47 rpao
80 * Re-implement MULTI_TX dev->tbusy handling.
81 *
82 * Revision 0.14 1995/05/23 03:19:30 rpao
83 * Added, in nmclan_config(), "tuple.Attributes = 0;".
84 * Modified MACE ID check to ignore chip revision level.
85 * Avoid tx_free_frames race condition between _start_xmit and _interrupt.
86 *
87 * Revision 0.13 1995/05/18 05:56:34 rpao
88 * Statistics changes.
89 * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list.
90 * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT. Fixes driver lockup.
91 *
92 * Revision 0.12 1995/05/14 00:12:23 rpao
93 * Statistics overhaul.
94 *
95
9695/05/13 rpao V0.10a
97 Bug fix: MACE statistics counters used wrong I/O ports.
98 Bug fix: mace_interrupt() needed to allow statistics to be
99 processed without RX or TX interrupts pending.
10095/05/11 rpao V0.10
101 Multiple transmit request processing.
102 Modified statistics to use MACE counters where possible.
10395/05/10 rpao V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO.
104 *Released
10595/05/10 rpao V0.08
106 Bug fix: Make all non-exported functions private by using
107 static keyword.
108 Bug fix: Test IntrCnt _before_ reading MACE_IR.
10995/05/10 rpao V0.07 Statistics.
11095/05/09 rpao V0.06 Fix rx_framecnt problem by addition of PCIC wait states.
111
112---------------------------------------------------------------------------- */
113
114#define DRV_NAME "nmclan_cs"
115#define DRV_VERSION "0.16"
116
117
118/* ----------------------------------------------------------------------------
119Conditional Compilation Options
120---------------------------------------------------------------------------- */
121
122#define MULTI_TX 0
123#define RESET_ON_TIMEOUT 1
124#define TX_INTERRUPTABLE 1
125#define RESET_XILINX 0
126
127/* ----------------------------------------------------------------------------
128Include Files
129---------------------------------------------------------------------------- */
130
131#include <linux/module.h>
132#include <linux/kernel.h>
133#include <linux/init.h>
134#include <linux/ptrace.h>
135#include <linux/slab.h>
136#include <linux/string.h>
137#include <linux/timer.h>
138#include <linux/interrupt.h>
139#include <linux/in.h>
140#include <linux/delay.h>
141#include <linux/ethtool.h>
142#include <linux/netdevice.h>
143#include <linux/etherdevice.h>
144#include <linux/skbuff.h>
145#include <linux/if_arp.h>
146#include <linux/ioport.h>
147#include <linux/bitops.h>
148
1da177e4
LT		 149#include <pcmcia/cs_types.h>
150#include <pcmcia/cs.h>
151#include <pcmcia/cisreg.h>
152#include <pcmcia/cistpl.h>
153#include <pcmcia/ds.h>
154
155#include <asm/uaccess.h>
156#include <asm/io.h>
157#include <asm/system.h>
158
159/* ----------------------------------------------------------------------------
160Defines
161---------------------------------------------------------------------------- */
162
163#define ETHER_ADDR_LEN ETH_ALEN
164 /* 6 bytes in an Ethernet Address */
165#define MACE_LADRF_LEN 8
166 /* 8 bytes in Logical Address Filter */
167
168/* Loop Control Defines */
169#define MACE_MAX_IR_ITERATIONS 10
170#define MACE_MAX_RX_ITERATIONS 12
171 /*
172 TBD: Dean brought this up, and I assumed the hardware would
173 handle it:
174
175 If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be
176 non-zero when the isr exits. We may not get another interrupt
177 to process the remaining packets for some time.
178 */
179
180/*
181The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA)
182which manages the interface between the MACE and the PCMCIA bus. It
183also includes buffer management for the 32K x 8 SRAM to control up to
184four transmit and 12 receive frames at a time.
185*/
186#define AM2150_MAX_TX_FRAMES 4
187#define AM2150_MAX_RX_FRAMES 12
188
189/* Am2150 Ethernet Card I/O Mapping */
190#define AM2150_RCV 0x00
191#define AM2150_XMT 0x04
192#define AM2150_XMT_SKIP 0x09
193#define AM2150_RCV_NEXT 0x0A
194#define AM2150_RCV_FRAME_COUNT 0x0B
195#define AM2150_MACE_BANK 0x0C
196#define AM2150_MACE_BASE 0x10
197
198/* MACE Registers */
199#define MACE_RCVFIFO 0
200#define MACE_XMTFIFO 1
201#define MACE_XMTFC 2
202#define MACE_XMTFS 3
203#define MACE_XMTRC 4
204#define MACE_RCVFC 5
205#define MACE_RCVFS 6
206#define MACE_FIFOFC 7
207#define MACE_IR 8
208#define MACE_IMR 9
209#define MACE_PR 10
210#define MACE_BIUCC 11
211#define MACE_FIFOCC 12
212#define MACE_MACCC 13
213#define MACE_PLSCC 14
214#define MACE_PHYCC 15
215#define MACE_CHIPIDL 16
216#define MACE_CHIPIDH 17
217#define MACE_IAC 18
218/* Reserved */
219#define MACE_LADRF 20
220#define MACE_PADR 21
221/* Reserved */
222/* Reserved */
223#define MACE_MPC 24
224/* Reserved */
225#define MACE_RNTPC 26
226#define MACE_RCVCC 27
227/* Reserved */
228#define MACE_UTR 29
229#define MACE_RTR1 30
230#define MACE_RTR2 31
231
232/* MACE Bit Masks */
233#define MACE_XMTRC_EXDEF 0x80
234#define MACE_XMTRC_XMTRC 0x0F
235
236#define MACE_XMTFS_XMTSV 0x80
237#define MACE_XMTFS_UFLO 0x40
238#define MACE_XMTFS_LCOL 0x20
239#define MACE_XMTFS_MORE 0x10
240#define MACE_XMTFS_ONE 0x08
241#define MACE_XMTFS_DEFER 0x04
242#define MACE_XMTFS_LCAR 0x02
243#define MACE_XMTFS_RTRY 0x01
244
245#define MACE_RCVFS_RCVSTS 0xF000
246#define MACE_RCVFS_OFLO 0x8000
247#define MACE_RCVFS_CLSN 0x4000
248#define MACE_RCVFS_FRAM 0x2000
249#define MACE_RCVFS_FCS 0x1000
250
251#define MACE_FIFOFC_RCVFC 0xF0
252#define MACE_FIFOFC_XMTFC 0x0F
253
254#define MACE_IR_JAB 0x80
255#define MACE_IR_BABL 0x40
256#define MACE_IR_CERR 0x20
257#define MACE_IR_RCVCCO 0x10
258#define MACE_IR_RNTPCO 0x08
259#define MACE_IR_MPCO 0x04
260#define MACE_IR_RCVINT 0x02
261#define MACE_IR_XMTINT 0x01
262
263#define MACE_MACCC_PROM 0x80
264#define MACE_MACCC_DXMT2PD 0x40
265#define MACE_MACCC_EMBA 0x20
266#define MACE_MACCC_RESERVED 0x10
267#define MACE_MACCC_DRCVPA 0x08
268#define MACE_MACCC_DRCVBC 0x04
269#define MACE_MACCC_ENXMT 0x02
270#define MACE_MACCC_ENRCV 0x01
271
272#define MACE_PHYCC_LNKFL 0x80
273#define MACE_PHYCC_DLNKTST 0x40
274#define MACE_PHYCC_REVPOL 0x20
275#define MACE_PHYCC_DAPC 0x10
276#define MACE_PHYCC_LRT 0x08
277#define MACE_PHYCC_ASEL 0x04
278#define MACE_PHYCC_RWAKE 0x02
279#define MACE_PHYCC_AWAKE 0x01
280
281#define MACE_IAC_ADDRCHG 0x80
282#define MACE_IAC_PHYADDR 0x04
283#define MACE_IAC_LOGADDR 0x02
284
285#define MACE_UTR_RTRE 0x80
286#define MACE_UTR_RTRD 0x40
287#define MACE_UTR_RPA 0x20
288#define MACE_UTR_FCOLL 0x10
289#define MACE_UTR_RCVFCSE 0x08
290#define MACE_UTR_LOOP_INCL_MENDEC 0x06
291#define MACE_UTR_LOOP_NO_MENDEC 0x04
292#define MACE_UTR_LOOP_EXTERNAL 0x02
293#define MACE_UTR_LOOP_NONE 0x00
294#define MACE_UTR_RESERVED 0x01
295
296/* Switch MACE register bank (only 0 and 1 are valid) */
297#define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
298
299#define MACE_IMR_DEFAULT \
300 (0xFF - \
301 ( \
302 MACE_IR_CERR | \
303 MACE_IR_RCVCCO | \
304 MACE_IR_RNTPCO | \
305 MACE_IR_MPCO | \
306 MACE_IR_RCVINT | \
307 MACE_IR_XMTINT \
308 ) \
309 )
310#undef MACE_IMR_DEFAULT
311#define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */
312
313#define TX_TIMEOUT ((400*HZ)/1000)
314
315/* ----------------------------------------------------------------------------
316Type Definitions
317---------------------------------------------------------------------------- */
318
319typedef struct _mace_statistics {
320 /* MACE_XMTFS */
321 int xmtsv;
322 int uflo;
323 int lcol;
324 int more;
325 int one;
326 int defer;
327 int lcar;
328 int rtry;
329
330 /* MACE_XMTRC */
331 int exdef;
332 int xmtrc;
333
334 /* RFS1--Receive Status (RCVSTS) */
335 int oflo;
336 int clsn;
337 int fram;
338 int fcs;
339
340 /* RFS2--Runt Packet Count (RNTPC) */
341 int rfs_rntpc;
342
343 /* RFS3--Receive Collision Count (RCVCC) */
344 int rfs_rcvcc;
345
346 /* MACE_IR */
347 int jab;
348 int babl;
349 int cerr;
350 int rcvcco;
351 int rntpco;
352 int mpco;
353
354 /* MACE_MPC */
355 int mpc;
356
357 /* MACE_RNTPC */
358 int rntpc;
359
360 /* MACE_RCVCC */
361 int rcvcc;
362} mace_statistics;
363
364typedef struct _mace_private {
fd238232 365 struct pcmcia_device *p_dev;
1da177e4
LT		 366 struct net_device_stats linux_stats; /* Linux statistics counters */
367 mace_statistics mace_stats; /* MACE chip statistics counters */
368
369 /* restore_multicast_list() state variables */
370 int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */
371 int multicast_num_addrs;
372
373 char tx_free_frames; /* Number of free transmit frame buffers */
374 char tx_irq_disabled; /* MACE TX interrupt disabled */
375
376 spinlock_t bank_lock; /* Must be held if you step off bank 0 */
377} mace_private;
378
379/* ----------------------------------------------------------------------------
380Private Global Variables
381---------------------------------------------------------------------------- */
382
f71e1309 383static const char *if_names[]={
1da177e4
LT		 384 "Auto", "10baseT", "BNC",
385};
386
387/* ----------------------------------------------------------------------------
388Parameters
389 These are the parameters that can be set during loading with
390 'insmod'.
391---------------------------------------------------------------------------- */
392
393MODULE_DESCRIPTION("New Media PCMCIA ethernet driver");
394MODULE_LICENSE("GPL");
395
396#define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
397
398/* 0=auto, 1=10baseT, 2 = 10base2, default=auto */
399INT_MODULE_PARM(if_port, 0);
400
1da177e4
LT		 401
402/* ----------------------------------------------------------------------------
403Function Prototypes
404---------------------------------------------------------------------------- */
405
15b99ac1 406static int nmclan_config(struct pcmcia_device *link);
fba395ee 407static void nmclan_release(struct pcmcia_device *link);
1da177e4
LT		 408
409static void nmclan_reset(struct net_device *dev);
410static int mace_config(struct net_device *dev, struct ifmap *map);
411static int mace_open(struct net_device *dev);
412static int mace_close(struct net_device *dev);
dbf02fae
SH		 413static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
414 struct net_device *dev);
1da177e4 415static void mace_tx_timeout(struct net_device *dev);
7d12e780 416static irqreturn_t mace_interrupt(int irq, void *dev_id);
1da177e4
LT		 417static struct net_device_stats *mace_get_stats(struct net_device *dev);
418static int mace_rx(struct net_device *dev, unsigned char RxCnt);
419static void restore_multicast_list(struct net_device *dev);
420static void set_multicast_list(struct net_device *dev);
7282d491 421static const struct ethtool_ops netdev_ethtool_ops;
1da177e4
LT		 422
423
cc3b4866 424static void nmclan_detach(struct pcmcia_device *p_dev);
1da177e4 425
28b1801d
SH		 426static const struct net_device_ops mace_netdev_ops = {
427 .ndo_open = mace_open,
428 .ndo_stop = mace_close,
429 .ndo_start_xmit = mace_start_xmit,
430 .ndo_tx_timeout = mace_tx_timeout,
431 .ndo_set_config = mace_config,
432 .ndo_get_stats = mace_get_stats,
433 .ndo_set_multicast_list = set_multicast_list,
434 .ndo_change_mtu = eth_change_mtu,
435 .ndo_set_mac_address = eth_mac_addr,
436 .ndo_validate_addr = eth_validate_addr,
437};
438
1da177e4
LT		 439/* ----------------------------------------------------------------------------
440nmclan_attach
441 Creates an "instance" of the driver, allocating local data
442 structures for one device. The device is registered with Card
443 Services.
444---------------------------------------------------------------------------- */
445
15b99ac1 446static int nmclan_probe(struct pcmcia_device *link)
1da177e4
LT		 447{
448 mace_private *lp;
1da177e4 449 struct net_device *dev;
1da177e4 450
dd0fab5b 451 dev_dbg(&link->dev, "nmclan_attach()\n");
1da177e4
LT		 452
453 /* Create new ethernet device */
454 dev = alloc_etherdev(sizeof(mace_private));
455 if (!dev)
f8cfa618 456 return -ENOMEM;
1da177e4 457 lp = netdev_priv(dev);
fba395ee 458 lp->p_dev = link;
1da177e4
LT		 459 link->priv = dev;
460
461 spin_lock_init(&lp->bank_lock);
462 link->io.NumPorts1 = 32;
463 link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
464 link->io.IOAddrLines = 5;
1da177e4 465 link->conf.Attributes = CONF_ENABLE_IRQ;
1da177e4
LT		 466 link->conf.IntType = INT_MEMORY_AND_IO;
467 link->conf.ConfigIndex = 1;
468 link->conf.Present = PRESENT_OPTION;
469
470 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
471
28b1801d 472 dev->netdev_ops = &mace_netdev_ops;
1da177e4 473 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
1da177e4 474 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4 475
15b99ac1 476 return nmclan_config(link);
1da177e4
LT		 477} /* nmclan_attach */
478
479/* ----------------------------------------------------------------------------
480nmclan_detach
481 This deletes a driver "instance". The device is de-registered
482 with Card Services. If it has been released, all local data
483 structures are freed. Otherwise, the structures will be freed
484 when the device is released.
485---------------------------------------------------------------------------- */
486
fba395ee 487static void nmclan_detach(struct pcmcia_device *link)
1da177e4
LT		 488{
489 struct net_device *dev = link->priv;
1da177e4 490
dd0fab5b 491 dev_dbg(&link->dev, "nmclan_detach\n");
1da177e4 492
c7c2fa07 493 unregister_netdev(dev);
1da177e4 494
e2d40963 495 nmclan_release(link);
1da177e4 496
1da177e4
LT		 497 free_netdev(dev);
498} /* nmclan_detach */
499
500/* ----------------------------------------------------------------------------
501mace_read
502 Reads a MACE register. This is bank independent; however, the
503 caller must ensure that this call is not interruptable. We are
504 assuming that during normal operation, the MACE is always in
505 bank 0.
506---------------------------------------------------------------------------- */
906da809 507static int mace_read(mace_private *lp, unsigned int ioaddr, int reg)
1da177e4
LT		 508{
509 int data = 0xFF;
510 unsigned long flags;
511
512 switch (reg >> 4) {
513 case 0: /* register 0-15 */
514 data = inb(ioaddr + AM2150_MACE_BASE + reg);
515 break;
516 case 1: /* register 16-31 */
517 spin_lock_irqsave(&lp->bank_lock, flags);
518 MACEBANK(1);
519 data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
520 MACEBANK(0);
521 spin_unlock_irqrestore(&lp->bank_lock, flags);
522 break;
523 }
524 return (data & 0xFF);
525} /* mace_read */
526
527/* ----------------------------------------------------------------------------
528mace_write
529 Writes to a MACE register. This is bank independent; however,
530 the caller must ensure that this call is not interruptable. We
531 are assuming that during normal operation, the MACE is always in
532 bank 0.
533---------------------------------------------------------------------------- */
906da809
OJ		 534static void mace_write(mace_private *lp, unsigned int ioaddr, int reg,
535 int data)
1da177e4
LT		 536{
537 unsigned long flags;
538
539 switch (reg >> 4) {
540 case 0: /* register 0-15 */
541 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
542 break;
543 case 1: /* register 16-31 */
544 spin_lock_irqsave(&lp->bank_lock, flags);
545 MACEBANK(1);
546 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
547 MACEBANK(0);
548 spin_unlock_irqrestore(&lp->bank_lock, flags);
549 break;
550 }
551} /* mace_write */
552
553/* ----------------------------------------------------------------------------
554mace_init
555 Resets the MACE chip.
556---------------------------------------------------------------------------- */
906da809 557static int mace_init(mace_private *lp, unsigned int ioaddr, char *enet_addr)
1da177e4
LT		 558{
559 int i;
560 int ct = 0;
561
562 /* MACE Software reset */
563 mace_write(lp, ioaddr, MACE_BIUCC, 1);
564 while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {
565 /* Wait for reset bit to be cleared automatically after <= 200ns */;
566 if(++ct > 500)
567 {
568 printk(KERN_ERR "mace: reset failed, card removed ?\n");
569 return -1;
570 }
571 udelay(1);
572 }
573 mace_write(lp, ioaddr, MACE_BIUCC, 0);
574
575 /* The Am2150 requires that the MACE FIFOs operate in burst mode. */
576 mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
577
578 mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
579 mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
580
581 /*
582 * Bit 2-1 PORTSEL[1-0] Port Select.
583 * 00 AUI/10Base-2
584 * 01 10Base-T
585 * 10 DAI Port (reserved in Am2150)
586 * 11 GPSI
587 * For this card, only the first two are valid.
588 * So, PLSCC should be set to
589 * 0x00 for 10Base-2
590 * 0x02 for 10Base-T
591 * Or just set ASEL in PHYCC below!
592 */
593 switch (if_port) {
594 case 1:
595 mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
596 break;
597 case 2:
598 mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
599 break;
600 default:
601 mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);
602 /* ASEL Auto Select. When set, the PORTSEL[1-0] bits are overridden,
603 and the MACE device will automatically select the operating media
604 interface port. */
605 break;
606 }
607
608 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
609 /* Poll ADDRCHG bit */
610 ct = 0;
611 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
612 {
613 if(++ ct > 500)
614 {
615 printk(KERN_ERR "mace: ADDRCHG timeout, card removed ?\n");
616 return -1;
617 }
618 }
619 /* Set PADR register */
620 for (i = 0; i < ETHER_ADDR_LEN; i++)
621 mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
622
623 /* MAC Configuration Control Register should be written last */
624 /* Let set_multicast_list set this. */
625 /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
626 mace_write(lp, ioaddr, MACE_MACCC, 0x00);
627 return 0;
628} /* mace_init */
629
630/* ----------------------------------------------------------------------------
631nmclan_config
632 This routine is scheduled to run after a CARD_INSERTION event
633 is received, to configure the PCMCIA socket, and to make the
634 ethernet device available to the system.
635---------------------------------------------------------------------------- */
636
15b99ac1 637static int nmclan_config(struct pcmcia_device *link)
1da177e4 638{
1da177e4
LT		 639 struct net_device *dev = link->priv;
640 mace_private *lp = netdev_priv(dev);
dddfbd82
DB		 641 u8 *buf;
642 size_t len;
dd0fab5b 643 int i, ret;
906da809 644 unsigned int ioaddr;
1da177e4 645
dd0fab5b
DB		 646 dev_dbg(&link->dev, "nmclan_config\n");
647
648 ret = pcmcia_request_io(link, &link->io);
649 if (ret)
650 goto failed;
eb14120f 651 ret = pcmcia_request_exclusive_irq(link, mace_interrupt);
dd0fab5b
DB		 652 if (ret)
653 goto failed;
654 ret = pcmcia_request_configuration(link, &link->conf);
655 if (ret)
656 goto failed;
1da177e4 657
eb14120f 658 dev->irq = link->irq;
1da177e4
LT		 659 dev->base_addr = link->io.BasePort1;
660
661 ioaddr = dev->base_addr;
662
663 /* Read the ethernet address from the CIS. */
dddfbd82
DB		 664 len = pcmcia_get_tuple(link, 0x80, &buf);
665 if (!buf || len < ETHER_ADDR_LEN) {
666 kfree(buf);
667 goto failed;
668 }
669 memcpy(dev->dev_addr, buf, ETHER_ADDR_LEN);
670 kfree(buf);
1da177e4
LT		 671
672 /* Verify configuration by reading the MACE ID. */
673 {
674 char sig[2];
675
676 sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL);
677 sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH);
678 if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
dd0fab5b 679 dev_dbg(&link->dev, "nmclan_cs configured: mace id=%x %x\n",
1da177e4
LT		 680 sig[0], sig[1]);
681 } else {
682 printk(KERN_NOTICE "nmclan_cs: mace id not found: %x %x should"
683 " be 0x40 0x?9\n", sig[0], sig[1]);
15b99ac1 684 return -ENODEV;
1da177e4
LT		 685 }
686 }
687
688 if(mace_init(lp, ioaddr, dev->dev_addr) == -1)
689 goto failed;
690
691 /* The if_port symbol can be set when the module is loaded */
692 if (if_port <= 2)
693 dev->if_port = if_port;
694 else
695 printk(KERN_NOTICE "nmclan_cs: invalid if_port requested\n");
696
dd2e5a15 697 SET_NETDEV_DEV(dev, &link->dev);
1da177e4
LT		 698
699 i = register_netdev(dev);
700 if (i != 0) {
701 printk(KERN_NOTICE "nmclan_cs: register_netdev() failed\n");
1da177e4
LT		 702 goto failed;
703 }
704
0795af57 705 printk(KERN_INFO "%s: nmclan: port %#3lx, irq %d, %s port,"
e174961c 706 " hw_addr %pM\n",
0795af57 707 dev->name, dev->base_addr, dev->irq, if_names[dev->if_port],
e174961c 708 dev->dev_addr);
15b99ac1 709 return 0;
1da177e4 710
1da177e4 711failed:
15b99ac1
DB		 712 nmclan_release(link);
713 return -ENODEV;
1da177e4
LT		 714} /* nmclan_config */
715
716/* ----------------------------------------------------------------------------
717nmclan_release
718 After a card is removed, nmclan_release() will unregister the
719 net device, and release the PCMCIA configuration. If the device
720 is still open, this will be postponed until it is closed.
721---------------------------------------------------------------------------- */
fba395ee 722static void nmclan_release(struct pcmcia_device *link)
1da177e4 723{
dd0fab5b 724 dev_dbg(&link->dev, "nmclan_release\n");
fba395ee 725 pcmcia_disable_device(link);
1da177e4
LT		 726}
727
fba395ee 728static int nmclan_suspend(struct pcmcia_device *link)
98e4c28b 729{
98e4c28b
DB		 730 struct net_device *dev = link->priv;
731
e2d40963 732 if (link->open)
8661bb5b 733 netif_device_detach(dev);
98e4c28b
DB		 734
735 return 0;
736}
737
fba395ee 738static int nmclan_resume(struct pcmcia_device *link)
98e4c28b 739{
98e4c28b
DB		 740 struct net_device *dev = link->priv;
741
e2d40963 742 if (link->open) {
8661bb5b
DB		 743 nmclan_reset(dev);
744 netif_device_attach(dev);
98e4c28b
DB		 745 }
746
747 return 0;
748}
749
1da177e4
LT		 750
751/* ----------------------------------------------------------------------------
752nmclan_reset
753 Reset and restore all of the Xilinx and MACE registers.
754---------------------------------------------------------------------------- */
755static void nmclan_reset(struct net_device *dev)
756{
757 mace_private *lp = netdev_priv(dev);
758
759#if RESET_XILINX
fba395ee 760 struct pcmcia_device *link = &lp->link;
1da177e4
LT		 761 conf_reg_t reg;
762 u_long OrigCorValue;
763
764 /* Save original COR value */
765 reg.Function = 0;
766 reg.Action = CS_READ;
767 reg.Offset = CISREG_COR;
768 reg.Value = 0;
fba395ee 769 pcmcia_access_configuration_register(link, &reg);
1da177e4
LT		 770 OrigCorValue = reg.Value;
771
772 /* Reset Xilinx */
773 reg.Action = CS_WRITE;
774 reg.Offset = CISREG_COR;
dd0fab5b 775 dev_dbg(&link->dev, "nmclan_reset: OrigCorValue=0x%lX, resetting...\n",
1da177e4
LT		 776 OrigCorValue);
777 reg.Value = COR_SOFT_RESET;
fba395ee 778 pcmcia_access_configuration_register(link, &reg);
1da177e4
LT		 779 /* Need to wait for 20 ms for PCMCIA to finish reset. */
780
781 /* Restore original COR configuration index */
782 reg.Value = COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK);
fba395ee 783 pcmcia_access_configuration_register(link, &reg);
1da177e4
LT		 784 /* Xilinx is now completely reset along with the MACE chip. */
785 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
786
787#endif /* #if RESET_XILINX */
788
789 /* Xilinx is now completely reset along with the MACE chip. */
790 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
791
792 /* Reinitialize the MACE chip for operation. */
793 mace_init(lp, dev->base_addr, dev->dev_addr);
794 mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
795
796 /* Restore the multicast list and enable TX and RX. */
797 restore_multicast_list(dev);
798} /* nmclan_reset */
799
800/* ----------------------------------------------------------------------------
801mace_config
802 [Someone tell me what this is supposed to do? Is if_port a defined
803 standard? If so, there should be defines to indicate 1=10Base-T,
804 2=10Base-2, etc. including limited automatic detection.]
805---------------------------------------------------------------------------- */
806static int mace_config(struct net_device *dev, struct ifmap *map)
807{
808 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
809 if (map->port <= 2) {
810 dev->if_port = map->port;
811 printk(KERN_INFO "%s: switched to %s port\n", dev->name,
812 if_names[dev->if_port]);
813 } else
814 return -EINVAL;
815 }
816 return 0;
817} /* mace_config */
818
819/* ----------------------------------------------------------------------------
820mace_open
821 Open device driver.
822---------------------------------------------------------------------------- */
823static int mace_open(struct net_device *dev)
824{
906da809 825 unsigned int ioaddr = dev->base_addr;
1da177e4 826 mace_private *lp = netdev_priv(dev);
fba395ee 827 struct pcmcia_device *link = lp->p_dev;
1da177e4 828
9940ec36 829 if (!pcmcia_dev_present(link))
1da177e4
LT		 830 return -ENODEV;
831
832 link->open++;
833
834 MACEBANK(0);
835
836 netif_start_queue(dev);
837 nmclan_reset(dev);
838
839 return 0; /* Always succeed */
840} /* mace_open */
841
842/* ----------------------------------------------------------------------------
843mace_close
844 Closes device driver.
845---------------------------------------------------------------------------- */
846static int mace_close(struct net_device *dev)
847{
906da809 848 unsigned int ioaddr = dev->base_addr;
1da177e4 849 mace_private *lp = netdev_priv(dev);
fba395ee 850 struct pcmcia_device *link = lp->p_dev;
1da177e4 851
dd0fab5b 852 dev_dbg(&link->dev, "%s: shutting down ethercard.\n", dev->name);
1da177e4
LT		 853
854 /* Mask off all interrupts from the MACE chip. */
855 outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
856
857 link->open--;
858 netif_stop_queue(dev);
859
860 return 0;
861} /* mace_close */
862
863static void netdev_get_drvinfo(struct net_device *dev,
864 struct ethtool_drvinfo *info)
865{
866 strcpy(info->driver, DRV_NAME);
867 strcpy(info->version, DRV_VERSION);
868 sprintf(info->bus_info, "PCMCIA 0x%lx", dev->base_addr);
869}
870
7282d491 871static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4 872 .get_drvinfo = netdev_get_drvinfo,
1da177e4
LT		 873};
874
875/* ----------------------------------------------------------------------------
876mace_start_xmit
877 This routine begins the packet transmit function. When completed,
878 it will generate a transmit interrupt.
879
880 According to /usr/src/linux/net/inet/dev.c, if _start_xmit
881 returns 0, the "packet is now solely the responsibility of the
882 driver." If _start_xmit returns non-zero, the "transmission
883 failed, put skb back into a list."
884---------------------------------------------------------------------------- */
885
886static void mace_tx_timeout(struct net_device *dev)
887{
888 mace_private *lp = netdev_priv(dev);
fba395ee 889 struct pcmcia_device *link = lp->p_dev;
1da177e4
LT		 890
891 printk(KERN_NOTICE "%s: transmit timed out -- ", dev->name);
892#if RESET_ON_TIMEOUT
893 printk("resetting card\n");
994917f8 894 pcmcia_reset_card(link->socket);
1da177e4
LT		 895#else /* #if RESET_ON_TIMEOUT */
896 printk("NOT resetting card\n");
897#endif /* #if RESET_ON_TIMEOUT */
1ae5dc34 898 dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT		 899 netif_wake_queue(dev);
900}
901
dbf02fae
SH		 902static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
903 struct net_device *dev)
1da177e4
LT		 904{
905 mace_private *lp = netdev_priv(dev);
906da809 906 unsigned int ioaddr = dev->base_addr;
1da177e4
LT		 907
908 netif_stop_queue(dev);
909
dd0fab5b 910 pr_debug("%s: mace_start_xmit(length = %ld) called.\n",
1da177e4
LT		 911 dev->name, (long)skb->len);
912
913#if (!TX_INTERRUPTABLE)
914 /* Disable MACE TX interrupts. */
915 outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
916 ioaddr + AM2150_MACE_BASE + MACE_IMR);
917 lp->tx_irq_disabled=1;
918#endif /* #if (!TX_INTERRUPTABLE) */
919
920 {
921 /* This block must not be interrupted by another transmit request!
922 mace_tx_timeout will take care of timer-based retransmissions from
923 the upper layers. The interrupt handler is guaranteed never to
924 service a transmit interrupt while we are in here.
925 */
926
927 lp->linux_stats.tx_bytes += skb->len;
928 lp->tx_free_frames--;
929
930 /* WARNING: Write the _exact_ number of bytes written in the header! */
931 /* Put out the word header [must be an outw()] . . . */
932 outw(skb->len, ioaddr + AM2150_XMT);
933 /* . . . and the packet [may be any combination of outw() and outb()] */
934 outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
935 if (skb->len & 1) {
936 /* Odd byte transfer */
937 outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
938 }
939
1da177e4
LT		 940#if MULTI_TX
941 if (lp->tx_free_frames > 0)
942 netif_start_queue(dev);
943#endif /* #if MULTI_TX */
944 }
945
946#if (!TX_INTERRUPTABLE)
947 /* Re-enable MACE TX interrupts. */
948 lp->tx_irq_disabled=0;
949 outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
950#endif /* #if (!TX_INTERRUPTABLE) */
951
952 dev_kfree_skb(skb);
953
6ed10654 954 return NETDEV_TX_OK;
1da177e4
LT		 955} /* mace_start_xmit */
956
957/* ----------------------------------------------------------------------------
958mace_interrupt
959 The interrupt handler.
960---------------------------------------------------------------------------- */
7d12e780 961static irqreturn_t mace_interrupt(int irq, void *dev_id)
1da177e4
LT		 962{
963 struct net_device *dev = (struct net_device *) dev_id;
964 mace_private *lp = netdev_priv(dev);
906da809 965 unsigned int ioaddr;
1da177e4
LT		 966 int status;
967 int IntrCnt = MACE_MAX_IR_ITERATIONS;
968
969 if (dev == NULL) {
dd0fab5b 970 pr_debug("mace_interrupt(): irq 0x%X for unknown device.\n",
1da177e4
LT		 971 irq);
972 return IRQ_NONE;
973 }
974
c196d80f
MG		 975 ioaddr = dev->base_addr;
976
1da177e4
LT		 977 if (lp->tx_irq_disabled) {
978 printk(
979 (lp->tx_irq_disabled?
980 KERN_NOTICE "%s: Interrupt with tx_irq_disabled "
981 "[isr=%02X, imr=%02X]\n":
982 KERN_NOTICE "%s: Re-entering the interrupt handler "
983 "[isr=%02X, imr=%02X]\n"),
984 dev->name,
985 inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
986 inb(ioaddr + AM2150_MACE_BASE + MACE_IMR)
987 );
988 /* WARNING: MACE_IR has been read! */
989 return IRQ_NONE;
990 }
991
992 if (!netif_device_present(dev)) {
dd0fab5b 993 pr_debug("%s: interrupt from dead card\n", dev->name);
1da177e4
LT		 994 return IRQ_NONE;
995 }
996
997 do {
998 /* WARNING: MACE_IR is a READ/CLEAR port! */
999 status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
1000
dd0fab5b 1001 pr_debug("mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
1da177e4
LT		 1002
1003 if (status & MACE_IR_RCVINT) {
1004 mace_rx(dev, MACE_MAX_RX_ITERATIONS);
1005 }
1006
1007 if (status & MACE_IR_XMTINT) {
1008 unsigned char fifofc;
1009 unsigned char xmtrc;
1010 unsigned char xmtfs;
1011
1012 fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
1013 if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
1014 lp->linux_stats.tx_errors++;
1015 outb(0xFF, ioaddr + AM2150_XMT_SKIP);
1016 }
1017
1018 /* Transmit Retry Count (XMTRC, reg 4) */
1019 xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
1020 if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
1021 lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
1022
1023 if (
1024 (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
1025 MACE_XMTFS_XMTSV /* Transmit Status Valid */
1026 ) {
1027 lp->mace_stats.xmtsv++;
1028
1029 if (xmtfs & ~MACE_XMTFS_XMTSV) {
1030 if (xmtfs & MACE_XMTFS_UFLO) {
1031 /* Underflow. Indicates that the Transmit FIFO emptied before
1032 the end of frame was reached. */
1033 lp->mace_stats.uflo++;
1034 }
1035 if (xmtfs & MACE_XMTFS_LCOL) {
1036 /* Late Collision */
1037 lp->mace_stats.lcol++;
1038 }
1039 if (xmtfs & MACE_XMTFS_MORE) {
1040 /* MORE than one retry was needed */
1041 lp->mace_stats.more++;
1042 }
1043 if (xmtfs & MACE_XMTFS_ONE) {
1044 /* Exactly ONE retry occurred */
1045 lp->mace_stats.one++;
1046 }
1047 if (xmtfs & MACE_XMTFS_DEFER) {
1048 /* Transmission was defered */
1049 lp->mace_stats.defer++;
1050 }
1051 if (xmtfs & MACE_XMTFS_LCAR) {
1052 /* Loss of carrier */
1053 lp->mace_stats.lcar++;
1054 }
1055 if (xmtfs & MACE_XMTFS_RTRY) {
1056 /* Retry error: transmit aborted after 16 attempts */
1057 lp->mace_stats.rtry++;
1058 }
1059 } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */
1060
1061 } /* if (xmtfs & MACE_XMTFS_XMTSV) */
1062
1063 lp->linux_stats.tx_packets++;
1064 lp->tx_free_frames++;
1065 netif_wake_queue(dev);
1066 } /* if (status & MACE_IR_XMTINT) */
1067
1068 if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1069 if (status & MACE_IR_JAB) {
1070 /* Jabber Error. Excessive transmit duration (20-150ms). */
1071 lp->mace_stats.jab++;
1072 }
1073 if (status & MACE_IR_BABL) {
1074 /* Babble Error. >1518 bytes transmitted. */
1075 lp->mace_stats.babl++;
1076 }
1077 if (status & MACE_IR_CERR) {
1078 /* Collision Error. CERR indicates the absence of the
1079 Signal Quality Error Test message after a packet
1080 transmission. */
1081 lp->mace_stats.cerr++;
1082 }
1083 if (status & MACE_IR_RCVCCO) {
1084 /* Receive Collision Count Overflow; */
1085 lp->mace_stats.rcvcco++;
1086 }
1087 if (status & MACE_IR_RNTPCO) {
1088 /* Runt Packet Count Overflow */
1089 lp->mace_stats.rntpco++;
1090 }
1091 if (status & MACE_IR_MPCO) {
1092 /* Missed Packet Count Overflow */
1093 lp->mace_stats.mpco++;
1094 }
1095 } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */
1096
1097 } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1098
1099 return IRQ_HANDLED;
1100} /* mace_interrupt */
1101
1102/* ----------------------------------------------------------------------------
1103mace_rx
1104 Receives packets.
1105---------------------------------------------------------------------------- */
1106static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1107{
1108 mace_private *lp = netdev_priv(dev);
906da809 1109 unsigned int ioaddr = dev->base_addr;
1da177e4
LT		 1110 unsigned char rx_framecnt;
1111 unsigned short rx_status;
1112
1113 while (
1114 ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1115 (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
1116 (RxCnt--)
1117 ) {
1118 rx_status = inw(ioaddr + AM2150_RCV);
1119
dd0fab5b 1120 pr_debug("%s: in mace_rx(), framecnt 0x%X, rx_status"
1da177e4
LT		 1121 " 0x%X.\n", dev->name, rx_framecnt, rx_status);
1122
1123 if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
1124 lp->linux_stats.rx_errors++;
1125 if (rx_status & MACE_RCVFS_OFLO) {
1126 lp->mace_stats.oflo++;
1127 }
1128 if (rx_status & MACE_RCVFS_CLSN) {
1129 lp->mace_stats.clsn++;
1130 }
1131 if (rx_status & MACE_RCVFS_FRAM) {
1132 lp->mace_stats.fram++;
1133 }
1134 if (rx_status & MACE_RCVFS_FCS) {
1135 lp->mace_stats.fcs++;
1136 }
1137 } else {
1138 short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1139 /* Auto Strip is off, always subtract 4 */
1140 struct sk_buff *skb;
1141
1142 lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1143 /* runt packet count */
1144 lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1145 /* rcv collision count */
1146
dd0fab5b 1147 pr_debug(" receiving packet size 0x%X rx_status"
1da177e4
LT		 1148 " 0x%X.\n", pkt_len, rx_status);
1149
1150 skb = dev_alloc_skb(pkt_len+2);
1151
1152 if (skb != NULL) {
1da177e4
LT		 1153 skb_reserve(skb, 2);
1154 insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1155 if (pkt_len & 1)
27a884dc 1156 *(skb_tail_pointer(skb) - 1) = inb(ioaddr + AM2150_RCV);
1da177e4
LT		 1157 skb->protocol = eth_type_trans(skb, dev);
1158
1159 netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
1160
1da177e4 1161 lp->linux_stats.rx_packets++;
6f258910 1162 lp->linux_stats.rx_bytes += pkt_len;
1da177e4
LT		 1163 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1164 continue;
1165 } else {
dd0fab5b 1166 pr_debug("%s: couldn't allocate a sk_buff of size"
1da177e4
LT		 1167 " %d.\n", dev->name, pkt_len);
1168 lp->linux_stats.rx_dropped++;
1169 }
1170 }
1171 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1172 } /* while */
1173
1174 return 0;
1175} /* mace_rx */
1176
1177/* ----------------------------------------------------------------------------
1178pr_linux_stats
1179---------------------------------------------------------------------------- */
1180static void pr_linux_stats(struct net_device_stats *pstats)
1181{
dd0fab5b
DB		 1182 pr_debug("pr_linux_stats\n");
1183 pr_debug(" rx_packets=%-7ld tx_packets=%ld\n",
1da177e4 1184 (long)pstats->rx_packets, (long)pstats->tx_packets);
dd0fab5b 1185 pr_debug(" rx_errors=%-7ld tx_errors=%ld\n",
1da177e4 1186 (long)pstats->rx_errors, (long)pstats->tx_errors);
dd0fab5b 1187 pr_debug(" rx_dropped=%-7ld tx_dropped=%ld\n",
1da177e4 1188 (long)pstats->rx_dropped, (long)pstats->tx_dropped);
dd0fab5b 1189 pr_debug(" multicast=%-7ld collisions=%ld\n",
1da177e4
LT		 1190 (long)pstats->multicast, (long)pstats->collisions);
1191
dd0fab5b 1192 pr_debug(" rx_length_errors=%-7ld rx_over_errors=%ld\n",
1da177e4 1193 (long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
dd0fab5b 1194 pr_debug(" rx_crc_errors=%-7ld rx_frame_errors=%ld\n",
1da177e4 1195 (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
dd0fab5b 1196 pr_debug(" rx_fifo_errors=%-7ld rx_missed_errors=%ld\n",
1da177e4
LT		 1197 (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1198
dd0fab5b 1199 pr_debug(" tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1da177e4 1200 (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
dd0fab5b 1201 pr_debug(" tx_fifo_errors=%-7ld tx_heartbeat_errors=%ld\n",
1da177e4 1202 (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
dd0fab5b 1203 pr_debug(" tx_window_errors=%ld\n",
1da177e4
LT		 1204 (long)pstats->tx_window_errors);
1205} /* pr_linux_stats */
1206
1207/* ----------------------------------------------------------------------------
1208pr_mace_stats
1209---------------------------------------------------------------------------- */
1210static void pr_mace_stats(mace_statistics *pstats)
1211{
dd0fab5b 1212 pr_debug("pr_mace_stats\n");
1da177e4 1213
dd0fab5b 1214 pr_debug(" xmtsv=%-7d uflo=%d\n",
1da177e4 1215 pstats->xmtsv, pstats->uflo);
dd0fab5b 1216 pr_debug(" lcol=%-7d more=%d\n",
1da177e4 1217 pstats->lcol, pstats->more);
dd0fab5b 1218 pr_debug(" one=%-7d defer=%d\n",
1da177e4 1219 pstats->one, pstats->defer);
dd0fab5b 1220 pr_debug(" lcar=%-7d rtry=%d\n",
1da177e4
LT		 1221 pstats->lcar, pstats->rtry);
1222
1223 /* MACE_XMTRC */
dd0fab5b 1224 pr_debug(" exdef=%-7d xmtrc=%d\n",
1da177e4
LT		 1225 pstats->exdef, pstats->xmtrc);
1226
1227 /* RFS1--Receive Status (RCVSTS) */
dd0fab5b 1228 pr_debug(" oflo=%-7d clsn=%d\n",
1da177e4 1229 pstats->oflo, pstats->clsn);
dd0fab5b 1230 pr_debug(" fram=%-7d fcs=%d\n",
1da177e4
LT		 1231 pstats->fram, pstats->fcs);
1232
1233 /* RFS2--Runt Packet Count (RNTPC) */
1234 /* RFS3--Receive Collision Count (RCVCC) */
dd0fab5b 1235 pr_debug(" rfs_rntpc=%-7d rfs_rcvcc=%d\n",
1da177e4
LT		 1236 pstats->rfs_rntpc, pstats->rfs_rcvcc);
1237
1238 /* MACE_IR */
dd0fab5b 1239 pr_debug(" jab=%-7d babl=%d\n",
1da177e4 1240 pstats->jab, pstats->babl);
dd0fab5b 1241 pr_debug(" cerr=%-7d rcvcco=%d\n",
1da177e4 1242 pstats->cerr, pstats->rcvcco);
dd0fab5b 1243 pr_debug(" rntpco=%-7d mpco=%d\n",
1da177e4
LT		 1244 pstats->rntpco, pstats->mpco);
1245
1246 /* MACE_MPC */
dd0fab5b 1247 pr_debug(" mpc=%d\n", pstats->mpc);
1da177e4
LT		 1248
1249 /* MACE_RNTPC */
dd0fab5b 1250 pr_debug(" rntpc=%d\n", pstats->rntpc);
1da177e4
LT		 1251
1252 /* MACE_RCVCC */
dd0fab5b 1253 pr_debug(" rcvcc=%d\n", pstats->rcvcc);
1da177e4
LT		 1254
1255} /* pr_mace_stats */
1256
1257/* ----------------------------------------------------------------------------
1258update_stats
1259 Update statistics. We change to register window 1, so this
1260 should be run single-threaded if the device is active. This is
1261 expected to be a rare operation, and it's simpler for the rest
1262 of the driver to assume that window 0 is always valid rather
1263 than use a special window-state variable.
1264
1265 oflo & uflo should _never_ occur since it would mean the Xilinx
1266 was not able to transfer data between the MACE FIFO and the
1267 card's SRAM fast enough. If this happens, something is
1268 seriously wrong with the hardware.
1269---------------------------------------------------------------------------- */
906da809 1270static void update_stats(unsigned int ioaddr, struct net_device *dev)
1da177e4
LT		 1271{
1272 mace_private *lp = netdev_priv(dev);
1273
1274 lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC);
1275 lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC);
1276 lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC);
1277 /* At this point, mace_stats is fully updated for this call.
1278 We may now update the linux_stats. */
1279
1280 /* The MACE has no equivalent for linux_stats field which are commented
1281 out. */
1282
1283 /* lp->linux_stats.multicast; */
1284 lp->linux_stats.collisions =
1285 lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1286 /* Collision: The MACE may retry sending a packet 15 times
1287 before giving up. The retry count is in XMTRC.
1288 Does each retry constitute a collision?
1289 If so, why doesn't the RCVCC record these collisions? */
1290
1291 /* detailed rx_errors: */
1292 lp->linux_stats.rx_length_errors =
1293 lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1294 /* lp->linux_stats.rx_over_errors */
1295 lp->linux_stats.rx_crc_errors = lp->mace_stats.fcs;
1296 lp->linux_stats.rx_frame_errors = lp->mace_stats.fram;
1297 lp->linux_stats.rx_fifo_errors = lp->mace_stats.oflo;
1298 lp->linux_stats.rx_missed_errors =
1299 lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1300
1301 /* detailed tx_errors */
1302 lp->linux_stats.tx_aborted_errors = lp->mace_stats.rtry;
1303 lp->linux_stats.tx_carrier_errors = lp->mace_stats.lcar;
1304 /* LCAR usually results from bad cabling. */
1305 lp->linux_stats.tx_fifo_errors = lp->mace_stats.uflo;
1306 lp->linux_stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1307 /* lp->linux_stats.tx_window_errors; */
1da177e4
LT		 1308} /* update_stats */
1309
1310/* ----------------------------------------------------------------------------
1311mace_get_stats
1312 Gathers ethernet statistics from the MACE chip.
1313---------------------------------------------------------------------------- */
1314static struct net_device_stats *mace_get_stats(struct net_device *dev)
1315{
1316 mace_private *lp = netdev_priv(dev);
1317
1318 update_stats(dev->base_addr, dev);
1319
dd0fab5b 1320 pr_debug("%s: updating the statistics.\n", dev->name);
1da177e4
LT		 1321 pr_linux_stats(&lp->linux_stats);
1322 pr_mace_stats(&lp->mace_stats);
1323
1324 return &lp->linux_stats;
1325} /* net_device_stats */
1326
1327/* ----------------------------------------------------------------------------
1328updateCRC
1329 Modified from Am79C90 data sheet.
1330---------------------------------------------------------------------------- */
1331
1332#ifdef BROKEN_MULTICAST
1333
1334static void updateCRC(int *CRC, int bit)
1335{
1336 int poly[]={
1337 1,1,1,0, 1,1,0,1,
1338 1,0,1,1, 1,0,0,0,
1339 1,0,0,0, 0,0,1,1,
1340 0,0,1,0, 0,0,0,0
1341 }; /* CRC polynomial. poly[n] = coefficient of the x**n term of the
1342 CRC generator polynomial. */
1343
1344 int j;
1345
1346 /* shift CRC and control bit (CRC[32]) */
1347 for (j = 32; j > 0; j--)
1348 CRC[j] = CRC[j-1];
1349 CRC[0] = 0;
1350
1351 /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */
1352 if (bit ^ CRC[32])
1353 for (j = 0; j < 32; j++)
1354 CRC[j] ^= poly[j];
1355} /* updateCRC */
1356
1357/* ----------------------------------------------------------------------------
1358BuildLAF
1359 Build logical address filter.
1360 Modified from Am79C90 data sheet.
1361
1362Input
1363 ladrf: logical address filter (contents initialized to 0)
1364 adr: ethernet address
1365---------------------------------------------------------------------------- */
1366static void BuildLAF(int *ladrf, int *adr)
1367{
1368 int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */
1369
1370 int i, byte; /* temporary array indices */
1371 int hashcode; /* the output object */
1372
1373 CRC[32]=0;
1374
1375 for (byte = 0; byte < 6; byte++)
1376 for (i = 0; i < 8; i++)
1377 updateCRC(CRC, (adr[byte] >> i) & 1);
1378
1379 hashcode = 0;
1380 for (i = 0; i < 6; i++)
1381 hashcode = (hashcode << 1) + CRC[i];
1382
1383 byte = hashcode >> 3;
1384 ladrf[byte] |= (1 << (hashcode & 7));
1385
1386#ifdef PCMCIA_DEBUG
dd0fab5b 1387 if (0)
ad361c98
JP		 1388 printk(KERN_DEBUG " adr =%pM\n", adr);
1389 printk(KERN_DEBUG " hashcode = %d(decimal), ladrf[0:63] =", hashcode);
1390 for (i = 0; i < 8; i++)
1391 printk(KERN_CONT " %02X", ladrf[i]);
1392 printk(KERN_CONT "\n");
1da177e4
LT		 1393#endif
1394} /* BuildLAF */
1395
1396/* ----------------------------------------------------------------------------
1397restore_multicast_list
1398 Restores the multicast filter for MACE chip to the last
1399 set_multicast_list() call.
1400
1401Input
1402 multicast_num_addrs
1403 multicast_ladrf[]
1404---------------------------------------------------------------------------- */
1405static void restore_multicast_list(struct net_device *dev)
1406{
1407 mace_private *lp = netdev_priv(dev);
1408 int num_addrs = lp->multicast_num_addrs;
1409 int *ladrf = lp->multicast_ladrf;
906da809 1410 unsigned int ioaddr = dev->base_addr;
1da177e4
LT		 1411 int i;
1412
dd0fab5b 1413 pr_debug("%s: restoring Rx mode to %d addresses.\n",
1da177e4
LT		 1414 dev->name, num_addrs);
1415
1416 if (num_addrs > 0) {
1417
dd0fab5b 1418 pr_debug("Attempt to restore multicast list detected.\n");
1da177e4
LT		 1419
1420 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1421 /* Poll ADDRCHG bit */
1422 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1423 ;
1424 /* Set LADRF register */
1425 for (i = 0; i < MACE_LADRF_LEN; i++)
1426 mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]);
1427
1428 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1429 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1430
1431 } else if (num_addrs < 0) {
1432
1433 /* Promiscuous mode: receive all packets */
1434 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1435 mace_write(lp, ioaddr, MACE_MACCC,
1436 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1437 );
1438
1439 } else {
1440
1441 /* Normal mode */
1442 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1443 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1444
1445 }
1446} /* restore_multicast_list */
1447
1448/* ----------------------------------------------------------------------------
1449set_multicast_list
1450 Set or clear the multicast filter for this adaptor.
1451
1452Input
1453 num_addrs == -1 Promiscuous mode, receive all packets
1454 num_addrs == 0 Normal mode, clear multicast list
1455 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
1456 best-effort filtering.
1457Output
1458 multicast_num_addrs
1459 multicast_ladrf[]
1460---------------------------------------------------------------------------- */
1461
1462static void set_multicast_list(struct net_device *dev)
1463{
1464 mace_private *lp = netdev_priv(dev);
1465 int adr[ETHER_ADDR_LEN] = {0}; /* Ethernet address */
22bedad3 1466 struct netdev_hw_addr *ha;
1da177e4
LT		 1467
1468#ifdef PCMCIA_DEBUG
dd0fab5b 1469 {
1da177e4 1470 static int old;
4cd24eaf
JP		 1471 if (netdev_mc_count(dev) != old) {
1472 old = netdev_mc_count(dev);
dd0fab5b 1473 pr_debug("%s: setting Rx mode to %d addresses.\n",
1da177e4
LT		 1474 dev->name, old);
1475 }
1476 }
1477#endif
1478
1479 /* Set multicast_num_addrs. */
4cd24eaf 1480 lp->multicast_num_addrs = netdev_mc_count(dev);
1da177e4
LT		 1481
1482 /* Set multicast_ladrf. */
1483 if (num_addrs > 0) {
1484 /* Calculate multicast logical address filter */
1485 memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
22bedad3
JP		 1486 netdev_for_each_mc_addr(ha, dev) {
1487 memcpy(adr, ha->addr, ETHER_ADDR_LEN);
1da177e4
LT		 1488 BuildLAF(lp->multicast_ladrf, adr);
1489 }
1490 }
1491
1492 restore_multicast_list(dev);
1493
1494} /* set_multicast_list */
1495
1496#endif /* BROKEN_MULTICAST */
1497
1498static void restore_multicast_list(struct net_device *dev)
1499{
906da809 1500 unsigned int ioaddr = dev->base_addr;
1da177e4
LT		 1501 mace_private *lp = netdev_priv(dev);
1502
dd0fab5b 1503 pr_debug("%s: restoring Rx mode to %d addresses.\n", dev->name,
1da177e4
LT		 1504 lp->multicast_num_addrs);
1505
1506 if (dev->flags & IFF_PROMISC) {
1507 /* Promiscuous mode: receive all packets */
1508 mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1509 mace_write(lp, ioaddr, MACE_MACCC,
1510 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1511 );
1512 } else {
1513 /* Normal mode */
1514 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1515 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1516 }
1517} /* restore_multicast_list */
1518
1519static void set_multicast_list(struct net_device *dev)
1520{
1521 mace_private *lp = netdev_priv(dev);
1522
1523#ifdef PCMCIA_DEBUG
dd0fab5b 1524 {
1da177e4 1525 static int old;
4cd24eaf
JP		 1526 if (netdev_mc_count(dev) != old) {
1527 old = netdev_mc_count(dev);
dd0fab5b 1528 pr_debug("%s: setting Rx mode to %d addresses.\n",
1da177e4
LT		 1529 dev->name, old);
1530 }
1531 }
1532#endif
1533
4cd24eaf 1534 lp->multicast_num_addrs = netdev_mc_count(dev);
1da177e4
LT		 1535 restore_multicast_list(dev);
1536
1537} /* set_multicast_list */
1538
a58e26cb
DB		 1539static struct pcmcia_device_id nmclan_ids[] = {
1540 PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941),
d277ad0e 1541 PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf),
a58e26cb
DB		 1542 PCMCIA_DEVICE_NULL,
1543};
1544MODULE_DEVICE_TABLE(pcmcia, nmclan_ids);
1545
1da177e4
LT		 1546static struct pcmcia_driver nmclan_cs_driver = {
1547 .owner = THIS_MODULE,
1548 .drv = {
1549 .name = "nmclan_cs",
1550 },
15b99ac1 1551 .probe = nmclan_probe,
cc3b4866 1552 .remove = nmclan_detach,
a58e26cb 1553 .id_table = nmclan_ids,
98e4c28b
DB		 1554 .suspend = nmclan_suspend,
1555 .resume = nmclan_resume,
1da177e4
LT		 1556};
1557
1558static int __init init_nmclan_cs(void)
1559{
1560 return pcmcia_register_driver(&nmclan_cs_driver);
1561}
1562
1563static void __exit exit_nmclan_cs(void)
1564{
1565 pcmcia_unregister_driver(&nmclan_cs_driver);
1da177e4
LT		 1566}
1567
1568module_init(init_nmclan_cs);
1569module_exit(exit_nmclan_cs);