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drivers/net/: all drivers/net/ cleanup with ARRAY_SIZE
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / pci-skeleton.c
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1da177e4
LT		 1/*
2
3 drivers/net/pci-skeleton.c
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6
7 Original code came from 8139too.c, which in turns was based
8 originally on Donald Becker's rtl8139.c driver, versions 1.11
9 and older. This driver was originally based on rtl8139.c
10 version 1.07. Header of rtl8139.c version 1.11:
11
12 -----<snip>-----
13
14 Written 1997-2000 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41
42-----------------------------------------------------------------------------
43
44 Theory of Operation
45
46I. Board Compatibility
47
48This device driver is designed for the RealTek RTL8139 series, the RealTek
49Fast Ethernet controllers for PCI and CardBus. This chip is used on many
50low-end boards, sometimes with its markings changed.
51
52
53II. Board-specific settings
54
55PCI bus devices are configured by the system at boot time, so no jumpers
56need to be set on the board. The system BIOS will assign the
57PCI INTA signal to a (preferably otherwise unused) system IRQ line.
58
59III. Driver operation
60
61IIIa. Rx Ring buffers
62
63The receive unit uses a single linear ring buffer rather than the more
64common (and more efficient) descriptor-based architecture. Incoming frames
65are sequentially stored into the Rx region, and the host copies them into
66skbuffs.
67
68Comment: While it is theoretically possible to process many frames in place,
69any delay in Rx processing would cause us to drop frames. More importantly,
70the Linux protocol stack is not designed to operate in this manner.
71
72IIIb. Tx operation
73
74The RTL8139 uses a fixed set of four Tx descriptors in register space.
75In a stunningly bad design choice, Tx frames must be 32 bit aligned. Linux
76aligns the IP header on word boundaries, and 14 byte ethernet header means
77that almost all frames will need to be copied to an alignment buffer.
78
79IVb. References
80
81http://www.realtek.com.tw/cn/cn.html
82http://www.scyld.com/expert/NWay.html
83
84IVc. Errata
85
86*/
87
1da177e4
LT		 88#include <linux/module.h>
89#include <linux/kernel.h>
90#include <linux/pci.h>
91#include <linux/init.h>
92#include <linux/ioport.h>
93#include <linux/netdevice.h>
94#include <linux/etherdevice.h>
95#include <linux/delay.h>
96#include <linux/ethtool.h>
97#include <linux/mii.h>
98#include <linux/crc32.h>
99#include <asm/io.h>
100
d5b20697 101#define NETDRV_VERSION "1.0.1"
1da177e4
LT		 102#define MODNAME "netdrv"
103#define NETDRV_DRIVER_LOAD_MSG "MyVendor Fast Ethernet driver " NETDRV_VERSION " loaded"
104#define PFX MODNAME ": "
105
106static char version[] __devinitdata =
107KERN_INFO NETDRV_DRIVER_LOAD_MSG "\n"
108KERN_INFO " Support available from http://foo.com/bar/baz.html\n";
109
110/* define to 1 to enable PIO instead of MMIO */
111#undef USE_IO_OPS
112
113/* define to 1 to enable copious debugging info */
114#undef NETDRV_DEBUG
115
116/* define to 1 to disable lightweight runtime debugging checks */
117#undef NETDRV_NDEBUG
118
119
120#ifdef NETDRV_DEBUG
121/* note: prints function name for you */
122# define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
123#else
124# define DPRINTK(fmt, args...)
125#endif
126
127#ifdef NETDRV_NDEBUG
128# define assert(expr) do {} while (0)
129#else
130# define assert(expr) \
131 if(!(expr)) { \
132 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
133 #expr,__FILE__,__FUNCTION__,__LINE__); \
134 }
135#endif
136
137
138/* A few user-configurable values. */
139/* media options */
140static int media[] = {-1, -1, -1, -1, -1, -1, -1, -1};
141
142/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
143static int max_interrupt_work = 20;
144
145/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
146 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
147static int multicast_filter_limit = 32;
148
149/* Size of the in-memory receive ring. */
150#define RX_BUF_LEN_IDX 2 /* 0==8K, 1==16K, 2==32K, 3==64K */
151#define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
152#define RX_BUF_PAD 16
153#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
154#define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
155
156/* Number of Tx descriptor registers. */
157#define NUM_TX_DESC 4
158
159/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
160#define MAX_ETH_FRAME_SIZE 1536
161
162/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
163#define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
164#define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
165
166/* PCI Tuning Parameters
167 Threshold is bytes transferred to chip before transmission starts. */
168#define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
169
170/* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
171#define RX_FIFO_THRESH 6 /* Rx buffer level before first PCI xfer. */
172#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
173#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
174
175
176/* Operational parameters that usually are not changed. */
177/* Time in jiffies before concluding the transmitter is hung. */
178#define TX_TIMEOUT (6*HZ)
179
180
181enum {
182 HAS_CHIP_XCVR = 0x020000,
183 HAS_LNK_CHNG = 0x040000,
184};
185
186#define NETDRV_MIN_IO_SIZE 0x80
187#define RTL8139B_IO_SIZE 256
188
189#define NETDRV_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
190
191typedef enum {
192 RTL8139 = 0,
193 NETDRV_CB,
194 SMC1211TX,
195 /*MPX5030,*/
196 DELTA8139,
197 ADDTRON8139,
198} board_t;
199
200
201/* indexed by board_t, above */
202static struct {
203 const char *name;
204} board_info[] __devinitdata = {
205 { "RealTek RTL8139 Fast Ethernet" },
206 { "RealTek RTL8139B PCI/CardBus" },
207 { "SMC1211TX EZCard 10/100 (RealTek RTL8139)" },
208/* { MPX5030, "Accton MPX5030 (RealTek RTL8139)" },*/
209 { "Delta Electronics 8139 10/100BaseTX" },
210 { "Addtron Technolgy 8139 10/100BaseTX" },
211};
212
213
214static struct pci_device_id netdrv_pci_tbl[] = {
215 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
216 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, NETDRV_CB },
217 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMC1211TX },
218/* {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MPX5030 },*/
219 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DELTA8139 },
220 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ADDTRON8139 },
221 {0,}
222};
223MODULE_DEVICE_TABLE (pci, netdrv_pci_tbl);
224
225
226/* The rest of these values should never change. */
227
228/* Symbolic offsets to registers. */
229enum NETDRV_registers {
230 MAC0 = 0, /* Ethernet hardware address. */
231 MAR0 = 8, /* Multicast filter. */
232 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
233 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
234 RxBuf = 0x30,
235 RxEarlyCnt = 0x34,
236 RxEarlyStatus = 0x36,
237 ChipCmd = 0x37,
238 RxBufPtr = 0x38,
239 RxBufAddr = 0x3A,
240 IntrMask = 0x3C,
241 IntrStatus = 0x3E,
242 TxConfig = 0x40,
243 ChipVersion = 0x43,
244 RxConfig = 0x44,
245 Timer = 0x48, /* A general-purpose counter. */
246 RxMissed = 0x4C, /* 24 bits valid, write clears. */
247 Cfg9346 = 0x50,
248 Config0 = 0x51,
249 Config1 = 0x52,
250 FlashReg = 0x54,
251 MediaStatus = 0x58,
252 Config3 = 0x59,
253 Config4 = 0x5A, /* absent on RTL-8139A */
254 HltClk = 0x5B,
255 MultiIntr = 0x5C,
256 TxSummary = 0x60,
257 BasicModeCtrl = 0x62,
258 BasicModeStatus = 0x64,
259 NWayAdvert = 0x66,
260 NWayLPAR = 0x68,
261 NWayExpansion = 0x6A,
262 /* Undocumented registers, but required for proper operation. */
263 FIFOTMS = 0x70, /* FIFO Control and test. */
264 CSCR = 0x74, /* Chip Status and Configuration Register. */
265 PARA78 = 0x78,
266 PARA7c = 0x7c, /* Magic transceiver parameter register. */
267 Config5 = 0xD8, /* absent on RTL-8139A */
268};
269
270enum ClearBitMasks {
271 MultiIntrClear = 0xF000,
272 ChipCmdClear = 0xE2,
273 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
274};
275
276enum ChipCmdBits {
277 CmdReset = 0x10,
278 CmdRxEnb = 0x08,
279 CmdTxEnb = 0x04,
280 RxBufEmpty = 0x01,
281};
282
283/* Interrupt register bits, using my own meaningful names. */
284enum IntrStatusBits {
285 PCIErr = 0x8000,
286 PCSTimeout = 0x4000,
287 RxFIFOOver = 0x40,
288 RxUnderrun = 0x20,
289 RxOverflow = 0x10,
290 TxErr = 0x08,
291 TxOK = 0x04,
292 RxErr = 0x02,
293 RxOK = 0x01,
294};
295enum TxStatusBits {
296 TxHostOwns = 0x2000,
297 TxUnderrun = 0x4000,
298 TxStatOK = 0x8000,
299 TxOutOfWindow = 0x20000000,
300 TxAborted = 0x40000000,
301 TxCarrierLost = 0x80000000,
302};
303enum RxStatusBits {
304 RxMulticast = 0x8000,
305 RxPhysical = 0x4000,
306 RxBroadcast = 0x2000,
307 RxBadSymbol = 0x0020,
308 RxRunt = 0x0010,
309 RxTooLong = 0x0008,
310 RxCRCErr = 0x0004,
311 RxBadAlign = 0x0002,
312 RxStatusOK = 0x0001,
313};
314
315/* Bits in RxConfig. */
316enum rx_mode_bits {
317 AcceptErr = 0x20,
318 AcceptRunt = 0x10,
319 AcceptBroadcast = 0x08,
320 AcceptMulticast = 0x04,
321 AcceptMyPhys = 0x02,
322 AcceptAllPhys = 0x01,
323};
324
325/* Bits in TxConfig. */
326enum tx_config_bits {
327 TxIFG1 = (1 << 25), /* Interframe Gap Time */
328 TxIFG0 = (1 << 24), /* Enabling these bits violates IEEE 802.3 */
329 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
330 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
331 TxClearAbt = (1 << 0), /* Clear abort (WO) */
332 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
333
334 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
335};
336
337/* Bits in Config1 */
338enum Config1Bits {
339 Cfg1_PM_Enable = 0x01,
340 Cfg1_VPD_Enable = 0x02,
341 Cfg1_PIO = 0x04,
342 Cfg1_MMIO = 0x08,
343 Cfg1_LWAKE = 0x10,
344 Cfg1_Driver_Load = 0x20,
345 Cfg1_LED0 = 0x40,
346 Cfg1_LED1 = 0x80,
347};
348
349enum RxConfigBits {
350 /* Early Rx threshold, none or X/16 */
351 RxCfgEarlyRxNone = 0,
352 RxCfgEarlyRxShift = 24,
353
354 /* rx fifo threshold */
355 RxCfgFIFOShift = 13,
356 RxCfgFIFONone = (7 << RxCfgFIFOShift),
357
358 /* Max DMA burst */
359 RxCfgDMAShift = 8,
360 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
361
362 /* rx ring buffer length */
363 RxCfgRcv8K = 0,
364 RxCfgRcv16K = (1 << 11),
365 RxCfgRcv32K = (1 << 12),
366 RxCfgRcv64K = (1 << 11) | (1 << 12),
367
368 /* Disable packet wrap at end of Rx buffer */
369 RxNoWrap = (1 << 7),
370};
371
372
373/* Twister tuning parameters from RealTek.
374 Completely undocumented, but required to tune bad links. */
375enum CSCRBits {
376 CSCR_LinkOKBit = 0x0400,
377 CSCR_LinkChangeBit = 0x0800,
378 CSCR_LinkStatusBits = 0x0f000,
379 CSCR_LinkDownOffCmd = 0x003c0,
380 CSCR_LinkDownCmd = 0x0f3c0,
381};
382
383
384enum Cfg9346Bits {
385 Cfg9346_Lock = 0x00,
386 Cfg9346_Unlock = 0xC0,
387};
388
389
390#define PARA78_default 0x78fa8388
391#define PARA7c_default 0xcb38de43 /* param[0][3] */
392#define PARA7c_xxx 0xcb38de43
393static const unsigned long param[4][4] = {
394 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
395 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
396 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
397 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
398};
399
400struct ring_info {
401 struct sk_buff *skb;
402 dma_addr_t mapping;
403};
404
405
406typedef enum {
407 CH_8139 = 0,
408 CH_8139_K,
409 CH_8139A,
410 CH_8139B,
411 CH_8130,
412 CH_8139C,
413} chip_t;
414
415
416/* directly indexed by chip_t, above */
3c6bee1d 417static const struct {
1da177e4
LT		 418 const char *name;
419 u8 version; /* from RTL8139C docs */
420 u32 RxConfigMask; /* should clear the bits supported by this chip */
421} rtl_chip_info[] = {
422 { "RTL-8139",
423 0x40,
424 0xf0fe0040, /* XXX copied from RTL8139A, verify */
425 },
426
427 { "RTL-8139 rev K",
428 0x60,
429 0xf0fe0040,
430 },
431
432 { "RTL-8139A",
433 0x70,
434 0xf0fe0040,
435 },
436
437 { "RTL-8139B",
438 0x78,
439 0xf0fc0040
440 },
441
442 { "RTL-8130",
443 0x7C,
444 0xf0fe0040, /* XXX copied from RTL8139A, verify */
445 },
446
447 { "RTL-8139C",
448 0x74,
449 0xf0fc0040, /* XXX copied from RTL8139B, verify */
450 },
451
452};
453
454
455struct netdrv_private {
456 board_t board;
457 void *mmio_addr;
458 int drv_flags;
459 struct pci_dev *pci_dev;
460 struct net_device_stats stats;
461 struct timer_list timer; /* Media selection timer. */
462 unsigned char *rx_ring;
463 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
464 unsigned int tx_flag;
465 atomic_t cur_tx;
466 atomic_t dirty_tx;
467 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
468 struct ring_info tx_info[NUM_TX_DESC];
469 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
470 unsigned char *tx_bufs; /* Tx bounce buffer region. */
471 dma_addr_t rx_ring_dma;
472 dma_addr_t tx_bufs_dma;
473 char phys[4]; /* MII device addresses. */
474 char twistie, twist_row, twist_col; /* Twister tune state. */
475 unsigned int full_duplex:1; /* Full-duplex operation requested. */
476 unsigned int duplex_lock:1;
477 unsigned int default_port:4; /* Last dev->if_port value. */
478 unsigned int media2:4; /* Secondary monitored media port. */
479 unsigned int medialock:1; /* Don't sense media type. */
480 unsigned int mediasense:1; /* Media sensing in progress. */
481 spinlock_t lock;
482 chip_t chipset;
483};
484
485MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
486MODULE_DESCRIPTION ("Skeleton for a PCI Fast Ethernet driver");
487MODULE_LICENSE("GPL");
2f761478
VF		 488module_param(multicast_filter_limit, int, 0);
489module_param(max_interrupt_work, int, 0);
490module_param_array(media, int, NULL, 0);
1da177e4
LT		 491MODULE_PARM_DESC (multicast_filter_limit, "pci-skeleton maximum number of filtered multicast addresses");
492MODULE_PARM_DESC (max_interrupt_work, "pci-skeleton maximum events handled per interrupt");
493MODULE_PARM_DESC (media, "pci-skeleton: Bits 0-3: media type, bit 17: full duplex");
494
495static int read_eeprom (void *ioaddr, int location, int addr_len);
496static int netdrv_open (struct net_device *dev);
497static int mdio_read (struct net_device *dev, int phy_id, int location);
498static void mdio_write (struct net_device *dev, int phy_id, int location,
499 int val);
500static void netdrv_timer (unsigned long data);
501static void netdrv_tx_timeout (struct net_device *dev);
502static void netdrv_init_ring (struct net_device *dev);
503static int netdrv_start_xmit (struct sk_buff *skb,
504 struct net_device *dev);
7d12e780 505static irqreturn_t netdrv_interrupt (int irq, void *dev_instance);
1da177e4
LT		 506static int netdrv_close (struct net_device *dev);
507static int netdrv_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
508static struct net_device_stats *netdrv_get_stats (struct net_device *dev);
509static void netdrv_set_rx_mode (struct net_device *dev);
510static void netdrv_hw_start (struct net_device *dev);
511
512
513#ifdef USE_IO_OPS
514
515#define NETDRV_R8(reg) inb (((unsigned long)ioaddr) + (reg))
516#define NETDRV_R16(reg) inw (((unsigned long)ioaddr) + (reg))
517#define NETDRV_R32(reg) ((unsigned long) inl (((unsigned long)ioaddr) + (reg)))
518#define NETDRV_W8(reg, val8) outb ((val8), ((unsigned long)ioaddr) + (reg))
519#define NETDRV_W16(reg, val16) outw ((val16), ((unsigned long)ioaddr) + (reg))
520#define NETDRV_W32(reg, val32) outl ((val32), ((unsigned long)ioaddr) + (reg))
521#define NETDRV_W8_F NETDRV_W8
522#define NETDRV_W16_F NETDRV_W16
523#define NETDRV_W32_F NETDRV_W32
524#undef readb
525#undef readw
526#undef readl
527#undef writeb
528#undef writew
529#undef writel
530#define readb(addr) inb((unsigned long)(addr))
531#define readw(addr) inw((unsigned long)(addr))
532#define readl(addr) inl((unsigned long)(addr))
533#define writeb(val,addr) outb((val),(unsigned long)(addr))
534#define writew(val,addr) outw((val),(unsigned long)(addr))
535#define writel(val,addr) outl((val),(unsigned long)(addr))
536
537#else
538
539/* write MMIO register, with flush */
540/* Flush avoids rtl8139 bug w/ posted MMIO writes */
541#define NETDRV_W8_F(reg, val8) do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
542#define NETDRV_W16_F(reg, val16) do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
543#define NETDRV_W32_F(reg, val32) do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
544
545
546#if MMIO_FLUSH_AUDIT_COMPLETE
547
548/* write MMIO register */
549#define NETDRV_W8(reg, val8) writeb ((val8), ioaddr + (reg))
550#define NETDRV_W16(reg, val16) writew ((val16), ioaddr + (reg))
551#define NETDRV_W32(reg, val32) writel ((val32), ioaddr + (reg))
552
553#else
554
555/* write MMIO register, then flush */
556#define NETDRV_W8 NETDRV_W8_F
557#define NETDRV_W16 NETDRV_W16_F
558#define NETDRV_W32 NETDRV_W32_F
559
560#endif /* MMIO_FLUSH_AUDIT_COMPLETE */
561
562/* read MMIO register */
563#define NETDRV_R8(reg) readb (ioaddr + (reg))
564#define NETDRV_R16(reg) readw (ioaddr + (reg))
565#define NETDRV_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
566
567#endif /* USE_IO_OPS */
568
569
570static const u16 netdrv_intr_mask =
571 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
572 TxErr | TxOK | RxErr | RxOK;
573
574static const unsigned int netdrv_rx_config =
575 RxCfgEarlyRxNone | RxCfgRcv32K | RxNoWrap |
576 (RX_FIFO_THRESH << RxCfgFIFOShift) |
577 (RX_DMA_BURST << RxCfgDMAShift);
578
579
580static int __devinit netdrv_init_board (struct pci_dev *pdev,
581 struct net_device **dev_out,
582 void **ioaddr_out)
583{
584 void *ioaddr = NULL;
585 struct net_device *dev;
586 struct netdrv_private *tp;
587 int rc, i;
588 u32 pio_start, pio_end, pio_flags, pio_len;
589 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
590 u32 tmp;
591
592 DPRINTK ("ENTER\n");
593
594 assert (pdev != NULL);
595 assert (ioaddr_out != NULL);
596
597 *ioaddr_out = NULL;
598 *dev_out = NULL;
599
600 /* dev zeroed in alloc_etherdev */
601 dev = alloc_etherdev (sizeof (*tp));
602 if (dev == NULL) {
9b91cf9d 603 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1da177e4
LT		 604 DPRINTK ("EXIT, returning -ENOMEM\n");
605 return -ENOMEM;
606 }
1da177e4
LT		 607 SET_NETDEV_DEV(dev, &pdev->dev);
608 tp = dev->priv;
609
610 /* enable device (incl. PCI PM wakeup), and bus-mastering */
611 rc = pci_enable_device (pdev);
612 if (rc)
613 goto err_out;
614
615 pio_start = pci_resource_start (pdev, 0);
616 pio_end = pci_resource_end (pdev, 0);
617 pio_flags = pci_resource_flags (pdev, 0);
618 pio_len = pci_resource_len (pdev, 0);
619
620 mmio_start = pci_resource_start (pdev, 1);
621 mmio_end = pci_resource_end (pdev, 1);
622 mmio_flags = pci_resource_flags (pdev, 1);
623 mmio_len = pci_resource_len (pdev, 1);
624
625 /* set this immediately, we need to know before
626 * we talk to the chip directly */
627 DPRINTK("PIO region size == 0x%02X\n", pio_len);
628 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
629
630 /* make sure PCI base addr 0 is PIO */
631 if (!(pio_flags & IORESOURCE_IO)) {
9b91cf9d 632 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
1da177e4
LT		 633 rc = -ENODEV;
634 goto err_out;
635 }
636
637 /* make sure PCI base addr 1 is MMIO */
638 if (!(mmio_flags & IORESOURCE_MEM)) {
9b91cf9d 639 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
1da177e4
LT		 640 rc = -ENODEV;
641 goto err_out;
642 }
643
644 /* check for weird/broken PCI region reporting */
645 if ((pio_len < NETDRV_MIN_IO_SIZE) ||
646 (mmio_len < NETDRV_MIN_IO_SIZE)) {
9b91cf9d 647 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
1da177e4
LT		 648 rc = -ENODEV;
649 goto err_out;
650 }
651
2e8a538d 652 rc = pci_request_regions (pdev, MODNAME);
1da177e4
LT		 653 if (rc)
654 goto err_out;
655
656 pci_set_master (pdev);
657
658#ifdef USE_IO_OPS
659 ioaddr = (void *) pio_start;
660#else
661 /* ioremap MMIO region */
662 ioaddr = ioremap (mmio_start, mmio_len);
663 if (ioaddr == NULL) {
9b91cf9d 664 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4
LT		 665 rc = -EIO;
666 goto err_out_free_res;
667 }
668#endif /* USE_IO_OPS */
669
670 /* Soft reset the chip. */
671 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) | CmdReset);
672
673 /* Check that the chip has finished the reset. */
674 for (i = 1000; i > 0; i--)
675 if ((NETDRV_R8 (ChipCmd) & CmdReset) == 0)
676 break;
677 else
678 udelay (10);
679
680 /* Bring the chip out of low-power mode. */
681 /* <insert device-specific code here> */
682
683#ifndef USE_IO_OPS
684 /* sanity checks -- ensure PIO and MMIO registers agree */
685 assert (inb (pio_start+Config0) == readb (ioaddr+Config0));
686 assert (inb (pio_start+Config1) == readb (ioaddr+Config1));
687 assert (inb (pio_start+TxConfig) == readb (ioaddr+TxConfig));
688 assert (inb (pio_start+RxConfig) == readb (ioaddr+RxConfig));
689#endif /* !USE_IO_OPS */
690
691 /* identify chip attached to board */
692 tmp = NETDRV_R8 (ChipVersion);
693 for (i = ARRAY_SIZE (rtl_chip_info) - 1; i >= 0; i--)
694 if (tmp == rtl_chip_info[i].version) {
695 tp->chipset = i;
696 goto match;
697 }
698
699 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
2e8a538d
JG		 700 dev_printk (KERN_DEBUG, &pdev->dev,
701 "unknown chip version, assuming RTL-8139\n");
702 dev_printk (KERN_DEBUG, &pdev->dev, "TxConfig = 0x%lx\n",
703 NETDRV_R32 (TxConfig));
1da177e4
LT		 704 tp->chipset = 0;
705
706match:
707 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
708 tmp,
709 tp->chipset,
710 rtl_chip_info[tp->chipset].name);
711
5c4851cc
AB		 712 rc = register_netdev (dev);
713 if (rc)
1da177e4
LT		 714 goto err_out_unmap;
715
716 DPRINTK ("EXIT, returning 0\n");
717 *ioaddr_out = ioaddr;
718 *dev_out = dev;
719 return 0;
720
721err_out_unmap:
722#ifndef USE_IO_OPS
723 iounmap(ioaddr);
724err_out_free_res:
725#endif
726 pci_release_regions (pdev);
727err_out:
728 free_netdev (dev);
729 DPRINTK ("EXIT, returning %d\n", rc);
730 return rc;
731}
732
733
734static int __devinit netdrv_init_one (struct pci_dev *pdev,
735 const struct pci_device_id *ent)
736{
737 struct net_device *dev = NULL;
738 struct netdrv_private *tp;
739 int i, addr_len, option;
740 void *ioaddr = NULL;
741 static int board_idx = -1;
742
743/* when built into the kernel, we only print version if device is found */
744#ifndef MODULE
745 static int printed_version;
746 if (!printed_version++)
747 printk(version);
748#endif
749
750 DPRINTK ("ENTER\n");
751
752 assert (pdev != NULL);
753 assert (ent != NULL);
754
755 board_idx++;
756
757 i = netdrv_init_board (pdev, &dev, &ioaddr);
758 if (i < 0) {
759 DPRINTK ("EXIT, returning %d\n", i);
760 return i;
761 }
762
763 tp = dev->priv;
764
765 assert (ioaddr != NULL);
766 assert (dev != NULL);
767 assert (tp != NULL);
768
769 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
770 for (i = 0; i < 3; i++)
771 ((u16 *) (dev->dev_addr))[i] =
772 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
773
774 /* The Rtl8139-specific entries in the device structure. */
775 dev->open = netdrv_open;
776 dev->hard_start_xmit = netdrv_start_xmit;
777 dev->stop = netdrv_close;
778 dev->get_stats = netdrv_get_stats;
779 dev->set_multicast_list = netdrv_set_rx_mode;
780 dev->do_ioctl = netdrv_ioctl;
781 dev->tx_timeout = netdrv_tx_timeout;
782 dev->watchdog_timeo = TX_TIMEOUT;
783
784 dev->irq = pdev->irq;
785 dev->base_addr = (unsigned long) ioaddr;
786
787 /* dev->priv/tp zeroed and aligned in alloc_etherdev */
788 tp = dev->priv;
789
790 /* note: tp->chipset set in netdrv_init_board */
791 tp->drv_flags = PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
792 PCI_COMMAND_MASTER | NETDRV_CAPS;
793 tp->pci_dev = pdev;
794 tp->board = ent->driver_data;
795 tp->mmio_addr = ioaddr;
796 spin_lock_init(&tp->lock);
797
798 pci_set_drvdata(pdev, dev);
799
800 tp->phys[0] = 32;
801
802 printk (KERN_INFO "%s: %s at 0x%lx, "
803 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
804 "IRQ %d\n",
805 dev->name,
806 board_info[ent->driver_data].name,
807 dev->base_addr,
808 dev->dev_addr[0], dev->dev_addr[1],
809 dev->dev_addr[2], dev->dev_addr[3],
810 dev->dev_addr[4], dev->dev_addr[5],
811 dev->irq);
812
813 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
814 dev->name, rtl_chip_info[tp->chipset].name);
815
816 /* Put the chip into low-power mode. */
817 NETDRV_W8_F (Cfg9346, Cfg9346_Unlock);
818
819 /* The lower four bits are the media type. */
820 option = (board_idx > 7) ? 0 : media[board_idx];
821 if (option > 0) {
822 tp->full_duplex = (option & 0x200) ? 1 : 0;
823 tp->default_port = option & 15;
824 if (tp->default_port)
825 tp->medialock = 1;
826 }
827
828 if (tp->full_duplex) {
829 printk (KERN_INFO
830 "%s: Media type forced to Full Duplex.\n",
831 dev->name);
832 mdio_write (dev, tp->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
833 tp->duplex_lock = 1;
834 }
835
836 DPRINTK ("EXIT - returning 0\n");
837 return 0;
838}
839
840
841static void __devexit netdrv_remove_one (struct pci_dev *pdev)
842{
843 struct net_device *dev = pci_get_drvdata (pdev);
844 struct netdrv_private *np;
845
846 DPRINTK ("ENTER\n");
847
848 assert (dev != NULL);
849
850 np = dev->priv;
851 assert (np != NULL);
852
853 unregister_netdev (dev);
854
855#ifndef USE_IO_OPS
856 iounmap (np->mmio_addr);
857#endif /* !USE_IO_OPS */
858
859 pci_release_regions (pdev);
860
861 free_netdev (dev);
862
863 pci_set_drvdata (pdev, NULL);
864
865 pci_disable_device (pdev);
866
867 DPRINTK ("EXIT\n");
868}
869
870
871/* Serial EEPROM section. */
872
873/* EEPROM_Ctrl bits. */
874#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
875#define EE_CS 0x08 /* EEPROM chip select. */
876#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
877#define EE_WRITE_0 0x00
878#define EE_WRITE_1 0x02
879#define EE_DATA_READ 0x01 /* EEPROM chip data out. */
880#define EE_ENB (0x80 | EE_CS)
881
882/* Delay between EEPROM clock transitions.
883 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
884 */
885
886#define eeprom_delay() readl(ee_addr)
887
888/* The EEPROM commands include the alway-set leading bit. */
889#define EE_WRITE_CMD (5)
890#define EE_READ_CMD (6)
891#define EE_ERASE_CMD (7)
892
893static int __devinit read_eeprom (void *ioaddr, int location, int addr_len)
894{
895 int i;
896 unsigned retval = 0;
897 void *ee_addr = ioaddr + Cfg9346;
898 int read_cmd = location | (EE_READ_CMD << addr_len);
899
900 DPRINTK ("ENTER\n");
901
902 writeb (EE_ENB & ~EE_CS, ee_addr);
903 writeb (EE_ENB, ee_addr);
904 eeprom_delay ();
905
906 /* Shift the read command bits out. */
907 for (i = 4 + addr_len; i >= 0; i--) {
908 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
909 writeb (EE_ENB | dataval, ee_addr);
910 eeprom_delay ();
911 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
912 eeprom_delay ();
913 }
914 writeb (EE_ENB, ee_addr);
915 eeprom_delay ();
916
917 for (i = 16; i > 0; i--) {
918 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
919 eeprom_delay ();
920 retval =
921 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
922 0);
923 writeb (EE_ENB, ee_addr);
924 eeprom_delay ();
925 }
926
927 /* Terminate the EEPROM access. */
928 writeb (~EE_CS, ee_addr);
929 eeprom_delay ();
930
931 DPRINTK ("EXIT - returning %d\n", retval);
932 return retval;
933}
934
935/* MII serial management: mostly bogus for now. */
936/* Read and write the MII management registers using software-generated
937 serial MDIO protocol.
938 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
939 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
940 "overclocking" issues. */
941#define MDIO_DIR 0x80
942#define MDIO_DATA_OUT 0x04
943#define MDIO_DATA_IN 0x02
944#define MDIO_CLK 0x01
945#define MDIO_WRITE0 (MDIO_DIR)
946#define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
947
948#define mdio_delay() readb(mdio_addr)
949
950
951static char mii_2_8139_map[8] = {
952 BasicModeCtrl,
953 BasicModeStatus,
954 0,
955 0,
956 NWayAdvert,
957 NWayLPAR,
958 NWayExpansion,
959 0
960};
961
962
963/* Syncronize the MII management interface by shifting 32 one bits out. */
964static void mdio_sync (void *mdio_addr)
965{
966 int i;
967
968 DPRINTK ("ENTER\n");
969
970 for (i = 32; i >= 0; i--) {
971 writeb (MDIO_WRITE1, mdio_addr);
972 mdio_delay ();
973 writeb (MDIO_WRITE1 | MDIO_CLK, mdio_addr);
974 mdio_delay ();
975 }
976
977 DPRINTK ("EXIT\n");
978}
979
980
981static int mdio_read (struct net_device *dev, int phy_id, int location)
982{
983 struct netdrv_private *tp = dev->priv;
984 void *mdio_addr = tp->mmio_addr + Config4;
985 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
986 int retval = 0;
987 int i;
988
989 DPRINTK ("ENTER\n");
990
991 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
992 DPRINTK ("EXIT after directly using 8139 internal regs\n");
993 return location < 8 && mii_2_8139_map[location] ?
994 readw (tp->mmio_addr + mii_2_8139_map[location]) : 0;
995 }
996 mdio_sync (mdio_addr);
997 /* Shift the read command bits out. */
998 for (i = 15; i >= 0; i--) {
999 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1000
1001 writeb (MDIO_DIR | dataval, mdio_addr);
1002 mdio_delay ();
1003 writeb (MDIO_DIR | dataval | MDIO_CLK, mdio_addr);
1004 mdio_delay ();
1005 }
1006
1007 /* Read the two transition, 16 data, and wire-idle bits. */
1008 for (i = 19; i > 0; i--) {
1009 writeb (0, mdio_addr);
1010 mdio_delay ();
1011 retval =
1012 (retval << 1) | ((readb (mdio_addr) & MDIO_DATA_IN) ? 1
1013 : 0);
1014 writeb (MDIO_CLK, mdio_addr);
1015 mdio_delay ();
1016 }
1017
1018 DPRINTK ("EXIT, returning %d\n", (retval >> 1) & 0xffff);
1019 return (retval >> 1) & 0xffff;
1020}
1021
1022
1023static void mdio_write (struct net_device *dev, int phy_id, int location,
1024 int value)
1025{
1026 struct netdrv_private *tp = dev->priv;
1027 void *mdio_addr = tp->mmio_addr + Config4;
1028 int mii_cmd =
1029 (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1030 int i;
1031
1032 DPRINTK ("ENTER\n");
1033
1034 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1035 if (location < 8 && mii_2_8139_map[location]) {
1036 writew (value,
1037 tp->mmio_addr + mii_2_8139_map[location]);
1038 readw (tp->mmio_addr + mii_2_8139_map[location]);
1039 }
1040 DPRINTK ("EXIT after directly using 8139 internal regs\n");
1041 return;
1042 }
1043 mdio_sync (mdio_addr);
1044
1045 /* Shift the command bits out. */
1046 for (i = 31; i >= 0; i--) {
1047 int dataval =
1048 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1049 writeb (dataval, mdio_addr);
1050 mdio_delay ();
1051 writeb (dataval | MDIO_CLK, mdio_addr);
1052 mdio_delay ();
1053 }
1054
1055 /* Clear out extra bits. */
1056 for (i = 2; i > 0; i--) {
1057 writeb (0, mdio_addr);
1058 mdio_delay ();
1059 writeb (MDIO_CLK, mdio_addr);
1060 mdio_delay ();
1061 }
1062
1063 DPRINTK ("EXIT\n");
1064}
1065
1066
1067static int netdrv_open (struct net_device *dev)
1068{
1069 struct netdrv_private *tp = dev->priv;
1070 int retval;
1071#ifdef NETDRV_DEBUG
1072 void *ioaddr = tp->mmio_addr;
1073#endif
1074
1075 DPRINTK ("ENTER\n");
1076
1fb9df5d 1077 retval = request_irq (dev->irq, netdrv_interrupt, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 1078 if (retval) {
1079 DPRINTK ("EXIT, returning %d\n", retval);
1080 return retval;
1081 }
1082
1083 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1084 &tp->tx_bufs_dma);
1085 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1086 &tp->rx_ring_dma);
1087 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1088 free_irq(dev->irq, dev);
1089
1090 if (tp->tx_bufs)
1091 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1092 tp->tx_bufs, tp->tx_bufs_dma);
1093 if (tp->rx_ring)
1094 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1095 tp->rx_ring, tp->rx_ring_dma);
1096
1097 DPRINTK ("EXIT, returning -ENOMEM\n");
1098 return -ENOMEM;
1099
1100 }
1101
1102 tp->full_duplex = tp->duplex_lock;
1103 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1104
1105 netdrv_init_ring (dev);
1106 netdrv_hw_start (dev);
1107
1108 DPRINTK ("%s: netdrv_open() ioaddr %#lx IRQ %d"
1109 " GP Pins %2.2x %s-duplex.\n",
1110 dev->name, pci_resource_start (tp->pci_dev, 1),
1111 dev->irq, NETDRV_R8 (MediaStatus),
1112 tp->full_duplex ? "full" : "half");
1113
1114 /* Set the timer to switch to check for link beat and perhaps switch
1115 to an alternate media type. */
1116 init_timer (&tp->timer);
1117 tp->timer.expires = jiffies + 3 * HZ;
1118 tp->timer.data = (unsigned long) dev;
1119 tp->timer.function = &netdrv_timer;
1120 add_timer (&tp->timer);
1121
1122 DPRINTK ("EXIT, returning 0\n");
1123 return 0;
1124}
1125
1126
1127/* Start the hardware at open or resume. */
1128static void netdrv_hw_start (struct net_device *dev)
1129{
1130 struct netdrv_private *tp = dev->priv;
1131 void *ioaddr = tp->mmio_addr;
1132 u32 i;
1133
1134 DPRINTK ("ENTER\n");
1135
1136 /* Soft reset the chip. */
1137 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) | CmdReset);
1138 udelay (100);
1139
1140 /* Check that the chip has finished the reset. */
1141 for (i = 1000; i > 0; i--)
1142 if ((NETDRV_R8 (ChipCmd) & CmdReset) == 0)
1143 break;
1144
1145 /* Restore our idea of the MAC address. */
1146 NETDRV_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1147 NETDRV_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1148
1149 /* Must enable Tx/Rx before setting transfer thresholds! */
1150 NETDRV_W8_F (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) |
1151 CmdRxEnb | CmdTxEnb);
1152
1153 i = netdrv_rx_config |
1154 (NETDRV_R32 (RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1155 NETDRV_W32_F (RxConfig, i);
1156
1157 /* Check this value: the documentation for IFG contradicts ifself. */
1158 NETDRV_W32 (TxConfig, (TX_DMA_BURST << TxDMAShift));
1159
1160 /* unlock Config[01234] and BMCR register writes */
1161 NETDRV_W8_F (Cfg9346, Cfg9346_Unlock);
1162 udelay (10);
1163
1164 tp->cur_rx = 0;
1165
1166 /* Lock Config[01234] and BMCR register writes */
1167 NETDRV_W8_F (Cfg9346, Cfg9346_Lock);
1168 udelay (10);
1169
1170 /* init Rx ring buffer DMA address */
1171 NETDRV_W32_F (RxBuf, tp->rx_ring_dma);
1172
1173 /* init Tx buffer DMA addresses */
1174 for (i = 0; i < NUM_TX_DESC; i++)
1175 NETDRV_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1176
1177 NETDRV_W32_F (RxMissed, 0);
1178
1179 netdrv_set_rx_mode (dev);
1180
1181 /* no early-rx interrupts */
1182 NETDRV_W16 (MultiIntr, NETDRV_R16 (MultiIntr) & MultiIntrClear);
1183
1184 /* make sure RxTx has started */
1185 NETDRV_W8_F (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) |
1186 CmdRxEnb | CmdTxEnb);
1187
1188 /* Enable all known interrupts by setting the interrupt mask. */
1189 NETDRV_W16_F (IntrMask, netdrv_intr_mask);
1190
1191 netif_start_queue (dev);
1192
1193 DPRINTK ("EXIT\n");
1194}
1195
1196
1197/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1198static void netdrv_init_ring (struct net_device *dev)
1199{
1200 struct netdrv_private *tp = dev->priv;
1201 int i;
1202
1203 DPRINTK ("ENTER\n");
1204
1205 tp->cur_rx = 0;
1206 atomic_set (&tp->cur_tx, 0);
1207 atomic_set (&tp->dirty_tx, 0);
1208
1209 for (i = 0; i < NUM_TX_DESC; i++) {
1210 tp->tx_info[i].skb = NULL;
1211 tp->tx_info[i].mapping = 0;
1212 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1213 }
1214
1215 DPRINTK ("EXIT\n");
1216}
1217
1218
1219static void netdrv_timer (unsigned long data)
1220{
1221 struct net_device *dev = (struct net_device *) data;
1222 struct netdrv_private *tp = dev->priv;
1223 void *ioaddr = tp->mmio_addr;
1224 int next_tick = 60 * HZ;
1225 int mii_lpa;
1226
1227 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1228
1229 if (!tp->duplex_lock && mii_lpa != 0xffff) {
1230 int duplex = (mii_lpa & LPA_100FULL)
1231 || (mii_lpa & 0x01C0) == 0x0040;
1232 if (tp->full_duplex != duplex) {
1233 tp->full_duplex = duplex;
1234 printk (KERN_INFO
1235 "%s: Setting %s-duplex based on MII #%d link"
1236 " partner ability of %4.4x.\n", dev->name,
1237 tp->full_duplex ? "full" : "half",
1238 tp->phys[0], mii_lpa);
1239 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1240 NETDRV_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1241 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1242 }
1243 }
1244
1245 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1246 dev->name, NETDRV_R16 (NWayLPAR));
1247 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x"
1248 " RxStatus %4.4x.\n", dev->name,
1249 NETDRV_R16 (IntrMask),
1250 NETDRV_R16 (IntrStatus),
1251 NETDRV_R32 (RxEarlyStatus));
1252 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1253 dev->name, NETDRV_R8 (Config0),
1254 NETDRV_R8 (Config1));
1255
1256 tp->timer.expires = jiffies + next_tick;
1257 add_timer (&tp->timer);
1258}
1259
1260
1261static void netdrv_tx_clear (struct netdrv_private *tp)
1262{
1263 int i;
1264
1265 atomic_set (&tp->cur_tx, 0);
1266 atomic_set (&tp->dirty_tx, 0);
1267
1268 /* Dump the unsent Tx packets. */
1269 for (i = 0; i < NUM_TX_DESC; i++) {
1270 struct ring_info *rp = &tp->tx_info[i];
1271 if (rp->mapping != 0) {
1272 pci_unmap_single (tp->pci_dev, rp->mapping,
1273 rp->skb->len, PCI_DMA_TODEVICE);
1274 rp->mapping = 0;
1275 }
1276 if (rp->skb) {
1277 dev_kfree_skb (rp->skb);
1278 rp->skb = NULL;
1279 tp->stats.tx_dropped++;
1280 }
1281 }
1282}
1283
1284
1285static void netdrv_tx_timeout (struct net_device *dev)
1286{
1287 struct netdrv_private *tp = dev->priv;
1288 void *ioaddr = tp->mmio_addr;
1289 int i;
1290 u8 tmp8;
1291 unsigned long flags;
1292
1293 DPRINTK ("%s: Transmit timeout, status %2.2x %4.4x "
1294 "media %2.2x.\n", dev->name,
1295 NETDRV_R8 (ChipCmd),
1296 NETDRV_R16 (IntrStatus),
1297 NETDRV_R8 (MediaStatus));
1298
1299 /* disable Tx ASAP, if not already */
1300 tmp8 = NETDRV_R8 (ChipCmd);
1301 if (tmp8 & CmdTxEnb)
1302 NETDRV_W8 (ChipCmd, tmp8 & ~CmdTxEnb);
1303
1304 /* Disable interrupts by clearing the interrupt mask. */
1305 NETDRV_W16 (IntrMask, 0x0000);
1306
1307 /* Emit info to figure out what went wrong. */
1308 printk (KERN_DEBUG "%s: Tx queue start entry %d dirty entry %d.\n",
1309 dev->name, atomic_read (&tp->cur_tx),
1310 atomic_read (&tp->dirty_tx));
1311 for (i = 0; i < NUM_TX_DESC; i++)
1312 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1313 dev->name, i, NETDRV_R32 (TxStatus0 + (i * 4)),
1314 i == atomic_read (&tp->dirty_tx) % NUM_TX_DESC ?
1315 " (queue head)" : "");
1316
1317 /* Stop a shared interrupt from scavenging while we are. */
1318 spin_lock_irqsave (&tp->lock, flags);
6aa20a22 1319
1da177e4
LT		 1320 netdrv_tx_clear (tp);
1321
1322 spin_unlock_irqrestore (&tp->lock, flags);
1323
1324 /* ...and finally, reset everything */
1325 netdrv_hw_start (dev);
1326
1327 netif_wake_queue (dev);
1328}
1329
1330
1331
1332static int netdrv_start_xmit (struct sk_buff *skb, struct net_device *dev)
1333{
1334 struct netdrv_private *tp = dev->priv;
1335 void *ioaddr = tp->mmio_addr;
1336 int entry;
1337
1338 /* Calculate the next Tx descriptor entry. */
1339 entry = atomic_read (&tp->cur_tx) % NUM_TX_DESC;
1340
1341 assert (tp->tx_info[entry].skb == NULL);
1342 assert (tp->tx_info[entry].mapping == 0);
1343
1344 tp->tx_info[entry].skb = skb;
1345 /* tp->tx_info[entry].mapping = 0; */
d626f62b 1346 skb_copy_from_linear_data(skb, tp->tx_buf[entry], skb->len);
1da177e4
LT		 1347
1348 /* Note: the chip doesn't have auto-pad! */
1349 NETDRV_W32 (TxStatus0 + (entry * sizeof(u32)),
1350 tp->tx_flag | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1351
1352 dev->trans_start = jiffies;
1353 atomic_inc (&tp->cur_tx);
1354 if ((atomic_read (&tp->cur_tx) - atomic_read (&tp->dirty_tx)) >= NUM_TX_DESC)
1355 netif_stop_queue (dev);
1356
1357 DPRINTK ("%s: Queued Tx packet at %p size %u to slot %d.\n",
1358 dev->name, skb->data, skb->len, entry);
1359
1360 return 0;
1361}
1362
1363
1364static void netdrv_tx_interrupt (struct net_device *dev,
1365 struct netdrv_private *tp,
1366 void *ioaddr)
1367{
1368 int cur_tx, dirty_tx, tx_left;
1369
1370 assert (dev != NULL);
1371 assert (tp != NULL);
1372 assert (ioaddr != NULL);
1373
1374 dirty_tx = atomic_read (&tp->dirty_tx);
1375
1376 cur_tx = atomic_read (&tp->cur_tx);
1377 tx_left = cur_tx - dirty_tx;
1378 while (tx_left > 0) {
1379 int entry = dirty_tx % NUM_TX_DESC;
1380 int txstatus;
1381
1382 txstatus = NETDRV_R32 (TxStatus0 + (entry * sizeof (u32)));
1383
1384 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1385 break; /* It still hasn't been Txed */
1386
1387 /* Note: TxCarrierLost is always asserted at 100mbps. */
1388 if (txstatus & (TxOutOfWindow | TxAborted)) {
1389 /* There was an major error, log it. */
1390 DPRINTK ("%s: Transmit error, Tx status %8.8x.\n",
1391 dev->name, txstatus);
1392 tp->stats.tx_errors++;
1393 if (txstatus & TxAborted) {
1394 tp->stats.tx_aborted_errors++;
1395 NETDRV_W32 (TxConfig, TxClearAbt | (TX_DMA_BURST << TxDMAShift));
1396 }
1397 if (txstatus & TxCarrierLost)
1398 tp->stats.tx_carrier_errors++;
1399 if (txstatus & TxOutOfWindow)
1400 tp->stats.tx_window_errors++;
1401 } else {
1402 if (txstatus & TxUnderrun) {
1403 /* Add 64 to the Tx FIFO threshold. */
1404 if (tp->tx_flag < 0x00300000)
1405 tp->tx_flag += 0x00020000;
1406 tp->stats.tx_fifo_errors++;
1407 }
1408 tp->stats.collisions += (txstatus >> 24) & 15;
1409 tp->stats.tx_bytes += txstatus & 0x7ff;
1410 tp->stats.tx_packets++;
1411 }
1412
1413 /* Free the original skb. */
1414 if (tp->tx_info[entry].mapping != 0) {
1415 pci_unmap_single(tp->pci_dev,
1416 tp->tx_info[entry].mapping,
1417 tp->tx_info[entry].skb->len,
1418 PCI_DMA_TODEVICE);
1419 tp->tx_info[entry].mapping = 0;
1420 }
1421 dev_kfree_skb_irq (tp->tx_info[entry].skb);
1422 tp->tx_info[entry].skb = NULL;
1423 dirty_tx++;
1424 if (dirty_tx < 0) { /* handle signed int overflow */
1425 atomic_sub (cur_tx, &tp->cur_tx); /* XXX racy? */
1426 dirty_tx = cur_tx - tx_left + 1;
1427 }
1428 if (netif_queue_stopped (dev))
1429 netif_wake_queue (dev);
1430
1431 cur_tx = atomic_read (&tp->cur_tx);
1432 tx_left = cur_tx - dirty_tx;
1433
1434 }
1435
1436#ifndef NETDRV_NDEBUG
1437 if (atomic_read (&tp->cur_tx) - dirty_tx > NUM_TX_DESC) {
1438 printk (KERN_ERR
1439 "%s: Out-of-sync dirty pointer, %d vs. %d.\n",
1440 dev->name, dirty_tx, atomic_read (&tp->cur_tx));
1441 dirty_tx += NUM_TX_DESC;
1442 }
1443#endif /* NETDRV_NDEBUG */
1444
1445 atomic_set (&tp->dirty_tx, dirty_tx);
1446}
1447
1448
1449/* TODO: clean this up! Rx reset need not be this intensive */
1450static void netdrv_rx_err (u32 rx_status, struct net_device *dev,
1451 struct netdrv_private *tp, void *ioaddr)
1452{
1453 u8 tmp8;
1454 int tmp_work = 1000;
1455
1456 DPRINTK ("%s: Ethernet frame had errors, status %8.8x.\n",
1457 dev->name, rx_status);
1458 if (rx_status & RxTooLong) {
1459 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1460 dev->name, rx_status);
1461 /* A.C.: The chip hangs here. */
1462 }
1463 tp->stats.rx_errors++;
1464 if (rx_status & (RxBadSymbol | RxBadAlign))
1465 tp->stats.rx_frame_errors++;
1466 if (rx_status & (RxRunt | RxTooLong))
1467 tp->stats.rx_length_errors++;
1468 if (rx_status & RxCRCErr)
1469 tp->stats.rx_crc_errors++;
1470 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1471 tp->cur_rx = 0;
1472
1473 /* disable receive */
1474 tmp8 = NETDRV_R8 (ChipCmd) & ChipCmdClear;
1475 NETDRV_W8_F (ChipCmd, tmp8 | CmdTxEnb);
1476
1477 /* A.C.: Reset the multicast list. */
1478 netdrv_set_rx_mode (dev);
1479
1480 /* XXX potentially temporary hack to
1481 * restart hung receiver */
1482 while (--tmp_work > 0) {
1483 tmp8 = NETDRV_R8 (ChipCmd);
1484 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1485 break;
1486 NETDRV_W8_F (ChipCmd,
1487 (tmp8 & ChipCmdClear) | CmdRxEnb | CmdTxEnb);
1488 }
1489
1490 /* G.S.: Re-enable receiver */
1491 /* XXX temporary hack to work around receiver hang */
1492 netdrv_set_rx_mode (dev);
1493
1494 if (tmp_work <= 0)
1495 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1496}
1497
1498
1499/* The data sheet doesn't describe the Rx ring at all, so I'm guessing at the
1500 field alignments and semantics. */
1501static void netdrv_rx_interrupt (struct net_device *dev,
1502 struct netdrv_private *tp, void *ioaddr)
1503{
1504 unsigned char *rx_ring;
1505 u16 cur_rx;
1506
1507 assert (dev != NULL);
1508 assert (tp != NULL);
1509 assert (ioaddr != NULL);
1510
1511 rx_ring = tp->rx_ring;
1512 cur_rx = tp->cur_rx;
1513
1514 DPRINTK ("%s: In netdrv_rx(), current %4.4x BufAddr %4.4x,"
1515 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1516 NETDRV_R16 (RxBufAddr),
1517 NETDRV_R16 (RxBufPtr), NETDRV_R8 (ChipCmd));
1518
1519 while ((NETDRV_R8 (ChipCmd) & RxBufEmpty) == 0) {
1520 int ring_offset = cur_rx % RX_BUF_LEN;
1521 u32 rx_status;
1522 unsigned int rx_size;
1523 unsigned int pkt_size;
1524 struct sk_buff *skb;
1525
1526 /* read size+status of next frame from DMA ring buffer */
1527 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1528 rx_size = rx_status >> 16;
1529 pkt_size = rx_size - 4;
1530
1531 DPRINTK ("%s: netdrv_rx() status %4.4x, size %4.4x,"
1532 " cur %4.4x.\n", dev->name, rx_status,
1533 rx_size, cur_rx);
1534#if NETDRV_DEBUG > 2
1535 {
1536 int i;
1537 DPRINTK ("%s: Frame contents ", dev->name);
1538 for (i = 0; i < 70; i++)
1539 printk (" %2.2x",
1540 rx_ring[ring_offset + i]);
1541 printk (".\n");
1542 }
1543#endif
1544
1545 /* If Rx err or invalid rx_size/rx_status received
1546 * (which happens if we get lost in the ring),
1547 * Rx process gets reset, so we abort any further
1548 * Rx processing.
1549 */
1550 if ((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1551 (!(rx_status & RxStatusOK))) {
1552 netdrv_rx_err (rx_status, dev, tp, ioaddr);
1553 return;
1554 }
1555
1556 /* Malloc up new buffer, compatible with net-2e. */
1557 /* Omit the four octet CRC from the length. */
1558
1559 /* TODO: consider allocating skb's outside of
1560 * interrupt context, both to speed interrupt processing,
1561 * and also to reduce the chances of having to
1562 * drop packets here under memory pressure.
1563 */
1564
1565 skb = dev_alloc_skb (pkt_size + 2);
1566 if (skb) {
1da177e4
LT		 1567 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
1568
8c7b7faa 1569 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
1da177e4
LT		 1570 skb_put (skb, pkt_size);
1571
1572 skb->protocol = eth_type_trans (skb, dev);
1573 netif_rx (skb);
1574 dev->last_rx = jiffies;
1575 tp->stats.rx_bytes += pkt_size;
1576 tp->stats.rx_packets++;
1577 } else {
1578 printk (KERN_WARNING
1579 "%s: Memory squeeze, dropping packet.\n",
1580 dev->name);
1581 tp->stats.rx_dropped++;
1582 }
1583
1584 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
1585 NETDRV_W16_F (RxBufPtr, cur_rx - 16);
1586 }
1587
1588 DPRINTK ("%s: Done netdrv_rx(), current %4.4x BufAddr %4.4x,"
1589 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1590 NETDRV_R16 (RxBufAddr),
1591 NETDRV_R16 (RxBufPtr), NETDRV_R8 (ChipCmd));
1592
1593 tp->cur_rx = cur_rx;
1594}
1595
1596
1597static void netdrv_weird_interrupt (struct net_device *dev,
1598 struct netdrv_private *tp,
1599 void *ioaddr,
1600 int status, int link_changed)
1601{
1602 printk (KERN_DEBUG "%s: Abnormal interrupt, status %8.8x.\n",
1603 dev->name, status);
1604
1605 assert (dev != NULL);
1606 assert (tp != NULL);
1607 assert (ioaddr != NULL);
1608
1609 /* Update the error count. */
1610 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1611 NETDRV_W32 (RxMissed, 0);
1612
1613 if ((status & RxUnderrun) && link_changed &&
1614 (tp->drv_flags & HAS_LNK_CHNG)) {
1615 /* Really link-change on new chips. */
1616 int lpar = NETDRV_R16 (NWayLPAR);
1617 int duplex = (lpar & 0x0100) || (lpar & 0x01C0) == 0x0040
1618 || tp->duplex_lock;
1619 if (tp->full_duplex != duplex) {
1620 tp->full_duplex = duplex;
1621 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1622 NETDRV_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1623 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1624 }
1625 status &= ~RxUnderrun;
1626 }
1627
1628 /* XXX along with netdrv_rx_err, are we double-counting errors? */
1629 if (status &
1630 (RxUnderrun | RxOverflow | RxErr | RxFIFOOver))
1631 tp->stats.rx_errors++;
1632
1633 if (status & (PCSTimeout))
1634 tp->stats.rx_length_errors++;
1635 if (status & (RxUnderrun | RxFIFOOver))
1636 tp->stats.rx_fifo_errors++;
1637 if (status & RxOverflow) {
1638 tp->stats.rx_over_errors++;
1639 tp->cur_rx = NETDRV_R16 (RxBufAddr) % RX_BUF_LEN;
1640 NETDRV_W16_F (RxBufPtr, tp->cur_rx - 16);
1641 }
1642 if (status & PCIErr) {
1643 u16 pci_cmd_status;
1644 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
1645
1646 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
1647 dev->name, pci_cmd_status);
1648 }
1649}
1650
1651
1652/* The interrupt handler does all of the Rx thread work and cleans up
1653 after the Tx thread. */
7d12e780 1654static irqreturn_t netdrv_interrupt (int irq, void *dev_instance)
1da177e4
LT		 1655{
1656 struct net_device *dev = (struct net_device *) dev_instance;
1657 struct netdrv_private *tp = dev->priv;
1658 int boguscnt = max_interrupt_work;
1659 void *ioaddr = tp->mmio_addr;
1660 int status = 0, link_changed = 0; /* avoid bogus "uninit" warning */
1661 int handled = 0;
1662
1663 spin_lock (&tp->lock);
1664
1665 do {
1666 status = NETDRV_R16 (IntrStatus);
1667
1668 /* h/w no longer present (hotplug?) or major error, bail */
1669 if (status == 0xFFFF)
1670 break;
1671
1672 handled = 1;
1673 /* Acknowledge all of the current interrupt sources ASAP */
1674 NETDRV_W16_F (IntrStatus, status);
1675
1676 DPRINTK ("%s: interrupt status=%#4.4x new intstat=%#4.4x.\n",
1677 dev->name, status,
1678 NETDRV_R16 (IntrStatus));
1679
1680 if ((status &
1681 (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1682 RxFIFOOver | TxErr | TxOK | RxErr | RxOK)) == 0)
1683 break;
1684
1685 /* Check uncommon events with one test. */
1686 if (status & (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1687 RxFIFOOver | TxErr | RxErr))
1688 netdrv_weird_interrupt (dev, tp, ioaddr,
1689 status, link_changed);
1690
1691 if (status & (RxOK | RxUnderrun | RxOverflow | RxFIFOOver)) /* Rx interrupt */
1692 netdrv_rx_interrupt (dev, tp, ioaddr);
1693
1694 if (status & (TxOK | TxErr))
1695 netdrv_tx_interrupt (dev, tp, ioaddr);
1696
1697 boguscnt--;
1698 } while (boguscnt > 0);
1699
1700 if (boguscnt <= 0) {
1701 printk (KERN_WARNING
1702 "%s: Too much work at interrupt, "
1703 "IntrStatus=0x%4.4x.\n", dev->name,
1704 status);
1705
1706 /* Clear all interrupt sources. */
1707 NETDRV_W16 (IntrStatus, 0xffff);
1708 }
1709
1710 spin_unlock (&tp->lock);
1711
1712 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
1713 dev->name, NETDRV_R16 (IntrStatus));
1714 return IRQ_RETVAL(handled);
1715}
1716
1717
1718static int netdrv_close (struct net_device *dev)
1719{
1720 struct netdrv_private *tp = dev->priv;
1721 void *ioaddr = tp->mmio_addr;
1722 unsigned long flags;
1723
1724 DPRINTK ("ENTER\n");
1725
1726 netif_stop_queue (dev);
1727
1728 DPRINTK ("%s: Shutting down ethercard, status was 0x%4.4x.\n",
1729 dev->name, NETDRV_R16 (IntrStatus));
1730
1731 del_timer_sync (&tp->timer);
1732
1733 spin_lock_irqsave (&tp->lock, flags);
1734
1735 /* Stop the chip's Tx and Rx DMA processes. */
1736 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear));
1737
1738 /* Disable interrupts by clearing the interrupt mask. */
1739 NETDRV_W16 (IntrMask, 0x0000);
1740
1741 /* Update the error counts. */
1742 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1743 NETDRV_W32 (RxMissed, 0);
1744
1745 spin_unlock_irqrestore (&tp->lock, flags);
1746
1747 synchronize_irq ();
1748 free_irq (dev->irq, dev);
1749
1750 netdrv_tx_clear (tp);
1751
1752 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1753 tp->rx_ring, tp->rx_ring_dma);
1754 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1755 tp->tx_bufs, tp->tx_bufs_dma);
1756 tp->rx_ring = NULL;
1757 tp->tx_bufs = NULL;
1758
1759 /* Green! Put the chip in low-power mode. */
1760 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1761 NETDRV_W8 (Config1, 0x03);
1762 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1763
1764 DPRINTK ("EXIT\n");
1765 return 0;
1766}
1767
1768
1769static int netdrv_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1770{
1771 struct netdrv_private *tp = dev->priv;
1772 struct mii_ioctl_data *data = if_mii(rq);
1773 unsigned long flags;
1774 int rc = 0;
1775
1776 DPRINTK ("ENTER\n");
1777
1778 switch (cmd) {
1779 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1780 data->phy_id = tp->phys[0] & 0x3f;
1781 /* Fall Through */
1782
1783 case SIOCGMIIREG: /* Read MII PHY register. */
1784 spin_lock_irqsave (&tp->lock, flags);
1785 data->val_out = mdio_read (dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
1786 spin_unlock_irqrestore (&tp->lock, flags);
1787 break;
1788
1789 case SIOCSMIIREG: /* Write MII PHY register. */
1790 if (!capable (CAP_NET_ADMIN)) {
1791 rc = -EPERM;
1792 break;
1793 }
1794
1795 spin_lock_irqsave (&tp->lock, flags);
1796 mdio_write (dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1797 spin_unlock_irqrestore (&tp->lock, flags);
1798 break;
1799
1800 default:
1801 rc = -EOPNOTSUPP;
1802 break;
1803 }
1804
1805 DPRINTK ("EXIT, returning %d\n", rc);
1806 return rc;
1807}
1808
1809
1810static struct net_device_stats *netdrv_get_stats (struct net_device *dev)
1811{
1812 struct netdrv_private *tp = dev->priv;
1813 void *ioaddr = tp->mmio_addr;
1814
1815 DPRINTK ("ENTER\n");
1816
1817 assert (tp != NULL);
1818
1819 if (netif_running(dev)) {
1820 unsigned long flags;
1821
1822 spin_lock_irqsave (&tp->lock, flags);
1823
1824 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1825 NETDRV_W32 (RxMissed, 0);
1826
1827 spin_unlock_irqrestore (&tp->lock, flags);
1828 }
1829
1830 DPRINTK ("EXIT\n");
1831 return &tp->stats;
1832}
1833
1834/* Set or clear the multicast filter for this adaptor.
1835 This routine is not state sensitive and need not be SMP locked. */
1836
1837static void netdrv_set_rx_mode (struct net_device *dev)
1838{
1839 struct netdrv_private *tp = dev->priv;
1840 void *ioaddr = tp->mmio_addr;
1841 u32 mc_filter[2]; /* Multicast hash filter */
1842 int i, rx_mode;
1843 u32 tmp;
1844
1845 DPRINTK ("ENTER\n");
1846
1847 DPRINTK ("%s: netdrv_set_rx_mode(%4.4x) done -- Rx config %8.8x.\n",
1848 dev->name, dev->flags, NETDRV_R32 (RxConfig));
1849
1850 /* Note: do not reorder, GCC is clever about common statements. */
1851 if (dev->flags & IFF_PROMISC) {
1da177e4
LT		 1852 rx_mode =
1853 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
1854 AcceptAllPhys;
1855 mc_filter[1] = mc_filter[0] = 0xffffffff;
1856 } else if ((dev->mc_count > multicast_filter_limit)
1857 || (dev->flags & IFF_ALLMULTI)) {
1858 /* Too many to filter perfectly -- accept all multicasts. */
1859 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1860 mc_filter[1] = mc_filter[0] = 0xffffffff;
1861 } else {
1862 struct dev_mc_list *mclist;
1863 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1864 mc_filter[1] = mc_filter[0] = 0;
1865 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1866 i++, mclist = mclist->next) {
1867 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1868
1869 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1870 }
1871 }
1872
1873 /* if called from irq handler, lock already acquired */
1874 if (!in_irq ())
1875 spin_lock_irq (&tp->lock);
1876
1877 /* We can safely update without stopping the chip. */
1878 tmp = netdrv_rx_config | rx_mode |
1879 (NETDRV_R32 (RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1880 NETDRV_W32_F (RxConfig, tmp);
1881 NETDRV_W32_F (MAR0 + 0, mc_filter[0]);
1882 NETDRV_W32_F (MAR0 + 4, mc_filter[1]);
1883
1884 if (!in_irq ())
1885 spin_unlock_irq (&tp->lock);
1886
1887 DPRINTK ("EXIT\n");
1888}
1889
1890
1891#ifdef CONFIG_PM
1892
05adc3b7 1893static int netdrv_suspend (struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 1894{
1895 struct net_device *dev = pci_get_drvdata (pdev);
1896 struct netdrv_private *tp = dev->priv;
1897 void *ioaddr = tp->mmio_addr;
1898 unsigned long flags;
1899
1900 if (!netif_running(dev))
1901 return 0;
1902 netif_device_detach (dev);
1903
1904 spin_lock_irqsave (&tp->lock, flags);
1905
1906 /* Disable interrupts, stop Tx and Rx. */
1907 NETDRV_W16 (IntrMask, 0x0000);
1908 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear));
1909
1910 /* Update the error counts. */
1911 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1912 NETDRV_W32 (RxMissed, 0);
1913
1914 spin_unlock_irqrestore (&tp->lock, flags);
1915
1916 pci_save_state (pdev);
1917 pci_set_power_state (pdev, PCI_D3hot);
1918
1919 return 0;
1920}
1921
1922
1923static int netdrv_resume (struct pci_dev *pdev)
1924{
1925 struct net_device *dev = pci_get_drvdata (pdev);
1926 struct netdrv_private *tp = dev->priv;
1927
1928 if (!netif_running(dev))
1929 return 0;
1930 pci_set_power_state (pdev, PCI_D0);
1931 pci_restore_state (pdev);
1932 netif_device_attach (dev);
1933 netdrv_hw_start (dev);
1934
1935 return 0;
1936}
1937
1938#endif /* CONFIG_PM */
1939
1940
1941static struct pci_driver netdrv_pci_driver = {
1942 .name = MODNAME,
1943 .id_table = netdrv_pci_tbl,
1944 .probe = netdrv_init_one,
1945 .remove = __devexit_p(netdrv_remove_one),
1946#ifdef CONFIG_PM
1947 .suspend = netdrv_suspend,
1948 .resume = netdrv_resume,
1949#endif /* CONFIG_PM */
1950};
1951
1952
1953static int __init netdrv_init_module (void)
1954{
1955/* when a module, this is printed whether or not devices are found in probe */
1956#ifdef MODULE
1957 printk(version);
1958#endif
29917620 1959 return pci_register_driver(&netdrv_pci_driver);
1da177e4
LT		 1960}
1961
1962
1963static void __exit netdrv_cleanup_module (void)
1964{
1965 pci_unregister_driver (&netdrv_pci_driver);
1966}
1967
1968
1969module_init(netdrv_init_module);
1970module_exit(netdrv_cleanup_module);
kernel source for telekom puls (alcatel/mediatek)