projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'master' into next
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / pch_gbe / pch_gbe_main.c
CommitLineData
77555ee7
MO		 1/*
2 * Copyright (C) 1999 - 2010 Intel Corporation.
a1dcfcb7 3 * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
77555ee7
MO		 4 *
5 * This code was derived from the Intel e1000e Linux driver.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21#include "pch_gbe.h"
22#include "pch_gbe_api.h"
23
24#define DRV_VERSION "1.00"
25const char pch_driver_version[] = DRV_VERSION;
26
27#define PCI_DEVICE_ID_INTEL_IOH1_GBE 0x8802 /* Pci device ID */
28#define PCH_GBE_MAR_ENTRIES 16
29#define PCH_GBE_SHORT_PKT 64
30#define DSC_INIT16 0xC000
31#define PCH_GBE_DMA_ALIGN 0
ac096642 32#define PCH_GBE_DMA_PADDING 2
77555ee7
MO		 33#define PCH_GBE_WATCHDOG_PERIOD (1 * HZ) /* watchdog time */
34#define PCH_GBE_COPYBREAK_DEFAULT 256
35#define PCH_GBE_PCI_BAR 1
36
b0e6baf5
T		 37/* Macros for ML7223 */
38#define PCI_VENDOR_ID_ROHM 0x10db
39#define PCI_DEVICE_ID_ROHM_ML7223_GBE 0x8013
40
77555ee7
MO		 41#define PCH_GBE_TX_WEIGHT 64
42#define PCH_GBE_RX_WEIGHT 64
43#define PCH_GBE_RX_BUFFER_WRITE 16
44
45/* Initialize the wake-on-LAN settings */
46#define PCH_GBE_WL_INIT_SETTING (PCH_GBE_WLC_MP)
47
48#define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \
49 PCH_GBE_CHIP_TYPE_INTERNAL | \
ce3dad0f 50 PCH_GBE_RGMII_MODE_RGMII \
77555ee7
MO		 51 )
52
53/* Ethertype field values */
54#define PCH_GBE_MAX_JUMBO_FRAME_SIZE 10318
55#define PCH_GBE_FRAME_SIZE_2048 2048
56#define PCH_GBE_FRAME_SIZE_4096 4096
57#define PCH_GBE_FRAME_SIZE_8192 8192
58
59#define PCH_GBE_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
60#define PCH_GBE_RX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc)
61#define PCH_GBE_TX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc)
62#define PCH_GBE_DESC_UNUSED(R) \
63 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
64 (R)->next_to_clean - (R)->next_to_use - 1)
65
66/* Pause packet value */
67#define PCH_GBE_PAUSE_PKT1_VALUE 0x00C28001
68#define PCH_GBE_PAUSE_PKT2_VALUE 0x00000100
69#define PCH_GBE_PAUSE_PKT4_VALUE 0x01000888
70#define PCH_GBE_PAUSE_PKT5_VALUE 0x0000FFFF
71
72#define PCH_GBE_ETH_ALEN 6
73
74/* This defines the bits that are set in the Interrupt Mask
75 * Set/Read Register. Each bit is documented below:
76 * o RXT0 = Receiver Timer Interrupt (ring 0)
77 * o TXDW = Transmit Descriptor Written Back
78 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
79 * o RXSEQ = Receive Sequence Error
80 * o LSC = Link Status Change
81 */
82#define PCH_GBE_INT_ENABLE_MASK ( \
83 PCH_GBE_INT_RX_DMA_CMPLT | \
84 PCH_GBE_INT_RX_DSC_EMP | \
85 PCH_GBE_INT_WOL_DET | \
86 PCH_GBE_INT_TX_CMPLT \
87 )
88
89
90static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT;
91
191cc687 92static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
93static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
94 int data);
98200ec2
TO		 95
96inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw)
97{
98 iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD);
99}
100
77555ee7
MO		 101/**
102 * pch_gbe_mac_read_mac_addr - Read MAC address
103 * @hw: Pointer to the HW structure
104 * Returns
105 * 0: Successful.
106 */
107s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
108{
109 u32 adr1a, adr1b;
110
111 adr1a = ioread32(&hw->reg->mac_adr[0].high);
112 adr1b = ioread32(&hw->reg->mac_adr[0].low);
113
114 hw->mac.addr[0] = (u8)(adr1a & 0xFF);
115 hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF);
116 hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF);
117 hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF);
118 hw->mac.addr[4] = (u8)(adr1b & 0xFF);
119 hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF);
120
121 pr_debug("hw->mac.addr : %pM\n", hw->mac.addr);
122 return 0;
123}
124
125/**
126 * pch_gbe_wait_clr_bit - Wait to clear a bit
127 * @reg: Pointer of register
128 * @busy: Busy bit
129 */
191cc687 130static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
77555ee7
MO		 131{
132 u32 tmp;
133 /* wait busy */
134 tmp = 1000;
135 while ((ioread32(reg) & bit) && --tmp)
136 cpu_relax();
137 if (!tmp)
138 pr_err("Error: busy bit is not cleared\n");
139}
140/**
141 * pch_gbe_mac_mar_set - Set MAC address register
142 * @hw: Pointer to the HW structure
143 * @addr: Pointer to the MAC address
144 * @index: MAC address array register
145 */
191cc687 146static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
77555ee7
MO		 147{
148 u32 mar_low, mar_high, adrmask;
149
150 pr_debug("index : 0x%x\n", index);
151
152 /*
153 * HW expects these in little endian so we reverse the byte order
154 * from network order (big endian) to little endian
155 */
156 mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) |
157 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
158 mar_low = ((u32) addr[4] | ((u32) addr[5] << 8));
159 /* Stop the MAC Address of index. */
160 adrmask = ioread32(&hw->reg->ADDR_MASK);
161 iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
162 /* wait busy */
163 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
164 /* Set the MAC address to the MAC address 1A/1B register */
165 iowrite32(mar_high, &hw->reg->mac_adr[index].high);
166 iowrite32(mar_low, &hw->reg->mac_adr[index].low);
167 /* Start the MAC address of index */
168 iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
169 /* wait busy */
170 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
171}
172
173/**
174 * pch_gbe_mac_reset_hw - Reset hardware
175 * @hw: Pointer to the HW structure
176 */
191cc687 177static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
77555ee7
MO		 178{
179 /* Read the MAC address. and store to the private data */
180 pch_gbe_mac_read_mac_addr(hw);
181 iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
182#ifdef PCH_GBE_MAC_IFOP_RGMII
183 iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
184#endif
185 pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
186 /* Setup the receive address */
187 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
188 return;
189}
190
191/**
192 * pch_gbe_mac_init_rx_addrs - Initialize receive address's
193 * @hw: Pointer to the HW structure
194 * @mar_count: Receive address registers
195 */
191cc687 196static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count)
77555ee7
MO		 197{
198 u32 i;
199
200 /* Setup the receive address */
201 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
202
203 /* Zero out the other receive addresses */
204 for (i = 1; i < mar_count; i++) {
205 iowrite32(0, &hw->reg->mac_adr[i].high);
206 iowrite32(0, &hw->reg->mac_adr[i].low);
207 }
208 iowrite32(0xFFFE, &hw->reg->ADDR_MASK);
209 /* wait busy */
210 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
211}
212
213
214/**
215 * pch_gbe_mac_mc_addr_list_update - Update Multicast addresses
216 * @hw: Pointer to the HW structure
217 * @mc_addr_list: Array of multicast addresses to program
218 * @mc_addr_count: Number of multicast addresses to program
219 * @mar_used_count: The first MAC Address register free to program
220 * @mar_total_num: Total number of supported MAC Address Registers
221 */
191cc687 222static void pch_gbe_mac_mc_addr_list_update(struct pch_gbe_hw *hw,
223 u8 *mc_addr_list, u32 mc_addr_count,
224 u32 mar_used_count, u32 mar_total_num)
77555ee7
MO		 225{
226 u32 i, adrmask;
227
228 /* Load the first set of multicast addresses into the exact
229 * filters (RAR). If there are not enough to fill the RAR
230 * array, clear the filters.
231 */
232 for (i = mar_used_count; i < mar_total_num; i++) {
233 if (mc_addr_count) {
234 pch_gbe_mac_mar_set(hw, mc_addr_list, i);
235 mc_addr_count--;
236 mc_addr_list += PCH_GBE_ETH_ALEN;
237 } else {
238 /* Clear MAC address mask */
239 adrmask = ioread32(&hw->reg->ADDR_MASK);
240 iowrite32((adrmask | (0x0001 << i)),
241 &hw->reg->ADDR_MASK);
242 /* wait busy */
243 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
244 /* Clear MAC address */
245 iowrite32(0, &hw->reg->mac_adr[i].high);
246 iowrite32(0, &hw->reg->mac_adr[i].low);
247 }
248 }
249}
250
251/**
252 * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
253 * @hw: Pointer to the HW structure
254 * Returns
255 * 0: Successful.
256 * Negative value: Failed.
257 */
258s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw)
259{
260 struct pch_gbe_mac_info *mac = &hw->mac;
261 u32 rx_fctrl;
262
263 pr_debug("mac->fc = %u\n", mac->fc);
264
265 rx_fctrl = ioread32(&hw->reg->RX_FCTRL);
266
267 switch (mac->fc) {
268 case PCH_GBE_FC_NONE:
269 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
270 mac->tx_fc_enable = false;
271 break;
272 case PCH_GBE_FC_RX_PAUSE:
273 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
274 mac->tx_fc_enable = false;
275 break;
276 case PCH_GBE_FC_TX_PAUSE:
277 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
278 mac->tx_fc_enable = true;
279 break;
280 case PCH_GBE_FC_FULL:
281 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
282 mac->tx_fc_enable = true;
283 break;
284 default:
285 pr_err("Flow control param set incorrectly\n");
286 return -EINVAL;
287 }
288 if (mac->link_duplex == DUPLEX_HALF)
289 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
290 iowrite32(rx_fctrl, &hw->reg->RX_FCTRL);
291 pr_debug("RX_FCTRL reg : 0x%08x mac->tx_fc_enable : %d\n",
292 ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable);
293 return 0;
294}
295
296/**
297 * pch_gbe_mac_set_wol_event - Set wake-on-lan event
298 * @hw: Pointer to the HW structure
299 * @wu_evt: Wake up event
300 */
191cc687 301static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt)
77555ee7
MO		 302{
303 u32 addr_mask;
304
305 pr_debug("wu_evt : 0x%08x ADDR_MASK reg : 0x%08x\n",
306 wu_evt, ioread32(&hw->reg->ADDR_MASK));
307
308 if (wu_evt) {
309 /* Set Wake-On-Lan address mask */
310 addr_mask = ioread32(&hw->reg->ADDR_MASK);
311 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK);
312 /* wait busy */
313 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY);
314 iowrite32(0, &hw->reg->WOL_ST);
315 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL);
316 iowrite32(0x02, &hw->reg->TCPIP_ACC);
317 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
318 } else {
319 iowrite32(0, &hw->reg->WOL_CTRL);
320 iowrite32(0, &hw->reg->WOL_ST);
321 }
322 return;
323}
324
325/**
326 * pch_gbe_mac_ctrl_miim - Control MIIM interface
327 * @hw: Pointer to the HW structure
328 * @addr: Address of PHY
329 * @dir: Operetion. (Write or Read)
330 * @reg: Access register of PHY
331 * @data: Write data.
332 *
333 * Returns: Read date.
334 */
335u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
336 u16 data)
337{
338 u32 data_out = 0;
339 unsigned int i;
340 unsigned long flags;
341
342 spin_lock_irqsave(&hw->miim_lock, flags);
343
344 for (i = 100; i; --i) {
345 if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY))
346 break;
347 udelay(20);
348 }
349 if (i == 0) {
350 pr_err("pch-gbe.miim won't go Ready\n");
351 spin_unlock_irqrestore(&hw->miim_lock, flags);
352 return 0; /* No way to indicate timeout error */
353 }
354 iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
355 (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
356 dir | data), &hw->reg->MIIM);
357 for (i = 0; i < 100; i++) {
358 udelay(20);
359 data_out = ioread32(&hw->reg->MIIM);
360 if ((data_out & PCH_GBE_MIIM_OPER_READY))
361 break;
362 }
363 spin_unlock_irqrestore(&hw->miim_lock, flags);
364
365 pr_debug("PHY %s: reg=%d, data=0x%04X\n",
366 dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg,
367 dir == PCH_GBE_MIIM_OPER_READ ? data_out : data);
368 return (u16) data_out;
369}
370
371/**
372 * pch_gbe_mac_set_pause_packet - Set pause packet
373 * @hw: Pointer to the HW structure
374 */
191cc687 375static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw)
77555ee7
MO		 376{
377 unsigned long tmp2, tmp3;
378
379 /* Set Pause packet */
380 tmp2 = hw->mac.addr[1];
381 tmp2 = (tmp2 << 8) | hw->mac.addr[0];
382 tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16);
383
384 tmp3 = hw->mac.addr[5];
385 tmp3 = (tmp3 << 8) | hw->mac.addr[4];
386 tmp3 = (tmp3 << 8) | hw->mac.addr[3];
387 tmp3 = (tmp3 << 8) | hw->mac.addr[2];
388
389 iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1);
390 iowrite32(tmp2, &hw->reg->PAUSE_PKT2);
391 iowrite32(tmp3, &hw->reg->PAUSE_PKT3);
392 iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4);
393 iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5);
394
395 /* Transmit Pause Packet */
396 iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ);
397
398 pr_debug("PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
399 ioread32(&hw->reg->PAUSE_PKT1), ioread32(&hw->reg->PAUSE_PKT2),
400 ioread32(&hw->reg->PAUSE_PKT3), ioread32(&hw->reg->PAUSE_PKT4),
401 ioread32(&hw->reg->PAUSE_PKT5));
402
403 return;
404}
405
406
407/**
408 * pch_gbe_alloc_queues - Allocate memory for all rings
409 * @adapter: Board private structure to initialize
410 * Returns
411 * 0: Successfully
412 * Negative value: Failed
413 */
414static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter)
415{
416 int size;
417
418 size = (int)sizeof(struct pch_gbe_tx_ring);
419 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
420 if (!adapter->tx_ring)
421 return -ENOMEM;
422 size = (int)sizeof(struct pch_gbe_rx_ring);
423 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
424 if (!adapter->rx_ring) {
425 kfree(adapter->tx_ring);
426 return -ENOMEM;
427 }
428 return 0;
429}
430
431/**
432 * pch_gbe_init_stats - Initialize status
433 * @adapter: Board private structure to initialize
434 */
435static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter)
436{
437 memset(&adapter->stats, 0, sizeof(adapter->stats));
438 return;
439}
440
441/**
442 * pch_gbe_init_phy - Initialize PHY
443 * @adapter: Board private structure to initialize
444 * Returns
445 * 0: Successfully
446 * Negative value: Failed
447 */
448static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter)
449{
450 struct net_device *netdev = adapter->netdev;
451 u32 addr;
452 u16 bmcr, stat;
453
454 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
455 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
456 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
457 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR);
458 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
459 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
460 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
461 break;
462 }
463 adapter->hw.phy.addr = adapter->mii.phy_id;
464 pr_debug("phy_addr = %d\n", adapter->mii.phy_id);
465 if (addr == 32)
466 return -EAGAIN;
467 /* Selected the phy and isolate the rest */
468 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
469 if (addr != adapter->mii.phy_id) {
470 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
471 BMCR_ISOLATE);
472 } else {
473 bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR);
474 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
475 bmcr & ~BMCR_ISOLATE);
476 }
477 }
478
479 /* MII setup */
480 adapter->mii.phy_id_mask = 0x1F;
481 adapter->mii.reg_num_mask = 0x1F;
482 adapter->mii.dev = adapter->netdev;
483 adapter->mii.mdio_read = pch_gbe_mdio_read;
484 adapter->mii.mdio_write = pch_gbe_mdio_write;
485 adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii);
486 return 0;
487}
488
489/**
490 * pch_gbe_mdio_read - The read function for mii
491 * @netdev: Network interface device structure
492 * @addr: Phy ID
493 * @reg: Access location
494 * Returns
495 * 0: Successfully
496 * Negative value: Failed
497 */
191cc687 498static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg)
77555ee7
MO		 499{
500 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
501 struct pch_gbe_hw *hw = &adapter->hw;
502
503 return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg,
504 (u16) 0);
505}
506
507/**
508 * pch_gbe_mdio_write - The write function for mii
509 * @netdev: Network interface device structure
510 * @addr: Phy ID (not used)
511 * @reg: Access location
512 * @data: Write data
513 */
191cc687 514static void pch_gbe_mdio_write(struct net_device *netdev,
515 int addr, int reg, int data)
77555ee7
MO		 516{
517 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
518 struct pch_gbe_hw *hw = &adapter->hw;
519
520 pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data);
521}
522
523/**
524 * pch_gbe_reset_task - Reset processing at the time of transmission timeout
525 * @work: Pointer of board private structure
526 */
527static void pch_gbe_reset_task(struct work_struct *work)
528{
529 struct pch_gbe_adapter *adapter;
530 adapter = container_of(work, struct pch_gbe_adapter, reset_task);
531
75d1a752 532 rtnl_lock();
77555ee7 533 pch_gbe_reinit_locked(adapter);
75d1a752 534 rtnl_unlock();
77555ee7
MO		 535}
536
537/**
538 * pch_gbe_reinit_locked- Re-initialization
539 * @adapter: Board private structure
540 */
541void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter)
542{
75d1a752
TO		 543 pch_gbe_down(adapter);
544 pch_gbe_up(adapter);
77555ee7
MO		 545}
546
547/**
548 * pch_gbe_reset - Reset GbE
549 * @adapter: Board private structure
550 */
551void pch_gbe_reset(struct pch_gbe_adapter *adapter)
552{
553 pch_gbe_mac_reset_hw(&adapter->hw);
554 /* Setup the receive address. */
555 pch_gbe_mac_init_rx_addrs(&adapter->hw, PCH_GBE_MAR_ENTRIES);
556 if (pch_gbe_hal_init_hw(&adapter->hw))
557 pr_err("Hardware Error\n");
558}
559
560/**
561 * pch_gbe_free_irq - Free an interrupt
562 * @adapter: Board private structure
563 */
564static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter)
565{
566 struct net_device *netdev = adapter->netdev;
567
568 free_irq(adapter->pdev->irq, netdev);
569 if (adapter->have_msi) {
570 pci_disable_msi(adapter->pdev);
571 pr_debug("call pci_disable_msi\n");
572 }
573}
574
575/**
576 * pch_gbe_irq_disable - Mask off interrupt generation on the NIC
577 * @adapter: Board private structure
578 */
579static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter)
580{
581 struct pch_gbe_hw *hw = &adapter->hw;
582
583 atomic_inc(&adapter->irq_sem);
584 iowrite32(0, &hw->reg->INT_EN);
585 ioread32(&hw->reg->INT_ST);
586 synchronize_irq(adapter->pdev->irq);
587
588 pr_debug("INT_EN reg : 0x%08x\n", ioread32(&hw->reg->INT_EN));
589}
590
591/**
592 * pch_gbe_irq_enable - Enable default interrupt generation settings
593 * @adapter: Board private structure
594 */
595static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter)
596{
597 struct pch_gbe_hw *hw = &adapter->hw;
598
599 if (likely(atomic_dec_and_test(&adapter->irq_sem)))
600 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
601 ioread32(&hw->reg->INT_ST);
602 pr_debug("INT_EN reg : 0x%08x\n", ioread32(&hw->reg->INT_EN));
603}
604
605
606
607/**
608 * pch_gbe_setup_tctl - configure the Transmit control registers
609 * @adapter: Board private structure
610 */
611static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter)
612{
613 struct pch_gbe_hw *hw = &adapter->hw;
614 u32 tx_mode, tcpip;
615
616 tx_mode = PCH_GBE_TM_LONG_PKT |
617 PCH_GBE_TM_ST_AND_FD |
618 PCH_GBE_TM_SHORT_PKT |
619 PCH_GBE_TM_TH_TX_STRT_8 |
620 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8;
621
622 iowrite32(tx_mode, &hw->reg->TX_MODE);
623
624 tcpip = ioread32(&hw->reg->TCPIP_ACC);
625 tcpip |= PCH_GBE_TX_TCPIPACC_EN;
626 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
627 return;
628}
629
630/**
631 * pch_gbe_configure_tx - Configure Transmit Unit after Reset
632 * @adapter: Board private structure
633 */
634static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
635{
636 struct pch_gbe_hw *hw = &adapter->hw;
637 u32 tdba, tdlen, dctrl;
638
639 pr_debug("dma addr = 0x%08llx size = 0x%08x\n",
640 (unsigned long long)adapter->tx_ring->dma,
641 adapter->tx_ring->size);
642
643 /* Setup the HW Tx Head and Tail descriptor pointers */
644 tdba = adapter->tx_ring->dma;
645 tdlen = adapter->tx_ring->size - 0x10;
646 iowrite32(tdba, &hw->reg->TX_DSC_BASE);
647 iowrite32(tdlen, &hw->reg->TX_DSC_SIZE);
648 iowrite32(tdba, &hw->reg->TX_DSC_SW_P);
649
650 /* Enables Transmission DMA */
651 dctrl = ioread32(&hw->reg->DMA_CTRL);
652 dctrl |= PCH_GBE_TX_DMA_EN;
653 iowrite32(dctrl, &hw->reg->DMA_CTRL);
654}
655
656/**
657 * pch_gbe_setup_rctl - Configure the receive control registers
658 * @adapter: Board private structure
659 */
660static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter)
661{
662 struct pch_gbe_hw *hw = &adapter->hw;
663 u32 rx_mode, tcpip;
664
665 rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN |
666 PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8;
667
668 iowrite32(rx_mode, &hw->reg->RX_MODE);
669
670 tcpip = ioread32(&hw->reg->TCPIP_ACC);
671
672 if (adapter->rx_csum) {
673 tcpip &= ~PCH_GBE_RX_TCPIPACC_OFF;
674 tcpip |= PCH_GBE_RX_TCPIPACC_EN;
675 } else {
676 tcpip |= PCH_GBE_RX_TCPIPACC_OFF;
677 tcpip &= ~PCH_GBE_RX_TCPIPACC_EN;
678 }
679 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
680 return;
681}
682
683/**
684 * pch_gbe_configure_rx - Configure Receive Unit after Reset
685 * @adapter: Board private structure
686 */
687static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
688{
689 struct pch_gbe_hw *hw = &adapter->hw;
690 u32 rdba, rdlen, rctl, rxdma;
691
692 pr_debug("dma adr = 0x%08llx size = 0x%08x\n",
693 (unsigned long long)adapter->rx_ring->dma,
694 adapter->rx_ring->size);
695
696 pch_gbe_mac_force_mac_fc(hw);
697
698 /* Disables Receive MAC */
699 rctl = ioread32(&hw->reg->MAC_RX_EN);
700 iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
701
702 /* Disables Receive DMA */
703 rxdma = ioread32(&hw->reg->DMA_CTRL);
704 rxdma &= ~PCH_GBE_RX_DMA_EN;
705 iowrite32(rxdma, &hw->reg->DMA_CTRL);
706
707 pr_debug("MAC_RX_EN reg = 0x%08x DMA_CTRL reg = 0x%08x\n",
708 ioread32(&hw->reg->MAC_RX_EN),
709 ioread32(&hw->reg->DMA_CTRL));
710
711 /* Setup the HW Rx Head and Tail Descriptor Pointers and
712 * the Base and Length of the Rx Descriptor Ring */
713 rdba = adapter->rx_ring->dma;
714 rdlen = adapter->rx_ring->size - 0x10;
715 iowrite32(rdba, &hw->reg->RX_DSC_BASE);
716 iowrite32(rdlen, &hw->reg->RX_DSC_SIZE);
717 iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P);
718
719 /* Enables Receive DMA */
720 rxdma = ioread32(&hw->reg->DMA_CTRL);
721 rxdma |= PCH_GBE_RX_DMA_EN;
722 iowrite32(rxdma, &hw->reg->DMA_CTRL);
723 /* Enables Receive */
724 iowrite32(PCH_GBE_MRE_MAC_RX_EN, &hw->reg->MAC_RX_EN);
725}
726
727/**
728 * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer
729 * @adapter: Board private structure
730 * @buffer_info: Buffer information structure
731 */
732static void pch_gbe_unmap_and_free_tx_resource(
733 struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info)
734{
735 if (buffer_info->mapped) {
736 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
737 buffer_info->length, DMA_TO_DEVICE);
738 buffer_info->mapped = false;
739 }
740 if (buffer_info->skb) {
741 dev_kfree_skb_any(buffer_info->skb);
742 buffer_info->skb = NULL;
743 }
744}
745
746/**
747 * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer
748 * @adapter: Board private structure
749 * @buffer_info: Buffer information structure
750 */
751static void pch_gbe_unmap_and_free_rx_resource(
752 struct pch_gbe_adapter *adapter,
753 struct pch_gbe_buffer *buffer_info)
754{
755 if (buffer_info->mapped) {
756 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
757 buffer_info->length, DMA_FROM_DEVICE);
758 buffer_info->mapped = false;
759 }
760 if (buffer_info->skb) {
761 dev_kfree_skb_any(buffer_info->skb);
762 buffer_info->skb = NULL;
763 }
764}
765
766/**
767 * pch_gbe_clean_tx_ring - Free Tx Buffers
768 * @adapter: Board private structure
769 * @tx_ring: Ring to be cleaned
770 */
771static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter,
772 struct pch_gbe_tx_ring *tx_ring)
773{
774 struct pch_gbe_hw *hw = &adapter->hw;
775 struct pch_gbe_buffer *buffer_info;
776 unsigned long size;
777 unsigned int i;
778
779 /* Free all the Tx ring sk_buffs */
780 for (i = 0; i < tx_ring->count; i++) {
781 buffer_info = &tx_ring->buffer_info[i];
782 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info);
783 }
784 pr_debug("call pch_gbe_unmap_and_free_tx_resource() %d count\n", i);
785
786 size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count;
787 memset(tx_ring->buffer_info, 0, size);
788
789 /* Zero out the descriptor ring */
790 memset(tx_ring->desc, 0, tx_ring->size);
791 tx_ring->next_to_use = 0;
792 tx_ring->next_to_clean = 0;
793 iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P);
794 iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE);
795}
796
797/**
798 * pch_gbe_clean_rx_ring - Free Rx Buffers
799 * @adapter: Board private structure
800 * @rx_ring: Ring to free buffers from
801 */
802static void
803pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter,
804 struct pch_gbe_rx_ring *rx_ring)
805{
806 struct pch_gbe_hw *hw = &adapter->hw;
807 struct pch_gbe_buffer *buffer_info;
808 unsigned long size;
809 unsigned int i;
810
811 /* Free all the Rx ring sk_buffs */
812 for (i = 0; i < rx_ring->count; i++) {
813 buffer_info = &rx_ring->buffer_info[i];
814 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info);
815 }
816 pr_debug("call pch_gbe_unmap_and_free_rx_resource() %d count\n", i);
817 size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count;
818 memset(rx_ring->buffer_info, 0, size);
819
820 /* Zero out the descriptor ring */
821 memset(rx_ring->desc, 0, rx_ring->size);
822 rx_ring->next_to_clean = 0;
823 rx_ring->next_to_use = 0;
824 iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P);
825 iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE);
826}
827
828static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed,
829 u16 duplex)
830{
831 struct pch_gbe_hw *hw = &adapter->hw;
832 unsigned long rgmii = 0;
833
834 /* Set the RGMII control. */
835#ifdef PCH_GBE_MAC_IFOP_RGMII
836 switch (speed) {
837 case SPEED_10:
838 rgmii = (PCH_GBE_RGMII_RATE_2_5M |
839 PCH_GBE_MAC_RGMII_CTRL_SETTING);
840 break;
841 case SPEED_100:
842 rgmii = (PCH_GBE_RGMII_RATE_25M |
843 PCH_GBE_MAC_RGMII_CTRL_SETTING);
844 break;
845 case SPEED_1000:
846 rgmii = (PCH_GBE_RGMII_RATE_125M |
847 PCH_GBE_MAC_RGMII_CTRL_SETTING);
848 break;
849 }
850 iowrite32(rgmii, &hw->reg->RGMII_CTRL);
851#else /* GMII */
852 rgmii = 0;
853 iowrite32(rgmii, &hw->reg->RGMII_CTRL);
854#endif
855}
856static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed,
857 u16 duplex)
858{
859 struct net_device *netdev = adapter->netdev;
860 struct pch_gbe_hw *hw = &adapter->hw;
861 unsigned long mode = 0;
862
863 /* Set the communication mode */
864 switch (speed) {
865 case SPEED_10:
866 mode = PCH_GBE_MODE_MII_ETHER;
867 netdev->tx_queue_len = 10;
868 break;
869 case SPEED_100:
870 mode = PCH_GBE_MODE_MII_ETHER;
871 netdev->tx_queue_len = 100;
872 break;
873 case SPEED_1000:
874 mode = PCH_GBE_MODE_GMII_ETHER;
875 break;
876 }
877 if (duplex == DUPLEX_FULL)
878 mode |= PCH_GBE_MODE_FULL_DUPLEX;
879 else
880 mode |= PCH_GBE_MODE_HALF_DUPLEX;
881 iowrite32(mode, &hw->reg->MODE);
882}
883
884/**
885 * pch_gbe_watchdog - Watchdog process
886 * @data: Board private structure
887 */
888static void pch_gbe_watchdog(unsigned long data)
889{
890 struct pch_gbe_adapter *adapter = (struct pch_gbe_adapter *)data;
891 struct net_device *netdev = adapter->netdev;
892 struct pch_gbe_hw *hw = &adapter->hw;
893 struct ethtool_cmd cmd;
894
895 pr_debug("right now = %ld\n", jiffies);
896
897 pch_gbe_update_stats(adapter);
898 if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) {
899 netdev->tx_queue_len = adapter->tx_queue_len;
900 /* mii library handles link maintenance tasks */
901 if (mii_ethtool_gset(&adapter->mii, &cmd)) {
902 pr_err("ethtool get setting Error\n");
903 mod_timer(&adapter->watchdog_timer,
904 round_jiffies(jiffies +
905 PCH_GBE_WATCHDOG_PERIOD));
906 return;
907 }
908 hw->mac.link_speed = cmd.speed;
909 hw->mac.link_duplex = cmd.duplex;
910 /* Set the RGMII control. */
911 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
912 hw->mac.link_duplex);
913 /* Set the communication mode */
914 pch_gbe_set_mode(adapter, hw->mac.link_speed,
915 hw->mac.link_duplex);
916 netdev_dbg(netdev,
917 "Link is Up %d Mbps %s-Duplex\n",
918 cmd.speed,
919 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
920 netif_carrier_on(netdev);
921 netif_wake_queue(netdev);
922 } else if ((!mii_link_ok(&adapter->mii)) &&
923 (netif_carrier_ok(netdev))) {
924 netdev_dbg(netdev, "NIC Link is Down\n");
925 hw->mac.link_speed = SPEED_10;
926 hw->mac.link_duplex = DUPLEX_HALF;
927 netif_carrier_off(netdev);
928 netif_stop_queue(netdev);
929 }
930 mod_timer(&adapter->watchdog_timer,
931 round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD));
932}
933
934/**
935 * pch_gbe_tx_queue - Carry out queuing of the transmission data
936 * @adapter: Board private structure
937 * @tx_ring: Tx descriptor ring structure
938 * @skb: Sockt buffer structure
939 */
940static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter,
941 struct pch_gbe_tx_ring *tx_ring,
942 struct sk_buff *skb)
943{
944 struct pch_gbe_hw *hw = &adapter->hw;
945 struct pch_gbe_tx_desc *tx_desc;
946 struct pch_gbe_buffer *buffer_info;
947 struct sk_buff *tmp_skb;
948 unsigned int frame_ctrl;
949 unsigned int ring_num;
950 unsigned long flags;
951
952 /*-- Set frame control --*/
953 frame_ctrl = 0;
954 if (unlikely(skb->len < PCH_GBE_SHORT_PKT))
955 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
956 if (unlikely(!adapter->tx_csum))
957 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
958
959 /* Performs checksum processing */
960 /*
961 * It is because the hardware accelerator does not support a checksum,
962 * when the received data size is less than 64 bytes.
963 */
964 if ((skb->len < PCH_GBE_SHORT_PKT) && (adapter->tx_csum)) {
965 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD |
966 PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
967 if (skb->protocol == htons(ETH_P_IP)) {
968 struct iphdr *iph = ip_hdr(skb);
969 unsigned int offset;
970 iph->check = 0;
971 iph->check = ip_fast_csum((u8 *) iph, iph->ihl);
972 offset = skb_transport_offset(skb);
973 if (iph->protocol == IPPROTO_TCP) {
974 skb->csum = 0;
975 tcp_hdr(skb)->check = 0;
976 skb->csum = skb_checksum(skb, offset,
977 skb->len - offset, 0);
978 tcp_hdr(skb)->check =
979 csum_tcpudp_magic(iph->saddr,
980 iph->daddr,
981 skb->len - offset,
982 IPPROTO_TCP,
983 skb->csum);
984 } else if (iph->protocol == IPPROTO_UDP) {
985 skb->csum = 0;
986 udp_hdr(skb)->check = 0;
987 skb->csum =
988 skb_checksum(skb, offset,
989 skb->len - offset, 0);
990 udp_hdr(skb)->check =
991 csum_tcpudp_magic(iph->saddr,
992 iph->daddr,
993 skb->len - offset,
994 IPPROTO_UDP,
995 skb->csum);
996 }
997 }
998 }
999 spin_lock_irqsave(&tx_ring->tx_lock, flags);
1000 ring_num = tx_ring->next_to_use;
1001 if (unlikely((ring_num + 1) == tx_ring->count))
1002 tx_ring->next_to_use = 0;
1003 else
1004 tx_ring->next_to_use = ring_num + 1;
1005
1006 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1007 buffer_info = &tx_ring->buffer_info[ring_num];
1008 tmp_skb = buffer_info->skb;
1009
1010 /* [Header:14][payload] ---> [Header:14][paddong:2][payload] */
1011 memcpy(tmp_skb->data, skb->data, ETH_HLEN);
1012 tmp_skb->data[ETH_HLEN] = 0x00;
1013 tmp_skb->data[ETH_HLEN + 1] = 0x00;
1014 tmp_skb->len = skb->len;
1015 memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN],
1016 (skb->len - ETH_HLEN));
25985edc 1017 /*-- Set Buffer information --*/
77555ee7
MO		 1018 buffer_info->length = tmp_skb->len;
1019 buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data,
1020 buffer_info->length,
1021 DMA_TO_DEVICE);
1022 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1023 pr_err("TX DMA map failed\n");
1024 buffer_info->dma = 0;
1025 buffer_info->time_stamp = 0;
1026 tx_ring->next_to_use = ring_num;
1027 return;
1028 }
1029 buffer_info->mapped = true;
1030 buffer_info->time_stamp = jiffies;
1031
1032 /*-- Set Tx descriptor --*/
1033 tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
1034 tx_desc->buffer_addr = (buffer_info->dma);
1035 tx_desc->length = (tmp_skb->len);
1036 tx_desc->tx_words_eob = ((tmp_skb->len + 3));
1037 tx_desc->tx_frame_ctrl = (frame_ctrl);
1038 tx_desc->gbec_status = (DSC_INIT16);
1039
1040 if (unlikely(++ring_num == tx_ring->count))
1041 ring_num = 0;
1042
1043 /* Update software pointer of TX descriptor */
1044 iowrite32(tx_ring->dma +
1045 (int)sizeof(struct pch_gbe_tx_desc) * ring_num,
1046 &hw->reg->TX_DSC_SW_P);
1047 dev_kfree_skb_any(skb);
1048}
1049
1050/**
1051 * pch_gbe_update_stats - Update the board statistics counters
1052 * @adapter: Board private structure
1053 */
1054void pch_gbe_update_stats(struct pch_gbe_adapter *adapter)
1055{
1056 struct net_device *netdev = adapter->netdev;
1057 struct pci_dev *pdev = adapter->pdev;
1058 struct pch_gbe_hw_stats *stats = &adapter->stats;
1059 unsigned long flags;
1060
1061 /*
1062 * Prevent stats update while adapter is being reset, or if the pci
1063 * connection is down.
1064 */
1065 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1066 return;
1067
1068 spin_lock_irqsave(&adapter->stats_lock, flags);
1069
1070 /* Update device status "adapter->stats" */
1071 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors;
1072 stats->tx_errors = stats->tx_length_errors +
1073 stats->tx_aborted_errors +
1074 stats->tx_carrier_errors + stats->tx_timeout_count;
1075
1076 /* Update network device status "adapter->net_stats" */
1077 netdev->stats.rx_packets = stats->rx_packets;
1078 netdev->stats.rx_bytes = stats->rx_bytes;
1079 netdev->stats.rx_dropped = stats->rx_dropped;
1080 netdev->stats.tx_packets = stats->tx_packets;
1081 netdev->stats.tx_bytes = stats->tx_bytes;
1082 netdev->stats.tx_dropped = stats->tx_dropped;
1083 /* Fill out the OS statistics structure */
1084 netdev->stats.multicast = stats->multicast;
1085 netdev->stats.collisions = stats->collisions;
1086 /* Rx Errors */
1087 netdev->stats.rx_errors = stats->rx_errors;
1088 netdev->stats.rx_crc_errors = stats->rx_crc_errors;
1089 netdev->stats.rx_frame_errors = stats->rx_frame_errors;
1090 /* Tx Errors */
1091 netdev->stats.tx_errors = stats->tx_errors;
1092 netdev->stats.tx_aborted_errors = stats->tx_aborted_errors;
1093 netdev->stats.tx_carrier_errors = stats->tx_carrier_errors;
1094
1095 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1096}
1097
1098/**
1099 * pch_gbe_intr - Interrupt Handler
1100 * @irq: Interrupt number
1101 * @data: Pointer to a network interface device structure
1102 * Returns
1103 * - IRQ_HANDLED: Our interrupt
1104 * - IRQ_NONE: Not our interrupt
1105 */
1106static irqreturn_t pch_gbe_intr(int irq, void *data)
1107{
1108 struct net_device *netdev = data;
1109 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1110 struct pch_gbe_hw *hw = &adapter->hw;
1111 u32 int_st;
1112 u32 int_en;
1113
1114 /* Check request status */
1115 int_st = ioread32(&hw->reg->INT_ST);
1116 int_st = int_st & ioread32(&hw->reg->INT_EN);
1117 /* When request status is no interruption factor */
1118 if (unlikely(!int_st))
1119 return IRQ_NONE; /* Not our interrupt. End processing. */
1120 pr_debug("%s occur int_st = 0x%08x\n", __func__, int_st);
1121 if (int_st & PCH_GBE_INT_RX_FRAME_ERR)
1122 adapter->stats.intr_rx_frame_err_count++;
1123 if (int_st & PCH_GBE_INT_RX_FIFO_ERR)
1124 adapter->stats.intr_rx_fifo_err_count++;
1125 if (int_st & PCH_GBE_INT_RX_DMA_ERR)
1126 adapter->stats.intr_rx_dma_err_count++;
1127 if (int_st & PCH_GBE_INT_TX_FIFO_ERR)
1128 adapter->stats.intr_tx_fifo_err_count++;
1129 if (int_st & PCH_GBE_INT_TX_DMA_ERR)
1130 adapter->stats.intr_tx_dma_err_count++;
1131 if (int_st & PCH_GBE_INT_TCPIP_ERR)
1132 adapter->stats.intr_tcpip_err_count++;
1133 /* When Rx descriptor is empty */
1134 if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) {
1135 adapter->stats.intr_rx_dsc_empty_count++;
1136 pr_err("Rx descriptor is empty\n");
1137 int_en = ioread32(&hw->reg->INT_EN);
1138 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN);
1139 if (hw->mac.tx_fc_enable) {
1140 /* Set Pause packet */
1141 pch_gbe_mac_set_pause_packet(hw);
1142 }
1143 if ((int_en & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT))
1144 == 0) {
1145 return IRQ_HANDLED;
1146 }
1147 }
1148
1149 /* When request status is Receive interruption */
1150 if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT))) {
1151 if (likely(napi_schedule_prep(&adapter->napi))) {
1152 /* Enable only Rx Descriptor empty */
1153 atomic_inc(&adapter->irq_sem);
1154 int_en = ioread32(&hw->reg->INT_EN);
1155 int_en &=
1156 ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT);
1157 iowrite32(int_en, &hw->reg->INT_EN);
1158 /* Start polling for NAPI */
1159 __napi_schedule(&adapter->napi);
1160 }
1161 }
1162 pr_debug("return = 0x%08x INT_EN reg = 0x%08x\n",
1163 IRQ_HANDLED, ioread32(&hw->reg->INT_EN));
1164 return IRQ_HANDLED;
1165}
1166
1167/**
1168 * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1169 * @adapter: Board private structure
1170 * @rx_ring: Rx descriptor ring
1171 * @cleaned_count: Cleaned count
1172 */
1173static void
1174pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter,
1175 struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1176{
1177 struct net_device *netdev = adapter->netdev;
1178 struct pci_dev *pdev = adapter->pdev;
1179 struct pch_gbe_hw *hw = &adapter->hw;
1180 struct pch_gbe_rx_desc *rx_desc;
1181 struct pch_gbe_buffer *buffer_info;
1182 struct sk_buff *skb;
1183 unsigned int i;
1184 unsigned int bufsz;
1185
1186 bufsz = adapter->rx_buffer_len + PCH_GBE_DMA_ALIGN;
1187 i = rx_ring->next_to_use;
1188
1189 while ((cleaned_count--)) {
1190 buffer_info = &rx_ring->buffer_info[i];
1191 skb = buffer_info->skb;
1192 if (skb) {
1193 skb_trim(skb, 0);
1194 } else {
1195 skb = netdev_alloc_skb(netdev, bufsz);
1196 if (unlikely(!skb)) {
1197 /* Better luck next round */
1198 adapter->stats.rx_alloc_buff_failed++;
1199 break;
1200 }
1201 /* 64byte align */
1202 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1203
1204 buffer_info->skb = skb;
1205 buffer_info->length = adapter->rx_buffer_len;
1206 }
1207 buffer_info->dma = dma_map_single(&pdev->dev,
1208 skb->data,
1209 buffer_info->length,
1210 DMA_FROM_DEVICE);
1211 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1212 dev_kfree_skb(skb);
1213 buffer_info->skb = NULL;
1214 buffer_info->dma = 0;
1215 adapter->stats.rx_alloc_buff_failed++;
1216 break; /* while !buffer_info->skb */
1217 }
1218 buffer_info->mapped = true;
1219 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1220 rx_desc->buffer_addr = (buffer_info->dma);
1221 rx_desc->gbec_status = DSC_INIT16;
1222
1223 pr_debug("i = %d buffer_info->dma = 0x08%llx buffer_info->length = 0x%x\n",
1224 i, (unsigned long long)buffer_info->dma,
1225 buffer_info->length);
1226
1227 if (unlikely(++i == rx_ring->count))
1228 i = 0;
1229 }
1230 if (likely(rx_ring->next_to_use != i)) {
1231 rx_ring->next_to_use = i;
1232 if (unlikely(i-- == 0))
1233 i = (rx_ring->count - 1);
1234 iowrite32(rx_ring->dma +
1235 (int)sizeof(struct pch_gbe_rx_desc) * i,
1236 &hw->reg->RX_DSC_SW_P);
1237 }
1238 return;
1239}
1240
1241/**
1242 * pch_gbe_alloc_tx_buffers - Allocate transmit buffers
1243 * @adapter: Board private structure
1244 * @tx_ring: Tx descriptor ring
1245 */
1246static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter,
1247 struct pch_gbe_tx_ring *tx_ring)
1248{
1249 struct pch_gbe_buffer *buffer_info;
1250 struct sk_buff *skb;
1251 unsigned int i;
1252 unsigned int bufsz;
1253 struct pch_gbe_tx_desc *tx_desc;
1254
1255 bufsz =
1256 adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN;
1257
1258 for (i = 0; i < tx_ring->count; i++) {
1259 buffer_info = &tx_ring->buffer_info[i];
1260 skb = netdev_alloc_skb(adapter->netdev, bufsz);
1261 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1262 buffer_info->skb = skb;
1263 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1264 tx_desc->gbec_status = (DSC_INIT16);
1265 }
1266 return;
1267}
1268
1269/**
1270 * pch_gbe_clean_tx - Reclaim resources after transmit completes
1271 * @adapter: Board private structure
1272 * @tx_ring: Tx descriptor ring
1273 * Returns
1274 * true: Cleaned the descriptor
1275 * false: Not cleaned the descriptor
1276 */
1277static bool
1278pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
1279 struct pch_gbe_tx_ring *tx_ring)
1280{
1281 struct pch_gbe_tx_desc *tx_desc;
1282 struct pch_gbe_buffer *buffer_info;
1283 struct sk_buff *skb;
1284 unsigned int i;
1285 unsigned int cleaned_count = 0;
1286 bool cleaned = false;
1287
1288 pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean);
1289
1290 i = tx_ring->next_to_clean;
1291 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1292 pr_debug("gbec_status:0x%04x dma_status:0x%04x\n",
1293 tx_desc->gbec_status, tx_desc->dma_status);
1294
1295 while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
1296 pr_debug("gbec_status:0x%04x\n", tx_desc->gbec_status);
1297 cleaned = true;
1298 buffer_info = &tx_ring->buffer_info[i];
1299 skb = buffer_info->skb;
1300
1301 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) {
1302 adapter->stats.tx_aborted_errors++;
1303 pr_err("Transfer Abort Error\n");
1304 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER)
1305 ) {
1306 adapter->stats.tx_carrier_errors++;
1307 pr_err("Transfer Carrier Sense Error\n");
1308 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL)
1309 ) {
1310 adapter->stats.tx_aborted_errors++;
1311 pr_err("Transfer Collision Abort Error\n");
1312 } else if ((tx_desc->gbec_status &
1313 (PCH_GBE_TXD_GMAC_STAT_SNGCOL |
1314 PCH_GBE_TXD_GMAC_STAT_MLTCOL))) {
1315 adapter->stats.collisions++;
1316 adapter->stats.tx_packets++;
1317 adapter->stats.tx_bytes += skb->len;
1318 pr_debug("Transfer Collision\n");
1319 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT)
1320 ) {
1321 adapter->stats.tx_packets++;
1322 adapter->stats.tx_bytes += skb->len;
1323 }
1324 if (buffer_info->mapped) {
1325 pr_debug("unmap buffer_info->dma : %d\n", i);
1326 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1327 buffer_info->length, DMA_TO_DEVICE);
1328 buffer_info->mapped = false;
1329 }
1330 if (buffer_info->skb) {
1331 pr_debug("trim buffer_info->skb : %d\n", i);
1332 skb_trim(buffer_info->skb, 0);
1333 }
1334 tx_desc->gbec_status = DSC_INIT16;
1335 if (unlikely(++i == tx_ring->count))
1336 i = 0;
1337 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1338
1339 /* weight of a sort for tx, to avoid endless transmit cleanup */
1340 if (cleaned_count++ == PCH_GBE_TX_WEIGHT)
1341 break;
1342 }
1343 pr_debug("called pch_gbe_unmap_and_free_tx_resource() %d count\n",
1344 cleaned_count);
1345 /* Recover from running out of Tx resources in xmit_frame */
1346 if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev)))) {
1347 netif_wake_queue(adapter->netdev);
1348 adapter->stats.tx_restart_count++;
1349 pr_debug("Tx wake queue\n");
1350 }
1351 spin_lock(&adapter->tx_queue_lock);
1352 tx_ring->next_to_clean = i;
1353 spin_unlock(&adapter->tx_queue_lock);
1354 pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean);
1355 return cleaned;
1356}
1357
1358/**
1359 * pch_gbe_clean_rx - Send received data up the network stack; legacy
1360 * @adapter: Board private structure
1361 * @rx_ring: Rx descriptor ring
1362 * @work_done: Completed count
1363 * @work_to_do: Request count
1364 * Returns
1365 * true: Cleaned the descriptor
1366 * false: Not cleaned the descriptor
1367 */
1368static bool
1369pch_gbe_clean_rx(struct pch_gbe_adapter *adapter,
1370 struct pch_gbe_rx_ring *rx_ring,
1371 int *work_done, int work_to_do)
1372{
1373 struct net_device *netdev = adapter->netdev;
1374 struct pci_dev *pdev = adapter->pdev;
1375 struct pch_gbe_buffer *buffer_info;
1376 struct pch_gbe_rx_desc *rx_desc;
1377 u32 length;
77555ee7
MO		 1378 unsigned int i;
1379 unsigned int cleaned_count = 0;
1380 bool cleaned = false;
ac096642 1381 struct sk_buff *skb, *new_skb;
77555ee7
MO		 1382 u8 dma_status;
1383 u16 gbec_status;
1384 u32 tcp_ip_status;
77555ee7
MO		 1385
1386 i = rx_ring->next_to_clean;
1387
1388 while (*work_done < work_to_do) {
1389 /* Check Rx descriptor status */
1390 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1391 if (rx_desc->gbec_status == DSC_INIT16)
1392 break;
1393 cleaned = true;
1394 cleaned_count++;
1395
1396 dma_status = rx_desc->dma_status;
1397 gbec_status = rx_desc->gbec_status;
1398 tcp_ip_status = rx_desc->tcp_ip_status;
1399 rx_desc->gbec_status = DSC_INIT16;
1400 buffer_info = &rx_ring->buffer_info[i];
1401 skb = buffer_info->skb;
1402
1403 /* unmap dma */
1404 dma_unmap_single(&pdev->dev, buffer_info->dma,
1405 buffer_info->length, DMA_FROM_DEVICE);
1406 buffer_info->mapped = false;
1407 /* Prefetch the packet */
1408 prefetch(skb->data);
1409
1410 pr_debug("RxDecNo = 0x%04x Status[DMA:0x%02x GBE:0x%04x "
1411 "TCP:0x%08x] BufInf = 0x%p\n",
1412 i, dma_status, gbec_status, tcp_ip_status,
1413 buffer_info);
1414 /* Error check */
1415 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) {
1416 adapter->stats.rx_frame_errors++;
1417 pr_err("Receive Not Octal Error\n");
1418 } else if (unlikely(gbec_status &
1419 PCH_GBE_RXD_GMAC_STAT_NBLERR)) {
1420 adapter->stats.rx_frame_errors++;
1421 pr_err("Receive Nibble Error\n");
1422 } else if (unlikely(gbec_status &
1423 PCH_GBE_RXD_GMAC_STAT_CRCERR)) {
1424 adapter->stats.rx_crc_errors++;
1425 pr_err("Receive CRC Error\n");
1426 } else {
1427 /* get receive length */
ac096642
TO		 1428 /* length convert[-3] */
1429 length = (rx_desc->rx_words_eob) - 3;
77555ee7
MO		 1430
1431 /* Decide the data conversion method */
1432 if (!adapter->rx_csum) {
1433 /* [Header:14][payload] */
ac096642
TO		 1434 if (NET_IP_ALIGN) {
1435 /* Because alignment differs,
1436 * the new_skb is newly allocated,
1437 * and data is copied to new_skb.*/
1438 new_skb = netdev_alloc_skb(netdev,
1439 length + NET_IP_ALIGN);
1440 if (!new_skb) {
1441 /* dorrop error */
1442 pr_err("New skb allocation "
1443 "Error\n");
1444 goto dorrop;
1445 }
1446 skb_reserve(new_skb, NET_IP_ALIGN);
1447 memcpy(new_skb->data, skb->data,
1448 length);
1449 skb = new_skb;
1450 } else {
1451 /* DMA buffer is used as SKB as it is.*/
1452 buffer_info->skb = NULL;
1453 }
77555ee7
MO		 1454 } else {
1455 /* [Header:14][padding:2][payload] */
ac096642
TO		 1456 /* The length includes padding length */
1457 length = length - PCH_GBE_DMA_PADDING;
1458 if ((length < copybreak) ||
1459 (NET_IP_ALIGN != PCH_GBE_DMA_PADDING)) {
1460 /* Because alignment differs,
1461 * the new_skb is newly allocated,
1462 * and data is copied to new_skb.
1463 * Padding data is deleted
1464 * at the time of a copy.*/
1465 new_skb = netdev_alloc_skb(netdev,
1466 length + NET_IP_ALIGN);
1467 if (!new_skb) {
1468 /* dorrop error */
1469 pr_err("New skb allocation "
1470 "Error\n");
1471 goto dorrop;
77555ee7 1472 }
ac096642 1473 skb_reserve(new_skb, NET_IP_ALIGN);
77555ee7 1474 memcpy(new_skb->data, skb->data,
ac096642
TO		 1475 ETH_HLEN);
1476 memcpy(&new_skb->data[ETH_HLEN],
1477 &skb->data[ETH_HLEN +
1478 PCH_GBE_DMA_PADDING],
1479 length - ETH_HLEN);
77555ee7 1480 skb = new_skb;
ac096642
TO		 1481 } else {
1482 /* Padding data is deleted
1483 * by moving header data.*/
1484 memmove(&skb->data[PCH_GBE_DMA_PADDING],
1485 &skb->data[0], ETH_HLEN);
1486 skb_reserve(skb, NET_IP_ALIGN);
1487 buffer_info->skb = NULL;
77555ee7 1488 }
77555ee7 1489 }
ac096642
TO		 1490 /* The length includes FCS length */
1491 length = length - ETH_FCS_LEN;
77555ee7
MO		 1492 /* update status of driver */
1493 adapter->stats.rx_bytes += length;
1494 adapter->stats.rx_packets++;
1495 if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT))
1496 adapter->stats.multicast++;
1497 /* Write meta date of skb */
1498 skb_put(skb, length);
1499 skb->protocol = eth_type_trans(skb, netdev);
5d05a04d 1500 if (tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK)
77555ee7 1501 skb->ip_summed = CHECKSUM_NONE;
5d05a04d
TO		 1502 else
1503 skb->ip_summed = CHECKSUM_UNNECESSARY;
1504
77555ee7
MO		 1505 napi_gro_receive(&adapter->napi, skb);
1506 (*work_done)++;
1507 pr_debug("Receive skb->ip_summed: %d length: %d\n",
1508 skb->ip_summed, length);
1509 }
1510dorrop:
1511 /* return some buffers to hardware, one at a time is too slow */
1512 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) {
1513 pch_gbe_alloc_rx_buffers(adapter, rx_ring,
1514 cleaned_count);
1515 cleaned_count = 0;
1516 }
1517 if (++i == rx_ring->count)
1518 i = 0;
1519 }
1520 rx_ring->next_to_clean = i;
1521 if (cleaned_count)
1522 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1523 return cleaned;
1524}
1525
1526/**
1527 * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors)
1528 * @adapter: Board private structure
1529 * @tx_ring: Tx descriptor ring (for a specific queue) to setup
1530 * Returns
1531 * 0: Successfully
1532 * Negative value: Failed
1533 */
1534int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
1535 struct pch_gbe_tx_ring *tx_ring)
1536{
1537 struct pci_dev *pdev = adapter->pdev;
1538 struct pch_gbe_tx_desc *tx_desc;
1539 int size;
1540 int desNo;
1541
1542 size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count;
89bf67f1 1543 tx_ring->buffer_info = vzalloc(size);
77555ee7 1544 if (!tx_ring->buffer_info) {
25985edc 1545 pr_err("Unable to allocate memory for the buffer information\n");
77555ee7
MO		 1546 return -ENOMEM;
1547 }
77555ee7
MO		 1548
1549 tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc);
1550
1551 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
1552 &tx_ring->dma, GFP_KERNEL);
1553 if (!tx_ring->desc) {
1554 vfree(tx_ring->buffer_info);
1555 pr_err("Unable to allocate memory for the transmit descriptor ring\n");
1556 return -ENOMEM;
1557 }
1558 memset(tx_ring->desc, 0, tx_ring->size);
1559
1560 tx_ring->next_to_use = 0;
1561 tx_ring->next_to_clean = 0;
1562 spin_lock_init(&tx_ring->tx_lock);
1563
1564 for (desNo = 0; desNo < tx_ring->count; desNo++) {
1565 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo);
1566 tx_desc->gbec_status = DSC_INIT16;
1567 }
1568 pr_debug("tx_ring->desc = 0x%p tx_ring->dma = 0x%08llx\n"
1569 "next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1570 tx_ring->desc, (unsigned long long)tx_ring->dma,
1571 tx_ring->next_to_clean, tx_ring->next_to_use);
1572 return 0;
1573}
1574
1575/**
1576 * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors)
1577 * @adapter: Board private structure
1578 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1579 * Returns
1580 * 0: Successfully
1581 * Negative value: Failed
1582 */
1583int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
1584 struct pch_gbe_rx_ring *rx_ring)
1585{
1586 struct pci_dev *pdev = adapter->pdev;
1587 struct pch_gbe_rx_desc *rx_desc;
1588 int size;
1589 int desNo;
1590
1591 size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count;
89bf67f1 1592 rx_ring->buffer_info = vzalloc(size);
77555ee7
MO		 1593 if (!rx_ring->buffer_info) {
1594 pr_err("Unable to allocate memory for the receive descriptor ring\n");
1595 return -ENOMEM;
1596 }
77555ee7
MO		 1597 rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc);
1598 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
1599 &rx_ring->dma, GFP_KERNEL);
1600
1601 if (!rx_ring->desc) {
1602 pr_err("Unable to allocate memory for the receive descriptor ring\n");
1603 vfree(rx_ring->buffer_info);
1604 return -ENOMEM;
1605 }
1606 memset(rx_ring->desc, 0, rx_ring->size);
1607 rx_ring->next_to_clean = 0;
1608 rx_ring->next_to_use = 0;
1609 for (desNo = 0; desNo < rx_ring->count; desNo++) {
1610 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo);
1611 rx_desc->gbec_status = DSC_INIT16;
1612 }
1613 pr_debug("rx_ring->desc = 0x%p rx_ring->dma = 0x%08llx "
1614 "next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1615 rx_ring->desc, (unsigned long long)rx_ring->dma,
1616 rx_ring->next_to_clean, rx_ring->next_to_use);
1617 return 0;
1618}
1619
1620/**
1621 * pch_gbe_free_tx_resources - Free Tx Resources
1622 * @adapter: Board private structure
1623 * @tx_ring: Tx descriptor ring for a specific queue
1624 */
1625void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
1626 struct pch_gbe_tx_ring *tx_ring)
1627{
1628 struct pci_dev *pdev = adapter->pdev;
1629
1630 pch_gbe_clean_tx_ring(adapter, tx_ring);
1631 vfree(tx_ring->buffer_info);
1632 tx_ring->buffer_info = NULL;
1633 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1634 tx_ring->desc = NULL;
1635}
1636
1637/**
1638 * pch_gbe_free_rx_resources - Free Rx Resources
1639 * @adapter: Board private structure
1640 * @rx_ring: Ring to clean the resources from
1641 */
1642void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
1643 struct pch_gbe_rx_ring *rx_ring)
1644{
1645 struct pci_dev *pdev = adapter->pdev;
1646
1647 pch_gbe_clean_rx_ring(adapter, rx_ring);
1648 vfree(rx_ring->buffer_info);
1649 rx_ring->buffer_info = NULL;
1650 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1651 rx_ring->desc = NULL;
1652}
1653
1654/**
1655 * pch_gbe_request_irq - Allocate an interrupt line
1656 * @adapter: Board private structure
1657 * Returns
1658 * 0: Successfully
1659 * Negative value: Failed
1660 */
1661static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter)
1662{
1663 struct net_device *netdev = adapter->netdev;
1664 int err;
1665 int flags;
1666
1667 flags = IRQF_SHARED;
1668 adapter->have_msi = false;
1669 err = pci_enable_msi(adapter->pdev);
1670 pr_debug("call pci_enable_msi\n");
1671 if (err) {
1672 pr_debug("call pci_enable_msi - Error: %d\n", err);
1673 } else {
1674 flags = 0;
1675 adapter->have_msi = true;
1676 }
1677 err = request_irq(adapter->pdev->irq, &pch_gbe_intr,
1678 flags, netdev->name, netdev);
1679 if (err)
1680 pr_err("Unable to allocate interrupt Error: %d\n", err);
1681 pr_debug("adapter->have_msi : %d flags : 0x%04x return : 0x%04x\n",
1682 adapter->have_msi, flags, err);
1683 return err;
1684}
1685
1686
1687static void pch_gbe_set_multi(struct net_device *netdev);
1688/**
1689 * pch_gbe_up - Up GbE network device
1690 * @adapter: Board private structure
1691 * Returns
1692 * 0: Successfully
1693 * Negative value: Failed
1694 */
1695int pch_gbe_up(struct pch_gbe_adapter *adapter)
1696{
1697 struct net_device *netdev = adapter->netdev;
1698 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1699 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1700 int err;
1701
1702 /* hardware has been reset, we need to reload some things */
1703 pch_gbe_set_multi(netdev);
1704
1705 pch_gbe_setup_tctl(adapter);
1706 pch_gbe_configure_tx(adapter);
1707 pch_gbe_setup_rctl(adapter);
1708 pch_gbe_configure_rx(adapter);
1709
1710 err = pch_gbe_request_irq(adapter);
1711 if (err) {
1712 pr_err("Error: can't bring device up\n");
1713 return err;
1714 }
1715 pch_gbe_alloc_tx_buffers(adapter, tx_ring);
1716 pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
1717 adapter->tx_queue_len = netdev->tx_queue_len;
1718
1719 mod_timer(&adapter->watchdog_timer, jiffies);
1720
1721 napi_enable(&adapter->napi);
1722 pch_gbe_irq_enable(adapter);
1723 netif_start_queue(adapter->netdev);
1724
1725 return 0;
1726}
1727
1728/**
1729 * pch_gbe_down - Down GbE network device
1730 * @adapter: Board private structure
1731 */
1732void pch_gbe_down(struct pch_gbe_adapter *adapter)
1733{
1734 struct net_device *netdev = adapter->netdev;
1735
1736 /* signal that we're down so the interrupt handler does not
1737 * reschedule our watchdog timer */
1738 napi_disable(&adapter->napi);
1739 atomic_set(&adapter->irq_sem, 0);
1740
1741 pch_gbe_irq_disable(adapter);
1742 pch_gbe_free_irq(adapter);
1743
1744 del_timer_sync(&adapter->watchdog_timer);
1745
1746 netdev->tx_queue_len = adapter->tx_queue_len;
1747 netif_carrier_off(netdev);
1748 netif_stop_queue(netdev);
1749
1750 pch_gbe_reset(adapter);
1751 pch_gbe_clean_tx_ring(adapter, adapter->tx_ring);
1752 pch_gbe_clean_rx_ring(adapter, adapter->rx_ring);
1753}
1754
1755/**
1756 * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter)
1757 * @adapter: Board private structure to initialize
1758 * Returns
1759 * 0: Successfully
1760 * Negative value: Failed
1761 */
1762static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter)
1763{
1764 struct pch_gbe_hw *hw = &adapter->hw;
1765 struct net_device *netdev = adapter->netdev;
1766
1767 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
1768 hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1769 hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1770
1771 /* Initialize the hardware-specific values */
1772 if (pch_gbe_hal_setup_init_funcs(hw)) {
1773 pr_err("Hardware Initialization Failure\n");
1774 return -EIO;
1775 }
1776 if (pch_gbe_alloc_queues(adapter)) {
1777 pr_err("Unable to allocate memory for queues\n");
1778 return -ENOMEM;
1779 }
1780 spin_lock_init(&adapter->hw.miim_lock);
1781 spin_lock_init(&adapter->tx_queue_lock);
1782 spin_lock_init(&adapter->stats_lock);
1783 spin_lock_init(&adapter->ethtool_lock);
1784 atomic_set(&adapter->irq_sem, 0);
1785 pch_gbe_irq_disable(adapter);
1786
1787 pch_gbe_init_stats(adapter);
1788
1789 pr_debug("rx_buffer_len : %d mac.min_frame_size : %d mac.max_frame_size : %d\n",
1790 (u32) adapter->rx_buffer_len,
1791 hw->mac.min_frame_size, hw->mac.max_frame_size);
1792 return 0;
1793}
1794
1795/**
1796 * pch_gbe_open - Called when a network interface is made active
1797 * @netdev: Network interface device structure
1798 * Returns
1799 * 0: Successfully
1800 * Negative value: Failed
1801 */
1802static int pch_gbe_open(struct net_device *netdev)
1803{
1804 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1805 struct pch_gbe_hw *hw = &adapter->hw;
1806 int err;
1807
1808 /* allocate transmit descriptors */
1809 err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring);
1810 if (err)
1811 goto err_setup_tx;
1812 /* allocate receive descriptors */
1813 err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring);
1814 if (err)
1815 goto err_setup_rx;
1816 pch_gbe_hal_power_up_phy(hw);
1817 err = pch_gbe_up(adapter);
1818 if (err)
1819 goto err_up;
1820 pr_debug("Success End\n");
1821 return 0;
1822
1823err_up:
1824 if (!adapter->wake_up_evt)
1825 pch_gbe_hal_power_down_phy(hw);
1826 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
1827err_setup_rx:
1828 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
1829err_setup_tx:
1830 pch_gbe_reset(adapter);
1831 pr_err("Error End\n");
1832 return err;
1833}
1834
1835/**
1836 * pch_gbe_stop - Disables a network interface
1837 * @netdev: Network interface device structure
1838 * Returns
1839 * 0: Successfully
1840 */
1841static int pch_gbe_stop(struct net_device *netdev)
1842{
1843 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1844 struct pch_gbe_hw *hw = &adapter->hw;
1845
1846 pch_gbe_down(adapter);
1847 if (!adapter->wake_up_evt)
1848 pch_gbe_hal_power_down_phy(hw);
1849 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
1850 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
1851 return 0;
1852}
1853
1854/**
1855 * pch_gbe_xmit_frame - Packet transmitting start
1856 * @skb: Socket buffer structure
1857 * @netdev: Network interface device structure
1858 * Returns
1859 * - NETDEV_TX_OK: Normal end
1860 * - NETDEV_TX_BUSY: Error end
1861 */
1862static int pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1863{
1864 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1865 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1866 unsigned long flags;
1867
1868 if (unlikely(skb->len > (adapter->hw.mac.max_frame_size - 4))) {
77555ee7
MO		 1869 pr_err("Transfer length Error: skb len: %d > max: %d\n",
1870 skb->len, adapter->hw.mac.max_frame_size);
419c2046 1871 dev_kfree_skb_any(skb);
77555ee7
MO		 1872 adapter->stats.tx_length_errors++;
1873 return NETDEV_TX_OK;
1874 }
1875 if (!spin_trylock_irqsave(&tx_ring->tx_lock, flags)) {
1876 /* Collision - tell upper layer to requeue */
1877 return NETDEV_TX_LOCKED;
1878 }
1879 if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) {
1880 netif_stop_queue(netdev);
1881 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1882 pr_debug("Return : BUSY next_to use : 0x%08x next_to clean : 0x%08x\n",
1883 tx_ring->next_to_use, tx_ring->next_to_clean);
1884 return NETDEV_TX_BUSY;
1885 }
1886 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1887
1888 /* CRC,ITAG no support */
1889 pch_gbe_tx_queue(adapter, tx_ring, skb);
1890 return NETDEV_TX_OK;
1891}
1892
1893/**
1894 * pch_gbe_get_stats - Get System Network Statistics
1895 * @netdev: Network interface device structure
1896 * Returns: The current stats
1897 */
1898static struct net_device_stats *pch_gbe_get_stats(struct net_device *netdev)
1899{
1900 /* only return the current stats */
1901 return &netdev->stats;
1902}
1903
1904/**
1905 * pch_gbe_set_multi - Multicast and Promiscuous mode set
1906 * @netdev: Network interface device structure
1907 */
1908static void pch_gbe_set_multi(struct net_device *netdev)
1909{
1910 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1911 struct pch_gbe_hw *hw = &adapter->hw;
1912 struct netdev_hw_addr *ha;
1913 u8 *mta_list;
1914 u32 rctl;
1915 int i;
1916 int mc_count;
1917
1918 pr_debug("netdev->flags : 0x%08x\n", netdev->flags);
1919
1920 /* Check for Promiscuous and All Multicast modes */
1921 rctl = ioread32(&hw->reg->RX_MODE);
1922 mc_count = netdev_mc_count(netdev);
1923 if ((netdev->flags & IFF_PROMISC)) {
1924 rctl &= ~PCH_GBE_ADD_FIL_EN;
1925 rctl &= ~PCH_GBE_MLT_FIL_EN;
1926 } else if ((netdev->flags & IFF_ALLMULTI)) {
1927 /* all the multicasting receive permissions */
1928 rctl |= PCH_GBE_ADD_FIL_EN;
1929 rctl &= ~PCH_GBE_MLT_FIL_EN;
1930 } else {
1931 if (mc_count >= PCH_GBE_MAR_ENTRIES) {
1932 /* all the multicasting receive permissions */
1933 rctl |= PCH_GBE_ADD_FIL_EN;
1934 rctl &= ~PCH_GBE_MLT_FIL_EN;
1935 } else {
1936 rctl |= (PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
1937 }
1938 }
1939 iowrite32(rctl, &hw->reg->RX_MODE);
1940
1941 if (mc_count >= PCH_GBE_MAR_ENTRIES)
1942 return;
1943 mta_list = kmalloc(mc_count * ETH_ALEN, GFP_ATOMIC);
1944 if (!mta_list)
1945 return;
1946
1947 /* The shared function expects a packed array of only addresses. */
1948 i = 0;
1949 netdev_for_each_mc_addr(ha, netdev) {
1950 if (i == mc_count)
1951 break;
1952 memcpy(mta_list + (i++ * ETH_ALEN), &ha->addr, ETH_ALEN);
1953 }
1954 pch_gbe_mac_mc_addr_list_update(hw, mta_list, i, 1,
1955 PCH_GBE_MAR_ENTRIES);
1956 kfree(mta_list);
1957
1958 pr_debug("RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x netdev->mc_count : 0x%08x\n",
1959 ioread32(&hw->reg->RX_MODE), mc_count);
1960}
1961
1962/**
1963 * pch_gbe_set_mac - Change the Ethernet Address of the NIC
1964 * @netdev: Network interface device structure
1965 * @addr: Pointer to an address structure
1966 * Returns
1967 * 0: Successfully
1968 * -EADDRNOTAVAIL: Failed
1969 */
1970static int pch_gbe_set_mac(struct net_device *netdev, void *addr)
1971{
1972 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1973 struct sockaddr *skaddr = addr;
1974 int ret_val;
1975
1976 if (!is_valid_ether_addr(skaddr->sa_data)) {
1977 ret_val = -EADDRNOTAVAIL;
1978 } else {
1979 memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len);
1980 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len);
1981 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1982 ret_val = 0;
1983 }
1984 pr_debug("ret_val : 0x%08x\n", ret_val);
1985 pr_debug("dev_addr : %pM\n", netdev->dev_addr);
1986 pr_debug("mac_addr : %pM\n", adapter->hw.mac.addr);
1987 pr_debug("MAC_ADR1AB reg : 0x%08x 0x%08x\n",
1988 ioread32(&adapter->hw.reg->mac_adr[0].high),
1989 ioread32(&adapter->hw.reg->mac_adr[0].low));
1990 return ret_val;
1991}
1992
1993/**
1994 * pch_gbe_change_mtu - Change the Maximum Transfer Unit
1995 * @netdev: Network interface device structure
1996 * @new_mtu: New value for maximum frame size
1997 * Returns
1998 * 0: Successfully
1999 * -EINVAL: Failed
2000 */
2001static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu)
2002{
2003 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2004 int max_frame;
2005
2006 max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2007 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2008 (max_frame > PCH_GBE_MAX_JUMBO_FRAME_SIZE)) {
2009 pr_err("Invalid MTU setting\n");
2010 return -EINVAL;
2011 }
2012 if (max_frame <= PCH_GBE_FRAME_SIZE_2048)
2013 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2014 else if (max_frame <= PCH_GBE_FRAME_SIZE_4096)
2015 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096;
2016 else if (max_frame <= PCH_GBE_FRAME_SIZE_8192)
2017 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192;
2018 else
2019 adapter->rx_buffer_len = PCH_GBE_MAX_JUMBO_FRAME_SIZE;
2020 netdev->mtu = new_mtu;
2021 adapter->hw.mac.max_frame_size = max_frame;
2022
2023 if (netif_running(netdev))
2024 pch_gbe_reinit_locked(adapter);
2025 else
2026 pch_gbe_reset(adapter);
2027
2028 pr_debug("max_frame : %d rx_buffer_len : %d mtu : %d max_frame_size : %d\n",
2029 max_frame, (u32) adapter->rx_buffer_len, netdev->mtu,
2030 adapter->hw.mac.max_frame_size);
2031 return 0;
2032}
2033
2034/**
2035 * pch_gbe_ioctl - Controls register through a MII interface
2036 * @netdev: Network interface device structure
2037 * @ifr: Pointer to ifr structure
2038 * @cmd: Control command
2039 * Returns
2040 * 0: Successfully
2041 * Negative value: Failed
2042 */
2043static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2044{
2045 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2046
2047 pr_debug("cmd : 0x%04x\n", cmd);
2048
2049 return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
2050}
2051
2052/**
2053 * pch_gbe_tx_timeout - Respond to a Tx Hang
2054 * @netdev: Network interface device structure
2055 */
2056static void pch_gbe_tx_timeout(struct net_device *netdev)
2057{
2058 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2059
2060 /* Do the reset outside of interrupt context */
2061 adapter->stats.tx_timeout_count++;
2062 schedule_work(&adapter->reset_task);
2063}
2064
2065/**
2066 * pch_gbe_napi_poll - NAPI receive and transfer polling callback
2067 * @napi: Pointer of polling device struct
2068 * @budget: The maximum number of a packet
2069 * Returns
2070 * false: Exit the polling mode
2071 * true: Continue the polling mode
2072 */
2073static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
2074{
2075 struct pch_gbe_adapter *adapter =
2076 container_of(napi, struct pch_gbe_adapter, napi);
2077 struct net_device *netdev = adapter->netdev;
2078 int work_done = 0;
2079 bool poll_end_flag = false;
2080 bool cleaned = false;
2081
2082 pr_debug("budget : %d\n", budget);
2083
2084 /* Keep link state information with original netdev */
2085 if (!netif_carrier_ok(netdev)) {
2086 poll_end_flag = true;
2087 } else {
2088 cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
2089 pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
2090
2091 if (cleaned)
2092 work_done = budget;
2093 /* If no Tx and not enough Rx work done,
2094 * exit the polling mode
2095 */
2096 if ((work_done < budget) || !netif_running(netdev))
2097 poll_end_flag = true;
2098 }
2099
2100 if (poll_end_flag) {
2101 napi_complete(napi);
2102 pch_gbe_irq_enable(adapter);
2103 }
2104
2105 pr_debug("poll_end_flag : %d work_done : %d budget : %d\n",
2106 poll_end_flag, work_done, budget);
2107
2108 return work_done;
2109}
2110
2111#ifdef CONFIG_NET_POLL_CONTROLLER
2112/**
2113 * pch_gbe_netpoll - Used by things like netconsole to send skbs
2114 * @netdev: Network interface device structure
2115 */
2116static void pch_gbe_netpoll(struct net_device *netdev)
2117{
2118 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2119
2120 disable_irq(adapter->pdev->irq);
2121 pch_gbe_intr(adapter->pdev->irq, netdev);
2122 enable_irq(adapter->pdev->irq);
2123}
2124#endif
2125
2126static const struct net_device_ops pch_gbe_netdev_ops = {
2127 .ndo_open = pch_gbe_open,
2128 .ndo_stop = pch_gbe_stop,
2129 .ndo_start_xmit = pch_gbe_xmit_frame,
2130 .ndo_get_stats = pch_gbe_get_stats,
2131 .ndo_set_mac_address = pch_gbe_set_mac,
2132 .ndo_tx_timeout = pch_gbe_tx_timeout,
2133 .ndo_change_mtu = pch_gbe_change_mtu,
2134 .ndo_do_ioctl = pch_gbe_ioctl,
2135 .ndo_set_multicast_list = &pch_gbe_set_multi,
2136#ifdef CONFIG_NET_POLL_CONTROLLER
2137 .ndo_poll_controller = pch_gbe_netpoll,
2138#endif
2139};
2140
2141static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev,
2142 pci_channel_state_t state)
2143{
2144 struct net_device *netdev = pci_get_drvdata(pdev);
2145 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2146
2147 netif_device_detach(netdev);
2148 if (netif_running(netdev))
2149 pch_gbe_down(adapter);
2150 pci_disable_device(pdev);
2151 /* Request a slot slot reset. */
2152 return PCI_ERS_RESULT_NEED_RESET;
2153}
2154
2155static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev)
2156{
2157 struct net_device *netdev = pci_get_drvdata(pdev);
2158 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2159 struct pch_gbe_hw *hw = &adapter->hw;
2160
2161 if (pci_enable_device(pdev)) {
2162 pr_err("Cannot re-enable PCI device after reset\n");
2163 return PCI_ERS_RESULT_DISCONNECT;
2164 }
2165 pci_set_master(pdev);
2166 pci_enable_wake(pdev, PCI_D0, 0);
2167 pch_gbe_hal_power_up_phy(hw);
2168 pch_gbe_reset(adapter);
2169 /* Clear wake up status */
2170 pch_gbe_mac_set_wol_event(hw, 0);
2171
2172 return PCI_ERS_RESULT_RECOVERED;
2173}
2174
2175static void pch_gbe_io_resume(struct pci_dev *pdev)
2176{
2177 struct net_device *netdev = pci_get_drvdata(pdev);
2178 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2179
2180 if (netif_running(netdev)) {
2181 if (pch_gbe_up(adapter)) {
2182 pr_debug("can't bring device back up after reset\n");
2183 return;
2184 }
2185 }
2186 netif_device_attach(netdev);
2187}
2188
2189static int __pch_gbe_suspend(struct pci_dev *pdev)
2190{
2191 struct net_device *netdev = pci_get_drvdata(pdev);
2192 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2193 struct pch_gbe_hw *hw = &adapter->hw;
2194 u32 wufc = adapter->wake_up_evt;
2195 int retval = 0;
2196
2197 netif_device_detach(netdev);
2198 if (netif_running(netdev))
2199 pch_gbe_down(adapter);
2200 if (wufc) {
2201 pch_gbe_set_multi(netdev);
2202 pch_gbe_setup_rctl(adapter);
2203 pch_gbe_configure_rx(adapter);
2204 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
2205 hw->mac.link_duplex);
2206 pch_gbe_set_mode(adapter, hw->mac.link_speed,
2207 hw->mac.link_duplex);
2208 pch_gbe_mac_set_wol_event(hw, wufc);
2209 pci_disable_device(pdev);
2210 } else {
2211 pch_gbe_hal_power_down_phy(hw);
2212 pch_gbe_mac_set_wol_event(hw, wufc);
2213 pci_disable_device(pdev);
2214 }
2215 return retval;
2216}
2217
2218#ifdef CONFIG_PM
2219static int pch_gbe_suspend(struct device *device)
2220{
2221 struct pci_dev *pdev = to_pci_dev(device);
2222
2223 return __pch_gbe_suspend(pdev);
2224}
2225
2226static int pch_gbe_resume(struct device *device)
2227{
2228 struct pci_dev *pdev = to_pci_dev(device);
2229 struct net_device *netdev = pci_get_drvdata(pdev);
2230 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2231 struct pch_gbe_hw *hw = &adapter->hw;
2232 u32 err;
2233
2234 err = pci_enable_device(pdev);
2235 if (err) {
2236 pr_err("Cannot enable PCI device from suspend\n");
2237 return err;
2238 }
2239 pci_set_master(pdev);
2240 pch_gbe_hal_power_up_phy(hw);
2241 pch_gbe_reset(adapter);
2242 /* Clear wake on lan control and status */
2243 pch_gbe_mac_set_wol_event(hw, 0);
2244
2245 if (netif_running(netdev))
2246 pch_gbe_up(adapter);
2247 netif_device_attach(netdev);
2248
2249 return 0;
2250}
2251#endif /* CONFIG_PM */
2252
2253static void pch_gbe_shutdown(struct pci_dev *pdev)
2254{
2255 __pch_gbe_suspend(pdev);
2256 if (system_state == SYSTEM_POWER_OFF) {
2257 pci_wake_from_d3(pdev, true);
2258 pci_set_power_state(pdev, PCI_D3hot);
2259 }
2260}
2261
2262static void pch_gbe_remove(struct pci_dev *pdev)
2263{
2264 struct net_device *netdev = pci_get_drvdata(pdev);
2265 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2266
2321f3b4 2267 cancel_work_sync(&adapter->reset_task);
77555ee7
MO		 2268 unregister_netdev(netdev);
2269
2270 pch_gbe_hal_phy_hw_reset(&adapter->hw);
2271
2272 kfree(adapter->tx_ring);
2273 kfree(adapter->rx_ring);
2274
2275 iounmap(adapter->hw.reg);
2276 pci_release_regions(pdev);
2277 free_netdev(netdev);
2278 pci_disable_device(pdev);
2279}
2280
2281static int pch_gbe_probe(struct pci_dev *pdev,
2282 const struct pci_device_id *pci_id)
2283{
2284 struct net_device *netdev;
2285 struct pch_gbe_adapter *adapter;
2286 int ret;
2287
2288 ret = pci_enable_device(pdev);
2289 if (ret)
2290 return ret;
2291
2292 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2293 || pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2294 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2295 if (ret) {
2296 ret = pci_set_consistent_dma_mask(pdev,
2297 DMA_BIT_MASK(32));
2298 if (ret) {
2299 dev_err(&pdev->dev, "ERR: No usable DMA "
2300 "configuration, aborting\n");
2301 goto err_disable_device;
2302 }
2303 }
2304 }
2305
2306 ret = pci_request_regions(pdev, KBUILD_MODNAME);
2307 if (ret) {
2308 dev_err(&pdev->dev,
2309 "ERR: Can't reserve PCI I/O and memory resources\n");
2310 goto err_disable_device;
2311 }
2312 pci_set_master(pdev);
2313
2314 netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter));
2315 if (!netdev) {
2316 ret = -ENOMEM;
2317 dev_err(&pdev->dev,
2318 "ERR: Can't allocate and set up an Ethernet device\n");
2319 goto err_release_pci;
2320 }
2321 SET_NETDEV_DEV(netdev, &pdev->dev);
2322
2323 pci_set_drvdata(pdev, netdev);
2324 adapter = netdev_priv(netdev);
2325 adapter->netdev = netdev;
2326 adapter->pdev = pdev;
2327 adapter->hw.back = adapter;
2328 adapter->hw.reg = pci_iomap(pdev, PCH_GBE_PCI_BAR, 0);
2329 if (!adapter->hw.reg) {
2330 ret = -EIO;
2331 dev_err(&pdev->dev, "Can't ioremap\n");
2332 goto err_free_netdev;
2333 }
2334
2335 netdev->netdev_ops = &pch_gbe_netdev_ops;
2336 netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
2337 netif_napi_add(netdev, &adapter->napi,
2338 pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT);
79032644 2339 netdev->features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_GRO;
77555ee7
MO		 2340 pch_gbe_set_ethtool_ops(netdev);
2341
98200ec2 2342 pch_gbe_mac_load_mac_addr(&adapter->hw);
77555ee7
MO		 2343 pch_gbe_mac_reset_hw(&adapter->hw);
2344
2345 /* setup the private structure */
2346 ret = pch_gbe_sw_init(adapter);
2347 if (ret)
2348 goto err_iounmap;
2349
2350 /* Initialize PHY */
2351 ret = pch_gbe_init_phy(adapter);
2352 if (ret) {
2353 dev_err(&pdev->dev, "PHY initialize error\n");
2354 goto err_free_adapter;
2355 }
2356 pch_gbe_hal_get_bus_info(&adapter->hw);
2357
2358 /* Read the MAC address. and store to the private data */
2359 ret = pch_gbe_hal_read_mac_addr(&adapter->hw);
2360 if (ret) {
2361 dev_err(&pdev->dev, "MAC address Read Error\n");
2362 goto err_free_adapter;
2363 }
2364
2365 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
2366 if (!is_valid_ether_addr(netdev->dev_addr)) {
2367 dev_err(&pdev->dev, "Invalid MAC Address\n");
2368 ret = -EIO;
2369 goto err_free_adapter;
2370 }
2371 setup_timer(&adapter->watchdog_timer, pch_gbe_watchdog,
2372 (unsigned long)adapter);
2373
2374 INIT_WORK(&adapter->reset_task, pch_gbe_reset_task);
2375
2376 pch_gbe_check_options(adapter);
2377
2378 if (adapter->tx_csum)
79032644 2379 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
77555ee7 2380 else
79032644 2381 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
77555ee7
MO		 2382
2383 /* initialize the wol settings based on the eeprom settings */
2384 adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
2385 dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr);
2386
2387 /* reset the hardware with the new settings */
2388 pch_gbe_reset(adapter);
2389
2390 ret = register_netdev(netdev);
2391 if (ret)
2392 goto err_free_adapter;
2393 /* tell the stack to leave us alone until pch_gbe_open() is called */
2394 netif_carrier_off(netdev);
2395 netif_stop_queue(netdev);
2396
2397 dev_dbg(&pdev->dev, "OKIsemi(R) PCH Network Connection\n");
2398
2399 device_set_wakeup_enable(&pdev->dev, 1);
2400 return 0;
2401
2402err_free_adapter:
2403 pch_gbe_hal_phy_hw_reset(&adapter->hw);
2404 kfree(adapter->tx_ring);
2405 kfree(adapter->rx_ring);
2406err_iounmap:
2407 iounmap(adapter->hw.reg);
2408err_free_netdev:
2409 free_netdev(netdev);
2410err_release_pci:
2411 pci_release_regions(pdev);
2412err_disable_device:
2413 pci_disable_device(pdev);
2414 return ret;
2415}
2416
7fc44633 2417static DEFINE_PCI_DEVICE_TABLE(pch_gbe_pcidev_id) = {
77555ee7
MO		 2418 {.vendor = PCI_VENDOR_ID_INTEL,
2419 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2420 .subvendor = PCI_ANY_ID,
2421 .subdevice = PCI_ANY_ID,
2422 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2423 .class_mask = (0xFFFF00)
2424 },
b0e6baf5
T		 2425 {.vendor = PCI_VENDOR_ID_ROHM,
2426 .device = PCI_DEVICE_ID_ROHM_ML7223_GBE,
2427 .subvendor = PCI_ANY_ID,
2428 .subdevice = PCI_ANY_ID,
2429 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2430 .class_mask = (0xFFFF00)
2431 },
77555ee7
MO		 2432 /* required last entry */
2433 {0}
2434};
2435
2436#ifdef CONFIG_PM
2437static const struct dev_pm_ops pch_gbe_pm_ops = {
2438 .suspend = pch_gbe_suspend,
2439 .resume = pch_gbe_resume,
2440 .freeze = pch_gbe_suspend,
2441 .thaw = pch_gbe_resume,
2442 .poweroff = pch_gbe_suspend,
2443 .restore = pch_gbe_resume,
2444};
2445#endif
2446
2447static struct pci_error_handlers pch_gbe_err_handler = {
2448 .error_detected = pch_gbe_io_error_detected,
2449 .slot_reset = pch_gbe_io_slot_reset,
2450 .resume = pch_gbe_io_resume
2451};
2452
f7594d42 2453static struct pci_driver pch_gbe_driver = {
77555ee7
MO		 2454 .name = KBUILD_MODNAME,
2455 .id_table = pch_gbe_pcidev_id,
2456 .probe = pch_gbe_probe,
2457 .remove = pch_gbe_remove,
aa338601 2458#ifdef CONFIG_PM
77555ee7
MO		 2459 .driver.pm = &pch_gbe_pm_ops,
2460#endif
2461 .shutdown = pch_gbe_shutdown,
2462 .err_handler = &pch_gbe_err_handler
2463};
2464
2465
2466static int __init pch_gbe_init_module(void)
2467{
2468 int ret;
2469
f7594d42 2470 ret = pci_register_driver(&pch_gbe_driver);
77555ee7
MO		 2471 if (copybreak != PCH_GBE_COPYBREAK_DEFAULT) {
2472 if (copybreak == 0) {
2473 pr_info("copybreak disabled\n");
2474 } else {
2475 pr_info("copybreak enabled for packets <= %u bytes\n",
2476 copybreak);
2477 }
2478 }
2479 return ret;
2480}
2481
2482static void __exit pch_gbe_exit_module(void)
2483{
f7594d42 2484 pci_unregister_driver(&pch_gbe_driver);
77555ee7
MO		 2485}
2486
2487module_init(pch_gbe_init_module);
2488module_exit(pch_gbe_exit_module);
2489
a1dcfcb7
TO		 2490MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
2491MODULE_AUTHOR("OKI SEMICONDUCTOR, <toshiharu-linux@dsn.okisemi.com>");
77555ee7
MO		 2492MODULE_LICENSE("GPL");
2493MODULE_VERSION(DRV_VERSION);
2494MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
2495
2496module_param(copybreak, uint, 0644);
2497MODULE_PARM_DESC(copybreak,
2498 "Maximum size of packet that is copied to a new buffer on receive");
2499
2500/* pch_gbe_main.c */
kernel source for telekom puls (alcatel/mediatek)