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a3138df9 DM |
1 | /* niu.c: Neptune ethernet driver. |
2 | * | |
3 | * Copyright (C) 2007 David S. Miller (davem@davemloft.net) | |
4 | */ | |
5 | ||
6 | #include <linux/module.h> | |
7 | #include <linux/init.h> | |
8 | #include <linux/pci.h> | |
9 | #include <linux/dma-mapping.h> | |
10 | #include <linux/netdevice.h> | |
11 | #include <linux/ethtool.h> | |
12 | #include <linux/etherdevice.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/bitops.h> | |
16 | #include <linux/mii.h> | |
17 | #include <linux/if_ether.h> | |
18 | #include <linux/if_vlan.h> | |
19 | #include <linux/ip.h> | |
20 | #include <linux/in.h> | |
21 | #include <linux/ipv6.h> | |
22 | #include <linux/log2.h> | |
23 | #include <linux/jiffies.h> | |
24 | #include <linux/crc32.h> | |
25 | ||
26 | #include <linux/io.h> | |
27 | ||
28 | #ifdef CONFIG_SPARC64 | |
29 | #include <linux/of_device.h> | |
30 | #endif | |
31 | ||
32 | #include "niu.h" | |
33 | ||
34 | #define DRV_MODULE_NAME "niu" | |
35 | #define PFX DRV_MODULE_NAME ": " | |
a4425859 DM |
36 | #define DRV_MODULE_VERSION "0.7" |
37 | #define DRV_MODULE_RELDATE "February 18, 2008" | |
a3138df9 DM |
38 | |
39 | static char version[] __devinitdata = | |
40 | DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; | |
41 | ||
42 | MODULE_AUTHOR("David S. Miller (davem@davemloft.net)"); | |
43 | MODULE_DESCRIPTION("NIU ethernet driver"); | |
44 | MODULE_LICENSE("GPL"); | |
45 | MODULE_VERSION(DRV_MODULE_VERSION); | |
46 | ||
47 | #ifndef DMA_44BIT_MASK | |
48 | #define DMA_44BIT_MASK 0x00000fffffffffffULL | |
49 | #endif | |
50 | ||
51 | #ifndef readq | |
52 | static u64 readq(void __iomem *reg) | |
53 | { | |
54 | return (((u64)readl(reg + 0x4UL) << 32) | | |
55 | (u64)readl(reg)); | |
56 | } | |
57 | ||
58 | static void writeq(u64 val, void __iomem *reg) | |
59 | { | |
60 | writel(val & 0xffffffff, reg); | |
61 | writel(val >> 32, reg + 0x4UL); | |
62 | } | |
63 | #endif | |
64 | ||
65 | static struct pci_device_id niu_pci_tbl[] = { | |
66 | {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)}, | |
67 | {} | |
68 | }; | |
69 | ||
70 | MODULE_DEVICE_TABLE(pci, niu_pci_tbl); | |
71 | ||
72 | #define NIU_TX_TIMEOUT (5 * HZ) | |
73 | ||
74 | #define nr64(reg) readq(np->regs + (reg)) | |
75 | #define nw64(reg, val) writeq((val), np->regs + (reg)) | |
76 | ||
77 | #define nr64_mac(reg) readq(np->mac_regs + (reg)) | |
78 | #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg)) | |
79 | ||
80 | #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg)) | |
81 | #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg)) | |
82 | ||
83 | #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg)) | |
84 | #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg)) | |
85 | ||
86 | #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg)) | |
87 | #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg)) | |
88 | ||
89 | #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) | |
90 | ||
91 | static int niu_debug; | |
92 | static int debug = -1; | |
93 | module_param(debug, int, 0); | |
94 | MODULE_PARM_DESC(debug, "NIU debug level"); | |
95 | ||
96 | #define niudbg(TYPE, f, a...) \ | |
97 | do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \ | |
98 | printk(KERN_DEBUG PFX f, ## a); \ | |
99 | } while (0) | |
100 | ||
101 | #define niuinfo(TYPE, f, a...) \ | |
102 | do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \ | |
103 | printk(KERN_INFO PFX f, ## a); \ | |
104 | } while (0) | |
105 | ||
106 | #define niuwarn(TYPE, f, a...) \ | |
107 | do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \ | |
108 | printk(KERN_WARNING PFX f, ## a); \ | |
109 | } while (0) | |
110 | ||
111 | #define niu_lock_parent(np, flags) \ | |
112 | spin_lock_irqsave(&np->parent->lock, flags) | |
113 | #define niu_unlock_parent(np, flags) \ | |
114 | spin_unlock_irqrestore(&np->parent->lock, flags) | |
115 | ||
116 | static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg, | |
117 | u64 bits, int limit, int delay) | |
118 | { | |
119 | while (--limit >= 0) { | |
120 | u64 val = nr64_mac(reg); | |
121 | ||
122 | if (!(val & bits)) | |
123 | break; | |
124 | udelay(delay); | |
125 | } | |
126 | if (limit < 0) | |
127 | return -ENODEV; | |
128 | return 0; | |
129 | } | |
130 | ||
131 | static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg, | |
132 | u64 bits, int limit, int delay, | |
133 | const char *reg_name) | |
134 | { | |
135 | int err; | |
136 | ||
137 | nw64_mac(reg, bits); | |
138 | err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay); | |
139 | if (err) | |
140 | dev_err(np->device, PFX "%s: bits (%llx) of register %s " | |
141 | "would not clear, val[%llx]\n", | |
142 | np->dev->name, (unsigned long long) bits, reg_name, | |
143 | (unsigned long long) nr64_mac(reg)); | |
144 | return err; | |
145 | } | |
146 | ||
147 | #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ | |
148 | ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ | |
149 | __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ | |
150 | }) | |
151 | ||
152 | static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg, | |
153 | u64 bits, int limit, int delay) | |
154 | { | |
155 | while (--limit >= 0) { | |
156 | u64 val = nr64_ipp(reg); | |
157 | ||
158 | if (!(val & bits)) | |
159 | break; | |
160 | udelay(delay); | |
161 | } | |
162 | if (limit < 0) | |
163 | return -ENODEV; | |
164 | return 0; | |
165 | } | |
166 | ||
167 | static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg, | |
168 | u64 bits, int limit, int delay, | |
169 | const char *reg_name) | |
170 | { | |
171 | int err; | |
172 | u64 val; | |
173 | ||
174 | val = nr64_ipp(reg); | |
175 | val |= bits; | |
176 | nw64_ipp(reg, val); | |
177 | ||
178 | err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay); | |
179 | if (err) | |
180 | dev_err(np->device, PFX "%s: bits (%llx) of register %s " | |
181 | "would not clear, val[%llx]\n", | |
182 | np->dev->name, (unsigned long long) bits, reg_name, | |
183 | (unsigned long long) nr64_ipp(reg)); | |
184 | return err; | |
185 | } | |
186 | ||
187 | #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ | |
188 | ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ | |
189 | __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ | |
190 | }) | |
191 | ||
192 | static int __niu_wait_bits_clear(struct niu *np, unsigned long reg, | |
193 | u64 bits, int limit, int delay) | |
194 | { | |
195 | while (--limit >= 0) { | |
196 | u64 val = nr64(reg); | |
197 | ||
198 | if (!(val & bits)) | |
199 | break; | |
200 | udelay(delay); | |
201 | } | |
202 | if (limit < 0) | |
203 | return -ENODEV; | |
204 | return 0; | |
205 | } | |
206 | ||
207 | #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \ | |
208 | ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ | |
209 | __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \ | |
210 | }) | |
211 | ||
212 | static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg, | |
213 | u64 bits, int limit, int delay, | |
214 | const char *reg_name) | |
215 | { | |
216 | int err; | |
217 | ||
218 | nw64(reg, bits); | |
219 | err = __niu_wait_bits_clear(np, reg, bits, limit, delay); | |
220 | if (err) | |
221 | dev_err(np->device, PFX "%s: bits (%llx) of register %s " | |
222 | "would not clear, val[%llx]\n", | |
223 | np->dev->name, (unsigned long long) bits, reg_name, | |
224 | (unsigned long long) nr64(reg)); | |
225 | return err; | |
226 | } | |
227 | ||
228 | #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ | |
229 | ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ | |
230 | __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ | |
231 | }) | |
232 | ||
233 | static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on) | |
234 | { | |
235 | u64 val = (u64) lp->timer; | |
236 | ||
237 | if (on) | |
238 | val |= LDG_IMGMT_ARM; | |
239 | ||
240 | nw64(LDG_IMGMT(lp->ldg_num), val); | |
241 | } | |
242 | ||
243 | static int niu_ldn_irq_enable(struct niu *np, int ldn, int on) | |
244 | { | |
245 | unsigned long mask_reg, bits; | |
246 | u64 val; | |
247 | ||
248 | if (ldn < 0 || ldn > LDN_MAX) | |
249 | return -EINVAL; | |
250 | ||
251 | if (ldn < 64) { | |
252 | mask_reg = LD_IM0(ldn); | |
253 | bits = LD_IM0_MASK; | |
254 | } else { | |
255 | mask_reg = LD_IM1(ldn - 64); | |
256 | bits = LD_IM1_MASK; | |
257 | } | |
258 | ||
259 | val = nr64(mask_reg); | |
260 | if (on) | |
261 | val &= ~bits; | |
262 | else | |
263 | val |= bits; | |
264 | nw64(mask_reg, val); | |
265 | ||
266 | return 0; | |
267 | } | |
268 | ||
269 | static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on) | |
270 | { | |
271 | struct niu_parent *parent = np->parent; | |
272 | int i; | |
273 | ||
274 | for (i = 0; i <= LDN_MAX; i++) { | |
275 | int err; | |
276 | ||
277 | if (parent->ldg_map[i] != lp->ldg_num) | |
278 | continue; | |
279 | ||
280 | err = niu_ldn_irq_enable(np, i, on); | |
281 | if (err) | |
282 | return err; | |
283 | } | |
284 | return 0; | |
285 | } | |
286 | ||
287 | static int niu_enable_interrupts(struct niu *np, int on) | |
288 | { | |
289 | int i; | |
290 | ||
291 | for (i = 0; i < np->num_ldg; i++) { | |
292 | struct niu_ldg *lp = &np->ldg[i]; | |
293 | int err; | |
294 | ||
295 | err = niu_enable_ldn_in_ldg(np, lp, on); | |
296 | if (err) | |
297 | return err; | |
298 | } | |
299 | for (i = 0; i < np->num_ldg; i++) | |
300 | niu_ldg_rearm(np, &np->ldg[i], on); | |
301 | ||
302 | return 0; | |
303 | } | |
304 | ||
305 | static u32 phy_encode(u32 type, int port) | |
306 | { | |
307 | return (type << (port * 2)); | |
308 | } | |
309 | ||
310 | static u32 phy_decode(u32 val, int port) | |
311 | { | |
312 | return (val >> (port * 2)) & PORT_TYPE_MASK; | |
313 | } | |
314 | ||
315 | static int mdio_wait(struct niu *np) | |
316 | { | |
317 | int limit = 1000; | |
318 | u64 val; | |
319 | ||
320 | while (--limit > 0) { | |
321 | val = nr64(MIF_FRAME_OUTPUT); | |
322 | if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1) | |
323 | return val & MIF_FRAME_OUTPUT_DATA; | |
324 | ||
325 | udelay(10); | |
326 | } | |
327 | ||
328 | return -ENODEV; | |
329 | } | |
330 | ||
331 | static int mdio_read(struct niu *np, int port, int dev, int reg) | |
332 | { | |
333 | int err; | |
334 | ||
335 | nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg)); | |
336 | err = mdio_wait(np); | |
337 | if (err < 0) | |
338 | return err; | |
339 | ||
340 | nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev)); | |
341 | return mdio_wait(np); | |
342 | } | |
343 | ||
344 | static int mdio_write(struct niu *np, int port, int dev, int reg, int data) | |
345 | { | |
346 | int err; | |
347 | ||
348 | nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg)); | |
349 | err = mdio_wait(np); | |
350 | if (err < 0) | |
351 | return err; | |
352 | ||
353 | nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data)); | |
354 | err = mdio_wait(np); | |
355 | if (err < 0) | |
356 | return err; | |
357 | ||
358 | return 0; | |
359 | } | |
360 | ||
361 | static int mii_read(struct niu *np, int port, int reg) | |
362 | { | |
363 | nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg)); | |
364 | return mdio_wait(np); | |
365 | } | |
366 | ||
367 | static int mii_write(struct niu *np, int port, int reg, int data) | |
368 | { | |
369 | int err; | |
370 | ||
371 | nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data)); | |
372 | err = mdio_wait(np); | |
373 | if (err < 0) | |
374 | return err; | |
375 | ||
376 | return 0; | |
377 | } | |
378 | ||
379 | static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val) | |
380 | { | |
381 | int err; | |
382 | ||
383 | err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, | |
384 | ESR2_TI_PLL_TX_CFG_L(channel), | |
385 | val & 0xffff); | |
386 | if (!err) | |
387 | err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, | |
388 | ESR2_TI_PLL_TX_CFG_H(channel), | |
389 | val >> 16); | |
390 | return err; | |
391 | } | |
392 | ||
393 | static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val) | |
394 | { | |
395 | int err; | |
396 | ||
397 | err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, | |
398 | ESR2_TI_PLL_RX_CFG_L(channel), | |
399 | val & 0xffff); | |
400 | if (!err) | |
401 | err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, | |
402 | ESR2_TI_PLL_RX_CFG_H(channel), | |
403 | val >> 16); | |
404 | return err; | |
405 | } | |
406 | ||
407 | /* Mode is always 10G fiber. */ | |
408 | static int serdes_init_niu(struct niu *np) | |
409 | { | |
410 | struct niu_link_config *lp = &np->link_config; | |
411 | u32 tx_cfg, rx_cfg; | |
412 | unsigned long i; | |
413 | ||
414 | tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV); | |
415 | rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT | | |
416 | PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH | | |
417 | PLL_RX_CFG_EQ_LP_ADAPTIVE); | |
418 | ||
419 | if (lp->loopback_mode == LOOPBACK_PHY) { | |
420 | u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS; | |
421 | ||
422 | mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, | |
423 | ESR2_TI_PLL_TEST_CFG_L, test_cfg); | |
424 | ||
425 | tx_cfg |= PLL_TX_CFG_ENTEST; | |
426 | rx_cfg |= PLL_RX_CFG_ENTEST; | |
427 | } | |
428 | ||
429 | /* Initialize all 4 lanes of the SERDES. */ | |
430 | for (i = 0; i < 4; i++) { | |
431 | int err = esr2_set_tx_cfg(np, i, tx_cfg); | |
432 | if (err) | |
433 | return err; | |
434 | } | |
435 | ||
436 | for (i = 0; i < 4; i++) { | |
437 | int err = esr2_set_rx_cfg(np, i, rx_cfg); | |
438 | if (err) | |
439 | return err; | |
440 | } | |
441 | ||
442 | return 0; | |
443 | } | |
444 | ||
445 | static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val) | |
446 | { | |
447 | int err; | |
448 | ||
449 | err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan)); | |
450 | if (err >= 0) { | |
451 | *val = (err & 0xffff); | |
452 | err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, | |
453 | ESR_RXTX_CTRL_H(chan)); | |
454 | if (err >= 0) | |
455 | *val |= ((err & 0xffff) << 16); | |
456 | err = 0; | |
457 | } | |
458 | return err; | |
459 | } | |
460 | ||
461 | static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val) | |
462 | { | |
463 | int err; | |
464 | ||
465 | err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, | |
466 | ESR_GLUE_CTRL0_L(chan)); | |
467 | if (err >= 0) { | |
468 | *val = (err & 0xffff); | |
469 | err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, | |
470 | ESR_GLUE_CTRL0_H(chan)); | |
471 | if (err >= 0) { | |
472 | *val |= ((err & 0xffff) << 16); | |
473 | err = 0; | |
474 | } | |
475 | } | |
476 | return err; | |
477 | } | |
478 | ||
479 | static int esr_read_reset(struct niu *np, u32 *val) | |
480 | { | |
481 | int err; | |
482 | ||
483 | err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, | |
484 | ESR_RXTX_RESET_CTRL_L); | |
485 | if (err >= 0) { | |
486 | *val = (err & 0xffff); | |
487 | err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, | |
488 | ESR_RXTX_RESET_CTRL_H); | |
489 | if (err >= 0) { | |
490 | *val |= ((err & 0xffff) << 16); | |
491 | err = 0; | |
492 | } | |
493 | } | |
494 | return err; | |
495 | } | |
496 | ||
497 | static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val) | |
498 | { | |
499 | int err; | |
500 | ||
501 | err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, | |
502 | ESR_RXTX_CTRL_L(chan), val & 0xffff); | |
503 | if (!err) | |
504 | err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, | |
505 | ESR_RXTX_CTRL_H(chan), (val >> 16)); | |
506 | return err; | |
507 | } | |
508 | ||
509 | static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val) | |
510 | { | |
511 | int err; | |
512 | ||
513 | err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, | |
514 | ESR_GLUE_CTRL0_L(chan), val & 0xffff); | |
515 | if (!err) | |
516 | err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, | |
517 | ESR_GLUE_CTRL0_H(chan), (val >> 16)); | |
518 | return err; | |
519 | } | |
520 | ||
521 | static int esr_reset(struct niu *np) | |
522 | { | |
523 | u32 reset; | |
524 | int err; | |
525 | ||
526 | err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, | |
527 | ESR_RXTX_RESET_CTRL_L, 0x0000); | |
528 | if (err) | |
529 | return err; | |
530 | err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, | |
531 | ESR_RXTX_RESET_CTRL_H, 0xffff); | |
532 | if (err) | |
533 | return err; | |
534 | udelay(200); | |
535 | ||
536 | err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, | |
537 | ESR_RXTX_RESET_CTRL_L, 0xffff); | |
538 | if (err) | |
539 | return err; | |
540 | udelay(200); | |
541 | ||
542 | err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, | |
543 | ESR_RXTX_RESET_CTRL_H, 0x0000); | |
544 | if (err) | |
545 | return err; | |
546 | udelay(200); | |
547 | ||
548 | err = esr_read_reset(np, &reset); | |
549 | if (err) | |
550 | return err; | |
551 | if (reset != 0) { | |
552 | dev_err(np->device, PFX "Port %u ESR_RESET " | |
553 | "did not clear [%08x]\n", | |
554 | np->port, reset); | |
555 | return -ENODEV; | |
556 | } | |
557 | ||
558 | return 0; | |
559 | } | |
560 | ||
561 | static int serdes_init_10g(struct niu *np) | |
562 | { | |
563 | struct niu_link_config *lp = &np->link_config; | |
564 | unsigned long ctrl_reg, test_cfg_reg, i; | |
565 | u64 ctrl_val, test_cfg_val, sig, mask, val; | |
566 | int err; | |
567 | ||
568 | switch (np->port) { | |
569 | case 0: | |
570 | ctrl_reg = ENET_SERDES_0_CTRL_CFG; | |
571 | test_cfg_reg = ENET_SERDES_0_TEST_CFG; | |
572 | break; | |
573 | case 1: | |
574 | ctrl_reg = ENET_SERDES_1_CTRL_CFG; | |
575 | test_cfg_reg = ENET_SERDES_1_TEST_CFG; | |
576 | break; | |
577 | ||
578 | default: | |
579 | return -EINVAL; | |
580 | } | |
581 | ctrl_val = (ENET_SERDES_CTRL_SDET_0 | | |
582 | ENET_SERDES_CTRL_SDET_1 | | |
583 | ENET_SERDES_CTRL_SDET_2 | | |
584 | ENET_SERDES_CTRL_SDET_3 | | |
585 | (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) | | |
586 | (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) | | |
587 | (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) | | |
588 | (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) | | |
589 | (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) | | |
590 | (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) | | |
591 | (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) | | |
592 | (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT)); | |
593 | test_cfg_val = 0; | |
594 | ||
595 | if (lp->loopback_mode == LOOPBACK_PHY) { | |
596 | test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK << | |
597 | ENET_SERDES_TEST_MD_0_SHIFT) | | |
598 | (ENET_TEST_MD_PAD_LOOPBACK << | |
599 | ENET_SERDES_TEST_MD_1_SHIFT) | | |
600 | (ENET_TEST_MD_PAD_LOOPBACK << | |
601 | ENET_SERDES_TEST_MD_2_SHIFT) | | |
602 | (ENET_TEST_MD_PAD_LOOPBACK << | |
603 | ENET_SERDES_TEST_MD_3_SHIFT)); | |
604 | } | |
605 | ||
606 | nw64(ctrl_reg, ctrl_val); | |
607 | nw64(test_cfg_reg, test_cfg_val); | |
608 | ||
609 | /* Initialize all 4 lanes of the SERDES. */ | |
610 | for (i = 0; i < 4; i++) { | |
611 | u32 rxtx_ctrl, glue0; | |
612 | ||
613 | err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl); | |
614 | if (err) | |
615 | return err; | |
616 | err = esr_read_glue0(np, i, &glue0); | |
617 | if (err) | |
618 | return err; | |
619 | ||
620 | rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO); | |
621 | rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH | | |
622 | (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT)); | |
623 | ||
624 | glue0 &= ~(ESR_GLUE_CTRL0_SRATE | | |
625 | ESR_GLUE_CTRL0_THCNT | | |
626 | ESR_GLUE_CTRL0_BLTIME); | |
627 | glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB | | |
628 | (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) | | |
629 | (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) | | |
630 | (BLTIME_300_CYCLES << | |
631 | ESR_GLUE_CTRL0_BLTIME_SHIFT)); | |
632 | ||
633 | err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl); | |
634 | if (err) | |
635 | return err; | |
636 | err = esr_write_glue0(np, i, glue0); | |
637 | if (err) | |
638 | return err; | |
639 | } | |
640 | ||
641 | err = esr_reset(np); | |
642 | if (err) | |
643 | return err; | |
644 | ||
645 | sig = nr64(ESR_INT_SIGNALS); | |
646 | switch (np->port) { | |
647 | case 0: | |
648 | mask = ESR_INT_SIGNALS_P0_BITS; | |
649 | val = (ESR_INT_SRDY0_P0 | | |
650 | ESR_INT_DET0_P0 | | |
651 | ESR_INT_XSRDY_P0 | | |
652 | ESR_INT_XDP_P0_CH3 | | |
653 | ESR_INT_XDP_P0_CH2 | | |
654 | ESR_INT_XDP_P0_CH1 | | |
655 | ESR_INT_XDP_P0_CH0); | |
656 | break; | |
657 | ||
658 | case 1: | |
659 | mask = ESR_INT_SIGNALS_P1_BITS; | |
660 | val = (ESR_INT_SRDY0_P1 | | |
661 | ESR_INT_DET0_P1 | | |
662 | ESR_INT_XSRDY_P1 | | |
663 | ESR_INT_XDP_P1_CH3 | | |
664 | ESR_INT_XDP_P1_CH2 | | |
665 | ESR_INT_XDP_P1_CH1 | | |
666 | ESR_INT_XDP_P1_CH0); | |
667 | break; | |
668 | ||
669 | default: | |
670 | return -EINVAL; | |
671 | } | |
672 | ||
673 | if ((sig & mask) != val) { | |
674 | dev_err(np->device, PFX "Port %u signal bits [%08x] are not " | |
675 | "[%08x]\n", np->port, (int) (sig & mask), (int) val); | |
676 | return -ENODEV; | |
677 | } | |
678 | ||
679 | return 0; | |
680 | } | |
681 | ||
682 | static int serdes_init_1g(struct niu *np) | |
683 | { | |
684 | u64 val; | |
685 | ||
686 | val = nr64(ENET_SERDES_1_PLL_CFG); | |
687 | val &= ~ENET_SERDES_PLL_FBDIV2; | |
688 | switch (np->port) { | |
689 | case 0: | |
690 | val |= ENET_SERDES_PLL_HRATE0; | |
691 | break; | |
692 | case 1: | |
693 | val |= ENET_SERDES_PLL_HRATE1; | |
694 | break; | |
695 | case 2: | |
696 | val |= ENET_SERDES_PLL_HRATE2; | |
697 | break; | |
698 | case 3: | |
699 | val |= ENET_SERDES_PLL_HRATE3; | |
700 | break; | |
701 | default: | |
702 | return -EINVAL; | |
703 | } | |
704 | nw64(ENET_SERDES_1_PLL_CFG, val); | |
705 | ||
706 | return 0; | |
707 | } | |
708 | ||
709 | static int bcm8704_reset(struct niu *np) | |
710 | { | |
711 | int err, limit; | |
712 | ||
713 | err = mdio_read(np, np->phy_addr, | |
714 | BCM8704_PHYXS_DEV_ADDR, MII_BMCR); | |
715 | if (err < 0) | |
716 | return err; | |
717 | err |= BMCR_RESET; | |
718 | err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, | |
719 | MII_BMCR, err); | |
720 | if (err) | |
721 | return err; | |
722 | ||
723 | limit = 1000; | |
724 | while (--limit >= 0) { | |
725 | err = mdio_read(np, np->phy_addr, | |
726 | BCM8704_PHYXS_DEV_ADDR, MII_BMCR); | |
727 | if (err < 0) | |
728 | return err; | |
729 | if (!(err & BMCR_RESET)) | |
730 | break; | |
731 | } | |
732 | if (limit < 0) { | |
733 | dev_err(np->device, PFX "Port %u PHY will not reset " | |
734 | "(bmcr=%04x)\n", np->port, (err & 0xffff)); | |
735 | return -ENODEV; | |
736 | } | |
737 | return 0; | |
738 | } | |
739 | ||
740 | /* When written, certain PHY registers need to be read back twice | |
741 | * in order for the bits to settle properly. | |
742 | */ | |
743 | static int bcm8704_user_dev3_readback(struct niu *np, int reg) | |
744 | { | |
745 | int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg); | |
746 | if (err < 0) | |
747 | return err; | |
748 | err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg); | |
749 | if (err < 0) | |
750 | return err; | |
751 | return 0; | |
752 | } | |
753 | ||
754 | static int bcm8704_init_user_dev3(struct niu *np) | |
755 | { | |
756 | int err; | |
757 | ||
758 | err = mdio_write(np, np->phy_addr, | |
759 | BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL, | |
760 | (USER_CONTROL_OPTXRST_LVL | | |
761 | USER_CONTROL_OPBIASFLT_LVL | | |
762 | USER_CONTROL_OBTMPFLT_LVL | | |
763 | USER_CONTROL_OPPRFLT_LVL | | |
764 | USER_CONTROL_OPTXFLT_LVL | | |
765 | USER_CONTROL_OPRXLOS_LVL | | |
766 | USER_CONTROL_OPRXFLT_LVL | | |
767 | USER_CONTROL_OPTXON_LVL | | |
768 | (0x3f << USER_CONTROL_RES1_SHIFT))); | |
769 | if (err) | |
770 | return err; | |
771 | ||
772 | err = mdio_write(np, np->phy_addr, | |
773 | BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL, | |
774 | (USER_PMD_TX_CTL_XFP_CLKEN | | |
775 | (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) | | |
776 | (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) | | |
777 | USER_PMD_TX_CTL_TSCK_LPWREN)); | |
778 | if (err) | |
779 | return err; | |
780 | ||
781 | err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL); | |
782 | if (err) | |
783 | return err; | |
784 | err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL); | |
785 | if (err) | |
786 | return err; | |
787 | ||
788 | err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, | |
789 | BCM8704_USER_OPT_DIGITAL_CTRL); | |
790 | if (err < 0) | |
791 | return err; | |
792 | err &= ~USER_ODIG_CTRL_GPIOS; | |
793 | err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT); | |
794 | err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, | |
795 | BCM8704_USER_OPT_DIGITAL_CTRL, err); | |
796 | if (err) | |
797 | return err; | |
798 | ||
799 | mdelay(1000); | |
800 | ||
801 | return 0; | |
802 | } | |
803 | ||
b0de8e40 ML |
804 | static int mrvl88x2011_act_led(struct niu *np, int val) |
805 | { | |
806 | int err; | |
807 | ||
808 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, | |
809 | MRVL88X2011_LED_8_TO_11_CTL); | |
810 | if (err < 0) | |
811 | return err; | |
812 | ||
813 | err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK); | |
814 | err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val); | |
815 | ||
816 | return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, | |
817 | MRVL88X2011_LED_8_TO_11_CTL, err); | |
818 | } | |
819 | ||
820 | static int mrvl88x2011_led_blink_rate(struct niu *np, int rate) | |
821 | { | |
822 | int err; | |
823 | ||
824 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, | |
825 | MRVL88X2011_LED_BLINK_CTL); | |
826 | if (err >= 0) { | |
827 | err &= ~MRVL88X2011_LED_BLKRATE_MASK; | |
828 | err |= (rate << 4); | |
829 | ||
830 | err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, | |
831 | MRVL88X2011_LED_BLINK_CTL, err); | |
832 | } | |
833 | ||
834 | return err; | |
835 | } | |
836 | ||
837 | static int xcvr_init_10g_mrvl88x2011(struct niu *np) | |
838 | { | |
839 | int err; | |
840 | ||
841 | /* Set LED functions */ | |
842 | err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS); | |
843 | if (err) | |
844 | return err; | |
845 | ||
846 | /* led activity */ | |
847 | err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF); | |
848 | if (err) | |
849 | return err; | |
850 | ||
851 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, | |
852 | MRVL88X2011_GENERAL_CTL); | |
853 | if (err < 0) | |
854 | return err; | |
855 | ||
856 | err |= MRVL88X2011_ENA_XFPREFCLK; | |
857 | ||
858 | err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, | |
859 | MRVL88X2011_GENERAL_CTL, err); | |
860 | if (err < 0) | |
861 | return err; | |
862 | ||
863 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, | |
864 | MRVL88X2011_PMA_PMD_CTL_1); | |
865 | if (err < 0) | |
866 | return err; | |
867 | ||
868 | if (np->link_config.loopback_mode == LOOPBACK_MAC) | |
869 | err |= MRVL88X2011_LOOPBACK; | |
870 | else | |
871 | err &= ~MRVL88X2011_LOOPBACK; | |
872 | ||
873 | err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, | |
874 | MRVL88X2011_PMA_PMD_CTL_1, err); | |
875 | if (err < 0) | |
876 | return err; | |
877 | ||
878 | /* Enable PMD */ | |
879 | return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, | |
880 | MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX); | |
881 | } | |
882 | ||
883 | static int xcvr_init_10g_bcm8704(struct niu *np) | |
a3138df9 DM |
884 | { |
885 | struct niu_link_config *lp = &np->link_config; | |
886 | u16 analog_stat0, tx_alarm_status; | |
887 | int err; | |
a3138df9 DM |
888 | |
889 | err = bcm8704_reset(np); | |
890 | if (err) | |
891 | return err; | |
892 | ||
893 | err = bcm8704_init_user_dev3(np); | |
894 | if (err) | |
895 | return err; | |
896 | ||
897 | err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, | |
898 | MII_BMCR); | |
899 | if (err < 0) | |
900 | return err; | |
901 | err &= ~BMCR_LOOPBACK; | |
902 | ||
903 | if (lp->loopback_mode == LOOPBACK_MAC) | |
904 | err |= BMCR_LOOPBACK; | |
905 | ||
906 | err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, | |
907 | MII_BMCR, err); | |
908 | if (err) | |
909 | return err; | |
910 | ||
911 | #if 1 | |
912 | err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR, | |
913 | MII_STAT1000); | |
914 | if (err < 0) | |
915 | return err; | |
916 | pr_info(PFX "Port %u PMA_PMD(MII_STAT1000) [%04x]\n", | |
917 | np->port, err); | |
918 | ||
919 | err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20); | |
920 | if (err < 0) | |
921 | return err; | |
922 | pr_info(PFX "Port %u USER_DEV3(0x20) [%04x]\n", | |
923 | np->port, err); | |
924 | ||
925 | err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, | |
926 | MII_NWAYTEST); | |
927 | if (err < 0) | |
928 | return err; | |
929 | pr_info(PFX "Port %u PHYXS(MII_NWAYTEST) [%04x]\n", | |
930 | np->port, err); | |
931 | #endif | |
932 | ||
933 | /* XXX dig this out it might not be so useful XXX */ | |
934 | err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, | |
935 | BCM8704_USER_ANALOG_STATUS0); | |
936 | if (err < 0) | |
937 | return err; | |
938 | err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, | |
939 | BCM8704_USER_ANALOG_STATUS0); | |
940 | if (err < 0) | |
941 | return err; | |
942 | analog_stat0 = err; | |
943 | ||
944 | err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, | |
945 | BCM8704_USER_TX_ALARM_STATUS); | |
946 | if (err < 0) | |
947 | return err; | |
948 | err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, | |
949 | BCM8704_USER_TX_ALARM_STATUS); | |
950 | if (err < 0) | |
951 | return err; | |
952 | tx_alarm_status = err; | |
953 | ||
954 | if (analog_stat0 != 0x03fc) { | |
955 | if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) { | |
956 | pr_info(PFX "Port %u cable not connected " | |
957 | "or bad cable.\n", np->port); | |
958 | } else if (analog_stat0 == 0x639c) { | |
959 | pr_info(PFX "Port %u optical module is bad " | |
960 | "or missing.\n", np->port); | |
961 | } | |
962 | } | |
963 | ||
964 | return 0; | |
965 | } | |
966 | ||
b0de8e40 ML |
967 | static int xcvr_init_10g(struct niu *np) |
968 | { | |
969 | int phy_id, err; | |
970 | u64 val; | |
971 | ||
972 | val = nr64_mac(XMAC_CONFIG); | |
973 | val &= ~XMAC_CONFIG_LED_POLARITY; | |
974 | val |= XMAC_CONFIG_FORCE_LED_ON; | |
975 | nw64_mac(XMAC_CONFIG, val); | |
976 | ||
977 | /* XXX shared resource, lock parent XXX */ | |
978 | val = nr64(MIF_CONFIG); | |
979 | val |= MIF_CONFIG_INDIRECT_MODE; | |
980 | nw64(MIF_CONFIG, val); | |
981 | ||
982 | phy_id = phy_decode(np->parent->port_phy, np->port); | |
983 | phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port]; | |
984 | ||
985 | /* handle different phy types */ | |
986 | switch (phy_id & NIU_PHY_ID_MASK) { | |
987 | case NIU_PHY_ID_MRVL88X2011: | |
988 | err = xcvr_init_10g_mrvl88x2011(np); | |
989 | break; | |
990 | ||
991 | default: /* bcom 8704 */ | |
992 | err = xcvr_init_10g_bcm8704(np); | |
993 | break; | |
994 | } | |
995 | ||
996 | return 0; | |
997 | } | |
998 | ||
a3138df9 DM |
999 | static int mii_reset(struct niu *np) |
1000 | { | |
1001 | int limit, err; | |
1002 | ||
1003 | err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET); | |
1004 | if (err) | |
1005 | return err; | |
1006 | ||
1007 | limit = 1000; | |
1008 | while (--limit >= 0) { | |
1009 | udelay(500); | |
1010 | err = mii_read(np, np->phy_addr, MII_BMCR); | |
1011 | if (err < 0) | |
1012 | return err; | |
1013 | if (!(err & BMCR_RESET)) | |
1014 | break; | |
1015 | } | |
1016 | if (limit < 0) { | |
1017 | dev_err(np->device, PFX "Port %u MII would not reset, " | |
1018 | "bmcr[%04x]\n", np->port, err); | |
1019 | return -ENODEV; | |
1020 | } | |
1021 | ||
1022 | return 0; | |
1023 | } | |
1024 | ||
1025 | static int mii_init_common(struct niu *np) | |
1026 | { | |
1027 | struct niu_link_config *lp = &np->link_config; | |
1028 | u16 bmcr, bmsr, adv, estat; | |
1029 | int err; | |
1030 | ||
1031 | err = mii_reset(np); | |
1032 | if (err) | |
1033 | return err; | |
1034 | ||
1035 | err = mii_read(np, np->phy_addr, MII_BMSR); | |
1036 | if (err < 0) | |
1037 | return err; | |
1038 | bmsr = err; | |
1039 | ||
1040 | estat = 0; | |
1041 | if (bmsr & BMSR_ESTATEN) { | |
1042 | err = mii_read(np, np->phy_addr, MII_ESTATUS); | |
1043 | if (err < 0) | |
1044 | return err; | |
1045 | estat = err; | |
1046 | } | |
1047 | ||
1048 | bmcr = 0; | |
1049 | err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); | |
1050 | if (err) | |
1051 | return err; | |
1052 | ||
1053 | if (lp->loopback_mode == LOOPBACK_MAC) { | |
1054 | bmcr |= BMCR_LOOPBACK; | |
1055 | if (lp->active_speed == SPEED_1000) | |
1056 | bmcr |= BMCR_SPEED1000; | |
1057 | if (lp->active_duplex == DUPLEX_FULL) | |
1058 | bmcr |= BMCR_FULLDPLX; | |
1059 | } | |
1060 | ||
1061 | if (lp->loopback_mode == LOOPBACK_PHY) { | |
1062 | u16 aux; | |
1063 | ||
1064 | aux = (BCM5464R_AUX_CTL_EXT_LB | | |
1065 | BCM5464R_AUX_CTL_WRITE_1); | |
1066 | err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux); | |
1067 | if (err) | |
1068 | return err; | |
1069 | } | |
1070 | ||
1071 | /* XXX configurable XXX */ | |
1072 | /* XXX for now don't advertise half-duplex or asym pause... XXX */ | |
1073 | adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP; | |
1074 | if (bmsr & BMSR_10FULL) | |
1075 | adv |= ADVERTISE_10FULL; | |
1076 | if (bmsr & BMSR_100FULL) | |
1077 | adv |= ADVERTISE_100FULL; | |
1078 | err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv); | |
1079 | if (err) | |
1080 | return err; | |
1081 | ||
1082 | if (bmsr & BMSR_ESTATEN) { | |
1083 | u16 ctrl1000 = 0; | |
1084 | ||
1085 | if (estat & ESTATUS_1000_TFULL) | |
1086 | ctrl1000 |= ADVERTISE_1000FULL; | |
1087 | err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000); | |
1088 | if (err) | |
1089 | return err; | |
1090 | } | |
1091 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
1092 | ||
1093 | err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); | |
1094 | if (err) | |
1095 | return err; | |
1096 | ||
1097 | err = mii_read(np, np->phy_addr, MII_BMCR); | |
1098 | if (err < 0) | |
1099 | return err; | |
1100 | err = mii_read(np, np->phy_addr, MII_BMSR); | |
1101 | if (err < 0) | |
1102 | return err; | |
1103 | #if 0 | |
1104 | pr_info(PFX "Port %u after MII init bmcr[%04x] bmsr[%04x]\n", | |
1105 | np->port, bmcr, bmsr); | |
1106 | #endif | |
1107 | ||
1108 | return 0; | |
1109 | } | |
1110 | ||
1111 | static int xcvr_init_1g(struct niu *np) | |
1112 | { | |
1113 | u64 val; | |
1114 | ||
1115 | /* XXX shared resource, lock parent XXX */ | |
1116 | val = nr64(MIF_CONFIG); | |
1117 | val &= ~MIF_CONFIG_INDIRECT_MODE; | |
1118 | nw64(MIF_CONFIG, val); | |
1119 | ||
1120 | return mii_init_common(np); | |
1121 | } | |
1122 | ||
1123 | static int niu_xcvr_init(struct niu *np) | |
1124 | { | |
1125 | const struct niu_phy_ops *ops = np->phy_ops; | |
1126 | int err; | |
1127 | ||
1128 | err = 0; | |
1129 | if (ops->xcvr_init) | |
1130 | err = ops->xcvr_init(np); | |
1131 | ||
1132 | return err; | |
1133 | } | |
1134 | ||
1135 | static int niu_serdes_init(struct niu *np) | |
1136 | { | |
1137 | const struct niu_phy_ops *ops = np->phy_ops; | |
1138 | int err; | |
1139 | ||
1140 | err = 0; | |
1141 | if (ops->serdes_init) | |
1142 | err = ops->serdes_init(np); | |
1143 | ||
1144 | return err; | |
1145 | } | |
1146 | ||
1147 | static void niu_init_xif(struct niu *); | |
0c3b091b | 1148 | static void niu_handle_led(struct niu *, int status); |
a3138df9 DM |
1149 | |
1150 | static int niu_link_status_common(struct niu *np, int link_up) | |
1151 | { | |
1152 | struct niu_link_config *lp = &np->link_config; | |
1153 | struct net_device *dev = np->dev; | |
1154 | unsigned long flags; | |
1155 | ||
1156 | if (!netif_carrier_ok(dev) && link_up) { | |
1157 | niuinfo(LINK, "%s: Link is up at %s, %s duplex\n", | |
1158 | dev->name, | |
1159 | (lp->active_speed == SPEED_10000 ? | |
1160 | "10Gb/sec" : | |
1161 | (lp->active_speed == SPEED_1000 ? | |
1162 | "1Gb/sec" : | |
1163 | (lp->active_speed == SPEED_100 ? | |
1164 | "100Mbit/sec" : "10Mbit/sec"))), | |
1165 | (lp->active_duplex == DUPLEX_FULL ? | |
1166 | "full" : "half")); | |
1167 | ||
1168 | spin_lock_irqsave(&np->lock, flags); | |
1169 | niu_init_xif(np); | |
0c3b091b | 1170 | niu_handle_led(np, 1); |
a3138df9 DM |
1171 | spin_unlock_irqrestore(&np->lock, flags); |
1172 | ||
1173 | netif_carrier_on(dev); | |
1174 | } else if (netif_carrier_ok(dev) && !link_up) { | |
1175 | niuwarn(LINK, "%s: Link is down\n", dev->name); | |
0c3b091b ML |
1176 | spin_lock_irqsave(&np->lock, flags); |
1177 | niu_handle_led(np, 0); | |
1178 | spin_unlock_irqrestore(&np->lock, flags); | |
a3138df9 DM |
1179 | netif_carrier_off(dev); |
1180 | } | |
1181 | ||
1182 | return 0; | |
1183 | } | |
1184 | ||
b0de8e40 | 1185 | static int link_status_10g_mrvl(struct niu *np, int *link_up_p) |
a3138df9 | 1186 | { |
b0de8e40 | 1187 | int err, link_up, pma_status, pcs_status; |
a3138df9 DM |
1188 | |
1189 | link_up = 0; | |
1190 | ||
b0de8e40 ML |
1191 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, |
1192 | MRVL88X2011_10G_PMD_STATUS_2); | |
1193 | if (err < 0) | |
1194 | goto out; | |
a3138df9 | 1195 | |
b0de8e40 ML |
1196 | /* Check PMA/PMD Register: 1.0001.2 == 1 */ |
1197 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, | |
1198 | MRVL88X2011_PMA_PMD_STATUS_1); | |
1199 | if (err < 0) | |
1200 | goto out; | |
1201 | ||
1202 | pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0); | |
1203 | ||
1204 | /* Check PMC Register : 3.0001.2 == 1: read twice */ | |
1205 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, | |
1206 | MRVL88X2011_PMA_PMD_STATUS_1); | |
1207 | if (err < 0) | |
1208 | goto out; | |
1209 | ||
1210 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, | |
1211 | MRVL88X2011_PMA_PMD_STATUS_1); | |
1212 | if (err < 0) | |
1213 | goto out; | |
1214 | ||
1215 | pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0); | |
1216 | ||
1217 | /* Check XGXS Register : 4.0018.[0-3,12] */ | |
1218 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR, | |
1219 | MRVL88X2011_10G_XGXS_LANE_STAT); | |
1220 | if (err < 0) | |
a3138df9 DM |
1221 | goto out; |
1222 | ||
b0de8e40 ML |
1223 | if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 | |
1224 | PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 | | |
1225 | PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC | | |
1226 | 0x800)) | |
1227 | link_up = (pma_status && pcs_status) ? 1 : 0; | |
1228 | ||
1229 | np->link_config.active_speed = SPEED_10000; | |
1230 | np->link_config.active_duplex = DUPLEX_FULL; | |
1231 | err = 0; | |
1232 | out: | |
1233 | mrvl88x2011_act_led(np, (link_up ? | |
1234 | MRVL88X2011_LED_CTL_PCS_ACT : | |
1235 | MRVL88X2011_LED_CTL_OFF)); | |
1236 | ||
1237 | *link_up_p = link_up; | |
1238 | return err; | |
1239 | } | |
1240 | ||
1241 | static int link_status_10g_bcom(struct niu *np, int *link_up_p) | |
1242 | { | |
1243 | int err, link_up; | |
1244 | ||
1245 | link_up = 0; | |
1246 | ||
a3138df9 DM |
1247 | err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR, |
1248 | BCM8704_PMD_RCV_SIGDET); | |
1249 | if (err < 0) | |
1250 | goto out; | |
1251 | if (!(err & PMD_RCV_SIGDET_GLOBAL)) { | |
1252 | err = 0; | |
1253 | goto out; | |
1254 | } | |
1255 | ||
1256 | err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, | |
1257 | BCM8704_PCS_10G_R_STATUS); | |
1258 | if (err < 0) | |
1259 | goto out; | |
1260 | if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) { | |
1261 | err = 0; | |
1262 | goto out; | |
1263 | } | |
1264 | ||
1265 | err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, | |
1266 | BCM8704_PHYXS_XGXS_LANE_STAT); | |
1267 | if (err < 0) | |
1268 | goto out; | |
1269 | ||
1270 | if (err != (PHYXS_XGXS_LANE_STAT_ALINGED | | |
1271 | PHYXS_XGXS_LANE_STAT_MAGIC | | |
1272 | PHYXS_XGXS_LANE_STAT_LANE3 | | |
1273 | PHYXS_XGXS_LANE_STAT_LANE2 | | |
1274 | PHYXS_XGXS_LANE_STAT_LANE1 | | |
1275 | PHYXS_XGXS_LANE_STAT_LANE0)) { | |
1276 | err = 0; | |
1277 | goto out; | |
1278 | } | |
1279 | ||
1280 | link_up = 1; | |
1281 | np->link_config.active_speed = SPEED_10000; | |
1282 | np->link_config.active_duplex = DUPLEX_FULL; | |
1283 | err = 0; | |
1284 | ||
1285 | out: | |
b0de8e40 ML |
1286 | *link_up_p = link_up; |
1287 | return err; | |
1288 | } | |
1289 | ||
1290 | static int link_status_10g(struct niu *np, int *link_up_p) | |
1291 | { | |
1292 | unsigned long flags; | |
1293 | int err = -EINVAL; | |
1294 | ||
1295 | spin_lock_irqsave(&np->lock, flags); | |
1296 | ||
1297 | if (np->link_config.loopback_mode == LOOPBACK_DISABLED) { | |
1298 | int phy_id; | |
1299 | ||
1300 | phy_id = phy_decode(np->parent->port_phy, np->port); | |
1301 | phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port]; | |
1302 | ||
1303 | /* handle different phy types */ | |
1304 | switch (phy_id & NIU_PHY_ID_MASK) { | |
1305 | case NIU_PHY_ID_MRVL88X2011: | |
1306 | err = link_status_10g_mrvl(np, link_up_p); | |
1307 | break; | |
1308 | ||
1309 | default: /* bcom 8704 */ | |
1310 | err = link_status_10g_bcom(np, link_up_p); | |
1311 | break; | |
1312 | } | |
1313 | } | |
1314 | ||
a3138df9 DM |
1315 | spin_unlock_irqrestore(&np->lock, flags); |
1316 | ||
a3138df9 DM |
1317 | return err; |
1318 | } | |
1319 | ||
1320 | static int link_status_1g(struct niu *np, int *link_up_p) | |
1321 | { | |
e415e6ea | 1322 | struct niu_link_config *lp = &np->link_config; |
a3138df9 DM |
1323 | u16 current_speed, bmsr; |
1324 | unsigned long flags; | |
1325 | u8 current_duplex; | |
1326 | int err, link_up; | |
1327 | ||
1328 | link_up = 0; | |
1329 | current_speed = SPEED_INVALID; | |
1330 | current_duplex = DUPLEX_INVALID; | |
1331 | ||
1332 | spin_lock_irqsave(&np->lock, flags); | |
1333 | ||
1334 | err = -EINVAL; | |
1335 | if (np->link_config.loopback_mode != LOOPBACK_DISABLED) | |
1336 | goto out; | |
1337 | ||
1338 | err = mii_read(np, np->phy_addr, MII_BMSR); | |
1339 | if (err < 0) | |
1340 | goto out; | |
1341 | ||
1342 | bmsr = err; | |
1343 | if (bmsr & BMSR_LSTATUS) { | |
1344 | u16 adv, lpa, common, estat; | |
1345 | ||
1346 | err = mii_read(np, np->phy_addr, MII_ADVERTISE); | |
1347 | if (err < 0) | |
1348 | goto out; | |
1349 | adv = err; | |
1350 | ||
1351 | err = mii_read(np, np->phy_addr, MII_LPA); | |
1352 | if (err < 0) | |
1353 | goto out; | |
1354 | lpa = err; | |
1355 | ||
1356 | common = adv & lpa; | |
1357 | ||
1358 | err = mii_read(np, np->phy_addr, MII_ESTATUS); | |
1359 | if (err < 0) | |
1360 | goto out; | |
1361 | estat = err; | |
1362 | ||
1363 | link_up = 1; | |
1364 | if (estat & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) { | |
1365 | current_speed = SPEED_1000; | |
1366 | if (estat & ESTATUS_1000_TFULL) | |
1367 | current_duplex = DUPLEX_FULL; | |
1368 | else | |
1369 | current_duplex = DUPLEX_HALF; | |
1370 | } else { | |
1371 | if (common & ADVERTISE_100BASE4) { | |
1372 | current_speed = SPEED_100; | |
1373 | current_duplex = DUPLEX_HALF; | |
1374 | } else if (common & ADVERTISE_100FULL) { | |
1375 | current_speed = SPEED_100; | |
1376 | current_duplex = DUPLEX_FULL; | |
1377 | } else if (common & ADVERTISE_100HALF) { | |
1378 | current_speed = SPEED_100; | |
1379 | current_duplex = DUPLEX_HALF; | |
1380 | } else if (common & ADVERTISE_10FULL) { | |
1381 | current_speed = SPEED_10; | |
1382 | current_duplex = DUPLEX_FULL; | |
1383 | } else if (common & ADVERTISE_10HALF) { | |
1384 | current_speed = SPEED_10; | |
1385 | current_duplex = DUPLEX_HALF; | |
1386 | } else | |
1387 | link_up = 0; | |
1388 | } | |
1389 | } | |
e415e6ea DM |
1390 | lp->active_speed = current_speed; |
1391 | lp->active_duplex = current_duplex; | |
a3138df9 DM |
1392 | err = 0; |
1393 | ||
1394 | out: | |
1395 | spin_unlock_irqrestore(&np->lock, flags); | |
1396 | ||
1397 | *link_up_p = link_up; | |
1398 | return err; | |
1399 | } | |
1400 | ||
1401 | static int niu_link_status(struct niu *np, int *link_up_p) | |
1402 | { | |
1403 | const struct niu_phy_ops *ops = np->phy_ops; | |
1404 | int err; | |
1405 | ||
1406 | err = 0; | |
1407 | if (ops->link_status) | |
1408 | err = ops->link_status(np, link_up_p); | |
1409 | ||
1410 | return err; | |
1411 | } | |
1412 | ||
1413 | static void niu_timer(unsigned long __opaque) | |
1414 | { | |
1415 | struct niu *np = (struct niu *) __opaque; | |
1416 | unsigned long off; | |
1417 | int err, link_up; | |
1418 | ||
1419 | err = niu_link_status(np, &link_up); | |
1420 | if (!err) | |
1421 | niu_link_status_common(np, link_up); | |
1422 | ||
1423 | if (netif_carrier_ok(np->dev)) | |
1424 | off = 5 * HZ; | |
1425 | else | |
1426 | off = 1 * HZ; | |
1427 | np->timer.expires = jiffies + off; | |
1428 | ||
1429 | add_timer(&np->timer); | |
1430 | } | |
1431 | ||
1432 | static const struct niu_phy_ops phy_ops_10g_fiber_niu = { | |
1433 | .serdes_init = serdes_init_niu, | |
1434 | .xcvr_init = xcvr_init_10g, | |
1435 | .link_status = link_status_10g, | |
1436 | }; | |
1437 | ||
1438 | static const struct niu_phy_ops phy_ops_10g_fiber = { | |
1439 | .serdes_init = serdes_init_10g, | |
1440 | .xcvr_init = xcvr_init_10g, | |
1441 | .link_status = link_status_10g, | |
1442 | }; | |
1443 | ||
1444 | static const struct niu_phy_ops phy_ops_10g_copper = { | |
1445 | .serdes_init = serdes_init_10g, | |
1446 | .link_status = link_status_10g, /* XXX */ | |
1447 | }; | |
1448 | ||
1449 | static const struct niu_phy_ops phy_ops_1g_fiber = { | |
1450 | .serdes_init = serdes_init_1g, | |
1451 | .xcvr_init = xcvr_init_1g, | |
1452 | .link_status = link_status_1g, | |
1453 | }; | |
1454 | ||
1455 | static const struct niu_phy_ops phy_ops_1g_copper = { | |
1456 | .xcvr_init = xcvr_init_1g, | |
1457 | .link_status = link_status_1g, | |
1458 | }; | |
1459 | ||
1460 | struct niu_phy_template { | |
1461 | const struct niu_phy_ops *ops; | |
1462 | u32 phy_addr_base; | |
1463 | }; | |
1464 | ||
1465 | static const struct niu_phy_template phy_template_niu = { | |
1466 | .ops = &phy_ops_10g_fiber_niu, | |
1467 | .phy_addr_base = 16, | |
1468 | }; | |
1469 | ||
1470 | static const struct niu_phy_template phy_template_10g_fiber = { | |
1471 | .ops = &phy_ops_10g_fiber, | |
1472 | .phy_addr_base = 8, | |
1473 | }; | |
1474 | ||
1475 | static const struct niu_phy_template phy_template_10g_copper = { | |
1476 | .ops = &phy_ops_10g_copper, | |
1477 | .phy_addr_base = 10, | |
1478 | }; | |
1479 | ||
1480 | static const struct niu_phy_template phy_template_1g_fiber = { | |
1481 | .ops = &phy_ops_1g_fiber, | |
1482 | .phy_addr_base = 0, | |
1483 | }; | |
1484 | ||
1485 | static const struct niu_phy_template phy_template_1g_copper = { | |
1486 | .ops = &phy_ops_1g_copper, | |
1487 | .phy_addr_base = 0, | |
1488 | }; | |
1489 | ||
1490 | static int niu_determine_phy_disposition(struct niu *np) | |
1491 | { | |
1492 | struct niu_parent *parent = np->parent; | |
1493 | u8 plat_type = parent->plat_type; | |
1494 | const struct niu_phy_template *tp; | |
1495 | u32 phy_addr_off = 0; | |
1496 | ||
1497 | if (plat_type == PLAT_TYPE_NIU) { | |
1498 | tp = &phy_template_niu; | |
1499 | phy_addr_off += np->port; | |
1500 | } else { | |
1501 | switch (np->flags & (NIU_FLAGS_10G | NIU_FLAGS_FIBER)) { | |
1502 | case 0: | |
1503 | /* 1G copper */ | |
1504 | tp = &phy_template_1g_copper; | |
1505 | if (plat_type == PLAT_TYPE_VF_P0) | |
1506 | phy_addr_off = 10; | |
1507 | else if (plat_type == PLAT_TYPE_VF_P1) | |
1508 | phy_addr_off = 26; | |
1509 | ||
1510 | phy_addr_off += (np->port ^ 0x3); | |
1511 | break; | |
1512 | ||
1513 | case NIU_FLAGS_10G: | |
1514 | /* 10G copper */ | |
1515 | tp = &phy_template_1g_copper; | |
1516 | break; | |
1517 | ||
1518 | case NIU_FLAGS_FIBER: | |
1519 | /* 1G fiber */ | |
1520 | tp = &phy_template_1g_fiber; | |
1521 | break; | |
1522 | ||
1523 | case NIU_FLAGS_10G | NIU_FLAGS_FIBER: | |
1524 | /* 10G fiber */ | |
1525 | tp = &phy_template_10g_fiber; | |
1526 | if (plat_type == PLAT_TYPE_VF_P0 || | |
1527 | plat_type == PLAT_TYPE_VF_P1) | |
1528 | phy_addr_off = 8; | |
1529 | phy_addr_off += np->port; | |
1530 | break; | |
1531 | ||
1532 | default: | |
1533 | return -EINVAL; | |
1534 | } | |
1535 | } | |
1536 | ||
1537 | np->phy_ops = tp->ops; | |
1538 | np->phy_addr = tp->phy_addr_base + phy_addr_off; | |
1539 | ||
1540 | return 0; | |
1541 | } | |
1542 | ||
1543 | static int niu_init_link(struct niu *np) | |
1544 | { | |
1545 | struct niu_parent *parent = np->parent; | |
1546 | int err, ignore; | |
1547 | ||
1548 | if (parent->plat_type == PLAT_TYPE_NIU) { | |
1549 | err = niu_xcvr_init(np); | |
1550 | if (err) | |
1551 | return err; | |
1552 | msleep(200); | |
1553 | } | |
1554 | err = niu_serdes_init(np); | |
1555 | if (err) | |
1556 | return err; | |
1557 | msleep(200); | |
1558 | err = niu_xcvr_init(np); | |
1559 | if (!err) | |
1560 | niu_link_status(np, &ignore); | |
1561 | return 0; | |
1562 | } | |
1563 | ||
1564 | static void niu_set_primary_mac(struct niu *np, unsigned char *addr) | |
1565 | { | |
1566 | u16 reg0 = addr[4] << 8 | addr[5]; | |
1567 | u16 reg1 = addr[2] << 8 | addr[3]; | |
1568 | u16 reg2 = addr[0] << 8 | addr[1]; | |
1569 | ||
1570 | if (np->flags & NIU_FLAGS_XMAC) { | |
1571 | nw64_mac(XMAC_ADDR0, reg0); | |
1572 | nw64_mac(XMAC_ADDR1, reg1); | |
1573 | nw64_mac(XMAC_ADDR2, reg2); | |
1574 | } else { | |
1575 | nw64_mac(BMAC_ADDR0, reg0); | |
1576 | nw64_mac(BMAC_ADDR1, reg1); | |
1577 | nw64_mac(BMAC_ADDR2, reg2); | |
1578 | } | |
1579 | } | |
1580 | ||
1581 | static int niu_num_alt_addr(struct niu *np) | |
1582 | { | |
1583 | if (np->flags & NIU_FLAGS_XMAC) | |
1584 | return XMAC_NUM_ALT_ADDR; | |
1585 | else | |
1586 | return BMAC_NUM_ALT_ADDR; | |
1587 | } | |
1588 | ||
1589 | static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr) | |
1590 | { | |
1591 | u16 reg0 = addr[4] << 8 | addr[5]; | |
1592 | u16 reg1 = addr[2] << 8 | addr[3]; | |
1593 | u16 reg2 = addr[0] << 8 | addr[1]; | |
1594 | ||
1595 | if (index >= niu_num_alt_addr(np)) | |
1596 | return -EINVAL; | |
1597 | ||
1598 | if (np->flags & NIU_FLAGS_XMAC) { | |
1599 | nw64_mac(XMAC_ALT_ADDR0(index), reg0); | |
1600 | nw64_mac(XMAC_ALT_ADDR1(index), reg1); | |
1601 | nw64_mac(XMAC_ALT_ADDR2(index), reg2); | |
1602 | } else { | |
1603 | nw64_mac(BMAC_ALT_ADDR0(index), reg0); | |
1604 | nw64_mac(BMAC_ALT_ADDR1(index), reg1); | |
1605 | nw64_mac(BMAC_ALT_ADDR2(index), reg2); | |
1606 | } | |
1607 | ||
1608 | return 0; | |
1609 | } | |
1610 | ||
1611 | static int niu_enable_alt_mac(struct niu *np, int index, int on) | |
1612 | { | |
1613 | unsigned long reg; | |
1614 | u64 val, mask; | |
1615 | ||
1616 | if (index >= niu_num_alt_addr(np)) | |
1617 | return -EINVAL; | |
1618 | ||
fa907895 | 1619 | if (np->flags & NIU_FLAGS_XMAC) { |
a3138df9 | 1620 | reg = XMAC_ADDR_CMPEN; |
fa907895 MW |
1621 | mask = 1 << index; |
1622 | } else { | |
a3138df9 | 1623 | reg = BMAC_ADDR_CMPEN; |
fa907895 MW |
1624 | mask = 1 << (index + 1); |
1625 | } | |
a3138df9 DM |
1626 | |
1627 | val = nr64_mac(reg); | |
1628 | if (on) | |
1629 | val |= mask; | |
1630 | else | |
1631 | val &= ~mask; | |
1632 | nw64_mac(reg, val); | |
1633 | ||
1634 | return 0; | |
1635 | } | |
1636 | ||
1637 | static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg, | |
1638 | int num, int mac_pref) | |
1639 | { | |
1640 | u64 val = nr64_mac(reg); | |
1641 | val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR); | |
1642 | val |= num; | |
1643 | if (mac_pref) | |
1644 | val |= HOST_INFO_MPR; | |
1645 | nw64_mac(reg, val); | |
1646 | } | |
1647 | ||
1648 | static int __set_rdc_table_num(struct niu *np, | |
1649 | int xmac_index, int bmac_index, | |
1650 | int rdc_table_num, int mac_pref) | |
1651 | { | |
1652 | unsigned long reg; | |
1653 | ||
1654 | if (rdc_table_num & ~HOST_INFO_MACRDCTBLN) | |
1655 | return -EINVAL; | |
1656 | if (np->flags & NIU_FLAGS_XMAC) | |
1657 | reg = XMAC_HOST_INFO(xmac_index); | |
1658 | else | |
1659 | reg = BMAC_HOST_INFO(bmac_index); | |
1660 | __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref); | |
1661 | return 0; | |
1662 | } | |
1663 | ||
1664 | static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num, | |
1665 | int mac_pref) | |
1666 | { | |
1667 | return __set_rdc_table_num(np, 17, 0, table_num, mac_pref); | |
1668 | } | |
1669 | ||
1670 | static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num, | |
1671 | int mac_pref) | |
1672 | { | |
1673 | return __set_rdc_table_num(np, 16, 8, table_num, mac_pref); | |
1674 | } | |
1675 | ||
1676 | static int niu_set_alt_mac_rdc_table(struct niu *np, int idx, | |
1677 | int table_num, int mac_pref) | |
1678 | { | |
1679 | if (idx >= niu_num_alt_addr(np)) | |
1680 | return -EINVAL; | |
1681 | return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref); | |
1682 | } | |
1683 | ||
1684 | static u64 vlan_entry_set_parity(u64 reg_val) | |
1685 | { | |
1686 | u64 port01_mask; | |
1687 | u64 port23_mask; | |
1688 | ||
1689 | port01_mask = 0x00ff; | |
1690 | port23_mask = 0xff00; | |
1691 | ||
1692 | if (hweight64(reg_val & port01_mask) & 1) | |
1693 | reg_val |= ENET_VLAN_TBL_PARITY0; | |
1694 | else | |
1695 | reg_val &= ~ENET_VLAN_TBL_PARITY0; | |
1696 | ||
1697 | if (hweight64(reg_val & port23_mask) & 1) | |
1698 | reg_val |= ENET_VLAN_TBL_PARITY1; | |
1699 | else | |
1700 | reg_val &= ~ENET_VLAN_TBL_PARITY1; | |
1701 | ||
1702 | return reg_val; | |
1703 | } | |
1704 | ||
1705 | static void vlan_tbl_write(struct niu *np, unsigned long index, | |
1706 | int port, int vpr, int rdc_table) | |
1707 | { | |
1708 | u64 reg_val = nr64(ENET_VLAN_TBL(index)); | |
1709 | ||
1710 | reg_val &= ~((ENET_VLAN_TBL_VPR | | |
1711 | ENET_VLAN_TBL_VLANRDCTBLN) << | |
1712 | ENET_VLAN_TBL_SHIFT(port)); | |
1713 | if (vpr) | |
1714 | reg_val |= (ENET_VLAN_TBL_VPR << | |
1715 | ENET_VLAN_TBL_SHIFT(port)); | |
1716 | reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port)); | |
1717 | ||
1718 | reg_val = vlan_entry_set_parity(reg_val); | |
1719 | ||
1720 | nw64(ENET_VLAN_TBL(index), reg_val); | |
1721 | } | |
1722 | ||
1723 | static void vlan_tbl_clear(struct niu *np) | |
1724 | { | |
1725 | int i; | |
1726 | ||
1727 | for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) | |
1728 | nw64(ENET_VLAN_TBL(i), 0); | |
1729 | } | |
1730 | ||
1731 | static int tcam_wait_bit(struct niu *np, u64 bit) | |
1732 | { | |
1733 | int limit = 1000; | |
1734 | ||
1735 | while (--limit > 0) { | |
1736 | if (nr64(TCAM_CTL) & bit) | |
1737 | break; | |
1738 | udelay(1); | |
1739 | } | |
1740 | if (limit < 0) | |
1741 | return -ENODEV; | |
1742 | ||
1743 | return 0; | |
1744 | } | |
1745 | ||
1746 | static int tcam_flush(struct niu *np, int index) | |
1747 | { | |
1748 | nw64(TCAM_KEY_0, 0x00); | |
1749 | nw64(TCAM_KEY_MASK_0, 0xff); | |
1750 | nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index)); | |
1751 | ||
1752 | return tcam_wait_bit(np, TCAM_CTL_STAT); | |
1753 | } | |
1754 | ||
1755 | #if 0 | |
1756 | static int tcam_read(struct niu *np, int index, | |
1757 | u64 *key, u64 *mask) | |
1758 | { | |
1759 | int err; | |
1760 | ||
1761 | nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index)); | |
1762 | err = tcam_wait_bit(np, TCAM_CTL_STAT); | |
1763 | if (!err) { | |
1764 | key[0] = nr64(TCAM_KEY_0); | |
1765 | key[1] = nr64(TCAM_KEY_1); | |
1766 | key[2] = nr64(TCAM_KEY_2); | |
1767 | key[3] = nr64(TCAM_KEY_3); | |
1768 | mask[0] = nr64(TCAM_KEY_MASK_0); | |
1769 | mask[1] = nr64(TCAM_KEY_MASK_1); | |
1770 | mask[2] = nr64(TCAM_KEY_MASK_2); | |
1771 | mask[3] = nr64(TCAM_KEY_MASK_3); | |
1772 | } | |
1773 | return err; | |
1774 | } | |
1775 | #endif | |
1776 | ||
1777 | static int tcam_write(struct niu *np, int index, | |
1778 | u64 *key, u64 *mask) | |
1779 | { | |
1780 | nw64(TCAM_KEY_0, key[0]); | |
1781 | nw64(TCAM_KEY_1, key[1]); | |
1782 | nw64(TCAM_KEY_2, key[2]); | |
1783 | nw64(TCAM_KEY_3, key[3]); | |
1784 | nw64(TCAM_KEY_MASK_0, mask[0]); | |
1785 | nw64(TCAM_KEY_MASK_1, mask[1]); | |
1786 | nw64(TCAM_KEY_MASK_2, mask[2]); | |
1787 | nw64(TCAM_KEY_MASK_3, mask[3]); | |
1788 | nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index)); | |
1789 | ||
1790 | return tcam_wait_bit(np, TCAM_CTL_STAT); | |
1791 | } | |
1792 | ||
1793 | #if 0 | |
1794 | static int tcam_assoc_read(struct niu *np, int index, u64 *data) | |
1795 | { | |
1796 | int err; | |
1797 | ||
1798 | nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index)); | |
1799 | err = tcam_wait_bit(np, TCAM_CTL_STAT); | |
1800 | if (!err) | |
1801 | *data = nr64(TCAM_KEY_1); | |
1802 | ||
1803 | return err; | |
1804 | } | |
1805 | #endif | |
1806 | ||
1807 | static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data) | |
1808 | { | |
1809 | nw64(TCAM_KEY_1, assoc_data); | |
1810 | nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index)); | |
1811 | ||
1812 | return tcam_wait_bit(np, TCAM_CTL_STAT); | |
1813 | } | |
1814 | ||
1815 | static void tcam_enable(struct niu *np, int on) | |
1816 | { | |
1817 | u64 val = nr64(FFLP_CFG_1); | |
1818 | ||
1819 | if (on) | |
1820 | val &= ~FFLP_CFG_1_TCAM_DIS; | |
1821 | else | |
1822 | val |= FFLP_CFG_1_TCAM_DIS; | |
1823 | nw64(FFLP_CFG_1, val); | |
1824 | } | |
1825 | ||
1826 | static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio) | |
1827 | { | |
1828 | u64 val = nr64(FFLP_CFG_1); | |
1829 | ||
1830 | val &= ~(FFLP_CFG_1_FFLPINITDONE | | |
1831 | FFLP_CFG_1_CAMLAT | | |
1832 | FFLP_CFG_1_CAMRATIO); | |
1833 | val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT); | |
1834 | val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT); | |
1835 | nw64(FFLP_CFG_1, val); | |
1836 | ||
1837 | val = nr64(FFLP_CFG_1); | |
1838 | val |= FFLP_CFG_1_FFLPINITDONE; | |
1839 | nw64(FFLP_CFG_1, val); | |
1840 | } | |
1841 | ||
1842 | static int tcam_user_eth_class_enable(struct niu *np, unsigned long class, | |
1843 | int on) | |
1844 | { | |
1845 | unsigned long reg; | |
1846 | u64 val; | |
1847 | ||
1848 | if (class < CLASS_CODE_ETHERTYPE1 || | |
1849 | class > CLASS_CODE_ETHERTYPE2) | |
1850 | return -EINVAL; | |
1851 | ||
1852 | reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1); | |
1853 | val = nr64(reg); | |
1854 | if (on) | |
1855 | val |= L2_CLS_VLD; | |
1856 | else | |
1857 | val &= ~L2_CLS_VLD; | |
1858 | nw64(reg, val); | |
1859 | ||
1860 | return 0; | |
1861 | } | |
1862 | ||
1863 | #if 0 | |
1864 | static int tcam_user_eth_class_set(struct niu *np, unsigned long class, | |
1865 | u64 ether_type) | |
1866 | { | |
1867 | unsigned long reg; | |
1868 | u64 val; | |
1869 | ||
1870 | if (class < CLASS_CODE_ETHERTYPE1 || | |
1871 | class > CLASS_CODE_ETHERTYPE2 || | |
1872 | (ether_type & ~(u64)0xffff) != 0) | |
1873 | return -EINVAL; | |
1874 | ||
1875 | reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1); | |
1876 | val = nr64(reg); | |
1877 | val &= ~L2_CLS_ETYPE; | |
1878 | val |= (ether_type << L2_CLS_ETYPE_SHIFT); | |
1879 | nw64(reg, val); | |
1880 | ||
1881 | return 0; | |
1882 | } | |
1883 | #endif | |
1884 | ||
1885 | static int tcam_user_ip_class_enable(struct niu *np, unsigned long class, | |
1886 | int on) | |
1887 | { | |
1888 | unsigned long reg; | |
1889 | u64 val; | |
1890 | ||
1891 | if (class < CLASS_CODE_USER_PROG1 || | |
1892 | class > CLASS_CODE_USER_PROG4) | |
1893 | return -EINVAL; | |
1894 | ||
1895 | reg = L3_CLS(class - CLASS_CODE_USER_PROG1); | |
1896 | val = nr64(reg); | |
1897 | if (on) | |
1898 | val |= L3_CLS_VALID; | |
1899 | else | |
1900 | val &= ~L3_CLS_VALID; | |
1901 | nw64(reg, val); | |
1902 | ||
1903 | return 0; | |
1904 | } | |
1905 | ||
1906 | #if 0 | |
1907 | static int tcam_user_ip_class_set(struct niu *np, unsigned long class, | |
1908 | int ipv6, u64 protocol_id, | |
1909 | u64 tos_mask, u64 tos_val) | |
1910 | { | |
1911 | unsigned long reg; | |
1912 | u64 val; | |
1913 | ||
1914 | if (class < CLASS_CODE_USER_PROG1 || | |
1915 | class > CLASS_CODE_USER_PROG4 || | |
1916 | (protocol_id & ~(u64)0xff) != 0 || | |
1917 | (tos_mask & ~(u64)0xff) != 0 || | |
1918 | (tos_val & ~(u64)0xff) != 0) | |
1919 | return -EINVAL; | |
1920 | ||
1921 | reg = L3_CLS(class - CLASS_CODE_USER_PROG1); | |
1922 | val = nr64(reg); | |
1923 | val &= ~(L3_CLS_IPVER | L3_CLS_PID | | |
1924 | L3_CLS_TOSMASK | L3_CLS_TOS); | |
1925 | if (ipv6) | |
1926 | val |= L3_CLS_IPVER; | |
1927 | val |= (protocol_id << L3_CLS_PID_SHIFT); | |
1928 | val |= (tos_mask << L3_CLS_TOSMASK_SHIFT); | |
1929 | val |= (tos_val << L3_CLS_TOS_SHIFT); | |
1930 | nw64(reg, val); | |
1931 | ||
1932 | return 0; | |
1933 | } | |
1934 | #endif | |
1935 | ||
1936 | static int tcam_early_init(struct niu *np) | |
1937 | { | |
1938 | unsigned long i; | |
1939 | int err; | |
1940 | ||
1941 | tcam_enable(np, 0); | |
1942 | tcam_set_lat_and_ratio(np, | |
1943 | DEFAULT_TCAM_LATENCY, | |
1944 | DEFAULT_TCAM_ACCESS_RATIO); | |
1945 | for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) { | |
1946 | err = tcam_user_eth_class_enable(np, i, 0); | |
1947 | if (err) | |
1948 | return err; | |
1949 | } | |
1950 | for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) { | |
1951 | err = tcam_user_ip_class_enable(np, i, 0); | |
1952 | if (err) | |
1953 | return err; | |
1954 | } | |
1955 | ||
1956 | return 0; | |
1957 | } | |
1958 | ||
1959 | static int tcam_flush_all(struct niu *np) | |
1960 | { | |
1961 | unsigned long i; | |
1962 | ||
1963 | for (i = 0; i < np->parent->tcam_num_entries; i++) { | |
1964 | int err = tcam_flush(np, i); | |
1965 | if (err) | |
1966 | return err; | |
1967 | } | |
1968 | return 0; | |
1969 | } | |
1970 | ||
1971 | static u64 hash_addr_regval(unsigned long index, unsigned long num_entries) | |
1972 | { | |
1973 | return ((u64)index | (num_entries == 1 ? | |
1974 | HASH_TBL_ADDR_AUTOINC : 0)); | |
1975 | } | |
1976 | ||
1977 | #if 0 | |
1978 | static int hash_read(struct niu *np, unsigned long partition, | |
1979 | unsigned long index, unsigned long num_entries, | |
1980 | u64 *data) | |
1981 | { | |
1982 | u64 val = hash_addr_regval(index, num_entries); | |
1983 | unsigned long i; | |
1984 | ||
1985 | if (partition >= FCRAM_NUM_PARTITIONS || | |
1986 | index + num_entries > FCRAM_SIZE) | |
1987 | return -EINVAL; | |
1988 | ||
1989 | nw64(HASH_TBL_ADDR(partition), val); | |
1990 | for (i = 0; i < num_entries; i++) | |
1991 | data[i] = nr64(HASH_TBL_DATA(partition)); | |
1992 | ||
1993 | return 0; | |
1994 | } | |
1995 | #endif | |
1996 | ||
1997 | static int hash_write(struct niu *np, unsigned long partition, | |
1998 | unsigned long index, unsigned long num_entries, | |
1999 | u64 *data) | |
2000 | { | |
2001 | u64 val = hash_addr_regval(index, num_entries); | |
2002 | unsigned long i; | |
2003 | ||
2004 | if (partition >= FCRAM_NUM_PARTITIONS || | |
2005 | index + (num_entries * 8) > FCRAM_SIZE) | |
2006 | return -EINVAL; | |
2007 | ||
2008 | nw64(HASH_TBL_ADDR(partition), val); | |
2009 | for (i = 0; i < num_entries; i++) | |
2010 | nw64(HASH_TBL_DATA(partition), data[i]); | |
2011 | ||
2012 | return 0; | |
2013 | } | |
2014 | ||
2015 | static void fflp_reset(struct niu *np) | |
2016 | { | |
2017 | u64 val; | |
2018 | ||
2019 | nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST); | |
2020 | udelay(10); | |
2021 | nw64(FFLP_CFG_1, 0); | |
2022 | ||
2023 | val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE; | |
2024 | nw64(FFLP_CFG_1, val); | |
2025 | } | |
2026 | ||
2027 | static void fflp_set_timings(struct niu *np) | |
2028 | { | |
2029 | u64 val = nr64(FFLP_CFG_1); | |
2030 | ||
2031 | val &= ~FFLP_CFG_1_FFLPINITDONE; | |
2032 | val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT); | |
2033 | nw64(FFLP_CFG_1, val); | |
2034 | ||
2035 | val = nr64(FFLP_CFG_1); | |
2036 | val |= FFLP_CFG_1_FFLPINITDONE; | |
2037 | nw64(FFLP_CFG_1, val); | |
2038 | ||
2039 | val = nr64(FCRAM_REF_TMR); | |
2040 | val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN); | |
2041 | val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT); | |
2042 | val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT); | |
2043 | nw64(FCRAM_REF_TMR, val); | |
2044 | } | |
2045 | ||
2046 | static int fflp_set_partition(struct niu *np, u64 partition, | |
2047 | u64 mask, u64 base, int enable) | |
2048 | { | |
2049 | unsigned long reg; | |
2050 | u64 val; | |
2051 | ||
2052 | if (partition >= FCRAM_NUM_PARTITIONS || | |
2053 | (mask & ~(u64)0x1f) != 0 || | |
2054 | (base & ~(u64)0x1f) != 0) | |
2055 | return -EINVAL; | |
2056 | ||
2057 | reg = FLW_PRT_SEL(partition); | |
2058 | ||
2059 | val = nr64(reg); | |
2060 | val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE); | |
2061 | val |= (mask << FLW_PRT_SEL_MASK_SHIFT); | |
2062 | val |= (base << FLW_PRT_SEL_BASE_SHIFT); | |
2063 | if (enable) | |
2064 | val |= FLW_PRT_SEL_EXT; | |
2065 | nw64(reg, val); | |
2066 | ||
2067 | return 0; | |
2068 | } | |
2069 | ||
2070 | static int fflp_disable_all_partitions(struct niu *np) | |
2071 | { | |
2072 | unsigned long i; | |
2073 | ||
2074 | for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) { | |
2075 | int err = fflp_set_partition(np, 0, 0, 0, 0); | |
2076 | if (err) | |
2077 | return err; | |
2078 | } | |
2079 | return 0; | |
2080 | } | |
2081 | ||
2082 | static void fflp_llcsnap_enable(struct niu *np, int on) | |
2083 | { | |
2084 | u64 val = nr64(FFLP_CFG_1); | |
2085 | ||
2086 | if (on) | |
2087 | val |= FFLP_CFG_1_LLCSNAP; | |
2088 | else | |
2089 | val &= ~FFLP_CFG_1_LLCSNAP; | |
2090 | nw64(FFLP_CFG_1, val); | |
2091 | } | |
2092 | ||
2093 | static void fflp_errors_enable(struct niu *np, int on) | |
2094 | { | |
2095 | u64 val = nr64(FFLP_CFG_1); | |
2096 | ||
2097 | if (on) | |
2098 | val &= ~FFLP_CFG_1_ERRORDIS; | |
2099 | else | |
2100 | val |= FFLP_CFG_1_ERRORDIS; | |
2101 | nw64(FFLP_CFG_1, val); | |
2102 | } | |
2103 | ||
2104 | static int fflp_hash_clear(struct niu *np) | |
2105 | { | |
2106 | struct fcram_hash_ipv4 ent; | |
2107 | unsigned long i; | |
2108 | ||
2109 | /* IPV4 hash entry with valid bit clear, rest is don't care. */ | |
2110 | memset(&ent, 0, sizeof(ent)); | |
2111 | ent.header = HASH_HEADER_EXT; | |
2112 | ||
2113 | for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) { | |
2114 | int err = hash_write(np, 0, i, 1, (u64 *) &ent); | |
2115 | if (err) | |
2116 | return err; | |
2117 | } | |
2118 | return 0; | |
2119 | } | |
2120 | ||
2121 | static int fflp_early_init(struct niu *np) | |
2122 | { | |
2123 | struct niu_parent *parent; | |
2124 | unsigned long flags; | |
2125 | int err; | |
2126 | ||
2127 | niu_lock_parent(np, flags); | |
2128 | ||
2129 | parent = np->parent; | |
2130 | err = 0; | |
2131 | if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) { | |
2132 | niudbg(PROBE, "fflp_early_init: Initting hw on port %u\n", | |
2133 | np->port); | |
2134 | if (np->parent->plat_type != PLAT_TYPE_NIU) { | |
2135 | fflp_reset(np); | |
2136 | fflp_set_timings(np); | |
2137 | err = fflp_disable_all_partitions(np); | |
2138 | if (err) { | |
2139 | niudbg(PROBE, "fflp_disable_all_partitions " | |
2140 | "failed, err=%d\n", err); | |
2141 | goto out; | |
2142 | } | |
2143 | } | |
2144 | ||
2145 | err = tcam_early_init(np); | |
2146 | if (err) { | |
2147 | niudbg(PROBE, "tcam_early_init failed, err=%d\n", | |
2148 | err); | |
2149 | goto out; | |
2150 | } | |
2151 | fflp_llcsnap_enable(np, 1); | |
2152 | fflp_errors_enable(np, 0); | |
2153 | nw64(H1POLY, 0); | |
2154 | nw64(H2POLY, 0); | |
2155 | ||
2156 | err = tcam_flush_all(np); | |
2157 | if (err) { | |
2158 | niudbg(PROBE, "tcam_flush_all failed, err=%d\n", | |
2159 | err); | |
2160 | goto out; | |
2161 | } | |
2162 | if (np->parent->plat_type != PLAT_TYPE_NIU) { | |
2163 | err = fflp_hash_clear(np); | |
2164 | if (err) { | |
2165 | niudbg(PROBE, "fflp_hash_clear failed, " | |
2166 | "err=%d\n", err); | |
2167 | goto out; | |
2168 | } | |
2169 | } | |
2170 | ||
2171 | vlan_tbl_clear(np); | |
2172 | ||
2173 | niudbg(PROBE, "fflp_early_init: Success\n"); | |
2174 | parent->flags |= PARENT_FLGS_CLS_HWINIT; | |
2175 | } | |
2176 | out: | |
2177 | niu_unlock_parent(np, flags); | |
2178 | return err; | |
2179 | } | |
2180 | ||
2181 | static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key) | |
2182 | { | |
2183 | if (class_code < CLASS_CODE_USER_PROG1 || | |
2184 | class_code > CLASS_CODE_SCTP_IPV6) | |
2185 | return -EINVAL; | |
2186 | ||
2187 | nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key); | |
2188 | return 0; | |
2189 | } | |
2190 | ||
2191 | static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key) | |
2192 | { | |
2193 | if (class_code < CLASS_CODE_USER_PROG1 || | |
2194 | class_code > CLASS_CODE_SCTP_IPV6) | |
2195 | return -EINVAL; | |
2196 | ||
2197 | nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key); | |
2198 | return 0; | |
2199 | } | |
2200 | ||
2201 | static void niu_rx_skb_append(struct sk_buff *skb, struct page *page, | |
2202 | u32 offset, u32 size) | |
2203 | { | |
2204 | int i = skb_shinfo(skb)->nr_frags; | |
2205 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
2206 | ||
2207 | frag->page = page; | |
2208 | frag->page_offset = offset; | |
2209 | frag->size = size; | |
2210 | ||
2211 | skb->len += size; | |
2212 | skb->data_len += size; | |
2213 | skb->truesize += size; | |
2214 | ||
2215 | skb_shinfo(skb)->nr_frags = i + 1; | |
2216 | } | |
2217 | ||
2218 | static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a) | |
2219 | { | |
2220 | a >>= PAGE_SHIFT; | |
2221 | a ^= (a >> ilog2(MAX_RBR_RING_SIZE)); | |
2222 | ||
2223 | return (a & (MAX_RBR_RING_SIZE - 1)); | |
2224 | } | |
2225 | ||
2226 | static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr, | |
2227 | struct page ***link) | |
2228 | { | |
2229 | unsigned int h = niu_hash_rxaddr(rp, addr); | |
2230 | struct page *p, **pp; | |
2231 | ||
2232 | addr &= PAGE_MASK; | |
2233 | pp = &rp->rxhash[h]; | |
2234 | for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) { | |
2235 | if (p->index == addr) { | |
2236 | *link = pp; | |
2237 | break; | |
2238 | } | |
2239 | } | |
2240 | ||
2241 | return p; | |
2242 | } | |
2243 | ||
2244 | static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base) | |
2245 | { | |
2246 | unsigned int h = niu_hash_rxaddr(rp, base); | |
2247 | ||
2248 | page->index = base; | |
2249 | page->mapping = (struct address_space *) rp->rxhash[h]; | |
2250 | rp->rxhash[h] = page; | |
2251 | } | |
2252 | ||
2253 | static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp, | |
2254 | gfp_t mask, int start_index) | |
2255 | { | |
2256 | struct page *page; | |
2257 | u64 addr; | |
2258 | int i; | |
2259 | ||
2260 | page = alloc_page(mask); | |
2261 | if (!page) | |
2262 | return -ENOMEM; | |
2263 | ||
2264 | addr = np->ops->map_page(np->device, page, 0, | |
2265 | PAGE_SIZE, DMA_FROM_DEVICE); | |
2266 | ||
2267 | niu_hash_page(rp, page, addr); | |
2268 | if (rp->rbr_blocks_per_page > 1) | |
2269 | atomic_add(rp->rbr_blocks_per_page - 1, | |
2270 | &compound_head(page)->_count); | |
2271 | ||
2272 | for (i = 0; i < rp->rbr_blocks_per_page; i++) { | |
2273 | __le32 *rbr = &rp->rbr[start_index + i]; | |
2274 | ||
2275 | *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT); | |
2276 | addr += rp->rbr_block_size; | |
2277 | } | |
2278 | ||
2279 | return 0; | |
2280 | } | |
2281 | ||
2282 | static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask) | |
2283 | { | |
2284 | int index = rp->rbr_index; | |
2285 | ||
2286 | rp->rbr_pending++; | |
2287 | if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) { | |
2288 | int err = niu_rbr_add_page(np, rp, mask, index); | |
2289 | ||
2290 | if (unlikely(err)) { | |
2291 | rp->rbr_pending--; | |
2292 | return; | |
2293 | } | |
2294 | ||
2295 | rp->rbr_index += rp->rbr_blocks_per_page; | |
2296 | BUG_ON(rp->rbr_index > rp->rbr_table_size); | |
2297 | if (rp->rbr_index == rp->rbr_table_size) | |
2298 | rp->rbr_index = 0; | |
2299 | ||
2300 | if (rp->rbr_pending >= rp->rbr_kick_thresh) { | |
2301 | nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending); | |
2302 | rp->rbr_pending = 0; | |
2303 | } | |
2304 | } | |
2305 | } | |
2306 | ||
2307 | static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp) | |
2308 | { | |
2309 | unsigned int index = rp->rcr_index; | |
2310 | int num_rcr = 0; | |
2311 | ||
2312 | rp->rx_dropped++; | |
2313 | while (1) { | |
2314 | struct page *page, **link; | |
2315 | u64 addr, val; | |
2316 | u32 rcr_size; | |
2317 | ||
2318 | num_rcr++; | |
2319 | ||
2320 | val = le64_to_cpup(&rp->rcr[index]); | |
2321 | addr = (val & RCR_ENTRY_PKT_BUF_ADDR) << | |
2322 | RCR_ENTRY_PKT_BUF_ADDR_SHIFT; | |
2323 | page = niu_find_rxpage(rp, addr, &link); | |
2324 | ||
2325 | rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >> | |
2326 | RCR_ENTRY_PKTBUFSZ_SHIFT]; | |
2327 | if ((page->index + PAGE_SIZE) - rcr_size == addr) { | |
2328 | *link = (struct page *) page->mapping; | |
2329 | np->ops->unmap_page(np->device, page->index, | |
2330 | PAGE_SIZE, DMA_FROM_DEVICE); | |
2331 | page->index = 0; | |
2332 | page->mapping = NULL; | |
2333 | __free_page(page); | |
2334 | rp->rbr_refill_pending++; | |
2335 | } | |
2336 | ||
2337 | index = NEXT_RCR(rp, index); | |
2338 | if (!(val & RCR_ENTRY_MULTI)) | |
2339 | break; | |
2340 | ||
2341 | } | |
2342 | rp->rcr_index = index; | |
2343 | ||
2344 | return num_rcr; | |
2345 | } | |
2346 | ||
2347 | static int niu_process_rx_pkt(struct niu *np, struct rx_ring_info *rp) | |
2348 | { | |
2349 | unsigned int index = rp->rcr_index; | |
2350 | struct sk_buff *skb; | |
2351 | int len, num_rcr; | |
2352 | ||
2353 | skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE); | |
2354 | if (unlikely(!skb)) | |
2355 | return niu_rx_pkt_ignore(np, rp); | |
2356 | ||
2357 | num_rcr = 0; | |
2358 | while (1) { | |
2359 | struct page *page, **link; | |
2360 | u32 rcr_size, append_size; | |
2361 | u64 addr, val, off; | |
2362 | ||
2363 | num_rcr++; | |
2364 | ||
2365 | val = le64_to_cpup(&rp->rcr[index]); | |
2366 | ||
2367 | len = (val & RCR_ENTRY_L2_LEN) >> | |
2368 | RCR_ENTRY_L2_LEN_SHIFT; | |
2369 | len -= ETH_FCS_LEN; | |
2370 | ||
2371 | addr = (val & RCR_ENTRY_PKT_BUF_ADDR) << | |
2372 | RCR_ENTRY_PKT_BUF_ADDR_SHIFT; | |
2373 | page = niu_find_rxpage(rp, addr, &link); | |
2374 | ||
2375 | rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >> | |
2376 | RCR_ENTRY_PKTBUFSZ_SHIFT]; | |
2377 | ||
2378 | off = addr & ~PAGE_MASK; | |
2379 | append_size = rcr_size; | |
2380 | if (num_rcr == 1) { | |
2381 | int ptype; | |
2382 | ||
2383 | off += 2; | |
2384 | append_size -= 2; | |
2385 | ||
2386 | ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT); | |
2387 | if ((ptype == RCR_PKT_TYPE_TCP || | |
2388 | ptype == RCR_PKT_TYPE_UDP) && | |
2389 | !(val & (RCR_ENTRY_NOPORT | | |
2390 | RCR_ENTRY_ERROR))) | |
2391 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
2392 | else | |
2393 | skb->ip_summed = CHECKSUM_NONE; | |
2394 | } | |
2395 | if (!(val & RCR_ENTRY_MULTI)) | |
2396 | append_size = len - skb->len; | |
2397 | ||
2398 | niu_rx_skb_append(skb, page, off, append_size); | |
2399 | if ((page->index + rp->rbr_block_size) - rcr_size == addr) { | |
2400 | *link = (struct page *) page->mapping; | |
2401 | np->ops->unmap_page(np->device, page->index, | |
2402 | PAGE_SIZE, DMA_FROM_DEVICE); | |
2403 | page->index = 0; | |
2404 | page->mapping = NULL; | |
2405 | rp->rbr_refill_pending++; | |
2406 | } else | |
2407 | get_page(page); | |
2408 | ||
2409 | index = NEXT_RCR(rp, index); | |
2410 | if (!(val & RCR_ENTRY_MULTI)) | |
2411 | break; | |
2412 | ||
2413 | } | |
2414 | rp->rcr_index = index; | |
2415 | ||
2416 | skb_reserve(skb, NET_IP_ALIGN); | |
2417 | __pskb_pull_tail(skb, min(len, NIU_RXPULL_MAX)); | |
2418 | ||
2419 | rp->rx_packets++; | |
2420 | rp->rx_bytes += skb->len; | |
2421 | ||
2422 | skb->protocol = eth_type_trans(skb, np->dev); | |
2423 | netif_receive_skb(skb); | |
2424 | ||
792dd90f DM |
2425 | np->dev->last_rx = jiffies; |
2426 | ||
a3138df9 DM |
2427 | return num_rcr; |
2428 | } | |
2429 | ||
2430 | static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask) | |
2431 | { | |
2432 | int blocks_per_page = rp->rbr_blocks_per_page; | |
2433 | int err, index = rp->rbr_index; | |
2434 | ||
2435 | err = 0; | |
2436 | while (index < (rp->rbr_table_size - blocks_per_page)) { | |
2437 | err = niu_rbr_add_page(np, rp, mask, index); | |
2438 | if (err) | |
2439 | break; | |
2440 | ||
2441 | index += blocks_per_page; | |
2442 | } | |
2443 | ||
2444 | rp->rbr_index = index; | |
2445 | return err; | |
2446 | } | |
2447 | ||
2448 | static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp) | |
2449 | { | |
2450 | int i; | |
2451 | ||
2452 | for (i = 0; i < MAX_RBR_RING_SIZE; i++) { | |
2453 | struct page *page; | |
2454 | ||
2455 | page = rp->rxhash[i]; | |
2456 | while (page) { | |
2457 | struct page *next = (struct page *) page->mapping; | |
2458 | u64 base = page->index; | |
2459 | ||
2460 | np->ops->unmap_page(np->device, base, PAGE_SIZE, | |
2461 | DMA_FROM_DEVICE); | |
2462 | page->index = 0; | |
2463 | page->mapping = NULL; | |
2464 | ||
2465 | __free_page(page); | |
2466 | ||
2467 | page = next; | |
2468 | } | |
2469 | } | |
2470 | ||
2471 | for (i = 0; i < rp->rbr_table_size; i++) | |
2472 | rp->rbr[i] = cpu_to_le32(0); | |
2473 | rp->rbr_index = 0; | |
2474 | } | |
2475 | ||
2476 | static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx) | |
2477 | { | |
2478 | struct tx_buff_info *tb = &rp->tx_buffs[idx]; | |
2479 | struct sk_buff *skb = tb->skb; | |
2480 | struct tx_pkt_hdr *tp; | |
2481 | u64 tx_flags; | |
2482 | int i, len; | |
2483 | ||
2484 | tp = (struct tx_pkt_hdr *) skb->data; | |
2485 | tx_flags = le64_to_cpup(&tp->flags); | |
2486 | ||
2487 | rp->tx_packets++; | |
2488 | rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) - | |
2489 | ((tx_flags & TXHDR_PAD) / 2)); | |
2490 | ||
2491 | len = skb_headlen(skb); | |
2492 | np->ops->unmap_single(np->device, tb->mapping, | |
2493 | len, DMA_TO_DEVICE); | |
2494 | ||
2495 | if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK) | |
2496 | rp->mark_pending--; | |
2497 | ||
2498 | tb->skb = NULL; | |
2499 | do { | |
2500 | idx = NEXT_TX(rp, idx); | |
2501 | len -= MAX_TX_DESC_LEN; | |
2502 | } while (len > 0); | |
2503 | ||
2504 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
2505 | tb = &rp->tx_buffs[idx]; | |
2506 | BUG_ON(tb->skb != NULL); | |
2507 | np->ops->unmap_page(np->device, tb->mapping, | |
2508 | skb_shinfo(skb)->frags[i].size, | |
2509 | DMA_TO_DEVICE); | |
2510 | idx = NEXT_TX(rp, idx); | |
2511 | } | |
2512 | ||
2513 | dev_kfree_skb(skb); | |
2514 | ||
2515 | return idx; | |
2516 | } | |
2517 | ||
2518 | #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4) | |
2519 | ||
2520 | static void niu_tx_work(struct niu *np, struct tx_ring_info *rp) | |
2521 | { | |
2522 | u16 pkt_cnt, tmp; | |
2523 | int cons; | |
2524 | u64 cs; | |
2525 | ||
2526 | cs = rp->tx_cs; | |
2527 | if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK)))) | |
2528 | goto out; | |
2529 | ||
2530 | tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT; | |
2531 | pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) & | |
2532 | (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT); | |
2533 | ||
2534 | rp->last_pkt_cnt = tmp; | |
2535 | ||
2536 | cons = rp->cons; | |
2537 | ||
2538 | niudbg(TX_DONE, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n", | |
2539 | np->dev->name, pkt_cnt, cons); | |
2540 | ||
2541 | while (pkt_cnt--) | |
2542 | cons = release_tx_packet(np, rp, cons); | |
2543 | ||
2544 | rp->cons = cons; | |
2545 | smp_mb(); | |
2546 | ||
2547 | out: | |
2548 | if (unlikely(netif_queue_stopped(np->dev) && | |
2549 | (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) { | |
2550 | netif_tx_lock(np->dev); | |
2551 | if (netif_queue_stopped(np->dev) && | |
2552 | (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))) | |
2553 | netif_wake_queue(np->dev); | |
2554 | netif_tx_unlock(np->dev); | |
2555 | } | |
2556 | } | |
2557 | ||
2558 | static int niu_rx_work(struct niu *np, struct rx_ring_info *rp, int budget) | |
2559 | { | |
2560 | int qlen, rcr_done = 0, work_done = 0; | |
2561 | struct rxdma_mailbox *mbox = rp->mbox; | |
2562 | u64 stat; | |
2563 | ||
2564 | #if 1 | |
2565 | stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel)); | |
2566 | qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN; | |
2567 | #else | |
2568 | stat = le64_to_cpup(&mbox->rx_dma_ctl_stat); | |
2569 | qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN); | |
2570 | #endif | |
2571 | mbox->rx_dma_ctl_stat = 0; | |
2572 | mbox->rcrstat_a = 0; | |
2573 | ||
2574 | niudbg(RX_STATUS, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n", | |
2575 | np->dev->name, rp->rx_channel, (unsigned long long) stat, qlen); | |
2576 | ||
2577 | rcr_done = work_done = 0; | |
2578 | qlen = min(qlen, budget); | |
2579 | while (work_done < qlen) { | |
2580 | rcr_done += niu_process_rx_pkt(np, rp); | |
2581 | work_done++; | |
2582 | } | |
2583 | ||
2584 | if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) { | |
2585 | unsigned int i; | |
2586 | ||
2587 | for (i = 0; i < rp->rbr_refill_pending; i++) | |
2588 | niu_rbr_refill(np, rp, GFP_ATOMIC); | |
2589 | rp->rbr_refill_pending = 0; | |
2590 | } | |
2591 | ||
2592 | stat = (RX_DMA_CTL_STAT_MEX | | |
2593 | ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) | | |
2594 | ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT)); | |
2595 | ||
2596 | nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat); | |
2597 | ||
2598 | return work_done; | |
2599 | } | |
2600 | ||
2601 | static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget) | |
2602 | { | |
2603 | u64 v0 = lp->v0; | |
2604 | u32 tx_vec = (v0 >> 32); | |
2605 | u32 rx_vec = (v0 & 0xffffffff); | |
2606 | int i, work_done = 0; | |
2607 | ||
2608 | niudbg(INTR, "%s: niu_poll_core() v0[%016llx]\n", | |
2609 | np->dev->name, (unsigned long long) v0); | |
2610 | ||
2611 | for (i = 0; i < np->num_tx_rings; i++) { | |
2612 | struct tx_ring_info *rp = &np->tx_rings[i]; | |
2613 | if (tx_vec & (1 << rp->tx_channel)) | |
2614 | niu_tx_work(np, rp); | |
2615 | nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0); | |
2616 | } | |
2617 | ||
2618 | for (i = 0; i < np->num_rx_rings; i++) { | |
2619 | struct rx_ring_info *rp = &np->rx_rings[i]; | |
2620 | ||
2621 | if (rx_vec & (1 << rp->rx_channel)) { | |
2622 | int this_work_done; | |
2623 | ||
2624 | this_work_done = niu_rx_work(np, rp, | |
2625 | budget); | |
2626 | ||
2627 | budget -= this_work_done; | |
2628 | work_done += this_work_done; | |
2629 | } | |
2630 | nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0); | |
2631 | } | |
2632 | ||
2633 | return work_done; | |
2634 | } | |
2635 | ||
2636 | static int niu_poll(struct napi_struct *napi, int budget) | |
2637 | { | |
2638 | struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi); | |
2639 | struct niu *np = lp->np; | |
2640 | int work_done; | |
2641 | ||
2642 | work_done = niu_poll_core(np, lp, budget); | |
2643 | ||
2644 | if (work_done < budget) { | |
2645 | netif_rx_complete(np->dev, napi); | |
2646 | niu_ldg_rearm(np, lp, 1); | |
2647 | } | |
2648 | return work_done; | |
2649 | } | |
2650 | ||
2651 | static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp, | |
2652 | u64 stat) | |
2653 | { | |
2654 | dev_err(np->device, PFX "%s: RX channel %u errors ( ", | |
2655 | np->dev->name, rp->rx_channel); | |
2656 | ||
2657 | if (stat & RX_DMA_CTL_STAT_RBR_TMOUT) | |
2658 | printk("RBR_TMOUT "); | |
2659 | if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR) | |
2660 | printk("RSP_CNT "); | |
2661 | if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS) | |
2662 | printk("BYTE_EN_BUS "); | |
2663 | if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR) | |
2664 | printk("RSP_DAT "); | |
2665 | if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR) | |
2666 | printk("RCR_ACK "); | |
2667 | if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR) | |
2668 | printk("RCR_SHA_PAR "); | |
2669 | if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR) | |
2670 | printk("RBR_PRE_PAR "); | |
2671 | if (stat & RX_DMA_CTL_STAT_CONFIG_ERR) | |
2672 | printk("CONFIG "); | |
2673 | if (stat & RX_DMA_CTL_STAT_RCRINCON) | |
2674 | printk("RCRINCON "); | |
2675 | if (stat & RX_DMA_CTL_STAT_RCRFULL) | |
2676 | printk("RCRFULL "); | |
2677 | if (stat & RX_DMA_CTL_STAT_RBRFULL) | |
2678 | printk("RBRFULL "); | |
2679 | if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE) | |
2680 | printk("RBRLOGPAGE "); | |
2681 | if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE) | |
2682 | printk("CFIGLOGPAGE "); | |
2683 | if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR) | |
2684 | printk("DC_FIDO "); | |
2685 | ||
2686 | printk(")\n"); | |
2687 | } | |
2688 | ||
2689 | static int niu_rx_error(struct niu *np, struct rx_ring_info *rp) | |
2690 | { | |
2691 | u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel)); | |
2692 | int err = 0; | |
2693 | ||
a3138df9 DM |
2694 | |
2695 | if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL | | |
2696 | RX_DMA_CTL_STAT_PORT_FATAL)) | |
2697 | err = -EINVAL; | |
2698 | ||
406f353c MW |
2699 | if (err) { |
2700 | dev_err(np->device, PFX "%s: RX channel %u error, stat[%llx]\n", | |
2701 | np->dev->name, rp->rx_channel, | |
2702 | (unsigned long long) stat); | |
2703 | ||
2704 | niu_log_rxchan_errors(np, rp, stat); | |
2705 | } | |
2706 | ||
a3138df9 DM |
2707 | nw64(RX_DMA_CTL_STAT(rp->rx_channel), |
2708 | stat & RX_DMA_CTL_WRITE_CLEAR_ERRS); | |
2709 | ||
2710 | return err; | |
2711 | } | |
2712 | ||
2713 | static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp, | |
2714 | u64 cs) | |
2715 | { | |
2716 | dev_err(np->device, PFX "%s: TX channel %u errors ( ", | |
2717 | np->dev->name, rp->tx_channel); | |
2718 | ||
2719 | if (cs & TX_CS_MBOX_ERR) | |
2720 | printk("MBOX "); | |
2721 | if (cs & TX_CS_PKT_SIZE_ERR) | |
2722 | printk("PKT_SIZE "); | |
2723 | if (cs & TX_CS_TX_RING_OFLOW) | |
2724 | printk("TX_RING_OFLOW "); | |
2725 | if (cs & TX_CS_PREF_BUF_PAR_ERR) | |
2726 | printk("PREF_BUF_PAR "); | |
2727 | if (cs & TX_CS_NACK_PREF) | |
2728 | printk("NACK_PREF "); | |
2729 | if (cs & TX_CS_NACK_PKT_RD) | |
2730 | printk("NACK_PKT_RD "); | |
2731 | if (cs & TX_CS_CONF_PART_ERR) | |
2732 | printk("CONF_PART "); | |
2733 | if (cs & TX_CS_PKT_PRT_ERR) | |
2734 | printk("PKT_PTR "); | |
2735 | ||
2736 | printk(")\n"); | |
2737 | } | |
2738 | ||
2739 | static int niu_tx_error(struct niu *np, struct tx_ring_info *rp) | |
2740 | { | |
2741 | u64 cs, logh, logl; | |
2742 | ||
2743 | cs = nr64(TX_CS(rp->tx_channel)); | |
2744 | logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel)); | |
2745 | logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel)); | |
2746 | ||
2747 | dev_err(np->device, PFX "%s: TX channel %u error, " | |
2748 | "cs[%llx] logh[%llx] logl[%llx]\n", | |
2749 | np->dev->name, rp->tx_channel, | |
2750 | (unsigned long long) cs, | |
2751 | (unsigned long long) logh, | |
2752 | (unsigned long long) logl); | |
2753 | ||
2754 | niu_log_txchan_errors(np, rp, cs); | |
2755 | ||
2756 | return -ENODEV; | |
2757 | } | |
2758 | ||
2759 | static int niu_mif_interrupt(struct niu *np) | |
2760 | { | |
2761 | u64 mif_status = nr64(MIF_STATUS); | |
2762 | int phy_mdint = 0; | |
2763 | ||
2764 | if (np->flags & NIU_FLAGS_XMAC) { | |
2765 | u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS); | |
2766 | ||
2767 | if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT) | |
2768 | phy_mdint = 1; | |
2769 | } | |
2770 | ||
2771 | dev_err(np->device, PFX "%s: MIF interrupt, " | |
2772 | "stat[%llx] phy_mdint(%d)\n", | |
2773 | np->dev->name, (unsigned long long) mif_status, phy_mdint); | |
2774 | ||
2775 | return -ENODEV; | |
2776 | } | |
2777 | ||
2778 | static void niu_xmac_interrupt(struct niu *np) | |
2779 | { | |
2780 | struct niu_xmac_stats *mp = &np->mac_stats.xmac; | |
2781 | u64 val; | |
2782 | ||
2783 | val = nr64_mac(XTXMAC_STATUS); | |
2784 | if (val & XTXMAC_STATUS_FRAME_CNT_EXP) | |
2785 | mp->tx_frames += TXMAC_FRM_CNT_COUNT; | |
2786 | if (val & XTXMAC_STATUS_BYTE_CNT_EXP) | |
2787 | mp->tx_bytes += TXMAC_BYTE_CNT_COUNT; | |
2788 | if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR) | |
2789 | mp->tx_fifo_errors++; | |
2790 | if (val & XTXMAC_STATUS_TXMAC_OFLOW) | |
2791 | mp->tx_overflow_errors++; | |
2792 | if (val & XTXMAC_STATUS_MAX_PSIZE_ERR) | |
2793 | mp->tx_max_pkt_size_errors++; | |
2794 | if (val & XTXMAC_STATUS_TXMAC_UFLOW) | |
2795 | mp->tx_underflow_errors++; | |
2796 | ||
2797 | val = nr64_mac(XRXMAC_STATUS); | |
2798 | if (val & XRXMAC_STATUS_LCL_FLT_STATUS) | |
2799 | mp->rx_local_faults++; | |
2800 | if (val & XRXMAC_STATUS_RFLT_DET) | |
2801 | mp->rx_remote_faults++; | |
2802 | if (val & XRXMAC_STATUS_LFLT_CNT_EXP) | |
2803 | mp->rx_link_faults += LINK_FAULT_CNT_COUNT; | |
2804 | if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP) | |
2805 | mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT; | |
2806 | if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP) | |
2807 | mp->rx_frags += RXMAC_FRAG_CNT_COUNT; | |
2808 | if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP) | |
2809 | mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT; | |
2810 | if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP) | |
2811 | mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT; | |
2812 | if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP) | |
2813 | mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT; | |
2814 | if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP) | |
2815 | mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT; | |
2816 | if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP) | |
2817 | mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT; | |
2818 | if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP) | |
2819 | mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT; | |
2820 | if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP) | |
2821 | mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT; | |
2822 | if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP) | |
2823 | mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT; | |
2824 | if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP) | |
2825 | mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT; | |
2826 | if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP) | |
2827 | mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT; | |
2828 | if (val & XRXMAC_STAT_MSK_RXOCTET_CNT_EXP) | |
2829 | mp->rx_octets += RXMAC_BT_CNT_COUNT; | |
2830 | if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP) | |
2831 | mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT; | |
2832 | if (val & XRXMAC_STATUS_LENERR_CNT_EXP) | |
2833 | mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT; | |
2834 | if (val & XRXMAC_STATUS_CRCERR_CNT_EXP) | |
2835 | mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT; | |
2836 | if (val & XRXMAC_STATUS_RXUFLOW) | |
2837 | mp->rx_underflows++; | |
2838 | if (val & XRXMAC_STATUS_RXOFLOW) | |
2839 | mp->rx_overflows++; | |
2840 | ||
2841 | val = nr64_mac(XMAC_FC_STAT); | |
2842 | if (val & XMAC_FC_STAT_TX_MAC_NPAUSE) | |
2843 | mp->pause_off_state++; | |
2844 | if (val & XMAC_FC_STAT_TX_MAC_PAUSE) | |
2845 | mp->pause_on_state++; | |
2846 | if (val & XMAC_FC_STAT_RX_MAC_RPAUSE) | |
2847 | mp->pause_received++; | |
2848 | } | |
2849 | ||
2850 | static void niu_bmac_interrupt(struct niu *np) | |
2851 | { | |
2852 | struct niu_bmac_stats *mp = &np->mac_stats.bmac; | |
2853 | u64 val; | |
2854 | ||
2855 | val = nr64_mac(BTXMAC_STATUS); | |
2856 | if (val & BTXMAC_STATUS_UNDERRUN) | |
2857 | mp->tx_underflow_errors++; | |
2858 | if (val & BTXMAC_STATUS_MAX_PKT_ERR) | |
2859 | mp->tx_max_pkt_size_errors++; | |
2860 | if (val & BTXMAC_STATUS_BYTE_CNT_EXP) | |
2861 | mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT; | |
2862 | if (val & BTXMAC_STATUS_FRAME_CNT_EXP) | |
2863 | mp->tx_frames += BTXMAC_FRM_CNT_COUNT; | |
2864 | ||
2865 | val = nr64_mac(BRXMAC_STATUS); | |
2866 | if (val & BRXMAC_STATUS_OVERFLOW) | |
2867 | mp->rx_overflows++; | |
2868 | if (val & BRXMAC_STATUS_FRAME_CNT_EXP) | |
2869 | mp->rx_frames += BRXMAC_FRAME_CNT_COUNT; | |
2870 | if (val & BRXMAC_STATUS_ALIGN_ERR_EXP) | |
2871 | mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT; | |
2872 | if (val & BRXMAC_STATUS_CRC_ERR_EXP) | |
2873 | mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT; | |
2874 | if (val & BRXMAC_STATUS_LEN_ERR_EXP) | |
2875 | mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT; | |
2876 | ||
2877 | val = nr64_mac(BMAC_CTRL_STATUS); | |
2878 | if (val & BMAC_CTRL_STATUS_NOPAUSE) | |
2879 | mp->pause_off_state++; | |
2880 | if (val & BMAC_CTRL_STATUS_PAUSE) | |
2881 | mp->pause_on_state++; | |
2882 | if (val & BMAC_CTRL_STATUS_PAUSE_RECV) | |
2883 | mp->pause_received++; | |
2884 | } | |
2885 | ||
2886 | static int niu_mac_interrupt(struct niu *np) | |
2887 | { | |
2888 | if (np->flags & NIU_FLAGS_XMAC) | |
2889 | niu_xmac_interrupt(np); | |
2890 | else | |
2891 | niu_bmac_interrupt(np); | |
2892 | ||
2893 | return 0; | |
2894 | } | |
2895 | ||
2896 | static void niu_log_device_error(struct niu *np, u64 stat) | |
2897 | { | |
2898 | dev_err(np->device, PFX "%s: Core device errors ( ", | |
2899 | np->dev->name); | |
2900 | ||
2901 | if (stat & SYS_ERR_MASK_META2) | |
2902 | printk("META2 "); | |
2903 | if (stat & SYS_ERR_MASK_META1) | |
2904 | printk("META1 "); | |
2905 | if (stat & SYS_ERR_MASK_PEU) | |
2906 | printk("PEU "); | |
2907 | if (stat & SYS_ERR_MASK_TXC) | |
2908 | printk("TXC "); | |
2909 | if (stat & SYS_ERR_MASK_RDMC) | |
2910 | printk("RDMC "); | |
2911 | if (stat & SYS_ERR_MASK_TDMC) | |
2912 | printk("TDMC "); | |
2913 | if (stat & SYS_ERR_MASK_ZCP) | |
2914 | printk("ZCP "); | |
2915 | if (stat & SYS_ERR_MASK_FFLP) | |
2916 | printk("FFLP "); | |
2917 | if (stat & SYS_ERR_MASK_IPP) | |
2918 | printk("IPP "); | |
2919 | if (stat & SYS_ERR_MASK_MAC) | |
2920 | printk("MAC "); | |
2921 | if (stat & SYS_ERR_MASK_SMX) | |
2922 | printk("SMX "); | |
2923 | ||
2924 | printk(")\n"); | |
2925 | } | |
2926 | ||
2927 | static int niu_device_error(struct niu *np) | |
2928 | { | |
2929 | u64 stat = nr64(SYS_ERR_STAT); | |
2930 | ||
2931 | dev_err(np->device, PFX "%s: Core device error, stat[%llx]\n", | |
2932 | np->dev->name, (unsigned long long) stat); | |
2933 | ||
2934 | niu_log_device_error(np, stat); | |
2935 | ||
2936 | return -ENODEV; | |
2937 | } | |
2938 | ||
406f353c MW |
2939 | static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp, |
2940 | u64 v0, u64 v1, u64 v2) | |
a3138df9 | 2941 | { |
406f353c | 2942 | |
a3138df9 DM |
2943 | int i, err = 0; |
2944 | ||
406f353c MW |
2945 | lp->v0 = v0; |
2946 | lp->v1 = v1; | |
2947 | lp->v2 = v2; | |
2948 | ||
a3138df9 DM |
2949 | if (v1 & 0x00000000ffffffffULL) { |
2950 | u32 rx_vec = (v1 & 0xffffffff); | |
2951 | ||
2952 | for (i = 0; i < np->num_rx_rings; i++) { | |
2953 | struct rx_ring_info *rp = &np->rx_rings[i]; | |
2954 | ||
2955 | if (rx_vec & (1 << rp->rx_channel)) { | |
2956 | int r = niu_rx_error(np, rp); | |
406f353c | 2957 | if (r) { |
a3138df9 | 2958 | err = r; |
406f353c MW |
2959 | } else { |
2960 | if (!v0) | |
2961 | nw64(RX_DMA_CTL_STAT(rp->rx_channel), | |
2962 | RX_DMA_CTL_STAT_MEX); | |
2963 | } | |
a3138df9 DM |
2964 | } |
2965 | } | |
2966 | } | |
2967 | if (v1 & 0x7fffffff00000000ULL) { | |
2968 | u32 tx_vec = (v1 >> 32) & 0x7fffffff; | |
2969 | ||
2970 | for (i = 0; i < np->num_tx_rings; i++) { | |
2971 | struct tx_ring_info *rp = &np->tx_rings[i]; | |
2972 | ||
2973 | if (tx_vec & (1 << rp->tx_channel)) { | |
2974 | int r = niu_tx_error(np, rp); | |
2975 | if (r) | |
2976 | err = r; | |
2977 | } | |
2978 | } | |
2979 | } | |
2980 | if ((v0 | v1) & 0x8000000000000000ULL) { | |
2981 | int r = niu_mif_interrupt(np); | |
2982 | if (r) | |
2983 | err = r; | |
2984 | } | |
2985 | if (v2) { | |
2986 | if (v2 & 0x01ef) { | |
2987 | int r = niu_mac_interrupt(np); | |
2988 | if (r) | |
2989 | err = r; | |
2990 | } | |
2991 | if (v2 & 0x0210) { | |
2992 | int r = niu_device_error(np); | |
2993 | if (r) | |
2994 | err = r; | |
2995 | } | |
2996 | } | |
2997 | ||
2998 | if (err) | |
2999 | niu_enable_interrupts(np, 0); | |
3000 | ||
406f353c | 3001 | return err; |
a3138df9 DM |
3002 | } |
3003 | ||
3004 | static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp, | |
3005 | int ldn) | |
3006 | { | |
3007 | struct rxdma_mailbox *mbox = rp->mbox; | |
3008 | u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat); | |
3009 | ||
3010 | stat_write = (RX_DMA_CTL_STAT_RCRTHRES | | |
3011 | RX_DMA_CTL_STAT_RCRTO); | |
3012 | nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write); | |
3013 | ||
3014 | niudbg(INTR, "%s: rxchan_intr stat[%llx]\n", | |
3015 | np->dev->name, (unsigned long long) stat); | |
3016 | } | |
3017 | ||
3018 | static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp, | |
3019 | int ldn) | |
3020 | { | |
3021 | rp->tx_cs = nr64(TX_CS(rp->tx_channel)); | |
3022 | ||
3023 | niudbg(INTR, "%s: txchan_intr cs[%llx]\n", | |
3024 | np->dev->name, (unsigned long long) rp->tx_cs); | |
3025 | } | |
3026 | ||
3027 | static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0) | |
3028 | { | |
3029 | struct niu_parent *parent = np->parent; | |
3030 | u32 rx_vec, tx_vec; | |
3031 | int i; | |
3032 | ||
3033 | tx_vec = (v0 >> 32); | |
3034 | rx_vec = (v0 & 0xffffffff); | |
3035 | ||
3036 | for (i = 0; i < np->num_rx_rings; i++) { | |
3037 | struct rx_ring_info *rp = &np->rx_rings[i]; | |
3038 | int ldn = LDN_RXDMA(rp->rx_channel); | |
3039 | ||
3040 | if (parent->ldg_map[ldn] != ldg) | |
3041 | continue; | |
3042 | ||
3043 | nw64(LD_IM0(ldn), LD_IM0_MASK); | |
3044 | if (rx_vec & (1 << rp->rx_channel)) | |
3045 | niu_rxchan_intr(np, rp, ldn); | |
3046 | } | |
3047 | ||
3048 | for (i = 0; i < np->num_tx_rings; i++) { | |
3049 | struct tx_ring_info *rp = &np->tx_rings[i]; | |
3050 | int ldn = LDN_TXDMA(rp->tx_channel); | |
3051 | ||
3052 | if (parent->ldg_map[ldn] != ldg) | |
3053 | continue; | |
3054 | ||
3055 | nw64(LD_IM0(ldn), LD_IM0_MASK); | |
3056 | if (tx_vec & (1 << rp->tx_channel)) | |
3057 | niu_txchan_intr(np, rp, ldn); | |
3058 | } | |
3059 | } | |
3060 | ||
3061 | static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp, | |
3062 | u64 v0, u64 v1, u64 v2) | |
3063 | { | |
3064 | if (likely(netif_rx_schedule_prep(np->dev, &lp->napi))) { | |
3065 | lp->v0 = v0; | |
3066 | lp->v1 = v1; | |
3067 | lp->v2 = v2; | |
3068 | __niu_fastpath_interrupt(np, lp->ldg_num, v0); | |
3069 | __netif_rx_schedule(np->dev, &lp->napi); | |
3070 | } | |
3071 | } | |
3072 | ||
3073 | static irqreturn_t niu_interrupt(int irq, void *dev_id) | |
3074 | { | |
3075 | struct niu_ldg *lp = dev_id; | |
3076 | struct niu *np = lp->np; | |
3077 | int ldg = lp->ldg_num; | |
3078 | unsigned long flags; | |
3079 | u64 v0, v1, v2; | |
3080 | ||
3081 | if (netif_msg_intr(np)) | |
3082 | printk(KERN_DEBUG PFX "niu_interrupt() ldg[%p](%d) ", | |
3083 | lp, ldg); | |
3084 | ||
3085 | spin_lock_irqsave(&np->lock, flags); | |
3086 | ||
3087 | v0 = nr64(LDSV0(ldg)); | |
3088 | v1 = nr64(LDSV1(ldg)); | |
3089 | v2 = nr64(LDSV2(ldg)); | |
3090 | ||
3091 | if (netif_msg_intr(np)) | |
3092 | printk("v0[%llx] v1[%llx] v2[%llx]\n", | |
3093 | (unsigned long long) v0, | |
3094 | (unsigned long long) v1, | |
3095 | (unsigned long long) v2); | |
3096 | ||
3097 | if (unlikely(!v0 && !v1 && !v2)) { | |
3098 | spin_unlock_irqrestore(&np->lock, flags); | |
3099 | return IRQ_NONE; | |
3100 | } | |
3101 | ||
3102 | if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) { | |
406f353c | 3103 | int err = niu_slowpath_interrupt(np, lp, v0, v1, v2); |
a3138df9 DM |
3104 | if (err) |
3105 | goto out; | |
3106 | } | |
3107 | if (likely(v0 & ~((u64)1 << LDN_MIF))) | |
3108 | niu_schedule_napi(np, lp, v0, v1, v2); | |
3109 | else | |
3110 | niu_ldg_rearm(np, lp, 1); | |
3111 | out: | |
3112 | spin_unlock_irqrestore(&np->lock, flags); | |
3113 | ||
3114 | return IRQ_HANDLED; | |
3115 | } | |
3116 | ||
3117 | static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp) | |
3118 | { | |
3119 | if (rp->mbox) { | |
3120 | np->ops->free_coherent(np->device, | |
3121 | sizeof(struct rxdma_mailbox), | |
3122 | rp->mbox, rp->mbox_dma); | |
3123 | rp->mbox = NULL; | |
3124 | } | |
3125 | if (rp->rcr) { | |
3126 | np->ops->free_coherent(np->device, | |
3127 | MAX_RCR_RING_SIZE * sizeof(__le64), | |
3128 | rp->rcr, rp->rcr_dma); | |
3129 | rp->rcr = NULL; | |
3130 | rp->rcr_table_size = 0; | |
3131 | rp->rcr_index = 0; | |
3132 | } | |
3133 | if (rp->rbr) { | |
3134 | niu_rbr_free(np, rp); | |
3135 | ||
3136 | np->ops->free_coherent(np->device, | |
3137 | MAX_RBR_RING_SIZE * sizeof(__le32), | |
3138 | rp->rbr, rp->rbr_dma); | |
3139 | rp->rbr = NULL; | |
3140 | rp->rbr_table_size = 0; | |
3141 | rp->rbr_index = 0; | |
3142 | } | |
3143 | kfree(rp->rxhash); | |
3144 | rp->rxhash = NULL; | |
3145 | } | |
3146 | ||
3147 | static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp) | |
3148 | { | |
3149 | if (rp->mbox) { | |
3150 | np->ops->free_coherent(np->device, | |
3151 | sizeof(struct txdma_mailbox), | |
3152 | rp->mbox, rp->mbox_dma); | |
3153 | rp->mbox = NULL; | |
3154 | } | |
3155 | if (rp->descr) { | |
3156 | int i; | |
3157 | ||
3158 | for (i = 0; i < MAX_TX_RING_SIZE; i++) { | |
3159 | if (rp->tx_buffs[i].skb) | |
3160 | (void) release_tx_packet(np, rp, i); | |
3161 | } | |
3162 | ||
3163 | np->ops->free_coherent(np->device, | |
3164 | MAX_TX_RING_SIZE * sizeof(__le64), | |
3165 | rp->descr, rp->descr_dma); | |
3166 | rp->descr = NULL; | |
3167 | rp->pending = 0; | |
3168 | rp->prod = 0; | |
3169 | rp->cons = 0; | |
3170 | rp->wrap_bit = 0; | |
3171 | } | |
3172 | } | |
3173 | ||
3174 | static void niu_free_channels(struct niu *np) | |
3175 | { | |
3176 | int i; | |
3177 | ||
3178 | if (np->rx_rings) { | |
3179 | for (i = 0; i < np->num_rx_rings; i++) { | |
3180 | struct rx_ring_info *rp = &np->rx_rings[i]; | |
3181 | ||
3182 | niu_free_rx_ring_info(np, rp); | |
3183 | } | |
3184 | kfree(np->rx_rings); | |
3185 | np->rx_rings = NULL; | |
3186 | np->num_rx_rings = 0; | |
3187 | } | |
3188 | ||
3189 | if (np->tx_rings) { | |
3190 | for (i = 0; i < np->num_tx_rings; i++) { | |
3191 | struct tx_ring_info *rp = &np->tx_rings[i]; | |
3192 | ||
3193 | niu_free_tx_ring_info(np, rp); | |
3194 | } | |
3195 | kfree(np->tx_rings); | |
3196 | np->tx_rings = NULL; | |
3197 | np->num_tx_rings = 0; | |
3198 | } | |
3199 | } | |
3200 | ||
3201 | static int niu_alloc_rx_ring_info(struct niu *np, | |
3202 | struct rx_ring_info *rp) | |
3203 | { | |
3204 | BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64); | |
3205 | ||
3206 | rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *), | |
3207 | GFP_KERNEL); | |
3208 | if (!rp->rxhash) | |
3209 | return -ENOMEM; | |
3210 | ||
3211 | rp->mbox = np->ops->alloc_coherent(np->device, | |
3212 | sizeof(struct rxdma_mailbox), | |
3213 | &rp->mbox_dma, GFP_KERNEL); | |
3214 | if (!rp->mbox) | |
3215 | return -ENOMEM; | |
3216 | if ((unsigned long)rp->mbox & (64UL - 1)) { | |
3217 | dev_err(np->device, PFX "%s: Coherent alloc gives misaligned " | |
3218 | "RXDMA mailbox %p\n", np->dev->name, rp->mbox); | |
3219 | return -EINVAL; | |
3220 | } | |
3221 | ||
3222 | rp->rcr = np->ops->alloc_coherent(np->device, | |
3223 | MAX_RCR_RING_SIZE * sizeof(__le64), | |
3224 | &rp->rcr_dma, GFP_KERNEL); | |
3225 | if (!rp->rcr) | |
3226 | return -ENOMEM; | |
3227 | if ((unsigned long)rp->rcr & (64UL - 1)) { | |
3228 | dev_err(np->device, PFX "%s: Coherent alloc gives misaligned " | |
3229 | "RXDMA RCR table %p\n", np->dev->name, rp->rcr); | |
3230 | return -EINVAL; | |
3231 | } | |
3232 | rp->rcr_table_size = MAX_RCR_RING_SIZE; | |
3233 | rp->rcr_index = 0; | |
3234 | ||
3235 | rp->rbr = np->ops->alloc_coherent(np->device, | |
3236 | MAX_RBR_RING_SIZE * sizeof(__le32), | |
3237 | &rp->rbr_dma, GFP_KERNEL); | |
3238 | if (!rp->rbr) | |
3239 | return -ENOMEM; | |
3240 | if ((unsigned long)rp->rbr & (64UL - 1)) { | |
3241 | dev_err(np->device, PFX "%s: Coherent alloc gives misaligned " | |
3242 | "RXDMA RBR table %p\n", np->dev->name, rp->rbr); | |
3243 | return -EINVAL; | |
3244 | } | |
3245 | rp->rbr_table_size = MAX_RBR_RING_SIZE; | |
3246 | rp->rbr_index = 0; | |
3247 | rp->rbr_pending = 0; | |
3248 | ||
3249 | return 0; | |
3250 | } | |
3251 | ||
3252 | static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp) | |
3253 | { | |
3254 | int mtu = np->dev->mtu; | |
3255 | ||
3256 | /* These values are recommended by the HW designers for fair | |
3257 | * utilization of DRR amongst the rings. | |
3258 | */ | |
3259 | rp->max_burst = mtu + 32; | |
3260 | if (rp->max_burst > 4096) | |
3261 | rp->max_burst = 4096; | |
3262 | } | |
3263 | ||
3264 | static int niu_alloc_tx_ring_info(struct niu *np, | |
3265 | struct tx_ring_info *rp) | |
3266 | { | |
3267 | BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64); | |
3268 | ||
3269 | rp->mbox = np->ops->alloc_coherent(np->device, | |
3270 | sizeof(struct txdma_mailbox), | |
3271 | &rp->mbox_dma, GFP_KERNEL); | |
3272 | if (!rp->mbox) | |
3273 | return -ENOMEM; | |
3274 | if ((unsigned long)rp->mbox & (64UL - 1)) { | |
3275 | dev_err(np->device, PFX "%s: Coherent alloc gives misaligned " | |
3276 | "TXDMA mailbox %p\n", np->dev->name, rp->mbox); | |
3277 | return -EINVAL; | |
3278 | } | |
3279 | ||
3280 | rp->descr = np->ops->alloc_coherent(np->device, | |
3281 | MAX_TX_RING_SIZE * sizeof(__le64), | |
3282 | &rp->descr_dma, GFP_KERNEL); | |
3283 | if (!rp->descr) | |
3284 | return -ENOMEM; | |
3285 | if ((unsigned long)rp->descr & (64UL - 1)) { | |
3286 | dev_err(np->device, PFX "%s: Coherent alloc gives misaligned " | |
3287 | "TXDMA descr table %p\n", np->dev->name, rp->descr); | |
3288 | return -EINVAL; | |
3289 | } | |
3290 | ||
3291 | rp->pending = MAX_TX_RING_SIZE; | |
3292 | rp->prod = 0; | |
3293 | rp->cons = 0; | |
3294 | rp->wrap_bit = 0; | |
3295 | ||
3296 | /* XXX make these configurable... XXX */ | |
3297 | rp->mark_freq = rp->pending / 4; | |
3298 | ||
3299 | niu_set_max_burst(np, rp); | |
3300 | ||
3301 | return 0; | |
3302 | } | |
3303 | ||
3304 | static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp) | |
3305 | { | |
81429973 | 3306 | u16 bss; |
a3138df9 | 3307 | |
81429973 | 3308 | bss = min(PAGE_SHIFT, 15); |
a3138df9 | 3309 | |
81429973 OJ |
3310 | rp->rbr_block_size = 1 << bss; |
3311 | rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss); | |
a3138df9 DM |
3312 | |
3313 | rp->rbr_sizes[0] = 256; | |
3314 | rp->rbr_sizes[1] = 1024; | |
3315 | if (np->dev->mtu > ETH_DATA_LEN) { | |
3316 | switch (PAGE_SIZE) { | |
3317 | case 4 * 1024: | |
3318 | rp->rbr_sizes[2] = 4096; | |
3319 | break; | |
3320 | ||
3321 | default: | |
3322 | rp->rbr_sizes[2] = 8192; | |
3323 | break; | |
3324 | } | |
3325 | } else { | |
3326 | rp->rbr_sizes[2] = 2048; | |
3327 | } | |
3328 | rp->rbr_sizes[3] = rp->rbr_block_size; | |
3329 | } | |
3330 | ||
3331 | static int niu_alloc_channels(struct niu *np) | |
3332 | { | |
3333 | struct niu_parent *parent = np->parent; | |
3334 | int first_rx_channel, first_tx_channel; | |
3335 | int i, port, err; | |
3336 | ||
3337 | port = np->port; | |
3338 | first_rx_channel = first_tx_channel = 0; | |
3339 | for (i = 0; i < port; i++) { | |
3340 | first_rx_channel += parent->rxchan_per_port[i]; | |
3341 | first_tx_channel += parent->txchan_per_port[i]; | |
3342 | } | |
3343 | ||
3344 | np->num_rx_rings = parent->rxchan_per_port[port]; | |
3345 | np->num_tx_rings = parent->txchan_per_port[port]; | |
3346 | ||
3347 | np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info), | |
3348 | GFP_KERNEL); | |
3349 | err = -ENOMEM; | |
3350 | if (!np->rx_rings) | |
3351 | goto out_err; | |
3352 | ||
3353 | for (i = 0; i < np->num_rx_rings; i++) { | |
3354 | struct rx_ring_info *rp = &np->rx_rings[i]; | |
3355 | ||
3356 | rp->np = np; | |
3357 | rp->rx_channel = first_rx_channel + i; | |
3358 | ||
3359 | err = niu_alloc_rx_ring_info(np, rp); | |
3360 | if (err) | |
3361 | goto out_err; | |
3362 | ||
3363 | niu_size_rbr(np, rp); | |
3364 | ||
3365 | /* XXX better defaults, configurable, etc... XXX */ | |
3366 | rp->nonsyn_window = 64; | |
3367 | rp->nonsyn_threshold = rp->rcr_table_size - 64; | |
3368 | rp->syn_window = 64; | |
3369 | rp->syn_threshold = rp->rcr_table_size - 64; | |
3370 | rp->rcr_pkt_threshold = 16; | |
3371 | rp->rcr_timeout = 8; | |
3372 | rp->rbr_kick_thresh = RBR_REFILL_MIN; | |
3373 | if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page) | |
3374 | rp->rbr_kick_thresh = rp->rbr_blocks_per_page; | |
3375 | ||
3376 | err = niu_rbr_fill(np, rp, GFP_KERNEL); | |
3377 | if (err) | |
3378 | return err; | |
3379 | } | |
3380 | ||
3381 | np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info), | |
3382 | GFP_KERNEL); | |
3383 | err = -ENOMEM; | |
3384 | if (!np->tx_rings) | |
3385 | goto out_err; | |
3386 | ||
3387 | for (i = 0; i < np->num_tx_rings; i++) { | |
3388 | struct tx_ring_info *rp = &np->tx_rings[i]; | |
3389 | ||
3390 | rp->np = np; | |
3391 | rp->tx_channel = first_tx_channel + i; | |
3392 | ||
3393 | err = niu_alloc_tx_ring_info(np, rp); | |
3394 | if (err) | |
3395 | goto out_err; | |
3396 | } | |
3397 | ||
3398 | return 0; | |
3399 | ||
3400 | out_err: | |
3401 | niu_free_channels(np); | |
3402 | return err; | |
3403 | } | |
3404 | ||
3405 | static int niu_tx_cs_sng_poll(struct niu *np, int channel) | |
3406 | { | |
3407 | int limit = 1000; | |
3408 | ||
3409 | while (--limit > 0) { | |
3410 | u64 val = nr64(TX_CS(channel)); | |
3411 | if (val & TX_CS_SNG_STATE) | |
3412 | return 0; | |
3413 | } | |
3414 | return -ENODEV; | |
3415 | } | |
3416 | ||
3417 | static int niu_tx_channel_stop(struct niu *np, int channel) | |
3418 | { | |
3419 | u64 val = nr64(TX_CS(channel)); | |
3420 | ||
3421 | val |= TX_CS_STOP_N_GO; | |
3422 | nw64(TX_CS(channel), val); | |
3423 | ||
3424 | return niu_tx_cs_sng_poll(np, channel); | |
3425 | } | |
3426 | ||
3427 | static int niu_tx_cs_reset_poll(struct niu *np, int channel) | |
3428 | { | |
3429 | int limit = 1000; | |
3430 | ||
3431 | while (--limit > 0) { | |
3432 | u64 val = nr64(TX_CS(channel)); | |
3433 | if (!(val & TX_CS_RST)) | |
3434 | return 0; | |
3435 | } | |
3436 | return -ENODEV; | |
3437 | } | |
3438 | ||
3439 | static int niu_tx_channel_reset(struct niu *np, int channel) | |
3440 | { | |
3441 | u64 val = nr64(TX_CS(channel)); | |
3442 | int err; | |
3443 | ||
3444 | val |= TX_CS_RST; | |
3445 | nw64(TX_CS(channel), val); | |
3446 | ||
3447 | err = niu_tx_cs_reset_poll(np, channel); | |
3448 | if (!err) | |
3449 | nw64(TX_RING_KICK(channel), 0); | |
3450 | ||
3451 | return err; | |
3452 | } | |
3453 | ||
3454 | static int niu_tx_channel_lpage_init(struct niu *np, int channel) | |
3455 | { | |
3456 | u64 val; | |
3457 | ||
3458 | nw64(TX_LOG_MASK1(channel), 0); | |
3459 | nw64(TX_LOG_VAL1(channel), 0); | |
3460 | nw64(TX_LOG_MASK2(channel), 0); | |
3461 | nw64(TX_LOG_VAL2(channel), 0); | |
3462 | nw64(TX_LOG_PAGE_RELO1(channel), 0); | |
3463 | nw64(TX_LOG_PAGE_RELO2(channel), 0); | |
3464 | nw64(TX_LOG_PAGE_HDL(channel), 0); | |
3465 | ||
3466 | val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT; | |
3467 | val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1); | |
3468 | nw64(TX_LOG_PAGE_VLD(channel), val); | |
3469 | ||
3470 | /* XXX TXDMA 32bit mode? XXX */ | |
3471 | ||
3472 | return 0; | |
3473 | } | |
3474 | ||
3475 | static void niu_txc_enable_port(struct niu *np, int on) | |
3476 | { | |
3477 | unsigned long flags; | |
3478 | u64 val, mask; | |
3479 | ||
3480 | niu_lock_parent(np, flags); | |
3481 | val = nr64(TXC_CONTROL); | |
3482 | mask = (u64)1 << np->port; | |
3483 | if (on) { | |
3484 | val |= TXC_CONTROL_ENABLE | mask; | |
3485 | } else { | |
3486 | val &= ~mask; | |
3487 | if ((val & ~TXC_CONTROL_ENABLE) == 0) | |
3488 | val &= ~TXC_CONTROL_ENABLE; | |
3489 | } | |
3490 | nw64(TXC_CONTROL, val); | |
3491 | niu_unlock_parent(np, flags); | |
3492 | } | |
3493 | ||
3494 | static void niu_txc_set_imask(struct niu *np, u64 imask) | |
3495 | { | |
3496 | unsigned long flags; | |
3497 | u64 val; | |
3498 | ||
3499 | niu_lock_parent(np, flags); | |
3500 | val = nr64(TXC_INT_MASK); | |
3501 | val &= ~TXC_INT_MASK_VAL(np->port); | |
3502 | val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port)); | |
3503 | niu_unlock_parent(np, flags); | |
3504 | } | |
3505 | ||
3506 | static void niu_txc_port_dma_enable(struct niu *np, int on) | |
3507 | { | |
3508 | u64 val = 0; | |
3509 | ||
3510 | if (on) { | |
3511 | int i; | |
3512 | ||
3513 | for (i = 0; i < np->num_tx_rings; i++) | |
3514 | val |= (1 << np->tx_rings[i].tx_channel); | |
3515 | } | |
3516 | nw64(TXC_PORT_DMA(np->port), val); | |
3517 | } | |
3518 | ||
3519 | static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp) | |
3520 | { | |
3521 | int err, channel = rp->tx_channel; | |
3522 | u64 val, ring_len; | |
3523 | ||
3524 | err = niu_tx_channel_stop(np, channel); | |
3525 | if (err) | |
3526 | return err; | |
3527 | ||
3528 | err = niu_tx_channel_reset(np, channel); | |
3529 | if (err) | |
3530 | return err; | |
3531 | ||
3532 | err = niu_tx_channel_lpage_init(np, channel); | |
3533 | if (err) | |
3534 | return err; | |
3535 | ||
3536 | nw64(TXC_DMA_MAX(channel), rp->max_burst); | |
3537 | nw64(TX_ENT_MSK(channel), 0); | |
3538 | ||
3539 | if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE | | |
3540 | TX_RNG_CFIG_STADDR)) { | |
3541 | dev_err(np->device, PFX "%s: TX ring channel %d " | |
3542 | "DMA addr (%llx) is not aligned.\n", | |
3543 | np->dev->name, channel, | |
3544 | (unsigned long long) rp->descr_dma); | |
3545 | return -EINVAL; | |
3546 | } | |
3547 | ||
3548 | /* The length field in TX_RNG_CFIG is measured in 64-byte | |
3549 | * blocks. rp->pending is the number of TX descriptors in | |
3550 | * our ring, 8 bytes each, thus we divide by 8 bytes more | |
3551 | * to get the proper value the chip wants. | |
3552 | */ | |
3553 | ring_len = (rp->pending / 8); | |
3554 | ||
3555 | val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) | | |
3556 | rp->descr_dma); | |
3557 | nw64(TX_RNG_CFIG(channel), val); | |
3558 | ||
3559 | if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) || | |
3560 | ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) { | |
3561 | dev_err(np->device, PFX "%s: TX ring channel %d " | |
3562 | "MBOX addr (%llx) is has illegal bits.\n", | |
3563 | np->dev->name, channel, | |
3564 | (unsigned long long) rp->mbox_dma); | |
3565 | return -EINVAL; | |
3566 | } | |
3567 | nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32); | |
3568 | nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR); | |
3569 | ||
3570 | nw64(TX_CS(channel), 0); | |
3571 | ||
3572 | rp->last_pkt_cnt = 0; | |
3573 | ||
3574 | return 0; | |
3575 | } | |
3576 | ||
3577 | static void niu_init_rdc_groups(struct niu *np) | |
3578 | { | |
3579 | struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port]; | |
3580 | int i, first_table_num = tp->first_table_num; | |
3581 | ||
3582 | for (i = 0; i < tp->num_tables; i++) { | |
3583 | struct rdc_table *tbl = &tp->tables[i]; | |
3584 | int this_table = first_table_num + i; | |
3585 | int slot; | |
3586 | ||
3587 | for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) | |
3588 | nw64(RDC_TBL(this_table, slot), | |
3589 | tbl->rxdma_channel[slot]); | |
3590 | } | |
3591 | ||
3592 | nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]); | |
3593 | } | |
3594 | ||
3595 | static void niu_init_drr_weight(struct niu *np) | |
3596 | { | |
3597 | int type = phy_decode(np->parent->port_phy, np->port); | |
3598 | u64 val; | |
3599 | ||
3600 | switch (type) { | |
3601 | case PORT_TYPE_10G: | |
3602 | val = PT_DRR_WEIGHT_DEFAULT_10G; | |
3603 | break; | |
3604 | ||
3605 | case PORT_TYPE_1G: | |
3606 | default: | |
3607 | val = PT_DRR_WEIGHT_DEFAULT_1G; | |
3608 | break; | |
3609 | } | |
3610 | nw64(PT_DRR_WT(np->port), val); | |
3611 | } | |
3612 | ||
3613 | static int niu_init_hostinfo(struct niu *np) | |
3614 | { | |
3615 | struct niu_parent *parent = np->parent; | |
3616 | struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port]; | |
3617 | int i, err, num_alt = niu_num_alt_addr(np); | |
3618 | int first_rdc_table = tp->first_table_num; | |
3619 | ||
3620 | err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1); | |
3621 | if (err) | |
3622 | return err; | |
3623 | ||
3624 | err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1); | |
3625 | if (err) | |
3626 | return err; | |
3627 | ||
3628 | for (i = 0; i < num_alt; i++) { | |
3629 | err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1); | |
3630 | if (err) | |
3631 | return err; | |
3632 | } | |
3633 | ||
3634 | return 0; | |
3635 | } | |
3636 | ||
3637 | static int niu_rx_channel_reset(struct niu *np, int channel) | |
3638 | { | |
3639 | return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel), | |
3640 | RXDMA_CFIG1_RST, 1000, 10, | |
3641 | "RXDMA_CFIG1"); | |
3642 | } | |
3643 | ||
3644 | static int niu_rx_channel_lpage_init(struct niu *np, int channel) | |
3645 | { | |
3646 | u64 val; | |
3647 | ||
3648 | nw64(RX_LOG_MASK1(channel), 0); | |
3649 | nw64(RX_LOG_VAL1(channel), 0); | |
3650 | nw64(RX_LOG_MASK2(channel), 0); | |
3651 | nw64(RX_LOG_VAL2(channel), 0); | |
3652 | nw64(RX_LOG_PAGE_RELO1(channel), 0); | |
3653 | nw64(RX_LOG_PAGE_RELO2(channel), 0); | |
3654 | nw64(RX_LOG_PAGE_HDL(channel), 0); | |
3655 | ||
3656 | val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT; | |
3657 | val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1); | |
3658 | nw64(RX_LOG_PAGE_VLD(channel), val); | |
3659 | ||
3660 | return 0; | |
3661 | } | |
3662 | ||
3663 | static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp) | |
3664 | { | |
3665 | u64 val; | |
3666 | ||
3667 | val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) | | |
3668 | ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) | | |
3669 | ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) | | |
3670 | ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT)); | |
3671 | nw64(RDC_RED_PARA(rp->rx_channel), val); | |
3672 | } | |
3673 | ||
3674 | static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret) | |
3675 | { | |
3676 | u64 val = 0; | |
3677 | ||
3678 | switch (rp->rbr_block_size) { | |
3679 | case 4 * 1024: | |
3680 | val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT); | |
3681 | break; | |
3682 | case 8 * 1024: | |
3683 | val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT); | |
3684 | break; | |
3685 | case 16 * 1024: | |
3686 | val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT); | |
3687 | break; | |
3688 | case 32 * 1024: | |
3689 | val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT); | |
3690 | break; | |
3691 | default: | |
3692 | return -EINVAL; | |
3693 | } | |
3694 | val |= RBR_CFIG_B_VLD2; | |
3695 | switch (rp->rbr_sizes[2]) { | |
3696 | case 2 * 1024: | |
3697 | val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT); | |
3698 | break; | |
3699 | case 4 * 1024: | |
3700 | val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT); | |
3701 | break; | |
3702 | case 8 * 1024: | |
3703 | val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT); | |
3704 | break; | |
3705 | case 16 * 1024: | |
3706 | val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT); | |
3707 | break; | |
3708 | ||
3709 | default: | |
3710 | return -EINVAL; | |
3711 | } | |
3712 | val |= RBR_CFIG_B_VLD1; | |
3713 | switch (rp->rbr_sizes[1]) { | |
3714 | case 1 * 1024: | |
3715 | val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT); | |
3716 | break; | |
3717 | case 2 * 1024: | |
3718 | val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT); | |
3719 | break; | |
3720 | case 4 * 1024: | |
3721 | val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT); | |
3722 | break; | |
3723 | case 8 * 1024: | |
3724 | val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT); | |
3725 | break; | |
3726 | ||
3727 | default: | |
3728 | return -EINVAL; | |
3729 | } | |
3730 | val |= RBR_CFIG_B_VLD0; | |
3731 | switch (rp->rbr_sizes[0]) { | |
3732 | case 256: | |
3733 | val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT); | |
3734 | break; | |
3735 | case 512: | |
3736 | val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT); | |
3737 | break; | |
3738 | case 1 * 1024: | |
3739 | val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT); | |
3740 | break; | |
3741 | case 2 * 1024: | |
3742 | val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT); | |
3743 | break; | |
3744 | ||
3745 | default: | |
3746 | return -EINVAL; | |
3747 | } | |
3748 | ||
3749 | *ret = val; | |
3750 | return 0; | |
3751 | } | |
3752 | ||
3753 | static int niu_enable_rx_channel(struct niu *np, int channel, int on) | |
3754 | { | |
3755 | u64 val = nr64(RXDMA_CFIG1(channel)); | |
3756 | int limit; | |
3757 | ||
3758 | if (on) | |
3759 | val |= RXDMA_CFIG1_EN; | |
3760 | else | |
3761 | val &= ~RXDMA_CFIG1_EN; | |
3762 | nw64(RXDMA_CFIG1(channel), val); | |
3763 | ||
3764 | limit = 1000; | |
3765 | while (--limit > 0) { | |
3766 | if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST) | |
3767 | break; | |
3768 | udelay(10); | |
3769 | } | |
3770 | if (limit <= 0) | |
3771 | return -ENODEV; | |
3772 | return 0; | |
3773 | } | |
3774 | ||
3775 | static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp) | |
3776 | { | |
3777 | int err, channel = rp->rx_channel; | |
3778 | u64 val; | |
3779 | ||
3780 | err = niu_rx_channel_reset(np, channel); | |
3781 | if (err) | |
3782 | return err; | |
3783 | ||
3784 | err = niu_rx_channel_lpage_init(np, channel); | |
3785 | if (err) | |
3786 | return err; | |
3787 | ||
3788 | niu_rx_channel_wred_init(np, rp); | |
3789 | ||
3790 | nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY); | |
3791 | nw64(RX_DMA_CTL_STAT(channel), | |
3792 | (RX_DMA_CTL_STAT_MEX | | |
3793 | RX_DMA_CTL_STAT_RCRTHRES | | |
3794 | RX_DMA_CTL_STAT_RCRTO | | |
3795 | RX_DMA_CTL_STAT_RBR_EMPTY)); | |
3796 | nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32); | |
3797 | nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0)); | |
3798 | nw64(RBR_CFIG_A(channel), | |
3799 | ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) | | |
3800 | (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR))); | |
3801 | err = niu_compute_rbr_cfig_b(rp, &val); | |
3802 | if (err) | |
3803 | return err; | |
3804 | nw64(RBR_CFIG_B(channel), val); | |
3805 | nw64(RCRCFIG_A(channel), | |
3806 | ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) | | |
3807 | (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR))); | |
3808 | nw64(RCRCFIG_B(channel), | |
3809 | ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) | | |
3810 | RCRCFIG_B_ENTOUT | | |
3811 | ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT)); | |
3812 | ||
3813 | err = niu_enable_rx_channel(np, channel, 1); | |
3814 | if (err) | |
3815 | return err; | |
3816 | ||
3817 | nw64(RBR_KICK(channel), rp->rbr_index); | |
3818 | ||
3819 | val = nr64(RX_DMA_CTL_STAT(channel)); | |
3820 | val |= RX_DMA_CTL_STAT_RBR_EMPTY; | |
3821 | nw64(RX_DMA_CTL_STAT(channel), val); | |
3822 | ||
3823 | return 0; | |
3824 | } | |
3825 | ||
3826 | static int niu_init_rx_channels(struct niu *np) | |
3827 | { | |
3828 | unsigned long flags; | |
3829 | u64 seed = jiffies_64; | |
3830 | int err, i; | |
3831 | ||
3832 | niu_lock_parent(np, flags); | |
3833 | nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider); | |
3834 | nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL)); | |
3835 | niu_unlock_parent(np, flags); | |
3836 | ||
3837 | /* XXX RXDMA 32bit mode? XXX */ | |
3838 | ||
3839 | niu_init_rdc_groups(np); | |
3840 | niu_init_drr_weight(np); | |
3841 | ||
3842 | err = niu_init_hostinfo(np); | |
3843 | if (err) | |
3844 | return err; | |
3845 | ||
3846 | for (i = 0; i < np->num_rx_rings; i++) { | |
3847 | struct rx_ring_info *rp = &np->rx_rings[i]; | |
3848 | ||
3849 | err = niu_init_one_rx_channel(np, rp); | |
3850 | if (err) | |
3851 | return err; | |
3852 | } | |
3853 | ||
3854 | return 0; | |
3855 | } | |
3856 | ||
3857 | static int niu_set_ip_frag_rule(struct niu *np) | |
3858 | { | |
3859 | struct niu_parent *parent = np->parent; | |
3860 | struct niu_classifier *cp = &np->clas; | |
3861 | struct niu_tcam_entry *tp; | |
3862 | int index, err; | |
3863 | ||
3864 | /* XXX fix this allocation scheme XXX */ | |
3865 | index = cp->tcam_index; | |
3866 | tp = &parent->tcam[index]; | |
3867 | ||
3868 | /* Note that the noport bit is the same in both ipv4 and | |
3869 | * ipv6 format TCAM entries. | |
3870 | */ | |
3871 | memset(tp, 0, sizeof(*tp)); | |
3872 | tp->key[1] = TCAM_V4KEY1_NOPORT; | |
3873 | tp->key_mask[1] = TCAM_V4KEY1_NOPORT; | |
3874 | tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET | | |
3875 | ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT)); | |
3876 | err = tcam_write(np, index, tp->key, tp->key_mask); | |
3877 | if (err) | |
3878 | return err; | |
3879 | err = tcam_assoc_write(np, index, tp->assoc_data); | |
3880 | if (err) | |
3881 | return err; | |
3882 | ||
3883 | return 0; | |
3884 | } | |
3885 | ||
3886 | static int niu_init_classifier_hw(struct niu *np) | |
3887 | { | |
3888 | struct niu_parent *parent = np->parent; | |
3889 | struct niu_classifier *cp = &np->clas; | |
3890 | int i, err; | |
3891 | ||
3892 | nw64(H1POLY, cp->h1_init); | |
3893 | nw64(H2POLY, cp->h2_init); | |
3894 | ||
3895 | err = niu_init_hostinfo(np); | |
3896 | if (err) | |
3897 | return err; | |
3898 | ||
3899 | for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) { | |
3900 | struct niu_vlan_rdc *vp = &cp->vlan_mappings[i]; | |
3901 | ||
3902 | vlan_tbl_write(np, i, np->port, | |
3903 | vp->vlan_pref, vp->rdc_num); | |
3904 | } | |
3905 | ||
3906 | for (i = 0; i < cp->num_alt_mac_mappings; i++) { | |
3907 | struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i]; | |
3908 | ||
3909 | err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num, | |
3910 | ap->rdc_num, ap->mac_pref); | |
3911 | if (err) | |
3912 | return err; | |
3913 | } | |
3914 | ||
3915 | for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) { | |
3916 | int index = i - CLASS_CODE_USER_PROG1; | |
3917 | ||
3918 | err = niu_set_tcam_key(np, i, parent->tcam_key[index]); | |
3919 | if (err) | |
3920 | return err; | |
3921 | err = niu_set_flow_key(np, i, parent->flow_key[index]); | |
3922 | if (err) | |
3923 | return err; | |
3924 | } | |
3925 | ||
3926 | err = niu_set_ip_frag_rule(np); | |
3927 | if (err) | |
3928 | return err; | |
3929 | ||
3930 | tcam_enable(np, 1); | |
3931 | ||
3932 | return 0; | |
3933 | } | |
3934 | ||
3935 | static int niu_zcp_write(struct niu *np, int index, u64 *data) | |
3936 | { | |
3937 | nw64(ZCP_RAM_DATA0, data[0]); | |
3938 | nw64(ZCP_RAM_DATA1, data[1]); | |
3939 | nw64(ZCP_RAM_DATA2, data[2]); | |
3940 | nw64(ZCP_RAM_DATA3, data[3]); | |
3941 | nw64(ZCP_RAM_DATA4, data[4]); | |
3942 | nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL); | |
3943 | nw64(ZCP_RAM_ACC, | |
3944 | (ZCP_RAM_ACC_WRITE | | |
3945 | (0 << ZCP_RAM_ACC_ZFCID_SHIFT) | | |
3946 | (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT))); | |
3947 | ||
3948 | return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY, | |
3949 | 1000, 100); | |
3950 | } | |
3951 | ||
3952 | static int niu_zcp_read(struct niu *np, int index, u64 *data) | |
3953 | { | |
3954 | int err; | |
3955 | ||
3956 | err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY, | |
3957 | 1000, 100); | |
3958 | if (err) { | |
3959 | dev_err(np->device, PFX "%s: ZCP read busy won't clear, " | |
3960 | "ZCP_RAM_ACC[%llx]\n", np->dev->name, | |
3961 | (unsigned long long) nr64(ZCP_RAM_ACC)); | |
3962 | return err; | |
3963 | } | |
3964 | ||
3965 | nw64(ZCP_RAM_ACC, | |
3966 | (ZCP_RAM_ACC_READ | | |
3967 | (0 << ZCP_RAM_ACC_ZFCID_SHIFT) | | |
3968 | (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT))); | |
3969 | ||
3970 | err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY, | |
3971 | 1000, 100); | |
3972 | if (err) { | |
3973 | dev_err(np->device, PFX "%s: ZCP read busy2 won't clear, " | |
3974 | "ZCP_RAM_ACC[%llx]\n", np->dev->name, | |
3975 | (unsigned long long) nr64(ZCP_RAM_ACC)); | |
3976 | return err; | |
3977 | } | |
3978 | ||
3979 | data[0] = nr64(ZCP_RAM_DATA0); | |
3980 | data[1] = nr64(ZCP_RAM_DATA1); | |
3981 | data[2] = nr64(ZCP_RAM_DATA2); | |
3982 | data[3] = nr64(ZCP_RAM_DATA3); | |
3983 | data[4] = nr64(ZCP_RAM_DATA4); | |
3984 | ||
3985 | return 0; | |
3986 | } | |
3987 | ||
3988 | static void niu_zcp_cfifo_reset(struct niu *np) | |
3989 | { | |
3990 | u64 val = nr64(RESET_CFIFO); | |
3991 | ||
3992 | val |= RESET_CFIFO_RST(np->port); | |
3993 | nw64(RESET_CFIFO, val); | |
3994 | udelay(10); | |
3995 | ||
3996 | val &= ~RESET_CFIFO_RST(np->port); | |
3997 | nw64(RESET_CFIFO, val); | |
3998 | } | |
3999 | ||
4000 | static int niu_init_zcp(struct niu *np) | |
4001 | { | |
4002 | u64 data[5], rbuf[5]; | |
4003 | int i, max, err; | |
4004 | ||
4005 | if (np->parent->plat_type != PLAT_TYPE_NIU) { | |
4006 | if (np->port == 0 || np->port == 1) | |
4007 | max = ATLAS_P0_P1_CFIFO_ENTRIES; | |
4008 | else | |
4009 | max = ATLAS_P2_P3_CFIFO_ENTRIES; | |
4010 | } else | |
4011 | max = NIU_CFIFO_ENTRIES; | |
4012 | ||
4013 | data[0] = 0; | |
4014 | data[1] = 0; | |
4015 | data[2] = 0; | |
4016 | data[3] = 0; | |
4017 | data[4] = 0; | |
4018 | ||
4019 | for (i = 0; i < max; i++) { | |
4020 | err = niu_zcp_write(np, i, data); | |
4021 | if (err) | |
4022 | return err; | |
4023 | err = niu_zcp_read(np, i, rbuf); | |
4024 | if (err) | |
4025 | return err; | |
4026 | } | |
4027 | ||
4028 | niu_zcp_cfifo_reset(np); | |
4029 | nw64(CFIFO_ECC(np->port), 0); | |
4030 | nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL); | |
4031 | (void) nr64(ZCP_INT_STAT); | |
4032 | nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL); | |
4033 | ||
4034 | return 0; | |
4035 | } | |
4036 | ||
4037 | static void niu_ipp_write(struct niu *np, int index, u64 *data) | |
4038 | { | |
4039 | u64 val = nr64_ipp(IPP_CFIG); | |
4040 | ||
4041 | nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W); | |
4042 | nw64_ipp(IPP_DFIFO_WR_PTR, index); | |
4043 | nw64_ipp(IPP_DFIFO_WR0, data[0]); | |
4044 | nw64_ipp(IPP_DFIFO_WR1, data[1]); | |
4045 | nw64_ipp(IPP_DFIFO_WR2, data[2]); | |
4046 | nw64_ipp(IPP_DFIFO_WR3, data[3]); | |
4047 | nw64_ipp(IPP_DFIFO_WR4, data[4]); | |
4048 | nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W); | |
4049 | } | |
4050 | ||
4051 | static void niu_ipp_read(struct niu *np, int index, u64 *data) | |
4052 | { | |
4053 | nw64_ipp(IPP_DFIFO_RD_PTR, index); | |
4054 | data[0] = nr64_ipp(IPP_DFIFO_RD0); | |
4055 | data[1] = nr64_ipp(IPP_DFIFO_RD1); | |
4056 | data[2] = nr64_ipp(IPP_DFIFO_RD2); | |
4057 | data[3] = nr64_ipp(IPP_DFIFO_RD3); | |
4058 | data[4] = nr64_ipp(IPP_DFIFO_RD4); | |
4059 | } | |
4060 | ||
4061 | static int niu_ipp_reset(struct niu *np) | |
4062 | { | |
4063 | return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST, | |
4064 | 1000, 100, "IPP_CFIG"); | |
4065 | } | |
4066 | ||
4067 | static int niu_init_ipp(struct niu *np) | |
4068 | { | |
4069 | u64 data[5], rbuf[5], val; | |
4070 | int i, max, err; | |
4071 | ||
4072 | if (np->parent->plat_type != PLAT_TYPE_NIU) { | |
4073 | if (np->port == 0 || np->port == 1) | |
4074 | max = ATLAS_P0_P1_DFIFO_ENTRIES; | |
4075 | else | |
4076 | max = ATLAS_P2_P3_DFIFO_ENTRIES; | |
4077 | } else | |
4078 | max = NIU_DFIFO_ENTRIES; | |
4079 | ||
4080 | data[0] = 0; | |
4081 | data[1] = 0; | |
4082 | data[2] = 0; | |
4083 | data[3] = 0; | |
4084 | data[4] = 0; | |
4085 | ||
4086 | for (i = 0; i < max; i++) { | |
4087 | niu_ipp_write(np, i, data); | |
4088 | niu_ipp_read(np, i, rbuf); | |
4089 | } | |
4090 | ||
4091 | (void) nr64_ipp(IPP_INT_STAT); | |
4092 | (void) nr64_ipp(IPP_INT_STAT); | |
4093 | ||
4094 | err = niu_ipp_reset(np); | |
4095 | if (err) | |
4096 | return err; | |
4097 | ||
4098 | (void) nr64_ipp(IPP_PKT_DIS); | |
4099 | (void) nr64_ipp(IPP_BAD_CS_CNT); | |
4100 | (void) nr64_ipp(IPP_ECC); | |
4101 | ||
4102 | (void) nr64_ipp(IPP_INT_STAT); | |
4103 | ||
4104 | nw64_ipp(IPP_MSK, ~IPP_MSK_ALL); | |
4105 | ||
4106 | val = nr64_ipp(IPP_CFIG); | |
4107 | val &= ~IPP_CFIG_IP_MAX_PKT; | |
4108 | val |= (IPP_CFIG_IPP_ENABLE | | |
4109 | IPP_CFIG_DFIFO_ECC_EN | | |
4110 | IPP_CFIG_DROP_BAD_CRC | | |
4111 | IPP_CFIG_CKSUM_EN | | |
4112 | (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT)); | |
4113 | nw64_ipp(IPP_CFIG, val); | |
4114 | ||
4115 | return 0; | |
4116 | } | |
4117 | ||
0c3b091b | 4118 | static void niu_handle_led(struct niu *np, int status) |
a3138df9 | 4119 | { |
a3138df9 | 4120 | u64 val; |
a3138df9 DM |
4121 | val = nr64_mac(XMAC_CONFIG); |
4122 | ||
4123 | if ((np->flags & NIU_FLAGS_10G) != 0 && | |
4124 | (np->flags & NIU_FLAGS_FIBER) != 0) { | |
0c3b091b | 4125 | if (status) { |
a3138df9 DM |
4126 | val |= XMAC_CONFIG_LED_POLARITY; |
4127 | val &= ~XMAC_CONFIG_FORCE_LED_ON; | |
4128 | } else { | |
4129 | val |= XMAC_CONFIG_FORCE_LED_ON; | |
4130 | val &= ~XMAC_CONFIG_LED_POLARITY; | |
4131 | } | |
4132 | } | |
4133 | ||
0c3b091b ML |
4134 | nw64_mac(XMAC_CONFIG, val); |
4135 | } | |
4136 | ||
4137 | static void niu_init_xif_xmac(struct niu *np) | |
4138 | { | |
4139 | struct niu_link_config *lp = &np->link_config; | |
4140 | u64 val; | |
4141 | ||
4142 | val = nr64_mac(XMAC_CONFIG); | |
a3138df9 DM |
4143 | val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC; |
4144 | ||
4145 | val |= XMAC_CONFIG_TX_OUTPUT_EN; | |
4146 | ||
4147 | if (lp->loopback_mode == LOOPBACK_MAC) { | |
4148 | val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC; | |
4149 | val |= XMAC_CONFIG_LOOPBACK; | |
4150 | } else { | |
4151 | val &= ~XMAC_CONFIG_LOOPBACK; | |
4152 | } | |
4153 | ||
4154 | if (np->flags & NIU_FLAGS_10G) { | |
4155 | val &= ~XMAC_CONFIG_LFS_DISABLE; | |
4156 | } else { | |
4157 | val |= XMAC_CONFIG_LFS_DISABLE; | |
4158 | if (!(np->flags & NIU_FLAGS_FIBER)) | |
4159 | val |= XMAC_CONFIG_1G_PCS_BYPASS; | |
4160 | else | |
4161 | val &= ~XMAC_CONFIG_1G_PCS_BYPASS; | |
4162 | } | |
4163 | ||
4164 | val &= ~XMAC_CONFIG_10G_XPCS_BYPASS; | |
4165 | ||
4166 | if (lp->active_speed == SPEED_100) | |
4167 | val |= XMAC_CONFIG_SEL_CLK_25MHZ; | |
4168 | else | |
4169 | val &= ~XMAC_CONFIG_SEL_CLK_25MHZ; | |
4170 | ||
4171 | nw64_mac(XMAC_CONFIG, val); | |
4172 | ||
4173 | val = nr64_mac(XMAC_CONFIG); | |
4174 | val &= ~XMAC_CONFIG_MODE_MASK; | |
4175 | if (np->flags & NIU_FLAGS_10G) { | |
4176 | val |= XMAC_CONFIG_MODE_XGMII; | |
4177 | } else { | |
4178 | if (lp->active_speed == SPEED_100) | |
4179 | val |= XMAC_CONFIG_MODE_MII; | |
4180 | else | |
4181 | val |= XMAC_CONFIG_MODE_GMII; | |
4182 | } | |
4183 | ||
4184 | nw64_mac(XMAC_CONFIG, val); | |
4185 | } | |
4186 | ||
4187 | static void niu_init_xif_bmac(struct niu *np) | |
4188 | { | |
4189 | struct niu_link_config *lp = &np->link_config; | |
4190 | u64 val; | |
4191 | ||
4192 | val = BMAC_XIF_CONFIG_TX_OUTPUT_EN; | |
4193 | ||
4194 | if (lp->loopback_mode == LOOPBACK_MAC) | |
4195 | val |= BMAC_XIF_CONFIG_MII_LOOPBACK; | |
4196 | else | |
4197 | val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK; | |
4198 | ||
4199 | if (lp->active_speed == SPEED_1000) | |
4200 | val |= BMAC_XIF_CONFIG_GMII_MODE; | |
4201 | else | |
4202 | val &= ~BMAC_XIF_CONFIG_GMII_MODE; | |
4203 | ||
4204 | val &= ~(BMAC_XIF_CONFIG_LINK_LED | | |
4205 | BMAC_XIF_CONFIG_LED_POLARITY); | |
4206 | ||
4207 | if (!(np->flags & NIU_FLAGS_10G) && | |
4208 | !(np->flags & NIU_FLAGS_FIBER) && | |
4209 | lp->active_speed == SPEED_100) | |
4210 | val |= BMAC_XIF_CONFIG_25MHZ_CLOCK; | |
4211 | else | |
4212 | val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK; | |
4213 | ||
4214 | nw64_mac(BMAC_XIF_CONFIG, val); | |
4215 | } | |
4216 | ||
4217 | static void niu_init_xif(struct niu *np) | |
4218 | { | |
4219 | if (np->flags & NIU_FLAGS_XMAC) | |
4220 | niu_init_xif_xmac(np); | |
4221 | else | |
4222 | niu_init_xif_bmac(np); | |
4223 | } | |
4224 | ||
4225 | static void niu_pcs_mii_reset(struct niu *np) | |
4226 | { | |
4227 | u64 val = nr64_pcs(PCS_MII_CTL); | |
4228 | val |= PCS_MII_CTL_RST; | |
4229 | nw64_pcs(PCS_MII_CTL, val); | |
4230 | } | |
4231 | ||
4232 | static void niu_xpcs_reset(struct niu *np) | |
4233 | { | |
4234 | u64 val = nr64_xpcs(XPCS_CONTROL1); | |
4235 | val |= XPCS_CONTROL1_RESET; | |
4236 | nw64_xpcs(XPCS_CONTROL1, val); | |
4237 | } | |
4238 | ||
4239 | static int niu_init_pcs(struct niu *np) | |
4240 | { | |
4241 | struct niu_link_config *lp = &np->link_config; | |
4242 | u64 val; | |
4243 | ||
4244 | switch (np->flags & (NIU_FLAGS_10G | NIU_FLAGS_FIBER)) { | |
4245 | case NIU_FLAGS_FIBER: | |
4246 | /* 1G fiber */ | |
4247 | nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE); | |
4248 | nw64_pcs(PCS_DPATH_MODE, 0); | |
4249 | niu_pcs_mii_reset(np); | |
4250 | break; | |
4251 | ||
4252 | case NIU_FLAGS_10G: | |
4253 | case NIU_FLAGS_10G | NIU_FLAGS_FIBER: | |
4254 | if (!(np->flags & NIU_FLAGS_XMAC)) | |
4255 | return -EINVAL; | |
4256 | ||
4257 | /* 10G copper or fiber */ | |
4258 | val = nr64_mac(XMAC_CONFIG); | |
4259 | val &= ~XMAC_CONFIG_10G_XPCS_BYPASS; | |
4260 | nw64_mac(XMAC_CONFIG, val); | |
4261 | ||
4262 | niu_xpcs_reset(np); | |
4263 | ||
4264 | val = nr64_xpcs(XPCS_CONTROL1); | |
4265 | if (lp->loopback_mode == LOOPBACK_PHY) | |
4266 | val |= XPCS_CONTROL1_LOOPBACK; | |
4267 | else | |
4268 | val &= ~XPCS_CONTROL1_LOOPBACK; | |
4269 | nw64_xpcs(XPCS_CONTROL1, val); | |
4270 | ||
4271 | nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0); | |
4272 | (void) nr64_xpcs(XPCS_SYMERR_CNT01); | |
4273 | (void) nr64_xpcs(XPCS_SYMERR_CNT23); | |
4274 | break; | |
4275 | ||
4276 | case 0: | |
4277 | /* 1G copper */ | |
4278 | nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII); | |
4279 | niu_pcs_mii_reset(np); | |
4280 | break; | |
4281 | ||
4282 | default: | |
4283 | return -EINVAL; | |
4284 | } | |
4285 | ||
4286 | return 0; | |
4287 | } | |
4288 | ||
4289 | static int niu_reset_tx_xmac(struct niu *np) | |
4290 | { | |
4291 | return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST, | |
4292 | (XTXMAC_SW_RST_REG_RS | | |
4293 | XTXMAC_SW_RST_SOFT_RST), | |
4294 | 1000, 100, "XTXMAC_SW_RST"); | |
4295 | } | |
4296 | ||
4297 | static int niu_reset_tx_bmac(struct niu *np) | |
4298 | { | |
4299 | int limit; | |
4300 | ||
4301 | nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET); | |
4302 | limit = 1000; | |
4303 | while (--limit >= 0) { | |
4304 | if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET)) | |
4305 | break; | |
4306 | udelay(100); | |
4307 | } | |
4308 | if (limit < 0) { | |
4309 | dev_err(np->device, PFX "Port %u TX BMAC would not reset, " | |
4310 | "BTXMAC_SW_RST[%llx]\n", | |
4311 | np->port, | |
4312 | (unsigned long long) nr64_mac(BTXMAC_SW_RST)); | |
4313 | return -ENODEV; | |
4314 | } | |
4315 | ||
4316 | return 0; | |
4317 | } | |
4318 | ||
4319 | static int niu_reset_tx_mac(struct niu *np) | |
4320 | { | |
4321 | if (np->flags & NIU_FLAGS_XMAC) | |
4322 | return niu_reset_tx_xmac(np); | |
4323 | else | |
4324 | return niu_reset_tx_bmac(np); | |
4325 | } | |
4326 | ||
4327 | static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max) | |
4328 | { | |
4329 | u64 val; | |
4330 | ||
4331 | val = nr64_mac(XMAC_MIN); | |
4332 | val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE | | |
4333 | XMAC_MIN_RX_MIN_PKT_SIZE); | |
4334 | val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT); | |
4335 | val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT); | |
4336 | nw64_mac(XMAC_MIN, val); | |
4337 | ||
4338 | nw64_mac(XMAC_MAX, max); | |
4339 | ||
4340 | nw64_mac(XTXMAC_STAT_MSK, ~(u64)0); | |
4341 | ||
4342 | val = nr64_mac(XMAC_IPG); | |
4343 | if (np->flags & NIU_FLAGS_10G) { | |
4344 | val &= ~XMAC_IPG_IPG_XGMII; | |
4345 | val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT); | |
4346 | } else { | |
4347 | val &= ~XMAC_IPG_IPG_MII_GMII; | |
4348 | val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT); | |
4349 | } | |
4350 | nw64_mac(XMAC_IPG, val); | |
4351 | ||
4352 | val = nr64_mac(XMAC_CONFIG); | |
4353 | val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC | | |
4354 | XMAC_CONFIG_STRETCH_MODE | | |
4355 | XMAC_CONFIG_VAR_MIN_IPG_EN | | |
4356 | XMAC_CONFIG_TX_ENABLE); | |
4357 | nw64_mac(XMAC_CONFIG, val); | |
4358 | ||
4359 | nw64_mac(TXMAC_FRM_CNT, 0); | |
4360 | nw64_mac(TXMAC_BYTE_CNT, 0); | |
4361 | } | |
4362 | ||
4363 | static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max) | |
4364 | { | |
4365 | u64 val; | |
4366 | ||
4367 | nw64_mac(BMAC_MIN_FRAME, min); | |
4368 | nw64_mac(BMAC_MAX_FRAME, max); | |
4369 | ||
4370 | nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0); | |
4371 | nw64_mac(BMAC_CTRL_TYPE, 0x8808); | |
4372 | nw64_mac(BMAC_PREAMBLE_SIZE, 7); | |
4373 | ||
4374 | val = nr64_mac(BTXMAC_CONFIG); | |
4375 | val &= ~(BTXMAC_CONFIG_FCS_DISABLE | | |
4376 | BTXMAC_CONFIG_ENABLE); | |
4377 | nw64_mac(BTXMAC_CONFIG, val); | |
4378 | } | |
4379 | ||
4380 | static void niu_init_tx_mac(struct niu *np) | |
4381 | { | |
4382 | u64 min, max; | |
4383 | ||
4384 | min = 64; | |
4385 | if (np->dev->mtu > ETH_DATA_LEN) | |
4386 | max = 9216; | |
4387 | else | |
4388 | max = 1522; | |
4389 | ||
4390 | /* The XMAC_MIN register only accepts values for TX min which | |
4391 | * have the low 3 bits cleared. | |
4392 | */ | |
4393 | BUILD_BUG_ON(min & 0x7); | |
4394 | ||
4395 | if (np->flags & NIU_FLAGS_XMAC) | |
4396 | niu_init_tx_xmac(np, min, max); | |
4397 | else | |
4398 | niu_init_tx_bmac(np, min, max); | |
4399 | } | |
4400 | ||
4401 | static int niu_reset_rx_xmac(struct niu *np) | |
4402 | { | |
4403 | int limit; | |
4404 | ||
4405 | nw64_mac(XRXMAC_SW_RST, | |
4406 | XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST); | |
4407 | limit = 1000; | |
4408 | while (--limit >= 0) { | |
4409 | if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS | | |
4410 | XRXMAC_SW_RST_SOFT_RST))) | |
4411 | break; | |
4412 | udelay(100); | |
4413 | } | |
4414 | if (limit < 0) { | |
4415 | dev_err(np->device, PFX "Port %u RX XMAC would not reset, " | |
4416 | "XRXMAC_SW_RST[%llx]\n", | |
4417 | np->port, | |
4418 | (unsigned long long) nr64_mac(XRXMAC_SW_RST)); | |
4419 | return -ENODEV; | |
4420 | } | |
4421 | ||
4422 | return 0; | |
4423 | } | |
4424 | ||
4425 | static int niu_reset_rx_bmac(struct niu *np) | |
4426 | { | |
4427 | int limit; | |
4428 | ||
4429 | nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET); | |
4430 | limit = 1000; | |
4431 | while (--limit >= 0) { | |
4432 | if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET)) | |
4433 | break; | |
4434 | udelay(100); | |
4435 | } | |
4436 | if (limit < 0) { | |
4437 | dev_err(np->device, PFX "Port %u RX BMAC would not reset, " | |
4438 | "BRXMAC_SW_RST[%llx]\n", | |
4439 | np->port, | |
4440 | (unsigned long long) nr64_mac(BRXMAC_SW_RST)); | |
4441 | return -ENODEV; | |
4442 | } | |
4443 | ||
4444 | return 0; | |
4445 | } | |
4446 | ||
4447 | static int niu_reset_rx_mac(struct niu *np) | |
4448 | { | |
4449 | if (np->flags & NIU_FLAGS_XMAC) | |
4450 | return niu_reset_rx_xmac(np); | |
4451 | else | |
4452 | return niu_reset_rx_bmac(np); | |
4453 | } | |
4454 | ||
4455 | static void niu_init_rx_xmac(struct niu *np) | |
4456 | { | |
4457 | struct niu_parent *parent = np->parent; | |
4458 | struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port]; | |
4459 | int first_rdc_table = tp->first_table_num; | |
4460 | unsigned long i; | |
4461 | u64 val; | |
4462 | ||
4463 | nw64_mac(XMAC_ADD_FILT0, 0); | |
4464 | nw64_mac(XMAC_ADD_FILT1, 0); | |
4465 | nw64_mac(XMAC_ADD_FILT2, 0); | |
4466 | nw64_mac(XMAC_ADD_FILT12_MASK, 0); | |
4467 | nw64_mac(XMAC_ADD_FILT00_MASK, 0); | |
4468 | for (i = 0; i < MAC_NUM_HASH; i++) | |
4469 | nw64_mac(XMAC_HASH_TBL(i), 0); | |
4470 | nw64_mac(XRXMAC_STAT_MSK, ~(u64)0); | |
4471 | niu_set_primary_mac_rdc_table(np, first_rdc_table, 1); | |
4472 | niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1); | |
4473 | ||
4474 | val = nr64_mac(XMAC_CONFIG); | |
4475 | val &= ~(XMAC_CONFIG_RX_MAC_ENABLE | | |
4476 | XMAC_CONFIG_PROMISCUOUS | | |
4477 | XMAC_CONFIG_PROMISC_GROUP | | |
4478 | XMAC_CONFIG_ERR_CHK_DIS | | |
4479 | XMAC_CONFIG_RX_CRC_CHK_DIS | | |
4480 | XMAC_CONFIG_RESERVED_MULTICAST | | |
4481 | XMAC_CONFIG_RX_CODEV_CHK_DIS | | |
4482 | XMAC_CONFIG_ADDR_FILTER_EN | | |
4483 | XMAC_CONFIG_RCV_PAUSE_ENABLE | | |
4484 | XMAC_CONFIG_STRIP_CRC | | |
4485 | XMAC_CONFIG_PASS_FLOW_CTRL | | |
4486 | XMAC_CONFIG_MAC2IPP_PKT_CNT_EN); | |
4487 | val |= (XMAC_CONFIG_HASH_FILTER_EN); | |
4488 | nw64_mac(XMAC_CONFIG, val); | |
4489 | ||
4490 | nw64_mac(RXMAC_BT_CNT, 0); | |
4491 | nw64_mac(RXMAC_BC_FRM_CNT, 0); | |
4492 | nw64_mac(RXMAC_MC_FRM_CNT, 0); | |
4493 | nw64_mac(RXMAC_FRAG_CNT, 0); | |
4494 | nw64_mac(RXMAC_HIST_CNT1, 0); | |
4495 | nw64_mac(RXMAC_HIST_CNT2, 0); | |
4496 | nw64_mac(RXMAC_HIST_CNT3, 0); | |
4497 | nw64_mac(RXMAC_HIST_CNT4, 0); | |
4498 | nw64_mac(RXMAC_HIST_CNT5, 0); | |
4499 | nw64_mac(RXMAC_HIST_CNT6, 0); | |
4500 | nw64_mac(RXMAC_HIST_CNT7, 0); | |
4501 | nw64_mac(RXMAC_MPSZER_CNT, 0); | |
4502 | nw64_mac(RXMAC_CRC_ER_CNT, 0); | |
4503 | nw64_mac(RXMAC_CD_VIO_CNT, 0); | |
4504 | nw64_mac(LINK_FAULT_CNT, 0); | |
4505 | } | |
4506 | ||
4507 | static void niu_init_rx_bmac(struct niu *np) | |
4508 | { | |
4509 | struct niu_parent *parent = np->parent; | |
4510 | struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port]; | |
4511 | int first_rdc_table = tp->first_table_num; | |
4512 | unsigned long i; | |
4513 | u64 val; | |
4514 | ||
4515 | nw64_mac(BMAC_ADD_FILT0, 0); | |
4516 | nw64_mac(BMAC_ADD_FILT1, 0); | |
4517 | nw64_mac(BMAC_ADD_FILT2, 0); | |
4518 | nw64_mac(BMAC_ADD_FILT12_MASK, 0); | |
4519 | nw64_mac(BMAC_ADD_FILT00_MASK, 0); | |
4520 | for (i = 0; i < MAC_NUM_HASH; i++) | |
4521 | nw64_mac(BMAC_HASH_TBL(i), 0); | |
4522 | niu_set_primary_mac_rdc_table(np, first_rdc_table, 1); | |
4523 | niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1); | |
4524 | nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0); | |
4525 | ||
4526 | val = nr64_mac(BRXMAC_CONFIG); | |
4527 | val &= ~(BRXMAC_CONFIG_ENABLE | | |
4528 | BRXMAC_CONFIG_STRIP_PAD | | |
4529 | BRXMAC_CONFIG_STRIP_FCS | | |
4530 | BRXMAC_CONFIG_PROMISC | | |
4531 | BRXMAC_CONFIG_PROMISC_GRP | | |
4532 | BRXMAC_CONFIG_ADDR_FILT_EN | | |
4533 | BRXMAC_CONFIG_DISCARD_DIS); | |
4534 | val |= (BRXMAC_CONFIG_HASH_FILT_EN); | |
4535 | nw64_mac(BRXMAC_CONFIG, val); | |
4536 | ||
4537 | val = nr64_mac(BMAC_ADDR_CMPEN); | |
4538 | val |= BMAC_ADDR_CMPEN_EN0; | |
4539 | nw64_mac(BMAC_ADDR_CMPEN, val); | |
4540 | } | |
4541 | ||
4542 | static void niu_init_rx_mac(struct niu *np) | |
4543 | { | |
4544 | niu_set_primary_mac(np, np->dev->dev_addr); | |
4545 | ||
4546 | if (np->flags & NIU_FLAGS_XMAC) | |
4547 | niu_init_rx_xmac(np); | |
4548 | else | |
4549 | niu_init_rx_bmac(np); | |
4550 | } | |
4551 | ||
4552 | static void niu_enable_tx_xmac(struct niu *np, int on) | |
4553 | { | |
4554 | u64 val = nr64_mac(XMAC_CONFIG); | |
4555 | ||
4556 | if (on) | |
4557 | val |= XMAC_CONFIG_TX_ENABLE; | |
4558 | else | |
4559 | val &= ~XMAC_CONFIG_TX_ENABLE; | |
4560 | nw64_mac(XMAC_CONFIG, val); | |
4561 | } | |
4562 | ||
4563 | static void niu_enable_tx_bmac(struct niu *np, int on) | |
4564 | { | |
4565 | u64 val = nr64_mac(BTXMAC_CONFIG); | |
4566 | ||
4567 | if (on) | |
4568 | val |= BTXMAC_CONFIG_ENABLE; | |
4569 | else | |
4570 | val &= ~BTXMAC_CONFIG_ENABLE; | |
4571 | nw64_mac(BTXMAC_CONFIG, val); | |
4572 | } | |
4573 | ||
4574 | static void niu_enable_tx_mac(struct niu *np, int on) | |
4575 | { | |
4576 | if (np->flags & NIU_FLAGS_XMAC) | |
4577 | niu_enable_tx_xmac(np, on); | |
4578 | else | |
4579 | niu_enable_tx_bmac(np, on); | |
4580 | } | |
4581 | ||
4582 | static void niu_enable_rx_xmac(struct niu *np, int on) | |
4583 | { | |
4584 | u64 val = nr64_mac(XMAC_CONFIG); | |
4585 | ||
4586 | val &= ~(XMAC_CONFIG_HASH_FILTER_EN | | |
4587 | XMAC_CONFIG_PROMISCUOUS); | |
4588 | ||
4589 | if (np->flags & NIU_FLAGS_MCAST) | |
4590 | val |= XMAC_CONFIG_HASH_FILTER_EN; | |
4591 | if (np->flags & NIU_FLAGS_PROMISC) | |
4592 | val |= XMAC_CONFIG_PROMISCUOUS; | |
4593 | ||
4594 | if (on) | |
4595 | val |= XMAC_CONFIG_RX_MAC_ENABLE; | |
4596 | else | |
4597 | val &= ~XMAC_CONFIG_RX_MAC_ENABLE; | |
4598 | nw64_mac(XMAC_CONFIG, val); | |
4599 | } | |
4600 | ||
4601 | static void niu_enable_rx_bmac(struct niu *np, int on) | |
4602 | { | |
4603 | u64 val = nr64_mac(BRXMAC_CONFIG); | |
4604 | ||
4605 | val &= ~(BRXMAC_CONFIG_HASH_FILT_EN | | |
4606 | BRXMAC_CONFIG_PROMISC); | |
4607 | ||
4608 | if (np->flags & NIU_FLAGS_MCAST) | |
4609 | val |= BRXMAC_CONFIG_HASH_FILT_EN; | |
4610 | if (np->flags & NIU_FLAGS_PROMISC) | |
4611 | val |= BRXMAC_CONFIG_PROMISC; | |
4612 | ||
4613 | if (on) | |
4614 | val |= BRXMAC_CONFIG_ENABLE; | |
4615 | else | |
4616 | val &= ~BRXMAC_CONFIG_ENABLE; | |
4617 | nw64_mac(BRXMAC_CONFIG, val); | |
4618 | } | |
4619 | ||
4620 | static void niu_enable_rx_mac(struct niu *np, int on) | |
4621 | { | |
4622 | if (np->flags & NIU_FLAGS_XMAC) | |
4623 | niu_enable_rx_xmac(np, on); | |
4624 | else | |
4625 | niu_enable_rx_bmac(np, on); | |
4626 | } | |
4627 | ||
4628 | static int niu_init_mac(struct niu *np) | |
4629 | { | |
4630 | int err; | |
4631 | ||
4632 | niu_init_xif(np); | |
4633 | err = niu_init_pcs(np); | |
4634 | if (err) | |
4635 | return err; | |
4636 | ||
4637 | err = niu_reset_tx_mac(np); | |
4638 | if (err) | |
4639 | return err; | |
4640 | niu_init_tx_mac(np); | |
4641 | err = niu_reset_rx_mac(np); | |
4642 | if (err) | |
4643 | return err; | |
4644 | niu_init_rx_mac(np); | |
4645 | ||
4646 | /* This looks hookey but the RX MAC reset we just did will | |
4647 | * undo some of the state we setup in niu_init_tx_mac() so we | |
4648 | * have to call it again. In particular, the RX MAC reset will | |
4649 | * set the XMAC_MAX register back to it's default value. | |
4650 | */ | |
4651 | niu_init_tx_mac(np); | |
4652 | niu_enable_tx_mac(np, 1); | |
4653 | ||
4654 | niu_enable_rx_mac(np, 1); | |
4655 | ||
4656 | return 0; | |
4657 | } | |
4658 | ||
4659 | static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp) | |
4660 | { | |
4661 | (void) niu_tx_channel_stop(np, rp->tx_channel); | |
4662 | } | |
4663 | ||
4664 | static void niu_stop_tx_channels(struct niu *np) | |
4665 | { | |
4666 | int i; | |
4667 | ||
4668 | for (i = 0; i < np->num_tx_rings; i++) { | |
4669 | struct tx_ring_info *rp = &np->tx_rings[i]; | |
4670 | ||
4671 | niu_stop_one_tx_channel(np, rp); | |
4672 | } | |
4673 | } | |
4674 | ||
4675 | static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp) | |
4676 | { | |
4677 | (void) niu_tx_channel_reset(np, rp->tx_channel); | |
4678 | } | |
4679 | ||
4680 | static void niu_reset_tx_channels(struct niu *np) | |
4681 | { | |
4682 | int i; | |
4683 | ||
4684 | for (i = 0; i < np->num_tx_rings; i++) { | |
4685 | struct tx_ring_info *rp = &np->tx_rings[i]; | |
4686 | ||
4687 | niu_reset_one_tx_channel(np, rp); | |
4688 | } | |
4689 | } | |
4690 | ||
4691 | static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp) | |
4692 | { | |
4693 | (void) niu_enable_rx_channel(np, rp->rx_channel, 0); | |
4694 | } | |
4695 | ||
4696 | static void niu_stop_rx_channels(struct niu *np) | |
4697 | { | |
4698 | int i; | |
4699 | ||
4700 | for (i = 0; i < np->num_rx_rings; i++) { | |
4701 | struct rx_ring_info *rp = &np->rx_rings[i]; | |
4702 | ||
4703 | niu_stop_one_rx_channel(np, rp); | |
4704 | } | |
4705 | } | |
4706 | ||
4707 | static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp) | |
4708 | { | |
4709 | int channel = rp->rx_channel; | |
4710 | ||
4711 | (void) niu_rx_channel_reset(np, channel); | |
4712 | nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL); | |
4713 | nw64(RX_DMA_CTL_STAT(channel), 0); | |
4714 | (void) niu_enable_rx_channel(np, channel, 0); | |
4715 | } | |
4716 | ||
4717 | static void niu_reset_rx_channels(struct niu *np) | |
4718 | { | |
4719 | int i; | |
4720 | ||
4721 | for (i = 0; i < np->num_rx_rings; i++) { | |
4722 | struct rx_ring_info *rp = &np->rx_rings[i]; | |
4723 | ||
4724 | niu_reset_one_rx_channel(np, rp); | |
4725 | } | |
4726 | } | |
4727 | ||
4728 | static void niu_disable_ipp(struct niu *np) | |
4729 | { | |
4730 | u64 rd, wr, val; | |
4731 | int limit; | |
4732 | ||
4733 | rd = nr64_ipp(IPP_DFIFO_RD_PTR); | |
4734 | wr = nr64_ipp(IPP_DFIFO_WR_PTR); | |
4735 | limit = 100; | |
4736 | while (--limit >= 0 && (rd != wr)) { | |
4737 | rd = nr64_ipp(IPP_DFIFO_RD_PTR); | |
4738 | wr = nr64_ipp(IPP_DFIFO_WR_PTR); | |
4739 | } | |
4740 | if (limit < 0 && | |
4741 | (rd != 0 && wr != 1)) { | |
4742 | dev_err(np->device, PFX "%s: IPP would not quiesce, " | |
4743 | "rd_ptr[%llx] wr_ptr[%llx]\n", | |
4744 | np->dev->name, | |
4745 | (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR), | |
4746 | (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR)); | |
4747 | } | |
4748 | ||
4749 | val = nr64_ipp(IPP_CFIG); | |
4750 | val &= ~(IPP_CFIG_IPP_ENABLE | | |
4751 | IPP_CFIG_DFIFO_ECC_EN | | |
4752 | IPP_CFIG_DROP_BAD_CRC | | |
4753 | IPP_CFIG_CKSUM_EN); | |
4754 | nw64_ipp(IPP_CFIG, val); | |
4755 | ||
4756 | (void) niu_ipp_reset(np); | |
4757 | } | |
4758 | ||
4759 | static int niu_init_hw(struct niu *np) | |
4760 | { | |
4761 | int i, err; | |
4762 | ||
4763 | niudbg(IFUP, "%s: Initialize TXC\n", np->dev->name); | |
4764 | niu_txc_enable_port(np, 1); | |
4765 | niu_txc_port_dma_enable(np, 1); | |
4766 | niu_txc_set_imask(np, 0); | |
4767 | ||
4768 | niudbg(IFUP, "%s: Initialize TX channels\n", np->dev->name); | |
4769 | for (i = 0; i < np->num_tx_rings; i++) { | |
4770 | struct tx_ring_info *rp = &np->tx_rings[i]; | |
4771 | ||
4772 | err = niu_init_one_tx_channel(np, rp); | |
4773 | if (err) | |
4774 | return err; | |
4775 | } | |
4776 | ||
4777 | niudbg(IFUP, "%s: Initialize RX channels\n", np->dev->name); | |
4778 | err = niu_init_rx_channels(np); | |
4779 | if (err) | |
4780 | goto out_uninit_tx_channels; | |
4781 | ||
4782 | niudbg(IFUP, "%s: Initialize classifier\n", np->dev->name); | |
4783 | err = niu_init_classifier_hw(np); | |
4784 | if (err) | |
4785 | goto out_uninit_rx_channels; | |
4786 | ||
4787 | niudbg(IFUP, "%s: Initialize ZCP\n", np->dev->name); | |
4788 | err = niu_init_zcp(np); | |
4789 | if (err) | |
4790 | goto out_uninit_rx_channels; | |
4791 | ||
4792 | niudbg(IFUP, "%s: Initialize IPP\n", np->dev->name); | |
4793 | err = niu_init_ipp(np); | |
4794 | if (err) | |
4795 | goto out_uninit_rx_channels; | |
4796 | ||
4797 | niudbg(IFUP, "%s: Initialize MAC\n", np->dev->name); | |
4798 | err = niu_init_mac(np); | |
4799 | if (err) | |
4800 | goto out_uninit_ipp; | |
4801 | ||
4802 | return 0; | |
4803 | ||
4804 | out_uninit_ipp: | |
4805 | niudbg(IFUP, "%s: Uninit IPP\n", np->dev->name); | |
4806 | niu_disable_ipp(np); | |
4807 | ||
4808 | out_uninit_rx_channels: | |
4809 | niudbg(IFUP, "%s: Uninit RX channels\n", np->dev->name); | |
4810 | niu_stop_rx_channels(np); | |
4811 | niu_reset_rx_channels(np); | |
4812 | ||
4813 | out_uninit_tx_channels: | |
4814 | niudbg(IFUP, "%s: Uninit TX channels\n", np->dev->name); | |
4815 | niu_stop_tx_channels(np); | |
4816 | niu_reset_tx_channels(np); | |
4817 | ||
4818 | return err; | |
4819 | } | |
4820 | ||
4821 | static void niu_stop_hw(struct niu *np) | |
4822 | { | |
4823 | niudbg(IFDOWN, "%s: Disable interrupts\n", np->dev->name); | |
4824 | niu_enable_interrupts(np, 0); | |
4825 | ||
4826 | niudbg(IFDOWN, "%s: Disable RX MAC\n", np->dev->name); | |
4827 | niu_enable_rx_mac(np, 0); | |
4828 | ||
4829 | niudbg(IFDOWN, "%s: Disable IPP\n", np->dev->name); | |
4830 | niu_disable_ipp(np); | |
4831 | ||
4832 | niudbg(IFDOWN, "%s: Stop TX channels\n", np->dev->name); | |
4833 | niu_stop_tx_channels(np); | |
4834 | ||
4835 | niudbg(IFDOWN, "%s: Stop RX channels\n", np->dev->name); | |
4836 | niu_stop_rx_channels(np); | |
4837 | ||
4838 | niudbg(IFDOWN, "%s: Reset TX channels\n", np->dev->name); | |
4839 | niu_reset_tx_channels(np); | |
4840 | ||
4841 | niudbg(IFDOWN, "%s: Reset RX channels\n", np->dev->name); | |
4842 | niu_reset_rx_channels(np); | |
4843 | } | |
4844 | ||
4845 | static int niu_request_irq(struct niu *np) | |
4846 | { | |
4847 | int i, j, err; | |
4848 | ||
4849 | err = 0; | |
4850 | for (i = 0; i < np->num_ldg; i++) { | |
4851 | struct niu_ldg *lp = &np->ldg[i]; | |
4852 | ||
4853 | err = request_irq(lp->irq, niu_interrupt, | |
4854 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, | |
4855 | np->dev->name, lp); | |
4856 | if (err) | |
4857 | goto out_free_irqs; | |
4858 | ||
4859 | } | |
4860 | ||
4861 | return 0; | |
4862 | ||
4863 | out_free_irqs: | |
4864 | for (j = 0; j < i; j++) { | |
4865 | struct niu_ldg *lp = &np->ldg[j]; | |
4866 | ||
4867 | free_irq(lp->irq, lp); | |
4868 | } | |
4869 | return err; | |
4870 | } | |
4871 | ||
4872 | static void niu_free_irq(struct niu *np) | |
4873 | { | |
4874 | int i; | |
4875 | ||
4876 | for (i = 0; i < np->num_ldg; i++) { | |
4877 | struct niu_ldg *lp = &np->ldg[i]; | |
4878 | ||
4879 | free_irq(lp->irq, lp); | |
4880 | } | |
4881 | } | |
4882 | ||
4883 | static void niu_enable_napi(struct niu *np) | |
4884 | { | |
4885 | int i; | |
4886 | ||
4887 | for (i = 0; i < np->num_ldg; i++) | |
4888 | napi_enable(&np->ldg[i].napi); | |
4889 | } | |
4890 | ||
4891 | static void niu_disable_napi(struct niu *np) | |
4892 | { | |
4893 | int i; | |
4894 | ||
4895 | for (i = 0; i < np->num_ldg; i++) | |
4896 | napi_disable(&np->ldg[i].napi); | |
4897 | } | |
4898 | ||
4899 | static int niu_open(struct net_device *dev) | |
4900 | { | |
4901 | struct niu *np = netdev_priv(dev); | |
4902 | int err; | |
4903 | ||
4904 | netif_carrier_off(dev); | |
4905 | ||
4906 | err = niu_alloc_channels(np); | |
4907 | if (err) | |
4908 | goto out_err; | |
4909 | ||
4910 | err = niu_enable_interrupts(np, 0); | |
4911 | if (err) | |
4912 | goto out_free_channels; | |
4913 | ||
4914 | err = niu_request_irq(np); | |
4915 | if (err) | |
4916 | goto out_free_channels; | |
4917 | ||
4918 | niu_enable_napi(np); | |
4919 | ||
4920 | spin_lock_irq(&np->lock); | |
4921 | ||
4922 | err = niu_init_hw(np); | |
4923 | if (!err) { | |
4924 | init_timer(&np->timer); | |
4925 | np->timer.expires = jiffies + HZ; | |
4926 | np->timer.data = (unsigned long) np; | |
4927 | np->timer.function = niu_timer; | |
4928 | ||
4929 | err = niu_enable_interrupts(np, 1); | |
4930 | if (err) | |
4931 | niu_stop_hw(np); | |
4932 | } | |
4933 | ||
4934 | spin_unlock_irq(&np->lock); | |
4935 | ||
4936 | if (err) { | |
4937 | niu_disable_napi(np); | |
4938 | goto out_free_irq; | |
4939 | } | |
4940 | ||
4941 | netif_start_queue(dev); | |
4942 | ||
4943 | if (np->link_config.loopback_mode != LOOPBACK_DISABLED) | |
4944 | netif_carrier_on(dev); | |
4945 | ||
4946 | add_timer(&np->timer); | |
4947 | ||
4948 | return 0; | |
4949 | ||
4950 | out_free_irq: | |
4951 | niu_free_irq(np); | |
4952 | ||
4953 | out_free_channels: | |
4954 | niu_free_channels(np); | |
4955 | ||
4956 | out_err: | |
4957 | return err; | |
4958 | } | |
4959 | ||
4960 | static void niu_full_shutdown(struct niu *np, struct net_device *dev) | |
4961 | { | |
4962 | cancel_work_sync(&np->reset_task); | |
4963 | ||
4964 | niu_disable_napi(np); | |
4965 | netif_stop_queue(dev); | |
4966 | ||
4967 | del_timer_sync(&np->timer); | |
4968 | ||
4969 | spin_lock_irq(&np->lock); | |
4970 | ||
4971 | niu_stop_hw(np); | |
4972 | ||
4973 | spin_unlock_irq(&np->lock); | |
4974 | } | |
4975 | ||
4976 | static int niu_close(struct net_device *dev) | |
4977 | { | |
4978 | struct niu *np = netdev_priv(dev); | |
4979 | ||
4980 | niu_full_shutdown(np, dev); | |
4981 | ||
4982 | niu_free_irq(np); | |
4983 | ||
4984 | niu_free_channels(np); | |
4985 | ||
0c3b091b ML |
4986 | niu_handle_led(np, 0); |
4987 | ||
a3138df9 DM |
4988 | return 0; |
4989 | } | |
4990 | ||
4991 | static void niu_sync_xmac_stats(struct niu *np) | |
4992 | { | |
4993 | struct niu_xmac_stats *mp = &np->mac_stats.xmac; | |
4994 | ||
4995 | mp->tx_frames += nr64_mac(TXMAC_FRM_CNT); | |
4996 | mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT); | |
4997 | ||
4998 | mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT); | |
4999 | mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT); | |
5000 | mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT); | |
5001 | mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT); | |
5002 | mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT); | |
5003 | mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1); | |
5004 | mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2); | |
5005 | mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3); | |
5006 | mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4); | |
5007 | mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5); | |
5008 | mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6); | |
5009 | mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7); | |
5010 | mp->rx_octets += nr64_mac(RXMAC_BT_CNT); | |
5011 | mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT); | |
5012 | mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT); | |
5013 | mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT); | |
5014 | } | |
5015 | ||
5016 | static void niu_sync_bmac_stats(struct niu *np) | |
5017 | { | |
5018 | struct niu_bmac_stats *mp = &np->mac_stats.bmac; | |
5019 | ||
5020 | mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT); | |
5021 | mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT); | |
5022 | ||
5023 | mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT); | |
5024 | mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT); | |
5025 | mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT); | |
5026 | mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT); | |
5027 | } | |
5028 | ||
5029 | static void niu_sync_mac_stats(struct niu *np) | |
5030 | { | |
5031 | if (np->flags & NIU_FLAGS_XMAC) | |
5032 | niu_sync_xmac_stats(np); | |
5033 | else | |
5034 | niu_sync_bmac_stats(np); | |
5035 | } | |
5036 | ||
5037 | static void niu_get_rx_stats(struct niu *np) | |
5038 | { | |
5039 | unsigned long pkts, dropped, errors, bytes; | |
5040 | int i; | |
5041 | ||
5042 | pkts = dropped = errors = bytes = 0; | |
5043 | for (i = 0; i < np->num_rx_rings; i++) { | |
5044 | struct rx_ring_info *rp = &np->rx_rings[i]; | |
5045 | ||
5046 | pkts += rp->rx_packets; | |
5047 | bytes += rp->rx_bytes; | |
5048 | dropped += rp->rx_dropped; | |
5049 | errors += rp->rx_errors; | |
5050 | } | |
5051 | np->net_stats.rx_packets = pkts; | |
5052 | np->net_stats.rx_bytes = bytes; | |
5053 | np->net_stats.rx_dropped = dropped; | |
5054 | np->net_stats.rx_errors = errors; | |
5055 | } | |
5056 | ||
5057 | static void niu_get_tx_stats(struct niu *np) | |
5058 | { | |
5059 | unsigned long pkts, errors, bytes; | |
5060 | int i; | |
5061 | ||
5062 | pkts = errors = bytes = 0; | |
5063 | for (i = 0; i < np->num_tx_rings; i++) { | |
5064 | struct tx_ring_info *rp = &np->tx_rings[i]; | |
5065 | ||
5066 | pkts += rp->tx_packets; | |
5067 | bytes += rp->tx_bytes; | |
5068 | errors += rp->tx_errors; | |
5069 | } | |
5070 | np->net_stats.tx_packets = pkts; | |
5071 | np->net_stats.tx_bytes = bytes; | |
5072 | np->net_stats.tx_errors = errors; | |
5073 | } | |
5074 | ||
5075 | static struct net_device_stats *niu_get_stats(struct net_device *dev) | |
5076 | { | |
5077 | struct niu *np = netdev_priv(dev); | |
5078 | ||
5079 | niu_get_rx_stats(np); | |
5080 | niu_get_tx_stats(np); | |
5081 | ||
5082 | return &np->net_stats; | |
5083 | } | |
5084 | ||
5085 | static void niu_load_hash_xmac(struct niu *np, u16 *hash) | |
5086 | { | |
5087 | int i; | |
5088 | ||
5089 | for (i = 0; i < 16; i++) | |
5090 | nw64_mac(XMAC_HASH_TBL(i), hash[i]); | |
5091 | } | |
5092 | ||
5093 | static void niu_load_hash_bmac(struct niu *np, u16 *hash) | |
5094 | { | |
5095 | int i; | |
5096 | ||
5097 | for (i = 0; i < 16; i++) | |
5098 | nw64_mac(BMAC_HASH_TBL(i), hash[i]); | |
5099 | } | |
5100 | ||
5101 | static void niu_load_hash(struct niu *np, u16 *hash) | |
5102 | { | |
5103 | if (np->flags & NIU_FLAGS_XMAC) | |
5104 | niu_load_hash_xmac(np, hash); | |
5105 | else | |
5106 | niu_load_hash_bmac(np, hash); | |
5107 | } | |
5108 | ||
5109 | static void niu_set_rx_mode(struct net_device *dev) | |
5110 | { | |
5111 | struct niu *np = netdev_priv(dev); | |
5112 | int i, alt_cnt, err; | |
5113 | struct dev_addr_list *addr; | |
5114 | unsigned long flags; | |
5115 | u16 hash[16] = { 0, }; | |
5116 | ||
5117 | spin_lock_irqsave(&np->lock, flags); | |
5118 | niu_enable_rx_mac(np, 0); | |
5119 | ||
5120 | np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC); | |
5121 | if (dev->flags & IFF_PROMISC) | |
5122 | np->flags |= NIU_FLAGS_PROMISC; | |
5123 | if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0)) | |
5124 | np->flags |= NIU_FLAGS_MCAST; | |
5125 | ||
5126 | alt_cnt = dev->uc_count; | |
5127 | if (alt_cnt > niu_num_alt_addr(np)) { | |
5128 | alt_cnt = 0; | |
5129 | np->flags |= NIU_FLAGS_PROMISC; | |
5130 | } | |
5131 | ||
5132 | if (alt_cnt) { | |
5133 | int index = 0; | |
5134 | ||
5135 | for (addr = dev->uc_list; addr; addr = addr->next) { | |
5136 | err = niu_set_alt_mac(np, index, | |
5137 | addr->da_addr); | |
5138 | if (err) | |
5139 | printk(KERN_WARNING PFX "%s: Error %d " | |
5140 | "adding alt mac %d\n", | |
5141 | dev->name, err, index); | |
5142 | err = niu_enable_alt_mac(np, index, 1); | |
5143 | if (err) | |
5144 | printk(KERN_WARNING PFX "%s: Error %d " | |
5145 | "enabling alt mac %d\n", | |
5146 | dev->name, err, index); | |
5147 | ||
5148 | index++; | |
5149 | } | |
5150 | } else { | |
3b5bcede MW |
5151 | int alt_start; |
5152 | if (np->flags & NIU_FLAGS_XMAC) | |
5153 | alt_start = 0; | |
5154 | else | |
5155 | alt_start = 1; | |
5156 | for (i = alt_start; i < niu_num_alt_addr(np); i++) { | |
a3138df9 DM |
5157 | err = niu_enable_alt_mac(np, i, 0); |
5158 | if (err) | |
5159 | printk(KERN_WARNING PFX "%s: Error %d " | |
5160 | "disabling alt mac %d\n", | |
5161 | dev->name, err, i); | |
5162 | } | |
5163 | } | |
5164 | if (dev->flags & IFF_ALLMULTI) { | |
5165 | for (i = 0; i < 16; i++) | |
5166 | hash[i] = 0xffff; | |
5167 | } else if (dev->mc_count > 0) { | |
5168 | for (addr = dev->mc_list; addr; addr = addr->next) { | |
5169 | u32 crc = ether_crc_le(ETH_ALEN, addr->da_addr); | |
5170 | ||
5171 | crc >>= 24; | |
5172 | hash[crc >> 4] |= (1 << (15 - (crc & 0xf))); | |
5173 | } | |
5174 | } | |
5175 | ||
5176 | if (np->flags & NIU_FLAGS_MCAST) | |
5177 | niu_load_hash(np, hash); | |
5178 | ||
5179 | niu_enable_rx_mac(np, 1); | |
5180 | spin_unlock_irqrestore(&np->lock, flags); | |
5181 | } | |
5182 | ||
5183 | static int niu_set_mac_addr(struct net_device *dev, void *p) | |
5184 | { | |
5185 | struct niu *np = netdev_priv(dev); | |
5186 | struct sockaddr *addr = p; | |
5187 | unsigned long flags; | |
5188 | ||
5189 | if (!is_valid_ether_addr(addr->sa_data)) | |
5190 | return -EINVAL; | |
5191 | ||
5192 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); | |
5193 | ||
5194 | if (!netif_running(dev)) | |
5195 | return 0; | |
5196 | ||
5197 | spin_lock_irqsave(&np->lock, flags); | |
5198 | niu_enable_rx_mac(np, 0); | |
5199 | niu_set_primary_mac(np, dev->dev_addr); | |
5200 | niu_enable_rx_mac(np, 1); | |
5201 | spin_unlock_irqrestore(&np->lock, flags); | |
5202 | ||
5203 | return 0; | |
5204 | } | |
5205 | ||
5206 | static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
5207 | { | |
5208 | return -EOPNOTSUPP; | |
5209 | } | |
5210 | ||
5211 | static void niu_netif_stop(struct niu *np) | |
5212 | { | |
5213 | np->dev->trans_start = jiffies; /* prevent tx timeout */ | |
5214 | ||
5215 | niu_disable_napi(np); | |
5216 | ||
5217 | netif_tx_disable(np->dev); | |
5218 | } | |
5219 | ||
5220 | static void niu_netif_start(struct niu *np) | |
5221 | { | |
5222 | /* NOTE: unconditional netif_wake_queue is only appropriate | |
5223 | * so long as all callers are assured to have free tx slots | |
5224 | * (such as after niu_init_hw). | |
5225 | */ | |
5226 | netif_wake_queue(np->dev); | |
5227 | ||
5228 | niu_enable_napi(np); | |
5229 | ||
5230 | niu_enable_interrupts(np, 1); | |
5231 | } | |
5232 | ||
5233 | static void niu_reset_task(struct work_struct *work) | |
5234 | { | |
5235 | struct niu *np = container_of(work, struct niu, reset_task); | |
5236 | unsigned long flags; | |
5237 | int err; | |
5238 | ||
5239 | spin_lock_irqsave(&np->lock, flags); | |
5240 | if (!netif_running(np->dev)) { | |
5241 | spin_unlock_irqrestore(&np->lock, flags); | |
5242 | return; | |
5243 | } | |
5244 | ||
5245 | spin_unlock_irqrestore(&np->lock, flags); | |
5246 | ||
5247 | del_timer_sync(&np->timer); | |
5248 | ||
5249 | niu_netif_stop(np); | |
5250 | ||
5251 | spin_lock_irqsave(&np->lock, flags); | |
5252 | ||
5253 | niu_stop_hw(np); | |
5254 | ||
5255 | err = niu_init_hw(np); | |
5256 | if (!err) { | |
5257 | np->timer.expires = jiffies + HZ; | |
5258 | add_timer(&np->timer); | |
5259 | niu_netif_start(np); | |
5260 | } | |
5261 | ||
5262 | spin_unlock_irqrestore(&np->lock, flags); | |
5263 | } | |
5264 | ||
5265 | static void niu_tx_timeout(struct net_device *dev) | |
5266 | { | |
5267 | struct niu *np = netdev_priv(dev); | |
5268 | ||
5269 | dev_err(np->device, PFX "%s: Transmit timed out, resetting\n", | |
5270 | dev->name); | |
5271 | ||
5272 | schedule_work(&np->reset_task); | |
5273 | } | |
5274 | ||
5275 | static void niu_set_txd(struct tx_ring_info *rp, int index, | |
5276 | u64 mapping, u64 len, u64 mark, | |
5277 | u64 n_frags) | |
5278 | { | |
5279 | __le64 *desc = &rp->descr[index]; | |
5280 | ||
5281 | *desc = cpu_to_le64(mark | | |
5282 | (n_frags << TX_DESC_NUM_PTR_SHIFT) | | |
5283 | (len << TX_DESC_TR_LEN_SHIFT) | | |
5284 | (mapping & TX_DESC_SAD)); | |
5285 | } | |
5286 | ||
5287 | static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr, | |
5288 | u64 pad_bytes, u64 len) | |
5289 | { | |
5290 | u16 eth_proto, eth_proto_inner; | |
5291 | u64 csum_bits, l3off, ihl, ret; | |
5292 | u8 ip_proto; | |
5293 | int ipv6; | |
5294 | ||
5295 | eth_proto = be16_to_cpu(ehdr->h_proto); | |
5296 | eth_proto_inner = eth_proto; | |
5297 | if (eth_proto == ETH_P_8021Q) { | |
5298 | struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr; | |
5299 | __be16 val = vp->h_vlan_encapsulated_proto; | |
5300 | ||
5301 | eth_proto_inner = be16_to_cpu(val); | |
5302 | } | |
5303 | ||
5304 | ipv6 = ihl = 0; | |
5305 | switch (skb->protocol) { | |
5306 | case __constant_htons(ETH_P_IP): | |
5307 | ip_proto = ip_hdr(skb)->protocol; | |
5308 | ihl = ip_hdr(skb)->ihl; | |
5309 | break; | |
5310 | case __constant_htons(ETH_P_IPV6): | |
5311 | ip_proto = ipv6_hdr(skb)->nexthdr; | |
5312 | ihl = (40 >> 2); | |
5313 | ipv6 = 1; | |
5314 | break; | |
5315 | default: | |
5316 | ip_proto = ihl = 0; | |
5317 | break; | |
5318 | } | |
5319 | ||
5320 | csum_bits = TXHDR_CSUM_NONE; | |
5321 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
5322 | u64 start, stuff; | |
5323 | ||
5324 | csum_bits = (ip_proto == IPPROTO_TCP ? | |
5325 | TXHDR_CSUM_TCP : | |
5326 | (ip_proto == IPPROTO_UDP ? | |
5327 | TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP)); | |
5328 | ||
5329 | start = skb_transport_offset(skb) - | |
5330 | (pad_bytes + sizeof(struct tx_pkt_hdr)); | |
5331 | stuff = start + skb->csum_offset; | |
5332 | ||
5333 | csum_bits |= (start / 2) << TXHDR_L4START_SHIFT; | |
5334 | csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT; | |
5335 | } | |
5336 | ||
5337 | l3off = skb_network_offset(skb) - | |
5338 | (pad_bytes + sizeof(struct tx_pkt_hdr)); | |
5339 | ||
5340 | ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) | | |
5341 | (len << TXHDR_LEN_SHIFT) | | |
5342 | ((l3off / 2) << TXHDR_L3START_SHIFT) | | |
5343 | (ihl << TXHDR_IHL_SHIFT) | | |
5344 | ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) | | |
5345 | ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) | | |
5346 | (ipv6 ? TXHDR_IP_VER : 0) | | |
5347 | csum_bits); | |
5348 | ||
5349 | return ret; | |
5350 | } | |
5351 | ||
5352 | static struct tx_ring_info *tx_ring_select(struct niu *np, struct sk_buff *skb) | |
5353 | { | |
5354 | return &np->tx_rings[0]; | |
5355 | } | |
5356 | ||
5357 | static int niu_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
5358 | { | |
5359 | struct niu *np = netdev_priv(dev); | |
5360 | unsigned long align, headroom; | |
5361 | struct tx_ring_info *rp; | |
5362 | struct tx_pkt_hdr *tp; | |
5363 | unsigned int len, nfg; | |
5364 | struct ethhdr *ehdr; | |
5365 | int prod, i, tlen; | |
5366 | u64 mapping, mrk; | |
5367 | ||
5368 | rp = tx_ring_select(np, skb); | |
5369 | ||
5370 | if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) { | |
5371 | netif_stop_queue(dev); | |
5372 | dev_err(np->device, PFX "%s: BUG! Tx ring full when " | |
5373 | "queue awake!\n", dev->name); | |
5374 | rp->tx_errors++; | |
5375 | return NETDEV_TX_BUSY; | |
5376 | } | |
5377 | ||
5378 | if (skb->len < ETH_ZLEN) { | |
5379 | unsigned int pad_bytes = ETH_ZLEN - skb->len; | |
5380 | ||
5381 | if (skb_pad(skb, pad_bytes)) | |
5382 | goto out; | |
5383 | skb_put(skb, pad_bytes); | |
5384 | } | |
5385 | ||
5386 | len = sizeof(struct tx_pkt_hdr) + 15; | |
5387 | if (skb_headroom(skb) < len) { | |
5388 | struct sk_buff *skb_new; | |
5389 | ||
5390 | skb_new = skb_realloc_headroom(skb, len); | |
5391 | if (!skb_new) { | |
5392 | rp->tx_errors++; | |
5393 | goto out_drop; | |
5394 | } | |
5395 | kfree_skb(skb); | |
5396 | skb = skb_new; | |
3ebebccf DM |
5397 | } else |
5398 | skb_orphan(skb); | |
a3138df9 DM |
5399 | |
5400 | align = ((unsigned long) skb->data & (16 - 1)); | |
5401 | headroom = align + sizeof(struct tx_pkt_hdr); | |
5402 | ||
5403 | ehdr = (struct ethhdr *) skb->data; | |
5404 | tp = (struct tx_pkt_hdr *) skb_push(skb, headroom); | |
5405 | ||
5406 | len = skb->len - sizeof(struct tx_pkt_hdr); | |
5407 | tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len)); | |
5408 | tp->resv = 0; | |
5409 | ||
5410 | len = skb_headlen(skb); | |
5411 | mapping = np->ops->map_single(np->device, skb->data, | |
5412 | len, DMA_TO_DEVICE); | |
5413 | ||
5414 | prod = rp->prod; | |
5415 | ||
5416 | rp->tx_buffs[prod].skb = skb; | |
5417 | rp->tx_buffs[prod].mapping = mapping; | |
5418 | ||
5419 | mrk = TX_DESC_SOP; | |
5420 | if (++rp->mark_counter == rp->mark_freq) { | |
5421 | rp->mark_counter = 0; | |
5422 | mrk |= TX_DESC_MARK; | |
5423 | rp->mark_pending++; | |
5424 | } | |
5425 | ||
5426 | tlen = len; | |
5427 | nfg = skb_shinfo(skb)->nr_frags; | |
5428 | while (tlen > 0) { | |
5429 | tlen -= MAX_TX_DESC_LEN; | |
5430 | nfg++; | |
5431 | } | |
5432 | ||
5433 | while (len > 0) { | |
5434 | unsigned int this_len = len; | |
5435 | ||
5436 | if (this_len > MAX_TX_DESC_LEN) | |
5437 | this_len = MAX_TX_DESC_LEN; | |
5438 | ||
5439 | niu_set_txd(rp, prod, mapping, this_len, mrk, nfg); | |
5440 | mrk = nfg = 0; | |
5441 | ||
5442 | prod = NEXT_TX(rp, prod); | |
5443 | mapping += this_len; | |
5444 | len -= this_len; | |
5445 | } | |
5446 | ||
5447 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
5448 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
5449 | ||
5450 | len = frag->size; | |
5451 | mapping = np->ops->map_page(np->device, frag->page, | |
5452 | frag->page_offset, len, | |
5453 | DMA_TO_DEVICE); | |
5454 | ||
5455 | rp->tx_buffs[prod].skb = NULL; | |
5456 | rp->tx_buffs[prod].mapping = mapping; | |
5457 | ||
5458 | niu_set_txd(rp, prod, mapping, len, 0, 0); | |
5459 | ||
5460 | prod = NEXT_TX(rp, prod); | |
5461 | } | |
5462 | ||
5463 | if (prod < rp->prod) | |
5464 | rp->wrap_bit ^= TX_RING_KICK_WRAP; | |
5465 | rp->prod = prod; | |
5466 | ||
5467 | nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3)); | |
5468 | ||
5469 | if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) { | |
5470 | netif_stop_queue(dev); | |
5471 | if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)) | |
5472 | netif_wake_queue(dev); | |
5473 | } | |
5474 | ||
5475 | dev->trans_start = jiffies; | |
5476 | ||
5477 | out: | |
5478 | return NETDEV_TX_OK; | |
5479 | ||
5480 | out_drop: | |
5481 | rp->tx_errors++; | |
5482 | kfree_skb(skb); | |
5483 | goto out; | |
5484 | } | |
5485 | ||
5486 | static int niu_change_mtu(struct net_device *dev, int new_mtu) | |
5487 | { | |
5488 | struct niu *np = netdev_priv(dev); | |
5489 | int err, orig_jumbo, new_jumbo; | |
5490 | ||
5491 | if (new_mtu < 68 || new_mtu > NIU_MAX_MTU) | |
5492 | return -EINVAL; | |
5493 | ||
5494 | orig_jumbo = (dev->mtu > ETH_DATA_LEN); | |
5495 | new_jumbo = (new_mtu > ETH_DATA_LEN); | |
5496 | ||
5497 | dev->mtu = new_mtu; | |
5498 | ||
5499 | if (!netif_running(dev) || | |
5500 | (orig_jumbo == new_jumbo)) | |
5501 | return 0; | |
5502 | ||
5503 | niu_full_shutdown(np, dev); | |
5504 | ||
5505 | niu_free_channels(np); | |
5506 | ||
5507 | niu_enable_napi(np); | |
5508 | ||
5509 | err = niu_alloc_channels(np); | |
5510 | if (err) | |
5511 | return err; | |
5512 | ||
5513 | spin_lock_irq(&np->lock); | |
5514 | ||
5515 | err = niu_init_hw(np); | |
5516 | if (!err) { | |
5517 | init_timer(&np->timer); | |
5518 | np->timer.expires = jiffies + HZ; | |
5519 | np->timer.data = (unsigned long) np; | |
5520 | np->timer.function = niu_timer; | |
5521 | ||
5522 | err = niu_enable_interrupts(np, 1); | |
5523 | if (err) | |
5524 | niu_stop_hw(np); | |
5525 | } | |
5526 | ||
5527 | spin_unlock_irq(&np->lock); | |
5528 | ||
5529 | if (!err) { | |
5530 | netif_start_queue(dev); | |
5531 | if (np->link_config.loopback_mode != LOOPBACK_DISABLED) | |
5532 | netif_carrier_on(dev); | |
5533 | ||
5534 | add_timer(&np->timer); | |
5535 | } | |
5536 | ||
5537 | return err; | |
5538 | } | |
5539 | ||
5540 | static void niu_get_drvinfo(struct net_device *dev, | |
5541 | struct ethtool_drvinfo *info) | |
5542 | { | |
5543 | struct niu *np = netdev_priv(dev); | |
5544 | struct niu_vpd *vpd = &np->vpd; | |
5545 | ||
5546 | strcpy(info->driver, DRV_MODULE_NAME); | |
5547 | strcpy(info->version, DRV_MODULE_VERSION); | |
5548 | sprintf(info->fw_version, "%d.%d", | |
5549 | vpd->fcode_major, vpd->fcode_minor); | |
5550 | if (np->parent->plat_type != PLAT_TYPE_NIU) | |
5551 | strcpy(info->bus_info, pci_name(np->pdev)); | |
5552 | } | |
5553 | ||
5554 | static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
5555 | { | |
5556 | struct niu *np = netdev_priv(dev); | |
5557 | struct niu_link_config *lp; | |
5558 | ||
5559 | lp = &np->link_config; | |
5560 | ||
5561 | memset(cmd, 0, sizeof(*cmd)); | |
5562 | cmd->phy_address = np->phy_addr; | |
5563 | cmd->supported = lp->supported; | |
5564 | cmd->advertising = lp->advertising; | |
5565 | cmd->autoneg = lp->autoneg; | |
5566 | cmd->speed = lp->active_speed; | |
5567 | cmd->duplex = lp->active_duplex; | |
5568 | ||
5569 | return 0; | |
5570 | } | |
5571 | ||
5572 | static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
5573 | { | |
5574 | return -EINVAL; | |
5575 | } | |
5576 | ||
5577 | static u32 niu_get_msglevel(struct net_device *dev) | |
5578 | { | |
5579 | struct niu *np = netdev_priv(dev); | |
5580 | return np->msg_enable; | |
5581 | } | |
5582 | ||
5583 | static void niu_set_msglevel(struct net_device *dev, u32 value) | |
5584 | { | |
5585 | struct niu *np = netdev_priv(dev); | |
5586 | np->msg_enable = value; | |
5587 | } | |
5588 | ||
5589 | static int niu_get_eeprom_len(struct net_device *dev) | |
5590 | { | |
5591 | struct niu *np = netdev_priv(dev); | |
5592 | ||
5593 | return np->eeprom_len; | |
5594 | } | |
5595 | ||
5596 | static int niu_get_eeprom(struct net_device *dev, | |
5597 | struct ethtool_eeprom *eeprom, u8 *data) | |
5598 | { | |
5599 | struct niu *np = netdev_priv(dev); | |
5600 | u32 offset, len, val; | |
5601 | ||
5602 | offset = eeprom->offset; | |
5603 | len = eeprom->len; | |
5604 | ||
5605 | if (offset + len < offset) | |
5606 | return -EINVAL; | |
5607 | if (offset >= np->eeprom_len) | |
5608 | return -EINVAL; | |
5609 | if (offset + len > np->eeprom_len) | |
5610 | len = eeprom->len = np->eeprom_len - offset; | |
5611 | ||
5612 | if (offset & 3) { | |
5613 | u32 b_offset, b_count; | |
5614 | ||
5615 | b_offset = offset & 3; | |
5616 | b_count = 4 - b_offset; | |
5617 | if (b_count > len) | |
5618 | b_count = len; | |
5619 | ||
5620 | val = nr64(ESPC_NCR((offset - b_offset) / 4)); | |
5621 | memcpy(data, ((char *)&val) + b_offset, b_count); | |
5622 | data += b_count; | |
5623 | len -= b_count; | |
5624 | offset += b_count; | |
5625 | } | |
5626 | while (len >= 4) { | |
5627 | val = nr64(ESPC_NCR(offset / 4)); | |
5628 | memcpy(data, &val, 4); | |
5629 | data += 4; | |
5630 | len -= 4; | |
5631 | offset += 4; | |
5632 | } | |
5633 | if (len) { | |
5634 | val = nr64(ESPC_NCR(offset / 4)); | |
5635 | memcpy(data, &val, len); | |
5636 | } | |
5637 | return 0; | |
5638 | } | |
5639 | ||
5640 | static const struct { | |
5641 | const char string[ETH_GSTRING_LEN]; | |
5642 | } niu_xmac_stat_keys[] = { | |
5643 | { "tx_frames" }, | |
5644 | { "tx_bytes" }, | |
5645 | { "tx_fifo_errors" }, | |
5646 | { "tx_overflow_errors" }, | |
5647 | { "tx_max_pkt_size_errors" }, | |
5648 | { "tx_underflow_errors" }, | |
5649 | { "rx_local_faults" }, | |
5650 | { "rx_remote_faults" }, | |
5651 | { "rx_link_faults" }, | |
5652 | { "rx_align_errors" }, | |
5653 | { "rx_frags" }, | |
5654 | { "rx_mcasts" }, | |
5655 | { "rx_bcasts" }, | |
5656 | { "rx_hist_cnt1" }, | |
5657 | { "rx_hist_cnt2" }, | |
5658 | { "rx_hist_cnt3" }, | |
5659 | { "rx_hist_cnt4" }, | |
5660 | { "rx_hist_cnt5" }, | |
5661 | { "rx_hist_cnt6" }, | |
5662 | { "rx_hist_cnt7" }, | |
5663 | { "rx_octets" }, | |
5664 | { "rx_code_violations" }, | |
5665 | { "rx_len_errors" }, | |
5666 | { "rx_crc_errors" }, | |
5667 | { "rx_underflows" }, | |
5668 | { "rx_overflows" }, | |
5669 | { "pause_off_state" }, | |
5670 | { "pause_on_state" }, | |
5671 | { "pause_received" }, | |
5672 | }; | |
5673 | ||
5674 | #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys) | |
5675 | ||
5676 | static const struct { | |
5677 | const char string[ETH_GSTRING_LEN]; | |
5678 | } niu_bmac_stat_keys[] = { | |
5679 | { "tx_underflow_errors" }, | |
5680 | { "tx_max_pkt_size_errors" }, | |
5681 | { "tx_bytes" }, | |
5682 | { "tx_frames" }, | |
5683 | { "rx_overflows" }, | |
5684 | { "rx_frames" }, | |
5685 | { "rx_align_errors" }, | |
5686 | { "rx_crc_errors" }, | |
5687 | { "rx_len_errors" }, | |
5688 | { "pause_off_state" }, | |
5689 | { "pause_on_state" }, | |
5690 | { "pause_received" }, | |
5691 | }; | |
5692 | ||
5693 | #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys) | |
5694 | ||
5695 | static const struct { | |
5696 | const char string[ETH_GSTRING_LEN]; | |
5697 | } niu_rxchan_stat_keys[] = { | |
5698 | { "rx_channel" }, | |
5699 | { "rx_packets" }, | |
5700 | { "rx_bytes" }, | |
5701 | { "rx_dropped" }, | |
5702 | { "rx_errors" }, | |
5703 | }; | |
5704 | ||
5705 | #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys) | |
5706 | ||
5707 | static const struct { | |
5708 | const char string[ETH_GSTRING_LEN]; | |
5709 | } niu_txchan_stat_keys[] = { | |
5710 | { "tx_channel" }, | |
5711 | { "tx_packets" }, | |
5712 | { "tx_bytes" }, | |
5713 | { "tx_errors" }, | |
5714 | }; | |
5715 | ||
5716 | #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys) | |
5717 | ||
5718 | static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
5719 | { | |
5720 | struct niu *np = netdev_priv(dev); | |
5721 | int i; | |
5722 | ||
5723 | if (stringset != ETH_SS_STATS) | |
5724 | return; | |
5725 | ||
5726 | if (np->flags & NIU_FLAGS_XMAC) { | |
5727 | memcpy(data, niu_xmac_stat_keys, | |
5728 | sizeof(niu_xmac_stat_keys)); | |
5729 | data += sizeof(niu_xmac_stat_keys); | |
5730 | } else { | |
5731 | memcpy(data, niu_bmac_stat_keys, | |
5732 | sizeof(niu_bmac_stat_keys)); | |
5733 | data += sizeof(niu_bmac_stat_keys); | |
5734 | } | |
5735 | for (i = 0; i < np->num_rx_rings; i++) { | |
5736 | memcpy(data, niu_rxchan_stat_keys, | |
5737 | sizeof(niu_rxchan_stat_keys)); | |
5738 | data += sizeof(niu_rxchan_stat_keys); | |
5739 | } | |
5740 | for (i = 0; i < np->num_tx_rings; i++) { | |
5741 | memcpy(data, niu_txchan_stat_keys, | |
5742 | sizeof(niu_txchan_stat_keys)); | |
5743 | data += sizeof(niu_txchan_stat_keys); | |
5744 | } | |
5745 | } | |
5746 | ||
5747 | static int niu_get_stats_count(struct net_device *dev) | |
5748 | { | |
5749 | struct niu *np = netdev_priv(dev); | |
5750 | ||
5751 | return ((np->flags & NIU_FLAGS_XMAC ? | |
5752 | NUM_XMAC_STAT_KEYS : | |
5753 | NUM_BMAC_STAT_KEYS) + | |
5754 | (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) + | |
5755 | (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS)); | |
5756 | } | |
5757 | ||
5758 | static void niu_get_ethtool_stats(struct net_device *dev, | |
5759 | struct ethtool_stats *stats, u64 *data) | |
5760 | { | |
5761 | struct niu *np = netdev_priv(dev); | |
5762 | int i; | |
5763 | ||
5764 | niu_sync_mac_stats(np); | |
5765 | if (np->flags & NIU_FLAGS_XMAC) { | |
5766 | memcpy(data, &np->mac_stats.xmac, | |
5767 | sizeof(struct niu_xmac_stats)); | |
5768 | data += (sizeof(struct niu_xmac_stats) / sizeof(u64)); | |
5769 | } else { | |
5770 | memcpy(data, &np->mac_stats.bmac, | |
5771 | sizeof(struct niu_bmac_stats)); | |
5772 | data += (sizeof(struct niu_bmac_stats) / sizeof(u64)); | |
5773 | } | |
5774 | for (i = 0; i < np->num_rx_rings; i++) { | |
5775 | struct rx_ring_info *rp = &np->rx_rings[i]; | |
5776 | ||
5777 | data[0] = rp->rx_channel; | |
5778 | data[1] = rp->rx_packets; | |
5779 | data[2] = rp->rx_bytes; | |
5780 | data[3] = rp->rx_dropped; | |
5781 | data[4] = rp->rx_errors; | |
5782 | data += 5; | |
5783 | } | |
5784 | for (i = 0; i < np->num_tx_rings; i++) { | |
5785 | struct tx_ring_info *rp = &np->tx_rings[i]; | |
5786 | ||
5787 | data[0] = rp->tx_channel; | |
5788 | data[1] = rp->tx_packets; | |
5789 | data[2] = rp->tx_bytes; | |
5790 | data[3] = rp->tx_errors; | |
5791 | data += 4; | |
5792 | } | |
5793 | } | |
5794 | ||
5795 | static u64 niu_led_state_save(struct niu *np) | |
5796 | { | |
5797 | if (np->flags & NIU_FLAGS_XMAC) | |
5798 | return nr64_mac(XMAC_CONFIG); | |
5799 | else | |
5800 | return nr64_mac(BMAC_XIF_CONFIG); | |
5801 | } | |
5802 | ||
5803 | static void niu_led_state_restore(struct niu *np, u64 val) | |
5804 | { | |
5805 | if (np->flags & NIU_FLAGS_XMAC) | |
5806 | nw64_mac(XMAC_CONFIG, val); | |
5807 | else | |
5808 | nw64_mac(BMAC_XIF_CONFIG, val); | |
5809 | } | |
5810 | ||
5811 | static void niu_force_led(struct niu *np, int on) | |
5812 | { | |
5813 | u64 val, reg, bit; | |
5814 | ||
5815 | if (np->flags & NIU_FLAGS_XMAC) { | |
5816 | reg = XMAC_CONFIG; | |
5817 | bit = XMAC_CONFIG_FORCE_LED_ON; | |
5818 | } else { | |
5819 | reg = BMAC_XIF_CONFIG; | |
5820 | bit = BMAC_XIF_CONFIG_LINK_LED; | |
5821 | } | |
5822 | ||
5823 | val = nr64_mac(reg); | |
5824 | if (on) | |
5825 | val |= bit; | |
5826 | else | |
5827 | val &= ~bit; | |
5828 | nw64_mac(reg, val); | |
5829 | } | |
5830 | ||
5831 | static int niu_phys_id(struct net_device *dev, u32 data) | |
5832 | { | |
5833 | struct niu *np = netdev_priv(dev); | |
5834 | u64 orig_led_state; | |
5835 | int i; | |
5836 | ||
5837 | if (!netif_running(dev)) | |
5838 | return -EAGAIN; | |
5839 | ||
5840 | if (data == 0) | |
5841 | data = 2; | |
5842 | ||
5843 | orig_led_state = niu_led_state_save(np); | |
5844 | for (i = 0; i < (data * 2); i++) { | |
5845 | int on = ((i % 2) == 0); | |
5846 | ||
5847 | niu_force_led(np, on); | |
5848 | ||
5849 | if (msleep_interruptible(500)) | |
5850 | break; | |
5851 | } | |
5852 | niu_led_state_restore(np, orig_led_state); | |
5853 | ||
5854 | return 0; | |
5855 | } | |
5856 | ||
5857 | static const struct ethtool_ops niu_ethtool_ops = { | |
5858 | .get_drvinfo = niu_get_drvinfo, | |
5859 | .get_link = ethtool_op_get_link, | |
5860 | .get_msglevel = niu_get_msglevel, | |
5861 | .set_msglevel = niu_set_msglevel, | |
5862 | .get_eeprom_len = niu_get_eeprom_len, | |
5863 | .get_eeprom = niu_get_eeprom, | |
5864 | .get_settings = niu_get_settings, | |
5865 | .set_settings = niu_set_settings, | |
5866 | .get_strings = niu_get_strings, | |
5867 | .get_stats_count = niu_get_stats_count, | |
5868 | .get_ethtool_stats = niu_get_ethtool_stats, | |
5869 | .phys_id = niu_phys_id, | |
5870 | }; | |
5871 | ||
5872 | static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent, | |
5873 | int ldg, int ldn) | |
5874 | { | |
5875 | if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) | |
5876 | return -EINVAL; | |
5877 | if (ldn < 0 || ldn > LDN_MAX) | |
5878 | return -EINVAL; | |
5879 | ||
5880 | parent->ldg_map[ldn] = ldg; | |
5881 | ||
5882 | if (np->parent->plat_type == PLAT_TYPE_NIU) { | |
5883 | /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by | |
5884 | * the firmware, and we're not supposed to change them. | |
5885 | * Validate the mapping, because if it's wrong we probably | |
5886 | * won't get any interrupts and that's painful to debug. | |
5887 | */ | |
5888 | if (nr64(LDG_NUM(ldn)) != ldg) { | |
5889 | dev_err(np->device, PFX "Port %u, mis-matched " | |
5890 | "LDG assignment " | |
5891 | "for ldn %d, should be %d is %llu\n", | |
5892 | np->port, ldn, ldg, | |
5893 | (unsigned long long) nr64(LDG_NUM(ldn))); | |
5894 | return -EINVAL; | |
5895 | } | |
5896 | } else | |
5897 | nw64(LDG_NUM(ldn), ldg); | |
5898 | ||
5899 | return 0; | |
5900 | } | |
5901 | ||
5902 | static int niu_set_ldg_timer_res(struct niu *np, int res) | |
5903 | { | |
5904 | if (res < 0 || res > LDG_TIMER_RES_VAL) | |
5905 | return -EINVAL; | |
5906 | ||
5907 | ||
5908 | nw64(LDG_TIMER_RES, res); | |
5909 | ||
5910 | return 0; | |
5911 | } | |
5912 | ||
5913 | static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector) | |
5914 | { | |
5915 | if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) || | |
5916 | (func < 0 || func > 3) || | |
5917 | (vector < 0 || vector > 0x1f)) | |
5918 | return -EINVAL; | |
5919 | ||
5920 | nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector); | |
5921 | ||
5922 | return 0; | |
5923 | } | |
5924 | ||
5925 | static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr) | |
5926 | { | |
5927 | u64 frame, frame_base = (ESPC_PIO_STAT_READ_START | | |
5928 | (addr << ESPC_PIO_STAT_ADDR_SHIFT)); | |
5929 | int limit; | |
5930 | ||
5931 | if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT)) | |
5932 | return -EINVAL; | |
5933 | ||
5934 | frame = frame_base; | |
5935 | nw64(ESPC_PIO_STAT, frame); | |
5936 | limit = 64; | |
5937 | do { | |
5938 | udelay(5); | |
5939 | frame = nr64(ESPC_PIO_STAT); | |
5940 | if (frame & ESPC_PIO_STAT_READ_END) | |
5941 | break; | |
5942 | } while (limit--); | |
5943 | if (!(frame & ESPC_PIO_STAT_READ_END)) { | |
5944 | dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n", | |
5945 | (unsigned long long) frame); | |
5946 | return -ENODEV; | |
5947 | } | |
5948 | ||
5949 | frame = frame_base; | |
5950 | nw64(ESPC_PIO_STAT, frame); | |
5951 | limit = 64; | |
5952 | do { | |
5953 | udelay(5); | |
5954 | frame = nr64(ESPC_PIO_STAT); | |
5955 | if (frame & ESPC_PIO_STAT_READ_END) | |
5956 | break; | |
5957 | } while (limit--); | |
5958 | if (!(frame & ESPC_PIO_STAT_READ_END)) { | |
5959 | dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n", | |
5960 | (unsigned long long) frame); | |
5961 | return -ENODEV; | |
5962 | } | |
5963 | ||
5964 | frame = nr64(ESPC_PIO_STAT); | |
5965 | return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT; | |
5966 | } | |
5967 | ||
5968 | static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off) | |
5969 | { | |
5970 | int err = niu_pci_eeprom_read(np, off); | |
5971 | u16 val; | |
5972 | ||
5973 | if (err < 0) | |
5974 | return err; | |
5975 | val = (err << 8); | |
5976 | err = niu_pci_eeprom_read(np, off + 1); | |
5977 | if (err < 0) | |
5978 | return err; | |
5979 | val |= (err & 0xff); | |
5980 | ||
5981 | return val; | |
5982 | } | |
5983 | ||
5984 | static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off) | |
5985 | { | |
5986 | int err = niu_pci_eeprom_read(np, off); | |
5987 | u16 val; | |
5988 | ||
5989 | if (err < 0) | |
5990 | return err; | |
5991 | ||
5992 | val = (err & 0xff); | |
5993 | err = niu_pci_eeprom_read(np, off + 1); | |
5994 | if (err < 0) | |
5995 | return err; | |
5996 | ||
5997 | val |= (err & 0xff) << 8; | |
5998 | ||
5999 | return val; | |
6000 | } | |
6001 | ||
6002 | static int __devinit niu_pci_vpd_get_propname(struct niu *np, | |
6003 | u32 off, | |
6004 | char *namebuf, | |
6005 | int namebuf_len) | |
6006 | { | |
6007 | int i; | |
6008 | ||
6009 | for (i = 0; i < namebuf_len; i++) { | |
6010 | int err = niu_pci_eeprom_read(np, off + i); | |
6011 | if (err < 0) | |
6012 | return err; | |
6013 | *namebuf++ = err; | |
6014 | if (!err) | |
6015 | break; | |
6016 | } | |
6017 | if (i >= namebuf_len) | |
6018 | return -EINVAL; | |
6019 | ||
6020 | return i + 1; | |
6021 | } | |
6022 | ||
6023 | static void __devinit niu_vpd_parse_version(struct niu *np) | |
6024 | { | |
6025 | struct niu_vpd *vpd = &np->vpd; | |
6026 | int len = strlen(vpd->version) + 1; | |
6027 | const char *s = vpd->version; | |
6028 | int i; | |
6029 | ||
6030 | for (i = 0; i < len - 5; i++) { | |
6031 | if (!strncmp(s + i, "FCode ", 5)) | |
6032 | break; | |
6033 | } | |
6034 | if (i >= len - 5) | |
6035 | return; | |
6036 | ||
6037 | s += i + 5; | |
6038 | sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor); | |
6039 | ||
6040 | niudbg(PROBE, "VPD_SCAN: FCODE major(%d) minor(%d)\n", | |
6041 | vpd->fcode_major, vpd->fcode_minor); | |
6042 | if (vpd->fcode_major > NIU_VPD_MIN_MAJOR || | |
6043 | (vpd->fcode_major == NIU_VPD_MIN_MAJOR && | |
6044 | vpd->fcode_minor >= NIU_VPD_MIN_MINOR)) | |
6045 | np->flags |= NIU_FLAGS_VPD_VALID; | |
6046 | } | |
6047 | ||
6048 | /* ESPC_PIO_EN_ENABLE must be set */ | |
6049 | static int __devinit niu_pci_vpd_scan_props(struct niu *np, | |
6050 | u32 start, u32 end) | |
6051 | { | |
6052 | unsigned int found_mask = 0; | |
6053 | #define FOUND_MASK_MODEL 0x00000001 | |
6054 | #define FOUND_MASK_BMODEL 0x00000002 | |
6055 | #define FOUND_MASK_VERS 0x00000004 | |
6056 | #define FOUND_MASK_MAC 0x00000008 | |
6057 | #define FOUND_MASK_NMAC 0x00000010 | |
6058 | #define FOUND_MASK_PHY 0x00000020 | |
6059 | #define FOUND_MASK_ALL 0x0000003f | |
6060 | ||
6061 | niudbg(PROBE, "VPD_SCAN: start[%x] end[%x]\n", | |
6062 | start, end); | |
6063 | while (start < end) { | |
6064 | int len, err, instance, type, prop_len; | |
6065 | char namebuf[64]; | |
6066 | u8 *prop_buf; | |
6067 | int max_len; | |
6068 | ||
6069 | if (found_mask == FOUND_MASK_ALL) { | |
6070 | niu_vpd_parse_version(np); | |
6071 | return 1; | |
6072 | } | |
6073 | ||
6074 | err = niu_pci_eeprom_read(np, start + 2); | |
6075 | if (err < 0) | |
6076 | return err; | |
6077 | len = err; | |
6078 | start += 3; | |
6079 | ||
6080 | instance = niu_pci_eeprom_read(np, start); | |
6081 | type = niu_pci_eeprom_read(np, start + 3); | |
6082 | prop_len = niu_pci_eeprom_read(np, start + 4); | |
6083 | err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64); | |
6084 | if (err < 0) | |
6085 | return err; | |
6086 | ||
6087 | prop_buf = NULL; | |
6088 | max_len = 0; | |
6089 | if (!strcmp(namebuf, "model")) { | |
6090 | prop_buf = np->vpd.model; | |
6091 | max_len = NIU_VPD_MODEL_MAX; | |
6092 | found_mask |= FOUND_MASK_MODEL; | |
6093 | } else if (!strcmp(namebuf, "board-model")) { | |
6094 | prop_buf = np->vpd.board_model; | |
6095 | max_len = NIU_VPD_BD_MODEL_MAX; | |
6096 | found_mask |= FOUND_MASK_BMODEL; | |
6097 | } else if (!strcmp(namebuf, "version")) { | |
6098 | prop_buf = np->vpd.version; | |
6099 | max_len = NIU_VPD_VERSION_MAX; | |
6100 | found_mask |= FOUND_MASK_VERS; | |
6101 | } else if (!strcmp(namebuf, "local-mac-address")) { | |
6102 | prop_buf = np->vpd.local_mac; | |
6103 | max_len = ETH_ALEN; | |
6104 | found_mask |= FOUND_MASK_MAC; | |
6105 | } else if (!strcmp(namebuf, "num-mac-addresses")) { | |
6106 | prop_buf = &np->vpd.mac_num; | |
6107 | max_len = 1; | |
6108 | found_mask |= FOUND_MASK_NMAC; | |
6109 | } else if (!strcmp(namebuf, "phy-type")) { | |
6110 | prop_buf = np->vpd.phy_type; | |
6111 | max_len = NIU_VPD_PHY_TYPE_MAX; | |
6112 | found_mask |= FOUND_MASK_PHY; | |
6113 | } | |
6114 | ||
6115 | if (max_len && prop_len > max_len) { | |
6116 | dev_err(np->device, PFX "Property '%s' length (%d) is " | |
6117 | "too long.\n", namebuf, prop_len); | |
6118 | return -EINVAL; | |
6119 | } | |
6120 | ||
6121 | if (prop_buf) { | |
6122 | u32 off = start + 5 + err; | |
6123 | int i; | |
6124 | ||
6125 | niudbg(PROBE, "VPD_SCAN: Reading in property [%s] " | |
6126 | "len[%d]\n", namebuf, prop_len); | |
6127 | for (i = 0; i < prop_len; i++) | |
6128 | *prop_buf++ = niu_pci_eeprom_read(np, off + i); | |
6129 | } | |
6130 | ||
6131 | start += len; | |
6132 | } | |
6133 | ||
6134 | return 0; | |
6135 | } | |
6136 | ||
6137 | /* ESPC_PIO_EN_ENABLE must be set */ | |
6138 | static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start) | |
6139 | { | |
6140 | u32 offset; | |
6141 | int err; | |
6142 | ||
6143 | err = niu_pci_eeprom_read16_swp(np, start + 1); | |
6144 | if (err < 0) | |
6145 | return; | |
6146 | ||
6147 | offset = err + 3; | |
6148 | ||
6149 | while (start + offset < ESPC_EEPROM_SIZE) { | |
6150 | u32 here = start + offset; | |
6151 | u32 end; | |
6152 | ||
6153 | err = niu_pci_eeprom_read(np, here); | |
6154 | if (err != 0x90) | |
6155 | return; | |
6156 | ||
6157 | err = niu_pci_eeprom_read16_swp(np, here + 1); | |
6158 | if (err < 0) | |
6159 | return; | |
6160 | ||
6161 | here = start + offset + 3; | |
6162 | end = start + offset + err; | |
6163 | ||
6164 | offset += err; | |
6165 | ||
6166 | err = niu_pci_vpd_scan_props(np, here, end); | |
6167 | if (err < 0 || err == 1) | |
6168 | return; | |
6169 | } | |
6170 | } | |
6171 | ||
6172 | /* ESPC_PIO_EN_ENABLE must be set */ | |
6173 | static u32 __devinit niu_pci_vpd_offset(struct niu *np) | |
6174 | { | |
6175 | u32 start = 0, end = ESPC_EEPROM_SIZE, ret; | |
6176 | int err; | |
6177 | ||
6178 | while (start < end) { | |
6179 | ret = start; | |
6180 | ||
6181 | /* ROM header signature? */ | |
6182 | err = niu_pci_eeprom_read16(np, start + 0); | |
6183 | if (err != 0x55aa) | |
6184 | return 0; | |
6185 | ||
6186 | /* Apply offset to PCI data structure. */ | |
6187 | err = niu_pci_eeprom_read16(np, start + 23); | |
6188 | if (err < 0) | |
6189 | return 0; | |
6190 | start += err; | |
6191 | ||
6192 | /* Check for "PCIR" signature. */ | |
6193 | err = niu_pci_eeprom_read16(np, start + 0); | |
6194 | if (err != 0x5043) | |
6195 | return 0; | |
6196 | err = niu_pci_eeprom_read16(np, start + 2); | |
6197 | if (err != 0x4952) | |
6198 | return 0; | |
6199 | ||
6200 | /* Check for OBP image type. */ | |
6201 | err = niu_pci_eeprom_read(np, start + 20); | |
6202 | if (err < 0) | |
6203 | return 0; | |
6204 | if (err != 0x01) { | |
6205 | err = niu_pci_eeprom_read(np, ret + 2); | |
6206 | if (err < 0) | |
6207 | return 0; | |
6208 | ||
6209 | start = ret + (err * 512); | |
6210 | continue; | |
6211 | } | |
6212 | ||
6213 | err = niu_pci_eeprom_read16_swp(np, start + 8); | |
6214 | if (err < 0) | |
6215 | return err; | |
6216 | ret += err; | |
6217 | ||
6218 | err = niu_pci_eeprom_read(np, ret + 0); | |
6219 | if (err != 0x82) | |
6220 | return 0; | |
6221 | ||
6222 | return ret; | |
6223 | } | |
6224 | ||
6225 | return 0; | |
6226 | } | |
6227 | ||
6228 | static int __devinit niu_phy_type_prop_decode(struct niu *np, | |
6229 | const char *phy_prop) | |
6230 | { | |
6231 | if (!strcmp(phy_prop, "mif")) { | |
6232 | /* 1G copper, MII */ | |
6233 | np->flags &= ~(NIU_FLAGS_FIBER | | |
6234 | NIU_FLAGS_10G); | |
6235 | np->mac_xcvr = MAC_XCVR_MII; | |
6236 | } else if (!strcmp(phy_prop, "xgf")) { | |
6237 | /* 10G fiber, XPCS */ | |
6238 | np->flags |= (NIU_FLAGS_10G | | |
6239 | NIU_FLAGS_FIBER); | |
6240 | np->mac_xcvr = MAC_XCVR_XPCS; | |
6241 | } else if (!strcmp(phy_prop, "pcs")) { | |
6242 | /* 1G fiber, PCS */ | |
6243 | np->flags &= ~NIU_FLAGS_10G; | |
6244 | np->flags |= NIU_FLAGS_FIBER; | |
6245 | np->mac_xcvr = MAC_XCVR_PCS; | |
6246 | } else if (!strcmp(phy_prop, "xgc")) { | |
6247 | /* 10G copper, XPCS */ | |
6248 | np->flags |= NIU_FLAGS_10G; | |
6249 | np->flags &= ~NIU_FLAGS_FIBER; | |
6250 | np->mac_xcvr = MAC_XCVR_XPCS; | |
6251 | } else { | |
6252 | return -EINVAL; | |
6253 | } | |
6254 | return 0; | |
6255 | } | |
6256 | ||
6257 | static void __devinit niu_pci_vpd_validate(struct niu *np) | |
6258 | { | |
6259 | struct net_device *dev = np->dev; | |
6260 | struct niu_vpd *vpd = &np->vpd; | |
6261 | u8 val8; | |
6262 | ||
6263 | if (!is_valid_ether_addr(&vpd->local_mac[0])) { | |
6264 | dev_err(np->device, PFX "VPD MAC invalid, " | |
6265 | "falling back to SPROM.\n"); | |
6266 | ||
6267 | np->flags &= ~NIU_FLAGS_VPD_VALID; | |
6268 | return; | |
6269 | } | |
6270 | ||
6271 | if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) { | |
6272 | dev_err(np->device, PFX "Illegal phy string [%s].\n", | |
6273 | np->vpd.phy_type); | |
6274 | dev_err(np->device, PFX "Falling back to SPROM.\n"); | |
6275 | np->flags &= ~NIU_FLAGS_VPD_VALID; | |
6276 | return; | |
6277 | } | |
6278 | ||
6279 | memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN); | |
6280 | ||
6281 | val8 = dev->perm_addr[5]; | |
6282 | dev->perm_addr[5] += np->port; | |
6283 | if (dev->perm_addr[5] < val8) | |
6284 | dev->perm_addr[4]++; | |
6285 | ||
6286 | memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len); | |
6287 | } | |
6288 | ||
6289 | static int __devinit niu_pci_probe_sprom(struct niu *np) | |
6290 | { | |
6291 | struct net_device *dev = np->dev; | |
6292 | int len, i; | |
6293 | u64 val, sum; | |
6294 | u8 val8; | |
6295 | ||
6296 | val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ); | |
6297 | val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT; | |
6298 | len = val / 4; | |
6299 | ||
6300 | np->eeprom_len = len; | |
6301 | ||
6302 | niudbg(PROBE, "SPROM: Image size %llu\n", (unsigned long long) val); | |
6303 | ||
6304 | sum = 0; | |
6305 | for (i = 0; i < len; i++) { | |
6306 | val = nr64(ESPC_NCR(i)); | |
6307 | sum += (val >> 0) & 0xff; | |
6308 | sum += (val >> 8) & 0xff; | |
6309 | sum += (val >> 16) & 0xff; | |
6310 | sum += (val >> 24) & 0xff; | |
6311 | } | |
6312 | niudbg(PROBE, "SPROM: Checksum %x\n", (int)(sum & 0xff)); | |
6313 | if ((sum & 0xff) != 0xab) { | |
6314 | dev_err(np->device, PFX "Bad SPROM checksum " | |
6315 | "(%x, should be 0xab)\n", (int) (sum & 0xff)); | |
6316 | return -EINVAL; | |
6317 | } | |
6318 | ||
6319 | val = nr64(ESPC_PHY_TYPE); | |
6320 | switch (np->port) { | |
6321 | case 0: | |
a9d41192 | 6322 | val8 = (val & ESPC_PHY_TYPE_PORT0) >> |
a3138df9 DM |
6323 | ESPC_PHY_TYPE_PORT0_SHIFT; |
6324 | break; | |
6325 | case 1: | |
a9d41192 | 6326 | val8 = (val & ESPC_PHY_TYPE_PORT1) >> |
a3138df9 DM |
6327 | ESPC_PHY_TYPE_PORT1_SHIFT; |
6328 | break; | |
6329 | case 2: | |
a9d41192 | 6330 | val8 = (val & ESPC_PHY_TYPE_PORT2) >> |
a3138df9 DM |
6331 | ESPC_PHY_TYPE_PORT2_SHIFT; |
6332 | break; | |
6333 | case 3: | |
a9d41192 | 6334 | val8 = (val & ESPC_PHY_TYPE_PORT3) >> |
a3138df9 DM |
6335 | ESPC_PHY_TYPE_PORT3_SHIFT; |
6336 | break; | |
6337 | default: | |
6338 | dev_err(np->device, PFX "Bogus port number %u\n", | |
6339 | np->port); | |
6340 | return -EINVAL; | |
6341 | } | |
a9d41192 | 6342 | niudbg(PROBE, "SPROM: PHY type %x\n", val8); |
a3138df9 | 6343 | |
a9d41192 | 6344 | switch (val8) { |
a3138df9 DM |
6345 | case ESPC_PHY_TYPE_1G_COPPER: |
6346 | /* 1G copper, MII */ | |
6347 | np->flags &= ~(NIU_FLAGS_FIBER | | |
6348 | NIU_FLAGS_10G); | |
6349 | np->mac_xcvr = MAC_XCVR_MII; | |
6350 | break; | |
6351 | ||
6352 | case ESPC_PHY_TYPE_1G_FIBER: | |
6353 | /* 1G fiber, PCS */ | |
6354 | np->flags &= ~NIU_FLAGS_10G; | |
6355 | np->flags |= NIU_FLAGS_FIBER; | |
6356 | np->mac_xcvr = MAC_XCVR_PCS; | |
6357 | break; | |
6358 | ||
6359 | case ESPC_PHY_TYPE_10G_COPPER: | |
6360 | /* 10G copper, XPCS */ | |
6361 | np->flags |= NIU_FLAGS_10G; | |
6362 | np->flags &= ~NIU_FLAGS_FIBER; | |
6363 | np->mac_xcvr = MAC_XCVR_XPCS; | |
6364 | break; | |
6365 | ||
6366 | case ESPC_PHY_TYPE_10G_FIBER: | |
6367 | /* 10G fiber, XPCS */ | |
6368 | np->flags |= (NIU_FLAGS_10G | | |
6369 | NIU_FLAGS_FIBER); | |
6370 | np->mac_xcvr = MAC_XCVR_XPCS; | |
6371 | break; | |
6372 | ||
6373 | default: | |
a9d41192 | 6374 | dev_err(np->device, PFX "Bogus SPROM phy type %u\n", val8); |
a3138df9 DM |
6375 | return -EINVAL; |
6376 | } | |
6377 | ||
6378 | val = nr64(ESPC_MAC_ADDR0); | |
6379 | niudbg(PROBE, "SPROM: MAC_ADDR0[%08llx]\n", | |
6380 | (unsigned long long) val); | |
6381 | dev->perm_addr[0] = (val >> 0) & 0xff; | |
6382 | dev->perm_addr[1] = (val >> 8) & 0xff; | |
6383 | dev->perm_addr[2] = (val >> 16) & 0xff; | |
6384 | dev->perm_addr[3] = (val >> 24) & 0xff; | |
6385 | ||
6386 | val = nr64(ESPC_MAC_ADDR1); | |
6387 | niudbg(PROBE, "SPROM: MAC_ADDR1[%08llx]\n", | |
6388 | (unsigned long long) val); | |
6389 | dev->perm_addr[4] = (val >> 0) & 0xff; | |
6390 | dev->perm_addr[5] = (val >> 8) & 0xff; | |
6391 | ||
6392 | if (!is_valid_ether_addr(&dev->perm_addr[0])) { | |
6393 | dev_err(np->device, PFX "SPROM MAC address invalid\n"); | |
6394 | dev_err(np->device, PFX "[ \n"); | |
6395 | for (i = 0; i < 6; i++) | |
6396 | printk("%02x ", dev->perm_addr[i]); | |
6397 | printk("]\n"); | |
6398 | return -EINVAL; | |
6399 | } | |
6400 | ||
6401 | val8 = dev->perm_addr[5]; | |
6402 | dev->perm_addr[5] += np->port; | |
6403 | if (dev->perm_addr[5] < val8) | |
6404 | dev->perm_addr[4]++; | |
6405 | ||
6406 | memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len); | |
6407 | ||
6408 | val = nr64(ESPC_MOD_STR_LEN); | |
6409 | niudbg(PROBE, "SPROM: MOD_STR_LEN[%llu]\n", | |
6410 | (unsigned long long) val); | |
e6a5fdf5 | 6411 | if (val >= 8 * 4) |
a3138df9 DM |
6412 | return -EINVAL; |
6413 | ||
6414 | for (i = 0; i < val; i += 4) { | |
6415 | u64 tmp = nr64(ESPC_NCR(5 + (i / 4))); | |
6416 | ||
6417 | np->vpd.model[i + 3] = (tmp >> 0) & 0xff; | |
6418 | np->vpd.model[i + 2] = (tmp >> 8) & 0xff; | |
6419 | np->vpd.model[i + 1] = (tmp >> 16) & 0xff; | |
6420 | np->vpd.model[i + 0] = (tmp >> 24) & 0xff; | |
6421 | } | |
6422 | np->vpd.model[val] = '\0'; | |
6423 | ||
6424 | val = nr64(ESPC_BD_MOD_STR_LEN); | |
6425 | niudbg(PROBE, "SPROM: BD_MOD_STR_LEN[%llu]\n", | |
6426 | (unsigned long long) val); | |
e6a5fdf5 | 6427 | if (val >= 4 * 4) |
a3138df9 DM |
6428 | return -EINVAL; |
6429 | ||
6430 | for (i = 0; i < val; i += 4) { | |
6431 | u64 tmp = nr64(ESPC_NCR(14 + (i / 4))); | |
6432 | ||
6433 | np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff; | |
6434 | np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff; | |
6435 | np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff; | |
6436 | np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff; | |
6437 | } | |
6438 | np->vpd.board_model[val] = '\0'; | |
6439 | ||
6440 | np->vpd.mac_num = | |
6441 | nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL; | |
6442 | niudbg(PROBE, "SPROM: NUM_PORTS_MACS[%d]\n", | |
6443 | np->vpd.mac_num); | |
6444 | ||
6445 | return 0; | |
6446 | } | |
6447 | ||
6448 | static int __devinit niu_get_and_validate_port(struct niu *np) | |
6449 | { | |
6450 | struct niu_parent *parent = np->parent; | |
6451 | ||
6452 | if (np->port <= 1) | |
6453 | np->flags |= NIU_FLAGS_XMAC; | |
6454 | ||
6455 | if (!parent->num_ports) { | |
6456 | if (parent->plat_type == PLAT_TYPE_NIU) { | |
6457 | parent->num_ports = 2; | |
6458 | } else { | |
6459 | parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) & | |
6460 | ESPC_NUM_PORTS_MACS_VAL; | |
6461 | ||
6462 | if (!parent->num_ports) | |
6463 | parent->num_ports = 4; | |
6464 | } | |
6465 | } | |
6466 | ||
6467 | niudbg(PROBE, "niu_get_and_validate_port: port[%d] num_ports[%d]\n", | |
6468 | np->port, parent->num_ports); | |
6469 | if (np->port >= parent->num_ports) | |
6470 | return -ENODEV; | |
6471 | ||
6472 | return 0; | |
6473 | } | |
6474 | ||
6475 | static int __devinit phy_record(struct niu_parent *parent, | |
6476 | struct phy_probe_info *p, | |
6477 | int dev_id_1, int dev_id_2, u8 phy_port, | |
6478 | int type) | |
6479 | { | |
6480 | u32 id = (dev_id_1 << 16) | dev_id_2; | |
6481 | u8 idx; | |
6482 | ||
6483 | if (dev_id_1 < 0 || dev_id_2 < 0) | |
6484 | return 0; | |
6485 | if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) { | |
b0de8e40 ML |
6486 | if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) && |
6487 | ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011)) | |
a3138df9 DM |
6488 | return 0; |
6489 | } else { | |
6490 | if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R) | |
6491 | return 0; | |
6492 | } | |
6493 | ||
6494 | pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n", | |
6495 | parent->index, id, | |
6496 | (type == PHY_TYPE_PMA_PMD ? | |
6497 | "PMA/PMD" : | |
6498 | (type == PHY_TYPE_PCS ? | |
6499 | "PCS" : "MII")), | |
6500 | phy_port); | |
6501 | ||
6502 | if (p->cur[type] >= NIU_MAX_PORTS) { | |
6503 | printk(KERN_ERR PFX "Too many PHY ports.\n"); | |
6504 | return -EINVAL; | |
6505 | } | |
6506 | idx = p->cur[type]; | |
6507 | p->phy_id[type][idx] = id; | |
6508 | p->phy_port[type][idx] = phy_port; | |
6509 | p->cur[type] = idx + 1; | |
6510 | return 0; | |
6511 | } | |
6512 | ||
6513 | static int __devinit port_has_10g(struct phy_probe_info *p, int port) | |
6514 | { | |
6515 | int i; | |
6516 | ||
6517 | for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) { | |
6518 | if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port) | |
6519 | return 1; | |
6520 | } | |
6521 | for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) { | |
6522 | if (p->phy_port[PHY_TYPE_PCS][i] == port) | |
6523 | return 1; | |
6524 | } | |
6525 | ||
6526 | return 0; | |
6527 | } | |
6528 | ||
6529 | static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest) | |
6530 | { | |
6531 | int port, cnt; | |
6532 | ||
6533 | cnt = 0; | |
6534 | *lowest = 32; | |
6535 | for (port = 8; port < 32; port++) { | |
6536 | if (port_has_10g(p, port)) { | |
6537 | if (!cnt) | |
6538 | *lowest = port; | |
6539 | cnt++; | |
6540 | } | |
6541 | } | |
6542 | ||
6543 | return cnt; | |
6544 | } | |
6545 | ||
6546 | static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest) | |
6547 | { | |
6548 | *lowest = 32; | |
6549 | if (p->cur[PHY_TYPE_MII]) | |
6550 | *lowest = p->phy_port[PHY_TYPE_MII][0]; | |
6551 | ||
6552 | return p->cur[PHY_TYPE_MII]; | |
6553 | } | |
6554 | ||
6555 | static void __devinit niu_n2_divide_channels(struct niu_parent *parent) | |
6556 | { | |
6557 | int num_ports = parent->num_ports; | |
6558 | int i; | |
6559 | ||
6560 | for (i = 0; i < num_ports; i++) { | |
6561 | parent->rxchan_per_port[i] = (16 / num_ports); | |
6562 | parent->txchan_per_port[i] = (16 / num_ports); | |
6563 | ||
6564 | pr_info(PFX "niu%d: Port %u [%u RX chans] " | |
6565 | "[%u TX chans]\n", | |
6566 | parent->index, i, | |
6567 | parent->rxchan_per_port[i], | |
6568 | parent->txchan_per_port[i]); | |
6569 | } | |
6570 | } | |
6571 | ||
6572 | static void __devinit niu_divide_channels(struct niu_parent *parent, | |
6573 | int num_10g, int num_1g) | |
6574 | { | |
6575 | int num_ports = parent->num_ports; | |
6576 | int rx_chans_per_10g, rx_chans_per_1g; | |
6577 | int tx_chans_per_10g, tx_chans_per_1g; | |
6578 | int i, tot_rx, tot_tx; | |
6579 | ||
6580 | if (!num_10g || !num_1g) { | |
6581 | rx_chans_per_10g = rx_chans_per_1g = | |
6582 | (NIU_NUM_RXCHAN / num_ports); | |
6583 | tx_chans_per_10g = tx_chans_per_1g = | |
6584 | (NIU_NUM_TXCHAN / num_ports); | |
6585 | } else { | |
6586 | rx_chans_per_1g = NIU_NUM_RXCHAN / 8; | |
6587 | rx_chans_per_10g = (NIU_NUM_RXCHAN - | |
6588 | (rx_chans_per_1g * num_1g)) / | |
6589 | num_10g; | |
6590 | ||
6591 | tx_chans_per_1g = NIU_NUM_TXCHAN / 6; | |
6592 | tx_chans_per_10g = (NIU_NUM_TXCHAN - | |
6593 | (tx_chans_per_1g * num_1g)) / | |
6594 | num_10g; | |
6595 | } | |
6596 | ||
6597 | tot_rx = tot_tx = 0; | |
6598 | for (i = 0; i < num_ports; i++) { | |
6599 | int type = phy_decode(parent->port_phy, i); | |
6600 | ||
6601 | if (type == PORT_TYPE_10G) { | |
6602 | parent->rxchan_per_port[i] = rx_chans_per_10g; | |
6603 | parent->txchan_per_port[i] = tx_chans_per_10g; | |
6604 | } else { | |
6605 | parent->rxchan_per_port[i] = rx_chans_per_1g; | |
6606 | parent->txchan_per_port[i] = tx_chans_per_1g; | |
6607 | } | |
6608 | pr_info(PFX "niu%d: Port %u [%u RX chans] " | |
6609 | "[%u TX chans]\n", | |
6610 | parent->index, i, | |
6611 | parent->rxchan_per_port[i], | |
6612 | parent->txchan_per_port[i]); | |
6613 | tot_rx += parent->rxchan_per_port[i]; | |
6614 | tot_tx += parent->txchan_per_port[i]; | |
6615 | } | |
6616 | ||
6617 | if (tot_rx > NIU_NUM_RXCHAN) { | |
6618 | printk(KERN_ERR PFX "niu%d: Too many RX channels (%d), " | |
6619 | "resetting to one per port.\n", | |
6620 | parent->index, tot_rx); | |
6621 | for (i = 0; i < num_ports; i++) | |
6622 | parent->rxchan_per_port[i] = 1; | |
6623 | } | |
6624 | if (tot_tx > NIU_NUM_TXCHAN) { | |
6625 | printk(KERN_ERR PFX "niu%d: Too many TX channels (%d), " | |
6626 | "resetting to one per port.\n", | |
6627 | parent->index, tot_tx); | |
6628 | for (i = 0; i < num_ports; i++) | |
6629 | parent->txchan_per_port[i] = 1; | |
6630 | } | |
6631 | if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) { | |
6632 | printk(KERN_WARNING PFX "niu%d: Driver bug, wasted channels, " | |
6633 | "RX[%d] TX[%d]\n", | |
6634 | parent->index, tot_rx, tot_tx); | |
6635 | } | |
6636 | } | |
6637 | ||
6638 | static void __devinit niu_divide_rdc_groups(struct niu_parent *parent, | |
6639 | int num_10g, int num_1g) | |
6640 | { | |
6641 | int i, num_ports = parent->num_ports; | |
6642 | int rdc_group, rdc_groups_per_port; | |
6643 | int rdc_channel_base; | |
6644 | ||
6645 | rdc_group = 0; | |
6646 | rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports; | |
6647 | ||
6648 | rdc_channel_base = 0; | |
6649 | ||
6650 | for (i = 0; i < num_ports; i++) { | |
6651 | struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i]; | |
6652 | int grp, num_channels = parent->rxchan_per_port[i]; | |
6653 | int this_channel_offset; | |
6654 | ||
6655 | tp->first_table_num = rdc_group; | |
6656 | tp->num_tables = rdc_groups_per_port; | |
6657 | this_channel_offset = 0; | |
6658 | for (grp = 0; grp < tp->num_tables; grp++) { | |
6659 | struct rdc_table *rt = &tp->tables[grp]; | |
6660 | int slot; | |
6661 | ||
6662 | pr_info(PFX "niu%d: Port %d RDC tbl(%d) [ ", | |
6663 | parent->index, i, tp->first_table_num + grp); | |
6664 | for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) { | |
6665 | rt->rxdma_channel[slot] = | |
6666 | rdc_channel_base + this_channel_offset; | |
6667 | ||
6668 | printk("%d ", rt->rxdma_channel[slot]); | |
6669 | ||
6670 | if (++this_channel_offset == num_channels) | |
6671 | this_channel_offset = 0; | |
6672 | } | |
6673 | printk("]\n"); | |
6674 | } | |
6675 | ||
6676 | parent->rdc_default[i] = rdc_channel_base; | |
6677 | ||
6678 | rdc_channel_base += num_channels; | |
6679 | rdc_group += rdc_groups_per_port; | |
6680 | } | |
6681 | } | |
6682 | ||
6683 | static int __devinit fill_phy_probe_info(struct niu *np, | |
6684 | struct niu_parent *parent, | |
6685 | struct phy_probe_info *info) | |
6686 | { | |
6687 | unsigned long flags; | |
6688 | int port, err; | |
6689 | ||
6690 | memset(info, 0, sizeof(*info)); | |
6691 | ||
6692 | /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */ | |
6693 | niu_lock_parent(np, flags); | |
6694 | err = 0; | |
6695 | for (port = 8; port < 32; port++) { | |
6696 | int dev_id_1, dev_id_2; | |
6697 | ||
6698 | dev_id_1 = mdio_read(np, port, | |
6699 | NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1); | |
6700 | dev_id_2 = mdio_read(np, port, | |
6701 | NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2); | |
6702 | err = phy_record(parent, info, dev_id_1, dev_id_2, port, | |
6703 | PHY_TYPE_PMA_PMD); | |
6704 | if (err) | |
6705 | break; | |
6706 | dev_id_1 = mdio_read(np, port, | |
6707 | NIU_PCS_DEV_ADDR, MII_PHYSID1); | |
6708 | dev_id_2 = mdio_read(np, port, | |
6709 | NIU_PCS_DEV_ADDR, MII_PHYSID2); | |
6710 | err = phy_record(parent, info, dev_id_1, dev_id_2, port, | |
6711 | PHY_TYPE_PCS); | |
6712 | if (err) | |
6713 | break; | |
6714 | dev_id_1 = mii_read(np, port, MII_PHYSID1); | |
6715 | dev_id_2 = mii_read(np, port, MII_PHYSID2); | |
6716 | err = phy_record(parent, info, dev_id_1, dev_id_2, port, | |
6717 | PHY_TYPE_MII); | |
6718 | if (err) | |
6719 | break; | |
6720 | } | |
6721 | niu_unlock_parent(np, flags); | |
6722 | ||
6723 | return err; | |
6724 | } | |
6725 | ||
6726 | static int __devinit walk_phys(struct niu *np, struct niu_parent *parent) | |
6727 | { | |
6728 | struct phy_probe_info *info = &parent->phy_probe_info; | |
6729 | int lowest_10g, lowest_1g; | |
6730 | int num_10g, num_1g; | |
6731 | u32 val; | |
6732 | int err; | |
6733 | ||
6734 | err = fill_phy_probe_info(np, parent, info); | |
6735 | if (err) | |
6736 | return err; | |
6737 | ||
6738 | num_10g = count_10g_ports(info, &lowest_10g); | |
6739 | num_1g = count_1g_ports(info, &lowest_1g); | |
6740 | ||
6741 | switch ((num_10g << 4) | num_1g) { | |
6742 | case 0x24: | |
6743 | if (lowest_1g == 10) | |
6744 | parent->plat_type = PLAT_TYPE_VF_P0; | |
6745 | else if (lowest_1g == 26) | |
6746 | parent->plat_type = PLAT_TYPE_VF_P1; | |
6747 | else | |
6748 | goto unknown_vg_1g_port; | |
6749 | ||
6750 | /* fallthru */ | |
6751 | case 0x22: | |
6752 | val = (phy_encode(PORT_TYPE_10G, 0) | | |
6753 | phy_encode(PORT_TYPE_10G, 1) | | |
6754 | phy_encode(PORT_TYPE_1G, 2) | | |
6755 | phy_encode(PORT_TYPE_1G, 3)); | |
6756 | break; | |
6757 | ||
6758 | case 0x20: | |
6759 | val = (phy_encode(PORT_TYPE_10G, 0) | | |
6760 | phy_encode(PORT_TYPE_10G, 1)); | |
6761 | break; | |
6762 | ||
6763 | case 0x10: | |
6764 | val = phy_encode(PORT_TYPE_10G, np->port); | |
6765 | break; | |
6766 | ||
6767 | case 0x14: | |
6768 | if (lowest_1g == 10) | |
6769 | parent->plat_type = PLAT_TYPE_VF_P0; | |
6770 | else if (lowest_1g == 26) | |
6771 | parent->plat_type = PLAT_TYPE_VF_P1; | |
6772 | else | |
6773 | goto unknown_vg_1g_port; | |
6774 | ||
6775 | /* fallthru */ | |
6776 | case 0x13: | |
6777 | if ((lowest_10g & 0x7) == 0) | |
6778 | val = (phy_encode(PORT_TYPE_10G, 0) | | |
6779 | phy_encode(PORT_TYPE_1G, 1) | | |
6780 | phy_encode(PORT_TYPE_1G, 2) | | |
6781 | phy_encode(PORT_TYPE_1G, 3)); | |
6782 | else | |
6783 | val = (phy_encode(PORT_TYPE_1G, 0) | | |
6784 | phy_encode(PORT_TYPE_10G, 1) | | |
6785 | phy_encode(PORT_TYPE_1G, 2) | | |
6786 | phy_encode(PORT_TYPE_1G, 3)); | |
6787 | break; | |
6788 | ||
6789 | case 0x04: | |
6790 | if (lowest_1g == 10) | |
6791 | parent->plat_type = PLAT_TYPE_VF_P0; | |
6792 | else if (lowest_1g == 26) | |
6793 | parent->plat_type = PLAT_TYPE_VF_P1; | |
6794 | else | |
6795 | goto unknown_vg_1g_port; | |
6796 | ||
6797 | val = (phy_encode(PORT_TYPE_1G, 0) | | |
6798 | phy_encode(PORT_TYPE_1G, 1) | | |
6799 | phy_encode(PORT_TYPE_1G, 2) | | |
6800 | phy_encode(PORT_TYPE_1G, 3)); | |
6801 | break; | |
6802 | ||
6803 | default: | |
6804 | printk(KERN_ERR PFX "Unsupported port config " | |
6805 | "10G[%d] 1G[%d]\n", | |
6806 | num_10g, num_1g); | |
6807 | return -EINVAL; | |
6808 | } | |
6809 | ||
6810 | parent->port_phy = val; | |
6811 | ||
6812 | if (parent->plat_type == PLAT_TYPE_NIU) | |
6813 | niu_n2_divide_channels(parent); | |
6814 | else | |
6815 | niu_divide_channels(parent, num_10g, num_1g); | |
6816 | ||
6817 | niu_divide_rdc_groups(parent, num_10g, num_1g); | |
6818 | ||
6819 | return 0; | |
6820 | ||
6821 | unknown_vg_1g_port: | |
6822 | printk(KERN_ERR PFX "Cannot identify platform type, 1gport=%d\n", | |
6823 | lowest_1g); | |
6824 | return -EINVAL; | |
6825 | } | |
6826 | ||
6827 | static int __devinit niu_probe_ports(struct niu *np) | |
6828 | { | |
6829 | struct niu_parent *parent = np->parent; | |
6830 | int err, i; | |
6831 | ||
6832 | niudbg(PROBE, "niu_probe_ports(): port_phy[%08x]\n", | |
6833 | parent->port_phy); | |
6834 | ||
6835 | if (parent->port_phy == PORT_PHY_UNKNOWN) { | |
6836 | err = walk_phys(np, parent); | |
6837 | if (err) | |
6838 | return err; | |
6839 | ||
6840 | niu_set_ldg_timer_res(np, 2); | |
6841 | for (i = 0; i <= LDN_MAX; i++) | |
6842 | niu_ldn_irq_enable(np, i, 0); | |
6843 | } | |
6844 | ||
6845 | if (parent->port_phy == PORT_PHY_INVALID) | |
6846 | return -EINVAL; | |
6847 | ||
6848 | return 0; | |
6849 | } | |
6850 | ||
6851 | static int __devinit niu_classifier_swstate_init(struct niu *np) | |
6852 | { | |
6853 | struct niu_classifier *cp = &np->clas; | |
6854 | ||
6855 | niudbg(PROBE, "niu_classifier_swstate_init: num_tcam(%d)\n", | |
6856 | np->parent->tcam_num_entries); | |
6857 | ||
6858 | cp->tcam_index = (u16) np->port; | |
6859 | cp->h1_init = 0xffffffff; | |
6860 | cp->h2_init = 0xffff; | |
6861 | ||
6862 | return fflp_early_init(np); | |
6863 | } | |
6864 | ||
6865 | static void __devinit niu_link_config_init(struct niu *np) | |
6866 | { | |
6867 | struct niu_link_config *lp = &np->link_config; | |
6868 | ||
6869 | lp->advertising = (ADVERTISED_10baseT_Half | | |
6870 | ADVERTISED_10baseT_Full | | |
6871 | ADVERTISED_100baseT_Half | | |
6872 | ADVERTISED_100baseT_Full | | |
6873 | ADVERTISED_1000baseT_Half | | |
6874 | ADVERTISED_1000baseT_Full | | |
6875 | ADVERTISED_10000baseT_Full | | |
6876 | ADVERTISED_Autoneg); | |
6877 | lp->speed = lp->active_speed = SPEED_INVALID; | |
6878 | lp->duplex = lp->active_duplex = DUPLEX_INVALID; | |
6879 | #if 0 | |
6880 | lp->loopback_mode = LOOPBACK_MAC; | |
6881 | lp->active_speed = SPEED_10000; | |
6882 | lp->active_duplex = DUPLEX_FULL; | |
6883 | #else | |
6884 | lp->loopback_mode = LOOPBACK_DISABLED; | |
6885 | #endif | |
6886 | } | |
6887 | ||
6888 | static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np) | |
6889 | { | |
6890 | switch (np->port) { | |
6891 | case 0: | |
6892 | np->mac_regs = np->regs + XMAC_PORT0_OFF; | |
6893 | np->ipp_off = 0x00000; | |
6894 | np->pcs_off = 0x04000; | |
6895 | np->xpcs_off = 0x02000; | |
6896 | break; | |
6897 | ||
6898 | case 1: | |
6899 | np->mac_regs = np->regs + XMAC_PORT1_OFF; | |
6900 | np->ipp_off = 0x08000; | |
6901 | np->pcs_off = 0x0a000; | |
6902 | np->xpcs_off = 0x08000; | |
6903 | break; | |
6904 | ||
6905 | case 2: | |
6906 | np->mac_regs = np->regs + BMAC_PORT2_OFF; | |
6907 | np->ipp_off = 0x04000; | |
6908 | np->pcs_off = 0x0e000; | |
6909 | np->xpcs_off = ~0UL; | |
6910 | break; | |
6911 | ||
6912 | case 3: | |
6913 | np->mac_regs = np->regs + BMAC_PORT3_OFF; | |
6914 | np->ipp_off = 0x0c000; | |
6915 | np->pcs_off = 0x12000; | |
6916 | np->xpcs_off = ~0UL; | |
6917 | break; | |
6918 | ||
6919 | default: | |
6920 | dev_err(np->device, PFX "Port %u is invalid, cannot " | |
6921 | "compute MAC block offset.\n", np->port); | |
6922 | return -EINVAL; | |
6923 | } | |
6924 | ||
6925 | return 0; | |
6926 | } | |
6927 | ||
6928 | static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map) | |
6929 | { | |
6930 | struct msix_entry msi_vec[NIU_NUM_LDG]; | |
6931 | struct niu_parent *parent = np->parent; | |
6932 | struct pci_dev *pdev = np->pdev; | |
6933 | int i, num_irqs, err; | |
6934 | u8 first_ldg; | |
6935 | ||
6936 | first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port; | |
6937 | for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++) | |
6938 | ldg_num_map[i] = first_ldg + i; | |
6939 | ||
6940 | num_irqs = (parent->rxchan_per_port[np->port] + | |
6941 | parent->txchan_per_port[np->port] + | |
6942 | (np->port == 0 ? 3 : 1)); | |
6943 | BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports)); | |
6944 | ||
6945 | retry: | |
6946 | for (i = 0; i < num_irqs; i++) { | |
6947 | msi_vec[i].vector = 0; | |
6948 | msi_vec[i].entry = i; | |
6949 | } | |
6950 | ||
6951 | err = pci_enable_msix(pdev, msi_vec, num_irqs); | |
6952 | if (err < 0) { | |
6953 | np->flags &= ~NIU_FLAGS_MSIX; | |
6954 | return; | |
6955 | } | |
6956 | if (err > 0) { | |
6957 | num_irqs = err; | |
6958 | goto retry; | |
6959 | } | |
6960 | ||
6961 | np->flags |= NIU_FLAGS_MSIX; | |
6962 | for (i = 0; i < num_irqs; i++) | |
6963 | np->ldg[i].irq = msi_vec[i].vector; | |
6964 | np->num_ldg = num_irqs; | |
6965 | } | |
6966 | ||
6967 | static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map) | |
6968 | { | |
6969 | #ifdef CONFIG_SPARC64 | |
6970 | struct of_device *op = np->op; | |
6971 | const u32 *int_prop; | |
6972 | int i; | |
6973 | ||
6974 | int_prop = of_get_property(op->node, "interrupts", NULL); | |
6975 | if (!int_prop) | |
6976 | return -ENODEV; | |
6977 | ||
6978 | for (i = 0; i < op->num_irqs; i++) { | |
6979 | ldg_num_map[i] = int_prop[i]; | |
6980 | np->ldg[i].irq = op->irqs[i]; | |
6981 | } | |
6982 | ||
6983 | np->num_ldg = op->num_irqs; | |
6984 | ||
6985 | return 0; | |
6986 | #else | |
6987 | return -EINVAL; | |
6988 | #endif | |
6989 | } | |
6990 | ||
6991 | static int __devinit niu_ldg_init(struct niu *np) | |
6992 | { | |
6993 | struct niu_parent *parent = np->parent; | |
6994 | u8 ldg_num_map[NIU_NUM_LDG]; | |
6995 | int first_chan, num_chan; | |
6996 | int i, err, ldg_rotor; | |
6997 | u8 port; | |
6998 | ||
6999 | np->num_ldg = 1; | |
7000 | np->ldg[0].irq = np->dev->irq; | |
7001 | if (parent->plat_type == PLAT_TYPE_NIU) { | |
7002 | err = niu_n2_irq_init(np, ldg_num_map); | |
7003 | if (err) | |
7004 | return err; | |
7005 | } else | |
7006 | niu_try_msix(np, ldg_num_map); | |
7007 | ||
7008 | port = np->port; | |
7009 | for (i = 0; i < np->num_ldg; i++) { | |
7010 | struct niu_ldg *lp = &np->ldg[i]; | |
7011 | ||
7012 | netif_napi_add(np->dev, &lp->napi, niu_poll, 64); | |
7013 | ||
7014 | lp->np = np; | |
7015 | lp->ldg_num = ldg_num_map[i]; | |
7016 | lp->timer = 2; /* XXX */ | |
7017 | ||
7018 | /* On N2 NIU the firmware has setup the SID mappings so they go | |
7019 | * to the correct values that will route the LDG to the proper | |
7020 | * interrupt in the NCU interrupt table. | |
7021 | */ | |
7022 | if (np->parent->plat_type != PLAT_TYPE_NIU) { | |
7023 | err = niu_set_ldg_sid(np, lp->ldg_num, port, i); | |
7024 | if (err) | |
7025 | return err; | |
7026 | } | |
7027 | } | |
7028 | ||
7029 | /* We adopt the LDG assignment ordering used by the N2 NIU | |
7030 | * 'interrupt' properties because that simplifies a lot of | |
7031 | * things. This ordering is: | |
7032 | * | |
7033 | * MAC | |
7034 | * MIF (if port zero) | |
7035 | * SYSERR (if port zero) | |
7036 | * RX channels | |
7037 | * TX channels | |
7038 | */ | |
7039 | ||
7040 | ldg_rotor = 0; | |
7041 | ||
7042 | err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor], | |
7043 | LDN_MAC(port)); | |
7044 | if (err) | |
7045 | return err; | |
7046 | ||
7047 | ldg_rotor++; | |
7048 | if (ldg_rotor == np->num_ldg) | |
7049 | ldg_rotor = 0; | |
7050 | ||
7051 | if (port == 0) { | |
7052 | err = niu_ldg_assign_ldn(np, parent, | |
7053 | ldg_num_map[ldg_rotor], | |
7054 | LDN_MIF); | |
7055 | if (err) | |
7056 | return err; | |
7057 | ||
7058 | ldg_rotor++; | |
7059 | if (ldg_rotor == np->num_ldg) | |
7060 | ldg_rotor = 0; | |
7061 | ||
7062 | err = niu_ldg_assign_ldn(np, parent, | |
7063 | ldg_num_map[ldg_rotor], | |
7064 | LDN_DEVICE_ERROR); | |
7065 | if (err) | |
7066 | return err; | |
7067 | ||
7068 | ldg_rotor++; | |
7069 | if (ldg_rotor == np->num_ldg) | |
7070 | ldg_rotor = 0; | |
7071 | ||
7072 | } | |
7073 | ||
7074 | first_chan = 0; | |
7075 | for (i = 0; i < port; i++) | |
7076 | first_chan += parent->rxchan_per_port[port]; | |
7077 | num_chan = parent->rxchan_per_port[port]; | |
7078 | ||
7079 | for (i = first_chan; i < (first_chan + num_chan); i++) { | |
7080 | err = niu_ldg_assign_ldn(np, parent, | |
7081 | ldg_num_map[ldg_rotor], | |
7082 | LDN_RXDMA(i)); | |
7083 | if (err) | |
7084 | return err; | |
7085 | ldg_rotor++; | |
7086 | if (ldg_rotor == np->num_ldg) | |
7087 | ldg_rotor = 0; | |
7088 | } | |
7089 | ||
7090 | first_chan = 0; | |
7091 | for (i = 0; i < port; i++) | |
7092 | first_chan += parent->txchan_per_port[port]; | |
7093 | num_chan = parent->txchan_per_port[port]; | |
7094 | for (i = first_chan; i < (first_chan + num_chan); i++) { | |
7095 | err = niu_ldg_assign_ldn(np, parent, | |
7096 | ldg_num_map[ldg_rotor], | |
7097 | LDN_TXDMA(i)); | |
7098 | if (err) | |
7099 | return err; | |
7100 | ldg_rotor++; | |
7101 | if (ldg_rotor == np->num_ldg) | |
7102 | ldg_rotor = 0; | |
7103 | } | |
7104 | ||
7105 | return 0; | |
7106 | } | |
7107 | ||
7108 | static void __devexit niu_ldg_free(struct niu *np) | |
7109 | { | |
7110 | if (np->flags & NIU_FLAGS_MSIX) | |
7111 | pci_disable_msix(np->pdev); | |
7112 | } | |
7113 | ||
7114 | static int __devinit niu_get_of_props(struct niu *np) | |
7115 | { | |
7116 | #ifdef CONFIG_SPARC64 | |
7117 | struct net_device *dev = np->dev; | |
7118 | struct device_node *dp; | |
7119 | const char *phy_type; | |
7120 | const u8 *mac_addr; | |
7121 | int prop_len; | |
7122 | ||
7123 | if (np->parent->plat_type == PLAT_TYPE_NIU) | |
7124 | dp = np->op->node; | |
7125 | else | |
7126 | dp = pci_device_to_OF_node(np->pdev); | |
7127 | ||
7128 | phy_type = of_get_property(dp, "phy-type", &prop_len); | |
7129 | if (!phy_type) { | |
7130 | dev_err(np->device, PFX "%s: OF node lacks " | |
7131 | "phy-type property\n", | |
7132 | dp->full_name); | |
7133 | return -EINVAL; | |
7134 | } | |
7135 | ||
7136 | if (!strcmp(phy_type, "none")) | |
7137 | return -ENODEV; | |
7138 | ||
7139 | strcpy(np->vpd.phy_type, phy_type); | |
7140 | ||
7141 | if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) { | |
7142 | dev_err(np->device, PFX "%s: Illegal phy string [%s].\n", | |
7143 | dp->full_name, np->vpd.phy_type); | |
7144 | return -EINVAL; | |
7145 | } | |
7146 | ||
7147 | mac_addr = of_get_property(dp, "local-mac-address", &prop_len); | |
7148 | if (!mac_addr) { | |
7149 | dev_err(np->device, PFX "%s: OF node lacks " | |
7150 | "local-mac-address property\n", | |
7151 | dp->full_name); | |
7152 | return -EINVAL; | |
7153 | } | |
7154 | if (prop_len != dev->addr_len) { | |
7155 | dev_err(np->device, PFX "%s: OF MAC address prop len (%d) " | |
7156 | "is wrong.\n", | |
7157 | dp->full_name, prop_len); | |
7158 | } | |
7159 | memcpy(dev->perm_addr, mac_addr, dev->addr_len); | |
7160 | if (!is_valid_ether_addr(&dev->perm_addr[0])) { | |
7161 | int i; | |
7162 | ||
7163 | dev_err(np->device, PFX "%s: OF MAC address is invalid\n", | |
7164 | dp->full_name); | |
7165 | dev_err(np->device, PFX "%s: [ \n", | |
7166 | dp->full_name); | |
7167 | for (i = 0; i < 6; i++) | |
7168 | printk("%02x ", dev->perm_addr[i]); | |
7169 | printk("]\n"); | |
7170 | return -EINVAL; | |
7171 | } | |
7172 | ||
7173 | memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len); | |
7174 | ||
7175 | return 0; | |
7176 | #else | |
7177 | return -EINVAL; | |
7178 | #endif | |
7179 | } | |
7180 | ||
7181 | static int __devinit niu_get_invariants(struct niu *np) | |
7182 | { | |
7183 | int err, have_props; | |
7184 | u32 offset; | |
7185 | ||
7186 | err = niu_get_of_props(np); | |
7187 | if (err == -ENODEV) | |
7188 | return err; | |
7189 | ||
7190 | have_props = !err; | |
7191 | ||
7192 | err = niu_get_and_validate_port(np); | |
7193 | if (err) | |
7194 | return err; | |
7195 | ||
7196 | err = niu_init_mac_ipp_pcs_base(np); | |
7197 | if (err) | |
7198 | return err; | |
7199 | ||
7200 | if (!have_props) { | |
7201 | if (np->parent->plat_type == PLAT_TYPE_NIU) | |
7202 | return -EINVAL; | |
7203 | ||
7204 | nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE); | |
7205 | offset = niu_pci_vpd_offset(np); | |
7206 | niudbg(PROBE, "niu_get_invariants: VPD offset [%08x]\n", | |
7207 | offset); | |
7208 | if (offset) | |
7209 | niu_pci_vpd_fetch(np, offset); | |
7210 | nw64(ESPC_PIO_EN, 0); | |
7211 | ||
7212 | if (np->flags & NIU_FLAGS_VPD_VALID) | |
7213 | niu_pci_vpd_validate(np); | |
7214 | ||
7215 | if (!(np->flags & NIU_FLAGS_VPD_VALID)) { | |
7216 | err = niu_pci_probe_sprom(np); | |
7217 | if (err) | |
7218 | return err; | |
7219 | } | |
7220 | } | |
7221 | ||
7222 | err = niu_probe_ports(np); | |
7223 | if (err) | |
7224 | return err; | |
7225 | ||
7226 | niu_ldg_init(np); | |
7227 | ||
7228 | niu_classifier_swstate_init(np); | |
7229 | niu_link_config_init(np); | |
7230 | ||
7231 | err = niu_determine_phy_disposition(np); | |
7232 | if (!err) | |
7233 | err = niu_init_link(np); | |
7234 | ||
7235 | return err; | |
7236 | } | |
7237 | ||
7238 | static LIST_HEAD(niu_parent_list); | |
7239 | static DEFINE_MUTEX(niu_parent_lock); | |
7240 | static int niu_parent_index; | |
7241 | ||
7242 | static ssize_t show_port_phy(struct device *dev, | |
7243 | struct device_attribute *attr, char *buf) | |
7244 | { | |
7245 | struct platform_device *plat_dev = to_platform_device(dev); | |
7246 | struct niu_parent *p = plat_dev->dev.platform_data; | |
7247 | u32 port_phy = p->port_phy; | |
7248 | char *orig_buf = buf; | |
7249 | int i; | |
7250 | ||
7251 | if (port_phy == PORT_PHY_UNKNOWN || | |
7252 | port_phy == PORT_PHY_INVALID) | |
7253 | return 0; | |
7254 | ||
7255 | for (i = 0; i < p->num_ports; i++) { | |
7256 | const char *type_str; | |
7257 | int type; | |
7258 | ||
7259 | type = phy_decode(port_phy, i); | |
7260 | if (type == PORT_TYPE_10G) | |
7261 | type_str = "10G"; | |
7262 | else | |
7263 | type_str = "1G"; | |
7264 | buf += sprintf(buf, | |
7265 | (i == 0) ? "%s" : " %s", | |
7266 | type_str); | |
7267 | } | |
7268 | buf += sprintf(buf, "\n"); | |
7269 | return buf - orig_buf; | |
7270 | } | |
7271 | ||
7272 | static ssize_t show_plat_type(struct device *dev, | |
7273 | struct device_attribute *attr, char *buf) | |
7274 | { | |
7275 | struct platform_device *plat_dev = to_platform_device(dev); | |
7276 | struct niu_parent *p = plat_dev->dev.platform_data; | |
7277 | const char *type_str; | |
7278 | ||
7279 | switch (p->plat_type) { | |
7280 | case PLAT_TYPE_ATLAS: | |
7281 | type_str = "atlas"; | |
7282 | break; | |
7283 | case PLAT_TYPE_NIU: | |
7284 | type_str = "niu"; | |
7285 | break; | |
7286 | case PLAT_TYPE_VF_P0: | |
7287 | type_str = "vf_p0"; | |
7288 | break; | |
7289 | case PLAT_TYPE_VF_P1: | |
7290 | type_str = "vf_p1"; | |
7291 | break; | |
7292 | default: | |
7293 | type_str = "unknown"; | |
7294 | break; | |
7295 | } | |
7296 | ||
7297 | return sprintf(buf, "%s\n", type_str); | |
7298 | } | |
7299 | ||
7300 | static ssize_t __show_chan_per_port(struct device *dev, | |
7301 | struct device_attribute *attr, char *buf, | |
7302 | int rx) | |
7303 | { | |
7304 | struct platform_device *plat_dev = to_platform_device(dev); | |
7305 | struct niu_parent *p = plat_dev->dev.platform_data; | |
7306 | char *orig_buf = buf; | |
7307 | u8 *arr; | |
7308 | int i; | |
7309 | ||
7310 | arr = (rx ? p->rxchan_per_port : p->txchan_per_port); | |
7311 | ||
7312 | for (i = 0; i < p->num_ports; i++) { | |
7313 | buf += sprintf(buf, | |
7314 | (i == 0) ? "%d" : " %d", | |
7315 | arr[i]); | |
7316 | } | |
7317 | buf += sprintf(buf, "\n"); | |
7318 | ||
7319 | return buf - orig_buf; | |
7320 | } | |
7321 | ||
7322 | static ssize_t show_rxchan_per_port(struct device *dev, | |
7323 | struct device_attribute *attr, char *buf) | |
7324 | { | |
7325 | return __show_chan_per_port(dev, attr, buf, 1); | |
7326 | } | |
7327 | ||
7328 | static ssize_t show_txchan_per_port(struct device *dev, | |
7329 | struct device_attribute *attr, char *buf) | |
7330 | { | |
7331 | return __show_chan_per_port(dev, attr, buf, 1); | |
7332 | } | |
7333 | ||
7334 | static ssize_t show_num_ports(struct device *dev, | |
7335 | struct device_attribute *attr, char *buf) | |
7336 | { | |
7337 | struct platform_device *plat_dev = to_platform_device(dev); | |
7338 | struct niu_parent *p = plat_dev->dev.platform_data; | |
7339 | ||
7340 | return sprintf(buf, "%d\n", p->num_ports); | |
7341 | } | |
7342 | ||
7343 | static struct device_attribute niu_parent_attributes[] = { | |
7344 | __ATTR(port_phy, S_IRUGO, show_port_phy, NULL), | |
7345 | __ATTR(plat_type, S_IRUGO, show_plat_type, NULL), | |
7346 | __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL), | |
7347 | __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL), | |
7348 | __ATTR(num_ports, S_IRUGO, show_num_ports, NULL), | |
7349 | {} | |
7350 | }; | |
7351 | ||
7352 | static struct niu_parent * __devinit niu_new_parent(struct niu *np, | |
7353 | union niu_parent_id *id, | |
7354 | u8 ptype) | |
7355 | { | |
7356 | struct platform_device *plat_dev; | |
7357 | struct niu_parent *p; | |
7358 | int i; | |
7359 | ||
7360 | niudbg(PROBE, "niu_new_parent: Creating new parent.\n"); | |
7361 | ||
7362 | plat_dev = platform_device_register_simple("niu", niu_parent_index, | |
7363 | NULL, 0); | |
7364 | if (!plat_dev) | |
7365 | return NULL; | |
7366 | ||
7367 | for (i = 0; attr_name(niu_parent_attributes[i]); i++) { | |
7368 | int err = device_create_file(&plat_dev->dev, | |
7369 | &niu_parent_attributes[i]); | |
7370 | if (err) | |
7371 | goto fail_unregister; | |
7372 | } | |
7373 | ||
7374 | p = kzalloc(sizeof(*p), GFP_KERNEL); | |
7375 | if (!p) | |
7376 | goto fail_unregister; | |
7377 | ||
7378 | p->index = niu_parent_index++; | |
7379 | ||
7380 | plat_dev->dev.platform_data = p; | |
7381 | p->plat_dev = plat_dev; | |
7382 | ||
7383 | memcpy(&p->id, id, sizeof(*id)); | |
7384 | p->plat_type = ptype; | |
7385 | INIT_LIST_HEAD(&p->list); | |
7386 | atomic_set(&p->refcnt, 0); | |
7387 | list_add(&p->list, &niu_parent_list); | |
7388 | spin_lock_init(&p->lock); | |
7389 | ||
7390 | p->rxdma_clock_divider = 7500; | |
7391 | ||
7392 | p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES; | |
7393 | if (p->plat_type == PLAT_TYPE_NIU) | |
7394 | p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES; | |
7395 | ||
7396 | for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) { | |
7397 | int index = i - CLASS_CODE_USER_PROG1; | |
7398 | ||
7399 | p->tcam_key[index] = TCAM_KEY_TSEL; | |
7400 | p->flow_key[index] = (FLOW_KEY_IPSA | | |
7401 | FLOW_KEY_IPDA | | |
7402 | FLOW_KEY_PROTO | | |
7403 | (FLOW_KEY_L4_BYTE12 << | |
7404 | FLOW_KEY_L4_0_SHIFT) | | |
7405 | (FLOW_KEY_L4_BYTE12 << | |
7406 | FLOW_KEY_L4_1_SHIFT)); | |
7407 | } | |
7408 | ||
7409 | for (i = 0; i < LDN_MAX + 1; i++) | |
7410 | p->ldg_map[i] = LDG_INVALID; | |
7411 | ||
7412 | return p; | |
7413 | ||
7414 | fail_unregister: | |
7415 | platform_device_unregister(plat_dev); | |
7416 | return NULL; | |
7417 | } | |
7418 | ||
7419 | static struct niu_parent * __devinit niu_get_parent(struct niu *np, | |
7420 | union niu_parent_id *id, | |
7421 | u8 ptype) | |
7422 | { | |
7423 | struct niu_parent *p, *tmp; | |
7424 | int port = np->port; | |
7425 | ||
7426 | niudbg(PROBE, "niu_get_parent: platform_type[%u] port[%u]\n", | |
7427 | ptype, port); | |
7428 | ||
7429 | mutex_lock(&niu_parent_lock); | |
7430 | p = NULL; | |
7431 | list_for_each_entry(tmp, &niu_parent_list, list) { | |
7432 | if (!memcmp(id, &tmp->id, sizeof(*id))) { | |
7433 | p = tmp; | |
7434 | break; | |
7435 | } | |
7436 | } | |
7437 | if (!p) | |
7438 | p = niu_new_parent(np, id, ptype); | |
7439 | ||
7440 | if (p) { | |
7441 | char port_name[6]; | |
7442 | int err; | |
7443 | ||
7444 | sprintf(port_name, "port%d", port); | |
7445 | err = sysfs_create_link(&p->plat_dev->dev.kobj, | |
7446 | &np->device->kobj, | |
7447 | port_name); | |
7448 | if (!err) { | |
7449 | p->ports[port] = np; | |
7450 | atomic_inc(&p->refcnt); | |
7451 | } | |
7452 | } | |
7453 | mutex_unlock(&niu_parent_lock); | |
7454 | ||
7455 | return p; | |
7456 | } | |
7457 | ||
7458 | static void niu_put_parent(struct niu *np) | |
7459 | { | |
7460 | struct niu_parent *p = np->parent; | |
7461 | u8 port = np->port; | |
7462 | char port_name[6]; | |
7463 | ||
7464 | BUG_ON(!p || p->ports[port] != np); | |
7465 | ||
7466 | niudbg(PROBE, "niu_put_parent: port[%u]\n", port); | |
7467 | ||
7468 | sprintf(port_name, "port%d", port); | |
7469 | ||
7470 | mutex_lock(&niu_parent_lock); | |
7471 | ||
7472 | sysfs_remove_link(&p->plat_dev->dev.kobj, port_name); | |
7473 | ||
7474 | p->ports[port] = NULL; | |
7475 | np->parent = NULL; | |
7476 | ||
7477 | if (atomic_dec_and_test(&p->refcnt)) { | |
7478 | list_del(&p->list); | |
7479 | platform_device_unregister(p->plat_dev); | |
7480 | } | |
7481 | ||
7482 | mutex_unlock(&niu_parent_lock); | |
7483 | } | |
7484 | ||
7485 | static void *niu_pci_alloc_coherent(struct device *dev, size_t size, | |
7486 | u64 *handle, gfp_t flag) | |
7487 | { | |
7488 | dma_addr_t dh; | |
7489 | void *ret; | |
7490 | ||
7491 | ret = dma_alloc_coherent(dev, size, &dh, flag); | |
7492 | if (ret) | |
7493 | *handle = dh; | |
7494 | return ret; | |
7495 | } | |
7496 | ||
7497 | static void niu_pci_free_coherent(struct device *dev, size_t size, | |
7498 | void *cpu_addr, u64 handle) | |
7499 | { | |
7500 | dma_free_coherent(dev, size, cpu_addr, handle); | |
7501 | } | |
7502 | ||
7503 | static u64 niu_pci_map_page(struct device *dev, struct page *page, | |
7504 | unsigned long offset, size_t size, | |
7505 | enum dma_data_direction direction) | |
7506 | { | |
7507 | return dma_map_page(dev, page, offset, size, direction); | |
7508 | } | |
7509 | ||
7510 | static void niu_pci_unmap_page(struct device *dev, u64 dma_address, | |
7511 | size_t size, enum dma_data_direction direction) | |
7512 | { | |
7513 | return dma_unmap_page(dev, dma_address, size, direction); | |
7514 | } | |
7515 | ||
7516 | static u64 niu_pci_map_single(struct device *dev, void *cpu_addr, | |
7517 | size_t size, | |
7518 | enum dma_data_direction direction) | |
7519 | { | |
7520 | return dma_map_single(dev, cpu_addr, size, direction); | |
7521 | } | |
7522 | ||
7523 | static void niu_pci_unmap_single(struct device *dev, u64 dma_address, | |
7524 | size_t size, | |
7525 | enum dma_data_direction direction) | |
7526 | { | |
7527 | dma_unmap_single(dev, dma_address, size, direction); | |
7528 | } | |
7529 | ||
7530 | static const struct niu_ops niu_pci_ops = { | |
7531 | .alloc_coherent = niu_pci_alloc_coherent, | |
7532 | .free_coherent = niu_pci_free_coherent, | |
7533 | .map_page = niu_pci_map_page, | |
7534 | .unmap_page = niu_pci_unmap_page, | |
7535 | .map_single = niu_pci_map_single, | |
7536 | .unmap_single = niu_pci_unmap_single, | |
7537 | }; | |
7538 | ||
7539 | static void __devinit niu_driver_version(void) | |
7540 | { | |
7541 | static int niu_version_printed; | |
7542 | ||
7543 | if (niu_version_printed++ == 0) | |
7544 | pr_info("%s", version); | |
7545 | } | |
7546 | ||
7547 | static struct net_device * __devinit niu_alloc_and_init( | |
7548 | struct device *gen_dev, struct pci_dev *pdev, | |
7549 | struct of_device *op, const struct niu_ops *ops, | |
7550 | u8 port) | |
7551 | { | |
7552 | struct net_device *dev = alloc_etherdev(sizeof(struct niu)); | |
7553 | struct niu *np; | |
7554 | ||
7555 | if (!dev) { | |
7556 | dev_err(gen_dev, PFX "Etherdev alloc failed, aborting.\n"); | |
7557 | return NULL; | |
7558 | } | |
7559 | ||
7560 | SET_NETDEV_DEV(dev, gen_dev); | |
7561 | ||
7562 | np = netdev_priv(dev); | |
7563 | np->dev = dev; | |
7564 | np->pdev = pdev; | |
7565 | np->op = op; | |
7566 | np->device = gen_dev; | |
7567 | np->ops = ops; | |
7568 | ||
7569 | np->msg_enable = niu_debug; | |
7570 | ||
7571 | spin_lock_init(&np->lock); | |
7572 | INIT_WORK(&np->reset_task, niu_reset_task); | |
7573 | ||
7574 | np->port = port; | |
7575 | ||
7576 | return dev; | |
7577 | } | |
7578 | ||
7579 | static void __devinit niu_assign_netdev_ops(struct net_device *dev) | |
7580 | { | |
7581 | dev->open = niu_open; | |
7582 | dev->stop = niu_close; | |
7583 | dev->get_stats = niu_get_stats; | |
7584 | dev->set_multicast_list = niu_set_rx_mode; | |
7585 | dev->set_mac_address = niu_set_mac_addr; | |
7586 | dev->do_ioctl = niu_ioctl; | |
7587 | dev->tx_timeout = niu_tx_timeout; | |
7588 | dev->hard_start_xmit = niu_start_xmit; | |
7589 | dev->ethtool_ops = &niu_ethtool_ops; | |
7590 | dev->watchdog_timeo = NIU_TX_TIMEOUT; | |
7591 | dev->change_mtu = niu_change_mtu; | |
7592 | } | |
7593 | ||
7594 | static void __devinit niu_device_announce(struct niu *np) | |
7595 | { | |
7596 | struct net_device *dev = np->dev; | |
2caf62f6 | 7597 | DECLARE_MAC_BUF(mac); |
a3138df9 | 7598 | |
2caf62f6 JP |
7599 | pr_info("%s: NIU Ethernet %s\n", |
7600 | dev->name, print_mac(mac, dev->dev_addr)); | |
a3138df9 DM |
7601 | |
7602 | pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n", | |
7603 | dev->name, | |
7604 | (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"), | |
7605 | (np->flags & NIU_FLAGS_10G ? "10G" : "1G"), | |
7606 | (np->flags & NIU_FLAGS_FIBER ? "FIBER" : "COPPER"), | |
7607 | (np->mac_xcvr == MAC_XCVR_MII ? "MII" : | |
7608 | (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")), | |
7609 | np->vpd.phy_type); | |
7610 | } | |
7611 | ||
7612 | static int __devinit niu_pci_init_one(struct pci_dev *pdev, | |
7613 | const struct pci_device_id *ent) | |
7614 | { | |
7615 | unsigned long niureg_base, niureg_len; | |
7616 | union niu_parent_id parent_id; | |
7617 | struct net_device *dev; | |
7618 | struct niu *np; | |
7619 | int err, pos; | |
7620 | u64 dma_mask; | |
7621 | u16 val16; | |
7622 | ||
7623 | niu_driver_version(); | |
7624 | ||
7625 | err = pci_enable_device(pdev); | |
7626 | if (err) { | |
7627 | dev_err(&pdev->dev, PFX "Cannot enable PCI device, " | |
7628 | "aborting.\n"); | |
7629 | return err; | |
7630 | } | |
7631 | ||
7632 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) || | |
7633 | !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { | |
7634 | dev_err(&pdev->dev, PFX "Cannot find proper PCI device " | |
7635 | "base addresses, aborting.\n"); | |
7636 | err = -ENODEV; | |
7637 | goto err_out_disable_pdev; | |
7638 | } | |
7639 | ||
7640 | err = pci_request_regions(pdev, DRV_MODULE_NAME); | |
7641 | if (err) { | |
7642 | dev_err(&pdev->dev, PFX "Cannot obtain PCI resources, " | |
7643 | "aborting.\n"); | |
7644 | goto err_out_disable_pdev; | |
7645 | } | |
7646 | ||
7647 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
7648 | if (pos <= 0) { | |
7649 | dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, " | |
7650 | "aborting.\n"); | |
7651 | goto err_out_free_res; | |
7652 | } | |
7653 | ||
7654 | dev = niu_alloc_and_init(&pdev->dev, pdev, NULL, | |
7655 | &niu_pci_ops, PCI_FUNC(pdev->devfn)); | |
7656 | if (!dev) { | |
7657 | err = -ENOMEM; | |
7658 | goto err_out_free_res; | |
7659 | } | |
7660 | np = netdev_priv(dev); | |
7661 | ||
7662 | memset(&parent_id, 0, sizeof(parent_id)); | |
7663 | parent_id.pci.domain = pci_domain_nr(pdev->bus); | |
7664 | parent_id.pci.bus = pdev->bus->number; | |
7665 | parent_id.pci.device = PCI_SLOT(pdev->devfn); | |
7666 | ||
7667 | np->parent = niu_get_parent(np, &parent_id, | |
7668 | PLAT_TYPE_ATLAS); | |
7669 | if (!np->parent) { | |
7670 | err = -ENOMEM; | |
7671 | goto err_out_free_dev; | |
7672 | } | |
7673 | ||
7674 | pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16); | |
7675 | val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; | |
7676 | val16 |= (PCI_EXP_DEVCTL_CERE | | |
7677 | PCI_EXP_DEVCTL_NFERE | | |
7678 | PCI_EXP_DEVCTL_FERE | | |
7679 | PCI_EXP_DEVCTL_URRE | | |
7680 | PCI_EXP_DEVCTL_RELAX_EN); | |
7681 | pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16); | |
7682 | ||
7683 | dma_mask = DMA_44BIT_MASK; | |
7684 | err = pci_set_dma_mask(pdev, dma_mask); | |
7685 | if (!err) { | |
7686 | dev->features |= NETIF_F_HIGHDMA; | |
7687 | err = pci_set_consistent_dma_mask(pdev, dma_mask); | |
7688 | if (err) { | |
7689 | dev_err(&pdev->dev, PFX "Unable to obtain 44 bit " | |
7690 | "DMA for consistent allocations, " | |
7691 | "aborting.\n"); | |
7692 | goto err_out_release_parent; | |
7693 | } | |
7694 | } | |
7695 | if (err || dma_mask == DMA_32BIT_MASK) { | |
7696 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
7697 | if (err) { | |
7698 | dev_err(&pdev->dev, PFX "No usable DMA configuration, " | |
7699 | "aborting.\n"); | |
7700 | goto err_out_release_parent; | |
7701 | } | |
7702 | } | |
7703 | ||
7704 | dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM); | |
7705 | ||
7706 | niureg_base = pci_resource_start(pdev, 0); | |
7707 | niureg_len = pci_resource_len(pdev, 0); | |
7708 | ||
7709 | np->regs = ioremap_nocache(niureg_base, niureg_len); | |
7710 | if (!np->regs) { | |
7711 | dev_err(&pdev->dev, PFX "Cannot map device registers, " | |
7712 | "aborting.\n"); | |
7713 | err = -ENOMEM; | |
7714 | goto err_out_release_parent; | |
7715 | } | |
7716 | ||
7717 | pci_set_master(pdev); | |
7718 | pci_save_state(pdev); | |
7719 | ||
7720 | dev->irq = pdev->irq; | |
7721 | ||
7722 | niu_assign_netdev_ops(dev); | |
7723 | ||
7724 | err = niu_get_invariants(np); | |
7725 | if (err) { | |
7726 | if (err != -ENODEV) | |
7727 | dev_err(&pdev->dev, PFX "Problem fetching invariants " | |
7728 | "of chip, aborting.\n"); | |
7729 | goto err_out_iounmap; | |
7730 | } | |
7731 | ||
7732 | err = register_netdev(dev); | |
7733 | if (err) { | |
7734 | dev_err(&pdev->dev, PFX "Cannot register net device, " | |
7735 | "aborting.\n"); | |
7736 | goto err_out_iounmap; | |
7737 | } | |
7738 | ||
7739 | pci_set_drvdata(pdev, dev); | |
7740 | ||
7741 | niu_device_announce(np); | |
7742 | ||
7743 | return 0; | |
7744 | ||
7745 | err_out_iounmap: | |
7746 | if (np->regs) { | |
7747 | iounmap(np->regs); | |
7748 | np->regs = NULL; | |
7749 | } | |
7750 | ||
7751 | err_out_release_parent: | |
7752 | niu_put_parent(np); | |
7753 | ||
7754 | err_out_free_dev: | |
7755 | free_netdev(dev); | |
7756 | ||
7757 | err_out_free_res: | |
7758 | pci_release_regions(pdev); | |
7759 | ||
7760 | err_out_disable_pdev: | |
7761 | pci_disable_device(pdev); | |
7762 | pci_set_drvdata(pdev, NULL); | |
7763 | ||
7764 | return err; | |
7765 | } | |
7766 | ||
7767 | static void __devexit niu_pci_remove_one(struct pci_dev *pdev) | |
7768 | { | |
7769 | struct net_device *dev = pci_get_drvdata(pdev); | |
7770 | ||
7771 | if (dev) { | |
7772 | struct niu *np = netdev_priv(dev); | |
7773 | ||
7774 | unregister_netdev(dev); | |
7775 | if (np->regs) { | |
7776 | iounmap(np->regs); | |
7777 | np->regs = NULL; | |
7778 | } | |
7779 | ||
7780 | niu_ldg_free(np); | |
7781 | ||
7782 | niu_put_parent(np); | |
7783 | ||
7784 | free_netdev(dev); | |
7785 | pci_release_regions(pdev); | |
7786 | pci_disable_device(pdev); | |
7787 | pci_set_drvdata(pdev, NULL); | |
7788 | } | |
7789 | } | |
7790 | ||
7791 | static int niu_suspend(struct pci_dev *pdev, pm_message_t state) | |
7792 | { | |
7793 | struct net_device *dev = pci_get_drvdata(pdev); | |
7794 | struct niu *np = netdev_priv(dev); | |
7795 | unsigned long flags; | |
7796 | ||
7797 | if (!netif_running(dev)) | |
7798 | return 0; | |
7799 | ||
7800 | flush_scheduled_work(); | |
7801 | niu_netif_stop(np); | |
7802 | ||
7803 | del_timer_sync(&np->timer); | |
7804 | ||
7805 | spin_lock_irqsave(&np->lock, flags); | |
7806 | niu_enable_interrupts(np, 0); | |
7807 | spin_unlock_irqrestore(&np->lock, flags); | |
7808 | ||
7809 | netif_device_detach(dev); | |
7810 | ||
7811 | spin_lock_irqsave(&np->lock, flags); | |
7812 | niu_stop_hw(np); | |
7813 | spin_unlock_irqrestore(&np->lock, flags); | |
7814 | ||
7815 | pci_save_state(pdev); | |
7816 | ||
7817 | return 0; | |
7818 | } | |
7819 | ||
7820 | static int niu_resume(struct pci_dev *pdev) | |
7821 | { | |
7822 | struct net_device *dev = pci_get_drvdata(pdev); | |
7823 | struct niu *np = netdev_priv(dev); | |
7824 | unsigned long flags; | |
7825 | int err; | |
7826 | ||
7827 | if (!netif_running(dev)) | |
7828 | return 0; | |
7829 | ||
7830 | pci_restore_state(pdev); | |
7831 | ||
7832 | netif_device_attach(dev); | |
7833 | ||
7834 | spin_lock_irqsave(&np->lock, flags); | |
7835 | ||
7836 | err = niu_init_hw(np); | |
7837 | if (!err) { | |
7838 | np->timer.expires = jiffies + HZ; | |
7839 | add_timer(&np->timer); | |
7840 | niu_netif_start(np); | |
7841 | } | |
7842 | ||
7843 | spin_unlock_irqrestore(&np->lock, flags); | |
7844 | ||
7845 | return err; | |
7846 | } | |
7847 | ||
7848 | static struct pci_driver niu_pci_driver = { | |
7849 | .name = DRV_MODULE_NAME, | |
7850 | .id_table = niu_pci_tbl, | |
7851 | .probe = niu_pci_init_one, | |
7852 | .remove = __devexit_p(niu_pci_remove_one), | |
7853 | .suspend = niu_suspend, | |
7854 | .resume = niu_resume, | |
7855 | }; | |
7856 | ||
7857 | #ifdef CONFIG_SPARC64 | |
7858 | static void *niu_phys_alloc_coherent(struct device *dev, size_t size, | |
7859 | u64 *dma_addr, gfp_t flag) | |
7860 | { | |
7861 | unsigned long order = get_order(size); | |
7862 | unsigned long page = __get_free_pages(flag, order); | |
7863 | ||
7864 | if (page == 0UL) | |
7865 | return NULL; | |
7866 | memset((char *)page, 0, PAGE_SIZE << order); | |
7867 | *dma_addr = __pa(page); | |
7868 | ||
7869 | return (void *) page; | |
7870 | } | |
7871 | ||
7872 | static void niu_phys_free_coherent(struct device *dev, size_t size, | |
7873 | void *cpu_addr, u64 handle) | |
7874 | { | |
7875 | unsigned long order = get_order(size); | |
7876 | ||
7877 | free_pages((unsigned long) cpu_addr, order); | |
7878 | } | |
7879 | ||
7880 | static u64 niu_phys_map_page(struct device *dev, struct page *page, | |
7881 | unsigned long offset, size_t size, | |
7882 | enum dma_data_direction direction) | |
7883 | { | |
7884 | return page_to_phys(page) + offset; | |
7885 | } | |
7886 | ||
7887 | static void niu_phys_unmap_page(struct device *dev, u64 dma_address, | |
7888 | size_t size, enum dma_data_direction direction) | |
7889 | { | |
7890 | /* Nothing to do. */ | |
7891 | } | |
7892 | ||
7893 | static u64 niu_phys_map_single(struct device *dev, void *cpu_addr, | |
7894 | size_t size, | |
7895 | enum dma_data_direction direction) | |
7896 | { | |
7897 | return __pa(cpu_addr); | |
7898 | } | |
7899 | ||
7900 | static void niu_phys_unmap_single(struct device *dev, u64 dma_address, | |
7901 | size_t size, | |
7902 | enum dma_data_direction direction) | |
7903 | { | |
7904 | /* Nothing to do. */ | |
7905 | } | |
7906 | ||
7907 | static const struct niu_ops niu_phys_ops = { | |
7908 | .alloc_coherent = niu_phys_alloc_coherent, | |
7909 | .free_coherent = niu_phys_free_coherent, | |
7910 | .map_page = niu_phys_map_page, | |
7911 | .unmap_page = niu_phys_unmap_page, | |
7912 | .map_single = niu_phys_map_single, | |
7913 | .unmap_single = niu_phys_unmap_single, | |
7914 | }; | |
7915 | ||
7916 | static unsigned long res_size(struct resource *r) | |
7917 | { | |
7918 | return r->end - r->start + 1UL; | |
7919 | } | |
7920 | ||
7921 | static int __devinit niu_of_probe(struct of_device *op, | |
7922 | const struct of_device_id *match) | |
7923 | { | |
7924 | union niu_parent_id parent_id; | |
7925 | struct net_device *dev; | |
7926 | struct niu *np; | |
7927 | const u32 *reg; | |
7928 | int err; | |
7929 | ||
7930 | niu_driver_version(); | |
7931 | ||
7932 | reg = of_get_property(op->node, "reg", NULL); | |
7933 | if (!reg) { | |
7934 | dev_err(&op->dev, PFX "%s: No 'reg' property, aborting.\n", | |
7935 | op->node->full_name); | |
7936 | return -ENODEV; | |
7937 | } | |
7938 | ||
7939 | dev = niu_alloc_and_init(&op->dev, NULL, op, | |
7940 | &niu_phys_ops, reg[0] & 0x1); | |
7941 | if (!dev) { | |
7942 | err = -ENOMEM; | |
7943 | goto err_out; | |
7944 | } | |
7945 | np = netdev_priv(dev); | |
7946 | ||
7947 | memset(&parent_id, 0, sizeof(parent_id)); | |
7948 | parent_id.of = of_get_parent(op->node); | |
7949 | ||
7950 | np->parent = niu_get_parent(np, &parent_id, | |
7951 | PLAT_TYPE_NIU); | |
7952 | if (!np->parent) { | |
7953 | err = -ENOMEM; | |
7954 | goto err_out_free_dev; | |
7955 | } | |
7956 | ||
7957 | dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM); | |
7958 | ||
7959 | np->regs = of_ioremap(&op->resource[1], 0, | |
7960 | res_size(&op->resource[1]), | |
7961 | "niu regs"); | |
7962 | if (!np->regs) { | |
7963 | dev_err(&op->dev, PFX "Cannot map device registers, " | |
7964 | "aborting.\n"); | |
7965 | err = -ENOMEM; | |
7966 | goto err_out_release_parent; | |
7967 | } | |
7968 | ||
7969 | np->vir_regs_1 = of_ioremap(&op->resource[2], 0, | |
7970 | res_size(&op->resource[2]), | |
7971 | "niu vregs-1"); | |
7972 | if (!np->vir_regs_1) { | |
7973 | dev_err(&op->dev, PFX "Cannot map device vir registers 1, " | |
7974 | "aborting.\n"); | |
7975 | err = -ENOMEM; | |
7976 | goto err_out_iounmap; | |
7977 | } | |
7978 | ||
7979 | np->vir_regs_2 = of_ioremap(&op->resource[3], 0, | |
7980 | res_size(&op->resource[3]), | |
7981 | "niu vregs-2"); | |
7982 | if (!np->vir_regs_2) { | |
7983 | dev_err(&op->dev, PFX "Cannot map device vir registers 2, " | |
7984 | "aborting.\n"); | |
7985 | err = -ENOMEM; | |
7986 | goto err_out_iounmap; | |
7987 | } | |
7988 | ||
7989 | niu_assign_netdev_ops(dev); | |
7990 | ||
7991 | err = niu_get_invariants(np); | |
7992 | if (err) { | |
7993 | if (err != -ENODEV) | |
7994 | dev_err(&op->dev, PFX "Problem fetching invariants " | |
7995 | "of chip, aborting.\n"); | |
7996 | goto err_out_iounmap; | |
7997 | } | |
7998 | ||
7999 | err = register_netdev(dev); | |
8000 | if (err) { | |
8001 | dev_err(&op->dev, PFX "Cannot register net device, " | |
8002 | "aborting.\n"); | |
8003 | goto err_out_iounmap; | |
8004 | } | |
8005 | ||
8006 | dev_set_drvdata(&op->dev, dev); | |
8007 | ||
8008 | niu_device_announce(np); | |
8009 | ||
8010 | return 0; | |
8011 | ||
8012 | err_out_iounmap: | |
8013 | if (np->vir_regs_1) { | |
8014 | of_iounmap(&op->resource[2], np->vir_regs_1, | |
8015 | res_size(&op->resource[2])); | |
8016 | np->vir_regs_1 = NULL; | |
8017 | } | |
8018 | ||
8019 | if (np->vir_regs_2) { | |
8020 | of_iounmap(&op->resource[3], np->vir_regs_2, | |
8021 | res_size(&op->resource[3])); | |
8022 | np->vir_regs_2 = NULL; | |
8023 | } | |
8024 | ||
8025 | if (np->regs) { | |
8026 | of_iounmap(&op->resource[1], np->regs, | |
8027 | res_size(&op->resource[1])); | |
8028 | np->regs = NULL; | |
8029 | } | |
8030 | ||
8031 | err_out_release_parent: | |
8032 | niu_put_parent(np); | |
8033 | ||
8034 | err_out_free_dev: | |
8035 | free_netdev(dev); | |
8036 | ||
8037 | err_out: | |
8038 | return err; | |
8039 | } | |
8040 | ||
8041 | static int __devexit niu_of_remove(struct of_device *op) | |
8042 | { | |
8043 | struct net_device *dev = dev_get_drvdata(&op->dev); | |
8044 | ||
8045 | if (dev) { | |
8046 | struct niu *np = netdev_priv(dev); | |
8047 | ||
8048 | unregister_netdev(dev); | |
8049 | ||
8050 | if (np->vir_regs_1) { | |
8051 | of_iounmap(&op->resource[2], np->vir_regs_1, | |
8052 | res_size(&op->resource[2])); | |
8053 | np->vir_regs_1 = NULL; | |
8054 | } | |
8055 | ||
8056 | if (np->vir_regs_2) { | |
8057 | of_iounmap(&op->resource[3], np->vir_regs_2, | |
8058 | res_size(&op->resource[3])); | |
8059 | np->vir_regs_2 = NULL; | |
8060 | } | |
8061 | ||
8062 | if (np->regs) { | |
8063 | of_iounmap(&op->resource[1], np->regs, | |
8064 | res_size(&op->resource[1])); | |
8065 | np->regs = NULL; | |
8066 | } | |
8067 | ||
8068 | niu_ldg_free(np); | |
8069 | ||
8070 | niu_put_parent(np); | |
8071 | ||
8072 | free_netdev(dev); | |
8073 | dev_set_drvdata(&op->dev, NULL); | |
8074 | } | |
8075 | return 0; | |
8076 | } | |
8077 | ||
8078 | static struct of_device_id niu_match[] = { | |
8079 | { | |
8080 | .name = "network", | |
8081 | .compatible = "SUNW,niusl", | |
8082 | }, | |
8083 | {}, | |
8084 | }; | |
8085 | MODULE_DEVICE_TABLE(of, niu_match); | |
8086 | ||
8087 | static struct of_platform_driver niu_of_driver = { | |
8088 | .name = "niu", | |
8089 | .match_table = niu_match, | |
8090 | .probe = niu_of_probe, | |
8091 | .remove = __devexit_p(niu_of_remove), | |
8092 | }; | |
8093 | ||
8094 | #endif /* CONFIG_SPARC64 */ | |
8095 | ||
8096 | static int __init niu_init(void) | |
8097 | { | |
8098 | int err = 0; | |
8099 | ||
81429973 | 8100 | BUILD_BUG_ON(PAGE_SIZE < 4 * 1024); |
a3138df9 DM |
8101 | |
8102 | niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT); | |
8103 | ||
8104 | #ifdef CONFIG_SPARC64 | |
8105 | err = of_register_driver(&niu_of_driver, &of_bus_type); | |
8106 | #endif | |
8107 | ||
8108 | if (!err) { | |
8109 | err = pci_register_driver(&niu_pci_driver); | |
8110 | #ifdef CONFIG_SPARC64 | |
8111 | if (err) | |
8112 | of_unregister_driver(&niu_of_driver); | |
8113 | #endif | |
8114 | } | |
8115 | ||
8116 | return err; | |
8117 | } | |
8118 | ||
8119 | static void __exit niu_exit(void) | |
8120 | { | |
8121 | pci_unregister_driver(&niu_pci_driver); | |
8122 | #ifdef CONFIG_SPARC64 | |
8123 | of_unregister_driver(&niu_of_driver); | |
8124 | #endif | |
8125 | } | |
8126 | ||
8127 | module_init(niu_init); | |
8128 | module_exit(niu_exit); |