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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / netxen / netxen_nic_init.c
CommitLineData
3d396eb1 1/*
5d242f1c 2 * Copyright (C) 2003 - 2009 NetXen, Inc.
13af7a6e 3 * Copyright (C) 2009 - QLogic Corporation.
3d396eb1 4 * All rights reserved.
80922fbc 5 *
3d396eb1
AK		 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
80922fbc 10 *
3d396eb1
AK		 11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
80922fbc 15 *
3d396eb1
AK		 16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
80922fbc 20 *
3d396eb1 21 * The full GNU General Public License is included in this distribution
4d21fef4 22 * in the file called "COPYING".
80922fbc 23 *
3d396eb1
AK		 24 */
25
26#include <linux/netdevice.h>
27#include <linux/delay.h>
5a0e3ad6 28#include <linux/slab.h>
3d396eb1
AK		 29#include "netxen_nic.h"
30#include "netxen_nic_hw.h"
3d396eb1
AK		 31
32struct crb_addr_pair {
e0e20a1a
LCMT		 33 u32 addr;
34 u32 data;
3d396eb1
AK		 35};
36
37#define NETXEN_MAX_CRB_XFORM 60
38static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
e0e20a1a 39#define NETXEN_ADDR_ERROR (0xffffffff)
3d396eb1
AK		 40
41#define crb_addr_transform(name) \
42 crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
43 NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
44
cb8011ad
AK		 45#define NETXEN_NIC_XDMA_RESET 0x8000ff
46
becf46a0 47static void
d8b100c5
DP		 48netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
49 struct nx_host_rds_ring *rds_ring);
f50330f9 50static int netxen_p3_has_mn(struct netxen_adapter *adapter);
993fb90c 51
3d396eb1
AK		 52static void crb_addr_transform_setup(void)
53{
54 crb_addr_transform(XDMA);
55 crb_addr_transform(TIMR);
56 crb_addr_transform(SRE);
57 crb_addr_transform(SQN3);
58 crb_addr_transform(SQN2);
59 crb_addr_transform(SQN1);
60 crb_addr_transform(SQN0);
61 crb_addr_transform(SQS3);
62 crb_addr_transform(SQS2);
63 crb_addr_transform(SQS1);
64 crb_addr_transform(SQS0);
65 crb_addr_transform(RPMX7);
66 crb_addr_transform(RPMX6);
67 crb_addr_transform(RPMX5);
68 crb_addr_transform(RPMX4);
69 crb_addr_transform(RPMX3);
70 crb_addr_transform(RPMX2);
71 crb_addr_transform(RPMX1);
72 crb_addr_transform(RPMX0);
73 crb_addr_transform(ROMUSB);
74 crb_addr_transform(SN);
75 crb_addr_transform(QMN);
76 crb_addr_transform(QMS);
77 crb_addr_transform(PGNI);
78 crb_addr_transform(PGND);
79 crb_addr_transform(PGN3);
80 crb_addr_transform(PGN2);
81 crb_addr_transform(PGN1);
82 crb_addr_transform(PGN0);
83 crb_addr_transform(PGSI);
84 crb_addr_transform(PGSD);
85 crb_addr_transform(PGS3);
86 crb_addr_transform(PGS2);
87 crb_addr_transform(PGS1);
88 crb_addr_transform(PGS0);
89 crb_addr_transform(PS);
90 crb_addr_transform(PH);
91 crb_addr_transform(NIU);
92 crb_addr_transform(I2Q);
93 crb_addr_transform(EG);
94 crb_addr_transform(MN);
95 crb_addr_transform(MS);
96 crb_addr_transform(CAS2);
97 crb_addr_transform(CAS1);
98 crb_addr_transform(CAS0);
99 crb_addr_transform(CAM);
100 crb_addr_transform(C2C1);
101 crb_addr_transform(C2C0);
1fcca1a5 102 crb_addr_transform(SMB);
e4c93c81
DP		 103 crb_addr_transform(OCM0);
104 crb_addr_transform(I2C0);
3d396eb1
AK		 105}
106
2956640d 107void netxen_release_rx_buffers(struct netxen_adapter *adapter)
3d396eb1 108{
2956640d 109 struct netxen_recv_context *recv_ctx;
48bfd1e0 110 struct nx_host_rds_ring *rds_ring;
2956640d 111 struct netxen_rx_buffer *rx_buf;
becf46a0
DP		 112 int i, ring;
113
114 recv_ctx = &adapter->recv_ctx;
115 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
116 rds_ring = &recv_ctx->rds_rings[ring];
438627c7 117 for (i = 0; i < rds_ring->num_desc; ++i) {
becf46a0
DP		 118 rx_buf = &(rds_ring->rx_buf_arr[i]);
119 if (rx_buf->state == NETXEN_BUFFER_FREE)
120 continue;
121 pci_unmap_single(adapter->pdev,
122 rx_buf->dma,
123 rds_ring->dma_size,
124 PCI_DMA_FROMDEVICE);
125 if (rx_buf->skb != NULL)
126 dev_kfree_skb_any(rx_buf->skb);
2956640d
DP		 127 }
128 }
129}
130
131void netxen_release_tx_buffers(struct netxen_adapter *adapter)
132{
133 struct netxen_cmd_buffer *cmd_buf;
134 struct netxen_skb_frag *buffrag;
135 int i, j;
4ea528a1 136 struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
2956640d 137
d877f1e3
DP		 138 cmd_buf = tx_ring->cmd_buf_arr;
139 for (i = 0; i < tx_ring->num_desc; i++) {
2956640d
DP		 140 buffrag = cmd_buf->frag_array;
141 if (buffrag->dma) {
142 pci_unmap_single(adapter->pdev, buffrag->dma,
143 buffrag->length, PCI_DMA_TODEVICE);
144 buffrag->dma = 0ULL;
145 }
146 for (j = 0; j < cmd_buf->frag_count; j++) {
147 buffrag++;
148 if (buffrag->dma) {
149 pci_unmap_page(adapter->pdev, buffrag->dma,
150 buffrag->length,
151 PCI_DMA_TODEVICE);
152 buffrag->dma = 0ULL;
153 }
154 }
2956640d
DP		 155 if (cmd_buf->skb) {
156 dev_kfree_skb_any(cmd_buf->skb);
157 cmd_buf->skb = NULL;
158 }
159 cmd_buf++;
160 }
161}
162
163void netxen_free_sw_resources(struct netxen_adapter *adapter)
164{
165 struct netxen_recv_context *recv_ctx;
48bfd1e0 166 struct nx_host_rds_ring *rds_ring;
d877f1e3 167 struct nx_host_tx_ring *tx_ring;
becf46a0
DP		 168 int ring;
169
170 recv_ctx = &adapter->recv_ctx;
4ea528a1
DP		 171
172 if (recv_ctx->rds_rings == NULL)
173 goto skip_rds;
174
becf46a0
DP		 175 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
176 rds_ring = &recv_ctx->rds_rings[ring];
f2333a01
F		 177 vfree(rds_ring->rx_buf_arr);
178 rds_ring->rx_buf_arr = NULL;
2956640d 179 }
4ea528a1
DP		 180 kfree(recv_ctx->rds_rings);
181
182skip_rds:
183 if (adapter->tx_ring == NULL)
184 return;
becf46a0 185
4ea528a1 186 tx_ring = adapter->tx_ring;
f2333a01 187 vfree(tx_ring->cmd_buf_arr);
011f4ea0
AKS		 188 kfree(tx_ring);
189 adapter->tx_ring = NULL;
2956640d
DP		 190}
191
192int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
193{
194 struct netxen_recv_context *recv_ctx;
48bfd1e0 195 struct nx_host_rds_ring *rds_ring;
d8b100c5 196 struct nx_host_sds_ring *sds_ring;
4ea528a1 197 struct nx_host_tx_ring *tx_ring;
2956640d 198 struct netxen_rx_buffer *rx_buf;
4ea528a1 199 int ring, i, size;
2956640d
DP		 200
201 struct netxen_cmd_buffer *cmd_buf_arr;
202 struct net_device *netdev = adapter->netdev;
d877f1e3 203 struct pci_dev *pdev = adapter->pdev;
2956640d 204
4ea528a1
DP		 205 size = sizeof(struct nx_host_tx_ring);
206 tx_ring = kzalloc(size, GFP_KERNEL);
207 if (tx_ring == NULL) {
208 dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
209 netdev->name);
210 return -ENOMEM;
211 }
212 adapter->tx_ring = tx_ring;
213
d877f1e3 214 tx_ring->num_desc = adapter->num_txd;
b2af9cb0 215 tx_ring->txq = netdev_get_tx_queue(netdev, 0);
4ea528a1
DP		 216
217 cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
2956640d 218 if (cmd_buf_arr == NULL) {
d877f1e3 219 dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
2956640d
DP		 220 netdev->name);
221 return -ENOMEM;
222 }
d877f1e3
DP		 223 memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
224 tx_ring->cmd_buf_arr = cmd_buf_arr;
2956640d 225
becf46a0 226 recv_ctx = &adapter->recv_ctx;
4ea528a1
DP		 227
228 size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
229 rds_ring = kzalloc(size, GFP_KERNEL);
230 if (rds_ring == NULL) {
231 dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
232 netdev->name);
233 return -ENOMEM;
234 }
235 recv_ctx->rds_rings = rds_ring;
236
becf46a0
DP		 237 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
238 rds_ring = &recv_ctx->rds_rings[ring];
438627c7
DP		 239 switch (ring) {
240 case RCV_RING_NORMAL:
241 rds_ring->num_desc = adapter->num_rxd;
becf46a0
DP		 242 if (adapter->ahw.cut_through) {
243 rds_ring->dma_size =
244 NX_CT_DEFAULT_RX_BUF_LEN;
48bfd1e0 245 rds_ring->skb_size =
becf46a0
DP		 246 NX_CT_DEFAULT_RX_BUF_LEN;
247 } else {
9b08beba
DP		 248 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
249 rds_ring->dma_size =
250 NX_P3_RX_BUF_MAX_LEN;
251 else
252 rds_ring->dma_size =
253 NX_P2_RX_BUF_MAX_LEN;
becf46a0 254 rds_ring->skb_size =
9b08beba 255 rds_ring->dma_size + NET_IP_ALIGN;
becf46a0
DP		 256 }
257 break;
2956640d 258
438627c7
DP		 259 case RCV_RING_JUMBO:
260 rds_ring->num_desc = adapter->num_jumbo_rxd;
becf46a0
DP		 261 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
262 rds_ring->dma_size =
263 NX_P3_RX_JUMBO_BUF_MAX_LEN;
264 else
265 rds_ring->dma_size =
266 NX_P2_RX_JUMBO_BUF_MAX_LEN;
bc75e5bf
DP		 267
268 if (adapter->capabilities & NX_CAP0_HW_LRO)
269 rds_ring->dma_size += NX_LRO_BUFFER_EXTRA;
270
becf46a0
DP		 271 rds_ring->skb_size =
272 rds_ring->dma_size + NET_IP_ALIGN;
273 break;
2956640d 274
becf46a0 275 case RCV_RING_LRO:
438627c7 276 rds_ring->num_desc = adapter->num_lro_rxd;
9b08beba
DP		 277 rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
278 rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
becf46a0
DP		 279 break;
280
281 }
282 rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
d8b100c5 283 vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
becf46a0
DP		 284 if (rds_ring->rx_buf_arr == NULL) {
285 printk(KERN_ERR "%s: Failed to allocate "
286 "rx buffer ring %d\n",
287 netdev->name, ring);
288 /* free whatever was already allocated */
289 goto err_out;
290 }
d8b100c5 291 memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
becf46a0
DP		 292 INIT_LIST_HEAD(&rds_ring->free_list);
293 /*
294 * Now go through all of them, set reference handles
295 * and put them in the queues.
296 */
becf46a0 297 rx_buf = rds_ring->rx_buf_arr;
4ea528a1 298 for (i = 0; i < rds_ring->num_desc; i++) {
becf46a0
DP		 299 list_add_tail(&rx_buf->list,
300 &rds_ring->free_list);
301 rx_buf->ref_handle = i;
302 rx_buf->state = NETXEN_BUFFER_FREE;
303 rx_buf++;
3d396eb1 304 }
d8b100c5
DP		 305 spin_lock_init(&rds_ring->lock);
306 }
307
308 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
309 sds_ring = &recv_ctx->sds_rings[ring];
310 sds_ring->irq = adapter->msix_entries[ring].vector;
d8b100c5
DP		 311 sds_ring->adapter = adapter;
312 sds_ring->num_desc = adapter->num_rxd;
313
314 for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
315 INIT_LIST_HEAD(&sds_ring->free_list[i]);
3d396eb1 316 }
2956640d
DP		 317
318 return 0;
319
320err_out:
321 netxen_free_sw_resources(adapter);
322 return -ENOMEM;
3d396eb1
AK		 323}
324
3d396eb1
AK		 325/*
326 * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
327 * address to external PCI CRB address.
328 */
993fb90c 329static u32 netxen_decode_crb_addr(u32 addr)
3d396eb1
AK		 330{
331 int i;
e0e20a1a 332 u32 base_addr, offset, pci_base;
3d396eb1
AK		 333
334 crb_addr_transform_setup();
335
336 pci_base = NETXEN_ADDR_ERROR;
337 base_addr = addr & 0xfff00000;
338 offset = addr & 0x000fffff;
339
340 for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
341 if (crb_addr_xform[i] == base_addr) {
342 pci_base = i << 20;
343 break;
344 }
345 }
346 if (pci_base == NETXEN_ADDR_ERROR)
347 return pci_base;
348 else
349 return (pci_base + offset);
350}
351
c9517e58 352#define NETXEN_MAX_ROM_WAIT_USEC 100
3d396eb1 353
993fb90c 354static int netxen_wait_rom_done(struct netxen_adapter *adapter)
3d396eb1
AK		 355{
356 long timeout = 0;
357 long done = 0;
358
27c915a4
DP		 359 cond_resched();
360
3d396eb1 361 while (done == 0) {
f98a9f69 362 done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
3d396eb1 363 done &= 2;
c9517e58
DP		 364 if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) {
365 dev_err(&adapter->pdev->dev,
366 "Timeout reached waiting for rom done");
3d396eb1
AK		 367 return -EIO;
368 }
c9517e58 369 udelay(1);
3d396eb1
AK		 370 }
371 return 0;
372}
373
993fb90c
AB		 374static int do_rom_fast_read(struct netxen_adapter *adapter,
375 int addr, int *valp)
3d396eb1 376{
f98a9f69
DP		 377 NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
378 NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
379 NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
380 NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
3d396eb1
AK		 381 if (netxen_wait_rom_done(adapter)) {
382 printk("Error waiting for rom done\n");
383 return -EIO;
384 }
385 /* reset abyte_cnt and dummy_byte_cnt */
f98a9f69 386 NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
27c915a4 387 udelay(10);
f98a9f69 388 NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
3d396eb1 389
f98a9f69 390 *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
3d396eb1
AK		 391 return 0;
392}
393
993fb90c
AB		 394static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
395 u8 *bytes, size_t size)
27d2ab54
AK		 396{
397 int addridx;
398 int ret = 0;
399
400 for (addridx = addr; addridx < (addr + size); addridx += 4) {
f305f789
AV		 401 int v;
402 ret = do_rom_fast_read(adapter, addridx, &v);
27d2ab54
AK		 403 if (ret != 0)
404 break;
f305f789 405 *(__le32 *)bytes = cpu_to_le32(v);
27d2ab54
AK		 406 bytes += 4;
407 }
408
409 return ret;
410}
411
412int
4790654c 413netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
27d2ab54
AK		 414 u8 *bytes, size_t size)
415{
416 int ret;
417
c9517e58 418 ret = netxen_rom_lock(adapter);
27d2ab54
AK		 419 if (ret < 0)
420 return ret;
421
422 ret = do_rom_fast_read_words(adapter, addr, bytes, size);
423
424 netxen_rom_unlock(adapter);
425 return ret;
426}
427
3d396eb1
AK		 428int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
429{
430 int ret;
431
c9517e58 432 if (netxen_rom_lock(adapter) != 0)
3d396eb1
AK		 433 return -EIO;
434
435 ret = do_rom_fast_read(adapter, addr, valp);
cb8011ad
AK		 436 netxen_rom_unlock(adapter);
437 return ret;
438}
439
3d396eb1
AK		 440#define NETXEN_BOARDTYPE 0x4008
441#define NETXEN_BOARDNUM 0x400c
442#define NETXEN_CHIPNUM 0x4010
3d396eb1 443
0be367bd 444int netxen_pinit_from_rom(struct netxen_adapter *adapter)
3d396eb1 445{
dcd56fdb 446 int addr, val;
27c915a4 447 int i, n, init_delay = 0;
3d396eb1 448 struct crb_addr_pair *buf;
27c915a4 449 unsigned offset;
e0e20a1a 450 u32 off;
3d396eb1
AK		 451
452 /* resetall */
c9517e58 453 netxen_rom_lock(adapter);
f98a9f69 454 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
27c915a4 455 netxen_rom_unlock(adapter);
3d396eb1 456
2956640d
DP		 457 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
458 if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
27c915a4 459 (n != 0xcafecafe) ||
2956640d
DP		 460 netxen_rom_fast_read(adapter, 4, &n) != 0) {
461 printk(KERN_ERR "%s: ERROR Reading crb_init area: "
462 "n: %08x\n", netxen_nic_driver_name, n);
3d396eb1
AK		 463 return -EIO;
464 }
2956640d
DP		 465 offset = n & 0xffffU;
466 n = (n >> 16) & 0xffffU;
467 } else {
468 if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
469 !(n & 0x80000000)) {
470 printk(KERN_ERR "%s: ERROR Reading crb_init area: "
471 "n: %08x\n", netxen_nic_driver_name, n);
472 return -EIO;
3d396eb1 473 }
2956640d
DP		 474 offset = 1;
475 n &= ~0x80000000;
476 }
477
0be367bd 478 if (n >= 1024) {
2956640d
DP		 479 printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
480 " initialized.\n", __func__, n);
481 return -EIO;
482 }
3d396eb1 483
2956640d
DP		 484 buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
485 if (buf == NULL) {
486 printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
487 netxen_nic_driver_name);
488 return -ENOMEM;
489 }
0be367bd 490
2956640d
DP		 491 for (i = 0; i < n; i++) {
492 if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
584dbe94
DM		 493 netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
494 kfree(buf);
2956640d 495 return -EIO;
584dbe94 496 }
2956640d
DP		 497
498 buf[i].addr = addr;
499 buf[i].data = val;
500
2956640d 501 }
0be367bd 502
2956640d
DP		 503 for (i = 0; i < n; i++) {
504
505 off = netxen_decode_crb_addr(buf[i].addr);
506 if (off == NETXEN_ADDR_ERROR) {
507 printk(KERN_ERR"CRB init value out of range %x\n",
1fcca1a5 508 buf[i].addr);
2956640d
DP		 509 continue;
510 }
511 off += NETXEN_PCI_CRBSPACE;
0be367bd
AKS		 512
513 if (off & 1)
514 continue;
515
2956640d
DP		 516 /* skipping cold reboot MAGIC */
517 if (off == NETXEN_CAM_RAM(0x1fc))
518 continue;
519
520 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
8bee0a91
DP		 521 if (off == (NETXEN_CRB_I2C0 + 0x1c))
522 continue;
2956640d
DP		 523 /* do not reset PCI */
524 if (off == (ROMUSB_GLB + 0xbc))
1fcca1a5 525 continue;
27c915a4
DP		 526 if (off == (ROMUSB_GLB + 0xa8))
527 continue;
528 if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
529 continue;
530 if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
531 continue;
532 if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
533 continue;
e7473f12
AKS		 534 if ((off & 0x0ff00000) == NETXEN_CRB_DDR_NET)
535 continue;
0be367bd
AKS		 536 if (off == (NETXEN_CRB_PEG_NET_1 + 0x18) &&
537 !NX_IS_REVISION_P3P(adapter->ahw.revision_id))
2956640d
DP		 538 buf[i].data = 0x1020;
539 /* skip the function enable register */
540 if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
3d396eb1 541 continue;
2956640d
DP		 542 if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
543 continue;
544 if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
545 continue;
546 }
3d396eb1 547
27c915a4 548 init_delay = 1;
2956640d
DP		 549 /* After writing this register, HW needs time for CRB */
550 /* to quiet down (else crb_window returns 0xffffffff) */
551 if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
27c915a4 552 init_delay = 1000;
2956640d 553 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
3d396eb1 554 /* hold xdma in reset also */
cb8011ad 555 buf[i].data = NETXEN_NIC_XDMA_RESET;
27c915a4 556 buf[i].data = 0x8000ff;
3d396eb1 557 }
2956640d 558 }
3d396eb1 559
f98a9f69 560 NXWR32(adapter, off, buf[i].data);
3d396eb1 561
27c915a4 562 msleep(init_delay);
2956640d
DP		 563 }
564 kfree(buf);
3d396eb1 565
2956640d 566 /* disable_peg_cache_all */
3d396eb1 567
2956640d
DP		 568 /* unreset_net_cache */
569 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
f98a9f69
DP		 570 val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
571 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
3d396eb1 572 }
2956640d
DP		 573
574 /* p2dn replyCount */
f98a9f69 575 NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
2956640d 576 /* disable_peg_cache 0 */
f98a9f69 577 NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
2956640d 578 /* disable_peg_cache 1 */
f98a9f69 579 NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
2956640d
DP		 580
581 /* peg_clr_all */
582
583 /* peg_clr 0 */
f98a9f69
DP		 584 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
585 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
2956640d 586 /* peg_clr 1 */
f98a9f69
DP		 587 NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
588 NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
2956640d 589 /* peg_clr 2 */
f98a9f69
DP		 590 NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
591 NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
2956640d 592 /* peg_clr 3 */
f98a9f69
DP		 593 NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
594 NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
3d396eb1
AK		 595 return 0;
596}
597
f50330f9
AKS		 598static struct uni_table_desc *nx_get_table_desc(const u8 *unirom, int section)
599{
600 uint32_t i;
601 struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
602 __le32 entries = cpu_to_le32(directory->num_entries);
603
604 for (i = 0; i < entries; i++) {
605
606 __le32 offs = cpu_to_le32(directory->findex) +
607 (i * cpu_to_le32(directory->entry_size));
608 __le32 tab_type = cpu_to_le32(*((u32 *)&unirom[offs] + 8));
609
610 if (tab_type == section)
611 return (struct uni_table_desc *) &unirom[offs];
612 }
613
614 return NULL;
615}
616
617static int
618nx_set_product_offs(struct netxen_adapter *adapter)
619{
620 struct uni_table_desc *ptab_descr;
621 const u8 *unirom = adapter->fw->data;
622 uint32_t i;
623 __le32 entries;
624
634d7df8
DP		 625 int mn_present = (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ?
626 1 : netxen_p3_has_mn(adapter);
627
f50330f9
AKS		 628 ptab_descr = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_PRODUCT_TBL);
629 if (ptab_descr == NULL)
630 return -1;
631
632 entries = cpu_to_le32(ptab_descr->num_entries);
633
634d7df8 634nomn:
f50330f9
AKS		 635 for (i = 0; i < entries; i++) {
636
637 __le32 flags, file_chiprev, offs;
638 u8 chiprev = adapter->ahw.revision_id;
f50330f9
AKS		 639 uint32_t flagbit;
640
641 offs = cpu_to_le32(ptab_descr->findex) +
642 (i * cpu_to_le32(ptab_descr->entry_size));
643 flags = cpu_to_le32(*((int *)&unirom[offs] + NX_UNI_FLAGS_OFF));
644 file_chiprev = cpu_to_le32(*((int *)&unirom[offs] +
645 NX_UNI_CHIP_REV_OFF));
646
647 flagbit = mn_present ? 1 : 2;
648
649 if ((chiprev == file_chiprev) &&
650 ((1ULL << flagbit) & flags)) {
651 adapter->file_prd_off = offs;
652 return 0;
653 }
654 }
655
634d7df8
DP		 656 if (mn_present && NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
657 mn_present = 0;
658 goto nomn;
659 }
660
f50330f9
AKS		 661 return -1;
662}
663
664
665static struct uni_data_desc *nx_get_data_desc(struct netxen_adapter *adapter,
666 u32 section, u32 idx_offset)
667{
668 const u8 *unirom = adapter->fw->data;
669 int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
670 idx_offset));
671 struct uni_table_desc *tab_desc;
672 __le32 offs;
673
674 tab_desc = nx_get_table_desc(unirom, section);
675
676 if (tab_desc == NULL)
677 return NULL;
678
679 offs = cpu_to_le32(tab_desc->findex) +
680 (cpu_to_le32(tab_desc->entry_size) * idx);
681
682 return (struct uni_data_desc *)&unirom[offs];
683}
684
685static u8 *
686nx_get_bootld_offs(struct netxen_adapter *adapter)
687{
688 u32 offs = NETXEN_BOOTLD_START;
689
690 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
691 offs = cpu_to_le32((nx_get_data_desc(adapter,
692 NX_UNI_DIR_SECT_BOOTLD,
693 NX_UNI_BOOTLD_IDX_OFF))->findex);
694
695 return (u8 *)&adapter->fw->data[offs];
696}
697
698static u8 *
699nx_get_fw_offs(struct netxen_adapter *adapter)
700{
701 u32 offs = NETXEN_IMAGE_START;
702
703 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
704 offs = cpu_to_le32((nx_get_data_desc(adapter,
705 NX_UNI_DIR_SECT_FW,
706 NX_UNI_FIRMWARE_IDX_OFF))->findex);
707
708 return (u8 *)&adapter->fw->data[offs];
709}
710
711static __le32
712nx_get_fw_size(struct netxen_adapter *adapter)
713{
714 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
715 return cpu_to_le32((nx_get_data_desc(adapter,
716 NX_UNI_DIR_SECT_FW,
717 NX_UNI_FIRMWARE_IDX_OFF))->size);
718 else
719 return cpu_to_le32(
720 *(u32 *)&adapter->fw->data[NX_FW_SIZE_OFFSET]);
721}
722
723static __le32
724nx_get_fw_version(struct netxen_adapter *adapter)
725{
726 struct uni_data_desc *fw_data_desc;
727 const struct firmware *fw = adapter->fw;
728 __le32 major, minor, sub;
729 const u8 *ver_str;
730 int i, ret = 0;
731
732 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
733
734 fw_data_desc = nx_get_data_desc(adapter,
735 NX_UNI_DIR_SECT_FW, NX_UNI_FIRMWARE_IDX_OFF);
736 ver_str = fw->data + cpu_to_le32(fw_data_desc->findex) +
737 cpu_to_le32(fw_data_desc->size) - 17;
738
739 for (i = 0; i < 12; i++) {
740 if (!strncmp(&ver_str[i], "REV=", 4)) {
741 ret = sscanf(&ver_str[i+4], "%u.%u.%u ",
742 &major, &minor, &sub);
743 break;
744 }
745 }
746
747 if (ret != 3)
748 return 0;
749
750 return major + (minor << 8) + (sub << 16);
751
752 } else
753 return cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
754}
755
756static __le32
757nx_get_bios_version(struct netxen_adapter *adapter)
758{
759 const struct firmware *fw = adapter->fw;
760 __le32 bios_ver, prd_off = adapter->file_prd_off;
761
762 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
763 bios_ver = cpu_to_le32(*((u32 *) (&fw->data[prd_off])
764 + NX_UNI_BIOS_VERSION_OFF));
bb2792e0 765 return (bios_ver << 16) + ((bios_ver >> 8) & 0xff00) +
f50330f9
AKS		 766 (bios_ver >> 24);
767 } else
768 return cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
769
770}
771
67c38fc6
DP		 772int
773netxen_need_fw_reset(struct netxen_adapter *adapter)
774{
775 u32 count, old_count;
776 u32 val, version, major, minor, build;
777 int i, timeout;
778 u8 fw_type;
779
780 /* NX2031 firmware doesn't support heartbit */
781 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
782 return 1;
783
6a808c6c
AKS		 784 if (adapter->need_fw_reset)
785 return 1;
786
67c38fc6
DP		 787 /* last attempt had failed */
788 if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
789 return 1;
790
581e8ae4 791 old_count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
67c38fc6
DP		 792
793 for (i = 0; i < 10; i++) {
794
795 timeout = msleep_interruptible(200);
796 if (timeout) {
797 NXWR32(adapter, CRB_CMDPEG_STATE,
798 PHAN_INITIALIZE_FAILED);
799 return -EINTR;
800 }
801
802 count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
803 if (count != old_count)
804 break;
805 }
806
807 /* firmware is dead */
808 if (count == old_count)
809 return 1;
810
811 /* check if we have got newer or different file firmware */
812 if (adapter->fw) {
813
f50330f9 814 val = nx_get_fw_version(adapter);
67c38fc6 815
67c38fc6
DP		 816 version = NETXEN_DECODE_VERSION(val);
817
818 major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
819 minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
820 build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
821
822 if (version > NETXEN_VERSION_CODE(major, minor, build))
823 return 1;
824
f50330f9
AKS		 825 if (version == NETXEN_VERSION_CODE(major, minor, build) &&
826 adapter->fw_type != NX_UNIFIED_ROMIMAGE) {
67c38fc6
DP		 827
828 val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
829 fw_type = (val & 0x4) ?
830 NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
831
832 if (adapter->fw_type != fw_type)
833 return 1;
834 }
835 }
836
837 return 0;
838}
839
840static char *fw_name[] = {
7e8e5d97
DP		 841 NX_P2_MN_ROMIMAGE_NAME,
842 NX_P3_CT_ROMIMAGE_NAME,
843 NX_P3_MN_ROMIMAGE_NAME,
844 NX_UNIFIED_ROMIMAGE_NAME,
845 NX_FLASH_ROMIMAGE_NAME,
67c38fc6
DP		 846};
847
f7185c71
DP		 848int
849netxen_load_firmware(struct netxen_adapter *adapter)
850{
851 u64 *ptr64;
852 u32 i, flashaddr, size;
853 const struct firmware *fw = adapter->fw;
67c38fc6
DP		 854 struct pci_dev *pdev = adapter->pdev;
855
856 dev_info(&pdev->dev, "loading firmware from %s\n",
857 fw_name[adapter->fw_type]);
f7185c71
DP		 858
859 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
860 NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
861
862 if (fw) {
863 __le64 data;
864
865 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
866
f50330f9 867 ptr64 = (u64 *)nx_get_bootld_offs(adapter);
f7185c71
DP		 868 flashaddr = NETXEN_BOOTLD_START;
869
870 for (i = 0; i < size; i++) {
871 data = cpu_to_le64(ptr64[i]);
f50330f9
AKS		 872
873 if (adapter->pci_mem_write(adapter, flashaddr, data))
1f5e055d
AKS		 874 return -EIO;
875
f7185c71
DP		 876 flashaddr += 8;
877 }
878
f50330f9 879 size = (__force u32)nx_get_fw_size(adapter) / 8;
f7185c71 880
f50330f9 881 ptr64 = (u64 *)nx_get_fw_offs(adapter);
f7185c71
DP		 882 flashaddr = NETXEN_IMAGE_START;
883
884 for (i = 0; i < size; i++) {
885 data = cpu_to_le64(ptr64[i]);
886
887 if (adapter->pci_mem_write(adapter,
1f5e055d 888 flashaddr, data))
f7185c71
DP		 889 return -EIO;
890
891 flashaddr += 8;
892 }
893 } else {
f78c0850
AKS		 894 u64 data;
895 u32 hi, lo;
f7185c71 896
f78c0850 897 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
f7185c71
DP		 898 flashaddr = NETXEN_BOOTLD_START;
899
900 for (i = 0; i < size; i++) {
901 if (netxen_rom_fast_read(adapter,
1f5e055d 902 flashaddr, (int *)&lo) != 0)
f78c0850
AKS		 903 return -EIO;
904 if (netxen_rom_fast_read(adapter,
1f5e055d 905 flashaddr + 4, (int *)&hi) != 0)
f7185c71
DP		 906 return -EIO;
907
f78c0850
AKS		 908 /* hi, lo are already in host endian byteorder */
909 data = (((u64)hi << 32) | lo);
910
f7185c71 911 if (adapter->pci_mem_write(adapter,
1f5e055d 912 flashaddr, data))
f7185c71
DP		 913 return -EIO;
914
f78c0850 915 flashaddr += 8;
f7185c71
DP		 916 }
917 }
918 msleep(1);
919
0be367bd
AKS		 920 if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) {
921 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x18, 0x1020);
922 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001e);
923 } else if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
f7185c71
DP		 924 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
925 else {
926 NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
927 NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
928 }
929
930 return 0;
931}
932
933static int
f50330f9 934netxen_validate_firmware(struct netxen_adapter *adapter)
f7185c71
DP		 935{
936 __le32 val;
f50330f9 937 u32 ver, min_ver, bios, min_size;
f7185c71
DP		 938 struct pci_dev *pdev = adapter->pdev;
939 const struct firmware *fw = adapter->fw;
f50330f9 940 u8 fw_type = adapter->fw_type;
f7185c71 941
f50330f9
AKS		 942 if (fw_type == NX_UNIFIED_ROMIMAGE) {
943 if (nx_set_product_offs(adapter))
944 return -EINVAL;
945
946 min_size = NX_UNI_FW_MIN_SIZE;
947 } else {
948 val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
949 if ((__force u32)val != NETXEN_BDINFO_MAGIC)
950 return -EINVAL;
f7185c71 951
f50330f9
AKS		 952 min_size = NX_FW_MIN_SIZE;
953 }
954
955 if (fw->size < min_size)
f7185c71
DP		 956 return -EINVAL;
957
f50330f9 958 val = nx_get_fw_version(adapter);
f7185c71
DP		 959
960 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
961 min_ver = NETXEN_VERSION_CODE(4, 0, 216);
962 else
963 min_ver = NETXEN_VERSION_CODE(3, 4, 216);
964
98e31bb0 965 ver = NETXEN_DECODE_VERSION(val);
f7185c71 966
98e31bb0 967 if ((_major(ver) > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
f7185c71
DP		 968 dev_err(&pdev->dev,
969 "%s: firmware version %d.%d.%d unsupported\n",
f50330f9 970 fw_name[fw_type], _major(ver), _minor(ver), _build(ver));
f7185c71
DP		 971 return -EINVAL;
972 }
973
f50330f9 974 val = nx_get_bios_version(adapter);
f7185c71
DP		 975 netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
976 if ((__force u32)val != bios) {
977 dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
f50330f9 978 fw_name[fw_type]);
f7185c71
DP		 979 return -EINVAL;
980 }
981
982 /* check if flashed firmware is newer */
983 if (netxen_rom_fast_read(adapter,
984 NX_FW_VERSION_OFFSET, (int *)&val))
985 return -EIO;
98e31bb0
DP		 986 val = NETXEN_DECODE_VERSION(val);
987 if (val > ver) {
988 dev_info(&pdev->dev, "%s: firmware is older than flash\n",
f50330f9 989 fw_name[fw_type]);
f7185c71 990 return -EINVAL;
98e31bb0 991 }
f7185c71
DP		 992
993 NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
994 return 0;
995}
996
f50330f9
AKS		 997static void
998nx_get_next_fwtype(struct netxen_adapter *adapter)
999{
1000 u8 fw_type;
1001
1002 switch (adapter->fw_type) {
1003 case NX_UNKNOWN_ROMIMAGE:
1004 fw_type = NX_UNIFIED_ROMIMAGE;
1005 break;
1006
1007 case NX_UNIFIED_ROMIMAGE:
1008 if (NX_IS_REVISION_P3P(adapter->ahw.revision_id))
1009 fw_type = NX_FLASH_ROMIMAGE;
1010 else if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1011 fw_type = NX_P2_MN_ROMIMAGE;
1012 else if (netxen_p3_has_mn(adapter))
1013 fw_type = NX_P3_MN_ROMIMAGE;
1014 else
1015 fw_type = NX_P3_CT_ROMIMAGE;
1016 break;
1017
1018 case NX_P3_MN_ROMIMAGE:
1019 fw_type = NX_P3_CT_ROMIMAGE;
1020 break;
1021
1022 case NX_P2_MN_ROMIMAGE:
1023 case NX_P3_CT_ROMIMAGE:
1024 default:
1025 fw_type = NX_FLASH_ROMIMAGE;
1026 break;
1027 }
1028
1029 adapter->fw_type = fw_type;
1030}
1031
6598b169
DP		 1032static int
1033netxen_p3_has_mn(struct netxen_adapter *adapter)
f7185c71
DP		 1034{
1035 u32 capability, flashed_ver;
f7185c71
DP		 1036 capability = 0;
1037
634d7df8
DP		 1038 /* NX2031 always had MN */
1039 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1040 return 1;
1041
f7185c71
DP		 1042 netxen_rom_fast_read(adapter,
1043 NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
98e31bb0
DP		 1044 flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
1045
f7185c71 1046 if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
6598b169 1047
f7185c71 1048 capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
6598b169
DP		 1049 if (capability & NX_PEG_TUNE_MN_PRESENT)
1050 return 1;
1051 }
1052 return 0;
1053}
1054
1055void netxen_request_firmware(struct netxen_adapter *adapter)
1056{
6598b169
DP		 1057 struct pci_dev *pdev = adapter->pdev;
1058 int rc = 0;
1059
f50330f9 1060 adapter->fw_type = NX_UNKNOWN_ROMIMAGE;
f7185c71 1061
f50330f9
AKS		 1062next:
1063 nx_get_next_fwtype(adapter);
f7185c71 1064
f50330f9 1065 if (adapter->fw_type == NX_FLASH_ROMIMAGE) {
f7185c71 1066 adapter->fw = NULL;
f50330f9
AKS		 1067 } else {
1068 rc = request_firmware(&adapter->fw,
1069 fw_name[adapter->fw_type], &pdev->dev);
1070 if (rc != 0)
1071 goto next;
1072
1073 rc = netxen_validate_firmware(adapter);
1074 if (rc != 0) {
1075 release_firmware(adapter->fw);
f7185c71 1076 msleep(1);
f50330f9 1077 goto next;
f7185c71 1078 }
f7185c71 1079 }
f7185c71
DP		 1080}
1081
1082
1083void
1084netxen_release_firmware(struct netxen_adapter *adapter)
1085{
1086 if (adapter->fw)
1087 release_firmware(adapter->fw);
db4cfd8a 1088 adapter->fw = NULL;
f7185c71
DP		 1089}
1090
83ac51fa 1091int netxen_init_dummy_dma(struct netxen_adapter *adapter)
ed25ffa1 1092{
83ac51fa
DP		 1093 u64 addr;
1094 u32 hi, lo;
ed25ffa1 1095
83ac51fa
DP		 1096 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
1097 return 0;
1098
1099 adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
ed25ffa1
AK		 1100 NETXEN_HOST_DUMMY_DMA_SIZE,
1101 &adapter->dummy_dma.phys_addr);
1102 if (adapter->dummy_dma.addr == NULL) {
83ac51fa
DP		 1103 dev_err(&adapter->pdev->dev,
1104 "ERROR: Could not allocate dummy DMA memory\n");
ed25ffa1
AK		 1105 return -ENOMEM;
1106 }
1107
1108 addr = (uint64_t) adapter->dummy_dma.phys_addr;
1109 hi = (addr >> 32) & 0xffffffff;
1110 lo = addr & 0xffffffff;
1111
f98a9f69
DP		 1112 NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
1113 NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
ed25ffa1
AK		 1114
1115 return 0;
1116}
1117
83ac51fa
DP		 1118/*
1119 * NetXen DMA watchdog control:
1120 *
1121 * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
1122 * Bit 1 : disable_request => 1 req disable dma watchdog
1123 * Bit 2 : enable_request => 1 req enable dma watchdog
1124 * Bit 3-31 : unused
1125 */
1126void netxen_free_dummy_dma(struct netxen_adapter *adapter)
ed25ffa1 1127{
15eef1e1 1128 int i = 100;
83ac51fa
DP		 1129 u32 ctrl;
1130
1131 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
1132 return;
15eef1e1
DP		 1133
1134 if (!adapter->dummy_dma.addr)
1135 return;
439b454e 1136
83ac51fa
DP		 1137 ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
1138 if ((ctrl & 0x1) != 0) {
1139 NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
1140
1141 while ((ctrl & 0x1) != 0) {
1142
439b454e 1143 msleep(50);
83ac51fa
DP		 1144
1145 ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
1146
1147 if (--i == 0)
439b454e 1148 break;
83ac51fa 1149 };
15eef1e1 1150 }
439b454e 1151
15eef1e1
DP		 1152 if (i) {
1153 pci_free_consistent(adapter->pdev,
1154 NETXEN_HOST_DUMMY_DMA_SIZE,
1155 adapter->dummy_dma.addr,
1156 adapter->dummy_dma.phys_addr);
1157 adapter->dummy_dma.addr = NULL;
83ac51fa
DP		 1158 } else
1159 dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
ed25ffa1
AK		 1160}
1161
96acb6eb 1162int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
3d396eb1
AK		 1163{
1164 u32 val = 0;
2956640d 1165 int retries = 60;
3d396eb1 1166
96f2ebd2
DP		 1167 if (pegtune_val)
1168 return 0;
1169
1170 do {
1171 val = NXRD32(adapter, CRB_CMDPEG_STATE);
96acb6eb 1172
96f2ebd2
DP		 1173 switch (val) {
1174 case PHAN_INITIALIZE_COMPLETE:
1175 case PHAN_INITIALIZE_ACK:
1176 return 0;
1177 case PHAN_INITIALIZE_FAILED:
1178 goto out_err;
1179 default:
1180 break;
1181 }
96acb6eb 1182
96f2ebd2 1183 msleep(500);
2956640d 1184
96f2ebd2 1185 } while (--retries);
2956640d 1186
96f2ebd2 1187 NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
96acb6eb 1188
96f2ebd2
DP		 1189out_err:
1190 dev_warn(&adapter->pdev->dev, "firmware init failed\n");
1191 return -EIO;
3d396eb1
AK		 1192}
1193
56a00787
DP		 1194static int
1195netxen_receive_peg_ready(struct netxen_adapter *adapter)
2956640d
DP		 1196{
1197 u32 val = 0;
1198 int retries = 2000;
1199
1200 do {
f98a9f69 1201 val = NXRD32(adapter, CRB_RCVPEG_STATE);
2956640d
DP		 1202
1203 if (val == PHAN_PEG_RCV_INITIALIZED)
1204 return 0;
1205
1206 msleep(10);
1207
1208 } while (--retries);
1209
1210 if (!retries) {
1211 printk(KERN_ERR "Receive Peg initialization not "
1212 "complete, state: 0x%x.\n", val);
1213 return -EIO;
1214 }
1215
1216 return 0;
1217}
1218
56a00787
DP		 1219int netxen_init_firmware(struct netxen_adapter *adapter)
1220{
1221 int err;
1222
1223 err = netxen_receive_peg_ready(adapter);
1224 if (err)
1225 return err;
1226
f98a9f69
DP		 1227 NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
1228 NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
1229 NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
1230 NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
56a00787
DP		 1231
1232 return err;
1233}
1234
3bf26ce3
DP		 1235static void
1236netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
1237{
1238 u32 cable_OUI;
1239 u16 cable_len;
1240 u16 link_speed;
1241 u8 link_status, module, duplex, autoneg;
1242 struct net_device *netdev = adapter->netdev;
1243
1244 adapter->has_link_events = 1;
1245
1246 cable_OUI = msg->body[1] & 0xffffffff;
1247 cable_len = (msg->body[1] >> 32) & 0xffff;
1248 link_speed = (msg->body[1] >> 48) & 0xffff;
1249
1250 link_status = msg->body[2] & 0xff;
1251 duplex = (msg->body[2] >> 16) & 0xff;
1252 autoneg = (msg->body[2] >> 24) & 0xff;
1253
1254 module = (msg->body[2] >> 8) & 0xff;
1255 if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
1256 printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
1257 netdev->name, cable_OUI, cable_len);
1258 } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
1259 printk(KERN_INFO "%s: unsupported cable length %d\n",
1260 netdev->name, cable_len);
1261 }
1262
1263 netxen_advert_link_change(adapter, link_status);
1264
1265 /* update link parameters */
1266 if (duplex == LINKEVENT_FULL_DUPLEX)
1267 adapter->link_duplex = DUPLEX_FULL;
1268 else
1269 adapter->link_duplex = DUPLEX_HALF;
1270 adapter->module_type = module;
1271 adapter->link_autoneg = autoneg;
1272 adapter->link_speed = link_speed;
1273}
1274
1275static void
1276netxen_handle_fw_message(int desc_cnt, int index,
1277 struct nx_host_sds_ring *sds_ring)
1278{
1279 nx_fw_msg_t msg;
1280 struct status_desc *desc;
1281 int i = 0, opcode;
1282
1283 while (desc_cnt > 0 && i < 8) {
1284 desc = &sds_ring->desc_head[index];
1285 msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
1286 msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
1287
1288 index = get_next_index(index, sds_ring->num_desc);
1289 desc_cnt--;
1290 }
1291
1292 opcode = netxen_get_nic_msg_opcode(msg.body[0]);
1293 switch (opcode) {
1294 case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
1295 netxen_handle_linkevent(sds_ring->adapter, &msg);
1296 break;
1297 default:
1298 break;
1299 }
1300}
1301
d8b100c5
DP		 1302static int
1303netxen_alloc_rx_skb(struct netxen_adapter *adapter,
1304 struct nx_host_rds_ring *rds_ring,
1305 struct netxen_rx_buffer *buffer)
1306{
1307 struct sk_buff *skb;
1308 dma_addr_t dma;
1309 struct pci_dev *pdev = adapter->pdev;
1310
1311 buffer->skb = dev_alloc_skb(rds_ring->skb_size);
1312 if (!buffer->skb)
1313 return 1;
1314
1315 skb = buffer->skb;
1316
1317 if (!adapter->ahw.cut_through)
1318 skb_reserve(skb, 2);
1319
1320 dma = pci_map_single(pdev, skb->data,
1321 rds_ring->dma_size, PCI_DMA_FROMDEVICE);
1322
1323 if (pci_dma_mapping_error(pdev, dma)) {
1324 dev_kfree_skb_any(skb);
1325 buffer->skb = NULL;
1326 return 1;
1327 }
1328
1329 buffer->skb = skb;
1330 buffer->dma = dma;
1331 buffer->state = NETXEN_BUFFER_BUSY;
1332
1333 return 0;
1334}
1335
d9e651bc
DP		 1336static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
1337 struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
1338{
1339 struct netxen_rx_buffer *buffer;
1340 struct sk_buff *skb;
1341
1342 buffer = &rds_ring->rx_buf_arr[index];
1343
1344 pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
1345 PCI_DMA_FROMDEVICE);
1346
1347 skb = buffer->skb;
1348 if (!skb)
1349 goto no_skb;
1350
1351 if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
1352 adapter->stats.csummed++;
1353 skb->ip_summed = CHECKSUM_UNNECESSARY;
1354 } else
1355 skb->ip_summed = CHECKSUM_NONE;
1356
1357 skb->dev = adapter->netdev;
1358
1359 buffer->skb = NULL;
d9e651bc
DP		 1360no_skb:
1361 buffer->state = NETXEN_BUFFER_FREE;
d9e651bc
DP		 1362 return skb;
1363}
1364
d8b100c5 1365static struct netxen_rx_buffer *
9b3ef55c 1366netxen_process_rcv(struct netxen_adapter *adapter,
c1c00ab8
DP		 1367 struct nx_host_sds_ring *sds_ring,
1368 int ring, u64 sts_data0)
3d396eb1 1369{
3176ff3e 1370 struct net_device *netdev = adapter->netdev;
becf46a0 1371 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
3d396eb1
AK		 1372 struct netxen_rx_buffer *buffer;
1373 struct sk_buff *skb;
c1c00ab8
DP		 1374 struct nx_host_rds_ring *rds_ring;
1375 int index, length, cksum, pkt_offset;
3d396eb1 1376
c1c00ab8
DP		 1377 if (unlikely(ring >= adapter->max_rds_rings))
1378 return NULL;
1379
1380 rds_ring = &recv_ctx->rds_rings[ring];
1381
1382 index = netxen_get_sts_refhandle(sts_data0);
1383 if (unlikely(index >= rds_ring->num_desc))
d8b100c5 1384 return NULL;
438627c7 1385
48bfd1e0 1386 buffer = &rds_ring->rx_buf_arr[index];
3d396eb1 1387
c1c00ab8
DP		 1388 length = netxen_get_sts_totallength(sts_data0);
1389 cksum = netxen_get_sts_status(sts_data0);
1390 pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
1391
d9e651bc
DP		 1392 skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
1393 if (!skb)
d8b100c5 1394 return buffer;
200eef20 1395
9b3ef55c
DP		 1396 if (length > rds_ring->skb_size)
1397 skb_put(skb, rds_ring->skb_size);
1398 else
1399 skb_put(skb, length);
d9e651bc 1400
9b3ef55c
DP		 1401
1402 if (pkt_offset)
1403 skb_pull(skb, pkt_offset);
ed25ffa1 1404
bc75e5bf 1405 skb->truesize = skb->len + sizeof(struct sk_buff);
3d396eb1
AK		 1406 skb->protocol = eth_type_trans(skb, netdev);
1407
a92e9e65 1408 napi_gro_receive(&sds_ring->napi, skb);
d9e651bc 1409
1bb482f8 1410 adapter->stats.rx_pkts++;
0ddc110c 1411 adapter->stats.rxbytes += length;
d8b100c5
DP		 1412
1413 return buffer;
3d396eb1
AK		 1414}
1415
c1c00ab8
DP		 1416#define TCP_HDR_SIZE 20
1417#define TCP_TS_OPTION_SIZE 12
1418#define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
1419
1420static struct netxen_rx_buffer *
1421netxen_process_lro(struct netxen_adapter *adapter,
1422 struct nx_host_sds_ring *sds_ring,
1423 int ring, u64 sts_data0, u64 sts_data1)
1424{
1425 struct net_device *netdev = adapter->netdev;
1426 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
1427 struct netxen_rx_buffer *buffer;
1428 struct sk_buff *skb;
1429 struct nx_host_rds_ring *rds_ring;
1430 struct iphdr *iph;
1431 struct tcphdr *th;
1432 bool push, timestamp;
1433 int l2_hdr_offset, l4_hdr_offset;
1434 int index;
1435 u16 lro_length, length, data_offset;
1436 u32 seq_number;
1437
1438 if (unlikely(ring > adapter->max_rds_rings))
1439 return NULL;
1440
1441 rds_ring = &recv_ctx->rds_rings[ring];
1442
1443 index = netxen_get_lro_sts_refhandle(sts_data0);
1444 if (unlikely(index > rds_ring->num_desc))
1445 return NULL;
1446
1447 buffer = &rds_ring->rx_buf_arr[index];
1448
1449 timestamp = netxen_get_lro_sts_timestamp(sts_data0);
1450 lro_length = netxen_get_lro_sts_length(sts_data0);
1451 l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
1452 l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
1453 push = netxen_get_lro_sts_push_flag(sts_data0);
1454 seq_number = netxen_get_lro_sts_seq_number(sts_data1);
1455
1456 skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
1457 if (!skb)
1458 return buffer;
1459
1460 if (timestamp)
1461 data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
1462 else
1463 data_offset = l4_hdr_offset + TCP_HDR_SIZE;
1464
1465 skb_put(skb, lro_length + data_offset);
1466
bc75e5bf 1467 skb->truesize = skb->len + sizeof(struct sk_buff) + skb_headroom(skb);
c1c00ab8
DP		 1468
1469 skb_pull(skb, l2_hdr_offset);
1470 skb->protocol = eth_type_trans(skb, netdev);
1471
1472 iph = (struct iphdr *)skb->data;
1473 th = (struct tcphdr *)(skb->data + (iph->ihl << 2));
1474
1475 length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
1476 iph->tot_len = htons(length);
1477 iph->check = 0;
1478 iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
1479 th->psh = push;
1480 th->seq = htonl(seq_number);
1481
1bb482f8
NK		 1482 length = skb->len;
1483
c1c00ab8
DP		 1484 netif_receive_skb(skb);
1485
1bb482f8
NK		 1486 adapter->stats.lro_pkts++;
1487 adapter->stats.rxbytes += length;
1488
c1c00ab8
DP		 1489 return buffer;
1490}
1491
d8b100c5
DP		 1492#define netxen_merge_rx_buffers(list, head) \
1493 do { list_splice_tail_init(list, head); } while (0);
1494
becf46a0 1495int
d8b100c5 1496netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
3d396eb1 1497{
d8b100c5
DP		 1498 struct netxen_adapter *adapter = sds_ring->adapter;
1499
1500 struct list_head *cur;
1501
0ddc110c 1502 struct status_desc *desc;
d8b100c5
DP		 1503 struct netxen_rx_buffer *rxbuf;
1504
1505 u32 consumer = sds_ring->consumer;
1506
9b3ef55c 1507 int count = 0;
c1c00ab8
DP		 1508 u64 sts_data0, sts_data1;
1509 int opcode, ring = 0, desc_cnt;
3d396eb1 1510
3d396eb1 1511 while (count < max) {
d8b100c5 1512 desc = &sds_ring->desc_head[consumer];
c1c00ab8 1513 sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
0ddc110c 1514
c1c00ab8 1515 if (!(sts_data0 & STATUS_OWNER_HOST))
3d396eb1 1516 break;
d9e651bc 1517
c1c00ab8 1518 desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
3bf26ce3 1519
c1c00ab8 1520 opcode = netxen_get_sts_opcode(sts_data0);
d9e651bc 1521
3bf26ce3
DP		 1522 switch (opcode) {
1523 case NETXEN_NIC_RXPKT_DESC:
1524 case NETXEN_OLD_RXPKT_DESC:
6598b169 1525 case NETXEN_NIC_SYN_OFFLOAD:
c1c00ab8
DP		 1526 ring = netxen_get_sts_type(sts_data0);
1527 rxbuf = netxen_process_rcv(adapter, sds_ring,
1528 ring, sts_data0);
1529 break;
1530 case NETXEN_NIC_LRO_DESC:
1531 ring = netxen_get_lro_sts_type(sts_data0);
1532 sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
1533 rxbuf = netxen_process_lro(adapter, sds_ring,
1534 ring, sts_data0, sts_data1);
3bf26ce3
DP		 1535 break;
1536 case NETXEN_NIC_RESPONSE_DESC:
1537 netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
1538 default:
1539 goto skip;
1540 }
1541
1542 WARN_ON(desc_cnt > 1);
1543
d8b100c5
DP		 1544 if (rxbuf)
1545 list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
1546
3bf26ce3
DP		 1547skip:
1548 for (; desc_cnt > 0; desc_cnt--) {
1549 desc = &sds_ring->desc_head[consumer];
1550 desc->status_desc_data[0] =
1551 cpu_to_le64(STATUS_OWNER_PHANTOM);
1552 consumer = get_next_index(consumer, sds_ring->num_desc);
1553 }
3d396eb1
AK		 1554 count++;
1555 }
0ddc110c 1556
d8b100c5
DP		 1557 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1558 struct nx_host_rds_ring *rds_ring =
1559 &adapter->recv_ctx.rds_rings[ring];
1560
1561 if (!list_empty(&sds_ring->free_list[ring])) {
1562 list_for_each(cur, &sds_ring->free_list[ring]) {
1563 rxbuf = list_entry(cur,
1564 struct netxen_rx_buffer, list);
1565 netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
1566 }
1567 spin_lock(&rds_ring->lock);
1568 netxen_merge_rx_buffers(&sds_ring->free_list[ring],
1569 &rds_ring->free_list);
1570 spin_unlock(&rds_ring->lock);
1571 }
1572
1573 netxen_post_rx_buffers_nodb(adapter, rds_ring);
1574 }
3d396eb1 1575
3d396eb1 1576 if (count) {
d8b100c5 1577 sds_ring->consumer = consumer;
195c5f98 1578 NXWRIO(adapter, sds_ring->crb_sts_consumer, consumer);
3d396eb1
AK		 1579 }
1580
1581 return count;
1582}
1583
1584/* Process Command status ring */
05aaa02d 1585int netxen_process_cmd_ring(struct netxen_adapter *adapter)
3d396eb1 1586{
d877f1e3 1587 u32 sw_consumer, hw_consumer;
ba53e6b4 1588 int count = 0, i;
3d396eb1 1589 struct netxen_cmd_buffer *buffer;
ba53e6b4
DP		 1590 struct pci_dev *pdev = adapter->pdev;
1591 struct net_device *netdev = adapter->netdev;
3d396eb1 1592 struct netxen_skb_frag *frag;
ba53e6b4 1593 int done = 0;
4ea528a1 1594 struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
3d396eb1 1595
d8b100c5
DP		 1596 if (!spin_trylock(&adapter->tx_clean_lock))
1597 return 1;
1598
d877f1e3 1599 sw_consumer = tx_ring->sw_consumer;
d877f1e3 1600 hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
3d396eb1 1601
d877f1e3
DP		 1602 while (sw_consumer != hw_consumer) {
1603 buffer = &tx_ring->cmd_buf_arr[sw_consumer];
53a01e00 1604 if (buffer->skb) {
1605 frag = &buffer->frag_array[0];
3d396eb1
AK		 1606 pci_unmap_single(pdev, frag->dma, frag->length,
1607 PCI_DMA_TODEVICE);
96acb6eb 1608 frag->dma = 0ULL;
3d396eb1 1609 for (i = 1; i < buffer->frag_count; i++) {
3d396eb1
AK		 1610 frag++; /* Get the next frag */
1611 pci_unmap_page(pdev, frag->dma, frag->length,
1612 PCI_DMA_TODEVICE);
96acb6eb 1613 frag->dma = 0ULL;
3d396eb1
AK		 1614 }
1615
ba53e6b4 1616 adapter->stats.xmitfinished++;
53a01e00 1617 dev_kfree_skb_any(buffer->skb);
1618 buffer->skb = NULL;
3d396eb1
AK		 1619 }
1620
d877f1e3 1621 sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
ba53e6b4
DP		 1622 if (++count >= MAX_STATUS_HANDLE)
1623 break;
3d396eb1 1624 }
3d396eb1 1625
22527864 1626 if (count && netif_running(netdev)) {
cb2107be
DP		 1627 tx_ring->sw_consumer = sw_consumer;
1628
ba53e6b4 1629 smp_mb();
cb2107be 1630
22527864 1631 if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) {
b2af9cb0 1632 __netif_tx_lock(tx_ring->txq, smp_processor_id());
74c520da 1633 if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH) {
cb2107be 1634 netif_wake_queue(netdev);
74c520da
AKS		 1635 adapter->tx_timeo_cnt = 0;
1636 }
b2af9cb0 1637 __netif_tx_unlock(tx_ring->txq);
3d396eb1
AK		 1638 }
1639 }
ed25ffa1
AK		 1640 /*
1641 * If everything is freed up to consumer then check if the ring is full
1642 * If the ring is full then check if more needs to be freed and
1643 * schedule the call back again.
1644 *
1645 * This happens when there are 2 CPUs. One could be freeing and the
1646 * other filling it. If the ring is full when we get out of here and
1647 * the card has already interrupted the host then the host can miss the
1648 * interrupt.
1649 *
1650 * There is still a possible race condition and the host could miss an
1651 * interrupt. The card has to take care of this.
1652 */
d877f1e3
DP		 1653 hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
1654 done = (sw_consumer == hw_consumer);
d8b100c5 1655 spin_unlock(&adapter->tx_clean_lock);
3d396eb1 1656
ed25ffa1 1657 return (done);
3d396eb1
AK		 1658}
1659
becf46a0 1660void
d8b100c5
DP		 1661netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1662 struct nx_host_rds_ring *rds_ring)
3d396eb1 1663{
3d396eb1
AK		 1664 struct rcv_desc *pdesc;
1665 struct netxen_rx_buffer *buffer;
d8b100c5 1666 int producer, count = 0;
ed25ffa1 1667 netxen_ctx_msg msg = 0;
d9e651bc 1668 struct list_head *head;
3d396eb1 1669
48bfd1e0 1670 producer = rds_ring->producer;
d9e651bc 1671
d8b100c5
DP		 1672 spin_lock(&rds_ring->lock);
1673 head = &rds_ring->free_list;
d9e651bc
DP		 1674 while (!list_empty(head)) {
1675
d8b100c5 1676 buffer = list_entry(head->next, struct netxen_rx_buffer, list);
6f703406 1677
d8b100c5
DP		 1678 if (!buffer->skb) {
1679 if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
1680 break;
6f703406
DP		 1681 }
1682
1683 count++;
d9e651bc
DP		 1684 list_del(&buffer->list);
1685
ed25ffa1 1686 /* make a rcv descriptor */
6f703406 1687 pdesc = &rds_ring->desc_head[producer];
d8b100c5 1688 pdesc->addr_buffer = cpu_to_le64(buffer->dma);
ed33ebe4 1689 pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
48bfd1e0 1690 pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
6f703406 1691
438627c7 1692 producer = get_next_index(producer, rds_ring->num_desc);
ed25ffa1 1693 }
d8b100c5 1694 spin_unlock(&rds_ring->lock);
9b3ef55c 1695
ed25ffa1 1696 if (count) {
48bfd1e0 1697 rds_ring->producer = producer;
195c5f98 1698 NXWRIO(adapter, rds_ring->crb_rcv_producer,
438627c7 1699 (producer-1) & (rds_ring->num_desc-1));
48bfd1e0 1700
4f96b988 1701 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
ed25ffa1
AK		 1702 /*
1703 * Write a doorbell msg to tell phanmon of change in
1704 * receive ring producer
48bfd1e0 1705 * Only for firmware version < 4.0.0
ed25ffa1
AK		 1706 */
1707 netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
1708 netxen_set_msg_privid(msg);
1709 netxen_set_msg_count(msg,
438627c7
DP		 1710 ((producer - 1) &
1711 (rds_ring->num_desc - 1)));
3176ff3e 1712 netxen_set_msg_ctxid(msg, adapter->portnum);
ed25ffa1 1713 netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
f03b0ebd
DP		 1714 NXWRIO(adapter, DB_NORMALIZE(adapter,
1715 NETXEN_RCV_PRODUCER_OFFSET), msg);
48bfd1e0 1716 }
ed25ffa1
AK		 1717 }
1718}
1719
becf46a0 1720static void
d8b100c5
DP		 1721netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
1722 struct nx_host_rds_ring *rds_ring)
ed25ffa1 1723{
ed25ffa1
AK		 1724 struct rcv_desc *pdesc;
1725 struct netxen_rx_buffer *buffer;
d8b100c5 1726 int producer, count = 0;
d9e651bc 1727 struct list_head *head;
ed25ffa1 1728
48bfd1e0 1729 producer = rds_ring->producer;
d8b100c5
DP		 1730 if (!spin_trylock(&rds_ring->lock))
1731 return;
1732
d9e651bc 1733 head = &rds_ring->free_list;
d9e651bc
DP		 1734 while (!list_empty(head)) {
1735
d8b100c5 1736 buffer = list_entry(head->next, struct netxen_rx_buffer, list);
6f703406 1737
d8b100c5
DP		 1738 if (!buffer->skb) {
1739 if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
1740 break;
6f703406
DP		 1741 }
1742
1743 count++;
d9e651bc
DP		 1744 list_del(&buffer->list);
1745
3d396eb1 1746 /* make a rcv descriptor */
6f703406 1747 pdesc = &rds_ring->desc_head[producer];
ed33ebe4 1748 pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
48bfd1e0 1749 pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
3d396eb1 1750 pdesc->addr_buffer = cpu_to_le64(buffer->dma);
6f703406 1751
438627c7 1752 producer = get_next_index(producer, rds_ring->num_desc);
3d396eb1
AK		 1753 }
1754
3d396eb1 1755 if (count) {
48bfd1e0 1756 rds_ring->producer = producer;
195c5f98 1757 NXWRIO(adapter, rds_ring->crb_rcv_producer,
438627c7 1758 (producer - 1) & (rds_ring->num_desc - 1));
3d396eb1 1759 }
d8b100c5 1760 spin_unlock(&rds_ring->lock);
3d396eb1
AK		 1761}
1762
3d396eb1
AK		 1763void netxen_nic_clear_stats(struct netxen_adapter *adapter)
1764{
3d396eb1 1765 memset(&adapter->stats, 0, sizeof(adapter->stats));
3176ff3e 1766 return;
3d396eb1
AK		 1767}
1768
kernel source for telekom puls (alcatel/mediatek)