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3d396eb1 AK |
1 | /* |
2 | * Copyright (C) 2003 - 2006 NetXen, Inc. | |
3 | * All rights reserved. | |
80922fbc | 4 | * |
3d396eb1 AK |
5 | * This program is free software; you can redistribute it and/or |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
80922fbc | 9 | * |
3d396eb1 AK |
10 | * This program is distributed in the hope that it will be useful, but |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
80922fbc | 14 | * |
3d396eb1 AK |
15 | * You should have received a copy of the GNU General Public License |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
18 | * MA 02111-1307, USA. | |
80922fbc | 19 | * |
3d396eb1 AK |
20 | * The full GNU General Public License is included in this distribution |
21 | * in the file called LICENSE. | |
80922fbc | 22 | * |
3d396eb1 AK |
23 | * Contact Information: |
24 | * info@netxen.com | |
25 | * NetXen, | |
26 | * 3965 Freedom Circle, Fourth floor, | |
27 | * Santa Clara, CA 95054 | |
28 | */ | |
29 | ||
30 | #ifndef _NETXEN_NIC_H_ | |
31 | #define _NETXEN_NIC_H_ | |
32 | ||
3d396eb1 AK |
33 | #include <linux/module.h> |
34 | #include <linux/kernel.h> | |
35 | #include <linux/types.h> | |
36 | #include <linux/compiler.h> | |
37 | #include <linux/slab.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/init.h> | |
40 | #include <linux/ioport.h> | |
41 | #include <linux/pci.h> | |
42 | #include <linux/netdevice.h> | |
43 | #include <linux/etherdevice.h> | |
44 | #include <linux/ip.h> | |
45 | #include <linux/in.h> | |
46 | #include <linux/tcp.h> | |
47 | #include <linux/skbuff.h> | |
48 | #include <linux/version.h> | |
49 | ||
50 | #include <linux/ethtool.h> | |
51 | #include <linux/mii.h> | |
52 | #include <linux/interrupt.h> | |
53 | #include <linux/timer.h> | |
54 | ||
55 | #include <linux/mm.h> | |
56 | #include <linux/mman.h> | |
57 | ||
58 | #include <asm/system.h> | |
59 | #include <asm/io.h> | |
60 | #include <asm/byteorder.h> | |
61 | #include <asm/uaccess.h> | |
62 | #include <asm/pgtable.h> | |
63 | ||
64 | #include "netxen_nic_hw.h" | |
65 | ||
184231bd | 66 | #define NETXEN_NIC_BUILD_NO "2" |
ed25ffa1 | 67 | #define _NETXEN_NIC_LINUX_MAJOR 3 |
3d396eb1 | 68 | #define _NETXEN_NIC_LINUX_MINOR 3 |
90f8b1d2 AK |
69 | #define _NETXEN_NIC_LINUX_SUBVERSION 3 |
70 | #define NETXEN_NIC_LINUX_VERSIONID "3.3.3" "-" NETXEN_NIC_BUILD_NO | |
3d396eb1 AK |
71 | |
72 | #define RCV_DESC_RINGSIZE \ | |
73 | (sizeof(struct rcv_desc) * adapter->max_rx_desc_count) | |
74 | #define STATUS_DESC_RINGSIZE \ | |
75 | (sizeof(struct status_desc)* adapter->max_rx_desc_count) | |
ed25ffa1 AK |
76 | #define LRO_DESC_RINGSIZE \ |
77 | (sizeof(rcvDesc_t) * adapter->max_lro_rx_desc_count) | |
3d396eb1 AK |
78 | #define TX_RINGSIZE \ |
79 | (sizeof(struct netxen_cmd_buffer) * adapter->max_tx_desc_count) | |
80 | #define RCV_BUFFSIZE \ | |
81 | (sizeof(struct netxen_rx_buffer) * rcv_desc->max_rx_desc_count) | |
82 | #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a))) | |
83 | ||
ed25ffa1 AK |
84 | #define NETXEN_NETDEV_STATUS 0x1 |
85 | #define NETXEN_RCV_PRODUCER_OFFSET 0 | |
86 | #define NETXEN_RCV_PEG_DB_ID 2 | |
87 | #define NETXEN_HOST_DUMMY_DMA_SIZE 1024 | |
3d396eb1 AK |
88 | |
89 | #define ADDR_IN_WINDOW1(off) \ | |
90 | ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0 | |
ed25ffa1 AK |
91 | /* |
92 | * In netxen_nic_down(), we must wait for any pending callback requests into | |
93 | * netxen_watchdog_task() to complete; eg otherwise the watchdog_timer could be | |
94 | * reenabled right after it is deleted in netxen_nic_down(). FLUSH_SCHEDULED_WORK() | |
95 | * does this synchronization. | |
96 | * | |
97 | * Normally, schedule_work()/flush_scheduled_work() could have worked, but | |
98 | * netxen_nic_close() is invoked with kernel rtnl lock held. netif_carrier_off() | |
99 | * call in netxen_nic_close() triggers a schedule_work(&linkwatch_work), and a | |
100 | * subsequent call to flush_scheduled_work() in netxen_nic_down() would cause | |
101 | * linkwatch_event() to be executed which also attempts to acquire the rtnl | |
102 | * lock thus causing a deadlock. | |
103 | */ | |
104 | ||
105 | #define SCHEDULE_WORK(tp) queue_work(netxen_workq, tp) | |
106 | #define FLUSH_SCHEDULED_WORK() flush_workqueue(netxen_workq) | |
107 | extern struct workqueue_struct *netxen_workq; | |
3d396eb1 AK |
108 | |
109 | /* | |
110 | * normalize a 64MB crb address to 32MB PCI window | |
111 | * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1 | |
112 | */ | |
80922fbc AK |
113 | #define NETXEN_CRB_NORMAL(reg) \ |
114 | ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST) | |
cb8011ad | 115 | |
3d396eb1 | 116 | #define NETXEN_CRB_NORMALIZE(adapter, reg) \ |
cb8011ad AK |
117 | pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg)) |
118 | ||
ed25ffa1 AK |
119 | #define DB_NORMALIZE(adapter, off) \ |
120 | (adapter->ahw.db_base + (off)) | |
121 | ||
122 | #define NX_P2_C0 0x24 | |
123 | #define NX_P2_C1 0x25 | |
124 | ||
cb8011ad | 125 | #define FIRST_PAGE_GROUP_START 0 |
ed25ffa1 | 126 | #define FIRST_PAGE_GROUP_END 0x100000 |
cb8011ad AK |
127 | |
128 | #define SECOND_PAGE_GROUP_START 0x4000000 | |
129 | #define SECOND_PAGE_GROUP_END 0x66BC000 | |
130 | ||
131 | #define THIRD_PAGE_GROUP_START 0x70E4000 | |
132 | #define THIRD_PAGE_GROUP_END 0x8000000 | |
133 | ||
134 | #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START | |
135 | #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START | |
136 | #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START | |
3d396eb1 | 137 | |
ed25ffa1 | 138 | #define MAX_RX_BUFFER_LENGTH 1760 |
bd56c6b1 | 139 | #define MAX_RX_JUMBO_BUFFER_LENGTH 8062 |
ed25ffa1 AK |
140 | #define MAX_RX_LRO_BUFFER_LENGTH ((48*1024)-512) |
141 | #define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - 2) | |
3d396eb1 | 142 | #define RX_JUMBO_DMA_MAP_LEN \ |
ed25ffa1 AK |
143 | (MAX_RX_JUMBO_BUFFER_LENGTH - 2) |
144 | #define RX_LRO_DMA_MAP_LEN (MAX_RX_LRO_BUFFER_LENGTH - 2) | |
3d396eb1 AK |
145 | #define NETXEN_ROM_ROUNDUP 0x80000000ULL |
146 | ||
147 | /* | |
148 | * Maximum number of ring contexts | |
149 | */ | |
150 | #define MAX_RING_CTX 1 | |
151 | ||
152 | /* Opcodes to be used with the commands */ | |
153 | enum { | |
154 | TX_ETHER_PKT = 0x01, | |
155 | /* The following opcodes are for IP checksum */ | |
156 | TX_TCP_PKT, | |
157 | TX_UDP_PKT, | |
158 | TX_IP_PKT, | |
159 | TX_TCP_LSO, | |
160 | TX_IPSEC, | |
161 | TX_IPSEC_CMD | |
162 | }; | |
163 | ||
164 | /* The following opcodes are for internal consumption. */ | |
165 | #define NETXEN_CONTROL_OP 0x10 | |
166 | #define PEGNET_REQUEST 0x11 | |
167 | ||
168 | #define MAX_NUM_CARDS 4 | |
169 | ||
170 | #define MAX_BUFFERS_PER_CMD 32 | |
171 | ||
172 | /* | |
173 | * Following are the states of the Phantom. Phantom will set them and | |
174 | * Host will read to check if the fields are correct. | |
175 | */ | |
176 | #define PHAN_INITIALIZE_START 0xff00 | |
177 | #define PHAN_INITIALIZE_FAILED 0xffff | |
178 | #define PHAN_INITIALIZE_COMPLETE 0xff01 | |
179 | ||
180 | /* Host writes the following to notify that it has done the init-handshake */ | |
181 | #define PHAN_INITIALIZE_ACK 0xf00f | |
182 | ||
ed25ffa1 | 183 | #define NUM_RCV_DESC_RINGS 3 /* No of Rcv Descriptor contexts */ |
3d396eb1 AK |
184 | |
185 | /* descriptor types */ | |
186 | #define RCV_DESC_NORMAL 0x01 | |
187 | #define RCV_DESC_JUMBO 0x02 | |
ed25ffa1 | 188 | #define RCV_DESC_LRO 0x04 |
3d396eb1 AK |
189 | #define RCV_DESC_NORMAL_CTXID 0 |
190 | #define RCV_DESC_JUMBO_CTXID 1 | |
ed25ffa1 | 191 | #define RCV_DESC_LRO_CTXID 2 |
3d396eb1 AK |
192 | |
193 | #define RCV_DESC_TYPE(ID) \ | |
ed25ffa1 AK |
194 | ((ID == RCV_DESC_JUMBO_CTXID) \ |
195 | ? RCV_DESC_JUMBO \ | |
196 | : ((ID == RCV_DESC_LRO_CTXID) \ | |
197 | ? RCV_DESC_LRO : \ | |
198 | (RCV_DESC_NORMAL))) | |
3d396eb1 AK |
199 | |
200 | #define MAX_CMD_DESCRIPTORS 1024 | |
bd56c6b1 AK |
201 | #define MAX_RCV_DESCRIPTORS 16384 |
202 | #define MAX_JUMBO_RCV_DESCRIPTORS 1024 | |
203 | #define MAX_LRO_RCV_DESCRIPTORS 64 | |
3d396eb1 AK |
204 | #define MAX_RCVSTATUS_DESCRIPTORS MAX_RCV_DESCRIPTORS |
205 | #define MAX_JUMBO_RCV_DESC MAX_JUMBO_RCV_DESCRIPTORS | |
206 | #define MAX_RCV_DESC MAX_RCV_DESCRIPTORS | |
207 | #define MAX_RCVSTATUS_DESC MAX_RCV_DESCRIPTORS | |
3d396eb1 | 208 | #define MAX_EPG_DESCRIPTORS (MAX_CMD_DESCRIPTORS * 8) |
ed25ffa1 AK |
209 | #define NUM_RCV_DESC (MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS + \ |
210 | MAX_LRO_RCV_DESCRIPTORS) | |
3d396eb1 AK |
211 | #define MIN_TX_COUNT 4096 |
212 | #define MIN_RX_COUNT 4096 | |
ed25ffa1 AK |
213 | #define NETXEN_CTX_SIGNATURE 0xdee0 |
214 | #define NETXEN_RCV_PRODUCER(ringid) (ringid) | |
3d396eb1 AK |
215 | #define MAX_FRAME_SIZE 0x10000 /* 64K MAX size for LSO */ |
216 | ||
217 | #define PHAN_PEG_RCV_INITIALIZED 0xff01 | |
218 | #define PHAN_PEG_RCV_START_INITIALIZE 0xff00 | |
219 | ||
220 | #define get_next_index(index, length) \ | |
221 | (((index) + 1) & ((length) - 1)) | |
222 | ||
223 | #define get_index_range(index,length,count) \ | |
224 | (((index) + (count)) & ((length) - 1)) | |
225 | ||
ed25ffa1 AK |
226 | #define MPORT_SINGLE_FUNCTION_MODE 0x1111 |
227 | ||
228 | extern unsigned long long netxen_dma_mask; | |
229 | ||
230 | /* | |
231 | * NetXen host-peg signal message structure | |
232 | * | |
233 | * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx | |
234 | * Bit 2 : priv_id => must be 1 | |
235 | * Bit 3-17 : count => for doorbell | |
236 | * Bit 18-27 : ctx_id => Context id | |
237 | * Bit 28-31 : opcode | |
238 | */ | |
239 | ||
240 | typedef u32 netxen_ctx_msg; | |
241 | ||
ed25ffa1 | 242 | #define netxen_set_msg_peg_id(config_word, val) \ |
a608ab9c | 243 | ((config_word) &= ~3, (config_word) |= val & 3) |
ed25ffa1 | 244 | #define netxen_set_msg_privid(config_word) \ |
a608ab9c | 245 | ((config_word) |= 1 << 2) |
ed25ffa1 | 246 | #define netxen_set_msg_count(config_word, val) \ |
a608ab9c | 247 | ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3) |
ed25ffa1 | 248 | #define netxen_set_msg_ctxid(config_word, val) \ |
a608ab9c | 249 | ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18) |
ed25ffa1 | 250 | #define netxen_set_msg_opcode(config_word, val) \ |
a608ab9c | 251 | ((config_word) &= ~(0xf<<24), (config_word) |= (val & 0xf) << 24) |
ed25ffa1 AK |
252 | |
253 | struct netxen_rcv_context { | |
a608ab9c AV |
254 | __le64 rcv_ring_addr; |
255 | __le32 rcv_ring_size; | |
256 | __le32 rsrvd; | |
ed25ffa1 AK |
257 | }; |
258 | ||
259 | struct netxen_ring_ctx { | |
260 | ||
261 | /* one command ring */ | |
a608ab9c AV |
262 | __le64 cmd_consumer_offset; |
263 | __le64 cmd_ring_addr; | |
264 | __le32 cmd_ring_size; | |
265 | __le32 rsrvd; | |
ed25ffa1 AK |
266 | |
267 | /* three receive rings */ | |
268 | struct netxen_rcv_context rcv_ctx[3]; | |
269 | ||
270 | /* one status ring */ | |
a608ab9c AV |
271 | __le64 sts_ring_addr; |
272 | __le32 sts_ring_size; | |
ed25ffa1 | 273 | |
a608ab9c | 274 | __le32 ctx_id; |
ed25ffa1 AK |
275 | } __attribute__ ((aligned(64))); |
276 | ||
3d396eb1 AK |
277 | /* |
278 | * Following data structures describe the descriptors that will be used. | |
279 | * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when | |
280 | * we are doing LSO (above the 1500 size packet) only. | |
281 | */ | |
282 | ||
283 | /* | |
284 | * The size of reference handle been changed to 16 bits to pass the MSS fields | |
285 | * for the LSO packet | |
286 | */ | |
287 | ||
288 | #define FLAGS_CHECKSUM_ENABLED 0x01 | |
289 | #define FLAGS_LSO_ENABLED 0x02 | |
290 | #define FLAGS_IPSEC_SA_ADD 0x04 | |
291 | #define FLAGS_IPSEC_SA_DELETE 0x08 | |
292 | #define FLAGS_VLAN_TAGGED 0x10 | |
293 | ||
ed25ffa1 AK |
294 | #define netxen_set_cmd_desc_port(cmd_desc, var) \ |
295 | ((cmd_desc)->port_ctxid |= ((var) & 0x0F)) | |
3d396eb1 | 296 | |
ed25ffa1 | 297 | #define netxen_set_cmd_desc_flags(cmd_desc, val) \ |
a608ab9c AV |
298 | ((cmd_desc)->flags_opcode &= ~cpu_to_le16(0x7f), \ |
299 | (cmd_desc)->flags_opcode |= cpu_to_le16((val) & 0x7f)) | |
ed25ffa1 | 300 | #define netxen_set_cmd_desc_opcode(cmd_desc, val) \ |
a608ab9c AV |
301 | ((cmd_desc)->flags_opcode &= ~cpu_to_le16(0x3f<<7), \ |
302 | (cmd_desc)->flags_opcode |= cpu_to_le16((val) & (0x3f<<7))) | |
ed25ffa1 AK |
303 | |
304 | #define netxen_set_cmd_desc_num_of_buff(cmd_desc, val) \ | |
a608ab9c AV |
305 | ((cmd_desc)->num_of_buffers_total_length &= ~cpu_to_le32(0xff), \ |
306 | (cmd_desc)->num_of_buffers_total_length |= cpu_to_le32((val) & 0xff)) | |
ed25ffa1 | 307 | #define netxen_set_cmd_desc_totallength(cmd_desc, val) \ |
a608ab9c AV |
308 | ((cmd_desc)->num_of_buffers_total_length &= cpu_to_le32(0xff), \ |
309 | (cmd_desc)->num_of_buffers_total_length |= cpu_to_le32(val << 24)) | |
ed25ffa1 AK |
310 | |
311 | #define netxen_get_cmd_desc_opcode(cmd_desc) \ | |
a608ab9c | 312 | ((le16_to_cpu((cmd_desc)->flags_opcode) >> 7) & 0x003F) |
ed25ffa1 | 313 | #define netxen_get_cmd_desc_totallength(cmd_desc) \ |
a608ab9c | 314 | (le32_to_cpu((cmd_desc)->num_of_buffers_total_length) >> 8) |
3d396eb1 AK |
315 | |
316 | struct cmd_desc_type0 { | |
ed25ffa1 AK |
317 | u8 tcp_hdr_offset; /* For LSO only */ |
318 | u8 ip_hdr_offset; /* For LSO only */ | |
319 | /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */ | |
a608ab9c | 320 | __le16 flags_opcode; |
ed25ffa1 AK |
321 | /* Bit pattern: 0-7 total number of segments, |
322 | 8-31 Total size of the packet */ | |
a608ab9c | 323 | __le32 num_of_buffers_total_length; |
3d396eb1 AK |
324 | union { |
325 | struct { | |
a608ab9c AV |
326 | __le32 addr_low_part2; |
327 | __le32 addr_high_part2; | |
3d396eb1 | 328 | }; |
a608ab9c | 329 | __le64 addr_buffer2; |
3d396eb1 AK |
330 | }; |
331 | ||
a608ab9c AV |
332 | __le16 reference_handle; /* changed to u16 to add mss */ |
333 | __le16 mss; /* passed by NDIS_PACKET for LSO */ | |
3d396eb1 AK |
334 | /* Bit pattern 0-3 port, 0-3 ctx id */ |
335 | u8 port_ctxid; | |
336 | u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ | |
a608ab9c | 337 | __le16 conn_id; /* IPSec offoad only */ |
3d396eb1 AK |
338 | |
339 | union { | |
340 | struct { | |
a608ab9c AV |
341 | __le32 addr_low_part3; |
342 | __le32 addr_high_part3; | |
3d396eb1 | 343 | }; |
a608ab9c | 344 | __le64 addr_buffer3; |
3d396eb1 | 345 | }; |
3d396eb1 AK |
346 | union { |
347 | struct { | |
a608ab9c AV |
348 | __le32 addr_low_part1; |
349 | __le32 addr_high_part1; | |
3d396eb1 | 350 | }; |
a608ab9c | 351 | __le64 addr_buffer1; |
3d396eb1 AK |
352 | }; |
353 | ||
a608ab9c AV |
354 | __le16 buffer1_length; |
355 | __le16 buffer2_length; | |
356 | __le16 buffer3_length; | |
357 | __le16 buffer4_length; | |
3d396eb1 AK |
358 | |
359 | union { | |
360 | struct { | |
a608ab9c AV |
361 | __le32 addr_low_part4; |
362 | __le32 addr_high_part4; | |
3d396eb1 | 363 | }; |
a608ab9c | 364 | __le64 addr_buffer4; |
3d396eb1 AK |
365 | }; |
366 | ||
a608ab9c | 367 | __le64 unused; |
ed25ffa1 | 368 | |
3d396eb1 AK |
369 | } __attribute__ ((aligned(64))); |
370 | ||
371 | /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ | |
372 | struct rcv_desc { | |
a608ab9c AV |
373 | __le16 reference_handle; |
374 | __le16 reserved; | |
375 | __le32 buffer_length; /* allocated buffer length (usually 2K) */ | |
376 | __le64 addr_buffer; | |
3d396eb1 AK |
377 | }; |
378 | ||
379 | /* opcode field in status_desc */ | |
380 | #define RCV_NIC_PKT (0xA) | |
381 | #define STATUS_NIC_PKT ((RCV_NIC_PKT) << 12) | |
382 | ||
383 | /* for status field in status_desc */ | |
384 | #define STATUS_NEED_CKSUM (1) | |
385 | #define STATUS_CKSUM_OK (2) | |
386 | ||
387 | /* owner bits of status_desc */ | |
388 | #define STATUS_OWNER_HOST (0x1) | |
389 | #define STATUS_OWNER_PHANTOM (0x2) | |
390 | ||
391 | #define NETXEN_PROT_IP (1) | |
392 | #define NETXEN_PROT_UNKNOWN (0) | |
393 | ||
394 | /* Note: sizeof(status_desc) should always be a mutliple of 2 */ | |
ed25ffa1 AK |
395 | |
396 | #define netxen_get_sts_desc_lro_cnt(status_desc) \ | |
397 | ((status_desc)->lro & 0x7F) | |
398 | #define netxen_get_sts_desc_lro_last_frag(status_desc) \ | |
399 | (((status_desc)->lro & 0x80) >> 7) | |
400 | ||
401 | #define netxen_get_sts_port(status_desc) \ | |
a608ab9c | 402 | (le64_to_cpu((status_desc)->status_desc_data) & 0x0F) |
ed25ffa1 | 403 | #define netxen_get_sts_status(status_desc) \ |
a608ab9c | 404 | ((le64_to_cpu((status_desc)->status_desc_data) >> 4) & 0x0F) |
ed25ffa1 | 405 | #define netxen_get_sts_type(status_desc) \ |
a608ab9c | 406 | ((le64_to_cpu((status_desc)->status_desc_data) >> 8) & 0x0F) |
ed25ffa1 | 407 | #define netxen_get_sts_totallength(status_desc) \ |
a608ab9c | 408 | ((le64_to_cpu((status_desc)->status_desc_data) >> 12) & 0xFFFF) |
ed25ffa1 | 409 | #define netxen_get_sts_refhandle(status_desc) \ |
a608ab9c | 410 | ((le64_to_cpu((status_desc)->status_desc_data) >> 28) & 0xFFFF) |
ed25ffa1 | 411 | #define netxen_get_sts_prot(status_desc) \ |
a608ab9c | 412 | ((le64_to_cpu((status_desc)->status_desc_data) >> 44) & 0x0F) |
ed25ffa1 | 413 | #define netxen_get_sts_owner(status_desc) \ |
a608ab9c | 414 | ((le64_to_cpu((status_desc)->status_desc_data) >> 56) & 0x03) |
ed25ffa1 | 415 | #define netxen_get_sts_opcode(status_desc) \ |
a608ab9c | 416 | ((le64_to_cpu((status_desc)->status_desc_data) >> 58) & 0x03F) |
ed25ffa1 AK |
417 | |
418 | #define netxen_clear_sts_owner(status_desc) \ | |
419 | ((status_desc)->status_desc_data &= \ | |
a608ab9c | 420 | ~cpu_to_le64(((unsigned long long)3) << 56 )) |
ed25ffa1 AK |
421 | #define netxen_set_sts_owner(status_desc, val) \ |
422 | ((status_desc)->status_desc_data |= \ | |
a608ab9c | 423 | cpu_to_le64(((unsigned long long)((val) & 0x3)) << 56 )) |
3d396eb1 AK |
424 | |
425 | struct status_desc { | |
ed25ffa1 AK |
426 | /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-27 total_length |
427 | 28-43 reference_handle, 44-47 protocol, 48-52 unused | |
428 | 53-55 desc_cnt, 56-57 owner, 58-63 opcode | |
429 | */ | |
a608ab9c AV |
430 | __le64 status_desc_data; |
431 | __le32 hash_value; | |
ed25ffa1 AK |
432 | u8 hash_type; |
433 | u8 msg_type; | |
434 | u8 unused; | |
435 | /* Bit pattern: 0-6 lro_count indicates frag sequence, | |
436 | 7 last_frag indicates last frag */ | |
437 | u8 lro; | |
3d396eb1 AK |
438 | } __attribute__ ((aligned(8))); |
439 | ||
440 | enum { | |
441 | NETXEN_RCV_PEG_0 = 0, | |
442 | NETXEN_RCV_PEG_1 | |
443 | }; | |
444 | /* The version of the main data structure */ | |
445 | #define NETXEN_BDINFO_VERSION 1 | |
446 | ||
447 | /* Magic number to let user know flash is programmed */ | |
448 | #define NETXEN_BDINFO_MAGIC 0x12345678 | |
449 | ||
450 | /* Max number of Gig ports on a Phantom board */ | |
451 | #define NETXEN_MAX_PORTS 4 | |
452 | ||
453 | typedef enum { | |
454 | NETXEN_BRDTYPE_P1_BD = 0x0000, | |
455 | NETXEN_BRDTYPE_P1_SB = 0x0001, | |
456 | NETXEN_BRDTYPE_P1_SMAX = 0x0002, | |
457 | NETXEN_BRDTYPE_P1_SOCK = 0x0003, | |
458 | ||
459 | NETXEN_BRDTYPE_P2_SOCK_31 = 0x0008, | |
460 | NETXEN_BRDTYPE_P2_SOCK_35 = 0x0009, | |
461 | NETXEN_BRDTYPE_P2_SB35_4G = 0x000a, | |
462 | NETXEN_BRDTYPE_P2_SB31_10G = 0x000b, | |
463 | NETXEN_BRDTYPE_P2_SB31_2G = 0x000c, | |
464 | ||
465 | NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d, | |
466 | NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e, | |
467 | NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f | |
468 | } netxen_brdtype_t; | |
469 | ||
470 | typedef enum { | |
471 | NETXEN_BRDMFG_INVENTEC = 1 | |
472 | } netxen_brdmfg; | |
473 | ||
474 | typedef enum { | |
475 | MEM_ORG_128Mbx4 = 0x0, /* DDR1 only */ | |
476 | MEM_ORG_128Mbx8 = 0x1, /* DDR1 only */ | |
477 | MEM_ORG_128Mbx16 = 0x2, /* DDR1 only */ | |
478 | MEM_ORG_256Mbx4 = 0x3, | |
479 | MEM_ORG_256Mbx8 = 0x4, | |
480 | MEM_ORG_256Mbx16 = 0x5, | |
481 | MEM_ORG_512Mbx4 = 0x6, | |
482 | MEM_ORG_512Mbx8 = 0x7, | |
483 | MEM_ORG_512Mbx16 = 0x8, | |
484 | MEM_ORG_1Gbx4 = 0x9, | |
485 | MEM_ORG_1Gbx8 = 0xa, | |
486 | MEM_ORG_1Gbx16 = 0xb, | |
487 | MEM_ORG_2Gbx4 = 0xc, | |
488 | MEM_ORG_2Gbx8 = 0xd, | |
489 | MEM_ORG_2Gbx16 = 0xe, | |
490 | MEM_ORG_128Mbx32 = 0x10002, /* GDDR only */ | |
491 | MEM_ORG_256Mbx32 = 0x10005 /* GDDR only */ | |
492 | } netxen_mn_mem_org_t; | |
493 | ||
494 | typedef enum { | |
495 | MEM_ORG_512Kx36 = 0x0, | |
496 | MEM_ORG_1Mx36 = 0x1, | |
497 | MEM_ORG_2Mx36 = 0x2 | |
498 | } netxen_sn_mem_org_t; | |
499 | ||
500 | typedef enum { | |
501 | MEM_DEPTH_4MB = 0x1, | |
502 | MEM_DEPTH_8MB = 0x2, | |
503 | MEM_DEPTH_16MB = 0x3, | |
504 | MEM_DEPTH_32MB = 0x4, | |
505 | MEM_DEPTH_64MB = 0x5, | |
506 | MEM_DEPTH_128MB = 0x6, | |
507 | MEM_DEPTH_256MB = 0x7, | |
508 | MEM_DEPTH_512MB = 0x8, | |
509 | MEM_DEPTH_1GB = 0x9, | |
510 | MEM_DEPTH_2GB = 0xa, | |
511 | MEM_DEPTH_4GB = 0xb, | |
512 | MEM_DEPTH_8GB = 0xc, | |
513 | MEM_DEPTH_16GB = 0xd, | |
514 | MEM_DEPTH_32GB = 0xe | |
515 | } netxen_mem_depth_t; | |
516 | ||
517 | struct netxen_board_info { | |
518 | u32 header_version; | |
519 | ||
520 | u32 board_mfg; | |
521 | u32 board_type; | |
522 | u32 board_num; | |
523 | u32 chip_id; | |
524 | u32 chip_minor; | |
525 | u32 chip_major; | |
526 | u32 chip_pkg; | |
527 | u32 chip_lot; | |
528 | ||
529 | u32 port_mask; /* available niu ports */ | |
530 | u32 peg_mask; /* available pegs */ | |
531 | u32 icache_ok; /* can we run with icache? */ | |
532 | u32 dcache_ok; /* can we run with dcache? */ | |
533 | u32 casper_ok; | |
534 | ||
535 | u32 mac_addr_lo_0; | |
536 | u32 mac_addr_lo_1; | |
537 | u32 mac_addr_lo_2; | |
538 | u32 mac_addr_lo_3; | |
539 | ||
540 | /* MN-related config */ | |
541 | u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */ | |
542 | u32 mn_sync_shift_cclk; | |
543 | u32 mn_sync_shift_mclk; | |
544 | u32 mn_wb_en; | |
545 | u32 mn_crystal_freq; /* in MHz */ | |
546 | u32 mn_speed; /* in MHz */ | |
547 | u32 mn_org; | |
548 | u32 mn_depth; | |
549 | u32 mn_ranks_0; /* ranks per slot */ | |
550 | u32 mn_ranks_1; /* ranks per slot */ | |
551 | u32 mn_rd_latency_0; | |
552 | u32 mn_rd_latency_1; | |
553 | u32 mn_rd_latency_2; | |
554 | u32 mn_rd_latency_3; | |
555 | u32 mn_rd_latency_4; | |
556 | u32 mn_rd_latency_5; | |
557 | u32 mn_rd_latency_6; | |
558 | u32 mn_rd_latency_7; | |
559 | u32 mn_rd_latency_8; | |
560 | u32 mn_dll_val[18]; | |
561 | u32 mn_mode_reg; /* MIU DDR Mode Register */ | |
562 | u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */ | |
563 | u32 mn_timing_0; /* MIU Memory Control Timing Rgister */ | |
564 | u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */ | |
565 | u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */ | |
566 | ||
567 | /* SN-related config */ | |
568 | u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */ | |
569 | u32 sn_pt_mode; /* pass through mode */ | |
570 | u32 sn_ecc_en; | |
571 | u32 sn_wb_en; | |
572 | u32 sn_crystal_freq; | |
573 | u32 sn_speed; | |
574 | u32 sn_org; | |
575 | u32 sn_depth; | |
576 | u32 sn_dll_tap; | |
577 | u32 sn_rd_latency; | |
578 | ||
579 | u32 mac_addr_hi_0; | |
580 | u32 mac_addr_hi_1; | |
581 | u32 mac_addr_hi_2; | |
582 | u32 mac_addr_hi_3; | |
583 | ||
584 | u32 magic; /* indicates flash has been initialized */ | |
585 | ||
586 | u32 mn_rdimm; | |
587 | u32 mn_dll_override; | |
588 | ||
589 | }; | |
590 | ||
591 | #define FLASH_NUM_PORTS (4) | |
592 | ||
593 | struct netxen_flash_mac_addr { | |
594 | u32 flash_addr[32]; | |
595 | }; | |
596 | ||
597 | struct netxen_user_old_info { | |
598 | u8 flash_md5[16]; | |
599 | u8 crbinit_md5[16]; | |
600 | u8 brdcfg_md5[16]; | |
601 | /* bootloader */ | |
602 | u32 bootld_version; | |
603 | u32 bootld_size; | |
604 | u8 bootld_md5[16]; | |
605 | /* image */ | |
606 | u32 image_version; | |
607 | u32 image_size; | |
608 | u8 image_md5[16]; | |
609 | /* primary image status */ | |
610 | u32 primary_status; | |
611 | u32 secondary_present; | |
612 | ||
613 | /* MAC address , 4 ports */ | |
614 | struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS]; | |
615 | }; | |
616 | #define FLASH_NUM_MAC_PER_PORT 32 | |
617 | struct netxen_user_info { | |
618 | u8 flash_md5[16 * 64]; | |
619 | /* bootloader */ | |
620 | u32 bootld_version; | |
621 | u32 bootld_size; | |
622 | /* image */ | |
623 | u32 image_version; | |
624 | u32 image_size; | |
625 | /* primary image status */ | |
626 | u32 primary_status; | |
627 | u32 secondary_present; | |
628 | ||
629 | /* MAC address , 4 ports, 32 address per port */ | |
630 | u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT]; | |
631 | u32 sub_sys_id; | |
632 | u8 serial_num[32]; | |
633 | ||
634 | /* Any user defined data */ | |
635 | }; | |
636 | ||
637 | /* | |
638 | * Flash Layout - new format. | |
639 | */ | |
640 | struct netxen_new_user_info { | |
641 | u8 flash_md5[16 * 64]; | |
642 | /* bootloader */ | |
643 | u32 bootld_version; | |
644 | u32 bootld_size; | |
645 | /* image */ | |
646 | u32 image_version; | |
647 | u32 image_size; | |
648 | /* primary image status */ | |
649 | u32 primary_status; | |
650 | u32 secondary_present; | |
651 | ||
652 | /* MAC address , 4 ports, 32 address per port */ | |
653 | u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT]; | |
654 | u32 sub_sys_id; | |
655 | u8 serial_num[32]; | |
656 | ||
657 | /* Any user defined data */ | |
658 | }; | |
659 | ||
660 | #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6 | |
661 | #define SECONDARY_IMAGE_ABSENT 0xffffffff | |
662 | #define PRIMARY_IMAGE_GOOD 0x5a5a5a5a | |
663 | #define PRIMARY_IMAGE_BAD 0xffffffff | |
664 | ||
665 | /* Flash memory map */ | |
666 | typedef enum { | |
667 | CRBINIT_START = 0, /* Crbinit section */ | |
668 | BRDCFG_START = 0x4000, /* board config */ | |
669 | INITCODE_START = 0x6000, /* pegtune code */ | |
670 | BOOTLD_START = 0x10000, /* bootld */ | |
671 | IMAGE_START = 0x43000, /* compressed image */ | |
672 | SECONDARY_START = 0x200000, /* backup images */ | |
673 | PXE_START = 0x3E0000, /* user defined region */ | |
674 | USER_START = 0x3E8000, /* User defined region for new boards */ | |
675 | FIXED_START = 0x3F0000 /* backup of crbinit */ | |
676 | } netxen_flash_map_t; | |
677 | ||
678 | #define USER_START_OLD PXE_START /* for backward compatibility */ | |
679 | ||
680 | #define FLASH_START (CRBINIT_START) | |
681 | #define INIT_SECTOR (0) | |
682 | #define PRIMARY_START (BOOTLD_START) | |
683 | #define FLASH_CRBINIT_SIZE (0x4000) | |
684 | #define FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info)) | |
80922fbc | 685 | #define FLASH_USER_SIZE (sizeof(struct netxen_user_info)/sizeof(u32)) |
3d396eb1 AK |
686 | #define FLASH_SECONDARY_SIZE (USER_START-SECONDARY_START) |
687 | #define NUM_PRIMARY_SECTORS (0x20) | |
688 | #define NUM_CONFIG_SECTORS (1) | |
ed25ffa1 AK |
689 | #define PFX "NetXen: " |
690 | extern char netxen_nic_driver_name[]; | |
3d396eb1 AK |
691 | |
692 | /* Note: Make sure to not call this before adapter->port is valid */ | |
693 | #if !defined(NETXEN_DEBUG) | |
694 | #define DPRINTK(klevel, fmt, args...) do { \ | |
695 | } while (0) | |
696 | #else | |
697 | #define DPRINTK(klevel, fmt, args...) do { \ | |
698 | printk(KERN_##klevel PFX "%s: %s: " fmt, __FUNCTION__,\ | |
80922fbc | 699 | (adapter != NULL && \ |
3d396eb1 AK |
700 | adapter->port[0] != NULL && \ |
701 | adapter->port[0]->netdev != NULL) ? \ | |
702 | adapter->port[0]->netdev->name : NULL, \ | |
703 | ## args); } while(0) | |
704 | #endif | |
705 | ||
706 | /* Number of status descriptors to handle per interrupt */ | |
707 | #define MAX_STATUS_HANDLE (128) | |
708 | ||
709 | /* | |
710 | * netxen_skb_frag{} is to contain mapping info for each SG list. This | |
711 | * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}. | |
712 | */ | |
713 | struct netxen_skb_frag { | |
714 | u64 dma; | |
715 | u32 length; | |
716 | }; | |
717 | ||
718 | /* Following defines are for the state of the buffers */ | |
719 | #define NETXEN_BUFFER_FREE 0 | |
720 | #define NETXEN_BUFFER_BUSY 1 | |
721 | ||
722 | /* | |
723 | * There will be one netxen_buffer per skb packet. These will be | |
724 | * used to save the dma info for pci_unmap_page() | |
725 | */ | |
726 | struct netxen_cmd_buffer { | |
727 | struct sk_buff *skb; | |
728 | struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1]; | |
729 | u32 total_length; | |
730 | u32 mss; | |
731 | u16 port; | |
732 | u8 cmd; | |
733 | u8 frag_count; | |
734 | unsigned long time_stamp; | |
735 | u32 state; | |
3d396eb1 AK |
736 | }; |
737 | ||
738 | /* In rx_buffer, we do not need multiple fragments as is a single buffer */ | |
739 | struct netxen_rx_buffer { | |
740 | struct sk_buff *skb; | |
741 | u64 dma; | |
742 | u16 ref_handle; | |
743 | u16 state; | |
ed25ffa1 AK |
744 | u32 lro_expected_frags; |
745 | u32 lro_current_frags; | |
746 | u32 lro_length; | |
3d396eb1 AK |
747 | }; |
748 | ||
749 | /* Board types */ | |
750 | #define NETXEN_NIC_GBE 0x01 | |
751 | #define NETXEN_NIC_XGBE 0x02 | |
752 | ||
753 | /* | |
754 | * One hardware_context{} per adapter | |
755 | * contains interrupt info as well shared hardware info. | |
756 | */ | |
757 | struct netxen_hardware_context { | |
758 | struct pci_dev *pdev; | |
cb8011ad AK |
759 | void __iomem *pci_base0; |
760 | void __iomem *pci_base1; | |
761 | void __iomem *pci_base2; | |
ed25ffa1 AK |
762 | void __iomem *db_base; |
763 | unsigned long db_len; | |
cb8011ad | 764 | |
3d396eb1 AK |
765 | u8 revision_id; |
766 | u16 board_type; | |
767 | u16 max_ports; | |
768 | struct netxen_board_info boardcfg; | |
769 | u32 xg_linkup; | |
cb8011ad | 770 | u32 qg_linksup; |
3d396eb1 AK |
771 | /* Address of cmd ring in Phantom */ |
772 | struct cmd_desc_type0 *cmd_desc_head; | |
cb8011ad | 773 | struct pci_dev *cmd_desc_pdev; |
3d396eb1 AK |
774 | dma_addr_t cmd_desc_phys_addr; |
775 | struct netxen_adapter *adapter; | |
776 | }; | |
777 | ||
ed25ffa1 AK |
778 | #define RCV_RING_LRO RCV_DESC_LRO |
779 | ||
3d396eb1 AK |
780 | #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ |
781 | #define ETHERNET_FCS_SIZE 4 | |
782 | ||
783 | struct netxen_adapter_stats { | |
784 | u64 ints; | |
785 | u64 hostints; | |
786 | u64 otherints; | |
787 | u64 process_rcv; | |
788 | u64 process_xmit; | |
789 | u64 noxmitdone; | |
790 | u64 xmitcsummed; | |
791 | u64 post_called; | |
792 | u64 posted; | |
793 | u64 lastposted; | |
794 | u64 goodskbposts; | |
795 | }; | |
796 | ||
797 | /* | |
798 | * Rcv Descriptor Context. One such per Rcv Descriptor. There may | |
799 | * be one Rcv Descriptor for normal packets, one for jumbo and may be others. | |
800 | */ | |
801 | struct netxen_rcv_desc_ctx { | |
802 | u32 flags; | |
803 | u32 producer; | |
804 | u32 rcv_pending; /* Num of bufs posted in phantom */ | |
805 | u32 rcv_free; /* Num of bufs in free list */ | |
806 | dma_addr_t phys_addr; | |
cb8011ad | 807 | struct pci_dev *phys_pdev; |
3d396eb1 AK |
808 | struct rcv_desc *desc_head; /* address of rx ring in Phantom */ |
809 | u32 max_rx_desc_count; | |
810 | u32 dma_size; | |
811 | u32 skb_size; | |
812 | struct netxen_rx_buffer *rx_buf_arr; /* rx buffers for receive */ | |
813 | int begin_alloc; | |
814 | }; | |
815 | ||
816 | /* | |
817 | * Receive context. There is one such structure per instance of the | |
818 | * receive processing. Any state information that is relevant to | |
819 | * the receive, and is must be in this structure. The global data may be | |
820 | * present elsewhere. | |
821 | */ | |
822 | struct netxen_recv_context { | |
823 | struct netxen_rcv_desc_ctx rcv_desc[NUM_RCV_DESC_RINGS]; | |
824 | u32 status_rx_producer; | |
825 | u32 status_rx_consumer; | |
826 | dma_addr_t rcv_status_desc_phys_addr; | |
cb8011ad | 827 | struct pci_dev *rcv_status_desc_pdev; |
3d396eb1 AK |
828 | struct status_desc *rcv_status_desc_head; |
829 | }; | |
830 | ||
831 | #define NETXEN_NIC_MSI_ENABLED 0x02 | |
ed25ffa1 AK |
832 | #define NETXEN_DMA_MASK 0xfffffffe |
833 | #define NETXEN_DB_MAPSIZE_BYTES 0x1000 | |
834 | ||
835 | struct netxen_dummy_dma { | |
836 | void *addr; | |
837 | dma_addr_t phys_addr; | |
838 | }; | |
3d396eb1 | 839 | |
3d396eb1 AK |
840 | struct netxen_adapter { |
841 | struct netxen_hardware_context ahw; | |
842 | int port_count; /* Number of configured ports */ | |
843 | int active_ports; /* Number of open ports */ | |
844 | struct netxen_port *port[NETXEN_MAX_PORTS]; /* ptr to each port */ | |
845 | spinlock_t tx_lock; | |
846 | spinlock_t lock; | |
847 | struct work_struct watchdog_task; | |
3d396eb1 AK |
848 | struct timer_list watchdog_timer; |
849 | ||
850 | u32 curr_window; | |
851 | ||
852 | u32 cmd_producer; | |
ed25ffa1 | 853 | u32 *cmd_consumer; |
3d396eb1 AK |
854 | |
855 | u32 last_cmd_consumer; | |
856 | u32 max_tx_desc_count; | |
857 | u32 max_rx_desc_count; | |
858 | u32 max_jumbo_rx_desc_count; | |
ed25ffa1 | 859 | u32 max_lro_rx_desc_count; |
3d396eb1 AK |
860 | /* Num of instances active on cmd buffer ring */ |
861 | u32 proc_cmd_buf_counter; | |
862 | ||
863 | u32 num_threads, total_threads; /*Use to keep track of xmit threads */ | |
864 | ||
865 | u32 flags; | |
866 | u32 irq; | |
867 | int driver_mismatch; | |
cb8011ad | 868 | u32 temp; |
3d396eb1 AK |
869 | |
870 | struct netxen_adapter_stats stats; | |
871 | ||
872 | struct netxen_cmd_buffer *cmd_buf_arr; /* Command buffers for xmit */ | |
873 | ||
874 | /* | |
875 | * Receive instances. These can be either one per port, | |
876 | * or one per peg, etc. | |
877 | */ | |
878 | struct netxen_recv_context recv_ctx[MAX_RCV_CTX]; | |
879 | ||
880 | int is_up; | |
ed25ffa1 AK |
881 | struct netxen_dummy_dma dummy_dma; |
882 | ||
883 | /* Context interface shared between card and host */ | |
884 | struct netxen_ring_ctx *ctx_desc; | |
885 | struct pci_dev *ctx_desc_pdev; | |
886 | dma_addr_t ctx_desc_phys_addr; | |
80922fbc AK |
887 | int (*enable_phy_interrupts) (struct netxen_adapter *, int); |
888 | int (*disable_phy_interrupts) (struct netxen_adapter *, int); | |
889 | void (*handle_phy_intr) (struct netxen_adapter *); | |
890 | int (*macaddr_set) (struct netxen_port *, netxen_ethernet_macaddr_t); | |
891 | int (*set_mtu) (struct netxen_port *, int); | |
892 | int (*set_promisc) (struct netxen_adapter *, int, | |
893 | netxen_niu_prom_mode_t); | |
894 | int (*unset_promisc) (struct netxen_adapter *, int, | |
895 | netxen_niu_prom_mode_t); | |
896 | int (*phy_read) (struct netxen_adapter *, long phy, long reg, u32 *); | |
897 | int (*phy_write) (struct netxen_adapter *, long phy, long reg, u32 val); | |
898 | int (*init_port) (struct netxen_adapter *, int); | |
899 | void (*init_niu) (struct netxen_adapter *); | |
900 | int (*stop_port) (struct netxen_adapter *, int); | |
3d396eb1 AK |
901 | }; /* netxen_adapter structure */ |
902 | ||
903 | /* Max number of xmit producer threads that can run simultaneously */ | |
904 | #define MAX_XMIT_PRODUCERS 16 | |
905 | ||
906 | struct netxen_port_stats { | |
907 | u64 rcvdbadskb; | |
908 | u64 xmitcalled; | |
909 | u64 xmitedframes; | |
910 | u64 xmitfinished; | |
911 | u64 badskblen; | |
912 | u64 nocmddescriptor; | |
913 | u64 polled; | |
914 | u64 uphappy; | |
915 | u64 updropped; | |
916 | u64 uplcong; | |
917 | u64 uphcong; | |
918 | u64 upmcong; | |
919 | u64 updunno; | |
920 | u64 skbfreed; | |
921 | u64 txdropped; | |
922 | u64 txnullskb; | |
923 | u64 csummed; | |
924 | u64 no_rcv; | |
925 | u64 rxbytes; | |
926 | u64 txbytes; | |
927 | }; | |
928 | ||
929 | struct netxen_port { | |
930 | struct netxen_adapter *adapter; | |
931 | ||
932 | u16 portnum; /* GBE port number */ | |
933 | u16 link_speed; | |
934 | u16 link_duplex; | |
935 | u16 link_autoneg; | |
936 | ||
937 | int flags; | |
938 | ||
939 | struct net_device *netdev; | |
940 | struct pci_dev *pdev; | |
941 | struct net_device_stats net_stats; | |
942 | struct netxen_port_stats stats; | |
6c586644 | 943 | struct work_struct tx_timeout_task; |
3d396eb1 AK |
944 | }; |
945 | ||
cb8011ad AK |
946 | #define PCI_OFFSET_FIRST_RANGE(adapter, off) \ |
947 | ((adapter)->ahw.pci_base0 + (off)) | |
948 | #define PCI_OFFSET_SECOND_RANGE(adapter, off) \ | |
949 | ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START) | |
950 | #define PCI_OFFSET_THIRD_RANGE(adapter, off) \ | |
951 | ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START) | |
952 | ||
953 | static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter, | |
954 | unsigned long off) | |
955 | { | |
956 | if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) { | |
957 | return (adapter->ahw.pci_base0 + off); | |
958 | } else if ((off < SECOND_PAGE_GROUP_END) && | |
959 | (off >= SECOND_PAGE_GROUP_START)) { | |
960 | return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START); | |
961 | } else if ((off < THIRD_PAGE_GROUP_END) && | |
962 | (off >= THIRD_PAGE_GROUP_START)) { | |
963 | return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START); | |
964 | } | |
965 | return NULL; | |
966 | } | |
967 | ||
968 | static inline void __iomem *pci_base(struct netxen_adapter *adapter, | |
969 | unsigned long off) | |
970 | { | |
971 | if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) { | |
972 | return adapter->ahw.pci_base0; | |
973 | } else if ((off < SECOND_PAGE_GROUP_END) && | |
974 | (off >= SECOND_PAGE_GROUP_START)) { | |
975 | return adapter->ahw.pci_base1; | |
976 | } else if ((off < THIRD_PAGE_GROUP_END) && | |
977 | (off >= THIRD_PAGE_GROUP_START)) { | |
978 | return adapter->ahw.pci_base2; | |
979 | } | |
980 | return NULL; | |
981 | } | |
982 | ||
3d396eb1 AK |
983 | int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter, |
984 | int port); | |
985 | int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter, | |
986 | int port); | |
987 | int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter, | |
988 | int port); | |
989 | int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter, | |
990 | int port); | |
991 | int netxen_niu_xgbe_clear_phy_interrupts(struct netxen_adapter *adapter, | |
992 | int port); | |
993 | int netxen_niu_gbe_clear_phy_interrupts(struct netxen_adapter *adapter, | |
994 | int port); | |
995 | void netxen_nic_xgbe_handle_phy_intr(struct netxen_adapter *adapter); | |
996 | void netxen_nic_gbe_handle_phy_intr(struct netxen_adapter *adapter); | |
997 | void netxen_niu_gbe_set_mii_mode(struct netxen_adapter *adapter, int port, | |
998 | long enable); | |
999 | void netxen_niu_gbe_set_gmii_mode(struct netxen_adapter *adapter, int port, | |
1000 | long enable); | |
1001 | int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long phy, long reg, | |
a608ab9c | 1002 | __u32 * readval); |
3d396eb1 | 1003 | int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long phy, |
a608ab9c | 1004 | long reg, __u32 val); |
3d396eb1 AK |
1005 | |
1006 | /* Functions available from netxen_nic_hw.c */ | |
3d396eb1 AK |
1007 | int netxen_nic_set_mtu_xgb(struct netxen_port *port, int new_mtu); |
1008 | int netxen_nic_set_mtu_gb(struct netxen_port *port, int new_mtu); | |
1009 | void netxen_nic_init_niu_gb(struct netxen_adapter *adapter); | |
1010 | void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw); | |
1011 | void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val); | |
1012 | int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off); | |
1013 | void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value); | |
1014 | void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value); | |
1015 | ||
1016 | int netxen_nic_get_board_info(struct netxen_adapter *adapter); | |
1017 | int netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data, | |
1018 | int len); | |
1019 | int netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data, | |
1020 | int len); | |
1021 | void netxen_crb_writelit_adapter(struct netxen_adapter *adapter, | |
1022 | unsigned long off, int data); | |
1023 | ||
1024 | /* Functions from netxen_nic_init.c */ | |
ed25ffa1 AK |
1025 | void netxen_free_adapter_offload(struct netxen_adapter *adapter); |
1026 | int netxen_initialize_adapter_offload(struct netxen_adapter *adapter); | |
cb8011ad | 1027 | void netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val); |
3d396eb1 AK |
1028 | void netxen_load_firmware(struct netxen_adapter *adapter); |
1029 | int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose); | |
1030 | int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp); | |
cb8011ad AK |
1031 | int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data); |
1032 | int netxen_rom_se(struct netxen_adapter *adapter, int addr); | |
1033 | int netxen_do_rom_se(struct netxen_adapter *adapter, int addr); | |
3d396eb1 AK |
1034 | |
1035 | /* Functions from netxen_nic_isr.c */ | |
1036 | void netxen_nic_isr_other(struct netxen_adapter *adapter); | |
1037 | void netxen_indicate_link_status(struct netxen_adapter *adapter, u32 port, | |
1038 | u32 link); | |
1039 | void netxen_handle_port_int(struct netxen_adapter *adapter, u32 port, | |
1040 | u32 enable); | |
1041 | void netxen_nic_stop_all_ports(struct netxen_adapter *adapter); | |
1042 | void netxen_initialize_adapter_sw(struct netxen_adapter *adapter); | |
1043 | void netxen_initialize_adapter_hw(struct netxen_adapter *adapter); | |
cb8011ad AK |
1044 | void *netxen_alloc(struct pci_dev *pdev, size_t sz, dma_addr_t * ptr, |
1045 | struct pci_dev **used_dev); | |
3d396eb1 AK |
1046 | void netxen_initialize_adapter_ops(struct netxen_adapter *adapter); |
1047 | int netxen_init_firmware(struct netxen_adapter *adapter); | |
1048 | void netxen_free_hw_resources(struct netxen_adapter *adapter); | |
1049 | void netxen_tso_check(struct netxen_adapter *adapter, | |
1050 | struct cmd_desc_type0 *desc, struct sk_buff *skb); | |
1051 | int netxen_nic_hw_resources(struct netxen_adapter *adapter); | |
1052 | void netxen_nic_clear_stats(struct netxen_adapter *adapter); | |
3d396eb1 AK |
1053 | int netxen_nic_rx_has_work(struct netxen_adapter *adapter); |
1054 | int netxen_nic_tx_has_work(struct netxen_adapter *adapter); | |
6d5aefb8 | 1055 | void netxen_watchdog_task(struct work_struct *work); |
3d396eb1 AK |
1056 | void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, |
1057 | u32 ringid); | |
ed25ffa1 AK |
1058 | void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, u32 ctx, |
1059 | u32 ringid); | |
1060 | int netxen_process_cmd_ring(unsigned long data); | |
3d396eb1 AK |
1061 | u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctx, int max); |
1062 | void netxen_nic_set_multi(struct net_device *netdev); | |
1063 | int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu); | |
1064 | int netxen_nic_set_mac(struct net_device *netdev, void *p); | |
1065 | struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev); | |
1066 | ||
1067 | static inline void netxen_nic_disable_int(struct netxen_adapter *adapter) | |
1068 | { | |
1069 | /* | |
1070 | * ISR_INT_MASK: Can be read from window 0 or 1. | |
1071 | */ | |
71bd7877 | 1072 | writel(0x7ff, PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_MASK)); |
cb8011ad | 1073 | |
3d396eb1 AK |
1074 | } |
1075 | ||
1076 | static inline void netxen_nic_enable_int(struct netxen_adapter *adapter) | |
1077 | { | |
1078 | u32 mask; | |
1079 | ||
1080 | switch (adapter->ahw.board_type) { | |
1081 | case NETXEN_NIC_GBE: | |
1082 | mask = 0x77b; | |
1083 | break; | |
1084 | case NETXEN_NIC_XGBE: | |
1085 | mask = 0x77f; | |
1086 | break; | |
1087 | default: | |
1088 | mask = 0x7ff; | |
1089 | break; | |
1090 | } | |
1091 | ||
71bd7877 | 1092 | writel(mask, PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_MASK)); |
3d396eb1 AK |
1093 | |
1094 | if (!(adapter->flags & NETXEN_NIC_MSI_ENABLED)) { | |
1095 | mask = 0xbff; | |
71bd7877 AK |
1096 | writel(mask, PCI_OFFSET_SECOND_RANGE(adapter, |
1097 | ISR_INT_TARGET_MASK)); | |
cb8011ad AK |
1098 | } |
1099 | } | |
1100 | ||
1101 | /* | |
1102 | * NetXen Board information | |
1103 | */ | |
1104 | ||
1105 | #define NETXEN_MAX_SHORT_NAME 16 | |
71bd7877 | 1106 | struct netxen_brdinfo { |
cb8011ad AK |
1107 | netxen_brdtype_t brdtype; /* type of board */ |
1108 | long ports; /* max no of physical ports */ | |
1109 | char short_name[NETXEN_MAX_SHORT_NAME]; | |
71bd7877 | 1110 | }; |
cb8011ad | 1111 | |
71bd7877 | 1112 | static const struct netxen_brdinfo netxen_boards[] = { |
cb8011ad AK |
1113 | {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"}, |
1114 | {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"}, | |
1115 | {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"}, | |
1116 | {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"}, | |
1117 | {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"}, | |
1118 | {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"}, | |
1119 | }; | |
1120 | ||
71bd7877 | 1121 | #define NUM_SUPPORTED_BOARDS (sizeof(netxen_boards)/sizeof(struct netxen_brdinfo)) |
cb8011ad AK |
1122 | |
1123 | static inline void get_brd_port_by_type(u32 type, int *ports) | |
1124 | { | |
1125 | int i, found = 0; | |
1126 | for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) { | |
1127 | if (netxen_boards[i].brdtype == type) { | |
1128 | *ports = netxen_boards[i].ports; | |
1129 | found = 1; | |
1130 | break; | |
1131 | } | |
1132 | } | |
1133 | if (!found) | |
1134 | *ports = 0; | |
1135 | } | |
1136 | ||
1137 | static inline void get_brd_name_by_type(u32 type, char *name) | |
1138 | { | |
1139 | int i, found = 0; | |
1140 | for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) { | |
1141 | if (netxen_boards[i].brdtype == type) { | |
1142 | strcpy(name, netxen_boards[i].short_name); | |
1143 | found = 1; | |
1144 | break; | |
1145 | } | |
1146 | ||
3d396eb1 | 1147 | } |
cb8011ad AK |
1148 | if (!found) |
1149 | name = "Unknown"; | |
3d396eb1 AK |
1150 | } |
1151 | ||
1152 | int netxen_is_flash_supported(struct netxen_adapter *adapter); | |
1153 | int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 mac[]); | |
3d396eb1 AK |
1154 | extern void netxen_change_ringparam(struct netxen_adapter *adapter); |
1155 | extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, | |
1156 | int *valp); | |
1157 | ||
1158 | extern struct ethtool_ops netxen_nic_ethtool_ops; | |
1159 | ||
1160 | #endif /* __NETXEN_NIC_H_ */ |