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[PATCH] irq-flags: drivers/net: Use the new IRQF_ constants
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / net / natsemi.c
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1da177e4
LT		 1/* natsemi.c: A Linux PCI Ethernet driver for the NatSemi DP8381x series. */
2/*
3 Written/copyright 1999-2001 by Donald Becker.
4 Portions copyright (c) 2001,2002 Sun Microsystems (thockin@sun.com)
5 Portions copyright 2001,2002 Manfred Spraul (manfred@colorfullife.com)
b27a16b7 6 Portions copyright 2004 Harald Welte <laforge@gnumonks.org>
1da177e4
LT		 7
8 This software may be used and distributed according to the terms of
9 the GNU General Public License (GPL), incorporated herein by reference.
10 Drivers based on or derived from this code fall under the GPL and must
11 retain the authorship, copyright and license notice. This file is not
12 a complete program and may only be used when the entire operating
13 system is licensed under the GPL. License for under other terms may be
14 available. Contact the original author for details.
15
16 The original author may be reached as becker@scyld.com, or at
17 Scyld Computing Corporation
18 410 Severn Ave., Suite 210
19 Annapolis MD 21403
20
21 Support information and updates available at
22 http://www.scyld.com/network/netsemi.html
23
24
25 Linux kernel modifications:
26
27 Version 1.0.1:
28 - Spinlock fixes
29 - Bug fixes and better intr performance (Tjeerd)
30 Version 1.0.2:
31 - Now reads correct MAC address from eeprom
32 Version 1.0.3:
33 - Eliminate redundant priv->tx_full flag
34 - Call netif_start_queue from dev->tx_timeout
35 - wmb() in start_tx() to flush data
36 - Update Tx locking
37 - Clean up PCI enable (davej)
38 Version 1.0.4:
39 - Merge Donald Becker's natsemi.c version 1.07
40 Version 1.0.5:
41 - { fill me in }
42 Version 1.0.6:
43 * ethtool support (jgarzik)
44 * Proper initialization of the card (which sometimes
45 fails to occur and leaves the card in a non-functional
46 state). (uzi)
47
48 * Some documented register settings to optimize some
49 of the 100Mbit autodetection circuitry in rev C cards. (uzi)
50
51 * Polling of the PHY intr for stuff like link state
52 change and auto- negotiation to finally work properly. (uzi)
53
54 * One-liner removal of a duplicate declaration of
55 netdev_error(). (uzi)
56
57 Version 1.0.7: (Manfred Spraul)
58 * pci dma
59 * SMP locking update
60 * full reset added into tx_timeout
61 * correct multicast hash generation (both big and little endian)
62 [copied from a natsemi driver version
63 from Myrio Corporation, Greg Smith]
64 * suspend/resume
65
66 version 1.0.8 (Tim Hockin <thockin@sun.com>)
67 * ETHTOOL_* support
68 * Wake on lan support (Erik Gilling)
69 * MXDMA fixes for serverworks
70 * EEPROM reload
71
72 version 1.0.9 (Manfred Spraul)
73 * Main change: fix lack of synchronize
74 netif_close/netif_suspend against a last interrupt
75 or packet.
76 * do not enable superflous interrupts (e.g. the
77 drivers relies on TxDone - TxIntr not needed)
78 * wait that the hardware has really stopped in close
79 and suspend.
80 * workaround for the (at least) gcc-2.95.1 compiler
81 problem. Also simplifies the code a bit.
82 * disable_irq() in tx_timeout - needed to protect
83 against rx interrupts.
84 * stop the nic before switching into silent rx mode
85 for wol (required according to docu).
86
87 version 1.0.10:
88 * use long for ee_addr (various)
89 * print pointers properly (DaveM)
90 * include asm/irq.h (?)
91
92 version 1.0.11:
93 * check and reset if PHY errors appear (Adrian Sun)
94 * WoL cleanup (Tim Hockin)
95 * Magic number cleanup (Tim Hockin)
96 * Don't reload EEPROM on every reset (Tim Hockin)
97 * Save and restore EEPROM state across reset (Tim Hockin)
98 * MDIO Cleanup (Tim Hockin)
99 * Reformat register offsets/bits (jgarzik)
100
101 version 1.0.12:
102 * ETHTOOL_* further support (Tim Hockin)
103
104 version 1.0.13:
105 * ETHTOOL_[G]EEPROM support (Tim Hockin)
106
107 version 1.0.13:
108 * crc cleanup (Matt Domsch <Matt_Domsch@dell.com>)
109
110 version 1.0.14:
111 * Cleanup some messages and autoneg in ethtool (Tim Hockin)
112
113 version 1.0.15:
114 * Get rid of cable_magic flag
115 * use new (National provided) solution for cable magic issue
116
117 version 1.0.16:
118 * call netdev_rx() for RxErrors (Manfred Spraul)
119 * formatting and cleanups
120 * change options and full_duplex arrays to be zero
121 initialized
122 * enable only the WoL and PHY interrupts in wol mode
123
124 version 1.0.17:
125 * only do cable_magic on 83815 and early 83816 (Tim Hockin)
126 * create a function for rx refill (Manfred Spraul)
127 * combine drain_ring and init_ring (Manfred Spraul)
128 * oom handling (Manfred Spraul)
129 * hands_off instead of playing with netif_device_{de,a}ttach
130 (Manfred Spraul)
131 * be sure to write the MAC back to the chip (Manfred Spraul)
132 * lengthen EEPROM timeout, and always warn about timeouts
133 (Manfred Spraul)
134 * comments update (Manfred)
135 * do the right thing on a phy-reset (Manfred and Tim)
136
137 TODO:
138 * big endian support with CFG:BEM instead of cpu_to_le32
1da177e4
LT		 139*/
140
1da177e4
LT		 141#include <linux/module.h>
142#include <linux/kernel.h>
143#include <linux/string.h>
144#include <linux/timer.h>
145#include <linux/errno.h>
146#include <linux/ioport.h>
147#include <linux/slab.h>
148#include <linux/interrupt.h>
149#include <linux/pci.h>
150#include <linux/netdevice.h>
151#include <linux/etherdevice.h>
152#include <linux/skbuff.h>
153#include <linux/init.h>
154#include <linux/spinlock.h>
155#include <linux/ethtool.h>
156#include <linux/delay.h>
157#include <linux/rtnetlink.h>
158#include <linux/mii.h>
159#include <linux/crc32.h>
160#include <linux/bitops.h>
b27a16b7 161#include <linux/prefetch.h>
1da177e4
LT		 162#include <asm/processor.h> /* Processor type for cache alignment. */
163#include <asm/io.h>
164#include <asm/irq.h>
165#include <asm/uaccess.h>
166
167#define DRV_NAME "natsemi"
168#define DRV_VERSION "1.07+LK1.0.17"
169#define DRV_RELDATE "Sep 27, 2002"
170
171#define RX_OFFSET 2
172
173/* Updated to recommendations in pci-skeleton v2.03. */
174
175/* The user-configurable values.
176 These may be modified when a driver module is loaded.*/
177
178#define NATSEMI_DEF_MSG (NETIF_MSG_DRV | \
179 NETIF_MSG_LINK | \
180 NETIF_MSG_WOL | \
181 NETIF_MSG_RX_ERR | \
182 NETIF_MSG_TX_ERR)
183static int debug = -1;
184
1da177e4
LT		 185static int mtu;
186
187/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
188 This chip uses a 512 element hash table based on the Ethernet CRC. */
f71e1309 189static const int multicast_filter_limit = 100;
1da177e4
LT		 190
191/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
192 Setting to > 1518 effectively disables this feature. */
193static int rx_copybreak;
194
195/* Used to pass the media type, etc.
196 Both 'options[]' and 'full_duplex[]' should exist for driver
197 interoperability.
198 The media type is usually passed in 'options[]'.
199*/
200#define MAX_UNITS 8 /* More are supported, limit only on options */
201static int options[MAX_UNITS];
202static int full_duplex[MAX_UNITS];
203
204/* Operational parameters that are set at compile time. */
205
206/* Keep the ring sizes a power of two for compile efficiency.
207 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
208 Making the Tx ring too large decreases the effectiveness of channel
209 bonding and packet priority.
210 There are no ill effects from too-large receive rings. */
211#define TX_RING_SIZE 16
212#define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */
213#define RX_RING_SIZE 32
214
215/* Operational parameters that usually are not changed. */
216/* Time in jiffies before concluding the transmitter is hung. */
217#define TX_TIMEOUT (2*HZ)
218
219#define NATSEMI_HW_TIMEOUT 400
220#define NATSEMI_TIMER_FREQ 3*HZ
221#define NATSEMI_PG0_NREGS 64
222#define NATSEMI_RFDR_NREGS 8
223#define NATSEMI_PG1_NREGS 4
224#define NATSEMI_NREGS (NATSEMI_PG0_NREGS + NATSEMI_RFDR_NREGS + \
225 NATSEMI_PG1_NREGS)
226#define NATSEMI_REGS_VER 1 /* v1 added RFDR registers */
227#define NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32))
1da177e4
LT		 228
229/* Buffer sizes:
230 * The nic writes 32-bit values, even if the upper bytes of
231 * a 32-bit value are beyond the end of the buffer.
232 */
233#define NATSEMI_HEADERS 22 /* 2*mac,type,vlan,crc */
234#define NATSEMI_PADDING 16 /* 2 bytes should be sufficient */
235#define NATSEMI_LONGPKT 1518 /* limit for normal packets */
236#define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */
237
238/* These identify the driver base version and may not be removed. */
e19360f2 239static const char version[] __devinitdata =
1da177e4
LT		 240 KERN_INFO DRV_NAME " dp8381x driver, version "
241 DRV_VERSION ", " DRV_RELDATE "\n"
242 KERN_INFO " originally by Donald Becker <becker@scyld.com>\n"
243 KERN_INFO " http://www.scyld.com/network/natsemi.html\n"
244 KERN_INFO " 2.4.x kernel port by Jeff Garzik, Tjeerd Mulder\n";
245
246MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
247MODULE_DESCRIPTION("National Semiconductor DP8381x series PCI Ethernet driver");
248MODULE_LICENSE("GPL");
249
1da177e4
LT		 250module_param(mtu, int, 0);
251module_param(debug, int, 0);
252module_param(rx_copybreak, int, 0);
253module_param_array(options, int, NULL, 0);
254module_param_array(full_duplex, int, NULL, 0);
1da177e4
LT		 255MODULE_PARM_DESC(mtu, "DP8381x MTU (all boards)");
256MODULE_PARM_DESC(debug, "DP8381x default debug level");
257MODULE_PARM_DESC(rx_copybreak,
258 "DP8381x copy breakpoint for copy-only-tiny-frames");
259MODULE_PARM_DESC(options,
260 "DP8381x: Bits 0-3: media type, bit 17: full duplex");
261MODULE_PARM_DESC(full_duplex, "DP8381x full duplex setting(s) (1)");
262
263/*
264 Theory of Operation
265
266I. Board Compatibility
267
268This driver is designed for National Semiconductor DP83815 PCI Ethernet NIC.
269It also works with other chips in in the DP83810 series.
270
271II. Board-specific settings
272
273This driver requires the PCI interrupt line to be valid.
274It honors the EEPROM-set values.
275
276III. Driver operation
277
278IIIa. Ring buffers
279
280This driver uses two statically allocated fixed-size descriptor lists
281formed into rings by a branch from the final descriptor to the beginning of
282the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
283The NatSemi design uses a 'next descriptor' pointer that the driver forms
284into a list.
285
286IIIb/c. Transmit/Receive Structure
287
288This driver uses a zero-copy receive and transmit scheme.
289The driver allocates full frame size skbuffs for the Rx ring buffers at
290open() time and passes the skb->data field to the chip as receive data
291buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
292a fresh skbuff is allocated and the frame is copied to the new skbuff.
293When the incoming frame is larger, the skbuff is passed directly up the
294protocol stack. Buffers consumed this way are replaced by newly allocated
295skbuffs in a later phase of receives.
296
297The RX_COPYBREAK value is chosen to trade-off the memory wasted by
298using a full-sized skbuff for small frames vs. the copying costs of larger
299frames. New boards are typically used in generously configured machines
300and the underfilled buffers have negligible impact compared to the benefit of
301a single allocation size, so the default value of zero results in never
302copying packets. When copying is done, the cost is usually mitigated by using
303a combined copy/checksum routine. Copying also preloads the cache, which is
304most useful with small frames.
305
306A subtle aspect of the operation is that unaligned buffers are not permitted
307by the hardware. Thus the IP header at offset 14 in an ethernet frame isn't
308longword aligned for further processing. On copies frames are put into the
309skbuff at an offset of "+2", 16-byte aligning the IP header.
310
311IIId. Synchronization
312
313Most operations are synchronized on the np->lock irq spinlock, except the
314performance critical codepaths:
315
316The rx process only runs in the interrupt handler. Access from outside
317the interrupt handler is only permitted after disable_irq().
318
932ff279 319The rx process usually runs under the netif_tx_lock. If np->intr_tx_reap
1da177e4
LT		 320is set, then access is permitted under spin_lock_irq(&np->lock).
321
322Thus configuration functions that want to access everything must call
323 disable_irq(dev->irq);
932ff279 324 netif_tx_lock_bh(dev);
1da177e4
LT		 325 spin_lock_irq(&np->lock);
326
327IV. Notes
328
329NatSemi PCI network controllers are very uncommon.
330
331IVb. References
332
333http://www.scyld.com/expert/100mbps.html
334http://www.scyld.com/expert/NWay.html
335Datasheet is available from:
336http://www.national.com/pf/DP/DP83815.html
337
338IVc. Errata
339
340None characterised.
341*/
342
343
344
1da177e4
LT		 345/*
346 * Support for fibre connections on Am79C874:
347 * This phy needs a special setup when connected to a fibre cable.
348 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf
349 */
350#define PHYID_AM79C874 0x0022561b
351
a2b524b2
JG		 352enum {
353 MII_MCTRL = 0x15, /* mode control register */
354 MII_FX_SEL = 0x0001, /* 100BASE-FX (fiber) */
355 MII_EN_SCRM = 0x0004, /* enable scrambler (tp) */
356};
1da177e4
LT		 357
358
359/* array of board data directly indexed by pci_tbl[x].driver_data */
f71e1309 360static const struct {
1da177e4
LT		 361 const char *name;
362 unsigned long flags;
a2b524b2 363 unsigned int eeprom_size;
1da177e4 364} natsemi_pci_info[] __devinitdata = {
a2b524b2 365 { "NatSemi DP8381[56]", 0, 24 },
1da177e4
LT		 366};
367
a2b524b2
JG		 368static const struct pci_device_id natsemi_pci_tbl[] __devinitdata = {
369 { PCI_VENDOR_ID_NS, 0x0020, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
370 { } /* terminate list */
1da177e4
LT		 371};
372MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl);
373
374/* Offsets to the device registers.
375 Unlike software-only systems, device drivers interact with complex hardware.
376 It's not useful to define symbolic names for every register bit in the
377 device.
378*/
379enum register_offsets {
380 ChipCmd = 0x00,
381 ChipConfig = 0x04,
382 EECtrl = 0x08,
383 PCIBusCfg = 0x0C,
384 IntrStatus = 0x10,
385 IntrMask = 0x14,
386 IntrEnable = 0x18,
387 IntrHoldoff = 0x1C, /* DP83816 only */
388 TxRingPtr = 0x20,
389 TxConfig = 0x24,
390 RxRingPtr = 0x30,
391 RxConfig = 0x34,
392 ClkRun = 0x3C,
393 WOLCmd = 0x40,
394 PauseCmd = 0x44,
395 RxFilterAddr = 0x48,
396 RxFilterData = 0x4C,
397 BootRomAddr = 0x50,
398 BootRomData = 0x54,
399 SiliconRev = 0x58,
400 StatsCtrl = 0x5C,
401 StatsData = 0x60,
402 RxPktErrs = 0x60,
403 RxMissed = 0x68,
404 RxCRCErrs = 0x64,
405 BasicControl = 0x80,
406 BasicStatus = 0x84,
407 AnegAdv = 0x90,
408 AnegPeer = 0x94,
409 PhyStatus = 0xC0,
410 MIntrCtrl = 0xC4,
411 MIntrStatus = 0xC8,
412 PhyCtrl = 0xE4,
413
414 /* These are from the spec, around page 78... on a separate table.
415 * The meaning of these registers depend on the value of PGSEL. */
416 PGSEL = 0xCC,
417 PMDCSR = 0xE4,
418 TSTDAT = 0xFC,
419 DSPCFG = 0xF4,
420 SDCFG = 0xF8
421};
422/* the values for the 'magic' registers above (PGSEL=1) */
423#define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */
424#define TSTDAT_VAL 0x0
425#define DSPCFG_VAL 0x5040
426#define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */
427#define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */
428#define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */
429#define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */
430
431/* misc PCI space registers */
432enum pci_register_offsets {
433 PCIPM = 0x44,
434};
435
436enum ChipCmd_bits {
437 ChipReset = 0x100,
438 RxReset = 0x20,
439 TxReset = 0x10,
440 RxOff = 0x08,
441 RxOn = 0x04,
442 TxOff = 0x02,
443 TxOn = 0x01,
444};
445
446enum ChipConfig_bits {
447 CfgPhyDis = 0x200,
448 CfgPhyRst = 0x400,
449 CfgExtPhy = 0x1000,
450 CfgAnegEnable = 0x2000,
451 CfgAneg100 = 0x4000,
452 CfgAnegFull = 0x8000,
453 CfgAnegDone = 0x8000000,
454 CfgFullDuplex = 0x20000000,
455 CfgSpeed100 = 0x40000000,
456 CfgLink = 0x80000000,
457};
458
459enum EECtrl_bits {
460 EE_ShiftClk = 0x04,
461 EE_DataIn = 0x01,
462 EE_ChipSelect = 0x08,
463 EE_DataOut = 0x02,
464 MII_Data = 0x10,
465 MII_Write = 0x20,
466 MII_ShiftClk = 0x40,
467};
468
469enum PCIBusCfg_bits {
470 EepromReload = 0x4,
471};
472
473/* Bits in the interrupt status/mask registers. */
474enum IntrStatus_bits {
475 IntrRxDone = 0x0001,
476 IntrRxIntr = 0x0002,
477 IntrRxErr = 0x0004,
478 IntrRxEarly = 0x0008,
479 IntrRxIdle = 0x0010,
480 IntrRxOverrun = 0x0020,
481 IntrTxDone = 0x0040,
482 IntrTxIntr = 0x0080,
483 IntrTxErr = 0x0100,
484 IntrTxIdle = 0x0200,
485 IntrTxUnderrun = 0x0400,
486 StatsMax = 0x0800,
487 SWInt = 0x1000,
488 WOLPkt = 0x2000,
489 LinkChange = 0x4000,
490 IntrHighBits = 0x8000,
491 RxStatusFIFOOver = 0x10000,
492 IntrPCIErr = 0xf00000,
493 RxResetDone = 0x1000000,
494 TxResetDone = 0x2000000,
495 IntrAbnormalSummary = 0xCD20,
496};
497
498/*
499 * Default Interrupts:
500 * Rx OK, Rx Packet Error, Rx Overrun,
501 * Tx OK, Tx Packet Error, Tx Underrun,
502 * MIB Service, Phy Interrupt, High Bits,
503 * Rx Status FIFO overrun,
504 * Received Target Abort, Received Master Abort,
505 * Signalled System Error, Received Parity Error
506 */
507#define DEFAULT_INTR 0x00f1cd65
508
509enum TxConfig_bits {
510 TxDrthMask = 0x3f,
511 TxFlthMask = 0x3f00,
512 TxMxdmaMask = 0x700000,
513 TxMxdma_512 = 0x0,
514 TxMxdma_4 = 0x100000,
515 TxMxdma_8 = 0x200000,
516 TxMxdma_16 = 0x300000,
517 TxMxdma_32 = 0x400000,
518 TxMxdma_64 = 0x500000,
519 TxMxdma_128 = 0x600000,
520 TxMxdma_256 = 0x700000,
521 TxCollRetry = 0x800000,
522 TxAutoPad = 0x10000000,
523 TxMacLoop = 0x20000000,
524 TxHeartIgn = 0x40000000,
525 TxCarrierIgn = 0x80000000
526};
527
528/*
529 * Tx Configuration:
530 * - 256 byte DMA burst length
531 * - fill threshold 512 bytes (i.e. restart DMA when 512 bytes are free)
532 * - 64 bytes initial drain threshold (i.e. begin actual transmission
533 * when 64 byte are in the fifo)
534 * - on tx underruns, increase drain threshold by 64.
535 * - at most use a drain threshold of 1472 bytes: The sum of the fill
536 * threshold and the drain threshold must be less than 2016 bytes.
537 *
538 */
539#define TX_FLTH_VAL ((512/32) << 8)
540#define TX_DRTH_VAL_START (64/32)
541#define TX_DRTH_VAL_INC 2
542#define TX_DRTH_VAL_LIMIT (1472/32)
543
544enum RxConfig_bits {
545 RxDrthMask = 0x3e,
546 RxMxdmaMask = 0x700000,
547 RxMxdma_512 = 0x0,
548 RxMxdma_4 = 0x100000,
549 RxMxdma_8 = 0x200000,
550 RxMxdma_16 = 0x300000,
551 RxMxdma_32 = 0x400000,
552 RxMxdma_64 = 0x500000,
553 RxMxdma_128 = 0x600000,
554 RxMxdma_256 = 0x700000,
555 RxAcceptLong = 0x8000000,
556 RxAcceptTx = 0x10000000,
557 RxAcceptRunt = 0x40000000,
558 RxAcceptErr = 0x80000000
559};
560#define RX_DRTH_VAL (128/8)
561
562enum ClkRun_bits {
563 PMEEnable = 0x100,
564 PMEStatus = 0x8000,
565};
566
567enum WolCmd_bits {
568 WakePhy = 0x1,
569 WakeUnicast = 0x2,
570 WakeMulticast = 0x4,
571 WakeBroadcast = 0x8,
572 WakeArp = 0x10,
573 WakePMatch0 = 0x20,
574 WakePMatch1 = 0x40,
575 WakePMatch2 = 0x80,
576 WakePMatch3 = 0x100,
577 WakeMagic = 0x200,
578 WakeMagicSecure = 0x400,
579 SecureHack = 0x100000,
580 WokePhy = 0x400000,
581 WokeUnicast = 0x800000,
582 WokeMulticast = 0x1000000,
583 WokeBroadcast = 0x2000000,
584 WokeArp = 0x4000000,
585 WokePMatch0 = 0x8000000,
586 WokePMatch1 = 0x10000000,
587 WokePMatch2 = 0x20000000,
588 WokePMatch3 = 0x40000000,
589 WokeMagic = 0x80000000,
590 WakeOptsSummary = 0x7ff
591};
592
593enum RxFilterAddr_bits {
594 RFCRAddressMask = 0x3ff,
595 AcceptMulticast = 0x00200000,
596 AcceptMyPhys = 0x08000000,
597 AcceptAllPhys = 0x10000000,
598 AcceptAllMulticast = 0x20000000,
599 AcceptBroadcast = 0x40000000,
600 RxFilterEnable = 0x80000000
601};
602
603enum StatsCtrl_bits {
604 StatsWarn = 0x1,
605 StatsFreeze = 0x2,
606 StatsClear = 0x4,
607 StatsStrobe = 0x8,
608};
609
610enum MIntrCtrl_bits {
611 MICRIntEn = 0x2,
612};
613
614enum PhyCtrl_bits {
615 PhyAddrMask = 0x1f,
616};
617
618#define PHY_ADDR_NONE 32
619#define PHY_ADDR_INTERNAL 1
620
621/* values we might find in the silicon revision register */
622#define SRR_DP83815_C 0x0302
623#define SRR_DP83815_D 0x0403
624#define SRR_DP83816_A4 0x0504
625#define SRR_DP83816_A5 0x0505
626
627/* The Rx and Tx buffer descriptors. */
628/* Note that using only 32 bit fields simplifies conversion to big-endian
629 architectures. */
630struct netdev_desc {
631 u32 next_desc;
632 s32 cmd_status;
633 u32 addr;
634 u32 software_use;
635};
636
637/* Bits in network_desc.status */
638enum desc_status_bits {
639 DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000,
640 DescNoCRC=0x10000000, DescPktOK=0x08000000,
641 DescSizeMask=0xfff,
642
643 DescTxAbort=0x04000000, DescTxFIFO=0x02000000,
644 DescTxCarrier=0x01000000, DescTxDefer=0x00800000,
645 DescTxExcDefer=0x00400000, DescTxOOWCol=0x00200000,
646 DescTxExcColl=0x00100000, DescTxCollCount=0x000f0000,
647
648 DescRxAbort=0x04000000, DescRxOver=0x02000000,
649 DescRxDest=0x01800000, DescRxLong=0x00400000,
650 DescRxRunt=0x00200000, DescRxInvalid=0x00100000,
651 DescRxCRC=0x00080000, DescRxAlign=0x00040000,
652 DescRxLoop=0x00020000, DesRxColl=0x00010000,
653};
654
655struct netdev_private {
656 /* Descriptor rings first for alignment */
657 dma_addr_t ring_dma;
658 struct netdev_desc *rx_ring;
659 struct netdev_desc *tx_ring;
660 /* The addresses of receive-in-place skbuffs */
661 struct sk_buff *rx_skbuff[RX_RING_SIZE];
662 dma_addr_t rx_dma[RX_RING_SIZE];
663 /* address of a sent-in-place packet/buffer, for later free() */
664 struct sk_buff *tx_skbuff[TX_RING_SIZE];
665 dma_addr_t tx_dma[TX_RING_SIZE];
666 struct net_device_stats stats;
667 /* Media monitoring timer */
668 struct timer_list timer;
669 /* Frequently used values: keep some adjacent for cache effect */
670 struct pci_dev *pci_dev;
671 struct netdev_desc *rx_head_desc;
672 /* Producer/consumer ring indices */
673 unsigned int cur_rx, dirty_rx;
674 unsigned int cur_tx, dirty_tx;
675 /* Based on MTU+slack. */
676 unsigned int rx_buf_sz;
677 int oom;
b27a16b7
MB		 678 /* Interrupt status */
679 u32 intr_status;
1da177e4
LT		 680 /* Do not touch the nic registers */
681 int hands_off;
682 /* external phy that is used: only valid if dev->if_port != PORT_TP */
683 int mii;
684 int phy_addr_external;
685 unsigned int full_duplex;
686 /* Rx filter */
687 u32 cur_rx_mode;
688 u32 rx_filter[16];
689 /* FIFO and PCI burst thresholds */
690 u32 tx_config, rx_config;
691 /* original contents of ClkRun register */
692 u32 SavedClkRun;
693 /* silicon revision */
694 u32 srr;
695 /* expected DSPCFG value */
696 u16 dspcfg;
697 /* parms saved in ethtool format */
698 u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */
699 u8 duplex; /* Duplex, half or full */
700 u8 autoneg; /* Autonegotiation enabled */
701 /* MII transceiver section */
702 u16 advertising;
703 unsigned int iosize;
704 spinlock_t lock;
705 u32 msg_enable;
a8b4cf42
MB		 706 /* EEPROM data */
707 int eeprom_size;
1da177e4
LT		 708};
709
710static void move_int_phy(struct net_device *dev, int addr);
711static int eeprom_read(void __iomem *ioaddr, int location);
712static int mdio_read(struct net_device *dev, int reg);
713static void mdio_write(struct net_device *dev, int reg, u16 data);
714static void init_phy_fixup(struct net_device *dev);
715static int miiport_read(struct net_device *dev, int phy_id, int reg);
716static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data);
717static int find_mii(struct net_device *dev);
718static void natsemi_reset(struct net_device *dev);
719static void natsemi_reload_eeprom(struct net_device *dev);
720static void natsemi_stop_rxtx(struct net_device *dev);
721static int netdev_open(struct net_device *dev);
722static void do_cable_magic(struct net_device *dev);
723static void undo_cable_magic(struct net_device *dev);
724static void check_link(struct net_device *dev);
725static void netdev_timer(unsigned long data);
726static void dump_ring(struct net_device *dev);
727static void tx_timeout(struct net_device *dev);
728static int alloc_ring(struct net_device *dev);
729static void refill_rx(struct net_device *dev);
730static void init_ring(struct net_device *dev);
731static void drain_tx(struct net_device *dev);
732static void drain_ring(struct net_device *dev);
733static void free_ring(struct net_device *dev);
734static void reinit_ring(struct net_device *dev);
735static void init_registers(struct net_device *dev);
736static int start_tx(struct sk_buff *skb, struct net_device *dev);
737static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *regs);
738static void netdev_error(struct net_device *dev, int intr_status);
b27a16b7
MB		 739static int natsemi_poll(struct net_device *dev, int *budget);
740static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do);
1da177e4
LT		 741static void netdev_tx_done(struct net_device *dev);
742static int natsemi_change_mtu(struct net_device *dev, int new_mtu);
743#ifdef CONFIG_NET_POLL_CONTROLLER
744static void natsemi_poll_controller(struct net_device *dev);
745#endif
746static void __set_rx_mode(struct net_device *dev);
747static void set_rx_mode(struct net_device *dev);
748static void __get_stats(struct net_device *dev);
749static struct net_device_stats *get_stats(struct net_device *dev);
750static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
751static int netdev_set_wol(struct net_device *dev, u32 newval);
752static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur);
753static int netdev_set_sopass(struct net_device *dev, u8 *newval);
754static int netdev_get_sopass(struct net_device *dev, u8 *data);
755static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
756static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
757static void enable_wol_mode(struct net_device *dev, int enable_intr);
758static int netdev_close(struct net_device *dev);
759static int netdev_get_regs(struct net_device *dev, u8 *buf);
760static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
761static struct ethtool_ops ethtool_ops;
762
763static inline void __iomem *ns_ioaddr(struct net_device *dev)
764{
765 return (void __iomem *) dev->base_addr;
766}
767
b27a16b7
MB		 768static inline void natsemi_irq_enable(struct net_device *dev)
769{
770 writel(1, ns_ioaddr(dev) + IntrEnable);
771 readl(ns_ioaddr(dev) + IntrEnable);
772}
773
774static inline void natsemi_irq_disable(struct net_device *dev)
775{
776 writel(0, ns_ioaddr(dev) + IntrEnable);
777 readl(ns_ioaddr(dev) + IntrEnable);
778}
779
1da177e4
LT		 780static void move_int_phy(struct net_device *dev, int addr)
781{
782 struct netdev_private *np = netdev_priv(dev);
783 void __iomem *ioaddr = ns_ioaddr(dev);
784 int target = 31;
785
786 /*
787 * The internal phy is visible on the external mii bus. Therefore we must
788 * move it away before we can send commands to an external phy.
789 * There are two addresses we must avoid:
790 * - the address on the external phy that is used for transmission.
791 * - the address that we want to access. User space can access phys
792 * on the mii bus with SIOCGMIIREG/SIOCSMIIREG, independant from the
793 * phy that is used for transmission.
794 */
795
796 if (target == addr)
797 target--;
798 if (target == np->phy_addr_external)
799 target--;
800 writew(target, ioaddr + PhyCtrl);
801 readw(ioaddr + PhyCtrl);
802 udelay(1);
803}
804
5a40f09b
JG		 805static void __devinit natsemi_init_media (struct net_device *dev)
806{
807 struct netdev_private *np = netdev_priv(dev);
808 u32 tmp;
809
810 netif_carrier_off(dev);
811
812 /* get the initial settings from hardware */
813 tmp = mdio_read(dev, MII_BMCR);
814 np->speed = (tmp & BMCR_SPEED100)? SPEED_100 : SPEED_10;
815 np->duplex = (tmp & BMCR_FULLDPLX)? DUPLEX_FULL : DUPLEX_HALF;
816 np->autoneg = (tmp & BMCR_ANENABLE)? AUTONEG_ENABLE: AUTONEG_DISABLE;
817 np->advertising= mdio_read(dev, MII_ADVERTISE);
818
819 if ((np->advertising & ADVERTISE_ALL) != ADVERTISE_ALL
820 && netif_msg_probe(np)) {
821 printk(KERN_INFO "natsemi %s: Transceiver default autonegotiation %s "
822 "10%s %s duplex.\n",
823 pci_name(np->pci_dev),
824 (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE)?
825 "enabled, advertise" : "disabled, force",
826 (np->advertising &
827 (ADVERTISE_100FULL|ADVERTISE_100HALF))?
828 "0" : "",
829 (np->advertising &
830 (ADVERTISE_100FULL|ADVERTISE_10FULL))?
831 "full" : "half");
832 }
833 if (netif_msg_probe(np))
834 printk(KERN_INFO
835 "natsemi %s: Transceiver status %#04x advertising %#04x.\n",
836 pci_name(np->pci_dev), mdio_read(dev, MII_BMSR),
837 np->advertising);
838
839}
840
1da177e4
LT		 841static int __devinit natsemi_probe1 (struct pci_dev *pdev,
842 const struct pci_device_id *ent)
843{
844 struct net_device *dev;
845 struct netdev_private *np;
846 int i, option, irq, chip_idx = ent->driver_data;
847 static int find_cnt = -1;
848 unsigned long iostart, iosize;
849 void __iomem *ioaddr;
850 const int pcibar = 1; /* PCI base address register */
851 int prev_eedata;
852 u32 tmp;
853
854/* when built into the kernel, we only print version if device is found */
855#ifndef MODULE
856 static int printed_version;
857 if (!printed_version++)
858 printk(version);
859#endif
860
861 i = pci_enable_device(pdev);
862 if (i) return i;
863
864 /* natsemi has a non-standard PM control register
865 * in PCI config space. Some boards apparently need
866 * to be brought to D0 in this manner.
867 */
868 pci_read_config_dword(pdev, PCIPM, &tmp);
869 if (tmp & PCI_PM_CTRL_STATE_MASK) {
870 /* D0 state, disable PME assertion */
871 u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK;
872 pci_write_config_dword(pdev, PCIPM, newtmp);
873 }
874
875 find_cnt++;
876 iostart = pci_resource_start(pdev, pcibar);
877 iosize = pci_resource_len(pdev, pcibar);
878 irq = pdev->irq;
879
a2b524b2 880 pci_set_master(pdev);
1da177e4
LT		 881
882 dev = alloc_etherdev(sizeof (struct netdev_private));
883 if (!dev)
884 return -ENOMEM;
885 SET_MODULE_OWNER(dev);
886 SET_NETDEV_DEV(dev, &pdev->dev);
887
888 i = pci_request_regions(pdev, DRV_NAME);
889 if (i)
890 goto err_pci_request_regions;
891
892 ioaddr = ioremap(iostart, iosize);
893 if (!ioaddr) {
894 i = -ENOMEM;
895 goto err_ioremap;
896 }
897
898 /* Work around the dropped serial bit. */
899 prev_eedata = eeprom_read(ioaddr, 6);
900 for (i = 0; i < 3; i++) {
901 int eedata = eeprom_read(ioaddr, i + 7);
902 dev->dev_addr[i*2] = (eedata << 1) + (prev_eedata >> 15);
903 dev->dev_addr[i*2+1] = eedata >> 7;
904 prev_eedata = eedata;
905 }
906
907 dev->base_addr = (unsigned long __force) ioaddr;
908 dev->irq = irq;
909
910 np = netdev_priv(dev);
911
912 np->pci_dev = pdev;
913 pci_set_drvdata(pdev, dev);
914 np->iosize = iosize;
915 spin_lock_init(&np->lock);
916 np->msg_enable = (debug >= 0) ? (1<<debug)-1 : NATSEMI_DEF_MSG;
917 np->hands_off = 0;
b27a16b7 918 np->intr_status = 0;
a2b524b2 919 np->eeprom_size = natsemi_pci_info[chip_idx].eeprom_size;
1da177e4
LT		 920
921 /* Initial port:
922 * - If the nic was configured to use an external phy and if find_mii
923 * finds a phy: use external port, first phy that replies.
924 * - Otherwise: internal port.
925 * Note that the phy address for the internal phy doesn't matter:
926 * The address would be used to access a phy over the mii bus, but
927 * the internal phy is accessed through mapped registers.
928 */
929 if (readl(ioaddr + ChipConfig) & CfgExtPhy)
930 dev->if_port = PORT_MII;
931 else
932 dev->if_port = PORT_TP;
933 /* Reset the chip to erase previous misconfiguration. */
934 natsemi_reload_eeprom(dev);
935 natsemi_reset(dev);
936
937 if (dev->if_port != PORT_TP) {
938 np->phy_addr_external = find_mii(dev);
939 if (np->phy_addr_external == PHY_ADDR_NONE) {
940 dev->if_port = PORT_TP;
941 np->phy_addr_external = PHY_ADDR_INTERNAL;
942 }
943 } else {
944 np->phy_addr_external = PHY_ADDR_INTERNAL;
945 }
946
947 option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
948 if (dev->mem_start)
949 option = dev->mem_start;
950
951 /* The lower four bits are the media type. */
952 if (option) {
953 if (option & 0x200)
954 np->full_duplex = 1;
955 if (option & 15)
956 printk(KERN_INFO
957 "natsemi %s: ignoring user supplied media type %d",
958 pci_name(np->pci_dev), option & 15);
959 }
960 if (find_cnt < MAX_UNITS && full_duplex[find_cnt])
961 np->full_duplex = 1;
962
963 /* The chip-specific entries in the device structure. */
964 dev->open = &netdev_open;
965 dev->hard_start_xmit = &start_tx;
966 dev->stop = &netdev_close;
967 dev->get_stats = &get_stats;
968 dev->set_multicast_list = &set_rx_mode;
969 dev->change_mtu = &natsemi_change_mtu;
970 dev->do_ioctl = &netdev_ioctl;
971 dev->tx_timeout = &tx_timeout;
972 dev->watchdog_timeo = TX_TIMEOUT;
b27a16b7
MB		 973 dev->poll = natsemi_poll;
974 dev->weight = 64;
975
1da177e4
LT		 976#ifdef CONFIG_NET_POLL_CONTROLLER
977 dev->poll_controller = &natsemi_poll_controller;
978#endif
979 SET_ETHTOOL_OPS(dev, &ethtool_ops);
980
981 if (mtu)
982 dev->mtu = mtu;
983
5a40f09b 984 natsemi_init_media(dev);
1da177e4
LT		 985
986 /* save the silicon revision for later querying */
987 np->srr = readl(ioaddr + SiliconRev);
988 if (netif_msg_hw(np))
989 printk(KERN_INFO "natsemi %s: silicon revision %#04x.\n",
990 pci_name(np->pci_dev), np->srr);
991
992 i = register_netdev(dev);
993 if (i)
994 goto err_register_netdev;
995
996 if (netif_msg_drv(np)) {
997 printk(KERN_INFO "natsemi %s: %s at %#08lx (%s), ",
998 dev->name, natsemi_pci_info[chip_idx].name, iostart,
999 pci_name(np->pci_dev));
1000 for (i = 0; i < ETH_ALEN-1; i++)
1001 printk("%02x:", dev->dev_addr[i]);
1002 printk("%02x, IRQ %d", dev->dev_addr[i], irq);
1003 if (dev->if_port == PORT_TP)
1004 printk(", port TP.\n");
1005 else
1006 printk(", port MII, phy ad %d.\n", np->phy_addr_external);
1007 }
1008 return 0;
1009
1010 err_register_netdev:
1011 iounmap(ioaddr);
1012
1013 err_ioremap:
1014 pci_release_regions(pdev);
1015 pci_set_drvdata(pdev, NULL);
1016
1017 err_pci_request_regions:
1018 free_netdev(dev);
1019 return i;
1020}
1021
1022
1023/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
1024 The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */
1025
1026/* Delay between EEPROM clock transitions.
1027 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
1028 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
1029 made udelay() unreliable.
1030 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
1031 depricated.
1032*/
1033#define eeprom_delay(ee_addr) readl(ee_addr)
1034
1035#define EE_Write0 (EE_ChipSelect)
1036#define EE_Write1 (EE_ChipSelect | EE_DataIn)
1037
1038/* The EEPROM commands include the alway-set leading bit. */
1039enum EEPROM_Cmds {
1040 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
1041};
1042
1043static int eeprom_read(void __iomem *addr, int location)
1044{
1045 int i;
1046 int retval = 0;
1047 void __iomem *ee_addr = addr + EECtrl;
1048 int read_cmd = location | EE_ReadCmd;
1049
1050 writel(EE_Write0, ee_addr);
1051
1052 /* Shift the read command bits out. */
1053 for (i = 10; i >= 0; i--) {
1054 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
1055 writel(dataval, ee_addr);
1056 eeprom_delay(ee_addr);
1057 writel(dataval | EE_ShiftClk, ee_addr);
1058 eeprom_delay(ee_addr);
1059 }
1060 writel(EE_ChipSelect, ee_addr);
1061 eeprom_delay(ee_addr);
1062
1063 for (i = 0; i < 16; i++) {
1064 writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
1065 eeprom_delay(ee_addr);
1066 retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0;
1067 writel(EE_ChipSelect, ee_addr);
1068 eeprom_delay(ee_addr);
1069 }
1070
1071 /* Terminate the EEPROM access. */
1072 writel(EE_Write0, ee_addr);
1073 writel(0, ee_addr);
1074 return retval;
1075}
1076
1077/* MII transceiver control section.
1078 * The 83815 series has an internal transceiver, and we present the
1079 * internal management registers as if they were MII connected.
1080 * External Phy registers are referenced through the MII interface.
1081 */
1082
1083/* clock transitions >= 20ns (25MHz)
1084 * One readl should be good to PCI @ 100MHz
1085 */
1086#define mii_delay(ioaddr) readl(ioaddr + EECtrl)
1087
1088static int mii_getbit (struct net_device *dev)
1089{
1090 int data;
1091 void __iomem *ioaddr = ns_ioaddr(dev);
1092
1093 writel(MII_ShiftClk, ioaddr + EECtrl);
1094 data = readl(ioaddr + EECtrl);
1095 writel(0, ioaddr + EECtrl);
1096 mii_delay(ioaddr);
1097 return (data & MII_Data)? 1 : 0;
1098}
1099
1100static void mii_send_bits (struct net_device *dev, u32 data, int len)
1101{
1102 u32 i;
1103 void __iomem *ioaddr = ns_ioaddr(dev);
1104
1105 for (i = (1 << (len-1)); i; i >>= 1)
1106 {
1107 u32 mdio_val = MII_Write | ((data & i)? MII_Data : 0);
1108 writel(mdio_val, ioaddr + EECtrl);
1109 mii_delay(ioaddr);
1110 writel(mdio_val | MII_ShiftClk, ioaddr + EECtrl);
1111 mii_delay(ioaddr);
1112 }
1113 writel(0, ioaddr + EECtrl);
1114 mii_delay(ioaddr);
1115}
1116
1117static int miiport_read(struct net_device *dev, int phy_id, int reg)
1118{
1119 u32 cmd;
1120 int i;
1121 u32 retval = 0;
1122
1123 /* Ensure sync */
1124 mii_send_bits (dev, 0xffffffff, 32);
1125 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1126 /* ST,OP = 0110'b for read operation */
1127 cmd = (0x06 << 10) | (phy_id << 5) | reg;
1128 mii_send_bits (dev, cmd, 14);
1129 /* Turnaround */
1130 if (mii_getbit (dev))
1131 return 0;
1132 /* Read data */
1133 for (i = 0; i < 16; i++) {
1134 retval <<= 1;
1135 retval |= mii_getbit (dev);
1136 }
1137 /* End cycle */
1138 mii_getbit (dev);
1139 return retval;
1140}
1141
1142static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data)
1143{
1144 u32 cmd;
1145
1146 /* Ensure sync */
1147 mii_send_bits (dev, 0xffffffff, 32);
1148 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1149 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1150 cmd = (0x5002 << 16) | (phy_id << 23) | (reg << 18) | data;
1151 mii_send_bits (dev, cmd, 32);
1152 /* End cycle */
1153 mii_getbit (dev);
1154}
1155
1156static int mdio_read(struct net_device *dev, int reg)
1157{
1158 struct netdev_private *np = netdev_priv(dev);
1159 void __iomem *ioaddr = ns_ioaddr(dev);
1160
1161 /* The 83815 series has two ports:
1162 * - an internal transceiver
1163 * - an external mii bus
1164 */
1165 if (dev->if_port == PORT_TP)
1166 return readw(ioaddr+BasicControl+(reg<<2));
1167 else
1168 return miiport_read(dev, np->phy_addr_external, reg);
1169}
1170
1171static void mdio_write(struct net_device *dev, int reg, u16 data)
1172{
1173 struct netdev_private *np = netdev_priv(dev);
1174 void __iomem *ioaddr = ns_ioaddr(dev);
1175
1176 /* The 83815 series has an internal transceiver; handle separately */
1177 if (dev->if_port == PORT_TP)
1178 writew(data, ioaddr+BasicControl+(reg<<2));
1179 else
1180 miiport_write(dev, np->phy_addr_external, reg, data);
1181}
1182
1183static void init_phy_fixup(struct net_device *dev)
1184{
1185 struct netdev_private *np = netdev_priv(dev);
1186 void __iomem *ioaddr = ns_ioaddr(dev);
1187 int i;
1188 u32 cfg;
1189 u16 tmp;
1190
1191 /* restore stuff lost when power was out */
1192 tmp = mdio_read(dev, MII_BMCR);
1193 if (np->autoneg == AUTONEG_ENABLE) {
1194 /* renegotiate if something changed */
1195 if ((tmp & BMCR_ANENABLE) == 0
1196 || np->advertising != mdio_read(dev, MII_ADVERTISE))
1197 {
1198 /* turn on autonegotiation and force negotiation */
1199 tmp |= (BMCR_ANENABLE | BMCR_ANRESTART);
1200 mdio_write(dev, MII_ADVERTISE, np->advertising);
1201 }
1202 } else {
1203 /* turn off auto negotiation, set speed and duplexity */
1204 tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
1205 if (np->speed == SPEED_100)
1206 tmp |= BMCR_SPEED100;
1207 if (np->duplex == DUPLEX_FULL)
1208 tmp |= BMCR_FULLDPLX;
1209 /*
1210 * Note: there is no good way to inform the link partner
1211 * that our capabilities changed. The user has to unplug
1212 * and replug the network cable after some changes, e.g.
1213 * after switching from 10HD, autoneg off to 100 HD,
1214 * autoneg off.
1215 */
1216 }
1217 mdio_write(dev, MII_BMCR, tmp);
1218 readl(ioaddr + ChipConfig);
1219 udelay(1);
1220
1221 /* find out what phy this is */
1222 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1223 + mdio_read(dev, MII_PHYSID2);
1224
1225 /* handle external phys here */
1226 switch (np->mii) {
1227 case PHYID_AM79C874:
1228 /* phy specific configuration for fibre/tp operation */
1229 tmp = mdio_read(dev, MII_MCTRL);
1230 tmp &= ~(MII_FX_SEL | MII_EN_SCRM);
1231 if (dev->if_port == PORT_FIBRE)
1232 tmp |= MII_FX_SEL;
1233 else
1234 tmp |= MII_EN_SCRM;
1235 mdio_write(dev, MII_MCTRL, tmp);
1236 break;
1237 default:
1238 break;
1239 }
1240 cfg = readl(ioaddr + ChipConfig);
1241 if (cfg & CfgExtPhy)
1242 return;
1243
1244 /* On page 78 of the spec, they recommend some settings for "optimum
1245 performance" to be done in sequence. These settings optimize some
1246 of the 100Mbit autodetection circuitry. They say we only want to
1247 do this for rev C of the chip, but engineers at NSC (Bradley
1248 Kennedy) recommends always setting them. If you don't, you get
1249 errors on some autonegotiations that make the device unusable.
1250
1251 It seems that the DSP needs a few usec to reinitialize after
1252 the start of the phy. Just retry writing these values until they
1253 stick.
1254 */
1255 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1256
1257 int dspcfg;
1258 writew(1, ioaddr + PGSEL);
1259 writew(PMDCSR_VAL, ioaddr + PMDCSR);
1260 writew(TSTDAT_VAL, ioaddr + TSTDAT);
1261 np->dspcfg = (np->srr <= SRR_DP83815_C)?
1262 DSPCFG_VAL : (DSPCFG_COEF | readw(ioaddr + DSPCFG));
1263 writew(np->dspcfg, ioaddr + DSPCFG);
1264 writew(SDCFG_VAL, ioaddr + SDCFG);
1265 writew(0, ioaddr + PGSEL);
1266 readl(ioaddr + ChipConfig);
1267 udelay(10);
1268
1269 writew(1, ioaddr + PGSEL);
1270 dspcfg = readw(ioaddr + DSPCFG);
1271 writew(0, ioaddr + PGSEL);
1272 if (np->dspcfg == dspcfg)
1273 break;
1274 }
1275
1276 if (netif_msg_link(np)) {
1277 if (i==NATSEMI_HW_TIMEOUT) {
1278 printk(KERN_INFO
1279 "%s: DSPCFG mismatch after retrying for %d usec.\n",
1280 dev->name, i*10);
1281 } else {
1282 printk(KERN_INFO
1283 "%s: DSPCFG accepted after %d usec.\n",
1284 dev->name, i*10);
1285 }
1286 }
1287 /*
1288 * Enable PHY Specific event based interrupts. Link state change
1289 * and Auto-Negotiation Completion are among the affected.
1290 * Read the intr status to clear it (needed for wake events).
1291 */
1292 readw(ioaddr + MIntrStatus);
1293 writew(MICRIntEn, ioaddr + MIntrCtrl);
1294}
1295
1296static int switch_port_external(struct net_device *dev)
1297{
1298 struct netdev_private *np = netdev_priv(dev);
1299 void __iomem *ioaddr = ns_ioaddr(dev);
1300 u32 cfg;
1301
1302 cfg = readl(ioaddr + ChipConfig);
1303 if (cfg & CfgExtPhy)
1304 return 0;
1305
1306 if (netif_msg_link(np)) {
1307 printk(KERN_INFO "%s: switching to external transceiver.\n",
1308 dev->name);
1309 }
1310
1311 /* 1) switch back to external phy */
1312 writel(cfg | (CfgExtPhy | CfgPhyDis), ioaddr + ChipConfig);
1313 readl(ioaddr + ChipConfig);
1314 udelay(1);
1315
1316 /* 2) reset the external phy: */
1317 /* resetting the external PHY has been known to cause a hub supplying
1318 * power over Ethernet to kill the power. We don't want to kill
1319 * power to this computer, so we avoid resetting the phy.
1320 */
1321
1322 /* 3) reinit the phy fixup, it got lost during power down. */
1323 move_int_phy(dev, np->phy_addr_external);
1324 init_phy_fixup(dev);
1325
1326 return 1;
1327}
1328
1329static int switch_port_internal(struct net_device *dev)
1330{
1331 struct netdev_private *np = netdev_priv(dev);
1332 void __iomem *ioaddr = ns_ioaddr(dev);
1333 int i;
1334 u32 cfg;
1335 u16 bmcr;
1336
1337 cfg = readl(ioaddr + ChipConfig);
1338 if (!(cfg &CfgExtPhy))
1339 return 0;
1340
1341 if (netif_msg_link(np)) {
1342 printk(KERN_INFO "%s: switching to internal transceiver.\n",
1343 dev->name);
1344 }
1345 /* 1) switch back to internal phy: */
1346 cfg = cfg & ~(CfgExtPhy | CfgPhyDis);
1347 writel(cfg, ioaddr + ChipConfig);
1348 readl(ioaddr + ChipConfig);
1349 udelay(1);
1350
1351 /* 2) reset the internal phy: */
1352 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1353 writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2));
1354 readl(ioaddr + ChipConfig);
1355 udelay(10);
1356 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1357 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1358 if (!(bmcr & BMCR_RESET))
1359 break;
1360 udelay(10);
1361 }
1362 if (i==NATSEMI_HW_TIMEOUT && netif_msg_link(np)) {
1363 printk(KERN_INFO
1364 "%s: phy reset did not complete in %d usec.\n",
1365 dev->name, i*10);
1366 }
1367 /* 3) reinit the phy fixup, it got lost during power down. */
1368 init_phy_fixup(dev);
1369
1370 return 1;
1371}
1372
1373/* Scan for a PHY on the external mii bus.
1374 * There are two tricky points:
1375 * - Do not scan while the internal phy is enabled. The internal phy will
1376 * crash: e.g. reads from the DSPCFG register will return odd values and
1377 * the nasty random phy reset code will reset the nic every few seconds.
1378 * - The internal phy must be moved around, an external phy could
1379 * have the same address as the internal phy.
1380 */
1381static int find_mii(struct net_device *dev)
1382{
1383 struct netdev_private *np = netdev_priv(dev);
1384 int tmp;
1385 int i;
1386 int did_switch;
1387
1388 /* Switch to external phy */
1389 did_switch = switch_port_external(dev);
1390
1391 /* Scan the possible phy addresses:
1392 *
1393 * PHY address 0 means that the phy is in isolate mode. Not yet
1394 * supported due to lack of test hardware. User space should
1395 * handle it through ethtool.
1396 */
1397 for (i = 1; i <= 31; i++) {
1398 move_int_phy(dev, i);
1399 tmp = miiport_read(dev, i, MII_BMSR);
1400 if (tmp != 0xffff && tmp != 0x0000) {
1401 /* found something! */
1402 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1403 + mdio_read(dev, MII_PHYSID2);
1404 if (netif_msg_probe(np)) {
1405 printk(KERN_INFO "natsemi %s: found external phy %08x at address %d.\n",
1406 pci_name(np->pci_dev), np->mii, i);
1407 }
1408 break;
1409 }
1410 }
1411 /* And switch back to internal phy: */
1412 if (did_switch)
1413 switch_port_internal(dev);
1414 return i;
1415}
1416
1417/* CFG bits [13:16] [18:23] */
1418#define CFG_RESET_SAVE 0xfde000
1419/* WCSR bits [0:4] [9:10] */
1420#define WCSR_RESET_SAVE 0x61f
1421/* RFCR bits [20] [22] [27:31] */
1422#define RFCR_RESET_SAVE 0xf8500000;
1423
1424static void natsemi_reset(struct net_device *dev)
1425{
1426 int i;
1427 u32 cfg;
1428 u32 wcsr;
1429 u32 rfcr;
1430 u16 pmatch[3];
1431 u16 sopass[3];
1432 struct netdev_private *np = netdev_priv(dev);
1433 void __iomem *ioaddr = ns_ioaddr(dev);
1434
1435 /*
1436 * Resetting the chip causes some registers to be lost.
1437 * Natsemi suggests NOT reloading the EEPROM while live, so instead
1438 * we save the state that would have been loaded from EEPROM
1439 * on a normal power-up (see the spec EEPROM map). This assumes
1440 * whoever calls this will follow up with init_registers() eventually.
1441 */
1442
1443 /* CFG */
1444 cfg = readl(ioaddr + ChipConfig) & CFG_RESET_SAVE;
1445 /* WCSR */
1446 wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE;
1447 /* RFCR */
1448 rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE;
1449 /* PMATCH */
1450 for (i = 0; i < 3; i++) {
1451 writel(i*2, ioaddr + RxFilterAddr);
1452 pmatch[i] = readw(ioaddr + RxFilterData);
1453 }
1454 /* SOPAS */
1455 for (i = 0; i < 3; i++) {
1456 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1457 sopass[i] = readw(ioaddr + RxFilterData);
1458 }
1459
1460 /* now whack the chip */
1461 writel(ChipReset, ioaddr + ChipCmd);
1462 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1463 if (!(readl(ioaddr + ChipCmd) & ChipReset))
1464 break;
1465 udelay(5);
1466 }
1467 if (i==NATSEMI_HW_TIMEOUT) {
1468 printk(KERN_WARNING "%s: reset did not complete in %d usec.\n",
1469 dev->name, i*5);
1470 } else if (netif_msg_hw(np)) {
1471 printk(KERN_DEBUG "%s: reset completed in %d usec.\n",
1472 dev->name, i*5);
1473 }
1474
1475 /* restore CFG */
1476 cfg |= readl(ioaddr + ChipConfig) & ~CFG_RESET_SAVE;
1477 /* turn on external phy if it was selected */
1478 if (dev->if_port == PORT_TP)
1479 cfg &= ~(CfgExtPhy | CfgPhyDis);
1480 else
1481 cfg |= (CfgExtPhy | CfgPhyDis);
1482 writel(cfg, ioaddr + ChipConfig);
1483 /* restore WCSR */
1484 wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE;
1485 writel(wcsr, ioaddr + WOLCmd);
1486 /* read RFCR */
1487 rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE;
1488 /* restore PMATCH */
1489 for (i = 0; i < 3; i++) {
1490 writel(i*2, ioaddr + RxFilterAddr);
1491 writew(pmatch[i], ioaddr + RxFilterData);
1492 }
1493 for (i = 0; i < 3; i++) {
1494 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1495 writew(sopass[i], ioaddr + RxFilterData);
1496 }
1497 /* restore RFCR */
1498 writel(rfcr, ioaddr + RxFilterAddr);
1499}
1500
e72fd96e
MB		 1501static void reset_rx(struct net_device *dev)
1502{
1503 int i;
1504 struct netdev_private *np = netdev_priv(dev);
1505 void __iomem *ioaddr = ns_ioaddr(dev);
1506
1507 np->intr_status &= ~RxResetDone;
1508
1509 writel(RxReset, ioaddr + ChipCmd);
1510
1511 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1512 np->intr_status |= readl(ioaddr + IntrStatus);
1513 if (np->intr_status & RxResetDone)
1514 break;
1515 udelay(15);
1516 }
1517 if (i==NATSEMI_HW_TIMEOUT) {
1518 printk(KERN_WARNING "%s: RX reset did not complete in %d usec.\n",
1519 dev->name, i*15);
1520 } else if (netif_msg_hw(np)) {
1521 printk(KERN_WARNING "%s: RX reset took %d usec.\n",
1522 dev->name, i*15);
1523 }
1524}
1525
1da177e4
LT		 1526static void natsemi_reload_eeprom(struct net_device *dev)
1527{
1528 struct netdev_private *np = netdev_priv(dev);
1529 void __iomem *ioaddr = ns_ioaddr(dev);
1530 int i;
1531
1532 writel(EepromReload, ioaddr + PCIBusCfg);
1533 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1534 udelay(50);
1535 if (!(readl(ioaddr + PCIBusCfg) & EepromReload))
1536 break;
1537 }
1538 if (i==NATSEMI_HW_TIMEOUT) {
1539 printk(KERN_WARNING "natsemi %s: EEPROM did not reload in %d usec.\n",
1540 pci_name(np->pci_dev), i*50);
1541 } else if (netif_msg_hw(np)) {
1542 printk(KERN_DEBUG "natsemi %s: EEPROM reloaded in %d usec.\n",
1543 pci_name(np->pci_dev), i*50);
1544 }
1545}
1546
1547static void natsemi_stop_rxtx(struct net_device *dev)
1548{
1549 void __iomem * ioaddr = ns_ioaddr(dev);
1550 struct netdev_private *np = netdev_priv(dev);
1551 int i;
1552
1553 writel(RxOff | TxOff, ioaddr + ChipCmd);
1554 for(i=0;i< NATSEMI_HW_TIMEOUT;i++) {
1555 if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0)
1556 break;
1557 udelay(5);
1558 }
1559 if (i==NATSEMI_HW_TIMEOUT) {
1560 printk(KERN_WARNING "%s: Tx/Rx process did not stop in %d usec.\n",
1561 dev->name, i*5);
1562 } else if (netif_msg_hw(np)) {
1563 printk(KERN_DEBUG "%s: Tx/Rx process stopped in %d usec.\n",
1564 dev->name, i*5);
1565 }
1566}
1567
1568static int netdev_open(struct net_device *dev)
1569{
1570 struct netdev_private *np = netdev_priv(dev);
1571 void __iomem * ioaddr = ns_ioaddr(dev);
1572 int i;
1573
1574 /* Reset the chip, just in case. */
1575 natsemi_reset(dev);
1576
1fb9df5d 1577 i = request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 1578 if (i) return i;
1579
1580 if (netif_msg_ifup(np))
1581 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
1582 dev->name, dev->irq);
1583 i = alloc_ring(dev);
1584 if (i < 0) {
1585 free_irq(dev->irq, dev);
1586 return i;
1587 }
1588 init_ring(dev);
1589 spin_lock_irq(&np->lock);
1590 init_registers(dev);
1591 /* now set the MAC address according to dev->dev_addr */
1592 for (i = 0; i < 3; i++) {
1593 u16 mac = (dev->dev_addr[2*i+1]<<8) + dev->dev_addr[2*i];
1594
1595 writel(i*2, ioaddr + RxFilterAddr);
1596 writew(mac, ioaddr + RxFilterData);
1597 }
1598 writel(np->cur_rx_mode, ioaddr + RxFilterAddr);
1599 spin_unlock_irq(&np->lock);
1600
1601 netif_start_queue(dev);
1602
1603 if (netif_msg_ifup(np))
1604 printk(KERN_DEBUG "%s: Done netdev_open(), status: %#08x.\n",
1605 dev->name, (int)readl(ioaddr + ChipCmd));
1606
1607 /* Set the timer to check for link beat. */
1608 init_timer(&np->timer);
1609 np->timer.expires = jiffies + NATSEMI_TIMER_FREQ;
1610 np->timer.data = (unsigned long)dev;
1611 np->timer.function = &netdev_timer; /* timer handler */
1612 add_timer(&np->timer);
1613
1614 return 0;
1615}
1616
1617static void do_cable_magic(struct net_device *dev)
1618{
1619 struct netdev_private *np = netdev_priv(dev);
1620 void __iomem *ioaddr = ns_ioaddr(dev);
1621
1622 if (dev->if_port != PORT_TP)
1623 return;
1624
1625 if (np->srr >= SRR_DP83816_A5)
1626 return;
1627
1628 /*
1629 * 100 MBit links with short cables can trip an issue with the chip.
1630 * The problem manifests as lots of CRC errors and/or flickering
1631 * activity LED while idle. This process is based on instructions
1632 * from engineers at National.
1633 */
1634 if (readl(ioaddr + ChipConfig) & CfgSpeed100) {
1635 u16 data;
1636
1637 writew(1, ioaddr + PGSEL);
1638 /*
1639 * coefficient visibility should already be enabled via
1640 * DSPCFG | 0x1000
1641 */
1642 data = readw(ioaddr + TSTDAT) & 0xff;
1643 /*
1644 * the value must be negative, and within certain values
1645 * (these values all come from National)
1646 */
1647 if (!(data & 0x80) || ((data >= 0xd8) && (data <= 0xff))) {
1648 struct netdev_private *np = netdev_priv(dev);
1649
1650 /* the bug has been triggered - fix the coefficient */
1651 writew(TSTDAT_FIXED, ioaddr + TSTDAT);
1652 /* lock the value */
1653 data = readw(ioaddr + DSPCFG);
1654 np->dspcfg = data | DSPCFG_LOCK;
1655 writew(np->dspcfg, ioaddr + DSPCFG);
1656 }
1657 writew(0, ioaddr + PGSEL);
1658 }
1659}
1660
1661static void undo_cable_magic(struct net_device *dev)
1662{
1663 u16 data;
1664 struct netdev_private *np = netdev_priv(dev);
1665 void __iomem * ioaddr = ns_ioaddr(dev);
1666
1667 if (dev->if_port != PORT_TP)
1668 return;
1669
1670 if (np->srr >= SRR_DP83816_A5)
1671 return;
1672
1673 writew(1, ioaddr + PGSEL);
1674 /* make sure the lock bit is clear */
1675 data = readw(ioaddr + DSPCFG);
1676 np->dspcfg = data & ~DSPCFG_LOCK;
1677 writew(np->dspcfg, ioaddr + DSPCFG);
1678 writew(0, ioaddr + PGSEL);
1679}
1680
1681static void check_link(struct net_device *dev)
1682{
1683 struct netdev_private *np = netdev_priv(dev);
1684 void __iomem * ioaddr = ns_ioaddr(dev);
1685 int duplex;
1686 u16 bmsr;
1687
1688 /* The link status field is latched: it remains low after a temporary
1689 * link failure until it's read. We need the current link status,
1690 * thus read twice.
1691 */
1692 mdio_read(dev, MII_BMSR);
1693 bmsr = mdio_read(dev, MII_BMSR);
1694
1695 if (!(bmsr & BMSR_LSTATUS)) {
1696 if (netif_carrier_ok(dev)) {
1697 if (netif_msg_link(np))
1698 printk(KERN_NOTICE "%s: link down.\n",
1699 dev->name);
1700 netif_carrier_off(dev);
1701 undo_cable_magic(dev);
1702 }
1703 return;
1704 }
1705 if (!netif_carrier_ok(dev)) {
1706 if (netif_msg_link(np))
1707 printk(KERN_NOTICE "%s: link up.\n", dev->name);
1708 netif_carrier_on(dev);
1709 do_cable_magic(dev);
1710 }
1711
1712 duplex = np->full_duplex;
1713 if (!duplex) {
1714 if (bmsr & BMSR_ANEGCOMPLETE) {
1715 int tmp = mii_nway_result(
1716 np->advertising & mdio_read(dev, MII_LPA));
1717 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
1718 duplex = 1;
1719 } else if (mdio_read(dev, MII_BMCR) & BMCR_FULLDPLX)
1720 duplex = 1;
1721 }
1722
1723 /* if duplex is set then bit 28 must be set, too */
1724 if (duplex ^ !!(np->rx_config & RxAcceptTx)) {
1725 if (netif_msg_link(np))
1726 printk(KERN_INFO
1727 "%s: Setting %s-duplex based on negotiated "
1728 "link capability.\n", dev->name,
1729 duplex ? "full" : "half");
1730 if (duplex) {
1731 np->rx_config |= RxAcceptTx;
1732 np->tx_config |= TxCarrierIgn | TxHeartIgn;
1733 } else {
1734 np->rx_config &= ~RxAcceptTx;
1735 np->tx_config &= ~(TxCarrierIgn | TxHeartIgn);
1736 }
1737 writel(np->tx_config, ioaddr + TxConfig);
1738 writel(np->rx_config, ioaddr + RxConfig);
1739 }
1740}
1741
1742static void init_registers(struct net_device *dev)
1743{
1744 struct netdev_private *np = netdev_priv(dev);
1745 void __iomem * ioaddr = ns_ioaddr(dev);
1746
1747 init_phy_fixup(dev);
1748
1749 /* clear any interrupts that are pending, such as wake events */
1750 readl(ioaddr + IntrStatus);
1751
1752 writel(np->ring_dma, ioaddr + RxRingPtr);
1753 writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc),
1754 ioaddr + TxRingPtr);
1755
1756 /* Initialize other registers.
1757 * Configure the PCI bus bursts and FIFO thresholds.
1758 * Configure for standard, in-spec Ethernet.
1759 * Start with half-duplex. check_link will update
1760 * to the correct settings.
1761 */
1762
1763 /* DRTH: 2: start tx if 64 bytes are in the fifo
1764 * FLTH: 0x10: refill with next packet if 512 bytes are free
1765 * MXDMA: 0: up to 256 byte bursts.
1766 * MXDMA must be <= FLTH
1767 * ECRETRY=1
1768 * ATP=1
1769 */
1770 np->tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 |
1771 TX_FLTH_VAL | TX_DRTH_VAL_START;
1772 writel(np->tx_config, ioaddr + TxConfig);
1773
1774 /* DRTH 0x10: start copying to memory if 128 bytes are in the fifo
1775 * MXDMA 0: up to 256 byte bursts
1776 */
1777 np->rx_config = RxMxdma_256 | RX_DRTH_VAL;
1778 /* if receive ring now has bigger buffers than normal, enable jumbo */
1779 if (np->rx_buf_sz > NATSEMI_LONGPKT)
1780 np->rx_config |= RxAcceptLong;
1781
1782 writel(np->rx_config, ioaddr + RxConfig);
1783
1784 /* Disable PME:
1785 * The PME bit is initialized from the EEPROM contents.
1786 * PCI cards probably have PME disabled, but motherboard
1787 * implementations may have PME set to enable WakeOnLan.
1788 * With PME set the chip will scan incoming packets but
1789 * nothing will be written to memory. */
1790 np->SavedClkRun = readl(ioaddr + ClkRun);
1791 writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun);
1792 if (np->SavedClkRun & PMEStatus && netif_msg_wol(np)) {
1793 printk(KERN_NOTICE "%s: Wake-up event %#08x\n",
1794 dev->name, readl(ioaddr + WOLCmd));
1795 }
1796
1797 check_link(dev);
1798 __set_rx_mode(dev);
1799
1800 /* Enable interrupts by setting the interrupt mask. */
1801 writel(DEFAULT_INTR, ioaddr + IntrMask);
1802 writel(1, ioaddr + IntrEnable);
1803
1804 writel(RxOn | TxOn, ioaddr + ChipCmd);
1805 writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */
1806}
1807
1808/*
1809 * netdev_timer:
1810 * Purpose:
1811 * 1) check for link changes. Usually they are handled by the MII interrupt
1812 * but it doesn't hurt to check twice.
1813 * 2) check for sudden death of the NIC:
1814 * It seems that a reference set for this chip went out with incorrect info,
1815 * and there exist boards that aren't quite right. An unexpected voltage
1816 * drop can cause the PHY to get itself in a weird state (basically reset).
1817 * NOTE: this only seems to affect revC chips.
1818 * 3) check of death of the RX path due to OOM
1819 */
1820static void netdev_timer(unsigned long data)
1821{
1822 struct net_device *dev = (struct net_device *)data;
1823 struct netdev_private *np = netdev_priv(dev);
1824 void __iomem * ioaddr = ns_ioaddr(dev);
1825 int next_tick = 5*HZ;
1826
1827 if (netif_msg_timer(np)) {
1828 /* DO NOT read the IntrStatus register,
1829 * a read clears any pending interrupts.
1830 */
1831 printk(KERN_DEBUG "%s: Media selection timer tick.\n",
1832 dev->name);
1833 }
1834
1835 if (dev->if_port == PORT_TP) {
1836 u16 dspcfg;
1837
1838 spin_lock_irq(&np->lock);
1839 /* check for a nasty random phy-reset - use dspcfg as a flag */
1840 writew(1, ioaddr+PGSEL);
1841 dspcfg = readw(ioaddr+DSPCFG);
1842 writew(0, ioaddr+PGSEL);
1843 if (dspcfg != np->dspcfg) {
1844 if (!netif_queue_stopped(dev)) {
1845 spin_unlock_irq(&np->lock);
1846 if (netif_msg_hw(np))
1847 printk(KERN_NOTICE "%s: possible phy reset: "
1848 "re-initializing\n", dev->name);
1849 disable_irq(dev->irq);
1850 spin_lock_irq(&np->lock);
1851 natsemi_stop_rxtx(dev);
1852 dump_ring(dev);
1853 reinit_ring(dev);
1854 init_registers(dev);
1855 spin_unlock_irq(&np->lock);
1856 enable_irq(dev->irq);
1857 } else {
1858 /* hurry back */
1859 next_tick = HZ;
1860 spin_unlock_irq(&np->lock);
1861 }
1862 } else {
1863 /* init_registers() calls check_link() for the above case */
1864 check_link(dev);
1865 spin_unlock_irq(&np->lock);
1866 }
1867 } else {
1868 spin_lock_irq(&np->lock);
1869 check_link(dev);
1870 spin_unlock_irq(&np->lock);
1871 }
1872 if (np->oom) {
1873 disable_irq(dev->irq);
1874 np->oom = 0;
1875 refill_rx(dev);
1876 enable_irq(dev->irq);
1877 if (!np->oom) {
1878 writel(RxOn, ioaddr + ChipCmd);
1879 } else {
1880 next_tick = 1;
1881 }
1882 }
1883 mod_timer(&np->timer, jiffies + next_tick);
1884}
1885
1886static void dump_ring(struct net_device *dev)
1887{
1888 struct netdev_private *np = netdev_priv(dev);
1889
1890 if (netif_msg_pktdata(np)) {
1891 int i;
1892 printk(KERN_DEBUG " Tx ring at %p:\n", np->tx_ring);
1893 for (i = 0; i < TX_RING_SIZE; i++) {
1894 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1895 i, np->tx_ring[i].next_desc,
1896 np->tx_ring[i].cmd_status,
1897 np->tx_ring[i].addr);
1898 }
1899 printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring);
1900 for (i = 0; i < RX_RING_SIZE; i++) {
1901 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1902 i, np->rx_ring[i].next_desc,
1903 np->rx_ring[i].cmd_status,
1904 np->rx_ring[i].addr);
1905 }
1906 }
1907}
1908
1909static void tx_timeout(struct net_device *dev)
1910{
1911 struct netdev_private *np = netdev_priv(dev);
1912 void __iomem * ioaddr = ns_ioaddr(dev);
1913
1914 disable_irq(dev->irq);
1915 spin_lock_irq(&np->lock);
1916 if (!np->hands_off) {
1917 if (netif_msg_tx_err(np))
1918 printk(KERN_WARNING
1919 "%s: Transmit timed out, status %#08x,"
1920 " resetting...\n",
1921 dev->name, readl(ioaddr + IntrStatus));
1922 dump_ring(dev);
1923
1924 natsemi_reset(dev);
1925 reinit_ring(dev);
1926 init_registers(dev);
1927 } else {
1928 printk(KERN_WARNING
1929 "%s: tx_timeout while in hands_off state?\n",
1930 dev->name);
1931 }
1932 spin_unlock_irq(&np->lock);
1933 enable_irq(dev->irq);
1934
1935 dev->trans_start = jiffies;
1936 np->stats.tx_errors++;
1937 netif_wake_queue(dev);
1938}
1939
1940static int alloc_ring(struct net_device *dev)
1941{
1942 struct netdev_private *np = netdev_priv(dev);
1943 np->rx_ring = pci_alloc_consistent(np->pci_dev,
1944 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
1945 &np->ring_dma);
1946 if (!np->rx_ring)
1947 return -ENOMEM;
1948 np->tx_ring = &np->rx_ring[RX_RING_SIZE];
1949 return 0;
1950}
1951
1952static void refill_rx(struct net_device *dev)
1953{
1954 struct netdev_private *np = netdev_priv(dev);
1955
1956 /* Refill the Rx ring buffers. */
1957 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1958 struct sk_buff *skb;
1959 int entry = np->dirty_rx % RX_RING_SIZE;
1960 if (np->rx_skbuff[entry] == NULL) {
1961 unsigned int buflen = np->rx_buf_sz+NATSEMI_PADDING;
1962 skb = dev_alloc_skb(buflen);
1963 np->rx_skbuff[entry] = skb;
1964 if (skb == NULL)
1965 break; /* Better luck next round. */
1966 skb->dev = dev; /* Mark as being used by this device. */
1967 np->rx_dma[entry] = pci_map_single(np->pci_dev,
689be439 1968 skb->data, buflen, PCI_DMA_FROMDEVICE);
1da177e4
LT		 1969 np->rx_ring[entry].addr = cpu_to_le32(np->rx_dma[entry]);
1970 }
1971 np->rx_ring[entry].cmd_status = cpu_to_le32(np->rx_buf_sz);
1972 }
1973 if (np->cur_rx - np->dirty_rx == RX_RING_SIZE) {
1974 if (netif_msg_rx_err(np))
1975 printk(KERN_WARNING "%s: going OOM.\n", dev->name);
1976 np->oom = 1;
1977 }
1978}
1979
1980static void set_bufsize(struct net_device *dev)
1981{
1982 struct netdev_private *np = netdev_priv(dev);
1983 if (dev->mtu <= ETH_DATA_LEN)
1984 np->rx_buf_sz = ETH_DATA_LEN + NATSEMI_HEADERS;
1985 else
1986 np->rx_buf_sz = dev->mtu + NATSEMI_HEADERS;
1987}
1988
1989/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1990static void init_ring(struct net_device *dev)
1991{
1992 struct netdev_private *np = netdev_priv(dev);
1993 int i;
1994
1995 /* 1) TX ring */
1996 np->dirty_tx = np->cur_tx = 0;
1997 for (i = 0; i < TX_RING_SIZE; i++) {
1998 np->tx_skbuff[i] = NULL;
1999 np->tx_ring[i].next_desc = cpu_to_le32(np->ring_dma
2000 +sizeof(struct netdev_desc)
2001 *((i+1)%TX_RING_SIZE+RX_RING_SIZE));
2002 np->tx_ring[i].cmd_status = 0;
2003 }
2004
2005 /* 2) RX ring */
2006 np->dirty_rx = 0;
2007 np->cur_rx = RX_RING_SIZE;
2008 np->oom = 0;
2009 set_bufsize(dev);
2010
2011 np->rx_head_desc = &np->rx_ring[0];
2012
2013 /* Please be carefull before changing this loop - at least gcc-2.95.1
2014 * miscompiles it otherwise.
2015 */
2016 /* Initialize all Rx descriptors. */
2017 for (i = 0; i < RX_RING_SIZE; i++) {
2018 np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma
2019 +sizeof(struct netdev_desc)
2020 *((i+1)%RX_RING_SIZE));
2021 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2022 np->rx_skbuff[i] = NULL;
2023 }
2024 refill_rx(dev);
2025 dump_ring(dev);
2026}
2027
2028static void drain_tx(struct net_device *dev)
2029{
2030 struct netdev_private *np = netdev_priv(dev);
2031 int i;
2032
2033 for (i = 0; i < TX_RING_SIZE; i++) {
2034 if (np->tx_skbuff[i]) {
2035 pci_unmap_single(np->pci_dev,
2036 np->tx_dma[i], np->tx_skbuff[i]->len,
2037 PCI_DMA_TODEVICE);
2038 dev_kfree_skb(np->tx_skbuff[i]);
2039 np->stats.tx_dropped++;
2040 }
2041 np->tx_skbuff[i] = NULL;
2042 }
2043}
2044
2045static void drain_rx(struct net_device *dev)
2046{
2047 struct netdev_private *np = netdev_priv(dev);
2048 unsigned int buflen = np->rx_buf_sz;
2049 int i;
2050
2051 /* Free all the skbuffs in the Rx queue. */
2052 for (i = 0; i < RX_RING_SIZE; i++) {
2053 np->rx_ring[i].cmd_status = 0;
2054 np->rx_ring[i].addr = 0xBADF00D0; /* An invalid address. */
2055 if (np->rx_skbuff[i]) {
2056 pci_unmap_single(np->pci_dev,
2057 np->rx_dma[i], buflen,
2058 PCI_DMA_FROMDEVICE);
2059 dev_kfree_skb(np->rx_skbuff[i]);
2060 }
2061 np->rx_skbuff[i] = NULL;
2062 }
2063}
2064
2065static void drain_ring(struct net_device *dev)
2066{
2067 drain_rx(dev);
2068 drain_tx(dev);
2069}
2070
2071static void free_ring(struct net_device *dev)
2072{
2073 struct netdev_private *np = netdev_priv(dev);
2074 pci_free_consistent(np->pci_dev,
2075 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
2076 np->rx_ring, np->ring_dma);
2077}
2078
2079static void reinit_rx(struct net_device *dev)
2080{
2081 struct netdev_private *np = netdev_priv(dev);
2082 int i;
2083
2084 /* RX Ring */
2085 np->dirty_rx = 0;
2086 np->cur_rx = RX_RING_SIZE;
2087 np->rx_head_desc = &np->rx_ring[0];
2088 /* Initialize all Rx descriptors. */
2089 for (i = 0; i < RX_RING_SIZE; i++)
2090 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2091
2092 refill_rx(dev);
2093}
2094
2095static void reinit_ring(struct net_device *dev)
2096{
2097 struct netdev_private *np = netdev_priv(dev);
2098 int i;
2099
2100 /* drain TX ring */
2101 drain_tx(dev);
2102 np->dirty_tx = np->cur_tx = 0;
2103 for (i=0;i<TX_RING_SIZE;i++)
2104 np->tx_ring[i].cmd_status = 0;
2105
2106 reinit_rx(dev);
2107}
2108
2109static int start_tx(struct sk_buff *skb, struct net_device *dev)
2110{
2111 struct netdev_private *np = netdev_priv(dev);
2112 void __iomem * ioaddr = ns_ioaddr(dev);
2113 unsigned entry;
2114
2115 /* Note: Ordering is important here, set the field with the
2116 "ownership" bit last, and only then increment cur_tx. */
2117
2118 /* Calculate the next Tx descriptor entry. */
2119 entry = np->cur_tx % TX_RING_SIZE;
2120
2121 np->tx_skbuff[entry] = skb;
2122 np->tx_dma[entry] = pci_map_single(np->pci_dev,
2123 skb->data,skb->len, PCI_DMA_TODEVICE);
2124
2125 np->tx_ring[entry].addr = cpu_to_le32(np->tx_dma[entry]);
2126
2127 spin_lock_irq(&np->lock);
2128
2129 if (!np->hands_off) {
2130 np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len);
2131 /* StrongARM: Explicitly cache flush np->tx_ring and
2132 * skb->data,skb->len. */
2133 wmb();
2134 np->cur_tx++;
2135 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) {
2136 netdev_tx_done(dev);
2137 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1)
2138 netif_stop_queue(dev);
2139 }
2140 /* Wake the potentially-idle transmit channel. */
2141 writel(TxOn, ioaddr + ChipCmd);
2142 } else {
2143 dev_kfree_skb_irq(skb);
2144 np->stats.tx_dropped++;
2145 }
2146 spin_unlock_irq(&np->lock);
2147
2148 dev->trans_start = jiffies;
2149
2150 if (netif_msg_tx_queued(np)) {
2151 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
2152 dev->name, np->cur_tx, entry);
2153 }
2154 return 0;
2155}
2156
2157static void netdev_tx_done(struct net_device *dev)
2158{
2159 struct netdev_private *np = netdev_priv(dev);
2160
2161 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
2162 int entry = np->dirty_tx % TX_RING_SIZE;
2163 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescOwn))
2164 break;
2165 if (netif_msg_tx_done(np))
2166 printk(KERN_DEBUG
2167 "%s: tx frame #%d finished, status %#08x.\n",
2168 dev->name, np->dirty_tx,
2169 le32_to_cpu(np->tx_ring[entry].cmd_status));
2170 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescPktOK)) {
2171 np->stats.tx_packets++;
2172 np->stats.tx_bytes += np->tx_skbuff[entry]->len;
2173 } else { /* Various Tx errors */
2174 int tx_status =
2175 le32_to_cpu(np->tx_ring[entry].cmd_status);
2176 if (tx_status & (DescTxAbort|DescTxExcColl))
2177 np->stats.tx_aborted_errors++;
2178 if (tx_status & DescTxFIFO)
2179 np->stats.tx_fifo_errors++;
2180 if (tx_status & DescTxCarrier)
2181 np->stats.tx_carrier_errors++;
2182 if (tx_status & DescTxOOWCol)
2183 np->stats.tx_window_errors++;
2184 np->stats.tx_errors++;
2185 }
2186 pci_unmap_single(np->pci_dev,np->tx_dma[entry],
2187 np->tx_skbuff[entry]->len,
2188 PCI_DMA_TODEVICE);
2189 /* Free the original skb. */
2190 dev_kfree_skb_irq(np->tx_skbuff[entry]);
2191 np->tx_skbuff[entry] = NULL;
2192 }
2193 if (netif_queue_stopped(dev)
2194 && np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
2195 /* The ring is no longer full, wake queue. */
2196 netif_wake_queue(dev);
2197 }
2198}
2199
b27a16b7
MB		 2200/* The interrupt handler doesn't actually handle interrupts itself, it
2201 * schedules a NAPI poll if there is anything to do. */
1da177e4
LT		 2202static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *rgs)
2203{
2204 struct net_device *dev = dev_instance;
2205 struct netdev_private *np = netdev_priv(dev);
2206 void __iomem * ioaddr = ns_ioaddr(dev);
1da177e4
LT		 2207
2208 if (np->hands_off)
2209 return IRQ_NONE;
b27a16b7
MB		 2210
2211 /* Reading automatically acknowledges. */
2212 np->intr_status = readl(ioaddr + IntrStatus);
1da177e4 2213
b27a16b7
MB		 2214 if (netif_msg_intr(np))
2215 printk(KERN_DEBUG
2216 "%s: Interrupt, status %#08x, mask %#08x.\n",
2217 dev->name, np->intr_status,
2218 readl(ioaddr + IntrMask));
1da177e4 2219
b27a16b7
MB		 2220 if (!np->intr_status)
2221 return IRQ_NONE;
1da177e4 2222
b27a16b7
MB		 2223 prefetch(&np->rx_skbuff[np->cur_rx % RX_RING_SIZE]);
2224
2225 if (netif_rx_schedule_prep(dev)) {
2226 /* Disable interrupts and register for poll */
2227 natsemi_irq_disable(dev);
2228 __netif_rx_schedule(dev);
2229 }
2230 return IRQ_HANDLED;
2231}
2232
2233/* This is the NAPI poll routine. As well as the standard RX handling
2234 * it also handles all other interrupts that the chip might raise.
2235 */
2236static int natsemi_poll(struct net_device *dev, int *budget)
2237{
2238 struct netdev_private *np = netdev_priv(dev);
2239 void __iomem * ioaddr = ns_ioaddr(dev);
1da177e4 2240
b27a16b7
MB		 2241 int work_to_do = min(*budget, dev->quota);
2242 int work_done = 0;
2243
2244 do {
2245 if (np->intr_status &
2246 (IntrTxDone | IntrTxIntr | IntrTxIdle | IntrTxErr)) {
1da177e4
LT		 2247 spin_lock(&np->lock);
2248 netdev_tx_done(dev);
2249 spin_unlock(&np->lock);
2250 }
2251
2252 /* Abnormal error summary/uncommon events handlers. */
b27a16b7
MB		 2253 if (np->intr_status & IntrAbnormalSummary)
2254 netdev_error(dev, np->intr_status);
2255
2256 if (np->intr_status &
2257 (IntrRxDone | IntrRxIntr | RxStatusFIFOOver |
2258 IntrRxErr | IntrRxOverrun)) {
2259 netdev_rx(dev, &work_done, work_to_do);
1da177e4 2260 }
b27a16b7
MB		 2261
2262 *budget -= work_done;
2263 dev->quota -= work_done;
1da177e4 2264
b27a16b7
MB		 2265 if (work_done >= work_to_do)
2266 return 1;
2267
2268 np->intr_status = readl(ioaddr + IntrStatus);
2269 } while (np->intr_status);
1da177e4 2270
b27a16b7
MB		 2271 netif_rx_complete(dev);
2272
2273 /* Reenable interrupts providing nothing is trying to shut
2274 * the chip down. */
2275 spin_lock(&np->lock);
2276 if (!np->hands_off && netif_running(dev))
2277 natsemi_irq_enable(dev);
2278 spin_unlock(&np->lock);
2279
2280 return 0;
1da177e4
LT		 2281}
2282
2283/* This routine is logically part of the interrupt handler, but separated
2284 for clarity and better register allocation. */
b27a16b7 2285static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do)
1da177e4
LT		 2286{
2287 struct netdev_private *np = netdev_priv(dev);
2288 int entry = np->cur_rx % RX_RING_SIZE;
2289 int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
2290 s32 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2291 unsigned int buflen = np->rx_buf_sz;
2292 void __iomem * ioaddr = ns_ioaddr(dev);
2293
2294 /* If the driver owns the next entry it's a new packet. Send it up. */
2295 while (desc_status < 0) { /* e.g. & DescOwn */
2296 int pkt_len;
2297 if (netif_msg_rx_status(np))
2298 printk(KERN_DEBUG
2299 " netdev_rx() entry %d status was %#08x.\n",
2300 entry, desc_status);
2301 if (--boguscnt < 0)
2302 break;
b27a16b7
MB		 2303
2304 if (*work_done >= work_to_do)
2305 break;
2306
2307 (*work_done)++;
2308
1da177e4
LT		 2309 pkt_len = (desc_status & DescSizeMask) - 4;
2310 if ((desc_status&(DescMore|DescPktOK|DescRxLong)) != DescPktOK){
2311 if (desc_status & DescMore) {
2312 if (netif_msg_rx_err(np))
2313 printk(KERN_WARNING
2314 "%s: Oversized(?) Ethernet "
2315 "frame spanned multiple "
2316 "buffers, entry %#08x "
2317 "status %#08x.\n", dev->name,
2318 np->cur_rx, desc_status);
2319 np->stats.rx_length_errors++;
e72fd96e
MB		 2320
2321 /* The RX state machine has probably
2322 * locked up beneath us. Follow the
2323 * reset procedure documented in
2324 * AN-1287. */
2325
2326 spin_lock_irq(&np->lock);
2327 reset_rx(dev);
2328 reinit_rx(dev);
2329 writel(np->ring_dma, ioaddr + RxRingPtr);
2330 check_link(dev);
2331 spin_unlock_irq(&np->lock);
2332
2333 /* We'll enable RX on exit from this
2334 * function. */
2335 break;
2336
1da177e4
LT		 2337 } else {
2338 /* There was an error. */
2339 np->stats.rx_errors++;
2340 if (desc_status & (DescRxAbort|DescRxOver))
2341 np->stats.rx_over_errors++;
2342 if (desc_status & (DescRxLong|DescRxRunt))
2343 np->stats.rx_length_errors++;
2344 if (desc_status & (DescRxInvalid|DescRxAlign))
2345 np->stats.rx_frame_errors++;
2346 if (desc_status & DescRxCRC)
2347 np->stats.rx_crc_errors++;
2348 }
2349 } else if (pkt_len > np->rx_buf_sz) {
2350 /* if this is the tail of a double buffer
2351 * packet, we've already counted the error
2352 * on the first part. Ignore the second half.
2353 */
2354 } else {
2355 struct sk_buff *skb;
2356 /* Omit CRC size. */
2357 /* Check if the packet is long enough to accept
2358 * without copying to a minimally-sized skbuff. */
2359 if (pkt_len < rx_copybreak
2360 && (skb = dev_alloc_skb(pkt_len + RX_OFFSET)) != NULL) {
2361 skb->dev = dev;
2362 /* 16 byte align the IP header */
2363 skb_reserve(skb, RX_OFFSET);
2364 pci_dma_sync_single_for_cpu(np->pci_dev,
2365 np->rx_dma[entry],
2366 buflen,
2367 PCI_DMA_FROMDEVICE);
2368 eth_copy_and_sum(skb,
689be439 2369 np->rx_skbuff[entry]->data, pkt_len, 0);
1da177e4
LT		 2370 skb_put(skb, pkt_len);
2371 pci_dma_sync_single_for_device(np->pci_dev,
2372 np->rx_dma[entry],
2373 buflen,
2374 PCI_DMA_FROMDEVICE);
2375 } else {
2376 pci_unmap_single(np->pci_dev, np->rx_dma[entry],
2377 buflen, PCI_DMA_FROMDEVICE);
2378 skb_put(skb = np->rx_skbuff[entry], pkt_len);
2379 np->rx_skbuff[entry] = NULL;
2380 }
2381 skb->protocol = eth_type_trans(skb, dev);
b27a16b7 2382 netif_receive_skb(skb);
1da177e4
LT		 2383 dev->last_rx = jiffies;
2384 np->stats.rx_packets++;
2385 np->stats.rx_bytes += pkt_len;
2386 }
2387 entry = (++np->cur_rx) % RX_RING_SIZE;
2388 np->rx_head_desc = &np->rx_ring[entry];
2389 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2390 }
2391 refill_rx(dev);
2392
2393 /* Restart Rx engine if stopped. */
2394 if (np->oom)
2395 mod_timer(&np->timer, jiffies + 1);
2396 else
2397 writel(RxOn, ioaddr + ChipCmd);
2398}
2399
2400static void netdev_error(struct net_device *dev, int intr_status)
2401{
2402 struct netdev_private *np = netdev_priv(dev);
2403 void __iomem * ioaddr = ns_ioaddr(dev);
2404
2405 spin_lock(&np->lock);
2406 if (intr_status & LinkChange) {
2407 u16 lpa = mdio_read(dev, MII_LPA);
2408 if (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE
2409 && netif_msg_link(np)) {
2410 printk(KERN_INFO
2411 "%s: Autonegotiation advertising"
2412 " %#04x partner %#04x.\n", dev->name,
2413 np->advertising, lpa);
2414 }
2415
2416 /* read MII int status to clear the flag */
2417 readw(ioaddr + MIntrStatus);
2418 check_link(dev);
2419 }
2420 if (intr_status & StatsMax) {
2421 __get_stats(dev);
2422 }
2423 if (intr_status & IntrTxUnderrun) {
2424 if ((np->tx_config & TxDrthMask) < TX_DRTH_VAL_LIMIT) {
2425 np->tx_config += TX_DRTH_VAL_INC;
2426 if (netif_msg_tx_err(np))
2427 printk(KERN_NOTICE
2428 "%s: increased tx threshold, txcfg %#08x.\n",
2429 dev->name, np->tx_config);
2430 } else {
2431 if (netif_msg_tx_err(np))
2432 printk(KERN_NOTICE
2433 "%s: tx underrun with maximum tx threshold, txcfg %#08x.\n",
2434 dev->name, np->tx_config);
2435 }
2436 writel(np->tx_config, ioaddr + TxConfig);
2437 }
2438 if (intr_status & WOLPkt && netif_msg_wol(np)) {
2439 int wol_status = readl(ioaddr + WOLCmd);
2440 printk(KERN_NOTICE "%s: Link wake-up event %#08x\n",
2441 dev->name, wol_status);
2442 }
2443 if (intr_status & RxStatusFIFOOver) {
2444 if (netif_msg_rx_err(np) && netif_msg_intr(np)) {
2445 printk(KERN_NOTICE "%s: Rx status FIFO overrun\n",
2446 dev->name);
2447 }
2448 np->stats.rx_fifo_errors++;
2449 }
2450 /* Hmmmmm, it's not clear how to recover from PCI faults. */
2451 if (intr_status & IntrPCIErr) {
2452 printk(KERN_NOTICE "%s: PCI error %#08x\n", dev->name,
2453 intr_status & IntrPCIErr);
2454 np->stats.tx_fifo_errors++;
2455 np->stats.rx_fifo_errors++;
2456 }
2457 spin_unlock(&np->lock);
2458}
2459
2460static void __get_stats(struct net_device *dev)
2461{
2462 void __iomem * ioaddr = ns_ioaddr(dev);
2463 struct netdev_private *np = netdev_priv(dev);
2464
2465 /* The chip only need report frame silently dropped. */
2466 np->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs);
2467 np->stats.rx_missed_errors += readl(ioaddr + RxMissed);
2468}
2469
2470static struct net_device_stats *get_stats(struct net_device *dev)
2471{
2472 struct netdev_private *np = netdev_priv(dev);
2473
2474 /* The chip only need report frame silently dropped. */
2475 spin_lock_irq(&np->lock);
2476 if (netif_running(dev) && !np->hands_off)
2477 __get_stats(dev);
2478 spin_unlock_irq(&np->lock);
2479
2480 return &np->stats;
2481}
2482
2483#ifdef CONFIG_NET_POLL_CONTROLLER
2484static void natsemi_poll_controller(struct net_device *dev)
2485{
2486 disable_irq(dev->irq);
2487 intr_handler(dev->irq, dev, NULL);
2488 enable_irq(dev->irq);
2489}
2490#endif
2491
2492#define HASH_TABLE 0x200
2493static void __set_rx_mode(struct net_device *dev)
2494{
2495 void __iomem * ioaddr = ns_ioaddr(dev);
2496 struct netdev_private *np = netdev_priv(dev);
2497 u8 mc_filter[64]; /* Multicast hash filter */
2498 u32 rx_mode;
2499
2500 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
2501 /* Unconditionally log net taps. */
2502 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2503 dev->name);
2504 rx_mode = RxFilterEnable | AcceptBroadcast
2505 | AcceptAllMulticast | AcceptAllPhys | AcceptMyPhys;
2506 } else if ((dev->mc_count > multicast_filter_limit)
2507 || (dev->flags & IFF_ALLMULTI)) {
2508 rx_mode = RxFilterEnable | AcceptBroadcast
2509 | AcceptAllMulticast | AcceptMyPhys;
2510 } else {
2511 struct dev_mc_list *mclist;
2512 int i;
2513 memset(mc_filter, 0, sizeof(mc_filter));
2514 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2515 i++, mclist = mclist->next) {
2516 int i = (ether_crc(ETH_ALEN, mclist->dmi_addr) >> 23) & 0x1ff;
2517 mc_filter[i/8] |= (1 << (i & 0x07));
2518 }
2519 rx_mode = RxFilterEnable | AcceptBroadcast
2520 | AcceptMulticast | AcceptMyPhys;
2521 for (i = 0; i < 64; i += 2) {
760f86d7
HX		 2522 writel(HASH_TABLE + i, ioaddr + RxFilterAddr);
2523 writel((mc_filter[i + 1] << 8) + mc_filter[i],
2524 ioaddr + RxFilterData);
1da177e4
LT		 2525 }
2526 }
2527 writel(rx_mode, ioaddr + RxFilterAddr);
2528 np->cur_rx_mode = rx_mode;
2529}
2530
2531static int natsemi_change_mtu(struct net_device *dev, int new_mtu)
2532{
2533 if (new_mtu < 64 || new_mtu > NATSEMI_RX_LIMIT-NATSEMI_HEADERS)
2534 return -EINVAL;
2535
2536 dev->mtu = new_mtu;
2537
2538 /* synchronized against open : rtnl_lock() held by caller */
2539 if (netif_running(dev)) {
2540 struct netdev_private *np = netdev_priv(dev);
2541 void __iomem * ioaddr = ns_ioaddr(dev);
2542
2543 disable_irq(dev->irq);
2544 spin_lock(&np->lock);
2545 /* stop engines */
2546 natsemi_stop_rxtx(dev);
2547 /* drain rx queue */
2548 drain_rx(dev);
2549 /* change buffers */
2550 set_bufsize(dev);
2551 reinit_rx(dev);
2552 writel(np->ring_dma, ioaddr + RxRingPtr);
2553 /* restart engines */
2554 writel(RxOn | TxOn, ioaddr + ChipCmd);
2555 spin_unlock(&np->lock);
2556 enable_irq(dev->irq);
2557 }
2558 return 0;
2559}
2560
2561static void set_rx_mode(struct net_device *dev)
2562{
2563 struct netdev_private *np = netdev_priv(dev);
2564 spin_lock_irq(&np->lock);
2565 if (!np->hands_off)
2566 __set_rx_mode(dev);
2567 spin_unlock_irq(&np->lock);
2568}
2569
2570static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2571{
2572 struct netdev_private *np = netdev_priv(dev);
2573 strncpy(info->driver, DRV_NAME, ETHTOOL_BUSINFO_LEN);
2574 strncpy(info->version, DRV_VERSION, ETHTOOL_BUSINFO_LEN);
2575 strncpy(info->bus_info, pci_name(np->pci_dev), ETHTOOL_BUSINFO_LEN);
2576}
2577
2578static int get_regs_len(struct net_device *dev)
2579{
2580 return NATSEMI_REGS_SIZE;
2581}
2582
2583static int get_eeprom_len(struct net_device *dev)
2584{
a8b4cf42
MB		 2585 struct netdev_private *np = netdev_priv(dev);
2586 return np->eeprom_size;
1da177e4
LT		 2587}
2588
2589static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2590{
2591 struct netdev_private *np = netdev_priv(dev);
2592 spin_lock_irq(&np->lock);
2593 netdev_get_ecmd(dev, ecmd);
2594 spin_unlock_irq(&np->lock);
2595 return 0;
2596}
2597
2598static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2599{
2600 struct netdev_private *np = netdev_priv(dev);
2601 int res;
2602 spin_lock_irq(&np->lock);
2603 res = netdev_set_ecmd(dev, ecmd);
2604 spin_unlock_irq(&np->lock);
2605 return res;
2606}
2607
2608static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2609{
2610 struct netdev_private *np = netdev_priv(dev);
2611 spin_lock_irq(&np->lock);
2612 netdev_get_wol(dev, &wol->supported, &wol->wolopts);
2613 netdev_get_sopass(dev, wol->sopass);
2614 spin_unlock_irq(&np->lock);
2615}
2616
2617static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2618{
2619 struct netdev_private *np = netdev_priv(dev);
2620 int res;
2621 spin_lock_irq(&np->lock);
2622 netdev_set_wol(dev, wol->wolopts);
2623 res = netdev_set_sopass(dev, wol->sopass);
2624 spin_unlock_irq(&np->lock);
2625 return res;
2626}
2627
2628static void get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2629{
2630 struct netdev_private *np = netdev_priv(dev);
2631 regs->version = NATSEMI_REGS_VER;
2632 spin_lock_irq(&np->lock);
2633 netdev_get_regs(dev, buf);
2634 spin_unlock_irq(&np->lock);
2635}
2636
2637static u32 get_msglevel(struct net_device *dev)
2638{
2639 struct netdev_private *np = netdev_priv(dev);
2640 return np->msg_enable;
2641}
2642
2643static void set_msglevel(struct net_device *dev, u32 val)
2644{
2645 struct netdev_private *np = netdev_priv(dev);
2646 np->msg_enable = val;
2647}
2648
2649static int nway_reset(struct net_device *dev)
2650{
2651 int tmp;
2652 int r = -EINVAL;
2653 /* if autoneg is off, it's an error */
2654 tmp = mdio_read(dev, MII_BMCR);
2655 if (tmp & BMCR_ANENABLE) {
2656 tmp |= (BMCR_ANRESTART);
2657 mdio_write(dev, MII_BMCR, tmp);
2658 r = 0;
2659 }
2660 return r;
2661}
2662
2663static u32 get_link(struct net_device *dev)
2664{
2665 /* LSTATUS is latched low until a read - so read twice */
2666 mdio_read(dev, MII_BMSR);
2667 return (mdio_read(dev, MII_BMSR)&BMSR_LSTATUS) ? 1:0;
2668}
2669
2670static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
2671{
2672 struct netdev_private *np = netdev_priv(dev);
a8b4cf42 2673 u8 *eebuf;
1da177e4
LT		 2674 int res;
2675
a8b4cf42
MB		 2676 eebuf = kmalloc(np->eeprom_size, GFP_KERNEL);
2677 if (!eebuf)
2678 return -ENOMEM;
2679
1da177e4
LT		 2680 eeprom->magic = PCI_VENDOR_ID_NS | (PCI_DEVICE_ID_NS_83815<<16);
2681 spin_lock_irq(&np->lock);
2682 res = netdev_get_eeprom(dev, eebuf);
2683 spin_unlock_irq(&np->lock);
2684 if (!res)
2685 memcpy(data, eebuf+eeprom->offset, eeprom->len);
a8b4cf42 2686 kfree(eebuf);
1da177e4
LT		 2687 return res;
2688}
2689
2690static struct ethtool_ops ethtool_ops = {
2691 .get_drvinfo = get_drvinfo,
2692 .get_regs_len = get_regs_len,
2693 .get_eeprom_len = get_eeprom_len,
2694 .get_settings = get_settings,
2695 .set_settings = set_settings,
2696 .get_wol = get_wol,
2697 .set_wol = set_wol,
2698 .get_regs = get_regs,
2699 .get_msglevel = get_msglevel,
2700 .set_msglevel = set_msglevel,
2701 .nway_reset = nway_reset,
2702 .get_link = get_link,
2703 .get_eeprom = get_eeprom,
2704};
2705
2706static int netdev_set_wol(struct net_device *dev, u32 newval)
2707{
2708 struct netdev_private *np = netdev_priv(dev);
2709 void __iomem * ioaddr = ns_ioaddr(dev);
2710 u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary;
2711
2712 /* translate to bitmasks this chip understands */
2713 if (newval & WAKE_PHY)
2714 data |= WakePhy;
2715 if (newval & WAKE_UCAST)
2716 data |= WakeUnicast;
2717 if (newval & WAKE_MCAST)
2718 data |= WakeMulticast;
2719 if (newval & WAKE_BCAST)
2720 data |= WakeBroadcast;
2721 if (newval & WAKE_ARP)
2722 data |= WakeArp;
2723 if (newval & WAKE_MAGIC)
2724 data |= WakeMagic;
2725 if (np->srr >= SRR_DP83815_D) {
2726 if (newval & WAKE_MAGICSECURE) {
2727 data |= WakeMagicSecure;
2728 }
2729 }
2730
2731 writel(data, ioaddr + WOLCmd);
2732
2733 return 0;
2734}
2735
2736static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur)
2737{
2738 struct netdev_private *np = netdev_priv(dev);
2739 void __iomem * ioaddr = ns_ioaddr(dev);
2740 u32 regval = readl(ioaddr + WOLCmd);
2741
2742 *supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST
2743 | WAKE_ARP | WAKE_MAGIC);
2744
2745 if (np->srr >= SRR_DP83815_D) {
2746 /* SOPASS works on revD and higher */
2747 *supported |= WAKE_MAGICSECURE;
2748 }
2749 *cur = 0;
2750
2751 /* translate from chip bitmasks */
2752 if (regval & WakePhy)
2753 *cur |= WAKE_PHY;
2754 if (regval & WakeUnicast)
2755 *cur |= WAKE_UCAST;
2756 if (regval & WakeMulticast)
2757 *cur |= WAKE_MCAST;
2758 if (regval & WakeBroadcast)
2759 *cur |= WAKE_BCAST;
2760 if (regval & WakeArp)
2761 *cur |= WAKE_ARP;
2762 if (regval & WakeMagic)
2763 *cur |= WAKE_MAGIC;
2764 if (regval & WakeMagicSecure) {
2765 /* this can be on in revC, but it's broken */
2766 *cur |= WAKE_MAGICSECURE;
2767 }
2768
2769 return 0;
2770}
2771
2772static int netdev_set_sopass(struct net_device *dev, u8 *newval)
2773{
2774 struct netdev_private *np = netdev_priv(dev);
2775 void __iomem * ioaddr = ns_ioaddr(dev);
2776 u16 *sval = (u16 *)newval;
2777 u32 addr;
2778
2779 if (np->srr < SRR_DP83815_D) {
2780 return 0;
2781 }
2782
2783 /* enable writing to these registers by disabling the RX filter */
2784 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2785 addr &= ~RxFilterEnable;
2786 writel(addr, ioaddr + RxFilterAddr);
2787
2788 /* write the three words to (undocumented) RFCR vals 0xa, 0xc, 0xe */
2789 writel(addr | 0xa, ioaddr + RxFilterAddr);
2790 writew(sval[0], ioaddr + RxFilterData);
2791
2792 writel(addr | 0xc, ioaddr + RxFilterAddr);
2793 writew(sval[1], ioaddr + RxFilterData);
2794
2795 writel(addr | 0xe, ioaddr + RxFilterAddr);
2796 writew(sval[2], ioaddr + RxFilterData);
2797
2798 /* re-enable the RX filter */
2799 writel(addr | RxFilterEnable, ioaddr + RxFilterAddr);
2800
2801 return 0;
2802}
2803
2804static int netdev_get_sopass(struct net_device *dev, u8 *data)
2805{
2806 struct netdev_private *np = netdev_priv(dev);
2807 void __iomem * ioaddr = ns_ioaddr(dev);
2808 u16 *sval = (u16 *)data;
2809 u32 addr;
2810
2811 if (np->srr < SRR_DP83815_D) {
2812 sval[0] = sval[1] = sval[2] = 0;
2813 return 0;
2814 }
2815
2816 /* read the three words from (undocumented) RFCR vals 0xa, 0xc, 0xe */
2817 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2818
2819 writel(addr | 0xa, ioaddr + RxFilterAddr);
2820 sval[0] = readw(ioaddr + RxFilterData);
2821
2822 writel(addr | 0xc, ioaddr + RxFilterAddr);
2823 sval[1] = readw(ioaddr + RxFilterData);
2824
2825 writel(addr | 0xe, ioaddr + RxFilterAddr);
2826 sval[2] = readw(ioaddr + RxFilterData);
2827
2828 writel(addr, ioaddr + RxFilterAddr);
2829
2830 return 0;
2831}
2832
2833static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2834{
2835 struct netdev_private *np = netdev_priv(dev);
2836 u32 tmp;
2837
2838 ecmd->port = dev->if_port;
2839 ecmd->speed = np->speed;
2840 ecmd->duplex = np->duplex;
2841 ecmd->autoneg = np->autoneg;
2842 ecmd->advertising = 0;
2843 if (np->advertising & ADVERTISE_10HALF)
2844 ecmd->advertising |= ADVERTISED_10baseT_Half;
2845 if (np->advertising & ADVERTISE_10FULL)
2846 ecmd->advertising |= ADVERTISED_10baseT_Full;
2847 if (np->advertising & ADVERTISE_100HALF)
2848 ecmd->advertising |= ADVERTISED_100baseT_Half;
2849 if (np->advertising & ADVERTISE_100FULL)
2850 ecmd->advertising |= ADVERTISED_100baseT_Full;
2851 ecmd->supported = (SUPPORTED_Autoneg |
2852 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2853 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2854 SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_FIBRE);
2855 ecmd->phy_address = np->phy_addr_external;
2856 /*
2857 * We intentionally report the phy address of the external
2858 * phy, even if the internal phy is used. This is necessary
2859 * to work around a deficiency of the ethtool interface:
2860 * It's only possible to query the settings of the active
2861 * port. Therefore
2862 * # ethtool -s ethX port mii
2863 * actually sends an ioctl to switch to port mii with the
2864 * settings that are used for the current active port.
2865 * If we would report a different phy address in this
2866 * command, then
2867 * # ethtool -s ethX port tp;ethtool -s ethX port mii
2868 * would unintentionally change the phy address.
2869 *
2870 * Fortunately the phy address doesn't matter with the
2871 * internal phy...
2872 */
2873
2874 /* set information based on active port type */
2875 switch (ecmd->port) {
2876 default:
2877 case PORT_TP:
2878 ecmd->advertising |= ADVERTISED_TP;
2879 ecmd->transceiver = XCVR_INTERNAL;
2880 break;
2881 case PORT_MII:
2882 ecmd->advertising |= ADVERTISED_MII;
2883 ecmd->transceiver = XCVR_EXTERNAL;
2884 break;
2885 case PORT_FIBRE:
2886 ecmd->advertising |= ADVERTISED_FIBRE;
2887 ecmd->transceiver = XCVR_EXTERNAL;
2888 break;
2889 }
2890
2891 /* if autonegotiation is on, try to return the active speed/duplex */
2892 if (ecmd->autoneg == AUTONEG_ENABLE) {
2893 ecmd->advertising |= ADVERTISED_Autoneg;
2894 tmp = mii_nway_result(
2895 np->advertising & mdio_read(dev, MII_LPA));
2896 if (tmp == LPA_100FULL || tmp == LPA_100HALF)
2897 ecmd->speed = SPEED_100;
2898 else
2899 ecmd->speed = SPEED_10;
2900 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
2901 ecmd->duplex = DUPLEX_FULL;
2902 else
2903 ecmd->duplex = DUPLEX_HALF;
2904 }
2905
2906 /* ignore maxtxpkt, maxrxpkt for now */
2907
2908 return 0;
2909}
2910
2911static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2912{
2913 struct netdev_private *np = netdev_priv(dev);
2914
2915 if (ecmd->port != PORT_TP && ecmd->port != PORT_MII && ecmd->port != PORT_FIBRE)
2916 return -EINVAL;
2917 if (ecmd->transceiver != XCVR_INTERNAL && ecmd->transceiver != XCVR_EXTERNAL)
2918 return -EINVAL;
2919 if (ecmd->autoneg == AUTONEG_ENABLE) {
2920 if ((ecmd->advertising & (ADVERTISED_10baseT_Half |
2921 ADVERTISED_10baseT_Full |
2922 ADVERTISED_100baseT_Half |
2923 ADVERTISED_100baseT_Full)) == 0) {
2924 return -EINVAL;
2925 }
2926 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2927 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2928 return -EINVAL;
2929 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2930 return -EINVAL;
2931 } else {
2932 return -EINVAL;
2933 }
2934
2935 /*
2936 * maxtxpkt, maxrxpkt: ignored for now.
2937 *
2938 * transceiver:
2939 * PORT_TP is always XCVR_INTERNAL, PORT_MII and PORT_FIBRE are always
2940 * XCVR_EXTERNAL. The implementation thus ignores ecmd->transceiver and
2941 * selects based on ecmd->port.
2942 *
2943 * Actually PORT_FIBRE is nearly identical to PORT_MII: it's for fibre
2944 * phys that are connected to the mii bus. It's used to apply fibre
2945 * specific updates.
2946 */
2947
2948 /* WHEW! now lets bang some bits */
2949
2950 /* save the parms */
2951 dev->if_port = ecmd->port;
2952 np->autoneg = ecmd->autoneg;
2953 np->phy_addr_external = ecmd->phy_address & PhyAddrMask;
2954 if (np->autoneg == AUTONEG_ENABLE) {
2955 /* advertise only what has been requested */
2956 np->advertising &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2957 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2958 np->advertising |= ADVERTISE_10HALF;
2959 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2960 np->advertising |= ADVERTISE_10FULL;
2961 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2962 np->advertising |= ADVERTISE_100HALF;
2963 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2964 np->advertising |= ADVERTISE_100FULL;
2965 } else {
2966 np->speed = ecmd->speed;
2967 np->duplex = ecmd->duplex;
2968 /* user overriding the initial full duplex parm? */
2969 if (np->duplex == DUPLEX_HALF)
2970 np->full_duplex = 0;
2971 }
2972
2973 /* get the right phy enabled */
2974 if (ecmd->port == PORT_TP)
2975 switch_port_internal(dev);
2976 else
2977 switch_port_external(dev);
2978
2979 /* set parms and see how this affected our link status */
2980 init_phy_fixup(dev);
2981 check_link(dev);
2982 return 0;
2983}
2984
2985static int netdev_get_regs(struct net_device *dev, u8 *buf)
2986{
2987 int i;
2988 int j;
2989 u32 rfcr;
2990 u32 *rbuf = (u32 *)buf;
2991 void __iomem * ioaddr = ns_ioaddr(dev);
2992
2993 /* read non-mii page 0 of registers */
2994 for (i = 0; i < NATSEMI_PG0_NREGS/2; i++) {
2995 rbuf[i] = readl(ioaddr + i*4);
2996 }
2997
2998 /* read current mii registers */
2999 for (i = NATSEMI_PG0_NREGS/2; i < NATSEMI_PG0_NREGS; i++)
3000 rbuf[i] = mdio_read(dev, i & 0x1f);
3001
3002 /* read only the 'magic' registers from page 1 */
3003 writew(1, ioaddr + PGSEL);
3004 rbuf[i++] = readw(ioaddr + PMDCSR);
3005 rbuf[i++] = readw(ioaddr + TSTDAT);
3006 rbuf[i++] = readw(ioaddr + DSPCFG);
3007 rbuf[i++] = readw(ioaddr + SDCFG);
3008 writew(0, ioaddr + PGSEL);
3009
3010 /* read RFCR indexed registers */
3011 rfcr = readl(ioaddr + RxFilterAddr);
3012 for (j = 0; j < NATSEMI_RFDR_NREGS; j++) {
3013 writel(j*2, ioaddr + RxFilterAddr);
3014 rbuf[i++] = readw(ioaddr + RxFilterData);
3015 }
3016 writel(rfcr, ioaddr + RxFilterAddr);
3017
3018 /* the interrupt status is clear-on-read - see if we missed any */
3019 if (rbuf[4] & rbuf[5]) {
3020 printk(KERN_WARNING
3021 "%s: shoot, we dropped an interrupt (%#08x)\n",
3022 dev->name, rbuf[4] & rbuf[5]);
3023 }
3024
3025 return 0;
3026}
3027
3028#define SWAP_BITS(x) ( (((x) & 0x0001) << 15) | (((x) & 0x0002) << 13) \
3029 | (((x) & 0x0004) << 11) | (((x) & 0x0008) << 9) \
3030 | (((x) & 0x0010) << 7) | (((x) & 0x0020) << 5) \
3031 | (((x) & 0x0040) << 3) | (((x) & 0x0080) << 1) \
3032 | (((x) & 0x0100) >> 1) | (((x) & 0x0200) >> 3) \
3033 | (((x) & 0x0400) >> 5) | (((x) & 0x0800) >> 7) \
3034 | (((x) & 0x1000) >> 9) | (((x) & 0x2000) >> 11) \
3035 | (((x) & 0x4000) >> 13) | (((x) & 0x8000) >> 15) )
3036
3037static int netdev_get_eeprom(struct net_device *dev, u8 *buf)
3038{
3039 int i;
3040 u16 *ebuf = (u16 *)buf;
3041 void __iomem * ioaddr = ns_ioaddr(dev);
a8b4cf42 3042 struct netdev_private *np = netdev_priv(dev);
1da177e4
LT		 3043
3044 /* eeprom_read reads 16 bits, and indexes by 16 bits */
a8b4cf42 3045 for (i = 0; i < np->eeprom_size/2; i++) {
1da177e4
LT		 3046 ebuf[i] = eeprom_read(ioaddr, i);
3047 /* The EEPROM itself stores data bit-swapped, but eeprom_read
3048 * reads it back "sanely". So we swap it back here in order to
3049 * present it to userland as it is stored. */
3050 ebuf[i] = SWAP_BITS(ebuf[i]);
3051 }
3052 return 0;
3053}
3054
3055static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3056{
3057 struct mii_ioctl_data *data = if_mii(rq);
3058 struct netdev_private *np = netdev_priv(dev);
3059
3060 switch(cmd) {
3061 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
3062 case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */
3063 data->phy_id = np->phy_addr_external;
3064 /* Fall Through */
3065
3066 case SIOCGMIIREG: /* Read MII PHY register. */
3067 case SIOCDEVPRIVATE+1: /* for binary compat, remove in 2.5 */
3068 /* The phy_id is not enough to uniquely identify
3069 * the intended target. Therefore the command is sent to
3070 * the given mii on the current port.
3071 */
3072 if (dev->if_port == PORT_TP) {
3073 if ((data->phy_id & 0x1f) == np->phy_addr_external)
3074 data->val_out = mdio_read(dev,
3075 data->reg_num & 0x1f);
3076 else
3077 data->val_out = 0;
3078 } else {
3079 move_int_phy(dev, data->phy_id & 0x1f);
3080 data->val_out = miiport_read(dev, data->phy_id & 0x1f,
3081 data->reg_num & 0x1f);
3082 }
3083 return 0;
3084
3085 case SIOCSMIIREG: /* Write MII PHY register. */
3086 case SIOCDEVPRIVATE+2: /* for binary compat, remove in 2.5 */
3087 if (!capable(CAP_NET_ADMIN))
3088 return -EPERM;
3089 if (dev->if_port == PORT_TP) {
3090 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3091 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3092 np->advertising = data->val_in;
3093 mdio_write(dev, data->reg_num & 0x1f,
3094 data->val_in);
3095 }
3096 } else {
3097 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3098 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3099 np->advertising = data->val_in;
3100 }
3101 move_int_phy(dev, data->phy_id & 0x1f);
3102 miiport_write(dev, data->phy_id & 0x1f,
3103 data->reg_num & 0x1f,
3104 data->val_in);
3105 }
3106 return 0;
3107 default:
3108 return -EOPNOTSUPP;
3109 }
3110}
3111
3112static void enable_wol_mode(struct net_device *dev, int enable_intr)
3113{
3114 void __iomem * ioaddr = ns_ioaddr(dev);
3115 struct netdev_private *np = netdev_priv(dev);
3116
3117 if (netif_msg_wol(np))
3118 printk(KERN_INFO "%s: remaining active for wake-on-lan\n",
3119 dev->name);
3120
3121 /* For WOL we must restart the rx process in silent mode.
3122 * Write NULL to the RxRingPtr. Only possible if
3123 * rx process is stopped
3124 */
3125 writel(0, ioaddr + RxRingPtr);
3126
3127 /* read WoL status to clear */
3128 readl(ioaddr + WOLCmd);
3129
3130 /* PME on, clear status */
3131 writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun);
3132
3133 /* and restart the rx process */
3134 writel(RxOn, ioaddr + ChipCmd);
3135
3136 if (enable_intr) {
3137 /* enable the WOL interrupt.
3138 * Could be used to send a netlink message.
3139 */
3140 writel(WOLPkt | LinkChange, ioaddr + IntrMask);
3141 writel(1, ioaddr + IntrEnable);
3142 }
3143}
3144
3145static int netdev_close(struct net_device *dev)
3146{
3147 void __iomem * ioaddr = ns_ioaddr(dev);
3148 struct netdev_private *np = netdev_priv(dev);
3149
3150 if (netif_msg_ifdown(np))
3151 printk(KERN_DEBUG
3152 "%s: Shutting down ethercard, status was %#04x.\n",
3153 dev->name, (int)readl(ioaddr + ChipCmd));
3154 if (netif_msg_pktdata(np))
3155 printk(KERN_DEBUG
3156 "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
3157 dev->name, np->cur_tx, np->dirty_tx,
3158 np->cur_rx, np->dirty_rx);
3159
3160 /*
3161 * FIXME: what if someone tries to close a device
3162 * that is suspended?
3163 * Should we reenable the nic to switch to
3164 * the final WOL settings?
3165 */
3166
3167 del_timer_sync(&np->timer);
3168 disable_irq(dev->irq);
3169 spin_lock_irq(&np->lock);
b27a16b7 3170 natsemi_irq_disable(dev);
1da177e4
LT		 3171 np->hands_off = 1;
3172 spin_unlock_irq(&np->lock);
3173 enable_irq(dev->irq);
3174
3175 free_irq(dev->irq, dev);
3176
3177 /* Interrupt disabled, interrupt handler released,
3178 * queue stopped, timer deleted, rtnl_lock held
3179 * All async codepaths that access the driver are disabled.
3180 */
3181 spin_lock_irq(&np->lock);
3182 np->hands_off = 0;
3183 readl(ioaddr + IntrMask);
3184 readw(ioaddr + MIntrStatus);
3185
3186 /* Freeze Stats */
3187 writel(StatsFreeze, ioaddr + StatsCtrl);
3188
3189 /* Stop the chip's Tx and Rx processes. */
3190 natsemi_stop_rxtx(dev);
3191
3192 __get_stats(dev);
3193 spin_unlock_irq(&np->lock);
3194
3195 /* clear the carrier last - an interrupt could reenable it otherwise */
3196 netif_carrier_off(dev);
3197 netif_stop_queue(dev);
3198
3199 dump_ring(dev);
3200 drain_ring(dev);
3201 free_ring(dev);
3202
3203 {
3204 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3205 if (wol) {
3206 /* restart the NIC in WOL mode.
3207 * The nic must be stopped for this.
3208 */
3209 enable_wol_mode(dev, 0);
3210 } else {
3211 /* Restore PME enable bit unmolested */
3212 writel(np->SavedClkRun, ioaddr + ClkRun);
3213 }
3214 }
3215 return 0;
3216}
3217
3218
3219static void __devexit natsemi_remove1 (struct pci_dev *pdev)
3220{
3221 struct net_device *dev = pci_get_drvdata(pdev);
3222 void __iomem * ioaddr = ns_ioaddr(dev);
3223
3224 unregister_netdev (dev);
3225 pci_release_regions (pdev);
3226 iounmap(ioaddr);
3227 free_netdev (dev);
3228 pci_set_drvdata(pdev, NULL);
3229}
3230
3231#ifdef CONFIG_PM
3232
3233/*
3234 * The ns83815 chip doesn't have explicit RxStop bits.
3235 * Kicking the Rx or Tx process for a new packet reenables the Rx process
3236 * of the nic, thus this function must be very careful:
3237 *
3238 * suspend/resume synchronization:
3239 * entry points:
3240 * netdev_open, netdev_close, netdev_ioctl, set_rx_mode, intr_handler,
3241 * start_tx, tx_timeout
3242 *
3243 * No function accesses the hardware without checking np->hands_off.
3244 * the check occurs under spin_lock_irq(&np->lock);
3245 * exceptions:
3246 * * netdev_ioctl: noncritical access.
3247 * * netdev_open: cannot happen due to the device_detach
3248 * * netdev_close: doesn't hurt.
3249 * * netdev_timer: timer stopped by natsemi_suspend.
3250 * * intr_handler: doesn't acquire the spinlock. suspend calls
3251 * disable_irq() to enforce synchronization.
b27a16b7
MB		 3252 * * natsemi_poll: checks before reenabling interrupts. suspend
3253 * sets hands_off, disables interrupts and then waits with
3254 * netif_poll_disable().
1da177e4
LT		 3255 *
3256 * Interrupts must be disabled, otherwise hands_off can cause irq storms.
3257 */
3258
3259static int natsemi_suspend (struct pci_dev *pdev, pm_message_t state)
3260{
3261 struct net_device *dev = pci_get_drvdata (pdev);
3262 struct netdev_private *np = netdev_priv(dev);
3263 void __iomem * ioaddr = ns_ioaddr(dev);
3264
3265 rtnl_lock();
3266 if (netif_running (dev)) {
3267 del_timer_sync(&np->timer);
3268
3269 disable_irq(dev->irq);
3270 spin_lock_irq(&np->lock);
3271
3272 writel(0, ioaddr + IntrEnable);
3273 np->hands_off = 1;
3274 natsemi_stop_rxtx(dev);
3275 netif_stop_queue(dev);
3276
3277 spin_unlock_irq(&np->lock);
3278 enable_irq(dev->irq);
3279
b27a16b7
MB		 3280 netif_poll_disable(dev);
3281
1da177e4
LT		 3282 /* Update the error counts. */
3283 __get_stats(dev);
3284
3285 /* pci_power_off(pdev, -1); */
3286 drain_ring(dev);
3287 {
3288 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3289 /* Restore PME enable bit */
3290 if (wol) {
3291 /* restart the NIC in WOL mode.
3292 * The nic must be stopped for this.
3293 * FIXME: use the WOL interrupt
3294 */
3295 enable_wol_mode(dev, 0);
3296 } else {
3297 /* Restore PME enable bit unmolested */
3298 writel(np->SavedClkRun, ioaddr + ClkRun);
3299 }
3300 }
3301 }
3302 netif_device_detach(dev);
3303 rtnl_unlock();
3304 return 0;
3305}
3306
3307
3308static int natsemi_resume (struct pci_dev *pdev)
3309{
3310 struct net_device *dev = pci_get_drvdata (pdev);
3311 struct netdev_private *np = netdev_priv(dev);
3312
3313 rtnl_lock();
3314 if (netif_device_present(dev))
3315 goto out;
3316 if (netif_running(dev)) {
3317 BUG_ON(!np->hands_off);
3318 pci_enable_device(pdev);
3319 /* pci_power_on(pdev); */
3320
3321 natsemi_reset(dev);
3322 init_ring(dev);
3323 disable_irq(dev->irq);
3324 spin_lock_irq(&np->lock);
3325 np->hands_off = 0;
3326 init_registers(dev);
3327 netif_device_attach(dev);
3328 spin_unlock_irq(&np->lock);
3329 enable_irq(dev->irq);
3330
3331 mod_timer(&np->timer, jiffies + 1*HZ);
3332 }
3333 netif_device_attach(dev);
b27a16b7 3334 netif_poll_enable(dev);
1da177e4
LT		 3335out:
3336 rtnl_unlock();
3337 return 0;
3338}
3339
3340#endif /* CONFIG_PM */
3341
3342static struct pci_driver natsemi_driver = {
3343 .name = DRV_NAME,
3344 .id_table = natsemi_pci_tbl,
3345 .probe = natsemi_probe1,
3346 .remove = __devexit_p(natsemi_remove1),
3347#ifdef CONFIG_PM
3348 .suspend = natsemi_suspend,
3349 .resume = natsemi_resume,
3350#endif
3351};
3352
3353static int __init natsemi_init_mod (void)
3354{
3355/* when a module, this is printed whether or not devices are found in probe */
3356#ifdef MODULE
3357 printk(version);
3358#endif
3359
3360 return pci_module_init (&natsemi_driver);
3361}
3362
3363static void __exit natsemi_exit_mod (void)
3364{
3365 pci_unregister_driver (&natsemi_driver);
3366}
3367
3368module_init(natsemi_init_mod);
3369module_exit(natsemi_exit_mod);
3370