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sparc: Move SBUS DMA attribute interfaces out of asm/sbus.h
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / myri_sbus.c
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a46c30fd 1/* myri_sbus.c: MyriCOM MyriNET SBUS card driver.
1da177e4 2 *
a46c30fd 3 * Copyright (C) 1996, 1999, 2006 David S. Miller (davem@davemloft.net)
1da177e4
LT		 4 */
5
6static char version[] =
a46c30fd 7 "myri_sbus.c:v2.0 June 23, 2006 David S. Miller (davem@davemloft.net)\n";
1da177e4
LT		 8
9#include <linux/module.h>
1da177e4
LT		 10#include <linux/errno.h>
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/fcntl.h>
14#include <linux/interrupt.h>
15#include <linux/ioport.h>
16#include <linux/in.h>
17#include <linux/slab.h>
18#include <linux/string.h>
19#include <linux/delay.h>
20#include <linux/init.h>
21#include <linux/netdevice.h>
22#include <linux/etherdevice.h>
23#include <linux/skbuff.h>
24#include <linux/bitops.h>
738f2b7b 25#include <linux/dma-mapping.h>
1da177e4
LT		 26
27#include <net/dst.h>
28#include <net/arp.h>
29#include <net/sock.h>
30#include <net/ipv6.h>
31
32#include <asm/system.h>
33#include <asm/io.h>
34#include <asm/dma.h>
35#include <asm/byteorder.h>
36#include <asm/idprom.h>
37#include <asm/sbus.h>
38#include <asm/openprom.h>
39#include <asm/oplib.h>
40#include <asm/auxio.h>
41#include <asm/pgtable.h>
42#include <asm/irq.h>
1da177e4
LT		 43
44#include "myri_sbus.h"
45#include "myri_code.h"
46
47/* #define DEBUG_DETECT */
48/* #define DEBUG_IRQ */
49/* #define DEBUG_TRANSMIT */
50/* #define DEBUG_RECEIVE */
51/* #define DEBUG_HEADER */
52
53#ifdef DEBUG_DETECT
54#define DET(x) printk x
55#else
56#define DET(x)
57#endif
58
59#ifdef DEBUG_IRQ
60#define DIRQ(x) printk x
61#else
62#define DIRQ(x)
63#endif
64
65#ifdef DEBUG_TRANSMIT
66#define DTX(x) printk x
67#else
68#define DTX(x)
69#endif
70
71#ifdef DEBUG_RECEIVE
72#define DRX(x) printk x
73#else
74#define DRX(x)
75#endif
76
77#ifdef DEBUG_HEADER
78#define DHDR(x) printk x
79#else
80#define DHDR(x)
81#endif
82
1da177e4
LT		 83static void myri_reset_off(void __iomem *lp, void __iomem *cregs)
84{
85 /* Clear IRQ mask. */
86 sbus_writel(0, lp + LANAI_EIMASK);
87
88 /* Turn RESET function off. */
89 sbus_writel(CONTROL_ROFF, cregs + MYRICTRL_CTRL);
90}
91
92static void myri_reset_on(void __iomem *cregs)
93{
94 /* Enable RESET function. */
95 sbus_writel(CONTROL_RON, cregs + MYRICTRL_CTRL);
96
97 /* Disable IRQ's. */
98 sbus_writel(CONTROL_DIRQ, cregs + MYRICTRL_CTRL);
99}
100
101static void myri_disable_irq(void __iomem *lp, void __iomem *cregs)
102{
103 sbus_writel(CONTROL_DIRQ, cregs + MYRICTRL_CTRL);
104 sbus_writel(0, lp + LANAI_EIMASK);
105 sbus_writel(ISTAT_HOST, lp + LANAI_ISTAT);
106}
107
108static void myri_enable_irq(void __iomem *lp, void __iomem *cregs)
109{
110 sbus_writel(CONTROL_EIRQ, cregs + MYRICTRL_CTRL);
111 sbus_writel(ISTAT_HOST, lp + LANAI_EIMASK);
112}
113
114static inline void bang_the_chip(struct myri_eth *mp)
115{
116 struct myri_shmem __iomem *shmem = mp->shmem;
117 void __iomem *cregs = mp->cregs;
118
119 sbus_writel(1, &shmem->send);
120 sbus_writel(CONTROL_WON, cregs + MYRICTRL_CTRL);
121}
122
123static int myri_do_handshake(struct myri_eth *mp)
124{
125 struct myri_shmem __iomem *shmem = mp->shmem;
126 void __iomem *cregs = mp->cregs;
127 struct myri_channel __iomem *chan = &shmem->channel;
128 int tick = 0;
129
130 DET(("myri_do_handshake: "));
131 if (sbus_readl(&chan->state) == STATE_READY) {
132 DET(("Already STATE_READY, failed.\n"));
133 return -1; /* We're hosed... */
134 }
135
136 myri_disable_irq(mp->lregs, cregs);
137
9db7720c 138 while (tick++ < 25) {
1da177e4
LT		 139 u32 softstate;
140
141 /* Wake it up. */
142 DET(("shakedown, CONTROL_WON, "));
143 sbus_writel(1, &shmem->shakedown);
144 sbus_writel(CONTROL_WON, cregs + MYRICTRL_CTRL);
145
146 softstate = sbus_readl(&chan->state);
147 DET(("chanstate[%08x] ", softstate));
148 if (softstate == STATE_READY) {
149 DET(("wakeup successful, "));
150 break;
151 }
152
153 if (softstate != STATE_WFN) {
154 DET(("not WFN setting that, "));
155 sbus_writel(STATE_WFN, &chan->state);
156 }
157
158 udelay(20);
159 }
160
161 myri_enable_irq(mp->lregs, cregs);
162
163 if (tick > 25) {
164 DET(("25 ticks we lose, failure.\n"));
165 return -1;
166 }
167 DET(("success\n"));
168 return 0;
169}
170
b48194bf 171static int __devinit myri_load_lanai(struct myri_eth *mp)
1da177e4
LT		 172{
173 struct net_device *dev = mp->dev;
174 struct myri_shmem __iomem *shmem = mp->shmem;
175 void __iomem *rptr;
176 int i;
177
178 myri_disable_irq(mp->lregs, mp->cregs);
179 myri_reset_on(mp->cregs);
180
181 rptr = mp->lanai;
182 for (i = 0; i < mp->eeprom.ramsz; i++)
183 sbus_writeb(0, rptr + i);
184
185 if (mp->eeprom.cpuvers >= CPUVERS_3_0)
186 sbus_writel(mp->eeprom.cval, mp->lregs + LANAI_CVAL);
187
188 /* Load executable code. */
189 for (i = 0; i < sizeof(lanai4_code); i++)
190 sbus_writeb(lanai4_code[i], rptr + (lanai4_code_off * 2) + i);
191
192 /* Load data segment. */
193 for (i = 0; i < sizeof(lanai4_data); i++)
194 sbus_writeb(lanai4_data[i], rptr + (lanai4_data_off * 2) + i);
195
196 /* Set device address. */
197 sbus_writeb(0, &shmem->addr[0]);
198 sbus_writeb(0, &shmem->addr[1]);
199 for (i = 0; i < 6; i++)
200 sbus_writeb(dev->dev_addr[i],
201 &shmem->addr[i + 2]);
202
203 /* Set SBUS bursts and interrupt mask. */
204 sbus_writel(((mp->myri_bursts & 0xf8) >> 3), &shmem->burst);
205 sbus_writel(SHMEM_IMASK_RX, &shmem->imask);
206
207 /* Release the LANAI. */
208 myri_disable_irq(mp->lregs, mp->cregs);
209 myri_reset_off(mp->lregs, mp->cregs);
210 myri_disable_irq(mp->lregs, mp->cregs);
211
212 /* Wait for the reset to complete. */
213 for (i = 0; i < 5000; i++) {
214 if (sbus_readl(&shmem->channel.state) != STATE_READY)
215 break;
216 else
217 udelay(10);
218 }
219
220 if (i == 5000)
221 printk(KERN_ERR "myricom: Chip would not reset after firmware load.\n");
222
223 i = myri_do_handshake(mp);
224 if (i)
225 printk(KERN_ERR "myricom: Handshake with LANAI failed.\n");
226
227 if (mp->eeprom.cpuvers == CPUVERS_4_0)
228 sbus_writel(0, mp->lregs + LANAI_VERS);
229
230 return i;
231}
232
233static void myri_clean_rings(struct myri_eth *mp)
234{
235 struct sendq __iomem *sq = mp->sq;
236 struct recvq __iomem *rq = mp->rq;
237 int i;
238
239 sbus_writel(0, &rq->tail);
240 sbus_writel(0, &rq->head);
241 for (i = 0; i < (RX_RING_SIZE+1); i++) {
242 if (mp->rx_skbs[i] != NULL) {
243 struct myri_rxd __iomem *rxd = &rq->myri_rxd[i];
244 u32 dma_addr;
245
246 dma_addr = sbus_readl(&rxd->myri_scatters[0].addr);
738f2b7b
DM		 247 dma_unmap_single(&mp->myri_sdev->ofdev.dev, dma_addr,
248 RX_ALLOC_SIZE, DMA_FROM_DEVICE);
1da177e4
LT		 249 dev_kfree_skb(mp->rx_skbs[i]);
250 mp->rx_skbs[i] = NULL;
251 }
252 }
253
254 mp->tx_old = 0;
255 sbus_writel(0, &sq->tail);
256 sbus_writel(0, &sq->head);
257 for (i = 0; i < TX_RING_SIZE; i++) {
258 if (mp->tx_skbs[i] != NULL) {
259 struct sk_buff *skb = mp->tx_skbs[i];
260 struct myri_txd __iomem *txd = &sq->myri_txd[i];
261 u32 dma_addr;
262
263 dma_addr = sbus_readl(&txd->myri_gathers[0].addr);
738f2b7b
DM		 264 dma_unmap_single(&mp->myri_sdev->ofdev.dev, dma_addr,
265 (skb->len + 3) & ~3,
266 DMA_TO_DEVICE);
1da177e4
LT		 267 dev_kfree_skb(mp->tx_skbs[i]);
268 mp->tx_skbs[i] = NULL;
269 }
270 }
271}
272
273static void myri_init_rings(struct myri_eth *mp, int from_irq)
274{
275 struct recvq __iomem *rq = mp->rq;
276 struct myri_rxd __iomem *rxd = &rq->myri_rxd[0];
277 struct net_device *dev = mp->dev;
9e24974d 278 gfp_t gfp_flags = GFP_KERNEL;
1da177e4
LT		 279 int i;
280
281 if (from_irq || in_interrupt())
282 gfp_flags = GFP_ATOMIC;
283
284 myri_clean_rings(mp);
285 for (i = 0; i < RX_RING_SIZE; i++) {
286 struct sk_buff *skb = myri_alloc_skb(RX_ALLOC_SIZE, gfp_flags);
287 u32 dma_addr;
288
289 if (!skb)
290 continue;
291 mp->rx_skbs[i] = skb;
292 skb->dev = dev;
293 skb_put(skb, RX_ALLOC_SIZE);
294
738f2b7b
DM		 295 dma_addr = dma_map_single(&mp->myri_sdev->ofdev.dev,
296 skb->data, RX_ALLOC_SIZE,
297 DMA_FROM_DEVICE);
1da177e4
LT		 298 sbus_writel(dma_addr, &rxd[i].myri_scatters[0].addr);
299 sbus_writel(RX_ALLOC_SIZE, &rxd[i].myri_scatters[0].len);
300 sbus_writel(i, &rxd[i].ctx);
301 sbus_writel(1, &rxd[i].num_sg);
302 }
303 sbus_writel(0, &rq->head);
304 sbus_writel(RX_RING_SIZE, &rq->tail);
305}
306
307static int myri_init(struct myri_eth *mp, int from_irq)
308{
309 myri_init_rings(mp, from_irq);
310 return 0;
311}
312
313static void myri_is_not_so_happy(struct myri_eth *mp)
314{
315}
316
317#ifdef DEBUG_HEADER
318static void dump_ehdr(struct ethhdr *ehdr)
319{
0795af57
JP		 320 DECLARE_MAC_BUF(mac);
321 DECLARE_MAC_BUF(mac2);
322 printk("ehdr[h_dst(%s)"
323 "h_source(%s)"
324 "h_proto(%04x)]\n",
325 print_mac(mac, ehdr->h_dest), print_mac(mac2, ehdr->h_source),
1da177e4
LT		 326 ehdr->h_proto);
327}
328
329static void dump_ehdr_and_myripad(unsigned char *stuff)
330{
331 struct ethhdr *ehdr = (struct ethhdr *) (stuff + 2);
332
333 printk("pad[%02x:%02x]", stuff[0], stuff[1]);
0795af57 334 dump_ehdr(ehdr);
1da177e4
LT		 335}
336#endif
337
338static void myri_tx(struct myri_eth *mp, struct net_device *dev)
339{
340 struct sendq __iomem *sq= mp->sq;
341 int entry = mp->tx_old;
342 int limit = sbus_readl(&sq->head);
343
344 DTX(("entry[%d] limit[%d] ", entry, limit));
345 if (entry == limit)
346 return;
347 while (entry != limit) {
348 struct sk_buff *skb = mp->tx_skbs[entry];
349 u32 dma_addr;
350
351 DTX(("SKB[%d] ", entry));
352 dma_addr = sbus_readl(&sq->myri_txd[entry].myri_gathers[0].addr);
738f2b7b
DM		 353 dma_unmap_single(&mp->myri_sdev->ofdev.dev, dma_addr,
354 skb->len, DMA_TO_DEVICE);
1da177e4
LT		 355 dev_kfree_skb(skb);
356 mp->tx_skbs[entry] = NULL;
09f75cd7 357 dev->stats.tx_packets++;
1da177e4
LT		 358 entry = NEXT_TX(entry);
359 }
360 mp->tx_old = entry;
361}
362
6aa20a22 363/* Determine the packet's protocol ID. The rule here is that we
1da177e4
LT		 364 * assume 802.3 if the type field is short enough to be a length.
365 * This is normal practice and works for any 'now in use' protocol.
366 */
ab611487 367static __be16 myri_type_trans(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 368{
369 struct ethhdr *eth;
370 unsigned char *rawp;
6aa20a22 371
48d49d0c 372 skb_set_mac_header(skb, MYRI_PAD_LEN);
1da177e4
LT		 373 skb_pull(skb, dev->hard_header_len);
374 eth = eth_hdr(skb);
6aa20a22 375
1da177e4
LT		 376#ifdef DEBUG_HEADER
377 DHDR(("myri_type_trans: "));
378 dump_ehdr(eth);
379#endif
380 if (*eth->h_dest & 1) {
381 if (memcmp(eth->h_dest, dev->broadcast, ETH_ALEN)==0)
382 skb->pkt_type = PACKET_BROADCAST;
383 else
384 skb->pkt_type = PACKET_MULTICAST;
385 } else if (dev->flags & (IFF_PROMISC|IFF_ALLMULTI)) {
386 if (memcmp(eth->h_dest, dev->dev_addr, ETH_ALEN))
387 skb->pkt_type = PACKET_OTHERHOST;
388 }
6aa20a22 389
1da177e4
LT		 390 if (ntohs(eth->h_proto) >= 1536)
391 return eth->h_proto;
6aa20a22 392
1da177e4 393 rawp = skb->data;
6aa20a22 394
1da177e4
LT		 395 /* This is a magic hack to spot IPX packets. Older Novell breaks
396 * the protocol design and runs IPX over 802.3 without an 802.2 LLC
397 * layer. We look for FFFF which isn't a used 802.2 SSAP/DSAP. This
398 * won't work for fault tolerant netware but does for the rest.
399 */
400 if (*(unsigned short *)rawp == 0xFFFF)
401 return htons(ETH_P_802_3);
6aa20a22 402
1da177e4
LT		 403 /* Real 802.2 LLC */
404 return htons(ETH_P_802_2);
405}
406
407static void myri_rx(struct myri_eth *mp, struct net_device *dev)
408{
409 struct recvq __iomem *rq = mp->rq;
410 struct recvq __iomem *rqa = mp->rqack;
411 int entry = sbus_readl(&rqa->head);
412 int limit = sbus_readl(&rqa->tail);
413 int drops;
414
415 DRX(("entry[%d] limit[%d] ", entry, limit));
416 if (entry == limit)
417 return;
418 drops = 0;
419 DRX(("\n"));
420 while (entry != limit) {
421 struct myri_rxd __iomem *rxdack = &rqa->myri_rxd[entry];
422 u32 csum = sbus_readl(&rxdack->csum);
423 int len = sbus_readl(&rxdack->myri_scatters[0].len);
424 int index = sbus_readl(&rxdack->ctx);
425 struct myri_rxd __iomem *rxd = &rq->myri_rxd[sbus_readl(&rq->tail)];
426 struct sk_buff *skb = mp->rx_skbs[index];
427
428 /* Ack it. */
429 sbus_writel(NEXT_RX(entry), &rqa->head);
430
431 /* Check for errors. */
432 DRX(("rxd[%d]: %p len[%d] csum[%08x] ", entry, rxd, len, csum));
738f2b7b
DM		 433 dma_sync_single_for_cpu(&mp->myri_sdev->ofdev.dev,
434 sbus_readl(&rxd->myri_scatters[0].addr),
435 RX_ALLOC_SIZE, DMA_FROM_DEVICE);
1da177e4
LT		 436 if (len < (ETH_HLEN + MYRI_PAD_LEN) || (skb->data[0] != MYRI_PAD_LEN)) {
437 DRX(("ERROR["));
09f75cd7 438 dev->stats.rx_errors++;
1da177e4
LT		 439 if (len < (ETH_HLEN + MYRI_PAD_LEN)) {
440 DRX(("BAD_LENGTH] "));
09f75cd7 441 dev->stats.rx_length_errors++;
1da177e4
LT		 442 } else {
443 DRX(("NO_PADDING] "));
09f75cd7 444 dev->stats.rx_frame_errors++;
1da177e4
LT		 445 }
446
447 /* Return it to the LANAI. */
448 drop_it:
449 drops++;
450 DRX(("DROP "));
09f75cd7 451 dev->stats.rx_dropped++;
738f2b7b
DM		 452 dma_sync_single_for_device(&mp->myri_sdev->ofdev.dev,
453 sbus_readl(&rxd->myri_scatters[0].addr),
454 RX_ALLOC_SIZE,
455 DMA_FROM_DEVICE);
1da177e4
LT		 456 sbus_writel(RX_ALLOC_SIZE, &rxd->myri_scatters[0].len);
457 sbus_writel(index, &rxd->ctx);
458 sbus_writel(1, &rxd->num_sg);
459 sbus_writel(NEXT_RX(sbus_readl(&rq->tail)), &rq->tail);
460 goto next;
461 }
462
463 DRX(("len[%d] ", len));
464 if (len > RX_COPY_THRESHOLD) {
465 struct sk_buff *new_skb;
466 u32 dma_addr;
467
468 DRX(("BIGBUFF "));
469 new_skb = myri_alloc_skb(RX_ALLOC_SIZE, GFP_ATOMIC);
470 if (new_skb == NULL) {
471 DRX(("skb_alloc(FAILED) "));
472 goto drop_it;
473 }
738f2b7b
DM		 474 dma_unmap_single(&mp->myri_sdev->ofdev.dev,
475 sbus_readl(&rxd->myri_scatters[0].addr),
476 RX_ALLOC_SIZE,
477 DMA_FROM_DEVICE);
1da177e4
LT		 478 mp->rx_skbs[index] = new_skb;
479 new_skb->dev = dev;
480 skb_put(new_skb, RX_ALLOC_SIZE);
738f2b7b
DM		 481 dma_addr = dma_map_single(&mp->myri_sdev->ofdev.dev,
482 new_skb->data,
483 RX_ALLOC_SIZE,
484 DMA_FROM_DEVICE);
1da177e4
LT		 485 sbus_writel(dma_addr, &rxd->myri_scatters[0].addr);
486 sbus_writel(RX_ALLOC_SIZE, &rxd->myri_scatters[0].len);
487 sbus_writel(index, &rxd->ctx);
488 sbus_writel(1, &rxd->num_sg);
489 sbus_writel(NEXT_RX(sbus_readl(&rq->tail)), &rq->tail);
490
491 /* Trim the original skb for the netif. */
492 DRX(("trim(%d) ", len));
493 skb_trim(skb, len);
494 } else {
495 struct sk_buff *copy_skb = dev_alloc_skb(len);
496
497 DRX(("SMALLBUFF "));
498 if (copy_skb == NULL) {
499 DRX(("dev_alloc_skb(FAILED) "));
500 goto drop_it;
501 }
502 /* DMA sync already done above. */
503 copy_skb->dev = dev;
504 DRX(("resv_and_put "));
505 skb_put(copy_skb, len);
d626f62b 506 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 507
508 /* Reuse original ring buffer. */
509 DRX(("reuse "));
738f2b7b
DM		 510 dma_sync_single_for_device(&mp->myri_sdev->ofdev.dev,
511 sbus_readl(&rxd->myri_scatters[0].addr),
512 RX_ALLOC_SIZE,
513 DMA_FROM_DEVICE);
1da177e4
LT		 514 sbus_writel(RX_ALLOC_SIZE, &rxd->myri_scatters[0].len);
515 sbus_writel(index, &rxd->ctx);
516 sbus_writel(1, &rxd->num_sg);
517 sbus_writel(NEXT_RX(sbus_readl(&rq->tail)), &rq->tail);
518
519 skb = copy_skb;
520 }
521
522 /* Just like the happy meal we get checksums from this card. */
523 skb->csum = csum;
524 skb->ip_summed = CHECKSUM_UNNECESSARY; /* XXX */
525
526 skb->protocol = myri_type_trans(skb, dev);
527 DRX(("prot[%04x] netif_rx ", skb->protocol));
528 netif_rx(skb);
529
530 dev->last_rx = jiffies;
09f75cd7
JG		 531 dev->stats.rx_packets++;
532 dev->stats.rx_bytes += len;
1da177e4
LT		 533 next:
534 DRX(("NEXT\n"));
535 entry = NEXT_RX(entry);
536 }
537}
538
7d12e780 539static irqreturn_t myri_interrupt(int irq, void *dev_id)
1da177e4
LT		 540{
541 struct net_device *dev = (struct net_device *) dev_id;
542 struct myri_eth *mp = (struct myri_eth *) dev->priv;
543 void __iomem *lregs = mp->lregs;
544 struct myri_channel __iomem *chan = &mp->shmem->channel;
545 unsigned long flags;
546 u32 status;
547 int handled = 0;
548
549 spin_lock_irqsave(&mp->irq_lock, flags);
550
551 status = sbus_readl(lregs + LANAI_ISTAT);
552 DIRQ(("myri_interrupt: status[%08x] ", status));
553 if (status & ISTAT_HOST) {
554 u32 softstate;
555
556 handled = 1;
557 DIRQ(("IRQ_DISAB "));
558 myri_disable_irq(lregs, mp->cregs);
559 softstate = sbus_readl(&chan->state);
560 DIRQ(("state[%08x] ", softstate));
561 if (softstate != STATE_READY) {
562 DIRQ(("myri_not_so_happy "));
563 myri_is_not_so_happy(mp);
564 }
565 DIRQ(("\nmyri_rx: "));
566 myri_rx(mp, dev);
567 DIRQ(("\nistat=ISTAT_HOST "));
568 sbus_writel(ISTAT_HOST, lregs + LANAI_ISTAT);
569 DIRQ(("IRQ_ENAB "));
570 myri_enable_irq(lregs, mp->cregs);
571 }
572 DIRQ(("\n"));
573
574 spin_unlock_irqrestore(&mp->irq_lock, flags);
575
576 return IRQ_RETVAL(handled);
577}
578
579static int myri_open(struct net_device *dev)
580{
581 struct myri_eth *mp = (struct myri_eth *) dev->priv;
582
583 return myri_init(mp, in_interrupt());
584}
585
586static int myri_close(struct net_device *dev)
587{
588 struct myri_eth *mp = (struct myri_eth *) dev->priv;
589
590 myri_clean_rings(mp);
591 return 0;
592}
593
594static void myri_tx_timeout(struct net_device *dev)
595{
596 struct myri_eth *mp = (struct myri_eth *) dev->priv;
597
598 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
599
09f75cd7 600 dev->stats.tx_errors++;
1da177e4
LT		 601 myri_init(mp, 0);
602 netif_wake_queue(dev);
603}
604
605static int myri_start_xmit(struct sk_buff *skb, struct net_device *dev)
606{
607 struct myri_eth *mp = (struct myri_eth *) dev->priv;
608 struct sendq __iomem *sq = mp->sq;
609 struct myri_txd __iomem *txd;
610 unsigned long flags;
611 unsigned int head, tail;
612 int len, entry;
613 u32 dma_addr;
614
615 DTX(("myri_start_xmit: "));
616
617 myri_tx(mp, dev);
618
619 netif_stop_queue(dev);
620
621 /* This is just to prevent multiple PIO reads for TX_BUFFS_AVAIL. */
622 head = sbus_readl(&sq->head);
623 tail = sbus_readl(&sq->tail);
624
625 if (!TX_BUFFS_AVAIL(head, tail)) {
626 DTX(("no buffs available, returning 1\n"));
627 return 1;
628 }
629
630 spin_lock_irqsave(&mp->irq_lock, flags);
631
632 DHDR(("xmit[skbdata(%p)]\n", skb->data));
633#ifdef DEBUG_HEADER
634 dump_ehdr_and_myripad(((unsigned char *) skb->data));
635#endif
636
637 /* XXX Maybe this can go as well. */
638 len = skb->len;
639 if (len & 3) {
640 DTX(("len&3 "));
641 len = (len + 4) & (~3);
642 }
643
644 entry = sbus_readl(&sq->tail);
645
646 txd = &sq->myri_txd[entry];
647 mp->tx_skbs[entry] = skb;
648
649 /* Must do this before we sbus map it. */
650 if (skb->data[MYRI_PAD_LEN] & 0x1) {
651 sbus_writew(0xffff, &txd->addr[0]);
652 sbus_writew(0xffff, &txd->addr[1]);
653 sbus_writew(0xffff, &txd->addr[2]);
654 sbus_writew(0xffff, &txd->addr[3]);
655 } else {
656 sbus_writew(0xffff, &txd->addr[0]);
657 sbus_writew((skb->data[0] << 8) | skb->data[1], &txd->addr[1]);
658 sbus_writew((skb->data[2] << 8) | skb->data[3], &txd->addr[2]);
659 sbus_writew((skb->data[4] << 8) | skb->data[5], &txd->addr[3]);
660 }
661
738f2b7b
DM		 662 dma_addr = dma_map_single(&mp->myri_sdev->ofdev.dev, skb->data,
663 len, DMA_TO_DEVICE);
1da177e4
LT		 664 sbus_writel(dma_addr, &txd->myri_gathers[0].addr);
665 sbus_writel(len, &txd->myri_gathers[0].len);
666 sbus_writel(1, &txd->num_sg);
667 sbus_writel(KERNEL_CHANNEL, &txd->chan);
668 sbus_writel(len, &txd->len);
669 sbus_writel((u32)-1, &txd->csum_off);
670 sbus_writel(0, &txd->csum_field);
671
672 sbus_writel(NEXT_TX(entry), &sq->tail);
673 DTX(("BangTheChip "));
674 bang_the_chip(mp);
675
676 DTX(("tbusy=0, returning 0\n"));
677 netif_start_queue(dev);
678 spin_unlock_irqrestore(&mp->irq_lock, flags);
679 return 0;
680}
681
6aa20a22 682/* Create the MyriNet MAC header for an arbitrary protocol layer
1da177e4
LT		 683 *
684 * saddr=NULL means use device source address
685 * daddr=NULL means leave destination address (eg unresolved arp)
686 */
3b04ddde
SH		 687static int myri_header(struct sk_buff *skb, struct net_device *dev,
688 unsigned short type, const void *daddr,
689 const void *saddr, unsigned len)
1da177e4
LT		 690{
691 struct ethhdr *eth = (struct ethhdr *) skb_push(skb, ETH_HLEN);
692 unsigned char *pad = (unsigned char *) skb_push(skb, MYRI_PAD_LEN);
693
694#ifdef DEBUG_HEADER
695 DHDR(("myri_header: pad[%02x,%02x] ", pad[0], pad[1]));
696 dump_ehdr(eth);
697#endif
698
699 /* Set the MyriNET padding identifier. */
700 pad[0] = MYRI_PAD_LEN;
701 pad[1] = 0xab;
702
703 /* Set the protocol type. For a packet of type ETH_P_802_3 we put the length
704 * in here instead. It is up to the 802.2 layer to carry protocol information.
705 */
6aa20a22 706 if (type != ETH_P_802_3)
1da177e4
LT		 707 eth->h_proto = htons(type);
708 else
709 eth->h_proto = htons(len);
710
711 /* Set the source hardware address. */
712 if (saddr)
713 memcpy(eth->h_source, saddr, dev->addr_len);
714 else
715 memcpy(eth->h_source, dev->dev_addr, dev->addr_len);
716
717 /* Anyway, the loopback-device should never use this function... */
718 if (dev->flags & IFF_LOOPBACK) {
719 int i;
720 for (i = 0; i < dev->addr_len; i++)
721 eth->h_dest[i] = 0;
722 return(dev->hard_header_len);
723 }
6aa20a22 724
1da177e4
LT		 725 if (daddr) {
726 memcpy(eth->h_dest, daddr, dev->addr_len);
727 return dev->hard_header_len;
728 }
729 return -dev->hard_header_len;
730}
731
732/* Rebuild the MyriNet MAC header. This is called after an ARP
733 * (or in future other address resolution) has completed on this
734 * sk_buff. We now let ARP fill in the other fields.
735 */
736static int myri_rebuild_header(struct sk_buff *skb)
737{
738 unsigned char *pad = (unsigned char *) skb->data;
739 struct ethhdr *eth = (struct ethhdr *) (pad + MYRI_PAD_LEN);
740 struct net_device *dev = skb->dev;
741
742#ifdef DEBUG_HEADER
743 DHDR(("myri_rebuild_header: pad[%02x,%02x] ", pad[0], pad[1]));
744 dump_ehdr(eth);
745#endif
746
747 /* Refill MyriNet padding identifiers, this is just being anal. */
748 pad[0] = MYRI_PAD_LEN;
749 pad[1] = 0xab;
750
751 switch (eth->h_proto)
752 {
753#ifdef CONFIG_INET
754 case __constant_htons(ETH_P_IP):
755 return arp_find(eth->h_dest, skb);
756#endif
757
758 default:
6aa20a22
JG		 759 printk(KERN_DEBUG
760 "%s: unable to resolve type %X addresses.\n",
1da177e4 761 dev->name, (int)eth->h_proto);
6aa20a22 762
1da177e4
LT		 763 memcpy(eth->h_source, dev->dev_addr, dev->addr_len);
764 return 0;
765 break;
766 }
767
6aa20a22 768 return 0;
1da177e4
LT		 769}
770
3b04ddde 771static int myri_header_cache(const struct neighbour *neigh, struct hh_cache *hh)
1da177e4
LT		 772{
773 unsigned short type = hh->hh_type;
774 unsigned char *pad;
775 struct ethhdr *eth;
3b04ddde 776 const struct net_device *dev = neigh->dev;
1da177e4
LT		 777
778 pad = ((unsigned char *) hh->hh_data) +
779 HH_DATA_OFF(sizeof(*eth) + MYRI_PAD_LEN);
780 eth = (struct ethhdr *) (pad + MYRI_PAD_LEN);
781
3b04ddde 782 if (type == htons(ETH_P_802_3))
1da177e4
LT		 783 return -1;
784
785 /* Refill MyriNet padding identifiers, this is just being anal. */
786 pad[0] = MYRI_PAD_LEN;
787 pad[1] = 0xab;
788
789 eth->h_proto = type;
790 memcpy(eth->h_source, dev->dev_addr, dev->addr_len);
791 memcpy(eth->h_dest, neigh->ha, dev->addr_len);
792 hh->hh_len = 16;
793 return 0;
794}
795
796
797/* Called by Address Resolution module to notify changes in address. */
3b04ddde
SH		 798void myri_header_cache_update(struct hh_cache *hh,
799 const struct net_device *dev,
800 const unsigned char * haddr)
1da177e4
LT		 801{
802 memcpy(((u8*)hh->hh_data) + HH_DATA_OFF(sizeof(struct ethhdr)),
803 haddr, dev->addr_len);
804}
805
806static int myri_change_mtu(struct net_device *dev, int new_mtu)
807{
808 if ((new_mtu < (ETH_HLEN + MYRI_PAD_LEN)) || (new_mtu > MYRINET_MTU))
809 return -EINVAL;
810 dev->mtu = new_mtu;
811 return 0;
812}
813
1da177e4
LT		 814static void myri_set_multicast(struct net_device *dev)
815{
816 /* Do nothing, all MyriCOM nodes transmit multicast frames
817 * as broadcast packets...
818 */
819}
820
821static inline void set_boardid_from_idprom(struct myri_eth *mp, int num)
822{
823 mp->eeprom.id[0] = 0;
824 mp->eeprom.id[1] = idprom->id_machtype;
825 mp->eeprom.id[2] = (idprom->id_sernum >> 16) & 0xff;
826 mp->eeprom.id[3] = (idprom->id_sernum >> 8) & 0xff;
827 mp->eeprom.id[4] = (idprom->id_sernum >> 0) & 0xff;
828 mp->eeprom.id[5] = num;
829}
830
831static inline void determine_reg_space_size(struct myri_eth *mp)
832{
833 switch(mp->eeprom.cpuvers) {
834 case CPUVERS_2_3:
835 case CPUVERS_3_0:
836 case CPUVERS_3_1:
837 case CPUVERS_3_2:
838 mp->reg_size = (3 * 128 * 1024) + 4096;
839 break;
840
841 case CPUVERS_4_0:
842 case CPUVERS_4_1:
843 mp->reg_size = ((4096<<1) + mp->eeprom.ramsz);
844 break;
845
846 case CPUVERS_4_2:
847 case CPUVERS_5_0:
848 default:
849 printk("myricom: AIEEE weird cpu version %04x assuming pre4.0\n",
850 mp->eeprom.cpuvers);
851 mp->reg_size = (3 * 128 * 1024) + 4096;
852 };
853}
854
855#ifdef DEBUG_DETECT
856static void dump_eeprom(struct myri_eth *mp)
857{
858 printk("EEPROM: clockval[%08x] cpuvers[%04x] "
859 "id[%02x,%02x,%02x,%02x,%02x,%02x]\n",
860 mp->eeprom.cval, mp->eeprom.cpuvers,
861 mp->eeprom.id[0], mp->eeprom.id[1], mp->eeprom.id[2],
862 mp->eeprom.id[3], mp->eeprom.id[4], mp->eeprom.id[5]);
863 printk("EEPROM: ramsz[%08x]\n", mp->eeprom.ramsz);
864 printk("EEPROM: fvers[%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n",
865 mp->eeprom.fvers[0], mp->eeprom.fvers[1], mp->eeprom.fvers[2],
866 mp->eeprom.fvers[3], mp->eeprom.fvers[4], mp->eeprom.fvers[5],
867 mp->eeprom.fvers[6], mp->eeprom.fvers[7]);
868 printk("EEPROM: %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n",
869 mp->eeprom.fvers[8], mp->eeprom.fvers[9], mp->eeprom.fvers[10],
870 mp->eeprom.fvers[11], mp->eeprom.fvers[12], mp->eeprom.fvers[13],
871 mp->eeprom.fvers[14], mp->eeprom.fvers[15]);
872 printk("EEPROM: %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n",
873 mp->eeprom.fvers[16], mp->eeprom.fvers[17], mp->eeprom.fvers[18],
874 mp->eeprom.fvers[19], mp->eeprom.fvers[20], mp->eeprom.fvers[21],
875 mp->eeprom.fvers[22], mp->eeprom.fvers[23]);
876 printk("EEPROM: %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x]\n",
877 mp->eeprom.fvers[24], mp->eeprom.fvers[25], mp->eeprom.fvers[26],
878 mp->eeprom.fvers[27], mp->eeprom.fvers[28], mp->eeprom.fvers[29],
879 mp->eeprom.fvers[30], mp->eeprom.fvers[31]);
880 printk("EEPROM: mvers[%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n",
881 mp->eeprom.mvers[0], mp->eeprom.mvers[1], mp->eeprom.mvers[2],
882 mp->eeprom.mvers[3], mp->eeprom.mvers[4], mp->eeprom.mvers[5],
883 mp->eeprom.mvers[6], mp->eeprom.mvers[7]);
884 printk("EEPROM: %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x]\n",
885 mp->eeprom.mvers[8], mp->eeprom.mvers[9], mp->eeprom.mvers[10],
886 mp->eeprom.mvers[11], mp->eeprom.mvers[12], mp->eeprom.mvers[13],
887 mp->eeprom.mvers[14], mp->eeprom.mvers[15]);
888 printk("EEPROM: dlval[%04x] brd_type[%04x] bus_type[%04x] prod_code[%04x]\n",
889 mp->eeprom.dlval, mp->eeprom.brd_type, mp->eeprom.bus_type,
890 mp->eeprom.prod_code);
891 printk("EEPROM: serial_num[%08x]\n", mp->eeprom.serial_num);
892}
893#endif
894
3b04ddde
SH		 895static const struct header_ops myri_header_ops = {
896 .create = myri_header,
897 .rebuild = myri_rebuild_header,
898 .cache = myri_header_cache,
899 .cache_update = myri_header_cache_update,
900};
901
b48194bf 902static int __devinit myri_ether_init(struct sbus_dev *sdev)
1da177e4 903{
a46c30fd 904 static int num;
1da177e4
LT		 905 static unsigned version_printed;
906 struct net_device *dev;
907 struct myri_eth *mp;
908 unsigned char prop_buf[32];
909 int i;
0795af57 910 DECLARE_MAC_BUF(mac);
1da177e4
LT		 911
912 DET(("myri_ether_init(%p,%d):\n", sdev, num));
913 dev = alloc_etherdev(sizeof(struct myri_eth));
914
915 if (!dev)
916 return -ENOMEM;
917
918 if (version_printed++ == 0)
919 printk(version);
920
a46c30fd
DM		 921 SET_NETDEV_DEV(dev, &sdev->ofdev.dev);
922
1da177e4
LT		 923 mp = (struct myri_eth *) dev->priv;
924 spin_lock_init(&mp->irq_lock);
925 mp->myri_sdev = sdev;
926
927 /* Clean out skb arrays. */
928 for (i = 0; i < (RX_RING_SIZE + 1); i++)
929 mp->rx_skbs[i] = NULL;
930
931 for (i = 0; i < TX_RING_SIZE; i++)
932 mp->tx_skbs[i] = NULL;
933
934 /* First check for EEPROM information. */
935 i = prom_getproperty(sdev->prom_node, "myrinet-eeprom-info",
936 (char *)&mp->eeprom, sizeof(struct myri_eeprom));
937 DET(("prom_getprop(myrinet-eeprom-info) returns %d\n", i));
938 if (i == 0 || i == -1) {
939 /* No eeprom property, must cook up the values ourselves. */
940 DET(("No EEPROM: "));
941 mp->eeprom.bus_type = BUS_TYPE_SBUS;
942 mp->eeprom.cpuvers = prom_getintdefault(sdev->prom_node,"cpu_version",0);
943 mp->eeprom.cval = prom_getintdefault(sdev->prom_node,"clock_value",0);
944 mp->eeprom.ramsz = prom_getintdefault(sdev->prom_node,"sram_size",0);
945 DET(("cpuvers[%d] cval[%d] ramsz[%d]\n", mp->eeprom.cpuvers,
946 mp->eeprom.cval, mp->eeprom.ramsz));
947 if (mp->eeprom.cpuvers == 0) {
948 DET(("EEPROM: cpuvers was zero, setting to %04x\n",CPUVERS_2_3));
949 mp->eeprom.cpuvers = CPUVERS_2_3;
950 }
951 if (mp->eeprom.cpuvers < CPUVERS_3_0) {
952 DET(("EEPROM: cpuvers < CPUVERS_3_0, clockval set to zero.\n"));
953 mp->eeprom.cval = 0;
954 }
955 if (mp->eeprom.ramsz == 0) {
956 DET(("EEPROM: ramsz == 0, setting to 128k\n"));
957 mp->eeprom.ramsz = (128 * 1024);
958 }
959 i = prom_getproperty(sdev->prom_node, "myrinet-board-id",
960 &prop_buf[0], 10);
961 DET(("EEPROM: prom_getprop(myrinet-board-id) returns %d\n", i));
962 if ((i != 0) && (i != -1))
963 memcpy(&mp->eeprom.id[0], &prop_buf[0], 6);
964 else
965 set_boardid_from_idprom(mp, num);
966 i = prom_getproperty(sdev->prom_node, "fpga_version",
967 &mp->eeprom.fvers[0], 32);
968 DET(("EEPROM: prom_getprop(fpga_version) returns %d\n", i));
969 if (i == 0 || i == -1)
970 memset(&mp->eeprom.fvers[0], 0, 32);
971
972 if (mp->eeprom.cpuvers == CPUVERS_4_1) {
973 DET(("EEPROM: cpuvers CPUVERS_4_1, "));
974 if (mp->eeprom.ramsz == (128 * 1024)) {
975 DET(("ramsize 128k, setting to 256k, "));
976 mp->eeprom.ramsz = (256 * 1024);
977 }
978 if ((mp->eeprom.cval==0x40414041)||(mp->eeprom.cval==0x90449044)){
979 DET(("changing cval from %08x to %08x ",
980 mp->eeprom.cval, 0x50e450e4));
981 mp->eeprom.cval = 0x50e450e4;
982 }
983 DET(("\n"));
984 }
985 }
986#ifdef DEBUG_DETECT
987 dump_eeprom(mp);
988#endif
989
990 for (i = 0; i < 6; i++)
991 dev->dev_addr[i] = mp->eeprom.id[i];
992
993 determine_reg_space_size(mp);
994
995 /* Map in the MyriCOM register/localram set. */
996 if (mp->eeprom.cpuvers < CPUVERS_4_0) {
997 /* XXX Makes no sense, if control reg is non-existant this
998 * XXX driver cannot function at all... maybe pre-4.0 is
999 * XXX only a valid version for PCI cards? Ask feldy...
1000 */
1001 DET(("Mapping regs for cpuvers < CPUVERS_4_0\n"));
1002 mp->regs = sbus_ioremap(&sdev->resource[0], 0,
1003 mp->reg_size, "MyriCOM Regs");
1004 if (!mp->regs) {
1005 printk("MyriCOM: Cannot map MyriCOM registers.\n");
1006 goto err;
1007 }
1008 mp->lanai = mp->regs + (256 * 1024);
1009 mp->lregs = mp->lanai + (0x10000 * 2);
1010 } else {
1011 DET(("Mapping regs for cpuvers >= CPUVERS_4_0\n"));
1012 mp->cregs = sbus_ioremap(&sdev->resource[0], 0,
1013 PAGE_SIZE, "MyriCOM Control Regs");
1014 mp->lregs = sbus_ioremap(&sdev->resource[0], (256 * 1024),
1015 PAGE_SIZE, "MyriCOM LANAI Regs");
1016 mp->lanai =
1017 sbus_ioremap(&sdev->resource[0], (512 * 1024),
1018 mp->eeprom.ramsz, "MyriCOM SRAM");
1019 }
1020 DET(("Registers mapped: cregs[%p] lregs[%p] lanai[%p]\n",
1021 mp->cregs, mp->lregs, mp->lanai));
1022
1023 if (mp->eeprom.cpuvers >= CPUVERS_4_0)
1024 mp->shmem_base = 0xf000;
1025 else
1026 mp->shmem_base = 0x8000;
1027
1028 DET(("Shared memory base is %04x, ", mp->shmem_base));
1029
1030 mp->shmem = (struct myri_shmem __iomem *)
1031 (mp->lanai + (mp->shmem_base * 2));
1032 DET(("shmem mapped at %p\n", mp->shmem));
1033
1034 mp->rqack = &mp->shmem->channel.recvqa;
1035 mp->rq = &mp->shmem->channel.recvq;
1036 mp->sq = &mp->shmem->channel.sendq;
1037
1038 /* Reset the board. */
1039 DET(("Resetting LANAI\n"));
1040 myri_reset_off(mp->lregs, mp->cregs);
1041 myri_reset_on(mp->cregs);
1042
1043 /* Turn IRQ's off. */
1044 myri_disable_irq(mp->lregs, mp->cregs);
1045
1046 /* Reset once more. */
1047 myri_reset_on(mp->cregs);
1048
1049 /* Get the supported DVMA burst sizes from our SBUS. */
1050 mp->myri_bursts = prom_getintdefault(mp->myri_sdev->bus->prom_node,
1051 "burst-sizes", 0x00);
1052
63237eeb 1053 if (!sbus_can_burst64())
1da177e4
LT		 1054 mp->myri_bursts &= ~(DMA_BURST64);
1055
1056 DET(("MYRI bursts %02x\n", mp->myri_bursts));
1057
1058 /* Encode SBUS interrupt level in second control register. */
1059 i = prom_getint(sdev->prom_node, "interrupts");
1060 if (i == 0)
1061 i = 4;
1062 DET(("prom_getint(interrupts)==%d, irqlvl set to %04x\n",
1063 i, (1 << i)));
1064
1065 sbus_writel((1 << i), mp->cregs + MYRICTRL_IRQLVL);
1066
1067 mp->dev = dev;
1068 dev->open = &myri_open;
1069 dev->stop = &myri_close;
1070 dev->hard_start_xmit = &myri_start_xmit;
1071 dev->tx_timeout = &myri_tx_timeout;
1072 dev->watchdog_timeo = 5*HZ;
1da177e4
LT		 1073 dev->set_multicast_list = &myri_set_multicast;
1074 dev->irq = sdev->irqs[0];
1075
1076 /* Register interrupt handler now. */
1077 DET(("Requesting MYRIcom IRQ line.\n"));
1078 if (request_irq(dev->irq, &myri_interrupt,
1fb9df5d 1079 IRQF_SHARED, "MyriCOM Ethernet", (void *) dev)) {
1da177e4
LT		 1080 printk("MyriCOM: Cannot register interrupt handler.\n");
1081 goto err;
1082 }
1083
1084 dev->mtu = MYRINET_MTU;
1085 dev->change_mtu = myri_change_mtu;
3b04ddde
SH		 1086 dev->header_ops = &myri_header_ops;
1087
1da177e4 1088 dev->hard_header_len = (ETH_HLEN + MYRI_PAD_LEN);
1da177e4
LT		 1089
1090 /* Load code onto the LANai. */
1091 DET(("Loading LANAI firmware\n"));
1092 myri_load_lanai(mp);
1093
1094 if (register_netdev(dev)) {
1095 printk("MyriCOM: Cannot register device.\n");
1096 goto err_free_irq;
1097 }
1098
a46c30fd
DM		 1099 dev_set_drvdata(&sdev->ofdev.dev, mp);
1100
1101 num++;
1da177e4 1102
0795af57
JP		 1103 printk("%s: MyriCOM MyriNET Ethernet %s\n",
1104 dev->name, print_mac(mac, dev->dev_addr));
1da177e4
LT		 1105
1106 return 0;
1107
1108err_free_irq:
1109 free_irq(dev->irq, dev);
1110err:
1111 /* This will also free the co-allocated 'dev->priv' */
1112 free_netdev(dev);
1113 return -ENODEV;
1114}
1115
1da177e4 1116
a46c30fd
DM		 1117static int __devinit myri_sbus_probe(struct of_device *dev, const struct of_device_id *match)
1118{
1119 struct sbus_dev *sdev = to_sbus_device(&dev->dev);
1da177e4 1120
a46c30fd 1121 return myri_ether_init(sdev);
1da177e4
LT		 1122}
1123
a46c30fd 1124static int __devexit myri_sbus_remove(struct of_device *dev)
1da177e4 1125{
a46c30fd
DM		 1126 struct myri_eth *mp = dev_get_drvdata(&dev->dev);
1127 struct net_device *net_dev = mp->dev;
1da177e4 1128
a46c30fd 1129 unregister_netdevice(net_dev);
1da177e4 1130
a46c30fd
DM		 1131 free_irq(net_dev->irq, net_dev);
1132
1133 if (mp->eeprom.cpuvers < CPUVERS_4_0) {
1134 sbus_iounmap(mp->regs, mp->reg_size);
1135 } else {
1136 sbus_iounmap(mp->cregs, PAGE_SIZE);
1137 sbus_iounmap(mp->lregs, (256 * 1024));
1138 sbus_iounmap(mp->lanai, (512 * 1024));
1da177e4 1139 }
a46c30fd
DM		 1140
1141 free_netdev(net_dev);
1142
1143 dev_set_drvdata(&dev->dev, NULL);
1144
1da177e4
LT		 1145 return 0;
1146}
1147
a46c30fd
DM		 1148static struct of_device_id myri_sbus_match[] = {
1149 {
1150 .name = "MYRICOM,mlanai",
1151 },
1152 {
1153 .name = "myri",
1154 },
1155 {},
1156};
1157
1158MODULE_DEVICE_TABLE(of, myri_sbus_match);
1159
1160static struct of_platform_driver myri_sbus_driver = {
1161 .name = "myri",
1162 .match_table = myri_sbus_match,
1163 .probe = myri_sbus_probe,
1164 .remove = __devexit_p(myri_sbus_remove),
1165};
1166
1167static int __init myri_sbus_init(void)
1168{
1169 return of_register_driver(&myri_sbus_driver, &sbus_bus_type);
1170}
1171
1172static void __exit myri_sbus_exit(void)
1da177e4 1173{
a46c30fd 1174 of_unregister_driver(&myri_sbus_driver);
1da177e4
LT		 1175}
1176
a46c30fd
DM		 1177module_init(myri_sbus_init);
1178module_exit(myri_sbus_exit);
1179
1da177e4 1180MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)