Commit | Line | Data |
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1da177e4 | 1 | /* |
9c1bbdfe | 2 | * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports |
1da177e4 LT |
3 | * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> |
4 | * | |
5 | * Based on the 64360 driver from: | |
4547fa61 LB |
6 | * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il> |
7 | * Rabeeh Khoury <rabeeh@marvell.com> | |
1da177e4 LT |
8 | * |
9 | * Copyright (C) 2003 PMC-Sierra, Inc., | |
3bb8a18a | 10 | * written by Manish Lachwani |
1da177e4 LT |
11 | * |
12 | * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> | |
13 | * | |
c8aaea25 | 14 | * Copyright (C) 2004-2006 MontaVista Software, Inc. |
1da177e4 LT |
15 | * Dale Farnsworth <dale@farnsworth.org> |
16 | * | |
17 | * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> | |
18 | * <sjhill@realitydiluted.com> | |
19 | * | |
4547fa61 LB |
20 | * Copyright (C) 2007-2008 Marvell Semiconductor |
21 | * Lennert Buytenhek <buytenh@marvell.com> | |
22 | * | |
1da177e4 LT |
23 | * This program is free software; you can redistribute it and/or |
24 | * modify it under the terms of the GNU General Public License | |
25 | * as published by the Free Software Foundation; either version 2 | |
26 | * of the License, or (at your option) any later version. | |
27 | * | |
28 | * This program is distributed in the hope that it will be useful, | |
29 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
30 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
31 | * GNU General Public License for more details. | |
32 | * | |
33 | * You should have received a copy of the GNU General Public License | |
34 | * along with this program; if not, write to the Free Software | |
35 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
36 | */ | |
a779d38c | 37 | |
1da177e4 LT |
38 | #include <linux/init.h> |
39 | #include <linux/dma-mapping.h> | |
b6298c22 | 40 | #include <linux/in.h> |
c3efab8e | 41 | #include <linux/ip.h> |
1da177e4 LT |
42 | #include <linux/tcp.h> |
43 | #include <linux/udp.h> | |
44 | #include <linux/etherdevice.h> | |
1da177e4 LT |
45 | #include <linux/delay.h> |
46 | #include <linux/ethtool.h> | |
d052d1be | 47 | #include <linux/platform_device.h> |
fbd6a754 LB |
48 | #include <linux/module.h> |
49 | #include <linux/kernel.h> | |
50 | #include <linux/spinlock.h> | |
51 | #include <linux/workqueue.h> | |
ed94493f | 52 | #include <linux/phy.h> |
fbd6a754 | 53 | #include <linux/mv643xx_eth.h> |
10a9948d LB |
54 | #include <linux/io.h> |
55 | #include <linux/types.h> | |
eaf5d590 | 56 | #include <linux/inet_lro.h> |
1da177e4 | 57 | #include <asm/system.h> |
fbd6a754 | 58 | |
e5371493 | 59 | static char mv643xx_eth_driver_name[] = "mv643xx_eth"; |
042af53c | 60 | static char mv643xx_eth_driver_version[] = "1.4"; |
c9df406f | 61 | |
fbd6a754 | 62 | |
fbd6a754 LB |
63 | /* |
64 | * Registers shared between all ports. | |
65 | */ | |
3cb4667c LB |
66 | #define PHY_ADDR 0x0000 |
67 | #define SMI_REG 0x0004 | |
45c5d3bc LB |
68 | #define SMI_BUSY 0x10000000 |
69 | #define SMI_READ_VALID 0x08000000 | |
70 | #define SMI_OPCODE_READ 0x04000000 | |
71 | #define SMI_OPCODE_WRITE 0x00000000 | |
72 | #define ERR_INT_CAUSE 0x0080 | |
73 | #define ERR_INT_SMI_DONE 0x00000010 | |
74 | #define ERR_INT_MASK 0x0084 | |
3cb4667c LB |
75 | #define WINDOW_BASE(w) (0x0200 + ((w) << 3)) |
76 | #define WINDOW_SIZE(w) (0x0204 + ((w) << 3)) | |
77 | #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2)) | |
78 | #define WINDOW_BAR_ENABLE 0x0290 | |
79 | #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4)) | |
fbd6a754 LB |
80 | |
81 | /* | |
37a6084f LB |
82 | * Main per-port registers. These live at offset 0x0400 for |
83 | * port #0, 0x0800 for port #1, and 0x0c00 for port #2. | |
fbd6a754 | 84 | */ |
37a6084f | 85 | #define PORT_CONFIG 0x0000 |
d9a073ea | 86 | #define UNICAST_PROMISCUOUS_MODE 0x00000001 |
37a6084f LB |
87 | #define PORT_CONFIG_EXT 0x0004 |
88 | #define MAC_ADDR_LOW 0x0014 | |
89 | #define MAC_ADDR_HIGH 0x0018 | |
90 | #define SDMA_CONFIG 0x001c | |
becfad97 LB |
91 | #define TX_BURST_SIZE_16_64BIT 0x01000000 |
92 | #define TX_BURST_SIZE_4_64BIT 0x00800000 | |
93 | #define BLM_TX_NO_SWAP 0x00000020 | |
94 | #define BLM_RX_NO_SWAP 0x00000010 | |
95 | #define RX_BURST_SIZE_16_64BIT 0x00000008 | |
96 | #define RX_BURST_SIZE_4_64BIT 0x00000004 | |
37a6084f | 97 | #define PORT_SERIAL_CONTROL 0x003c |
becfad97 LB |
98 | #define SET_MII_SPEED_TO_100 0x01000000 |
99 | #define SET_GMII_SPEED_TO_1000 0x00800000 | |
100 | #define SET_FULL_DUPLEX_MODE 0x00200000 | |
101 | #define MAX_RX_PACKET_9700BYTE 0x000a0000 | |
102 | #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000 | |
103 | #define DO_NOT_FORCE_LINK_FAIL 0x00000400 | |
104 | #define SERIAL_PORT_CONTROL_RESERVED 0x00000200 | |
105 | #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008 | |
106 | #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004 | |
107 | #define FORCE_LINK_PASS 0x00000002 | |
108 | #define SERIAL_PORT_ENABLE 0x00000001 | |
37a6084f | 109 | #define PORT_STATUS 0x0044 |
a2a41689 | 110 | #define TX_FIFO_EMPTY 0x00000400 |
ae9ae064 | 111 | #define TX_IN_PROGRESS 0x00000080 |
2f7eb47a LB |
112 | #define PORT_SPEED_MASK 0x00000030 |
113 | #define PORT_SPEED_1000 0x00000010 | |
114 | #define PORT_SPEED_100 0x00000020 | |
115 | #define PORT_SPEED_10 0x00000000 | |
116 | #define FLOW_CONTROL_ENABLED 0x00000008 | |
117 | #define FULL_DUPLEX 0x00000004 | |
81600eea | 118 | #define LINK_UP 0x00000002 |
37a6084f LB |
119 | #define TXQ_COMMAND 0x0048 |
120 | #define TXQ_FIX_PRIO_CONF 0x004c | |
121 | #define TX_BW_RATE 0x0050 | |
122 | #define TX_BW_MTU 0x0058 | |
123 | #define TX_BW_BURST 0x005c | |
124 | #define INT_CAUSE 0x0060 | |
226bb6b7 | 125 | #define INT_TX_END 0x07f80000 |
befefe21 | 126 | #define INT_RX 0x000003fc |
073a345c | 127 | #define INT_EXT 0x00000002 |
37a6084f | 128 | #define INT_CAUSE_EXT 0x0064 |
befefe21 LB |
129 | #define INT_EXT_LINK_PHY 0x00110000 |
130 | #define INT_EXT_TX 0x000000ff | |
37a6084f LB |
131 | #define INT_MASK 0x0068 |
132 | #define INT_MASK_EXT 0x006c | |
133 | #define TX_FIFO_URGENT_THRESHOLD 0x0074 | |
134 | #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc | |
135 | #define TX_BW_RATE_MOVED 0x00e0 | |
136 | #define TX_BW_MTU_MOVED 0x00e8 | |
137 | #define TX_BW_BURST_MOVED 0x00ec | |
138 | #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4)) | |
139 | #define RXQ_COMMAND 0x0280 | |
140 | #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2)) | |
141 | #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4)) | |
142 | #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4)) | |
143 | #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4)) | |
144 | ||
145 | /* | |
146 | * Misc per-port registers. | |
147 | */ | |
3cb4667c LB |
148 | #define MIB_COUNTERS(p) (0x1000 + ((p) << 7)) |
149 | #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10)) | |
150 | #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10)) | |
151 | #define UNICAST_TABLE(p) (0x1600 + ((p) << 10)) | |
fbd6a754 | 152 | |
2679a550 LB |
153 | |
154 | /* | |
becfad97 | 155 | * SDMA configuration register default value. |
2679a550 | 156 | */ |
fbd6a754 LB |
157 | #if defined(__BIG_ENDIAN) |
158 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
e0c6ef93 LB |
159 | (RX_BURST_SIZE_4_64BIT | \ |
160 | TX_BURST_SIZE_4_64BIT) | |
fbd6a754 LB |
161 | #elif defined(__LITTLE_ENDIAN) |
162 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
e0c6ef93 LB |
163 | (RX_BURST_SIZE_4_64BIT | \ |
164 | BLM_RX_NO_SWAP | \ | |
165 | BLM_TX_NO_SWAP | \ | |
166 | TX_BURST_SIZE_4_64BIT) | |
fbd6a754 LB |
167 | #else |
168 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
169 | #endif | |
170 | ||
2beff77b LB |
171 | |
172 | /* | |
becfad97 | 173 | * Misc definitions. |
2beff77b | 174 | */ |
becfad97 LB |
175 | #define DEFAULT_RX_QUEUE_SIZE 128 |
176 | #define DEFAULT_TX_QUEUE_SIZE 256 | |
fbd6a754 | 177 | |
fbd6a754 | 178 | |
7ca72a3b LB |
179 | /* |
180 | * RX/TX descriptors. | |
fbd6a754 LB |
181 | */ |
182 | #if defined(__BIG_ENDIAN) | |
cc9754b3 | 183 | struct rx_desc { |
fbd6a754 LB |
184 | u16 byte_cnt; /* Descriptor buffer byte count */ |
185 | u16 buf_size; /* Buffer size */ | |
186 | u32 cmd_sts; /* Descriptor command status */ | |
187 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
188 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
189 | }; | |
190 | ||
cc9754b3 | 191 | struct tx_desc { |
fbd6a754 LB |
192 | u16 byte_cnt; /* buffer byte count */ |
193 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
194 | u32 cmd_sts; /* Command/status field */ | |
195 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
196 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
197 | }; | |
198 | #elif defined(__LITTLE_ENDIAN) | |
cc9754b3 | 199 | struct rx_desc { |
fbd6a754 LB |
200 | u32 cmd_sts; /* Descriptor command status */ |
201 | u16 buf_size; /* Buffer size */ | |
202 | u16 byte_cnt; /* Descriptor buffer byte count */ | |
203 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
204 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
205 | }; | |
206 | ||
cc9754b3 | 207 | struct tx_desc { |
fbd6a754 LB |
208 | u32 cmd_sts; /* Command/status field */ |
209 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
210 | u16 byte_cnt; /* buffer byte count */ | |
211 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
212 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
213 | }; | |
214 | #else | |
215 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
216 | #endif | |
217 | ||
7ca72a3b | 218 | /* RX & TX descriptor command */ |
cc9754b3 | 219 | #define BUFFER_OWNED_BY_DMA 0x80000000 |
7ca72a3b LB |
220 | |
221 | /* RX & TX descriptor status */ | |
cc9754b3 | 222 | #define ERROR_SUMMARY 0x00000001 |
7ca72a3b LB |
223 | |
224 | /* RX descriptor status */ | |
cc9754b3 LB |
225 | #define LAYER_4_CHECKSUM_OK 0x40000000 |
226 | #define RX_ENABLE_INTERRUPT 0x20000000 | |
227 | #define RX_FIRST_DESC 0x08000000 | |
228 | #define RX_LAST_DESC 0x04000000 | |
eaf5d590 LB |
229 | #define RX_IP_HDR_OK 0x02000000 |
230 | #define RX_PKT_IS_IPV4 0x01000000 | |
231 | #define RX_PKT_IS_ETHERNETV2 0x00800000 | |
232 | #define RX_PKT_LAYER4_TYPE_MASK 0x00600000 | |
233 | #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000 | |
234 | #define RX_PKT_IS_VLAN_TAGGED 0x00080000 | |
7ca72a3b LB |
235 | |
236 | /* TX descriptor command */ | |
cc9754b3 LB |
237 | #define TX_ENABLE_INTERRUPT 0x00800000 |
238 | #define GEN_CRC 0x00400000 | |
239 | #define TX_FIRST_DESC 0x00200000 | |
240 | #define TX_LAST_DESC 0x00100000 | |
241 | #define ZERO_PADDING 0x00080000 | |
242 | #define GEN_IP_V4_CHECKSUM 0x00040000 | |
243 | #define GEN_TCP_UDP_CHECKSUM 0x00020000 | |
244 | #define UDP_FRAME 0x00010000 | |
e32b6617 LB |
245 | #define MAC_HDR_EXTRA_4_BYTES 0x00008000 |
246 | #define MAC_HDR_EXTRA_8_BYTES 0x00000200 | |
7ca72a3b | 247 | |
cc9754b3 | 248 | #define TX_IHL_SHIFT 11 |
7ca72a3b LB |
249 | |
250 | ||
c9df406f | 251 | /* global *******************************************************************/ |
e5371493 | 252 | struct mv643xx_eth_shared_private { |
fc32b0e2 LB |
253 | /* |
254 | * Ethernet controller base address. | |
255 | */ | |
cc9754b3 | 256 | void __iomem *base; |
c9df406f | 257 | |
fc0eb9f2 LB |
258 | /* |
259 | * Points at the right SMI instance to use. | |
260 | */ | |
261 | struct mv643xx_eth_shared_private *smi; | |
262 | ||
fc32b0e2 | 263 | /* |
ed94493f | 264 | * Provides access to local SMI interface. |
fc32b0e2 | 265 | */ |
298cf9be | 266 | struct mii_bus *smi_bus; |
c9df406f | 267 | |
45c5d3bc LB |
268 | /* |
269 | * If we have access to the error interrupt pin (which is | |
270 | * somewhat misnamed as it not only reflects internal errors | |
271 | * but also reflects SMI completion), use that to wait for | |
272 | * SMI access completion instead of polling the SMI busy bit. | |
273 | */ | |
274 | int err_interrupt; | |
275 | wait_queue_head_t smi_busy_wait; | |
276 | ||
fc32b0e2 LB |
277 | /* |
278 | * Per-port MBUS window access register value. | |
279 | */ | |
c9df406f LB |
280 | u32 win_protect; |
281 | ||
fc32b0e2 LB |
282 | /* |
283 | * Hardware-specific parameters. | |
284 | */ | |
c9df406f | 285 | unsigned int t_clk; |
773fc3ee | 286 | int extended_rx_coal_limit; |
457b1d5a | 287 | int tx_bw_control; |
c9df406f LB |
288 | }; |
289 | ||
457b1d5a LB |
290 | #define TX_BW_CONTROL_ABSENT 0 |
291 | #define TX_BW_CONTROL_OLD_LAYOUT 1 | |
292 | #define TX_BW_CONTROL_NEW_LAYOUT 2 | |
293 | ||
e7d2f4db LB |
294 | static int mv643xx_eth_open(struct net_device *dev); |
295 | static int mv643xx_eth_stop(struct net_device *dev); | |
296 | ||
c9df406f LB |
297 | |
298 | /* per-port *****************************************************************/ | |
e5371493 | 299 | struct mib_counters { |
fbd6a754 LB |
300 | u64 good_octets_received; |
301 | u32 bad_octets_received; | |
302 | u32 internal_mac_transmit_err; | |
303 | u32 good_frames_received; | |
304 | u32 bad_frames_received; | |
305 | u32 broadcast_frames_received; | |
306 | u32 multicast_frames_received; | |
307 | u32 frames_64_octets; | |
308 | u32 frames_65_to_127_octets; | |
309 | u32 frames_128_to_255_octets; | |
310 | u32 frames_256_to_511_octets; | |
311 | u32 frames_512_to_1023_octets; | |
312 | u32 frames_1024_to_max_octets; | |
313 | u64 good_octets_sent; | |
314 | u32 good_frames_sent; | |
315 | u32 excessive_collision; | |
316 | u32 multicast_frames_sent; | |
317 | u32 broadcast_frames_sent; | |
318 | u32 unrec_mac_control_received; | |
319 | u32 fc_sent; | |
320 | u32 good_fc_received; | |
321 | u32 bad_fc_received; | |
322 | u32 undersize_received; | |
323 | u32 fragments_received; | |
324 | u32 oversize_received; | |
325 | u32 jabber_received; | |
326 | u32 mac_receive_error; | |
327 | u32 bad_crc_event; | |
328 | u32 collision; | |
329 | u32 late_collision; | |
330 | }; | |
331 | ||
eaf5d590 LB |
332 | struct lro_counters { |
333 | u32 lro_aggregated; | |
334 | u32 lro_flushed; | |
335 | u32 lro_no_desc; | |
336 | }; | |
337 | ||
8a578111 | 338 | struct rx_queue { |
64da80a2 LB |
339 | int index; |
340 | ||
8a578111 LB |
341 | int rx_ring_size; |
342 | ||
343 | int rx_desc_count; | |
344 | int rx_curr_desc; | |
345 | int rx_used_desc; | |
346 | ||
347 | struct rx_desc *rx_desc_area; | |
348 | dma_addr_t rx_desc_dma; | |
349 | int rx_desc_area_size; | |
350 | struct sk_buff **rx_skb; | |
eaf5d590 | 351 | |
eaf5d590 LB |
352 | struct net_lro_mgr lro_mgr; |
353 | struct net_lro_desc lro_arr[8]; | |
8a578111 LB |
354 | }; |
355 | ||
13d64285 | 356 | struct tx_queue { |
3d6b35bc LB |
357 | int index; |
358 | ||
13d64285 | 359 | int tx_ring_size; |
fbd6a754 | 360 | |
13d64285 LB |
361 | int tx_desc_count; |
362 | int tx_curr_desc; | |
363 | int tx_used_desc; | |
fbd6a754 | 364 | |
5daffe94 | 365 | struct tx_desc *tx_desc_area; |
fbd6a754 LB |
366 | dma_addr_t tx_desc_dma; |
367 | int tx_desc_area_size; | |
99ab08e0 LB |
368 | |
369 | struct sk_buff_head tx_skb; | |
8fd89211 LB |
370 | |
371 | unsigned long tx_packets; | |
372 | unsigned long tx_bytes; | |
373 | unsigned long tx_dropped; | |
13d64285 LB |
374 | }; |
375 | ||
376 | struct mv643xx_eth_private { | |
377 | struct mv643xx_eth_shared_private *shared; | |
37a6084f | 378 | void __iomem *base; |
fc32b0e2 | 379 | int port_num; |
13d64285 | 380 | |
fc32b0e2 | 381 | struct net_device *dev; |
fbd6a754 | 382 | |
ed94493f | 383 | struct phy_device *phy; |
fbd6a754 | 384 | |
4ff3495a LB |
385 | struct timer_list mib_counters_timer; |
386 | spinlock_t mib_counters_lock; | |
fc32b0e2 | 387 | struct mib_counters mib_counters; |
4ff3495a | 388 | |
eaf5d590 LB |
389 | struct lro_counters lro_counters; |
390 | ||
fc32b0e2 | 391 | struct work_struct tx_timeout_task; |
8a578111 | 392 | |
1fa38c58 | 393 | struct napi_struct napi; |
1319ebad | 394 | u8 oom; |
1fa38c58 LB |
395 | u8 work_link; |
396 | u8 work_tx; | |
397 | u8 work_tx_end; | |
398 | u8 work_rx; | |
399 | u8 work_rx_refill; | |
1fa38c58 | 400 | |
2bcb4b0f LB |
401 | int skb_size; |
402 | struct sk_buff_head rx_recycle; | |
403 | ||
8a578111 LB |
404 | /* |
405 | * RX state. | |
406 | */ | |
e7d2f4db | 407 | int rx_ring_size; |
8a578111 LB |
408 | unsigned long rx_desc_sram_addr; |
409 | int rx_desc_sram_size; | |
f7981c1c | 410 | int rxq_count; |
2257e05c | 411 | struct timer_list rx_oom; |
64da80a2 | 412 | struct rx_queue rxq[8]; |
13d64285 LB |
413 | |
414 | /* | |
415 | * TX state. | |
416 | */ | |
e7d2f4db | 417 | int tx_ring_size; |
13d64285 LB |
418 | unsigned long tx_desc_sram_addr; |
419 | int tx_desc_sram_size; | |
f7981c1c | 420 | int txq_count; |
3d6b35bc | 421 | struct tx_queue txq[8]; |
fbd6a754 | 422 | }; |
1da177e4 | 423 | |
fbd6a754 | 424 | |
c9df406f | 425 | /* port register accessors **************************************************/ |
e5371493 | 426 | static inline u32 rdl(struct mv643xx_eth_private *mp, int offset) |
c9df406f | 427 | { |
cc9754b3 | 428 | return readl(mp->shared->base + offset); |
c9df406f | 429 | } |
fbd6a754 | 430 | |
37a6084f LB |
431 | static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset) |
432 | { | |
433 | return readl(mp->base + offset); | |
434 | } | |
435 | ||
e5371493 | 436 | static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data) |
c9df406f | 437 | { |
cc9754b3 | 438 | writel(data, mp->shared->base + offset); |
c9df406f | 439 | } |
fbd6a754 | 440 | |
37a6084f LB |
441 | static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data) |
442 | { | |
443 | writel(data, mp->base + offset); | |
444 | } | |
445 | ||
fbd6a754 | 446 | |
c9df406f | 447 | /* rxq/txq helper functions *************************************************/ |
8a578111 | 448 | static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq) |
c9df406f | 449 | { |
64da80a2 | 450 | return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]); |
c9df406f | 451 | } |
fbd6a754 | 452 | |
13d64285 LB |
453 | static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq) |
454 | { | |
3d6b35bc | 455 | return container_of(txq, struct mv643xx_eth_private, txq[txq->index]); |
13d64285 LB |
456 | } |
457 | ||
8a578111 | 458 | static void rxq_enable(struct rx_queue *rxq) |
c9df406f | 459 | { |
8a578111 | 460 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
37a6084f | 461 | wrlp(mp, RXQ_COMMAND, 1 << rxq->index); |
8a578111 | 462 | } |
1da177e4 | 463 | |
8a578111 LB |
464 | static void rxq_disable(struct rx_queue *rxq) |
465 | { | |
466 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); | |
64da80a2 | 467 | u8 mask = 1 << rxq->index; |
1da177e4 | 468 | |
37a6084f LB |
469 | wrlp(mp, RXQ_COMMAND, mask << 8); |
470 | while (rdlp(mp, RXQ_COMMAND) & mask) | |
8a578111 | 471 | udelay(10); |
c9df406f LB |
472 | } |
473 | ||
6b368f68 LB |
474 | static void txq_reset_hw_ptr(struct tx_queue *txq) |
475 | { | |
476 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
6b368f68 LB |
477 | u32 addr; |
478 | ||
479 | addr = (u32)txq->tx_desc_dma; | |
480 | addr += txq->tx_curr_desc * sizeof(struct tx_desc); | |
37a6084f | 481 | wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr); |
6b368f68 LB |
482 | } |
483 | ||
13d64285 | 484 | static void txq_enable(struct tx_queue *txq) |
1da177e4 | 485 | { |
13d64285 | 486 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
37a6084f | 487 | wrlp(mp, TXQ_COMMAND, 1 << txq->index); |
1da177e4 LT |
488 | } |
489 | ||
13d64285 | 490 | static void txq_disable(struct tx_queue *txq) |
1da177e4 | 491 | { |
13d64285 | 492 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
3d6b35bc | 493 | u8 mask = 1 << txq->index; |
c9df406f | 494 | |
37a6084f LB |
495 | wrlp(mp, TXQ_COMMAND, mask << 8); |
496 | while (rdlp(mp, TXQ_COMMAND) & mask) | |
13d64285 LB |
497 | udelay(10); |
498 | } | |
499 | ||
1fa38c58 | 500 | static void txq_maybe_wake(struct tx_queue *txq) |
13d64285 LB |
501 | { |
502 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
e5ef1de1 | 503 | struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); |
3d6b35bc | 504 | |
8fd89211 LB |
505 | if (netif_tx_queue_stopped(nq)) { |
506 | __netif_tx_lock(nq, smp_processor_id()); | |
507 | if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1) | |
508 | netif_tx_wake_queue(nq); | |
509 | __netif_tx_unlock(nq); | |
510 | } | |
1da177e4 LT |
511 | } |
512 | ||
c9df406f | 513 | |
1fa38c58 | 514 | /* rx napi ******************************************************************/ |
eaf5d590 LB |
515 | static int |
516 | mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph, | |
517 | u64 *hdr_flags, void *priv) | |
518 | { | |
519 | unsigned long cmd_sts = (unsigned long)priv; | |
520 | ||
521 | /* | |
522 | * Make sure that this packet is Ethernet II, is not VLAN | |
523 | * tagged, is IPv4, has a valid IP header, and is TCP. | |
524 | */ | |
525 | if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 | | |
526 | RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK | | |
527 | RX_PKT_IS_VLAN_TAGGED)) != | |
528 | (RX_IP_HDR_OK | RX_PKT_IS_IPV4 | | |
529 | RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4)) | |
530 | return -1; | |
531 | ||
532 | skb_reset_network_header(skb); | |
533 | skb_set_transport_header(skb, ip_hdrlen(skb)); | |
534 | *iphdr = ip_hdr(skb); | |
535 | *tcph = tcp_hdr(skb); | |
536 | *hdr_flags = LRO_IPV4 | LRO_TCP; | |
537 | ||
538 | return 0; | |
539 | } | |
eaf5d590 | 540 | |
8a578111 | 541 | static int rxq_process(struct rx_queue *rxq, int budget) |
1da177e4 | 542 | { |
8a578111 LB |
543 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
544 | struct net_device_stats *stats = &mp->dev->stats; | |
eaf5d590 | 545 | int lro_flush_needed; |
8a578111 | 546 | int rx; |
1da177e4 | 547 | |
eaf5d590 | 548 | lro_flush_needed = 0; |
8a578111 | 549 | rx = 0; |
9e1f3772 | 550 | while (rx < budget && rxq->rx_desc_count) { |
fc32b0e2 | 551 | struct rx_desc *rx_desc; |
96587661 | 552 | unsigned int cmd_sts; |
fc32b0e2 | 553 | struct sk_buff *skb; |
6b8f90c2 | 554 | u16 byte_cnt; |
ff561eef | 555 | |
8a578111 | 556 | rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc]; |
1da177e4 | 557 | |
96587661 | 558 | cmd_sts = rx_desc->cmd_sts; |
2257e05c | 559 | if (cmd_sts & BUFFER_OWNED_BY_DMA) |
96587661 | 560 | break; |
96587661 | 561 | rmb(); |
1da177e4 | 562 | |
8a578111 LB |
563 | skb = rxq->rx_skb[rxq->rx_curr_desc]; |
564 | rxq->rx_skb[rxq->rx_curr_desc] = NULL; | |
ff561eef | 565 | |
9da78745 LB |
566 | rxq->rx_curr_desc++; |
567 | if (rxq->rx_curr_desc == rxq->rx_ring_size) | |
568 | rxq->rx_curr_desc = 0; | |
ff561eef | 569 | |
3a499481 | 570 | dma_unmap_single(NULL, rx_desc->buf_ptr, |
abe78717 | 571 | rx_desc->buf_size, DMA_FROM_DEVICE); |
8a578111 LB |
572 | rxq->rx_desc_count--; |
573 | rx++; | |
b1dd9ca1 | 574 | |
1fa38c58 LB |
575 | mp->work_rx_refill |= 1 << rxq->index; |
576 | ||
6b8f90c2 LB |
577 | byte_cnt = rx_desc->byte_cnt; |
578 | ||
468d09f8 DF |
579 | /* |
580 | * Update statistics. | |
fc32b0e2 LB |
581 | * |
582 | * Note that the descriptor byte count includes 2 dummy | |
583 | * bytes automatically inserted by the hardware at the | |
584 | * start of the packet (which we don't count), and a 4 | |
585 | * byte CRC at the end of the packet (which we do count). | |
468d09f8 | 586 | */ |
1da177e4 | 587 | stats->rx_packets++; |
6b8f90c2 | 588 | stats->rx_bytes += byte_cnt - 2; |
96587661 | 589 | |
1da177e4 | 590 | /* |
fc32b0e2 LB |
591 | * In case we received a packet without first / last bits |
592 | * on, or the error summary bit is set, the packet needs | |
593 | * to be dropped. | |
1da177e4 | 594 | */ |
f61e5547 LB |
595 | if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY)) |
596 | != (RX_FIRST_DESC | RX_LAST_DESC)) | |
597 | goto err; | |
598 | ||
599 | /* | |
600 | * The -4 is for the CRC in the trailer of the | |
601 | * received packet | |
602 | */ | |
603 | skb_put(skb, byte_cnt - 2 - 4); | |
604 | ||
605 | if (cmd_sts & LAYER_4_CHECKSUM_OK) | |
606 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
607 | skb->protocol = eth_type_trans(skb, mp->dev); | |
eaf5d590 | 608 | |
eaf5d590 LB |
609 | if (skb->dev->features & NETIF_F_LRO && |
610 | skb->ip_summed == CHECKSUM_UNNECESSARY) { | |
611 | lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts); | |
612 | lro_flush_needed = 1; | |
613 | } else | |
eaf5d590 | 614 | netif_receive_skb(skb); |
f61e5547 LB |
615 | |
616 | continue; | |
617 | ||
618 | err: | |
619 | stats->rx_dropped++; | |
620 | ||
621 | if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != | |
622 | (RX_FIRST_DESC | RX_LAST_DESC)) { | |
623 | if (net_ratelimit()) | |
624 | dev_printk(KERN_ERR, &mp->dev->dev, | |
625 | "received packet spanning " | |
626 | "multiple descriptors\n"); | |
1da177e4 | 627 | } |
f61e5547 LB |
628 | |
629 | if (cmd_sts & ERROR_SUMMARY) | |
630 | stats->rx_errors++; | |
631 | ||
632 | dev_kfree_skb(skb); | |
1da177e4 | 633 | } |
fc32b0e2 | 634 | |
eaf5d590 LB |
635 | if (lro_flush_needed) |
636 | lro_flush_all(&rxq->lro_mgr); | |
eaf5d590 | 637 | |
1fa38c58 LB |
638 | if (rx < budget) |
639 | mp->work_rx &= ~(1 << rxq->index); | |
640 | ||
8a578111 | 641 | return rx; |
1da177e4 LT |
642 | } |
643 | ||
1fa38c58 | 644 | static int rxq_refill(struct rx_queue *rxq, int budget) |
d0412d96 | 645 | { |
1fa38c58 | 646 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
1fa38c58 | 647 | int refilled; |
8a578111 | 648 | |
1fa38c58 LB |
649 | refilled = 0; |
650 | while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) { | |
651 | struct sk_buff *skb; | |
652 | int unaligned; | |
653 | int rx; | |
53771522 | 654 | struct rx_desc *rx_desc; |
d0412d96 | 655 | |
2bcb4b0f LB |
656 | skb = __skb_dequeue(&mp->rx_recycle); |
657 | if (skb == NULL) | |
658 | skb = dev_alloc_skb(mp->skb_size + | |
659 | dma_get_cache_alignment() - 1); | |
660 | ||
1fa38c58 | 661 | if (skb == NULL) { |
1319ebad | 662 | mp->oom = 1; |
1fa38c58 LB |
663 | goto oom; |
664 | } | |
d0412d96 | 665 | |
1fa38c58 LB |
666 | unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1); |
667 | if (unaligned) | |
668 | skb_reserve(skb, dma_get_cache_alignment() - unaligned); | |
2257e05c | 669 | |
1fa38c58 LB |
670 | refilled++; |
671 | rxq->rx_desc_count++; | |
c9df406f | 672 | |
1fa38c58 LB |
673 | rx = rxq->rx_used_desc++; |
674 | if (rxq->rx_used_desc == rxq->rx_ring_size) | |
675 | rxq->rx_used_desc = 0; | |
2257e05c | 676 | |
53771522 LB |
677 | rx_desc = rxq->rx_desc_area + rx; |
678 | ||
679 | rx_desc->buf_ptr = dma_map_single(NULL, skb->data, | |
680 | mp->skb_size, DMA_FROM_DEVICE); | |
681 | rx_desc->buf_size = mp->skb_size; | |
1fa38c58 LB |
682 | rxq->rx_skb[rx] = skb; |
683 | wmb(); | |
53771522 | 684 | rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT; |
1fa38c58 | 685 | wmb(); |
2257e05c | 686 | |
1fa38c58 LB |
687 | /* |
688 | * The hardware automatically prepends 2 bytes of | |
689 | * dummy data to each received packet, so that the | |
690 | * IP header ends up 16-byte aligned. | |
691 | */ | |
692 | skb_reserve(skb, 2); | |
693 | } | |
694 | ||
695 | if (refilled < budget) | |
696 | mp->work_rx_refill &= ~(1 << rxq->index); | |
697 | ||
698 | oom: | |
699 | return refilled; | |
d0412d96 JC |
700 | } |
701 | ||
c9df406f LB |
702 | |
703 | /* tx ***********************************************************************/ | |
c9df406f | 704 | static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) |
1da177e4 | 705 | { |
13d64285 | 706 | int frag; |
1da177e4 | 707 | |
c9df406f | 708 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { |
13d64285 LB |
709 | skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag]; |
710 | if (fragp->size <= 8 && fragp->page_offset & 7) | |
c9df406f | 711 | return 1; |
1da177e4 | 712 | } |
13d64285 | 713 | |
c9df406f LB |
714 | return 0; |
715 | } | |
7303fde8 | 716 | |
13d64285 | 717 | static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb) |
c9df406f | 718 | { |
13d64285 | 719 | int nr_frags = skb_shinfo(skb)->nr_frags; |
c9df406f | 720 | int frag; |
1da177e4 | 721 | |
13d64285 LB |
722 | for (frag = 0; frag < nr_frags; frag++) { |
723 | skb_frag_t *this_frag; | |
724 | int tx_index; | |
725 | struct tx_desc *desc; | |
726 | ||
727 | this_frag = &skb_shinfo(skb)->frags[frag]; | |
66823b92 LB |
728 | tx_index = txq->tx_curr_desc++; |
729 | if (txq->tx_curr_desc == txq->tx_ring_size) | |
730 | txq->tx_curr_desc = 0; | |
13d64285 LB |
731 | desc = &txq->tx_desc_area[tx_index]; |
732 | ||
733 | /* | |
734 | * The last fragment will generate an interrupt | |
735 | * which will free the skb on TX completion. | |
736 | */ | |
737 | if (frag == nr_frags - 1) { | |
738 | desc->cmd_sts = BUFFER_OWNED_BY_DMA | | |
739 | ZERO_PADDING | TX_LAST_DESC | | |
740 | TX_ENABLE_INTERRUPT; | |
13d64285 LB |
741 | } else { |
742 | desc->cmd_sts = BUFFER_OWNED_BY_DMA; | |
13d64285 LB |
743 | } |
744 | ||
c9df406f LB |
745 | desc->l4i_chk = 0; |
746 | desc->byte_cnt = this_frag->size; | |
747 | desc->buf_ptr = dma_map_page(NULL, this_frag->page, | |
748 | this_frag->page_offset, | |
749 | this_frag->size, | |
750 | DMA_TO_DEVICE); | |
751 | } | |
1da177e4 LT |
752 | } |
753 | ||
c9df406f LB |
754 | static inline __be16 sum16_as_be(__sum16 sum) |
755 | { | |
756 | return (__force __be16)sum; | |
757 | } | |
1da177e4 | 758 | |
4df89bd5 | 759 | static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb) |
1da177e4 | 760 | { |
8fa89bf5 | 761 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
13d64285 | 762 | int nr_frags = skb_shinfo(skb)->nr_frags; |
c9df406f | 763 | int tx_index; |
cc9754b3 | 764 | struct tx_desc *desc; |
c9df406f | 765 | u32 cmd_sts; |
4df89bd5 | 766 | u16 l4i_chk; |
c9df406f | 767 | int length; |
1da177e4 | 768 | |
cc9754b3 | 769 | cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA; |
4df89bd5 | 770 | l4i_chk = 0; |
c9df406f LB |
771 | |
772 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
4df89bd5 | 773 | int tag_bytes; |
e32b6617 LB |
774 | |
775 | BUG_ON(skb->protocol != htons(ETH_P_IP) && | |
776 | skb->protocol != htons(ETH_P_8021Q)); | |
c9df406f | 777 | |
4df89bd5 LB |
778 | tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN; |
779 | if (unlikely(tag_bytes & ~12)) { | |
780 | if (skb_checksum_help(skb) == 0) | |
781 | goto no_csum; | |
782 | kfree_skb(skb); | |
783 | return 1; | |
784 | } | |
c9df406f | 785 | |
4df89bd5 | 786 | if (tag_bytes & 4) |
e32b6617 | 787 | cmd_sts |= MAC_HDR_EXTRA_4_BYTES; |
4df89bd5 | 788 | if (tag_bytes & 8) |
e32b6617 | 789 | cmd_sts |= MAC_HDR_EXTRA_8_BYTES; |
4df89bd5 LB |
790 | |
791 | cmd_sts |= GEN_TCP_UDP_CHECKSUM | | |
792 | GEN_IP_V4_CHECKSUM | | |
793 | ip_hdr(skb)->ihl << TX_IHL_SHIFT; | |
e32b6617 | 794 | |
c9df406f LB |
795 | switch (ip_hdr(skb)->protocol) { |
796 | case IPPROTO_UDP: | |
cc9754b3 | 797 | cmd_sts |= UDP_FRAME; |
4df89bd5 | 798 | l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check)); |
c9df406f LB |
799 | break; |
800 | case IPPROTO_TCP: | |
4df89bd5 | 801 | l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check)); |
c9df406f LB |
802 | break; |
803 | default: | |
804 | BUG(); | |
805 | } | |
806 | } else { | |
4df89bd5 | 807 | no_csum: |
c9df406f | 808 | /* Errata BTS #50, IHL must be 5 if no HW checksum */ |
cc9754b3 | 809 | cmd_sts |= 5 << TX_IHL_SHIFT; |
c9df406f LB |
810 | } |
811 | ||
66823b92 LB |
812 | tx_index = txq->tx_curr_desc++; |
813 | if (txq->tx_curr_desc == txq->tx_ring_size) | |
814 | txq->tx_curr_desc = 0; | |
4df89bd5 LB |
815 | desc = &txq->tx_desc_area[tx_index]; |
816 | ||
817 | if (nr_frags) { | |
818 | txq_submit_frag_skb(txq, skb); | |
819 | length = skb_headlen(skb); | |
820 | } else { | |
821 | cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT; | |
822 | length = skb->len; | |
823 | } | |
824 | ||
825 | desc->l4i_chk = l4i_chk; | |
826 | desc->byte_cnt = length; | |
827 | desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); | |
828 | ||
99ab08e0 LB |
829 | __skb_queue_tail(&txq->tx_skb, skb); |
830 | ||
c9df406f LB |
831 | /* ensure all other descriptors are written before first cmd_sts */ |
832 | wmb(); | |
833 | desc->cmd_sts = cmd_sts; | |
834 | ||
1fa38c58 LB |
835 | /* clear TX_END status */ |
836 | mp->work_tx_end &= ~(1 << txq->index); | |
8fa89bf5 | 837 | |
c9df406f LB |
838 | /* ensure all descriptors are written before poking hardware */ |
839 | wmb(); | |
13d64285 | 840 | txq_enable(txq); |
c9df406f | 841 | |
13d64285 | 842 | txq->tx_desc_count += nr_frags + 1; |
4df89bd5 LB |
843 | |
844 | return 0; | |
1da177e4 | 845 | } |
1da177e4 | 846 | |
fc32b0e2 | 847 | static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 848 | { |
e5371493 | 849 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
e5ef1de1 | 850 | int queue; |
13d64285 | 851 | struct tx_queue *txq; |
e5ef1de1 | 852 | struct netdev_queue *nq; |
afdb57a2 | 853 | |
8fd89211 LB |
854 | queue = skb_get_queue_mapping(skb); |
855 | txq = mp->txq + queue; | |
856 | nq = netdev_get_tx_queue(dev, queue); | |
857 | ||
c9df406f | 858 | if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { |
8fd89211 | 859 | txq->tx_dropped++; |
fc32b0e2 LB |
860 | dev_printk(KERN_DEBUG, &dev->dev, |
861 | "failed to linearize skb with tiny " | |
862 | "unaligned fragment\n"); | |
c9df406f LB |
863 | return NETDEV_TX_BUSY; |
864 | } | |
865 | ||
17cd0a59 | 866 | if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) { |
e5ef1de1 LB |
867 | if (net_ratelimit()) |
868 | dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n"); | |
3d6b35bc LB |
869 | kfree_skb(skb); |
870 | return NETDEV_TX_OK; | |
c9df406f LB |
871 | } |
872 | ||
4df89bd5 LB |
873 | if (!txq_submit_skb(txq, skb)) { |
874 | int entries_left; | |
875 | ||
876 | txq->tx_bytes += skb->len; | |
877 | txq->tx_packets++; | |
878 | dev->trans_start = jiffies; | |
c9df406f | 879 | |
4df89bd5 LB |
880 | entries_left = txq->tx_ring_size - txq->tx_desc_count; |
881 | if (entries_left < MAX_SKB_FRAGS + 1) | |
882 | netif_tx_stop_queue(nq); | |
883 | } | |
c9df406f | 884 | |
c9df406f | 885 | return NETDEV_TX_OK; |
1da177e4 LT |
886 | } |
887 | ||
c9df406f | 888 | |
1fa38c58 LB |
889 | /* tx napi ******************************************************************/ |
890 | static void txq_kick(struct tx_queue *txq) | |
891 | { | |
892 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
8fd89211 | 893 | struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); |
1fa38c58 LB |
894 | u32 hw_desc_ptr; |
895 | u32 expected_ptr; | |
896 | ||
8fd89211 | 897 | __netif_tx_lock(nq, smp_processor_id()); |
1fa38c58 | 898 | |
37a6084f | 899 | if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index)) |
1fa38c58 LB |
900 | goto out; |
901 | ||
37a6084f | 902 | hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index)); |
1fa38c58 LB |
903 | expected_ptr = (u32)txq->tx_desc_dma + |
904 | txq->tx_curr_desc * sizeof(struct tx_desc); | |
905 | ||
906 | if (hw_desc_ptr != expected_ptr) | |
907 | txq_enable(txq); | |
908 | ||
909 | out: | |
8fd89211 | 910 | __netif_tx_unlock(nq); |
1fa38c58 LB |
911 | |
912 | mp->work_tx_end &= ~(1 << txq->index); | |
913 | } | |
914 | ||
915 | static int txq_reclaim(struct tx_queue *txq, int budget, int force) | |
916 | { | |
917 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
8fd89211 | 918 | struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); |
1fa38c58 LB |
919 | int reclaimed; |
920 | ||
8fd89211 | 921 | __netif_tx_lock(nq, smp_processor_id()); |
1fa38c58 LB |
922 | |
923 | reclaimed = 0; | |
924 | while (reclaimed < budget && txq->tx_desc_count > 0) { | |
925 | int tx_index; | |
926 | struct tx_desc *desc; | |
927 | u32 cmd_sts; | |
928 | struct sk_buff *skb; | |
1fa38c58 LB |
929 | |
930 | tx_index = txq->tx_used_desc; | |
931 | desc = &txq->tx_desc_area[tx_index]; | |
932 | cmd_sts = desc->cmd_sts; | |
933 | ||
934 | if (cmd_sts & BUFFER_OWNED_BY_DMA) { | |
935 | if (!force) | |
936 | break; | |
937 | desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA; | |
938 | } | |
939 | ||
940 | txq->tx_used_desc = tx_index + 1; | |
941 | if (txq->tx_used_desc == txq->tx_ring_size) | |
942 | txq->tx_used_desc = 0; | |
943 | ||
944 | reclaimed++; | |
945 | txq->tx_desc_count--; | |
946 | ||
99ab08e0 LB |
947 | skb = NULL; |
948 | if (cmd_sts & TX_LAST_DESC) | |
949 | skb = __skb_dequeue(&txq->tx_skb); | |
1fa38c58 LB |
950 | |
951 | if (cmd_sts & ERROR_SUMMARY) { | |
952 | dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n"); | |
953 | mp->dev->stats.tx_errors++; | |
954 | } | |
955 | ||
a418950c LB |
956 | if (cmd_sts & TX_FIRST_DESC) { |
957 | dma_unmap_single(NULL, desc->buf_ptr, | |
958 | desc->byte_cnt, DMA_TO_DEVICE); | |
959 | } else { | |
960 | dma_unmap_page(NULL, desc->buf_ptr, | |
961 | desc->byte_cnt, DMA_TO_DEVICE); | |
962 | } | |
1fa38c58 | 963 | |
2bcb4b0f LB |
964 | if (skb != NULL) { |
965 | if (skb_queue_len(&mp->rx_recycle) < | |
e7d2f4db | 966 | mp->rx_ring_size && |
11b4aa03 LB |
967 | skb_recycle_check(skb, mp->skb_size + |
968 | dma_get_cache_alignment() - 1)) | |
2bcb4b0f LB |
969 | __skb_queue_head(&mp->rx_recycle, skb); |
970 | else | |
971 | dev_kfree_skb(skb); | |
972 | } | |
1fa38c58 LB |
973 | } |
974 | ||
8fd89211 LB |
975 | __netif_tx_unlock(nq); |
976 | ||
1fa38c58 LB |
977 | if (reclaimed < budget) |
978 | mp->work_tx &= ~(1 << txq->index); | |
979 | ||
1fa38c58 LB |
980 | return reclaimed; |
981 | } | |
982 | ||
983 | ||
89df5fdc LB |
984 | /* tx rate control **********************************************************/ |
985 | /* | |
986 | * Set total maximum TX rate (shared by all TX queues for this port) | |
987 | * to 'rate' bits per second, with a maximum burst of 'burst' bytes. | |
988 | */ | |
989 | static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst) | |
990 | { | |
991 | int token_rate; | |
992 | int mtu; | |
993 | int bucket_size; | |
994 | ||
995 | token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000); | |
996 | if (token_rate > 1023) | |
997 | token_rate = 1023; | |
998 | ||
999 | mtu = (mp->dev->mtu + 255) >> 8; | |
1000 | if (mtu > 63) | |
1001 | mtu = 63; | |
1002 | ||
1003 | bucket_size = (burst + 255) >> 8; | |
1004 | if (bucket_size > 65535) | |
1005 | bucket_size = 65535; | |
1006 | ||
457b1d5a LB |
1007 | switch (mp->shared->tx_bw_control) { |
1008 | case TX_BW_CONTROL_OLD_LAYOUT: | |
37a6084f LB |
1009 | wrlp(mp, TX_BW_RATE, token_rate); |
1010 | wrlp(mp, TX_BW_MTU, mtu); | |
1011 | wrlp(mp, TX_BW_BURST, bucket_size); | |
457b1d5a LB |
1012 | break; |
1013 | case TX_BW_CONTROL_NEW_LAYOUT: | |
37a6084f LB |
1014 | wrlp(mp, TX_BW_RATE_MOVED, token_rate); |
1015 | wrlp(mp, TX_BW_MTU_MOVED, mtu); | |
1016 | wrlp(mp, TX_BW_BURST_MOVED, bucket_size); | |
457b1d5a | 1017 | break; |
1e881592 | 1018 | } |
89df5fdc LB |
1019 | } |
1020 | ||
1021 | static void txq_set_rate(struct tx_queue *txq, int rate, int burst) | |
1022 | { | |
1023 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
1024 | int token_rate; | |
1025 | int bucket_size; | |
1026 | ||
1027 | token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000); | |
1028 | if (token_rate > 1023) | |
1029 | token_rate = 1023; | |
1030 | ||
1031 | bucket_size = (burst + 255) >> 8; | |
1032 | if (bucket_size > 65535) | |
1033 | bucket_size = 65535; | |
1034 | ||
37a6084f LB |
1035 | wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14); |
1036 | wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate); | |
89df5fdc LB |
1037 | } |
1038 | ||
1039 | static void txq_set_fixed_prio_mode(struct tx_queue *txq) | |
1040 | { | |
1041 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
1042 | int off; | |
1043 | u32 val; | |
1044 | ||
1045 | /* | |
1046 | * Turn on fixed priority mode. | |
1047 | */ | |
457b1d5a LB |
1048 | off = 0; |
1049 | switch (mp->shared->tx_bw_control) { | |
1050 | case TX_BW_CONTROL_OLD_LAYOUT: | |
37a6084f | 1051 | off = TXQ_FIX_PRIO_CONF; |
457b1d5a LB |
1052 | break; |
1053 | case TX_BW_CONTROL_NEW_LAYOUT: | |
37a6084f | 1054 | off = TXQ_FIX_PRIO_CONF_MOVED; |
457b1d5a LB |
1055 | break; |
1056 | } | |
89df5fdc | 1057 | |
457b1d5a | 1058 | if (off) { |
37a6084f | 1059 | val = rdlp(mp, off); |
457b1d5a | 1060 | val |= 1 << txq->index; |
37a6084f | 1061 | wrlp(mp, off, val); |
457b1d5a | 1062 | } |
89df5fdc LB |
1063 | } |
1064 | ||
1065 | static void txq_set_wrr(struct tx_queue *txq, int weight) | |
1066 | { | |
1067 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
1068 | int off; | |
1069 | u32 val; | |
1070 | ||
1071 | /* | |
1072 | * Turn off fixed priority mode. | |
1073 | */ | |
457b1d5a LB |
1074 | off = 0; |
1075 | switch (mp->shared->tx_bw_control) { | |
1076 | case TX_BW_CONTROL_OLD_LAYOUT: | |
37a6084f | 1077 | off = TXQ_FIX_PRIO_CONF; |
457b1d5a LB |
1078 | break; |
1079 | case TX_BW_CONTROL_NEW_LAYOUT: | |
37a6084f | 1080 | off = TXQ_FIX_PRIO_CONF_MOVED; |
457b1d5a LB |
1081 | break; |
1082 | } | |
89df5fdc | 1083 | |
457b1d5a | 1084 | if (off) { |
37a6084f | 1085 | val = rdlp(mp, off); |
457b1d5a | 1086 | val &= ~(1 << txq->index); |
37a6084f | 1087 | wrlp(mp, off, val); |
89df5fdc | 1088 | |
457b1d5a LB |
1089 | /* |
1090 | * Configure WRR weight for this queue. | |
1091 | */ | |
89df5fdc | 1092 | |
37a6084f | 1093 | val = rdlp(mp, off); |
457b1d5a | 1094 | val = (val & ~0xff) | (weight & 0xff); |
37a6084f | 1095 | wrlp(mp, TXQ_BW_WRR_CONF(txq->index), val); |
457b1d5a | 1096 | } |
89df5fdc LB |
1097 | } |
1098 | ||
1099 | ||
c9df406f | 1100 | /* mii management interface *************************************************/ |
45c5d3bc LB |
1101 | static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id) |
1102 | { | |
1103 | struct mv643xx_eth_shared_private *msp = dev_id; | |
1104 | ||
1105 | if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) { | |
1106 | writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE); | |
1107 | wake_up(&msp->smi_busy_wait); | |
1108 | return IRQ_HANDLED; | |
1109 | } | |
1110 | ||
1111 | return IRQ_NONE; | |
1112 | } | |
c9df406f | 1113 | |
45c5d3bc | 1114 | static int smi_is_done(struct mv643xx_eth_shared_private *msp) |
1da177e4 | 1115 | { |
45c5d3bc LB |
1116 | return !(readl(msp->base + SMI_REG) & SMI_BUSY); |
1117 | } | |
1da177e4 | 1118 | |
45c5d3bc LB |
1119 | static int smi_wait_ready(struct mv643xx_eth_shared_private *msp) |
1120 | { | |
1121 | if (msp->err_interrupt == NO_IRQ) { | |
1122 | int i; | |
c9df406f | 1123 | |
45c5d3bc LB |
1124 | for (i = 0; !smi_is_done(msp); i++) { |
1125 | if (i == 10) | |
1126 | return -ETIMEDOUT; | |
1127 | msleep(10); | |
c9df406f | 1128 | } |
45c5d3bc LB |
1129 | |
1130 | return 0; | |
1131 | } | |
1132 | ||
ee04448d LB |
1133 | if (!smi_is_done(msp)) { |
1134 | wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp), | |
1135 | msecs_to_jiffies(100)); | |
1136 | if (!smi_is_done(msp)) | |
1137 | return -ETIMEDOUT; | |
1138 | } | |
45c5d3bc LB |
1139 | |
1140 | return 0; | |
1141 | } | |
1142 | ||
ed94493f | 1143 | static int smi_bus_read(struct mii_bus *bus, int addr, int reg) |
45c5d3bc | 1144 | { |
ed94493f | 1145 | struct mv643xx_eth_shared_private *msp = bus->priv; |
45c5d3bc LB |
1146 | void __iomem *smi_reg = msp->base + SMI_REG; |
1147 | int ret; | |
1148 | ||
45c5d3bc | 1149 | if (smi_wait_ready(msp)) { |
10a9948d | 1150 | printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n"); |
ed94493f | 1151 | return -ETIMEDOUT; |
1da177e4 LT |
1152 | } |
1153 | ||
fc32b0e2 | 1154 | writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg); |
1da177e4 | 1155 | |
45c5d3bc | 1156 | if (smi_wait_ready(msp)) { |
10a9948d | 1157 | printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n"); |
ed94493f | 1158 | return -ETIMEDOUT; |
45c5d3bc LB |
1159 | } |
1160 | ||
1161 | ret = readl(smi_reg); | |
1162 | if (!(ret & SMI_READ_VALID)) { | |
10a9948d | 1163 | printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n"); |
ed94493f | 1164 | return -ENODEV; |
c9df406f LB |
1165 | } |
1166 | ||
ed94493f | 1167 | return ret & 0xffff; |
1da177e4 LT |
1168 | } |
1169 | ||
ed94493f | 1170 | static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val) |
1da177e4 | 1171 | { |
ed94493f | 1172 | struct mv643xx_eth_shared_private *msp = bus->priv; |
45c5d3bc | 1173 | void __iomem *smi_reg = msp->base + SMI_REG; |
1da177e4 | 1174 | |
45c5d3bc | 1175 | if (smi_wait_ready(msp)) { |
10a9948d | 1176 | printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n"); |
45c5d3bc | 1177 | return -ETIMEDOUT; |
1da177e4 LT |
1178 | } |
1179 | ||
fc32b0e2 | 1180 | writel(SMI_OPCODE_WRITE | (reg << 21) | |
ed94493f | 1181 | (addr << 16) | (val & 0xffff), smi_reg); |
45c5d3bc | 1182 | |
ed94493f | 1183 | if (smi_wait_ready(msp)) { |
10a9948d | 1184 | printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n"); |
ed94493f LB |
1185 | return -ETIMEDOUT; |
1186 | } | |
45c5d3bc LB |
1187 | |
1188 | return 0; | |
c9df406f | 1189 | } |
1da177e4 | 1190 | |
c9df406f | 1191 | |
8fd89211 LB |
1192 | /* statistics ***************************************************************/ |
1193 | static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev) | |
1194 | { | |
1195 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1196 | struct net_device_stats *stats = &dev->stats; | |
1197 | unsigned long tx_packets = 0; | |
1198 | unsigned long tx_bytes = 0; | |
1199 | unsigned long tx_dropped = 0; | |
1200 | int i; | |
1201 | ||
1202 | for (i = 0; i < mp->txq_count; i++) { | |
1203 | struct tx_queue *txq = mp->txq + i; | |
1204 | ||
1205 | tx_packets += txq->tx_packets; | |
1206 | tx_bytes += txq->tx_bytes; | |
1207 | tx_dropped += txq->tx_dropped; | |
1208 | } | |
1209 | ||
1210 | stats->tx_packets = tx_packets; | |
1211 | stats->tx_bytes = tx_bytes; | |
1212 | stats->tx_dropped = tx_dropped; | |
1213 | ||
1214 | return stats; | |
1215 | } | |
1216 | ||
eaf5d590 LB |
1217 | static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp) |
1218 | { | |
1219 | u32 lro_aggregated = 0; | |
1220 | u32 lro_flushed = 0; | |
1221 | u32 lro_no_desc = 0; | |
1222 | int i; | |
1223 | ||
eaf5d590 LB |
1224 | for (i = 0; i < mp->rxq_count; i++) { |
1225 | struct rx_queue *rxq = mp->rxq + i; | |
1226 | ||
1227 | lro_aggregated += rxq->lro_mgr.stats.aggregated; | |
1228 | lro_flushed += rxq->lro_mgr.stats.flushed; | |
1229 | lro_no_desc += rxq->lro_mgr.stats.no_desc; | |
1230 | } | |
eaf5d590 LB |
1231 | |
1232 | mp->lro_counters.lro_aggregated = lro_aggregated; | |
1233 | mp->lro_counters.lro_flushed = lro_flushed; | |
1234 | mp->lro_counters.lro_no_desc = lro_no_desc; | |
1235 | } | |
1236 | ||
fc32b0e2 | 1237 | static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset) |
c9df406f | 1238 | { |
fc32b0e2 | 1239 | return rdl(mp, MIB_COUNTERS(mp->port_num) + offset); |
1da177e4 LT |
1240 | } |
1241 | ||
fc32b0e2 | 1242 | static void mib_counters_clear(struct mv643xx_eth_private *mp) |
d0412d96 | 1243 | { |
fc32b0e2 LB |
1244 | int i; |
1245 | ||
1246 | for (i = 0; i < 0x80; i += 4) | |
1247 | mib_read(mp, i); | |
c9df406f | 1248 | } |
d0412d96 | 1249 | |
fc32b0e2 | 1250 | static void mib_counters_update(struct mv643xx_eth_private *mp) |
c9df406f | 1251 | { |
e5371493 | 1252 | struct mib_counters *p = &mp->mib_counters; |
4b8e3655 | 1253 | |
57e8f26a | 1254 | spin_lock_bh(&mp->mib_counters_lock); |
fc32b0e2 | 1255 | p->good_octets_received += mib_read(mp, 0x00); |
fc32b0e2 LB |
1256 | p->bad_octets_received += mib_read(mp, 0x08); |
1257 | p->internal_mac_transmit_err += mib_read(mp, 0x0c); | |
1258 | p->good_frames_received += mib_read(mp, 0x10); | |
1259 | p->bad_frames_received += mib_read(mp, 0x14); | |
1260 | p->broadcast_frames_received += mib_read(mp, 0x18); | |
1261 | p->multicast_frames_received += mib_read(mp, 0x1c); | |
1262 | p->frames_64_octets += mib_read(mp, 0x20); | |
1263 | p->frames_65_to_127_octets += mib_read(mp, 0x24); | |
1264 | p->frames_128_to_255_octets += mib_read(mp, 0x28); | |
1265 | p->frames_256_to_511_octets += mib_read(mp, 0x2c); | |
1266 | p->frames_512_to_1023_octets += mib_read(mp, 0x30); | |
1267 | p->frames_1024_to_max_octets += mib_read(mp, 0x34); | |
1268 | p->good_octets_sent += mib_read(mp, 0x38); | |
fc32b0e2 LB |
1269 | p->good_frames_sent += mib_read(mp, 0x40); |
1270 | p->excessive_collision += mib_read(mp, 0x44); | |
1271 | p->multicast_frames_sent += mib_read(mp, 0x48); | |
1272 | p->broadcast_frames_sent += mib_read(mp, 0x4c); | |
1273 | p->unrec_mac_control_received += mib_read(mp, 0x50); | |
1274 | p->fc_sent += mib_read(mp, 0x54); | |
1275 | p->good_fc_received += mib_read(mp, 0x58); | |
1276 | p->bad_fc_received += mib_read(mp, 0x5c); | |
1277 | p->undersize_received += mib_read(mp, 0x60); | |
1278 | p->fragments_received += mib_read(mp, 0x64); | |
1279 | p->oversize_received += mib_read(mp, 0x68); | |
1280 | p->jabber_received += mib_read(mp, 0x6c); | |
1281 | p->mac_receive_error += mib_read(mp, 0x70); | |
1282 | p->bad_crc_event += mib_read(mp, 0x74); | |
1283 | p->collision += mib_read(mp, 0x78); | |
1284 | p->late_collision += mib_read(mp, 0x7c); | |
57e8f26a | 1285 | spin_unlock_bh(&mp->mib_counters_lock); |
4ff3495a LB |
1286 | |
1287 | mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ); | |
1288 | } | |
1289 | ||
1290 | static void mib_counters_timer_wrapper(unsigned long _mp) | |
1291 | { | |
1292 | struct mv643xx_eth_private *mp = (void *)_mp; | |
1293 | ||
1294 | mib_counters_update(mp); | |
d0412d96 JC |
1295 | } |
1296 | ||
c9df406f | 1297 | |
3e508034 LB |
1298 | /* interrupt coalescing *****************************************************/ |
1299 | /* | |
1300 | * Hardware coalescing parameters are set in units of 64 t_clk | |
1301 | * cycles. I.e.: | |
1302 | * | |
1303 | * coal_delay_in_usec = 64000000 * register_value / t_clk_rate | |
1304 | * | |
1305 | * register_value = coal_delay_in_usec * t_clk_rate / 64000000 | |
1306 | * | |
1307 | * In the ->set*() methods, we round the computed register value | |
1308 | * to the nearest integer. | |
1309 | */ | |
1310 | static unsigned int get_rx_coal(struct mv643xx_eth_private *mp) | |
1311 | { | |
1312 | u32 val = rdlp(mp, SDMA_CONFIG); | |
1313 | u64 temp; | |
1314 | ||
1315 | if (mp->shared->extended_rx_coal_limit) | |
1316 | temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7); | |
1317 | else | |
1318 | temp = (val & 0x003fff00) >> 8; | |
1319 | ||
1320 | temp *= 64000000; | |
1321 | do_div(temp, mp->shared->t_clk); | |
1322 | ||
1323 | return (unsigned int)temp; | |
1324 | } | |
1325 | ||
1326 | static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec) | |
1327 | { | |
1328 | u64 temp; | |
1329 | u32 val; | |
1330 | ||
1331 | temp = (u64)usec * mp->shared->t_clk; | |
1332 | temp += 31999999; | |
1333 | do_div(temp, 64000000); | |
1334 | ||
1335 | val = rdlp(mp, SDMA_CONFIG); | |
1336 | if (mp->shared->extended_rx_coal_limit) { | |
1337 | if (temp > 0xffff) | |
1338 | temp = 0xffff; | |
1339 | val &= ~0x023fff80; | |
1340 | val |= (temp & 0x8000) << 10; | |
1341 | val |= (temp & 0x7fff) << 7; | |
1342 | } else { | |
1343 | if (temp > 0x3fff) | |
1344 | temp = 0x3fff; | |
1345 | val &= ~0x003fff00; | |
1346 | val |= (temp & 0x3fff) << 8; | |
1347 | } | |
1348 | wrlp(mp, SDMA_CONFIG, val); | |
1349 | } | |
1350 | ||
1351 | static unsigned int get_tx_coal(struct mv643xx_eth_private *mp) | |
1352 | { | |
1353 | u64 temp; | |
1354 | ||
1355 | temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4; | |
1356 | temp *= 64000000; | |
1357 | do_div(temp, mp->shared->t_clk); | |
1358 | ||
1359 | return (unsigned int)temp; | |
1360 | } | |
1361 | ||
1362 | static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec) | |
1363 | { | |
1364 | u64 temp; | |
1365 | ||
1366 | temp = (u64)usec * mp->shared->t_clk; | |
1367 | temp += 31999999; | |
1368 | do_div(temp, 64000000); | |
1369 | ||
1370 | if (temp > 0x3fff) | |
1371 | temp = 0x3fff; | |
1372 | ||
1373 | wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4); | |
1374 | } | |
1375 | ||
1376 | ||
c9df406f | 1377 | /* ethtool ******************************************************************/ |
e5371493 | 1378 | struct mv643xx_eth_stats { |
c9df406f LB |
1379 | char stat_string[ETH_GSTRING_LEN]; |
1380 | int sizeof_stat; | |
16820054 LB |
1381 | int netdev_off; |
1382 | int mp_off; | |
c9df406f LB |
1383 | }; |
1384 | ||
16820054 LB |
1385 | #define SSTAT(m) \ |
1386 | { #m, FIELD_SIZEOF(struct net_device_stats, m), \ | |
1387 | offsetof(struct net_device, stats.m), -1 } | |
1388 | ||
1389 | #define MIBSTAT(m) \ | |
1390 | { #m, FIELD_SIZEOF(struct mib_counters, m), \ | |
1391 | -1, offsetof(struct mv643xx_eth_private, mib_counters.m) } | |
1392 | ||
eaf5d590 LB |
1393 | #define LROSTAT(m) \ |
1394 | { #m, FIELD_SIZEOF(struct lro_counters, m), \ | |
1395 | -1, offsetof(struct mv643xx_eth_private, lro_counters.m) } | |
1396 | ||
16820054 LB |
1397 | static const struct mv643xx_eth_stats mv643xx_eth_stats[] = { |
1398 | SSTAT(rx_packets), | |
1399 | SSTAT(tx_packets), | |
1400 | SSTAT(rx_bytes), | |
1401 | SSTAT(tx_bytes), | |
1402 | SSTAT(rx_errors), | |
1403 | SSTAT(tx_errors), | |
1404 | SSTAT(rx_dropped), | |
1405 | SSTAT(tx_dropped), | |
1406 | MIBSTAT(good_octets_received), | |
1407 | MIBSTAT(bad_octets_received), | |
1408 | MIBSTAT(internal_mac_transmit_err), | |
1409 | MIBSTAT(good_frames_received), | |
1410 | MIBSTAT(bad_frames_received), | |
1411 | MIBSTAT(broadcast_frames_received), | |
1412 | MIBSTAT(multicast_frames_received), | |
1413 | MIBSTAT(frames_64_octets), | |
1414 | MIBSTAT(frames_65_to_127_octets), | |
1415 | MIBSTAT(frames_128_to_255_octets), | |
1416 | MIBSTAT(frames_256_to_511_octets), | |
1417 | MIBSTAT(frames_512_to_1023_octets), | |
1418 | MIBSTAT(frames_1024_to_max_octets), | |
1419 | MIBSTAT(good_octets_sent), | |
1420 | MIBSTAT(good_frames_sent), | |
1421 | MIBSTAT(excessive_collision), | |
1422 | MIBSTAT(multicast_frames_sent), | |
1423 | MIBSTAT(broadcast_frames_sent), | |
1424 | MIBSTAT(unrec_mac_control_received), | |
1425 | MIBSTAT(fc_sent), | |
1426 | MIBSTAT(good_fc_received), | |
1427 | MIBSTAT(bad_fc_received), | |
1428 | MIBSTAT(undersize_received), | |
1429 | MIBSTAT(fragments_received), | |
1430 | MIBSTAT(oversize_received), | |
1431 | MIBSTAT(jabber_received), | |
1432 | MIBSTAT(mac_receive_error), | |
1433 | MIBSTAT(bad_crc_event), | |
1434 | MIBSTAT(collision), | |
1435 | MIBSTAT(late_collision), | |
eaf5d590 LB |
1436 | LROSTAT(lro_aggregated), |
1437 | LROSTAT(lro_flushed), | |
1438 | LROSTAT(lro_no_desc), | |
c9df406f LB |
1439 | }; |
1440 | ||
10a9948d | 1441 | static int |
6bdf576e LB |
1442 | mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp, |
1443 | struct ethtool_cmd *cmd) | |
d0412d96 | 1444 | { |
d0412d96 JC |
1445 | int err; |
1446 | ||
ed94493f LB |
1447 | err = phy_read_status(mp->phy); |
1448 | if (err == 0) | |
1449 | err = phy_ethtool_gset(mp->phy, cmd); | |
d0412d96 | 1450 | |
fc32b0e2 LB |
1451 | /* |
1452 | * The MAC does not support 1000baseT_Half. | |
1453 | */ | |
d0412d96 JC |
1454 | cmd->supported &= ~SUPPORTED_1000baseT_Half; |
1455 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; | |
1456 | ||
1457 | return err; | |
1458 | } | |
1459 | ||
10a9948d | 1460 | static int |
6bdf576e | 1461 | mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp, |
10a9948d | 1462 | struct ethtool_cmd *cmd) |
bedfe324 | 1463 | { |
81600eea LB |
1464 | u32 port_status; |
1465 | ||
37a6084f | 1466 | port_status = rdlp(mp, PORT_STATUS); |
81600eea | 1467 | |
bedfe324 LB |
1468 | cmd->supported = SUPPORTED_MII; |
1469 | cmd->advertising = ADVERTISED_MII; | |
81600eea LB |
1470 | switch (port_status & PORT_SPEED_MASK) { |
1471 | case PORT_SPEED_10: | |
1472 | cmd->speed = SPEED_10; | |
1473 | break; | |
1474 | case PORT_SPEED_100: | |
1475 | cmd->speed = SPEED_100; | |
1476 | break; | |
1477 | case PORT_SPEED_1000: | |
1478 | cmd->speed = SPEED_1000; | |
1479 | break; | |
1480 | default: | |
1481 | cmd->speed = -1; | |
1482 | break; | |
1483 | } | |
1484 | cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF; | |
bedfe324 LB |
1485 | cmd->port = PORT_MII; |
1486 | cmd->phy_address = 0; | |
1487 | cmd->transceiver = XCVR_INTERNAL; | |
1488 | cmd->autoneg = AUTONEG_DISABLE; | |
1489 | cmd->maxtxpkt = 1; | |
1490 | cmd->maxrxpkt = 1; | |
1491 | ||
1492 | return 0; | |
1493 | } | |
1494 | ||
6bdf576e LB |
1495 | static int |
1496 | mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1497 | { | |
1498 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1499 | ||
1500 | if (mp->phy != NULL) | |
1501 | return mv643xx_eth_get_settings_phy(mp, cmd); | |
1502 | else | |
1503 | return mv643xx_eth_get_settings_phyless(mp, cmd); | |
1504 | } | |
1505 | ||
10a9948d LB |
1506 | static int |
1507 | mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1da177e4 | 1508 | { |
e5371493 | 1509 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
ab4384a6 | 1510 | |
6bdf576e LB |
1511 | if (mp->phy == NULL) |
1512 | return -EINVAL; | |
1513 | ||
fc32b0e2 LB |
1514 | /* |
1515 | * The MAC does not support 1000baseT_Half. | |
1516 | */ | |
1517 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; | |
1518 | ||
ed94493f | 1519 | return phy_ethtool_sset(mp->phy, cmd); |
c9df406f | 1520 | } |
1da177e4 | 1521 | |
fc32b0e2 LB |
1522 | static void mv643xx_eth_get_drvinfo(struct net_device *dev, |
1523 | struct ethtool_drvinfo *drvinfo) | |
c9df406f | 1524 | { |
e5371493 LB |
1525 | strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32); |
1526 | strncpy(drvinfo->version, mv643xx_eth_driver_version, 32); | |
c9df406f | 1527 | strncpy(drvinfo->fw_version, "N/A", 32); |
fc32b0e2 | 1528 | strncpy(drvinfo->bus_info, "platform", 32); |
16820054 | 1529 | drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats); |
c9df406f | 1530 | } |
1da177e4 | 1531 | |
fc32b0e2 | 1532 | static int mv643xx_eth_nway_reset(struct net_device *dev) |
c9df406f | 1533 | { |
e5371493 | 1534 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 1535 | |
6bdf576e LB |
1536 | if (mp->phy == NULL) |
1537 | return -EINVAL; | |
1da177e4 | 1538 | |
6bdf576e | 1539 | return genphy_restart_aneg(mp->phy); |
bedfe324 LB |
1540 | } |
1541 | ||
c9df406f LB |
1542 | static u32 mv643xx_eth_get_link(struct net_device *dev) |
1543 | { | |
ed94493f | 1544 | return !!netif_carrier_ok(dev); |
bedfe324 LB |
1545 | } |
1546 | ||
3e508034 LB |
1547 | static int |
1548 | mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) | |
1549 | { | |
1550 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1551 | ||
1552 | ec->rx_coalesce_usecs = get_rx_coal(mp); | |
1553 | ec->tx_coalesce_usecs = get_tx_coal(mp); | |
1554 | ||
1555 | return 0; | |
1556 | } | |
1557 | ||
1558 | static int | |
1559 | mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) | |
1560 | { | |
1561 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1562 | ||
1563 | set_rx_coal(mp, ec->rx_coalesce_usecs); | |
1564 | set_tx_coal(mp, ec->tx_coalesce_usecs); | |
1565 | ||
1566 | return 0; | |
1567 | } | |
1568 | ||
e7d2f4db LB |
1569 | static void |
1570 | mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er) | |
1571 | { | |
1572 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1573 | ||
1574 | er->rx_max_pending = 4096; | |
1575 | er->tx_max_pending = 4096; | |
1576 | er->rx_mini_max_pending = 0; | |
1577 | er->rx_jumbo_max_pending = 0; | |
1578 | ||
1579 | er->rx_pending = mp->rx_ring_size; | |
1580 | er->tx_pending = mp->tx_ring_size; | |
1581 | er->rx_mini_pending = 0; | |
1582 | er->rx_jumbo_pending = 0; | |
1583 | } | |
1584 | ||
1585 | static int | |
1586 | mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er) | |
1587 | { | |
1588 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1589 | ||
1590 | if (er->rx_mini_pending || er->rx_jumbo_pending) | |
1591 | return -EINVAL; | |
1592 | ||
1593 | mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096; | |
1594 | mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096; | |
1595 | ||
1596 | if (netif_running(dev)) { | |
1597 | mv643xx_eth_stop(dev); | |
1598 | if (mv643xx_eth_open(dev)) { | |
1599 | dev_printk(KERN_ERR, &dev->dev, | |
1600 | "fatal error on re-opening device after " | |
1601 | "ring param change\n"); | |
1602 | return -ENOMEM; | |
1603 | } | |
1604 | } | |
1605 | ||
1606 | return 0; | |
1607 | } | |
1608 | ||
d888b373 LB |
1609 | static u32 |
1610 | mv643xx_eth_get_rx_csum(struct net_device *dev) | |
1611 | { | |
1612 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1613 | ||
1614 | return !!(rdlp(mp, PORT_CONFIG) & 0x02000000); | |
1615 | } | |
1616 | ||
1617 | static int | |
1618 | mv643xx_eth_set_rx_csum(struct net_device *dev, u32 rx_csum) | |
1619 | { | |
1620 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1621 | ||
1622 | wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000); | |
1623 | ||
1624 | return 0; | |
1625 | } | |
1626 | ||
fc32b0e2 LB |
1627 | static void mv643xx_eth_get_strings(struct net_device *dev, |
1628 | uint32_t stringset, uint8_t *data) | |
c9df406f LB |
1629 | { |
1630 | int i; | |
1da177e4 | 1631 | |
fc32b0e2 LB |
1632 | if (stringset == ETH_SS_STATS) { |
1633 | for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { | |
c9df406f | 1634 | memcpy(data + i * ETH_GSTRING_LEN, |
16820054 | 1635 | mv643xx_eth_stats[i].stat_string, |
e5371493 | 1636 | ETH_GSTRING_LEN); |
c9df406f | 1637 | } |
c9df406f LB |
1638 | } |
1639 | } | |
1da177e4 | 1640 | |
fc32b0e2 LB |
1641 | static void mv643xx_eth_get_ethtool_stats(struct net_device *dev, |
1642 | struct ethtool_stats *stats, | |
1643 | uint64_t *data) | |
c9df406f | 1644 | { |
b9873841 | 1645 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 1646 | int i; |
1da177e4 | 1647 | |
8fd89211 | 1648 | mv643xx_eth_get_stats(dev); |
fc32b0e2 | 1649 | mib_counters_update(mp); |
eaf5d590 | 1650 | mv643xx_eth_grab_lro_stats(mp); |
1da177e4 | 1651 | |
16820054 LB |
1652 | for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { |
1653 | const struct mv643xx_eth_stats *stat; | |
1654 | void *p; | |
1655 | ||
1656 | stat = mv643xx_eth_stats + i; | |
1657 | ||
1658 | if (stat->netdev_off >= 0) | |
1659 | p = ((void *)mp->dev) + stat->netdev_off; | |
1660 | else | |
1661 | p = ((void *)mp) + stat->mp_off; | |
1662 | ||
1663 | data[i] = (stat->sizeof_stat == 8) ? | |
1664 | *(uint64_t *)p : *(uint32_t *)p; | |
1da177e4 | 1665 | } |
c9df406f | 1666 | } |
1da177e4 | 1667 | |
fc32b0e2 | 1668 | static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset) |
c9df406f | 1669 | { |
fc32b0e2 | 1670 | if (sset == ETH_SS_STATS) |
16820054 | 1671 | return ARRAY_SIZE(mv643xx_eth_stats); |
fc32b0e2 LB |
1672 | |
1673 | return -EOPNOTSUPP; | |
c9df406f | 1674 | } |
1da177e4 | 1675 | |
e5371493 | 1676 | static const struct ethtool_ops mv643xx_eth_ethtool_ops = { |
fc32b0e2 LB |
1677 | .get_settings = mv643xx_eth_get_settings, |
1678 | .set_settings = mv643xx_eth_set_settings, | |
1679 | .get_drvinfo = mv643xx_eth_get_drvinfo, | |
1680 | .nway_reset = mv643xx_eth_nway_reset, | |
1681 | .get_link = mv643xx_eth_get_link, | |
3e508034 LB |
1682 | .get_coalesce = mv643xx_eth_get_coalesce, |
1683 | .set_coalesce = mv643xx_eth_set_coalesce, | |
e7d2f4db LB |
1684 | .get_ringparam = mv643xx_eth_get_ringparam, |
1685 | .set_ringparam = mv643xx_eth_set_ringparam, | |
d888b373 LB |
1686 | .get_rx_csum = mv643xx_eth_get_rx_csum, |
1687 | .set_rx_csum = mv643xx_eth_set_rx_csum, | |
b8df184f | 1688 | .set_tx_csum = ethtool_op_set_tx_csum, |
c9df406f | 1689 | .set_sg = ethtool_op_set_sg, |
fc32b0e2 LB |
1690 | .get_strings = mv643xx_eth_get_strings, |
1691 | .get_ethtool_stats = mv643xx_eth_get_ethtool_stats, | |
eaf5d590 LB |
1692 | .get_flags = ethtool_op_get_flags, |
1693 | .set_flags = ethtool_op_set_flags, | |
e5371493 | 1694 | .get_sset_count = mv643xx_eth_get_sset_count, |
c9df406f | 1695 | }; |
1da177e4 | 1696 | |
bea3348e | 1697 | |
c9df406f | 1698 | /* address handling *********************************************************/ |
5daffe94 | 1699 | static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr) |
c9df406f | 1700 | { |
66e63ffb LB |
1701 | unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH); |
1702 | unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW); | |
1da177e4 | 1703 | |
5daffe94 LB |
1704 | addr[0] = (mac_h >> 24) & 0xff; |
1705 | addr[1] = (mac_h >> 16) & 0xff; | |
1706 | addr[2] = (mac_h >> 8) & 0xff; | |
1707 | addr[3] = mac_h & 0xff; | |
1708 | addr[4] = (mac_l >> 8) & 0xff; | |
1709 | addr[5] = mac_l & 0xff; | |
c9df406f | 1710 | } |
1da177e4 | 1711 | |
66e63ffb | 1712 | static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr) |
c9df406f | 1713 | { |
66e63ffb LB |
1714 | wrlp(mp, MAC_ADDR_HIGH, |
1715 | (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]); | |
1716 | wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]); | |
c9df406f | 1717 | } |
d0412d96 | 1718 | |
66e63ffb | 1719 | static u32 uc_addr_filter_mask(struct net_device *dev) |
c9df406f | 1720 | { |
66e63ffb LB |
1721 | struct dev_addr_list *uc_ptr; |
1722 | u32 nibbles; | |
1da177e4 | 1723 | |
66e63ffb LB |
1724 | if (dev->flags & IFF_PROMISC) |
1725 | return 0; | |
1da177e4 | 1726 | |
66e63ffb LB |
1727 | nibbles = 1 << (dev->dev_addr[5] & 0x0f); |
1728 | for (uc_ptr = dev->uc_list; uc_ptr != NULL; uc_ptr = uc_ptr->next) { | |
1729 | if (memcmp(dev->dev_addr, uc_ptr->da_addr, 5)) | |
1730 | return 0; | |
1731 | if ((dev->dev_addr[5] ^ uc_ptr->da_addr[5]) & 0xf0) | |
1732 | return 0; | |
ff561eef | 1733 | |
66e63ffb LB |
1734 | nibbles |= 1 << (uc_ptr->da_addr[5] & 0x0f); |
1735 | } | |
1da177e4 | 1736 | |
66e63ffb | 1737 | return nibbles; |
1da177e4 LT |
1738 | } |
1739 | ||
66e63ffb | 1740 | static void mv643xx_eth_program_unicast_filter(struct net_device *dev) |
1da177e4 | 1741 | { |
e5371493 | 1742 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
66e63ffb LB |
1743 | u32 port_config; |
1744 | u32 nibbles; | |
1745 | int i; | |
1da177e4 | 1746 | |
cc9754b3 | 1747 | uc_addr_set(mp, dev->dev_addr); |
1da177e4 | 1748 | |
66e63ffb LB |
1749 | port_config = rdlp(mp, PORT_CONFIG); |
1750 | nibbles = uc_addr_filter_mask(dev); | |
1751 | if (!nibbles) { | |
1752 | port_config |= UNICAST_PROMISCUOUS_MODE; | |
1753 | wrlp(mp, PORT_CONFIG, port_config); | |
1754 | return; | |
1755 | } | |
1756 | ||
1757 | for (i = 0; i < 16; i += 4) { | |
1758 | int off = UNICAST_TABLE(mp->port_num) + i; | |
1759 | u32 v; | |
1760 | ||
1761 | v = 0; | |
1762 | if (nibbles & 1) | |
1763 | v |= 0x00000001; | |
1764 | if (nibbles & 2) | |
1765 | v |= 0x00000100; | |
1766 | if (nibbles & 4) | |
1767 | v |= 0x00010000; | |
1768 | if (nibbles & 8) | |
1769 | v |= 0x01000000; | |
1770 | nibbles >>= 4; | |
1771 | ||
1772 | wrl(mp, off, v); | |
1773 | } | |
1774 | ||
1775 | port_config &= ~UNICAST_PROMISCUOUS_MODE; | |
1776 | wrlp(mp, PORT_CONFIG, port_config); | |
1da177e4 LT |
1777 | } |
1778 | ||
69876569 LB |
1779 | static int addr_crc(unsigned char *addr) |
1780 | { | |
1781 | int crc = 0; | |
1782 | int i; | |
1783 | ||
1784 | for (i = 0; i < 6; i++) { | |
1785 | int j; | |
1786 | ||
1787 | crc = (crc ^ addr[i]) << 8; | |
1788 | for (j = 7; j >= 0; j--) { | |
1789 | if (crc & (0x100 << j)) | |
1790 | crc ^= 0x107 << j; | |
1791 | } | |
1792 | } | |
1793 | ||
1794 | return crc; | |
1795 | } | |
1796 | ||
66e63ffb | 1797 | static void mv643xx_eth_program_multicast_filter(struct net_device *dev) |
1da177e4 | 1798 | { |
fc32b0e2 | 1799 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
66e63ffb LB |
1800 | u32 *mc_spec; |
1801 | u32 *mc_other; | |
fc32b0e2 LB |
1802 | struct dev_addr_list *addr; |
1803 | int i; | |
c8aaea25 | 1804 | |
fc32b0e2 | 1805 | if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) { |
66e63ffb LB |
1806 | int port_num; |
1807 | u32 accept; | |
c8aaea25 | 1808 | |
66e63ffb LB |
1809 | oom: |
1810 | port_num = mp->port_num; | |
1811 | accept = 0x01010101; | |
fc32b0e2 LB |
1812 | for (i = 0; i < 0x100; i += 4) { |
1813 | wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept); | |
1814 | wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept); | |
c9df406f LB |
1815 | } |
1816 | return; | |
1817 | } | |
c8aaea25 | 1818 | |
82a5bd6a | 1819 | mc_spec = kmalloc(0x200, GFP_ATOMIC); |
66e63ffb LB |
1820 | if (mc_spec == NULL) |
1821 | goto oom; | |
1822 | mc_other = mc_spec + (0x100 >> 2); | |
1823 | ||
1824 | memset(mc_spec, 0, 0x100); | |
1825 | memset(mc_other, 0, 0x100); | |
1da177e4 | 1826 | |
fc32b0e2 LB |
1827 | for (addr = dev->mc_list; addr != NULL; addr = addr->next) { |
1828 | u8 *a = addr->da_addr; | |
66e63ffb LB |
1829 | u32 *table; |
1830 | int entry; | |
1da177e4 | 1831 | |
fc32b0e2 | 1832 | if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) { |
66e63ffb LB |
1833 | table = mc_spec; |
1834 | entry = a[5]; | |
fc32b0e2 | 1835 | } else { |
66e63ffb LB |
1836 | table = mc_other; |
1837 | entry = addr_crc(a); | |
fc32b0e2 | 1838 | } |
66e63ffb | 1839 | |
2b448334 | 1840 | table[entry >> 2] |= 1 << (8 * (entry & 3)); |
fc32b0e2 | 1841 | } |
66e63ffb LB |
1842 | |
1843 | for (i = 0; i < 0x100; i += 4) { | |
1844 | wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]); | |
1845 | wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]); | |
1846 | } | |
1847 | ||
1848 | kfree(mc_spec); | |
1849 | } | |
1850 | ||
1851 | static void mv643xx_eth_set_rx_mode(struct net_device *dev) | |
1852 | { | |
1853 | mv643xx_eth_program_unicast_filter(dev); | |
1854 | mv643xx_eth_program_multicast_filter(dev); | |
1855 | } | |
1856 | ||
1857 | static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) | |
1858 | { | |
1859 | struct sockaddr *sa = addr; | |
1860 | ||
1861 | memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN); | |
1862 | ||
1863 | netif_addr_lock_bh(dev); | |
1864 | mv643xx_eth_program_unicast_filter(dev); | |
1865 | netif_addr_unlock_bh(dev); | |
1866 | ||
1867 | return 0; | |
c9df406f | 1868 | } |
c8aaea25 | 1869 | |
c8aaea25 | 1870 | |
c9df406f | 1871 | /* rx/tx queue initialisation ***********************************************/ |
64da80a2 | 1872 | static int rxq_init(struct mv643xx_eth_private *mp, int index) |
c9df406f | 1873 | { |
64da80a2 | 1874 | struct rx_queue *rxq = mp->rxq + index; |
8a578111 LB |
1875 | struct rx_desc *rx_desc; |
1876 | int size; | |
c9df406f LB |
1877 | int i; |
1878 | ||
64da80a2 LB |
1879 | rxq->index = index; |
1880 | ||
e7d2f4db | 1881 | rxq->rx_ring_size = mp->rx_ring_size; |
8a578111 LB |
1882 | |
1883 | rxq->rx_desc_count = 0; | |
1884 | rxq->rx_curr_desc = 0; | |
1885 | rxq->rx_used_desc = 0; | |
1886 | ||
1887 | size = rxq->rx_ring_size * sizeof(struct rx_desc); | |
1888 | ||
f7981c1c | 1889 | if (index == 0 && size <= mp->rx_desc_sram_size) { |
8a578111 LB |
1890 | rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr, |
1891 | mp->rx_desc_sram_size); | |
1892 | rxq->rx_desc_dma = mp->rx_desc_sram_addr; | |
1893 | } else { | |
1894 | rxq->rx_desc_area = dma_alloc_coherent(NULL, size, | |
1895 | &rxq->rx_desc_dma, | |
1896 | GFP_KERNEL); | |
f7ea3337 PJ |
1897 | } |
1898 | ||
8a578111 LB |
1899 | if (rxq->rx_desc_area == NULL) { |
1900 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1901 | "can't allocate rx ring (%d bytes)\n", size); | |
1902 | goto out; | |
1903 | } | |
1904 | memset(rxq->rx_desc_area, 0, size); | |
1da177e4 | 1905 | |
8a578111 LB |
1906 | rxq->rx_desc_area_size = size; |
1907 | rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb), | |
1908 | GFP_KERNEL); | |
1909 | if (rxq->rx_skb == NULL) { | |
1910 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1911 | "can't allocate rx skb ring\n"); | |
1912 | goto out_free; | |
1913 | } | |
1914 | ||
1915 | rx_desc = (struct rx_desc *)rxq->rx_desc_area; | |
1916 | for (i = 0; i < rxq->rx_ring_size; i++) { | |
9da78745 LB |
1917 | int nexti; |
1918 | ||
1919 | nexti = i + 1; | |
1920 | if (nexti == rxq->rx_ring_size) | |
1921 | nexti = 0; | |
1922 | ||
8a578111 LB |
1923 | rx_desc[i].next_desc_ptr = rxq->rx_desc_dma + |
1924 | nexti * sizeof(struct rx_desc); | |
1925 | } | |
1926 | ||
eaf5d590 LB |
1927 | rxq->lro_mgr.dev = mp->dev; |
1928 | memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats)); | |
1929 | rxq->lro_mgr.features = LRO_F_NAPI; | |
1930 | rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY; | |
1931 | rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY; | |
1932 | rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr); | |
1933 | rxq->lro_mgr.max_aggr = 32; | |
1934 | rxq->lro_mgr.frag_align_pad = 0; | |
1935 | rxq->lro_mgr.lro_arr = rxq->lro_arr; | |
1936 | rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header; | |
1937 | ||
1938 | memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr)); | |
eaf5d590 | 1939 | |
8a578111 LB |
1940 | return 0; |
1941 | ||
1942 | ||
1943 | out_free: | |
f7981c1c | 1944 | if (index == 0 && size <= mp->rx_desc_sram_size) |
8a578111 LB |
1945 | iounmap(rxq->rx_desc_area); |
1946 | else | |
1947 | dma_free_coherent(NULL, size, | |
1948 | rxq->rx_desc_area, | |
1949 | rxq->rx_desc_dma); | |
1950 | ||
1951 | out: | |
1952 | return -ENOMEM; | |
c9df406f | 1953 | } |
c8aaea25 | 1954 | |
8a578111 | 1955 | static void rxq_deinit(struct rx_queue *rxq) |
c9df406f | 1956 | { |
8a578111 LB |
1957 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
1958 | int i; | |
1959 | ||
1960 | rxq_disable(rxq); | |
c8aaea25 | 1961 | |
8a578111 LB |
1962 | for (i = 0; i < rxq->rx_ring_size; i++) { |
1963 | if (rxq->rx_skb[i]) { | |
1964 | dev_kfree_skb(rxq->rx_skb[i]); | |
1965 | rxq->rx_desc_count--; | |
1da177e4 | 1966 | } |
c8aaea25 | 1967 | } |
1da177e4 | 1968 | |
8a578111 LB |
1969 | if (rxq->rx_desc_count) { |
1970 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1971 | "error freeing rx ring -- %d skbs stuck\n", | |
1972 | rxq->rx_desc_count); | |
1973 | } | |
1974 | ||
f7981c1c | 1975 | if (rxq->index == 0 && |
64da80a2 | 1976 | rxq->rx_desc_area_size <= mp->rx_desc_sram_size) |
8a578111 | 1977 | iounmap(rxq->rx_desc_area); |
c9df406f | 1978 | else |
8a578111 LB |
1979 | dma_free_coherent(NULL, rxq->rx_desc_area_size, |
1980 | rxq->rx_desc_area, rxq->rx_desc_dma); | |
1981 | ||
1982 | kfree(rxq->rx_skb); | |
c9df406f | 1983 | } |
1da177e4 | 1984 | |
3d6b35bc | 1985 | static int txq_init(struct mv643xx_eth_private *mp, int index) |
c9df406f | 1986 | { |
3d6b35bc | 1987 | struct tx_queue *txq = mp->txq + index; |
13d64285 LB |
1988 | struct tx_desc *tx_desc; |
1989 | int size; | |
c9df406f | 1990 | int i; |
1da177e4 | 1991 | |
3d6b35bc LB |
1992 | txq->index = index; |
1993 | ||
e7d2f4db | 1994 | txq->tx_ring_size = mp->tx_ring_size; |
13d64285 LB |
1995 | |
1996 | txq->tx_desc_count = 0; | |
1997 | txq->tx_curr_desc = 0; | |
1998 | txq->tx_used_desc = 0; | |
1999 | ||
2000 | size = txq->tx_ring_size * sizeof(struct tx_desc); | |
2001 | ||
f7981c1c | 2002 | if (index == 0 && size <= mp->tx_desc_sram_size) { |
13d64285 LB |
2003 | txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr, |
2004 | mp->tx_desc_sram_size); | |
2005 | txq->tx_desc_dma = mp->tx_desc_sram_addr; | |
2006 | } else { | |
2007 | txq->tx_desc_area = dma_alloc_coherent(NULL, size, | |
2008 | &txq->tx_desc_dma, | |
2009 | GFP_KERNEL); | |
2010 | } | |
2011 | ||
2012 | if (txq->tx_desc_area == NULL) { | |
2013 | dev_printk(KERN_ERR, &mp->dev->dev, | |
2014 | "can't allocate tx ring (%d bytes)\n", size); | |
99ab08e0 | 2015 | return -ENOMEM; |
c9df406f | 2016 | } |
13d64285 LB |
2017 | memset(txq->tx_desc_area, 0, size); |
2018 | ||
2019 | txq->tx_desc_area_size = size; | |
13d64285 LB |
2020 | |
2021 | tx_desc = (struct tx_desc *)txq->tx_desc_area; | |
2022 | for (i = 0; i < txq->tx_ring_size; i++) { | |
6b368f68 | 2023 | struct tx_desc *txd = tx_desc + i; |
9da78745 LB |
2024 | int nexti; |
2025 | ||
2026 | nexti = i + 1; | |
2027 | if (nexti == txq->tx_ring_size) | |
2028 | nexti = 0; | |
6b368f68 LB |
2029 | |
2030 | txd->cmd_sts = 0; | |
2031 | txd->next_desc_ptr = txq->tx_desc_dma + | |
13d64285 LB |
2032 | nexti * sizeof(struct tx_desc); |
2033 | } | |
2034 | ||
99ab08e0 | 2035 | skb_queue_head_init(&txq->tx_skb); |
c9df406f | 2036 | |
99ab08e0 | 2037 | return 0; |
c8aaea25 | 2038 | } |
1da177e4 | 2039 | |
13d64285 | 2040 | static void txq_deinit(struct tx_queue *txq) |
c9df406f | 2041 | { |
13d64285 | 2042 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
fa3959f4 | 2043 | |
13d64285 | 2044 | txq_disable(txq); |
1fa38c58 | 2045 | txq_reclaim(txq, txq->tx_ring_size, 1); |
1da177e4 | 2046 | |
13d64285 | 2047 | BUG_ON(txq->tx_used_desc != txq->tx_curr_desc); |
1da177e4 | 2048 | |
f7981c1c | 2049 | if (txq->index == 0 && |
3d6b35bc | 2050 | txq->tx_desc_area_size <= mp->tx_desc_sram_size) |
13d64285 | 2051 | iounmap(txq->tx_desc_area); |
c9df406f | 2052 | else |
13d64285 LB |
2053 | dma_free_coherent(NULL, txq->tx_desc_area_size, |
2054 | txq->tx_desc_area, txq->tx_desc_dma); | |
c9df406f | 2055 | } |
1da177e4 | 2056 | |
1da177e4 | 2057 | |
c9df406f | 2058 | /* netdev ops and related ***************************************************/ |
1fa38c58 LB |
2059 | static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp) |
2060 | { | |
2061 | u32 int_cause; | |
2062 | u32 int_cause_ext; | |
2063 | ||
37a6084f | 2064 | int_cause = rdlp(mp, INT_CAUSE) & (INT_TX_END | INT_RX | INT_EXT); |
1fa38c58 LB |
2065 | if (int_cause == 0) |
2066 | return 0; | |
2067 | ||
2068 | int_cause_ext = 0; | |
2069 | if (int_cause & INT_EXT) | |
37a6084f | 2070 | int_cause_ext = rdlp(mp, INT_CAUSE_EXT); |
1fa38c58 LB |
2071 | |
2072 | int_cause &= INT_TX_END | INT_RX; | |
2073 | if (int_cause) { | |
37a6084f | 2074 | wrlp(mp, INT_CAUSE, ~int_cause); |
1fa38c58 | 2075 | mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) & |
37a6084f | 2076 | ~(rdlp(mp, TXQ_COMMAND) & 0xff); |
1fa38c58 LB |
2077 | mp->work_rx |= (int_cause & INT_RX) >> 2; |
2078 | } | |
2079 | ||
2080 | int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX; | |
2081 | if (int_cause_ext) { | |
37a6084f | 2082 | wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext); |
1fa38c58 LB |
2083 | if (int_cause_ext & INT_EXT_LINK_PHY) |
2084 | mp->work_link = 1; | |
2085 | mp->work_tx |= int_cause_ext & INT_EXT_TX; | |
2086 | } | |
2087 | ||
2088 | return 1; | |
2089 | } | |
2090 | ||
2091 | static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id) | |
2092 | { | |
2093 | struct net_device *dev = (struct net_device *)dev_id; | |
2094 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
2095 | ||
2096 | if (unlikely(!mv643xx_eth_collect_events(mp))) | |
2097 | return IRQ_NONE; | |
2098 | ||
37a6084f | 2099 | wrlp(mp, INT_MASK, 0); |
1fa38c58 LB |
2100 | napi_schedule(&mp->napi); |
2101 | ||
2102 | return IRQ_HANDLED; | |
2103 | } | |
2104 | ||
2f7eb47a LB |
2105 | static void handle_link_event(struct mv643xx_eth_private *mp) |
2106 | { | |
2107 | struct net_device *dev = mp->dev; | |
2108 | u32 port_status; | |
2109 | int speed; | |
2110 | int duplex; | |
2111 | int fc; | |
2112 | ||
37a6084f | 2113 | port_status = rdlp(mp, PORT_STATUS); |
2f7eb47a LB |
2114 | if (!(port_status & LINK_UP)) { |
2115 | if (netif_carrier_ok(dev)) { | |
2116 | int i; | |
2117 | ||
2118 | printk(KERN_INFO "%s: link down\n", dev->name); | |
2119 | ||
2120 | netif_carrier_off(dev); | |
2f7eb47a | 2121 | |
f7981c1c | 2122 | for (i = 0; i < mp->txq_count; i++) { |
2f7eb47a LB |
2123 | struct tx_queue *txq = mp->txq + i; |
2124 | ||
1fa38c58 | 2125 | txq_reclaim(txq, txq->tx_ring_size, 1); |
f7981c1c | 2126 | txq_reset_hw_ptr(txq); |
2f7eb47a LB |
2127 | } |
2128 | } | |
2129 | return; | |
2130 | } | |
2131 | ||
2132 | switch (port_status & PORT_SPEED_MASK) { | |
2133 | case PORT_SPEED_10: | |
2134 | speed = 10; | |
2135 | break; | |
2136 | case PORT_SPEED_100: | |
2137 | speed = 100; | |
2138 | break; | |
2139 | case PORT_SPEED_1000: | |
2140 | speed = 1000; | |
2141 | break; | |
2142 | default: | |
2143 | speed = -1; | |
2144 | break; | |
2145 | } | |
2146 | duplex = (port_status & FULL_DUPLEX) ? 1 : 0; | |
2147 | fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0; | |
2148 | ||
2149 | printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, " | |
2150 | "flow control %sabled\n", dev->name, | |
2151 | speed, duplex ? "full" : "half", | |
2152 | fc ? "en" : "dis"); | |
2153 | ||
4fdeca3f | 2154 | if (!netif_carrier_ok(dev)) |
2f7eb47a | 2155 | netif_carrier_on(dev); |
2f7eb47a LB |
2156 | } |
2157 | ||
1fa38c58 | 2158 | static int mv643xx_eth_poll(struct napi_struct *napi, int budget) |
c9df406f | 2159 | { |
1fa38c58 LB |
2160 | struct mv643xx_eth_private *mp; |
2161 | int work_done; | |
ce4e2e45 | 2162 | |
1fa38c58 | 2163 | mp = container_of(napi, struct mv643xx_eth_private, napi); |
fc32b0e2 | 2164 | |
1319ebad LB |
2165 | if (unlikely(mp->oom)) { |
2166 | mp->oom = 0; | |
2167 | del_timer(&mp->rx_oom); | |
2168 | } | |
1da177e4 | 2169 | |
1fa38c58 LB |
2170 | work_done = 0; |
2171 | while (work_done < budget) { | |
2172 | u8 queue_mask; | |
2173 | int queue; | |
2174 | int work_tbd; | |
2175 | ||
2176 | if (mp->work_link) { | |
2177 | mp->work_link = 0; | |
2178 | handle_link_event(mp); | |
26ef1f17 | 2179 | work_done++; |
1fa38c58 LB |
2180 | continue; |
2181 | } | |
1da177e4 | 2182 | |
1319ebad LB |
2183 | queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx; |
2184 | if (likely(!mp->oom)) | |
2185 | queue_mask |= mp->work_rx_refill; | |
2186 | ||
1fa38c58 LB |
2187 | if (!queue_mask) { |
2188 | if (mv643xx_eth_collect_events(mp)) | |
2189 | continue; | |
2190 | break; | |
2191 | } | |
1da177e4 | 2192 | |
1fa38c58 LB |
2193 | queue = fls(queue_mask) - 1; |
2194 | queue_mask = 1 << queue; | |
2195 | ||
2196 | work_tbd = budget - work_done; | |
2197 | if (work_tbd > 16) | |
2198 | work_tbd = 16; | |
2199 | ||
2200 | if (mp->work_tx_end & queue_mask) { | |
2201 | txq_kick(mp->txq + queue); | |
2202 | } else if (mp->work_tx & queue_mask) { | |
2203 | work_done += txq_reclaim(mp->txq + queue, work_tbd, 0); | |
2204 | txq_maybe_wake(mp->txq + queue); | |
2205 | } else if (mp->work_rx & queue_mask) { | |
2206 | work_done += rxq_process(mp->rxq + queue, work_tbd); | |
1319ebad | 2207 | } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) { |
1fa38c58 LB |
2208 | work_done += rxq_refill(mp->rxq + queue, work_tbd); |
2209 | } else { | |
2210 | BUG(); | |
2211 | } | |
84dd619e | 2212 | } |
fc32b0e2 | 2213 | |
1fa38c58 | 2214 | if (work_done < budget) { |
1319ebad | 2215 | if (mp->oom) |
1fa38c58 LB |
2216 | mod_timer(&mp->rx_oom, jiffies + (HZ / 10)); |
2217 | napi_complete(napi); | |
37a6084f | 2218 | wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT); |
226bb6b7 | 2219 | } |
3d6b35bc | 2220 | |
1fa38c58 LB |
2221 | return work_done; |
2222 | } | |
8fa89bf5 | 2223 | |
1fa38c58 LB |
2224 | static inline void oom_timer_wrapper(unsigned long data) |
2225 | { | |
2226 | struct mv643xx_eth_private *mp = (void *)data; | |
1da177e4 | 2227 | |
1fa38c58 | 2228 | napi_schedule(&mp->napi); |
1da177e4 LT |
2229 | } |
2230 | ||
e5371493 | 2231 | static void phy_reset(struct mv643xx_eth_private *mp) |
1da177e4 | 2232 | { |
45c5d3bc LB |
2233 | int data; |
2234 | ||
ed94493f | 2235 | data = phy_read(mp->phy, MII_BMCR); |
45c5d3bc LB |
2236 | if (data < 0) |
2237 | return; | |
1da177e4 | 2238 | |
7f106c1d | 2239 | data |= BMCR_RESET; |
ed94493f | 2240 | if (phy_write(mp->phy, MII_BMCR, data) < 0) |
45c5d3bc | 2241 | return; |
1da177e4 | 2242 | |
c9df406f | 2243 | do { |
ed94493f | 2244 | data = phy_read(mp->phy, MII_BMCR); |
45c5d3bc | 2245 | } while (data >= 0 && data & BMCR_RESET); |
1da177e4 LT |
2246 | } |
2247 | ||
fc32b0e2 | 2248 | static void port_start(struct mv643xx_eth_private *mp) |
1da177e4 | 2249 | { |
d0412d96 | 2250 | u32 pscr; |
8a578111 | 2251 | int i; |
1da177e4 | 2252 | |
bedfe324 LB |
2253 | /* |
2254 | * Perform PHY reset, if there is a PHY. | |
2255 | */ | |
ed94493f | 2256 | if (mp->phy != NULL) { |
bedfe324 LB |
2257 | struct ethtool_cmd cmd; |
2258 | ||
2259 | mv643xx_eth_get_settings(mp->dev, &cmd); | |
2260 | phy_reset(mp); | |
2261 | mv643xx_eth_set_settings(mp->dev, &cmd); | |
2262 | } | |
1da177e4 | 2263 | |
81600eea LB |
2264 | /* |
2265 | * Configure basic link parameters. | |
2266 | */ | |
37a6084f | 2267 | pscr = rdlp(mp, PORT_SERIAL_CONTROL); |
81600eea LB |
2268 | |
2269 | pscr |= SERIAL_PORT_ENABLE; | |
37a6084f | 2270 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
81600eea LB |
2271 | |
2272 | pscr |= DO_NOT_FORCE_LINK_FAIL; | |
ed94493f | 2273 | if (mp->phy == NULL) |
81600eea | 2274 | pscr |= FORCE_LINK_PASS; |
37a6084f | 2275 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
81600eea | 2276 | |
13d64285 LB |
2277 | /* |
2278 | * Configure TX path and queues. | |
2279 | */ | |
89df5fdc | 2280 | tx_set_rate(mp, 1000000000, 16777216); |
f7981c1c | 2281 | for (i = 0; i < mp->txq_count; i++) { |
3d6b35bc | 2282 | struct tx_queue *txq = mp->txq + i; |
13d64285 | 2283 | |
6b368f68 | 2284 | txq_reset_hw_ptr(txq); |
89df5fdc LB |
2285 | txq_set_rate(txq, 1000000000, 16777216); |
2286 | txq_set_fixed_prio_mode(txq); | |
13d64285 LB |
2287 | } |
2288 | ||
d9a073ea LB |
2289 | /* |
2290 | * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast | |
170e7108 LB |
2291 | * frames to RX queue #0, and include the pseudo-header when |
2292 | * calculating receive checksums. | |
d9a073ea | 2293 | */ |
37a6084f | 2294 | wrlp(mp, PORT_CONFIG, 0x02000000); |
01999873 | 2295 | |
376489a2 LB |
2296 | /* |
2297 | * Treat BPDUs as normal multicasts, and disable partition mode. | |
2298 | */ | |
37a6084f | 2299 | wrlp(mp, PORT_CONFIG_EXT, 0x00000000); |
01999873 | 2300 | |
5a893922 LB |
2301 | /* |
2302 | * Add configured unicast addresses to address filter table. | |
2303 | */ | |
2304 | mv643xx_eth_program_unicast_filter(mp->dev); | |
2305 | ||
8a578111 | 2306 | /* |
64da80a2 | 2307 | * Enable the receive queues. |
8a578111 | 2308 | */ |
f7981c1c | 2309 | for (i = 0; i < mp->rxq_count; i++) { |
64da80a2 | 2310 | struct rx_queue *rxq = mp->rxq + i; |
8a578111 | 2311 | u32 addr; |
1da177e4 | 2312 | |
8a578111 LB |
2313 | addr = (u32)rxq->rx_desc_dma; |
2314 | addr += rxq->rx_curr_desc * sizeof(struct rx_desc); | |
37a6084f | 2315 | wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr); |
1da177e4 | 2316 | |
8a578111 LB |
2317 | rxq_enable(rxq); |
2318 | } | |
1da177e4 LT |
2319 | } |
2320 | ||
2bcb4b0f LB |
2321 | static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp) |
2322 | { | |
2323 | int skb_size; | |
2324 | ||
2325 | /* | |
2326 | * Reserve 2+14 bytes for an ethernet header (the hardware | |
2327 | * automatically prepends 2 bytes of dummy data to each | |
2328 | * received packet), 16 bytes for up to four VLAN tags, and | |
2329 | * 4 bytes for the trailing FCS -- 36 bytes total. | |
2330 | */ | |
2331 | skb_size = mp->dev->mtu + 36; | |
2332 | ||
2333 | /* | |
2334 | * Make sure that the skb size is a multiple of 8 bytes, as | |
2335 | * the lower three bits of the receive descriptor's buffer | |
2336 | * size field are ignored by the hardware. | |
2337 | */ | |
2338 | mp->skb_size = (skb_size + 7) & ~7; | |
2339 | } | |
2340 | ||
c9df406f | 2341 | static int mv643xx_eth_open(struct net_device *dev) |
16e03018 | 2342 | { |
e5371493 | 2343 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 2344 | int err; |
64da80a2 | 2345 | int i; |
16e03018 | 2346 | |
37a6084f LB |
2347 | wrlp(mp, INT_CAUSE, 0); |
2348 | wrlp(mp, INT_CAUSE_EXT, 0); | |
2349 | rdlp(mp, INT_CAUSE_EXT); | |
c9df406f | 2350 | |
fc32b0e2 | 2351 | err = request_irq(dev->irq, mv643xx_eth_irq, |
2a1867a7 | 2352 | IRQF_SHARED, dev->name, dev); |
c9df406f | 2353 | if (err) { |
fc32b0e2 | 2354 | dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n"); |
c9df406f | 2355 | return -EAGAIN; |
16e03018 DF |
2356 | } |
2357 | ||
2bcb4b0f LB |
2358 | mv643xx_eth_recalc_skb_size(mp); |
2359 | ||
2257e05c LB |
2360 | napi_enable(&mp->napi); |
2361 | ||
2bcb4b0f LB |
2362 | skb_queue_head_init(&mp->rx_recycle); |
2363 | ||
f7981c1c | 2364 | for (i = 0; i < mp->rxq_count; i++) { |
64da80a2 LB |
2365 | err = rxq_init(mp, i); |
2366 | if (err) { | |
2367 | while (--i >= 0) | |
f7981c1c | 2368 | rxq_deinit(mp->rxq + i); |
64da80a2 LB |
2369 | goto out; |
2370 | } | |
2371 | ||
1fa38c58 | 2372 | rxq_refill(mp->rxq + i, INT_MAX); |
2257e05c LB |
2373 | } |
2374 | ||
1319ebad | 2375 | if (mp->oom) { |
2257e05c LB |
2376 | mp->rx_oom.expires = jiffies + (HZ / 10); |
2377 | add_timer(&mp->rx_oom); | |
64da80a2 | 2378 | } |
8a578111 | 2379 | |
f7981c1c | 2380 | for (i = 0; i < mp->txq_count; i++) { |
3d6b35bc LB |
2381 | err = txq_init(mp, i); |
2382 | if (err) { | |
2383 | while (--i >= 0) | |
f7981c1c | 2384 | txq_deinit(mp->txq + i); |
3d6b35bc LB |
2385 | goto out_free; |
2386 | } | |
2387 | } | |
16e03018 | 2388 | |
fc32b0e2 | 2389 | port_start(mp); |
16e03018 | 2390 | |
37a6084f LB |
2391 | wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX); |
2392 | wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT); | |
16e03018 | 2393 | |
c9df406f LB |
2394 | return 0; |
2395 | ||
13d64285 | 2396 | |
fc32b0e2 | 2397 | out_free: |
f7981c1c LB |
2398 | for (i = 0; i < mp->rxq_count; i++) |
2399 | rxq_deinit(mp->rxq + i); | |
fc32b0e2 | 2400 | out: |
c9df406f LB |
2401 | free_irq(dev->irq, dev); |
2402 | ||
2403 | return err; | |
16e03018 DF |
2404 | } |
2405 | ||
e5371493 | 2406 | static void port_reset(struct mv643xx_eth_private *mp) |
1da177e4 | 2407 | { |
fc32b0e2 | 2408 | unsigned int data; |
64da80a2 | 2409 | int i; |
1da177e4 | 2410 | |
f7981c1c LB |
2411 | for (i = 0; i < mp->rxq_count; i++) |
2412 | rxq_disable(mp->rxq + i); | |
2413 | for (i = 0; i < mp->txq_count; i++) | |
2414 | txq_disable(mp->txq + i); | |
ae9ae064 LB |
2415 | |
2416 | while (1) { | |
37a6084f | 2417 | u32 ps = rdlp(mp, PORT_STATUS); |
ae9ae064 LB |
2418 | |
2419 | if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY) | |
2420 | break; | |
13d64285 | 2421 | udelay(10); |
ae9ae064 | 2422 | } |
1da177e4 | 2423 | |
c9df406f | 2424 | /* Reset the Enable bit in the Configuration Register */ |
37a6084f | 2425 | data = rdlp(mp, PORT_SERIAL_CONTROL); |
fc32b0e2 LB |
2426 | data &= ~(SERIAL_PORT_ENABLE | |
2427 | DO_NOT_FORCE_LINK_FAIL | | |
2428 | FORCE_LINK_PASS); | |
37a6084f | 2429 | wrlp(mp, PORT_SERIAL_CONTROL, data); |
1da177e4 LT |
2430 | } |
2431 | ||
c9df406f | 2432 | static int mv643xx_eth_stop(struct net_device *dev) |
1da177e4 | 2433 | { |
e5371493 | 2434 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
64da80a2 | 2435 | int i; |
1da177e4 | 2436 | |
fe65e704 | 2437 | wrlp(mp, INT_MASK_EXT, 0x00000000); |
37a6084f LB |
2438 | wrlp(mp, INT_MASK, 0x00000000); |
2439 | rdlp(mp, INT_MASK); | |
1da177e4 | 2440 | |
c9df406f | 2441 | napi_disable(&mp->napi); |
78fff83b | 2442 | |
2257e05c LB |
2443 | del_timer_sync(&mp->rx_oom); |
2444 | ||
c9df406f | 2445 | netif_carrier_off(dev); |
1da177e4 | 2446 | |
fc32b0e2 LB |
2447 | free_irq(dev->irq, dev); |
2448 | ||
cc9754b3 | 2449 | port_reset(mp); |
8fd89211 | 2450 | mv643xx_eth_get_stats(dev); |
fc32b0e2 | 2451 | mib_counters_update(mp); |
57e8f26a | 2452 | del_timer_sync(&mp->mib_counters_timer); |
1da177e4 | 2453 | |
2bcb4b0f LB |
2454 | skb_queue_purge(&mp->rx_recycle); |
2455 | ||
f7981c1c LB |
2456 | for (i = 0; i < mp->rxq_count; i++) |
2457 | rxq_deinit(mp->rxq + i); | |
2458 | for (i = 0; i < mp->txq_count; i++) | |
2459 | txq_deinit(mp->txq + i); | |
1da177e4 | 2460 | |
c9df406f | 2461 | return 0; |
1da177e4 LT |
2462 | } |
2463 | ||
fc32b0e2 | 2464 | static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
1da177e4 | 2465 | { |
e5371493 | 2466 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 2467 | |
ed94493f LB |
2468 | if (mp->phy != NULL) |
2469 | return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd); | |
bedfe324 LB |
2470 | |
2471 | return -EOPNOTSUPP; | |
1da177e4 LT |
2472 | } |
2473 | ||
c9df406f | 2474 | static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) |
1da177e4 | 2475 | { |
89df5fdc LB |
2476 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
2477 | ||
fc32b0e2 | 2478 | if (new_mtu < 64 || new_mtu > 9500) |
c9df406f | 2479 | return -EINVAL; |
1da177e4 | 2480 | |
c9df406f | 2481 | dev->mtu = new_mtu; |
2bcb4b0f | 2482 | mv643xx_eth_recalc_skb_size(mp); |
89df5fdc LB |
2483 | tx_set_rate(mp, 1000000000, 16777216); |
2484 | ||
c9df406f LB |
2485 | if (!netif_running(dev)) |
2486 | return 0; | |
1da177e4 | 2487 | |
c9df406f LB |
2488 | /* |
2489 | * Stop and then re-open the interface. This will allocate RX | |
2490 | * skbs of the new MTU. | |
2491 | * There is a possible danger that the open will not succeed, | |
fc32b0e2 | 2492 | * due to memory being full. |
c9df406f LB |
2493 | */ |
2494 | mv643xx_eth_stop(dev); | |
2495 | if (mv643xx_eth_open(dev)) { | |
fc32b0e2 LB |
2496 | dev_printk(KERN_ERR, &dev->dev, |
2497 | "fatal error on re-opening device after " | |
2498 | "MTU change\n"); | |
c9df406f LB |
2499 | } |
2500 | ||
2501 | return 0; | |
1da177e4 LT |
2502 | } |
2503 | ||
fc32b0e2 | 2504 | static void tx_timeout_task(struct work_struct *ugly) |
1da177e4 | 2505 | { |
fc32b0e2 | 2506 | struct mv643xx_eth_private *mp; |
1da177e4 | 2507 | |
fc32b0e2 LB |
2508 | mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task); |
2509 | if (netif_running(mp->dev)) { | |
e5ef1de1 | 2510 | netif_tx_stop_all_queues(mp->dev); |
fc32b0e2 LB |
2511 | port_reset(mp); |
2512 | port_start(mp); | |
e5ef1de1 | 2513 | netif_tx_wake_all_queues(mp->dev); |
fc32b0e2 | 2514 | } |
c9df406f LB |
2515 | } |
2516 | ||
c9df406f | 2517 | static void mv643xx_eth_tx_timeout(struct net_device *dev) |
1da177e4 | 2518 | { |
e5371493 | 2519 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 2520 | |
fc32b0e2 | 2521 | dev_printk(KERN_INFO, &dev->dev, "tx timeout\n"); |
d0412d96 | 2522 | |
c9df406f | 2523 | schedule_work(&mp->tx_timeout_task); |
1da177e4 LT |
2524 | } |
2525 | ||
c9df406f | 2526 | #ifdef CONFIG_NET_POLL_CONTROLLER |
fc32b0e2 | 2527 | static void mv643xx_eth_netpoll(struct net_device *dev) |
9f8dd319 | 2528 | { |
fc32b0e2 | 2529 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 2530 | |
37a6084f LB |
2531 | wrlp(mp, INT_MASK, 0x00000000); |
2532 | rdlp(mp, INT_MASK); | |
c9df406f | 2533 | |
fc32b0e2 | 2534 | mv643xx_eth_irq(dev->irq, dev); |
c9df406f | 2535 | |
37a6084f | 2536 | wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT); |
9f8dd319 | 2537 | } |
c9df406f | 2538 | #endif |
9f8dd319 | 2539 | |
9f8dd319 | 2540 | |
c9df406f | 2541 | /* platform glue ************************************************************/ |
e5371493 LB |
2542 | static void |
2543 | mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp, | |
2544 | struct mbus_dram_target_info *dram) | |
c9df406f | 2545 | { |
cc9754b3 | 2546 | void __iomem *base = msp->base; |
c9df406f LB |
2547 | u32 win_enable; |
2548 | u32 win_protect; | |
2549 | int i; | |
9f8dd319 | 2550 | |
c9df406f LB |
2551 | for (i = 0; i < 6; i++) { |
2552 | writel(0, base + WINDOW_BASE(i)); | |
2553 | writel(0, base + WINDOW_SIZE(i)); | |
2554 | if (i < 4) | |
2555 | writel(0, base + WINDOW_REMAP_HIGH(i)); | |
9f8dd319 DF |
2556 | } |
2557 | ||
c9df406f LB |
2558 | win_enable = 0x3f; |
2559 | win_protect = 0; | |
2560 | ||
2561 | for (i = 0; i < dram->num_cs; i++) { | |
2562 | struct mbus_dram_window *cs = dram->cs + i; | |
2563 | ||
2564 | writel((cs->base & 0xffff0000) | | |
2565 | (cs->mbus_attr << 8) | | |
2566 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); | |
2567 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); | |
2568 | ||
2569 | win_enable &= ~(1 << i); | |
2570 | win_protect |= 3 << (2 * i); | |
2571 | } | |
2572 | ||
2573 | writel(win_enable, base + WINDOW_BAR_ENABLE); | |
2574 | msp->win_protect = win_protect; | |
9f8dd319 DF |
2575 | } |
2576 | ||
773fc3ee LB |
2577 | static void infer_hw_params(struct mv643xx_eth_shared_private *msp) |
2578 | { | |
2579 | /* | |
2580 | * Check whether we have a 14-bit coal limit field in bits | |
2581 | * [21:8], or a 16-bit coal limit in bits [25,21:7] of the | |
2582 | * SDMA config register. | |
2583 | */ | |
37a6084f LB |
2584 | writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG); |
2585 | if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000) | |
773fc3ee LB |
2586 | msp->extended_rx_coal_limit = 1; |
2587 | else | |
2588 | msp->extended_rx_coal_limit = 0; | |
1e881592 LB |
2589 | |
2590 | /* | |
457b1d5a LB |
2591 | * Check whether the MAC supports TX rate control, and if |
2592 | * yes, whether its associated registers are in the old or | |
2593 | * the new place. | |
1e881592 | 2594 | */ |
37a6084f LB |
2595 | writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED); |
2596 | if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) { | |
457b1d5a LB |
2597 | msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT; |
2598 | } else { | |
37a6084f LB |
2599 | writel(7, msp->base + 0x0400 + TX_BW_RATE); |
2600 | if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7) | |
457b1d5a LB |
2601 | msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT; |
2602 | else | |
2603 | msp->tx_bw_control = TX_BW_CONTROL_ABSENT; | |
2604 | } | |
773fc3ee LB |
2605 | } |
2606 | ||
c9df406f | 2607 | static int mv643xx_eth_shared_probe(struct platform_device *pdev) |
9f8dd319 | 2608 | { |
10a9948d | 2609 | static int mv643xx_eth_version_printed; |
c9df406f | 2610 | struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data; |
e5371493 | 2611 | struct mv643xx_eth_shared_private *msp; |
c9df406f LB |
2612 | struct resource *res; |
2613 | int ret; | |
9f8dd319 | 2614 | |
e5371493 | 2615 | if (!mv643xx_eth_version_printed++) |
7dde154d LB |
2616 | printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet " |
2617 | "driver version %s\n", mv643xx_eth_driver_version); | |
9f8dd319 | 2618 | |
c9df406f LB |
2619 | ret = -EINVAL; |
2620 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2621 | if (res == NULL) | |
2622 | goto out; | |
9f8dd319 | 2623 | |
c9df406f LB |
2624 | ret = -ENOMEM; |
2625 | msp = kmalloc(sizeof(*msp), GFP_KERNEL); | |
2626 | if (msp == NULL) | |
2627 | goto out; | |
2628 | memset(msp, 0, sizeof(*msp)); | |
2629 | ||
cc9754b3 LB |
2630 | msp->base = ioremap(res->start, res->end - res->start + 1); |
2631 | if (msp->base == NULL) | |
c9df406f LB |
2632 | goto out_free; |
2633 | ||
ed94493f LB |
2634 | /* |
2635 | * Set up and register SMI bus. | |
2636 | */ | |
2637 | if (pd == NULL || pd->shared_smi == NULL) { | |
298cf9be LB |
2638 | msp->smi_bus = mdiobus_alloc(); |
2639 | if (msp->smi_bus == NULL) | |
ed94493f | 2640 | goto out_unmap; |
298cf9be LB |
2641 | |
2642 | msp->smi_bus->priv = msp; | |
2643 | msp->smi_bus->name = "mv643xx_eth smi"; | |
2644 | msp->smi_bus->read = smi_bus_read; | |
2645 | msp->smi_bus->write = smi_bus_write, | |
2646 | snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id); | |
2647 | msp->smi_bus->parent = &pdev->dev; | |
2648 | msp->smi_bus->phy_mask = 0xffffffff; | |
2649 | if (mdiobus_register(msp->smi_bus) < 0) | |
2650 | goto out_free_mii_bus; | |
ed94493f LB |
2651 | msp->smi = msp; |
2652 | } else { | |
fc0eb9f2 | 2653 | msp->smi = platform_get_drvdata(pd->shared_smi); |
ed94493f | 2654 | } |
c9df406f | 2655 | |
45c5d3bc LB |
2656 | msp->err_interrupt = NO_IRQ; |
2657 | init_waitqueue_head(&msp->smi_busy_wait); | |
2658 | ||
2659 | /* | |
2660 | * Check whether the error interrupt is hooked up. | |
2661 | */ | |
2662 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
2663 | if (res != NULL) { | |
2664 | int err; | |
2665 | ||
2666 | err = request_irq(res->start, mv643xx_eth_err_irq, | |
2667 | IRQF_SHARED, "mv643xx_eth", msp); | |
2668 | if (!err) { | |
2669 | writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK); | |
2670 | msp->err_interrupt = res->start; | |
2671 | } | |
2672 | } | |
2673 | ||
c9df406f LB |
2674 | /* |
2675 | * (Re-)program MBUS remapping windows if we are asked to. | |
2676 | */ | |
2677 | if (pd != NULL && pd->dram != NULL) | |
2678 | mv643xx_eth_conf_mbus_windows(msp, pd->dram); | |
2679 | ||
fc32b0e2 LB |
2680 | /* |
2681 | * Detect hardware parameters. | |
2682 | */ | |
2683 | msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000; | |
773fc3ee | 2684 | infer_hw_params(msp); |
fc32b0e2 LB |
2685 | |
2686 | platform_set_drvdata(pdev, msp); | |
2687 | ||
c9df406f LB |
2688 | return 0; |
2689 | ||
298cf9be LB |
2690 | out_free_mii_bus: |
2691 | mdiobus_free(msp->smi_bus); | |
ed94493f LB |
2692 | out_unmap: |
2693 | iounmap(msp->base); | |
c9df406f LB |
2694 | out_free: |
2695 | kfree(msp); | |
2696 | out: | |
2697 | return ret; | |
2698 | } | |
2699 | ||
2700 | static int mv643xx_eth_shared_remove(struct platform_device *pdev) | |
2701 | { | |
e5371493 | 2702 | struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev); |
ed94493f | 2703 | struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data; |
c9df406f | 2704 | |
298cf9be | 2705 | if (pd == NULL || pd->shared_smi == NULL) { |
298cf9be | 2706 | mdiobus_unregister(msp->smi_bus); |
bcb3336c | 2707 | mdiobus_free(msp->smi_bus); |
298cf9be | 2708 | } |
45c5d3bc LB |
2709 | if (msp->err_interrupt != NO_IRQ) |
2710 | free_irq(msp->err_interrupt, msp); | |
cc9754b3 | 2711 | iounmap(msp->base); |
c9df406f LB |
2712 | kfree(msp); |
2713 | ||
2714 | return 0; | |
9f8dd319 DF |
2715 | } |
2716 | ||
c9df406f | 2717 | static struct platform_driver mv643xx_eth_shared_driver = { |
fc32b0e2 LB |
2718 | .probe = mv643xx_eth_shared_probe, |
2719 | .remove = mv643xx_eth_shared_remove, | |
c9df406f | 2720 | .driver = { |
fc32b0e2 | 2721 | .name = MV643XX_ETH_SHARED_NAME, |
c9df406f LB |
2722 | .owner = THIS_MODULE, |
2723 | }, | |
2724 | }; | |
2725 | ||
e5371493 | 2726 | static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr) |
1da177e4 | 2727 | { |
c9df406f | 2728 | int addr_shift = 5 * mp->port_num; |
fc32b0e2 | 2729 | u32 data; |
1da177e4 | 2730 | |
fc32b0e2 LB |
2731 | data = rdl(mp, PHY_ADDR); |
2732 | data &= ~(0x1f << addr_shift); | |
2733 | data |= (phy_addr & 0x1f) << addr_shift; | |
2734 | wrl(mp, PHY_ADDR, data); | |
1da177e4 LT |
2735 | } |
2736 | ||
e5371493 | 2737 | static int phy_addr_get(struct mv643xx_eth_private *mp) |
1da177e4 | 2738 | { |
fc32b0e2 LB |
2739 | unsigned int data; |
2740 | ||
2741 | data = rdl(mp, PHY_ADDR); | |
2742 | ||
2743 | return (data >> (5 * mp->port_num)) & 0x1f; | |
2744 | } | |
2745 | ||
2746 | static void set_params(struct mv643xx_eth_private *mp, | |
2747 | struct mv643xx_eth_platform_data *pd) | |
2748 | { | |
2749 | struct net_device *dev = mp->dev; | |
2750 | ||
2751 | if (is_valid_ether_addr(pd->mac_addr)) | |
2752 | memcpy(dev->dev_addr, pd->mac_addr, 6); | |
2753 | else | |
2754 | uc_addr_get(mp, dev->dev_addr); | |
2755 | ||
e7d2f4db | 2756 | mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE; |
fc32b0e2 | 2757 | if (pd->rx_queue_size) |
e7d2f4db | 2758 | mp->rx_ring_size = pd->rx_queue_size; |
fc32b0e2 LB |
2759 | mp->rx_desc_sram_addr = pd->rx_sram_addr; |
2760 | mp->rx_desc_sram_size = pd->rx_sram_size; | |
1da177e4 | 2761 | |
f7981c1c | 2762 | mp->rxq_count = pd->rx_queue_count ? : 1; |
64da80a2 | 2763 | |
e7d2f4db | 2764 | mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE; |
fc32b0e2 | 2765 | if (pd->tx_queue_size) |
e7d2f4db | 2766 | mp->tx_ring_size = pd->tx_queue_size; |
fc32b0e2 LB |
2767 | mp->tx_desc_sram_addr = pd->tx_sram_addr; |
2768 | mp->tx_desc_sram_size = pd->tx_sram_size; | |
3d6b35bc | 2769 | |
f7981c1c | 2770 | mp->txq_count = pd->tx_queue_count ? : 1; |
1da177e4 LT |
2771 | } |
2772 | ||
ed94493f LB |
2773 | static struct phy_device *phy_scan(struct mv643xx_eth_private *mp, |
2774 | int phy_addr) | |
1da177e4 | 2775 | { |
298cf9be | 2776 | struct mii_bus *bus = mp->shared->smi->smi_bus; |
ed94493f LB |
2777 | struct phy_device *phydev; |
2778 | int start; | |
2779 | int num; | |
2780 | int i; | |
45c5d3bc | 2781 | |
ed94493f LB |
2782 | if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) { |
2783 | start = phy_addr_get(mp) & 0x1f; | |
2784 | num = 32; | |
2785 | } else { | |
2786 | start = phy_addr & 0x1f; | |
2787 | num = 1; | |
2788 | } | |
45c5d3bc | 2789 | |
ed94493f LB |
2790 | phydev = NULL; |
2791 | for (i = 0; i < num; i++) { | |
2792 | int addr = (start + i) & 0x1f; | |
fc32b0e2 | 2793 | |
ed94493f LB |
2794 | if (bus->phy_map[addr] == NULL) |
2795 | mdiobus_scan(bus, addr); | |
1da177e4 | 2796 | |
ed94493f LB |
2797 | if (phydev == NULL) { |
2798 | phydev = bus->phy_map[addr]; | |
2799 | if (phydev != NULL) | |
2800 | phy_addr_set(mp, addr); | |
2801 | } | |
2802 | } | |
1da177e4 | 2803 | |
ed94493f | 2804 | return phydev; |
1da177e4 LT |
2805 | } |
2806 | ||
ed94493f | 2807 | static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex) |
c28a4f89 | 2808 | { |
ed94493f | 2809 | struct phy_device *phy = mp->phy; |
c28a4f89 | 2810 | |
fc32b0e2 LB |
2811 | phy_reset(mp); |
2812 | ||
db1d7bf7 | 2813 | phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII); |
ed94493f LB |
2814 | |
2815 | if (speed == 0) { | |
2816 | phy->autoneg = AUTONEG_ENABLE; | |
2817 | phy->speed = 0; | |
2818 | phy->duplex = 0; | |
2819 | phy->advertising = phy->supported | ADVERTISED_Autoneg; | |
c9df406f | 2820 | } else { |
ed94493f LB |
2821 | phy->autoneg = AUTONEG_DISABLE; |
2822 | phy->advertising = 0; | |
2823 | phy->speed = speed; | |
2824 | phy->duplex = duplex; | |
c9df406f | 2825 | } |
ed94493f | 2826 | phy_start_aneg(phy); |
c28a4f89 JC |
2827 | } |
2828 | ||
81600eea LB |
2829 | static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex) |
2830 | { | |
2831 | u32 pscr; | |
2832 | ||
37a6084f | 2833 | pscr = rdlp(mp, PORT_SERIAL_CONTROL); |
81600eea LB |
2834 | if (pscr & SERIAL_PORT_ENABLE) { |
2835 | pscr &= ~SERIAL_PORT_ENABLE; | |
37a6084f | 2836 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
81600eea LB |
2837 | } |
2838 | ||
2839 | pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED; | |
ed94493f | 2840 | if (mp->phy == NULL) { |
81600eea LB |
2841 | pscr |= DISABLE_AUTO_NEG_SPEED_GMII; |
2842 | if (speed == SPEED_1000) | |
2843 | pscr |= SET_GMII_SPEED_TO_1000; | |
2844 | else if (speed == SPEED_100) | |
2845 | pscr |= SET_MII_SPEED_TO_100; | |
2846 | ||
2847 | pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL; | |
2848 | ||
2849 | pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX; | |
2850 | if (duplex == DUPLEX_FULL) | |
2851 | pscr |= SET_FULL_DUPLEX_MODE; | |
2852 | } | |
2853 | ||
37a6084f | 2854 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
81600eea LB |
2855 | } |
2856 | ||
ea8a8642 LB |
2857 | static const struct net_device_ops mv643xx_eth_netdev_ops = { |
2858 | .ndo_open = mv643xx_eth_open, | |
2859 | .ndo_stop = mv643xx_eth_stop, | |
2860 | .ndo_start_xmit = mv643xx_eth_xmit, | |
2861 | .ndo_set_rx_mode = mv643xx_eth_set_rx_mode, | |
2862 | .ndo_set_mac_address = mv643xx_eth_set_mac_address, | |
2863 | .ndo_do_ioctl = mv643xx_eth_ioctl, | |
2864 | .ndo_change_mtu = mv643xx_eth_change_mtu, | |
2865 | .ndo_tx_timeout = mv643xx_eth_tx_timeout, | |
2866 | .ndo_get_stats = mv643xx_eth_get_stats, | |
2867 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2868 | .ndo_poll_controller = mv643xx_eth_netpoll, | |
2869 | #endif | |
2870 | }; | |
2871 | ||
c9df406f | 2872 | static int mv643xx_eth_probe(struct platform_device *pdev) |
1da177e4 | 2873 | { |
c9df406f | 2874 | struct mv643xx_eth_platform_data *pd; |
e5371493 | 2875 | struct mv643xx_eth_private *mp; |
c9df406f | 2876 | struct net_device *dev; |
c9df406f | 2877 | struct resource *res; |
fc32b0e2 | 2878 | int err; |
1da177e4 | 2879 | |
c9df406f LB |
2880 | pd = pdev->dev.platform_data; |
2881 | if (pd == NULL) { | |
fc32b0e2 LB |
2882 | dev_printk(KERN_ERR, &pdev->dev, |
2883 | "no mv643xx_eth_platform_data\n"); | |
c9df406f LB |
2884 | return -ENODEV; |
2885 | } | |
1da177e4 | 2886 | |
c9df406f | 2887 | if (pd->shared == NULL) { |
fc32b0e2 LB |
2888 | dev_printk(KERN_ERR, &pdev->dev, |
2889 | "no mv643xx_eth_platform_data->shared\n"); | |
c9df406f LB |
2890 | return -ENODEV; |
2891 | } | |
8f518703 | 2892 | |
e5ef1de1 | 2893 | dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8); |
c9df406f LB |
2894 | if (!dev) |
2895 | return -ENOMEM; | |
1da177e4 | 2896 | |
c9df406f | 2897 | mp = netdev_priv(dev); |
fc32b0e2 LB |
2898 | platform_set_drvdata(pdev, mp); |
2899 | ||
2900 | mp->shared = platform_get_drvdata(pd->shared); | |
37a6084f | 2901 | mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10); |
fc32b0e2 LB |
2902 | mp->port_num = pd->port_number; |
2903 | ||
c9df406f | 2904 | mp->dev = dev; |
78fff83b | 2905 | |
fc32b0e2 | 2906 | set_params(mp, pd); |
e5ef1de1 | 2907 | dev->real_num_tx_queues = mp->txq_count; |
fc32b0e2 | 2908 | |
ed94493f LB |
2909 | if (pd->phy_addr != MV643XX_ETH_PHY_NONE) |
2910 | mp->phy = phy_scan(mp, pd->phy_addr); | |
bedfe324 | 2911 | |
6bdf576e | 2912 | if (mp->phy != NULL) |
ed94493f | 2913 | phy_init(mp, pd->speed, pd->duplex); |
6bdf576e LB |
2914 | |
2915 | SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops); | |
ed94493f | 2916 | |
81600eea | 2917 | init_pscr(mp, pd->speed, pd->duplex); |
fc32b0e2 | 2918 | |
4ff3495a LB |
2919 | |
2920 | mib_counters_clear(mp); | |
2921 | ||
2922 | init_timer(&mp->mib_counters_timer); | |
2923 | mp->mib_counters_timer.data = (unsigned long)mp; | |
2924 | mp->mib_counters_timer.function = mib_counters_timer_wrapper; | |
2925 | mp->mib_counters_timer.expires = jiffies + 30 * HZ; | |
2926 | add_timer(&mp->mib_counters_timer); | |
2927 | ||
2928 | spin_lock_init(&mp->mib_counters_lock); | |
2929 | ||
2930 | INIT_WORK(&mp->tx_timeout_task, tx_timeout_task); | |
2931 | ||
2257e05c LB |
2932 | netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128); |
2933 | ||
2934 | init_timer(&mp->rx_oom); | |
2935 | mp->rx_oom.data = (unsigned long)mp; | |
2936 | mp->rx_oom.function = oom_timer_wrapper; | |
2937 | ||
fc32b0e2 | 2938 | |
c9df406f LB |
2939 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
2940 | BUG_ON(!res); | |
2941 | dev->irq = res->start; | |
1da177e4 | 2942 | |
ea8a8642 LB |
2943 | dev->netdev_ops = &mv643xx_eth_netdev_ops; |
2944 | ||
c9df406f LB |
2945 | dev->watchdog_timeo = 2 * HZ; |
2946 | dev->base_addr = 0; | |
1da177e4 | 2947 | |
c9df406f | 2948 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; |
e32b6617 | 2949 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM; |
1da177e4 | 2950 | |
fc32b0e2 | 2951 | SET_NETDEV_DEV(dev, &pdev->dev); |
8f518703 | 2952 | |
c9df406f | 2953 | if (mp->shared->win_protect) |
fc32b0e2 | 2954 | wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect); |
1da177e4 | 2955 | |
a5fe3616 LB |
2956 | netif_carrier_off(dev); |
2957 | ||
b5e86db4 LB |
2958 | wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE); |
2959 | ||
4fb0a54a | 2960 | set_rx_coal(mp, 250); |
a5fe3616 LB |
2961 | set_tx_coal(mp, 0); |
2962 | ||
c9df406f LB |
2963 | err = register_netdev(dev); |
2964 | if (err) | |
2965 | goto out; | |
1da177e4 | 2966 | |
e174961c JB |
2967 | dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n", |
2968 | mp->port_num, dev->dev_addr); | |
1da177e4 | 2969 | |
13d64285 | 2970 | if (mp->tx_desc_sram_size > 0) |
fc32b0e2 | 2971 | dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n"); |
1da177e4 | 2972 | |
c9df406f | 2973 | return 0; |
1da177e4 | 2974 | |
c9df406f LB |
2975 | out: |
2976 | free_netdev(dev); | |
1da177e4 | 2977 | |
c9df406f | 2978 | return err; |
1da177e4 LT |
2979 | } |
2980 | ||
c9df406f | 2981 | static int mv643xx_eth_remove(struct platform_device *pdev) |
1da177e4 | 2982 | { |
fc32b0e2 | 2983 | struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); |
1da177e4 | 2984 | |
fc32b0e2 | 2985 | unregister_netdev(mp->dev); |
ed94493f LB |
2986 | if (mp->phy != NULL) |
2987 | phy_detach(mp->phy); | |
c9df406f | 2988 | flush_scheduled_work(); |
fc32b0e2 | 2989 | free_netdev(mp->dev); |
c9df406f | 2990 | |
c9df406f | 2991 | platform_set_drvdata(pdev, NULL); |
fc32b0e2 | 2992 | |
c9df406f | 2993 | return 0; |
1da177e4 LT |
2994 | } |
2995 | ||
c9df406f | 2996 | static void mv643xx_eth_shutdown(struct platform_device *pdev) |
d0412d96 | 2997 | { |
fc32b0e2 | 2998 | struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); |
d0412d96 | 2999 | |
c9df406f | 3000 | /* Mask all interrupts on ethernet port */ |
37a6084f LB |
3001 | wrlp(mp, INT_MASK, 0); |
3002 | rdlp(mp, INT_MASK); | |
c9df406f | 3003 | |
fc32b0e2 LB |
3004 | if (netif_running(mp->dev)) |
3005 | port_reset(mp); | |
d0412d96 JC |
3006 | } |
3007 | ||
c9df406f | 3008 | static struct platform_driver mv643xx_eth_driver = { |
fc32b0e2 LB |
3009 | .probe = mv643xx_eth_probe, |
3010 | .remove = mv643xx_eth_remove, | |
3011 | .shutdown = mv643xx_eth_shutdown, | |
c9df406f | 3012 | .driver = { |
fc32b0e2 | 3013 | .name = MV643XX_ETH_NAME, |
c9df406f LB |
3014 | .owner = THIS_MODULE, |
3015 | }, | |
3016 | }; | |
3017 | ||
e5371493 | 3018 | static int __init mv643xx_eth_init_module(void) |
d0412d96 | 3019 | { |
c9df406f | 3020 | int rc; |
d0412d96 | 3021 | |
c9df406f LB |
3022 | rc = platform_driver_register(&mv643xx_eth_shared_driver); |
3023 | if (!rc) { | |
3024 | rc = platform_driver_register(&mv643xx_eth_driver); | |
3025 | if (rc) | |
3026 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
3027 | } | |
fc32b0e2 | 3028 | |
c9df406f | 3029 | return rc; |
d0412d96 | 3030 | } |
fc32b0e2 | 3031 | module_init(mv643xx_eth_init_module); |
d0412d96 | 3032 | |
e5371493 | 3033 | static void __exit mv643xx_eth_cleanup_module(void) |
d0412d96 | 3034 | { |
c9df406f LB |
3035 | platform_driver_unregister(&mv643xx_eth_driver); |
3036 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
d0412d96 | 3037 | } |
e5371493 | 3038 | module_exit(mv643xx_eth_cleanup_module); |
1da177e4 | 3039 | |
45675bc6 LB |
3040 | MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, " |
3041 | "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek"); | |
c9df406f | 3042 | MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); |
fc32b0e2 | 3043 | MODULE_LICENSE("GPL"); |
c9df406f | 3044 | MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME); |
fc32b0e2 | 3045 | MODULE_ALIAS("platform:" MV643XX_ETH_NAME); |