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mv643xx_eth: introduce per-port register area pointer
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
c3efab8e 41#include <linux/ip.h>
1da177e4
LT		 42#include <linux/tcp.h>
43#include <linux/udp.h>
44#include <linux/etherdevice.h>
1da177e4
LT		 45#include <linux/delay.h>
46#include <linux/ethtool.h>
d052d1be 47#include <linux/platform_device.h>
fbd6a754
LB		 48#include <linux/module.h>
49#include <linux/kernel.h>
50#include <linux/spinlock.h>
51#include <linux/workqueue.h>
ed94493f 52#include <linux/phy.h>
fbd6a754 53#include <linux/mv643xx_eth.h>
10a9948d
LB		 54#include <linux/io.h>
55#include <linux/types.h>
1da177e4 56#include <asm/system.h>
fbd6a754 57
e5371493 58static char mv643xx_eth_driver_name[] = "mv643xx_eth";
042af53c 59static char mv643xx_eth_driver_version[] = "1.4";
c9df406f 60
fbd6a754 61
fbd6a754
LB		 62/*
63 * Registers shared between all ports.
64 */
3cb4667c
LB		 65#define PHY_ADDR 0x0000
66#define SMI_REG 0x0004
45c5d3bc
LB		 67#define SMI_BUSY 0x10000000
68#define SMI_READ_VALID 0x08000000
69#define SMI_OPCODE_READ 0x04000000
70#define SMI_OPCODE_WRITE 0x00000000
71#define ERR_INT_CAUSE 0x0080
72#define ERR_INT_SMI_DONE 0x00000010
73#define ERR_INT_MASK 0x0084
3cb4667c
LB		 74#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
75#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
76#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
77#define WINDOW_BAR_ENABLE 0x0290
78#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 79
80/*
37a6084f
LB		 81 * Main per-port registers. These live at offset 0x0400 for
82 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
fbd6a754 83 */
37a6084f 84#define PORT_CONFIG 0x0000
d9a073ea 85#define UNICAST_PROMISCUOUS_MODE 0x00000001
37a6084f
LB		 86#define PORT_CONFIG_EXT 0x0004
87#define MAC_ADDR_LOW 0x0014
88#define MAC_ADDR_HIGH 0x0018
89#define SDMA_CONFIG 0x001c
90#define PORT_SERIAL_CONTROL 0x003c
91#define PORT_STATUS 0x0044
a2a41689 92#define TX_FIFO_EMPTY 0x00000400
ae9ae064 93#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 94#define PORT_SPEED_MASK 0x00000030
95#define PORT_SPEED_1000 0x00000010
96#define PORT_SPEED_100 0x00000020
97#define PORT_SPEED_10 0x00000000
98#define FLOW_CONTROL_ENABLED 0x00000008
99#define FULL_DUPLEX 0x00000004
81600eea 100#define LINK_UP 0x00000002
37a6084f
LB		 101#define TXQ_COMMAND 0x0048
102#define TXQ_FIX_PRIO_CONF 0x004c
103#define TX_BW_RATE 0x0050
104#define TX_BW_MTU 0x0058
105#define TX_BW_BURST 0x005c
106#define INT_CAUSE 0x0060
226bb6b7 107#define INT_TX_END 0x07f80000
befefe21 108#define INT_RX 0x000003fc
073a345c 109#define INT_EXT 0x00000002
37a6084f 110#define INT_CAUSE_EXT 0x0064
befefe21
LB		 111#define INT_EXT_LINK_PHY 0x00110000
112#define INT_EXT_TX 0x000000ff
37a6084f
LB		 113#define INT_MASK 0x0068
114#define INT_MASK_EXT 0x006c
115#define TX_FIFO_URGENT_THRESHOLD 0x0074
116#define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
117#define TX_BW_RATE_MOVED 0x00e0
118#define TX_BW_MTU_MOVED 0x00e8
119#define TX_BW_BURST_MOVED 0x00ec
120#define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
121#define RXQ_COMMAND 0x0280
122#define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
123#define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
124#define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
125#define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
126
127/*
128 * Misc per-port registers.
129 */
3cb4667c
LB		 130#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
131#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
132#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
133#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 134
2679a550
LB		 135
136/*
137 * SDMA configuration register.
138 */
cd4ccf76 139#define RX_BURST_SIZE_16_64BIT (4 << 1)
fbd6a754 140#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 141#define BLM_TX_NO_SWAP (1 << 5)
cd4ccf76 142#define TX_BURST_SIZE_16_64BIT (4 << 22)
fbd6a754
LB		 143
144#if defined(__BIG_ENDIAN)
145#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
10a9948d
LB		 146 (RX_BURST_SIZE_16_64BIT | \
147 TX_BURST_SIZE_16_64BIT)
fbd6a754
LB		 148#elif defined(__LITTLE_ENDIAN)
149#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
10a9948d 150 (RX_BURST_SIZE_16_64BIT | \
fbd6a754
LB		 151 BLM_RX_NO_SWAP | \
152 BLM_TX_NO_SWAP | \
10a9948d 153 TX_BURST_SIZE_16_64BIT)
fbd6a754
LB		 154#else
155#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
156#endif
157
2beff77b
LB		 158
159/*
160 * Port serial control register.
161 */
162#define SET_MII_SPEED_TO_100 (1 << 24)
163#define SET_GMII_SPEED_TO_1000 (1 << 23)
164#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 165#define MAX_RX_PACKET_9700BYTE (5 << 17)
2beff77b
LB		 166#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
167#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
168#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
169#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
170#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
171#define FORCE_LINK_PASS (1 << 1)
172#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 173
2b4a624d
LB		 174#define DEFAULT_RX_QUEUE_SIZE 128
175#define DEFAULT_TX_QUEUE_SIZE 256
fbd6a754 176
fbd6a754 177
7ca72a3b
LB		 178/*
179 * RX/TX descriptors.
fbd6a754
LB		 180 */
181#if defined(__BIG_ENDIAN)
cc9754b3 182struct rx_desc {
fbd6a754
LB		 183 u16 byte_cnt; /* Descriptor buffer byte count */
184 u16 buf_size; /* Buffer size */
185 u32 cmd_sts; /* Descriptor command status */
186 u32 next_desc_ptr; /* Next descriptor pointer */
187 u32 buf_ptr; /* Descriptor buffer pointer */
188};
189
cc9754b3 190struct tx_desc {
fbd6a754
LB		 191 u16 byte_cnt; /* buffer byte count */
192 u16 l4i_chk; /* CPU provided TCP checksum */
193 u32 cmd_sts; /* Command/status field */
194 u32 next_desc_ptr; /* Pointer to next descriptor */
195 u32 buf_ptr; /* pointer to buffer for this descriptor*/
196};
197#elif defined(__LITTLE_ENDIAN)
cc9754b3 198struct rx_desc {
fbd6a754
LB		 199 u32 cmd_sts; /* Descriptor command status */
200 u16 buf_size; /* Buffer size */
201 u16 byte_cnt; /* Descriptor buffer byte count */
202 u32 buf_ptr; /* Descriptor buffer pointer */
203 u32 next_desc_ptr; /* Next descriptor pointer */
204};
205
cc9754b3 206struct tx_desc {
fbd6a754
LB		 207 u32 cmd_sts; /* Command/status field */
208 u16 l4i_chk; /* CPU provided TCP checksum */
209 u16 byte_cnt; /* buffer byte count */
210 u32 buf_ptr; /* pointer to buffer for this descriptor*/
211 u32 next_desc_ptr; /* Pointer to next descriptor */
212};
213#else
214#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
215#endif
216
7ca72a3b 217/* RX & TX descriptor command */
cc9754b3 218#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 219
220/* RX & TX descriptor status */
cc9754b3 221#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 222
223/* RX descriptor status */
cc9754b3
LB		 224#define LAYER_4_CHECKSUM_OK 0x40000000
225#define RX_ENABLE_INTERRUPT 0x20000000
226#define RX_FIRST_DESC 0x08000000
227#define RX_LAST_DESC 0x04000000
7ca72a3b
LB		 228
229/* TX descriptor command */
cc9754b3
LB		 230#define TX_ENABLE_INTERRUPT 0x00800000
231#define GEN_CRC 0x00400000
232#define TX_FIRST_DESC 0x00200000
233#define TX_LAST_DESC 0x00100000
234#define ZERO_PADDING 0x00080000
235#define GEN_IP_V4_CHECKSUM 0x00040000
236#define GEN_TCP_UDP_CHECKSUM 0x00020000
237#define UDP_FRAME 0x00010000
e32b6617
LB		 238#define MAC_HDR_EXTRA_4_BYTES 0x00008000
239#define MAC_HDR_EXTRA_8_BYTES 0x00000200
7ca72a3b 240
cc9754b3 241#define TX_IHL_SHIFT 11
7ca72a3b
LB		 242
243
c9df406f 244/* global *******************************************************************/
e5371493 245struct mv643xx_eth_shared_private {
fc32b0e2
LB		 246 /*
247 * Ethernet controller base address.
248 */
cc9754b3 249 void __iomem *base;
c9df406f 250
fc0eb9f2
LB		 251 /*
252 * Points at the right SMI instance to use.
253 */
254 struct mv643xx_eth_shared_private *smi;
255
fc32b0e2 256 /*
ed94493f 257 * Provides access to local SMI interface.
fc32b0e2 258 */
298cf9be 259 struct mii_bus *smi_bus;
c9df406f 260
45c5d3bc
LB		 261 /*
262 * If we have access to the error interrupt pin (which is
263 * somewhat misnamed as it not only reflects internal errors
264 * but also reflects SMI completion), use that to wait for
265 * SMI access completion instead of polling the SMI busy bit.
266 */
267 int err_interrupt;
268 wait_queue_head_t smi_busy_wait;
269
fc32b0e2
LB		 270 /*
271 * Per-port MBUS window access register value.
272 */
c9df406f
LB		 273 u32 win_protect;
274
fc32b0e2
LB		 275 /*
276 * Hardware-specific parameters.
277 */
c9df406f 278 unsigned int t_clk;
773fc3ee 279 int extended_rx_coal_limit;
457b1d5a 280 int tx_bw_control;
c9df406f
LB		 281};
282
457b1d5a
LB		 283#define TX_BW_CONTROL_ABSENT 0
284#define TX_BW_CONTROL_OLD_LAYOUT 1
285#define TX_BW_CONTROL_NEW_LAYOUT 2
286
c9df406f
LB		 287
288/* per-port *****************************************************************/
e5371493 289struct mib_counters {
fbd6a754
LB		 290 u64 good_octets_received;
291 u32 bad_octets_received;
292 u32 internal_mac_transmit_err;
293 u32 good_frames_received;
294 u32 bad_frames_received;
295 u32 broadcast_frames_received;
296 u32 multicast_frames_received;
297 u32 frames_64_octets;
298 u32 frames_65_to_127_octets;
299 u32 frames_128_to_255_octets;
300 u32 frames_256_to_511_octets;
301 u32 frames_512_to_1023_octets;
302 u32 frames_1024_to_max_octets;
303 u64 good_octets_sent;
304 u32 good_frames_sent;
305 u32 excessive_collision;
306 u32 multicast_frames_sent;
307 u32 broadcast_frames_sent;
308 u32 unrec_mac_control_received;
309 u32 fc_sent;
310 u32 good_fc_received;
311 u32 bad_fc_received;
312 u32 undersize_received;
313 u32 fragments_received;
314 u32 oversize_received;
315 u32 jabber_received;
316 u32 mac_receive_error;
317 u32 bad_crc_event;
318 u32 collision;
319 u32 late_collision;
320};
321
8a578111 322struct rx_queue {
64da80a2
LB		 323 int index;
324
8a578111
LB		 325 int rx_ring_size;
326
327 int rx_desc_count;
328 int rx_curr_desc;
329 int rx_used_desc;
330
331 struct rx_desc *rx_desc_area;
332 dma_addr_t rx_desc_dma;
333 int rx_desc_area_size;
334 struct sk_buff **rx_skb;
8a578111
LB		 335};
336
13d64285 337struct tx_queue {
3d6b35bc
LB		 338 int index;
339
13d64285 340 int tx_ring_size;
fbd6a754 341
13d64285
LB		 342 int tx_desc_count;
343 int tx_curr_desc;
344 int tx_used_desc;
fbd6a754 345
5daffe94 346 struct tx_desc *tx_desc_area;
fbd6a754
LB		 347 dma_addr_t tx_desc_dma;
348 int tx_desc_area_size;
99ab08e0
LB		 349
350 struct sk_buff_head tx_skb;
8fd89211
LB		 351
352 unsigned long tx_packets;
353 unsigned long tx_bytes;
354 unsigned long tx_dropped;
13d64285
LB		 355};
356
357struct mv643xx_eth_private {
358 struct mv643xx_eth_shared_private *shared;
37a6084f 359 void __iomem *base;
fc32b0e2 360 int port_num;
13d64285 361
fc32b0e2 362 struct net_device *dev;
fbd6a754 363
ed94493f 364 struct phy_device *phy;
fbd6a754 365
4ff3495a
LB		 366 struct timer_list mib_counters_timer;
367 spinlock_t mib_counters_lock;
fc32b0e2 368 struct mib_counters mib_counters;
4ff3495a 369
fc32b0e2 370 struct work_struct tx_timeout_task;
8a578111 371
1fa38c58
LB		 372 struct napi_struct napi;
373 u8 work_link;
374 u8 work_tx;
375 u8 work_tx_end;
376 u8 work_rx;
377 u8 work_rx_refill;
378 u8 work_rx_oom;
379
2bcb4b0f
LB		 380 int skb_size;
381 struct sk_buff_head rx_recycle;
382
8a578111
LB		 383 /*
384 * RX state.
385 */
386 int default_rx_ring_size;
387 unsigned long rx_desc_sram_addr;
388 int rx_desc_sram_size;
f7981c1c 389 int rxq_count;
2257e05c 390 struct timer_list rx_oom;
64da80a2 391 struct rx_queue rxq[8];
13d64285
LB		 392
393 /*
394 * TX state.
395 */
396 int default_tx_ring_size;
397 unsigned long tx_desc_sram_addr;
398 int tx_desc_sram_size;
f7981c1c 399 int txq_count;
3d6b35bc 400 struct tx_queue txq[8];
fbd6a754 401};
1da177e4 402
fbd6a754 403
c9df406f 404/* port register accessors **************************************************/
e5371493 405static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 406{
cc9754b3 407 return readl(mp->shared->base + offset);
c9df406f 408}
fbd6a754 409
37a6084f
LB		 410static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
411{
412 return readl(mp->base + offset);
413}
414
e5371493 415static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 416{
cc9754b3 417 writel(data, mp->shared->base + offset);
c9df406f 418}
fbd6a754 419
37a6084f
LB		 420static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
421{
422 writel(data, mp->base + offset);
423}
424
fbd6a754 425
c9df406f 426/* rxq/txq helper functions *************************************************/
8a578111 427static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 428{
64da80a2 429 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 430}
fbd6a754 431
13d64285
LB		 432static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
433{
3d6b35bc 434 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 435}
436
8a578111 437static void rxq_enable(struct rx_queue *rxq)
c9df406f 438{
8a578111 439 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
37a6084f 440 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
8a578111 441}
1da177e4 442
8a578111
LB		 443static void rxq_disable(struct rx_queue *rxq)
444{
445 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 446 u8 mask = 1 << rxq->index;
1da177e4 447
37a6084f
LB		 448 wrlp(mp, RXQ_COMMAND, mask << 8);
449 while (rdlp(mp, RXQ_COMMAND) & mask)
8a578111 450 udelay(10);
c9df406f
LB		 451}
452
6b368f68
LB		 453static void txq_reset_hw_ptr(struct tx_queue *txq)
454{
455 struct mv643xx_eth_private *mp = txq_to_mp(txq);
6b368f68
LB		 456 u32 addr;
457
458 addr = (u32)txq->tx_desc_dma;
459 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
37a6084f 460 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
6b368f68
LB		 461}
462
13d64285 463static void txq_enable(struct tx_queue *txq)
1da177e4 464{
13d64285 465 struct mv643xx_eth_private *mp = txq_to_mp(txq);
37a6084f 466 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
1da177e4
LT		 467}
468
13d64285 469static void txq_disable(struct tx_queue *txq)
1da177e4 470{
13d64285 471 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 472 u8 mask = 1 << txq->index;
c9df406f 473
37a6084f
LB		 474 wrlp(mp, TXQ_COMMAND, mask << 8);
475 while (rdlp(mp, TXQ_COMMAND) & mask)
13d64285
LB		 476 udelay(10);
477}
478
1fa38c58 479static void txq_maybe_wake(struct tx_queue *txq)
13d64285
LB		 480{
481 struct mv643xx_eth_private *mp = txq_to_mp(txq);
e5ef1de1 482 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
3d6b35bc 483
8fd89211
LB		 484 if (netif_tx_queue_stopped(nq)) {
485 __netif_tx_lock(nq, smp_processor_id());
486 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
487 netif_tx_wake_queue(nq);
488 __netif_tx_unlock(nq);
489 }
1da177e4
LT		 490}
491
c9df406f 492
1fa38c58 493/* rx napi ******************************************************************/
8a578111 494static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 495{
8a578111
LB		 496 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
497 struct net_device_stats *stats = &mp->dev->stats;
498 int rx;
1da177e4 499
8a578111 500 rx = 0;
9e1f3772 501 while (rx < budget && rxq->rx_desc_count) {
fc32b0e2 502 struct rx_desc *rx_desc;
96587661 503 unsigned int cmd_sts;
fc32b0e2 504 struct sk_buff *skb;
6b8f90c2 505 u16 byte_cnt;
ff561eef 506
8a578111 507 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 508
96587661 509 cmd_sts = rx_desc->cmd_sts;
2257e05c 510 if (cmd_sts & BUFFER_OWNED_BY_DMA)
96587661 511 break;
96587661 512 rmb();
1da177e4 513
8a578111
LB		 514 skb = rxq->rx_skb[rxq->rx_curr_desc];
515 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 516
9da78745
LB		 517 rxq->rx_curr_desc++;
518 if (rxq->rx_curr_desc == rxq->rx_ring_size)
519 rxq->rx_curr_desc = 0;
ff561eef 520
3a499481 521 dma_unmap_single(NULL, rx_desc->buf_ptr,
abe78717 522 rx_desc->buf_size, DMA_FROM_DEVICE);
8a578111
LB		 523 rxq->rx_desc_count--;
524 rx++;
b1dd9ca1 525
1fa38c58
LB		 526 mp->work_rx_refill |= 1 << rxq->index;
527
6b8f90c2
LB		 528 byte_cnt = rx_desc->byte_cnt;
529
468d09f8
DF		 530 /*
531 * Update statistics.
fc32b0e2
LB		 532 *
533 * Note that the descriptor byte count includes 2 dummy
534 * bytes automatically inserted by the hardware at the
535 * start of the packet (which we don't count), and a 4
536 * byte CRC at the end of the packet (which we do count).
468d09f8 537 */
1da177e4 538 stats->rx_packets++;
6b8f90c2 539 stats->rx_bytes += byte_cnt - 2;
96587661 540
1da177e4 541 /*
fc32b0e2
LB		 542 * In case we received a packet without first / last bits
543 * on, or the error summary bit is set, the packet needs
544 * to be dropped.
1da177e4 545 */
96587661 546 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 547 (RX_FIRST_DESC | RX_LAST_DESC))
96587661 548 || (cmd_sts & ERROR_SUMMARY)) {
1da177e4 549 stats->rx_dropped++;
fc32b0e2 550
96587661 551 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 552 (RX_FIRST_DESC | RX_LAST_DESC)) {
1da177e4 553 if (net_ratelimit())
fc32b0e2
LB		 554 dev_printk(KERN_ERR, &mp->dev->dev,
555 "received packet spanning "
556 "multiple descriptors\n");
1da177e4 557 }
fc32b0e2 558
96587661 559 if (cmd_sts & ERROR_SUMMARY)
1da177e4
LT		 560 stats->rx_errors++;
561
78fff83b 562 dev_kfree_skb(skb);
1da177e4
LT		 563 } else {
564 /*
565 * The -4 is for the CRC in the trailer of the
566 * received packet
567 */
6b8f90c2 568 skb_put(skb, byte_cnt - 2 - 4);
1da177e4 569
170e7108 570 if (cmd_sts & LAYER_4_CHECKSUM_OK)
1da177e4 571 skb->ip_summed = CHECKSUM_UNNECESSARY;
8a578111 572 skb->protocol = eth_type_trans(skb, mp->dev);
1da177e4 573 netif_receive_skb(skb);
1da177e4
LT		 574 }
575 }
fc32b0e2 576
1fa38c58
LB		 577 if (rx < budget)
578 mp->work_rx &= ~(1 << rxq->index);
579
8a578111 580 return rx;
1da177e4
LT		 581}
582
1fa38c58 583static int rxq_refill(struct rx_queue *rxq, int budget)
d0412d96 584{
1fa38c58 585 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1fa38c58 586 int refilled;
8a578111 587
1fa38c58
LB		 588 refilled = 0;
589 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
590 struct sk_buff *skb;
591 int unaligned;
592 int rx;
d0412d96 593
2bcb4b0f
LB		 594 skb = __skb_dequeue(&mp->rx_recycle);
595 if (skb == NULL)
596 skb = dev_alloc_skb(mp->skb_size +
597 dma_get_cache_alignment() - 1);
598
1fa38c58
LB		 599 if (skb == NULL) {
600 mp->work_rx_oom |= 1 << rxq->index;
601 goto oom;
602 }
d0412d96 603
1fa38c58
LB		 604 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
605 if (unaligned)
606 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
2257e05c 607
1fa38c58
LB		 608 refilled++;
609 rxq->rx_desc_count++;
c9df406f 610
1fa38c58
LB		 611 rx = rxq->rx_used_desc++;
612 if (rxq->rx_used_desc == rxq->rx_ring_size)
613 rxq->rx_used_desc = 0;
2257e05c 614
1fa38c58 615 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
2bcb4b0f
LB		 616 mp->skb_size, DMA_FROM_DEVICE);
617 rxq->rx_desc_area[rx].buf_size = mp->skb_size;
1fa38c58
LB		 618 rxq->rx_skb[rx] = skb;
619 wmb();
620 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
621 RX_ENABLE_INTERRUPT;
622 wmb();
2257e05c 623
1fa38c58
LB		 624 /*
625 * The hardware automatically prepends 2 bytes of
626 * dummy data to each received packet, so that the
627 * IP header ends up 16-byte aligned.
628 */
629 skb_reserve(skb, 2);
630 }
631
632 if (refilled < budget)
633 mp->work_rx_refill &= ~(1 << rxq->index);
634
635oom:
636 return refilled;
d0412d96
JC		 637}
638
c9df406f
LB		 639
640/* tx ***********************************************************************/
c9df406f 641static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 642{
13d64285 643 int frag;
1da177e4 644
c9df406f 645 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 646 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
647 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 648 return 1;
1da177e4 649 }
13d64285 650
c9df406f
LB		 651 return 0;
652}
7303fde8 653
13d64285 654static int txq_alloc_desc_index(struct tx_queue *txq)
c9df406f
LB		 655{
656 int tx_desc_curr;
d0412d96 657
13d64285 658 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
1da177e4 659
9da78745
LB		 660 tx_desc_curr = txq->tx_curr_desc++;
661 if (txq->tx_curr_desc == txq->tx_ring_size)
662 txq->tx_curr_desc = 0;
e4d00fa9 663
13d64285 664 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
468d09f8 665
c9df406f
LB		 666 return tx_desc_curr;
667}
468d09f8 668
13d64285 669static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 670{
13d64285 671 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 672 int frag;
1da177e4 673
13d64285
LB		 674 for (frag = 0; frag < nr_frags; frag++) {
675 skb_frag_t *this_frag;
676 int tx_index;
677 struct tx_desc *desc;
678
679 this_frag = &skb_shinfo(skb)->frags[frag];
680 tx_index = txq_alloc_desc_index(txq);
681 desc = &txq->tx_desc_area[tx_index];
682
683 /*
684 * The last fragment will generate an interrupt
685 * which will free the skb on TX completion.
686 */
687 if (frag == nr_frags - 1) {
688 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
689 ZERO_PADDING | TX_LAST_DESC |
690 TX_ENABLE_INTERRUPT;
13d64285
LB		 691 } else {
692 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
13d64285
LB		 693 }
694
c9df406f
LB		 695 desc->l4i_chk = 0;
696 desc->byte_cnt = this_frag->size;
697 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
698 this_frag->page_offset,
699 this_frag->size,
700 DMA_TO_DEVICE);
701 }
1da177e4
LT		 702}
703
c9df406f
LB		 704static inline __be16 sum16_as_be(__sum16 sum)
705{
706 return (__force __be16)sum;
707}
1da177e4 708
4df89bd5 709static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 710{
8fa89bf5 711 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 712 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 713 int tx_index;
cc9754b3 714 struct tx_desc *desc;
c9df406f 715 u32 cmd_sts;
4df89bd5 716 u16 l4i_chk;
c9df406f 717 int length;
1da177e4 718
cc9754b3 719 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
4df89bd5 720 l4i_chk = 0;
c9df406f
LB		 721
722 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4df89bd5 723 int tag_bytes;
e32b6617
LB		 724
725 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
726 skb->protocol != htons(ETH_P_8021Q));
c9df406f 727
4df89bd5
LB		 728 tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
729 if (unlikely(tag_bytes & ~12)) {
730 if (skb_checksum_help(skb) == 0)
731 goto no_csum;
732 kfree_skb(skb);
733 return 1;
734 }
c9df406f 735
4df89bd5 736 if (tag_bytes & 4)
e32b6617 737 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
4df89bd5 738 if (tag_bytes & 8)
e32b6617 739 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
4df89bd5
LB		 740
741 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
742 GEN_IP_V4_CHECKSUM |
743 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
e32b6617 744
c9df406f
LB		 745 switch (ip_hdr(skb)->protocol) {
746 case IPPROTO_UDP:
cc9754b3 747 cmd_sts |= UDP_FRAME;
4df89bd5 748 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
c9df406f
LB		 749 break;
750 case IPPROTO_TCP:
4df89bd5 751 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
c9df406f
LB		 752 break;
753 default:
754 BUG();
755 }
756 } else {
4df89bd5 757no_csum:
c9df406f 758 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 759 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 760 }
761
4df89bd5
LB		 762 tx_index = txq_alloc_desc_index(txq);
763 desc = &txq->tx_desc_area[tx_index];
764
765 if (nr_frags) {
766 txq_submit_frag_skb(txq, skb);
767 length = skb_headlen(skb);
768 } else {
769 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
770 length = skb->len;
771 }
772
773 desc->l4i_chk = l4i_chk;
774 desc->byte_cnt = length;
775 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
776
99ab08e0
LB		 777 __skb_queue_tail(&txq->tx_skb, skb);
778
c9df406f
LB		 779 /* ensure all other descriptors are written before first cmd_sts */
780 wmb();
781 desc->cmd_sts = cmd_sts;
782
1fa38c58
LB		 783 /* clear TX_END status */
784 mp->work_tx_end &= ~(1 << txq->index);
8fa89bf5 785
c9df406f
LB		 786 /* ensure all descriptors are written before poking hardware */
787 wmb();
13d64285 788 txq_enable(txq);
c9df406f 789
13d64285 790 txq->tx_desc_count += nr_frags + 1;
4df89bd5
LB		 791
792 return 0;
1da177e4 793}
1da177e4 794
fc32b0e2 795static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 796{
e5371493 797 struct mv643xx_eth_private *mp = netdev_priv(dev);
e5ef1de1 798 int queue;
13d64285 799 struct tx_queue *txq;
e5ef1de1 800 struct netdev_queue *nq;
afdb57a2 801
8fd89211
LB		 802 queue = skb_get_queue_mapping(skb);
803 txq = mp->txq + queue;
804 nq = netdev_get_tx_queue(dev, queue);
805
c9df406f 806 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
8fd89211 807 txq->tx_dropped++;
fc32b0e2
LB		 808 dev_printk(KERN_DEBUG, &dev->dev,
809 "failed to linearize skb with tiny "
810 "unaligned fragment\n");
c9df406f
LB		 811 return NETDEV_TX_BUSY;
812 }
813
17cd0a59 814 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
e5ef1de1
LB		 815 if (net_ratelimit())
816 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
3d6b35bc
LB		 817 kfree_skb(skb);
818 return NETDEV_TX_OK;
c9df406f
LB		 819 }
820
4df89bd5
LB		 821 if (!txq_submit_skb(txq, skb)) {
822 int entries_left;
823
824 txq->tx_bytes += skb->len;
825 txq->tx_packets++;
826 dev->trans_start = jiffies;
c9df406f 827
4df89bd5
LB		 828 entries_left = txq->tx_ring_size - txq->tx_desc_count;
829 if (entries_left < MAX_SKB_FRAGS + 1)
830 netif_tx_stop_queue(nq);
831 }
c9df406f 832
c9df406f 833 return NETDEV_TX_OK;
1da177e4
LT		 834}
835
c9df406f 836
1fa38c58
LB		 837/* tx napi ******************************************************************/
838static void txq_kick(struct tx_queue *txq)
839{
840 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 841 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 842 u32 hw_desc_ptr;
843 u32 expected_ptr;
844
8fd89211 845 __netif_tx_lock(nq, smp_processor_id());
1fa38c58 846
37a6084f 847 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1fa38c58
LB		 848 goto out;
849
37a6084f 850 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1fa38c58
LB		 851 expected_ptr = (u32)txq->tx_desc_dma +
852 txq->tx_curr_desc * sizeof(struct tx_desc);
853
854 if (hw_desc_ptr != expected_ptr)
855 txq_enable(txq);
856
857out:
8fd89211 858 __netif_tx_unlock(nq);
1fa38c58
LB		 859
860 mp->work_tx_end &= ~(1 << txq->index);
861}
862
863static int txq_reclaim(struct tx_queue *txq, int budget, int force)
864{
865 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 866 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 867 int reclaimed;
868
8fd89211 869 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 870
871 reclaimed = 0;
872 while (reclaimed < budget && txq->tx_desc_count > 0) {
873 int tx_index;
874 struct tx_desc *desc;
875 u32 cmd_sts;
876 struct sk_buff *skb;
1fa38c58
LB		 877
878 tx_index = txq->tx_used_desc;
879 desc = &txq->tx_desc_area[tx_index];
880 cmd_sts = desc->cmd_sts;
881
882 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
883 if (!force)
884 break;
885 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
886 }
887
888 txq->tx_used_desc = tx_index + 1;
889 if (txq->tx_used_desc == txq->tx_ring_size)
890 txq->tx_used_desc = 0;
891
892 reclaimed++;
893 txq->tx_desc_count--;
894
99ab08e0
LB		 895 skb = NULL;
896 if (cmd_sts & TX_LAST_DESC)
897 skb = __skb_dequeue(&txq->tx_skb);
1fa38c58
LB		 898
899 if (cmd_sts & ERROR_SUMMARY) {
900 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
901 mp->dev->stats.tx_errors++;
902 }
903
a418950c
LB		 904 if (cmd_sts & TX_FIRST_DESC) {
905 dma_unmap_single(NULL, desc->buf_ptr,
906 desc->byte_cnt, DMA_TO_DEVICE);
907 } else {
908 dma_unmap_page(NULL, desc->buf_ptr,
909 desc->byte_cnt, DMA_TO_DEVICE);
910 }
1fa38c58 911
2bcb4b0f
LB		 912 if (skb != NULL) {
913 if (skb_queue_len(&mp->rx_recycle) <
914 mp->default_rx_ring_size &&
915 skb_recycle_check(skb, mp->skb_size))
916 __skb_queue_head(&mp->rx_recycle, skb);
917 else
918 dev_kfree_skb(skb);
919 }
1fa38c58
LB		 920 }
921
8fd89211
LB		 922 __netif_tx_unlock(nq);
923
1fa38c58
LB		 924 if (reclaimed < budget)
925 mp->work_tx &= ~(1 << txq->index);
926
1fa38c58
LB		 927 return reclaimed;
928}
929
930
89df5fdc
LB		 931/* tx rate control **********************************************************/
932/*
933 * Set total maximum TX rate (shared by all TX queues for this port)
934 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
935 */
936static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
937{
938 int token_rate;
939 int mtu;
940 int bucket_size;
941
942 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
943 if (token_rate > 1023)
944 token_rate = 1023;
945
946 mtu = (mp->dev->mtu + 255) >> 8;
947 if (mtu > 63)
948 mtu = 63;
949
950 bucket_size = (burst + 255) >> 8;
951 if (bucket_size > 65535)
952 bucket_size = 65535;
953
457b1d5a
LB		 954 switch (mp->shared->tx_bw_control) {
955 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f
LB		 956 wrlp(mp, TX_BW_RATE, token_rate);
957 wrlp(mp, TX_BW_MTU, mtu);
958 wrlp(mp, TX_BW_BURST, bucket_size);
457b1d5a
LB		 959 break;
960 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f
LB		 961 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
962 wrlp(mp, TX_BW_MTU_MOVED, mtu);
963 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
457b1d5a 964 break;
1e881592 965 }
89df5fdc
LB		 966}
967
968static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
969{
970 struct mv643xx_eth_private *mp = txq_to_mp(txq);
971 int token_rate;
972 int bucket_size;
973
974 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
975 if (token_rate > 1023)
976 token_rate = 1023;
977
978 bucket_size = (burst + 255) >> 8;
979 if (bucket_size > 65535)
980 bucket_size = 65535;
981
37a6084f
LB		 982 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
983 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
89df5fdc
LB		 984}
985
986static void txq_set_fixed_prio_mode(struct tx_queue *txq)
987{
988 struct mv643xx_eth_private *mp = txq_to_mp(txq);
989 int off;
990 u32 val;
991
992 /*
993 * Turn on fixed priority mode.
994 */
457b1d5a
LB		 995 off = 0;
996 switch (mp->shared->tx_bw_control) {
997 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f 998 off = TXQ_FIX_PRIO_CONF;
457b1d5a
LB		 999 break;
1000 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f 1001 off = TXQ_FIX_PRIO_CONF_MOVED;
457b1d5a
LB		 1002 break;
1003 }
89df5fdc 1004
457b1d5a 1005 if (off) {
37a6084f 1006 val = rdlp(mp, off);
457b1d5a 1007 val |= 1 << txq->index;
37a6084f 1008 wrlp(mp, off, val);
457b1d5a 1009 }
89df5fdc
LB		 1010}
1011
1012static void txq_set_wrr(struct tx_queue *txq, int weight)
1013{
1014 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1015 int off;
1016 u32 val;
1017
1018 /*
1019 * Turn off fixed priority mode.
1020 */
457b1d5a
LB		 1021 off = 0;
1022 switch (mp->shared->tx_bw_control) {
1023 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f 1024 off = TXQ_FIX_PRIO_CONF;
457b1d5a
LB		 1025 break;
1026 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f 1027 off = TXQ_FIX_PRIO_CONF_MOVED;
457b1d5a
LB		 1028 break;
1029 }
89df5fdc 1030
457b1d5a 1031 if (off) {
37a6084f 1032 val = rdlp(mp, off);
457b1d5a 1033 val &= ~(1 << txq->index);
37a6084f 1034 wrlp(mp, off, val);
89df5fdc 1035
457b1d5a
LB		 1036 /*
1037 * Configure WRR weight for this queue.
1038 */
89df5fdc 1039
37a6084f 1040 val = rdlp(mp, off);
457b1d5a 1041 val = (val & ~0xff) | (weight & 0xff);
37a6084f 1042 wrlp(mp, TXQ_BW_WRR_CONF(txq->index), val);
457b1d5a 1043 }
89df5fdc
LB		 1044}
1045
1046
c9df406f 1047/* mii management interface *************************************************/
45c5d3bc
LB		 1048static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1049{
1050 struct mv643xx_eth_shared_private *msp = dev_id;
1051
1052 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1053 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1054 wake_up(&msp->smi_busy_wait);
1055 return IRQ_HANDLED;
1056 }
1057
1058 return IRQ_NONE;
1059}
c9df406f 1060
45c5d3bc 1061static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1da177e4 1062{
45c5d3bc
LB		 1063 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1064}
1da177e4 1065
45c5d3bc
LB		 1066static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1067{
1068 if (msp->err_interrupt == NO_IRQ) {
1069 int i;
c9df406f 1070
45c5d3bc
LB		 1071 for (i = 0; !smi_is_done(msp); i++) {
1072 if (i == 10)
1073 return -ETIMEDOUT;
1074 msleep(10);
c9df406f 1075 }
45c5d3bc
LB		 1076
1077 return 0;
1078 }
1079
ee04448d
LB		 1080 if (!smi_is_done(msp)) {
1081 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1082 msecs_to_jiffies(100));
1083 if (!smi_is_done(msp))
1084 return -ETIMEDOUT;
1085 }
45c5d3bc
LB		 1086
1087 return 0;
1088}
1089
ed94493f 1090static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
45c5d3bc 1091{
ed94493f 1092 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc
LB		 1093 void __iomem *smi_reg = msp->base + SMI_REG;
1094 int ret;
1095
45c5d3bc 1096 if (smi_wait_ready(msp)) {
10a9948d 1097 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f 1098 return -ETIMEDOUT;
1da177e4
LT		 1099 }
1100
fc32b0e2 1101 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 1102
45c5d3bc 1103 if (smi_wait_ready(msp)) {
10a9948d 1104 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f 1105 return -ETIMEDOUT;
45c5d3bc
LB		 1106 }
1107
1108 ret = readl(smi_reg);
1109 if (!(ret & SMI_READ_VALID)) {
10a9948d 1110 printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n");
ed94493f 1111 return -ENODEV;
c9df406f
LB		 1112 }
1113
ed94493f 1114 return ret & 0xffff;
1da177e4
LT		 1115}
1116
ed94493f 1117static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1da177e4 1118{
ed94493f 1119 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc 1120 void __iomem *smi_reg = msp->base + SMI_REG;
1da177e4 1121
45c5d3bc 1122 if (smi_wait_ready(msp)) {
10a9948d 1123 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
45c5d3bc 1124 return -ETIMEDOUT;
1da177e4
LT		 1125 }
1126
fc32b0e2 1127 writel(SMI_OPCODE_WRITE | (reg << 21) |
ed94493f 1128 (addr << 16) | (val & 0xffff), smi_reg);
45c5d3bc 1129
ed94493f 1130 if (smi_wait_ready(msp)) {
10a9948d 1131 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f
LB		 1132 return -ETIMEDOUT;
1133 }
45c5d3bc
LB		 1134
1135 return 0;
c9df406f 1136}
1da177e4 1137
c9df406f 1138
8fd89211
LB		 1139/* statistics ***************************************************************/
1140static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1141{
1142 struct mv643xx_eth_private *mp = netdev_priv(dev);
1143 struct net_device_stats *stats = &dev->stats;
1144 unsigned long tx_packets = 0;
1145 unsigned long tx_bytes = 0;
1146 unsigned long tx_dropped = 0;
1147 int i;
1148
1149 for (i = 0; i < mp->txq_count; i++) {
1150 struct tx_queue *txq = mp->txq + i;
1151
1152 tx_packets += txq->tx_packets;
1153 tx_bytes += txq->tx_bytes;
1154 tx_dropped += txq->tx_dropped;
1155 }
1156
1157 stats->tx_packets = tx_packets;
1158 stats->tx_bytes = tx_bytes;
1159 stats->tx_dropped = tx_dropped;
1160
1161 return stats;
1162}
1163
fc32b0e2 1164static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1165{
fc32b0e2 1166 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1167}
1168
fc32b0e2 1169static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1170{
fc32b0e2
LB		 1171 int i;
1172
1173 for (i = 0; i < 0x80; i += 4)
1174 mib_read(mp, i);
c9df406f 1175}
d0412d96 1176
fc32b0e2 1177static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1178{
e5371493 1179 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1180
4ff3495a 1181 spin_lock(&mp->mib_counters_lock);
fc32b0e2
LB		 1182 p->good_octets_received += mib_read(mp, 0x00);
1183 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1184 p->bad_octets_received += mib_read(mp, 0x08);
1185 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1186 p->good_frames_received += mib_read(mp, 0x10);
1187 p->bad_frames_received += mib_read(mp, 0x14);
1188 p->broadcast_frames_received += mib_read(mp, 0x18);
1189 p->multicast_frames_received += mib_read(mp, 0x1c);
1190 p->frames_64_octets += mib_read(mp, 0x20);
1191 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1192 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1193 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1194 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1195 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1196 p->good_octets_sent += mib_read(mp, 0x38);
1197 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1198 p->good_frames_sent += mib_read(mp, 0x40);
1199 p->excessive_collision += mib_read(mp, 0x44);
1200 p->multicast_frames_sent += mib_read(mp, 0x48);
1201 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1202 p->unrec_mac_control_received += mib_read(mp, 0x50);
1203 p->fc_sent += mib_read(mp, 0x54);
1204 p->good_fc_received += mib_read(mp, 0x58);
1205 p->bad_fc_received += mib_read(mp, 0x5c);
1206 p->undersize_received += mib_read(mp, 0x60);
1207 p->fragments_received += mib_read(mp, 0x64);
1208 p->oversize_received += mib_read(mp, 0x68);
1209 p->jabber_received += mib_read(mp, 0x6c);
1210 p->mac_receive_error += mib_read(mp, 0x70);
1211 p->bad_crc_event += mib_read(mp, 0x74);
1212 p->collision += mib_read(mp, 0x78);
1213 p->late_collision += mib_read(mp, 0x7c);
4ff3495a
LB		 1214 spin_unlock(&mp->mib_counters_lock);
1215
1216 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1217}
1218
1219static void mib_counters_timer_wrapper(unsigned long _mp)
1220{
1221 struct mv643xx_eth_private *mp = (void *)_mp;
1222
1223 mib_counters_update(mp);
d0412d96
JC		 1224}
1225
c9df406f
LB		 1226
1227/* ethtool ******************************************************************/
e5371493 1228struct mv643xx_eth_stats {
c9df406f
LB		 1229 char stat_string[ETH_GSTRING_LEN];
1230 int sizeof_stat;
16820054
LB		 1231 int netdev_off;
1232 int mp_off;
c9df406f
LB		 1233};
1234
16820054
LB		 1235#define SSTAT(m) \
1236 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1237 offsetof(struct net_device, stats.m), -1 }
1238
1239#define MIBSTAT(m) \
1240 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1241 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1242
1243static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1244 SSTAT(rx_packets),
1245 SSTAT(tx_packets),
1246 SSTAT(rx_bytes),
1247 SSTAT(tx_bytes),
1248 SSTAT(rx_errors),
1249 SSTAT(tx_errors),
1250 SSTAT(rx_dropped),
1251 SSTAT(tx_dropped),
1252 MIBSTAT(good_octets_received),
1253 MIBSTAT(bad_octets_received),
1254 MIBSTAT(internal_mac_transmit_err),
1255 MIBSTAT(good_frames_received),
1256 MIBSTAT(bad_frames_received),
1257 MIBSTAT(broadcast_frames_received),
1258 MIBSTAT(multicast_frames_received),
1259 MIBSTAT(frames_64_octets),
1260 MIBSTAT(frames_65_to_127_octets),
1261 MIBSTAT(frames_128_to_255_octets),
1262 MIBSTAT(frames_256_to_511_octets),
1263 MIBSTAT(frames_512_to_1023_octets),
1264 MIBSTAT(frames_1024_to_max_octets),
1265 MIBSTAT(good_octets_sent),
1266 MIBSTAT(good_frames_sent),
1267 MIBSTAT(excessive_collision),
1268 MIBSTAT(multicast_frames_sent),
1269 MIBSTAT(broadcast_frames_sent),
1270 MIBSTAT(unrec_mac_control_received),
1271 MIBSTAT(fc_sent),
1272 MIBSTAT(good_fc_received),
1273 MIBSTAT(bad_fc_received),
1274 MIBSTAT(undersize_received),
1275 MIBSTAT(fragments_received),
1276 MIBSTAT(oversize_received),
1277 MIBSTAT(jabber_received),
1278 MIBSTAT(mac_receive_error),
1279 MIBSTAT(bad_crc_event),
1280 MIBSTAT(collision),
1281 MIBSTAT(late_collision),
c9df406f
LB		 1282};
1283
10a9948d
LB		 1284static int
1285mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
d0412d96 1286{
e5371493 1287 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96
JC		 1288 int err;
1289
ed94493f
LB		 1290 err = phy_read_status(mp->phy);
1291 if (err == 0)
1292 err = phy_ethtool_gset(mp->phy, cmd);
d0412d96 1293
fc32b0e2
LB		 1294 /*
1295 * The MAC does not support 1000baseT_Half.
1296 */
d0412d96
JC		 1297 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1298 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1299
1300 return err;
1301}
1302
10a9948d
LB		 1303static int
1304mv643xx_eth_get_settings_phyless(struct net_device *dev,
1305 struct ethtool_cmd *cmd)
bedfe324 1306{
81600eea
LB		 1307 struct mv643xx_eth_private *mp = netdev_priv(dev);
1308 u32 port_status;
1309
37a6084f 1310 port_status = rdlp(mp, PORT_STATUS);
81600eea 1311
bedfe324
LB		 1312 cmd->supported = SUPPORTED_MII;
1313 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1314 switch (port_status & PORT_SPEED_MASK) {
1315 case PORT_SPEED_10:
1316 cmd->speed = SPEED_10;
1317 break;
1318 case PORT_SPEED_100:
1319 cmd->speed = SPEED_100;
1320 break;
1321 case PORT_SPEED_1000:
1322 cmd->speed = SPEED_1000;
1323 break;
1324 default:
1325 cmd->speed = -1;
1326 break;
1327 }
1328 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1329 cmd->port = PORT_MII;
1330 cmd->phy_address = 0;
1331 cmd->transceiver = XCVR_INTERNAL;
1332 cmd->autoneg = AUTONEG_DISABLE;
1333 cmd->maxtxpkt = 1;
1334 cmd->maxrxpkt = 1;
1335
1336 return 0;
1337}
1338
10a9948d
LB		 1339static int
1340mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1341{
e5371493 1342 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6 1343
fc32b0e2
LB		 1344 /*
1345 * The MAC does not support 1000baseT_Half.
1346 */
1347 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1348
ed94493f 1349 return phy_ethtool_sset(mp->phy, cmd);
c9df406f 1350}
1da177e4 1351
10a9948d
LB		 1352static int
1353mv643xx_eth_set_settings_phyless(struct net_device *dev,
1354 struct ethtool_cmd *cmd)
bedfe324
LB		 1355{
1356 return -EINVAL;
1357}
1358
fc32b0e2
LB		 1359static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1360 struct ethtool_drvinfo *drvinfo)
c9df406f 1361{
e5371493
LB		 1362 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1363 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1364 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1365 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1366 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1367}
1da177e4 1368
fc32b0e2 1369static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1370{
e5371493 1371 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1372
ed94493f 1373 return genphy_restart_aneg(mp->phy);
c9df406f 1374}
1da177e4 1375
bedfe324
LB		 1376static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1377{
1378 return -EINVAL;
1379}
1380
c9df406f
LB		 1381static u32 mv643xx_eth_get_link(struct net_device *dev)
1382{
ed94493f 1383 return !!netif_carrier_ok(dev);
bedfe324
LB		 1384}
1385
fc32b0e2
LB		 1386static void mv643xx_eth_get_strings(struct net_device *dev,
1387 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1388{
1389 int i;
1da177e4 1390
fc32b0e2
LB		 1391 if (stringset == ETH_SS_STATS) {
1392 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1393 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1394 mv643xx_eth_stats[i].stat_string,
e5371493 1395 ETH_GSTRING_LEN);
c9df406f 1396 }
c9df406f
LB		 1397 }
1398}
1da177e4 1399
fc32b0e2
LB		 1400static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1401 struct ethtool_stats *stats,
1402 uint64_t *data)
c9df406f 1403{
b9873841 1404 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1405 int i;
1da177e4 1406
8fd89211 1407 mv643xx_eth_get_stats(dev);
fc32b0e2 1408 mib_counters_update(mp);
1da177e4 1409
16820054
LB		 1410 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1411 const struct mv643xx_eth_stats *stat;
1412 void *p;
1413
1414 stat = mv643xx_eth_stats + i;
1415
1416 if (stat->netdev_off >= 0)
1417 p = ((void *)mp->dev) + stat->netdev_off;
1418 else
1419 p = ((void *)mp) + stat->mp_off;
1420
1421 data[i] = (stat->sizeof_stat == 8) ?
1422 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1423 }
c9df406f 1424}
1da177e4 1425
fc32b0e2 1426static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1427{
fc32b0e2 1428 if (sset == ETH_SS_STATS)
16820054 1429 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1430
1431 return -EOPNOTSUPP;
c9df406f 1432}
1da177e4 1433
e5371493 1434static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1435 .get_settings = mv643xx_eth_get_settings,
1436 .set_settings = mv643xx_eth_set_settings,
1437 .get_drvinfo = mv643xx_eth_get_drvinfo,
1438 .nway_reset = mv643xx_eth_nway_reset,
1439 .get_link = mv643xx_eth_get_link,
c9df406f 1440 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1441 .get_strings = mv643xx_eth_get_strings,
1442 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1443 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1444};
1da177e4 1445
bedfe324
LB		 1446static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1447 .get_settings = mv643xx_eth_get_settings_phyless,
1448 .set_settings = mv643xx_eth_set_settings_phyless,
1449 .get_drvinfo = mv643xx_eth_get_drvinfo,
1450 .nway_reset = mv643xx_eth_nway_reset_phyless,
ed94493f 1451 .get_link = mv643xx_eth_get_link,
bedfe324
LB		 1452 .set_sg = ethtool_op_set_sg,
1453 .get_strings = mv643xx_eth_get_strings,
1454 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1455 .get_sset_count = mv643xx_eth_get_sset_count,
1456};
1457
bea3348e 1458
c9df406f 1459/* address handling *********************************************************/
5daffe94 1460static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1461{
c9df406f
LB		 1462 unsigned int mac_h;
1463 unsigned int mac_l;
1da177e4 1464
37a6084f
LB		 1465 mac_h = rdlp(mp, MAC_ADDR_HIGH);
1466 mac_l = rdlp(mp, MAC_ADDR_LOW);
1da177e4 1467
5daffe94
LB		 1468 addr[0] = (mac_h >> 24) & 0xff;
1469 addr[1] = (mac_h >> 16) & 0xff;
1470 addr[2] = (mac_h >> 8) & 0xff;
1471 addr[3] = mac_h & 0xff;
1472 addr[4] = (mac_l >> 8) & 0xff;
1473 addr[5] = mac_l & 0xff;
c9df406f 1474}
1da177e4 1475
e5371493 1476static void init_mac_tables(struct mv643xx_eth_private *mp)
c9df406f 1477{
fc32b0e2 1478 int i;
1da177e4 1479
fc32b0e2
LB		 1480 for (i = 0; i < 0x100; i += 4) {
1481 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1482 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
c9df406f 1483 }
fc32b0e2
LB		 1484
1485 for (i = 0; i < 0x10; i += 4)
1486 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
c9df406f 1487}
d0412d96 1488
e5371493 1489static void set_filter_table_entry(struct mv643xx_eth_private *mp,
fc32b0e2 1490 int table, unsigned char entry)
c9df406f
LB		 1491{
1492 unsigned int table_reg;
ab4384a6 1493
c9df406f 1494 /* Set "accepts frame bit" at specified table entry */
fc32b0e2
LB		 1495 table_reg = rdl(mp, table + (entry & 0xfc));
1496 table_reg |= 0x01 << (8 * (entry & 3));
1497 wrl(mp, table + (entry & 0xfc), table_reg);
1da177e4
LT		 1498}
1499
5daffe94 1500static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1da177e4 1501{
c9df406f
LB		 1502 unsigned int mac_h;
1503 unsigned int mac_l;
1504 int table;
1da177e4 1505
fc32b0e2
LB		 1506 mac_l = (addr[4] << 8) | addr[5];
1507 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
ff561eef 1508
37a6084f
LB		 1509 wrlp(mp, MAC_ADDR_LOW, mac_l);
1510 wrlp(mp, MAC_ADDR_HIGH, mac_h);
1da177e4 1511
fc32b0e2 1512 table = UNICAST_TABLE(mp->port_num);
5daffe94 1513 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1da177e4
LT		 1514}
1515
fc32b0e2 1516static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1da177e4 1517{
e5371493 1518 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1519
fc32b0e2
LB		 1520 /* +2 is for the offset of the HW addr type */
1521 memcpy(dev->dev_addr, addr + 2, 6);
1522
cc9754b3
LB		 1523 init_mac_tables(mp);
1524 uc_addr_set(mp, dev->dev_addr);
1da177e4
LT		 1525
1526 return 0;
1527}
1528
69876569
LB		 1529static int addr_crc(unsigned char *addr)
1530{
1531 int crc = 0;
1532 int i;
1533
1534 for (i = 0; i < 6; i++) {
1535 int j;
1536
1537 crc = (crc ^ addr[i]) << 8;
1538 for (j = 7; j >= 0; j--) {
1539 if (crc & (0x100 << j))
1540 crc ^= 0x107 << j;
1541 }
1542 }
1543
1544 return crc;
1545}
1546
fc32b0e2 1547static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1da177e4 1548{
fc32b0e2
LB		 1549 struct mv643xx_eth_private *mp = netdev_priv(dev);
1550 u32 port_config;
1551 struct dev_addr_list *addr;
1552 int i;
c8aaea25 1553
37a6084f 1554 port_config = rdlp(mp, PORT_CONFIG);
fc32b0e2
LB		 1555 if (dev->flags & IFF_PROMISC)
1556 port_config |= UNICAST_PROMISCUOUS_MODE;
1557 else
1558 port_config &= ~UNICAST_PROMISCUOUS_MODE;
37a6084f 1559 wrlp(mp, PORT_CONFIG, port_config);
1da177e4 1560
fc32b0e2
LB		 1561 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1562 int port_num = mp->port_num;
1563 u32 accept = 0x01010101;
c8aaea25 1564
fc32b0e2
LB		 1565 for (i = 0; i < 0x100; i += 4) {
1566 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1567 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1568 }
1569 return;
1570 }
c8aaea25 1571
fc32b0e2
LB		 1572 for (i = 0; i < 0x100; i += 4) {
1573 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1574 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1da177e4
LT		 1575 }
1576
fc32b0e2
LB		 1577 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1578 u8 *a = addr->da_addr;
1579 int table;
324ff2c1 1580
fc32b0e2
LB		 1581 if (addr->da_addrlen != 6)
1582 continue;
1da177e4 1583
fc32b0e2
LB		 1584 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1585 table = SPECIAL_MCAST_TABLE(mp->port_num);
1586 set_filter_table_entry(mp, table, a[5]);
1587 } else {
1588 int crc = addr_crc(a);
1da177e4 1589
fc32b0e2
LB		 1590 table = OTHER_MCAST_TABLE(mp->port_num);
1591 set_filter_table_entry(mp, table, crc);
1592 }
1593 }
c9df406f 1594}
c8aaea25 1595
c8aaea25 1596
c9df406f 1597/* rx/tx queue initialisation ***********************************************/
64da80a2 1598static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1599{
64da80a2 1600 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1601 struct rx_desc *rx_desc;
1602 int size;
c9df406f
LB		 1603 int i;
1604
64da80a2
LB		 1605 rxq->index = index;
1606
8a578111
LB		 1607 rxq->rx_ring_size = mp->default_rx_ring_size;
1608
1609 rxq->rx_desc_count = 0;
1610 rxq->rx_curr_desc = 0;
1611 rxq->rx_used_desc = 0;
1612
1613 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1614
f7981c1c 1615 if (index == 0 && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1616 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1617 mp->rx_desc_sram_size);
1618 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1619 } else {
1620 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1621 &rxq->rx_desc_dma,
1622 GFP_KERNEL);
f7ea3337
PJ		 1623 }
1624
8a578111
LB		 1625 if (rxq->rx_desc_area == NULL) {
1626 dev_printk(KERN_ERR, &mp->dev->dev,
1627 "can't allocate rx ring (%d bytes)\n", size);
1628 goto out;
1629 }
1630 memset(rxq->rx_desc_area, 0, size);
1da177e4 1631
8a578111
LB		 1632 rxq->rx_desc_area_size = size;
1633 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1634 GFP_KERNEL);
1635 if (rxq->rx_skb == NULL) {
1636 dev_printk(KERN_ERR, &mp->dev->dev,
1637 "can't allocate rx skb ring\n");
1638 goto out_free;
1639 }
1640
1641 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1642 for (i = 0; i < rxq->rx_ring_size; i++) {
9da78745
LB		 1643 int nexti;
1644
1645 nexti = i + 1;
1646 if (nexti == rxq->rx_ring_size)
1647 nexti = 0;
1648
8a578111
LB		 1649 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1650 nexti * sizeof(struct rx_desc);
1651 }
1652
8a578111
LB		 1653 return 0;
1654
1655
1656out_free:
f7981c1c 1657 if (index == 0 && size <= mp->rx_desc_sram_size)
8a578111
LB		 1658 iounmap(rxq->rx_desc_area);
1659 else
1660 dma_free_coherent(NULL, size,
1661 rxq->rx_desc_area,
1662 rxq->rx_desc_dma);
1663
1664out:
1665 return -ENOMEM;
c9df406f 1666}
c8aaea25 1667
8a578111 1668static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1669{
8a578111
LB		 1670 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1671 int i;
1672
1673 rxq_disable(rxq);
c8aaea25 1674
8a578111
LB		 1675 for (i = 0; i < rxq->rx_ring_size; i++) {
1676 if (rxq->rx_skb[i]) {
1677 dev_kfree_skb(rxq->rx_skb[i]);
1678 rxq->rx_desc_count--;
1da177e4 1679 }
c8aaea25 1680 }
1da177e4 1681
8a578111
LB		 1682 if (rxq->rx_desc_count) {
1683 dev_printk(KERN_ERR, &mp->dev->dev,
1684 "error freeing rx ring -- %d skbs stuck\n",
1685 rxq->rx_desc_count);
1686 }
1687
f7981c1c 1688 if (rxq->index == 0 &&
64da80a2 1689 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1690 iounmap(rxq->rx_desc_area);
c9df406f 1691 else
8a578111
LB		 1692 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1693 rxq->rx_desc_area, rxq->rx_desc_dma);
1694
1695 kfree(rxq->rx_skb);
c9df406f 1696}
1da177e4 1697
3d6b35bc 1698static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1699{
3d6b35bc 1700 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1701 struct tx_desc *tx_desc;
1702 int size;
c9df406f 1703 int i;
1da177e4 1704
3d6b35bc
LB		 1705 txq->index = index;
1706
13d64285
LB		 1707 txq->tx_ring_size = mp->default_tx_ring_size;
1708
1709 txq->tx_desc_count = 0;
1710 txq->tx_curr_desc = 0;
1711 txq->tx_used_desc = 0;
1712
1713 size = txq->tx_ring_size * sizeof(struct tx_desc);
1714
f7981c1c 1715 if (index == 0 && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1716 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1717 mp->tx_desc_sram_size);
1718 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1719 } else {
1720 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1721 &txq->tx_desc_dma,
1722 GFP_KERNEL);
1723 }
1724
1725 if (txq->tx_desc_area == NULL) {
1726 dev_printk(KERN_ERR, &mp->dev->dev,
1727 "can't allocate tx ring (%d bytes)\n", size);
99ab08e0 1728 return -ENOMEM;
c9df406f 1729 }
13d64285
LB		 1730 memset(txq->tx_desc_area, 0, size);
1731
1732 txq->tx_desc_area_size = size;
13d64285
LB		 1733
1734 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1735 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 1736 struct tx_desc *txd = tx_desc + i;
9da78745
LB		 1737 int nexti;
1738
1739 nexti = i + 1;
1740 if (nexti == txq->tx_ring_size)
1741 nexti = 0;
6b368f68
LB		 1742
1743 txd->cmd_sts = 0;
1744 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 1745 nexti * sizeof(struct tx_desc);
1746 }
1747
99ab08e0 1748 skb_queue_head_init(&txq->tx_skb);
c9df406f 1749
99ab08e0 1750 return 0;
c8aaea25 1751}
1da177e4 1752
13d64285 1753static void txq_deinit(struct tx_queue *txq)
c9df406f 1754{
13d64285 1755 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 1756
13d64285 1757 txq_disable(txq);
1fa38c58 1758 txq_reclaim(txq, txq->tx_ring_size, 1);
1da177e4 1759
13d64285 1760 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 1761
f7981c1c 1762 if (txq->index == 0 &&
3d6b35bc 1763 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 1764 iounmap(txq->tx_desc_area);
c9df406f 1765 else
13d64285
LB		 1766 dma_free_coherent(NULL, txq->tx_desc_area_size,
1767 txq->tx_desc_area, txq->tx_desc_dma);
c9df406f 1768}
1da177e4 1769
1da177e4 1770
c9df406f 1771/* netdev ops and related ***************************************************/
1fa38c58
LB		 1772static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1773{
1774 u32 int_cause;
1775 u32 int_cause_ext;
1776
37a6084f 1777 int_cause = rdlp(mp, INT_CAUSE) & (INT_TX_END | INT_RX | INT_EXT);
1fa38c58
LB		 1778 if (int_cause == 0)
1779 return 0;
1780
1781 int_cause_ext = 0;
1782 if (int_cause & INT_EXT)
37a6084f 1783 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
1fa38c58
LB		 1784
1785 int_cause &= INT_TX_END | INT_RX;
1786 if (int_cause) {
37a6084f 1787 wrlp(mp, INT_CAUSE, ~int_cause);
1fa38c58 1788 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
37a6084f 1789 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1fa38c58
LB		 1790 mp->work_rx |= (int_cause & INT_RX) >> 2;
1791 }
1792
1793 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1794 if (int_cause_ext) {
37a6084f 1795 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1fa38c58
LB		 1796 if (int_cause_ext & INT_EXT_LINK_PHY)
1797 mp->work_link = 1;
1798 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1799 }
1800
1801 return 1;
1802}
1803
1804static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1805{
1806 struct net_device *dev = (struct net_device *)dev_id;
1807 struct mv643xx_eth_private *mp = netdev_priv(dev);
1808
1809 if (unlikely(!mv643xx_eth_collect_events(mp)))
1810 return IRQ_NONE;
1811
37a6084f 1812 wrlp(mp, INT_MASK, 0);
1fa38c58
LB		 1813 napi_schedule(&mp->napi);
1814
1815 return IRQ_HANDLED;
1816}
1817
2f7eb47a
LB		 1818static void handle_link_event(struct mv643xx_eth_private *mp)
1819{
1820 struct net_device *dev = mp->dev;
1821 u32 port_status;
1822 int speed;
1823 int duplex;
1824 int fc;
1825
37a6084f 1826 port_status = rdlp(mp, PORT_STATUS);
2f7eb47a
LB		 1827 if (!(port_status & LINK_UP)) {
1828 if (netif_carrier_ok(dev)) {
1829 int i;
1830
1831 printk(KERN_INFO "%s: link down\n", dev->name);
1832
1833 netif_carrier_off(dev);
2f7eb47a 1834
f7981c1c 1835 for (i = 0; i < mp->txq_count; i++) {
2f7eb47a
LB		 1836 struct tx_queue *txq = mp->txq + i;
1837
1fa38c58 1838 txq_reclaim(txq, txq->tx_ring_size, 1);
f7981c1c 1839 txq_reset_hw_ptr(txq);
2f7eb47a
LB		 1840 }
1841 }
1842 return;
1843 }
1844
1845 switch (port_status & PORT_SPEED_MASK) {
1846 case PORT_SPEED_10:
1847 speed = 10;
1848 break;
1849 case PORT_SPEED_100:
1850 speed = 100;
1851 break;
1852 case PORT_SPEED_1000:
1853 speed = 1000;
1854 break;
1855 default:
1856 speed = -1;
1857 break;
1858 }
1859 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1860 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1861
1862 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1863 "flow control %sabled\n", dev->name,
1864 speed, duplex ? "full" : "half",
1865 fc ? "en" : "dis");
1866
4fdeca3f 1867 if (!netif_carrier_ok(dev))
2f7eb47a 1868 netif_carrier_on(dev);
2f7eb47a
LB		 1869}
1870
1fa38c58 1871static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
c9df406f 1872{
1fa38c58
LB		 1873 struct mv643xx_eth_private *mp;
1874 int work_done;
ce4e2e45 1875
1fa38c58 1876 mp = container_of(napi, struct mv643xx_eth_private, napi);
fc32b0e2 1877
1fa38c58
LB		 1878 mp->work_rx_refill |= mp->work_rx_oom;
1879 mp->work_rx_oom = 0;
1da177e4 1880
1fa38c58
LB		 1881 work_done = 0;
1882 while (work_done < budget) {
1883 u8 queue_mask;
1884 int queue;
1885 int work_tbd;
1886
1887 if (mp->work_link) {
1888 mp->work_link = 0;
1889 handle_link_event(mp);
1890 continue;
1891 }
1da177e4 1892
1fa38c58
LB		 1893 queue_mask = mp->work_tx | mp->work_tx_end |
1894 mp->work_rx | mp->work_rx_refill;
1895 if (!queue_mask) {
1896 if (mv643xx_eth_collect_events(mp))
1897 continue;
1898 break;
1899 }
1da177e4 1900
1fa38c58
LB		 1901 queue = fls(queue_mask) - 1;
1902 queue_mask = 1 << queue;
1903
1904 work_tbd = budget - work_done;
1905 if (work_tbd > 16)
1906 work_tbd = 16;
1907
1908 if (mp->work_tx_end & queue_mask) {
1909 txq_kick(mp->txq + queue);
1910 } else if (mp->work_tx & queue_mask) {
1911 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
1912 txq_maybe_wake(mp->txq + queue);
1913 } else if (mp->work_rx & queue_mask) {
1914 work_done += rxq_process(mp->rxq + queue, work_tbd);
1915 } else if (mp->work_rx_refill & queue_mask) {
1916 work_done += rxq_refill(mp->rxq + queue, work_tbd);
1917 } else {
1918 BUG();
1919 }
84dd619e 1920 }
fc32b0e2 1921
1fa38c58
LB		 1922 if (work_done < budget) {
1923 if (mp->work_rx_oom)
1924 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
1925 napi_complete(napi);
37a6084f 1926 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
226bb6b7 1927 }
3d6b35bc 1928
1fa38c58
LB		 1929 return work_done;
1930}
8fa89bf5 1931
1fa38c58
LB		 1932static inline void oom_timer_wrapper(unsigned long data)
1933{
1934 struct mv643xx_eth_private *mp = (void *)data;
1da177e4 1935
1fa38c58 1936 napi_schedule(&mp->napi);
1da177e4
LT		 1937}
1938
e5371493 1939static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 1940{
45c5d3bc
LB		 1941 int data;
1942
ed94493f 1943 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc
LB		 1944 if (data < 0)
1945 return;
1da177e4 1946
7f106c1d 1947 data |= BMCR_RESET;
ed94493f 1948 if (phy_write(mp->phy, MII_BMCR, data) < 0)
45c5d3bc 1949 return;
1da177e4 1950
c9df406f 1951 do {
ed94493f 1952 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc 1953 } while (data >= 0 && data & BMCR_RESET);
1da177e4
LT		 1954}
1955
fc32b0e2 1956static void port_start(struct mv643xx_eth_private *mp)
1da177e4 1957{
d0412d96 1958 u32 pscr;
8a578111 1959 int i;
1da177e4 1960
bedfe324
LB		 1961 /*
1962 * Perform PHY reset, if there is a PHY.
1963 */
ed94493f 1964 if (mp->phy != NULL) {
bedfe324
LB		 1965 struct ethtool_cmd cmd;
1966
1967 mv643xx_eth_get_settings(mp->dev, &cmd);
1968 phy_reset(mp);
1969 mv643xx_eth_set_settings(mp->dev, &cmd);
1970 }
1da177e4 1971
81600eea
LB		 1972 /*
1973 * Configure basic link parameters.
1974 */
37a6084f 1975 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 1976
1977 pscr |= SERIAL_PORT_ENABLE;
37a6084f 1978 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 1979
1980 pscr |= DO_NOT_FORCE_LINK_FAIL;
ed94493f 1981 if (mp->phy == NULL)
81600eea 1982 pscr |= FORCE_LINK_PASS;
37a6084f 1983 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea 1984
37a6084f 1985 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
81600eea 1986
13d64285
LB		 1987 /*
1988 * Configure TX path and queues.
1989 */
89df5fdc 1990 tx_set_rate(mp, 1000000000, 16777216);
f7981c1c 1991 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc 1992 struct tx_queue *txq = mp->txq + i;
13d64285 1993
6b368f68 1994 txq_reset_hw_ptr(txq);
89df5fdc
LB		 1995 txq_set_rate(txq, 1000000000, 16777216);
1996 txq_set_fixed_prio_mode(txq);
13d64285
LB		 1997 }
1998
fc32b0e2
LB		 1999 /*
2000 * Add configured unicast address to address filter table.
2001 */
2002 uc_addr_set(mp, mp->dev->dev_addr);
1da177e4 2003
d9a073ea
LB		 2004 /*
2005 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
170e7108
LB		 2006 * frames to RX queue #0, and include the pseudo-header when
2007 * calculating receive checksums.
d9a073ea 2008 */
37a6084f 2009 wrlp(mp, PORT_CONFIG, 0x02000000);
01999873 2010
376489a2
LB		 2011 /*
2012 * Treat BPDUs as normal multicasts, and disable partition mode.
2013 */
37a6084f 2014 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
01999873 2015
8a578111 2016 /*
64da80a2 2017 * Enable the receive queues.
8a578111 2018 */
f7981c1c 2019 for (i = 0; i < mp->rxq_count; i++) {
64da80a2 2020 struct rx_queue *rxq = mp->rxq + i;
8a578111 2021 u32 addr;
1da177e4 2022
8a578111
LB		 2023 addr = (u32)rxq->rx_desc_dma;
2024 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
37a6084f 2025 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
1da177e4 2026
8a578111
LB		 2027 rxq_enable(rxq);
2028 }
1da177e4
LT		 2029}
2030
ffd86bbe 2031static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 2032{
c9df406f 2033 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
773fc3ee 2034 u32 val;
1da177e4 2035
37a6084f 2036 val = rdlp(mp, SDMA_CONFIG);
773fc3ee
LB		 2037 if (mp->shared->extended_rx_coal_limit) {
2038 if (coal > 0xffff)
2039 coal = 0xffff;
2040 val &= ~0x023fff80;
2041 val |= (coal & 0x8000) << 10;
2042 val |= (coal & 0x7fff) << 7;
2043 } else {
2044 if (coal > 0x3fff)
2045 coal = 0x3fff;
2046 val &= ~0x003fff00;
2047 val |= (coal & 0x3fff) << 8;
2048 }
37a6084f 2049 wrlp(mp, SDMA_CONFIG, val);
1da177e4
LT		 2050}
2051
ffd86bbe 2052static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 2053{
c9df406f 2054 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 2055
fc32b0e2
LB		 2056 if (coal > 0x3fff)
2057 coal = 0x3fff;
37a6084f 2058 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, (coal & 0x3fff) << 4);
16e03018
DF		 2059}
2060
2bcb4b0f
LB		 2061static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2062{
2063 int skb_size;
2064
2065 /*
2066 * Reserve 2+14 bytes for an ethernet header (the hardware
2067 * automatically prepends 2 bytes of dummy data to each
2068 * received packet), 16 bytes for up to four VLAN tags, and
2069 * 4 bytes for the trailing FCS -- 36 bytes total.
2070 */
2071 skb_size = mp->dev->mtu + 36;
2072
2073 /*
2074 * Make sure that the skb size is a multiple of 8 bytes, as
2075 * the lower three bits of the receive descriptor's buffer
2076 * size field are ignored by the hardware.
2077 */
2078 mp->skb_size = (skb_size + 7) & ~7;
2079}
2080
c9df406f 2081static int mv643xx_eth_open(struct net_device *dev)
16e03018 2082{
e5371493 2083 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2084 int err;
64da80a2 2085 int i;
16e03018 2086
37a6084f
LB		 2087 wrlp(mp, INT_CAUSE, 0);
2088 wrlp(mp, INT_CAUSE_EXT, 0);
2089 rdlp(mp, INT_CAUSE_EXT);
c9df406f 2090
fc32b0e2 2091 err = request_irq(dev->irq, mv643xx_eth_irq,
2a1867a7 2092 IRQF_SHARED, dev->name, dev);
c9df406f 2093 if (err) {
fc32b0e2 2094 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 2095 return -EAGAIN;
16e03018
DF		 2096 }
2097
fc32b0e2 2098 init_mac_tables(mp);
16e03018 2099
2bcb4b0f
LB		 2100 mv643xx_eth_recalc_skb_size(mp);
2101
2257e05c
LB		 2102 napi_enable(&mp->napi);
2103
2bcb4b0f
LB		 2104 skb_queue_head_init(&mp->rx_recycle);
2105
f7981c1c 2106 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2107 err = rxq_init(mp, i);
2108 if (err) {
2109 while (--i >= 0)
f7981c1c 2110 rxq_deinit(mp->rxq + i);
64da80a2
LB		 2111 goto out;
2112 }
2113
1fa38c58 2114 rxq_refill(mp->rxq + i, INT_MAX);
2257e05c
LB		 2115 }
2116
1fa38c58 2117 if (mp->work_rx_oom) {
2257e05c
LB		 2118 mp->rx_oom.expires = jiffies + (HZ / 10);
2119 add_timer(&mp->rx_oom);
64da80a2 2120 }
8a578111 2121
f7981c1c 2122 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc
LB		 2123 err = txq_init(mp, i);
2124 if (err) {
2125 while (--i >= 0)
f7981c1c 2126 txq_deinit(mp->txq + i);
3d6b35bc
LB		 2127 goto out_free;
2128 }
2129 }
16e03018 2130
2f7eb47a 2131 netif_carrier_off(dev);
2f7eb47a 2132
fc32b0e2 2133 port_start(mp);
16e03018 2134
ffd86bbe
LB		 2135 set_rx_coal(mp, 0);
2136 set_tx_coal(mp, 0);
16e03018 2137
37a6084f
LB		 2138 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2139 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
16e03018 2140
c9df406f
LB		 2141 return 0;
2142
13d64285 2143
fc32b0e2 2144out_free:
f7981c1c
LB		 2145 for (i = 0; i < mp->rxq_count; i++)
2146 rxq_deinit(mp->rxq + i);
fc32b0e2 2147out:
c9df406f
LB		 2148 free_irq(dev->irq, dev);
2149
2150 return err;
16e03018
DF		 2151}
2152
e5371493 2153static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2154{
fc32b0e2 2155 unsigned int data;
64da80a2 2156 int i;
1da177e4 2157
f7981c1c
LB		 2158 for (i = 0; i < mp->rxq_count; i++)
2159 rxq_disable(mp->rxq + i);
2160 for (i = 0; i < mp->txq_count; i++)
2161 txq_disable(mp->txq + i);
ae9ae064
LB		 2162
2163 while (1) {
37a6084f 2164 u32 ps = rdlp(mp, PORT_STATUS);
ae9ae064
LB		 2165
2166 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2167 break;
13d64285 2168 udelay(10);
ae9ae064 2169 }
1da177e4 2170
c9df406f 2171 /* Reset the Enable bit in the Configuration Register */
37a6084f 2172 data = rdlp(mp, PORT_SERIAL_CONTROL);
fc32b0e2
LB		 2173 data &= ~(SERIAL_PORT_ENABLE |
2174 DO_NOT_FORCE_LINK_FAIL |
2175 FORCE_LINK_PASS);
37a6084f 2176 wrlp(mp, PORT_SERIAL_CONTROL, data);
1da177e4
LT		 2177}
2178
c9df406f 2179static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2180{
e5371493 2181 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2182 int i;
1da177e4 2183
37a6084f
LB		 2184 wrlp(mp, INT_MASK, 0x00000000);
2185 rdlp(mp, INT_MASK);
1da177e4 2186
4ff3495a
LB		 2187 del_timer_sync(&mp->mib_counters_timer);
2188
c9df406f 2189 napi_disable(&mp->napi);
78fff83b 2190
2257e05c
LB		 2191 del_timer_sync(&mp->rx_oom);
2192
c9df406f 2193 netif_carrier_off(dev);
1da177e4 2194
fc32b0e2
LB		 2195 free_irq(dev->irq, dev);
2196
cc9754b3 2197 port_reset(mp);
8fd89211 2198 mv643xx_eth_get_stats(dev);
fc32b0e2 2199 mib_counters_update(mp);
1da177e4 2200
2bcb4b0f
LB		 2201 skb_queue_purge(&mp->rx_recycle);
2202
f7981c1c
LB		 2203 for (i = 0; i < mp->rxq_count; i++)
2204 rxq_deinit(mp->rxq + i);
2205 for (i = 0; i < mp->txq_count; i++)
2206 txq_deinit(mp->txq + i);
1da177e4 2207
c9df406f 2208 return 0;
1da177e4
LT		 2209}
2210
fc32b0e2 2211static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2212{
e5371493 2213 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2214
ed94493f
LB		 2215 if (mp->phy != NULL)
2216 return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd);
bedfe324
LB		 2217
2218 return -EOPNOTSUPP;
1da177e4
LT		 2219}
2220
c9df406f 2221static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2222{
89df5fdc
LB		 2223 struct mv643xx_eth_private *mp = netdev_priv(dev);
2224
fc32b0e2 2225 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2226 return -EINVAL;
1da177e4 2227
c9df406f 2228 dev->mtu = new_mtu;
2bcb4b0f 2229 mv643xx_eth_recalc_skb_size(mp);
89df5fdc
LB		 2230 tx_set_rate(mp, 1000000000, 16777216);
2231
c9df406f
LB		 2232 if (!netif_running(dev))
2233 return 0;
1da177e4 2234
c9df406f
LB		 2235 /*
2236 * Stop and then re-open the interface. This will allocate RX
2237 * skbs of the new MTU.
2238 * There is a possible danger that the open will not succeed,
fc32b0e2 2239 * due to memory being full.
c9df406f
LB		 2240 */
2241 mv643xx_eth_stop(dev);
2242 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 2243 dev_printk(KERN_ERR, &dev->dev,
2244 "fatal error on re-opening device after "
2245 "MTU change\n");
c9df406f
LB		 2246 }
2247
2248 return 0;
1da177e4
LT		 2249}
2250
fc32b0e2 2251static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2252{
fc32b0e2 2253 struct mv643xx_eth_private *mp;
1da177e4 2254
fc32b0e2
LB		 2255 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2256 if (netif_running(mp->dev)) {
e5ef1de1 2257 netif_tx_stop_all_queues(mp->dev);
fc32b0e2
LB		 2258 port_reset(mp);
2259 port_start(mp);
e5ef1de1 2260 netif_tx_wake_all_queues(mp->dev);
fc32b0e2 2261 }
c9df406f
LB		 2262}
2263
c9df406f 2264static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2265{
e5371493 2266 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2267
fc32b0e2 2268 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 2269
c9df406f 2270 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2271}
2272
c9df406f 2273#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2274static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2275{
fc32b0e2 2276 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2277
37a6084f
LB		 2278 wrlp(mp, INT_MASK, 0x00000000);
2279 rdlp(mp, INT_MASK);
c9df406f 2280
fc32b0e2 2281 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2282
37a6084f 2283 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
9f8dd319 2284}
c9df406f 2285#endif
9f8dd319 2286
9f8dd319 2287
c9df406f 2288/* platform glue ************************************************************/
e5371493
LB		 2289static void
2290mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2291 struct mbus_dram_target_info *dram)
c9df406f 2292{
cc9754b3 2293 void __iomem *base = msp->base;
c9df406f
LB		 2294 u32 win_enable;
2295 u32 win_protect;
2296 int i;
9f8dd319 2297
c9df406f
LB		 2298 for (i = 0; i < 6; i++) {
2299 writel(0, base + WINDOW_BASE(i));
2300 writel(0, base + WINDOW_SIZE(i));
2301 if (i < 4)
2302 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2303 }
2304
c9df406f
LB		 2305 win_enable = 0x3f;
2306 win_protect = 0;
2307
2308 for (i = 0; i < dram->num_cs; i++) {
2309 struct mbus_dram_window *cs = dram->cs + i;
2310
2311 writel((cs->base & 0xffff0000) |
2312 (cs->mbus_attr << 8) |
2313 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2314 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2315
2316 win_enable &= ~(1 << i);
2317 win_protect |= 3 << (2 * i);
2318 }
2319
2320 writel(win_enable, base + WINDOW_BAR_ENABLE);
2321 msp->win_protect = win_protect;
9f8dd319
DF		 2322}
2323
773fc3ee
LB		 2324static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2325{
2326 /*
2327 * Check whether we have a 14-bit coal limit field in bits
2328 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2329 * SDMA config register.
2330 */
37a6084f
LB		 2331 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2332 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
773fc3ee
LB		 2333 msp->extended_rx_coal_limit = 1;
2334 else
2335 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2336
2337 /*
457b1d5a
LB		 2338 * Check whether the MAC supports TX rate control, and if
2339 * yes, whether its associated registers are in the old or
2340 * the new place.
1e881592 2341 */
37a6084f
LB		 2342 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2343 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
457b1d5a
LB		 2344 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2345 } else {
37a6084f
LB		 2346 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2347 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
457b1d5a
LB		 2348 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2349 else
2350 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2351 }
773fc3ee
LB		 2352}
2353
c9df406f 2354static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2355{
10a9948d 2356 static int mv643xx_eth_version_printed;
c9df406f 2357 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2358 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2359 struct resource *res;
2360 int ret;
9f8dd319 2361
e5371493 2362 if (!mv643xx_eth_version_printed++)
7dde154d
LB		 2363 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2364 "driver version %s\n", mv643xx_eth_driver_version);
9f8dd319 2365
c9df406f
LB		 2366 ret = -EINVAL;
2367 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2368 if (res == NULL)
2369 goto out;
9f8dd319 2370
c9df406f
LB		 2371 ret = -ENOMEM;
2372 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2373 if (msp == NULL)
2374 goto out;
2375 memset(msp, 0, sizeof(*msp));
2376
cc9754b3
LB		 2377 msp->base = ioremap(res->start, res->end - res->start + 1);
2378 if (msp->base == NULL)
c9df406f
LB		 2379 goto out_free;
2380
ed94493f
LB		 2381 /*
2382 * Set up and register SMI bus.
2383 */
2384 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be
LB		 2385 msp->smi_bus = mdiobus_alloc();
2386 if (msp->smi_bus == NULL)
ed94493f 2387 goto out_unmap;
298cf9be
LB		 2388
2389 msp->smi_bus->priv = msp;
2390 msp->smi_bus->name = "mv643xx_eth smi";
2391 msp->smi_bus->read = smi_bus_read;
2392 msp->smi_bus->write = smi_bus_write,
2393 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
2394 msp->smi_bus->parent = &pdev->dev;
2395 msp->smi_bus->phy_mask = 0xffffffff;
2396 if (mdiobus_register(msp->smi_bus) < 0)
2397 goto out_free_mii_bus;
ed94493f
LB		 2398 msp->smi = msp;
2399 } else {
fc0eb9f2 2400 msp->smi = platform_get_drvdata(pd->shared_smi);
ed94493f 2401 }
c9df406f 2402
45c5d3bc
LB		 2403 msp->err_interrupt = NO_IRQ;
2404 init_waitqueue_head(&msp->smi_busy_wait);
2405
2406 /*
2407 * Check whether the error interrupt is hooked up.
2408 */
2409 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2410 if (res != NULL) {
2411 int err;
2412
2413 err = request_irq(res->start, mv643xx_eth_err_irq,
2414 IRQF_SHARED, "mv643xx_eth", msp);
2415 if (!err) {
2416 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2417 msp->err_interrupt = res->start;
2418 }
2419 }
2420
c9df406f
LB		 2421 /*
2422 * (Re-)program MBUS remapping windows if we are asked to.
2423 */
2424 if (pd != NULL && pd->dram != NULL)
2425 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2426
fc32b0e2
LB		 2427 /*
2428 * Detect hardware parameters.
2429 */
2430 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
773fc3ee 2431 infer_hw_params(msp);
fc32b0e2
LB		 2432
2433 platform_set_drvdata(pdev, msp);
2434
c9df406f
LB		 2435 return 0;
2436
298cf9be
LB		 2437out_free_mii_bus:
2438 mdiobus_free(msp->smi_bus);
ed94493f
LB		 2439out_unmap:
2440 iounmap(msp->base);
c9df406f
LB		 2441out_free:
2442 kfree(msp);
2443out:
2444 return ret;
2445}
2446
2447static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2448{
e5371493 2449 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
ed94493f 2450 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
c9df406f 2451
298cf9be
LB		 2452 if (pd == NULL || pd->shared_smi == NULL) {
2453 mdiobus_free(msp->smi_bus);
2454 mdiobus_unregister(msp->smi_bus);
2455 }
45c5d3bc
LB		 2456 if (msp->err_interrupt != NO_IRQ)
2457 free_irq(msp->err_interrupt, msp);
cc9754b3 2458 iounmap(msp->base);
c9df406f
LB		 2459 kfree(msp);
2460
2461 return 0;
9f8dd319
DF		 2462}
2463
c9df406f 2464static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2465 .probe = mv643xx_eth_shared_probe,
2466 .remove = mv643xx_eth_shared_remove,
c9df406f 2467 .driver = {
fc32b0e2 2468 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2469 .owner = THIS_MODULE,
2470 },
2471};
2472
e5371493 2473static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2474{
c9df406f 2475 int addr_shift = 5 * mp->port_num;
fc32b0e2 2476 u32 data;
1da177e4 2477
fc32b0e2
LB		 2478 data = rdl(mp, PHY_ADDR);
2479 data &= ~(0x1f << addr_shift);
2480 data |= (phy_addr & 0x1f) << addr_shift;
2481 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2482}
2483
e5371493 2484static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2485{
fc32b0e2
LB		 2486 unsigned int data;
2487
2488 data = rdl(mp, PHY_ADDR);
2489
2490 return (data >> (5 * mp->port_num)) & 0x1f;
2491}
2492
2493static void set_params(struct mv643xx_eth_private *mp,
2494 struct mv643xx_eth_platform_data *pd)
2495{
2496 struct net_device *dev = mp->dev;
2497
2498 if (is_valid_ether_addr(pd->mac_addr))
2499 memcpy(dev->dev_addr, pd->mac_addr, 6);
2500 else
2501 uc_addr_get(mp, dev->dev_addr);
2502
fc32b0e2
LB		 2503 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2504 if (pd->rx_queue_size)
2505 mp->default_rx_ring_size = pd->rx_queue_size;
2506 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2507 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2508
f7981c1c 2509 mp->rxq_count = pd->rx_queue_count ? : 1;
64da80a2 2510
fc32b0e2
LB		 2511 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2512 if (pd->tx_queue_size)
2513 mp->default_tx_ring_size = pd->tx_queue_size;
2514 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2515 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc 2516
f7981c1c 2517 mp->txq_count = pd->tx_queue_count ? : 1;
1da177e4
LT		 2518}
2519
ed94493f
LB		 2520static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2521 int phy_addr)
1da177e4 2522{
298cf9be 2523 struct mii_bus *bus = mp->shared->smi->smi_bus;
ed94493f
LB		 2524 struct phy_device *phydev;
2525 int start;
2526 int num;
2527 int i;
45c5d3bc 2528
ed94493f
LB		 2529 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2530 start = phy_addr_get(mp) & 0x1f;
2531 num = 32;
2532 } else {
2533 start = phy_addr & 0x1f;
2534 num = 1;
2535 }
45c5d3bc 2536
ed94493f
LB		 2537 phydev = NULL;
2538 for (i = 0; i < num; i++) {
2539 int addr = (start + i) & 0x1f;
fc32b0e2 2540
ed94493f
LB		 2541 if (bus->phy_map[addr] == NULL)
2542 mdiobus_scan(bus, addr);
1da177e4 2543
ed94493f
LB		 2544 if (phydev == NULL) {
2545 phydev = bus->phy_map[addr];
2546 if (phydev != NULL)
2547 phy_addr_set(mp, addr);
2548 }
2549 }
1da177e4 2550
ed94493f 2551 return phydev;
1da177e4
LT		 2552}
2553
ed94493f 2554static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
c28a4f89 2555{
ed94493f 2556 struct phy_device *phy = mp->phy;
c28a4f89 2557
fc32b0e2
LB		 2558 phy_reset(mp);
2559
ed94493f
LB		 2560 phy_attach(mp->dev, phy->dev.bus_id, 0, PHY_INTERFACE_MODE_GMII);
2561
2562 if (speed == 0) {
2563 phy->autoneg = AUTONEG_ENABLE;
2564 phy->speed = 0;
2565 phy->duplex = 0;
2566 phy->advertising = phy->supported | ADVERTISED_Autoneg;
c9df406f 2567 } else {
ed94493f
LB		 2568 phy->autoneg = AUTONEG_DISABLE;
2569 phy->advertising = 0;
2570 phy->speed = speed;
2571 phy->duplex = duplex;
c9df406f 2572 }
ed94493f 2573 phy_start_aneg(phy);
c28a4f89
JC		 2574}
2575
81600eea
LB		 2576static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2577{
2578 u32 pscr;
2579
37a6084f 2580 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2581 if (pscr & SERIAL_PORT_ENABLE) {
2582 pscr &= ~SERIAL_PORT_ENABLE;
37a6084f 2583 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2584 }
2585
2586 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
ed94493f 2587 if (mp->phy == NULL) {
81600eea
LB		 2588 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2589 if (speed == SPEED_1000)
2590 pscr |= SET_GMII_SPEED_TO_1000;
2591 else if (speed == SPEED_100)
2592 pscr |= SET_MII_SPEED_TO_100;
2593
2594 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2595
2596 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2597 if (duplex == DUPLEX_FULL)
2598 pscr |= SET_FULL_DUPLEX_MODE;
2599 }
2600
37a6084f 2601 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2602}
2603
c9df406f 2604static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2605{
c9df406f 2606 struct mv643xx_eth_platform_data *pd;
e5371493 2607 struct mv643xx_eth_private *mp;
c9df406f 2608 struct net_device *dev;
c9df406f 2609 struct resource *res;
fc32b0e2 2610 int err;
1da177e4 2611
c9df406f
LB		 2612 pd = pdev->dev.platform_data;
2613 if (pd == NULL) {
fc32b0e2
LB		 2614 dev_printk(KERN_ERR, &pdev->dev,
2615 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2616 return -ENODEV;
2617 }
1da177e4 2618
c9df406f 2619 if (pd->shared == NULL) {
fc32b0e2
LB		 2620 dev_printk(KERN_ERR, &pdev->dev,
2621 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2622 return -ENODEV;
2623 }
8f518703 2624
e5ef1de1 2625 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
c9df406f
LB		 2626 if (!dev)
2627 return -ENOMEM;
1da177e4 2628
c9df406f 2629 mp = netdev_priv(dev);
fc32b0e2
LB		 2630 platform_set_drvdata(pdev, mp);
2631
2632 mp->shared = platform_get_drvdata(pd->shared);
37a6084f 2633 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
fc32b0e2
LB		 2634 mp->port_num = pd->port_number;
2635
c9df406f 2636 mp->dev = dev;
78fff83b 2637
fc32b0e2 2638 set_params(mp, pd);
e5ef1de1 2639 dev->real_num_tx_queues = mp->txq_count;
fc32b0e2 2640
ed94493f
LB		 2641 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2642 mp->phy = phy_scan(mp, pd->phy_addr);
bedfe324 2643
ed94493f
LB		 2644 if (mp->phy != NULL) {
2645 phy_init(mp, pd->speed, pd->duplex);
bedfe324
LB		 2646 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2647 } else {
2648 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2649 }
ed94493f 2650
81600eea 2651 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2 2652
4ff3495a
LB		 2653
2654 mib_counters_clear(mp);
2655
2656 init_timer(&mp->mib_counters_timer);
2657 mp->mib_counters_timer.data = (unsigned long)mp;
2658 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2659 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2660 add_timer(&mp->mib_counters_timer);
2661
2662 spin_lock_init(&mp->mib_counters_lock);
2663
2664 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2665
2257e05c
LB		 2666 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2667
2668 init_timer(&mp->rx_oom);
2669 mp->rx_oom.data = (unsigned long)mp;
2670 mp->rx_oom.function = oom_timer_wrapper;
2671
fc32b0e2 2672
c9df406f
LB		 2673 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2674 BUG_ON(!res);
2675 dev->irq = res->start;
1da177e4 2676
8fd89211 2677 dev->get_stats = mv643xx_eth_get_stats;
fc32b0e2 2678 dev->hard_start_xmit = mv643xx_eth_xmit;
c9df406f
LB		 2679 dev->open = mv643xx_eth_open;
2680 dev->stop = mv643xx_eth_stop;
c9df406f 2681 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
fc32b0e2
LB		 2682 dev->set_mac_address = mv643xx_eth_set_mac_address;
2683 dev->do_ioctl = mv643xx_eth_ioctl;
2684 dev->change_mtu = mv643xx_eth_change_mtu;
c9df406f 2685 dev->tx_timeout = mv643xx_eth_tx_timeout;
c9df406f 2686#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 2687 dev->poll_controller = mv643xx_eth_netpoll;
c9df406f 2688#endif
c9df406f
LB		 2689 dev->watchdog_timeo = 2 * HZ;
2690 dev->base_addr = 0;
1da177e4 2691
c9df406f 2692 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
e32b6617 2693 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4 2694
fc32b0e2 2695 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2696
c9df406f 2697 if (mp->shared->win_protect)
fc32b0e2 2698 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2699
c9df406f
LB		 2700 err = register_netdev(dev);
2701 if (err)
2702 goto out;
1da177e4 2703
e174961c
JB		 2704 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n",
2705 mp->port_num, dev->dev_addr);
1da177e4 2706
13d64285 2707 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2708 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2709
c9df406f 2710 return 0;
1da177e4 2711
c9df406f
LB		 2712out:
2713 free_netdev(dev);
1da177e4 2714
c9df406f 2715 return err;
1da177e4
LT		 2716}
2717
c9df406f 2718static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2719{
fc32b0e2 2720 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2721
fc32b0e2 2722 unregister_netdev(mp->dev);
ed94493f
LB		 2723 if (mp->phy != NULL)
2724 phy_detach(mp->phy);
c9df406f 2725 flush_scheduled_work();
fc32b0e2 2726 free_netdev(mp->dev);
c9df406f 2727
c9df406f 2728 platform_set_drvdata(pdev, NULL);
fc32b0e2 2729
c9df406f 2730 return 0;
1da177e4
LT		 2731}
2732
c9df406f 2733static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2734{
fc32b0e2 2735 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2736
c9df406f 2737 /* Mask all interrupts on ethernet port */
37a6084f
LB		 2738 wrlp(mp, INT_MASK, 0);
2739 rdlp(mp, INT_MASK);
c9df406f 2740
fc32b0e2
LB		 2741 if (netif_running(mp->dev))
2742 port_reset(mp);
d0412d96
JC		 2743}
2744
c9df406f 2745static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2746 .probe = mv643xx_eth_probe,
2747 .remove = mv643xx_eth_remove,
2748 .shutdown = mv643xx_eth_shutdown,
c9df406f 2749 .driver = {
fc32b0e2 2750 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2751 .owner = THIS_MODULE,
2752 },
2753};
2754
e5371493 2755static int __init mv643xx_eth_init_module(void)
d0412d96 2756{
c9df406f 2757 int rc;
d0412d96 2758
c9df406f
LB		 2759 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2760 if (!rc) {
2761 rc = platform_driver_register(&mv643xx_eth_driver);
2762 if (rc)
2763 platform_driver_unregister(&mv643xx_eth_shared_driver);
2764 }
fc32b0e2 2765
c9df406f 2766 return rc;
d0412d96 2767}
fc32b0e2 2768module_init(mv643xx_eth_init_module);
d0412d96 2769
e5371493 2770static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2771{
c9df406f
LB		 2772 platform_driver_unregister(&mv643xx_eth_driver);
2773 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 2774}
e5371493 2775module_exit(mv643xx_eth_cleanup_module);
1da177e4 2776
45675bc6
LB		 2777MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2778 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 2779MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 2780MODULE_LICENSE("GPL");
c9df406f 2781MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 2782MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
kernel source for telekom puls (alcatel/mediatek)