[GitHub/MotorolaMobilityLLC/kernel-slsi.git] / drivers / net / mlx4 / mlx4.h

/*
 * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
 * Copyright (c) 2005, 2006, 2007 Cisco Systems.  All rights reserved.
 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef MLX4_H
#define MLX4_H

#include <linux/mutex.h>
#include <linux/radix-tree.h>
#include <linux/timer.h>

#include <linux/mlx4/device.h>
#include <linux/mlx4/doorbell.h>

#define DRV_NAME	"mlx4_core"
#define PFX		DRV_NAME ": "
#define DRV_VERSION	"0.01"
#define DRV_RELDATE	"May 1, 2007"

enum {
	MLX4_HCR_BASE		= 0x80680,
	MLX4_HCR_SIZE		= 0x0001c,
	MLX4_CLR_INT_SIZE	= 0x00008
};

enum {
	MLX4_BOARD_ID_LEN	= 64
};

enum {
	MLX4_MGM_ENTRY_SIZE	=  0x40,
	MLX4_QP_PER_MGM		= 4 * (MLX4_MGM_ENTRY_SIZE / 16 - 2),
	MLX4_MTT_ENTRY_PER_SEG	= 8
};

enum {
	MLX4_EQ_ASYNC,
	MLX4_EQ_COMP,
	MLX4_NUM_EQ
};

enum {
	MLX4_NUM_PDS		= 1 << 15
};

enum {
	MLX4_CMPT_TYPE_QP	= 0,
	MLX4_CMPT_TYPE_SRQ	= 1,
	MLX4_CMPT_TYPE_CQ	= 2,
	MLX4_CMPT_TYPE_EQ	= 3,
	MLX4_CMPT_NUM_TYPE
};

enum {
	MLX4_CMPT_SHIFT		= 24,
	MLX4_NUM_CMPTS		= MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
};

#ifdef CONFIG_MLX4_DEBUG
extern int mlx4_debug_level;

#define mlx4_dbg(mdev, format, arg...)					\
	do {								\
		if (mlx4_debug_level)					\
			dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ## arg); \
	} while (0)

#else /* CONFIG_MLX4_DEBUG */

#define mlx4_dbg(mdev, format, arg...) do { (void) mdev; } while (0)

#endif /* CONFIG_MLX4_DEBUG */

#define mlx4_err(mdev, format, arg...) \
	dev_err(&mdev->pdev->dev, format, ## arg)
#define mlx4_info(mdev, format, arg...) \
	dev_info(&mdev->pdev->dev, format, ## arg)
#define mlx4_warn(mdev, format, arg...) \
	dev_warn(&mdev->pdev->dev, format, ## arg)

struct mlx4_bitmap {
	u32			last;
	u32			top;
	u32			max;
	u32			mask;
	spinlock_t		lock;
	unsigned long	       *table;
};

struct mlx4_buddy {
	unsigned long	      **bits;
	int			max_order;
	spinlock_t		lock;
};

struct mlx4_icm;

struct mlx4_icm_table {
	u64			virt;
	int			num_icm;
	int			num_obj;
	int			obj_size;
	int			lowmem;
	struct mutex		mutex;
	struct mlx4_icm	      **icm;
};

struct mlx4_eq {
	struct mlx4_dev	       *dev;
	void __iomem	       *doorbell;
	int			eqn;
	u32			cons_index;
	u16			irq;
	u16			have_irq;
	int			nent;
	struct mlx4_buf_list   *page_list;
	struct mlx4_mtt		mtt;
};

struct mlx4_profile {
	int			num_qp;
	int			rdmarc_per_qp;
	int			num_srq;
	int			num_cq;
	int			num_mcg;
	int			num_mpt;
	int			num_mtt;
};

struct mlx4_fw {
	u64			clr_int_base;
	u64			catas_offset;
	struct mlx4_icm	       *fw_icm;
	struct mlx4_icm	       *aux_icm;
	u32			catas_size;
	u16			fw_pages;
	u8			clr_int_bar;
	u8			catas_bar;
};

struct mlx4_cmd {
	struct pci_pool	       *pool;
	void __iomem	       *hcr;
	struct mutex		hcr_mutex;
	struct semaphore	poll_sem;
	struct semaphore	event_sem;
	int			max_cmds;
	spinlock_t		context_lock;
	int			free_head;
	struct mlx4_cmd_context *context;
	u16			token_mask;
	u8			use_events;
	u8			toggle;
};

struct mlx4_uar_table {
	struct mlx4_bitmap	bitmap;
};

struct mlx4_mr_table {
	struct mlx4_bitmap	mpt_bitmap;
	struct mlx4_buddy	mtt_buddy;
	u64			mtt_base;
	u64			mpt_base;
	struct mlx4_icm_table	mtt_table;
	struct mlx4_icm_table	dmpt_table;
};

struct mlx4_cq_table {
	struct mlx4_bitmap	bitmap;
	spinlock_t		lock;
	struct radix_tree_root	tree;
	struct mlx4_icm_table	table;
	struct mlx4_icm_table	cmpt_table;
};

struct mlx4_eq_table {
	struct mlx4_bitmap	bitmap;
	void __iomem	       *clr_int;
	void __iomem	       *uar_map[(MLX4_NUM_EQ + 6) / 4];
	u32			clr_mask;
	struct mlx4_eq		eq[MLX4_NUM_EQ];
	u64			icm_virt;
	struct page	       *icm_page;
	dma_addr_t		icm_dma;
	struct mlx4_icm_table	cmpt_table;
	int			have_irq;
	u8			inta_pin;
};

struct mlx4_srq_table {
	struct mlx4_bitmap	bitmap;
	spinlock_t		lock;
	struct radix_tree_root	tree;
	struct mlx4_icm_table	table;
	struct mlx4_icm_table	cmpt_table;
};

struct mlx4_qp_table {
	struct mlx4_bitmap	bitmap;
	u32			rdmarc_base;
	int			rdmarc_shift;
	spinlock_t		lock;
	struct mlx4_icm_table	qp_table;
	struct mlx4_icm_table	auxc_table;
	struct mlx4_icm_table	altc_table;
	struct mlx4_icm_table	rdmarc_table;
	struct mlx4_icm_table	cmpt_table;
};

struct mlx4_mcg_table {
	struct mutex		mutex;
	struct mlx4_bitmap	bitmap;
	struct mlx4_icm_table	table;
};

struct mlx4_catas_err {
	u32 __iomem	       *map;
	struct timer_list	timer;
	struct list_head	list;
};

struct mlx4_priv {
	struct mlx4_dev		dev;

	struct list_head	dev_list;
	struct list_head	ctx_list;
	spinlock_t		ctx_lock;

	struct mlx4_fw		fw;
	struct mlx4_cmd		cmd;

	struct mlx4_bitmap	pd_bitmap;
	struct mlx4_uar_table	uar_table;
	struct mlx4_mr_table	mr_table;
	struct mlx4_cq_table	cq_table;
	struct mlx4_eq_table	eq_table;
	struct mlx4_srq_table	srq_table;
	struct mlx4_qp_table	qp_table;
	struct mlx4_mcg_table	mcg_table;

	struct mlx4_catas_err	catas_err;

	void __iomem	       *clr_base;

	struct mlx4_uar		driver_uar;
	void __iomem	       *kar;

	u32			rev_id;
	char			board_id[MLX4_BOARD_ID_LEN];
};

static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
{
	return container_of(dev, struct mlx4_priv, dev);
}

u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, u32 reserved);
void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);

int mlx4_reset(struct mlx4_dev *dev);

int mlx4_init_pd_table(struct mlx4_dev *dev);
int mlx4_init_uar_table(struct mlx4_dev *dev);
int mlx4_init_mr_table(struct mlx4_dev *dev);
int mlx4_init_eq_table(struct mlx4_dev *dev);
int mlx4_init_cq_table(struct mlx4_dev *dev);
int mlx4_init_qp_table(struct mlx4_dev *dev);
int mlx4_init_srq_table(struct mlx4_dev *dev);
int mlx4_init_mcg_table(struct mlx4_dev *dev);

void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);

void mlx4_start_catas_poll(struct mlx4_dev *dev);
void mlx4_stop_catas_poll(struct mlx4_dev *dev);
int mlx4_catas_init(void);
void mlx4_catas_cleanup(void);
int mlx4_restart_one(struct pci_dev *pdev);
int mlx4_register_device(struct mlx4_dev *dev);
void mlx4_unregister_device(struct mlx4_dev *dev);
void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_event type,
			 int subtype, int port);

struct mlx4_dev_cap;
struct mlx4_init_hca_param;

u64 mlx4_make_profile(struct mlx4_dev *dev,
		      struct mlx4_profile *request,
		      struct mlx4_dev_cap *dev_cap,
		      struct mlx4_init_hca_param *init_hca);

int mlx4_map_eq_icm(struct mlx4_dev *dev, u64 icm_virt);
void mlx4_unmap_eq_icm(struct mlx4_dev *dev);

int mlx4_cmd_init(struct mlx4_dev *dev);
void mlx4_cmd_cleanup(struct mlx4_dev *dev);
void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
int mlx4_cmd_use_events(struct mlx4_dev *dev);
void mlx4_cmd_use_polling(struct mlx4_dev *dev);

void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);

void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);

void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);

void mlx4_handle_catas_err(struct mlx4_dev *dev);

#endif /* MLX4_H */
Commit	Line	Data
225c7b1f RD	1	/*
	2	* Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
	3	* Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
	4	* Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
	5	* Copyright (c) 2005 Mellanox Technologies. All rights reserved.
	6	* Copyright (c) 2004 Voltaire, Inc. All rights reserved.
	7	*
	8	* This software is available to you under a choice of one of two
	9	* licenses. You may choose to be licensed under the terms of the GNU
	10	* General Public License (GPL) Version 2, available from the file
	11	* COPYING in the main directory of this source tree, or the
	12	* OpenIB.org BSD license below:
	13	*
	14	* Redistribution and use in source and binary forms, with or
	15	* without modification, are permitted provided that the following
	16	* conditions are met:
	17	*
	18	* - Redistributions of source code must retain the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer.
	21	*
	22	* - Redistributions in binary form must reproduce the above
	23	* copyright notice, this list of conditions and the following
	24	* disclaimer in the documentation and/or other materials
	25	* provided with the distribution.
	26	*
	27	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	28	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	29	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	30	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	31	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	32	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	33	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	34	* SOFTWARE.
	35	*/
	36
	37	#ifndef MLX4_H
	38	#define MLX4_H
	39
525f5f44	40	#include <linux/mutex.h>
225c7b1f	41	#include <linux/radix-tree.h>
ee49bd93	42	#include <linux/timer.h>
225c7b1f RD	43
	44	#include <linux/mlx4/device.h>
	45	#include <linux/mlx4/doorbell.h>
	46
	47	#define DRV_NAME "mlx4_core"
	48	#define PFX DRV_NAME ": "
	49	#define DRV_VERSION "0.01"
	50	#define DRV_RELDATE "May 1, 2007"
	51
	52	enum {
	53	MLX4_HCR_BASE = 0x80680,
	54	MLX4_HCR_SIZE = 0x0001c,
	55	MLX4_CLR_INT_SIZE = 0x00008
	56	};
	57
	58	enum {
	59	MLX4_BOARD_ID_LEN = 64
	60	};
	61
	62	enum {
	63	MLX4_MGM_ENTRY_SIZE = 0x40,
	64	MLX4_QP_PER_MGM = 4 * (MLX4_MGM_ENTRY_SIZE / 16 - 2),
	65	MLX4_MTT_ENTRY_PER_SEG = 8
	66	};
	67
	68	enum {
	69	MLX4_EQ_ASYNC,
	70	MLX4_EQ_COMP,
225c7b1f RD	71	MLX4_NUM_EQ
	72	};
	73
	74	enum {
	75	MLX4_NUM_PDS = 1 << 15
	76	};
	77
	78	enum {
	79	MLX4_CMPT_TYPE_QP = 0,
	80	MLX4_CMPT_TYPE_SRQ = 1,
	81	MLX4_CMPT_TYPE_CQ = 2,
	82	MLX4_CMPT_TYPE_EQ = 3,
	83	MLX4_CMPT_NUM_TYPE
	84	};
	85
	86	enum {
	87	MLX4_CMPT_SHIFT = 24,
	88	MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
	89	};
	90
	91	#ifdef CONFIG_MLX4_DEBUG
	92	extern int mlx4_debug_level;
	93
	94	#define mlx4_dbg(mdev, format, arg...) \
	95	do { \
	96	if (mlx4_debug_level) \
	97	dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ## arg); \
	98	} while (0)
	99
	100	#else /* CONFIG_MLX4_DEBUG */
	101
	102	#define mlx4_dbg(mdev, format, arg...) do { (void) mdev; } while (0)
	103
	104	#endif /* CONFIG_MLX4_DEBUG */
	105
	106	#define mlx4_err(mdev, format, arg...) \
	107	dev_err(&mdev->pdev->dev, format, ## arg)
	108	#define mlx4_info(mdev, format, arg...) \
	109	dev_info(&mdev->pdev->dev, format, ## arg)
	110	#define mlx4_warn(mdev, format, arg...) \
	111	dev_warn(&mdev->pdev->dev, format, ## arg)
	112
	113	struct mlx4_bitmap {
	114	u32 last;
	115	u32 top;
	116	u32 max;
	117	u32 mask;
	118	spinlock_t lock;
	119	unsigned long *table;
	120	};
	121
	122	struct mlx4_buddy {
	123	unsigned long **bits;
	124	int max_order;
	125	spinlock_t lock;
	126	};
	127
	128	struct mlx4_icm;
	129
	130	struct mlx4_icm_table {
	131	u64 virt;
	132	int num_icm;
	133	int num_obj;
	134	int obj_size;
135	int lowmem;
136	struct mutex mutex;
137	struct mlx4_icm **icm;
138	};
139
140	struct mlx4_eq {
141	struct mlx4_dev *dev;
142	void __iomem *doorbell;
143	int eqn;
144	u32 cons_index;
145	u16 irq;
146	u16 have_irq;
147	int nent;
148	struct mlx4_buf_list *page_list;
149	struct mlx4_mtt mtt;
150	};
151
152	struct mlx4_profile {
153	int num_qp;
154	int rdmarc_per_qp;
155	int num_srq;
156	int num_cq;
157	int num_mcg;
158	int num_mpt;
159	int num_mtt;
160	};
161
162	struct mlx4_fw {
163	u64 clr_int_base;
164	u64 catas_offset;
165	struct mlx4_icm *fw_icm;
166	struct mlx4_icm *aux_icm;
167	u32 catas_size;
168	u16 fw_pages;
169	u8 clr_int_bar;
170	u8 catas_bar;
171	};
172
173	struct mlx4_cmd {
174	struct pci_pool *pool;
175	void __iomem *hcr;
176	struct mutex hcr_mutex;
177	struct semaphore poll_sem;
178	struct semaphore event_sem;
179	int max_cmds;
180	spinlock_t context_lock;
181	int free_head;
182	struct mlx4_cmd_context *context;
183	u16 token_mask;
184	u8 use_events;
185	u8 toggle;
186	};
187
188	struct mlx4_uar_table {
189	struct mlx4_bitmap bitmap;
190	};
191
192	struct mlx4_mr_table {
193	struct mlx4_bitmap mpt_bitmap;
194	struct mlx4_buddy mtt_buddy;
195	u64 mtt_base;
196	u64 mpt_base;
197	struct mlx4_icm_table mtt_table;
198	struct mlx4_icm_table dmpt_table;
199	};
200
201	struct mlx4_cq_table {
202	struct mlx4_bitmap bitmap;
203	spinlock_t lock;
204	struct radix_tree_root tree;
205	struct mlx4_icm_table table;
206	struct mlx4_icm_table cmpt_table;
207	};
208
209	struct mlx4_eq_table {
210	struct mlx4_bitmap bitmap;
211	void __iomem *clr_int;
212	void __iomem *uar_map[(MLX4_NUM_EQ + 6) / 4];
213	u32 clr_mask;
214	struct mlx4_eq eq[MLX4_NUM_EQ];
215	u64 icm_virt;
216	struct page *icm_page;
217	dma_addr_t icm_dma;
218	struct mlx4_icm_table cmpt_table;
219	int have_irq;
220	u8 inta_pin;
221	};
222
223	struct mlx4_srq_table {
224	struct mlx4_bitmap bitmap;
225	spinlock_t lock;
226	struct radix_tree_root tree;
227	struct mlx4_icm_table table;
228	struct mlx4_icm_table cmpt_table;
229	};
230
231	struct mlx4_qp_table {
232	struct mlx4_bitmap bitmap;
233	u32 rdmarc_base;
234	int rdmarc_shift;
235	spinlock_t lock;
236	struct mlx4_icm_table qp_table;
237	struct mlx4_icm_table auxc_table;
238	struct mlx4_icm_table altc_table;
239	struct mlx4_icm_table rdmarc_table;
240	struct mlx4_icm_table cmpt_table;
241	};
242
243	struct mlx4_mcg_table {
244	struct mutex mutex;
245	struct mlx4_bitmap bitmap;
246	struct mlx4_icm_table table;
247	};
248
249	struct mlx4_catas_err {
250	u32 __iomem *map;
ee49bd93 JM	251	struct timer_list timer;
ee49bd93 JM	252	struct list_head list;
225c7b1f RD	253	};
	254
	255	struct mlx4_priv {
	256	struct mlx4_dev dev;
	257
	258	struct list_head dev_list;
	259	struct list_head ctx_list;
	260	spinlock_t ctx_lock;
	261
	262	struct mlx4_fw fw;
	263	struct mlx4_cmd cmd;
	264
	265	struct mlx4_bitmap pd_bitmap;
	266	struct mlx4_uar_table uar_table;
	267	struct mlx4_mr_table mr_table;
	268	struct mlx4_cq_table cq_table;
	269	struct mlx4_eq_table eq_table;
	270	struct mlx4_srq_table srq_table;
	271	struct mlx4_qp_table qp_table;
	272	struct mlx4_mcg_table mcg_table;
	273
	274	struct mlx4_catas_err catas_err;
	275
	276	void __iomem *clr_base;
	277
	278	struct mlx4_uar driver_uar;
	279	void __iomem *kar;
225c7b1f RD	280
	281	u32 rev_id;
	282	char board_id[MLX4_BOARD_ID_LEN];
	283	};
	284
	285	static inline struct mlx4_priv mlx4_priv(struct mlx4_dev dev)
	286	{
	287	return container_of(dev, struct mlx4_priv, dev);
	288	}
	289
	290	u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
	291	void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
	292	int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, u32 reserved);
	293	void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
	294
	295	int mlx4_reset(struct mlx4_dev *dev);
	296
	297	int mlx4_init_pd_table(struct mlx4_dev *dev);
	298	int mlx4_init_uar_table(struct mlx4_dev *dev);
	299	int mlx4_init_mr_table(struct mlx4_dev *dev);
	300	int mlx4_init_eq_table(struct mlx4_dev *dev);
	301	int mlx4_init_cq_table(struct mlx4_dev *dev);
	302	int mlx4_init_qp_table(struct mlx4_dev *dev);
	303	int mlx4_init_srq_table(struct mlx4_dev *dev);
	304	int mlx4_init_mcg_table(struct mlx4_dev *dev);
	305
	306	void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
	307	void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
	308	void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
	309	void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
	310	void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
	311	void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
	312	void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
	313	void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
	314
ee49bd93 JM	315	void mlx4_start_catas_poll(struct mlx4_dev *dev);
	316	void mlx4_stop_catas_poll(struct mlx4_dev *dev);
	317	int mlx4_catas_init(void);
	318	void mlx4_catas_cleanup(void);
	319	int mlx4_restart_one(struct pci_dev *pdev);
225c7b1f RD	320	int mlx4_register_device(struct mlx4_dev *dev);
	321	void mlx4_unregister_device(struct mlx4_dev *dev);
	322	void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_event type,
	323	int subtype, int port);
	324
	325	struct mlx4_dev_cap;
	326	struct mlx4_init_hca_param;
	327
	328	u64 mlx4_make_profile(struct mlx4_dev *dev,
	329	struct mlx4_profile *request,
	330	struct mlx4_dev_cap *dev_cap,
	331	struct mlx4_init_hca_param *init_hca);
	332
	333	int mlx4_map_eq_icm(struct mlx4_dev *dev, u64 icm_virt);
	334	void mlx4_unmap_eq_icm(struct mlx4_dev *dev);
	335
	336	int mlx4_cmd_init(struct mlx4_dev *dev);
	337	void mlx4_cmd_cleanup(struct mlx4_dev *dev);
	338	void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
	339	int mlx4_cmd_use_events(struct mlx4_dev *dev);
	340	void mlx4_cmd_use_polling(struct mlx4_dev *dev);
	341
	342	void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
	343	void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
	344
	345	void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
	346
	347	void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
	348
	349	void mlx4_handle_catas_err(struct mlx4_dev *dev);
	350
	351	#endif /* MLX4_H */