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mlx4_core: Ethernet MAC/VLAN management
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
41
42#include <linux/mlx4/device.h>
43#include <linux/mlx4/doorbell.h>
44
45#include "mlx4.h"
46#include "fw.h"
47#include "icm.h"
48
49MODULE_AUTHOR("Roland Dreier");
50MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
51MODULE_LICENSE("Dual BSD/GPL");
52MODULE_VERSION(DRV_VERSION);
53
54#ifdef CONFIG_MLX4_DEBUG
55
56int mlx4_debug_level = 0;
57module_param_named(debug_level, mlx4_debug_level, int, 0644);
58MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
59
60#endif /* CONFIG_MLX4_DEBUG */
61
62#ifdef CONFIG_PCI_MSI
63
08fb1055 64static int msi_x = 1;
225c7b1f
RD		 65module_param(msi_x, int, 0444);
66MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
67
68#else /* CONFIG_PCI_MSI */
69
70#define msi_x (0)
71
72#endif /* CONFIG_PCI_MSI */
73
f33afc26 74static char mlx4_version[] __devinitdata =
225c7b1f
RD		 75 DRV_NAME ": Mellanox ConnectX core driver v"
76 DRV_VERSION " (" DRV_RELDATE ")\n";
77
78static struct mlx4_profile default_profile = {
9b1f3851 79 .num_qp = 1 << 17,
225c7b1f 80 .num_srq = 1 << 16,
c9f2ba5e 81 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 82 .num_cq = 1 << 16,
83 .num_mcg = 1 << 13,
84 .num_mpt = 1 << 17,
85 .num_mtt = 1 << 20,
86};
87
93fc9e1b
YP		 88static int log_num_mac = 2;
89module_param_named(log_num_mac, log_num_mac, int, 0444);
90MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
91
92static int log_num_vlan;
93module_param_named(log_num_vlan, log_num_vlan, int, 0444);
94MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
95
96static int use_prio;
97module_param_named(use_prio, use_prio, bool, 0444);
98MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
99 "(0/1, default 0)");
100
3d73c288 101static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 102{
103 int err;
5ae2a7a8 104 int i;
225c7b1f
RD		 105
106 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
107 if (err) {
108 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
109 return err;
110 }
111
112 if (dev_cap->min_page_sz > PAGE_SIZE) {
113 mlx4_err(dev, "HCA minimum page size of %d bigger than "
114 "kernel PAGE_SIZE of %ld, aborting.\n",
115 dev_cap->min_page_sz, PAGE_SIZE);
116 return -ENODEV;
117 }
118 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
119 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
120 "aborting.\n",
121 dev_cap->num_ports, MLX4_MAX_PORTS);
122 return -ENODEV;
123 }
124
125 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
126 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
127 "PCI resource 2 size of 0x%llx, aborting.\n",
128 dev_cap->uar_size,
129 (unsigned long long) pci_resource_len(dev->pdev, 2));
130 return -ENODEV;
131 }
132
133 dev->caps.num_ports = dev_cap->num_ports;
5ae2a7a8
RD		 134 for (i = 1; i <= dev->caps.num_ports; ++i) {
135 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
b79acb49 136 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
5ae2a7a8
RD		 137 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
138 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
139 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
b79acb49
YP		 140 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
141 dev->caps.def_mac[i] = dev_cap->def_mac[i];
5ae2a7a8
RD		 142 }
143
225c7b1f 144 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 145 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
146 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
147 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
148 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
149 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
150 dev->caps.max_wqes = dev_cap->max_qp_sz;
151 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 152 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
153 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
154 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
155 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
156 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
157 dev->caps.num_qp_per_mgm = MLX4_QP_PER_MGM;
158 /*
159 * Subtract 1 from the limit because we need to allocate a
160 * spare CQE so the HCA HW can tell the difference between an
161 * empty CQ and a full CQ.
162 */
163 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
164 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
165 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
121964ec
RD		 166 dev->caps.reserved_mtts = DIV_ROUND_UP(dev_cap->reserved_mtts,
167 MLX4_MTT_ENTRY_PER_SEG);
225c7b1f
RD		 168 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
169 dev->caps.reserved_uars = dev_cap->reserved_uars;
170 dev->caps.reserved_pds = dev_cap->reserved_pds;
225c7b1f 171 dev->caps.mtt_entry_sz = MLX4_MTT_ENTRY_PER_SEG * dev_cap->mtt_entry_sz;
149983af 172 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 173 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
174 dev->caps.flags = dev_cap->flags;
95d04f07
RD		 175 dev->caps.bmme_flags = dev_cap->bmme_flags;
176 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 177 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 178 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
225c7b1f 179
93fc9e1b
YP		 180 dev->caps.log_num_macs = log_num_mac;
181 dev->caps.log_num_vlans = log_num_vlan;
182 dev->caps.log_num_prios = use_prio ? 3 : 0;
183
184 for (i = 1; i <= dev->caps.num_ports; ++i) {
185 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
186 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
187 mlx4_warn(dev, "Requested number of MACs is too much "
188 "for port %d, reducing to %d.\n",
189 i, 1 << dev->caps.log_num_macs);
190 }
191 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
192 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
193 mlx4_warn(dev, "Requested number of VLANs is too much "
194 "for port %d, reducing to %d.\n",
195 i, 1 << dev->caps.log_num_vlans);
196 }
197 }
198
199 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
200 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
201 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
202 (1 << dev->caps.log_num_macs) *
203 (1 << dev->caps.log_num_vlans) *
204 (1 << dev->caps.log_num_prios) *
205 dev->caps.num_ports;
206 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
207
208 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
209 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
210 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
211 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
212
225c7b1f
RD		 213 return 0;
214}
215
e8f9b2ed 216static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 217{
218 struct mlx4_priv *priv = mlx4_priv(dev);
219 int err;
220
221 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 222 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 223 if (!priv->fw.fw_icm) {
224 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
225 return -ENOMEM;
226 }
227
228 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
229 if (err) {
230 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
231 goto err_free;
232 }
233
234 err = mlx4_RUN_FW(dev);
235 if (err) {
236 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
237 goto err_unmap_fa;
238 }
239
240 return 0;
241
242err_unmap_fa:
243 mlx4_UNMAP_FA(dev);
244
245err_free:
5b0bf5e2 246 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 247 return err;
248}
249
e8f9b2ed
RD		 250static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
251 int cmpt_entry_sz)
225c7b1f
RD		 252{
253 struct mlx4_priv *priv = mlx4_priv(dev);
254 int err;
255
256 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
257 cmpt_base +
258 ((u64) (MLX4_CMPT_TYPE_QP *
259 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
260 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 261 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
262 0, 0);
225c7b1f
RD		 263 if (err)
264 goto err;
265
266 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
267 cmpt_base +
268 ((u64) (MLX4_CMPT_TYPE_SRQ *
269 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
270 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 271 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 272 if (err)
273 goto err_qp;
274
275 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
276 cmpt_base +
277 ((u64) (MLX4_CMPT_TYPE_CQ *
278 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
279 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 280 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 281 if (err)
282 goto err_srq;
283
284 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
285 cmpt_base +
286 ((u64) (MLX4_CMPT_TYPE_EQ *
287 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
288 cmpt_entry_sz,
289 roundup_pow_of_two(MLX4_NUM_EQ +
290 dev->caps.reserved_eqs),
5b0bf5e2 291 MLX4_NUM_EQ + dev->caps.reserved_eqs, 0, 0);
225c7b1f
RD		 292 if (err)
293 goto err_cq;
294
295 return 0;
296
297err_cq:
298 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
299
300err_srq:
301 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
302
303err_qp:
304 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
305
306err:
307 return err;
308}
309
3d73c288
RD		 310static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
311 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 312{
313 struct mlx4_priv *priv = mlx4_priv(dev);
314 u64 aux_pages;
315 int err;
316
317 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
318 if (err) {
319 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
320 return err;
321 }
322
323 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
324 (unsigned long long) icm_size >> 10,
325 (unsigned long long) aux_pages << 2);
326
327 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 328 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 329 if (!priv->fw.aux_icm) {
330 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
331 return -ENOMEM;
332 }
333
334 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
335 if (err) {
336 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
337 goto err_free_aux;
338 }
339
340 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
341 if (err) {
342 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
343 goto err_unmap_aux;
344 }
345
346 err = mlx4_map_eq_icm(dev, init_hca->eqc_base);
347 if (err) {
348 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
349 goto err_unmap_cmpt;
350 }
351
d7bb58fb
JM		 352 /*
353 * Reserved MTT entries must be aligned up to a cacheline
354 * boundary, since the FW will write to them, while the driver
355 * writes to all other MTT entries. (The variable
356 * dev->caps.mtt_entry_sz below is really the MTT segment
357 * size, not the raw entry size)
358 */
359 dev->caps.reserved_mtts =
360 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
361 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
362
225c7b1f
RD		 363 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
364 init_hca->mtt_base,
365 dev->caps.mtt_entry_sz,
366 dev->caps.num_mtt_segs,
5b0bf5e2 367 dev->caps.reserved_mtts, 1, 0);
225c7b1f
RD		 368 if (err) {
369 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
370 goto err_unmap_eq;
371 }
372
373 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
374 init_hca->dmpt_base,
375 dev_cap->dmpt_entry_sz,
376 dev->caps.num_mpts,
5b0bf5e2 377 dev->caps.reserved_mrws, 1, 1);
225c7b1f
RD		 378 if (err) {
379 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
380 goto err_unmap_mtt;
381 }
382
383 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
384 init_hca->qpc_base,
385 dev_cap->qpc_entry_sz,
386 dev->caps.num_qps,
93fc9e1b
YP		 387 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
388 0, 0);
225c7b1f
RD		 389 if (err) {
390 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
391 goto err_unmap_dmpt;
392 }
393
394 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
395 init_hca->auxc_base,
396 dev_cap->aux_entry_sz,
397 dev->caps.num_qps,
93fc9e1b
YP		 398 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
399 0, 0);
225c7b1f
RD		 400 if (err) {
401 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
402 goto err_unmap_qp;
403 }
404
405 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
406 init_hca->altc_base,
407 dev_cap->altc_entry_sz,
408 dev->caps.num_qps,
93fc9e1b
YP		 409 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
410 0, 0);
225c7b1f
RD		 411 if (err) {
412 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
413 goto err_unmap_auxc;
414 }
415
416 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
417 init_hca->rdmarc_base,
418 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
419 dev->caps.num_qps,
93fc9e1b
YP		 420 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
421 0, 0);
225c7b1f
RD		 422 if (err) {
423 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
424 goto err_unmap_altc;
425 }
426
427 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
428 init_hca->cqc_base,
429 dev_cap->cqc_entry_sz,
430 dev->caps.num_cqs,
5b0bf5e2 431 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 432 if (err) {
433 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
434 goto err_unmap_rdmarc;
435 }
436
437 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
438 init_hca->srqc_base,
439 dev_cap->srq_entry_sz,
440 dev->caps.num_srqs,
5b0bf5e2 441 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 442 if (err) {
443 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
444 goto err_unmap_cq;
445 }
446
447 /*
448 * It's not strictly required, but for simplicity just map the
449 * whole multicast group table now. The table isn't very big
450 * and it's a lot easier than trying to track ref counts.
451 */
452 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
453 init_hca->mc_base, MLX4_MGM_ENTRY_SIZE,
454 dev->caps.num_mgms + dev->caps.num_amgms,
455 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 456 0, 0);
225c7b1f
RD		 457 if (err) {
458 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
459 goto err_unmap_srq;
460 }
461
462 return 0;
463
464err_unmap_srq:
465 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
466
467err_unmap_cq:
468 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
469
470err_unmap_rdmarc:
471 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
472
473err_unmap_altc:
474 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
475
476err_unmap_auxc:
477 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
478
479err_unmap_qp:
480 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
481
482err_unmap_dmpt:
483 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
484
485err_unmap_mtt:
486 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
487
488err_unmap_eq:
489 mlx4_unmap_eq_icm(dev);
490
491err_unmap_cmpt:
492 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
493 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
494 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
495 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
496
497err_unmap_aux:
498 mlx4_UNMAP_ICM_AUX(dev);
499
500err_free_aux:
5b0bf5e2 501 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 502
503 return err;
504}
505
506static void mlx4_free_icms(struct mlx4_dev *dev)
507{
508 struct mlx4_priv *priv = mlx4_priv(dev);
509
510 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
511 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
512 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
513 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
514 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
515 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
516 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
517 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
518 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
519 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
520 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
521 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
522 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
523 mlx4_unmap_eq_icm(dev);
524
525 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 526 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 527}
528
529static void mlx4_close_hca(struct mlx4_dev *dev)
530{
531 mlx4_CLOSE_HCA(dev, 0);
532 mlx4_free_icms(dev);
533 mlx4_UNMAP_FA(dev);
5b0bf5e2 534 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
225c7b1f
RD		 535}
536
3d73c288 537static int mlx4_init_hca(struct mlx4_dev *dev)
225c7b1f
RD		 538{
539 struct mlx4_priv *priv = mlx4_priv(dev);
540 struct mlx4_adapter adapter;
541 struct mlx4_dev_cap dev_cap;
2d928651 542 struct mlx4_mod_stat_cfg mlx4_cfg;
225c7b1f
RD		 543 struct mlx4_profile profile;
544 struct mlx4_init_hca_param init_hca;
545 u64 icm_size;
546 int err;
547
548 err = mlx4_QUERY_FW(dev);
549 if (err) {
550 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
551 return err;
552 }
553
554 err = mlx4_load_fw(dev);
555 if (err) {
556 mlx4_err(dev, "Failed to start FW, aborting.\n");
557 return err;
558 }
559
2d928651
VS		 560 mlx4_cfg.log_pg_sz_m = 1;
561 mlx4_cfg.log_pg_sz = 0;
562 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
563 if (err)
564 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
565
225c7b1f
RD		 566 err = mlx4_dev_cap(dev, &dev_cap);
567 if (err) {
568 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
569 goto err_stop_fw;
570 }
571
572 profile = default_profile;
573
574 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, &init_hca);
575 if ((long long) icm_size < 0) {
576 err = icm_size;
577 goto err_stop_fw;
578 }
579
580 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
581
582 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
583 if (err)
584 goto err_stop_fw;
585
586 err = mlx4_INIT_HCA(dev, &init_hca);
587 if (err) {
588 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
589 goto err_free_icm;
590 }
591
592 err = mlx4_QUERY_ADAPTER(dev, &adapter);
593 if (err) {
594 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
595 goto err_close;
596 }
597
598 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8 599 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 600
601 return 0;
602
603err_close:
604 mlx4_close_hca(dev);
605
606err_free_icm:
607 mlx4_free_icms(dev);
608
609err_stop_fw:
610 mlx4_UNMAP_FA(dev);
5b0bf5e2 611 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 612
613 return err;
614}
615
3d73c288 616static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 617{
618 struct mlx4_priv *priv = mlx4_priv(dev);
619 int err;
620
225c7b1f
RD		 621 err = mlx4_init_uar_table(dev);
622 if (err) {
623 mlx4_err(dev, "Failed to initialize "
624 "user access region table, aborting.\n");
625 return err;
626 }
627
628 err = mlx4_uar_alloc(dev, &priv->driver_uar);
629 if (err) {
630 mlx4_err(dev, "Failed to allocate driver access region, "
631 "aborting.\n");
632 goto err_uar_table_free;
633 }
634
635 priv->kar = ioremap(priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
636 if (!priv->kar) {
637 mlx4_err(dev, "Couldn't map kernel access region, "
638 "aborting.\n");
639 err = -ENOMEM;
640 goto err_uar_free;
641 }
642
643 err = mlx4_init_pd_table(dev);
644 if (err) {
645 mlx4_err(dev, "Failed to initialize "
646 "protection domain table, aborting.\n");
647 goto err_kar_unmap;
648 }
649
650 err = mlx4_init_mr_table(dev);
651 if (err) {
652 mlx4_err(dev, "Failed to initialize "
653 "memory region table, aborting.\n");
654 goto err_pd_table_free;
655 }
656
225c7b1f
RD		 657 err = mlx4_init_eq_table(dev);
658 if (err) {
659 mlx4_err(dev, "Failed to initialize "
660 "event queue table, aborting.\n");
ee49bd93 661 goto err_mr_table_free;
225c7b1f
RD		 662 }
663
664 err = mlx4_cmd_use_events(dev);
665 if (err) {
666 mlx4_err(dev, "Failed to switch to event-driven "
667 "firmware commands, aborting.\n");
668 goto err_eq_table_free;
669 }
670
671 err = mlx4_NOP(dev);
672 if (err) {
08fb1055
MT		 673 if (dev->flags & MLX4_FLAG_MSI_X) {
674 mlx4_warn(dev, "NOP command failed to generate MSI-X "
675 "interrupt IRQ %d).\n",
676 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
677 mlx4_warn(dev, "Trying again without MSI-X.\n");
678 } else {
679 mlx4_err(dev, "NOP command failed to generate interrupt "
680 "(IRQ %d), aborting.\n",
681 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
225c7b1f 682 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 683 }
225c7b1f
RD		 684
685 goto err_cmd_poll;
686 }
687
688 mlx4_dbg(dev, "NOP command IRQ test passed\n");
689
690 err = mlx4_init_cq_table(dev);
691 if (err) {
692 mlx4_err(dev, "Failed to initialize "
693 "completion queue table, aborting.\n");
694 goto err_cmd_poll;
695 }
696
697 err = mlx4_init_srq_table(dev);
698 if (err) {
699 mlx4_err(dev, "Failed to initialize "
700 "shared receive queue table, aborting.\n");
701 goto err_cq_table_free;
702 }
703
704 err = mlx4_init_qp_table(dev);
705 if (err) {
706 mlx4_err(dev, "Failed to initialize "
707 "queue pair table, aborting.\n");
708 goto err_srq_table_free;
709 }
710
711 err = mlx4_init_mcg_table(dev);
712 if (err) {
713 mlx4_err(dev, "Failed to initialize "
714 "multicast group table, aborting.\n");
715 goto err_qp_table_free;
716 }
717
718 return 0;
719
720err_qp_table_free:
721 mlx4_cleanup_qp_table(dev);
722
723err_srq_table_free:
724 mlx4_cleanup_srq_table(dev);
725
726err_cq_table_free:
727 mlx4_cleanup_cq_table(dev);
728
729err_cmd_poll:
730 mlx4_cmd_use_polling(dev);
731
732err_eq_table_free:
733 mlx4_cleanup_eq_table(dev);
734
ee49bd93 735err_mr_table_free:
225c7b1f
RD		 736 mlx4_cleanup_mr_table(dev);
737
738err_pd_table_free:
739 mlx4_cleanup_pd_table(dev);
740
741err_kar_unmap:
742 iounmap(priv->kar);
743
744err_uar_free:
745 mlx4_uar_free(dev, &priv->driver_uar);
746
747err_uar_table_free:
748 mlx4_cleanup_uar_table(dev);
749 return err;
750}
751
e8f9b2ed 752static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 753{
754 struct mlx4_priv *priv = mlx4_priv(dev);
755 struct msix_entry entries[MLX4_NUM_EQ];
756 int err;
757 int i;
758
759 if (msi_x) {
760 for (i = 0; i < MLX4_NUM_EQ; ++i)
761 entries[i].entry = i;
762
763 err = pci_enable_msix(dev->pdev, entries, ARRAY_SIZE(entries));
764 if (err) {
765 if (err > 0)
766 mlx4_info(dev, "Only %d MSI-X vectors available, "
767 "not using MSI-X\n", err);
768 goto no_msi;
769 }
770
771 for (i = 0; i < MLX4_NUM_EQ; ++i)
772 priv->eq_table.eq[i].irq = entries[i].vector;
773
774 dev->flags |= MLX4_FLAG_MSI_X;
775 return;
776 }
777
778no_msi:
779 for (i = 0; i < MLX4_NUM_EQ; ++i)
780 priv->eq_table.eq[i].irq = dev->pdev->irq;
781}
782
2a2336f8
YP		 783static void mlx4_init_port_info(struct mlx4_dev *dev, int port)
784{
785 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
786
787 info->dev = dev;
788 info->port = port;
789 mlx4_init_mac_table(dev, &info->mac_table);
790 mlx4_init_vlan_table(dev, &info->vlan_table);
791}
792
3d73c288 793static int __mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
225c7b1f 794{
225c7b1f
RD		 795 struct mlx4_priv *priv;
796 struct mlx4_dev *dev;
797 int err;
2a2336f8 798 int port;
225c7b1f 799
225c7b1f
RD		 800 printk(KERN_INFO PFX "Initializing %s\n",
801 pci_name(pdev));
802
803 err = pci_enable_device(pdev);
804 if (err) {
805 dev_err(&pdev->dev, "Cannot enable PCI device, "
806 "aborting.\n");
807 return err;
808 }
809
810 /*
4ff08a76 811 * Check for BARs. We expect 0: 1MB
225c7b1f
RD		 812 */
813 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
814 pci_resource_len(pdev, 0) != 1 << 20) {
815 dev_err(&pdev->dev, "Missing DCS, aborting.\n");
816 err = -ENODEV;
817 goto err_disable_pdev;
818 }
819 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
820 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
821 err = -ENODEV;
822 goto err_disable_pdev;
823 }
824
825 err = pci_request_region(pdev, 0, DRV_NAME);
826 if (err) {
827 dev_err(&pdev->dev, "Cannot request control region, aborting.\n");
828 goto err_disable_pdev;
829 }
830
831 err = pci_request_region(pdev, 2, DRV_NAME);
832 if (err) {
833 dev_err(&pdev->dev, "Cannot request UAR region, aborting.\n");
834 goto err_release_bar0;
835 }
836
837 pci_set_master(pdev);
838
839 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
840 if (err) {
841 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
842 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
843 if (err) {
844 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
845 goto err_release_bar2;
846 }
847 }
848 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
849 if (err) {
850 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
851 "consistent PCI DMA mask.\n");
852 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
853 if (err) {
854 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
855 "aborting.\n");
856 goto err_release_bar2;
857 }
858 }
859
860 priv = kzalloc(sizeof *priv, GFP_KERNEL);
861 if (!priv) {
862 dev_err(&pdev->dev, "Device struct alloc failed, "
863 "aborting.\n");
864 err = -ENOMEM;
865 goto err_release_bar2;
866 }
867
868 dev = &priv->dev;
869 dev->pdev = pdev;
b581401e
RD		 870 INIT_LIST_HEAD(&priv->ctx_list);
871 spin_lock_init(&priv->ctx_lock);
225c7b1f 872
6296883c
YP		 873 INIT_LIST_HEAD(&priv->pgdir_list);
874 mutex_init(&priv->pgdir_mutex);
875
225c7b1f
RD		 876 /*
877 * Now reset the HCA before we touch the PCI capabilities or
878 * attempt a firmware command, since a boot ROM may have left
879 * the HCA in an undefined state.
880 */
881 err = mlx4_reset(dev);
882 if (err) {
883 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
884 goto err_free_dev;
885 }
886
225c7b1f
RD		 887 if (mlx4_cmd_init(dev)) {
888 mlx4_err(dev, "Failed to init command interface, aborting.\n");
889 goto err_free_dev;
890 }
891
892 err = mlx4_init_hca(dev);
893 if (err)
894 goto err_cmd;
895
08fb1055
MT		 896 mlx4_enable_msi_x(dev);
897
225c7b1f 898 err = mlx4_setup_hca(dev);
08fb1055
MT		 899 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X)) {
900 dev->flags &= ~MLX4_FLAG_MSI_X;
901 pci_disable_msix(pdev);
902 err = mlx4_setup_hca(dev);
903 }
904
225c7b1f
RD		 905 if (err)
906 goto err_close;
907
2a2336f8
YP		 908 for (port = 1; port <= dev->caps.num_ports; port++)
909 mlx4_init_port_info(dev, port);
910
225c7b1f
RD		 911 err = mlx4_register_device(dev);
912 if (err)
913 goto err_cleanup;
914
915 pci_set_drvdata(pdev, dev);
916
917 return 0;
918
919err_cleanup:
920 mlx4_cleanup_mcg_table(dev);
921 mlx4_cleanup_qp_table(dev);
922 mlx4_cleanup_srq_table(dev);
923 mlx4_cleanup_cq_table(dev);
924 mlx4_cmd_use_polling(dev);
925 mlx4_cleanup_eq_table(dev);
225c7b1f
RD		 926 mlx4_cleanup_mr_table(dev);
927 mlx4_cleanup_pd_table(dev);
928 mlx4_cleanup_uar_table(dev);
929
930err_close:
08fb1055
MT		 931 if (dev->flags & MLX4_FLAG_MSI_X)
932 pci_disable_msix(pdev);
933
225c7b1f
RD		 934 mlx4_close_hca(dev);
935
936err_cmd:
937 mlx4_cmd_cleanup(dev);
938
939err_free_dev:
225c7b1f
RD		 940 kfree(priv);
941
942err_release_bar2:
943 pci_release_region(pdev, 2);
944
945err_release_bar0:
946 pci_release_region(pdev, 0);
947
948err_disable_pdev:
949 pci_disable_device(pdev);
950 pci_set_drvdata(pdev, NULL);
951 return err;
952}
953
3d73c288
RD		 954static int __devinit mlx4_init_one(struct pci_dev *pdev,
955 const struct pci_device_id *id)
956{
957 static int mlx4_version_printed;
958
959 if (!mlx4_version_printed) {
960 printk(KERN_INFO "%s", mlx4_version);
961 ++mlx4_version_printed;
962 }
963
b027cacd 964 return __mlx4_init_one(pdev, id);
3d73c288
RD		 965}
966
967static void mlx4_remove_one(struct pci_dev *pdev)
225c7b1f
RD		 968{
969 struct mlx4_dev *dev = pci_get_drvdata(pdev);
970 struct mlx4_priv *priv = mlx4_priv(dev);
971 int p;
972
973 if (dev) {
974 mlx4_unregister_device(dev);
975
976 for (p = 1; p <= dev->caps.num_ports; ++p)
977 mlx4_CLOSE_PORT(dev, p);
978
979 mlx4_cleanup_mcg_table(dev);
980 mlx4_cleanup_qp_table(dev);
981 mlx4_cleanup_srq_table(dev);
982 mlx4_cleanup_cq_table(dev);
983 mlx4_cmd_use_polling(dev);
984 mlx4_cleanup_eq_table(dev);
225c7b1f
RD		 985 mlx4_cleanup_mr_table(dev);
986 mlx4_cleanup_pd_table(dev);
987
988 iounmap(priv->kar);
989 mlx4_uar_free(dev, &priv->driver_uar);
990 mlx4_cleanup_uar_table(dev);
991 mlx4_close_hca(dev);
992 mlx4_cmd_cleanup(dev);
993
994 if (dev->flags & MLX4_FLAG_MSI_X)
995 pci_disable_msix(pdev);
996
997 kfree(priv);
998 pci_release_region(pdev, 2);
999 pci_release_region(pdev, 0);
1000 pci_disable_device(pdev);
1001 pci_set_drvdata(pdev, NULL);
1002 }
1003}
1004
ee49bd93
JM		 1005int mlx4_restart_one(struct pci_dev *pdev)
1006{
1007 mlx4_remove_one(pdev);
3d73c288 1008 return __mlx4_init_one(pdev, NULL);
ee49bd93
JM		 1009}
1010
225c7b1f
RD		 1011static struct pci_device_id mlx4_pci_table[] = {
1012 { PCI_VDEVICE(MELLANOX, 0x6340) }, /* MT25408 "Hermon" SDR */
1013 { PCI_VDEVICE(MELLANOX, 0x634a) }, /* MT25408 "Hermon" DDR */
1014 { PCI_VDEVICE(MELLANOX, 0x6354) }, /* MT25408 "Hermon" QDR */
786f238e
JM		 1015 { PCI_VDEVICE(MELLANOX, 0x6732) }, /* MT25408 "Hermon" DDR PCIe gen2 */
1016 { PCI_VDEVICE(MELLANOX, 0x673c) }, /* MT25408 "Hermon" QDR PCIe gen2 */
225c7b1f
RD		 1017 { 0, }
1018};
1019
1020MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
1021
1022static struct pci_driver mlx4_driver = {
1023 .name = DRV_NAME,
1024 .id_table = mlx4_pci_table,
1025 .probe = mlx4_init_one,
1026 .remove = __devexit_p(mlx4_remove_one)
1027};
1028
1029static int __init mlx4_init(void)
1030{
1031 int ret;
1032
ee49bd93
JM		 1033 ret = mlx4_catas_init();
1034 if (ret)
1035 return ret;
1036
225c7b1f
RD		 1037 ret = pci_register_driver(&mlx4_driver);
1038 return ret < 0 ? ret : 0;
1039}
1040
1041static void __exit mlx4_cleanup(void)
1042{
1043 pci_unregister_driver(&mlx4_driver);
ee49bd93 1044 mlx4_catas_cleanup();
225c7b1f
RD		 1045}
1046
1047module_init(mlx4_init);
1048module_exit(mlx4_cleanup);
kernel source for telekom puls (alcatel/mediatek)