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mlx4_core: Get ethernet MTU and default address from firmware
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / mlx4 / fw.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#include <linux/mlx4/cmd.h>
36
37#include "fw.h"
38#include "icm.h"
39
fe40900f 40enum {
5ae2a7a8
RD		 41 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
42 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
43 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
fe40900f
RD		 44};
45
225c7b1f
RD		 46extern void __buggy_use_of_MLX4_GET(void);
47extern void __buggy_use_of_MLX4_PUT(void);
48
51f5f0ee
JM		 49static int enable_qos;
50module_param(enable_qos, bool, 0444);
51MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
52
225c7b1f
RD		 53#define MLX4_GET(dest, source, offset) \
54 do { \
55 void *__p = (char *) (source) + (offset); \
56 switch (sizeof (dest)) { \
57 case 1: (dest) = *(u8 *) __p; break; \
58 case 2: (dest) = be16_to_cpup(__p); break; \
59 case 4: (dest) = be32_to_cpup(__p); break; \
60 case 8: (dest) = be64_to_cpup(__p); break; \
61 default: __buggy_use_of_MLX4_GET(); \
62 } \
63 } while (0)
64
65#define MLX4_PUT(dest, source, offset) \
66 do { \
67 void *__d = ((char *) (dest) + (offset)); \
68 switch (sizeof(source)) { \
69 case 1: *(u8 *) __d = (source); break; \
70 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
71 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
72 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
73 default: __buggy_use_of_MLX4_PUT(); \
74 } \
75 } while (0)
76
77static void dump_dev_cap_flags(struct mlx4_dev *dev, u32 flags)
78{
79 static const char *fname[] = {
80 [ 0] = "RC transport",
81 [ 1] = "UC transport",
82 [ 2] = "UD transport",
ea98054f 83 [ 3] = "XRC transport",
225c7b1f
RD		 84 [ 4] = "reliable multicast",
85 [ 5] = "FCoIB support",
86 [ 6] = "SRQ support",
87 [ 7] = "IPoIB checksum offload",
88 [ 8] = "P_Key violation counter",
89 [ 9] = "Q_Key violation counter",
90 [10] = "VMM",
91 [16] = "MW support",
92 [17] = "APM support",
93 [18] = "Atomic ops support",
94 [19] = "Raw multicast support",
95 [20] = "Address vector port checking support",
96 [21] = "UD multicast support",
97 [24] = "Demand paging support",
98 [25] = "Router support"
99 };
100 int i;
101
102 mlx4_dbg(dev, "DEV_CAP flags:\n");
23c15c21 103 for (i = 0; i < ARRAY_SIZE(fname); ++i)
225c7b1f
RD		 104 if (fname[i] && (flags & (1 << i)))
105 mlx4_dbg(dev, " %s\n", fname[i]);
106}
107
2d928651
VS		 108int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
109{
110 struct mlx4_cmd_mailbox *mailbox;
111 u32 *inbox;
112 int err = 0;
113
114#define MOD_STAT_CFG_IN_SIZE 0x100
115
116#define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
117#define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
118
119 mailbox = mlx4_alloc_cmd_mailbox(dev);
120 if (IS_ERR(mailbox))
121 return PTR_ERR(mailbox);
122 inbox = mailbox->buf;
123
124 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
125
126 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
127 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
128
129 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
130 MLX4_CMD_TIME_CLASS_A);
131
132 mlx4_free_cmd_mailbox(dev, mailbox);
133 return err;
134}
135
225c7b1f
RD		 136int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
137{
138 struct mlx4_cmd_mailbox *mailbox;
139 u32 *outbox;
140 u8 field;
141 u16 size;
142 u16 stat_rate;
143 int err;
5ae2a7a8 144 int i;
225c7b1f
RD		 145
146#define QUERY_DEV_CAP_OUT_SIZE 0x100
147#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
148#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
149#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
150#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
151#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
152#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
153#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
154#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
155#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
156#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
157#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
158#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
159#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
160#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
161#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
162#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
163#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
164#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
165#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
166#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
167#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
b832be1e 168#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
225c7b1f
RD		 169#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
170#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
171#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
172#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
173#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
149983af 174#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
225c7b1f
RD		 175#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
176#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
177#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
178#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
179#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
180#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
181#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
182#define QUERY_DEV_CAP_BF_OFFSET 0x4c
183#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
184#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
185#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
186#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
187#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
188#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
189#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
190#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
191#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
192#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
193#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
194#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
195#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
196#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
197#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
198#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
199#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
200#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
201#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
202#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
203#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
204#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
95d04f07 205#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
225c7b1f
RD		 206#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
207#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
208
209 mailbox = mlx4_alloc_cmd_mailbox(dev);
210 if (IS_ERR(mailbox))
211 return PTR_ERR(mailbox);
212 outbox = mailbox->buf;
213
214 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
215 MLX4_CMD_TIME_CLASS_A);
225c7b1f
RD		 216 if (err)
217 goto out;
218
219 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
220 dev_cap->reserved_qps = 1 << (field & 0xf);
221 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
222 dev_cap->max_qps = 1 << (field & 0x1f);
223 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
224 dev_cap->reserved_srqs = 1 << (field >> 4);
225 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
226 dev_cap->max_srqs = 1 << (field & 0x1f);
227 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
228 dev_cap->max_cq_sz = 1 << field;
229 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
230 dev_cap->reserved_cqs = 1 << (field & 0xf);
231 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
232 dev_cap->max_cqs = 1 << (field & 0x1f);
233 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
234 dev_cap->max_mpts = 1 << (field & 0x3f);
235 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
236 dev_cap->reserved_eqs = 1 << (field & 0xf);
237 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
5920869f 238 dev_cap->max_eqs = 1 << (field & 0xf);
225c7b1f
RD		 239 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
240 dev_cap->reserved_mtts = 1 << (field >> 4);
241 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
242 dev_cap->max_mrw_sz = 1 << field;
243 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
244 dev_cap->reserved_mrws = 1 << (field & 0xf);
245 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
246 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
247 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
248 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
249 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
250 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
b832be1e
EC		 251 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
252 field &= 0x1f;
253 if (!field)
254 dev_cap->max_gso_sz = 0;
255 else
256 dev_cap->max_gso_sz = 1 << field;
257
225c7b1f
RD		 258 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
259 dev_cap->max_rdma_global = 1 << (field & 0x3f);
260 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
261 dev_cap->local_ca_ack_delay = field & 0x1f;
225c7b1f 262 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
225c7b1f 263 dev_cap->num_ports = field & 0xf;
149983af
DB		 264 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
265 dev_cap->max_msg_sz = 1 << (field & 0x1f);
225c7b1f
RD		 266 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
267 dev_cap->stat_rate_support = stat_rate;
225c7b1f
RD		 268 MLX4_GET(dev_cap->flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
269 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
270 dev_cap->reserved_uars = field >> 4;
271 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
272 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
273 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
274 dev_cap->min_page_sz = 1 << field;
275
276 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
277 if (field & 0x80) {
278 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
279 dev_cap->bf_reg_size = 1 << (field & 0x1f);
280 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
281 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
282 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
283 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
284 } else {
285 dev_cap->bf_reg_size = 0;
286 mlx4_dbg(dev, "BlueFlame not available\n");
287 }
288
289 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
290 dev_cap->max_sq_sg = field;
291 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
292 dev_cap->max_sq_desc_sz = size;
293
294 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
295 dev_cap->max_qp_per_mcg = 1 << field;
296 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
297 dev_cap->reserved_mgms = field & 0xf;
298 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
299 dev_cap->max_mcgs = 1 << field;
300 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
301 dev_cap->reserved_pds = field >> 4;
302 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
303 dev_cap->max_pds = 1 << (field & 0x3f);
304
305 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
306 dev_cap->rdmarc_entry_sz = size;
307 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
308 dev_cap->qpc_entry_sz = size;
309 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
310 dev_cap->aux_entry_sz = size;
311 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
312 dev_cap->altc_entry_sz = size;
313 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
314 dev_cap->eqc_entry_sz = size;
315 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
316 dev_cap->cqc_entry_sz = size;
317 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
318 dev_cap->srq_entry_sz = size;
319 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
320 dev_cap->cmpt_entry_sz = size;
321 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
322 dev_cap->mtt_entry_sz = size;
323 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
324 dev_cap->dmpt_entry_sz = size;
325
326 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
327 dev_cap->max_srq_sz = 1 << field;
328 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
329 dev_cap->max_qp_sz = 1 << field;
330 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
331 dev_cap->resize_srq = field & 1;
332 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
333 dev_cap->max_rq_sg = field;
334 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
335 dev_cap->max_rq_desc_sz = size;
336
337 MLX4_GET(dev_cap->bmme_flags, outbox,
338 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
339 MLX4_GET(dev_cap->reserved_lkey, outbox,
340 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
341 MLX4_GET(dev_cap->max_icm_sz, outbox,
342 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
343
5ae2a7a8
RD		 344 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
345 for (i = 1; i <= dev_cap->num_ports; ++i) {
346 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
347 dev_cap->max_vl[i] = field >> 4;
348 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
b79acb49 349 dev_cap->ib_mtu[i] = field >> 4;
5ae2a7a8
RD		 350 dev_cap->max_port_width[i] = field & 0xf;
351 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
352 dev_cap->max_gids[i] = 1 << (field & 0xf);
353 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
354 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
355 }
356 } else {
357#define QUERY_PORT_MTU_OFFSET 0x01
b79acb49 358#define QUERY_PORT_ETH_MTU_OFFSET 0x02
5ae2a7a8
RD		 359#define QUERY_PORT_WIDTH_OFFSET 0x06
360#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
b79acb49 361#define QUERY_PORT_MAC_OFFSET 0x08
93fc9e1b 362#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
5ae2a7a8
RD		 363#define QUERY_PORT_MAX_VL_OFFSET 0x0b
364
365 for (i = 1; i <= dev_cap->num_ports; ++i) {
366 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
367 MLX4_CMD_TIME_CLASS_B);
368 if (err)
369 goto out;
370
371 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
b79acb49 372 dev_cap->ib_mtu[i] = field & 0xf;
5ae2a7a8
RD		 373 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
374 dev_cap->max_port_width[i] = field & 0xf;
375 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
376 dev_cap->max_gids[i] = 1 << (field >> 4);
377 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
378 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
379 dev_cap->max_vl[i] = field & 0xf;
93fc9e1b
YP		 380 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
381 dev_cap->log_max_macs[i] = field & 0xf;
382 dev_cap->log_max_vlans[i] = field >> 4;
b79acb49
YP		 383 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
384 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
5ae2a7a8
RD		 385 }
386 }
387
95d04f07
RD		 388 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
389 dev_cap->bmme_flags, dev_cap->reserved_lkey);
225c7b1f
RD		 390
391 /*
392 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
393 * we can't use any EQs whose doorbell falls on that page,
394 * even if the EQ itself isn't reserved.
395 */
396 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
397 dev_cap->reserved_eqs);
398
399 mlx4_dbg(dev, "Max ICM size %lld MB\n",
400 (unsigned long long) dev_cap->max_icm_sz >> 20);
401 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
402 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
403 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
404 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
405 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
406 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
407 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
408 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
409 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
410 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
411 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
412 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
413 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
414 dev_cap->max_pds, dev_cap->reserved_mgms);
415 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
416 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
417 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
b79acb49 418 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
5ae2a7a8 419 dev_cap->max_port_width[1]);
225c7b1f
RD		 420 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
421 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
422 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
423 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
b832be1e 424 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
225c7b1f
RD		 425
426 dump_dev_cap_flags(dev, dev_cap->flags);
427
428out:
429 mlx4_free_cmd_mailbox(dev, mailbox);
430 return err;
431}
432
433int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
434{
435 struct mlx4_cmd_mailbox *mailbox;
436 struct mlx4_icm_iter iter;
437 __be64 *pages;
438 int lg;
439 int nent = 0;
440 int i;
441 int err = 0;
442 int ts = 0, tc = 0;
443
444 mailbox = mlx4_alloc_cmd_mailbox(dev);
445 if (IS_ERR(mailbox))
446 return PTR_ERR(mailbox);
447 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
448 pages = mailbox->buf;
449
450 for (mlx4_icm_first(icm, &iter);
451 !mlx4_icm_last(&iter);
452 mlx4_icm_next(&iter)) {
453 /*
454 * We have to pass pages that are aligned to their
455 * size, so find the least significant 1 in the
456 * address or size and use that as our log2 size.
457 */
458 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
459 if (lg < MLX4_ICM_PAGE_SHIFT) {
460 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
461 MLX4_ICM_PAGE_SIZE,
462 (unsigned long long) mlx4_icm_addr(&iter),
463 mlx4_icm_size(&iter));
464 err = -EINVAL;
465 goto out;
466 }
467
468 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
469 if (virt != -1) {
470 pages[nent * 2] = cpu_to_be64(virt);
471 virt += 1 << lg;
472 }
473
474 pages[nent * 2 + 1] =
475 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
476 (lg - MLX4_ICM_PAGE_SHIFT));
477 ts += 1 << (lg - 10);
478 ++tc;
479
480 if (++nent == MLX4_MAILBOX_SIZE / 16) {
481 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
482 MLX4_CMD_TIME_CLASS_B);
483 if (err)
484 goto out;
485 nent = 0;
486 }
487 }
488 }
489
490 if (nent)
491 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, MLX4_CMD_TIME_CLASS_B);
492 if (err)
493 goto out;
494
495 switch (op) {
496 case MLX4_CMD_MAP_FA:
497 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
498 break;
499 case MLX4_CMD_MAP_ICM_AUX:
500 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
501 break;
502 case MLX4_CMD_MAP_ICM:
503 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
504 tc, ts, (unsigned long long) virt - (ts << 10));
505 break;
506 }
507
508out:
509 mlx4_free_cmd_mailbox(dev, mailbox);
510 return err;
511}
512
513int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
514{
515 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
516}
517
518int mlx4_UNMAP_FA(struct mlx4_dev *dev)
519{
520 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, MLX4_CMD_TIME_CLASS_B);
521}
522
523
524int mlx4_RUN_FW(struct mlx4_dev *dev)
525{
526 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, MLX4_CMD_TIME_CLASS_A);
527}
528
529int mlx4_QUERY_FW(struct mlx4_dev *dev)
530{
531 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
532 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
533 struct mlx4_cmd_mailbox *mailbox;
534 u32 *outbox;
535 int err = 0;
536 u64 fw_ver;
fe40900f 537 u16 cmd_if_rev;
225c7b1f
RD		 538 u8 lg;
539
540#define QUERY_FW_OUT_SIZE 0x100
541#define QUERY_FW_VER_OFFSET 0x00
fe40900f 542#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
225c7b1f
RD		 543#define QUERY_FW_MAX_CMD_OFFSET 0x0f
544#define QUERY_FW_ERR_START_OFFSET 0x30
545#define QUERY_FW_ERR_SIZE_OFFSET 0x38
546#define QUERY_FW_ERR_BAR_OFFSET 0x3c
547
548#define QUERY_FW_SIZE_OFFSET 0x00
549#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
550#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
551
552 mailbox = mlx4_alloc_cmd_mailbox(dev);
553 if (IS_ERR(mailbox))
554 return PTR_ERR(mailbox);
555 outbox = mailbox->buf;
556
557 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
558 MLX4_CMD_TIME_CLASS_A);
559 if (err)
560 goto out;
561
562 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
563 /*
3e1db334 564 * FW subminor version is at more significant bits than minor
225c7b1f
RD		 565 * version, so swap here.
566 */
567 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
568 ((fw_ver & 0xffff0000ull) >> 16) |
569 ((fw_ver & 0x0000ffffull) << 16);
570
fe40900f 571 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
5ae2a7a8
RD		 572 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
573 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
fe40900f
RD		 574 mlx4_err(dev, "Installed FW has unsupported "
575 "command interface revision %d.\n",
576 cmd_if_rev);
577 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
578 (int) (dev->caps.fw_ver >> 32),
579 (int) (dev->caps.fw_ver >> 16) & 0xffff,
580 (int) dev->caps.fw_ver & 0xffff);
5ae2a7a8
RD		 581 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
582 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
fe40900f
RD		 583 err = -ENODEV;
584 goto out;
585 }
586
5ae2a7a8
RD		 587 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
588 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
589
225c7b1f
RD		 590 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
591 cmd->max_cmds = 1 << lg;
592
fe40900f 593 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
225c7b1f
RD		 594 (int) (dev->caps.fw_ver >> 32),
595 (int) (dev->caps.fw_ver >> 16) & 0xffff,
596 (int) dev->caps.fw_ver & 0xffff,
fe40900f 597 cmd_if_rev, cmd->max_cmds);
225c7b1f
RD		 598
599 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
600 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
601 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
602 fw->catas_bar = (fw->catas_bar >> 6) * 2;
603
604 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
605 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
606
607 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
608 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
609 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
610 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
611
612 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
613
614 /*
615 * Round up number of system pages needed in case
616 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
617 */
618 fw->fw_pages =
619 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
620 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
621
622 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
623 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
624
625out:
626 mlx4_free_cmd_mailbox(dev, mailbox);
627 return err;
628}
629
630static void get_board_id(void *vsd, char *board_id)
631{
632 int i;
633
634#define VSD_OFFSET_SIG1 0x00
635#define VSD_OFFSET_SIG2 0xde
636#define VSD_OFFSET_MLX_BOARD_ID 0xd0
637#define VSD_OFFSET_TS_BOARD_ID 0x20
638
639#define VSD_SIGNATURE_TOPSPIN 0x5ad
640
641 memset(board_id, 0, MLX4_BOARD_ID_LEN);
642
643 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
644 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
645 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
646 } else {
647 /*
648 * The board ID is a string but the firmware byte
649 * swaps each 4-byte word before passing it back to
650 * us. Therefore we need to swab it before printing.
651 */
652 for (i = 0; i < 4; ++i)
653 ((u32 *) board_id)[i] =
654 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
655 }
656}
657
658int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
659{
660 struct mlx4_cmd_mailbox *mailbox;
661 u32 *outbox;
662 int err;
663
664#define QUERY_ADAPTER_OUT_SIZE 0x100
225c7b1f
RD		 665#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
666#define QUERY_ADAPTER_VSD_OFFSET 0x20
667
668 mailbox = mlx4_alloc_cmd_mailbox(dev);
669 if (IS_ERR(mailbox))
670 return PTR_ERR(mailbox);
671 outbox = mailbox->buf;
672
673 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
674 MLX4_CMD_TIME_CLASS_A);
675 if (err)
676 goto out;
677
225c7b1f
RD		 678 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
679
680 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
681 adapter->board_id);
682
683out:
684 mlx4_free_cmd_mailbox(dev, mailbox);
685 return err;
686}
687
688int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
689{
690 struct mlx4_cmd_mailbox *mailbox;
691 __be32 *inbox;
692 int err;
693
694#define INIT_HCA_IN_SIZE 0x200
695#define INIT_HCA_VERSION_OFFSET 0x000
696#define INIT_HCA_VERSION 2
697#define INIT_HCA_FLAGS_OFFSET 0x014
698#define INIT_HCA_QPC_OFFSET 0x020
699#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
700#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
701#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
702#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
703#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
704#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
705#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
706#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
707#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
708#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
709#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
710#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
711#define INIT_HCA_MCAST_OFFSET 0x0c0
712#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
713#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
714#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
715#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
716#define INIT_HCA_TPT_OFFSET 0x0f0
717#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
718#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
719#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
720#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
721#define INIT_HCA_UAR_OFFSET 0x120
722#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
723#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
724
725 mailbox = mlx4_alloc_cmd_mailbox(dev);
726 if (IS_ERR(mailbox))
727 return PTR_ERR(mailbox);
728 inbox = mailbox->buf;
729
730 memset(inbox, 0, INIT_HCA_IN_SIZE);
731
732 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
733
734#if defined(__LITTLE_ENDIAN)
735 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
736#elif defined(__BIG_ENDIAN)
737 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
738#else
739#error Host endianness not defined
740#endif
741 /* Check port for UD address vector: */
742 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
743
8ff095ec
EC		 744 /* Enable IPoIB checksumming if we can: */
745 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
746 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
747
51f5f0ee
JM		 748 /* Enable QoS support if module parameter set */
749 if (enable_qos)
750 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
751
225c7b1f
RD		 752 /* QPC/EEC/CQC/EQC/RDMARC attributes */
753
754 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
755 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
756 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
757 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
758 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
759 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
760 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
761 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
762 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
763 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
764 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
765 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
766
767 /* multicast attributes */
768
769 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
770 MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
771 MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
772 MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
773
774 /* TPT attributes */
775
776 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
777 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
778 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
779 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
780
781 /* UAR attributes */
782
783 MLX4_PUT(inbox, (u8) (PAGE_SHIFT - 12), INIT_HCA_UAR_PAGE_SZ_OFFSET);
784 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
785
77109cc2 786 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000);
225c7b1f
RD		 787
788 if (err)
789 mlx4_err(dev, "INIT_HCA returns %d\n", err);
790
791 mlx4_free_cmd_mailbox(dev, mailbox);
792 return err;
793}
794
5ae2a7a8 795int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
225c7b1f
RD		 796{
797 struct mlx4_cmd_mailbox *mailbox;
798 u32 *inbox;
799 int err;
800 u32 flags;
5ae2a7a8 801 u16 field;
225c7b1f 802
5ae2a7a8 803 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
225c7b1f
RD		 804#define INIT_PORT_IN_SIZE 256
805#define INIT_PORT_FLAGS_OFFSET 0x00
806#define INIT_PORT_FLAG_SIG (1 << 18)
807#define INIT_PORT_FLAG_NG (1 << 17)
808#define INIT_PORT_FLAG_G0 (1 << 16)
809#define INIT_PORT_VL_SHIFT 4
810#define INIT_PORT_PORT_WIDTH_SHIFT 8
811#define INIT_PORT_MTU_OFFSET 0x04
812#define INIT_PORT_MAX_GID_OFFSET 0x06
813#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
814#define INIT_PORT_GUID0_OFFSET 0x10
815#define INIT_PORT_NODE_GUID_OFFSET 0x18
816#define INIT_PORT_SI_GUID_OFFSET 0x20
817
5ae2a7a8
RD		 818 mailbox = mlx4_alloc_cmd_mailbox(dev);
819 if (IS_ERR(mailbox))
820 return PTR_ERR(mailbox);
821 inbox = mailbox->buf;
225c7b1f 822
5ae2a7a8 823 memset(inbox, 0, INIT_PORT_IN_SIZE);
225c7b1f 824
5ae2a7a8
RD		 825 flags = 0;
826 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
827 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
828 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
225c7b1f 829
b79acb49 830 field = 128 << dev->caps.ib_mtu_cap[port];
5ae2a7a8
RD		 831 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
832 field = dev->caps.gid_table_len[port];
833 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
834 field = dev->caps.pkey_table_len[port];
835 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
225c7b1f 836
5ae2a7a8
RD		 837 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
838 MLX4_CMD_TIME_CLASS_A);
225c7b1f 839
5ae2a7a8
RD		 840 mlx4_free_cmd_mailbox(dev, mailbox);
841 } else
842 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
843 MLX4_CMD_TIME_CLASS_A);
225c7b1f
RD		 844
845 return err;
846}
847EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
848
849int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
850{
851 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000);
852}
853EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
854
855int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
856{
857 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000);
858}
859
860int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
861{
862 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
863 MLX4_CMD_SET_ICM_SIZE,
864 MLX4_CMD_TIME_CLASS_A);
865 if (ret)
866 return ret;
867
868 /*
869 * Round up number of system pages needed in case
870 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
871 */
872 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
873 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
874
875 return 0;
876}
877
878int mlx4_NOP(struct mlx4_dev *dev)
879{
880 /* Input modifier of 0x1f means "finish as soon as possible." */
881 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100);
882}
kernel source for telekom puls (alcatel/mediatek)