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mlx4_core: Use MOD_STAT_CFG command to get minimal page size
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / mlx4 / fw.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#include <linux/mlx4/cmd.h>
36
37#include "fw.h"
38#include "icm.h"
39
fe40900f 40enum {
5ae2a7a8
RD		 41 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
42 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
43 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
fe40900f
RD		 44};
45
225c7b1f
RD		 46extern void __buggy_use_of_MLX4_GET(void);
47extern void __buggy_use_of_MLX4_PUT(void);
48
49#define MLX4_GET(dest, source, offset) \
50 do { \
51 void *__p = (char *) (source) + (offset); \
52 switch (sizeof (dest)) { \
53 case 1: (dest) = *(u8 *) __p; break; \
54 case 2: (dest) = be16_to_cpup(__p); break; \
55 case 4: (dest) = be32_to_cpup(__p); break; \
56 case 8: (dest) = be64_to_cpup(__p); break; \
57 default: __buggy_use_of_MLX4_GET(); \
58 } \
59 } while (0)
60
61#define MLX4_PUT(dest, source, offset) \
62 do { \
63 void *__d = ((char *) (dest) + (offset)); \
64 switch (sizeof(source)) { \
65 case 1: *(u8 *) __d = (source); break; \
66 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
67 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
68 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
69 default: __buggy_use_of_MLX4_PUT(); \
70 } \
71 } while (0)
72
73static void dump_dev_cap_flags(struct mlx4_dev *dev, u32 flags)
74{
75 static const char *fname[] = {
76 [ 0] = "RC transport",
77 [ 1] = "UC transport",
78 [ 2] = "UD transport",
ea98054f 79 [ 3] = "XRC transport",
225c7b1f
RD		 80 [ 4] = "reliable multicast",
81 [ 5] = "FCoIB support",
82 [ 6] = "SRQ support",
83 [ 7] = "IPoIB checksum offload",
84 [ 8] = "P_Key violation counter",
85 [ 9] = "Q_Key violation counter",
86 [10] = "VMM",
87 [16] = "MW support",
88 [17] = "APM support",
89 [18] = "Atomic ops support",
90 [19] = "Raw multicast support",
91 [20] = "Address vector port checking support",
92 [21] = "UD multicast support",
93 [24] = "Demand paging support",
94 [25] = "Router support"
95 };
96 int i;
97
98 mlx4_dbg(dev, "DEV_CAP flags:\n");
23c15c21 99 for (i = 0; i < ARRAY_SIZE(fname); ++i)
225c7b1f
RD		 100 if (fname[i] && (flags & (1 << i)))
101 mlx4_dbg(dev, " %s\n", fname[i]);
102}
103
2d928651
VS		 104int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
105{
106 struct mlx4_cmd_mailbox *mailbox;
107 u32 *inbox;
108 int err = 0;
109
110#define MOD_STAT_CFG_IN_SIZE 0x100
111
112#define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
113#define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
114
115 mailbox = mlx4_alloc_cmd_mailbox(dev);
116 if (IS_ERR(mailbox))
117 return PTR_ERR(mailbox);
118 inbox = mailbox->buf;
119
120 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
121
122 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
123 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
124
125 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
126 MLX4_CMD_TIME_CLASS_A);
127
128 mlx4_free_cmd_mailbox(dev, mailbox);
129 return err;
130}
131
225c7b1f
RD		 132int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
133{
134 struct mlx4_cmd_mailbox *mailbox;
135 u32 *outbox;
136 u8 field;
137 u16 size;
138 u16 stat_rate;
139 int err;
5ae2a7a8 140 int i;
225c7b1f
RD		 141
142#define QUERY_DEV_CAP_OUT_SIZE 0x100
143#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
144#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
145#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
146#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
147#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
148#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
149#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
150#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
151#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
152#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
153#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
154#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
155#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
156#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
157#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
158#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
159#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
160#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
161#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
162#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
163#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
b832be1e 164#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
225c7b1f
RD		 165#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
166#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
167#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
168#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
169#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
149983af 170#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
225c7b1f
RD		 171#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
172#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
173#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
174#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
175#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
176#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
177#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
178#define QUERY_DEV_CAP_BF_OFFSET 0x4c
179#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
180#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
181#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
182#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
183#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
184#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
185#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
186#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
187#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
188#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
189#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
190#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
191#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
192#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
193#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
194#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
195#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
196#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
197#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
198#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
199#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
200#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
201#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x97
202#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
203#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
204
205 mailbox = mlx4_alloc_cmd_mailbox(dev);
206 if (IS_ERR(mailbox))
207 return PTR_ERR(mailbox);
208 outbox = mailbox->buf;
209
210 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
211 MLX4_CMD_TIME_CLASS_A);
225c7b1f
RD		 212 if (err)
213 goto out;
214
215 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
216 dev_cap->reserved_qps = 1 << (field & 0xf);
217 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
218 dev_cap->max_qps = 1 << (field & 0x1f);
219 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
220 dev_cap->reserved_srqs = 1 << (field >> 4);
221 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
222 dev_cap->max_srqs = 1 << (field & 0x1f);
223 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
224 dev_cap->max_cq_sz = 1 << field;
225 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
226 dev_cap->reserved_cqs = 1 << (field & 0xf);
227 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
228 dev_cap->max_cqs = 1 << (field & 0x1f);
229 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
230 dev_cap->max_mpts = 1 << (field & 0x3f);
231 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
232 dev_cap->reserved_eqs = 1 << (field & 0xf);
233 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
5920869f 234 dev_cap->max_eqs = 1 << (field & 0xf);
225c7b1f
RD		 235 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
236 dev_cap->reserved_mtts = 1 << (field >> 4);
237 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
238 dev_cap->max_mrw_sz = 1 << field;
239 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
240 dev_cap->reserved_mrws = 1 << (field & 0xf);
241 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
242 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
243 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
244 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
245 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
246 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
b832be1e
EC		 247 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
248 field &= 0x1f;
249 if (!field)
250 dev_cap->max_gso_sz = 0;
251 else
252 dev_cap->max_gso_sz = 1 << field;
253
225c7b1f
RD		 254 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
255 dev_cap->max_rdma_global = 1 << (field & 0x3f);
256 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
257 dev_cap->local_ca_ack_delay = field & 0x1f;
225c7b1f 258 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
225c7b1f 259 dev_cap->num_ports = field & 0xf;
149983af
DB		 260 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
261 dev_cap->max_msg_sz = 1 << (field & 0x1f);
225c7b1f
RD		 262 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
263 dev_cap->stat_rate_support = stat_rate;
225c7b1f
RD		 264 MLX4_GET(dev_cap->flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
265 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
266 dev_cap->reserved_uars = field >> 4;
267 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
268 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
269 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
270 dev_cap->min_page_sz = 1 << field;
271
272 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
273 if (field & 0x80) {
274 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
275 dev_cap->bf_reg_size = 1 << (field & 0x1f);
276 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
277 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
278 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
279 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
280 } else {
281 dev_cap->bf_reg_size = 0;
282 mlx4_dbg(dev, "BlueFlame not available\n");
283 }
284
285 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
286 dev_cap->max_sq_sg = field;
287 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
288 dev_cap->max_sq_desc_sz = size;
289
290 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
291 dev_cap->max_qp_per_mcg = 1 << field;
292 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
293 dev_cap->reserved_mgms = field & 0xf;
294 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
295 dev_cap->max_mcgs = 1 << field;
296 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
297 dev_cap->reserved_pds = field >> 4;
298 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
299 dev_cap->max_pds = 1 << (field & 0x3f);
300
301 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
302 dev_cap->rdmarc_entry_sz = size;
303 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
304 dev_cap->qpc_entry_sz = size;
305 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
306 dev_cap->aux_entry_sz = size;
307 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
308 dev_cap->altc_entry_sz = size;
309 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
310 dev_cap->eqc_entry_sz = size;
311 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
312 dev_cap->cqc_entry_sz = size;
313 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
314 dev_cap->srq_entry_sz = size;
315 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
316 dev_cap->cmpt_entry_sz = size;
317 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
318 dev_cap->mtt_entry_sz = size;
319 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
320 dev_cap->dmpt_entry_sz = size;
321
322 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
323 dev_cap->max_srq_sz = 1 << field;
324 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
325 dev_cap->max_qp_sz = 1 << field;
326 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
327 dev_cap->resize_srq = field & 1;
328 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
329 dev_cap->max_rq_sg = field;
330 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
331 dev_cap->max_rq_desc_sz = size;
332
333 MLX4_GET(dev_cap->bmme_flags, outbox,
334 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
335 MLX4_GET(dev_cap->reserved_lkey, outbox,
336 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
337 MLX4_GET(dev_cap->max_icm_sz, outbox,
338 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
339
5ae2a7a8
RD		 340 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
341 for (i = 1; i <= dev_cap->num_ports; ++i) {
342 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
343 dev_cap->max_vl[i] = field >> 4;
344 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
345 dev_cap->max_mtu[i] = field >> 4;
346 dev_cap->max_port_width[i] = field & 0xf;
347 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
348 dev_cap->max_gids[i] = 1 << (field & 0xf);
349 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
350 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
351 }
352 } else {
353#define QUERY_PORT_MTU_OFFSET 0x01
354#define QUERY_PORT_WIDTH_OFFSET 0x06
355#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
356#define QUERY_PORT_MAX_VL_OFFSET 0x0b
357
358 for (i = 1; i <= dev_cap->num_ports; ++i) {
359 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
360 MLX4_CMD_TIME_CLASS_B);
361 if (err)
362 goto out;
363
364 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
365 dev_cap->max_mtu[i] = field & 0xf;
366 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
367 dev_cap->max_port_width[i] = field & 0xf;
368 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
369 dev_cap->max_gids[i] = 1 << (field >> 4);
370 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
371 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
372 dev_cap->max_vl[i] = field & 0xf;
373 }
374 }
375
225c7b1f
RD		 376 if (dev_cap->bmme_flags & 1)
377 mlx4_dbg(dev, "Base MM extensions: yes "
378 "(flags %d, rsvd L_Key %08x)\n",
379 dev_cap->bmme_flags, dev_cap->reserved_lkey);
380 else
381 mlx4_dbg(dev, "Base MM extensions: no\n");
382
383 /*
384 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
385 * we can't use any EQs whose doorbell falls on that page,
386 * even if the EQ itself isn't reserved.
387 */
388 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
389 dev_cap->reserved_eqs);
390
391 mlx4_dbg(dev, "Max ICM size %lld MB\n",
392 (unsigned long long) dev_cap->max_icm_sz >> 20);
393 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
394 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
395 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
396 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
397 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
398 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
399 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
400 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
401 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
402 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
403 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
404 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
405 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
406 dev_cap->max_pds, dev_cap->reserved_mgms);
407 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
408 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
409 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
5ae2a7a8
RD		 410 dev_cap->local_ca_ack_delay, 128 << dev_cap->max_mtu[1],
411 dev_cap->max_port_width[1]);
225c7b1f
RD		 412 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
413 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
414 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
415 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
b832be1e 416 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
225c7b1f
RD		 417
418 dump_dev_cap_flags(dev, dev_cap->flags);
419
420out:
421 mlx4_free_cmd_mailbox(dev, mailbox);
422 return err;
423}
424
425int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
426{
427 struct mlx4_cmd_mailbox *mailbox;
428 struct mlx4_icm_iter iter;
429 __be64 *pages;
430 int lg;
431 int nent = 0;
432 int i;
433 int err = 0;
434 int ts = 0, tc = 0;
435
436 mailbox = mlx4_alloc_cmd_mailbox(dev);
437 if (IS_ERR(mailbox))
438 return PTR_ERR(mailbox);
439 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
440 pages = mailbox->buf;
441
442 for (mlx4_icm_first(icm, &iter);
443 !mlx4_icm_last(&iter);
444 mlx4_icm_next(&iter)) {
445 /*
446 * We have to pass pages that are aligned to their
447 * size, so find the least significant 1 in the
448 * address or size and use that as our log2 size.
449 */
450 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
451 if (lg < MLX4_ICM_PAGE_SHIFT) {
452 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
453 MLX4_ICM_PAGE_SIZE,
454 (unsigned long long) mlx4_icm_addr(&iter),
455 mlx4_icm_size(&iter));
456 err = -EINVAL;
457 goto out;
458 }
459
460 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
461 if (virt != -1) {
462 pages[nent * 2] = cpu_to_be64(virt);
463 virt += 1 << lg;
464 }
465
466 pages[nent * 2 + 1] =
467 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
468 (lg - MLX4_ICM_PAGE_SHIFT));
469 ts += 1 << (lg - 10);
470 ++tc;
471
472 if (++nent == MLX4_MAILBOX_SIZE / 16) {
473 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
474 MLX4_CMD_TIME_CLASS_B);
475 if (err)
476 goto out;
477 nent = 0;
478 }
479 }
480 }
481
482 if (nent)
483 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, MLX4_CMD_TIME_CLASS_B);
484 if (err)
485 goto out;
486
487 switch (op) {
488 case MLX4_CMD_MAP_FA:
489 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
490 break;
491 case MLX4_CMD_MAP_ICM_AUX:
492 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
493 break;
494 case MLX4_CMD_MAP_ICM:
495 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
496 tc, ts, (unsigned long long) virt - (ts << 10));
497 break;
498 }
499
500out:
501 mlx4_free_cmd_mailbox(dev, mailbox);
502 return err;
503}
504
505int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
506{
507 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
508}
509
510int mlx4_UNMAP_FA(struct mlx4_dev *dev)
511{
512 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, MLX4_CMD_TIME_CLASS_B);
513}
514
515
516int mlx4_RUN_FW(struct mlx4_dev *dev)
517{
518 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, MLX4_CMD_TIME_CLASS_A);
519}
520
521int mlx4_QUERY_FW(struct mlx4_dev *dev)
522{
523 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
524 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
525 struct mlx4_cmd_mailbox *mailbox;
526 u32 *outbox;
527 int err = 0;
528 u64 fw_ver;
fe40900f 529 u16 cmd_if_rev;
225c7b1f
RD		 530 u8 lg;
531
532#define QUERY_FW_OUT_SIZE 0x100
533#define QUERY_FW_VER_OFFSET 0x00
fe40900f 534#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
225c7b1f
RD		 535#define QUERY_FW_MAX_CMD_OFFSET 0x0f
536#define QUERY_FW_ERR_START_OFFSET 0x30
537#define QUERY_FW_ERR_SIZE_OFFSET 0x38
538#define QUERY_FW_ERR_BAR_OFFSET 0x3c
539
540#define QUERY_FW_SIZE_OFFSET 0x00
541#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
542#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
543
544 mailbox = mlx4_alloc_cmd_mailbox(dev);
545 if (IS_ERR(mailbox))
546 return PTR_ERR(mailbox);
547 outbox = mailbox->buf;
548
549 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
550 MLX4_CMD_TIME_CLASS_A);
551 if (err)
552 goto out;
553
554 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
555 /*
3e1db334 556 * FW subminor version is at more significant bits than minor
225c7b1f
RD		 557 * version, so swap here.
558 */
559 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
560 ((fw_ver & 0xffff0000ull) >> 16) |
561 ((fw_ver & 0x0000ffffull) << 16);
562
fe40900f 563 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
5ae2a7a8
RD		 564 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
565 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
fe40900f
RD		 566 mlx4_err(dev, "Installed FW has unsupported "
567 "command interface revision %d.\n",
568 cmd_if_rev);
569 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
570 (int) (dev->caps.fw_ver >> 32),
571 (int) (dev->caps.fw_ver >> 16) & 0xffff,
572 (int) dev->caps.fw_ver & 0xffff);
5ae2a7a8
RD		 573 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
574 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
fe40900f
RD		 575 err = -ENODEV;
576 goto out;
577 }
578
5ae2a7a8
RD		 579 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
580 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
581
225c7b1f
RD		 582 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
583 cmd->max_cmds = 1 << lg;
584
fe40900f 585 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
225c7b1f
RD		 586 (int) (dev->caps.fw_ver >> 32),
587 (int) (dev->caps.fw_ver >> 16) & 0xffff,
588 (int) dev->caps.fw_ver & 0xffff,
fe40900f 589 cmd_if_rev, cmd->max_cmds);
225c7b1f
RD		 590
591 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
592 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
593 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
594 fw->catas_bar = (fw->catas_bar >> 6) * 2;
595
596 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
597 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
598
599 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
600 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
601 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
602 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
603
604 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
605
606 /*
607 * Round up number of system pages needed in case
608 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
609 */
610 fw->fw_pages =
611 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
612 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
613
614 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
615 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
616
617out:
618 mlx4_free_cmd_mailbox(dev, mailbox);
619 return err;
620}
621
622static void get_board_id(void *vsd, char *board_id)
623{
624 int i;
625
626#define VSD_OFFSET_SIG1 0x00
627#define VSD_OFFSET_SIG2 0xde
628#define VSD_OFFSET_MLX_BOARD_ID 0xd0
629#define VSD_OFFSET_TS_BOARD_ID 0x20
630
631#define VSD_SIGNATURE_TOPSPIN 0x5ad
632
633 memset(board_id, 0, MLX4_BOARD_ID_LEN);
634
635 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
636 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
637 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
638 } else {
639 /*
640 * The board ID is a string but the firmware byte
641 * swaps each 4-byte word before passing it back to
642 * us. Therefore we need to swab it before printing.
643 */
644 for (i = 0; i < 4; ++i)
645 ((u32 *) board_id)[i] =
646 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
647 }
648}
649
650int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
651{
652 struct mlx4_cmd_mailbox *mailbox;
653 u32 *outbox;
654 int err;
655
656#define QUERY_ADAPTER_OUT_SIZE 0x100
225c7b1f
RD		 657#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
658#define QUERY_ADAPTER_VSD_OFFSET 0x20
659
660 mailbox = mlx4_alloc_cmd_mailbox(dev);
661 if (IS_ERR(mailbox))
662 return PTR_ERR(mailbox);
663 outbox = mailbox->buf;
664
665 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
666 MLX4_CMD_TIME_CLASS_A);
667 if (err)
668 goto out;
669
225c7b1f
RD		 670 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
671
672 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
673 adapter->board_id);
674
675out:
676 mlx4_free_cmd_mailbox(dev, mailbox);
677 return err;
678}
679
680int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
681{
682 struct mlx4_cmd_mailbox *mailbox;
683 __be32 *inbox;
684 int err;
685
686#define INIT_HCA_IN_SIZE 0x200
687#define INIT_HCA_VERSION_OFFSET 0x000
688#define INIT_HCA_VERSION 2
689#define INIT_HCA_FLAGS_OFFSET 0x014
690#define INIT_HCA_QPC_OFFSET 0x020
691#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
692#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
693#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
694#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
695#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
696#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
697#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
698#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
699#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
700#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
701#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
702#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
703#define INIT_HCA_MCAST_OFFSET 0x0c0
704#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
705#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
706#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
707#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
708#define INIT_HCA_TPT_OFFSET 0x0f0
709#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
710#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
711#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
712#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
713#define INIT_HCA_UAR_OFFSET 0x120
714#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
715#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
716
717 mailbox = mlx4_alloc_cmd_mailbox(dev);
718 if (IS_ERR(mailbox))
719 return PTR_ERR(mailbox);
720 inbox = mailbox->buf;
721
722 memset(inbox, 0, INIT_HCA_IN_SIZE);
723
724 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
725
726#if defined(__LITTLE_ENDIAN)
727 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
728#elif defined(__BIG_ENDIAN)
729 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
730#else
731#error Host endianness not defined
732#endif
733 /* Check port for UD address vector: */
734 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
735
8ff095ec
EC		 736 /* Enable IPoIB checksumming if we can: */
737 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
738 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
739
225c7b1f
RD		 740 /* QPC/EEC/CQC/EQC/RDMARC attributes */
741
742 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
743 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
744 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
745 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
746 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
747 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
748 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
749 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
750 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
751 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
752 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
753 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
754
755 /* multicast attributes */
756
757 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
758 MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
759 MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
760 MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
761
762 /* TPT attributes */
763
764 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
765 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
766 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
767 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
768
769 /* UAR attributes */
770
771 MLX4_PUT(inbox, (u8) (PAGE_SHIFT - 12), INIT_HCA_UAR_PAGE_SZ_OFFSET);
772 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
773
77109cc2 774 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000);
225c7b1f
RD		 775
776 if (err)
777 mlx4_err(dev, "INIT_HCA returns %d\n", err);
778
779 mlx4_free_cmd_mailbox(dev, mailbox);
780 return err;
781}
782
5ae2a7a8 783int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
225c7b1f
RD		 784{
785 struct mlx4_cmd_mailbox *mailbox;
786 u32 *inbox;
787 int err;
788 u32 flags;
5ae2a7a8 789 u16 field;
225c7b1f 790
5ae2a7a8 791 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
225c7b1f
RD		 792#define INIT_PORT_IN_SIZE 256
793#define INIT_PORT_FLAGS_OFFSET 0x00
794#define INIT_PORT_FLAG_SIG (1 << 18)
795#define INIT_PORT_FLAG_NG (1 << 17)
796#define INIT_PORT_FLAG_G0 (1 << 16)
797#define INIT_PORT_VL_SHIFT 4
798#define INIT_PORT_PORT_WIDTH_SHIFT 8
799#define INIT_PORT_MTU_OFFSET 0x04
800#define INIT_PORT_MAX_GID_OFFSET 0x06
801#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
802#define INIT_PORT_GUID0_OFFSET 0x10
803#define INIT_PORT_NODE_GUID_OFFSET 0x18
804#define INIT_PORT_SI_GUID_OFFSET 0x20
805
5ae2a7a8
RD		 806 mailbox = mlx4_alloc_cmd_mailbox(dev);
807 if (IS_ERR(mailbox))
808 return PTR_ERR(mailbox);
809 inbox = mailbox->buf;
225c7b1f 810
5ae2a7a8 811 memset(inbox, 0, INIT_PORT_IN_SIZE);
225c7b1f 812
5ae2a7a8
RD		 813 flags = 0;
814 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
815 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
816 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
225c7b1f 817
5ae2a7a8
RD		 818 field = 128 << dev->caps.mtu_cap[port];
819 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
820 field = dev->caps.gid_table_len[port];
821 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
822 field = dev->caps.pkey_table_len[port];
823 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
225c7b1f 824
5ae2a7a8
RD		 825 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
826 MLX4_CMD_TIME_CLASS_A);
225c7b1f 827
5ae2a7a8
RD		 828 mlx4_free_cmd_mailbox(dev, mailbox);
829 } else
830 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
831 MLX4_CMD_TIME_CLASS_A);
225c7b1f
RD		 832
833 return err;
834}
835EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
836
837int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
838{
839 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000);
840}
841EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
842
843int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
844{
845 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000);
846}
847
848int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
849{
850 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
851 MLX4_CMD_SET_ICM_SIZE,
852 MLX4_CMD_TIME_CLASS_A);
853 if (ret)
854 return ret;
855
856 /*
857 * Round up number of system pages needed in case
858 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
859 */
860 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
861 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
862
863 return 0;
864}
865
866int mlx4_NOP(struct mlx4_dev *dev)
867{
868 /* Input modifier of 0x1f means "finish as soon as possible." */
869 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100);
870}
kernel source for telekom puls (alcatel/mediatek)