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ixgbe: add a refcnt when turning on/off FCoE offload capability
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / mlx4 / fw.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#include <linux/mlx4/cmd.h>
c57e20dc 36#include <linux/cache.h>
225c7b1f
RD		 37
38#include "fw.h"
39#include "icm.h"
40
fe40900f 41enum {
5ae2a7a8
RD		 42 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
43 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
44 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
fe40900f
RD		 45};
46
225c7b1f
RD		 47extern void __buggy_use_of_MLX4_GET(void);
48extern void __buggy_use_of_MLX4_PUT(void);
49
51f5f0ee
JM		 50static int enable_qos;
51module_param(enable_qos, bool, 0444);
52MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
53
225c7b1f
RD		 54#define MLX4_GET(dest, source, offset) \
55 do { \
56 void *__p = (char *) (source) + (offset); \
57 switch (sizeof (dest)) { \
58 case 1: (dest) = *(u8 *) __p; break; \
59 case 2: (dest) = be16_to_cpup(__p); break; \
60 case 4: (dest) = be32_to_cpup(__p); break; \
61 case 8: (dest) = be64_to_cpup(__p); break; \
62 default: __buggy_use_of_MLX4_GET(); \
63 } \
64 } while (0)
65
66#define MLX4_PUT(dest, source, offset) \
67 do { \
68 void *__d = ((char *) (dest) + (offset)); \
69 switch (sizeof(source)) { \
70 case 1: *(u8 *) __d = (source); break; \
71 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
72 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
73 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
74 default: __buggy_use_of_MLX4_PUT(); \
75 } \
76 } while (0)
77
78static void dump_dev_cap_flags(struct mlx4_dev *dev, u32 flags)
79{
80 static const char *fname[] = {
81 [ 0] = "RC transport",
82 [ 1] = "UC transport",
83 [ 2] = "UD transport",
ea98054f 84 [ 3] = "XRC transport",
225c7b1f
RD		 85 [ 4] = "reliable multicast",
86 [ 5] = "FCoIB support",
87 [ 6] = "SRQ support",
88 [ 7] = "IPoIB checksum offload",
89 [ 8] = "P_Key violation counter",
90 [ 9] = "Q_Key violation counter",
91 [10] = "VMM",
7ff93f8b 92 [12] = "DPDP",
417608c2 93 [15] = "Big LSO headers",
225c7b1f
RD		 94 [16] = "MW support",
95 [17] = "APM support",
96 [18] = "Atomic ops support",
97 [19] = "Raw multicast support",
98 [20] = "Address vector port checking support",
99 [21] = "UD multicast support",
100 [24] = "Demand paging support",
101 [25] = "Router support"
102 };
103 int i;
104
105 mlx4_dbg(dev, "DEV_CAP flags:\n");
23c15c21 106 for (i = 0; i < ARRAY_SIZE(fname); ++i)
225c7b1f
RD		 107 if (fname[i] && (flags & (1 << i)))
108 mlx4_dbg(dev, " %s\n", fname[i]);
109}
110
2d928651
VS		 111int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
112{
113 struct mlx4_cmd_mailbox *mailbox;
114 u32 *inbox;
115 int err = 0;
116
117#define MOD_STAT_CFG_IN_SIZE 0x100
118
119#define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
120#define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
121
122 mailbox = mlx4_alloc_cmd_mailbox(dev);
123 if (IS_ERR(mailbox))
124 return PTR_ERR(mailbox);
125 inbox = mailbox->buf;
126
127 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
128
129 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
130 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
131
132 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
133 MLX4_CMD_TIME_CLASS_A);
134
135 mlx4_free_cmd_mailbox(dev, mailbox);
136 return err;
137}
138
225c7b1f
RD		 139int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
140{
141 struct mlx4_cmd_mailbox *mailbox;
142 u32 *outbox;
143 u8 field;
7699517d 144 u32 field32;
225c7b1f
RD		 145 u16 size;
146 u16 stat_rate;
147 int err;
5ae2a7a8 148 int i;
225c7b1f
RD		 149
150#define QUERY_DEV_CAP_OUT_SIZE 0x100
151#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
152#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
153#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
154#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
155#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
156#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
157#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
158#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
159#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
160#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
161#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
162#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
163#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
164#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
165#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
166#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
167#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
168#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
169#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
170#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
171#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
b832be1e 172#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
225c7b1f
RD		 173#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
174#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
175#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
176#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
177#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
149983af 178#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
225c7b1f
RD		 179#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
180#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
181#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
0533943c 182#define QUERY_DEV_CAP_UDP_RSS_OFFSET 0x42
e7c1c2c4 183#define QUERY_DEV_CAP_ETH_UC_LOOPBACK_OFFSET 0x43
225c7b1f
RD		 184#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
185#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
186#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
187#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
188#define QUERY_DEV_CAP_BF_OFFSET 0x4c
189#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
190#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
191#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
192#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
193#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
194#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
195#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
196#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
197#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
198#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
199#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
200#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
201#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
202#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
203#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
204#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
205#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
206#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
207#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
208#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
209#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
210#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
95d04f07 211#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
225c7b1f
RD		 212#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
213#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
214
215 mailbox = mlx4_alloc_cmd_mailbox(dev);
216 if (IS_ERR(mailbox))
217 return PTR_ERR(mailbox);
218 outbox = mailbox->buf;
219
220 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
221 MLX4_CMD_TIME_CLASS_A);
225c7b1f
RD		 222 if (err)
223 goto out;
224
225 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
226 dev_cap->reserved_qps = 1 << (field & 0xf);
227 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
228 dev_cap->max_qps = 1 << (field & 0x1f);
229 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
230 dev_cap->reserved_srqs = 1 << (field >> 4);
231 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
232 dev_cap->max_srqs = 1 << (field & 0x1f);
233 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
234 dev_cap->max_cq_sz = 1 << field;
235 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
236 dev_cap->reserved_cqs = 1 << (field & 0xf);
237 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
238 dev_cap->max_cqs = 1 << (field & 0x1f);
239 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
240 dev_cap->max_mpts = 1 << (field & 0x3f);
241 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
be504b0b 242 dev_cap->reserved_eqs = field & 0xf;
225c7b1f 243 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
5920869f 244 dev_cap->max_eqs = 1 << (field & 0xf);
225c7b1f
RD		 245 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
246 dev_cap->reserved_mtts = 1 << (field >> 4);
247 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
248 dev_cap->max_mrw_sz = 1 << field;
249 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
250 dev_cap->reserved_mrws = 1 << (field & 0xf);
251 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
252 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
253 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
254 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
255 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
256 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
b832be1e
EC		 257 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
258 field &= 0x1f;
259 if (!field)
260 dev_cap->max_gso_sz = 0;
261 else
262 dev_cap->max_gso_sz = 1 << field;
263
225c7b1f
RD		 264 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
265 dev_cap->max_rdma_global = 1 << (field & 0x3f);
266 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
267 dev_cap->local_ca_ack_delay = field & 0x1f;
225c7b1f 268 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
225c7b1f 269 dev_cap->num_ports = field & 0xf;
149983af
DB		 270 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
271 dev_cap->max_msg_sz = 1 << (field & 0x1f);
225c7b1f
RD		 272 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
273 dev_cap->stat_rate_support = stat_rate;
0533943c
YP		 274 MLX4_GET(field, outbox, QUERY_DEV_CAP_UDP_RSS_OFFSET);
275 dev_cap->udp_rss = field & 0x1;
e7c1c2c4
YP		 276 MLX4_GET(field, outbox, QUERY_DEV_CAP_ETH_UC_LOOPBACK_OFFSET);
277 dev_cap->loopback_support = field & 0x1;
225c7b1f
RD		 278 MLX4_GET(dev_cap->flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
279 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
280 dev_cap->reserved_uars = field >> 4;
281 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
282 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
283 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
284 dev_cap->min_page_sz = 1 << field;
285
286 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
287 if (field & 0x80) {
288 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
289 dev_cap->bf_reg_size = 1 << (field & 0x1f);
290 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
291 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
292 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
293 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
294 } else {
295 dev_cap->bf_reg_size = 0;
296 mlx4_dbg(dev, "BlueFlame not available\n");
297 }
298
299 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
300 dev_cap->max_sq_sg = field;
301 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
302 dev_cap->max_sq_desc_sz = size;
303
304 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
305 dev_cap->max_qp_per_mcg = 1 << field;
306 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
307 dev_cap->reserved_mgms = field & 0xf;
308 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
309 dev_cap->max_mcgs = 1 << field;
310 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
311 dev_cap->reserved_pds = field >> 4;
312 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
313 dev_cap->max_pds = 1 << (field & 0x3f);
314
315 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
316 dev_cap->rdmarc_entry_sz = size;
317 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
318 dev_cap->qpc_entry_sz = size;
319 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
320 dev_cap->aux_entry_sz = size;
321 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
322 dev_cap->altc_entry_sz = size;
323 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
324 dev_cap->eqc_entry_sz = size;
325 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
326 dev_cap->cqc_entry_sz = size;
327 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
328 dev_cap->srq_entry_sz = size;
329 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
330 dev_cap->cmpt_entry_sz = size;
331 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
332 dev_cap->mtt_entry_sz = size;
333 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
334 dev_cap->dmpt_entry_sz = size;
335
336 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
337 dev_cap->max_srq_sz = 1 << field;
338 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
339 dev_cap->max_qp_sz = 1 << field;
340 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
341 dev_cap->resize_srq = field & 1;
342 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
343 dev_cap->max_rq_sg = field;
344 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
345 dev_cap->max_rq_desc_sz = size;
346
347 MLX4_GET(dev_cap->bmme_flags, outbox,
348 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
349 MLX4_GET(dev_cap->reserved_lkey, outbox,
350 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
351 MLX4_GET(dev_cap->max_icm_sz, outbox,
352 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
353
5ae2a7a8
RD		 354 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
355 for (i = 1; i <= dev_cap->num_ports; ++i) {
356 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
357 dev_cap->max_vl[i] = field >> 4;
358 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
b79acb49 359 dev_cap->ib_mtu[i] = field >> 4;
5ae2a7a8
RD		 360 dev_cap->max_port_width[i] = field & 0xf;
361 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
362 dev_cap->max_gids[i] = 1 << (field & 0xf);
363 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
364 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
365 }
366 } else {
7ff93f8b 367#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
5ae2a7a8 368#define QUERY_PORT_MTU_OFFSET 0x01
b79acb49 369#define QUERY_PORT_ETH_MTU_OFFSET 0x02
5ae2a7a8
RD		 370#define QUERY_PORT_WIDTH_OFFSET 0x06
371#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
93fc9e1b 372#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
5ae2a7a8 373#define QUERY_PORT_MAX_VL_OFFSET 0x0b
e65b9591 374#define QUERY_PORT_MAC_OFFSET 0x10
7699517d
YP		 375#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
376#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
377#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
5ae2a7a8
RD		 378
379 for (i = 1; i <= dev_cap->num_ports; ++i) {
380 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
381 MLX4_CMD_TIME_CLASS_B);
382 if (err)
383 goto out;
384
7ff93f8b
YP		 385 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
386 dev_cap->supported_port_types[i] = field & 3;
5ae2a7a8 387 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
b79acb49 388 dev_cap->ib_mtu[i] = field & 0xf;
5ae2a7a8
RD		 389 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
390 dev_cap->max_port_width[i] = field & 0xf;
391 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
392 dev_cap->max_gids[i] = 1 << (field >> 4);
393 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
394 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
395 dev_cap->max_vl[i] = field & 0xf;
93fc9e1b
YP		 396 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
397 dev_cap->log_max_macs[i] = field & 0xf;
398 dev_cap->log_max_vlans[i] = field >> 4;
b79acb49
YP		 399 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
400 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
7699517d
YP		 401 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
402 dev_cap->trans_type[i] = field32 >> 24;
403 dev_cap->vendor_oui[i] = field32 & 0xffffff;
404 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
405 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
5ae2a7a8
RD		 406 }
407 }
408
95d04f07
RD		 409 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
410 dev_cap->bmme_flags, dev_cap->reserved_lkey);
225c7b1f
RD		 411
412 /*
413 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
414 * we can't use any EQs whose doorbell falls on that page,
415 * even if the EQ itself isn't reserved.
416 */
417 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
418 dev_cap->reserved_eqs);
419
420 mlx4_dbg(dev, "Max ICM size %lld MB\n",
421 (unsigned long long) dev_cap->max_icm_sz >> 20);
422 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
423 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
424 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
425 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
426 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
427 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
428 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
429 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
430 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
431 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
432 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
433 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
434 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
435 dev_cap->max_pds, dev_cap->reserved_mgms);
436 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
437 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
438 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
b79acb49 439 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
5ae2a7a8 440 dev_cap->max_port_width[1]);
225c7b1f
RD		 441 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
442 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
443 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
444 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
b832be1e 445 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
225c7b1f
RD		 446
447 dump_dev_cap_flags(dev, dev_cap->flags);
448
449out:
450 mlx4_free_cmd_mailbox(dev, mailbox);
451 return err;
452}
453
454int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
455{
456 struct mlx4_cmd_mailbox *mailbox;
457 struct mlx4_icm_iter iter;
458 __be64 *pages;
459 int lg;
460 int nent = 0;
461 int i;
462 int err = 0;
463 int ts = 0, tc = 0;
464
465 mailbox = mlx4_alloc_cmd_mailbox(dev);
466 if (IS_ERR(mailbox))
467 return PTR_ERR(mailbox);
468 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
469 pages = mailbox->buf;
470
471 for (mlx4_icm_first(icm, &iter);
472 !mlx4_icm_last(&iter);
473 mlx4_icm_next(&iter)) {
474 /*
475 * We have to pass pages that are aligned to their
476 * size, so find the least significant 1 in the
477 * address or size and use that as our log2 size.
478 */
479 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
480 if (lg < MLX4_ICM_PAGE_SHIFT) {
481 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
482 MLX4_ICM_PAGE_SIZE,
483 (unsigned long long) mlx4_icm_addr(&iter),
484 mlx4_icm_size(&iter));
485 err = -EINVAL;
486 goto out;
487 }
488
489 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
490 if (virt != -1) {
491 pages[nent * 2] = cpu_to_be64(virt);
492 virt += 1 << lg;
493 }
494
495 pages[nent * 2 + 1] =
496 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
497 (lg - MLX4_ICM_PAGE_SHIFT));
498 ts += 1 << (lg - 10);
499 ++tc;
500
501 if (++nent == MLX4_MAILBOX_SIZE / 16) {
502 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
503 MLX4_CMD_TIME_CLASS_B);
504 if (err)
505 goto out;
506 nent = 0;
507 }
508 }
509 }
510
511 if (nent)
512 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, MLX4_CMD_TIME_CLASS_B);
513 if (err)
514 goto out;
515
516 switch (op) {
517 case MLX4_CMD_MAP_FA:
518 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
519 break;
520 case MLX4_CMD_MAP_ICM_AUX:
521 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
522 break;
523 case MLX4_CMD_MAP_ICM:
524 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
525 tc, ts, (unsigned long long) virt - (ts << 10));
526 break;
527 }
528
529out:
530 mlx4_free_cmd_mailbox(dev, mailbox);
531 return err;
532}
533
534int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
535{
536 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
537}
538
539int mlx4_UNMAP_FA(struct mlx4_dev *dev)
540{
541 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, MLX4_CMD_TIME_CLASS_B);
542}
543
544
545int mlx4_RUN_FW(struct mlx4_dev *dev)
546{
547 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, MLX4_CMD_TIME_CLASS_A);
548}
549
550int mlx4_QUERY_FW(struct mlx4_dev *dev)
551{
552 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
553 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
554 struct mlx4_cmd_mailbox *mailbox;
555 u32 *outbox;
556 int err = 0;
557 u64 fw_ver;
fe40900f 558 u16 cmd_if_rev;
225c7b1f
RD		 559 u8 lg;
560
561#define QUERY_FW_OUT_SIZE 0x100
562#define QUERY_FW_VER_OFFSET 0x00
fe40900f 563#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
225c7b1f
RD		 564#define QUERY_FW_MAX_CMD_OFFSET 0x0f
565#define QUERY_FW_ERR_START_OFFSET 0x30
566#define QUERY_FW_ERR_SIZE_OFFSET 0x38
567#define QUERY_FW_ERR_BAR_OFFSET 0x3c
568
569#define QUERY_FW_SIZE_OFFSET 0x00
570#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
571#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
572
573 mailbox = mlx4_alloc_cmd_mailbox(dev);
574 if (IS_ERR(mailbox))
575 return PTR_ERR(mailbox);
576 outbox = mailbox->buf;
577
578 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
579 MLX4_CMD_TIME_CLASS_A);
580 if (err)
581 goto out;
582
583 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
584 /*
3e1db334 585 * FW subminor version is at more significant bits than minor
225c7b1f
RD		 586 * version, so swap here.
587 */
588 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
589 ((fw_ver & 0xffff0000ull) >> 16) |
590 ((fw_ver & 0x0000ffffull) << 16);
591
fe40900f 592 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
5ae2a7a8
RD		 593 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
594 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
fe40900f
RD		 595 mlx4_err(dev, "Installed FW has unsupported "
596 "command interface revision %d.\n",
597 cmd_if_rev);
598 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
599 (int) (dev->caps.fw_ver >> 32),
600 (int) (dev->caps.fw_ver >> 16) & 0xffff,
601 (int) dev->caps.fw_ver & 0xffff);
5ae2a7a8
RD		 602 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
603 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
fe40900f
RD		 604 err = -ENODEV;
605 goto out;
606 }
607
5ae2a7a8
RD		 608 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
609 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
610
225c7b1f
RD		 611 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
612 cmd->max_cmds = 1 << lg;
613
fe40900f 614 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
225c7b1f
RD		 615 (int) (dev->caps.fw_ver >> 32),
616 (int) (dev->caps.fw_ver >> 16) & 0xffff,
617 (int) dev->caps.fw_ver & 0xffff,
fe40900f 618 cmd_if_rev, cmd->max_cmds);
225c7b1f
RD		 619
620 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
621 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
622 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
623 fw->catas_bar = (fw->catas_bar >> 6) * 2;
624
625 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
626 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
627
628 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
629 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
630 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
631 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
632
633 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
634
635 /*
636 * Round up number of system pages needed in case
637 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
638 */
639 fw->fw_pages =
640 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
641 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
642
643 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
644 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
645
646out:
647 mlx4_free_cmd_mailbox(dev, mailbox);
648 return err;
649}
650
651static void get_board_id(void *vsd, char *board_id)
652{
653 int i;
654
655#define VSD_OFFSET_SIG1 0x00
656#define VSD_OFFSET_SIG2 0xde
657#define VSD_OFFSET_MLX_BOARD_ID 0xd0
658#define VSD_OFFSET_TS_BOARD_ID 0x20
659
660#define VSD_SIGNATURE_TOPSPIN 0x5ad
661
662 memset(board_id, 0, MLX4_BOARD_ID_LEN);
663
664 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
665 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
666 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
667 } else {
668 /*
669 * The board ID is a string but the firmware byte
670 * swaps each 4-byte word before passing it back to
671 * us. Therefore we need to swab it before printing.
672 */
673 for (i = 0; i < 4; ++i)
674 ((u32 *) board_id)[i] =
675 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
676 }
677}
678
679int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
680{
681 struct mlx4_cmd_mailbox *mailbox;
682 u32 *outbox;
683 int err;
684
685#define QUERY_ADAPTER_OUT_SIZE 0x100
225c7b1f
RD		 686#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
687#define QUERY_ADAPTER_VSD_OFFSET 0x20
688
689 mailbox = mlx4_alloc_cmd_mailbox(dev);
690 if (IS_ERR(mailbox))
691 return PTR_ERR(mailbox);
692 outbox = mailbox->buf;
693
694 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
695 MLX4_CMD_TIME_CLASS_A);
696 if (err)
697 goto out;
698
225c7b1f
RD		 699 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
700
701 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
702 adapter->board_id);
703
704out:
705 mlx4_free_cmd_mailbox(dev, mailbox);
706 return err;
707}
708
709int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
710{
711 struct mlx4_cmd_mailbox *mailbox;
712 __be32 *inbox;
713 int err;
714
715#define INIT_HCA_IN_SIZE 0x200
716#define INIT_HCA_VERSION_OFFSET 0x000
717#define INIT_HCA_VERSION 2
c57e20dc 718#define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
225c7b1f
RD		 719#define INIT_HCA_FLAGS_OFFSET 0x014
720#define INIT_HCA_QPC_OFFSET 0x020
721#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
722#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
723#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
724#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
725#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
726#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
727#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
728#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
729#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
730#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
731#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
732#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
733#define INIT_HCA_MCAST_OFFSET 0x0c0
734#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
735#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
736#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
737#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
738#define INIT_HCA_TPT_OFFSET 0x0f0
739#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
740#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
741#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
742#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
743#define INIT_HCA_UAR_OFFSET 0x120
744#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
745#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
746
747 mailbox = mlx4_alloc_cmd_mailbox(dev);
748 if (IS_ERR(mailbox))
749 return PTR_ERR(mailbox);
750 inbox = mailbox->buf;
751
752 memset(inbox, 0, INIT_HCA_IN_SIZE);
753
754 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
755
c57e20dc
EC		 756 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
757 (ilog2(cache_line_size()) - 4) << 5;
758
225c7b1f
RD		 759#if defined(__LITTLE_ENDIAN)
760 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
761#elif defined(__BIG_ENDIAN)
762 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
763#else
764#error Host endianness not defined
765#endif
766 /* Check port for UD address vector: */
767 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
768
8ff095ec
EC		 769 /* Enable IPoIB checksumming if we can: */
770 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
771 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
772
51f5f0ee
JM		 773 /* Enable QoS support if module parameter set */
774 if (enable_qos)
775 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
776
225c7b1f
RD		 777 /* QPC/EEC/CQC/EQC/RDMARC attributes */
778
779 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
780 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
781 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
782 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
783 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
784 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
785 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
786 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
787 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
788 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
789 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
790 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
791
792 /* multicast attributes */
793
794 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
795 MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
796 MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
797 MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
798
799 /* TPT attributes */
800
801 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
802 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
803 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
804 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
805
806 /* UAR attributes */
807
808 MLX4_PUT(inbox, (u8) (PAGE_SHIFT - 12), INIT_HCA_UAR_PAGE_SZ_OFFSET);
809 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
810
77109cc2 811 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000);
225c7b1f
RD		 812
813 if (err)
814 mlx4_err(dev, "INIT_HCA returns %d\n", err);
815
816 mlx4_free_cmd_mailbox(dev, mailbox);
817 return err;
818}
819
5ae2a7a8 820int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
225c7b1f
RD		 821{
822 struct mlx4_cmd_mailbox *mailbox;
823 u32 *inbox;
824 int err;
825 u32 flags;
5ae2a7a8 826 u16 field;
225c7b1f 827
5ae2a7a8 828 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
225c7b1f
RD		 829#define INIT_PORT_IN_SIZE 256
830#define INIT_PORT_FLAGS_OFFSET 0x00
831#define INIT_PORT_FLAG_SIG (1 << 18)
832#define INIT_PORT_FLAG_NG (1 << 17)
833#define INIT_PORT_FLAG_G0 (1 << 16)
834#define INIT_PORT_VL_SHIFT 4
835#define INIT_PORT_PORT_WIDTH_SHIFT 8
836#define INIT_PORT_MTU_OFFSET 0x04
837#define INIT_PORT_MAX_GID_OFFSET 0x06
838#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
839#define INIT_PORT_GUID0_OFFSET 0x10
840#define INIT_PORT_NODE_GUID_OFFSET 0x18
841#define INIT_PORT_SI_GUID_OFFSET 0x20
842
5ae2a7a8
RD		 843 mailbox = mlx4_alloc_cmd_mailbox(dev);
844 if (IS_ERR(mailbox))
845 return PTR_ERR(mailbox);
846 inbox = mailbox->buf;
225c7b1f 847
5ae2a7a8 848 memset(inbox, 0, INIT_PORT_IN_SIZE);
225c7b1f 849
5ae2a7a8
RD		 850 flags = 0;
851 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
852 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
853 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
225c7b1f 854
b79acb49 855 field = 128 << dev->caps.ib_mtu_cap[port];
5ae2a7a8
RD		 856 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
857 field = dev->caps.gid_table_len[port];
858 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
859 field = dev->caps.pkey_table_len[port];
860 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
225c7b1f 861
5ae2a7a8
RD		 862 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
863 MLX4_CMD_TIME_CLASS_A);
225c7b1f 864
5ae2a7a8
RD		 865 mlx4_free_cmd_mailbox(dev, mailbox);
866 } else
867 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
868 MLX4_CMD_TIME_CLASS_A);
225c7b1f
RD		 869
870 return err;
871}
872EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
873
874int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
875{
876 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000);
877}
878EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
879
880int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
881{
882 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000);
883}
884
885int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
886{
887 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
888 MLX4_CMD_SET_ICM_SIZE,
889 MLX4_CMD_TIME_CLASS_A);
890 if (ret)
891 return ret;
892
893 /*
894 * Round up number of system pages needed in case
895 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
896 */
897 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
898 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
899
900 return 0;
901}
902
903int mlx4_NOP(struct mlx4_dev *dev)
904{
905 /* Input modifier of 0x1f means "finish as soon as possible." */
906 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100);
907}
kernel source for telekom puls (alcatel/mediatek)