[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / mlx4 / cq.c

/*
 * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <linux/init.h>
#include <linux/hardirq.h>

#include <linux/mlx4/cmd.h>
#include <linux/mlx4/cq.h>

#include "mlx4.h"
#include "icm.h"

struct mlx4_cq_context {
	__be32			flags;
	u16			reserved1[3];
	__be16			page_offset;
	__be32			logsize_usrpage;
	__be16			cq_period;
	__be16			cq_max_count;
	u8			reserved2[3];
	u8			comp_eqn;
	u8			log_page_size;
	u8			reserved3[2];
	u8			mtt_base_addr_h;
	__be32			mtt_base_addr_l;
	__be32			last_notified_index;
	__be32			solicit_producer_index;
	__be32			consumer_index;
	__be32			producer_index;
	u32			reserved4[2];
	__be64			db_rec_addr;
};

#define MLX4_CQ_STATUS_OK		( 0 << 28)
#define MLX4_CQ_STATUS_OVERFLOW		( 9 << 28)
#define MLX4_CQ_STATUS_WRITE_FAIL	(10 << 28)
#define MLX4_CQ_FLAG_CC			( 1 << 18)
#define MLX4_CQ_FLAG_OI			( 1 << 17)
#define MLX4_CQ_STATE_ARMED		( 9 <<  8)
#define MLX4_CQ_STATE_ARMED_SOL		( 6 <<  8)
#define MLX4_EQ_STATE_FIRED		(10 <<  8)

void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn)
{
	struct mlx4_cq *cq;

	cq = radix_tree_lookup(&mlx4_priv(dev)->cq_table.tree,
			       cqn & (dev->caps.num_cqs - 1));
	if (!cq) {
		mlx4_warn(dev, "Completion event for bogus CQ %08x\n", cqn);
		return;
	}

	++cq->arm_sn;

	cq->comp(cq);
}

void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type)
{
	struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table;
	struct mlx4_cq *cq;

	spin_lock(&cq_table->lock);

	cq = radix_tree_lookup(&cq_table->tree, cqn & (dev->caps.num_cqs - 1));
	if (cq)
		atomic_inc(&cq->refcount);

	spin_unlock(&cq_table->lock);

	if (!cq) {
		mlx4_warn(dev, "Async event for bogus CQ %08x\n", cqn);
		return;
	}

	cq->event(cq, event_type);

	if (atomic_dec_and_test(&cq->refcount))
		complete(&cq->free);
}

static int mlx4_SW2HW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
			 int cq_num)
{
	return mlx4_cmd(dev, mailbox->dma, cq_num, 0, MLX4_CMD_SW2HW_CQ,
			MLX4_CMD_TIME_CLASS_A);
}

static int mlx4_MODIFY_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
			 int cq_num, u32 opmod)
{
	return mlx4_cmd(dev, mailbox->dma, cq_num, opmod, MLX4_CMD_MODIFY_CQ,
			MLX4_CMD_TIME_CLASS_A);
}

static int mlx4_HW2SW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
			 int cq_num)
{
	return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, cq_num,
			    mailbox ? 0 : 1, MLX4_CMD_HW2SW_CQ,
			    MLX4_CMD_TIME_CLASS_A);
}

int mlx4_cq_modify(struct mlx4_dev *dev, struct mlx4_cq *cq,
		   u16 count, u16 period)
{
	struct mlx4_cmd_mailbox *mailbox;
	struct mlx4_cq_context *cq_context;
	int err;

	mailbox = mlx4_alloc_cmd_mailbox(dev);
	if (IS_ERR(mailbox))
		return PTR_ERR(mailbox);

	cq_context = mailbox->buf;
	memset(cq_context, 0, sizeof *cq_context);

	cq_context->cq_max_count = cpu_to_be16(count);
	cq_context->cq_period    = cpu_to_be16(period);

	err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 1);

	mlx4_free_cmd_mailbox(dev, mailbox);
	return err;
}
EXPORT_SYMBOL_GPL(mlx4_cq_modify);

int mlx4_cq_resize(struct mlx4_dev *dev, struct mlx4_cq *cq,
		   int entries, struct mlx4_mtt *mtt)
{
	struct mlx4_cmd_mailbox *mailbox;
	struct mlx4_cq_context *cq_context;
	u64 mtt_addr;
	int err;

	mailbox = mlx4_alloc_cmd_mailbox(dev);
	if (IS_ERR(mailbox))
		return PTR_ERR(mailbox);

	cq_context = mailbox->buf;
	memset(cq_context, 0, sizeof *cq_context);

	cq_context->logsize_usrpage = cpu_to_be32(ilog2(entries) << 24);
	cq_context->log_page_size   = mtt->page_shift - 12;
	mtt_addr = mlx4_mtt_addr(dev, mtt);
	cq_context->mtt_base_addr_h = mtt_addr >> 32;
	cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);

	err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 0);

	mlx4_free_cmd_mailbox(dev, mailbox);
	return err;
}
EXPORT_SYMBOL_GPL(mlx4_cq_resize);

int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
		  struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	struct mlx4_cq_table *cq_table = &priv->cq_table;
	struct mlx4_cmd_mailbox *mailbox;
	struct mlx4_cq_context *cq_context;
	u64 mtt_addr;
	int err;

	cq->cqn = mlx4_bitmap_alloc(&cq_table->bitmap);
	if (cq->cqn == -1)
		return -ENOMEM;

	err = mlx4_table_get(dev, &cq_table->table, cq->cqn);
	if (err)
		goto err_out;

	err = mlx4_table_get(dev, &cq_table->cmpt_table, cq->cqn);
	if (err)
		goto err_put;

	spin_lock_irq(&cq_table->lock);
	err = radix_tree_insert(&cq_table->tree, cq->cqn, cq);
	spin_unlock_irq(&cq_table->lock);
	if (err)
		goto err_cmpt_put;

	mailbox = mlx4_alloc_cmd_mailbox(dev);
	if (IS_ERR(mailbox)) {
		err = PTR_ERR(mailbox);
		goto err_radix;
	}

	cq_context = mailbox->buf;
	memset(cq_context, 0, sizeof *cq_context);

	cq_context->logsize_usrpage = cpu_to_be32((ilog2(nent) << 24) | uar->index);
	cq_context->comp_eqn        = priv->eq_table.eq[MLX4_EQ_COMP].eqn;
	cq_context->log_page_size   = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;

	mtt_addr = mlx4_mtt_addr(dev, mtt);
	cq_context->mtt_base_addr_h = mtt_addr >> 32;
	cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
	cq_context->db_rec_addr     = cpu_to_be64(db_rec);

	err = mlx4_SW2HW_CQ(dev, mailbox, cq->cqn);
	mlx4_free_cmd_mailbox(dev, mailbox);
	if (err)
		goto err_radix;

	cq->cons_index = 0;
	cq->arm_sn     = 1;
	cq->uar        = uar;
	atomic_set(&cq->refcount, 1);
	init_completion(&cq->free);

	return 0;

err_radix:
	spin_lock_irq(&cq_table->lock);
	radix_tree_delete(&cq_table->tree, cq->cqn);
	spin_unlock_irq(&cq_table->lock);

err_cmpt_put:
	mlx4_table_put(dev, &cq_table->cmpt_table, cq->cqn);

err_put:
	mlx4_table_put(dev, &cq_table->table, cq->cqn);

err_out:
	mlx4_bitmap_free(&cq_table->bitmap, cq->cqn);

	return err;
}
EXPORT_SYMBOL_GPL(mlx4_cq_alloc);

void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	struct mlx4_cq_table *cq_table = &priv->cq_table;
	int err;

	err = mlx4_HW2SW_CQ(dev, NULL, cq->cqn);
	if (err)
		mlx4_warn(dev, "HW2SW_CQ failed (%d) for CQN %06x\n", err, cq->cqn);

	synchronize_irq(priv->eq_table.eq[MLX4_EQ_COMP].irq);

	spin_lock_irq(&cq_table->lock);
	radix_tree_delete(&cq_table->tree, cq->cqn);
	spin_unlock_irq(&cq_table->lock);

	if (atomic_dec_and_test(&cq->refcount))
		complete(&cq->free);
	wait_for_completion(&cq->free);

	mlx4_table_put(dev, &cq_table->table, cq->cqn);
	mlx4_bitmap_free(&cq_table->bitmap, cq->cqn);
}
EXPORT_SYMBOL_GPL(mlx4_cq_free);

int mlx4_init_cq_table(struct mlx4_dev *dev)
{
	struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table;
	int err;

	spin_lock_init(&cq_table->lock);
	INIT_RADIX_TREE(&cq_table->tree, GFP_ATOMIC);

	err = mlx4_bitmap_init(&cq_table->bitmap, dev->caps.num_cqs,
			       dev->caps.num_cqs - 1, dev->caps.reserved_cqs);
	if (err)
		return err;

	return 0;
}

void mlx4_cleanup_cq_table(struct mlx4_dev *dev)
{
	/* Nothing to do to clean up radix_tree */
	mlx4_bitmap_cleanup(&mlx4_priv(dev)->cq_table.bitmap);
}
Commit	Line	Data
225c7b1f RD	1	/*
	2	* Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
	3	* Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
	4	* Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
	5	* Copyright (c) 2005 Mellanox Technologies. All rights reserved.
	6	* Copyright (c) 2004 Voltaire, Inc. All rights reserved.
	7	*
	8	* This software is available to you under a choice of one of two
	9	* licenses. You may choose to be licensed under the terms of the GNU
	10	* General Public License (GPL) Version 2, available from the file
	11	* COPYING in the main directory of this source tree, or the
	12	* OpenIB.org BSD license below:
	13	*
	14	* Redistribution and use in source and binary forms, with or
	15	* without modification, are permitted provided that the following
	16	* conditions are met:
	17	*
	18	* - Redistributions of source code must retain the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer.
	21	*
	22	* - Redistributions in binary form must reproduce the above
	23	* copyright notice, this list of conditions and the following
	24	* disclaimer in the documentation and/or other materials
	25	* provided with the distribution.
	26	*
	27	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	28	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	29	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	30	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	31	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	32	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	33	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	34	* SOFTWARE.
	35	*/
	36
	37	#include <linux/init.h>
	38	#include <linux/hardirq.h>
	39
	40	#include <linux/mlx4/cmd.h>
3fdcb97f	41	#include <linux/mlx4/cq.h>
225c7b1f RD	42
	43	#include "mlx4.h"
	44	#include "icm.h"
	45
	46	struct mlx4_cq_context {
	47	__be32 flags;
	48	u16 reserved1[3];
	49	__be16 page_offset;
	50	__be32 logsize_usrpage;
3fdcb97f EC	51	__be16 cq_period;
	52	__be16 cq_max_count;
	53	u8 reserved2[3];
225c7b1f RD	54	u8 comp_eqn;
225c7b1f RD	55	u8 log_page_size;
3fdcb97f	56	u8 reserved3[2];
225c7b1f RD	57	u8 mtt_base_addr_h;
	58	__be32 mtt_base_addr_l;
	59	__be32 last_notified_index;
	60	__be32 solicit_producer_index;
	61	__be32 consumer_index;
	62	__be32 producer_index;
3fdcb97f	63	u32 reserved4[2];
225c7b1f RD	64	__be64 db_rec_addr;
	65	};
	66
	67	#define MLX4_CQ_STATUS_OK ( 0 << 28)
	68	#define MLX4_CQ_STATUS_OVERFLOW ( 9 << 28)
	69	#define MLX4_CQ_STATUS_WRITE_FAIL (10 << 28)
	70	#define MLX4_CQ_FLAG_CC ( 1 << 18)
	71	#define MLX4_CQ_FLAG_OI ( 1 << 17)
	72	#define MLX4_CQ_STATE_ARMED ( 9 << 8)
	73	#define MLX4_CQ_STATE_ARMED_SOL ( 6 << 8)
	74	#define MLX4_EQ_STATE_FIRED (10 << 8)
	75
	76	void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn)
	77	{
	78	struct mlx4_cq *cq;
	79
	80	cq = radix_tree_lookup(&mlx4_priv(dev)->cq_table.tree,
	81	cqn & (dev->caps.num_cqs - 1));
	82	if (!cq) {
	83	mlx4_warn(dev, "Completion event for bogus CQ %08x\n", cqn);
	84	return;
	85	}
	86
	87	++cq->arm_sn;
	88
	89	cq->comp(cq);
	90	}
	91
	92	void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type)
	93	{
	94	struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table;
	95	struct mlx4_cq *cq;
	96
	97	spin_lock(&cq_table->lock);
	98
	99	cq = radix_tree_lookup(&cq_table->tree, cqn & (dev->caps.num_cqs - 1));
	100	if (cq)
	101	atomic_inc(&cq->refcount);
	102
	103	spin_unlock(&cq_table->lock);
	104
	105	if (!cq) {
	106	mlx4_warn(dev, "Async event for bogus CQ %08x\n", cqn);
	107	return;
	108	}
	109
	110	cq->event(cq, event_type);
	111
	112	if (atomic_dec_and_test(&cq->refcount))
	113	complete(&cq->free);
	114	}
	115
	116	static int mlx4_SW2HW_CQ(struct mlx4_dev dev, struct mlx4_cmd_mailbox mailbox,
	117	int cq_num)
	118	{
	119	return mlx4_cmd(dev, mailbox->dma, cq_num, 0, MLX4_CMD_SW2HW_CQ,
	120	MLX4_CMD_TIME_CLASS_A);
	121	}
	122
3fdcb97f EC	123	static int mlx4_MODIFY_CQ(struct mlx4_dev dev, struct mlx4_cmd_mailbox mailbox,
	124	int cq_num, u32 opmod)
	125	{
	126	return mlx4_cmd(dev, mailbox->dma, cq_num, opmod, MLX4_CMD_MODIFY_CQ,
	127	MLX4_CMD_TIME_CLASS_A);
	128	}
	129
225c7b1f RD	130	static int mlx4_HW2SW_CQ(struct mlx4_dev dev, struct mlx4_cmd_mailbox mailbox,
	131	int cq_num)
	132	{
	133	return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, cq_num,
	134	mailbox ? 0 : 1, MLX4_CMD_HW2SW_CQ,
	135	MLX4_CMD_TIME_CLASS_A);
	136	}
	137
3fdcb97f EC	138	int mlx4_cq_modify(struct mlx4_dev dev, struct mlx4_cq cq,
	139	u16 count, u16 period)
	140	{
	141	struct mlx4_cmd_mailbox *mailbox;
	142	struct mlx4_cq_context *cq_context;
	143	int err;
	144
	145	mailbox = mlx4_alloc_cmd_mailbox(dev);
	146	if (IS_ERR(mailbox))
	147	return PTR_ERR(mailbox);
	148
	149	cq_context = mailbox->buf;
	150	memset(cq_context, 0, sizeof *cq_context);
	151
	152	cq_context->cq_max_count = cpu_to_be16(count);
	153	cq_context->cq_period = cpu_to_be16(period);
	154
	155	err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 1);
	156
	157	mlx4_free_cmd_mailbox(dev, mailbox);
	158	return err;
	159	}
	160	EXPORT_SYMBOL_GPL(mlx4_cq_modify);
	161
bbf8eed1 VS	162	int mlx4_cq_resize(struct mlx4_dev dev, struct mlx4_cq cq,
	163	int entries, struct mlx4_mtt *mtt)
	164	{
	165	struct mlx4_cmd_mailbox *mailbox;
	166	struct mlx4_cq_context *cq_context;
	167	u64 mtt_addr;
	168	int err;
	169
	170	mailbox = mlx4_alloc_cmd_mailbox(dev);
	171	if (IS_ERR(mailbox))
	172	return PTR_ERR(mailbox);
	173
	174	cq_context = mailbox->buf;
	175	memset(cq_context, 0, sizeof *cq_context);
	176
	177	cq_context->logsize_usrpage = cpu_to_be32(ilog2(entries) << 24);
	178	cq_context->log_page_size = mtt->page_shift - 12;
	179	mtt_addr = mlx4_mtt_addr(dev, mtt);
	180	cq_context->mtt_base_addr_h = mtt_addr >> 32;
	181	cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
	182
f5b3a096	183	err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 0);
bbf8eed1 VS	184
	185	mlx4_free_cmd_mailbox(dev, mailbox);
	186	return err;
	187	}
	188	EXPORT_SYMBOL_GPL(mlx4_cq_resize);
	189
225c7b1f RD	190	int mlx4_cq_alloc(struct mlx4_dev dev, int nent, struct mlx4_mtt mtt,
	191	struct mlx4_uar uar, u64 db_rec, struct mlx4_cq cq)
	192	{
	193	struct mlx4_priv *priv = mlx4_priv(dev);
	194	struct mlx4_cq_table *cq_table = &priv->cq_table;
	195	struct mlx4_cmd_mailbox *mailbox;
	196	struct mlx4_cq_context *cq_context;
	197	u64 mtt_addr;
	198	int err;
	199
	200	cq->cqn = mlx4_bitmap_alloc(&cq_table->bitmap);
	201	if (cq->cqn == -1)
	202	return -ENOMEM;
	203
	204	err = mlx4_table_get(dev, &cq_table->table, cq->cqn);
	205	if (err)
	206	goto err_out;
	207
	208	err = mlx4_table_get(dev, &cq_table->cmpt_table, cq->cqn);
	209	if (err)
	210	goto err_put;
	211
	212	spin_lock_irq(&cq_table->lock);
	213	err = radix_tree_insert(&cq_table->tree, cq->cqn, cq);
	214	spin_unlock_irq(&cq_table->lock);
	215	if (err)
	216	goto err_cmpt_put;
	217
	218	mailbox = mlx4_alloc_cmd_mailbox(dev);
	219	if (IS_ERR(mailbox)) {
	220	err = PTR_ERR(mailbox);
	221	goto err_radix;
	222	}
	223
	224	cq_context = mailbox->buf;
	225	memset(cq_context, 0, sizeof *cq_context);
	226
	227	cq_context->logsize_usrpage = cpu_to_be32((ilog2(nent) << 24) \| uar->index);
	228	cq_context->comp_eqn = priv->eq_table.eq[MLX4_EQ_COMP].eqn;
	229	cq_context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;
	230
	231	mtt_addr = mlx4_mtt_addr(dev, mtt);
	232	cq_context->mtt_base_addr_h = mtt_addr >> 32;
	233	cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
	234	cq_context->db_rec_addr = cpu_to_be64(db_rec);
	235
	236	err = mlx4_SW2HW_CQ(dev, mailbox, cq->cqn);
	237	mlx4_free_cmd_mailbox(dev, mailbox);
	238	if (err)
	239	goto err_radix;
	240
	241	cq->cons_index = 0;
	242	cq->arm_sn = 1;
	243	cq->uar = uar;
	244	atomic_set(&cq->refcount, 1);
	245	init_completion(&cq->free);
	246
	247	return 0;
	248
	249	err_radix:
	250	spin_lock_irq(&cq_table->lock);
	251	radix_tree_delete(&cq_table->tree, cq->cqn);
	252	spin_unlock_irq(&cq_table->lock);
	253
254	err_cmpt_put:
255	mlx4_table_put(dev, &cq_table->cmpt_table, cq->cqn);
256
257	err_put:
258	mlx4_table_put(dev, &cq_table->table, cq->cqn);
259
260	err_out:
261	mlx4_bitmap_free(&cq_table->bitmap, cq->cqn);
262
263	return err;
264	}
265	EXPORT_SYMBOL_GPL(mlx4_cq_alloc);
266
267	void mlx4_cq_free(struct mlx4_dev dev, struct mlx4_cq cq)
268	{
269	struct mlx4_priv *priv = mlx4_priv(dev);
270	struct mlx4_cq_table *cq_table = &priv->cq_table;
271	int err;
272
273	err = mlx4_HW2SW_CQ(dev, NULL, cq->cqn);
274	if (err)
275	mlx4_warn(dev, "HW2SW_CQ failed (%d) for CQN %06x\n", err, cq->cqn);
276
277	synchronize_irq(priv->eq_table.eq[MLX4_EQ_COMP].irq);
278
279	spin_lock_irq(&cq_table->lock);
280	radix_tree_delete(&cq_table->tree, cq->cqn);
281	spin_unlock_irq(&cq_table->lock);
282
283	if (atomic_dec_and_test(&cq->refcount))
284	complete(&cq->free);
285	wait_for_completion(&cq->free);
286
287	mlx4_table_put(dev, &cq_table->table, cq->cqn);
288	mlx4_bitmap_free(&cq_table->bitmap, cq->cqn);
289	}
290	EXPORT_SYMBOL_GPL(mlx4_cq_free);
291
3d73c288	292	int mlx4_init_cq_table(struct mlx4_dev *dev)
225c7b1f RD	293	{
	294	struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table;
	295	int err;
	296
	297	spin_lock_init(&cq_table->lock);
	298	INIT_RADIX_TREE(&cq_table->tree, GFP_ATOMIC);
	299
	300	err = mlx4_bitmap_init(&cq_table->bitmap, dev->caps.num_cqs,
	301	dev->caps.num_cqs - 1, dev->caps.reserved_cqs);
	302	if (err)
	303	return err;
	304
	305	return 0;
	306	}
	307
	308	void mlx4_cleanup_cq_table(struct mlx4_dev *dev)
	309	{
	310	/* Nothing to do to clean up radix_tree */
	311	mlx4_bitmap_cleanup(&mlx4_priv(dev)->cq_table.bitmap);
	312	}