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macb: Use generic PHY layer
[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / drivers / net / macb.c
CommitLineData
89e5785f
HS		 1/*
2 * Atmel MACB Ethernet Controller driver
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/clk.h>
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/slab.h>
17#include <linux/init.h>
18#include <linux/netdevice.h>
19#include <linux/etherdevice.h>
89e5785f 20#include <linux/dma-mapping.h>
89e5785f 21#include <linux/platform_device.h>
6c36a707 22#include <linux/phy.h>
89e5785f
HS		 23
24#include <asm/arch/board.h>
6c36a707 25#include <asm/arch/cpu.h>
89e5785f
HS		 26
27#include "macb.h"
28
89e5785f
HS		 29#define RX_BUFFER_SIZE 128
30#define RX_RING_SIZE 512
31#define RX_RING_BYTES (sizeof(struct dma_desc) * RX_RING_SIZE)
32
33/* Make the IP header word-aligned (the ethernet header is 14 bytes) */
34#define RX_OFFSET 2
35
36#define TX_RING_SIZE 128
37#define DEF_TX_RING_PENDING (TX_RING_SIZE - 1)
38#define TX_RING_BYTES (sizeof(struct dma_desc) * TX_RING_SIZE)
39
40#define TX_RING_GAP(bp) \
41 (TX_RING_SIZE - (bp)->tx_pending)
42#define TX_BUFFS_AVAIL(bp) \
43 (((bp)->tx_tail <= (bp)->tx_head) ? \
44 (bp)->tx_tail + (bp)->tx_pending - (bp)->tx_head : \
45 (bp)->tx_tail - (bp)->tx_head - TX_RING_GAP(bp))
46#define NEXT_TX(n) (((n) + 1) & (TX_RING_SIZE - 1))
47
48#define NEXT_RX(n) (((n) + 1) & (RX_RING_SIZE - 1))
49
50/* minimum number of free TX descriptors before waking up TX process */
51#define MACB_TX_WAKEUP_THRESH (TX_RING_SIZE / 4)
52
53#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
54 | MACB_BIT(ISR_ROVR))
55
56static void __macb_set_hwaddr(struct macb *bp)
57{
58 u32 bottom;
59 u16 top;
60
61 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
62 macb_writel(bp, SA1B, bottom);
63 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
64 macb_writel(bp, SA1T, top);
65}
66
67static void __init macb_get_hwaddr(struct macb *bp)
68{
69 u32 bottom;
70 u16 top;
71 u8 addr[6];
72
73 bottom = macb_readl(bp, SA1B);
74 top = macb_readl(bp, SA1T);
75
76 addr[0] = bottom & 0xff;
77 addr[1] = (bottom >> 8) & 0xff;
78 addr[2] = (bottom >> 16) & 0xff;
79 addr[3] = (bottom >> 24) & 0xff;
80 addr[4] = top & 0xff;
81 addr[5] = (top >> 8) & 0xff;
82
83 if (is_valid_ether_addr(addr))
84 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
85}
86
6c36a707 87static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
89e5785f 88{
6c36a707 89 struct macb *bp = bus->priv;
89e5785f
HS		 90 int value;
91
89e5785f
HS		 92 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
93 | MACB_BF(RW, MACB_MAN_READ)
6c36a707
R		 94 | MACB_BF(PHYA, mii_id)
95 | MACB_BF(REGA, regnum)
89e5785f
HS		 96 | MACB_BF(CODE, MACB_MAN_CODE)));
97
6c36a707
R		 98 /* wait for end of transfer */
99 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
100 cpu_relax();
89e5785f
HS		 101
102 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
89e5785f
HS		 103
104 return value;
105}
106
6c36a707
R		 107static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
108 u16 value)
89e5785f 109{
6c36a707 110 struct macb *bp = bus->priv;
89e5785f
HS		 111
112 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
113 | MACB_BF(RW, MACB_MAN_WRITE)
6c36a707
R		 114 | MACB_BF(PHYA, mii_id)
115 | MACB_BF(REGA, regnum)
89e5785f 116 | MACB_BF(CODE, MACB_MAN_CODE)
6c36a707 117 | MACB_BF(DATA, value)));
89e5785f 118
6c36a707
R		 119 /* wait for end of transfer */
120 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
121 cpu_relax();
122
123 return 0;
124}
89e5785f 125
6c36a707
R		 126static int macb_mdio_reset(struct mii_bus *bus)
127{
128 return 0;
89e5785f
HS		 129}
130
6c36a707 131static void macb_handle_link_change(struct net_device *dev)
89e5785f 132{
6c36a707
R		 133 struct macb *bp = netdev_priv(dev);
134 struct phy_device *phydev = bp->phy_dev;
135 unsigned long flags;
89e5785f 136
6c36a707 137 int status_change = 0;
89e5785f 138
6c36a707
R		 139 spin_lock_irqsave(&bp->lock, flags);
140
141 if (phydev->link) {
142 if ((bp->speed != phydev->speed) ||
143 (bp->duplex != phydev->duplex)) {
144 u32 reg;
145
146 reg = macb_readl(bp, NCFGR);
147 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
148
149 if (phydev->duplex)
150 reg |= MACB_BIT(FD);
151 if (phydev->speed)
152 reg |= MACB_BIT(SPD);
153
154 macb_writel(bp, NCFGR, reg);
155
156 bp->speed = phydev->speed;
157 bp->duplex = phydev->duplex;
158 status_change = 1;
159 }
89e5785f
HS		 160 }
161
6c36a707
R		 162 if (phydev->link != bp->link) {
163 if (phydev->link)
164 netif_schedule(dev);
165 else {
166 bp->speed = 0;
167 bp->duplex = -1;
168 }
169 bp->link = phydev->link;
89e5785f 170
6c36a707
R		 171 status_change = 1;
172 }
89e5785f 173
6c36a707
R		 174 spin_unlock_irqrestore(&bp->lock, flags);
175
176 if (status_change) {
177 if (phydev->link)
178 printk(KERN_INFO "%s: link up (%d/%s)\n",
179 dev->name, phydev->speed,
180 DUPLEX_FULL == phydev->duplex ? "Full":"Half");
181 else
182 printk(KERN_INFO "%s: link down\n", dev->name);
183 }
89e5785f
HS		 184}
185
6c36a707
R		 186/* based on au1000_eth. c*/
187static int macb_mii_probe(struct net_device *dev)
89e5785f 188{
6c36a707
R		 189 struct macb *bp = netdev_priv(dev);
190 struct phy_device *phydev = NULL;
191 struct eth_platform_data *pdata;
192 int phy_addr;
89e5785f 193
6c36a707
R		 194 /* find the first phy */
195 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
196 if (bp->mii_bus.phy_map[phy_addr]) {
197 phydev = bp->mii_bus.phy_map[phy_addr];
198 break;
199 }
200 }
201
202 if (!phydev) {
203 printk (KERN_ERR "%s: no PHY found\n", dev->name);
204 return -1;
205 }
206
207 pdata = bp->pdev->dev.platform_data;
208 /* TODO : add pin_irq */
209
210 /* attach the mac to the phy */
211 if (pdata && pdata->is_rmii) {
212 phydev = phy_connect(dev, phydev->dev.bus_id,
213 &macb_handle_link_change, 0, PHY_INTERFACE_MODE_RMII);
214 } else {
215 phydev = phy_connect(dev, phydev->dev.bus_id,
216 &macb_handle_link_change, 0, PHY_INTERFACE_MODE_MII);
217 }
218
219 if (IS_ERR(phydev)) {
220 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
221 return PTR_ERR(phydev);
222 }
223
224 /* mask with MAC supported features */
225 phydev->supported &= PHY_BASIC_FEATURES;
226
227 phydev->advertising = phydev->supported;
228
229 bp->link = 0;
230 bp->speed = 0;
231 bp->duplex = -1;
232 bp->phy_dev = phydev;
233
234 return 0;
89e5785f
HS		 235}
236
6c36a707 237static int macb_mii_init(struct macb *bp)
89e5785f 238{
6c36a707
R		 239 struct eth_platform_data *pdata;
240 int err = -ENXIO, i;
89e5785f 241
6c36a707
R		 242 /* Enable managment port */
243 macb_writel(bp, NCR, MACB_BIT(MPE));
89e5785f 244
6c36a707
R		 245 bp->mii_bus.name = "MACB_mii_bus",
246 bp->mii_bus.read = &macb_mdio_read,
247 bp->mii_bus.write = &macb_mdio_write,
248 bp->mii_bus.reset = &macb_mdio_reset,
249 bp->mii_bus.id = bp->pdev->id,
250 bp->mii_bus.priv = bp,
251 bp->mii_bus.dev = &bp->dev->dev;
252 pdata = bp->pdev->dev.platform_data;
89e5785f 253
6c36a707
R		 254 if (pdata)
255 bp->mii_bus.phy_mask = pdata->phy_mask;
89e5785f 256
6c36a707
R		 257 bp->mii_bus.irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
258 if (!bp->mii_bus.irq) {
259 err = -ENOMEM;
260 goto err_out;
89e5785f
HS		 261 }
262
6c36a707
R		 263 for (i = 0; i < PHY_MAX_ADDR; i++)
264 bp->mii_bus.irq[i] = PHY_POLL;
89e5785f 265
6c36a707 266 platform_set_drvdata(bp->dev, &bp->mii_bus);
89e5785f 267
6c36a707
R		 268 if (mdiobus_register(&bp->mii_bus))
269 goto err_out_free_mdio_irq;
89e5785f 270
6c36a707
R		 271 if (macb_mii_probe(bp->dev) != 0) {
272 goto err_out_unregister_bus;
273 }
89e5785f 274
6c36a707 275 return 0;
89e5785f 276
6c36a707
R		 277err_out_unregister_bus:
278 mdiobus_unregister(&bp->mii_bus);
279err_out_free_mdio_irq:
280 kfree(bp->mii_bus.irq);
281err_out:
282 return err;
89e5785f
HS		 283}
284
285static void macb_update_stats(struct macb *bp)
286{
287 u32 __iomem *reg = bp->regs + MACB_PFR;
288 u32 *p = &bp->hw_stats.rx_pause_frames;
289 u32 *end = &bp->hw_stats.tx_pause_frames + 1;
290
291 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
292
293 for(; p < end; p++, reg++)
0f0d84e5 294 *p += __raw_readl(reg);
89e5785f
HS		 295}
296
89e5785f
HS		 297static void macb_tx(struct macb *bp)
298{
299 unsigned int tail;
300 unsigned int head;
301 u32 status;
302
303 status = macb_readl(bp, TSR);
304 macb_writel(bp, TSR, status);
305
306 dev_dbg(&bp->pdev->dev, "macb_tx status = %02lx\n",
307 (unsigned long)status);
308
309 if (status & MACB_BIT(UND)) {
310 printk(KERN_ERR "%s: TX underrun, resetting buffers\n",
311 bp->dev->name);
312 bp->tx_head = bp->tx_tail = 0;
313 }
314
315 if (!(status & MACB_BIT(COMP)))
316 /*
317 * This may happen when a buffer becomes complete
318 * between reading the ISR and scanning the
319 * descriptors. Nothing to worry about.
320 */
321 return;
322
323 head = bp->tx_head;
324 for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
325 struct ring_info *rp = &bp->tx_skb[tail];
326 struct sk_buff *skb = rp->skb;
327 u32 bufstat;
328
329 BUG_ON(skb == NULL);
330
331 rmb();
332 bufstat = bp->tx_ring[tail].ctrl;
333
334 if (!(bufstat & MACB_BIT(TX_USED)))
335 break;
336
337 dev_dbg(&bp->pdev->dev, "skb %u (data %p) TX complete\n",
338 tail, skb->data);
339 dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
340 DMA_TO_DEVICE);
341 bp->stats.tx_packets++;
342 bp->stats.tx_bytes += skb->len;
343 rp->skb = NULL;
344 dev_kfree_skb_irq(skb);
345 }
346
347 bp->tx_tail = tail;
348 if (netif_queue_stopped(bp->dev) &&
349 TX_BUFFS_AVAIL(bp) > MACB_TX_WAKEUP_THRESH)
350 netif_wake_queue(bp->dev);
351}
352
353static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
354 unsigned int last_frag)
355{
356 unsigned int len;
357 unsigned int frag;
358 unsigned int offset = 0;
359 struct sk_buff *skb;
360
361 len = MACB_BFEXT(RX_FRMLEN, bp->rx_ring[last_frag].ctrl);
362
363 dev_dbg(&bp->pdev->dev, "macb_rx_frame frags %u - %u (len %u)\n",
364 first_frag, last_frag, len);
365
366 skb = dev_alloc_skb(len + RX_OFFSET);
367 if (!skb) {
368 bp->stats.rx_dropped++;
369 for (frag = first_frag; ; frag = NEXT_RX(frag)) {
370 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
371 if (frag == last_frag)
372 break;
373 }
374 wmb();
375 return 1;
376 }
377
378 skb_reserve(skb, RX_OFFSET);
89e5785f
HS		 379 skb->ip_summed = CHECKSUM_NONE;
380 skb_put(skb, len);
381
382 for (frag = first_frag; ; frag = NEXT_RX(frag)) {
383 unsigned int frag_len = RX_BUFFER_SIZE;
384
385 if (offset + frag_len > len) {
386 BUG_ON(frag != last_frag);
387 frag_len = len - offset;
388 }
27d7ff46
ACM		 389 skb_copy_to_linear_data_offset(skb, offset,
390 (bp->rx_buffers +
391 (RX_BUFFER_SIZE * frag)),
392 frag_len);
89e5785f
HS		 393 offset += RX_BUFFER_SIZE;
394 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
395 wmb();
396
397 if (frag == last_frag)
398 break;
399 }
400
401 skb->protocol = eth_type_trans(skb, bp->dev);
402
403 bp->stats.rx_packets++;
404 bp->stats.rx_bytes += len;
405 bp->dev->last_rx = jiffies;
406 dev_dbg(&bp->pdev->dev, "received skb of length %u, csum: %08x\n",
407 skb->len, skb->csum);
408 netif_receive_skb(skb);
409
410 return 0;
411}
412
413/* Mark DMA descriptors from begin up to and not including end as unused */
414static void discard_partial_frame(struct macb *bp, unsigned int begin,
415 unsigned int end)
416{
417 unsigned int frag;
418
419 for (frag = begin; frag != end; frag = NEXT_RX(frag))
420 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
421 wmb();
422
423 /*
424 * When this happens, the hardware stats registers for
425 * whatever caused this is updated, so we don't have to record
426 * anything.
427 */
428}
429
430static int macb_rx(struct macb *bp, int budget)
431{
432 int received = 0;
433 unsigned int tail = bp->rx_tail;
434 int first_frag = -1;
435
436 for (; budget > 0; tail = NEXT_RX(tail)) {
437 u32 addr, ctrl;
438
439 rmb();
440 addr = bp->rx_ring[tail].addr;
441 ctrl = bp->rx_ring[tail].ctrl;
442
443 if (!(addr & MACB_BIT(RX_USED)))
444 break;
445
446 if (ctrl & MACB_BIT(RX_SOF)) {
447 if (first_frag != -1)
448 discard_partial_frame(bp, first_frag, tail);
449 first_frag = tail;
450 }
451
452 if (ctrl & MACB_BIT(RX_EOF)) {
453 int dropped;
454 BUG_ON(first_frag == -1);
455
456 dropped = macb_rx_frame(bp, first_frag, tail);
457 first_frag = -1;
458 if (!dropped) {
459 received++;
460 budget--;
461 }
462 }
463 }
464
465 if (first_frag != -1)
466 bp->rx_tail = first_frag;
467 else
468 bp->rx_tail = tail;
469
470 return received;
471}
472
473static int macb_poll(struct net_device *dev, int *budget)
474{
475 struct macb *bp = netdev_priv(dev);
476 int orig_budget, work_done, retval = 0;
477 u32 status;
478
479 status = macb_readl(bp, RSR);
480 macb_writel(bp, RSR, status);
481
482 if (!status) {
483 /*
484 * This may happen if an interrupt was pending before
485 * this function was called last time, and no packets
486 * have been received since.
487 */
488 netif_rx_complete(dev);
489 goto out;
490 }
491
492 dev_dbg(&bp->pdev->dev, "poll: status = %08lx, budget = %d\n",
493 (unsigned long)status, *budget);
494
495 if (!(status & MACB_BIT(REC))) {
496 dev_warn(&bp->pdev->dev,
497 "No RX buffers complete, status = %02lx\n",
498 (unsigned long)status);
499 netif_rx_complete(dev);
500 goto out;
501 }
502
503 orig_budget = *budget;
504 if (orig_budget > dev->quota)
505 orig_budget = dev->quota;
506
507 work_done = macb_rx(bp, orig_budget);
508 if (work_done < orig_budget) {
509 netif_rx_complete(dev);
510 retval = 0;
511 } else {
512 retval = 1;
513 }
514
515 /*
516 * We've done what we can to clean the buffers. Make sure we
517 * get notified when new packets arrive.
518 */
519out:
520 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
521
522 /* TODO: Handle errors */
523
524 return retval;
525}
526
527static irqreturn_t macb_interrupt(int irq, void *dev_id)
528{
529 struct net_device *dev = dev_id;
530 struct macb *bp = netdev_priv(dev);
531 u32 status;
532
533 status = macb_readl(bp, ISR);
534
535 if (unlikely(!status))
536 return IRQ_NONE;
537
538 spin_lock(&bp->lock);
539
540 while (status) {
89e5785f
HS		 541 /* close possible race with dev_close */
542 if (unlikely(!netif_running(dev))) {
543 macb_writel(bp, IDR, ~0UL);
544 break;
545 }
546
547 if (status & MACB_RX_INT_FLAGS) {
548 if (netif_rx_schedule_prep(dev)) {
549 /*
550 * There's no point taking any more interrupts
551 * until we have processed the buffers
552 */
553 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
6c36a707
R		 554 dev_dbg(&bp->pdev->dev,
555 "scheduling RX softirq\n");
89e5785f
HS		 556 __netif_rx_schedule(dev);
557 }
558 }
559
560 if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND)))
561 macb_tx(bp);
562
563 /*
564 * Link change detection isn't possible with RMII, so we'll
565 * add that if/when we get our hands on a full-blown MII PHY.
566 */
567
568 if (status & MACB_BIT(HRESP)) {
569 /*
570 * TODO: Reset the hardware, and maybe move the printk
571 * to a lower-priority context as well (work queue?)
572 */
573 printk(KERN_ERR "%s: DMA bus error: HRESP not OK\n",
574 dev->name);
575 }
576
577 status = macb_readl(bp, ISR);
578 }
579
580 spin_unlock(&bp->lock);
581
582 return IRQ_HANDLED;
583}
584
585static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
586{
587 struct macb *bp = netdev_priv(dev);
588 dma_addr_t mapping;
589 unsigned int len, entry;
590 u32 ctrl;
591
592#ifdef DEBUG
593 int i;
594 dev_dbg(&bp->pdev->dev,
595 "start_xmit: len %u head %p data %p tail %p end %p\n",
27a884dc 596 skb->len, skb->head, skb->data,
4305b541 597 skb_tail_pointer(skb), skb_end_pointer(skb));
89e5785f
HS		 598 dev_dbg(&bp->pdev->dev,
599 "data:");
600 for (i = 0; i < 16; i++)
601 printk(" %02x", (unsigned int)skb->data[i]);
602 printk("\n");
603#endif
604
605 len = skb->len;
606 spin_lock_irq(&bp->lock);
607
608 /* This is a hard error, log it. */
609 if (TX_BUFFS_AVAIL(bp) < 1) {
610 netif_stop_queue(dev);
611 spin_unlock_irq(&bp->lock);
612 dev_err(&bp->pdev->dev,
613 "BUG! Tx Ring full when queue awake!\n");
614 dev_dbg(&bp->pdev->dev, "tx_head = %u, tx_tail = %u\n",
615 bp->tx_head, bp->tx_tail);
616 return 1;
617 }
618
619 entry = bp->tx_head;
620 dev_dbg(&bp->pdev->dev, "Allocated ring entry %u\n", entry);
621 mapping = dma_map_single(&bp->pdev->dev, skb->data,
622 len, DMA_TO_DEVICE);
623 bp->tx_skb[entry].skb = skb;
624 bp->tx_skb[entry].mapping = mapping;
625 dev_dbg(&bp->pdev->dev, "Mapped skb data %p to DMA addr %08lx\n",
626 skb->data, (unsigned long)mapping);
627
628 ctrl = MACB_BF(TX_FRMLEN, len);
629 ctrl |= MACB_BIT(TX_LAST);
630 if (entry == (TX_RING_SIZE - 1))
631 ctrl |= MACB_BIT(TX_WRAP);
632
633 bp->tx_ring[entry].addr = mapping;
634 bp->tx_ring[entry].ctrl = ctrl;
635 wmb();
636
637 entry = NEXT_TX(entry);
638 bp->tx_head = entry;
639
640 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
641
642 if (TX_BUFFS_AVAIL(bp) < 1)
643 netif_stop_queue(dev);
644
645 spin_unlock_irq(&bp->lock);
646
647 dev->trans_start = jiffies;
648
649 return 0;
650}
651
652static void macb_free_consistent(struct macb *bp)
653{
654 if (bp->tx_skb) {
655 kfree(bp->tx_skb);
656 bp->tx_skb = NULL;
657 }
658 if (bp->rx_ring) {
659 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
660 bp->rx_ring, bp->rx_ring_dma);
661 bp->rx_ring = NULL;
662 }
663 if (bp->tx_ring) {
664 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
665 bp->tx_ring, bp->tx_ring_dma);
666 bp->tx_ring = NULL;
667 }
668 if (bp->rx_buffers) {
669 dma_free_coherent(&bp->pdev->dev,
670 RX_RING_SIZE * RX_BUFFER_SIZE,
671 bp->rx_buffers, bp->rx_buffers_dma);
672 bp->rx_buffers = NULL;
673 }
674}
675
676static int macb_alloc_consistent(struct macb *bp)
677{
678 int size;
679
680 size = TX_RING_SIZE * sizeof(struct ring_info);
681 bp->tx_skb = kmalloc(size, GFP_KERNEL);
682 if (!bp->tx_skb)
683 goto out_err;
684
685 size = RX_RING_BYTES;
686 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
687 &bp->rx_ring_dma, GFP_KERNEL);
688 if (!bp->rx_ring)
689 goto out_err;
690 dev_dbg(&bp->pdev->dev,
691 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
692 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
693
694 size = TX_RING_BYTES;
695 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
696 &bp->tx_ring_dma, GFP_KERNEL);
697 if (!bp->tx_ring)
698 goto out_err;
699 dev_dbg(&bp->pdev->dev,
700 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
701 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
702
703 size = RX_RING_SIZE * RX_BUFFER_SIZE;
704 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
705 &bp->rx_buffers_dma, GFP_KERNEL);
706 if (!bp->rx_buffers)
707 goto out_err;
708 dev_dbg(&bp->pdev->dev,
709 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
710 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
711
712 return 0;
713
714out_err:
715 macb_free_consistent(bp);
716 return -ENOMEM;
717}
718
719static void macb_init_rings(struct macb *bp)
720{
721 int i;
722 dma_addr_t addr;
723
724 addr = bp->rx_buffers_dma;
725 for (i = 0; i < RX_RING_SIZE; i++) {
726 bp->rx_ring[i].addr = addr;
727 bp->rx_ring[i].ctrl = 0;
728 addr += RX_BUFFER_SIZE;
729 }
730 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
731
732 for (i = 0; i < TX_RING_SIZE; i++) {
733 bp->tx_ring[i].addr = 0;
734 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
735 }
736 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
737
738 bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
739}
740
741static void macb_reset_hw(struct macb *bp)
742{
743 /* Make sure we have the write buffer for ourselves */
744 wmb();
745
746 /*
747 * Disable RX and TX (XXX: Should we halt the transmission
748 * more gracefully?)
749 */
750 macb_writel(bp, NCR, 0);
751
752 /* Clear the stats registers (XXX: Update stats first?) */
753 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
754
755 /* Clear all status flags */
756 macb_writel(bp, TSR, ~0UL);
757 macb_writel(bp, RSR, ~0UL);
758
759 /* Disable all interrupts */
760 macb_writel(bp, IDR, ~0UL);
761 macb_readl(bp, ISR);
762}
763
764static void macb_init_hw(struct macb *bp)
765{
766 u32 config;
767
768 macb_reset_hw(bp);
769 __macb_set_hwaddr(bp);
770
771 config = macb_readl(bp, NCFGR) & MACB_BF(CLK, -1L);
772 config |= MACB_BIT(PAE); /* PAuse Enable */
773 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
774 if (bp->dev->flags & IFF_PROMISC)
775 config |= MACB_BIT(CAF); /* Copy All Frames */
776 if (!(bp->dev->flags & IFF_BROADCAST))
777 config |= MACB_BIT(NBC); /* No BroadCast */
778 macb_writel(bp, NCFGR, config);
779
780 /* Initialize TX and RX buffers */
781 macb_writel(bp, RBQP, bp->rx_ring_dma);
782 macb_writel(bp, TBQP, bp->tx_ring_dma);
783
784 /* Enable TX and RX */
6c36a707 785 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
89e5785f
HS		 786
787 /* Enable interrupts */
788 macb_writel(bp, IER, (MACB_BIT(RCOMP)
789 | MACB_BIT(RXUBR)
790 | MACB_BIT(ISR_TUND)
791 | MACB_BIT(ISR_RLE)
792 | MACB_BIT(TXERR)
793 | MACB_BIT(TCOMP)
794 | MACB_BIT(ISR_ROVR)
795 | MACB_BIT(HRESP)));
89e5785f 796
89e5785f
HS		 797}
798
799static int macb_open(struct net_device *dev)
800{
801 struct macb *bp = netdev_priv(dev);
802 int err;
803
804 dev_dbg(&bp->pdev->dev, "open\n");
805
6c36a707
R		 806 /* if the phy is not yet register, retry later*/
807 if (!bp->phy_dev)
808 return -EAGAIN;
809
89e5785f
HS		 810 if (!is_valid_ether_addr(dev->dev_addr))
811 return -EADDRNOTAVAIL;
812
813 err = macb_alloc_consistent(bp);
814 if (err) {
815 printk(KERN_ERR
816 "%s: Unable to allocate DMA memory (error %d)\n",
817 dev->name, err);
818 return err;
819 }
820
821 macb_init_rings(bp);
822 macb_init_hw(bp);
89e5785f 823
6c36a707
R		 824 /* schedule a link state check */
825 phy_start(bp->phy_dev);
89e5785f 826
6c36a707 827 netif_start_queue(dev);
89e5785f
HS		 828
829 return 0;
830}
831
832static int macb_close(struct net_device *dev)
833{
834 struct macb *bp = netdev_priv(dev);
835 unsigned long flags;
836
89e5785f
HS		 837 netif_stop_queue(dev);
838
6c36a707
R		 839 if (bp->phy_dev)
840 phy_stop(bp->phy_dev);
841
89e5785f
HS		 842 spin_lock_irqsave(&bp->lock, flags);
843 macb_reset_hw(bp);
844 netif_carrier_off(dev);
845 spin_unlock_irqrestore(&bp->lock, flags);
846
847 macb_free_consistent(bp);
848
849 return 0;
850}
851
852static struct net_device_stats *macb_get_stats(struct net_device *dev)
853{
854 struct macb *bp = netdev_priv(dev);
855 struct net_device_stats *nstat = &bp->stats;
856 struct macb_stats *hwstat = &bp->hw_stats;
857
6c36a707
R		 858 /* read stats from hardware */
859 macb_update_stats(bp);
860
89e5785f
HS		 861 /* Convert HW stats into netdevice stats */
862 nstat->rx_errors = (hwstat->rx_fcs_errors +
863 hwstat->rx_align_errors +
864 hwstat->rx_resource_errors +
865 hwstat->rx_overruns +
866 hwstat->rx_oversize_pkts +
867 hwstat->rx_jabbers +
868 hwstat->rx_undersize_pkts +
869 hwstat->sqe_test_errors +
870 hwstat->rx_length_mismatch);
871 nstat->tx_errors = (hwstat->tx_late_cols +
872 hwstat->tx_excessive_cols +
873 hwstat->tx_underruns +
874 hwstat->tx_carrier_errors);
875 nstat->collisions = (hwstat->tx_single_cols +
876 hwstat->tx_multiple_cols +
877 hwstat->tx_excessive_cols);
878 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
879 hwstat->rx_jabbers +
880 hwstat->rx_undersize_pkts +
881 hwstat->rx_length_mismatch);
882 nstat->rx_over_errors = hwstat->rx_resource_errors;
883 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
884 nstat->rx_frame_errors = hwstat->rx_align_errors;
885 nstat->rx_fifo_errors = hwstat->rx_overruns;
886 /* XXX: What does "missed" mean? */
887 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
888 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
889 nstat->tx_fifo_errors = hwstat->tx_underruns;
890 /* Don't know about heartbeat or window errors... */
891
892 return nstat;
893}
894
895static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
896{
897 struct macb *bp = netdev_priv(dev);
6c36a707
R		 898 struct phy_device *phydev = bp->phy_dev;
899
900 if (!phydev)
901 return -ENODEV;
89e5785f 902
6c36a707 903 return phy_ethtool_gset(phydev, cmd);
89e5785f
HS		 904}
905
906static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
907{
908 struct macb *bp = netdev_priv(dev);
6c36a707 909 struct phy_device *phydev = bp->phy_dev;
89e5785f 910
6c36a707
R		 911 if (!phydev)
912 return -ENODEV;
913
914 return phy_ethtool_sset(phydev, cmd);
89e5785f
HS		 915}
916
6c36a707
R		 917static void macb_get_drvinfo(struct net_device *dev,
918 struct ethtool_drvinfo *info)
89e5785f
HS		 919{
920 struct macb *bp = netdev_priv(dev);
921
922 strcpy(info->driver, bp->pdev->dev.driver->name);
923 strcpy(info->version, "$Revision: 1.14 $");
924 strcpy(info->bus_info, bp->pdev->dev.bus_id);
925}
926
89e5785f
HS		 927static struct ethtool_ops macb_ethtool_ops = {
928 .get_settings = macb_get_settings,
929 .set_settings = macb_set_settings,
930 .get_drvinfo = macb_get_drvinfo,
89e5785f
HS		 931 .get_link = ethtool_op_get_link,
932};
933
934static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
935{
936 struct macb *bp = netdev_priv(dev);
6c36a707 937 struct phy_device *phydev = bp->phy_dev;
89e5785f
HS		 938
939 if (!netif_running(dev))
940 return -EINVAL;
941
6c36a707
R		 942 if (!phydev)
943 return -ENODEV;
89e5785f 944
6c36a707 945 return phy_mii_ioctl(phydev, if_mii(rq), cmd);
89e5785f
HS		 946}
947
89e5785f
HS		 948static int __devinit macb_probe(struct platform_device *pdev)
949{
950 struct eth_platform_data *pdata;
951 struct resource *regs;
952 struct net_device *dev;
953 struct macb *bp;
6c36a707 954 struct phy_device *phydev;
89e5785f
HS		 955 unsigned long pclk_hz;
956 u32 config;
957 int err = -ENXIO;
958
959 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
960 if (!regs) {
961 dev_err(&pdev->dev, "no mmio resource defined\n");
962 goto err_out;
963 }
964
965 err = -ENOMEM;
966 dev = alloc_etherdev(sizeof(*bp));
967 if (!dev) {
968 dev_err(&pdev->dev, "etherdev alloc failed, aborting.\n");
969 goto err_out;
970 }
971
972 SET_MODULE_OWNER(dev);
973 SET_NETDEV_DEV(dev, &pdev->dev);
974
975 /* TODO: Actually, we have some interesting features... */
976 dev->features |= 0;
977
978 bp = netdev_priv(dev);
979 bp->pdev = pdev;
980 bp->dev = dev;
981
982 spin_lock_init(&bp->lock);
983
0cc8674f
AV		 984#if defined(CONFIG_ARCH_AT91)
985 bp->pclk = clk_get(&pdev->dev, "macb_clk");
986 if (IS_ERR(bp->pclk)) {
987 dev_err(&pdev->dev, "failed to get macb_clk\n");
988 goto err_out_free_dev;
989 }
990 clk_enable(bp->pclk);
991#else
89e5785f
HS		 992 bp->pclk = clk_get(&pdev->dev, "pclk");
993 if (IS_ERR(bp->pclk)) {
994 dev_err(&pdev->dev, "failed to get pclk\n");
995 goto err_out_free_dev;
996 }
997 bp->hclk = clk_get(&pdev->dev, "hclk");
998 if (IS_ERR(bp->hclk)) {
999 dev_err(&pdev->dev, "failed to get hclk\n");
1000 goto err_out_put_pclk;
1001 }
1002
1003 clk_enable(bp->pclk);
1004 clk_enable(bp->hclk);
0cc8674f 1005#endif
89e5785f
HS		 1006
1007 bp->regs = ioremap(regs->start, regs->end - regs->start + 1);
1008 if (!bp->regs) {
1009 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
1010 err = -ENOMEM;
1011 goto err_out_disable_clocks;
1012 }
1013
1014 dev->irq = platform_get_irq(pdev, 0);
38515e90 1015 err = request_irq(dev->irq, macb_interrupt, IRQF_SAMPLE_RANDOM,
89e5785f
HS		 1016 dev->name, dev);
1017 if (err) {
1018 printk(KERN_ERR
1019 "%s: Unable to request IRQ %d (error %d)\n",
1020 dev->name, dev->irq, err);
1021 goto err_out_iounmap;
1022 }
1023
1024 dev->open = macb_open;
1025 dev->stop = macb_close;
1026 dev->hard_start_xmit = macb_start_xmit;
1027 dev->get_stats = macb_get_stats;
1028 dev->do_ioctl = macb_ioctl;
1029 dev->poll = macb_poll;
1030 dev->weight = 64;
1031 dev->ethtool_ops = &macb_ethtool_ops;
1032
1033 dev->base_addr = regs->start;
1034
89e5785f
HS		 1035 /* Set MII management clock divider */
1036 pclk_hz = clk_get_rate(bp->pclk);
1037 if (pclk_hz <= 20000000)
1038 config = MACB_BF(CLK, MACB_CLK_DIV8);
1039 else if (pclk_hz <= 40000000)
1040 config = MACB_BF(CLK, MACB_CLK_DIV16);
1041 else if (pclk_hz <= 80000000)
1042 config = MACB_BF(CLK, MACB_CLK_DIV32);
1043 else
1044 config = MACB_BF(CLK, MACB_CLK_DIV64);
1045 macb_writel(bp, NCFGR, config);
1046
89e5785f 1047 macb_get_hwaddr(bp);
89e5785f 1048 pdata = pdev->dev.platform_data;
6c36a707 1049
89e5785f 1050 if (pdata && pdata->is_rmii)
0cc8674f
AV		 1051#if defined(CONFIG_ARCH_AT91)
1052 macb_writel(bp, USRIO, (MACB_BIT(RMII) | MACB_BIT(CLKEN)) );
1053#else
89e5785f 1054 macb_writel(bp, USRIO, 0);
0cc8674f 1055#endif
89e5785f 1056 else
0cc8674f
AV		 1057#if defined(CONFIG_ARCH_AT91)
1058 macb_writel(bp, USRIO, MACB_BIT(CLKEN));
1059#else
89e5785f 1060 macb_writel(bp, USRIO, MACB_BIT(MII));
0cc8674f 1061#endif
89e5785f
HS		 1062
1063 bp->tx_pending = DEF_TX_RING_PENDING;
1064
1065 err = register_netdev(dev);
1066 if (err) {
1067 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1068 goto err_out_free_irq;
1069 }
1070
6c36a707
R		 1071 if (macb_mii_init(bp) != 0) {
1072 goto err_out_unregister_netdev;
1073 }
89e5785f 1074
6c36a707 1075 platform_set_drvdata(pdev, dev);
89e5785f
HS		 1076
1077 printk(KERN_INFO "%s: Atmel MACB at 0x%08lx irq %d "
1078 "(%02x:%02x:%02x:%02x:%02x:%02x)\n",
1079 dev->name, dev->base_addr, dev->irq,
1080 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
1081 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
1082
6c36a707
R		 1083 phydev = bp->phy_dev;
1084 printk(KERN_INFO "%s: attached PHY driver [%s] "
1085 "(mii_bus:phy_addr=%s, irq=%d)\n",
1086 dev->name, phydev->drv->name, phydev->dev.bus_id, phydev->irq);
1087
89e5785f
HS		 1088 return 0;
1089
6c36a707
R		 1090err_out_unregister_netdev:
1091 unregister_netdev(dev);
89e5785f
HS		 1092err_out_free_irq:
1093 free_irq(dev->irq, dev);
1094err_out_iounmap:
1095 iounmap(bp->regs);
1096err_out_disable_clocks:
0cc8674f 1097#ifndef CONFIG_ARCH_AT91
89e5785f 1098 clk_disable(bp->hclk);
89e5785f 1099 clk_put(bp->hclk);
0cc8674f
AV		 1100#endif
1101 clk_disable(bp->pclk);
6c36a707 1102#ifndef CONFIG_ARCH_AT91
89e5785f 1103err_out_put_pclk:
6c36a707 1104#endif
89e5785f
HS		 1105 clk_put(bp->pclk);
1106err_out_free_dev:
1107 free_netdev(dev);
1108err_out:
1109 platform_set_drvdata(pdev, NULL);
1110 return err;
1111}
1112
1113static int __devexit macb_remove(struct platform_device *pdev)
1114{
1115 struct net_device *dev;
1116 struct macb *bp;
1117
1118 dev = platform_get_drvdata(pdev);
1119
1120 if (dev) {
1121 bp = netdev_priv(dev);
6c36a707
R		 1122 mdiobus_unregister(&bp->mii_bus);
1123 kfree(bp->mii_bus.irq);
89e5785f
HS		 1124 unregister_netdev(dev);
1125 free_irq(dev->irq, dev);
1126 iounmap(bp->regs);
0cc8674f 1127#ifndef CONFIG_ARCH_AT91
89e5785f 1128 clk_disable(bp->hclk);
89e5785f 1129 clk_put(bp->hclk);
0cc8674f
AV		 1130#endif
1131 clk_disable(bp->pclk);
89e5785f
HS		 1132 clk_put(bp->pclk);
1133 free_netdev(dev);
1134 platform_set_drvdata(pdev, NULL);
1135 }
1136
1137 return 0;
1138}
1139
1140static struct platform_driver macb_driver = {
1141 .probe = macb_probe,
1142 .remove = __devexit_p(macb_remove),
1143 .driver = {
1144 .name = "macb",
1145 },
1146};
1147
1148static int __init macb_init(void)
1149{
1150 return platform_driver_register(&macb_driver);
1151}
1152
1153static void __exit macb_exit(void)
1154{
1155 platform_driver_unregister(&macb_driver);
1156}
1157
1158module_init(macb_init);
1159module_exit(macb_exit);
1160
1161MODULE_LICENSE("GPL");
1162MODULE_DESCRIPTION("Atmel MACB Ethernet driver");
1163MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");