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ixgbe: DCB, misallocated packet buffer size with X540 device
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ixgbe / ixgbe_type.h
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_TYPE_H_
29#define _IXGBE_TYPE_H_
30
31#include <linux/types.h>
6b73e10d 32#include <linux/mdio.h>
32e7bfc4 33#include <linux/netdevice.h>
9a799d71
AK		 34
35/* Vendor ID */
36#define IXGBE_INTEL_VENDOR_ID 0x8086
37
38/* Device IDs */
1e336d0f 39#define IXGBE_DEV_ID_82598 0x10B6
2f21bdd3 40#define IXGBE_DEV_ID_82598_BX 0x1508
9a799d71
AK		 41#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
42#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
c4900be0 43#define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
0befdb3e 44#define IXGBE_DEV_ID_82598AT 0x10C8
3845bec0 45#define IXGBE_DEV_ID_82598AT2 0x150B
9a799d71 46#define IXGBE_DEV_ID_82598EB_CX4 0x10DD
8d792cd9 47#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
c4900be0
DS		 48#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
49#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
b95f5fcb 50#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
11afc1b1 51#define IXGBE_DEV_ID_82599_KX4 0x10F7
dbfec662 52#define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514
74757d49 53#define IXGBE_DEV_ID_82599_KR 0x1517
119fc60a 54#define IXGBE_DEV_ID_82599_T3_LOM 0x151C
8911184f 55#define IXGBE_DEV_ID_82599_CX4 0x10F9
11afc1b1 56#define IXGBE_DEV_ID_82599_SFP 0x10FB
dbffcb21
DS		 57#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152a
58#define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529
0b077fea 59#define IXGBE_SUBDEV_ID_82599_SFP 0x11A9
38ad1c8e 60#define IXGBE_DEV_ID_82599_SFP_EM 0x1507
4c40ef02 61#define IXGBE_DEV_ID_82599_SFP_SF2 0x154D
1fcf03e6 62#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
312eb931 63#define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
50d6c681 64#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C
b93a2226 65#define IXGBE_DEV_ID_X540T 0x1528
9a799d71
AK		 66
67/* General Registers */
68#define IXGBE_CTRL 0x00000
69#define IXGBE_STATUS 0x00008
70#define IXGBE_CTRL_EXT 0x00018
71#define IXGBE_ESDP 0x00020
72#define IXGBE_EODSDP 0x00028
11afc1b1 73#define IXGBE_I2CCTL 0x00028
9a799d71
AK		 74#define IXGBE_LEDCTL 0x00200
75#define IXGBE_FRTIMER 0x00048
76#define IXGBE_TCPTIMER 0x0004C
11afc1b1
PW		 77#define IXGBE_CORESPARE 0x00600
78#define IXGBE_EXVET 0x05078
9a799d71
AK		 79
80/* NVM Registers */
81#define IXGBE_EEC 0x10010
82#define IXGBE_EERD 0x10014
21ce849b 83#define IXGBE_EEWR 0x10018
9a799d71
AK		 84#define IXGBE_FLA 0x1001C
85#define IXGBE_EEMNGCTL 0x10110
86#define IXGBE_EEMNGDATA 0x10114
87#define IXGBE_FLMNGCTL 0x10118
88#define IXGBE_FLMNGDATA 0x1011C
89#define IXGBE_FLMNGCNT 0x10120
90#define IXGBE_FLOP 0x1013C
91#define IXGBE_GRC 0x10200
92
11afc1b1
PW		 93/* General Receive Control */
94#define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */
888be1a1 95#define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
11afc1b1
PW		 96
97#define IXGBE_VPDDIAG0 0x10204
98#define IXGBE_VPDDIAG1 0x10208
99
100/* I2CCTL Bit Masks */
101#define IXGBE_I2C_CLK_IN 0x00000001
102#define IXGBE_I2C_CLK_OUT 0x00000002
103#define IXGBE_I2C_DATA_IN 0x00000004
104#define IXGBE_I2C_DATA_OUT 0x00000008
105
9a799d71
AK		 106/* Interrupt Registers */
107#define IXGBE_EICR 0x00800
108#define IXGBE_EICS 0x00808
109#define IXGBE_EIMS 0x00880
110#define IXGBE_EIMC 0x00888
111#define IXGBE_EIAC 0x00810
112#define IXGBE_EIAM 0x00890
11afc1b1
PW		 113#define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)
114#define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)
115#define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4)
116#define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4)
509ee935
JB		 117/*
118 * 82598 EITR is 16 bits but set the limits based on the max
119 * supported by all ixgbe hardware. 82599 EITR is only 12 bits,
120 * with the lower 3 always zero.
121 */
122#define IXGBE_MAX_INT_RATE 488281
123#define IXGBE_MIN_INT_RATE 956
124#define IXGBE_MAX_EITR 0x00000FF8
125#define IXGBE_MIN_EITR 8
11afc1b1
PW		 126#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
127 (0x012300 + (((_i) - 24) * 4)))
509ee935 128#define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
11afc1b1
PW		 129#define IXGBE_EITR_LLI_MOD 0x00008000
130#define IXGBE_EITR_CNT_WDIS 0x80000000
c44ade9e 131#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
11afc1b1
PW		 132#define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */
133#define IXGBE_EITRSEL 0x00894
9a799d71
AK		 134#define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */
135#define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */
c44ade9e 136#define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
9a799d71
AK		 137#define IXGBE_GPIE 0x00898
138
139/* Flow Control Registers */
11afc1b1
PW		 140#define IXGBE_FCADBUL 0x03210
141#define IXGBE_FCADBUH 0x03214
142#define IXGBE_FCAMACL 0x04328
143#define IXGBE_FCAMACH 0x0432C
144#define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */
145#define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */
9a799d71
AK		 146#define IXGBE_PFCTOP 0x03008
147#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
148#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
149#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
150#define IXGBE_FCRTV 0x032A0
11afc1b1 151#define IXGBE_FCCFG 0x03D00
9a799d71
AK		 152#define IXGBE_TFCS 0x0CE00
153
154/* Receive DMA Registers */
11afc1b1
PW		 155#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
156 (0x0D000 + ((_i - 64) * 0x40)))
157#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
158 (0x0D004 + ((_i - 64) * 0x40)))
159#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
160 (0x0D008 + ((_i - 64) * 0x40)))
161#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
162 (0x0D010 + ((_i - 64) * 0x40)))
163#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
164 (0x0D018 + ((_i - 64) * 0x40)))
165#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
166 (0x0D028 + ((_i - 64) * 0x40)))
167#define IXGBE_RDDCC 0x02F20
168#define IXGBE_RXMEMWRAP 0x03190
169#define IXGBE_STARCTRL 0x03024
c44ade9e
JB		 170/*
171 * Split and Replication Receive Control Registers
172 * 00-15 : 0x02100 + n*4
173 * 16-64 : 0x01014 + n*0x40
174 * 64-127: 0x0D014 + (n-64)*0x40
175 */
176#define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
177 (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
178 (0x0D014 + ((_i - 64) * 0x40))))
179/*
180 * Rx DCA Control Register:
181 * 00-15 : 0x02200 + n*4
182 * 16-64 : 0x0100C + n*0x40
183 * 64-127: 0x0D00C + (n-64)*0x40
184 */
185#define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
186 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
187 (0x0D00C + ((_i - 64) * 0x40))))
188#define IXGBE_RDRXCTL 0x02F00
9a799d71 189#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
c44ade9e 190 /* 8 of these 0x03C00 - 0x03C1C */
9a799d71
AK		 191#define IXGBE_RXCTRL 0x03000
192#define IXGBE_DROPEN 0x03D04
193#define IXGBE_RXPBSIZE_SHIFT 10
194
195/* Receive Registers */
196#define IXGBE_RXCSUM 0x05000
197#define IXGBE_RFCTL 0x05008
c44ade9e
JB		 198#define IXGBE_DRECCCTL 0x02F08
199#define IXGBE_DRECCCTL_DISABLE 0
200/* Multicast Table Array - 128 entries */
9a799d71 201#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
11afc1b1
PW		 202#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
203 (0x0A200 + ((_i) * 8)))
204#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
205 (0x0A204 + ((_i) * 8)))
206#define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8))
207#define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8))
c44ade9e 208/* Packet split receive type */
11afc1b1
PW		 209#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
210 (0x0EA00 + ((_i) * 4)))
c44ade9e 211/* array of 4096 1-bit vlan filters */
9a799d71 212#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
c44ade9e 213/*array of 4096 4-bit vlan vmdq indices */
9a799d71 214#define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
9a799d71
AK		 215#define IXGBE_FCTRL 0x05080
216#define IXGBE_VLNCTRL 0x05088
217#define IXGBE_MCSTCTRL 0x05090
218#define IXGBE_MRQC 0x05818
11afc1b1
PW		 219#define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */
220#define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */
221#define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */
222#define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
223#define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */
224#define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */
225#define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */
226#define IXGBE_RQTC 0x0EC70
227#define IXGBE_MTQC 0x08120
228#define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */
229#define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */
7f01648a 230#define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */
11afc1b1
PW		 231#define IXGBE_VT_CTL 0x051B0
232#define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4))
233#define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4))
a985b6c3 234#define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4))
11afc1b1
PW		 235#define IXGBE_QDE 0x2F04
236#define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */
237#define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4))
238#define IXGBE_VMRCTL(_i) (0x0F600 + ((_i) * 4))
239#define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4))
240#define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4))
241#define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
242#define IXGBE_LLITHRESH 0x0EC90
9a799d71
AK		 243#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */
244#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */
245#define IXGBE_IMIRVP 0x05AC0
c44ade9e 246#define IXGBE_VMD_CTL 0x0581C
9a799d71
AK		 247#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */
248#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */
249
bfde493e
PWJ		 250/* Flow Director registers */
251#define IXGBE_FDIRCTRL 0x0EE00
252#define IXGBE_FDIRHKEY 0x0EE68
253#define IXGBE_FDIRSKEY 0x0EE6C
254#define IXGBE_FDIRDIP4M 0x0EE3C
255#define IXGBE_FDIRSIP4M 0x0EE40
256#define IXGBE_FDIRTCPM 0x0EE44
257#define IXGBE_FDIRUDPM 0x0EE48
258#define IXGBE_FDIRIP6M 0x0EE74
259#define IXGBE_FDIRM 0x0EE70
260
261/* Flow Director Stats registers */
262#define IXGBE_FDIRFREE 0x0EE38
263#define IXGBE_FDIRLEN 0x0EE4C
264#define IXGBE_FDIRUSTAT 0x0EE50
265#define IXGBE_FDIRFSTAT 0x0EE54
266#define IXGBE_FDIRMATCH 0x0EE58
267#define IXGBE_FDIRMISS 0x0EE5C
268
269/* Flow Director Programming registers */
270#define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */
271#define IXGBE_FDIRIPSA 0x0EE18
272#define IXGBE_FDIRIPDA 0x0EE1C
273#define IXGBE_FDIRPORT 0x0EE20
274#define IXGBE_FDIRVLAN 0x0EE24
275#define IXGBE_FDIRHASH 0x0EE28
276#define IXGBE_FDIRCMD 0x0EE2C
277
9a799d71 278/* Transmit DMA registers */
c44ade9e 279#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/
9a799d71
AK		 280#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
281#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
282#define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40))
283#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
284#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
285#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
286#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
287#define IXGBE_DTXCTL 0x07E00
c44ade9e 288
a985b6c3
GR		 289#define IXGBE_DMATXCTL 0x04A80
290#define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */
7f870475 291#define IXGBE_PFDTXGSWC 0x08220
11afc1b1
PW		 292#define IXGBE_DTXMXSZRQ 0x08100
293#define IXGBE_DTXTCPFLGL 0x04A88
294#define IXGBE_DTXTCPFLGH 0x04A8C
295#define IXGBE_LBDRPEN 0x0CA00
296#define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
297
298#define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */
299#define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */
300#define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */
301#define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */
7f870475
GR		 302
303#define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
a985b6c3
GR		 304
305/* Anti-spoofing defines */
306#define IXGBE_SPOOF_MACAS_MASK 0xFF
307#define IXGBE_SPOOF_VLANAS_MASK 0xFF00
308#define IXGBE_SPOOF_VLANAS_SHIFT 8
309#define IXGBE_PFVFSPOOF_REG_COUNT 8
310
c44ade9e 311#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
11afc1b1
PW		 312/* Tx DCA Control register : 128 of these (0-127) */
313#define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40))
9a799d71 314#define IXGBE_TIPG 0x0CB00
c44ade9e 315#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */
9a799d71
AK		 316#define IXGBE_MNGTXMAP 0x0CD10
317#define IXGBE_TIPG_FIBER_DEFAULT 3
318#define IXGBE_TXPBSIZE_SHIFT 10
319
320/* Wake up registers */
321#define IXGBE_WUC 0x05800
322#define IXGBE_WUFC 0x05808
323#define IXGBE_WUS 0x05810
324#define IXGBE_IPAV 0x05838
325#define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */
326#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */
c44ade9e 327
9a799d71
AK		 328#define IXGBE_WUPL 0x05900
329#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
11afc1b1
PW		 330#define IXGBE_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flex host filter table */
331#define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100)) /* Ext Flexible Host
332 * Filter Table */
333
334#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
335#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
336
337/* Each Flexible Filter is at most 128 (0x80) bytes in length */
338#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128
339#define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */
340#define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */
341
342/* Definitions for power management and wakeup registers */
343/* Wake Up Control */
344#define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */
345#define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */
888be1a1 346#define IXGBE_WUC_WKEN 0x00000010 /* Enable PE_WAKE_N pin assertion */
11afc1b1
PW		 347
348/* Wake Up Filter Control */
349#define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
350#define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
351#define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
352#define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
353#define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
354#define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
355#define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
356#define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
357#define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */
358
359#define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
360#define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
361#define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
362#define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
363#define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
364#define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
365#define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
366#define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */
367#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */
368#define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all 6 wakeup filters*/
369#define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
370
371/* Wake Up Status */
372#define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC
373#define IXGBE_WUS_MAG IXGBE_WUFC_MAG
374#define IXGBE_WUS_EX IXGBE_WUFC_EX
375#define IXGBE_WUS_MC IXGBE_WUFC_MC
376#define IXGBE_WUS_BC IXGBE_WUFC_BC
377#define IXGBE_WUS_ARP IXGBE_WUFC_ARP
378#define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4
379#define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6
380#define IXGBE_WUS_MNG IXGBE_WUFC_MNG
381#define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0
382#define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1
383#define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2
384#define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3
385#define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4
386#define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5
387#define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS
388
389/* Wake Up Packet Length */
390#define IXGBE_WUPL_LENGTH_MASK 0xFFFF
391
392/* DCB registers */
9a799d71
AK		 393#define IXGBE_RMCS 0x03D00
394#define IXGBE_DPMCS 0x07F40
395#define IXGBE_PDPMCS 0x0CD00
396#define IXGBE_RUPPBMR 0x050A0
397#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
398#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
399#define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
400#define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
401#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
402#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
403
c44ade9e 404
11afc1b1
PW		 405/* Security Control Registers */
406#define IXGBE_SECTXCTRL 0x08800
407#define IXGBE_SECTXSTAT 0x08804
408#define IXGBE_SECTXBUFFAF 0x08808
409#define IXGBE_SECTXMINIFG 0x08810
410#define IXGBE_SECTXSTAT 0x08804
411#define IXGBE_SECRXCTRL 0x08D00
412#define IXGBE_SECRXSTAT 0x08D04
413
414/* Security Bit Fields and Masks */
415#define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001
416#define IXGBE_SECTXCTRL_TX_DIS 0x00000002
417#define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004
418
419#define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001
420#define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002
421
422#define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001
423#define IXGBE_SECRXCTRL_RX_DIS 0x00000002
424
425#define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001
426#define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002
427
428/* LinkSec (MacSec) Registers */
429#define IXGBE_LSECTXCAP 0x08A00
430#define IXGBE_LSECRXCAP 0x08F00
431#define IXGBE_LSECTXCTRL 0x08A04
432#define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */
433#define IXGBE_LSECTXSCH 0x08A0C /* SCI High */
434#define IXGBE_LSECTXSA 0x08A10
435#define IXGBE_LSECTXPN0 0x08A14
436#define IXGBE_LSECTXPN1 0x08A18
437#define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
438#define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
439#define IXGBE_LSECRXCTRL 0x08F04
440#define IXGBE_LSECRXSCL 0x08F08
441#define IXGBE_LSECRXSCH 0x08F0C
442#define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
443#define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
444#define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
445#define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */
446#define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */
447#define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */
448#define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */
449#define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */
450#define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */
451#define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */
452#define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */
453#define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */
454#define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */
455#define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */
456#define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */
457#define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */
458#define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */
459#define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */
460#define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */
461#define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */
462#define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */
463#define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */
464
465/* LinkSec (MacSec) Bit Fields and Masks */
466#define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000
467#define IXGBE_LSECTXCAP_SUM_SHIFT 16
468#define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000
469#define IXGBE_LSECRXCAP_SUM_SHIFT 16
470
471#define IXGBE_LSECTXCTRL_EN_MASK 0x00000003
472#define IXGBE_LSECTXCTRL_DISABLE 0x0
473#define IXGBE_LSECTXCTRL_AUTH 0x1
474#define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2
475#define IXGBE_LSECTXCTRL_AISCI 0x00000020
476#define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
477#define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8
478
479#define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C
480#define IXGBE_LSECRXCTRL_EN_SHIFT 2
481#define IXGBE_LSECRXCTRL_DISABLE 0x0
482#define IXGBE_LSECRXCTRL_CHECK 0x1
483#define IXGBE_LSECRXCTRL_STRICT 0x2
484#define IXGBE_LSECRXCTRL_DROP 0x3
485#define IXGBE_LSECRXCTRL_PLSH 0x00000040
486#define IXGBE_LSECRXCTRL_RP 0x00000080
487#define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33
488
489/* IpSec Registers */
490#define IXGBE_IPSTXIDX 0x08900
491#define IXGBE_IPSTXSALT 0x08904
492#define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
493#define IXGBE_IPSRXIDX 0x08E00
494#define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
495#define IXGBE_IPSRXSPI 0x08E14
496#define IXGBE_IPSRXIPIDX 0x08E18
497#define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
498#define IXGBE_IPSRXSALT 0x08E2C
499#define IXGBE_IPSRXMOD 0x08E30
500
501#define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4
502
f8212f97
AD		 503/* HW RSC registers */
504#define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
505 (0x0D02C + ((_i - 64) * 0x40)))
506#define IXGBE_RSCDBU 0x03028
507#define IXGBE_RSCCTL_RSCEN 0x01
508#define IXGBE_RSCCTL_MAXDESC_1 0x00
509#define IXGBE_RSCCTL_MAXDESC_4 0x04
510#define IXGBE_RSCCTL_MAXDESC_8 0x08
511#define IXGBE_RSCCTL_MAXDESC_16 0x0C
512#define IXGBE_RXDADV_RSCCNT_SHIFT 17
513#define IXGBE_GPIE_RSC_DELAY_SHIFT 11
514#define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000
515#define IXGBE_RSCDBU_RSCACKDIS 0x00000080
516#define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000
517
11afc1b1
PW		 518/* DCB registers */
519#define IXGBE_RTRPCS 0x02430
520#define IXGBE_RTTDCS 0x04900
7f870475 521#define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */
11afc1b1
PW		 522#define IXGBE_RTTPCS 0x0CD00
523#define IXGBE_RTRUP2TC 0x03020
524#define IXGBE_RTTUP2TC 0x0C800
525#define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */
526#define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */
527#define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */
528#define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */
529#define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
530#define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
531#define IXGBE_RTTDQSEL 0x04904
532#define IXGBE_RTTDT1C 0x04908
533#define IXGBE_RTTDT1S 0x0490C
534#define IXGBE_RTTDTECC 0x04990
535#define IXGBE_RTTDTECC_NO_BCN 0x00000100
536#define IXGBE_RTTBCNRC 0x04984
ff4ab206
LL		 537#define IXGBE_RTTBCNRC_RS_ENA 0x80000000
538#define IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF
539#define IXGBE_RTTBCNRC_RF_INT_SHIFT 14
540#define IXGBE_RTTBCNRC_RF_INT_MASK \
541 (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)
542
c44ade9e 543
bff66176
YZ		 544/* FCoE registers */
545#define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */
546#define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */
547#define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */
548#define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */
549#define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0 */
550#define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4))
551#define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */
552#define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */
553#define IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */
554#define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */
555#define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */
556#define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3
557#define IXGBE_FCBUFF_BUFFCNT_SHIFT 8
558#define IXGBE_FCBUFF_OFFSET_SHIFT 16
559#define IXGBE_FCDMARW_WE (1 << 14) /* Write enable */
560#define IXGBE_FCDMARW_RE (1 << 15) /* Read enable */
561#define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */
562#define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */
563#define IXGBE_FCDMARW_LASTSIZE_SHIFT 16
564
565/* FCoE SOF/EOF */
566#define IXGBE_TEOFF 0x04A94 /* Tx FC EOF */
567#define IXGBE_TSOFF 0x04A98 /* Tx FC SOF */
568#define IXGBE_REOFF 0x05158 /* Rx FC EOF */
569#define IXGBE_RSOFF 0x051F8 /* Rx FC SOF */
570/* FCoE Filter Context Registers */
571#define IXGBE_FCFLT 0x05108 /* FC FLT Context */
572#define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */
573#define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */
574#define IXGBE_FCFLT_VALID (1 << 0) /* Filter Context Valid */
575#define IXGBE_FCFLT_FIRST (1 << 1) /* Filter First */
576#define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */
577#define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */
578#define IXGBE_FCFLTRW_RVALDT (1 << 13) /* Fast Re-Validation */
579#define IXGBE_FCFLTRW_WE (1 << 14) /* Write Enable */
580#define IXGBE_FCFLTRW_RE (1 << 15) /* Read Enable */
581/* FCoE Receive Control */
582#define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */
583#define IXGBE_FCRXCTRL_FCOELLI (1 << 0) /* Low latency interrupt */
584#define IXGBE_FCRXCTRL_SAVBAD (1 << 1) /* Save Bad Frames */
585#define IXGBE_FCRXCTRL_FRSTRDH (1 << 2) /* EN 1st Read Header */
586#define IXGBE_FCRXCTRL_LASTSEQH (1 << 3) /* EN Last Header in Seq */
587#define IXGBE_FCRXCTRL_ALLH (1 << 4) /* EN All Headers */
588#define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */
589#define IXGBE_FCRXCTRL_ICRC (1 << 6) /* Ignore Bad FC CRC */
590#define IXGBE_FCRXCTRL_FCCRCBO (1 << 7) /* FC CRC Byte Ordering */
591#define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */
592#define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8
593/* FCoE Redirection */
594#define IXGBE_FCRECTL 0x0ED00 /* FC Redirection Control */
595#define IXGBE_FCRETA0 0x0ED10 /* FC Redirection Table 0 */
596#define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */
597#define IXGBE_FCRECTL_ENA 0x1 /* FCoE Redir Table Enable */
598#define IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */
599#define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */
600
9a799d71
AK		 601/* Stats registers */
602#define IXGBE_CRCERRS 0x04000
603#define IXGBE_ILLERRC 0x04004
604#define IXGBE_ERRBC 0x04008
605#define IXGBE_MSPDC 0x04010
606#define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
607#define IXGBE_MLFC 0x04034
608#define IXGBE_MRFC 0x04038
609#define IXGBE_RLEC 0x04040
610#define IXGBE_LXONTXC 0x03F60
611#define IXGBE_LXONRXC 0x0CF60
612#define IXGBE_LXOFFTXC 0x03F68
613#define IXGBE_LXOFFRXC 0x0CF68
11afc1b1
PW		 614#define IXGBE_LXONRXCNT 0x041A4
615#define IXGBE_LXOFFRXCNT 0x041A8
616#define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */
617#define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */
618#define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */
9a799d71
AK		 619#define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
620#define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
621#define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
622#define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
623#define IXGBE_PRC64 0x0405C
624#define IXGBE_PRC127 0x04060
625#define IXGBE_PRC255 0x04064
626#define IXGBE_PRC511 0x04068
627#define IXGBE_PRC1023 0x0406C
628#define IXGBE_PRC1522 0x04070
629#define IXGBE_GPRC 0x04074
630#define IXGBE_BPRC 0x04078
631#define IXGBE_MPRC 0x0407C
632#define IXGBE_GPTC 0x04080
633#define IXGBE_GORCL 0x04088
634#define IXGBE_GORCH 0x0408C
635#define IXGBE_GOTCL 0x04090
636#define IXGBE_GOTCH 0x04094
637#define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
638#define IXGBE_RUC 0x040A4
639#define IXGBE_RFC 0x040A8
640#define IXGBE_ROC 0x040AC
641#define IXGBE_RJC 0x040B0
642#define IXGBE_MNGPRC 0x040B4
643#define IXGBE_MNGPDC 0x040B8
644#define IXGBE_MNGPTC 0x0CF90
645#define IXGBE_TORL 0x040C0
646#define IXGBE_TORH 0x040C4
647#define IXGBE_TPR 0x040D0
648#define IXGBE_TPT 0x040D4
649#define IXGBE_PTC64 0x040D8
650#define IXGBE_PTC127 0x040DC
651#define IXGBE_PTC255 0x040E0
652#define IXGBE_PTC511 0x040E4
653#define IXGBE_PTC1023 0x040E8
654#define IXGBE_PTC1522 0x040EC
655#define IXGBE_MPTC 0x040F0
656#define IXGBE_BPTC 0x040F4
657#define IXGBE_XEC 0x04120
11afc1b1 658#define IXGBE_SSVPC 0x08780
9a799d71 659
11afc1b1
PW		 660#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
661#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
662 (0x08600 + ((_i) * 4)))
663#define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4))
9a799d71
AK		 664
665#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
666#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
667#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
668#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
667c7565
ET		 669#define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
670#define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */
11afc1b1
PW		 671#define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */
672#define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */
673#define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */
bff66176
YZ		 674#define IXGBE_FCCRC 0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */
675#define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */
676#define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */
677#define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */
678#define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */
679#define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */
680#define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */
a3aeea0e
ET		 681#define IXGBE_PCRC8ECL 0x0E810
682#define IXGBE_PCRC8ECH 0x0E811
683#define IXGBE_PCRC8ECH_MASK 0x1F
684#define IXGBE_LDPCECL 0x0E820
685#define IXGBE_LDPCECH 0x0E821
9a799d71
AK		 686
687/* Management */
688#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
689#define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
690#define IXGBE_MANC 0x05820
691#define IXGBE_MFVAL 0x05824
692#define IXGBE_MANC2H 0x05860
693#define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
694#define IXGBE_MIPAF 0x058B0
695#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
696#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
697#define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */
11afc1b1
PW		 698#define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
699#define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
700#define IXGBE_LSWFW 0x15014
9a799d71
AK		 701
702/* ARC Subsystem registers */
703#define IXGBE_HICR 0x15F00
704#define IXGBE_FWSTS 0x15F0C
705#define IXGBE_HSMC0R 0x15F04
706#define IXGBE_HSMC1R 0x15F08
707#define IXGBE_SWSR 0x15F10
708#define IXGBE_HFDR 0x15FE8
709#define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */
710
711/* PCI-E registers */
712#define IXGBE_GCR 0x11000
713#define IXGBE_GTV 0x11004
714#define IXGBE_FUNCTAG 0x11008
715#define IXGBE_GLT 0x1100C
716#define IXGBE_GSCL_1 0x11010
717#define IXGBE_GSCL_2 0x11014
718#define IXGBE_GSCL_3 0x11018
719#define IXGBE_GSCL_4 0x1101C
720#define IXGBE_GSCN_0 0x11020
721#define IXGBE_GSCN_1 0x11024
722#define IXGBE_GSCN_2 0x11028
723#define IXGBE_GSCN_3 0x1102C
724#define IXGBE_FACTPS 0x10150
725#define IXGBE_PCIEANACTL 0x11040
726#define IXGBE_SWSM 0x10140
727#define IXGBE_FWSM 0x10148
728#define IXGBE_GSSR 0x10160
729#define IXGBE_MREVID 0x11064
730#define IXGBE_DCA_ID 0x11070
731#define IXGBE_DCA_CTRL 0x11074
21ce849b 732#define IXGBE_SWFW_SYNC IXGBE_GSSR
9a799d71 733
11afc1b1
PW		 734/* PCIe registers 82599-specific */
735#define IXGBE_GCR_EXT 0x11050
736#define IXGBE_GSCL_5_82599 0x11030
737#define IXGBE_GSCL_6_82599 0x11034
738#define IXGBE_GSCL_7_82599 0x11038
739#define IXGBE_GSCL_8_82599 0x1103C
740#define IXGBE_PHYADR_82599 0x11040
741#define IXGBE_PHYDAT_82599 0x11044
742#define IXGBE_PHYCTL_82599 0x11048
743#define IXGBE_PBACLR_82599 0x11068
744#define IXGBE_CIAA_82599 0x11088
745#define IXGBE_CIAD_82599 0x1108C
746#define IXGBE_PCIE_DIAG_0_82599 0x11090
747#define IXGBE_PCIE_DIAG_1_82599 0x11094
748#define IXGBE_PCIE_DIAG_2_82599 0x11098
749#define IXGBE_PCIE_DIAG_3_82599 0x1109C
750#define IXGBE_PCIE_DIAG_4_82599 0x110A0
751#define IXGBE_PCIE_DIAG_5_82599 0x110A4
752#define IXGBE_PCIE_DIAG_6_82599 0x110A8
753#define IXGBE_PCIE_DIAG_7_82599 0x110C0
754#define IXGBE_INTRPT_CSR_82599 0x110B0
755#define IXGBE_INTRPT_MASK_82599 0x110B8
756#define IXGBE_CDQ_MBR_82599 0x110B4
757#define IXGBE_MISC_REG_82599 0x110F0
758#define IXGBE_ECC_CTRL_0_82599 0x11100
759#define IXGBE_ECC_CTRL_1_82599 0x11104
760#define IXGBE_ECC_STATUS_82599 0x110E0
761#define IXGBE_BAR_CTRL_82599 0x110F4
762
202ff1ec
MC		 763/* PCI Express Control */
764#define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000
765#define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000
766#define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000
767#define IXGBE_GCR_CAP_VER2 0x00040000
768
7f870475
GR		 769#define IXGBE_GCR_EXT_MSIX_EN 0x80000000
770#define IXGBE_GCR_EXT_VT_MODE_16 0x00000001
771#define IXGBE_GCR_EXT_VT_MODE_32 0x00000002
772#define IXGBE_GCR_EXT_VT_MODE_64 0x00000003
773#define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \
774 IXGBE_GCR_EXT_VT_MODE_64)
775
11afc1b1
PW		 776/* Time Sync Registers */
777#define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */
778#define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */
779#define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */
780#define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */
781#define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */
782#define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */
783#define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */
784#define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */
785#define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */
786#define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */
787#define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */
788#define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */
789#define IXGBE_RXUDP 0x08C1C /* Time Sync Rx UDP Port - RW */
790
9a799d71 791/* Diagnostic Registers */
c44ade9e
JB		 792#define IXGBE_RDSTATCTL 0x02C20
793#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
794#define IXGBE_RDHMPN 0x02F08
98c00a1c 795#define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4))
c44ade9e 796#define IXGBE_RDPROBE 0x02F20
11afc1b1
PW		 797#define IXGBE_RDMAM 0x02F30
798#define IXGBE_RDMAD 0x02F34
c44ade9e
JB		 799#define IXGBE_TDSTATCTL 0x07C20
800#define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
801#define IXGBE_TDHMPN 0x07F08
11afc1b1
PW		 802#define IXGBE_TDHMPN2 0x082FC
803#define IXGBE_TXDESCIC 0x082CC
98c00a1c 804#define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4))
11afc1b1 805#define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4))
c44ade9e
JB		 806#define IXGBE_TDPROBE 0x07F20
807#define IXGBE_TXBUFCTRL 0x0C600
9a799d71
AK		 808#define IXGBE_TXBUFDATA0 0x0C610
809#define IXGBE_TXBUFDATA1 0x0C614
810#define IXGBE_TXBUFDATA2 0x0C618
811#define IXGBE_TXBUFDATA3 0x0C61C
812#define IXGBE_RXBUFCTRL 0x03600
813#define IXGBE_RXBUFDATA0 0x03610
814#define IXGBE_RXBUFDATA1 0x03614
815#define IXGBE_RXBUFDATA2 0x03618
816#define IXGBE_RXBUFDATA3 0x0361C
817#define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */
818#define IXGBE_RFVAL 0x050A4
819#define IXGBE_MDFTC1 0x042B8
820#define IXGBE_MDFTC2 0x042C0
821#define IXGBE_MDFTFIFO1 0x042C4
822#define IXGBE_MDFTFIFO2 0x042C8
823#define IXGBE_MDFTS 0x042CC
824#define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
825#define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
826#define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
827#define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
828#define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
829#define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
830#define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
831#define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
832#define IXGBE_PCIEECCCTL 0x1106C
11afc1b1
PW		 833#define IXGBE_PCIEECCCTL0 0x11100
834#define IXGBE_PCIEECCCTL1 0x11104
9a799d71
AK		 835#define IXGBE_PBTXECC 0x0C300
836#define IXGBE_PBRXECC 0x03300
837#define IXGBE_GHECCR 0x110B0
838
839/* MAC Registers */
840#define IXGBE_PCS1GCFIG 0x04200
841#define IXGBE_PCS1GLCTL 0x04208
842#define IXGBE_PCS1GLSTA 0x0420C
843#define IXGBE_PCS1GDBG0 0x04210
844#define IXGBE_PCS1GDBG1 0x04214
845#define IXGBE_PCS1GANA 0x04218
846#define IXGBE_PCS1GANLP 0x0421C
847#define IXGBE_PCS1GANNP 0x04220
848#define IXGBE_PCS1GANLPNP 0x04224
849#define IXGBE_HLREG0 0x04240
850#define IXGBE_HLREG1 0x04244
851#define IXGBE_PAP 0x04248
852#define IXGBE_MACA 0x0424C
853#define IXGBE_APAE 0x04250
854#define IXGBE_ARD 0x04254
855#define IXGBE_AIS 0x04258
856#define IXGBE_MSCA 0x0425C
857#define IXGBE_MSRWD 0x04260
858#define IXGBE_MLADD 0x04264
859#define IXGBE_MHADD 0x04268
11afc1b1 860#define IXGBE_MAXFRS 0x04268
9a799d71
AK		 861#define IXGBE_TREG 0x0426C
862#define IXGBE_PCSS1 0x04288
863#define IXGBE_PCSS2 0x0428C
864#define IXGBE_XPCSS 0x04290
11afc1b1 865#define IXGBE_MFLCN 0x04294
9a799d71
AK		 866#define IXGBE_SERDESC 0x04298
867#define IXGBE_MACS 0x0429C
868#define IXGBE_AUTOC 0x042A0
869#define IXGBE_LINKS 0x042A4
11afc1b1 870#define IXGBE_LINKS2 0x04324
9a799d71
AK		 871#define IXGBE_AUTOC2 0x042A8
872#define IXGBE_AUTOC3 0x042AC
873#define IXGBE_ANLP1 0x042B0
874#define IXGBE_ANLP2 0x042B4
875#define IXGBE_ATLASCTL 0x04800
11afc1b1
PW		 876#define IXGBE_MMNGC 0x042D0
877#define IXGBE_ANLPNP1 0x042D4
878#define IXGBE_ANLPNP2 0x042D8
879#define IXGBE_KRPCSFC 0x042E0
880#define IXGBE_KRPCSS 0x042E4
881#define IXGBE_FECS1 0x042E8
882#define IXGBE_FECS2 0x042EC
883#define IXGBE_SMADARCTL 0x14F10
884#define IXGBE_MPVC 0x04318
885#define IXGBE_SGMIIC 0x04314
886
734e979f
MC		 887#define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50
888
11afc1b1
PW		 889/* Omer CORECTL */
890#define IXGBE_CORECTL 0x014F00
891/* BARCTRL */
892#define IXGBE_BARCTRL 0x110F4
893#define IXGBE_BARCTRL_FLSIZE 0x0700
894#define IXGBE_BARCTRL_CSRSIZE 0x2000
9a799d71 895
cc41ac7c
JB		 896/* RDRXCTL Bit Masks */
897#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */
11afc1b1 898#define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */
cc41ac7c
JB		 899#define IXGBE_RDRXCTL_MVMEN 0x00000020
900#define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */
11afc1b1 901#define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */
7367096a
AD		 902#define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC enabled */
903#define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC enabled */
11afc1b1
PW		 904
905/* RQTC Bit Masks and Shifts */
906#define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)
907#define IXGBE_RQTC_TC0_MASK (0x7 << 0)
908#define IXGBE_RQTC_TC1_MASK (0x7 << 4)
909#define IXGBE_RQTC_TC2_MASK (0x7 << 8)
910#define IXGBE_RQTC_TC3_MASK (0x7 << 12)
911#define IXGBE_RQTC_TC4_MASK (0x7 << 16)
912#define IXGBE_RQTC_TC5_MASK (0x7 << 20)
913#define IXGBE_RQTC_TC6_MASK (0x7 << 24)
914#define IXGBE_RQTC_TC7_MASK (0x7 << 28)
915
916/* PSRTYPE.RQPL Bit masks and shift */
917#define IXGBE_PSRTYPE_RQPL_MASK 0x7
918#define IXGBE_PSRTYPE_RQPL_SHIFT 29
9a799d71
AK		 919
920/* CTRL Bit Masks */
921#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */
922#define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */
923#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */
924
925/* FACTPS */
926#define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */
927
928/* MHADD Bit Masks */
929#define IXGBE_MHADD_MFS_MASK 0xFFFF0000
930#define IXGBE_MHADD_MFS_SHIFT 16
931
932/* Extended Device Control */
11afc1b1 933#define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */
9a799d71
AK		 934#define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */
935#define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
936#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
937
938/* Direct Cache Access (DCA) definitions */
939#define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
940#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
941
942#define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
943#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
944
945#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
11afc1b1
PW		 946#define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */
947#define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */
9a799d71
AK		 948#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
949#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
950#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
15005a32
DS		 951#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */
952#define IXGBE_DCA_RXCTRL_DESC_WRO_EN (1 << 13) /* DCA Rx wr Desc Relax Order */
953#define IXGBE_DCA_RXCTRL_DESC_HSRO_EN (1 << 15) /* DCA Rx Split Header RO */
9a799d71
AK		 954
955#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
11afc1b1
PW		 956#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */
957#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */
9a799d71 958#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
c44ade9e 959#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
9a799d71
AK		 960#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */
961
962/* MSCA Bit Masks */
963#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */
964#define IXGBE_MSCA_NP_ADDR_SHIFT 0
965#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */
966#define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */
967#define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */
968#define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/
969#define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */
970#define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */
971#define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */
972#define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */
973#define IXGBE_MSCA_READ 0x08000000 /* OP CODE 10 (read) */
974#define IXGBE_MSCA_READ_AUTOINC 0x0C000000 /* OP CODE 11 (read, auto inc)*/
975#define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */
976#define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */
977#define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */
978#define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old protocol) */
979#define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */
980#define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */
981
982/* MSRWD bit masks */
c44ade9e
JB		 983#define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF
984#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0
985#define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000
986#define IXGBE_MSRWD_READ_DATA_SHIFT 16
9a799d71
AK		 987
988/* Atlas registers */
989#define IXGBE_ATLAS_PDN_LPBK 0x24
990#define IXGBE_ATLAS_PDN_10G 0xB
991#define IXGBE_ATLAS_PDN_1G 0xC
992#define IXGBE_ATLAS_PDN_AN 0xD
993
994/* Atlas bit masks */
995#define IXGBE_ATLASCTL_WRITE_CMD 0x00010000
996#define IXGBE_ATLAS_PDN_TX_REG_EN 0x10
997#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0
998#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
999#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
1000
11afc1b1
PW		 1001/* Omer bit masks */
1002#define IXGBE_CORECTL_WRITE_CMD 0x00010000
c44ade9e 1003
6b73e10d 1004/* MDIO definitions */
9a799d71 1005
c44ade9e
JB		 1006#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */
1007
9a799d71
AK		 1008#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */
1009#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */
1010#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */
1011#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
1012#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018
1013#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010
1014
11afc1b1 1015#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
c44ade9e
JB		 1016#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
1017#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
1018
9dda1736
ET		 1019/* MII clause 22/28 definitions */
1020#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
1021#define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */
1022#define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/
1023#define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/
1024#define IXGBE_MII_AUTONEG_REG 0x0
1025
9a799d71
AK		 1026#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
1027#define IXGBE_MAX_PHY_ADDR 32
1028
11afc1b1 1029/* PHY IDs*/
0befdb3e
JB		 1030#define TN1010_PHY_ID 0x00A19410
1031#define TNX_FW_REV 0xB
2b264909 1032#define X540_PHY_ID 0x01540200
9a799d71 1033#define QT2022_PHY_ID 0x0043A400
c4900be0 1034#define ATH_PHY_ID 0x03429050
fe15e8e1 1035#define AQ_FW_REV 0x20
9a799d71 1036
c44ade9e
JB		 1037/* PHY Types */
1038#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
1039
c4900be0
DS		 1040/* Special PHY Init Routine */
1041#define IXGBE_PHY_INIT_OFFSET_NL 0x002B
1042#define IXGBE_PHY_INIT_END_NL 0xFFFF
1043#define IXGBE_CONTROL_MASK_NL 0xF000
1044#define IXGBE_DATA_MASK_NL 0x0FFF
1045#define IXGBE_CONTROL_SHIFT_NL 12
1046#define IXGBE_DELAY_NL 0
1047#define IXGBE_DATA_NL 1
1048#define IXGBE_CONTROL_NL 0x000F
1049#define IXGBE_CONTROL_EOL_NL 0x0FFF
1050#define IXGBE_CONTROL_SOL_NL 0x0000
1051
9a799d71 1052/* General purpose Interrupt Enable */
c44ade9e
JB		 1053#define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */
1054#define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */
11afc1b1 1055#define IXGBE_SDP2_GPIEN 0x00000004 /* SDP2 */
c44ade9e
JB		 1056#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */
1057#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */
1058#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */
1059#define IXGBE_GPIE_EIAME 0x40000000
1060#define IXGBE_GPIE_PBA_SUPPORT 0x80000000
11afc1b1
PW		 1061#define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */
1062#define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */
1063#define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */
1064#define IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */
9a799d71
AK		 1065
1066/* Transmit Flow Control status */
1067#define IXGBE_TFCS_TXOFF 0x00000001
1068#define IXGBE_TFCS_TXOFF0 0x00000100
1069#define IXGBE_TFCS_TXOFF1 0x00000200
1070#define IXGBE_TFCS_TXOFF2 0x00000400
1071#define IXGBE_TFCS_TXOFF3 0x00000800
1072#define IXGBE_TFCS_TXOFF4 0x00001000
1073#define IXGBE_TFCS_TXOFF5 0x00002000
1074#define IXGBE_TFCS_TXOFF6 0x00004000
1075#define IXGBE_TFCS_TXOFF7 0x00008000
1076
1077/* TCP Timer */
1078#define IXGBE_TCPTIMER_KS 0x00000100
1079#define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200
1080#define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400
1081#define IXGBE_TCPTIMER_LOOP 0x00000800
1082#define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
1083
1084/* HLREG0 Bit Masks */
1085#define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */
1086#define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */
1087#define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */
1088#define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */
1089#define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */
1090#define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */
1091#define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */
1092#define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */
1093#define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */
1094#define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */
1095#define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */
1096#define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */
1097#define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */
1098#define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */
1099#define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */
1100
1101/* VMD_CTL bitmasks */
1102#define IXGBE_VMD_CTL_VMDQ_EN 0x00000001
1103#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
1104
11afc1b1
PW		 1105/* VT_CTL bitmasks */
1106#define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */
1107#define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */
1108#define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */
6e4e87d6
DS		 1109#define IXGBE_VT_CTL_POOL_SHIFT 7
1110#define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT)
11afc1b1
PW		 1111
1112/* VMOLR bitmasks */
1113#define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */
1114#define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */
1115#define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */
1116#define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */
1117#define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */
1118
1119/* VFRE bitmask */
1120#define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF
1121
7f870475
GR		 1122#define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
1123
9a799d71
AK		 1124/* RDHMPN and TDHMPN bitmasks */
1125#define IXGBE_RDHMPN_RDICADDR 0x007FF800
1126#define IXGBE_RDHMPN_RDICRDREQ 0x00800000
1127#define IXGBE_RDHMPN_RDICADDR_SHIFT 11
1128#define IXGBE_TDHMPN_TDICADDR 0x003FF800
1129#define IXGBE_TDHMPN_TDICRDREQ 0x00800000
1130#define IXGBE_TDHMPN_TDICADDR_SHIFT 11
1131
11afc1b1
PW		 1132#define IXGBE_RDMAM_MEM_SEL_SHIFT 13
1133#define IXGBE_RDMAM_DWORD_SHIFT 9
1134#define IXGBE_RDMAM_DESC_COMP_FIFO 1
1135#define IXGBE_RDMAM_DFC_CMD_FIFO 2
1136#define IXGBE_RDMAM_TCN_STATUS_RAM 4
1137#define IXGBE_RDMAM_WB_COLL_FIFO 5
1138#define IXGBE_RDMAM_QSC_CNT_RAM 6
1139#define IXGBE_RDMAM_QSC_QUEUE_CNT 8
1140#define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA
1141#define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135
1142#define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4
1143#define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48
1144#define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7
1145#define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256
1146#define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9
1147#define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8
1148#define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4
1149#define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64
1150#define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4
1151#define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32
1152#define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4
1153#define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128
1154#define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8
1155
1156#define IXGBE_TXDESCIC_READY 0x80000000
1157
9a799d71
AK		 1158/* Receive Checksum Control */
1159#define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
1160#define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
1161
1162/* FCRTL Bit Masks */
11afc1b1
PW		 1163#define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */
1164#define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */
9a799d71
AK		 1165
1166/* PAP bit masks*/
1167#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */
1168
1169/* RMCS Bit Masks */
c44ade9e 1170#define IXGBE_RMCS_RRM 0x00000002 /* Receive Recycle Mode enable */
9a799d71
AK		 1171/* Receive Arbitration Control: 0 Round Robin, 1 DFP */
1172#define IXGBE_RMCS_RAC 0x00000004
1173#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
11afc1b1
PW		 1174#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */
1175#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */
9a799d71
AK		 1176#define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */
1177
11afc1b1
PW		 1178/* FCCFG Bit Masks */
1179#define IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */
1180#define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */
c44ade9e 1181
9a799d71
AK		 1182/* Interrupt register bitmasks */
1183
1184/* Extended Interrupt Cause Read */
1185#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */
11afc1b1
PW		 1186#define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */
1187#define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */
1188#define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */
1189#define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */
9a799d71 1190#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */
11afc1b1 1191#define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */
c44ade9e
JB		 1192#define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */
1193#define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */
1194#define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */
11afc1b1
PW		 1195#define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */
1196#define IXGBE_EICR_ECC 0x10000000 /* ECC Error */
9a799d71
AK		 1197#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */
1198#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */
1199#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
1200#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
1201
1202/* Extended Interrupt Cause Set */
1203#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
11afc1b1
PW		 1204#define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1205#define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */
1206#define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */
1207#define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
c44ade9e
JB		 1208#define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */
1209#define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
1210#define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1211#define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
11afc1b1
PW		 1212#define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1213#define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */
c44ade9e
JB		 1214#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1215#define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */
9a799d71
AK		 1216#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1217#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1218
1219/* Extended Interrupt Mask Set */
1220#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
11afc1b1
PW		 1221#define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1222#define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1223#define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */
1224#define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
9a799d71
AK		 1225#define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */
1226#define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
c44ade9e
JB		 1227#define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1228#define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
11afc1b1
PW		 1229#define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1230#define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */
c44ade9e 1231#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
9a799d71
AK		 1232#define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */
1233#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1234#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1235
1236/* Extended Interrupt Mask Clear */
1237#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
11afc1b1
PW		 1238#define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1239#define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1240#define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */
1241#define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
9a799d71
AK		 1242#define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */
1243#define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
c44ade9e
JB		 1244#define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1245#define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
11afc1b1
PW		 1246#define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1247#define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */
c44ade9e
JB		 1248#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1249#define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */
9a799d71
AK		 1250#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1251#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1252
c44ade9e
JB		 1253#define IXGBE_EIMS_ENABLE_MASK ( \
1254 IXGBE_EIMS_RTX_QUEUE | \
1255 IXGBE_EIMS_LSC | \
1256 IXGBE_EIMS_TCP_TIMER | \
1257 IXGBE_EIMS_OTHER)
9a799d71 1258
c44ade9e 1259/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
9a799d71
AK		 1260#define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */
1261#define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */
1262#define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
1263#define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */
1264#define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */
1265#define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */
1266#define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */
1267#define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */
1268#define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */
1269#define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */
11afc1b1
PW		 1270#define IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */
1271#define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */
1272#define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */
1273#define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */
1274#define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */
1275#define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */
1276#define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */
1277#define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass check of control bits */
1278#define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */
1279#define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */
1280#define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */
1281#define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */
1282#define IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */
1283
1284#define IXGBE_MAX_FTQF_FILTERS 128
1285#define IXGBE_FTQF_PROTOCOL_MASK 0x00000003
1286#define IXGBE_FTQF_PROTOCOL_TCP 0x00000000
1287#define IXGBE_FTQF_PROTOCOL_UDP 0x00000001
1288#define IXGBE_FTQF_PROTOCOL_SCTP 2
1289#define IXGBE_FTQF_PRIORITY_MASK 0x00000007
1290#define IXGBE_FTQF_PRIORITY_SHIFT 2
1291#define IXGBE_FTQF_POOL_MASK 0x0000003F
1292#define IXGBE_FTQF_POOL_SHIFT 8
1293#define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F
1294#define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25
1295#define IXGBE_FTQF_POOL_MASK_EN 0x40000000
1296#define IXGBE_FTQF_QUEUE_ENABLE 0x80000000
9a799d71
AK		 1297
1298/* Interrupt clear mask */
1299#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF
1300
1301/* Interrupt Vector Allocation Registers */
1302#define IXGBE_IVAR_REG_NUM 25
e80e887a 1303#define IXGBE_IVAR_REG_NUM_82599 64
9a799d71
AK		 1304#define IXGBE_IVAR_TXRX_ENTRY 96
1305#define IXGBE_IVAR_RX_ENTRY 64
1306#define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i))
1307#define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i))
1308#define IXGBE_IVAR_TX_ENTRY 32
1309
1310#define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */
1311#define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */
1312
1313#define IXGBE_MSIX_VECTOR(_i) (0 + (_i))
1314
1315#define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
1316
11afc1b1
PW		 1317/* ETYPE Queue Filter/Select Bit Masks */
1318#define IXGBE_MAX_ETQF_FILTERS 8
bff66176 1319#define IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */
11afc1b1
PW		 1320#define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */
1321#define IXGBE_ETQF_1588 0x40000000 /* bit 30 */
1322#define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */
1323#define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */
1324
1325#define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */
1326#define IXGBE_ETQS_RX_QUEUE_SHIFT 16
1327#define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */
1328#define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */
1329
1330/*
1331 * ETQF filter list: one static filter per filter consumer. This is
1332 * to avoid filter collisions later. Add new filters
1333 * here!!
1334 *
1335 * Current filters:
1336 * EAPOL 802.1x (0x888e): Filter 0
1337 * BCN (0x8904): Filter 1
1338 * 1588 (0x88f7): Filter 3
1339 */
1340#define IXGBE_ETQF_FILTER_EAPOL 0
1341#define IXGBE_ETQF_FILTER_BCN 1
bff66176 1342#define IXGBE_ETQF_FILTER_FCOE 2
11afc1b1 1343#define IXGBE_ETQF_FILTER_1588 3
af06393b 1344#define IXGBE_ETQF_FILTER_FIP 4
9a799d71
AK		 1345/* VLAN Control Bit Masks */
1346#define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */
1347#define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */
1348#define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */
1349#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */
1350#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */
1351
11afc1b1
PW		 1352/* VLAN pool filtering masks */
1353#define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */
1354#define IXGBE_VLVF_ENTRIES 64
7f870475 1355#define IXGBE_VLVF_VLANID_MASK 0x00000FFF
c44ade9e 1356
7f01648a
GR		 1357/* Per VF Port VLAN insertion rules */
1358#define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
1359#define IXGBE_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */
1360
9a799d71
AK		 1361#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */
1362
1363/* STATUS Bit Masks */
11afc1b1
PW		 1364#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
1365#define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/
1366#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
9a799d71
AK		 1367
1368#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */
1369#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */
1370
1371/* ESDP Bit Masks */
50ac58ba
PWJ		 1372#define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */
1373#define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */
1374#define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */
1375#define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */
11afc1b1
PW		 1376#define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
1377#define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
1378#define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
9a799d71 1379#define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */
11afc1b1 1380#define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */
9a799d71
AK		 1381
1382/* LEDCTL Bit Masks */
1383#define IXGBE_LED_IVRT_BASE 0x00000040
1384#define IXGBE_LED_BLINK_BASE 0x00000080
1385#define IXGBE_LED_MODE_MASK_BASE 0x0000000F
1386#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
1387#define IXGBE_LED_MODE_SHIFT(_i) (8*(_i))
1388#define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
1389#define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
1390#define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
1391
1392/* LED modes */
1393#define IXGBE_LED_LINK_UP 0x0
1394#define IXGBE_LED_LINK_10G 0x1
1395#define IXGBE_LED_MAC 0x2
1396#define IXGBE_LED_FILTER 0x3
1397#define IXGBE_LED_LINK_ACTIVE 0x4
1398#define IXGBE_LED_LINK_1G 0x5
1399#define IXGBE_LED_ON 0xE
1400#define IXGBE_LED_OFF 0xF
1401
1402/* AUTOC Bit Masks */
3201d313 1403#define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000
9a799d71
AK		 1404#define IXGBE_AUTOC_KX4_SUPP 0x80000000
1405#define IXGBE_AUTOC_KX_SUPP 0x40000000
1406#define IXGBE_AUTOC_PAUSE 0x30000000
539e5f02
PWJ		 1407#define IXGBE_AUTOC_ASM_PAUSE 0x20000000
1408#define IXGBE_AUTOC_SYM_PAUSE 0x10000000
9a799d71
AK		 1409#define IXGBE_AUTOC_RF 0x08000000
1410#define IXGBE_AUTOC_PD_TMR 0x06000000
1411#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
1412#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
1413#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
11afc1b1
PW		 1414#define IXGBE_AUTOC_FECA 0x00040000
1415#define IXGBE_AUTOC_FECR 0x00020000
1416#define IXGBE_AUTOC_KR_SUPP 0x00010000
9a799d71
AK		 1417#define IXGBE_AUTOC_AN_RESTART 0x00001000
1418#define IXGBE_AUTOC_FLU 0x00000001
1419#define IXGBE_AUTOC_LMS_SHIFT 13
11afc1b1
PW		 1420#define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT)
1421#define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1422#define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT)
1423#define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1424#define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)
c44ade9e
JB		 1425#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1426#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
1427#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
1428#define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
1429#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1430#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1431#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1432
11afc1b1
PW		 1433#define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200
1434#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
1435#define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180
1436#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
9a799d71
AK		 1437#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1438#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1439#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1440#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1441#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
11afc1b1
PW		 1442#define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1443#define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1444
1445#define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000
1446#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000
1447#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
1448#define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1449#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1450#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
9a799d71
AK		 1451
1452/* LINKS Bit Masks */
1453#define IXGBE_LINKS_KX_AN_COMP 0x80000000
1454#define IXGBE_LINKS_UP 0x40000000
1455#define IXGBE_LINKS_SPEED 0x20000000
1456#define IXGBE_LINKS_MODE 0x18000000
1457#define IXGBE_LINKS_RX_MODE 0x06000000
1458#define IXGBE_LINKS_TX_MODE 0x01800000
1459#define IXGBE_LINKS_XGXS_EN 0x00400000
11afc1b1 1460#define IXGBE_LINKS_SGMII_EN 0x02000000
9a799d71
AK		 1461#define IXGBE_LINKS_PCS_1G_EN 0x00200000
1462#define IXGBE_LINKS_1G_AN_EN 0x00100000
1463#define IXGBE_LINKS_KX_AN_IDLE 0x00080000
1464#define IXGBE_LINKS_1G_SYNC 0x00040000
1465#define IXGBE_LINKS_10G_ALIGN 0x00020000
1466#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
1467#define IXGBE_LINKS_TL_FAULT 0x00001000
1468#define IXGBE_LINKS_SIGNAL 0x00000F00
1469
11afc1b1
PW		 1470#define IXGBE_LINKS_SPEED_82599 0x30000000
1471#define IXGBE_LINKS_SPEED_10G_82599 0x30000000
1472#define IXGBE_LINKS_SPEED_1G_82599 0x20000000
1473#define IXGBE_LINKS_SPEED_100_82599 0x10000000
cf8280ee 1474#define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
9a799d71
AK		 1475#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
1476
539e5f02
PWJ		 1477#define IXGBE_LINKS2_AN_SUPPORTED 0x00000040
1478
0ecc061d
PWJ		 1479/* PCS1GLSTA Bit Masks */
1480#define IXGBE_PCS1GLSTA_LINK_OK 1
1481#define IXGBE_PCS1GLSTA_SYNK_OK 0x10
1482#define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000
1483#define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000
1484#define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000
1485#define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
1486#define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000
1487
1488#define IXGBE_PCS1GANA_SYM_PAUSE 0x80
1489#define IXGBE_PCS1GANA_ASM_PAUSE 0x100
1490
1491/* PCS1GLCTL Bit Masks */
1492#define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */
1493#define IXGBE_PCS1GLCTL_FLV_LINK_UP 1
1494#define IXGBE_PCS1GLCTL_FORCE_LINK 0x20
1495#define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40
1496#define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000
1497#define IXGBE_PCS1GLCTL_AN_RESTART 0x20000
1498
539e5f02
PWJ		 1499/* ANLP1 Bit Masks */
1500#define IXGBE_ANLP1_PAUSE 0x0C00
1501#define IXGBE_ANLP1_SYM_PAUSE 0x0400
1502#define IXGBE_ANLP1_ASM_PAUSE 0x0800
a7f5a5fc
DS		 1503#define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000
1504
539e5f02 1505
9a799d71
AK		 1506/* SW Semaphore Register bitmasks */
1507#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
1508#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
1509#define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
21ce849b 1510#define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */
9a799d71 1511
21ce849b 1512/* SW_FW_SYNC/GSSR definitions */
9a799d71
AK		 1513#define IXGBE_GSSR_EEP_SM 0x0001
1514#define IXGBE_GSSR_PHY0_SM 0x0002
1515#define IXGBE_GSSR_PHY1_SM 0x0004
1516#define IXGBE_GSSR_MAC_CSR_SM 0x0008
1517#define IXGBE_GSSR_FLASH_SM 0x0010
1518
1519/* EEC Register */
1520#define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */
1521#define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */
1522#define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */
1523#define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */
1524#define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */
1525#define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */
1526#define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */
1527#define IXGBE_EEC_FWE_SHIFT 4
1528#define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */
1529#define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */
1530#define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */
1531#define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */
21ce849b 1532#define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */
fe15e8e1 1533#define IXGBE_EEC_SEC1VAL 0x02000000 /* Sector 1 Valid */
21ce849b 1534#define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */
9a799d71
AK		 1535/* EEPROM Addressing bits based on type (0-small, 1-large) */
1536#define IXGBE_EEC_ADDR_SIZE 0x00000400
1537#define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */
1538
1539#define IXGBE_EEC_SIZE_SHIFT 11
1540#define IXGBE_EEPROM_WORD_SIZE_SHIFT 6
1541#define IXGBE_EEPROM_OPCODE_BITS 8
1542
289700db
DS		 1543/* Part Number String Length */
1544#define IXGBE_PBANUM_LENGTH 11
1545
9a799d71 1546/* Checksum and EEPROM pointers */
289700db 1547#define IXGBE_PBANUM_PTR_GUARD 0xFAFA
9a799d71
AK		 1548#define IXGBE_EEPROM_CHECKSUM 0x3F
1549#define IXGBE_EEPROM_SUM 0xBABA
1550#define IXGBE_PCIE_ANALOG_PTR 0x03
1551#define IXGBE_ATLAS0_CONFIG_PTR 0x04
fe15e8e1 1552#define IXGBE_PHY_PTR 0x04
9a799d71 1553#define IXGBE_ATLAS1_CONFIG_PTR 0x05
fe15e8e1 1554#define IXGBE_OPTION_ROM_PTR 0x05
9a799d71
AK		 1555#define IXGBE_PCIE_GENERAL_PTR 0x06
1556#define IXGBE_PCIE_CONFIG0_PTR 0x07
1557#define IXGBE_PCIE_CONFIG1_PTR 0x08
1558#define IXGBE_CORE0_PTR 0x09
1559#define IXGBE_CORE1_PTR 0x0A
1560#define IXGBE_MAC0_PTR 0x0B
1561#define IXGBE_MAC1_PTR 0x0C
1562#define IXGBE_CSR0_CONFIG_PTR 0x0D
1563#define IXGBE_CSR1_CONFIG_PTR 0x0E
1564#define IXGBE_FW_PTR 0x0F
1565#define IXGBE_PBANUM0_PTR 0x15
1566#define IXGBE_PBANUM1_PTR 0x16
04193058 1567#define IXGBE_DEVICE_CAPS 0x2C
0365e6e4 1568#define IXGBE_SAN_MAC_ADDR_PTR 0x28
11afc1b1 1569#define IXGBE_PCIE_MSIX_82599_CAPS 0x72
eb7f139c
PWJ		 1570#define IXGBE_PCIE_MSIX_82598_CAPS 0x62
1571
1572/* MSI-X capability fields masks */
1573#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
9a799d71 1574
c44ade9e
JB		 1575/* Legacy EEPROM word offsets */
1576#define IXGBE_ISCSI_BOOT_CAPS 0x0033
1577#define IXGBE_ISCSI_SETUP_PORT_0 0x0030
1578#define IXGBE_ISCSI_SETUP_PORT_1 0x0034
1579
9a799d71
AK		 1580/* EEPROM Commands - SPI */
1581#define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */
1582#define IXGBE_EEPROM_STATUS_RDY_SPI 0x01
1583#define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
1584#define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
1585#define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */
1586#define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */
c44ade9e 1587/* EEPROM reset Write Enable latch */
9a799d71
AK		 1588#define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04
1589#define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */
1590#define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */
1591#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
1592#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
1593#define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
1594
1595/* EEPROM Read Register */
21ce849b
MC		 1596#define IXGBE_EEPROM_RW_REG_DATA 16 /* data offset in EEPROM read reg */
1597#define IXGBE_EEPROM_RW_REG_DONE 2 /* Offset to READ done bit */
1598#define IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */
1599#define IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1600#define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
1601#define IXGBE_NVM_POLL_READ 0 /* Flag for polling for read complete */
9a799d71
AK		 1602
1603#define IXGBE_ETH_LENGTH_OF_ADDRESS 6
1604
1605#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
1606#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1607#endif
1608
21ce849b
MC		 1609#ifndef IXGBE_EERD_EEWR_ATTEMPTS
1610/* Number of 5 microseconds we wait for EERD read and
1611 * EERW write to complete */
1612#define IXGBE_EERD_EEWR_ATTEMPTS 100000
1613#endif
1614
1615#ifndef IXGBE_FLUDONE_ATTEMPTS
1616/* # attempts we wait for flush update to complete */
1617#define IXGBE_FLUDONE_ATTEMPTS 20000
9a799d71
AK		 1618#endif
1619
c9130180
ET		 1620#define IXGBE_PCIE_CTRL2 0x5 /* PCIe Control 2 Offset */
1621#define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */
1622#define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */
1623#define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */
1624
0365e6e4
PW		 1625#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0
1626#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3
04193058 1627#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
eacd73f7 1628#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2
0fa6d832
ET		 1629#define IXGBE_FW_LESM_PARAMETERS_PTR 0x2
1630#define IXGBE_FW_LESM_STATE_1 0x1
1631#define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */
794caeb2
PWJ		 1632#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4
1633#define IXGBE_FW_PATCH_VERSION_4 0x7
04193058 1634
383ff34b
YZ		 1635/* Alternative SAN MAC Address Block */
1636#define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */
1637#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt. SAN MAC capability */
1638#define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */
1639#define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */
1640#define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt. WWNN prefix offset */
1641#define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt. WWPN prefix offset */
1642#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt. SAN MAC exists */
1643#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt. WWN base exists */
1644
9a799d71 1645/* PCI Bus Info */
a4297dc2
ET		 1646#define IXGBE_PCI_DEVICE_STATUS 0xAA
1647#define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020
9a799d71 1648#define IXGBE_PCI_LINK_STATUS 0xB2
202ff1ec 1649#define IXGBE_PCI_DEVICE_CONTROL2 0xC8
9a799d71
AK		 1650#define IXGBE_PCI_LINK_WIDTH 0x3F0
1651#define IXGBE_PCI_LINK_WIDTH_1 0x10
1652#define IXGBE_PCI_LINK_WIDTH_2 0x20
1653#define IXGBE_PCI_LINK_WIDTH_4 0x40
1654#define IXGBE_PCI_LINK_WIDTH_8 0x80
1655#define IXGBE_PCI_LINK_SPEED 0xF
1656#define IXGBE_PCI_LINK_SPEED_2500 0x1
1657#define IXGBE_PCI_LINK_SPEED_5000 0x2
11afc1b1
PW		 1658#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
1659#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
202ff1ec 1660#define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005
9a799d71
AK		 1661
1662/* Number of 100 microseconds we wait for PCI Express master disable */
1663#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
1664
9a799d71
AK		 1665/* Check whether address is multicast. This is little-endian specific check.*/
1666#define IXGBE_IS_MULTICAST(Address) \
c44ade9e 1667 (bool)(((u8 *)(Address))[0] & ((u8)0x01))
9a799d71
AK		 1668
1669/* Check whether an address is broadcast. */
1670#define IXGBE_IS_BROADCAST(Address) \
c44ade9e
JB		 1671 ((((u8 *)(Address))[0] == ((u8)0xff)) && \
1672 (((u8 *)(Address))[1] == ((u8)0xff)))
9a799d71
AK		 1673
1674/* RAH */
1675#define IXGBE_RAH_VIND_MASK 0x003C0000
1676#define IXGBE_RAH_VIND_SHIFT 18
1677#define IXGBE_RAH_AV 0x80000000
c44ade9e 1678#define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF
9a799d71 1679
9a799d71
AK		 1680/* Header split receive */
1681#define IXGBE_RFCTL_ISCSI_DIS 0x00000001
1682#define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E
1683#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
1684#define IXGBE_RFCTL_NFSW_DIS 0x00000040
1685#define IXGBE_RFCTL_NFSR_DIS 0x00000080
1686#define IXGBE_RFCTL_NFS_VER_MASK 0x00000300
1687#define IXGBE_RFCTL_NFS_VER_SHIFT 8
1688#define IXGBE_RFCTL_NFS_VER_2 0
1689#define IXGBE_RFCTL_NFS_VER_3 1
1690#define IXGBE_RFCTL_NFS_VER_4 2
1691#define IXGBE_RFCTL_IPV6_DIS 0x00000400
1692#define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800
1693#define IXGBE_RFCTL_IPFRSP_DIS 0x00004000
1694#define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000
1695#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
1696
1697/* Transmit Config masks */
1698#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */
1699#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */
1700/* Enable short packet padding to 64 bytes */
1701#define IXGBE_TX_PAD_ENABLE 0x00000400
1702#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */
1703/* This allows for 16K packets + 4k for vlan */
1704#define IXGBE_MAX_FRAME_SZ 0x40040000
1705
1706#define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */
c44ade9e 1707#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */
9a799d71
AK		 1708
1709/* Receive Config masks */
1710#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */
1711#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */
1712#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
11afc1b1 1713#define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */
e9f98072
GR		 1714#define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* Only supported on the X540 */
1715#define IXGBE_RXDCTL_RLPML_EN 0x00008000
9a799d71
AK		 1716
1717#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
1718#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
1719#define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */
1720#define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */
1721#define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */
1722#define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
c44ade9e 1723/* Receive Priority Flow Control Enable */
9a799d71
AK		 1724#define IXGBE_FCTRL_RPFCE 0x00004000
1725#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
11afc1b1
PW		 1726#define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */
1727#define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */
1728#define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */
1729#define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */
9a799d71
AK		 1730
1731/* Multiple Receive Queue Control */
1732#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */
11afc1b1
PW		 1733#define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */
1734#define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */
1735#define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */
1736#define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */
1737#define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */
1738#define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */
1739#define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */
1740#define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */
1741#define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */
1742#define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */
9a799d71
AK		 1743#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
1744#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
1745#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000
1746#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
1747#define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000
1748#define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000
1749#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
1750#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
1751#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
1752#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
11afc1b1
PW		 1753#define IXGBE_MRQC_L3L4TXSWEN 0x00008000
1754
1755/* Queue Drop Enable */
1756#define IXGBE_QDE_ENABLE 0x00000001
1757#define IXGBE_QDE_IDX_MASK 0x00007F00
1758#define IXGBE_QDE_IDX_SHIFT 8
9a799d71
AK		 1759
1760#define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
1761#define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
1762#define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */
1763#define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
1764#define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */
1765#define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */
1766#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
1767#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
1768#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */
1769
11afc1b1
PW		 1770#define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000
1771#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
1772#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
1773#define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000
1774#define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000
1775/* Multiple Transmit Queue Command Register */
1776#define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */
1777#define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */
1778#define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */
d988eadb
DS		 1779#define IXGBE_MTQC_32VF 0x8 /* 4 TX Queues per pool w/32VF's */
1780#define IXGBE_MTQC_64VF 0x4 /* 2 TX Queues per pool w/64VF's */
11afc1b1
PW		 1781#define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */
1782
9a799d71
AK		 1783/* Receive Descriptor bit definitions */
1784#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */
1785#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */
11afc1b1 1786#define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */
9a799d71 1787#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
11afc1b1
PW		 1788#define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */
1789#define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004
c44ade9e 1790#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
9a799d71
AK		 1791#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */
1792#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
1793#define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */
1794#define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
1795#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */
1796#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
1797#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
11afc1b1
PW		 1798#define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */
1799#define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */
1800#define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */
1801#define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */
9a799d71
AK		 1802#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
1803#define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */
1804#define IXGBE_RXD_ERR_LE 0x02 /* Length Error */
1805#define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */
1806#define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */
1807#define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */
1808#define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */
1809#define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */
11afc1b1
PW		 1810#define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */
1811#define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */
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YZ		 1812#define IXGBE_RXDADV_ERR_FCEOFE 0x80000000 /* FCoEFe/IPE */
1813#define IXGBE_RXDADV_ERR_FCERR 0x00700000 /* FCERR/FDIRERR */
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PWJ		 1814#define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000 /* FDIR Length error */
1815#define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000 /* FDIR Drop error */
1816#define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000 /* FDIR Collision error */
c44ade9e 1817#define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */
9a799d71
AK		 1818#define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */
1819#define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */
1820#define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */
1821#define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */
1822#define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */
1823#define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */
1824#define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */
1825#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
1826#define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
1827#define IXGBE_RXD_PRI_SHIFT 13
1828#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */
1829#define IXGBE_RXD_CFI_SHIFT 12
1830
11afc1b1
PW		 1831#define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */
1832#define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */
1833#define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */
1834#define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */
1835#define IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */
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YZ		 1836#define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */
1837#define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */
1838#define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */
1839#define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */
1840#define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */
1841#define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */
11afc1b1
PW		 1842
1843/* PSRTYPE bit definitions */
1844#define IXGBE_PSRTYPE_TCPHDR 0x00000010
1845#define IXGBE_PSRTYPE_UDPHDR 0x00000020
1846#define IXGBE_PSRTYPE_IPV4HDR 0x00000100
1847#define IXGBE_PSRTYPE_IPV6HDR 0x00000200
dfa12f05 1848#define IXGBE_PSRTYPE_L2HDR 0x00001000
c44ade9e 1849
9a799d71 1850/* SRRCTL bit definitions */
c44ade9e 1851#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
11afc1b1
PW		 1852#define IXGBE_SRRCTL_RDMTS_SHIFT 22
1853#define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000
1854#define IXGBE_SRRCTL_DROP_EN 0x10000000
c44ade9e
JB		 1855#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
1856#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
1857#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
9a799d71
AK		 1858#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
1859#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
1860#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
1861#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
c44ade9e 1862#define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000
9a799d71
AK		 1863
1864#define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000
1865#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
1866
1867#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F
1868#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0
11afc1b1 1869#define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0
9a799d71
AK		 1870#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
1871#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5
1872#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
1873#define IXGBE_RXDADV_SPH 0x8000
1874
1875/* RSS Hash results */
1876#define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000
1877#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
1878#define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002
1879#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
1880#define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004
1881#define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005
1882#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
1883#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007
1884#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008
1885#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
1886
1887/* RSS Packet Types as indicated in the receive descriptor. */
1888#define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000
1889#define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */
1890#define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */
1891#define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */
1892#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */
1893#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
1894#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
1895#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
1896#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
11afc1b1
PW		 1897#define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */
1898#define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */
1899#define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */
1900#define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */
1901#define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */
1902#define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
1903
1904/* Security Processing bit Indication */
1905#define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000
1906#define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000
1907#define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000
1908#define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000
1909#define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000
1910
9a799d71 1911/* Masks to determine if packets should be dropped due to frame errors */
c44ade9e
JB		 1912#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
1913 IXGBE_RXD_ERR_CE | \
1914 IXGBE_RXD_ERR_LE | \
1915 IXGBE_RXD_ERR_PE | \
1916 IXGBE_RXD_ERR_OSE | \
1917 IXGBE_RXD_ERR_USE)
1918
1919#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
1920 IXGBE_RXDADV_ERR_CE | \
1921 IXGBE_RXDADV_ERR_LE | \
1922 IXGBE_RXDADV_ERR_PE | \
1923 IXGBE_RXDADV_ERR_OSE | \
1924 IXGBE_RXDADV_ERR_USE)
9a799d71
AK		 1925
1926/* Multicast bit mask */
1927#define IXGBE_MCSTCTRL_MFE 0x4
1928
1929/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
1930#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
1931#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8
1932#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024
1933
1934/* Vlan-specific macros */
1935#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */
1936#define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */
1937#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
1938#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
1939
7f870475
GR		 1940/* SR-IOV specific macros */
1941#define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4)
1942#define IXGBE_MBVFICR(_i) (0x00710 + (_i * 4))
1943#define IXGBE_VFLRE(_i) (((_i & 1) ? 0x001C0 : 0x00600))
1944#define IXGBE_VFLREC(_i) (0x00700 + (_i * 4))
1945
11afc1b1
PW		 1946/* Little Endian defines */
1947#ifndef __le32
1948#define __le32 u32
1949#endif
1950#ifndef __le64
1951#define __le64 u64
1952
1953#endif
c44ade9e 1954
bfde493e
PWJ		 1955enum ixgbe_fdir_pballoc_type {
1956 IXGBE_FDIR_PBALLOC_64K = 0,
1957 IXGBE_FDIR_PBALLOC_128K,
1958 IXGBE_FDIR_PBALLOC_256K,
1959};
1960#define IXGBE_FDIR_PBALLOC_SIZE_SHIFT 16
1961
1962/* Flow Director register values */
1963#define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001
1964#define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002
1965#define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003
1966#define IXGBE_FDIRCTRL_INIT_DONE 0x00000008
1967#define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010
1968#define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020
1969#define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080
1970#define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8
1971#define IXGBE_FDIRCTRL_FLEX_SHIFT 16
1972#define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000
1973#define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24
1974#define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000
1975#define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28
1976
1977#define IXGBE_FDIRTCPM_DPORTM_SHIFT 16
1978#define IXGBE_FDIRUDPM_DPORTM_SHIFT 16
1979#define IXGBE_FDIRIP6M_DIPM_SHIFT 16
1980#define IXGBE_FDIRM_VLANID 0x00000001
1981#define IXGBE_FDIRM_VLANP 0x00000002
1982#define IXGBE_FDIRM_POOL 0x00000004
45b9f509
AD		 1983#define IXGBE_FDIRM_L4P 0x00000008
1984#define IXGBE_FDIRM_FLEX 0x00000010
1985#define IXGBE_FDIRM_DIPv6 0x00000020
bfde493e
PWJ		 1986
1987#define IXGBE_FDIRFREE_FREE_MASK 0xFFFF
1988#define IXGBE_FDIRFREE_FREE_SHIFT 0
1989#define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000
1990#define IXGBE_FDIRFREE_COLL_SHIFT 16
1991#define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F
1992#define IXGBE_FDIRLEN_MAXLEN_SHIFT 0
1993#define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000
1994#define IXGBE_FDIRLEN_MAXHASH_SHIFT 16
1995#define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF
1996#define IXGBE_FDIRUSTAT_ADD_SHIFT 0
1997#define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000
1998#define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16
1999#define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF
2000#define IXGBE_FDIRFSTAT_FADD_SHIFT 0
2001#define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00
2002#define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8
2003#define IXGBE_FDIRPORT_DESTINATION_SHIFT 16
2004#define IXGBE_FDIRVLAN_FLEX_SHIFT 16
2005#define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15
2006#define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16
2007
2008#define IXGBE_FDIRCMD_CMD_MASK 0x00000003
2009#define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001
2010#define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002
2011#define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003
2012#define IXGBE_FDIRCMD_CMD_QUERY_REM_HASH 0x00000007
2013#define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008
2014#define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010
2015#define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020
2016#define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040
2017#define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060
2018#define IXGBE_FDIRCMD_IPV6 0x00000080
2019#define IXGBE_FDIRCMD_CLEARHT 0x00000100
2020#define IXGBE_FDIRCMD_DROP 0x00000200
2021#define IXGBE_FDIRCMD_INT 0x00000400
2022#define IXGBE_FDIRCMD_LAST 0x00000800
2023#define IXGBE_FDIRCMD_COLLISION 0x00001000
2024#define IXGBE_FDIRCMD_QUEUE_EN 0x00008000
905e4a41 2025#define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5
bfde493e
PWJ		 2026#define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16
2027#define IXGBE_FDIRCMD_VT_POOL_SHIFT 24
2028#define IXGBE_FDIR_INIT_DONE_POLL 10
2029#define IXGBE_FDIRCMD_CMD_POLL 10
2030
9a799d71
AK		 2031/* Transmit Descriptor - Advanced */
2032union ixgbe_adv_tx_desc {
2033 struct {
c44ade9e 2034 __le64 buffer_addr; /* Address of descriptor's data buf */
8327d000
AV		 2035 __le32 cmd_type_len;
2036 __le32 olinfo_status;
9a799d71
AK		 2037 } read;
2038 struct {
8327d000
AV		 2039 __le64 rsvd; /* Reserved */
2040 __le32 nxtseq_seed;
2041 __le32 status;
9a799d71
AK		 2042 } wb;
2043};
2044
9a799d71
AK		 2045/* Receive Descriptor - Advanced */
2046union ixgbe_adv_rx_desc {
2047 struct {
8327d000
AV		 2048 __le64 pkt_addr; /* Packet buffer address */
2049 __le64 hdr_addr; /* Header buffer address */
9a799d71
AK		 2050 } read;
2051 struct {
2052 struct {
7c6e0a43
JB		 2053 union {
2054 __le32 data;
2055 struct {
c44ade9e
JB		 2056 __le16 pkt_info; /* RSS, Pkt type */
2057 __le16 hdr_info; /* Splithdr, hdrlen */
7c6e0a43 2058 } hs_rss;
9a799d71
AK		 2059 } lo_dword;
2060 union {
8327d000 2061 __le32 rss; /* RSS Hash */
9a799d71 2062 struct {
8327d000 2063 __le16 ip_id; /* IP id */
9da09bb1 2064 __le16 csum; /* Packet Checksum */
9a799d71
AK		 2065 } csum_ip;
2066 } hi_dword;
2067 } lower;
2068 struct {
8327d000
AV		 2069 __le32 status_error; /* ext status/error */
2070 __le16 length; /* Packet length */
2071 __le16 vlan; /* VLAN tag */
9a799d71
AK		 2072 } upper;
2073 } wb; /* writeback */
2074};
2075
2076/* Context descriptors */
2077struct ixgbe_adv_tx_context_desc {
8327d000
AV		 2078 __le32 vlan_macip_lens;
2079 __le32 seqnum_seed;
2080 __le32 type_tucmd_mlhl;
2081 __le32 mss_l4len_idx;
9a799d71
AK		 2082};
2083
2084/* Adv Transmit Descriptor Config Masks */
c44ade9e 2085#define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */
11afc1b1
PW		 2086#define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */
2087#define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */
2088#define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */
9a799d71
AK		 2089#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */
2090#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */
2091#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
2092#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */
2093#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */
9a799d71 2094#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */
c44ade9e 2095#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */
9a799d71
AK		 2096#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
2097#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */
2098#define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
2099#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */
c44ade9e 2100#define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */
9a799d71
AK		 2101#define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */
2102#define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
c44ade9e 2103#define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */
9a799d71
AK		 2104#define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */
2105#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
c44ade9e 2106 IXGBE_ADVTXD_POPTS_SHIFT)
9a799d71 2107#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
c44ade9e
JB		 2108 IXGBE_ADVTXD_POPTS_SHIFT)
2109#define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */
2110#define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
2111#define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
2112#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */
2113#define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */
2114#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
2115#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
2116#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
2117#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
2118#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
2119#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
2120#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
2121#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
2122#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/
11afc1b1
PW		 2123#define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */
2124#define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
2125#define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
bff66176
YZ		 2126#define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */
2127#define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */
2128#define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */
2129#define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */
2130#define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation: End */
2131#define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation: Start */
2132#define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */
2133#define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */
2134#define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */
2135#define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */
c44ade9e
JB		 2136#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
2137#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
2138
2139/* Autonegotiation advertised speeds */
2140typedef u32 ixgbe_autoneg_advertised;
9a799d71 2141/* Link speed */
c44ade9e 2142typedef u32 ixgbe_link_speed;
9a799d71
AK		 2143#define IXGBE_LINK_SPEED_UNKNOWN 0
2144#define IXGBE_LINK_SPEED_100_FULL 0x0008
2145#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
2146#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
c44ade9e
JB		 2147#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
2148 IXGBE_LINK_SPEED_10GB_FULL)
11afc1b1
PW		 2149#define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
2150 IXGBE_LINK_SPEED_1GB_FULL | \
2151 IXGBE_LINK_SPEED_10GB_FULL)
2152
2153#define IXGBE_PCIE_DEV_CTRL_2 0xC8
2154#define PCIE_COMPL_TO_VALUE 0x05
c44ade9e
JB		 2155
2156/* Physical layer type */
2157typedef u32 ixgbe_physical_layer;
2158#define IXGBE_PHYSICAL_LAYER_UNKNOWN 0
2159#define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001
2160#define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002
04193058 2161#define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004
c44ade9e
JB		 2162#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008
2163#define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010
2164#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020
2165#define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040
2166#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080
2167#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100
2168#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
2169#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
04193058 2170#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800
1fcf03e6 2171#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000
ea0a04df 2172#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000
9a799d71 2173
16b61beb
JF		 2174/* Flow Control Macros */
2175#define PAUSE_RTT 8
2176#define PAUSE_MTU(MTU) ((MTU + 1024 - 1) / 1024)
2177
2178#define FC_HIGH_WATER(MTU) ((((PAUSE_RTT + PAUSE_MTU(MTU)) * 144) + 99) / 100 +\
2179 PAUSE_MTU(MTU))
2180#define FC_LOW_WATER(MTU) (2 * (2 * PAUSE_MTU(MTU) + PAUSE_RTT))
2181
bfde493e 2182/* Software ATR hash keys */
905e4a41
AD		 2183#define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2
2184#define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614
bfde493e 2185
905e4a41
AD		 2186/* Software ATR input stream values and masks */
2187#define IXGBE_ATR_HASH_MASK 0x7fff
bfde493e 2188#define IXGBE_ATR_L4TYPE_MASK 0x3
bfde493e
PWJ		 2189#define IXGBE_ATR_L4TYPE_UDP 0x1
2190#define IXGBE_ATR_L4TYPE_TCP 0x2
2191#define IXGBE_ATR_L4TYPE_SCTP 0x3
905e4a41
AD		 2192#define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
2193enum ixgbe_atr_flow_type {
2194 IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0,
2195 IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1,
2196 IXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2,
2197 IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3,
2198 IXGBE_ATR_FLOW_TYPE_IPV6 = 0x4,
2199 IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5,
2200 IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6,
2201 IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
2202};
bfde493e
PWJ		 2203
2204/* Flow Director ATR input struct. */
905e4a41
AD		 2205union ixgbe_atr_input {
2206 /*
2207 * Byte layout in order, all values with MSB first:
bfde493e 2208 *
905e4a41
AD		 2209 * vm_pool - 1 byte
2210 * flow_type - 1 byte
bfde493e
PWJ		 2211 * vlan_id - 2 bytes
2212 * src_ip - 16 bytes
2213 * dst_ip - 16 bytes
2214 * src_port - 2 bytes
2215 * dst_port - 2 bytes
2216 * flex_bytes - 2 bytes
905e4a41 2217 * rsvd0 - 2 bytes - space reserved must be 0.
bfde493e 2218 */
905e4a41
AD		 2219 struct {
2220 u8 vm_pool;
2221 u8 flow_type;
2222 __be16 vlan_id;
2223 __be32 dst_ip[4];
2224 __be32 src_ip[4];
2225 __be16 src_port;
2226 __be16 dst_port;
2227 __be16 flex_bytes;
2228 __be16 rsvd0;
2229 } formatted;
2230 __be32 dword_stream[11];
bfde493e
PWJ		 2231};
2232
69830529
AD		 2233/* Flow Director compressed ATR hash input struct */
2234union ixgbe_atr_hash_dword {
2235 struct {
2236 u8 vm_pool;
2237 u8 flow_type;
2238 __be16 vlan_id;
2239 } formatted;
2240 __be32 ip;
2241 struct {
2242 __be16 src;
2243 __be16 dst;
2244 } port;
2245 __be16 flex_bytes;
2246 __be32 dword;
2247};
2248
9a713e7c 2249struct ixgbe_atr_input_masks {
45b9f509
AD		 2250 __be16 rsvd0;
2251 __be16 vlan_id_mask;
2252 __be32 dst_ip_mask[4];
2253 __be32 src_ip_mask[4];
905e4a41
AD		 2254 __be16 src_port_mask;
2255 __be16 dst_port_mask;
45b9f509 2256 __be16 flex_mask;
9a713e7c
PW		 2257};
2258
9a799d71
AK		 2259enum ixgbe_eeprom_type {
2260 ixgbe_eeprom_uninitialized = 0,
2261 ixgbe_eeprom_spi,
fe15e8e1 2262 ixgbe_flash,
9a799d71
AK		 2263 ixgbe_eeprom_none /* No NVM support */
2264};
2265
2266enum ixgbe_mac_type {
2267 ixgbe_mac_unknown = 0,
2268 ixgbe_mac_82598EB,
11afc1b1 2269 ixgbe_mac_82599EB,
fe15e8e1 2270 ixgbe_mac_X540,
9a799d71
AK		 2271 ixgbe_num_macs
2272};
2273
2274enum ixgbe_phy_type {
2275 ixgbe_phy_unknown = 0,
21cc5b4f 2276 ixgbe_phy_none,
0befdb3e 2277 ixgbe_phy_tn,
fe15e8e1 2278 ixgbe_phy_aq,
11afc1b1 2279 ixgbe_phy_cu_unknown,
9a799d71 2280 ixgbe_phy_qt,
c44ade9e 2281 ixgbe_phy_xaui,
c4900be0 2282 ixgbe_phy_nl,
ea0a04df
DS		 2283 ixgbe_phy_sfp_passive_tyco,
2284 ixgbe_phy_sfp_passive_unknown,
2285 ixgbe_phy_sfp_active_unknown,
c44ade9e
JB		 2286 ixgbe_phy_sfp_avago,
2287 ixgbe_phy_sfp_ftl,
ea0a04df 2288 ixgbe_phy_sfp_ftl_active,
c44ade9e 2289 ixgbe_phy_sfp_unknown,
11afc1b1 2290 ixgbe_phy_sfp_intel,
fa466e91 2291 ixgbe_phy_sfp_unsupported,
c44ade9e
JB		 2292 ixgbe_phy_generic
2293};
2294
2295/*
2296 * SFP+ module type IDs:
2297 *
11afc1b1 2298 * ID Module Type
c44ade9e 2299 * =============
11afc1b1
PW		 2300 * 0 SFP_DA_CU
2301 * 1 SFP_SR
2302 * 2 SFP_LR
2303 * 3 SFP_DA_CU_CORE0 - 82599-specific
2304 * 4 SFP_DA_CU_CORE1 - 82599-specific
2305 * 5 SFP_SR/LR_CORE0 - 82599-specific
2306 * 6 SFP_SR/LR_CORE1 - 82599-specific
c44ade9e
JB		 2307 */
2308enum ixgbe_sfp_type {
2309 ixgbe_sfp_type_da_cu = 0,
2310 ixgbe_sfp_type_sr = 1,
2311 ixgbe_sfp_type_lr = 2,
11afc1b1
PW		 2312 ixgbe_sfp_type_da_cu_core0 = 3,
2313 ixgbe_sfp_type_da_cu_core1 = 4,
2314 ixgbe_sfp_type_srlr_core0 = 5,
2315 ixgbe_sfp_type_srlr_core1 = 6,
ea0a04df
DS		 2316 ixgbe_sfp_type_da_act_lmt_core0 = 7,
2317 ixgbe_sfp_type_da_act_lmt_core1 = 8,
cb836a97
DS		 2318 ixgbe_sfp_type_1g_cu_core0 = 9,
2319 ixgbe_sfp_type_1g_cu_core1 = 10,
c4900be0 2320 ixgbe_sfp_type_not_present = 0xFFFE,
c44ade9e 2321 ixgbe_sfp_type_unknown = 0xFFFF
9a799d71
AK		 2322};
2323
2324enum ixgbe_media_type {
2325 ixgbe_media_type_unknown = 0,
2326 ixgbe_media_type_fiber,
2327 ixgbe_media_type_copper,
c44ade9e 2328 ixgbe_media_type_backplane,
6b1be199 2329 ixgbe_media_type_cx4,
c44ade9e 2330 ixgbe_media_type_virtual
9a799d71
AK		 2331};
2332
2333/* Flow Control Settings */
0ecc061d 2334enum ixgbe_fc_mode {
9a799d71
AK		 2335 ixgbe_fc_none = 0,
2336 ixgbe_fc_rx_pause,
2337 ixgbe_fc_tx_pause,
2338 ixgbe_fc_full,
bb3daa4a
PW		 2339#ifdef CONFIG_DCB
2340 ixgbe_fc_pfc,
2341#endif
9a799d71
AK		 2342 ixgbe_fc_default
2343};
2344
cd7e1f0b
DS		 2345/* Smart Speed Settings */
2346#define IXGBE_SMARTSPEED_MAX_RETRIES 3
2347enum ixgbe_smart_speed {
2348 ixgbe_smart_speed_auto = 0,
2349 ixgbe_smart_speed_on,
2350 ixgbe_smart_speed_off
2351};
2352
11afc1b1
PW		 2353/* PCI bus types */
2354enum ixgbe_bus_type {
2355 ixgbe_bus_type_unknown = 0,
2356 ixgbe_bus_type_pci,
2357 ixgbe_bus_type_pcix,
2358 ixgbe_bus_type_pci_express,
2359 ixgbe_bus_type_reserved
2360};
2361
2362/* PCI bus speeds */
2363enum ixgbe_bus_speed {
2364 ixgbe_bus_speed_unknown = 0,
26d6899b
ET		 2365 ixgbe_bus_speed_33 = 33,
2366 ixgbe_bus_speed_66 = 66,
2367 ixgbe_bus_speed_100 = 100,
2368 ixgbe_bus_speed_120 = 120,
2369 ixgbe_bus_speed_133 = 133,
2370 ixgbe_bus_speed_2500 = 2500,
2371 ixgbe_bus_speed_5000 = 5000,
11afc1b1
PW		 2372 ixgbe_bus_speed_reserved
2373};
2374
2375/* PCI bus widths */
2376enum ixgbe_bus_width {
2377 ixgbe_bus_width_unknown = 0,
26d6899b
ET		 2378 ixgbe_bus_width_pcie_x1 = 1,
2379 ixgbe_bus_width_pcie_x2 = 2,
11afc1b1
PW		 2380 ixgbe_bus_width_pcie_x4 = 4,
2381 ixgbe_bus_width_pcie_x8 = 8,
26d6899b
ET		 2382 ixgbe_bus_width_32 = 32,
2383 ixgbe_bus_width_64 = 64,
11afc1b1
PW		 2384 ixgbe_bus_width_reserved
2385};
2386
9a799d71
AK		 2387struct ixgbe_addr_filter_info {
2388 u32 num_mc_addrs;
2389 u32 rar_used_count;
9a799d71 2390 u32 mta_in_use;
2c5645cf 2391 u32 overflow_promisc;
e433ea1f 2392 bool uc_set_promisc;
2c5645cf 2393 bool user_set_promisc;
9a799d71
AK		 2394};
2395
11afc1b1
PW		 2396/* Bus parameters */
2397struct ixgbe_bus_info {
2398 enum ixgbe_bus_speed speed;
2399 enum ixgbe_bus_width width;
2400 enum ixgbe_bus_type type;
2401
2402 u16 func;
2403 u16 lan_id;
2404};
2405
9a799d71
AK		 2406/* Flow control parameters */
2407struct ixgbe_fc_info {
2408 u32 high_water; /* Flow Control High-water */
2409 u32 low_water; /* Flow Control Low-water */
2410 u16 pause_time; /* Flow Control Pause timer */
2411 bool send_xon; /* Flow control send XON */
2412 bool strict_ieee; /* Strict IEEE mode */
620fa036
MC		 2413 bool disable_fc_autoneg; /* Do not autonegotiate FC */
2414 bool fc_was_autonegged; /* Is current_mode the result of autonegging? */
0ecc061d
PWJ		 2415 enum ixgbe_fc_mode current_mode; /* FC mode in effect */
2416 enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */
9a799d71
AK		 2417};
2418
2419/* Statistics counters collected by the MAC */
2420struct ixgbe_hw_stats {
2421 u64 crcerrs;
2422 u64 illerrc;
2423 u64 errbc;
2424 u64 mspdc;
2425 u64 mpctotal;
2426 u64 mpc[8];
2427 u64 mlfc;
2428 u64 mrfc;
2429 u64 rlec;
2430 u64 lxontxc;
2431 u64 lxonrxc;
2432 u64 lxofftxc;
2433 u64 lxoffrxc;
2434 u64 pxontxc[8];
2435 u64 pxonrxc[8];
2436 u64 pxofftxc[8];
2437 u64 pxoffrxc[8];
2438 u64 prc64;
2439 u64 prc127;
2440 u64 prc255;
2441 u64 prc511;
2442 u64 prc1023;
2443 u64 prc1522;
2444 u64 gprc;
2445 u64 bprc;
2446 u64 mprc;
2447 u64 gptc;
2448 u64 gorc;
2449 u64 gotc;
2450 u64 rnbc[8];
2451 u64 ruc;
2452 u64 rfc;
2453 u64 roc;
2454 u64 rjc;
2455 u64 mngprc;
2456 u64 mngpdc;
2457 u64 mngptc;
2458 u64 tor;
2459 u64 tpr;
2460 u64 tpt;
2461 u64 ptc64;
2462 u64 ptc127;
2463 u64 ptc255;
2464 u64 ptc511;
2465 u64 ptc1023;
2466 u64 ptc1522;
2467 u64 mptc;
2468 u64 bptc;
2469 u64 xec;
2470 u64 rqsmr[16];
2471 u64 tqsmr[8];
2472 u64 qprc[16];
2473 u64 qptc[16];
2474 u64 qbrc[16];
2475 u64 qbtc[16];
11afc1b1
PW		 2476 u64 qprdc[16];
2477 u64 pxon2offc[8];
2478 u64 fdirustat_add;
2479 u64 fdirustat_remove;
2480 u64 fdirfstat_fadd;
2481 u64 fdirfstat_fremove;
2482 u64 fdirmatch;
2483 u64 fdirmiss;
6d45522c
YZ		 2484 u64 fccrc;
2485 u64 fcoerpdc;
2486 u64 fcoeprc;
2487 u64 fcoeptc;
2488 u64 fcoedwrc;
2489 u64 fcoedwtc;
9a799d71
AK		 2490};
2491
2492/* forward declaration */
2493struct ixgbe_hw;
2494
2c5645cf
CL		 2495/* iterator type for walking multicast address lists */
2496typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
2497 u32 *vmdq);
2498
c44ade9e
JB		 2499/* Function pointer table */
2500struct ixgbe_eeprom_operations {
2501 s32 (*init_params)(struct ixgbe_hw *);
2502 s32 (*read)(struct ixgbe_hw *, u16, u16 *);
2503 s32 (*write)(struct ixgbe_hw *, u16, u16);
2504 s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
2505 s32 (*update_checksum)(struct ixgbe_hw *);
a391f1d5 2506 u16 (*calc_checksum)(struct ixgbe_hw *);
c44ade9e
JB		 2507};
2508
9a799d71 2509struct ixgbe_mac_operations {
c44ade9e
JB		 2510 s32 (*init_hw)(struct ixgbe_hw *);
2511 s32 (*reset_hw)(struct ixgbe_hw *);
2512 s32 (*start_hw)(struct ixgbe_hw *);
2513 s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
9a799d71 2514 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
11afc1b1 2515 u32 (*get_supported_physical_layer)(struct ixgbe_hw *);
c44ade9e 2516 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
0365e6e4 2517 s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);
04193058 2518 s32 (*get_device_caps)(struct ixgbe_hw *, u16 *);
383ff34b 2519 s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *);
c44ade9e
JB		 2520 s32 (*stop_adapter)(struct ixgbe_hw *);
2521 s32 (*get_bus_info)(struct ixgbe_hw *);
11afc1b1 2522 void (*set_lan_id)(struct ixgbe_hw *);
c44ade9e
JB		 2523 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
2524 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
11afc1b1
PW		 2525 s32 (*setup_sfp)(struct ixgbe_hw *);
2526 s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
5e655105
DS		 2527 s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16);
2528 void (*release_swfw_sync)(struct ixgbe_hw *, u16);
c44ade9e
JB		 2529
2530 /* Link */
61fac744
PW		 2531 void (*disable_tx_laser)(struct ixgbe_hw *);
2532 void (*enable_tx_laser)(struct ixgbe_hw *);
1097cd17 2533 void (*flap_tx_laser)(struct ixgbe_hw *);
8620a103 2534 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool, bool);
c44ade9e
JB		 2535 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
2536 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
2537 bool *);
2538
2539 /* LED */
2540 s32 (*led_on)(struct ixgbe_hw *, u32);
2541 s32 (*led_off)(struct ixgbe_hw *, u32);
2542 s32 (*blink_led_start)(struct ixgbe_hw *, u32);
2543 s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
2544
2545 /* RAR, Multicast, VLAN */
2546 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
2547 s32 (*clear_rar)(struct ixgbe_hw *, u32);
2548 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
2549 s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
2550 s32 (*init_rx_addrs)(struct ixgbe_hw *);
2853eb89 2551 s32 (*update_mc_addr_list)(struct ixgbe_hw *, struct net_device *);
c44ade9e
JB		 2552 s32 (*enable_mc)(struct ixgbe_hw *);
2553 s32 (*disable_mc)(struct ixgbe_hw *);
2554 s32 (*clear_vfta)(struct ixgbe_hw *);
2555 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
2556 s32 (*init_uta_tables)(struct ixgbe_hw *);
a985b6c3
GR		 2557 void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
2558 void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
c44ade9e
JB		 2559
2560 /* Flow Control */
620fa036 2561 s32 (*fc_enable)(struct ixgbe_hw *, s32);
9a799d71
AK		 2562};
2563
2564struct ixgbe_phy_operations {
c44ade9e
JB		 2565 s32 (*identify)(struct ixgbe_hw *);
2566 s32 (*identify_sfp)(struct ixgbe_hw *);
04f165ef 2567 s32 (*init)(struct ixgbe_hw *);
c44ade9e
JB		 2568 s32 (*reset)(struct ixgbe_hw *);
2569 s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
2570 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
3957d63d 2571 s32 (*setup_link)(struct ixgbe_hw *);
c44ade9e
JB		 2572 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
2573 bool);
0befdb3e
JB		 2574 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
2575 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
c44ade9e
JB		 2576 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
2577 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
2578 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
2579 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
119fc60a 2580 s32 (*check_overtemp)(struct ixgbe_hw *);
9a799d71
AK		 2581};
2582
9a799d71 2583struct ixgbe_eeprom_info {
c44ade9e
JB		 2584 struct ixgbe_eeprom_operations ops;
2585 enum ixgbe_eeprom_type type;
11afc1b1 2586 u32 semaphore_delay;
c44ade9e
JB		 2587 u16 word_size;
2588 u16 address_bits;
9a799d71
AK		 2589};
2590
a4297dc2 2591#define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01
c44ade9e
JB		 2592struct ixgbe_mac_info {
2593 struct ixgbe_mac_operations ops;
2594 enum ixgbe_mac_type type;
2595 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
2596 u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
0365e6e4 2597 u8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
383ff34b
YZ		 2598 /* prefix for World Wide Node Name (WWNN) */
2599 u16 wwnn_prefix;
2600 /* prefix for World Wide Port Name (WWPN) */
2601 u16 wwpn_prefix;
80960ab0
ET		 2602#define IXGBE_MAX_MTA 128
2603 u32 mta_shadow[IXGBE_MAX_MTA];
c44ade9e
JB		 2604 s32 mc_filter_type;
2605 u32 mcft_size;
2606 u32 vft_size;
2607 u32 num_rar_entries;
21ce849b 2608 u32 rar_highwater;
e09ad236 2609 u32 rx_pb_size;
c44ade9e
JB		 2610 u32 max_tx_queues;
2611 u32 max_rx_queues;
eb7f139c 2612 u32 max_msix_vectors;
3201d313
PWJ		 2613 u32 orig_autoc;
2614 u32 orig_autoc2;
2615 bool orig_link_settings_stored;
50ac58ba 2616 bool autotry_restart;
a4297dc2 2617 u8 flags;
9a799d71
AK		 2618};
2619
c44ade9e
JB		 2620struct ixgbe_phy_info {
2621 struct ixgbe_phy_operations ops;
6b73e10d 2622 struct mdio_if_info mdio;
c44ade9e 2623 enum ixgbe_phy_type type;
c44ade9e
JB		 2624 u32 id;
2625 enum ixgbe_sfp_type sfp_type;
553b4497 2626 bool sfp_setup_needed;
c44ade9e
JB		 2627 u32 revision;
2628 enum ixgbe_media_type media_type;
2629 bool reset_disable;
2630 ixgbe_autoneg_advertised autoneg_advertised;
cd7e1f0b
DS		 2631 enum ixgbe_smart_speed smart_speed;
2632 bool smart_speed_active;
0ecc061d 2633 bool multispeed_fiber;
119fc60a 2634 bool reset_if_overtemp;
9a799d71
AK		 2635};
2636
7f870475
GR		 2637#include "ixgbe_mbx.h"
2638
2639struct ixgbe_mbx_operations {
2640 s32 (*init_params)(struct ixgbe_hw *hw);
2641 s32 (*read)(struct ixgbe_hw *, u32 *, u16, u16);
2642 s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16);
2643 s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16);
2644 s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16);
2645 s32 (*check_for_msg)(struct ixgbe_hw *, u16);
2646 s32 (*check_for_ack)(struct ixgbe_hw *, u16);
2647 s32 (*check_for_rst)(struct ixgbe_hw *, u16);
2648};
2649
2650struct ixgbe_mbx_stats {
2651 u32 msgs_tx;
2652 u32 msgs_rx;
2653
2654 u32 acks;
2655 u32 reqs;
2656 u32 rsts;
2657};
2658
2659struct ixgbe_mbx_info {
2660 struct ixgbe_mbx_operations ops;
2661 struct ixgbe_mbx_stats stats;
2662 u32 timeout;
2663 u32 usec_delay;
2664 u32 v2p_mailbox;
2665 u16 size;
2666};
2667
9a799d71
AK		 2668struct ixgbe_hw {
2669 u8 __iomem *hw_addr;
2670 void *back;
2671 struct ixgbe_mac_info mac;
2672 struct ixgbe_addr_filter_info addr_ctrl;
2673 struct ixgbe_fc_info fc;
2674 struct ixgbe_phy_info phy;
2675 struct ixgbe_eeprom_info eeprom;
11afc1b1 2676 struct ixgbe_bus_info bus;
7f870475 2677 struct ixgbe_mbx_info mbx;
9a799d71
AK		 2678 u16 device_id;
2679 u16 vendor_id;
2680 u16 subsystem_device_id;
2681 u16 subsystem_vendor_id;
2682 u8 revision_id;
2683 bool adapter_stopped;
fe15e8e1 2684 bool force_full_reset;
9a799d71
AK		 2685};
2686
c44ade9e
JB		 2687struct ixgbe_info {
2688 enum ixgbe_mac_type mac;
2689 s32 (*get_invariants)(struct ixgbe_hw *);
2690 struct ixgbe_mac_operations *mac_ops;
2691 struct ixgbe_eeprom_operations *eeprom_ops;
2692 struct ixgbe_phy_operations *phy_ops;
7f870475 2693 struct ixgbe_mbx_operations *mbx_ops;
c44ade9e
JB		 2694};
2695
2696
9a799d71
AK		 2697/* Error Codes */
2698#define IXGBE_ERR_EEPROM -1
2699#define IXGBE_ERR_EEPROM_CHECKSUM -2
2700#define IXGBE_ERR_PHY -3
2701#define IXGBE_ERR_CONFIG -4
2702#define IXGBE_ERR_PARAM -5
2703#define IXGBE_ERR_MAC_TYPE -6
2704#define IXGBE_ERR_UNKNOWN_PHY -7
2705#define IXGBE_ERR_LINK_SETUP -8
2706#define IXGBE_ERR_ADAPTER_STOPPED -9
2707#define IXGBE_ERR_INVALID_MAC_ADDR -10
2708#define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11
2709#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12
2710#define IXGBE_ERR_INVALID_LINK_SETTINGS -13
2711#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14
2712#define IXGBE_ERR_RESET_FAILED -15
2713#define IXGBE_ERR_SWFW_SYNC -16
2714#define IXGBE_ERR_PHY_ADDR_INVALID -17
c44ade9e
JB		 2715#define IXGBE_ERR_I2C -18
2716#define IXGBE_ERR_SFP_NOT_SUPPORTED -19
c4900be0 2717#define IXGBE_ERR_SFP_NOT_PRESENT -20
11afc1b1 2718#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21
21ce849b 2719#define IXGBE_ERR_NO_SAN_ADDR_PTR -22
bfde493e 2720#define IXGBE_ERR_FDIR_REINIT_FAILED -23
794caeb2 2721#define IXGBE_ERR_EEPROM_VERSION -24
21ce849b 2722#define IXGBE_ERR_NO_SPACE -25
119fc60a 2723#define IXGBE_ERR_OVERTEMP -26
0b0c2b31
ET		 2724#define IXGBE_ERR_FC_NOT_NEGOTIATED -27
2725#define IXGBE_ERR_FC_NOT_SUPPORTED -28
2726#define IXGBE_ERR_FLOW_CONTROL -29
a7f5a5fc 2727#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30
289700db
DS		 2728#define IXGBE_ERR_PBA_SECTION -31
2729#define IXGBE_ERR_INVALID_ARGUMENT -32
9a799d71
AK		 2730#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
2731
2732#endif /* _IXGBE_TYPE_H_ */
kernel source for telekom puls (alcatel/mediatek)