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net: convert unicast addr list
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ixgbe / ixgbe_type.h
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_TYPE_H_
29#define _IXGBE_TYPE_H_
30
31#include <linux/types.h>
6b73e10d 32#include <linux/mdio.h>
ccffad25 33#include <linux/list.h>
9a799d71
AK		 34
35/* Vendor ID */
36#define IXGBE_INTEL_VENDOR_ID 0x8086
37
38/* Device IDs */
1e336d0f 39#define IXGBE_DEV_ID_82598 0x10B6
2f21bdd3 40#define IXGBE_DEV_ID_82598_BX 0x1508
9a799d71
AK		 41#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
42#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
c4900be0 43#define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
0befdb3e 44#define IXGBE_DEV_ID_82598AT 0x10C8
9a799d71 45#define IXGBE_DEV_ID_82598EB_CX4 0x10DD
8d792cd9 46#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
c4900be0
DS		 47#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
48#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
b95f5fcb 49#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
11afc1b1
PW		 50#define IXGBE_DEV_ID_82599_KX4 0x10F7
51#define IXGBE_DEV_ID_82599_SFP 0x10FB
1fcf03e6 52#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
9a799d71
AK		 53
54/* General Registers */
55#define IXGBE_CTRL 0x00000
56#define IXGBE_STATUS 0x00008
57#define IXGBE_CTRL_EXT 0x00018
58#define IXGBE_ESDP 0x00020
59#define IXGBE_EODSDP 0x00028
11afc1b1 60#define IXGBE_I2CCTL 0x00028
9a799d71
AK		 61#define IXGBE_LEDCTL 0x00200
62#define IXGBE_FRTIMER 0x00048
63#define IXGBE_TCPTIMER 0x0004C
11afc1b1
PW		 64#define IXGBE_CORESPARE 0x00600
65#define IXGBE_EXVET 0x05078
9a799d71
AK		 66
67/* NVM Registers */
68#define IXGBE_EEC 0x10010
69#define IXGBE_EERD 0x10014
70#define IXGBE_FLA 0x1001C
71#define IXGBE_EEMNGCTL 0x10110
72#define IXGBE_EEMNGDATA 0x10114
73#define IXGBE_FLMNGCTL 0x10118
74#define IXGBE_FLMNGDATA 0x1011C
75#define IXGBE_FLMNGCNT 0x10120
76#define IXGBE_FLOP 0x1013C
77#define IXGBE_GRC 0x10200
78
11afc1b1
PW		 79/* General Receive Control */
80#define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */
81#define IXGBE_GRC_APME 0x00000002 /* Advanced Power Management Enable */
82
83#define IXGBE_VPDDIAG0 0x10204
84#define IXGBE_VPDDIAG1 0x10208
85
86/* I2CCTL Bit Masks */
87#define IXGBE_I2C_CLK_IN 0x00000001
88#define IXGBE_I2C_CLK_OUT 0x00000002
89#define IXGBE_I2C_DATA_IN 0x00000004
90#define IXGBE_I2C_DATA_OUT 0x00000008
91
9a799d71
AK		 92/* Interrupt Registers */
93#define IXGBE_EICR 0x00800
94#define IXGBE_EICS 0x00808
95#define IXGBE_EIMS 0x00880
96#define IXGBE_EIMC 0x00888
97#define IXGBE_EIAC 0x00810
98#define IXGBE_EIAM 0x00890
11afc1b1
PW		 99#define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)
100#define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)
101#define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4)
102#define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4)
509ee935
JB		 103/*
104 * 82598 EITR is 16 bits but set the limits based on the max
105 * supported by all ixgbe hardware. 82599 EITR is only 12 bits,
106 * with the lower 3 always zero.
107 */
108#define IXGBE_MAX_INT_RATE 488281
109#define IXGBE_MIN_INT_RATE 956
110#define IXGBE_MAX_EITR 0x00000FF8
111#define IXGBE_MIN_EITR 8
11afc1b1
PW		 112#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
113 (0x012300 + (((_i) - 24) * 4)))
509ee935 114#define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
11afc1b1
PW		 115#define IXGBE_EITR_LLI_MOD 0x00008000
116#define IXGBE_EITR_CNT_WDIS 0x80000000
c44ade9e 117#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
11afc1b1
PW		 118#define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */
119#define IXGBE_EITRSEL 0x00894
9a799d71
AK		 120#define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */
121#define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */
c44ade9e 122#define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
9a799d71
AK		 123#define IXGBE_GPIE 0x00898
124
125/* Flow Control Registers */
11afc1b1
PW		 126#define IXGBE_FCADBUL 0x03210
127#define IXGBE_FCADBUH 0x03214
128#define IXGBE_FCAMACL 0x04328
129#define IXGBE_FCAMACH 0x0432C
130#define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */
131#define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */
9a799d71
AK		 132#define IXGBE_PFCTOP 0x03008
133#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
134#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
135#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
136#define IXGBE_FCRTV 0x032A0
11afc1b1 137#define IXGBE_FCCFG 0x03D00
9a799d71
AK		 138#define IXGBE_TFCS 0x0CE00
139
140/* Receive DMA Registers */
11afc1b1
PW		 141#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
142 (0x0D000 + ((_i - 64) * 0x40)))
143#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
144 (0x0D004 + ((_i - 64) * 0x40)))
145#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
146 (0x0D008 + ((_i - 64) * 0x40)))
147#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
148 (0x0D010 + ((_i - 64) * 0x40)))
149#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
150 (0x0D018 + ((_i - 64) * 0x40)))
151#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
152 (0x0D028 + ((_i - 64) * 0x40)))
153#define IXGBE_RDDCC 0x02F20
154#define IXGBE_RXMEMWRAP 0x03190
155#define IXGBE_STARCTRL 0x03024
c44ade9e
JB		 156/*
157 * Split and Replication Receive Control Registers
158 * 00-15 : 0x02100 + n*4
159 * 16-64 : 0x01014 + n*0x40
160 * 64-127: 0x0D014 + (n-64)*0x40
161 */
162#define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
163 (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
164 (0x0D014 + ((_i - 64) * 0x40))))
165/*
166 * Rx DCA Control Register:
167 * 00-15 : 0x02200 + n*4
168 * 16-64 : 0x0100C + n*0x40
169 * 64-127: 0x0D00C + (n-64)*0x40
170 */
171#define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
172 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
173 (0x0D00C + ((_i - 64) * 0x40))))
174#define IXGBE_RDRXCTL 0x02F00
9a799d71 175#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
c44ade9e 176 /* 8 of these 0x03C00 - 0x03C1C */
9a799d71
AK		 177#define IXGBE_RXCTRL 0x03000
178#define IXGBE_DROPEN 0x03D04
179#define IXGBE_RXPBSIZE_SHIFT 10
180
181/* Receive Registers */
182#define IXGBE_RXCSUM 0x05000
183#define IXGBE_RFCTL 0x05008
c44ade9e
JB		 184#define IXGBE_DRECCCTL 0x02F08
185#define IXGBE_DRECCCTL_DISABLE 0
186/* Multicast Table Array - 128 entries */
9a799d71 187#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
11afc1b1
PW		 188#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
189 (0x0A200 + ((_i) * 8)))
190#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
191 (0x0A204 + ((_i) * 8)))
192#define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8))
193#define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8))
c44ade9e 194/* Packet split receive type */
11afc1b1
PW		 195#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
196 (0x0EA00 + ((_i) * 4)))
c44ade9e 197/* array of 4096 1-bit vlan filters */
9a799d71 198#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
c44ade9e 199/*array of 4096 4-bit vlan vmdq indices */
9a799d71 200#define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
9a799d71
AK		 201#define IXGBE_FCTRL 0x05080
202#define IXGBE_VLNCTRL 0x05088
203#define IXGBE_MCSTCTRL 0x05090
204#define IXGBE_MRQC 0x05818
11afc1b1
PW		 205#define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */
206#define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */
207#define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */
208#define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
209#define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */
210#define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */
211#define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */
212#define IXGBE_RQTC 0x0EC70
213#define IXGBE_MTQC 0x08120
214#define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */
215#define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */
216#define IXGBE_VT_CTL 0x051B0
217#define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4))
218#define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4))
219#define IXGBE_QDE 0x2F04
220#define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */
221#define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4))
222#define IXGBE_VMRCTL(_i) (0x0F600 + ((_i) * 4))
223#define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4))
224#define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4))
225#define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
226#define IXGBE_LLITHRESH 0x0EC90
9a799d71
AK		 227#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */
228#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */
229#define IXGBE_IMIRVP 0x05AC0
c44ade9e 230#define IXGBE_VMD_CTL 0x0581C
9a799d71
AK		 231#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */
232#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */
233
234/* Transmit DMA registers */
c44ade9e 235#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/
9a799d71
AK		 236#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
237#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
238#define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40))
239#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
240#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
241#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
242#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
243#define IXGBE_DTXCTL 0x07E00
c44ade9e 244
11afc1b1
PW		 245#define IXGBE_DMATXCTL 0x04A80
246#define IXGBE_DTXMXSZRQ 0x08100
247#define IXGBE_DTXTCPFLGL 0x04A88
248#define IXGBE_DTXTCPFLGH 0x04A8C
249#define IXGBE_LBDRPEN 0x0CA00
250#define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
251
252#define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */
253#define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */
254#define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */
255#define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */
c44ade9e 256#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
11afc1b1
PW		 257/* Tx DCA Control register : 128 of these (0-127) */
258#define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40))
9a799d71 259#define IXGBE_TIPG 0x0CB00
c44ade9e 260#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */
9a799d71
AK		 261#define IXGBE_MNGTXMAP 0x0CD10
262#define IXGBE_TIPG_FIBER_DEFAULT 3
263#define IXGBE_TXPBSIZE_SHIFT 10
264
265/* Wake up registers */
266#define IXGBE_WUC 0x05800
267#define IXGBE_WUFC 0x05808
268#define IXGBE_WUS 0x05810
269#define IXGBE_IPAV 0x05838
270#define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */
271#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */
c44ade9e 272
9a799d71
AK		 273#define IXGBE_WUPL 0x05900
274#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
11afc1b1
PW		 275#define IXGBE_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flex host filter table */
276#define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100)) /* Ext Flexible Host
277 * Filter Table */
278
279#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
280#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
281
282/* Each Flexible Filter is at most 128 (0x80) bytes in length */
283#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128
284#define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */
285#define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */
286
287/* Definitions for power management and wakeup registers */
288/* Wake Up Control */
289#define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */
290#define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */
291#define IXGBE_WUC_ADVD3WUC 0x00000010 /* D3Cold wake up cap. enable*/
292
293/* Wake Up Filter Control */
294#define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
295#define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
296#define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
297#define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
298#define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
299#define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
300#define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
301#define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
302#define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */
303
304#define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
305#define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
306#define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
307#define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
308#define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
309#define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
310#define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
311#define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */
312#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */
313#define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all 6 wakeup filters*/
314#define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
315
316/* Wake Up Status */
317#define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC
318#define IXGBE_WUS_MAG IXGBE_WUFC_MAG
319#define IXGBE_WUS_EX IXGBE_WUFC_EX
320#define IXGBE_WUS_MC IXGBE_WUFC_MC
321#define IXGBE_WUS_BC IXGBE_WUFC_BC
322#define IXGBE_WUS_ARP IXGBE_WUFC_ARP
323#define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4
324#define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6
325#define IXGBE_WUS_MNG IXGBE_WUFC_MNG
326#define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0
327#define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1
328#define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2
329#define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3
330#define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4
331#define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5
332#define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS
333
334/* Wake Up Packet Length */
335#define IXGBE_WUPL_LENGTH_MASK 0xFFFF
336
337/* DCB registers */
9a799d71
AK		 338#define IXGBE_RMCS 0x03D00
339#define IXGBE_DPMCS 0x07F40
340#define IXGBE_PDPMCS 0x0CD00
341#define IXGBE_RUPPBMR 0x050A0
342#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
343#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
344#define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
345#define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
346#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
347#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
348
c44ade9e 349
11afc1b1
PW		 350/* Security Control Registers */
351#define IXGBE_SECTXCTRL 0x08800
352#define IXGBE_SECTXSTAT 0x08804
353#define IXGBE_SECTXBUFFAF 0x08808
354#define IXGBE_SECTXMINIFG 0x08810
355#define IXGBE_SECTXSTAT 0x08804
356#define IXGBE_SECRXCTRL 0x08D00
357#define IXGBE_SECRXSTAT 0x08D04
358
359/* Security Bit Fields and Masks */
360#define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001
361#define IXGBE_SECTXCTRL_TX_DIS 0x00000002
362#define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004
363
364#define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001
365#define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002
366
367#define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001
368#define IXGBE_SECRXCTRL_RX_DIS 0x00000002
369
370#define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001
371#define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002
372
373/* LinkSec (MacSec) Registers */
374#define IXGBE_LSECTXCAP 0x08A00
375#define IXGBE_LSECRXCAP 0x08F00
376#define IXGBE_LSECTXCTRL 0x08A04
377#define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */
378#define IXGBE_LSECTXSCH 0x08A0C /* SCI High */
379#define IXGBE_LSECTXSA 0x08A10
380#define IXGBE_LSECTXPN0 0x08A14
381#define IXGBE_LSECTXPN1 0x08A18
382#define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
383#define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
384#define IXGBE_LSECRXCTRL 0x08F04
385#define IXGBE_LSECRXSCL 0x08F08
386#define IXGBE_LSECRXSCH 0x08F0C
387#define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
388#define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
389#define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
390#define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */
391#define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */
392#define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */
393#define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */
394#define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */
395#define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */
396#define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */
397#define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */
398#define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */
399#define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */
400#define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */
401#define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */
402#define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */
403#define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */
404#define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */
405#define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */
406#define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */
407#define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */
408#define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */
409
410/* LinkSec (MacSec) Bit Fields and Masks */
411#define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000
412#define IXGBE_LSECTXCAP_SUM_SHIFT 16
413#define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000
414#define IXGBE_LSECRXCAP_SUM_SHIFT 16
415
416#define IXGBE_LSECTXCTRL_EN_MASK 0x00000003
417#define IXGBE_LSECTXCTRL_DISABLE 0x0
418#define IXGBE_LSECTXCTRL_AUTH 0x1
419#define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2
420#define IXGBE_LSECTXCTRL_AISCI 0x00000020
421#define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
422#define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8
423
424#define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C
425#define IXGBE_LSECRXCTRL_EN_SHIFT 2
426#define IXGBE_LSECRXCTRL_DISABLE 0x0
427#define IXGBE_LSECRXCTRL_CHECK 0x1
428#define IXGBE_LSECRXCTRL_STRICT 0x2
429#define IXGBE_LSECRXCTRL_DROP 0x3
430#define IXGBE_LSECRXCTRL_PLSH 0x00000040
431#define IXGBE_LSECRXCTRL_RP 0x00000080
432#define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33
433
434/* IpSec Registers */
435#define IXGBE_IPSTXIDX 0x08900
436#define IXGBE_IPSTXSALT 0x08904
437#define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
438#define IXGBE_IPSRXIDX 0x08E00
439#define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
440#define IXGBE_IPSRXSPI 0x08E14
441#define IXGBE_IPSRXIPIDX 0x08E18
442#define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
443#define IXGBE_IPSRXSALT 0x08E2C
444#define IXGBE_IPSRXMOD 0x08E30
445
446#define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4
447
f8212f97
AD		 448/* HW RSC registers */
449#define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
450 (0x0D02C + ((_i - 64) * 0x40)))
451#define IXGBE_RSCDBU 0x03028
452#define IXGBE_RSCCTL_RSCEN 0x01
453#define IXGBE_RSCCTL_MAXDESC_1 0x00
454#define IXGBE_RSCCTL_MAXDESC_4 0x04
455#define IXGBE_RSCCTL_MAXDESC_8 0x08
456#define IXGBE_RSCCTL_MAXDESC_16 0x0C
457#define IXGBE_RXDADV_RSCCNT_SHIFT 17
458#define IXGBE_GPIE_RSC_DELAY_SHIFT 11
459#define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000
460#define IXGBE_RSCDBU_RSCACKDIS 0x00000080
461#define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000
462
11afc1b1
PW		 463/* DCB registers */
464#define IXGBE_RTRPCS 0x02430
465#define IXGBE_RTTDCS 0x04900
466#define IXGBE_RTTPCS 0x0CD00
467#define IXGBE_RTRUP2TC 0x03020
468#define IXGBE_RTTUP2TC 0x0C800
469#define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */
470#define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */
471#define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */
472#define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */
473#define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
474#define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
475#define IXGBE_RTTDQSEL 0x04904
476#define IXGBE_RTTDT1C 0x04908
477#define IXGBE_RTTDT1S 0x0490C
478#define IXGBE_RTTDTECC 0x04990
479#define IXGBE_RTTDTECC_NO_BCN 0x00000100
480#define IXGBE_RTTBCNRC 0x04984
c44ade9e 481
bff66176
YZ		 482/* FCoE registers */
483#define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */
484#define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */
485#define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */
486#define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */
487#define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0 */
488#define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4))
489#define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */
490#define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */
491#define IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */
492#define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */
493#define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */
494#define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3
495#define IXGBE_FCBUFF_BUFFCNT_SHIFT 8
496#define IXGBE_FCBUFF_OFFSET_SHIFT 16
497#define IXGBE_FCDMARW_WE (1 << 14) /* Write enable */
498#define IXGBE_FCDMARW_RE (1 << 15) /* Read enable */
499#define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */
500#define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */
501#define IXGBE_FCDMARW_LASTSIZE_SHIFT 16
502
503/* FCoE SOF/EOF */
504#define IXGBE_TEOFF 0x04A94 /* Tx FC EOF */
505#define IXGBE_TSOFF 0x04A98 /* Tx FC SOF */
506#define IXGBE_REOFF 0x05158 /* Rx FC EOF */
507#define IXGBE_RSOFF 0x051F8 /* Rx FC SOF */
508/* FCoE Filter Context Registers */
509#define IXGBE_FCFLT 0x05108 /* FC FLT Context */
510#define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */
511#define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */
512#define IXGBE_FCFLT_VALID (1 << 0) /* Filter Context Valid */
513#define IXGBE_FCFLT_FIRST (1 << 1) /* Filter First */
514#define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */
515#define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */
516#define IXGBE_FCFLTRW_RVALDT (1 << 13) /* Fast Re-Validation */
517#define IXGBE_FCFLTRW_WE (1 << 14) /* Write Enable */
518#define IXGBE_FCFLTRW_RE (1 << 15) /* Read Enable */
519/* FCoE Receive Control */
520#define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */
521#define IXGBE_FCRXCTRL_FCOELLI (1 << 0) /* Low latency interrupt */
522#define IXGBE_FCRXCTRL_SAVBAD (1 << 1) /* Save Bad Frames */
523#define IXGBE_FCRXCTRL_FRSTRDH (1 << 2) /* EN 1st Read Header */
524#define IXGBE_FCRXCTRL_LASTSEQH (1 << 3) /* EN Last Header in Seq */
525#define IXGBE_FCRXCTRL_ALLH (1 << 4) /* EN All Headers */
526#define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */
527#define IXGBE_FCRXCTRL_ICRC (1 << 6) /* Ignore Bad FC CRC */
528#define IXGBE_FCRXCTRL_FCCRCBO (1 << 7) /* FC CRC Byte Ordering */
529#define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */
530#define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8
531/* FCoE Redirection */
532#define IXGBE_FCRECTL 0x0ED00 /* FC Redirection Control */
533#define IXGBE_FCRETA0 0x0ED10 /* FC Redirection Table 0 */
534#define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */
535#define IXGBE_FCRECTL_ENA 0x1 /* FCoE Redir Table Enable */
536#define IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */
537#define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */
538
9a799d71
AK		 539/* Stats registers */
540#define IXGBE_CRCERRS 0x04000
541#define IXGBE_ILLERRC 0x04004
542#define IXGBE_ERRBC 0x04008
543#define IXGBE_MSPDC 0x04010
544#define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
545#define IXGBE_MLFC 0x04034
546#define IXGBE_MRFC 0x04038
547#define IXGBE_RLEC 0x04040
548#define IXGBE_LXONTXC 0x03F60
549#define IXGBE_LXONRXC 0x0CF60
550#define IXGBE_LXOFFTXC 0x03F68
551#define IXGBE_LXOFFRXC 0x0CF68
11afc1b1
PW		 552#define IXGBE_LXONRXCNT 0x041A4
553#define IXGBE_LXOFFRXCNT 0x041A8
554#define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */
555#define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */
556#define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */
9a799d71
AK		 557#define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
558#define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
559#define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
560#define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
561#define IXGBE_PRC64 0x0405C
562#define IXGBE_PRC127 0x04060
563#define IXGBE_PRC255 0x04064
564#define IXGBE_PRC511 0x04068
565#define IXGBE_PRC1023 0x0406C
566#define IXGBE_PRC1522 0x04070
567#define IXGBE_GPRC 0x04074
568#define IXGBE_BPRC 0x04078
569#define IXGBE_MPRC 0x0407C
570#define IXGBE_GPTC 0x04080
571#define IXGBE_GORCL 0x04088
572#define IXGBE_GORCH 0x0408C
573#define IXGBE_GOTCL 0x04090
574#define IXGBE_GOTCH 0x04094
575#define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
576#define IXGBE_RUC 0x040A4
577#define IXGBE_RFC 0x040A8
578#define IXGBE_ROC 0x040AC
579#define IXGBE_RJC 0x040B0
580#define IXGBE_MNGPRC 0x040B4
581#define IXGBE_MNGPDC 0x040B8
582#define IXGBE_MNGPTC 0x0CF90
583#define IXGBE_TORL 0x040C0
584#define IXGBE_TORH 0x040C4
585#define IXGBE_TPR 0x040D0
586#define IXGBE_TPT 0x040D4
587#define IXGBE_PTC64 0x040D8
588#define IXGBE_PTC127 0x040DC
589#define IXGBE_PTC255 0x040E0
590#define IXGBE_PTC511 0x040E4
591#define IXGBE_PTC1023 0x040E8
592#define IXGBE_PTC1522 0x040EC
593#define IXGBE_MPTC 0x040F0
594#define IXGBE_BPTC 0x040F4
595#define IXGBE_XEC 0x04120
11afc1b1 596#define IXGBE_SSVPC 0x08780
9a799d71 597
11afc1b1
PW		 598#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
599#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
600 (0x08600 + ((_i) * 4)))
601#define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4))
9a799d71
AK		 602
603#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
604#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
605#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
606#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
11afc1b1
PW		 607#define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */
608#define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */
609#define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */
bff66176
YZ		 610#define IXGBE_FCCRC 0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */
611#define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */
612#define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */
613#define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */
614#define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */
615#define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */
616#define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */
9a799d71
AK		 617
618/* Management */
619#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
620#define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
621#define IXGBE_MANC 0x05820
622#define IXGBE_MFVAL 0x05824
623#define IXGBE_MANC2H 0x05860
624#define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
625#define IXGBE_MIPAF 0x058B0
626#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
627#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
628#define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */
11afc1b1
PW		 629#define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
630#define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
631#define IXGBE_LSWFW 0x15014
9a799d71
AK		 632
633/* ARC Subsystem registers */
634#define IXGBE_HICR 0x15F00
635#define IXGBE_FWSTS 0x15F0C
636#define IXGBE_HSMC0R 0x15F04
637#define IXGBE_HSMC1R 0x15F08
638#define IXGBE_SWSR 0x15F10
639#define IXGBE_HFDR 0x15FE8
640#define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */
641
642/* PCI-E registers */
643#define IXGBE_GCR 0x11000
644#define IXGBE_GTV 0x11004
645#define IXGBE_FUNCTAG 0x11008
646#define IXGBE_GLT 0x1100C
647#define IXGBE_GSCL_1 0x11010
648#define IXGBE_GSCL_2 0x11014
649#define IXGBE_GSCL_3 0x11018
650#define IXGBE_GSCL_4 0x1101C
651#define IXGBE_GSCN_0 0x11020
652#define IXGBE_GSCN_1 0x11024
653#define IXGBE_GSCN_2 0x11028
654#define IXGBE_GSCN_3 0x1102C
655#define IXGBE_FACTPS 0x10150
656#define IXGBE_PCIEANACTL 0x11040
657#define IXGBE_SWSM 0x10140
658#define IXGBE_FWSM 0x10148
659#define IXGBE_GSSR 0x10160
660#define IXGBE_MREVID 0x11064
661#define IXGBE_DCA_ID 0x11070
662#define IXGBE_DCA_CTRL 0x11074
663
11afc1b1
PW		 664/* PCIe registers 82599-specific */
665#define IXGBE_GCR_EXT 0x11050
666#define IXGBE_GSCL_5_82599 0x11030
667#define IXGBE_GSCL_6_82599 0x11034
668#define IXGBE_GSCL_7_82599 0x11038
669#define IXGBE_GSCL_8_82599 0x1103C
670#define IXGBE_PHYADR_82599 0x11040
671#define IXGBE_PHYDAT_82599 0x11044
672#define IXGBE_PHYCTL_82599 0x11048
673#define IXGBE_PBACLR_82599 0x11068
674#define IXGBE_CIAA_82599 0x11088
675#define IXGBE_CIAD_82599 0x1108C
676#define IXGBE_PCIE_DIAG_0_82599 0x11090
677#define IXGBE_PCIE_DIAG_1_82599 0x11094
678#define IXGBE_PCIE_DIAG_2_82599 0x11098
679#define IXGBE_PCIE_DIAG_3_82599 0x1109C
680#define IXGBE_PCIE_DIAG_4_82599 0x110A0
681#define IXGBE_PCIE_DIAG_5_82599 0x110A4
682#define IXGBE_PCIE_DIAG_6_82599 0x110A8
683#define IXGBE_PCIE_DIAG_7_82599 0x110C0
684#define IXGBE_INTRPT_CSR_82599 0x110B0
685#define IXGBE_INTRPT_MASK_82599 0x110B8
686#define IXGBE_CDQ_MBR_82599 0x110B4
687#define IXGBE_MISC_REG_82599 0x110F0
688#define IXGBE_ECC_CTRL_0_82599 0x11100
689#define IXGBE_ECC_CTRL_1_82599 0x11104
690#define IXGBE_ECC_STATUS_82599 0x110E0
691#define IXGBE_BAR_CTRL_82599 0x110F4
692
693/* Time Sync Registers */
694#define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */
695#define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */
696#define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */
697#define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */
698#define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */
699#define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */
700#define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */
701#define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */
702#define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */
703#define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */
704#define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */
705#define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */
706#define IXGBE_RXUDP 0x08C1C /* Time Sync Rx UDP Port - RW */
707
9a799d71 708/* Diagnostic Registers */
c44ade9e
JB		 709#define IXGBE_RDSTATCTL 0x02C20
710#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
711#define IXGBE_RDHMPN 0x02F08
98c00a1c 712#define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4))
c44ade9e 713#define IXGBE_RDPROBE 0x02F20
11afc1b1
PW		 714#define IXGBE_RDMAM 0x02F30
715#define IXGBE_RDMAD 0x02F34
c44ade9e
JB		 716#define IXGBE_TDSTATCTL 0x07C20
717#define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
718#define IXGBE_TDHMPN 0x07F08
11afc1b1
PW		 719#define IXGBE_TDHMPN2 0x082FC
720#define IXGBE_TXDESCIC 0x082CC
98c00a1c 721#define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4))
11afc1b1 722#define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4))
c44ade9e
JB		 723#define IXGBE_TDPROBE 0x07F20
724#define IXGBE_TXBUFCTRL 0x0C600
9a799d71
AK		 725#define IXGBE_TXBUFDATA0 0x0C610
726#define IXGBE_TXBUFDATA1 0x0C614
727#define IXGBE_TXBUFDATA2 0x0C618
728#define IXGBE_TXBUFDATA3 0x0C61C
729#define IXGBE_RXBUFCTRL 0x03600
730#define IXGBE_RXBUFDATA0 0x03610
731#define IXGBE_RXBUFDATA1 0x03614
732#define IXGBE_RXBUFDATA2 0x03618
733#define IXGBE_RXBUFDATA3 0x0361C
734#define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */
735#define IXGBE_RFVAL 0x050A4
736#define IXGBE_MDFTC1 0x042B8
737#define IXGBE_MDFTC2 0x042C0
738#define IXGBE_MDFTFIFO1 0x042C4
739#define IXGBE_MDFTFIFO2 0x042C8
740#define IXGBE_MDFTS 0x042CC
741#define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
742#define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
743#define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
744#define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
745#define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
746#define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
747#define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
748#define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
749#define IXGBE_PCIEECCCTL 0x1106C
11afc1b1
PW		 750#define IXGBE_PCIEECCCTL0 0x11100
751#define IXGBE_PCIEECCCTL1 0x11104
9a799d71
AK		 752#define IXGBE_PBTXECC 0x0C300
753#define IXGBE_PBRXECC 0x03300
754#define IXGBE_GHECCR 0x110B0
755
756/* MAC Registers */
757#define IXGBE_PCS1GCFIG 0x04200
758#define IXGBE_PCS1GLCTL 0x04208
759#define IXGBE_PCS1GLSTA 0x0420C
760#define IXGBE_PCS1GDBG0 0x04210
761#define IXGBE_PCS1GDBG1 0x04214
762#define IXGBE_PCS1GANA 0x04218
763#define IXGBE_PCS1GANLP 0x0421C
764#define IXGBE_PCS1GANNP 0x04220
765#define IXGBE_PCS1GANLPNP 0x04224
766#define IXGBE_HLREG0 0x04240
767#define IXGBE_HLREG1 0x04244
768#define IXGBE_PAP 0x04248
769#define IXGBE_MACA 0x0424C
770#define IXGBE_APAE 0x04250
771#define IXGBE_ARD 0x04254
772#define IXGBE_AIS 0x04258
773#define IXGBE_MSCA 0x0425C
774#define IXGBE_MSRWD 0x04260
775#define IXGBE_MLADD 0x04264
776#define IXGBE_MHADD 0x04268
11afc1b1 777#define IXGBE_MAXFRS 0x04268
9a799d71
AK		 778#define IXGBE_TREG 0x0426C
779#define IXGBE_PCSS1 0x04288
780#define IXGBE_PCSS2 0x0428C
781#define IXGBE_XPCSS 0x04290
11afc1b1 782#define IXGBE_MFLCN 0x04294
9a799d71
AK		 783#define IXGBE_SERDESC 0x04298
784#define IXGBE_MACS 0x0429C
785#define IXGBE_AUTOC 0x042A0
786#define IXGBE_LINKS 0x042A4
11afc1b1 787#define IXGBE_LINKS2 0x04324
9a799d71
AK		 788#define IXGBE_AUTOC2 0x042A8
789#define IXGBE_AUTOC3 0x042AC
790#define IXGBE_ANLP1 0x042B0
791#define IXGBE_ANLP2 0x042B4
792#define IXGBE_ATLASCTL 0x04800
11afc1b1
PW		 793#define IXGBE_MMNGC 0x042D0
794#define IXGBE_ANLPNP1 0x042D4
795#define IXGBE_ANLPNP2 0x042D8
796#define IXGBE_KRPCSFC 0x042E0
797#define IXGBE_KRPCSS 0x042E4
798#define IXGBE_FECS1 0x042E8
799#define IXGBE_FECS2 0x042EC
800#define IXGBE_SMADARCTL 0x14F10
801#define IXGBE_MPVC 0x04318
802#define IXGBE_SGMIIC 0x04314
803
804/* Omer CORECTL */
805#define IXGBE_CORECTL 0x014F00
806/* BARCTRL */
807#define IXGBE_BARCTRL 0x110F4
808#define IXGBE_BARCTRL_FLSIZE 0x0700
809#define IXGBE_BARCTRL_CSRSIZE 0x2000
9a799d71 810
cc41ac7c
JB		 811/* RDRXCTL Bit Masks */
812#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */
11afc1b1 813#define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */
cc41ac7c
JB		 814#define IXGBE_RDRXCTL_MVMEN 0x00000020
815#define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */
11afc1b1
PW		 816#define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */
817
818/* RQTC Bit Masks and Shifts */
819#define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)
820#define IXGBE_RQTC_TC0_MASK (0x7 << 0)
821#define IXGBE_RQTC_TC1_MASK (0x7 << 4)
822#define IXGBE_RQTC_TC2_MASK (0x7 << 8)
823#define IXGBE_RQTC_TC3_MASK (0x7 << 12)
824#define IXGBE_RQTC_TC4_MASK (0x7 << 16)
825#define IXGBE_RQTC_TC5_MASK (0x7 << 20)
826#define IXGBE_RQTC_TC6_MASK (0x7 << 24)
827#define IXGBE_RQTC_TC7_MASK (0x7 << 28)
828
829/* PSRTYPE.RQPL Bit masks and shift */
830#define IXGBE_PSRTYPE_RQPL_MASK 0x7
831#define IXGBE_PSRTYPE_RQPL_SHIFT 29
9a799d71
AK		 832
833/* CTRL Bit Masks */
834#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */
835#define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */
836#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */
837
838/* FACTPS */
839#define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */
840
841/* MHADD Bit Masks */
842#define IXGBE_MHADD_MFS_MASK 0xFFFF0000
843#define IXGBE_MHADD_MFS_SHIFT 16
844
845/* Extended Device Control */
11afc1b1 846#define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */
9a799d71
AK		 847#define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */
848#define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
849#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
850
851/* Direct Cache Access (DCA) definitions */
852#define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
853#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
854
855#define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
856#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
857
858#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
11afc1b1
PW		 859#define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */
860#define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */
9a799d71
AK		 861#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
862#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
863#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
15005a32
DS		 864#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */
865#define IXGBE_DCA_RXCTRL_DESC_WRO_EN (1 << 13) /* DCA Rx wr Desc Relax Order */
866#define IXGBE_DCA_RXCTRL_DESC_HSRO_EN (1 << 15) /* DCA Rx Split Header RO */
9a799d71
AK		 867
868#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
11afc1b1
PW		 869#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */
870#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */
9a799d71 871#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
c44ade9e 872#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
9a799d71
AK		 873#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */
874
875/* MSCA Bit Masks */
876#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */
877#define IXGBE_MSCA_NP_ADDR_SHIFT 0
878#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */
879#define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */
880#define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */
881#define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/
882#define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */
883#define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */
884#define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */
885#define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */
886#define IXGBE_MSCA_READ 0x08000000 /* OP CODE 10 (read) */
887#define IXGBE_MSCA_READ_AUTOINC 0x0C000000 /* OP CODE 11 (read, auto inc)*/
888#define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */
889#define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */
890#define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */
891#define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old protocol) */
892#define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */
893#define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */
894
895/* MSRWD bit masks */
c44ade9e
JB		 896#define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF
897#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0
898#define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000
899#define IXGBE_MSRWD_READ_DATA_SHIFT 16
9a799d71
AK		 900
901/* Atlas registers */
902#define IXGBE_ATLAS_PDN_LPBK 0x24
903#define IXGBE_ATLAS_PDN_10G 0xB
904#define IXGBE_ATLAS_PDN_1G 0xC
905#define IXGBE_ATLAS_PDN_AN 0xD
906
907/* Atlas bit masks */
908#define IXGBE_ATLASCTL_WRITE_CMD 0x00010000
909#define IXGBE_ATLAS_PDN_TX_REG_EN 0x10
910#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0
911#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
912#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
913
11afc1b1
PW		 914/* Omer bit masks */
915#define IXGBE_CORECTL_WRITE_CMD 0x00010000
c44ade9e 916
6b73e10d 917/* MDIO definitions */
9a799d71 918
c44ade9e
JB		 919#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */
920
9a799d71
AK		 921#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */
922#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */
923#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */
924#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
925#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018
926#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010
927
11afc1b1 928#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
c44ade9e
JB		 929#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
930#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
931
9a799d71
AK		 932#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
933#define IXGBE_MAX_PHY_ADDR 32
934
11afc1b1 935/* PHY IDs*/
0befdb3e
JB		 936#define TN1010_PHY_ID 0x00A19410
937#define TNX_FW_REV 0xB
9a799d71 938#define QT2022_PHY_ID 0x0043A400
c4900be0 939#define ATH_PHY_ID 0x03429050
9a799d71 940
c44ade9e
JB		 941/* PHY Types */
942#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
943
c4900be0
DS		 944/* Special PHY Init Routine */
945#define IXGBE_PHY_INIT_OFFSET_NL 0x002B
946#define IXGBE_PHY_INIT_END_NL 0xFFFF
947#define IXGBE_CONTROL_MASK_NL 0xF000
948#define IXGBE_DATA_MASK_NL 0x0FFF
949#define IXGBE_CONTROL_SHIFT_NL 12
950#define IXGBE_DELAY_NL 0
951#define IXGBE_DATA_NL 1
952#define IXGBE_CONTROL_NL 0x000F
953#define IXGBE_CONTROL_EOL_NL 0x0FFF
954#define IXGBE_CONTROL_SOL_NL 0x0000
955
9a799d71 956/* General purpose Interrupt Enable */
c44ade9e
JB		 957#define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */
958#define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */
11afc1b1 959#define IXGBE_SDP2_GPIEN 0x00000004 /* SDP2 */
c44ade9e
JB		 960#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */
961#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */
962#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */
963#define IXGBE_GPIE_EIAME 0x40000000
964#define IXGBE_GPIE_PBA_SUPPORT 0x80000000
11afc1b1
PW		 965#define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */
966#define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */
967#define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */
968#define IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */
9a799d71
AK		 969
970/* Transmit Flow Control status */
971#define IXGBE_TFCS_TXOFF 0x00000001
972#define IXGBE_TFCS_TXOFF0 0x00000100
973#define IXGBE_TFCS_TXOFF1 0x00000200
974#define IXGBE_TFCS_TXOFF2 0x00000400
975#define IXGBE_TFCS_TXOFF3 0x00000800
976#define IXGBE_TFCS_TXOFF4 0x00001000
977#define IXGBE_TFCS_TXOFF5 0x00002000
978#define IXGBE_TFCS_TXOFF6 0x00004000
979#define IXGBE_TFCS_TXOFF7 0x00008000
980
981/* TCP Timer */
982#define IXGBE_TCPTIMER_KS 0x00000100
983#define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200
984#define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400
985#define IXGBE_TCPTIMER_LOOP 0x00000800
986#define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
987
988/* HLREG0 Bit Masks */
989#define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */
990#define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */
991#define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */
992#define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */
993#define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */
994#define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */
995#define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */
996#define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */
997#define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */
998#define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */
999#define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */
1000#define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */
1001#define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */
1002#define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */
1003#define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */
1004
1005/* VMD_CTL bitmasks */
1006#define IXGBE_VMD_CTL_VMDQ_EN 0x00000001
1007#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
1008
11afc1b1
PW		 1009/* VT_CTL bitmasks */
1010#define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */
1011#define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */
1012#define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */
6e4e87d6
DS		 1013#define IXGBE_VT_CTL_POOL_SHIFT 7
1014#define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT)
11afc1b1
PW		 1015
1016/* VMOLR bitmasks */
1017#define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */
1018#define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */
1019#define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */
1020#define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */
1021#define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */
1022
1023/* VFRE bitmask */
1024#define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF
1025
9a799d71
AK		 1026/* RDHMPN and TDHMPN bitmasks */
1027#define IXGBE_RDHMPN_RDICADDR 0x007FF800
1028#define IXGBE_RDHMPN_RDICRDREQ 0x00800000
1029#define IXGBE_RDHMPN_RDICADDR_SHIFT 11
1030#define IXGBE_TDHMPN_TDICADDR 0x003FF800
1031#define IXGBE_TDHMPN_TDICRDREQ 0x00800000
1032#define IXGBE_TDHMPN_TDICADDR_SHIFT 11
1033
11afc1b1
PW		 1034#define IXGBE_RDMAM_MEM_SEL_SHIFT 13
1035#define IXGBE_RDMAM_DWORD_SHIFT 9
1036#define IXGBE_RDMAM_DESC_COMP_FIFO 1
1037#define IXGBE_RDMAM_DFC_CMD_FIFO 2
1038#define IXGBE_RDMAM_TCN_STATUS_RAM 4
1039#define IXGBE_RDMAM_WB_COLL_FIFO 5
1040#define IXGBE_RDMAM_QSC_CNT_RAM 6
1041#define IXGBE_RDMAM_QSC_QUEUE_CNT 8
1042#define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA
1043#define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135
1044#define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4
1045#define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48
1046#define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7
1047#define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256
1048#define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9
1049#define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8
1050#define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4
1051#define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64
1052#define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4
1053#define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32
1054#define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4
1055#define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128
1056#define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8
1057
1058#define IXGBE_TXDESCIC_READY 0x80000000
1059
9a799d71
AK		 1060/* Receive Checksum Control */
1061#define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
1062#define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
1063
1064/* FCRTL Bit Masks */
11afc1b1
PW		 1065#define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */
1066#define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */
9a799d71
AK		 1067
1068/* PAP bit masks*/
1069#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */
1070
1071/* RMCS Bit Masks */
c44ade9e 1072#define IXGBE_RMCS_RRM 0x00000002 /* Receive Recycle Mode enable */
9a799d71
AK		 1073/* Receive Arbitration Control: 0 Round Robin, 1 DFP */
1074#define IXGBE_RMCS_RAC 0x00000004
1075#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
11afc1b1
PW		 1076#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */
1077#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */
9a799d71
AK		 1078#define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */
1079
11afc1b1
PW		 1080/* FCCFG Bit Masks */
1081#define IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */
1082#define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */
c44ade9e 1083
9a799d71
AK		 1084/* Interrupt register bitmasks */
1085
1086/* Extended Interrupt Cause Read */
1087#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */
11afc1b1
PW		 1088#define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */
1089#define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */
1090#define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */
1091#define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */
9a799d71 1092#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */
11afc1b1 1093#define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */
c44ade9e
JB		 1094#define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */
1095#define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */
1096#define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */
11afc1b1
PW		 1097#define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */
1098#define IXGBE_EICR_ECC 0x10000000 /* ECC Error */
9a799d71
AK		 1099#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */
1100#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */
1101#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
1102#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
1103
1104/* Extended Interrupt Cause Set */
1105#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
11afc1b1
PW		 1106#define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1107#define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */
1108#define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */
1109#define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
c44ade9e
JB		 1110#define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */
1111#define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
1112#define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1113#define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
11afc1b1
PW		 1114#define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1115#define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */
c44ade9e
JB		 1116#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1117#define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */
9a799d71
AK		 1118#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1119#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1120
1121/* Extended Interrupt Mask Set */
1122#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
11afc1b1
PW		 1123#define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1124#define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1125#define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */
1126#define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
9a799d71
AK		 1127#define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */
1128#define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
c44ade9e
JB		 1129#define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1130#define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
11afc1b1
PW		 1131#define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1132#define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */
c44ade9e 1133#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
9a799d71
AK		 1134#define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */
1135#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1136#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1137
1138/* Extended Interrupt Mask Clear */
1139#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
11afc1b1
PW		 1140#define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1141#define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1142#define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */
1143#define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
9a799d71
AK		 1144#define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */
1145#define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
c44ade9e
JB		 1146#define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1147#define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
11afc1b1
PW		 1148#define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1149#define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */
c44ade9e
JB		 1150#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1151#define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */
9a799d71
AK		 1152#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1153#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1154
c44ade9e
JB		 1155#define IXGBE_EIMS_ENABLE_MASK ( \
1156 IXGBE_EIMS_RTX_QUEUE | \
1157 IXGBE_EIMS_LSC | \
1158 IXGBE_EIMS_TCP_TIMER | \
1159 IXGBE_EIMS_OTHER)
9a799d71 1160
c44ade9e 1161/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
9a799d71
AK		 1162#define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */
1163#define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */
1164#define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
1165#define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */
1166#define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */
1167#define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */
1168#define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */
1169#define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */
1170#define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */
1171#define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */
11afc1b1
PW		 1172#define IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */
1173#define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */
1174#define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */
1175#define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */
1176#define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */
1177#define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */
1178#define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */
1179#define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass check of control bits */
1180#define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */
1181#define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */
1182#define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */
1183#define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */
1184#define IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */
1185
1186#define IXGBE_MAX_FTQF_FILTERS 128
1187#define IXGBE_FTQF_PROTOCOL_MASK 0x00000003
1188#define IXGBE_FTQF_PROTOCOL_TCP 0x00000000
1189#define IXGBE_FTQF_PROTOCOL_UDP 0x00000001
1190#define IXGBE_FTQF_PROTOCOL_SCTP 2
1191#define IXGBE_FTQF_PRIORITY_MASK 0x00000007
1192#define IXGBE_FTQF_PRIORITY_SHIFT 2
1193#define IXGBE_FTQF_POOL_MASK 0x0000003F
1194#define IXGBE_FTQF_POOL_SHIFT 8
1195#define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F
1196#define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25
1197#define IXGBE_FTQF_POOL_MASK_EN 0x40000000
1198#define IXGBE_FTQF_QUEUE_ENABLE 0x80000000
9a799d71
AK		 1199
1200/* Interrupt clear mask */
1201#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF
1202
1203/* Interrupt Vector Allocation Registers */
1204#define IXGBE_IVAR_REG_NUM 25
e80e887a 1205#define IXGBE_IVAR_REG_NUM_82599 64
9a799d71
AK		 1206#define IXGBE_IVAR_TXRX_ENTRY 96
1207#define IXGBE_IVAR_RX_ENTRY 64
1208#define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i))
1209#define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i))
1210#define IXGBE_IVAR_TX_ENTRY 32
1211
1212#define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */
1213#define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */
1214
1215#define IXGBE_MSIX_VECTOR(_i) (0 + (_i))
1216
1217#define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
1218
11afc1b1
PW		 1219/* ETYPE Queue Filter/Select Bit Masks */
1220#define IXGBE_MAX_ETQF_FILTERS 8
bff66176 1221#define IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */
11afc1b1
PW		 1222#define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */
1223#define IXGBE_ETQF_1588 0x40000000 /* bit 30 */
1224#define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */
1225#define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */
1226
1227#define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */
1228#define IXGBE_ETQS_RX_QUEUE_SHIFT 16
1229#define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */
1230#define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */
1231
1232/*
1233 * ETQF filter list: one static filter per filter consumer. This is
1234 * to avoid filter collisions later. Add new filters
1235 * here!!
1236 *
1237 * Current filters:
1238 * EAPOL 802.1x (0x888e): Filter 0
1239 * BCN (0x8904): Filter 1
1240 * 1588 (0x88f7): Filter 3
1241 */
1242#define IXGBE_ETQF_FILTER_EAPOL 0
1243#define IXGBE_ETQF_FILTER_BCN 1
bff66176 1244#define IXGBE_ETQF_FILTER_FCOE 2
11afc1b1 1245#define IXGBE_ETQF_FILTER_1588 3
9a799d71
AK		 1246/* VLAN Control Bit Masks */
1247#define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */
1248#define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */
1249#define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */
1250#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */
1251#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */
1252
11afc1b1
PW		 1253/* VLAN pool filtering masks */
1254#define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */
1255#define IXGBE_VLVF_ENTRIES 64
c44ade9e 1256
9a799d71
AK		 1257#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */
1258
1259/* STATUS Bit Masks */
11afc1b1
PW		 1260#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
1261#define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/
1262#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
9a799d71
AK		 1263
1264#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */
1265#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */
1266
1267/* ESDP Bit Masks */
11afc1b1
PW		 1268#define IXGBE_ESDP_SDP0 0x00000001
1269#define IXGBE_ESDP_SDP1 0x00000002
1270#define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
1271#define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
1272#define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
9a799d71 1273#define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */
11afc1b1 1274#define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */
9a799d71
AK		 1275
1276/* LEDCTL Bit Masks */
1277#define IXGBE_LED_IVRT_BASE 0x00000040
1278#define IXGBE_LED_BLINK_BASE 0x00000080
1279#define IXGBE_LED_MODE_MASK_BASE 0x0000000F
1280#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
1281#define IXGBE_LED_MODE_SHIFT(_i) (8*(_i))
1282#define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
1283#define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
1284#define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
1285
1286/* LED modes */
1287#define IXGBE_LED_LINK_UP 0x0
1288#define IXGBE_LED_LINK_10G 0x1
1289#define IXGBE_LED_MAC 0x2
1290#define IXGBE_LED_FILTER 0x3
1291#define IXGBE_LED_LINK_ACTIVE 0x4
1292#define IXGBE_LED_LINK_1G 0x5
1293#define IXGBE_LED_ON 0xE
1294#define IXGBE_LED_OFF 0xF
1295
1296/* AUTOC Bit Masks */
3201d313 1297#define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000
9a799d71
AK		 1298#define IXGBE_AUTOC_KX4_SUPP 0x80000000
1299#define IXGBE_AUTOC_KX_SUPP 0x40000000
1300#define IXGBE_AUTOC_PAUSE 0x30000000
1301#define IXGBE_AUTOC_RF 0x08000000
1302#define IXGBE_AUTOC_PD_TMR 0x06000000
1303#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
1304#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
1305#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
11afc1b1
PW		 1306#define IXGBE_AUTOC_FECA 0x00040000
1307#define IXGBE_AUTOC_FECR 0x00020000
1308#define IXGBE_AUTOC_KR_SUPP 0x00010000
9a799d71
AK		 1309#define IXGBE_AUTOC_AN_RESTART 0x00001000
1310#define IXGBE_AUTOC_FLU 0x00000001
1311#define IXGBE_AUTOC_LMS_SHIFT 13
11afc1b1
PW		 1312#define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT)
1313#define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1314#define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT)
1315#define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1316#define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)
c44ade9e
JB		 1317#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1318#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
1319#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
1320#define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
1321#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1322#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1323#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1324
11afc1b1
PW		 1325#define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200
1326#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
1327#define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180
1328#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
9a799d71
AK		 1329#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1330#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1331#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1332#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1333#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
11afc1b1
PW		 1334#define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1335#define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1336
1337#define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000
1338#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000
1339#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
1340#define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1341#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1342#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
9a799d71
AK		 1343
1344/* LINKS Bit Masks */
1345#define IXGBE_LINKS_KX_AN_COMP 0x80000000
1346#define IXGBE_LINKS_UP 0x40000000
1347#define IXGBE_LINKS_SPEED 0x20000000
1348#define IXGBE_LINKS_MODE 0x18000000
1349#define IXGBE_LINKS_RX_MODE 0x06000000
1350#define IXGBE_LINKS_TX_MODE 0x01800000
1351#define IXGBE_LINKS_XGXS_EN 0x00400000
11afc1b1 1352#define IXGBE_LINKS_SGMII_EN 0x02000000
9a799d71
AK		 1353#define IXGBE_LINKS_PCS_1G_EN 0x00200000
1354#define IXGBE_LINKS_1G_AN_EN 0x00100000
1355#define IXGBE_LINKS_KX_AN_IDLE 0x00080000
1356#define IXGBE_LINKS_1G_SYNC 0x00040000
1357#define IXGBE_LINKS_10G_ALIGN 0x00020000
1358#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
1359#define IXGBE_LINKS_TL_FAULT 0x00001000
1360#define IXGBE_LINKS_SIGNAL 0x00000F00
1361
11afc1b1
PW		 1362#define IXGBE_LINKS_SPEED_82599 0x30000000
1363#define IXGBE_LINKS_SPEED_10G_82599 0x30000000
1364#define IXGBE_LINKS_SPEED_1G_82599 0x20000000
1365#define IXGBE_LINKS_SPEED_100_82599 0x10000000
cf8280ee 1366#define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
9a799d71
AK		 1367#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
1368
0ecc061d
PWJ		 1369#define FIBER_LINK_UP_LIMIT 50
1370
1371/* PCS1GLSTA Bit Masks */
1372#define IXGBE_PCS1GLSTA_LINK_OK 1
1373#define IXGBE_PCS1GLSTA_SYNK_OK 0x10
1374#define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000
1375#define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000
1376#define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000
1377#define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
1378#define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000
1379
1380#define IXGBE_PCS1GANA_SYM_PAUSE 0x80
1381#define IXGBE_PCS1GANA_ASM_PAUSE 0x100
1382
1383/* PCS1GLCTL Bit Masks */
1384#define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */
1385#define IXGBE_PCS1GLCTL_FLV_LINK_UP 1
1386#define IXGBE_PCS1GLCTL_FORCE_LINK 0x20
1387#define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40
1388#define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000
1389#define IXGBE_PCS1GLCTL_AN_RESTART 0x20000
1390
9a799d71
AK		 1391/* SW Semaphore Register bitmasks */
1392#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
1393#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
1394#define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
1395
1396/* GSSR definitions */
1397#define IXGBE_GSSR_EEP_SM 0x0001
1398#define IXGBE_GSSR_PHY0_SM 0x0002
1399#define IXGBE_GSSR_PHY1_SM 0x0004
1400#define IXGBE_GSSR_MAC_CSR_SM 0x0008
1401#define IXGBE_GSSR_FLASH_SM 0x0010
1402
1403/* EEC Register */
1404#define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */
1405#define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */
1406#define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */
1407#define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */
1408#define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */
1409#define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */
1410#define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */
1411#define IXGBE_EEC_FWE_SHIFT 4
1412#define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */
1413#define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */
1414#define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */
1415#define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */
1416/* EEPROM Addressing bits based on type (0-small, 1-large) */
1417#define IXGBE_EEC_ADDR_SIZE 0x00000400
1418#define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */
1419
1420#define IXGBE_EEC_SIZE_SHIFT 11
1421#define IXGBE_EEPROM_WORD_SIZE_SHIFT 6
1422#define IXGBE_EEPROM_OPCODE_BITS 8
1423
1424/* Checksum and EEPROM pointers */
1425#define IXGBE_EEPROM_CHECKSUM 0x3F
1426#define IXGBE_EEPROM_SUM 0xBABA
1427#define IXGBE_PCIE_ANALOG_PTR 0x03
1428#define IXGBE_ATLAS0_CONFIG_PTR 0x04
1429#define IXGBE_ATLAS1_CONFIG_PTR 0x05
1430#define IXGBE_PCIE_GENERAL_PTR 0x06
1431#define IXGBE_PCIE_CONFIG0_PTR 0x07
1432#define IXGBE_PCIE_CONFIG1_PTR 0x08
1433#define IXGBE_CORE0_PTR 0x09
1434#define IXGBE_CORE1_PTR 0x0A
1435#define IXGBE_MAC0_PTR 0x0B
1436#define IXGBE_MAC1_PTR 0x0C
1437#define IXGBE_CSR0_CONFIG_PTR 0x0D
1438#define IXGBE_CSR1_CONFIG_PTR 0x0E
1439#define IXGBE_FW_PTR 0x0F
1440#define IXGBE_PBANUM0_PTR 0x15
1441#define IXGBE_PBANUM1_PTR 0x16
04193058 1442#define IXGBE_DEVICE_CAPS 0x2C
0365e6e4 1443#define IXGBE_SAN_MAC_ADDR_PTR 0x28
11afc1b1 1444#define IXGBE_PCIE_MSIX_82599_CAPS 0x72
eb7f139c
PWJ		 1445#define IXGBE_PCIE_MSIX_82598_CAPS 0x62
1446
1447/* MSI-X capability fields masks */
1448#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
9a799d71 1449
c44ade9e
JB		 1450/* Legacy EEPROM word offsets */
1451#define IXGBE_ISCSI_BOOT_CAPS 0x0033
1452#define IXGBE_ISCSI_SETUP_PORT_0 0x0030
1453#define IXGBE_ISCSI_SETUP_PORT_1 0x0034
1454
9a799d71
AK		 1455/* EEPROM Commands - SPI */
1456#define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */
1457#define IXGBE_EEPROM_STATUS_RDY_SPI 0x01
1458#define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
1459#define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
1460#define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */
1461#define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */
c44ade9e 1462/* EEPROM reset Write Enable latch */
9a799d71
AK		 1463#define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04
1464#define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */
1465#define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */
1466#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
1467#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
1468#define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
1469
1470/* EEPROM Read Register */
1471#define IXGBE_EEPROM_READ_REG_DATA 16 /* data offset in EEPROM read reg */
1472#define IXGBE_EEPROM_READ_REG_DONE 2 /* Offset to READ done bit */
1473#define IXGBE_EEPROM_READ_REG_START 1 /* First bit to start operation */
1474#define IXGBE_EEPROM_READ_ADDR_SHIFT 2 /* Shift to the address bits */
1475
1476#define IXGBE_ETH_LENGTH_OF_ADDRESS 6
1477
1478#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
1479#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1480#endif
1481
1482#ifndef IXGBE_EERD_ATTEMPTS
1483/* Number of 5 microseconds we wait for EERD read to complete */
1484#define IXGBE_EERD_ATTEMPTS 100000
1485#endif
1486
0365e6e4
PW		 1487#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0
1488#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3
04193058 1489#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
eacd73f7 1490#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2
04193058 1491
9a799d71
AK		 1492/* PCI Bus Info */
1493#define IXGBE_PCI_LINK_STATUS 0xB2
1494#define IXGBE_PCI_LINK_WIDTH 0x3F0
1495#define IXGBE_PCI_LINK_WIDTH_1 0x10
1496#define IXGBE_PCI_LINK_WIDTH_2 0x20
1497#define IXGBE_PCI_LINK_WIDTH_4 0x40
1498#define IXGBE_PCI_LINK_WIDTH_8 0x80
1499#define IXGBE_PCI_LINK_SPEED 0xF
1500#define IXGBE_PCI_LINK_SPEED_2500 0x1
1501#define IXGBE_PCI_LINK_SPEED_5000 0x2
11afc1b1
PW		 1502#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
1503#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
9a799d71
AK		 1504
1505/* Number of 100 microseconds we wait for PCI Express master disable */
1506#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
1507
9a799d71
AK		 1508/* Check whether address is multicast. This is little-endian specific check.*/
1509#define IXGBE_IS_MULTICAST(Address) \
c44ade9e 1510 (bool)(((u8 *)(Address))[0] & ((u8)0x01))
9a799d71
AK		 1511
1512/* Check whether an address is broadcast. */
1513#define IXGBE_IS_BROADCAST(Address) \
c44ade9e
JB		 1514 ((((u8 *)(Address))[0] == ((u8)0xff)) && \
1515 (((u8 *)(Address))[1] == ((u8)0xff)))
9a799d71
AK		 1516
1517/* RAH */
1518#define IXGBE_RAH_VIND_MASK 0x003C0000
1519#define IXGBE_RAH_VIND_SHIFT 18
1520#define IXGBE_RAH_AV 0x80000000
c44ade9e 1521#define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF
9a799d71 1522
9a799d71
AK		 1523/* Header split receive */
1524#define IXGBE_RFCTL_ISCSI_DIS 0x00000001
1525#define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E
1526#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
1527#define IXGBE_RFCTL_NFSW_DIS 0x00000040
1528#define IXGBE_RFCTL_NFSR_DIS 0x00000080
1529#define IXGBE_RFCTL_NFS_VER_MASK 0x00000300
1530#define IXGBE_RFCTL_NFS_VER_SHIFT 8
1531#define IXGBE_RFCTL_NFS_VER_2 0
1532#define IXGBE_RFCTL_NFS_VER_3 1
1533#define IXGBE_RFCTL_NFS_VER_4 2
1534#define IXGBE_RFCTL_IPV6_DIS 0x00000400
1535#define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800
1536#define IXGBE_RFCTL_IPFRSP_DIS 0x00004000
1537#define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000
1538#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
1539
1540/* Transmit Config masks */
1541#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */
1542#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */
1543/* Enable short packet padding to 64 bytes */
1544#define IXGBE_TX_PAD_ENABLE 0x00000400
1545#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */
1546/* This allows for 16K packets + 4k for vlan */
1547#define IXGBE_MAX_FRAME_SZ 0x40040000
1548
1549#define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */
c44ade9e 1550#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */
9a799d71
AK		 1551
1552/* Receive Config masks */
1553#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */
1554#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */
1555#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
11afc1b1 1556#define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */
9a799d71
AK		 1557
1558#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
1559#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
1560#define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */
1561#define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */
1562#define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */
1563#define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
c44ade9e 1564/* Receive Priority Flow Control Enable */
9a799d71
AK		 1565#define IXGBE_FCTRL_RPFCE 0x00004000
1566#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
11afc1b1
PW		 1567#define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */
1568#define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */
1569#define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */
1570#define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */
9a799d71
AK		 1571
1572/* Multiple Receive Queue Control */
1573#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */
11afc1b1
PW		 1574#define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */
1575#define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */
1576#define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */
1577#define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */
1578#define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */
1579#define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */
1580#define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */
1581#define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */
1582#define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */
1583#define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */
9a799d71
AK		 1584#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
1585#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
1586#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000
1587#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
1588#define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000
1589#define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000
1590#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
1591#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
1592#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
1593#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
11afc1b1
PW		 1594#define IXGBE_MRQC_L3L4TXSWEN 0x00008000
1595
1596/* Queue Drop Enable */
1597#define IXGBE_QDE_ENABLE 0x00000001
1598#define IXGBE_QDE_IDX_MASK 0x00007F00
1599#define IXGBE_QDE_IDX_SHIFT 8
9a799d71
AK		 1600
1601#define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
1602#define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
1603#define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */
1604#define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
1605#define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */
1606#define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */
1607#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
1608#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
1609#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */
1610
11afc1b1
PW		 1611#define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000
1612#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
1613#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
1614#define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000
1615#define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000
1616/* Multiple Transmit Queue Command Register */
1617#define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */
1618#define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */
1619#define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */
d988eadb
DS		 1620#define IXGBE_MTQC_32VF 0x8 /* 4 TX Queues per pool w/32VF's */
1621#define IXGBE_MTQC_64VF 0x4 /* 2 TX Queues per pool w/64VF's */
11afc1b1
PW		 1622#define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */
1623
9a799d71
AK		 1624/* Receive Descriptor bit definitions */
1625#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */
1626#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */
11afc1b1 1627#define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */
9a799d71 1628#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
11afc1b1
PW		 1629#define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */
1630#define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004
c44ade9e 1631#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
9a799d71
AK		 1632#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */
1633#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
1634#define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */
1635#define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
1636#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */
1637#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
1638#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
11afc1b1
PW		 1639#define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */
1640#define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */
1641#define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */
1642#define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */
9a799d71
AK		 1643#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
1644#define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */
1645#define IXGBE_RXD_ERR_LE 0x02 /* Length Error */
1646#define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */
1647#define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */
1648#define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */
1649#define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */
1650#define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */
11afc1b1
PW		 1651#define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */
1652#define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */
bff66176
YZ		 1653#define IXGBE_RXDADV_ERR_FCEOFE 0x80000000 /* FCoEFe/IPE */
1654#define IXGBE_RXDADV_ERR_FCERR 0x00700000 /* FCERR/FDIRERR */
c44ade9e 1655#define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */
9a799d71
AK		 1656#define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */
1657#define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */
1658#define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */
1659#define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */
1660#define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */
1661#define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */
1662#define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */
1663#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
1664#define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
1665#define IXGBE_RXD_PRI_SHIFT 13
1666#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */
1667#define IXGBE_RXD_CFI_SHIFT 12
1668
11afc1b1
PW		 1669#define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */
1670#define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */
1671#define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */
1672#define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */
1673#define IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */
bff66176
YZ		 1674#define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */
1675#define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */
1676#define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */
1677#define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */
1678#define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */
1679#define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */
11afc1b1
PW		 1680
1681/* PSRTYPE bit definitions */
1682#define IXGBE_PSRTYPE_TCPHDR 0x00000010
1683#define IXGBE_PSRTYPE_UDPHDR 0x00000020
1684#define IXGBE_PSRTYPE_IPV4HDR 0x00000100
1685#define IXGBE_PSRTYPE_IPV6HDR 0x00000200
dfa12f05 1686#define IXGBE_PSRTYPE_L2HDR 0x00001000
c44ade9e 1687
9a799d71 1688/* SRRCTL bit definitions */
c44ade9e 1689#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
11afc1b1
PW		 1690#define IXGBE_SRRCTL_RDMTS_SHIFT 22
1691#define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000
1692#define IXGBE_SRRCTL_DROP_EN 0x10000000
c44ade9e
JB		 1693#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
1694#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
1695#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
9a799d71
AK		 1696#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
1697#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
1698#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
1699#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
c44ade9e 1700#define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000
9a799d71
AK		 1701
1702#define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000
1703#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
1704
1705#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F
1706#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0
11afc1b1 1707#define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0
9a799d71
AK		 1708#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
1709#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5
1710#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
1711#define IXGBE_RXDADV_SPH 0x8000
1712
1713/* RSS Hash results */
1714#define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000
1715#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
1716#define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002
1717#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
1718#define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004
1719#define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005
1720#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
1721#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007
1722#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008
1723#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
1724
1725/* RSS Packet Types as indicated in the receive descriptor. */
1726#define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000
1727#define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */
1728#define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */
1729#define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */
1730#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */
1731#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
1732#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
1733#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
1734#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
11afc1b1
PW		 1735#define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */
1736#define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */
1737#define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */
1738#define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */
1739#define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */
1740#define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
1741
1742/* Security Processing bit Indication */
1743#define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000
1744#define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000
1745#define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000
1746#define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000
1747#define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000
1748
9a799d71 1749/* Masks to determine if packets should be dropped due to frame errors */
c44ade9e
JB		 1750#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
1751 IXGBE_RXD_ERR_CE | \
1752 IXGBE_RXD_ERR_LE | \
1753 IXGBE_RXD_ERR_PE | \
1754 IXGBE_RXD_ERR_OSE | \
1755 IXGBE_RXD_ERR_USE)
1756
1757#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
1758 IXGBE_RXDADV_ERR_CE | \
1759 IXGBE_RXDADV_ERR_LE | \
1760 IXGBE_RXDADV_ERR_PE | \
1761 IXGBE_RXDADV_ERR_OSE | \
1762 IXGBE_RXDADV_ERR_USE)
9a799d71
AK		 1763
1764/* Multicast bit mask */
1765#define IXGBE_MCSTCTRL_MFE 0x4
1766
1767/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
1768#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
1769#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8
1770#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024
1771
1772/* Vlan-specific macros */
1773#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */
1774#define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */
1775#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
1776#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
1777
11afc1b1
PW		 1778/* Little Endian defines */
1779#ifndef __le32
1780#define __le32 u32
1781#endif
1782#ifndef __le64
1783#define __le64 u64
1784
1785#endif
c44ade9e 1786
9a799d71
AK		 1787/* Transmit Descriptor - Legacy */
1788struct ixgbe_legacy_tx_desc {
1789 u64 buffer_addr; /* Address of the descriptor's data buffer */
1790 union {
8327d000 1791 __le32 data;
9a799d71 1792 struct {
8327d000 1793 __le16 length; /* Data buffer length */
9da09bb1
JB		 1794 u8 cso; /* Checksum offset */
1795 u8 cmd; /* Descriptor control */
9a799d71
AK		 1796 } flags;
1797 } lower;
1798 union {
8327d000 1799 __le32 data;
9a799d71 1800 struct {
c44ade9e
JB		 1801 u8 status; /* Descriptor status */
1802 u8 css; /* Checksum start */
8327d000 1803 __le16 vlan;
9a799d71
AK		 1804 } fields;
1805 } upper;
1806};
1807
1808/* Transmit Descriptor - Advanced */
1809union ixgbe_adv_tx_desc {
1810 struct {
c44ade9e 1811 __le64 buffer_addr; /* Address of descriptor's data buf */
8327d000
AV		 1812 __le32 cmd_type_len;
1813 __le32 olinfo_status;
9a799d71
AK		 1814 } read;
1815 struct {
8327d000
AV		 1816 __le64 rsvd; /* Reserved */
1817 __le32 nxtseq_seed;
1818 __le32 status;
9a799d71
AK		 1819 } wb;
1820};
1821
1822/* Receive Descriptor - Legacy */
1823struct ixgbe_legacy_rx_desc {
8327d000
AV		 1824 __le64 buffer_addr; /* Address of the descriptor's data buffer */
1825 __le16 length; /* Length of data DMAed into data buffer */
9da09bb1
JB		 1826 __le16 csum; /* Packet checksum */
1827 u8 status; /* Descriptor status */
1828 u8 errors; /* Descriptor Errors */
8327d000 1829 __le16 vlan;
9a799d71
AK		 1830};
1831
1832/* Receive Descriptor - Advanced */
1833union ixgbe_adv_rx_desc {
1834 struct {
8327d000
AV		 1835 __le64 pkt_addr; /* Packet buffer address */
1836 __le64 hdr_addr; /* Header buffer address */
9a799d71
AK		 1837 } read;
1838 struct {
1839 struct {
7c6e0a43
JB		 1840 union {
1841 __le32 data;
1842 struct {
c44ade9e
JB		 1843 __le16 pkt_info; /* RSS, Pkt type */
1844 __le16 hdr_info; /* Splithdr, hdrlen */
7c6e0a43 1845 } hs_rss;
9a799d71
AK		 1846 } lo_dword;
1847 union {
8327d000 1848 __le32 rss; /* RSS Hash */
9a799d71 1849 struct {
8327d000 1850 __le16 ip_id; /* IP id */
9da09bb1 1851 __le16 csum; /* Packet Checksum */
9a799d71
AK		 1852 } csum_ip;
1853 } hi_dword;
1854 } lower;
1855 struct {
8327d000
AV		 1856 __le32 status_error; /* ext status/error */
1857 __le16 length; /* Packet length */
1858 __le16 vlan; /* VLAN tag */
9a799d71
AK		 1859 } upper;
1860 } wb; /* writeback */
1861};
1862
1863/* Context descriptors */
1864struct ixgbe_adv_tx_context_desc {
8327d000
AV		 1865 __le32 vlan_macip_lens;
1866 __le32 seqnum_seed;
1867 __le32 type_tucmd_mlhl;
1868 __le32 mss_l4len_idx;
9a799d71
AK		 1869};
1870
1871/* Adv Transmit Descriptor Config Masks */
c44ade9e 1872#define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */
11afc1b1
PW		 1873#define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */
1874#define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */
1875#define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */
9a799d71
AK		 1876#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */
1877#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */
1878#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
1879#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */
1880#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */
9a799d71 1881#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */
c44ade9e 1882#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */
9a799d71
AK		 1883#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
1884#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */
1885#define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
1886#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */
c44ade9e 1887#define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */
9a799d71
AK		 1888#define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */
1889#define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
c44ade9e 1890#define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */
9a799d71
AK		 1891#define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */
1892#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
c44ade9e 1893 IXGBE_ADVTXD_POPTS_SHIFT)
9a799d71 1894#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
c44ade9e
JB		 1895 IXGBE_ADVTXD_POPTS_SHIFT)
1896#define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */
1897#define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
1898#define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
1899#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */
1900#define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */
1901#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
1902#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
1903#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
1904#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
1905#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
1906#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
1907#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
1908#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
1909#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/
11afc1b1
PW		 1910#define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */
1911#define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
1912#define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
bff66176
YZ		 1913#define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */
1914#define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */
1915#define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */
1916#define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */
1917#define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation: End */
1918#define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation: Start */
1919#define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */
1920#define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */
1921#define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */
1922#define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */
c44ade9e
JB		 1923#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
1924#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
1925
1926/* Autonegotiation advertised speeds */
1927typedef u32 ixgbe_autoneg_advertised;
9a799d71 1928/* Link speed */
c44ade9e 1929typedef u32 ixgbe_link_speed;
9a799d71
AK		 1930#define IXGBE_LINK_SPEED_UNKNOWN 0
1931#define IXGBE_LINK_SPEED_100_FULL 0x0008
1932#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
1933#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
c44ade9e
JB		 1934#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
1935 IXGBE_LINK_SPEED_10GB_FULL)
11afc1b1
PW		 1936#define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
1937 IXGBE_LINK_SPEED_1GB_FULL | \
1938 IXGBE_LINK_SPEED_10GB_FULL)
1939
1940#define IXGBE_PCIE_DEV_CTRL_2 0xC8
1941#define PCIE_COMPL_TO_VALUE 0x05
c44ade9e
JB		 1942
1943/* Physical layer type */
1944typedef u32 ixgbe_physical_layer;
1945#define IXGBE_PHYSICAL_LAYER_UNKNOWN 0
1946#define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001
1947#define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002
04193058 1948#define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004
c44ade9e
JB		 1949#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008
1950#define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010
1951#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020
1952#define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040
1953#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080
1954#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100
1955#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
1956#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
04193058 1957#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800
1fcf03e6 1958#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000
9a799d71 1959
9a799d71
AK		 1960enum ixgbe_eeprom_type {
1961 ixgbe_eeprom_uninitialized = 0,
1962 ixgbe_eeprom_spi,
1963 ixgbe_eeprom_none /* No NVM support */
1964};
1965
1966enum ixgbe_mac_type {
1967 ixgbe_mac_unknown = 0,
1968 ixgbe_mac_82598EB,
11afc1b1 1969 ixgbe_mac_82599EB,
9a799d71
AK		 1970 ixgbe_num_macs
1971};
1972
1973enum ixgbe_phy_type {
1974 ixgbe_phy_unknown = 0,
0befdb3e 1975 ixgbe_phy_tn,
11afc1b1 1976 ixgbe_phy_cu_unknown,
9a799d71 1977 ixgbe_phy_qt,
c44ade9e 1978 ixgbe_phy_xaui,
c4900be0 1979 ixgbe_phy_nl,
c44ade9e
JB		 1980 ixgbe_phy_tw_tyco,
1981 ixgbe_phy_tw_unknown,
1982 ixgbe_phy_sfp_avago,
1983 ixgbe_phy_sfp_ftl,
1984 ixgbe_phy_sfp_unknown,
11afc1b1 1985 ixgbe_phy_sfp_intel,
fa466e91 1986 ixgbe_phy_sfp_unsupported,
c44ade9e
JB		 1987 ixgbe_phy_generic
1988};
1989
1990/*
1991 * SFP+ module type IDs:
1992 *
11afc1b1 1993 * ID Module Type
c44ade9e 1994 * =============
11afc1b1
PW		 1995 * 0 SFP_DA_CU
1996 * 1 SFP_SR
1997 * 2 SFP_LR
1998 * 3 SFP_DA_CU_CORE0 - 82599-specific
1999 * 4 SFP_DA_CU_CORE1 - 82599-specific
2000 * 5 SFP_SR/LR_CORE0 - 82599-specific
2001 * 6 SFP_SR/LR_CORE1 - 82599-specific
c44ade9e
JB		 2002 */
2003enum ixgbe_sfp_type {
2004 ixgbe_sfp_type_da_cu = 0,
2005 ixgbe_sfp_type_sr = 1,
2006 ixgbe_sfp_type_lr = 2,
11afc1b1
PW		 2007 ixgbe_sfp_type_da_cu_core0 = 3,
2008 ixgbe_sfp_type_da_cu_core1 = 4,
2009 ixgbe_sfp_type_srlr_core0 = 5,
2010 ixgbe_sfp_type_srlr_core1 = 6,
c4900be0 2011 ixgbe_sfp_type_not_present = 0xFFFE,
c44ade9e 2012 ixgbe_sfp_type_unknown = 0xFFFF
9a799d71
AK		 2013};
2014
2015enum ixgbe_media_type {
2016 ixgbe_media_type_unknown = 0,
2017 ixgbe_media_type_fiber,
2018 ixgbe_media_type_copper,
c44ade9e
JB		 2019 ixgbe_media_type_backplane,
2020 ixgbe_media_type_virtual
9a799d71
AK		 2021};
2022
2023/* Flow Control Settings */
0ecc061d 2024enum ixgbe_fc_mode {
9a799d71
AK		 2025 ixgbe_fc_none = 0,
2026 ixgbe_fc_rx_pause,
2027 ixgbe_fc_tx_pause,
2028 ixgbe_fc_full,
bb3daa4a
PW		 2029#ifdef CONFIG_DCB
2030 ixgbe_fc_pfc,
2031#endif
9a799d71
AK		 2032 ixgbe_fc_default
2033};
2034
11afc1b1
PW		 2035/* PCI bus types */
2036enum ixgbe_bus_type {
2037 ixgbe_bus_type_unknown = 0,
2038 ixgbe_bus_type_pci,
2039 ixgbe_bus_type_pcix,
2040 ixgbe_bus_type_pci_express,
2041 ixgbe_bus_type_reserved
2042};
2043
2044/* PCI bus speeds */
2045enum ixgbe_bus_speed {
2046 ixgbe_bus_speed_unknown = 0,
2047 ixgbe_bus_speed_33,
2048 ixgbe_bus_speed_66,
2049 ixgbe_bus_speed_100,
2050 ixgbe_bus_speed_120,
2051 ixgbe_bus_speed_133,
2052 ixgbe_bus_speed_2500,
2053 ixgbe_bus_speed_5000,
2054 ixgbe_bus_speed_reserved
2055};
2056
2057/* PCI bus widths */
2058enum ixgbe_bus_width {
2059 ixgbe_bus_width_unknown = 0,
2060 ixgbe_bus_width_pcie_x1,
2061 ixgbe_bus_width_pcie_x2,
2062 ixgbe_bus_width_pcie_x4 = 4,
2063 ixgbe_bus_width_pcie_x8 = 8,
2064 ixgbe_bus_width_32,
2065 ixgbe_bus_width_64,
2066 ixgbe_bus_width_reserved
2067};
2068
9a799d71
AK		 2069struct ixgbe_addr_filter_info {
2070 u32 num_mc_addrs;
2071 u32 rar_used_count;
2072 u32 mc_addr_in_rar_count;
2073 u32 mta_in_use;
2c5645cf
CL		 2074 u32 overflow_promisc;
2075 bool user_set_promisc;
9a799d71
AK		 2076};
2077
11afc1b1
PW		 2078/* Bus parameters */
2079struct ixgbe_bus_info {
2080 enum ixgbe_bus_speed speed;
2081 enum ixgbe_bus_width width;
2082 enum ixgbe_bus_type type;
2083
2084 u16 func;
2085 u16 lan_id;
2086};
2087
9a799d71
AK		 2088/* Flow control parameters */
2089struct ixgbe_fc_info {
2090 u32 high_water; /* Flow Control High-water */
2091 u32 low_water; /* Flow Control Low-water */
2092 u16 pause_time; /* Flow Control Pause timer */
2093 bool send_xon; /* Flow control send XON */
2094 bool strict_ieee; /* Strict IEEE mode */
71fd570b 2095 bool disable_fc_autoneg; /* Turn off autoneg FC mode */
0ecc061d
PWJ		 2096 enum ixgbe_fc_mode current_mode; /* FC mode in effect */
2097 enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */
9a799d71
AK		 2098};
2099
2100/* Statistics counters collected by the MAC */
2101struct ixgbe_hw_stats {
2102 u64 crcerrs;
2103 u64 illerrc;
2104 u64 errbc;
2105 u64 mspdc;
2106 u64 mpctotal;
2107 u64 mpc[8];
2108 u64 mlfc;
2109 u64 mrfc;
2110 u64 rlec;
2111 u64 lxontxc;
2112 u64 lxonrxc;
2113 u64 lxofftxc;
2114 u64 lxoffrxc;
2115 u64 pxontxc[8];
2116 u64 pxonrxc[8];
2117 u64 pxofftxc[8];
2118 u64 pxoffrxc[8];
2119 u64 prc64;
2120 u64 prc127;
2121 u64 prc255;
2122 u64 prc511;
2123 u64 prc1023;
2124 u64 prc1522;
2125 u64 gprc;
2126 u64 bprc;
2127 u64 mprc;
2128 u64 gptc;
2129 u64 gorc;
2130 u64 gotc;
2131 u64 rnbc[8];
2132 u64 ruc;
2133 u64 rfc;
2134 u64 roc;
2135 u64 rjc;
2136 u64 mngprc;
2137 u64 mngpdc;
2138 u64 mngptc;
2139 u64 tor;
2140 u64 tpr;
2141 u64 tpt;
2142 u64 ptc64;
2143 u64 ptc127;
2144 u64 ptc255;
2145 u64 ptc511;
2146 u64 ptc1023;
2147 u64 ptc1522;
2148 u64 mptc;
2149 u64 bptc;
2150 u64 xec;
2151 u64 rqsmr[16];
2152 u64 tqsmr[8];
2153 u64 qprc[16];
2154 u64 qptc[16];
2155 u64 qbrc[16];
2156 u64 qbtc[16];
11afc1b1
PW		 2157 u64 qprdc[16];
2158 u64 pxon2offc[8];
2159 u64 fdirustat_add;
2160 u64 fdirustat_remove;
2161 u64 fdirfstat_fadd;
2162 u64 fdirfstat_fremove;
2163 u64 fdirmatch;
2164 u64 fdirmiss;
6d45522c
YZ		 2165 u64 fccrc;
2166 u64 fcoerpdc;
2167 u64 fcoeprc;
2168 u64 fcoeptc;
2169 u64 fcoedwrc;
2170 u64 fcoedwtc;
9a799d71
AK		 2171};
2172
2173/* forward declaration */
2174struct ixgbe_hw;
2175
2c5645cf
CL		 2176/* iterator type for walking multicast address lists */
2177typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
2178 u32 *vmdq);
2179
c44ade9e
JB		 2180/* Function pointer table */
2181struct ixgbe_eeprom_operations {
2182 s32 (*init_params)(struct ixgbe_hw *);
2183 s32 (*read)(struct ixgbe_hw *, u16, u16 *);
2184 s32 (*write)(struct ixgbe_hw *, u16, u16);
2185 s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
2186 s32 (*update_checksum)(struct ixgbe_hw *);
2187};
2188
9a799d71 2189struct ixgbe_mac_operations {
c44ade9e
JB		 2190 s32 (*init_hw)(struct ixgbe_hw *);
2191 s32 (*reset_hw)(struct ixgbe_hw *);
2192 s32 (*start_hw)(struct ixgbe_hw *);
2193 s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
9a799d71 2194 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
11afc1b1 2195 u32 (*get_supported_physical_layer)(struct ixgbe_hw *);
c44ade9e 2196 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
0365e6e4 2197 s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);
04193058 2198 s32 (*get_device_caps)(struct ixgbe_hw *, u16 *);
c44ade9e
JB		 2199 s32 (*stop_adapter)(struct ixgbe_hw *);
2200 s32 (*get_bus_info)(struct ixgbe_hw *);
11afc1b1 2201 void (*set_lan_id)(struct ixgbe_hw *);
c44ade9e
JB		 2202 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
2203 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
11afc1b1
PW		 2204 s32 (*setup_sfp)(struct ixgbe_hw *);
2205 s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
c44ade9e
JB		 2206
2207 /* Link */
3957d63d 2208 s32 (*setup_link)(struct ixgbe_hw *);
c44ade9e
JB		 2209 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
2210 bool);
2211 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
2212 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
2213 bool *);
2214
2215 /* LED */
2216 s32 (*led_on)(struct ixgbe_hw *, u32);
2217 s32 (*led_off)(struct ixgbe_hw *, u32);
2218 s32 (*blink_led_start)(struct ixgbe_hw *, u32);
2219 s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
2220
2221 /* RAR, Multicast, VLAN */
2222 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
2223 s32 (*clear_rar)(struct ixgbe_hw *, u32);
2224 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
2225 s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
2226 s32 (*init_rx_addrs)(struct ixgbe_hw *);
ccffad25 2227 s32 (*update_uc_addr_list)(struct ixgbe_hw *, struct list_head *);
c44ade9e
JB		 2228 s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,
2229 ixgbe_mc_addr_itr);
2230 s32 (*enable_mc)(struct ixgbe_hw *);
2231 s32 (*disable_mc)(struct ixgbe_hw *);
2232 s32 (*clear_vfta)(struct ixgbe_hw *);
2233 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
2234 s32 (*init_uta_tables)(struct ixgbe_hw *);
2235
2236 /* Flow Control */
2237 s32 (*setup_fc)(struct ixgbe_hw *, s32);
9a799d71
AK		 2238};
2239
2240struct ixgbe_phy_operations {
c44ade9e
JB		 2241 s32 (*identify)(struct ixgbe_hw *);
2242 s32 (*identify_sfp)(struct ixgbe_hw *);
04f165ef 2243 s32 (*init)(struct ixgbe_hw *);
c44ade9e
JB		 2244 s32 (*reset)(struct ixgbe_hw *);
2245 s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
2246 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
3957d63d 2247 s32 (*setup_link)(struct ixgbe_hw *);
c44ade9e
JB		 2248 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
2249 bool);
0befdb3e
JB		 2250 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
2251 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
c44ade9e
JB		 2252 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
2253 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
2254 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
2255 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
9a799d71
AK		 2256};
2257
9a799d71 2258struct ixgbe_eeprom_info {
c44ade9e
JB		 2259 struct ixgbe_eeprom_operations ops;
2260 enum ixgbe_eeprom_type type;
11afc1b1 2261 u32 semaphore_delay;
c44ade9e
JB		 2262 u16 word_size;
2263 u16 address_bits;
9a799d71
AK		 2264};
2265
c44ade9e
JB		 2266struct ixgbe_mac_info {
2267 struct ixgbe_mac_operations ops;
2268 enum ixgbe_mac_type type;
2269 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
2270 u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
0365e6e4 2271 u8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
c44ade9e
JB		 2272 s32 mc_filter_type;
2273 u32 mcft_size;
2274 u32 vft_size;
2275 u32 num_rar_entries;
2276 u32 max_tx_queues;
2277 u32 max_rx_queues;
eb7f139c 2278 u32 max_msix_vectors;
3201d313
PWJ		 2279 u32 orig_autoc;
2280 u32 orig_autoc2;
2281 bool orig_link_settings_stored;
c44ade9e 2282 bool autoneg;
3201d313 2283 bool autoneg_succeeded;
9a799d71
AK		 2284};
2285
c44ade9e
JB		 2286struct ixgbe_phy_info {
2287 struct ixgbe_phy_operations ops;
6b73e10d 2288 struct mdio_if_info mdio;
c44ade9e 2289 enum ixgbe_phy_type type;
c44ade9e
JB		 2290 u32 id;
2291 enum ixgbe_sfp_type sfp_type;
553b4497 2292 bool sfp_setup_needed;
c44ade9e
JB		 2293 u32 revision;
2294 enum ixgbe_media_type media_type;
2295 bool reset_disable;
2296 ixgbe_autoneg_advertised autoneg_advertised;
2297 bool autoneg_wait_to_complete;
0ecc061d 2298 bool multispeed_fiber;
9a799d71
AK		 2299};
2300
2301struct ixgbe_hw {
2302 u8 __iomem *hw_addr;
2303 void *back;
2304 struct ixgbe_mac_info mac;
2305 struct ixgbe_addr_filter_info addr_ctrl;
2306 struct ixgbe_fc_info fc;
2307 struct ixgbe_phy_info phy;
2308 struct ixgbe_eeprom_info eeprom;
11afc1b1 2309 struct ixgbe_bus_info bus;
9a799d71
AK		 2310 u16 device_id;
2311 u16 vendor_id;
2312 u16 subsystem_device_id;
2313 u16 subsystem_vendor_id;
2314 u8 revision_id;
2315 bool adapter_stopped;
2316};
2317
c44ade9e
JB		 2318struct ixgbe_info {
2319 enum ixgbe_mac_type mac;
2320 s32 (*get_invariants)(struct ixgbe_hw *);
2321 struct ixgbe_mac_operations *mac_ops;
2322 struct ixgbe_eeprom_operations *eeprom_ops;
2323 struct ixgbe_phy_operations *phy_ops;
2324};
2325
2326
9a799d71
AK		 2327/* Error Codes */
2328#define IXGBE_ERR_EEPROM -1
2329#define IXGBE_ERR_EEPROM_CHECKSUM -2
2330#define IXGBE_ERR_PHY -3
2331#define IXGBE_ERR_CONFIG -4
2332#define IXGBE_ERR_PARAM -5
2333#define IXGBE_ERR_MAC_TYPE -6
2334#define IXGBE_ERR_UNKNOWN_PHY -7
2335#define IXGBE_ERR_LINK_SETUP -8
2336#define IXGBE_ERR_ADAPTER_STOPPED -9
2337#define IXGBE_ERR_INVALID_MAC_ADDR -10
2338#define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11
2339#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12
2340#define IXGBE_ERR_INVALID_LINK_SETTINGS -13
2341#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14
2342#define IXGBE_ERR_RESET_FAILED -15
2343#define IXGBE_ERR_SWFW_SYNC -16
2344#define IXGBE_ERR_PHY_ADDR_INVALID -17
c44ade9e
JB		 2345#define IXGBE_ERR_I2C -18
2346#define IXGBE_ERR_SFP_NOT_SUPPORTED -19
c4900be0 2347#define IXGBE_ERR_SFP_NOT_PRESENT -20
11afc1b1 2348#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21
9a799d71
AK		 2349#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
2350
2351#endif /* _IXGBE_TYPE_H_ */
kernel source for telekom puls (alcatel/mediatek)