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ixgbe: Allow tx itr specific settings
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71
AK		 38#include <linux/ipv6.h>
39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
41#include <linux/ethtool.h>
42#include <linux/if_vlan.h>
eacd73f7 43#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 44
45#include "ixgbe.h"
46#include "ixgbe_common.h"
47
48char ixgbe_driver_name[] = "ixgbe";
9c8eb720 49static const char ixgbe_driver_string[] =
b4617240 50 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 51
bbf50e4d 52#define DRV_VERSION "2.0.37-k2"
9c8eb720 53const char ixgbe_driver_version[] = DRV_VERSION;
3efac5a0 54static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
9a799d71
AK		 55
56static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 57 [board_82598] = &ixgbe_82598_info,
e8e26350 58 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 59};
60
61/* ixgbe_pci_tbl - PCI Device ID Table
62 *
63 * Wildcard entries (PCI_ANY_ID) should come last
64 * Last entry must be all 0s
65 *
66 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
67 * Class, Class Mask, private data (not used) }
68 */
69static struct pci_device_id ixgbe_pci_tbl[] = {
1e336d0f
DS		 70 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
71 board_82598 },
9a799d71 72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 73 board_82598 },
9a799d71 74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 75 board_82598 },
0befdb3e
JB		 76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
77 board_82598 },
3845bec0
PWJ		 78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
79 board_82598 },
9a799d71 80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 81 board_82598 },
8d792cd9
JB		 82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
83 board_82598 },
c4900be0
DS		 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
85 board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
87 board_82598 },
b95f5fcb
JB		 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
89 board_82598 },
c4900be0
DS		 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
91 board_82598 },
2f21bdd3
DS		 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
93 board_82598 },
e8e26350
PW		 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
95 board_82599 },
1fcf03e6
PWJ		 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
97 board_82599 },
e8e26350
PW		 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
99 board_82599 },
8911184f
PWJ		 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
101 board_82599 },
9a799d71
AK		 102
103 /* required last entry */
104 {0, }
105};
106MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
107
5dd2d332 108#ifdef CONFIG_IXGBE_DCA
bd0362dd 109static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 110 void *p);
bd0362dd
JC		 111static struct notifier_block dca_notifier = {
112 .notifier_call = ixgbe_notify_dca,
113 .next = NULL,
114 .priority = 0
115};
116#endif
117
9a799d71
AK		 118MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
119MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
120MODULE_LICENSE("GPL");
121MODULE_VERSION(DRV_VERSION);
122
123#define DEFAULT_DEBUG_LEVEL_SHIFT 3
124
5eba3699
AV		 125static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
126{
127 u32 ctrl_ext;
128
129 /* Let firmware take over control of h/w */
130 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
131 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 132 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 133}
134
135static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
136{
137 u32 ctrl_ext;
138
139 /* Let firmware know the driver has taken over */
140 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
141 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 142 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 143}
9a799d71 144
e8e26350
PW		 145/*
146 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
147 * @adapter: pointer to adapter struct
148 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
149 * @queue: queue to map the corresponding interrupt to
150 * @msix_vector: the vector to map to the corresponding queue
151 *
152 */
153static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
154 u8 queue, u8 msix_vector)
9a799d71
AK		 155{
156 u32 ivar, index;
e8e26350
PW		 157 struct ixgbe_hw *hw = &adapter->hw;
158 switch (hw->mac.type) {
159 case ixgbe_mac_82598EB:
160 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
161 if (direction == -1)
162 direction = 0;
163 index = (((direction * 64) + queue) >> 2) & 0x1F;
164 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
165 ivar &= ~(0xFF << (8 * (queue & 0x3)));
166 ivar |= (msix_vector << (8 * (queue & 0x3)));
167 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
168 break;
169 case ixgbe_mac_82599EB:
170 if (direction == -1) {
171 /* other causes */
172 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
173 index = ((queue & 1) * 8);
174 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
175 ivar &= ~(0xFF << index);
176 ivar |= (msix_vector << index);
177 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
178 break;
179 } else {
180 /* tx or rx causes */
181 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
182 index = ((16 * (queue & 1)) + (8 * direction));
183 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
184 ivar &= ~(0xFF << index);
185 ivar |= (msix_vector << index);
186 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
187 break;
188 }
189 default:
190 break;
191 }
9a799d71
AK		 192}
193
fe49f04a
AD		 194static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
195 u64 qmask)
196{
197 u32 mask;
198
199 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
200 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
201 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
202 } else {
203 mask = (qmask & 0xFFFFFFFF);
204 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
205 mask = (qmask >> 32);
206 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
207 }
208}
209
9a799d71 210static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 211 struct ixgbe_tx_buffer
212 *tx_buffer_info)
9a799d71 213{
44df32c5 214 tx_buffer_info->dma = 0;
9a799d71 215 if (tx_buffer_info->skb) {
44df32c5
AD		 216 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
217 DMA_TO_DEVICE);
9a799d71
AK		 218 dev_kfree_skb_any(tx_buffer_info->skb);
219 tx_buffer_info->skb = NULL;
220 }
44df32c5 221 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 222 /* tx_buffer_info must be completely set up in the transmit path */
223}
224
225static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 226 struct ixgbe_ring *tx_ring,
227 unsigned int eop)
9a799d71 228{
e01c31a5 229 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 230
9a799d71 231 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 232 * check with the clearing of time_stamp and movement of eop */
9a799d71 233 adapter->detect_tx_hung = false;
44df32c5 234 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 235 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
236 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
237 /* detected Tx unit hang */
e01c31a5
JB		 238 union ixgbe_adv_tx_desc *tx_desc;
239 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 240 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 241 " Tx Queue <%d>\n"
242 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 243 " next_to_use <%x>\n"
244 " next_to_clean <%x>\n"
245 "tx_buffer_info[next_to_clean]\n"
246 " time_stamp <%lx>\n"
e01c31a5
JB		 247 " jiffies <%lx>\n",
248 tx_ring->queue_index,
44df32c5
AD		 249 IXGBE_READ_REG(hw, tx_ring->head),
250 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 251 tx_ring->next_to_use, eop,
252 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 253 return true;
254 }
255
256 return false;
257}
258
b4617240
PW		 259#define IXGBE_MAX_TXD_PWR 14
260#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 261
262/* Tx Descriptors needed, worst case */
263#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
264 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
265#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 266 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 267
e01c31a5
JB		 268static void ixgbe_tx_timeout(struct net_device *netdev);
269
9a799d71
AK		 270/**
271 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 272 * @q_vector: structure containing interrupt and ring information
e01c31a5 273 * @tx_ring: tx ring to clean
9a799d71 274 **/
fe49f04a 275static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e01c31a5 276 struct ixgbe_ring *tx_ring)
9a799d71 277{
fe49f04a 278 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 279 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 280 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
281 struct ixgbe_tx_buffer *tx_buffer_info;
282 unsigned int i, eop, count = 0;
e01c31a5 283 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 284
285 i = tx_ring->next_to_clean;
12207e49
PWJ		 286 eop = tx_ring->tx_buffer_info[i].next_to_watch;
287 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
288
289 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 290 (count < tx_ring->work_limit)) {
12207e49
PWJ		 291 bool cleaned = false;
292 for ( ; !cleaned; count++) {
293 struct sk_buff *skb;
9a799d71
AK		 294 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
295 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 296 cleaned = (i == eop);
e01c31a5 297 skb = tx_buffer_info->skb;
9a799d71 298
12207e49 299 if (cleaned && skb) {
e092be60 300 unsigned int segs, bytecount;
3d8fd385 301 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 302
303 /* gso_segs is currently only valid for tcp */
e092be60 304 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 305#ifdef IXGBE_FCOE
306 /* adjust for FCoE Sequence Offload */
307 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
308 && (skb->protocol == htons(ETH_P_FCOE)) &&
309 skb_is_gso(skb)) {
310 hlen = skb_transport_offset(skb) +
311 sizeof(struct fc_frame_header) +
312 sizeof(struct fcoe_crc_eof);
313 segs = DIV_ROUND_UP(skb->len - hlen,
314 skb_shinfo(skb)->gso_size);
315 }
316#endif /* IXGBE_FCOE */
e092be60 317 /* multiply data chunks by size of headers */
3d8fd385 318 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 319 total_packets += segs;
320 total_bytes += bytecount;
e092be60 321 }
e01c31a5 322
9a799d71 323 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 324 tx_buffer_info);
9a799d71 325
12207e49
PWJ		 326 tx_desc->wb.status = 0;
327
9a799d71
AK		 328 i++;
329 if (i == tx_ring->count)
330 i = 0;
e01c31a5 331 }
12207e49
PWJ		 332
333 eop = tx_ring->tx_buffer_info[i].next_to_watch;
334 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
335 }
336
9a799d71
AK		 337 tx_ring->next_to_clean = i;
338
e092be60 339#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 340 if (unlikely(count && netif_carrier_ok(netdev) &&
341 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 342 /* Make sure that anybody stopping the queue after this
343 * sees the new next_to_clean.
344 */
345 smp_mb();
30eba97a
AV		 346 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
347 !test_bit(__IXGBE_DOWN, &adapter->state)) {
348 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 349 ++adapter->restart_queue;
30eba97a 350 }
e092be60 351 }
9a799d71 352
e01c31a5
JB		 353 if (adapter->detect_tx_hung) {
354 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
355 /* schedule immediate reset if we believe we hung */
356 DPRINTK(PROBE, INFO,
357 "tx hang %d detected, resetting adapter\n",
358 adapter->tx_timeout_count + 1);
359 ixgbe_tx_timeout(adapter->netdev);
360 }
361 }
9a799d71 362
e01c31a5 363 /* re-arm the interrupt */
fe49f04a
AD		 364 if (count >= tx_ring->work_limit)
365 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 366
e01c31a5
JB		 367 tx_ring->total_bytes += total_bytes;
368 tx_ring->total_packets += total_packets;
e01c31a5 369 tx_ring->stats.packets += total_packets;
12207e49 370 tx_ring->stats.bytes += total_bytes;
e01c31a5
JB		 371 adapter->net_stats.tx_bytes += total_bytes;
372 adapter->net_stats.tx_packets += total_packets;
9a1a69ad 373 return (count < tx_ring->work_limit);
9a799d71
AK		 374}
375
5dd2d332 376#ifdef CONFIG_IXGBE_DCA
bd0362dd 377static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 378 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 379{
380 u32 rxctrl;
381 int cpu = get_cpu();
3a581073 382 int q = rx_ring - adapter->rx_ring;
bd0362dd 383
3a581073 384 if (rx_ring->cpu != cpu) {
bd0362dd 385 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 386 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
387 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
388 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
389 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
390 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
391 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
392 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
393 }
bd0362dd
JC		 394 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
395 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 396 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
397 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 398 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 399 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 400 rx_ring->cpu = cpu;
bd0362dd
JC		 401 }
402 put_cpu();
403}
404
405static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 406 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 407{
408 u32 txctrl;
409 int cpu = get_cpu();
3a581073 410 int q = tx_ring - adapter->tx_ring;
bd0362dd 411
3a581073 412 if (tx_ring->cpu != cpu) {
bd0362dd 413 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 414 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
415 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
416 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
417 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
418 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
419 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
420 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
421 }
bd0362dd
JC		 422 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
423 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 424 tx_ring->cpu = cpu;
bd0362dd
JC		 425 }
426 put_cpu();
427}
428
429static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
430{
431 int i;
432
433 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
434 return;
435
e35ec126
AD		 436 /* always use CB2 mode, difference is masked in the CB driver */
437 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
438
bd0362dd
JC		 439 for (i = 0; i < adapter->num_tx_queues; i++) {
440 adapter->tx_ring[i].cpu = -1;
441 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
442 }
443 for (i = 0; i < adapter->num_rx_queues; i++) {
444 adapter->rx_ring[i].cpu = -1;
445 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
446 }
447}
448
449static int __ixgbe_notify_dca(struct device *dev, void *data)
450{
451 struct net_device *netdev = dev_get_drvdata(dev);
452 struct ixgbe_adapter *adapter = netdev_priv(netdev);
453 unsigned long event = *(unsigned long *)data;
454
455 switch (event) {
456 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 457 /* if we're already enabled, don't do it again */
458 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
459 break;
652f093f 460 if (dca_add_requester(dev) == 0) {
96b0e0f6 461 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 462 ixgbe_setup_dca(adapter);
463 break;
464 }
465 /* Fall Through since DCA is disabled. */
466 case DCA_PROVIDER_REMOVE:
467 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
468 dca_remove_requester(dev);
469 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
470 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
471 }
472 break;
473 }
474
652f093f 475 return 0;
bd0362dd
JC		 476}
477
5dd2d332 478#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 479/**
480 * ixgbe_receive_skb - Send a completed packet up the stack
481 * @adapter: board private structure
482 * @skb: packet to send up
177db6ff
MC		 483 * @status: hardware indication of status of receive
484 * @rx_ring: rx descriptor ring (for a specific queue) to setup
485 * @rx_desc: rx descriptor
9a799d71 486 **/
78b6f4ce 487static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 488 struct sk_buff *skb, u8 status,
fdaff1ce 489 struct ixgbe_ring *ring,
177db6ff 490 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 491{
78b6f4ce
HX		 492 struct ixgbe_adapter *adapter = q_vector->adapter;
493 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 494 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
495 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 496
fdaff1ce 497 skb_record_rx_queue(skb, ring->queue_index);
182ff8df 498 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
8a62babf 499 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
78b6f4ce 500 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 501 else
78b6f4ce 502 napi_gro_receive(napi, skb);
177db6ff 503 } else {
8a62babf 504 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
182ff8df
AD		 505 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
506 else
507 netif_rx(skb);
9a799d71
AK		 508 }
509}
510
e59bd25d
AV		 511/**
512 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
513 * @adapter: address of board private structure
514 * @status_err: hardware indication of status of receive
515 * @skb: skb currently being received and modified
516 **/
9a799d71 517static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 518 union ixgbe_adv_rx_desc *rx_desc,
519 struct sk_buff *skb)
9a799d71 520{
8bae1b2b
DS		 521 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
522
9a799d71
AK		 523 skb->ip_summed = CHECKSUM_NONE;
524
712744be
JB		 525 /* Rx csum disabled */
526 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 527 return;
e59bd25d
AV		 528
529 /* if IP and error */
530 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
531 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 532 adapter->hw_csum_rx_error++;
533 return;
534 }
e59bd25d
AV		 535
536 if (!(status_err & IXGBE_RXD_STAT_L4CS))
537 return;
538
539 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 540 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
541
542 /*
543 * 82599 errata, UDP frames with a 0 checksum can be marked as
544 * checksum errors.
545 */
546 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
547 (adapter->hw.mac.type == ixgbe_mac_82599EB))
548 return;
549
e59bd25d
AV		 550 adapter->hw_csum_rx_error++;
551 return;
552 }
553
9a799d71 554 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 555 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 556 adapter->hw_csum_rx_good++;
557}
558
e8e26350
PW		 559static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
560 struct ixgbe_ring *rx_ring, u32 val)
561{
562 /*
563 * Force memory writes to complete before letting h/w
564 * know there are new descriptors to fetch. (Only
565 * applicable for weak-ordered memory model archs,
566 * such as IA-64).
567 */
568 wmb();
569 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
570}
571
9a799d71
AK		 572/**
573 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
574 * @adapter: address of board private structure
575 **/
576static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 577 struct ixgbe_ring *rx_ring,
578 int cleaned_count)
9a799d71 579{
9a799d71
AK		 580 struct pci_dev *pdev = adapter->pdev;
581 union ixgbe_adv_rx_desc *rx_desc;
3a581073 582 struct ixgbe_rx_buffer *bi;
9a799d71 583 unsigned int i;
9a799d71
AK		 584
585 i = rx_ring->next_to_use;
3a581073 586 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 587
588 while (cleaned_count--) {
589 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
590
762f4c57 591 if (!bi->page_dma &&
6e455b89 592 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 593 if (!bi->page) {
762f4c57
JB		 594 bi->page = alloc_page(GFP_ATOMIC);
595 if (!bi->page) {
596 adapter->alloc_rx_page_failed++;
597 goto no_buffers;
598 }
599 bi->page_offset = 0;
600 } else {
601 /* use a half page if we're re-using */
602 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 603 }
762f4c57
JB		 604
605 bi->page_dma = pci_map_page(pdev, bi->page,
606 bi->page_offset,
607 (PAGE_SIZE / 2),
608 PCI_DMA_FROMDEVICE);
9a799d71
AK		 609 }
610
3a581073 611 if (!bi->skb) {
5ecc3614 612 struct sk_buff *skb;
4f57ca6e
JB		 613 skb = netdev_alloc_skb(adapter->netdev,
614 (rx_ring->rx_buf_len +
615 NET_IP_ALIGN));
9a799d71
AK		 616
617 if (!skb) {
618 adapter->alloc_rx_buff_failed++;
619 goto no_buffers;
620 }
621
622 /*
623 * Make buffer alignment 2 beyond a 16 byte boundary
624 * this will result in a 16 byte aligned IP header after
625 * the 14 byte MAC header is removed
626 */
627 skb_reserve(skb, NET_IP_ALIGN);
628
3a581073 629 bi->skb = skb;
4f57ca6e
JB		 630 bi->dma = pci_map_single(pdev, skb->data,
631 rx_ring->rx_buf_len,
3a581073 632 PCI_DMA_FROMDEVICE);
9a799d71
AK		 633 }
634 /* Refresh the desc even if buffer_addrs didn't change because
635 * each write-back erases this info. */
6e455b89 636 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 637 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
638 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 639 } else {
3a581073 640 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 641 }
642
643 i++;
644 if (i == rx_ring->count)
645 i = 0;
3a581073 646 bi = &rx_ring->rx_buffer_info[i];
9a799d71 647 }
7c6e0a43 648
9a799d71
AK		 649no_buffers:
650 if (rx_ring->next_to_use != i) {
651 rx_ring->next_to_use = i;
652 if (i-- == 0)
653 i = (rx_ring->count - 1);
654
e8e26350 655 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 656 }
657}
658
7c6e0a43
JB		 659static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
660{
661 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
662}
663
664static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
665{
666 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
667}
668
f8212f97
AD		 669static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
670{
671 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
672 IXGBE_RXDADV_RSCCNT_MASK) >>
673 IXGBE_RXDADV_RSCCNT_SHIFT;
674}
675
676/**
677 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
678 * @skb: pointer to the last skb in the rsc queue
679 *
680 * This function changes a queue full of hw rsc buffers into a completed
681 * packet. It uses the ->prev pointers to find the first packet and then
682 * turns it into the frag list owner.
683 **/
684static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
685{
686 unsigned int frag_list_size = 0;
687
688 while (skb->prev) {
689 struct sk_buff *prev = skb->prev;
690 frag_list_size += skb->len;
691 skb->prev = NULL;
692 skb = prev;
693 }
694
695 skb_shinfo(skb)->frag_list = skb->next;
696 skb->next = NULL;
697 skb->len += frag_list_size;
698 skb->data_len += frag_list_size;
699 skb->truesize += frag_list_size;
700 return skb;
701}
702
78b6f4ce 703static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 704 struct ixgbe_ring *rx_ring,
705 int *work_done, int work_to_do)
9a799d71 706{
78b6f4ce 707 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 708 struct pci_dev *pdev = adapter->pdev;
709 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
710 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
711 struct sk_buff *skb;
f8212f97 712 unsigned int i, rsc_count = 0;
7c6e0a43 713 u32 len, staterr;
177db6ff
MC		 714 u16 hdr_info;
715 bool cleaned = false;
9a799d71 716 int cleaned_count = 0;
d2f4fbe2 717 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 718#ifdef IXGBE_FCOE
719 int ddp_bytes = 0;
720#endif /* IXGBE_FCOE */
9a799d71
AK		 721
722 i = rx_ring->next_to_clean;
9a799d71
AK		 723 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
724 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
725 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 726
727 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 728 u32 upper_len = 0;
9a799d71
AK		 729 if (*work_done >= work_to_do)
730 break;
731 (*work_done)++;
732
6e455b89 733 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 734 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
735 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 736 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 737 if (hdr_info & IXGBE_RXDADV_SPH)
738 adapter->rx_hdr_split++;
739 if (len > IXGBE_RX_HDR_SIZE)
740 len = IXGBE_RX_HDR_SIZE;
741 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 742 } else {
9a799d71 743 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 744 }
9a799d71
AK		 745
746 cleaned = true;
747 skb = rx_buffer_info->skb;
748 prefetch(skb->data - NET_IP_ALIGN);
749 rx_buffer_info->skb = NULL;
750
21fa4e66 751 if (rx_buffer_info->dma) {
9a799d71 752 pci_unmap_single(pdev, rx_buffer_info->dma,
5ecc3614 753 rx_ring->rx_buf_len,
b4617240 754 PCI_DMA_FROMDEVICE);
4f57ca6e 755 rx_buffer_info->dma = 0;
9a799d71
AK		 756 skb_put(skb, len);
757 }
758
759 if (upper_len) {
760 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 761 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 762 rx_buffer_info->page_dma = 0;
763 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 764 rx_buffer_info->page,
765 rx_buffer_info->page_offset,
766 upper_len);
767
768 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
769 (page_count(rx_buffer_info->page) != 1))
770 rx_buffer_info->page = NULL;
771 else
772 get_page(rx_buffer_info->page);
9a799d71
AK		 773
774 skb->len += upper_len;
775 skb->data_len += upper_len;
776 skb->truesize += upper_len;
777 }
778
779 i++;
780 if (i == rx_ring->count)
781 i = 0;
9a799d71
AK		 782
783 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
784 prefetch(next_rxd);
9a799d71 785 cleaned_count++;
f8212f97 786
0c19d6af 787 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 788 rsc_count = ixgbe_get_rsc_count(rx_desc);
789
790 if (rsc_count) {
791 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
792 IXGBE_RXDADV_NEXTP_SHIFT;
793 next_buffer = &rx_ring->rx_buffer_info[nextp];
794 rx_ring->rsc_count += (rsc_count - 1);
795 } else {
796 next_buffer = &rx_ring->rx_buffer_info[i];
797 }
798
9a799d71 799 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97
AD		 800 if (skb->prev)
801 skb = ixgbe_transform_rsc_queue(skb);
9a799d71
AK		 802 rx_ring->stats.packets++;
803 rx_ring->stats.bytes += skb->len;
804 } else {
6e455b89 805 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 806 rx_buffer_info->skb = next_buffer->skb;
807 rx_buffer_info->dma = next_buffer->dma;
808 next_buffer->skb = skb;
809 next_buffer->dma = 0;
810 } else {
811 skb->next = next_buffer->skb;
812 skb->next->prev = skb;
813 }
9a799d71
AK		 814 adapter->non_eop_descs++;
815 goto next_desc;
816 }
817
818 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
819 dev_kfree_skb_irq(skb);
820 goto next_desc;
821 }
822
8bae1b2b 823 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 824
825 /* probably a little skewed due to removing CRC */
826 total_rx_bytes += skb->len;
827 total_rx_packets++;
828
74ce8dd2 829 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 830#ifdef IXGBE_FCOE
831 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 832 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
833 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
834 if (!ddp_bytes)
332d4a7d 835 goto next_desc;
3d8fd385 836 }
332d4a7d 837#endif /* IXGBE_FCOE */
fdaff1ce 838 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 839
840next_desc:
841 rx_desc->wb.upper.status_error = 0;
842
843 /* return some buffers to hardware, one at a time is too slow */
844 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
845 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
846 cleaned_count = 0;
847 }
848
849 /* use prefetched values */
850 rx_desc = next_rxd;
f8212f97 851 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 852
853 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 854 }
855
9a799d71
AK		 856 rx_ring->next_to_clean = i;
857 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
858
859 if (cleaned_count)
860 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
861
3d8fd385
YZ		 862#ifdef IXGBE_FCOE
863 /* include DDPed FCoE data */
864 if (ddp_bytes > 0) {
865 unsigned int mss;
866
867 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
868 sizeof(struct fc_frame_header) -
869 sizeof(struct fcoe_crc_eof);
870 if (mss > 512)
871 mss &= ~511;
872 total_rx_bytes += ddp_bytes;
873 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
874 }
875#endif /* IXGBE_FCOE */
876
f494e8fa
AV		 877 rx_ring->total_packets += total_rx_packets;
878 rx_ring->total_bytes += total_rx_bytes;
879 adapter->net_stats.rx_bytes += total_rx_bytes;
880 adapter->net_stats.rx_packets += total_rx_packets;
881
9a799d71
AK		 882 return cleaned;
883}
884
021230d4 885static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 886/**
887 * ixgbe_configure_msix - Configure MSI-X hardware
888 * @adapter: board private structure
889 *
890 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
891 * interrupts.
892 **/
893static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
894{
021230d4
AV		 895 struct ixgbe_q_vector *q_vector;
896 int i, j, q_vectors, v_idx, r_idx;
897 u32 mask;
9a799d71 898
021230d4 899 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 900
4df10466
JB		 901 /*
902 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 903 * corresponding register.
904 */
905 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 906 q_vector = adapter->q_vector[v_idx];
021230d4
AV		 907 /* XXX for_each_bit(...) */
908 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 909 adapter->num_rx_queues);
021230d4
AV		 910
911 for (i = 0; i < q_vector->rxr_count; i++) {
912 j = adapter->rx_ring[r_idx].reg_idx;
e8e26350 913 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 914 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 915 adapter->num_rx_queues,
916 r_idx + 1);
021230d4
AV		 917 }
918 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 919 adapter->num_tx_queues);
021230d4
AV		 920
921 for (i = 0; i < q_vector->txr_count; i++) {
922 j = adapter->tx_ring[r_idx].reg_idx;
e8e26350 923 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 924 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 925 adapter->num_tx_queues,
926 r_idx + 1);
021230d4
AV		 927 }
928
021230d4 929 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 930 /* tx only */
931 q_vector->eitr = adapter->tx_eitr_param;
509ee935 932 else if (q_vector->rxr_count)
f7554a2b
NS		 933 /* rx or mixed */
934 q_vector->eitr = adapter->rx_eitr_param;
021230d4 935
fe49f04a 936 ixgbe_write_eitr(q_vector);
9a799d71
AK		 937 }
938
e8e26350
PW		 939 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
940 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
941 v_idx);
942 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
943 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 944 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
945
41fb9248 946 /* set up to autoclear timer, and the vectors */
021230d4 947 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 948 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 949 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 950}
951
f494e8fa
AV		 952enum latency_range {
953 lowest_latency = 0,
954 low_latency = 1,
955 bulk_latency = 2,
956 latency_invalid = 255
957};
958
959/**
960 * ixgbe_update_itr - update the dynamic ITR value based on statistics
961 * @adapter: pointer to adapter
962 * @eitr: eitr setting (ints per sec) to give last timeslice
963 * @itr_setting: current throttle rate in ints/second
964 * @packets: the number of packets during this measurement interval
965 * @bytes: the number of bytes during this measurement interval
966 *
967 * Stores a new ITR value based on packets and byte
968 * counts during the last interrupt. The advantage of per interrupt
969 * computation is faster updates and more accurate ITR for the current
970 * traffic pattern. Constants in this function were computed
971 * based on theoretical maximum wire speed and thresholds were set based
972 * on testing data as well as attempting to minimize response time
973 * while increasing bulk throughput.
974 * this functionality is controlled by the InterruptThrottleRate module
975 * parameter (see ixgbe_param.c)
976 **/
977static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 978 u32 eitr, u8 itr_setting,
979 int packets, int bytes)
f494e8fa
AV		 980{
981 unsigned int retval = itr_setting;
982 u32 timepassed_us;
983 u64 bytes_perint;
984
985 if (packets == 0)
986 goto update_itr_done;
987
988
989 /* simple throttlerate management
990 * 0-20MB/s lowest (100000 ints/s)
991 * 20-100MB/s low (20000 ints/s)
992 * 100-1249MB/s bulk (8000 ints/s)
993 */
994 /* what was last interrupt timeslice? */
995 timepassed_us = 1000000/eitr;
996 bytes_perint = bytes / timepassed_us; /* bytes/usec */
997
998 switch (itr_setting) {
999 case lowest_latency:
1000 if (bytes_perint > adapter->eitr_low)
1001 retval = low_latency;
1002 break;
1003 case low_latency:
1004 if (bytes_perint > adapter->eitr_high)
1005 retval = bulk_latency;
1006 else if (bytes_perint <= adapter->eitr_low)
1007 retval = lowest_latency;
1008 break;
1009 case bulk_latency:
1010 if (bytes_perint <= adapter->eitr_high)
1011 retval = low_latency;
1012 break;
1013 }
1014
1015update_itr_done:
1016 return retval;
1017}
1018
509ee935
JB		 1019/**
1020 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1021 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1022 *
1023 * This function is made to be called by ethtool and by the driver
1024 * when it needs to update EITR registers at runtime. Hardware
1025 * specific quirks/differences are taken care of here.
1026 */
fe49f04a 1027void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1028{
fe49f04a 1029 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1030 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1031 int v_idx = q_vector->v_idx;
1032 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1033
509ee935
JB		 1034 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1035 /* must write high and low 16 bits to reset counter */
1036 itr_reg |= (itr_reg << 16);
1037 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1038 /*
1039 * set the WDIS bit to not clear the timer bits and cause an
1040 * immediate assertion of the interrupt
1041 */
1042 itr_reg |= IXGBE_EITR_CNT_WDIS;
1043 }
1044 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1045}
1046
f494e8fa
AV		 1047static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1048{
1049 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1050 u32 new_itr;
1051 u8 current_itr, ret_itr;
fe49f04a 1052 int i, r_idx;
f494e8fa
AV		 1053 struct ixgbe_ring *rx_ring, *tx_ring;
1054
1055 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1056 for (i = 0; i < q_vector->txr_count; i++) {
1057 tx_ring = &(adapter->tx_ring[r_idx]);
1058 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1059 q_vector->tx_itr,
1060 tx_ring->total_packets,
1061 tx_ring->total_bytes);
f494e8fa
AV		 1062 /* if the result for this queue would decrease interrupt
1063 * rate for this vector then use that result */
30efa5a3 1064 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1065 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1066 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1067 r_idx + 1);
f494e8fa
AV		 1068 }
1069
1070 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1071 for (i = 0; i < q_vector->rxr_count; i++) {
1072 rx_ring = &(adapter->rx_ring[r_idx]);
1073 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1074 q_vector->rx_itr,
1075 rx_ring->total_packets,
1076 rx_ring->total_bytes);
f494e8fa
AV		 1077 /* if the result for this queue would decrease interrupt
1078 * rate for this vector then use that result */
30efa5a3 1079 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1080 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1081 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1082 r_idx + 1);
f494e8fa
AV		 1083 }
1084
30efa5a3 1085 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1086
1087 switch (current_itr) {
1088 /* counts and packets in update_itr are dependent on these numbers */
1089 case lowest_latency:
1090 new_itr = 100000;
1091 break;
1092 case low_latency:
1093 new_itr = 20000; /* aka hwitr = ~200 */
1094 break;
1095 case bulk_latency:
1096 default:
1097 new_itr = 8000;
1098 break;
1099 }
1100
1101 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1102 /* do an exponential smoothing */
1103 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1104
1105 /* save the algorithm value here, not the smoothed one */
1106 q_vector->eitr = new_itr;
fe49f04a
AD		 1107
1108 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1109 }
1110
1111 return;
1112}
1113
0befdb3e
JB		 1114static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1115{
1116 struct ixgbe_hw *hw = &adapter->hw;
1117
1118 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1119 (eicr & IXGBE_EICR_GPI_SDP1)) {
1120 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1121 /* write to clear the interrupt */
1122 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1123 }
1124}
cf8280ee 1125
e8e26350
PW		 1126static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1127{
1128 struct ixgbe_hw *hw = &adapter->hw;
1129
1130 if (eicr & IXGBE_EICR_GPI_SDP1) {
1131 /* Clear the interrupt */
1132 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1133 schedule_work(&adapter->multispeed_fiber_task);
1134 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1135 /* Clear the interrupt */
1136 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1137 schedule_work(&adapter->sfp_config_module_task);
1138 } else {
1139 /* Interrupt isn't for us... */
1140 return;
1141 }
1142}
1143
cf8280ee
JB		 1144static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1145{
1146 struct ixgbe_hw *hw = &adapter->hw;
1147
1148 adapter->lsc_int++;
1149 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1150 adapter->link_check_timeout = jiffies;
1151 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1152 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1153 schedule_work(&adapter->watchdog_task);
1154 }
1155}
1156
9a799d71
AK		 1157static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1158{
1159 struct net_device *netdev = data;
1160 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1161 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1162 u32 eicr;
1163
1164 /*
1165 * Workaround for Silicon errata. Use clear-by-write instead
1166 * of clear-by-read. Reading with EICS will return the
1167 * interrupt causes without clearing, which later be done
1168 * with the write to EICR.
1169 */
1170 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1171 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1172
cf8280ee
JB		 1173 if (eicr & IXGBE_EICR_LSC)
1174 ixgbe_check_lsc(adapter);
d4f80882 1175
e8e26350
PW		 1176 if (hw->mac.type == ixgbe_mac_82598EB)
1177 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1178
c4cf55e5 1179 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1180 ixgbe_check_sfp_event(adapter, eicr);
c4cf55e5
PWJ		 1181
1182 /* Handle Flow Director Full threshold interrupt */
1183 if (eicr & IXGBE_EICR_FLOW_DIR) {
1184 int i;
1185 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1186 /* Disable transmits before FDIR Re-initialization */
1187 netif_tx_stop_all_queues(netdev);
1188 for (i = 0; i < adapter->num_tx_queues; i++) {
1189 struct ixgbe_ring *tx_ring =
1190 &adapter->tx_ring[i];
1191 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1192 &tx_ring->reinit_state))
1193 schedule_work(&adapter->fdir_reinit_task);
1194 }
1195 }
1196 }
d4f80882
AV		 1197 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1198 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1199
1200 return IRQ_HANDLED;
1201}
1202
fe49f04a
AD		 1203static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1204 u64 qmask)
1205{
1206 u32 mask;
1207
1208 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1209 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1210 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1211 } else {
1212 mask = (qmask & 0xFFFFFFFF);
1213 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1214 mask = (qmask >> 32);
1215 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1216 }
1217 /* skip the flush */
1218}
1219
1220static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1221 u64 qmask)
1222{
1223 u32 mask;
1224
1225 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1226 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1227 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1228 } else {
1229 mask = (qmask & 0xFFFFFFFF);
1230 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1231 mask = (qmask >> 32);
1232 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1233 }
1234 /* skip the flush */
1235}
1236
9a799d71
AK		 1237static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1238{
021230d4
AV		 1239 struct ixgbe_q_vector *q_vector = data;
1240 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1241 struct ixgbe_ring *tx_ring;
021230d4
AV		 1242 int i, r_idx;
1243
1244 if (!q_vector->txr_count)
1245 return IRQ_HANDLED;
1246
1247 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1248 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 1249 tx_ring = &(adapter->tx_ring[r_idx]);
3a581073
JB		 1250 tx_ring->total_bytes = 0;
1251 tx_ring->total_packets = 0;
021230d4 1252 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1253 r_idx + 1);
021230d4 1254 }
9a799d71 1255
91281fd3
AD		 1256 /* disable interrupts on this vector only */
1257 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1258 napi_schedule(&q_vector->napi);
1259
9a799d71
AK		 1260 return IRQ_HANDLED;
1261}
1262
021230d4
AV		 1263/**
1264 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1265 * @irq: unused
1266 * @data: pointer to our q_vector struct for this interrupt vector
1267 **/
9a799d71
AK		 1268static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1269{
021230d4
AV		 1270 struct ixgbe_q_vector *q_vector = data;
1271 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1272 struct ixgbe_ring *rx_ring;
021230d4 1273 int r_idx;
30efa5a3 1274 int i;
021230d4
AV		 1275
1276 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 1277 for (i = 0; i < q_vector->rxr_count; i++) {
1278 rx_ring = &(adapter->rx_ring[r_idx]);
1279 rx_ring->total_bytes = 0;
1280 rx_ring->total_packets = 0;
1281 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1282 r_idx + 1);
1283 }
1284
021230d4
AV		 1285 if (!q_vector->rxr_count)
1286 return IRQ_HANDLED;
1287
30efa5a3 1288 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1289 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 1290 /* disable interrupts on this vector only */
fe49f04a 1291 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
288379f0 1292 napi_schedule(&q_vector->napi);
021230d4
AV		 1293
1294 return IRQ_HANDLED;
1295}
1296
1297static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1298{
91281fd3
AD		 1299 struct ixgbe_q_vector *q_vector = data;
1300 struct ixgbe_adapter *adapter = q_vector->adapter;
1301 struct ixgbe_ring *ring;
1302 int r_idx;
1303 int i;
1304
1305 if (!q_vector->txr_count && !q_vector->rxr_count)
1306 return IRQ_HANDLED;
1307
1308 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1309 for (i = 0; i < q_vector->txr_count; i++) {
1310 ring = &(adapter->tx_ring[r_idx]);
1311 ring->total_bytes = 0;
1312 ring->total_packets = 0;
1313 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1314 r_idx + 1);
1315 }
1316
1317 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1318 for (i = 0; i < q_vector->rxr_count; i++) {
1319 ring = &(adapter->rx_ring[r_idx]);
1320 ring->total_bytes = 0;
1321 ring->total_packets = 0;
1322 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1323 r_idx + 1);
1324 }
1325
1326 /* disable interrupts on this vector only */
1327 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1328 napi_schedule(&q_vector->napi);
9a799d71 1329
9a799d71
AK		 1330 return IRQ_HANDLED;
1331}
1332
021230d4
AV		 1333/**
1334 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1335 * @napi: napi struct with our devices info in it
1336 * @budget: amount of work driver is allowed to do this pass, in packets
1337 *
f0848276
JB		 1338 * This function is optimized for cleaning one queue only on a single
1339 * q_vector!!!
021230d4 1340 **/
9a799d71
AK		 1341static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1342{
021230d4 1343 struct ixgbe_q_vector *q_vector =
b4617240 1344 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1345 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1346 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1347 int work_done = 0;
021230d4 1348 long r_idx;
9a799d71 1349
021230d4 1350 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1351 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1352#ifdef CONFIG_IXGBE_DCA
bd0362dd 1353 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1354 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1355#endif
9a799d71 1356
78b6f4ce 1357 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1358
021230d4
AV		 1359 /* If all Rx work done, exit the polling mode */
1360 if (work_done < budget) {
288379f0 1361 napi_complete(napi);
f7554a2b 1362 if (adapter->rx_itr_setting & 1)
f494e8fa 1363 ixgbe_set_itr_msix(q_vector);
9a799d71 1364 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1365 ixgbe_irq_enable_queues(adapter,
1366 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1367 }
1368
1369 return work_done;
1370}
1371
f0848276 1372/**
91281fd3 1373 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1374 * @napi: napi struct with our devices info in it
1375 * @budget: amount of work driver is allowed to do this pass, in packets
1376 *
1377 * This function will clean more than one rx queue associated with a
1378 * q_vector.
1379 **/
91281fd3 1380static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1381{
1382 struct ixgbe_q_vector *q_vector =
1383 container_of(napi, struct ixgbe_q_vector, napi);
1384 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1385 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1386 int work_done = 0, i;
1387 long r_idx;
91281fd3
AD		 1388 bool tx_clean_complete = true;
1389
1390 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1391 for (i = 0; i < q_vector->txr_count; i++) {
1392 ring = &(adapter->tx_ring[r_idx]);
1393#ifdef CONFIG_IXGBE_DCA
1394 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1395 ixgbe_update_tx_dca(adapter, ring);
1396#endif
1397 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1398 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1399 r_idx + 1);
1400 }
f0848276
JB		 1401
1402 /* attempt to distribute budget to each queue fairly, but don't allow
1403 * the budget to go below 1 because we'll exit polling */
1404 budget /= (q_vector->rxr_count ?: 1);
1405 budget = max(budget, 1);
1406 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1407 for (i = 0; i < q_vector->rxr_count; i++) {
91281fd3 1408 ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1409#ifdef CONFIG_IXGBE_DCA
f0848276 1410 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1411 ixgbe_update_rx_dca(adapter, ring);
f0848276 1412#endif
91281fd3 1413 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276
JB		 1414 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1415 r_idx + 1);
1416 }
1417
1418 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
91281fd3 1419 ring = &(adapter->rx_ring[r_idx]);
f0848276 1420 /* If all Rx work done, exit the polling mode */
7f821875 1421 if (work_done < budget) {
288379f0 1422 napi_complete(napi);
f7554a2b 1423 if (adapter->rx_itr_setting & 1)
f0848276
JB		 1424 ixgbe_set_itr_msix(q_vector);
1425 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1426 ixgbe_irq_enable_queues(adapter,
1427 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1428 return 0;
1429 }
1430
1431 return work_done;
1432}
91281fd3
AD		 1433
1434/**
1435 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1436 * @napi: napi struct with our devices info in it
1437 * @budget: amount of work driver is allowed to do this pass, in packets
1438 *
1439 * This function is optimized for cleaning one queue only on a single
1440 * q_vector!!!
1441 **/
1442static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1443{
1444 struct ixgbe_q_vector *q_vector =
1445 container_of(napi, struct ixgbe_q_vector, napi);
1446 struct ixgbe_adapter *adapter = q_vector->adapter;
1447 struct ixgbe_ring *tx_ring = NULL;
1448 int work_done = 0;
1449 long r_idx;
1450
1451 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1452 tx_ring = &(adapter->tx_ring[r_idx]);
1453#ifdef CONFIG_IXGBE_DCA
1454 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1455 ixgbe_update_tx_dca(adapter, tx_ring);
1456#endif
1457
1458 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1459 work_done = budget;
1460
f7554a2b 1461 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 1462 if (work_done < budget) {
1463 napi_complete(napi);
f7554a2b 1464 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 1465 ixgbe_set_itr_msix(q_vector);
1466 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1467 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1468 }
1469
1470 return work_done;
1471}
1472
021230d4 1473static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1474 int r_idx)
021230d4 1475{
7a921c93
AD		 1476 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1477
1478 set_bit(r_idx, q_vector->rxr_idx);
1479 q_vector->rxr_count++;
021230d4
AV		 1480}
1481
1482static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 1483 int t_idx)
021230d4 1484{
7a921c93
AD		 1485 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1486
1487 set_bit(t_idx, q_vector->txr_idx);
1488 q_vector->txr_count++;
021230d4
AV		 1489}
1490
9a799d71 1491/**
021230d4
AV		 1492 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1493 * @adapter: board private structure to initialize
1494 * @vectors: allotted vector count for descriptor rings
9a799d71 1495 *
021230d4
AV		 1496 * This function maps descriptor rings to the queue-specific vectors
1497 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1498 * one vector per ring/queue, but on a constrained vector budget, we
1499 * group the rings as "efficiently" as possible. You would add new
1500 * mapping configurations in here.
9a799d71 1501 **/
021230d4 1502static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1503 int vectors)
021230d4
AV		 1504{
1505 int v_start = 0;
1506 int rxr_idx = 0, txr_idx = 0;
1507 int rxr_remaining = adapter->num_rx_queues;
1508 int txr_remaining = adapter->num_tx_queues;
1509 int i, j;
1510 int rqpv, tqpv;
1511 int err = 0;
1512
1513 /* No mapping required if MSI-X is disabled. */
1514 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1515 goto out;
9a799d71 1516
021230d4
AV		 1517 /*
1518 * The ideal configuration...
1519 * We have enough vectors to map one per queue.
1520 */
1521 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1522 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1523 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1524
021230d4
AV		 1525 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1526 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1527
9a799d71 1528 goto out;
021230d4 1529 }
9a799d71 1530
021230d4
AV		 1531 /*
1532 * If we don't have enough vectors for a 1-to-1
1533 * mapping, we'll have to group them so there are
1534 * multiple queues per vector.
1535 */
1536 /* Re-adjusting *qpv takes care of the remainder. */
1537 for (i = v_start; i < vectors; i++) {
1538 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1539 for (j = 0; j < rqpv; j++) {
1540 map_vector_to_rxq(adapter, i, rxr_idx);
1541 rxr_idx++;
1542 rxr_remaining--;
1543 }
1544 }
1545 for (i = v_start; i < vectors; i++) {
1546 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1547 for (j = 0; j < tqpv; j++) {
1548 map_vector_to_txq(adapter, i, txr_idx);
1549 txr_idx++;
1550 txr_remaining--;
9a799d71 1551 }
9a799d71
AK		 1552 }
1553
021230d4
AV		 1554out:
1555 return err;
1556}
1557
1558/**
1559 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1560 * @adapter: board private structure
1561 *
1562 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1563 * interrupts from the kernel.
1564 **/
1565static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1566{
1567 struct net_device *netdev = adapter->netdev;
1568 irqreturn_t (*handler)(int, void *);
1569 int i, vector, q_vectors, err;
cb13fc20 1570 int ri=0, ti=0;
021230d4
AV		 1571
1572 /* Decrement for Other and TCP Timer vectors */
1573 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1574
1575 /* Map the Tx/Rx rings to the vectors we were allotted. */
1576 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1577 if (err)
1578 goto out;
1579
1580#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1581 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1582 &ixgbe_msix_clean_many)
021230d4 1583 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 1584 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 1585
1586 if(handler == &ixgbe_msix_clean_rx) {
1587 sprintf(adapter->name[vector], "%s-%s-%d",
1588 netdev->name, "rx", ri++);
1589 }
1590 else if(handler == &ixgbe_msix_clean_tx) {
1591 sprintf(adapter->name[vector], "%s-%s-%d",
1592 netdev->name, "tx", ti++);
1593 }
1594 else
1595 sprintf(adapter->name[vector], "%s-%s-%d",
1596 netdev->name, "TxRx", vector);
1597
021230d4 1598 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1599 handler, 0, adapter->name[vector],
7a921c93 1600 adapter->q_vector[vector]);
9a799d71
AK		 1601 if (err) {
1602 DPRINTK(PROBE, ERR,
b4617240
PW		 1603 "request_irq failed for MSIX interrupt "
1604 "Error: %d\n", err);
021230d4 1605 goto free_queue_irqs;
9a799d71 1606 }
9a799d71
AK		 1607 }
1608
021230d4
AV		 1609 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1610 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1611 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1612 if (err) {
1613 DPRINTK(PROBE, ERR,
1614 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1615 goto free_queue_irqs;
9a799d71
AK		 1616 }
1617
9a799d71
AK		 1618 return 0;
1619
021230d4
AV		 1620free_queue_irqs:
1621 for (i = vector - 1; i >= 0; i--)
1622 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 1623 adapter->q_vector[i]);
021230d4
AV		 1624 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1625 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1626 kfree(adapter->msix_entries);
1627 adapter->msix_entries = NULL;
021230d4 1628out:
9a799d71
AK		 1629 return err;
1630}
1631
f494e8fa
AV		 1632static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1633{
7a921c93 1634 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 1635 u8 current_itr;
1636 u32 new_itr = q_vector->eitr;
1637 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1638 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1639
30efa5a3 1640 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1641 q_vector->tx_itr,
1642 tx_ring->total_packets,
1643 tx_ring->total_bytes);
30efa5a3 1644 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1645 q_vector->rx_itr,
1646 rx_ring->total_packets,
1647 rx_ring->total_bytes);
f494e8fa 1648
30efa5a3 1649 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1650
1651 switch (current_itr) {
1652 /* counts and packets in update_itr are dependent on these numbers */
1653 case lowest_latency:
1654 new_itr = 100000;
1655 break;
1656 case low_latency:
1657 new_itr = 20000; /* aka hwitr = ~200 */
1658 break;
1659 case bulk_latency:
1660 new_itr = 8000;
1661 break;
1662 default:
1663 break;
1664 }
1665
1666 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1667 /* do an exponential smoothing */
1668 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1669
1670 /* save the algorithm value here, not the smoothed one */
1671 q_vector->eitr = new_itr;
fe49f04a
AD		 1672
1673 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1674 }
1675
1676 return;
1677}
1678
79aefa45
AD		 1679/**
1680 * ixgbe_irq_enable - Enable default interrupt generation settings
1681 * @adapter: board private structure
1682 **/
1683static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1684{
1685 u32 mask;
835462fc
NS		 1686
1687 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 1688 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1689 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1690 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1691 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1692 mask |= IXGBE_EIMS_GPI_SDP1;
1693 mask |= IXGBE_EIMS_GPI_SDP2;
1694 }
c4cf55e5
PWJ		 1695 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1696 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1697 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 1698
79aefa45 1699 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 1700 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45
AD		 1701 IXGBE_WRITE_FLUSH(&adapter->hw);
1702}
021230d4 1703
9a799d71 1704/**
021230d4 1705 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1706 * @irq: interrupt number
1707 * @data: pointer to a network interface device structure
9a799d71
AK		 1708 **/
1709static irqreturn_t ixgbe_intr(int irq, void *data)
1710{
1711 struct net_device *netdev = data;
1712 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1713 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 1714 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 1715 u32 eicr;
1716
54037505
DS		 1717 /*
1718 * Workaround for silicon errata. Mask the interrupts
1719 * before the read of EICR.
1720 */
1721 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1722
021230d4
AV		 1723 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1724 * therefore no explict interrupt disable is necessary */
1725 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1726 if (!eicr) {
1727 /* shared interrupt alert!
1728 * make sure interrupts are enabled because the read will
1729 * have disabled interrupts due to EIAM */
1730 ixgbe_irq_enable(adapter);
9a799d71 1731 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1732 }
9a799d71 1733
cf8280ee
JB		 1734 if (eicr & IXGBE_EICR_LSC)
1735 ixgbe_check_lsc(adapter);
021230d4 1736
e8e26350
PW		 1737 if (hw->mac.type == ixgbe_mac_82599EB)
1738 ixgbe_check_sfp_event(adapter, eicr);
1739
0befdb3e
JB		 1740 ixgbe_check_fan_failure(adapter, eicr);
1741
7a921c93 1742 if (napi_schedule_prep(&(q_vector->napi))) {
f494e8fa
AV		 1743 adapter->tx_ring[0].total_packets = 0;
1744 adapter->tx_ring[0].total_bytes = 0;
1745 adapter->rx_ring[0].total_packets = 0;
1746 adapter->rx_ring[0].total_bytes = 0;
021230d4 1747 /* would disable interrupts here but EIAM disabled it */
7a921c93 1748 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 1749 }
1750
1751 return IRQ_HANDLED;
1752}
1753
021230d4
AV		 1754static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1755{
1756 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1757
1758 for (i = 0; i < q_vectors; i++) {
7a921c93 1759 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 1760 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1761 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1762 q_vector->rxr_count = 0;
1763 q_vector->txr_count = 0;
1764 }
1765}
1766
9a799d71
AK		 1767/**
1768 * ixgbe_request_irq - initialize interrupts
1769 * @adapter: board private structure
1770 *
1771 * Attempts to configure interrupts using the best available
1772 * capabilities of the hardware and kernel.
1773 **/
021230d4 1774static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1775{
1776 struct net_device *netdev = adapter->netdev;
021230d4 1777 int err;
9a799d71 1778
021230d4
AV		 1779 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1780 err = ixgbe_request_msix_irqs(adapter);
1781 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1782 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
b4617240 1783 netdev->name, netdev);
021230d4
AV		 1784 } else {
1785 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
b4617240 1786 netdev->name, netdev);
9a799d71
AK		 1787 }
1788
9a799d71
AK		 1789 if (err)
1790 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1791
9a799d71
AK		 1792 return err;
1793}
1794
1795static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1796{
1797 struct net_device *netdev = adapter->netdev;
1798
1799 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1800 int i, q_vectors;
9a799d71 1801
021230d4
AV		 1802 q_vectors = adapter->num_msix_vectors;
1803
1804 i = q_vectors - 1;
9a799d71 1805 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1806
021230d4
AV		 1807 i--;
1808 for (; i >= 0; i--) {
1809 free_irq(adapter->msix_entries[i].vector,
7a921c93 1810 adapter->q_vector[i]);
021230d4
AV		 1811 }
1812
1813 ixgbe_reset_q_vectors(adapter);
1814 } else {
1815 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1816 }
1817}
1818
22d5a71b
JB		 1819/**
1820 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1821 * @adapter: board private structure
1822 **/
1823static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1824{
835462fc
NS		 1825 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1826 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1827 } else {
1828 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1829 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 1830 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
22d5a71b
JB		 1831 }
1832 IXGBE_WRITE_FLUSH(&adapter->hw);
1833 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1834 int i;
1835 for (i = 0; i < adapter->num_msix_vectors; i++)
1836 synchronize_irq(adapter->msix_entries[i].vector);
1837 } else {
1838 synchronize_irq(adapter->pdev->irq);
1839 }
1840}
1841
9a799d71
AK		 1842/**
1843 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1844 *
1845 **/
1846static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1847{
9a799d71
AK		 1848 struct ixgbe_hw *hw = &adapter->hw;
1849
021230d4 1850 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
f7554a2b 1851 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 1852
e8e26350
PW		 1853 ixgbe_set_ivar(adapter, 0, 0, 0);
1854 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 1855
1856 map_vector_to_rxq(adapter, 0, 0);
1857 map_vector_to_txq(adapter, 0, 0);
1858
1859 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1860}
1861
1862/**
3a581073 1863 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1864 * @adapter: board private structure
1865 *
1866 * Configure the Tx unit of the MAC after a reset.
1867 **/
1868static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1869{
12207e49 1870 u64 tdba;
9a799d71 1871 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1872 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1873
1874 /* Setup the HW Tx Head and Tail descriptor pointers */
1875 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1876 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1877 j = ring->reg_idx;
1878 tdba = ring->dma;
1879 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1880 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 1881 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 1882 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1883 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1884 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1885 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1886 adapter->tx_ring[i].head = IXGBE_TDH(j);
1887 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1888 /* Disable Tx Head Writeback RO bit, since this hoses
1889 * bookkeeping if things aren't delivered in order.
1890 */
e01c31a5 1891 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1892 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1893 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1894 }
e8e26350
PW		 1895 if (hw->mac.type == ixgbe_mac_82599EB) {
1896 /* We enable 8 traffic classes, DCB only */
1897 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1898 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1899 IXGBE_MTQC_8TC_8TQ));
1900 }
9a799d71
AK		 1901}
1902
e8e26350 1903#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 1904
a6616b42
YZ		 1905static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
1906 struct ixgbe_ring *rx_ring)
cc41ac7c 1907{
cc41ac7c 1908 u32 srrctl;
a6616b42 1909 int index;
0cefafad 1910 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 1911
a6616b42
YZ		 1912 index = rx_ring->reg_idx;
1913 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1914 unsigned long mask;
0cefafad 1915 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 1916 index = index & mask;
cc41ac7c 1917 }
cc41ac7c
JB		 1918 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1919
1920 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1921 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1922
afafd5b0
AD		 1923 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1924 IXGBE_SRRCTL_BSIZEHDR_MASK;
1925
6e455b89 1926 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 1927#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1928 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1929#else
1930 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1931#endif
cc41ac7c 1932 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 1933 } else {
afafd5b0
AD		 1934 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1935 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 1936 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 1937 }
e8e26350 1938
cc41ac7c
JB		 1939 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1940}
9a799d71 1941
0cefafad
JB		 1942static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1943{
1944 u32 mrqc = 0;
1945 int mask;
1946
1947 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1948 return mrqc;
1949
1950 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1951#ifdef CONFIG_IXGBE_DCB
1952 | IXGBE_FLAG_DCB_ENABLED
1953#endif
1954 );
1955
1956 switch (mask) {
1957 case (IXGBE_FLAG_RSS_ENABLED):
1958 mrqc = IXGBE_MRQC_RSSEN;
1959 break;
1960#ifdef CONFIG_IXGBE_DCB
1961 case (IXGBE_FLAG_DCB_ENABLED):
1962 mrqc = IXGBE_MRQC_RT8TCEN;
1963 break;
1964#endif /* CONFIG_IXGBE_DCB */
1965 default:
1966 break;
1967 }
1968
1969 return mrqc;
1970}
1971
9a799d71 1972/**
3a581073 1973 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1974 * @adapter: board private structure
1975 *
1976 * Configure the Rx unit of the MAC after a reset.
1977 **/
1978static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1979{
1980 u64 rdba;
1981 struct ixgbe_hw *hw = &adapter->hw;
a6616b42 1982 struct ixgbe_ring *rx_ring;
9a799d71
AK		 1983 struct net_device *netdev = adapter->netdev;
1984 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1985 int i, j;
9a799d71 1986 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1987 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1988 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1989 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1990 u32 fctrl, hlreg0;
509ee935 1991 u32 reta = 0, mrqc = 0;
cc41ac7c 1992 u32 rdrxctl;
f8212f97 1993 u32 rscctrl;
7c6e0a43 1994 int rx_buf_len;
9a799d71
AK		 1995
1996 /* Decide whether to use packet split mode or not */
762f4c57 1997 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 1998
1999 /* Set the RX buffer length according to the mode */
2000 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2001 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 2002 if (hw->mac.type == ixgbe_mac_82599EB) {
2003 /* PSRTYPE must be initialized in 82599 */
2004 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2005 IXGBE_PSRTYPE_UDPHDR |
2006 IXGBE_PSRTYPE_IPV4HDR |
dfa12f05
YZ		 2007 IXGBE_PSRTYPE_IPV6HDR |
2008 IXGBE_PSRTYPE_L2HDR;
e8e26350
PW		 2009 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2010 }
9a799d71 2011 } else {
0c19d6af 2012 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2013 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2014 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2015 else
7c6e0a43 2016 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 2017 }
2018
2019 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2020 fctrl |= IXGBE_FCTRL_BAM;
021230d4 2021 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 2022 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 2023 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2024
2025 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2026 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2027 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2028 else
2029 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
63f39bd1 2030#ifdef IXGBE_FCOE
f34c5c82 2031 if (netdev->features & NETIF_F_FCOE_MTU)
63f39bd1
YZ		 2032 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2033#endif
9a799d71
AK		 2034 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2035
9a799d71
AK		 2036 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2037 /* disable receives while setting up the descriptors */
2038 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2039 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2040
0cefafad
JB		 2041 /*
2042 * Setup the HW Rx Head and Tail Descriptor Pointers and
2043 * the Base and Length of the Rx Descriptor Ring
2044 */
9a799d71 2045 for (i = 0; i < adapter->num_rx_queues; i++) {
a6616b42
YZ		 2046 rx_ring = &adapter->rx_ring[i];
2047 rdba = rx_ring->dma;
2048 j = rx_ring->reg_idx;
284901a9 2049 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 2050 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2051 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2052 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2053 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
a6616b42
YZ		 2054 rx_ring->head = IXGBE_RDH(j);
2055 rx_ring->tail = IXGBE_RDT(j);
2056 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2057
6e455b89
YZ		 2058 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2059 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
1b3ff02e
PWJ		 2060 else
2061 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2062
63f39bd1 2063#ifdef IXGBE_FCOE
f34c5c82 2064 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2065 struct ixgbe_ring_feature *f;
2066 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2067 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2068 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2069 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2070 rx_ring->rx_buf_len =
2071 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2072 }
63f39bd1
YZ		 2073 }
2074
2075#endif /* IXGBE_FCOE */
a6616b42 2076 ixgbe_configure_srrctl(adapter, rx_ring);
9a799d71
AK		 2077 }
2078
e8e26350
PW		 2079 if (hw->mac.type == ixgbe_mac_82598EB) {
2080 /*
2081 * For VMDq support of different descriptor types or
2082 * buffer sizes through the use of multiple SRRCTL
2083 * registers, RDRXCTL.MVMEN must be set to 1
2084 *
2085 * also, the manual doesn't mention it clearly but DCA hints
2086 * will only use queue 0's tags unless this bit is set. Side
2087 * effects of setting this bit are only that SRRCTL must be
2088 * fully programmed [0..15]
2089 */
2a41ff81
JB		 2090 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2091 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2092 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 2093 }
177db6ff 2094
e8e26350 2095 /* Program MRQC for the distribution of queues */
0cefafad 2096 mrqc = ixgbe_setup_mrqc(adapter);
e8e26350 2097
021230d4 2098 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 2099 /* Fill out redirection table */
021230d4
AV		 2100 for (i = 0, j = 0; i < 128; i++, j++) {
2101 if (j == adapter->ring_feature[RING_F_RSS].indices)
2102 j = 0;
2103 /* reta = 4-byte sliding window of
2104 * 0x00..(indices-1)(indices-1)00..etc. */
2105 reta = (reta << 8) | (j * 0x11);
2106 if ((i & 3) == 3)
2107 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 2108 }
2109
2110 /* Fill out hash function seeds */
2111 for (i = 0; i < 10; i++)
7c6e0a43 2112 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 2113
2a41ff81
JB		 2114 if (hw->mac.type == ixgbe_mac_82598EB)
2115 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 2116 /* Perform hash on these packet types */
2a41ff81
JB		 2117 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2118 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2119 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2120 | IXGBE_MRQC_RSS_FIELD_IPV6
2121 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2122 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 2123 }
2a41ff81 2124 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 2125
021230d4
AV		 2126 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2127
2128 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2129 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2130 /* Disable indicating checksum in descriptor, enables
2131 * RSS hash */
9a799d71 2132 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 2133 }
021230d4
AV		 2134 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2135 /* Enable IPv4 payload checksum for UDP fragments
2136 * if PCSD is not set */
2137 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2138 }
2139
2140 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 2141
2142 if (hw->mac.type == ixgbe_mac_82599EB) {
2143 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2144 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 2145 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 2146 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2147 }
f8212f97 2148
0c19d6af 2149 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97
AD		 2150 /* Enable 82599 HW-RSC */
2151 for (i = 0; i < adapter->num_rx_queues; i++) {
6e455b89
YZ		 2152 rx_ring = &adapter->rx_ring[i];
2153 j = rx_ring->reg_idx;
f8212f97
AD		 2154 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2155 rscctrl |= IXGBE_RSCCTL_RSCEN;
2156 /*
e76678dd
AD		 2157 * we must limit the number of descriptors so that the
2158 * total size of max desc * buf_len is not greater
2159 * than 65535
f8212f97 2160 */
6e455b89 2161 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
e76678dd
AD		 2162#if (MAX_SKB_FRAGS > 16)
2163 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2164#elif (MAX_SKB_FRAGS > 8)
f8212f97 2165 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
e76678dd
AD		 2166#elif (MAX_SKB_FRAGS > 4)
2167 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
f8212f97 2168#else
e76678dd 2169 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
f8212f97 2170#endif
e76678dd
AD		 2171 } else {
2172 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2173 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2174 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2175 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2176 else
2177 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2178 }
f8212f97
AD		 2179 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2180 }
2181 /* Disable RSC for ACK packets */
2182 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2183 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2184 }
9a799d71
AK		 2185}
2186
068c89b0
DS		 2187static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2188{
2189 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2190 struct ixgbe_hw *hw = &adapter->hw;
2191
2192 /* add VID to filter table */
2193 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2194}
2195
2196static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2197{
2198 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2199 struct ixgbe_hw *hw = &adapter->hw;
2200
2201 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2202 ixgbe_irq_disable(adapter);
2203
2204 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2205
2206 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2207 ixgbe_irq_enable(adapter);
2208
2209 /* remove VID from filter table */
2210 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2211}
2212
9a799d71 2213static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2214 struct vlan_group *grp)
9a799d71
AK		 2215{
2216 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2217 u32 ctrl;
e8e26350 2218 int i, j;
9a799d71 2219
d4f80882
AV		 2220 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2221 ixgbe_irq_disable(adapter);
9a799d71
AK		 2222 adapter->vlgrp = grp;
2223
2f90b865
AD		 2224 /*
2225 * For a DCB driver, always enable VLAN tag stripping so we can
2226 * still receive traffic from a DCB-enabled host even if we're
2227 * not in DCB mode.
2228 */
2229 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
e8e26350
PW		 2230 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2231 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2232 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2233 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2234 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2235 ctrl |= IXGBE_VLNCTRL_VFE;
9a799d71
AK		 2236 /* enable VLAN tag insert/strip */
2237 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
9a799d71
AK		 2238 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2239 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
e8e26350
PW		 2240 for (i = 0; i < adapter->num_rx_queues; i++) {
2241 j = adapter->rx_ring[i].reg_idx;
2242 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2243 ctrl |= IXGBE_RXDCTL_VME;
2244 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2245 }
9a799d71 2246 }
e8e26350 2247 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2248
d4f80882
AV		 2249 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2250 ixgbe_irq_enable(adapter);
9a799d71
AK		 2251}
2252
9a799d71
AK		 2253static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2254{
2255 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2256
2257 if (adapter->vlgrp) {
2258 u16 vid;
2259 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2260 if (!vlan_group_get_device(adapter->vlgrp, vid))
2261 continue;
2262 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2263 }
2264 }
2265}
2266
2c5645cf
CL		 2267static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2268{
2269 struct dev_mc_list *mc_ptr;
2270 u8 *addr = *mc_addr_ptr;
2271 *vmdq = 0;
2272
2273 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2274 if (mc_ptr->next)
2275 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2276 else
2277 *mc_addr_ptr = NULL;
2278
2279 return addr;
2280}
2281
9a799d71 2282/**
2c5645cf 2283 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2284 * @netdev: network interface device structure
2285 *
2c5645cf
CL		 2286 * The set_rx_method entry point is called whenever the unicast/multicast
2287 * address list or the network interface flags are updated. This routine is
2288 * responsible for configuring the hardware for proper unicast, multicast and
2289 * promiscuous mode.
9a799d71 2290 **/
2c5645cf 2291static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2292{
2293 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2294 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 2295 u32 fctrl, vlnctrl;
2c5645cf
CL		 2296 u8 *addr_list = NULL;
2297 int addr_count = 0;
9a799d71
AK		 2298
2299 /* Check for Promiscuous and All Multicast modes */
2300
2301 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 2302 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 2303
2304 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2305 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2306 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 2307 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 2308 } else {
746b9f02
PM		 2309 if (netdev->flags & IFF_ALLMULTI) {
2310 fctrl |= IXGBE_FCTRL_MPE;
2311 fctrl &= ~IXGBE_FCTRL_UPE;
2312 } else {
2313 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2314 }
3d01625a 2315 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 2316 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2317 }
2318
2319 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 2320 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 2321
2c5645cf 2322 /* reprogram secondary unicast list */
31278e71 2323 hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
9a799d71 2324
2c5645cf
CL		 2325 /* reprogram multicast list */
2326 addr_count = netdev->mc_count;
2327 if (addr_count)
2328 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 2329 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2330 ixgbe_addr_list_itr);
9a799d71
AK		 2331}
2332
021230d4
AV		 2333static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2334{
2335 int q_idx;
2336 struct ixgbe_q_vector *q_vector;
2337 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2338
2339 /* legacy and MSI only use one vector */
2340 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2341 q_vectors = 1;
2342
2343 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2344 struct napi_struct *napi;
7a921c93 2345 q_vector = adapter->q_vector[q_idx];
f0848276 2346 napi = &q_vector->napi;
91281fd3
AD		 2347 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2348 if (!q_vector->rxr_count || !q_vector->txr_count) {
2349 if (q_vector->txr_count == 1)
2350 napi->poll = &ixgbe_clean_txonly;
2351 else if (q_vector->rxr_count == 1)
2352 napi->poll = &ixgbe_clean_rxonly;
2353 }
2354 }
f0848276
JB		 2355
2356 napi_enable(napi);
021230d4
AV		 2357 }
2358}
2359
2360static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2361{
2362 int q_idx;
2363 struct ixgbe_q_vector *q_vector;
2364 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2365
2366 /* legacy and MSI only use one vector */
2367 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2368 q_vectors = 1;
2369
2370 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 2371 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2372 napi_disable(&q_vector->napi);
2373 }
2374}
2375
7a6b6f51 2376#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2377/*
2378 * ixgbe_configure_dcb - Configure DCB hardware
2379 * @adapter: ixgbe adapter struct
2380 *
2381 * This is called by the driver on open to configure the DCB hardware.
2382 * This is also called by the gennetlink interface when reconfiguring
2383 * the DCB state.
2384 */
2385static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2386{
2387 struct ixgbe_hw *hw = &adapter->hw;
2388 u32 txdctl, vlnctrl;
2389 int i, j;
2390
2391 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2392 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2393 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2394
2395 /* reconfigure the hardware */
2396 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2397
2398 for (i = 0; i < adapter->num_tx_queues; i++) {
2399 j = adapter->tx_ring[i].reg_idx;
2400 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2401 /* PThresh workaround for Tx hang with DFP enabled. */
2402 txdctl |= 32;
2403 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2404 }
2405 /* Enable VLAN tag insert/strip */
2406 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
e8e26350
PW		 2407 if (hw->mac.type == ixgbe_mac_82598EB) {
2408 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2409 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2410 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2411 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2412 vlnctrl |= IXGBE_VLNCTRL_VFE;
2413 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2414 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2415 for (i = 0; i < adapter->num_rx_queues; i++) {
2416 j = adapter->rx_ring[i].reg_idx;
2417 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2418 vlnctrl |= IXGBE_RXDCTL_VME;
2419 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2420 }
2421 }
2f90b865
AD		 2422 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2423}
2424
2425#endif
9a799d71
AK		 2426static void ixgbe_configure(struct ixgbe_adapter *adapter)
2427{
2428 struct net_device *netdev = adapter->netdev;
c4cf55e5 2429 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 2430 int i;
2431
2c5645cf 2432 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2433
2434 ixgbe_restore_vlan(adapter);
7a6b6f51 2435#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2436 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2437 netif_set_gso_max_size(netdev, 32768);
2438 ixgbe_configure_dcb(adapter);
2439 } else {
2440 netif_set_gso_max_size(netdev, 65536);
2441 }
2442#else
2443 netif_set_gso_max_size(netdev, 65536);
2444#endif
9a799d71 2445
eacd73f7
YZ		 2446#ifdef IXGBE_FCOE
2447 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2448 ixgbe_configure_fcoe(adapter);
2449
2450#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 2451 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2452 for (i = 0; i < adapter->num_tx_queues; i++)
2453 adapter->tx_ring[i].atr_sample_rate =
2454 adapter->atr_sample_rate;
2455 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2456 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2457 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2458 }
2459
9a799d71
AK		 2460 ixgbe_configure_tx(adapter);
2461 ixgbe_configure_rx(adapter);
2462 for (i = 0; i < adapter->num_rx_queues; i++)
2463 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 2464 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 2465}
2466
e8e26350
PW		 2467static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2468{
2469 switch (hw->phy.type) {
2470 case ixgbe_phy_sfp_avago:
2471 case ixgbe_phy_sfp_ftl:
2472 case ixgbe_phy_sfp_intel:
2473 case ixgbe_phy_sfp_unknown:
2474 case ixgbe_phy_tw_tyco:
2475 case ixgbe_phy_tw_unknown:
2476 return true;
2477 default:
2478 return false;
2479 }
2480}
2481
0ecc061d 2482/**
e8e26350
PW		 2483 * ixgbe_sfp_link_config - set up SFP+ link
2484 * @adapter: pointer to private adapter struct
2485 **/
2486static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2487{
2488 struct ixgbe_hw *hw = &adapter->hw;
2489
2490 if (hw->phy.multispeed_fiber) {
2491 /*
2492 * In multispeed fiber setups, the device may not have
2493 * had a physical connection when the driver loaded.
2494 * If that's the case, the initial link configuration
2495 * couldn't get the MAC into 10G or 1G mode, so we'll
2496 * never have a link status change interrupt fire.
2497 * We need to try and force an autonegotiation
2498 * session, then bring up link.
2499 */
2500 hw->mac.ops.setup_sfp(hw);
2501 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2502 schedule_work(&adapter->multispeed_fiber_task);
2503 } else {
2504 /*
2505 * Direct Attach Cu and non-multispeed fiber modules
2506 * still need to be configured properly prior to
2507 * attempting link.
2508 */
2509 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2510 schedule_work(&adapter->sfp_config_module_task);
2511 }
2512}
2513
2514/**
2515 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2516 * @hw: pointer to private hardware struct
2517 *
2518 * Returns 0 on success, negative on failure
2519 **/
e8e26350 2520static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2521{
2522 u32 autoneg;
8620a103 2523 bool negotiation, link_up = false;
0ecc061d
PWJ		 2524 u32 ret = IXGBE_ERR_LINK_SETUP;
2525
2526 if (hw->mac.ops.check_link)
2527 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2528
2529 if (ret)
2530 goto link_cfg_out;
2531
2532 if (hw->mac.ops.get_link_capabilities)
8620a103 2533 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
0ecc061d
PWJ		 2534 if (ret)
2535 goto link_cfg_out;
2536
8620a103
MC		 2537 if (hw->mac.ops.setup_link)
2538 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 2539link_cfg_out:
2540 return ret;
2541}
2542
e8e26350
PW		 2543#define IXGBE_MAX_RX_DESC_POLL 10
2544static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2545 int rxr)
2546{
2547 int j = adapter->rx_ring[rxr].reg_idx;
2548 int k;
2549
2550 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2551 if (IXGBE_READ_REG(&adapter->hw,
2552 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2553 break;
2554 else
2555 msleep(1);
2556 }
2557 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2558 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2559 "not set within the polling period\n", rxr);
2560 }
2561 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2562 (adapter->rx_ring[rxr].count - 1));
2563}
2564
9a799d71
AK		 2565static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2566{
2567 struct net_device *netdev = adapter->netdev;
9a799d71 2568 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2569 int i, j = 0;
e8e26350 2570 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2571 int err;
9a799d71 2572 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2573 u32 txdctl, rxdctl, mhadd;
e8e26350 2574 u32 dmatxctl;
021230d4 2575 u32 gpie;
9a799d71 2576
5eba3699
AV		 2577 ixgbe_get_hw_control(adapter);
2578
021230d4
AV		 2579 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2580 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2581 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2582 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2583 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2584 } else {
2585 /* MSI only */
021230d4 2586 gpie = 0;
9a799d71 2587 }
021230d4
AV		 2588 /* XXX: to interrupt immediately for EICS writes, enable this */
2589 /* gpie |= IXGBE_GPIE_EIMEN; */
2590 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2591 }
2592
021230d4
AV		 2593 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2594 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2595 * specifically only auto mask tx and rx interrupts */
2596 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2597 }
9a799d71 2598
0befdb3e
JB		 2599 /* Enable fan failure interrupt if media type is copper */
2600 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2601 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2602 gpie |= IXGBE_SDP1_GPIEN;
2603 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2604 }
2605
e8e26350
PW		 2606 if (hw->mac.type == ixgbe_mac_82599EB) {
2607 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2608 gpie |= IXGBE_SDP1_GPIEN;
2609 gpie |= IXGBE_SDP2_GPIEN;
2610 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2611 }
2612
63f39bd1
YZ		 2613#ifdef IXGBE_FCOE
2614 /* adjust max frame to be able to do baby jumbo for FCoE */
f34c5c82 2615 if ((netdev->features & NETIF_F_FCOE_MTU) &&
63f39bd1
YZ		 2616 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2617 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2618
2619#endif /* IXGBE_FCOE */
021230d4 2620 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2621 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2622 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2623 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2624
2625 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2626 }
2627
2628 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 2629 j = adapter->tx_ring[i].reg_idx;
2630 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2631 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2632 txdctl |= (8 << 16);
e8e26350
PW		 2633 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2634 }
2635
2636 if (hw->mac.type == ixgbe_mac_82599EB) {
2637 /* DMATXCTL.EN must be set after all Tx queue config is done */
2638 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2639 dmatxctl |= IXGBE_DMATXCTL_TE;
2640 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2641 }
2642 for (i = 0; i < adapter->num_tx_queues; i++) {
2643 j = adapter->tx_ring[i].reg_idx;
2644 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2645 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2646 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 2647 }
2648
e8e26350 2649 for (i = 0; i < num_rx_rings; i++) {
021230d4
AV		 2650 j = adapter->rx_ring[i].reg_idx;
2651 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2652 /* enable PTHRESH=32 descriptors (half the internal cache)
2653 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2654 * this also removes a pesky rx_no_buffer_count increment */
2655 rxdctl |= 0x0020;
9a799d71 2656 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2657 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2658 if (hw->mac.type == ixgbe_mac_82599EB)
2659 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2660 }
2661 /* enable all receives */
2662 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2663 if (hw->mac.type == ixgbe_mac_82598EB)
2664 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2665 else
2666 rxdctl |= IXGBE_RXCTRL_RXEN;
2667 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2668
2669 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2670 ixgbe_configure_msix(adapter);
2671 else
2672 ixgbe_configure_msi_and_legacy(adapter);
2673
2674 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2675 ixgbe_napi_enable_all(adapter);
2676
2677 /* clear any pending interrupts, may auto mask */
2678 IXGBE_READ_REG(hw, IXGBE_EICR);
2679
9a799d71
AK		 2680 ixgbe_irq_enable(adapter);
2681
bf069c97
DS		 2682 /*
2683 * If this adapter has a fan, check to see if we had a failure
2684 * before we enabled the interrupt.
2685 */
2686 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2687 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2688 if (esdp & IXGBE_ESDP_SDP1)
2689 DPRINTK(DRV, CRIT,
2690 "Fan has stopped, replace the adapter\n");
2691 }
2692
e8e26350
PW		 2693 /*
2694 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 2695 * arrived before interrupts were enabled but after probe. Such
2696 * devices wouldn't have their type identified yet. We need to
2697 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 2698 * If we're not hot-pluggable SFP+, we just need to configure link
2699 * and bring it up.
2700 */
19343de2
DS		 2701 if (hw->phy.type == ixgbe_phy_unknown) {
2702 err = hw->phy.ops.identify(hw);
2703 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 2704 /*
2705 * Take the device down and schedule the sfp tasklet
2706 * which will unregister_netdev and log it.
2707 */
19343de2 2708 ixgbe_down(adapter);
5da43c1a 2709 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 2710 return err;
2711 }
e8e26350
PW		 2712 }
2713
2714 if (ixgbe_is_sfp(hw)) {
2715 ixgbe_sfp_link_config(adapter);
2716 } else {
2717 err = ixgbe_non_sfp_link_config(hw);
2718 if (err)
2719 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2720 }
0ecc061d 2721
c4cf55e5
PWJ		 2722 for (i = 0; i < adapter->num_tx_queues; i++)
2723 set_bit(__IXGBE_FDIR_INIT_DONE,
2724 &(adapter->tx_ring[i].reinit_state));
2725
1da100bb
PWJ		 2726 /* enable transmits */
2727 netif_tx_start_all_queues(netdev);
2728
9a799d71
AK		 2729 /* bring the link up in the watchdog, this could race with our first
2730 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 2731 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2732 adapter->link_check_timeout = jiffies;
9a799d71
AK		 2733 mod_timer(&adapter->watchdog_timer, jiffies);
2734 return 0;
2735}
2736
d4f80882
AV		 2737void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2738{
2739 WARN_ON(in_interrupt());
2740 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2741 msleep(1);
2742 ixgbe_down(adapter);
2743 ixgbe_up(adapter);
2744 clear_bit(__IXGBE_RESETTING, &adapter->state);
2745}
2746
9a799d71
AK		 2747int ixgbe_up(struct ixgbe_adapter *adapter)
2748{
2749 /* hardware has been reset, we need to reload some things */
2750 ixgbe_configure(adapter);
2751
2752 return ixgbe_up_complete(adapter);
2753}
2754
2755void ixgbe_reset(struct ixgbe_adapter *adapter)
2756{
c44ade9e 2757 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 2758 int err;
2759
2760 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 2761 switch (err) {
2762 case 0:
2763 case IXGBE_ERR_SFP_NOT_PRESENT:
2764 break;
2765 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2766 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2767 break;
794caeb2
PWJ		 2768 case IXGBE_ERR_EEPROM_VERSION:
2769 /* We are running on a pre-production device, log a warning */
2770 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2771 "adapter/LOM. Please be aware there may be issues "
2772 "associated with your hardware. If you are "
2773 "experiencing problems please contact your Intel or "
2774 "hardware representative who provided you with this "
2775 "hardware.\n");
2776 break;
da4dd0f7
PWJ		 2777 default:
2778 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2779 }
9a799d71
AK		 2780
2781 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2782 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2783}
2784
9a799d71
AK		 2785/**
2786 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2787 * @adapter: board private structure
2788 * @rx_ring: ring to free buffers from
2789 **/
2790static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2791 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2792{
2793 struct pci_dev *pdev = adapter->pdev;
2794 unsigned long size;
2795 unsigned int i;
2796
2797 /* Free all the Rx ring sk_buffs */
2798
2799 for (i = 0; i < rx_ring->count; i++) {
2800 struct ixgbe_rx_buffer *rx_buffer_info;
2801
2802 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2803 if (rx_buffer_info->dma) {
2804 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2805 rx_ring->rx_buf_len,
2806 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2807 rx_buffer_info->dma = 0;
2808 }
2809 if (rx_buffer_info->skb) {
f8212f97 2810 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 2811 rx_buffer_info->skb = NULL;
f8212f97
AD		 2812 do {
2813 struct sk_buff *this = skb;
2814 skb = skb->prev;
2815 dev_kfree_skb(this);
2816 } while (skb);
9a799d71
AK		 2817 }
2818 if (!rx_buffer_info->page)
2819 continue;
4f57ca6e
JB		 2820 if (rx_buffer_info->page_dma) {
2821 pci_unmap_page(pdev, rx_buffer_info->page_dma,
2822 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2823 rx_buffer_info->page_dma = 0;
2824 }
9a799d71
AK		 2825 put_page(rx_buffer_info->page);
2826 rx_buffer_info->page = NULL;
762f4c57 2827 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2828 }
2829
2830 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2831 memset(rx_ring->rx_buffer_info, 0, size);
2832
2833 /* Zero out the descriptor ring */
2834 memset(rx_ring->desc, 0, rx_ring->size);
2835
2836 rx_ring->next_to_clean = 0;
2837 rx_ring->next_to_use = 0;
2838
9891ca7c
JB		 2839 if (rx_ring->head)
2840 writel(0, adapter->hw.hw_addr + rx_ring->head);
2841 if (rx_ring->tail)
2842 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 2843}
2844
2845/**
2846 * ixgbe_clean_tx_ring - Free Tx Buffers
2847 * @adapter: board private structure
2848 * @tx_ring: ring to be cleaned
2849 **/
2850static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2851 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2852{
2853 struct ixgbe_tx_buffer *tx_buffer_info;
2854 unsigned long size;
2855 unsigned int i;
2856
2857 /* Free all the Tx ring sk_buffs */
2858
2859 for (i = 0; i < tx_ring->count; i++) {
2860 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2861 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2862 }
2863
2864 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2865 memset(tx_ring->tx_buffer_info, 0, size);
2866
2867 /* Zero out the descriptor ring */
2868 memset(tx_ring->desc, 0, tx_ring->size);
2869
2870 tx_ring->next_to_use = 0;
2871 tx_ring->next_to_clean = 0;
2872
9891ca7c
JB		 2873 if (tx_ring->head)
2874 writel(0, adapter->hw.hw_addr + tx_ring->head);
2875 if (tx_ring->tail)
2876 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 2877}
2878
2879/**
021230d4 2880 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2881 * @adapter: board private structure
2882 **/
021230d4 2883static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2884{
2885 int i;
2886
021230d4
AV		 2887 for (i = 0; i < adapter->num_rx_queues; i++)
2888 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2889}
2890
2891/**
021230d4 2892 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2893 * @adapter: board private structure
2894 **/
021230d4 2895static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2896{
2897 int i;
2898
021230d4
AV		 2899 for (i = 0; i < adapter->num_tx_queues; i++)
2900 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2901}
2902
2903void ixgbe_down(struct ixgbe_adapter *adapter)
2904{
2905 struct net_device *netdev = adapter->netdev;
7f821875 2906 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2907 u32 rxctrl;
7f821875
JB		 2908 u32 txdctl;
2909 int i, j;
9a799d71
AK		 2910
2911 /* signal that we are down to the interrupt handler */
2912 set_bit(__IXGBE_DOWN, &adapter->state);
2913
2914 /* disable receives */
7f821875
JB		 2915 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2916 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 2917
2918 netif_tx_disable(netdev);
2919
7f821875 2920 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 2921 msleep(10);
2922
7f821875
JB		 2923 netif_tx_stop_all_queues(netdev);
2924
9a799d71
AK		 2925 ixgbe_irq_disable(adapter);
2926
021230d4 2927 ixgbe_napi_disable_all(adapter);
7f821875 2928
0a1f87cb
DS		 2929 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
2930 del_timer_sync(&adapter->sfp_timer);
9a799d71 2931 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 2932 cancel_work_sync(&adapter->watchdog_task);
9a799d71 2933
c4cf55e5
PWJ		 2934 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2935 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2936 cancel_work_sync(&adapter->fdir_reinit_task);
2937
7f821875
JB		 2938 /* disable transmits in the hardware now that interrupts are off */
2939 for (i = 0; i < adapter->num_tx_queues; i++) {
2940 j = adapter->tx_ring[i].reg_idx;
2941 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2942 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2943 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2944 }
88512539
PW		 2945 /* Disable the Tx DMA engine on 82599 */
2946 if (hw->mac.type == ixgbe_mac_82599EB)
2947 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2948 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2949 ~IXGBE_DMATXCTL_TE));
7f821875 2950
9a799d71 2951 netif_carrier_off(netdev);
9a799d71 2952
6f4a0e45
PL		 2953 if (!pci_channel_offline(adapter->pdev))
2954 ixgbe_reset(adapter);
9a799d71
AK		 2955 ixgbe_clean_all_tx_rings(adapter);
2956 ixgbe_clean_all_rx_rings(adapter);
2957
5dd2d332 2958#ifdef CONFIG_IXGBE_DCA
96b0e0f6 2959 /* since we reset the hardware DCA settings were cleared */
e35ec126 2960 ixgbe_setup_dca(adapter);
96b0e0f6 2961#endif
9a799d71
AK		 2962}
2963
9a799d71 2964/**
021230d4
AV		 2965 * ixgbe_poll - NAPI Rx polling callback
2966 * @napi: structure for representing this polling device
2967 * @budget: how many packets driver is allowed to clean
2968 *
2969 * This function is used for legacy and MSI, NAPI mode
9a799d71 2970 **/
021230d4 2971static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2972{
9a1a69ad
JB		 2973 struct ixgbe_q_vector *q_vector =
2974 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2975 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 2976 int tx_clean_complete, work_done = 0;
9a799d71 2977
5dd2d332 2978#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 2979 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2980 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2981 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2982 }
2983#endif
2984
fe49f04a 2985 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
78b6f4ce 2986 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
9a799d71 2987
9a1a69ad 2988 if (!tx_clean_complete)
d2c7ddd6
DM		 2989 work_done = budget;
2990
53e52c72
DM		 2991 /* If budget not fully consumed, exit the polling mode */
2992 if (work_done < budget) {
288379f0 2993 napi_complete(napi);
f7554a2b 2994 if (adapter->rx_itr_setting & 1)
f494e8fa 2995 ixgbe_set_itr(adapter);
d4f80882 2996 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 2997 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 2998 }
9a799d71
AK		 2999 return work_done;
3000}
3001
3002/**
3003 * ixgbe_tx_timeout - Respond to a Tx Hang
3004 * @netdev: network interface device structure
3005 **/
3006static void ixgbe_tx_timeout(struct net_device *netdev)
3007{
3008 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3009
3010 /* Do the reset outside of interrupt context */
3011 schedule_work(&adapter->reset_task);
3012}
3013
3014static void ixgbe_reset_task(struct work_struct *work)
3015{
3016 struct ixgbe_adapter *adapter;
3017 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3018
2f90b865
AD		 3019 /* If we're already down or resetting, just bail */
3020 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3021 test_bit(__IXGBE_RESETTING, &adapter->state))
3022 return;
3023
9a799d71
AK		 3024 adapter->tx_timeout_count++;
3025
d4f80882 3026 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3027}
3028
bc97114d
PWJ		 3029#ifdef CONFIG_IXGBE_DCB
3030static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3031{
bc97114d 3032 bool ret = false;
0cefafad 3033 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3034
0cefafad
JB		 3035 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3036 return ret;
3037
3038 f->mask = 0x7 << 3;
3039 adapter->num_rx_queues = f->indices;
3040 adapter->num_tx_queues = f->indices;
3041 ret = true;
2f90b865 3042
bc97114d
PWJ		 3043 return ret;
3044}
3045#endif
3046
4df10466
JB		 3047/**
3048 * ixgbe_set_rss_queues: Allocate queues for RSS
3049 * @adapter: board private structure to initialize
3050 *
3051 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3052 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3053 *
3054 **/
bc97114d
PWJ		 3055static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3056{
3057 bool ret = false;
0cefafad 3058 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3059
3060 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3061 f->mask = 0xF;
3062 adapter->num_rx_queues = f->indices;
3063 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3064 ret = true;
3065 } else {
bc97114d 3066 ret = false;
b9804972
JB		 3067 }
3068
bc97114d
PWJ		 3069 return ret;
3070}
3071
c4cf55e5
PWJ		 3072/**
3073 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3074 * @adapter: board private structure to initialize
3075 *
3076 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3077 * to the original CPU that initiated the Tx session. This runs in addition
3078 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3079 * Rx load across CPUs using RSS.
3080 *
3081 **/
3082static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3083{
3084 bool ret = false;
3085 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3086
3087 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3088 f_fdir->mask = 0;
3089
3090 /* Flow Director must have RSS enabled */
3091 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3092 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3093 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3094 adapter->num_tx_queues = f_fdir->indices;
3095 adapter->num_rx_queues = f_fdir->indices;
3096 ret = true;
3097 } else {
3098 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3099 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3100 }
3101 return ret;
3102}
3103
0331a832
YZ		 3104#ifdef IXGBE_FCOE
3105/**
3106 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3107 * @adapter: board private structure to initialize
3108 *
3109 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3110 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3111 * rx queues out of the max number of rx queues, instead, it is used as the
3112 * index of the first rx queue used by FCoE.
3113 *
3114 **/
3115static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3116{
3117 bool ret = false;
3118 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3119
3120 f->indices = min((int)num_online_cpus(), f->indices);
3121 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 3122 adapter->num_rx_queues = 1;
3123 adapter->num_tx_queues = 1;
0331a832
YZ		 3124#ifdef CONFIG_IXGBE_DCB
3125 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6 3126 DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
0331a832
YZ		 3127 ixgbe_set_dcb_queues(adapter);
3128 }
3129#endif
3130 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8de8b2e6 3131 DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
8faa2a78
YZ		 3132 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3133 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3134 ixgbe_set_fdir_queues(adapter);
3135 else
3136 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 3137 }
3138 /* adding FCoE rx rings to the end */
3139 f->mask = adapter->num_rx_queues;
3140 adapter->num_rx_queues += f->indices;
8de8b2e6 3141 adapter->num_tx_queues += f->indices;
0331a832
YZ		 3142
3143 ret = true;
3144 }
3145
3146 return ret;
3147}
3148
3149#endif /* IXGBE_FCOE */
4df10466
JB		 3150/*
3151 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3152 * @adapter: board private structure to initialize
3153 *
3154 * This is the top level queue allocation routine. The order here is very
3155 * important, starting with the "most" number of features turned on at once,
3156 * and ending with the smallest set of features. This way large combinations
3157 * can be allocated if they're turned on, and smaller combinations are the
3158 * fallthrough conditions.
3159 *
3160 **/
bc97114d
PWJ		 3161static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3162{
0331a832
YZ		 3163#ifdef IXGBE_FCOE
3164 if (ixgbe_set_fcoe_queues(adapter))
3165 goto done;
3166
3167#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3168#ifdef CONFIG_IXGBE_DCB
3169 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 3170 goto done;
bc97114d
PWJ		 3171
3172#endif
c4cf55e5
PWJ		 3173 if (ixgbe_set_fdir_queues(adapter))
3174 goto done;
3175
bc97114d 3176 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 3177 goto done;
3178
3179 /* fallback to base case */
3180 adapter->num_rx_queues = 1;
3181 adapter->num_tx_queues = 1;
3182
3183done:
3184 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3185 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 3186}
3187
021230d4 3188static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 3189 int vectors)
021230d4
AV		 3190{
3191 int err, vector_threshold;
3192
3193 /* We'll want at least 3 (vector_threshold):
3194 * 1) TxQ[0] Cleanup
3195 * 2) RxQ[0] Cleanup
3196 * 3) Other (Link Status Change, etc.)
3197 * 4) TCP Timer (optional)
3198 */
3199 vector_threshold = MIN_MSIX_COUNT;
3200
3201 /* The more we get, the more we will assign to Tx/Rx Cleanup
3202 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3203 * Right now, we simply care about how many we'll get; we'll
3204 * set them up later while requesting irq's.
3205 */
3206 while (vectors >= vector_threshold) {
3207 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 3208 vectors);
021230d4
AV		 3209 if (!err) /* Success in acquiring all requested vectors. */
3210 break;
3211 else if (err < 0)
3212 vectors = 0; /* Nasty failure, quit now */
3213 else /* err == number of vectors we should try again with */
3214 vectors = err;
3215 }
3216
3217 if (vectors < vector_threshold) {
3218 /* Can't allocate enough MSI-X interrupts? Oh well.
3219 * This just means we'll go with either a single MSI
3220 * vector or fall back to legacy interrupts.
3221 */
3222 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3223 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3224 kfree(adapter->msix_entries);
3225 adapter->msix_entries = NULL;
021230d4
AV		 3226 } else {
3227 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 3228 /*
3229 * Adjust for only the vectors we'll use, which is minimum
3230 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3231 * vectors we were allocated.
3232 */
3233 adapter->num_msix_vectors = min(vectors,
3234 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 3235 }
3236}
3237
021230d4 3238/**
bc97114d 3239 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 3240 * @adapter: board private structure to initialize
3241 *
bc97114d
PWJ		 3242 * Cache the descriptor ring offsets for RSS to the assigned rings.
3243 *
021230d4 3244 **/
bc97114d 3245static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 3246{
bc97114d
PWJ		 3247 int i;
3248 bool ret = false;
3249
3250 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3251 for (i = 0; i < adapter->num_rx_queues; i++)
3252 adapter->rx_ring[i].reg_idx = i;
3253 for (i = 0; i < adapter->num_tx_queues; i++)
3254 adapter->tx_ring[i].reg_idx = i;
3255 ret = true;
3256 } else {
3257 ret = false;
3258 }
3259
3260 return ret;
3261}
3262
3263#ifdef CONFIG_IXGBE_DCB
3264/**
3265 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3266 * @adapter: board private structure to initialize
3267 *
3268 * Cache the descriptor ring offsets for DCB to the assigned rings.
3269 *
3270 **/
3271static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3272{
3273 int i;
3274 bool ret = false;
3275 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3276
3277 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3278 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 3279 /* the number of queues is assumed to be symmetric */
3280 for (i = 0; i < dcb_i; i++) {
3281 adapter->rx_ring[i].reg_idx = i << 3;
3282 adapter->tx_ring[i].reg_idx = i << 2;
3283 }
bc97114d 3284 ret = true;
e8e26350 3285 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 3286 if (dcb_i == 8) {
3287 /*
3288 * Tx TC0 starts at: descriptor queue 0
3289 * Tx TC1 starts at: descriptor queue 32
3290 * Tx TC2 starts at: descriptor queue 64
3291 * Tx TC3 starts at: descriptor queue 80
3292 * Tx TC4 starts at: descriptor queue 96
3293 * Tx TC5 starts at: descriptor queue 104
3294 * Tx TC6 starts at: descriptor queue 112
3295 * Tx TC7 starts at: descriptor queue 120
3296 *
3297 * Rx TC0-TC7 are offset by 16 queues each
3298 */
3299 for (i = 0; i < 3; i++) {
3300 adapter->tx_ring[i].reg_idx = i << 5;
3301 adapter->rx_ring[i].reg_idx = i << 4;
3302 }
3303 for ( ; i < 5; i++) {
3304 adapter->tx_ring[i].reg_idx =
3305 ((i + 2) << 4);
3306 adapter->rx_ring[i].reg_idx = i << 4;
3307 }
3308 for ( ; i < dcb_i; i++) {
3309 adapter->tx_ring[i].reg_idx =
3310 ((i + 8) << 3);
3311 adapter->rx_ring[i].reg_idx = i << 4;
3312 }
3313
3314 ret = true;
3315 } else if (dcb_i == 4) {
3316 /*
3317 * Tx TC0 starts at: descriptor queue 0
3318 * Tx TC1 starts at: descriptor queue 64
3319 * Tx TC2 starts at: descriptor queue 96
3320 * Tx TC3 starts at: descriptor queue 112
3321 *
3322 * Rx TC0-TC3 are offset by 32 queues each
3323 */
3324 adapter->tx_ring[0].reg_idx = 0;
3325 adapter->tx_ring[1].reg_idx = 64;
3326 adapter->tx_ring[2].reg_idx = 96;
3327 adapter->tx_ring[3].reg_idx = 112;
3328 for (i = 0 ; i < dcb_i; i++)
3329 adapter->rx_ring[i].reg_idx = i << 5;
3330
3331 ret = true;
3332 } else {
3333 ret = false;
e8e26350 3334 }
bc97114d
PWJ		 3335 } else {
3336 ret = false;
021230d4 3337 }
bc97114d
PWJ		 3338 } else {
3339 ret = false;
021230d4 3340 }
bc97114d
PWJ		 3341
3342 return ret;
3343}
3344#endif
3345
c4cf55e5
PWJ		 3346/**
3347 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3348 * @adapter: board private structure to initialize
3349 *
3350 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3351 *
3352 **/
3353static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3354{
3355 int i;
3356 bool ret = false;
3357
3358 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3359 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3360 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3361 for (i = 0; i < adapter->num_rx_queues; i++)
3362 adapter->rx_ring[i].reg_idx = i;
3363 for (i = 0; i < adapter->num_tx_queues; i++)
3364 adapter->tx_ring[i].reg_idx = i;
3365 ret = true;
3366 }
3367
3368 return ret;
3369}
3370
0331a832
YZ		 3371#ifdef IXGBE_FCOE
3372/**
3373 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3374 * @adapter: board private structure to initialize
3375 *
3376 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3377 *
3378 */
3379static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3380{
8de8b2e6 3381 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 3382 bool ret = false;
3383 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3384
3385 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3386#ifdef CONFIG_IXGBE_DCB
3387 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 3388 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3389
0331a832 3390 ixgbe_cache_ring_dcb(adapter);
8de8b2e6
YZ		 3391 /* find out queues in TC for FCoE */
3392 fcoe_rx_i = adapter->rx_ring[fcoe->tc].reg_idx + 1;
3393 fcoe_tx_i = adapter->tx_ring[fcoe->tc].reg_idx + 1;
3394 /*
3395 * In 82599, the number of Tx queues for each traffic
3396 * class for both 8-TC and 4-TC modes are:
3397 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3398 * 8 TCs: 32 32 16 16 8 8 8 8
3399 * 4 TCs: 64 64 32 32
3400 * We have max 8 queues for FCoE, where 8 the is
3401 * FCoE redirection table size. If TC for FCoE is
3402 * less than or equal to TC3, we have enough queues
3403 * to add max of 8 queues for FCoE, so we start FCoE
3404 * tx descriptor from the next one, i.e., reg_idx + 1.
3405 * If TC for FCoE is above TC3, implying 8 TC mode,
3406 * and we need 8 for FCoE, we have to take all queues
3407 * in that traffic class for FCoE.
3408 */
3409 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3410 fcoe_tx_i--;
0331a832
YZ		 3411 }
3412#endif /* CONFIG_IXGBE_DCB */
3413 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 3414 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3415 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3416 ixgbe_cache_ring_fdir(adapter);
3417 else
3418 ixgbe_cache_ring_rss(adapter);
3419
8de8b2e6
YZ		 3420 fcoe_rx_i = f->mask;
3421 fcoe_tx_i = f->mask;
3422 }
3423 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3424 adapter->rx_ring[f->mask + i].reg_idx = fcoe_rx_i;
3425 adapter->tx_ring[f->mask + i].reg_idx = fcoe_tx_i;
0331a832 3426 }
0331a832
YZ		 3427 ret = true;
3428 }
3429 return ret;
3430}
3431
3432#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3433/**
3434 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3435 * @adapter: board private structure to initialize
3436 *
3437 * Once we know the feature-set enabled for the device, we'll cache
3438 * the register offset the descriptor ring is assigned to.
3439 *
3440 * Note, the order the various feature calls is important. It must start with
3441 * the "most" features enabled at the same time, then trickle down to the
3442 * least amount of features turned on at once.
3443 **/
3444static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3445{
3446 /* start with default case */
3447 adapter->rx_ring[0].reg_idx = 0;
3448 adapter->tx_ring[0].reg_idx = 0;
3449
0331a832
YZ		 3450#ifdef IXGBE_FCOE
3451 if (ixgbe_cache_ring_fcoe(adapter))
3452 return;
3453
3454#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3455#ifdef CONFIG_IXGBE_DCB
3456 if (ixgbe_cache_ring_dcb(adapter))
3457 return;
3458
3459#endif
c4cf55e5
PWJ		 3460 if (ixgbe_cache_ring_fdir(adapter))
3461 return;
3462
bc97114d
PWJ		 3463 if (ixgbe_cache_ring_rss(adapter))
3464 return;
021230d4
AV		 3465}
3466
9a799d71
AK		 3467/**
3468 * ixgbe_alloc_queues - Allocate memory for all rings
3469 * @adapter: board private structure to initialize
3470 *
3471 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 3472 * number of queues at compile-time. The polling_netdev array is
3473 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 3474 **/
2f90b865 3475static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 3476{
3477 int i;
3478
3479 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 3480 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 3481 if (!adapter->tx_ring)
021230d4 3482 goto err_tx_ring_allocation;
9a799d71
AK		 3483
3484 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 3485 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 3486 if (!adapter->rx_ring)
3487 goto err_rx_ring_allocation;
9a799d71 3488
021230d4 3489 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 3490 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 3491 adapter->tx_ring[i].queue_index = i;
3492 }
b9804972 3493
9a799d71 3494 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 3495 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 3496 adapter->rx_ring[i].queue_index = i;
3497 }
3498
3499 ixgbe_cache_ring_register(adapter);
3500
3501 return 0;
3502
3503err_rx_ring_allocation:
3504 kfree(adapter->tx_ring);
3505err_tx_ring_allocation:
3506 return -ENOMEM;
3507}
3508
3509/**
3510 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3511 * @adapter: board private structure to initialize
3512 *
3513 * Attempt to configure the interrupts using the best available
3514 * capabilities of the hardware and the kernel.
3515 **/
feea6a57 3516static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 3517{
8be0e467 3518 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 3519 int err = 0;
3520 int vector, v_budget;
3521
3522 /*
3523 * It's easy to be greedy for MSI-X vectors, but it really
3524 * doesn't do us much good if we have a lot more vectors
3525 * than CPU's. So let's be conservative and only ask for
3526 * (roughly) twice the number of vectors as there are CPU's.
3527 */
3528 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
b4617240 3529 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
021230d4
AV		 3530
3531 /*
3532 * At the same time, hardware can only support a maximum of
8be0e467
PW		 3533 * hw.mac->max_msix_vectors vectors. With features
3534 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3535 * descriptor queues supported by our device. Thus, we cap it off in
3536 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3537 */
8be0e467 3538 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3539
3540 /* A failure in MSI-X entry allocation isn't fatal, but it does
3541 * mean we disable MSI-X capabilities of the adapter. */
3542 adapter->msix_entries = kcalloc(v_budget,
b4617240 3543 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 3544 if (adapter->msix_entries) {
3545 for (vector = 0; vector < v_budget; vector++)
3546 adapter->msix_entries[vector].entry = vector;
021230d4 3547
7a921c93 3548 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 3549
7a921c93
AD		 3550 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3551 goto out;
3552 }
021230d4 3553
7a921c93
AD		 3554 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3555 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 3556 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3557 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3558 adapter->atr_sample_rate = 0;
7a921c93 3559 ixgbe_set_num_queues(adapter);
021230d4 3560
021230d4
AV		 3561 err = pci_enable_msi(adapter->pdev);
3562 if (!err) {
3563 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3564 } else {
3565 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 3566 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 3567 /* reset err */
3568 err = 0;
3569 }
3570
3571out:
021230d4
AV		 3572 return err;
3573}
3574
7a921c93
AD		 3575/**
3576 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3577 * @adapter: board private structure to initialize
3578 *
3579 * We allocate one q_vector per queue interrupt. If allocation fails we
3580 * return -ENOMEM.
3581 **/
3582static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3583{
3584 int q_idx, num_q_vectors;
3585 struct ixgbe_q_vector *q_vector;
3586 int napi_vectors;
3587 int (*poll)(struct napi_struct *, int);
3588
3589 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3590 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3591 napi_vectors = adapter->num_rx_queues;
91281fd3 3592 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 3593 } else {
3594 num_q_vectors = 1;
3595 napi_vectors = 1;
3596 poll = &ixgbe_poll;
3597 }
3598
3599 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3600 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3601 if (!q_vector)
3602 goto err_out;
3603 q_vector->adapter = adapter;
f7554a2b
NS		 3604 if (q_vector->txr_count && !q_vector->rxr_count)
3605 q_vector->eitr = adapter->tx_eitr_param;
3606 else
3607 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 3608 q_vector->v_idx = q_idx;
91281fd3 3609 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 3610 adapter->q_vector[q_idx] = q_vector;
3611 }
3612
3613 return 0;
3614
3615err_out:
3616 while (q_idx) {
3617 q_idx--;
3618 q_vector = adapter->q_vector[q_idx];
3619 netif_napi_del(&q_vector->napi);
3620 kfree(q_vector);
3621 adapter->q_vector[q_idx] = NULL;
3622 }
3623 return -ENOMEM;
3624}
3625
3626/**
3627 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3628 * @adapter: board private structure to initialize
3629 *
3630 * This function frees the memory allocated to the q_vectors. In addition if
3631 * NAPI is enabled it will delete any references to the NAPI struct prior
3632 * to freeing the q_vector.
3633 **/
3634static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3635{
3636 int q_idx, num_q_vectors;
7a921c93 3637
91281fd3 3638 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 3639 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 3640 else
7a921c93 3641 num_q_vectors = 1;
7a921c93
AD		 3642
3643 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3644 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 3645 adapter->q_vector[q_idx] = NULL;
91281fd3 3646 netif_napi_del(&q_vector->napi);
7a921c93
AD		 3647 kfree(q_vector);
3648 }
3649}
3650
7b25cdba 3651static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 3652{
3653 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3654 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3655 pci_disable_msix(adapter->pdev);
3656 kfree(adapter->msix_entries);
3657 adapter->msix_entries = NULL;
3658 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3659 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3660 pci_disable_msi(adapter->pdev);
3661 }
3662 return;
3663}
3664
3665/**
3666 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3667 * @adapter: board private structure to initialize
3668 *
3669 * We determine which interrupt scheme to use based on...
3670 * - Kernel support (MSI, MSI-X)
3671 * - which can be user-defined (via MODULE_PARAM)
3672 * - Hardware queue count (num_*_queues)
3673 * - defined by miscellaneous hardware support/features (RSS, etc.)
3674 **/
2f90b865 3675int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 3676{
3677 int err;
3678
3679 /* Number of supported queues */
3680 ixgbe_set_num_queues(adapter);
3681
021230d4
AV		 3682 err = ixgbe_set_interrupt_capability(adapter);
3683 if (err) {
3684 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3685 goto err_set_interrupt;
9a799d71
AK		 3686 }
3687
7a921c93
AD		 3688 err = ixgbe_alloc_q_vectors(adapter);
3689 if (err) {
3690 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3691 "vectors\n");
3692 goto err_alloc_q_vectors;
3693 }
3694
3695 err = ixgbe_alloc_queues(adapter);
3696 if (err) {
3697 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3698 goto err_alloc_queues;
3699 }
3700
021230d4 3701 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 3702 "Tx Queue count = %u\n",
3703 (adapter->num_rx_queues > 1) ? "Enabled" :
3704 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 3705
3706 set_bit(__IXGBE_DOWN, &adapter->state);
3707
9a799d71 3708 return 0;
021230d4 3709
7a921c93
AD		 3710err_alloc_queues:
3711 ixgbe_free_q_vectors(adapter);
3712err_alloc_q_vectors:
3713 ixgbe_reset_interrupt_capability(adapter);
021230d4 3714err_set_interrupt:
7a921c93
AD		 3715 return err;
3716}
3717
3718/**
3719 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3720 * @adapter: board private structure to clear interrupt scheme on
3721 *
3722 * We go through and clear interrupt specific resources and reset the structure
3723 * to pre-load conditions
3724 **/
3725void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3726{
021230d4
AV		 3727 kfree(adapter->tx_ring);
3728 kfree(adapter->rx_ring);
7a921c93
AD		 3729 adapter->tx_ring = NULL;
3730 adapter->rx_ring = NULL;
3731
3732 ixgbe_free_q_vectors(adapter);
3733 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 3734}
3735
c4900be0
DS		 3736/**
3737 * ixgbe_sfp_timer - worker thread to find a missing module
3738 * @data: pointer to our adapter struct
3739 **/
3740static void ixgbe_sfp_timer(unsigned long data)
3741{
3742 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3743
4df10466
JB		 3744 /*
3745 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 3746 * delays that sfp+ detection requires
3747 */
3748 schedule_work(&adapter->sfp_task);
3749}
3750
3751/**
3752 * ixgbe_sfp_task - worker thread to find a missing module
3753 * @work: pointer to work_struct containing our data
3754 **/
3755static void ixgbe_sfp_task(struct work_struct *work)
3756{
3757 struct ixgbe_adapter *adapter = container_of(work,
3758 struct ixgbe_adapter,
3759 sfp_task);
3760 struct ixgbe_hw *hw = &adapter->hw;
3761
3762 if ((hw->phy.type == ixgbe_phy_nl) &&
3763 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3764 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 3765 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 3766 goto reschedule;
3767 ret = hw->phy.ops.reset(hw);
3768 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 3769 dev_err(&adapter->pdev->dev, "failed to initialize "
3770 "because an unsupported SFP+ module type "
3771 "was detected.\n"
3772 "Reload the driver after installing a "
3773 "supported module.\n");
c4900be0
DS		 3774 unregister_netdev(adapter->netdev);
3775 } else {
3776 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3777 hw->phy.sfp_type);
3778 }
3779 /* don't need this routine any more */
3780 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3781 }
3782 return;
3783reschedule:
3784 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3785 mod_timer(&adapter->sfp_timer,
3786 round_jiffies(jiffies + (2 * HZ)));
3787}
3788
9a799d71
AK		 3789/**
3790 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3791 * @adapter: board private structure to initialize
3792 *
3793 * ixgbe_sw_init initializes the Adapter private data structure.
3794 * Fields are initialized based on PCI device information and
3795 * OS network device settings (MTU size).
3796 **/
3797static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3798{
3799 struct ixgbe_hw *hw = &adapter->hw;
3800 struct pci_dev *pdev = adapter->pdev;
021230d4 3801 unsigned int rss;
7a6b6f51 3802#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3803 int j;
3804 struct tc_configuration *tc;
3805#endif
021230d4 3806
c44ade9e
JB		 3807 /* PCI config space info */
3808
3809 hw->vendor_id = pdev->vendor;
3810 hw->device_id = pdev->device;
3811 hw->revision_id = pdev->revision;
3812 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3813 hw->subsystem_device_id = pdev->subsystem_device;
3814
021230d4
AV		 3815 /* Set capability flags */
3816 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3817 adapter->ring_feature[RING_F_RSS].indices = rss;
3818 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 3819 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 3820 if (hw->mac.type == ixgbe_mac_82598EB) {
3821 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3822 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 3823 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 3824 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 3825 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 3826 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3827 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
c4cf55e5
PWJ		 3828 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3829 adapter->ring_feature[RING_F_FDIR].indices =
3830 IXGBE_MAX_FDIR_INDICES;
3831 adapter->atr_sample_rate = 20;
3832 adapter->fdir_pballoc = 0;
eacd73f7 3833#ifdef IXGBE_FCOE
0d551589
YZ		 3834 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3835 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3836 adapter->ring_feature[RING_F_FCOE].indices = 0;
6ee16520
YZ		 3837 /* Default traffic class to use for FCoE */
3838 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
eacd73f7 3839#endif /* IXGBE_FCOE */
f8212f97 3840 }
2f90b865 3841
7a6b6f51 3842#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3843 /* Configure DCB traffic classes */
3844 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3845 tc = &adapter->dcb_cfg.tc_config[j];
3846 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3847 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3848 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3849 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3850 tc->dcb_pfc = pfc_disabled;
3851 }
3852 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3853 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3854 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 3855 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 3856 adapter->dcb_cfg.round_robin_enable = false;
3857 adapter->dcb_set_bitmap = 0x00;
3858 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3859 adapter->ring_feature[RING_F_DCB].indices);
3860
3861#endif
9a799d71
AK		 3862
3863 /* default flow control settings */
cd7664f6 3864 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 3865 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 3866#ifdef CONFIG_DCB
3867 adapter->last_lfc_mode = hw->fc.current_mode;
3868#endif
2b9ade93
JB		 3869 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3870 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3871 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3872 hw->fc.send_xon = true;
71fd570b 3873 hw->fc.disable_fc_autoneg = false;
9a799d71 3874
30efa5a3 3875 /* enable itr by default in dynamic mode */
f7554a2b
NS		 3876 adapter->rx_itr_setting = 1;
3877 adapter->rx_eitr_param = 20000;
3878 adapter->tx_itr_setting = 1;
3879 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 3880
3881 /* set defaults for eitr in MegaBytes */
3882 adapter->eitr_low = 10;
3883 adapter->eitr_high = 20;
3884
3885 /* set default ring sizes */
3886 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3887 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3888
9a799d71 3889 /* initialize eeprom parameters */
c44ade9e 3890 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 3891 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3892 return -EIO;
3893 }
3894
021230d4 3895 /* enable rx csum by default */
9a799d71
AK		 3896 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3897
9a799d71
AK		 3898 set_bit(__IXGBE_DOWN, &adapter->state);
3899
3900 return 0;
3901}
3902
3903/**
3904 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3905 * @adapter: board private structure
3a581073 3906 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3907 *
3908 * Return 0 on success, negative on failure
3909 **/
3910int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 3911 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3912{
3913 struct pci_dev *pdev = adapter->pdev;
3914 int size;
3915
3a581073
JB		 3916 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3917 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 3918 if (!tx_ring->tx_buffer_info)
3919 goto err;
3a581073 3920 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 3921
3922 /* round up to nearest 4K */
12207e49 3923 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 3924 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 3925
3a581073
JB		 3926 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3927 &tx_ring->dma);
e01c31a5
JB		 3928 if (!tx_ring->desc)
3929 goto err;
9a799d71 3930
3a581073
JB		 3931 tx_ring->next_to_use = 0;
3932 tx_ring->next_to_clean = 0;
3933 tx_ring->work_limit = tx_ring->count;
9a799d71 3934 return 0;
e01c31a5
JB		 3935
3936err:
3937 vfree(tx_ring->tx_buffer_info);
3938 tx_ring->tx_buffer_info = NULL;
3939 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3940 "descriptor ring\n");
3941 return -ENOMEM;
9a799d71
AK		 3942}
3943
69888674
AD		 3944/**
3945 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3946 * @adapter: board private structure
3947 *
3948 * If this function returns with an error, then it's possible one or
3949 * more of the rings is populated (while the rest are not). It is the
3950 * callers duty to clean those orphaned rings.
3951 *
3952 * Return 0 on success, negative on failure
3953 **/
3954static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3955{
3956 int i, err = 0;
3957
3958 for (i = 0; i < adapter->num_tx_queues; i++) {
3959 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3960 if (!err)
3961 continue;
3962 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3963 break;
3964 }
3965
3966 return err;
3967}
3968
9a799d71
AK		 3969/**
3970 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3971 * @adapter: board private structure
3a581073 3972 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3973 *
3974 * Returns 0 on success, negative on failure
3975 **/
3976int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 3977 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3978{
3979 struct pci_dev *pdev = adapter->pdev;
021230d4 3980 int size;
9a799d71 3981
3a581073
JB		 3982 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3983 rx_ring->rx_buffer_info = vmalloc(size);
3984 if (!rx_ring->rx_buffer_info) {
9a799d71 3985 DPRINTK(PROBE, ERR,
b4617240 3986 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 3987 goto alloc_failed;
9a799d71 3988 }
3a581073 3989 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 3990
9a799d71 3991 /* Round up to nearest 4K */
3a581073
JB		 3992 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3993 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 3994
3a581073 3995 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 3996
3a581073 3997 if (!rx_ring->desc) {
9a799d71 3998 DPRINTK(PROBE, ERR,
b4617240 3999 "Memory allocation failed for the rx desc ring\n");
3a581073 4000 vfree(rx_ring->rx_buffer_info);
177db6ff 4001 goto alloc_failed;
9a799d71
AK		 4002 }
4003
3a581073
JB		 4004 rx_ring->next_to_clean = 0;
4005 rx_ring->next_to_use = 0;
9a799d71
AK		 4006
4007 return 0;
177db6ff
MC		 4008
4009alloc_failed:
177db6ff 4010 return -ENOMEM;
9a799d71
AK		 4011}
4012
69888674
AD		 4013/**
4014 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4015 * @adapter: board private structure
4016 *
4017 * If this function returns with an error, then it's possible one or
4018 * more of the rings is populated (while the rest are not). It is the
4019 * callers duty to clean those orphaned rings.
4020 *
4021 * Return 0 on success, negative on failure
4022 **/
4023
4024static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4025{
4026 int i, err = 0;
4027
4028 for (i = 0; i < adapter->num_rx_queues; i++) {
4029 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4030 if (!err)
4031 continue;
4032 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4033 break;
4034 }
4035
4036 return err;
4037}
4038
9a799d71
AK		 4039/**
4040 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4041 * @adapter: board private structure
4042 * @tx_ring: Tx descriptor ring for a specific queue
4043 *
4044 * Free all transmit software resources
4045 **/
c431f97e
JB		 4046void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4047 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4048{
4049 struct pci_dev *pdev = adapter->pdev;
4050
4051 ixgbe_clean_tx_ring(adapter, tx_ring);
4052
4053 vfree(tx_ring->tx_buffer_info);
4054 tx_ring->tx_buffer_info = NULL;
4055
4056 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4057
4058 tx_ring->desc = NULL;
4059}
4060
4061/**
4062 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4063 * @adapter: board private structure
4064 *
4065 * Free all transmit software resources
4066 **/
4067static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4068{
4069 int i;
4070
4071 for (i = 0; i < adapter->num_tx_queues; i++)
9891ca7c
JB		 4072 if (adapter->tx_ring[i].desc)
4073 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 4074}
4075
4076/**
b4617240 4077 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4078 * @adapter: board private structure
4079 * @rx_ring: ring to clean the resources from
4080 *
4081 * Free all receive software resources
4082 **/
c431f97e
JB		 4083void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4084 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4085{
4086 struct pci_dev *pdev = adapter->pdev;
4087
4088 ixgbe_clean_rx_ring(adapter, rx_ring);
4089
4090 vfree(rx_ring->rx_buffer_info);
4091 rx_ring->rx_buffer_info = NULL;
4092
4093 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4094
4095 rx_ring->desc = NULL;
4096}
4097
4098/**
4099 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4100 * @adapter: board private structure
4101 *
4102 * Free all receive software resources
4103 **/
4104static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4105{
4106 int i;
4107
4108 for (i = 0; i < adapter->num_rx_queues; i++)
9891ca7c
JB		 4109 if (adapter->rx_ring[i].desc)
4110 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 4111}
4112
9a799d71
AK		 4113/**
4114 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4115 * @netdev: network interface device structure
4116 * @new_mtu: new value for maximum frame size
4117 *
4118 * Returns 0 on success, negative on failure
4119 **/
4120static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4121{
4122 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4123 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4124
42c783c5
JB		 4125 /* MTU < 68 is an error and causes problems on some kernels */
4126 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 4127 return -EINVAL;
4128
021230d4 4129 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 4130 netdev->mtu, new_mtu);
021230d4 4131 /* must set new MTU before calling down or up */
9a799d71
AK		 4132 netdev->mtu = new_mtu;
4133
d4f80882
AV		 4134 if (netif_running(netdev))
4135 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4136
4137 return 0;
4138}
4139
4140/**
4141 * ixgbe_open - Called when a network interface is made active
4142 * @netdev: network interface device structure
4143 *
4144 * Returns 0 on success, negative value on failure
4145 *
4146 * The open entry point is called when a network interface is made
4147 * active by the system (IFF_UP). At this point all resources needed
4148 * for transmit and receive operations are allocated, the interrupt
4149 * handler is registered with the OS, the watchdog timer is started,
4150 * and the stack is notified that the interface is ready.
4151 **/
4152static int ixgbe_open(struct net_device *netdev)
4153{
4154 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4155 int err;
4bebfaa5
AK		 4156
4157 /* disallow open during test */
4158 if (test_bit(__IXGBE_TESTING, &adapter->state))
4159 return -EBUSY;
9a799d71 4160
54386467
JB		 4161 netif_carrier_off(netdev);
4162
9a799d71
AK		 4163 /* allocate transmit descriptors */
4164 err = ixgbe_setup_all_tx_resources(adapter);
4165 if (err)
4166 goto err_setup_tx;
4167
9a799d71
AK		 4168 /* allocate receive descriptors */
4169 err = ixgbe_setup_all_rx_resources(adapter);
4170 if (err)
4171 goto err_setup_rx;
4172
4173 ixgbe_configure(adapter);
4174
021230d4 4175 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4176 if (err)
4177 goto err_req_irq;
4178
9a799d71
AK		 4179 err = ixgbe_up_complete(adapter);
4180 if (err)
4181 goto err_up;
4182
d55b53ff
JK		 4183 netif_tx_start_all_queues(netdev);
4184
9a799d71
AK		 4185 return 0;
4186
4187err_up:
5eba3699 4188 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4189 ixgbe_free_irq(adapter);
4190err_req_irq:
9a799d71 4191err_setup_rx:
a20a1199 4192 ixgbe_free_all_rx_resources(adapter);
9a799d71 4193err_setup_tx:
a20a1199 4194 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 4195 ixgbe_reset(adapter);
4196
4197 return err;
4198}
4199
4200/**
4201 * ixgbe_close - Disables a network interface
4202 * @netdev: network interface device structure
4203 *
4204 * Returns 0, this is not allowed to fail
4205 *
4206 * The close entry point is called when an interface is de-activated
4207 * by the OS. The hardware is still under the drivers control, but
4208 * needs to be disabled. A global MAC reset is issued to stop the
4209 * hardware, and all transmit and receive resources are freed.
4210 **/
4211static int ixgbe_close(struct net_device *netdev)
4212{
4213 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4214
4215 ixgbe_down(adapter);
4216 ixgbe_free_irq(adapter);
4217
4218 ixgbe_free_all_tx_resources(adapter);
4219 ixgbe_free_all_rx_resources(adapter);
4220
5eba3699 4221 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4222
4223 return 0;
4224}
4225
b3c8b4ba
AD		 4226#ifdef CONFIG_PM
4227static int ixgbe_resume(struct pci_dev *pdev)
4228{
4229 struct net_device *netdev = pci_get_drvdata(pdev);
4230 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4231 u32 err;
4232
4233 pci_set_power_state(pdev, PCI_D0);
4234 pci_restore_state(pdev);
9ce77666 4235
4236 err = pci_enable_device_mem(pdev);
b3c8b4ba 4237 if (err) {
69888674 4238 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 4239 "suspend\n");
4240 return err;
4241 }
4242 pci_set_master(pdev);
4243
dd4d8ca6 4244 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 4245
4246 err = ixgbe_init_interrupt_scheme(adapter);
4247 if (err) {
4248 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4249 "device\n");
4250 return err;
4251 }
4252
b3c8b4ba
AD		 4253 ixgbe_reset(adapter);
4254
495dce12
WJP		 4255 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4256
b3c8b4ba
AD		 4257 if (netif_running(netdev)) {
4258 err = ixgbe_open(adapter->netdev);
4259 if (err)
4260 return err;
4261 }
4262
4263 netif_device_attach(netdev);
4264
4265 return 0;
4266}
b3c8b4ba 4267#endif /* CONFIG_PM */
9d8d05ae
RW		 4268
4269static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 4270{
4271 struct net_device *netdev = pci_get_drvdata(pdev);
4272 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 4273 struct ixgbe_hw *hw = &adapter->hw;
4274 u32 ctrl, fctrl;
4275 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4276#ifdef CONFIG_PM
4277 int retval = 0;
4278#endif
4279
4280 netif_device_detach(netdev);
4281
4282 if (netif_running(netdev)) {
4283 ixgbe_down(adapter);
4284 ixgbe_free_irq(adapter);
4285 ixgbe_free_all_tx_resources(adapter);
4286 ixgbe_free_all_rx_resources(adapter);
4287 }
7a921c93 4288 ixgbe_clear_interrupt_scheme(adapter);
b3c8b4ba
AD		 4289
4290#ifdef CONFIG_PM
4291 retval = pci_save_state(pdev);
4292 if (retval)
4293 return retval;
4df10466 4294
b3c8b4ba 4295#endif
e8e26350
PW		 4296 if (wufc) {
4297 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4298
e8e26350
PW		 4299 /* turn on all-multi mode if wake on multicast is enabled */
4300 if (wufc & IXGBE_WUFC_MC) {
4301 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4302 fctrl |= IXGBE_FCTRL_MPE;
4303 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4304 }
4305
4306 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4307 ctrl |= IXGBE_CTRL_GIO_DIS;
4308 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4309
4310 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4311 } else {
4312 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4313 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4314 }
4315
dd4d8ca6
DS		 4316 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4317 pci_wake_from_d3(pdev, true);
4318 else
4319 pci_wake_from_d3(pdev, false);
b3c8b4ba 4320
9d8d05ae
RW		 4321 *enable_wake = !!wufc;
4322
b3c8b4ba
AD		 4323 ixgbe_release_hw_control(adapter);
4324
4325 pci_disable_device(pdev);
4326
9d8d05ae
RW		 4327 return 0;
4328}
4329
4330#ifdef CONFIG_PM
4331static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4332{
4333 int retval;
4334 bool wake;
4335
4336 retval = __ixgbe_shutdown(pdev, &wake);
4337 if (retval)
4338 return retval;
4339
4340 if (wake) {
4341 pci_prepare_to_sleep(pdev);
4342 } else {
4343 pci_wake_from_d3(pdev, false);
4344 pci_set_power_state(pdev, PCI_D3hot);
4345 }
b3c8b4ba
AD		 4346
4347 return 0;
4348}
9d8d05ae 4349#endif /* CONFIG_PM */
b3c8b4ba
AD		 4350
4351static void ixgbe_shutdown(struct pci_dev *pdev)
4352{
9d8d05ae
RW		 4353 bool wake;
4354
4355 __ixgbe_shutdown(pdev, &wake);
4356
4357 if (system_state == SYSTEM_POWER_OFF) {
4358 pci_wake_from_d3(pdev, wake);
4359 pci_set_power_state(pdev, PCI_D3hot);
4360 }
b3c8b4ba
AD		 4361}
4362
9a799d71
AK		 4363/**
4364 * ixgbe_update_stats - Update the board statistics counters.
4365 * @adapter: board private structure
4366 **/
4367void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4368{
4369 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 4370 u64 total_mpc = 0;
4371 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71 4372
d51019a4 4373 if (hw->mac.type == ixgbe_mac_82599EB) {
f8212f97 4374 u64 rsc_count = 0;
d51019a4
PW		 4375 for (i = 0; i < 16; i++)
4376 adapter->hw_rx_no_dma_resources +=
4377 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
f8212f97
AD		 4378 for (i = 0; i < adapter->num_rx_queues; i++)
4379 rsc_count += adapter->rx_ring[i].rsc_count;
4380 adapter->rsc_count = rsc_count;
d51019a4
PW		 4381 }
4382
9a799d71 4383 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 4384 for (i = 0; i < 8; i++) {
4385 /* for packet buffers not used, the register should read 0 */
4386 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4387 missed_rx += mpc;
4388 adapter->stats.mpc[i] += mpc;
4389 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 4390 if (hw->mac.type == ixgbe_mac_82598EB)
4391 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 4392 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4393 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4394 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4395 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 4396 if (hw->mac.type == ixgbe_mac_82599EB) {
4397 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4398 IXGBE_PXONRXCNT(i));
4399 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4400 IXGBE_PXOFFRXCNT(i));
4401 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 4402 } else {
4403 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4404 IXGBE_PXONRXC(i));
4405 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4406 IXGBE_PXOFFRXC(i));
4407 }
2f90b865
AD		 4408 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4409 IXGBE_PXONTXC(i));
2f90b865 4410 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 4411 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 4412 }
4413 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4414 /* work around hardware counting issue */
4415 adapter->stats.gprc -= missed_rx;
4416
4417 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350
PW		 4418 if (hw->mac.type == ixgbe_mac_82599EB) {
4419 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4420 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
4421 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4422 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
4423 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4424 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4425 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4426 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
c4cf55e5
PWJ		 4427 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4428 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c
YZ		 4429#ifdef IXGBE_FCOE
4430 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4431 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4432 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4433 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4434 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4435 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4436#endif /* IXGBE_FCOE */
e8e26350
PW		 4437 } else {
4438 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4439 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4440 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4441 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4442 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4443 }
9a799d71
AK		 4444 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4445 adapter->stats.bprc += bprc;
4446 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 4447 if (hw->mac.type == ixgbe_mac_82598EB)
4448 adapter->stats.mprc -= bprc;
9a799d71
AK		 4449 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4450 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4451 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4452 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4453 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4454 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4455 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 4456 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 4457 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4458 adapter->stats.lxontxc += lxon;
4459 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4460 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 4461 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4462 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 4463 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4464 /*
4465 * 82598 errata - tx of flow control packets is included in tx counters
4466 */
4467 xon_off_tot = lxon + lxoff;
4468 adapter->stats.gptc -= xon_off_tot;
4469 adapter->stats.mptc -= xon_off_tot;
4470 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 4471 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4472 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4473 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 4474 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4475 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 4476 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 4477 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4478 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4479 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4480 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4481 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 4482 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4483
4484 /* Fill out the OS statistics structure */
9a799d71
AK		 4485 adapter->net_stats.multicast = adapter->stats.mprc;
4486
4487 /* Rx Errors */
4488 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
b4617240 4489 adapter->stats.rlec;
9a799d71
AK		 4490 adapter->net_stats.rx_dropped = 0;
4491 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4492 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 4493 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 4494}
4495
4496/**
4497 * ixgbe_watchdog - Timer Call-back
4498 * @data: pointer to adapter cast into an unsigned long
4499 **/
4500static void ixgbe_watchdog(unsigned long data)
4501{
4502 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 4503 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 4504 u64 eics = 0;
4505 int i;
cf8280ee 4506
fe49f04a
AD		 4507 /*
4508 * Do the watchdog outside of interrupt context due to the lovely
4509 * delays that some of the newer hardware requires
4510 */
22d5a71b 4511
fe49f04a
AD		 4512 if (test_bit(__IXGBE_DOWN, &adapter->state))
4513 goto watchdog_short_circuit;
22d5a71b 4514
fe49f04a
AD		 4515 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4516 /*
4517 * for legacy and MSI interrupts don't set any bits
4518 * that are enabled for EIAM, because this operation
4519 * would set *both* EIMS and EICS for any bit in EIAM
4520 */
4521 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4522 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4523 goto watchdog_reschedule;
4524 }
4525
4526 /* get one bit for every active tx/rx interrupt vector */
4527 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4528 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4529 if (qv->rxr_count || qv->txr_count)
4530 eics |= ((u64)1 << i);
cf8280ee 4531 }
9a799d71 4532
fe49f04a
AD		 4533 /* Cause software interrupt to ensure rx rings are cleaned */
4534 ixgbe_irq_rearm_queues(adapter, eics);
4535
4536watchdog_reschedule:
4537 /* Reset the timer */
4538 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4539
4540watchdog_short_circuit:
cf8280ee
JB		 4541 schedule_work(&adapter->watchdog_task);
4542}
4543
e8e26350
PW		 4544/**
4545 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4546 * @work: pointer to work_struct containing our data
4547 **/
4548static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4549{
4550 struct ixgbe_adapter *adapter = container_of(work,
4551 struct ixgbe_adapter,
4552 multispeed_fiber_task);
4553 struct ixgbe_hw *hw = &adapter->hw;
4554 u32 autoneg;
8620a103 4555 bool negotiation;
e8e26350
PW		 4556
4557 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 4558 autoneg = hw->phy.autoneg_advertised;
4559 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103
MC		 4560 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4561 if (hw->mac.ops.setup_link)
4562 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 4563 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4564 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4565}
4566
4567/**
4568 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4569 * @work: pointer to work_struct containing our data
4570 **/
4571static void ixgbe_sfp_config_module_task(struct work_struct *work)
4572{
4573 struct ixgbe_adapter *adapter = container_of(work,
4574 struct ixgbe_adapter,
4575 sfp_config_module_task);
4576 struct ixgbe_hw *hw = &adapter->hw;
4577 u32 err;
4578
4579 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 4580
4581 /* Time for electrical oscillations to settle down */
4582 msleep(100);
e8e26350 4583 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4584
e8e26350 4585 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 4586 dev_err(&adapter->pdev->dev, "failed to initialize because "
4587 "an unsupported SFP+ module type was detected.\n"
4588 "Reload the driver after installing a supported "
4589 "module.\n");
63d6e1d8 4590 unregister_netdev(adapter->netdev);
e8e26350
PW		 4591 return;
4592 }
4593 hw->mac.ops.setup_sfp(hw);
4594
8d1c3c07 4595 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 4596 /* This will also work for DA Twinax connections */
4597 schedule_work(&adapter->multispeed_fiber_task);
4598 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4599}
4600
c4cf55e5
PWJ		 4601/**
4602 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4603 * @work: pointer to work_struct containing our data
4604 **/
4605static void ixgbe_fdir_reinit_task(struct work_struct *work)
4606{
4607 struct ixgbe_adapter *adapter = container_of(work,
4608 struct ixgbe_adapter,
4609 fdir_reinit_task);
4610 struct ixgbe_hw *hw = &adapter->hw;
4611 int i;
4612
4613 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4614 for (i = 0; i < adapter->num_tx_queues; i++)
4615 set_bit(__IXGBE_FDIR_INIT_DONE,
4616 &(adapter->tx_ring[i].reinit_state));
4617 } else {
4618 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4619 "ignored adding FDIR ATR filters \n");
4620 }
4621 /* Done FDIR Re-initialization, enable transmits */
4622 netif_tx_start_all_queues(adapter->netdev);
4623}
4624
cf8280ee 4625/**
69888674
AD		 4626 * ixgbe_watchdog_task - worker thread to bring link up
4627 * @work: pointer to work_struct containing our data
cf8280ee
JB		 4628 **/
4629static void ixgbe_watchdog_task(struct work_struct *work)
4630{
4631 struct ixgbe_adapter *adapter = container_of(work,
4632 struct ixgbe_adapter,
4633 watchdog_task);
4634 struct net_device *netdev = adapter->netdev;
4635 struct ixgbe_hw *hw = &adapter->hw;
4636 u32 link_speed = adapter->link_speed;
4637 bool link_up = adapter->link_up;
bc59fcda
NS		 4638 int i;
4639 struct ixgbe_ring *tx_ring;
4640 int some_tx_pending = 0;
cf8280ee
JB		 4641
4642 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4643
4644 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4645 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 4646 if (link_up) {
4647#ifdef CONFIG_DCB
4648 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4649 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 4650 hw->mac.ops.fc_enable(hw, i);
264857b8 4651 } else {
620fa036 4652 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 4653 }
4654#else
620fa036 4655 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 4656#endif
4657 }
4658
cf8280ee
JB		 4659 if (link_up ||
4660 time_after(jiffies, (adapter->link_check_timeout +
4661 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 4662 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 4663 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 4664 }
4665 adapter->link_up = link_up;
4666 adapter->link_speed = link_speed;
4667 }
9a799d71
AK		 4668
4669 if (link_up) {
4670 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 4671 bool flow_rx, flow_tx;
4672
4673 if (hw->mac.type == ixgbe_mac_82599EB) {
4674 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4675 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 4676 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
4677 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 4678 } else {
4679 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4680 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 4681 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
4682 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 4683 }
4684
a46e534b
JK		 4685 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4686 "Flow Control: %s\n",
4687 netdev->name,
4688 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4689 "10 Gbps" :
4690 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4691 "1 Gbps" : "unknown speed")),
e8e26350
PW		 4692 ((flow_rx && flow_tx) ? "RX/TX" :
4693 (flow_rx ? "RX" :
4694 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 4695
4696 netif_carrier_on(netdev);
9a799d71
AK		 4697 } else {
4698 /* Force detection of hung controller */
4699 adapter->detect_tx_hung = true;
4700 }
4701 } else {
cf8280ee
JB		 4702 adapter->link_up = false;
4703 adapter->link_speed = 0;
9a799d71 4704 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 4705 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4706 netdev->name);
9a799d71 4707 netif_carrier_off(netdev);
9a799d71
AK		 4708 }
4709 }
4710
bc59fcda
NS		 4711 if (!netif_carrier_ok(netdev)) {
4712 for (i = 0; i < adapter->num_tx_queues; i++) {
4713 tx_ring = &adapter->tx_ring[i];
4714 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4715 some_tx_pending = 1;
4716 break;
4717 }
4718 }
4719
4720 if (some_tx_pending) {
4721 /* We've lost link, so the controller stops DMA,
4722 * but we've got queued Tx work that's never going
4723 * to get done, so reset controller to flush Tx.
4724 * (Do the reset outside of interrupt context).
4725 */
4726 schedule_work(&adapter->reset_task);
4727 }
4728 }
4729
9a799d71 4730 ixgbe_update_stats(adapter);
cf8280ee 4731 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 4732}
4733
9a799d71 4734static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 4735 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4736 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 4737{
4738 struct ixgbe_adv_tx_context_desc *context_desc;
4739 unsigned int i;
4740 int err;
4741 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 4742 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4743 u32 mss_l4len_idx, l4len;
9a799d71
AK		 4744
4745 if (skb_is_gso(skb)) {
4746 if (skb_header_cloned(skb)) {
4747 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4748 if (err)
4749 return err;
4750 }
4751 l4len = tcp_hdrlen(skb);
4752 *hdr_len += l4len;
4753
8327d000 4754 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 4755 struct iphdr *iph = ip_hdr(skb);
4756 iph->tot_len = 0;
4757 iph->check = 0;
4758 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 4759 iph->daddr, 0,
4760 IPPROTO_TCP,
4761 0);
9a799d71
AK		 4762 adapter->hw_tso_ctxt++;
4763 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4764 ipv6_hdr(skb)->payload_len = 0;
4765 tcp_hdr(skb)->check =
4766 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 4767 &ipv6_hdr(skb)->daddr,
4768 0, IPPROTO_TCP, 0);
9a799d71
AK		 4769 adapter->hw_tso6_ctxt++;
4770 }
4771
4772 i = tx_ring->next_to_use;
4773
4774 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4775 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4776
4777 /* VLAN MACLEN IPLEN */
4778 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4779 vlan_macip_lens |=
4780 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4781 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 4782 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4783 *hdr_len += skb_network_offset(skb);
4784 vlan_macip_lens |=
4785 (skb_transport_header(skb) - skb_network_header(skb));
4786 *hdr_len +=
4787 (skb_transport_header(skb) - skb_network_header(skb));
4788 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4789 context_desc->seqnum_seed = 0;
4790
4791 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 4792 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 4793 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 4794
8327d000 4795 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4796 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4797 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4798 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4799
4800 /* MSS L4LEN IDX */
9f8cdf4f 4801 mss_l4len_idx =
9a799d71
AK		 4802 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4803 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 4804 /* use index 1 for TSO */
4805 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4806 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4807
4808 tx_buffer_info->time_stamp = jiffies;
4809 tx_buffer_info->next_to_watch = i;
4810
4811 i++;
4812 if (i == tx_ring->count)
4813 i = 0;
4814 tx_ring->next_to_use = i;
4815
4816 return true;
4817 }
4818 return false;
4819}
4820
4821static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 4822 struct ixgbe_ring *tx_ring,
4823 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 4824{
4825 struct ixgbe_adv_tx_context_desc *context_desc;
4826 unsigned int i;
4827 struct ixgbe_tx_buffer *tx_buffer_info;
4828 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4829
4830 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4831 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4832 i = tx_ring->next_to_use;
4833 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4834 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4835
4836 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4837 vlan_macip_lens |=
4838 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4839 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 4840 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4841 if (skb->ip_summed == CHECKSUM_PARTIAL)
4842 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 4843 skb_network_header(skb));
9a799d71
AK		 4844
4845 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4846 context_desc->seqnum_seed = 0;
4847
4848 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 4849 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 4850
4851 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71 4852 switch (skb->protocol) {
09640e63 4853 case cpu_to_be16(ETH_P_IP):
9a799d71 4854 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 4855 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4856 type_tucmd_mlhl |=
b4617240 4857 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4858 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4859 type_tucmd_mlhl |=
4860 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4861 break;
09640e63 4862 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 4863 /* XXX what about other V6 headers?? */
4864 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4865 type_tucmd_mlhl |=
b4617240 4866 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4867 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4868 type_tucmd_mlhl |=
4869 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4870 break;
41825d71
AK		 4871 default:
4872 if (unlikely(net_ratelimit())) {
4873 DPRINTK(PROBE, WARNING,
4874 "partial checksum but proto=%x!\n",
4875 skb->protocol);
4876 }
4877 break;
4878 }
9a799d71
AK		 4879 }
4880
4881 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 4882 /* use index zero for tx checksum offload */
9a799d71
AK		 4883 context_desc->mss_l4len_idx = 0;
4884
4885 tx_buffer_info->time_stamp = jiffies;
4886 tx_buffer_info->next_to_watch = i;
9f8cdf4f 4887
9a799d71
AK		 4888 adapter->hw_csum_tx_good++;
4889 i++;
4890 if (i == tx_ring->count)
4891 i = 0;
4892 tx_ring->next_to_use = i;
4893
4894 return true;
4895 }
9f8cdf4f 4896
9a799d71
AK		 4897 return false;
4898}
4899
4900static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 4901 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 4902 struct sk_buff *skb, u32 tx_flags,
4903 unsigned int first)
9a799d71
AK		 4904{
4905 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 4906 unsigned int len;
4907 unsigned int total = skb->len;
9a799d71
AK		 4908 unsigned int offset = 0, size, count = 0, i;
4909 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4910 unsigned int f;
44df32c5 4911 dma_addr_t *map;
9a799d71
AK		 4912
4913 i = tx_ring->next_to_use;
4914
44df32c5
AD		 4915 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4916 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4917 return 0;
4918 }
4919
4920 map = skb_shinfo(skb)->dma_maps;
4921
eacd73f7
YZ		 4922 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4923 /* excluding fcoe_crc_eof for FCoE */
4924 total -= sizeof(struct fcoe_crc_eof);
4925
4926 len = min(skb_headlen(skb), total);
9a799d71
AK		 4927 while (len) {
4928 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4929 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4930
4931 tx_buffer_info->length = size;
042a53a9 4932 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
9a799d71
AK		 4933 tx_buffer_info->time_stamp = jiffies;
4934 tx_buffer_info->next_to_watch = i;
4935
4936 len -= size;
eacd73f7 4937 total -= size;
9a799d71
AK		 4938 offset += size;
4939 count++;
44df32c5
AD		 4940
4941 if (len) {
4942 i++;
4943 if (i == tx_ring->count)
4944 i = 0;
4945 }
9a799d71
AK		 4946 }
4947
4948 for (f = 0; f < nr_frags; f++) {
4949 struct skb_frag_struct *frag;
4950
4951 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 4952 len = min((unsigned int)frag->size, total);
44df32c5 4953 offset = 0;
9a799d71
AK		 4954
4955 while (len) {
44df32c5
AD		 4956 i++;
4957 if (i == tx_ring->count)
4958 i = 0;
4959
9a799d71
AK		 4960 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4961 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4962
4963 tx_buffer_info->length = size;
042a53a9 4964 tx_buffer_info->dma = map[f] + offset;
9a799d71
AK		 4965 tx_buffer_info->time_stamp = jiffies;
4966 tx_buffer_info->next_to_watch = i;
4967
4968 len -= size;
eacd73f7 4969 total -= size;
9a799d71
AK		 4970 offset += size;
4971 count++;
9a799d71 4972 }
eacd73f7
YZ		 4973 if (total == 0)
4974 break;
9a799d71 4975 }
44df32c5 4976
9a799d71
AK		 4977 tx_ring->tx_buffer_info[i].skb = skb;
4978 tx_ring->tx_buffer_info[first].next_to_watch = i;
4979
4980 return count;
4981}
4982
4983static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 4984 struct ixgbe_ring *tx_ring,
4985 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 4986{
4987 union ixgbe_adv_tx_desc *tx_desc = NULL;
4988 struct ixgbe_tx_buffer *tx_buffer_info;
4989 u32 olinfo_status = 0, cmd_type_len = 0;
4990 unsigned int i;
4991 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4992
4993 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4994
4995 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4996
4997 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4998 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4999
5000 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5001 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5002
5003 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5004 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5005
4eeae6fd
PW		 5006 /* use index 1 context for tso */
5007 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5008 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5009 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 5010 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 5011
5012 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5013 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5014 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5015
eacd73f7
YZ		 5016 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5017 olinfo_status |= IXGBE_ADVTXD_CC;
5018 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5019 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5020 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5021 }
5022
9a799d71
AK		 5023 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5024
5025 i = tx_ring->next_to_use;
5026 while (count--) {
5027 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5028 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5029 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5030 tx_desc->read.cmd_type_len =
b4617240 5031 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 5032 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 5033 i++;
5034 if (i == tx_ring->count)
5035 i = 0;
5036 }
5037
5038 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5039
5040 /*
5041 * Force memory writes to complete before letting h/w
5042 * know there are new descriptors to fetch. (Only
5043 * applicable for weak-ordered memory model archs,
5044 * such as IA-64).
5045 */
5046 wmb();
5047
5048 tx_ring->next_to_use = i;
5049 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5050}
5051
c4cf55e5
PWJ		 5052static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5053 int queue, u32 tx_flags)
5054{
5055 /* Right now, we support IPv4 only */
5056 struct ixgbe_atr_input atr_input;
5057 struct tcphdr *th;
5058 struct udphdr *uh;
5059 struct iphdr *iph = ip_hdr(skb);
5060 struct ethhdr *eth = (struct ethhdr *)skb->data;
5061 u16 vlan_id, src_port, dst_port, flex_bytes;
5062 u32 src_ipv4_addr, dst_ipv4_addr;
5063 u8 l4type = 0;
5064
5065 /* check if we're UDP or TCP */
5066 if (iph->protocol == IPPROTO_TCP) {
5067 th = tcp_hdr(skb);
5068 src_port = th->source;
5069 dst_port = th->dest;
5070 l4type |= IXGBE_ATR_L4TYPE_TCP;
5071 /* l4type IPv4 type is 0, no need to assign */
5072 } else if(iph->protocol == IPPROTO_UDP) {
5073 uh = udp_hdr(skb);
5074 src_port = uh->source;
5075 dst_port = uh->dest;
5076 l4type |= IXGBE_ATR_L4TYPE_UDP;
5077 /* l4type IPv4 type is 0, no need to assign */
5078 } else {
5079 /* Unsupported L4 header, just bail here */
5080 return;
5081 }
5082
5083 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5084
5085 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5086 IXGBE_TX_FLAGS_VLAN_SHIFT;
5087 src_ipv4_addr = iph->saddr;
5088 dst_ipv4_addr = iph->daddr;
5089 flex_bytes = eth->h_proto;
5090
5091 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5092 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5093 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5094 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5095 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5096 /* src and dst are inverted, think how the receiver sees them */
5097 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5098 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5099
5100 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5101 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5102}
5103
e092be60 5104static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5105 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 5106{
5107 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5108
30eba97a 5109 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5110 /* Herbert's original patch had:
5111 * smp_mb__after_netif_stop_queue();
5112 * but since that doesn't exist yet, just open code it. */
5113 smp_mb();
5114
5115 /* We need to check again in a case another CPU has just
5116 * made room available. */
5117 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5118 return -EBUSY;
5119
5120 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 5121 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5122 ++adapter->restart_queue;
5123 return 0;
5124}
5125
5126static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5127 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 5128{
5129 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5130 return 0;
5131 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5132}
5133
09a3b1f8
SH		 5134static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5135{
5136 struct ixgbe_adapter *adapter = netdev_priv(dev);
5137
c4cf55e5
PWJ		 5138 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5139 return smp_processor_id();
5140
09a3b1f8 5141 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
36e89d73 5142 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
09a3b1f8
SH		 5143
5144 return skb_tx_hash(dev, skb);
5145}
5146
3b29a56d
SH		 5147static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5148 struct net_device *netdev)
9a799d71
AK		 5149{
5150 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5151 struct ixgbe_ring *tx_ring;
9a799d71
AK		 5152 unsigned int first;
5153 unsigned int tx_flags = 0;
30eba97a
AV		 5154 u8 hdr_len = 0;
5155 int r_idx = 0, tso;
9a799d71
AK		 5156 int count = 0;
5157 unsigned int f;
9f8cdf4f 5158
9f8cdf4f
JB		 5159 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5160 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 5161 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5162 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5163 tx_flags |= (skb->queue_mapping << 13);
5164 }
5165 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5166 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5167 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
60127865
LL		 5168 if (skb->priority != TC_PRIO_CONTROL) {
5169 tx_flags |= (skb->queue_mapping << 13);
5170 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5171 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5172 } else {
5173 skb->queue_mapping =
5174 adapter->ring_feature[RING_F_DCB].indices-1;
5175 }
9a799d71 5176 }
eacd73f7 5177
60127865
LL		 5178 r_idx = skb->queue_mapping;
5179 tx_ring = &adapter->tx_ring[r_idx];
5180
eacd73f7 5181 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
09ad1cc0 5182 (skb->protocol == htons(ETH_P_FCOE))) {
eacd73f7 5183 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0
YZ		 5184#ifdef IXGBE_FCOE
5185 r_idx = smp_processor_id();
5186 r_idx &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5187 r_idx += adapter->ring_feature[RING_F_FCOE].mask;
5188 tx_ring = &adapter->tx_ring[r_idx];
5189#endif
5190 }
eacd73f7 5191 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 5192 if (skb_is_gso(skb) ||
5193 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 5194 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5195 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 5196 count++;
5197
9f8cdf4f
JB		 5198 count += TXD_USE_COUNT(skb_headlen(skb));
5199 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 5200 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5201
e092be60 5202 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 5203 adapter->tx_busy++;
9a799d71
AK		 5204 return NETDEV_TX_BUSY;
5205 }
9a799d71 5206
9a799d71 5207 first = tx_ring->next_to_use;
eacd73f7
YZ		 5208 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5209#ifdef IXGBE_FCOE
5210 /* setup tx offload for FCoE */
5211 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5212 if (tso < 0) {
5213 dev_kfree_skb_any(skb);
5214 return NETDEV_TX_OK;
5215 }
5216 if (tso)
5217 tx_flags |= IXGBE_TX_FLAGS_FSO;
5218#endif /* IXGBE_FCOE */
5219 } else {
5220 if (skb->protocol == htons(ETH_P_IP))
5221 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5222 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5223 if (tso < 0) {
5224 dev_kfree_skb_any(skb);
5225 return NETDEV_TX_OK;
5226 }
9a799d71 5227
eacd73f7
YZ		 5228 if (tso)
5229 tx_flags |= IXGBE_TX_FLAGS_TSO;
5230 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5231 (skb->ip_summed == CHECKSUM_PARTIAL))
5232 tx_flags |= IXGBE_TX_FLAGS_CSUM;
5233 }
9a799d71 5234
eacd73f7 5235 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 5236 if (count) {
c4cf55e5
PWJ		 5237 /* add the ATR filter if ATR is on */
5238 if (tx_ring->atr_sample_rate) {
5239 ++tx_ring->atr_count;
5240 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5241 test_bit(__IXGBE_FDIR_INIT_DONE,
5242 &tx_ring->reinit_state)) {
5243 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5244 tx_flags);
5245 tx_ring->atr_count = 0;
5246 }
5247 }
44df32c5
AD		 5248 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5249 hdr_len);
44df32c5 5250 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 5251
44df32c5
AD		 5252 } else {
5253 dev_kfree_skb_any(skb);
5254 tx_ring->tx_buffer_info[first].time_stamp = 0;
5255 tx_ring->next_to_use = first;
5256 }
9a799d71
AK		 5257
5258 return NETDEV_TX_OK;
5259}
5260
5261/**
5262 * ixgbe_get_stats - Get System Network Statistics
5263 * @netdev: network interface device structure
5264 *
5265 * Returns the address of the device statistics structure.
5266 * The statistics are actually updated from the timer callback.
5267 **/
5268static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5269{
5270 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5271
5272 /* only return the current stats */
5273 return &adapter->net_stats;
5274}
5275
5276/**
5277 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5278 * @netdev: network interface device structure
5279 * @p: pointer to an address structure
5280 *
5281 * Returns 0 on success, negative on failure
5282 **/
5283static int ixgbe_set_mac(struct net_device *netdev, void *p)
5284{
5285 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 5286 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5287 struct sockaddr *addr = p;
5288
5289 if (!is_valid_ether_addr(addr->sa_data))
5290 return -EADDRNOTAVAIL;
5291
5292 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 5293 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 5294
b4617240 5295 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 5296
5297 return 0;
5298}
5299
6b73e10d
BH		 5300static int
5301ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5302{
5303 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5304 struct ixgbe_hw *hw = &adapter->hw;
5305 u16 value;
5306 int rc;
5307
5308 if (prtad != hw->phy.mdio.prtad)
5309 return -EINVAL;
5310 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5311 if (!rc)
5312 rc = value;
5313 return rc;
5314}
5315
5316static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5317 u16 addr, u16 value)
5318{
5319 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5320 struct ixgbe_hw *hw = &adapter->hw;
5321
5322 if (prtad != hw->phy.mdio.prtad)
5323 return -EINVAL;
5324 return hw->phy.ops.write_reg(hw, addr, devad, value);
5325}
5326
5327static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5328{
5329 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5330
5331 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5332}
5333
0365e6e4
PW		 5334/**
5335 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 5336 * netdev->dev_addrs
0365e6e4
PW		 5337 * @netdev: network interface device structure
5338 *
5339 * Returns non-zero on failure
5340 **/
5341static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5342{
5343 int err = 0;
5344 struct ixgbe_adapter *adapter = netdev_priv(dev);
5345 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5346
5347 if (is_valid_ether_addr(mac->san_addr)) {
5348 rtnl_lock();
5349 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5350 rtnl_unlock();
5351 }
5352 return err;
5353}
5354
5355/**
5356 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 5357 * netdev->dev_addrs
0365e6e4
PW		 5358 * @netdev: network interface device structure
5359 *
5360 * Returns non-zero on failure
5361 **/
5362static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5363{
5364 int err = 0;
5365 struct ixgbe_adapter *adapter = netdev_priv(dev);
5366 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5367
5368 if (is_valid_ether_addr(mac->san_addr)) {
5369 rtnl_lock();
5370 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5371 rtnl_unlock();
5372 }
5373 return err;
5374}
5375
9a799d71
AK		 5376#ifdef CONFIG_NET_POLL_CONTROLLER
5377/*
5378 * Polling 'interrupt' - used by things like netconsole to send skbs
5379 * without having to re-enable interrupts. It's not called while
5380 * the interrupt routine is executing.
5381 */
5382static void ixgbe_netpoll(struct net_device *netdev)
5383{
5384 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 5385 int i;
9a799d71 5386
9a799d71 5387 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 5388 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5389 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5390 for (i = 0; i < num_q_vectors; i++) {
5391 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5392 ixgbe_msix_clean_many(0, q_vector);
5393 }
5394 } else {
5395 ixgbe_intr(adapter->pdev->irq, netdev);
5396 }
9a799d71 5397 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 5398}
5399#endif
5400
0edc3527
SH		 5401static const struct net_device_ops ixgbe_netdev_ops = {
5402 .ndo_open = ixgbe_open,
5403 .ndo_stop = ixgbe_close,
00829823 5404 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 5405 .ndo_select_queue = ixgbe_select_queue,
0edc3527 5406 .ndo_get_stats = ixgbe_get_stats,
e90d400c 5407 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 5408 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5409 .ndo_validate_addr = eth_validate_addr,
5410 .ndo_set_mac_address = ixgbe_set_mac,
5411 .ndo_change_mtu = ixgbe_change_mtu,
5412 .ndo_tx_timeout = ixgbe_tx_timeout,
5413 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5414 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5415 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 5416 .ndo_do_ioctl = ixgbe_ioctl,
0edc3527
SH		 5417#ifdef CONFIG_NET_POLL_CONTROLLER
5418 .ndo_poll_controller = ixgbe_netpoll,
5419#endif
332d4a7d
YZ		 5420#ifdef IXGBE_FCOE
5421 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5422 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 5423 .ndo_fcoe_enable = ixgbe_fcoe_enable,
5424 .ndo_fcoe_disable = ixgbe_fcoe_disable,
332d4a7d 5425#endif /* IXGBE_FCOE */
0edc3527
SH		 5426};
5427
9a799d71
AK		 5428/**
5429 * ixgbe_probe - Device Initialization Routine
5430 * @pdev: PCI device information struct
5431 * @ent: entry in ixgbe_pci_tbl
5432 *
5433 * Returns 0 on success, negative on failure
5434 *
5435 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5436 * The OS initialization, configuring of the adapter private structure,
5437 * and a hardware reset occur.
5438 **/
5439static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 5440 const struct pci_device_id *ent)
9a799d71
AK		 5441{
5442 struct net_device *netdev;
5443 struct ixgbe_adapter *adapter = NULL;
5444 struct ixgbe_hw *hw;
5445 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 5446 static int cards_found;
5447 int i, err, pci_using_dac;
eacd73f7
YZ		 5448#ifdef IXGBE_FCOE
5449 u16 device_caps;
5450#endif
c44ade9e 5451 u32 part_num, eec;
9a799d71 5452
9ce77666 5453 err = pci_enable_device_mem(pdev);
9a799d71
AK		 5454 if (err)
5455 return err;
5456
6a35528a
YH		 5457 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5458 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
9a799d71
AK		 5459 pci_using_dac = 1;
5460 } else {
284901a9 5461 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5462 if (err) {
284901a9 5463 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5464 if (err) {
b4617240
PW		 5465 dev_err(&pdev->dev, "No usable DMA "
5466 "configuration, aborting\n");
9a799d71
AK		 5467 goto err_dma;
5468 }
5469 }
5470 pci_using_dac = 0;
5471 }
5472
9ce77666 5473 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5474 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 5475 if (err) {
9ce77666 5476 dev_err(&pdev->dev,
5477 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 5478 goto err_pci_reg;
5479 }
5480
6fabd715
PWJ		 5481 err = pci_enable_pcie_error_reporting(pdev);
5482 if (err) {
5483 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
5484 "0x%x\n", err);
5485 /* non-fatal, continue */
5486 }
5487
9a799d71 5488 pci_set_master(pdev);
fb3b27bc 5489 pci_save_state(pdev);
9a799d71 5490
30eba97a 5491 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 5492 if (!netdev) {
5493 err = -ENOMEM;
5494 goto err_alloc_etherdev;
5495 }
5496
9a799d71
AK		 5497 SET_NETDEV_DEV(netdev, &pdev->dev);
5498
5499 pci_set_drvdata(pdev, netdev);
5500 adapter = netdev_priv(netdev);
5501
5502 adapter->netdev = netdev;
5503 adapter->pdev = pdev;
5504 hw = &adapter->hw;
5505 hw->back = adapter;
5506 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5507
05857980
JK		 5508 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5509 pci_resource_len(pdev, 0));
9a799d71
AK		 5510 if (!hw->hw_addr) {
5511 err = -EIO;
5512 goto err_ioremap;
5513 }
5514
5515 for (i = 1; i <= 5; i++) {
5516 if (pci_resource_len(pdev, i) == 0)
5517 continue;
5518 }
5519
0edc3527 5520 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 5521 ixgbe_set_ethtool_ops(netdev);
9a799d71 5522 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 5523 strcpy(netdev->name, pci_name(pdev));
5524
9a799d71
AK		 5525 adapter->bd_number = cards_found;
5526
9a799d71
AK		 5527 /* Setup hw api */
5528 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 5529 hw->mac.type = ii->mac;
9a799d71 5530
c44ade9e
JB		 5531 /* EEPROM */
5532 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5533 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5534 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5535 if (!(eec & (1 << 8)))
5536 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5537
5538 /* PHY */
5539 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 5540 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 5541 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5542 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5543 hw->phy.mdio.mmds = 0;
5544 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5545 hw->phy.mdio.dev = netdev;
5546 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5547 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 5548
5549 /* set up this timer and work struct before calling get_invariants
5550 * which might start the timer
5551 */
5552 init_timer(&adapter->sfp_timer);
5553 adapter->sfp_timer.function = &ixgbe_sfp_timer;
5554 adapter->sfp_timer.data = (unsigned long) adapter;
5555
5556 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 5557
e8e26350
PW		 5558 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5559 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5560
5561 /* a new SFP+ module arrival, called from GPI SDP2 context */
5562 INIT_WORK(&adapter->sfp_config_module_task,
5563 ixgbe_sfp_config_module_task);
5564
8ca783ab 5565 ii->get_invariants(hw);
9a799d71
AK		 5566
5567 /* setup the private structure */
5568 err = ixgbe_sw_init(adapter);
5569 if (err)
5570 goto err_sw_init;
5571
bf069c97
DS		 5572 /*
5573 * If there is a fan on this device and it has failed log the
5574 * failure.
5575 */
5576 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5577 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5578 if (esdp & IXGBE_ESDP_SDP1)
5579 DPRINTK(PROBE, CRIT,
5580 "Fan has stopped, replace the adapter\n");
5581 }
5582
c44ade9e
JB		 5583 /* reset_hw fills in the perm_addr as well */
5584 err = hw->mac.ops.reset_hw(hw);
8ca783ab
DS		 5585 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5586 hw->mac.type == ixgbe_mac_82598EB) {
5587 /*
5588 * Start a kernel thread to watch for a module to arrive.
5589 * Only do this for 82598, since 82599 will generate
5590 * interrupts on module arrival.
5591 */
5592 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5593 mod_timer(&adapter->sfp_timer,
5594 round_jiffies(jiffies + (2 * HZ)));
5595 err = 0;
5596 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 5597 dev_err(&adapter->pdev->dev, "failed to initialize because "
5598 "an unsupported SFP+ module type was detected.\n"
5599 "Reload the driver after installing a supported "
5600 "module.\n");
04f165ef
PW		 5601 goto err_sw_init;
5602 } else if (err) {
c44ade9e
JB		 5603 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5604 goto err_sw_init;
5605 }
5606
9a799d71 5607 netdev->features = NETIF_F_SG |
b4617240
PW		 5608 NETIF_F_IP_CSUM |
5609 NETIF_F_HW_VLAN_TX |
5610 NETIF_F_HW_VLAN_RX |
5611 NETIF_F_HW_VLAN_FILTER;
9a799d71 5612
e9990a9c 5613 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 5614 netdev->features |= NETIF_F_TSO;
9a799d71 5615 netdev->features |= NETIF_F_TSO6;
78b6f4ce 5616 netdev->features |= NETIF_F_GRO;
ad31c402 5617
45a5ead0
JB		 5618 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5619 netdev->features |= NETIF_F_SCTP_CSUM;
5620
ad31c402
JK		 5621 netdev->vlan_features |= NETIF_F_TSO;
5622 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 5623 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 5624 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 5625 netdev->vlan_features |= NETIF_F_SG;
5626
2f90b865
AD		 5627 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5628 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5629
7a6b6f51 5630#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5631 netdev->dcbnl_ops = &dcbnl_ops;
5632#endif
5633
eacd73f7 5634#ifdef IXGBE_FCOE
0d551589 5635 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 5636 if (hw->mac.ops.get_device_caps) {
5637 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 5638 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5639 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 5640 }
5641 }
5642#endif /* IXGBE_FCOE */
9a799d71
AK		 5643 if (pci_using_dac)
5644 netdev->features |= NETIF_F_HIGHDMA;
5645
0c19d6af 5646 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 5647 netdev->features |= NETIF_F_LRO;
5648
9a799d71 5649 /* make sure the EEPROM is good */
c44ade9e 5650 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 5651 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5652 err = -EIO;
5653 goto err_eeprom;
5654 }
5655
5656 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5657 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5658
c44ade9e
JB		 5659 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5660 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 5661 err = -EIO;
5662 goto err_eeprom;
5663 }
5664
5665 init_timer(&adapter->watchdog_timer);
5666 adapter->watchdog_timer.function = &ixgbe_watchdog;
5667 adapter->watchdog_timer.data = (unsigned long)adapter;
5668
5669 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 5670 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 5671
021230d4
AV		 5672 err = ixgbe_init_interrupt_scheme(adapter);
5673 if (err)
5674 goto err_sw_init;
9a799d71 5675
e8e26350
PW		 5676 switch (pdev->device) {
5677 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 5678 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5679 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
bdf0a550
PWJ		 5680 /* Enable ACPI wakeup in GRC */
5681 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5682 (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
e8e26350
PW		 5683 break;
5684 default:
5685 adapter->wol = 0;
5686 break;
5687 }
e8e26350
PW		 5688 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5689
04f165ef
PW		 5690 /* pick up the PCI bus settings for reporting later */
5691 hw->mac.ops.get_bus_info(hw);
5692
9a799d71 5693 /* print bus type/speed/width info */
7c510e4b 5694 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 5695 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5696 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5697 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5698 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5699 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 5700 "Unknown"),
7c510e4b 5701 netdev->dev_addr);
c44ade9e 5702 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 5703 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5704 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5705 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5706 (part_num >> 8), (part_num & 0xff));
5707 else
5708 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5709 hw->mac.type, hw->phy.type,
5710 (part_num >> 8), (part_num & 0xff));
9a799d71 5711
e8e26350 5712 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 5713 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 5714 "this card is not sufficient for optimal "
5715 "performance.\n");
0c254d86 5716 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 5717 "PCI-Express slot is required.\n");
0c254d86
AK		 5718 }
5719
34b0368c
PWJ		 5720 /* save off EEPROM version number */
5721 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5722
9a799d71 5723 /* reset the hardware with the new settings */
794caeb2 5724 err = hw->mac.ops.start_hw(hw);
c44ade9e 5725
794caeb2
PWJ		 5726 if (err == IXGBE_ERR_EEPROM_VERSION) {
5727 /* We are running on a pre-production device, log a warning */
5728 dev_warn(&pdev->dev, "This device is a pre-production "
5729 "adapter/LOM. Please be aware there may be issues "
5730 "associated with your hardware. If you are "
5731 "experiencing problems please contact your Intel or "
5732 "hardware representative who provided you with this "
5733 "hardware.\n");
5734 }
9a799d71
AK		 5735 strcpy(netdev->name, "eth%d");
5736 err = register_netdev(netdev);
5737 if (err)
5738 goto err_register;
5739
54386467
JB		 5740 /* carrier off reporting is important to ethtool even BEFORE open */
5741 netif_carrier_off(netdev);
5742
c4cf55e5
PWJ		 5743 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5744 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5745 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5746
5dd2d332 5747#ifdef CONFIG_IXGBE_DCA
652f093f 5748 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 5749 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 5750 ixgbe_setup_dca(adapter);
5751 }
5752#endif
0365e6e4
PW		 5753 /* add san mac addr to netdev */
5754 ixgbe_add_sanmac_netdev(netdev);
9a799d71
AK		 5755
5756 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5757 cards_found++;
5758 return 0;
5759
5760err_register:
5eba3699 5761 ixgbe_release_hw_control(adapter);
7a921c93 5762 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 5763err_sw_init:
5764err_eeprom:
c4900be0
DS		 5765 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5766 del_timer_sync(&adapter->sfp_timer);
5767 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5768 cancel_work_sync(&adapter->multispeed_fiber_task);
5769 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 5770 iounmap(hw->hw_addr);
5771err_ioremap:
5772 free_netdev(netdev);
5773err_alloc_etherdev:
9ce77666 5774 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5775 IORESOURCE_MEM));
9a799d71
AK		 5776err_pci_reg:
5777err_dma:
5778 pci_disable_device(pdev);
5779 return err;
5780}
5781
5782/**
5783 * ixgbe_remove - Device Removal Routine
5784 * @pdev: PCI device information struct
5785 *
5786 * ixgbe_remove is called by the PCI subsystem to alert the driver
5787 * that it should release a PCI device. The could be caused by a
5788 * Hot-Plug event, or because the driver is going to be removed from
5789 * memory.
5790 **/
5791static void __devexit ixgbe_remove(struct pci_dev *pdev)
5792{
5793 struct net_device *netdev = pci_get_drvdata(pdev);
5794 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715 5795 int err;
9a799d71
AK		 5796
5797 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 5798 /* clear the module not found bit to make sure the worker won't
5799 * reschedule
5800 */
5801 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 5802 del_timer_sync(&adapter->watchdog_timer);
5803
c4900be0
DS		 5804 del_timer_sync(&adapter->sfp_timer);
5805 cancel_work_sync(&adapter->watchdog_task);
5806 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5807 cancel_work_sync(&adapter->multispeed_fiber_task);
5808 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 5809 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5810 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5811 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 5812 flush_scheduled_work();
5813
5dd2d332 5814#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5815 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5816 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5817 dca_remove_requester(&pdev->dev);
5818 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5819 }
5820
5821#endif
332d4a7d
YZ		 5822#ifdef IXGBE_FCOE
5823 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5824 ixgbe_cleanup_fcoe(adapter);
5825
5826#endif /* IXGBE_FCOE */
0365e6e4
PW		 5827
5828 /* remove the added san mac */
5829 ixgbe_del_sanmac_netdev(netdev);
5830
c4900be0
DS		 5831 if (netdev->reg_state == NETREG_REGISTERED)
5832 unregister_netdev(netdev);
9a799d71 5833
7a921c93 5834 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 5835
021230d4 5836 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5837
5838 iounmap(adapter->hw.hw_addr);
9ce77666 5839 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5840 IORESOURCE_MEM));
9a799d71 5841
021230d4 5842 DPRINTK(PROBE, INFO, "complete\n");
021230d4 5843
9a799d71
AK		 5844 free_netdev(netdev);
5845
6fabd715
PWJ		 5846 err = pci_disable_pcie_error_reporting(pdev);
5847 if (err)
5848 dev_err(&pdev->dev,
5849 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5850
9a799d71
AK		 5851 pci_disable_device(pdev);
5852}
5853
5854/**
5855 * ixgbe_io_error_detected - called when PCI error is detected
5856 * @pdev: Pointer to PCI device
5857 * @state: The current pci connection state
5858 *
5859 * This function is called after a PCI bus error affecting
5860 * this device has been detected.
5861 */
5862static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 5863 pci_channel_state_t state)
9a799d71
AK		 5864{
5865 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5866 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5867
5868 netif_device_detach(netdev);
5869
3044b8d1
BL		 5870 if (state == pci_channel_io_perm_failure)
5871 return PCI_ERS_RESULT_DISCONNECT;
5872
9a799d71
AK		 5873 if (netif_running(netdev))
5874 ixgbe_down(adapter);
5875 pci_disable_device(pdev);
5876
b4617240 5877 /* Request a slot reset. */
9a799d71
AK		 5878 return PCI_ERS_RESULT_NEED_RESET;
5879}
5880
5881/**
5882 * ixgbe_io_slot_reset - called after the pci bus has been reset.
5883 * @pdev: Pointer to PCI device
5884 *
5885 * Restart the card from scratch, as if from a cold-boot.
5886 */
5887static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5888{
5889 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5890 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 5891 pci_ers_result_t result;
5892 int err;
9a799d71 5893
9ce77666 5894 if (pci_enable_device_mem(pdev)) {
9a799d71 5895 DPRINTK(PROBE, ERR,
b4617240 5896 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 5897 result = PCI_ERS_RESULT_DISCONNECT;
5898 } else {
5899 pci_set_master(pdev);
5900 pci_restore_state(pdev);
9a799d71 5901
dd4d8ca6 5902 pci_wake_from_d3(pdev, false);
9a799d71 5903
6fabd715 5904 ixgbe_reset(adapter);
88512539 5905 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 5906 result = PCI_ERS_RESULT_RECOVERED;
5907 }
5908
5909 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5910 if (err) {
5911 dev_err(&pdev->dev,
5912 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5913 /* non-fatal, continue */
5914 }
9a799d71 5915
6fabd715 5916 return result;
9a799d71
AK		 5917}
5918
5919/**
5920 * ixgbe_io_resume - called when traffic can start flowing again.
5921 * @pdev: Pointer to PCI device
5922 *
5923 * This callback is called when the error recovery driver tells us that
5924 * its OK to resume normal operation.
5925 */
5926static void ixgbe_io_resume(struct pci_dev *pdev)
5927{
5928 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5929 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5930
5931 if (netif_running(netdev)) {
5932 if (ixgbe_up(adapter)) {
5933 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5934 return;
5935 }
5936 }
5937
5938 netif_device_attach(netdev);
9a799d71
AK		 5939}
5940
5941static struct pci_error_handlers ixgbe_err_handler = {
5942 .error_detected = ixgbe_io_error_detected,
5943 .slot_reset = ixgbe_io_slot_reset,
5944 .resume = ixgbe_io_resume,
5945};
5946
5947static struct pci_driver ixgbe_driver = {
5948 .name = ixgbe_driver_name,
5949 .id_table = ixgbe_pci_tbl,
5950 .probe = ixgbe_probe,
5951 .remove = __devexit_p(ixgbe_remove),
5952#ifdef CONFIG_PM
5953 .suspend = ixgbe_suspend,
5954 .resume = ixgbe_resume,
5955#endif
5956 .shutdown = ixgbe_shutdown,
5957 .err_handler = &ixgbe_err_handler
5958};
5959
5960/**
5961 * ixgbe_init_module - Driver Registration Routine
5962 *
5963 * ixgbe_init_module is the first routine called when the driver is
5964 * loaded. All it does is register with the PCI subsystem.
5965 **/
5966static int __init ixgbe_init_module(void)
5967{
5968 int ret;
5969 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5970 ixgbe_driver_string, ixgbe_driver_version);
5971
5972 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5973
5dd2d332 5974#ifdef CONFIG_IXGBE_DCA
bd0362dd 5975 dca_register_notify(&dca_notifier);
bd0362dd 5976#endif
5dd2d332 5977
9a799d71
AK		 5978 ret = pci_register_driver(&ixgbe_driver);
5979 return ret;
5980}
b4617240 5981
9a799d71
AK		 5982module_init(ixgbe_init_module);
5983
5984/**
5985 * ixgbe_exit_module - Driver Exit Cleanup Routine
5986 *
5987 * ixgbe_exit_module is called just before the driver is removed
5988 * from memory.
5989 **/
5990static void __exit ixgbe_exit_module(void)
5991{
5dd2d332 5992#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5993 dca_unregister_notify(&dca_notifier);
5994#endif
9a799d71
AK		 5995 pci_unregister_driver(&ixgbe_driver);
5996}
bd0362dd 5997
5dd2d332 5998#ifdef CONFIG_IXGBE_DCA
bd0362dd 5999static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 6000 void *p)
bd0362dd
JC		 6001{
6002 int ret_val;
6003
6004 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 6005 __ixgbe_notify_dca);
bd0362dd
JC		 6006
6007 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6008}
b453368d 6009
5dd2d332 6010#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 6011#ifdef DEBUG
6012/**
6013 * ixgbe_get_hw_dev_name - return device name string
6014 * used by hardware layer to print debugging information
6015 **/
6016char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6017{
6018 struct ixgbe_adapter *adapter = hw->back;
6019 return adapter->netdev->name;
6020}
bd0362dd 6021
b453368d 6022#endif
9a799d71
AK		 6023module_exit(ixgbe_exit_module);
6024
6025/* ixgbe_main.c */
kernel source for telekom puls (alcatel/mediatek)