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igbvf: double increment nr_frags
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71 38#include <linux/ipv6.h>
5a0e3ad6 39#include <linux/slab.h>
9a799d71
AK		 40#include <net/checksum.h>
41#include <net/ip6_checksum.h>
42#include <linux/ethtool.h>
43#include <linux/if_vlan.h>
eacd73f7 44#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 45
46#include "ixgbe.h"
47#include "ixgbe_common.h"
ee5f784a 48#include "ixgbe_dcb_82599.h"
1cdd1ec8 49#include "ixgbe_sriov.h"
9a799d71
AK		 50
51char ixgbe_driver_name[] = "ixgbe";
9c8eb720 52static const char ixgbe_driver_string[] =
b4617240 53 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 54
92eb879f 55#define DRV_VERSION "2.0.62-k2"
9c8eb720 56const char ixgbe_driver_version[] = DRV_VERSION;
8c47eaa7 57static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
9a799d71
AK		 58
59static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 60 [board_82598] = &ixgbe_82598_info,
e8e26350 61 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 62};
63
64/* ixgbe_pci_tbl - PCI Device ID Table
65 *
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
a3aa1884 72static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
74 board_82598 },
9a799d71 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 76 board_82598 },
9a799d71 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 78 board_82598 },
0befdb3e
JB		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
80 board_82598 },
3845bec0
PWJ		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
82 board_82598 },
9a799d71 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 84 board_82598 },
8d792cd9
JB		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
86 board_82598 },
c4900be0
DS		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
90 board_82598 },
b95f5fcb
JB		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
92 board_82598 },
c4900be0
DS		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
94 board_82598 },
2f21bdd3
DS		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
96 board_82598 },
e8e26350
PW		 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
98 board_82599 },
1fcf03e6
PWJ		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
100 board_82599 },
74757d49
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
102 board_82599 },
e8e26350
PW		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
104 board_82599 },
38ad1c8e
DS		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
106 board_82599 },
dbfec662
DS		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
108 board_82599 },
8911184f
PWJ		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
110 board_82599 },
312eb931
DS		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
112 board_82599 },
9a799d71
AK		 113
114 /* required last entry */
115 {0, }
116};
117MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
118
5dd2d332 119#ifdef CONFIG_IXGBE_DCA
bd0362dd 120static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 121 void *p);
bd0362dd
JC		 122static struct notifier_block dca_notifier = {
123 .notifier_call = ixgbe_notify_dca,
124 .next = NULL,
125 .priority = 0
126};
127#endif
128
1cdd1ec8
GR		 129#ifdef CONFIG_PCI_IOV
130static unsigned int max_vfs;
131module_param(max_vfs, uint, 0);
132MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
133 "per physical function");
134#endif /* CONFIG_PCI_IOV */
135
9a799d71
AK		 136MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
137MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
138MODULE_LICENSE("GPL");
139MODULE_VERSION(DRV_VERSION);
140
141#define DEFAULT_DEBUG_LEVEL_SHIFT 3
142
1cdd1ec8
GR		 143static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
144{
145 struct ixgbe_hw *hw = &adapter->hw;
146 u32 gcr;
147 u32 gpie;
148 u32 vmdctl;
149
150#ifdef CONFIG_PCI_IOV
151 /* disable iov and allow time for transactions to clear */
152 pci_disable_sriov(adapter->pdev);
153#endif
154
155 /* turn off device IOV mode */
156 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
157 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
158 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
159 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
160 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
161 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
162
163 /* set default pool back to 0 */
164 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
165 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
166 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
167
168 /* take a breather then clean up driver data */
169 msleep(100);
170 if (adapter->vfinfo)
171 kfree(adapter->vfinfo);
172 adapter->vfinfo = NULL;
173
174 adapter->num_vfs = 0;
175 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
176}
177
5eba3699
AV		 178static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
179{
180 u32 ctrl_ext;
181
182 /* Let firmware take over control of h/w */
183 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
184 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 185 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 186}
187
188static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
189{
190 u32 ctrl_ext;
191
192 /* Let firmware know the driver has taken over */
193 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
194 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 195 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 196}
9a799d71 197
e8e26350
PW		 198/*
199 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
200 * @adapter: pointer to adapter struct
201 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
202 * @queue: queue to map the corresponding interrupt to
203 * @msix_vector: the vector to map to the corresponding queue
204 *
205 */
206static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
207 u8 queue, u8 msix_vector)
9a799d71
AK		 208{
209 u32 ivar, index;
e8e26350
PW		 210 struct ixgbe_hw *hw = &adapter->hw;
211 switch (hw->mac.type) {
212 case ixgbe_mac_82598EB:
213 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
214 if (direction == -1)
215 direction = 0;
216 index = (((direction * 64) + queue) >> 2) & 0x1F;
217 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
218 ivar &= ~(0xFF << (8 * (queue & 0x3)));
219 ivar |= (msix_vector << (8 * (queue & 0x3)));
220 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
221 break;
222 case ixgbe_mac_82599EB:
223 if (direction == -1) {
224 /* other causes */
225 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
226 index = ((queue & 1) * 8);
227 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
228 ivar &= ~(0xFF << index);
229 ivar |= (msix_vector << index);
230 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
231 break;
232 } else {
233 /* tx or rx causes */
234 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
235 index = ((16 * (queue & 1)) + (8 * direction));
236 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
237 ivar &= ~(0xFF << index);
238 ivar |= (msix_vector << index);
239 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
240 break;
241 }
242 default:
243 break;
244 }
9a799d71
AK		 245}
246
fe49f04a
AD		 247static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
248 u64 qmask)
249{
250 u32 mask;
251
252 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
253 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
254 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
255 } else {
256 mask = (qmask & 0xFFFFFFFF);
257 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
258 mask = (qmask >> 32);
259 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
260 }
261}
262
9a799d71 263static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 264 struct ixgbe_tx_buffer
265 *tx_buffer_info)
9a799d71 266{
e5a43549
AD		 267 if (tx_buffer_info->dma) {
268 if (tx_buffer_info->mapped_as_page)
269 pci_unmap_page(adapter->pdev,
270 tx_buffer_info->dma,
271 tx_buffer_info->length,
272 PCI_DMA_TODEVICE);
273 else
274 pci_unmap_single(adapter->pdev,
275 tx_buffer_info->dma,
276 tx_buffer_info->length,
277 PCI_DMA_TODEVICE);
278 tx_buffer_info->dma = 0;
279 }
9a799d71
AK		 280 if (tx_buffer_info->skb) {
281 dev_kfree_skb_any(tx_buffer_info->skb);
282 tx_buffer_info->skb = NULL;
283 }
44df32c5 284 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 285 /* tx_buffer_info must be completely set up in the transmit path */
286}
287
26f23d82
YZ		 288/**
289 * ixgbe_tx_is_paused - check if the tx ring is paused
290 * @adapter: the ixgbe adapter
291 * @tx_ring: the corresponding tx_ring
292 *
293 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
294 * corresponding TC of this tx_ring when checking TFCS.
295 *
296 * Returns : true if paused
297 */
298static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
299 struct ixgbe_ring *tx_ring)
300{
26f23d82
YZ		 301 u32 txoff = IXGBE_TFCS_TXOFF;
302
303#ifdef CONFIG_IXGBE_DCB
304 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
30b76832 305 int tc;
26f23d82
YZ		 306 int reg_idx = tx_ring->reg_idx;
307 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
308
6837e895
PW		 309 switch (adapter->hw.mac.type) {
310 case ixgbe_mac_82598EB:
26f23d82
YZ		 311 tc = reg_idx >> 2;
312 txoff = IXGBE_TFCS_TXOFF0;
6837e895
PW		 313 break;
314 case ixgbe_mac_82599EB:
26f23d82
YZ		 315 tc = 0;
316 txoff = IXGBE_TFCS_TXOFF;
317 if (dcb_i == 8) {
318 /* TC0, TC1 */
319 tc = reg_idx >> 5;
320 if (tc == 2) /* TC2, TC3 */
321 tc += (reg_idx - 64) >> 4;
322 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
323 tc += 1 + ((reg_idx - 96) >> 3);
324 } else if (dcb_i == 4) {
325 /* TC0, TC1 */
326 tc = reg_idx >> 6;
327 if (tc == 1) {
328 tc += (reg_idx - 64) >> 5;
329 if (tc == 2) /* TC2, TC3 */
330 tc += (reg_idx - 96) >> 4;
331 }
332 }
6837e895
PW		 333 break;
334 default:
335 tc = 0;
26f23d82
YZ		 336 }
337 txoff <<= tc;
338 }
339#endif
340 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
341}
342
9a799d71 343static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 344 struct ixgbe_ring *tx_ring,
345 unsigned int eop)
9a799d71 346{
e01c31a5 347 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 348
9a799d71 349 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 350 * check with the clearing of time_stamp and movement of eop */
9a799d71 351 adapter->detect_tx_hung = false;
44df32c5 352 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71 353 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
26f23d82 354 !ixgbe_tx_is_paused(adapter, tx_ring)) {
9a799d71 355 /* detected Tx unit hang */
e01c31a5
JB		 356 union ixgbe_adv_tx_desc *tx_desc;
357 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 358 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 359 " Tx Queue <%d>\n"
360 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 361 " next_to_use <%x>\n"
362 " next_to_clean <%x>\n"
363 "tx_buffer_info[next_to_clean]\n"
364 " time_stamp <%lx>\n"
e01c31a5
JB		 365 " jiffies <%lx>\n",
366 tx_ring->queue_index,
44df32c5
AD		 367 IXGBE_READ_REG(hw, tx_ring->head),
368 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 369 tx_ring->next_to_use, eop,
370 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 371 return true;
372 }
373
374 return false;
375}
376
b4617240
PW		 377#define IXGBE_MAX_TXD_PWR 14
378#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 379
380/* Tx Descriptors needed, worst case */
381#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
382 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
383#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 384 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 385
e01c31a5
JB		 386static void ixgbe_tx_timeout(struct net_device *netdev);
387
9a799d71
AK		 388/**
389 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 390 * @q_vector: structure containing interrupt and ring information
e01c31a5 391 * @tx_ring: tx ring to clean
9a799d71 392 **/
fe49f04a 393static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e01c31a5 394 struct ixgbe_ring *tx_ring)
9a799d71 395{
fe49f04a 396 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 397 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 398 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
399 struct ixgbe_tx_buffer *tx_buffer_info;
400 unsigned int i, eop, count = 0;
e01c31a5 401 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 402
403 i = tx_ring->next_to_clean;
12207e49
PWJ		 404 eop = tx_ring->tx_buffer_info[i].next_to_watch;
405 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
406
407 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 408 (count < tx_ring->work_limit)) {
12207e49
PWJ		 409 bool cleaned = false;
410 for ( ; !cleaned; count++) {
411 struct sk_buff *skb;
9a799d71
AK		 412 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
413 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 414 cleaned = (i == eop);
e01c31a5 415 skb = tx_buffer_info->skb;
9a799d71 416
12207e49 417 if (cleaned && skb) {
e092be60 418 unsigned int segs, bytecount;
3d8fd385 419 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 420
421 /* gso_segs is currently only valid for tcp */
e092be60 422 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 423#ifdef IXGBE_FCOE
424 /* adjust for FCoE Sequence Offload */
425 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
426 && (skb->protocol == htons(ETH_P_FCOE)) &&
427 skb_is_gso(skb)) {
428 hlen = skb_transport_offset(skb) +
429 sizeof(struct fc_frame_header) +
430 sizeof(struct fcoe_crc_eof);
431 segs = DIV_ROUND_UP(skb->len - hlen,
432 skb_shinfo(skb)->gso_size);
433 }
434#endif /* IXGBE_FCOE */
e092be60 435 /* multiply data chunks by size of headers */
3d8fd385 436 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 437 total_packets += segs;
438 total_bytes += bytecount;
e092be60 439 }
e01c31a5 440
9a799d71 441 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 442 tx_buffer_info);
9a799d71 443
12207e49
PWJ		 444 tx_desc->wb.status = 0;
445
9a799d71
AK		 446 i++;
447 if (i == tx_ring->count)
448 i = 0;
e01c31a5 449 }
12207e49
PWJ		 450
451 eop = tx_ring->tx_buffer_info[i].next_to_watch;
452 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
453 }
454
9a799d71
AK		 455 tx_ring->next_to_clean = i;
456
e092be60 457#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 458 if (unlikely(count && netif_carrier_ok(netdev) &&
459 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 460 /* Make sure that anybody stopping the queue after this
461 * sees the new next_to_clean.
462 */
463 smp_mb();
30eba97a
AV		 464 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
465 !test_bit(__IXGBE_DOWN, &adapter->state)) {
466 netif_wake_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 467 ++tx_ring->restart_queue;
30eba97a 468 }
e092be60 469 }
9a799d71 470
e01c31a5
JB		 471 if (adapter->detect_tx_hung) {
472 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
473 /* schedule immediate reset if we believe we hung */
474 DPRINTK(PROBE, INFO,
475 "tx hang %d detected, resetting adapter\n",
476 adapter->tx_timeout_count + 1);
477 ixgbe_tx_timeout(adapter->netdev);
478 }
479 }
9a799d71 480
e01c31a5 481 /* re-arm the interrupt */
fe49f04a
AD		 482 if (count >= tx_ring->work_limit)
483 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 484
e01c31a5
JB		 485 tx_ring->total_bytes += total_bytes;
486 tx_ring->total_packets += total_packets;
e01c31a5 487 tx_ring->stats.packets += total_packets;
12207e49 488 tx_ring->stats.bytes += total_bytes;
9a1a69ad 489 return (count < tx_ring->work_limit);
9a799d71
AK		 490}
491
5dd2d332 492#ifdef CONFIG_IXGBE_DCA
bd0362dd 493static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 494 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 495{
496 u32 rxctrl;
497 int cpu = get_cpu();
4a0b9ca0 498 int q = rx_ring->reg_idx;
bd0362dd 499
3a581073 500 if (rx_ring->cpu != cpu) {
bd0362dd 501 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 502 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
503 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
504 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
505 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
506 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
507 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
508 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
509 }
bd0362dd
JC		 510 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
511 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 512 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
513 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 514 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 515 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 516 rx_ring->cpu = cpu;
bd0362dd
JC		 517 }
518 put_cpu();
519}
520
521static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 522 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 523{
524 u32 txctrl;
525 int cpu = get_cpu();
4a0b9ca0 526 int q = tx_ring->reg_idx;
ee5f784a 527 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 528
3a581073 529 if (tx_ring->cpu != cpu) {
e8e26350 530 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
ee5f784a 531 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 532 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
533 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
ee5f784a
DS		 534 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
535 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
e8e26350 536 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
ee5f784a 537 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
e8e26350
PW		 538 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
539 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
ee5f784a
DS		 540 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
541 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
542 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
e8e26350 543 }
3a581073 544 tx_ring->cpu = cpu;
bd0362dd
JC		 545 }
546 put_cpu();
547}
548
549static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
550{
551 int i;
552
553 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
554 return;
555
e35ec126
AD		 556 /* always use CB2 mode, difference is masked in the CB driver */
557 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
558
bd0362dd 559 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 560 adapter->tx_ring[i]->cpu = -1;
561 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
bd0362dd
JC		 562 }
563 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 564 adapter->rx_ring[i]->cpu = -1;
565 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
bd0362dd
JC		 566 }
567}
568
569static int __ixgbe_notify_dca(struct device *dev, void *data)
570{
571 struct net_device *netdev = dev_get_drvdata(dev);
572 struct ixgbe_adapter *adapter = netdev_priv(netdev);
573 unsigned long event = *(unsigned long *)data;
574
575 switch (event) {
576 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 577 /* if we're already enabled, don't do it again */
578 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
579 break;
652f093f 580 if (dca_add_requester(dev) == 0) {
96b0e0f6 581 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 582 ixgbe_setup_dca(adapter);
583 break;
584 }
585 /* Fall Through since DCA is disabled. */
586 case DCA_PROVIDER_REMOVE:
587 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
588 dca_remove_requester(dev);
589 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
590 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
591 }
592 break;
593 }
594
652f093f 595 return 0;
bd0362dd
JC		 596}
597
5dd2d332 598#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 599/**
600 * ixgbe_receive_skb - Send a completed packet up the stack
601 * @adapter: board private structure
602 * @skb: packet to send up
177db6ff
MC		 603 * @status: hardware indication of status of receive
604 * @rx_ring: rx descriptor ring (for a specific queue) to setup
605 * @rx_desc: rx descriptor
9a799d71 606 **/
78b6f4ce 607static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 608 struct sk_buff *skb, u8 status,
fdaff1ce 609 struct ixgbe_ring *ring,
177db6ff 610 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 611{
78b6f4ce
HX		 612 struct ixgbe_adapter *adapter = q_vector->adapter;
613 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 614 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
615 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 616
fdaff1ce 617 skb_record_rx_queue(skb, ring->queue_index);
182ff8df 618 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
8a62babf 619 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
78b6f4ce 620 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 621 else
78b6f4ce 622 napi_gro_receive(napi, skb);
177db6ff 623 } else {
8a62babf 624 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
182ff8df
AD		 625 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
626 else
627 netif_rx(skb);
9a799d71
AK		 628 }
629}
630
e59bd25d
AV		 631/**
632 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
633 * @adapter: address of board private structure
634 * @status_err: hardware indication of status of receive
635 * @skb: skb currently being received and modified
636 **/
9a799d71 637static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 638 union ixgbe_adv_rx_desc *rx_desc,
639 struct sk_buff *skb)
9a799d71 640{
8bae1b2b
DS		 641 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
642
9a799d71
AK		 643 skb->ip_summed = CHECKSUM_NONE;
644
712744be
JB		 645 /* Rx csum disabled */
646 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 647 return;
e59bd25d
AV		 648
649 /* if IP and error */
650 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
651 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 652 adapter->hw_csum_rx_error++;
653 return;
654 }
e59bd25d
AV		 655
656 if (!(status_err & IXGBE_RXD_STAT_L4CS))
657 return;
658
659 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 660 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
661
662 /*
663 * 82599 errata, UDP frames with a 0 checksum can be marked as
664 * checksum errors.
665 */
666 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
667 (adapter->hw.mac.type == ixgbe_mac_82599EB))
668 return;
669
e59bd25d
AV		 670 adapter->hw_csum_rx_error++;
671 return;
672 }
673
9a799d71 674 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 675 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 676}
677
e8e26350
PW		 678static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
679 struct ixgbe_ring *rx_ring, u32 val)
680{
681 /*
682 * Force memory writes to complete before letting h/w
683 * know there are new descriptors to fetch. (Only
684 * applicable for weak-ordered memory model archs,
685 * such as IA-64).
686 */
687 wmb();
688 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
689}
690
9a799d71
AK		 691/**
692 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
693 * @adapter: address of board private structure
694 **/
695static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 696 struct ixgbe_ring *rx_ring,
697 int cleaned_count)
9a799d71 698{
9a799d71
AK		 699 struct pci_dev *pdev = adapter->pdev;
700 union ixgbe_adv_rx_desc *rx_desc;
3a581073 701 struct ixgbe_rx_buffer *bi;
9a799d71 702 unsigned int i;
9a799d71
AK		 703
704 i = rx_ring->next_to_use;
3a581073 705 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 706
707 while (cleaned_count--) {
708 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
709
762f4c57 710 if (!bi->page_dma &&
6e455b89 711 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 712 if (!bi->page) {
762f4c57
JB		 713 bi->page = alloc_page(GFP_ATOMIC);
714 if (!bi->page) {
715 adapter->alloc_rx_page_failed++;
716 goto no_buffers;
717 }
718 bi->page_offset = 0;
719 } else {
720 /* use a half page if we're re-using */
721 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 722 }
762f4c57
JB		 723
724 bi->page_dma = pci_map_page(pdev, bi->page,
725 bi->page_offset,
726 (PAGE_SIZE / 2),
727 PCI_DMA_FROMDEVICE);
9a799d71
AK		 728 }
729
3a581073 730 if (!bi->skb) {
5ecc3614 731 struct sk_buff *skb;
7ca3bc58
JB		 732 /* netdev_alloc_skb reserves 32 bytes up front!! */
733 uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES;
734 skb = netdev_alloc_skb(adapter->netdev, bufsz);
9a799d71
AK		 735
736 if (!skb) {
737 adapter->alloc_rx_buff_failed++;
738 goto no_buffers;
739 }
740
7ca3bc58
JB		 741 /* advance the data pointer to the next cache line */
742 skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES)
743 - skb->data));
744
3a581073 745 bi->skb = skb;
4f57ca6e
JB		 746 bi->dma = pci_map_single(pdev, skb->data,
747 rx_ring->rx_buf_len,
3a581073 748 PCI_DMA_FROMDEVICE);
9a799d71
AK		 749 }
750 /* Refresh the desc even if buffer_addrs didn't change because
751 * each write-back erases this info. */
6e455b89 752 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 753 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
754 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 755 } else {
3a581073 756 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 757 }
758
759 i++;
760 if (i == rx_ring->count)
761 i = 0;
3a581073 762 bi = &rx_ring->rx_buffer_info[i];
9a799d71 763 }
7c6e0a43 764
9a799d71
AK		 765no_buffers:
766 if (rx_ring->next_to_use != i) {
767 rx_ring->next_to_use = i;
768 if (i-- == 0)
769 i = (rx_ring->count - 1);
770
e8e26350 771 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 772 }
773}
774
7c6e0a43
JB		 775static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
776{
777 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
778}
779
780static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
781{
782 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
783}
784
f8212f97
AD		 785static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
786{
787 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
788 IXGBE_RXDADV_RSCCNT_MASK) >>
789 IXGBE_RXDADV_RSCCNT_SHIFT;
790}
791
792/**
793 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
794 * @skb: pointer to the last skb in the rsc queue
94b982b2 795 * @count: pointer to number of packets coalesced in this context
f8212f97
AD		 796 *
797 * This function changes a queue full of hw rsc buffers into a completed
798 * packet. It uses the ->prev pointers to find the first packet and then
799 * turns it into the frag list owner.
800 **/
94b982b2
MC		 801static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
802 u64 *count)
f8212f97
AD		 803{
804 unsigned int frag_list_size = 0;
805
806 while (skb->prev) {
807 struct sk_buff *prev = skb->prev;
808 frag_list_size += skb->len;
809 skb->prev = NULL;
810 skb = prev;
94b982b2 811 *count += 1;
f8212f97
AD		 812 }
813
814 skb_shinfo(skb)->frag_list = skb->next;
815 skb->next = NULL;
816 skb->len += frag_list_size;
817 skb->data_len += frag_list_size;
818 skb->truesize += frag_list_size;
819 return skb;
820}
821
43634e82
MC		 822struct ixgbe_rsc_cb {
823 dma_addr_t dma;
824};
825
826#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
827
78b6f4ce 828static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 829 struct ixgbe_ring *rx_ring,
830 int *work_done, int work_to_do)
9a799d71 831{
78b6f4ce 832 struct ixgbe_adapter *adapter = q_vector->adapter;
2d86f139 833 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 834 struct pci_dev *pdev = adapter->pdev;
835 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
836 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
837 struct sk_buff *skb;
f8212f97 838 unsigned int i, rsc_count = 0;
7c6e0a43 839 u32 len, staterr;
177db6ff
MC		 840 u16 hdr_info;
841 bool cleaned = false;
9a799d71 842 int cleaned_count = 0;
d2f4fbe2 843 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 844#ifdef IXGBE_FCOE
845 int ddp_bytes = 0;
846#endif /* IXGBE_FCOE */
9a799d71
AK		 847
848 i = rx_ring->next_to_clean;
9a799d71
AK		 849 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
850 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
851 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 852
853 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 854 u32 upper_len = 0;
9a799d71
AK		 855 if (*work_done >= work_to_do)
856 break;
857 (*work_done)++;
858
3c945e5b 859 rmb(); /* read descriptor and rx_buffer_info after status DD */
6e455b89 860 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 861 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
862 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 863 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 864 if (len > IXGBE_RX_HDR_SIZE)
865 len = IXGBE_RX_HDR_SIZE;
866 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 867 } else {
9a799d71 868 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 869 }
9a799d71
AK		 870
871 cleaned = true;
872 skb = rx_buffer_info->skb;
7ca3bc58 873 prefetch(skb->data);
9a799d71
AK		 874 rx_buffer_info->skb = NULL;
875
21fa4e66 876 if (rx_buffer_info->dma) {
43634e82
MC		 877 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
878 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
879 (!(skb->prev)))
880 /*
881 * When HWRSC is enabled, delay unmapping
882 * of the first packet. It carries the
883 * header information, HW may still
884 * access the header after the writeback.
885 * Only unmap it when EOP is reached
886 */
887 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
888 else
889 pci_unmap_single(pdev, rx_buffer_info->dma,
890 rx_ring->rx_buf_len,
891 PCI_DMA_FROMDEVICE);
4f57ca6e 892 rx_buffer_info->dma = 0;
9a799d71
AK		 893 skb_put(skb, len);
894 }
895
896 if (upper_len) {
897 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 898 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 899 rx_buffer_info->page_dma = 0;
900 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 901 rx_buffer_info->page,
902 rx_buffer_info->page_offset,
903 upper_len);
904
905 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
906 (page_count(rx_buffer_info->page) != 1))
907 rx_buffer_info->page = NULL;
908 else
909 get_page(rx_buffer_info->page);
9a799d71
AK		 910
911 skb->len += upper_len;
912 skb->data_len += upper_len;
913 skb->truesize += upper_len;
914 }
915
916 i++;
917 if (i == rx_ring->count)
918 i = 0;
9a799d71
AK		 919
920 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
921 prefetch(next_rxd);
9a799d71 922 cleaned_count++;
f8212f97 923
0c19d6af 924 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 925 rsc_count = ixgbe_get_rsc_count(rx_desc);
926
927 if (rsc_count) {
928 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
929 IXGBE_RXDADV_NEXTP_SHIFT;
930 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 931 } else {
932 next_buffer = &rx_ring->rx_buffer_info[i];
933 }
934
9a799d71 935 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97 936 if (skb->prev)
94b982b2
MC		 937 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
938 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
fd3686a8 939 if (IXGBE_RSC_CB(skb)->dma) {
43634e82
MC		 940 pci_unmap_single(pdev, IXGBE_RSC_CB(skb)->dma,
941 rx_ring->rx_buf_len,
942 PCI_DMA_FROMDEVICE);
fd3686a8
MC		 943 IXGBE_RSC_CB(skb)->dma = 0;
944 }
94b982b2
MC		 945 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
946 rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
947 else
948 rx_ring->rsc_count++;
949 rx_ring->rsc_flush++;
950 }
9a799d71
AK		 951 rx_ring->stats.packets++;
952 rx_ring->stats.bytes += skb->len;
953 } else {
6e455b89 954 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 955 rx_buffer_info->skb = next_buffer->skb;
956 rx_buffer_info->dma = next_buffer->dma;
957 next_buffer->skb = skb;
958 next_buffer->dma = 0;
959 } else {
960 skb->next = next_buffer->skb;
961 skb->next->prev = skb;
962 }
7ca3bc58 963 rx_ring->non_eop_descs++;
9a799d71
AK		 964 goto next_desc;
965 }
966
967 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
968 dev_kfree_skb_irq(skb);
969 goto next_desc;
970 }
971
8bae1b2b 972 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 973
974 /* probably a little skewed due to removing CRC */
975 total_rx_bytes += skb->len;
976 total_rx_packets++;
977
74ce8dd2 978 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 979#ifdef IXGBE_FCOE
980 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 981 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
982 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
983 if (!ddp_bytes)
332d4a7d 984 goto next_desc;
3d8fd385 985 }
332d4a7d 986#endif /* IXGBE_FCOE */
fdaff1ce 987 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 988
989next_desc:
990 rx_desc->wb.upper.status_error = 0;
991
992 /* return some buffers to hardware, one at a time is too slow */
993 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
994 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
995 cleaned_count = 0;
996 }
997
998 /* use prefetched values */
999 rx_desc = next_rxd;
f8212f97 1000 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1001
1002 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1003 }
1004
9a799d71
AK		 1005 rx_ring->next_to_clean = i;
1006 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1007
1008 if (cleaned_count)
1009 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1010
3d8fd385
YZ		 1011#ifdef IXGBE_FCOE
1012 /* include DDPed FCoE data */
1013 if (ddp_bytes > 0) {
1014 unsigned int mss;
1015
1016 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1017 sizeof(struct fc_frame_header) -
1018 sizeof(struct fcoe_crc_eof);
1019 if (mss > 512)
1020 mss &= ~511;
1021 total_rx_bytes += ddp_bytes;
1022 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1023 }
1024#endif /* IXGBE_FCOE */
1025
f494e8fa
AV		 1026 rx_ring->total_packets += total_rx_packets;
1027 rx_ring->total_bytes += total_rx_bytes;
2d86f139
AK		 1028 netdev->stats.rx_bytes += total_rx_bytes;
1029 netdev->stats.rx_packets += total_rx_packets;
f494e8fa 1030
9a799d71
AK		 1031 return cleaned;
1032}
1033
021230d4 1034static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1035/**
1036 * ixgbe_configure_msix - Configure MSI-X hardware
1037 * @adapter: board private structure
1038 *
1039 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1040 * interrupts.
1041 **/
1042static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1043{
021230d4
AV		 1044 struct ixgbe_q_vector *q_vector;
1045 int i, j, q_vectors, v_idx, r_idx;
1046 u32 mask;
9a799d71 1047
021230d4 1048 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1049
4df10466
JB		 1050 /*
1051 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1052 * corresponding register.
1053 */
1054 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1055 q_vector = adapter->q_vector[v_idx];
984b3f57 1056 /* XXX for_each_set_bit(...) */
021230d4 1057 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 1058 adapter->num_rx_queues);
021230d4
AV		 1059
1060 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1061 j = adapter->rx_ring[r_idx]->reg_idx;
e8e26350 1062 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 1063 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 1064 adapter->num_rx_queues,
1065 r_idx + 1);
021230d4
AV		 1066 }
1067 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 1068 adapter->num_tx_queues);
021230d4
AV		 1069
1070 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1071 j = adapter->tx_ring[r_idx]->reg_idx;
e8e26350 1072 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 1073 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 1074 adapter->num_tx_queues,
1075 r_idx + 1);
021230d4
AV		 1076 }
1077
021230d4 1078 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1079 /* tx only */
1080 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1081 else if (q_vector->rxr_count)
f7554a2b
NS		 1082 /* rx or mixed */
1083 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1084
fe49f04a 1085 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1086 }
1087
e8e26350
PW		 1088 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1089 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1090 v_idx);
1091 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1092 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 1093 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1094
41fb9248 1095 /* set up to autoclear timer, and the vectors */
021230d4 1096 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1097 if (adapter->num_vfs)
1098 mask &= ~(IXGBE_EIMS_OTHER |
1099 IXGBE_EIMS_MAILBOX |
1100 IXGBE_EIMS_LSC);
1101 else
1102 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1103 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1104}
1105
f494e8fa
AV		 1106enum latency_range {
1107 lowest_latency = 0,
1108 low_latency = 1,
1109 bulk_latency = 2,
1110 latency_invalid = 255
1111};
1112
1113/**
1114 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1115 * @adapter: pointer to adapter
1116 * @eitr: eitr setting (ints per sec) to give last timeslice
1117 * @itr_setting: current throttle rate in ints/second
1118 * @packets: the number of packets during this measurement interval
1119 * @bytes: the number of bytes during this measurement interval
1120 *
1121 * Stores a new ITR value based on packets and byte
1122 * counts during the last interrupt. The advantage of per interrupt
1123 * computation is faster updates and more accurate ITR for the current
1124 * traffic pattern. Constants in this function were computed
1125 * based on theoretical maximum wire speed and thresholds were set based
1126 * on testing data as well as attempting to minimize response time
1127 * while increasing bulk throughput.
1128 * this functionality is controlled by the InterruptThrottleRate module
1129 * parameter (see ixgbe_param.c)
1130 **/
1131static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 1132 u32 eitr, u8 itr_setting,
1133 int packets, int bytes)
f494e8fa
AV		 1134{
1135 unsigned int retval = itr_setting;
1136 u32 timepassed_us;
1137 u64 bytes_perint;
1138
1139 if (packets == 0)
1140 goto update_itr_done;
1141
1142
1143 /* simple throttlerate management
1144 * 0-20MB/s lowest (100000 ints/s)
1145 * 20-100MB/s low (20000 ints/s)
1146 * 100-1249MB/s bulk (8000 ints/s)
1147 */
1148 /* what was last interrupt timeslice? */
1149 timepassed_us = 1000000/eitr;
1150 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1151
1152 switch (itr_setting) {
1153 case lowest_latency:
1154 if (bytes_perint > adapter->eitr_low)
1155 retval = low_latency;
1156 break;
1157 case low_latency:
1158 if (bytes_perint > adapter->eitr_high)
1159 retval = bulk_latency;
1160 else if (bytes_perint <= adapter->eitr_low)
1161 retval = lowest_latency;
1162 break;
1163 case bulk_latency:
1164 if (bytes_perint <= adapter->eitr_high)
1165 retval = low_latency;
1166 break;
1167 }
1168
1169update_itr_done:
1170 return retval;
1171}
1172
509ee935
JB		 1173/**
1174 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1175 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1176 *
1177 * This function is made to be called by ethtool and by the driver
1178 * when it needs to update EITR registers at runtime. Hardware
1179 * specific quirks/differences are taken care of here.
1180 */
fe49f04a 1181void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1182{
fe49f04a 1183 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1184 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1185 int v_idx = q_vector->v_idx;
1186 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1187
509ee935
JB		 1188 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1189 /* must write high and low 16 bits to reset counter */
1190 itr_reg |= (itr_reg << 16);
1191 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1192 /*
1193 * set the WDIS bit to not clear the timer bits and cause an
1194 * immediate assertion of the interrupt
1195 */
1196 itr_reg |= IXGBE_EITR_CNT_WDIS;
1197 }
1198 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1199}
1200
f494e8fa
AV		 1201static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1202{
1203 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1204 u32 new_itr;
1205 u8 current_itr, ret_itr;
fe49f04a 1206 int i, r_idx;
f494e8fa
AV		 1207 struct ixgbe_ring *rx_ring, *tx_ring;
1208
1209 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1210 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1211 tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1212 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1213 q_vector->tx_itr,
1214 tx_ring->total_packets,
1215 tx_ring->total_bytes);
f494e8fa
AV		 1216 /* if the result for this queue would decrease interrupt
1217 * rate for this vector then use that result */
30efa5a3 1218 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1219 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1220 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1221 r_idx + 1);
f494e8fa
AV		 1222 }
1223
1224 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1225 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1226 rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1227 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1228 q_vector->rx_itr,
1229 rx_ring->total_packets,
1230 rx_ring->total_bytes);
f494e8fa
AV		 1231 /* if the result for this queue would decrease interrupt
1232 * rate for this vector then use that result */
30efa5a3 1233 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1234 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1235 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1236 r_idx + 1);
f494e8fa
AV		 1237 }
1238
30efa5a3 1239 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1240
1241 switch (current_itr) {
1242 /* counts and packets in update_itr are dependent on these numbers */
1243 case lowest_latency:
1244 new_itr = 100000;
1245 break;
1246 case low_latency:
1247 new_itr = 20000; /* aka hwitr = ~200 */
1248 break;
1249 case bulk_latency:
1250 default:
1251 new_itr = 8000;
1252 break;
1253 }
1254
1255 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1256 /* do an exponential smoothing */
1257 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1258
1259 /* save the algorithm value here, not the smoothed one */
1260 q_vector->eitr = new_itr;
fe49f04a
AD		 1261
1262 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1263 }
1264
1265 return;
1266}
1267
0befdb3e
JB		 1268static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1269{
1270 struct ixgbe_hw *hw = &adapter->hw;
1271
1272 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1273 (eicr & IXGBE_EICR_GPI_SDP1)) {
1274 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1275 /* write to clear the interrupt */
1276 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1277 }
1278}
cf8280ee 1279
e8e26350
PW		 1280static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1281{
1282 struct ixgbe_hw *hw = &adapter->hw;
1283
1284 if (eicr & IXGBE_EICR_GPI_SDP1) {
1285 /* Clear the interrupt */
1286 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1287 schedule_work(&adapter->multispeed_fiber_task);
1288 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1289 /* Clear the interrupt */
1290 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1291 schedule_work(&adapter->sfp_config_module_task);
1292 } else {
1293 /* Interrupt isn't for us... */
1294 return;
1295 }
1296}
1297
cf8280ee
JB		 1298static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1299{
1300 struct ixgbe_hw *hw = &adapter->hw;
1301
1302 adapter->lsc_int++;
1303 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1304 adapter->link_check_timeout = jiffies;
1305 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1306 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1307 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1308 schedule_work(&adapter->watchdog_task);
1309 }
1310}
1311
9a799d71
AK		 1312static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1313{
1314 struct net_device *netdev = data;
1315 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1316 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1317 u32 eicr;
1318
1319 /*
1320 * Workaround for Silicon errata. Use clear-by-write instead
1321 * of clear-by-read. Reading with EICS will return the
1322 * interrupt causes without clearing, which later be done
1323 * with the write to EICR.
1324 */
1325 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1326 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1327
cf8280ee
JB		 1328 if (eicr & IXGBE_EICR_LSC)
1329 ixgbe_check_lsc(adapter);
d4f80882 1330
1cdd1ec8
GR		 1331 if (eicr & IXGBE_EICR_MAILBOX)
1332 ixgbe_msg_task(adapter);
1333
e8e26350
PW		 1334 if (hw->mac.type == ixgbe_mac_82598EB)
1335 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1336
c4cf55e5 1337 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1338 ixgbe_check_sfp_event(adapter, eicr);
c4cf55e5
PWJ		 1339
1340 /* Handle Flow Director Full threshold interrupt */
1341 if (eicr & IXGBE_EICR_FLOW_DIR) {
1342 int i;
1343 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1344 /* Disable transmits before FDIR Re-initialization */
1345 netif_tx_stop_all_queues(netdev);
1346 for (i = 0; i < adapter->num_tx_queues; i++) {
1347 struct ixgbe_ring *tx_ring =
4a0b9ca0 1348 adapter->tx_ring[i];
c4cf55e5
PWJ		 1349 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1350 &tx_ring->reinit_state))
1351 schedule_work(&adapter->fdir_reinit_task);
1352 }
1353 }
1354 }
d4f80882
AV		 1355 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1356 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1357
1358 return IRQ_HANDLED;
1359}
1360
fe49f04a
AD		 1361static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1362 u64 qmask)
1363{
1364 u32 mask;
1365
1366 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1367 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1368 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1369 } else {
1370 mask = (qmask & 0xFFFFFFFF);
1371 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1372 mask = (qmask >> 32);
1373 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1374 }
1375 /* skip the flush */
1376}
1377
1378static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1379 u64 qmask)
1380{
1381 u32 mask;
1382
1383 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1384 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1385 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1386 } else {
1387 mask = (qmask & 0xFFFFFFFF);
1388 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1389 mask = (qmask >> 32);
1390 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1391 }
1392 /* skip the flush */
1393}
1394
9a799d71
AK		 1395static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1396{
021230d4
AV		 1397 struct ixgbe_q_vector *q_vector = data;
1398 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1399 struct ixgbe_ring *tx_ring;
021230d4
AV		 1400 int i, r_idx;
1401
1402 if (!q_vector->txr_count)
1403 return IRQ_HANDLED;
1404
1405 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1406 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1407 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 1408 tx_ring->total_bytes = 0;
1409 tx_ring->total_packets = 0;
021230d4 1410 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1411 r_idx + 1);
021230d4 1412 }
9a799d71 1413
9b471446 1414 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 1415 napi_schedule(&q_vector->napi);
1416
9a799d71
AK		 1417 return IRQ_HANDLED;
1418}
1419
021230d4
AV		 1420/**
1421 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1422 * @irq: unused
1423 * @data: pointer to our q_vector struct for this interrupt vector
1424 **/
9a799d71
AK		 1425static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1426{
021230d4
AV		 1427 struct ixgbe_q_vector *q_vector = data;
1428 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1429 struct ixgbe_ring *rx_ring;
021230d4 1430 int r_idx;
30efa5a3 1431 int i;
021230d4
AV		 1432
1433 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3 1434 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1435 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 1436 rx_ring->total_bytes = 0;
1437 rx_ring->total_packets = 0;
1438 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1439 r_idx + 1);
1440 }
1441
021230d4
AV		 1442 if (!q_vector->rxr_count)
1443 return IRQ_HANDLED;
1444
021230d4 1445 /* disable interrupts on this vector only */
9b471446 1446 /* EIAM disabled interrupts (on this vector) for us */
288379f0 1447 napi_schedule(&q_vector->napi);
021230d4
AV		 1448
1449 return IRQ_HANDLED;
1450}
1451
1452static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1453{
91281fd3
AD		 1454 struct ixgbe_q_vector *q_vector = data;
1455 struct ixgbe_adapter *adapter = q_vector->adapter;
1456 struct ixgbe_ring *ring;
1457 int r_idx;
1458 int i;
1459
1460 if (!q_vector->txr_count && !q_vector->rxr_count)
1461 return IRQ_HANDLED;
1462
1463 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1464 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1465 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1466 ring->total_bytes = 0;
1467 ring->total_packets = 0;
1468 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1469 r_idx + 1);
1470 }
1471
1472 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1473 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1474 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 1475 ring->total_bytes = 0;
1476 ring->total_packets = 0;
1477 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1478 r_idx + 1);
1479 }
1480
9b471446 1481 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1482 napi_schedule(&q_vector->napi);
9a799d71 1483
9a799d71
AK		 1484 return IRQ_HANDLED;
1485}
1486
021230d4
AV		 1487/**
1488 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1489 * @napi: napi struct with our devices info in it
1490 * @budget: amount of work driver is allowed to do this pass, in packets
1491 *
f0848276
JB		 1492 * This function is optimized for cleaning one queue only on a single
1493 * q_vector!!!
021230d4 1494 **/
9a799d71
AK		 1495static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1496{
021230d4 1497 struct ixgbe_q_vector *q_vector =
b4617240 1498 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1499 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1500 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1501 int work_done = 0;
021230d4 1502 long r_idx;
9a799d71 1503
021230d4 1504 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1505 rx_ring = adapter->rx_ring[r_idx];
5dd2d332 1506#ifdef CONFIG_IXGBE_DCA
bd0362dd 1507 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1508 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1509#endif
9a799d71 1510
78b6f4ce 1511 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1512
021230d4
AV		 1513 /* If all Rx work done, exit the polling mode */
1514 if (work_done < budget) {
288379f0 1515 napi_complete(napi);
f7554a2b 1516 if (adapter->rx_itr_setting & 1)
f494e8fa 1517 ixgbe_set_itr_msix(q_vector);
9a799d71 1518 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1519 ixgbe_irq_enable_queues(adapter,
1520 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1521 }
1522
1523 return work_done;
1524}
1525
f0848276 1526/**
91281fd3 1527 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1528 * @napi: napi struct with our devices info in it
1529 * @budget: amount of work driver is allowed to do this pass, in packets
1530 *
1531 * This function will clean more than one rx queue associated with a
1532 * q_vector.
1533 **/
91281fd3 1534static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1535{
1536 struct ixgbe_q_vector *q_vector =
1537 container_of(napi, struct ixgbe_q_vector, napi);
1538 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1539 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1540 int work_done = 0, i;
1541 long r_idx;
91281fd3
AD		 1542 bool tx_clean_complete = true;
1543
1544 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1545 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1546 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1547#ifdef CONFIG_IXGBE_DCA
1548 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1549 ixgbe_update_tx_dca(adapter, ring);
1550#endif
1551 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1552 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1553 r_idx + 1);
1554 }
f0848276
JB		 1555
1556 /* attempt to distribute budget to each queue fairly, but don't allow
1557 * the budget to go below 1 because we'll exit polling */
1558 budget /= (q_vector->rxr_count ?: 1);
1559 budget = max(budget, 1);
1560 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1561 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1562 ring = adapter->rx_ring[r_idx];
5dd2d332 1563#ifdef CONFIG_IXGBE_DCA
f0848276 1564 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1565 ixgbe_update_rx_dca(adapter, ring);
f0848276 1566#endif
91281fd3 1567 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276
JB		 1568 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1569 r_idx + 1);
1570 }
1571
1572 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1573 ring = adapter->rx_ring[r_idx];
f0848276 1574 /* If all Rx work done, exit the polling mode */
7f821875 1575 if (work_done < budget) {
288379f0 1576 napi_complete(napi);
f7554a2b 1577 if (adapter->rx_itr_setting & 1)
f0848276
JB		 1578 ixgbe_set_itr_msix(q_vector);
1579 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1580 ixgbe_irq_enable_queues(adapter,
1581 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1582 return 0;
1583 }
1584
1585 return work_done;
1586}
91281fd3
AD		 1587
1588/**
1589 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1590 * @napi: napi struct with our devices info in it
1591 * @budget: amount of work driver is allowed to do this pass, in packets
1592 *
1593 * This function is optimized for cleaning one queue only on a single
1594 * q_vector!!!
1595 **/
1596static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1597{
1598 struct ixgbe_q_vector *q_vector =
1599 container_of(napi, struct ixgbe_q_vector, napi);
1600 struct ixgbe_adapter *adapter = q_vector->adapter;
1601 struct ixgbe_ring *tx_ring = NULL;
1602 int work_done = 0;
1603 long r_idx;
1604
1605 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
4a0b9ca0 1606 tx_ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1607#ifdef CONFIG_IXGBE_DCA
1608 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1609 ixgbe_update_tx_dca(adapter, tx_ring);
1610#endif
1611
1612 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1613 work_done = budget;
1614
f7554a2b 1615 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 1616 if (work_done < budget) {
1617 napi_complete(napi);
f7554a2b 1618 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 1619 ixgbe_set_itr_msix(q_vector);
1620 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1621 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1622 }
1623
1624 return work_done;
1625}
1626
021230d4 1627static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1628 int r_idx)
021230d4 1629{
7a921c93
AD		 1630 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1631
1632 set_bit(r_idx, q_vector->rxr_idx);
1633 q_vector->rxr_count++;
021230d4
AV		 1634}
1635
1636static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 1637 int t_idx)
021230d4 1638{
7a921c93
AD		 1639 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1640
1641 set_bit(t_idx, q_vector->txr_idx);
1642 q_vector->txr_count++;
021230d4
AV		 1643}
1644
9a799d71 1645/**
021230d4
AV		 1646 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1647 * @adapter: board private structure to initialize
1648 * @vectors: allotted vector count for descriptor rings
9a799d71 1649 *
021230d4
AV		 1650 * This function maps descriptor rings to the queue-specific vectors
1651 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1652 * one vector per ring/queue, but on a constrained vector budget, we
1653 * group the rings as "efficiently" as possible. You would add new
1654 * mapping configurations in here.
9a799d71 1655 **/
021230d4 1656static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1657 int vectors)
021230d4
AV		 1658{
1659 int v_start = 0;
1660 int rxr_idx = 0, txr_idx = 0;
1661 int rxr_remaining = adapter->num_rx_queues;
1662 int txr_remaining = adapter->num_tx_queues;
1663 int i, j;
1664 int rqpv, tqpv;
1665 int err = 0;
1666
1667 /* No mapping required if MSI-X is disabled. */
1668 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1669 goto out;
9a799d71 1670
021230d4
AV		 1671 /*
1672 * The ideal configuration...
1673 * We have enough vectors to map one per queue.
1674 */
1675 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1676 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1677 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1678
021230d4
AV		 1679 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1680 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1681
9a799d71 1682 goto out;
021230d4 1683 }
9a799d71 1684
021230d4
AV		 1685 /*
1686 * If we don't have enough vectors for a 1-to-1
1687 * mapping, we'll have to group them so there are
1688 * multiple queues per vector.
1689 */
1690 /* Re-adjusting *qpv takes care of the remainder. */
1691 for (i = v_start; i < vectors; i++) {
1692 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1693 for (j = 0; j < rqpv; j++) {
1694 map_vector_to_rxq(adapter, i, rxr_idx);
1695 rxr_idx++;
1696 rxr_remaining--;
1697 }
1698 }
1699 for (i = v_start; i < vectors; i++) {
1700 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1701 for (j = 0; j < tqpv; j++) {
1702 map_vector_to_txq(adapter, i, txr_idx);
1703 txr_idx++;
1704 txr_remaining--;
9a799d71 1705 }
9a799d71
AK		 1706 }
1707
021230d4
AV		 1708out:
1709 return err;
1710}
1711
1712/**
1713 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1714 * @adapter: board private structure
1715 *
1716 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1717 * interrupts from the kernel.
1718 **/
1719static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1720{
1721 struct net_device *netdev = adapter->netdev;
1722 irqreturn_t (*handler)(int, void *);
1723 int i, vector, q_vectors, err;
cb13fc20 1724 int ri=0, ti=0;
021230d4
AV		 1725
1726 /* Decrement for Other and TCP Timer vectors */
1727 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1728
1729 /* Map the Tx/Rx rings to the vectors we were allotted. */
1730 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1731 if (err)
1732 goto out;
1733
1734#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1735 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1736 &ixgbe_msix_clean_many)
021230d4 1737 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 1738 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 1739
1740 if(handler == &ixgbe_msix_clean_rx) {
1741 sprintf(adapter->name[vector], "%s-%s-%d",
1742 netdev->name, "rx", ri++);
1743 }
1744 else if(handler == &ixgbe_msix_clean_tx) {
1745 sprintf(adapter->name[vector], "%s-%s-%d",
1746 netdev->name, "tx", ti++);
1747 }
1748 else
1749 sprintf(adapter->name[vector], "%s-%s-%d",
1750 netdev->name, "TxRx", vector);
1751
021230d4 1752 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1753 handler, 0, adapter->name[vector],
7a921c93 1754 adapter->q_vector[vector]);
9a799d71
AK		 1755 if (err) {
1756 DPRINTK(PROBE, ERR,
b4617240
PW		 1757 "request_irq failed for MSIX interrupt "
1758 "Error: %d\n", err);
021230d4 1759 goto free_queue_irqs;
9a799d71 1760 }
9a799d71
AK		 1761 }
1762
021230d4
AV		 1763 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1764 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1765 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1766 if (err) {
1767 DPRINTK(PROBE, ERR,
1768 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1769 goto free_queue_irqs;
9a799d71
AK		 1770 }
1771
9a799d71
AK		 1772 return 0;
1773
021230d4
AV		 1774free_queue_irqs:
1775 for (i = vector - 1; i >= 0; i--)
1776 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 1777 adapter->q_vector[i]);
021230d4
AV		 1778 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1779 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1780 kfree(adapter->msix_entries);
1781 adapter->msix_entries = NULL;
021230d4 1782out:
9a799d71
AK		 1783 return err;
1784}
1785
f494e8fa
AV		 1786static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1787{
7a921c93 1788 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 1789 u8 current_itr;
1790 u32 new_itr = q_vector->eitr;
4a0b9ca0
PW		 1791 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
1792 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
f494e8fa 1793
30efa5a3 1794 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1795 q_vector->tx_itr,
1796 tx_ring->total_packets,
1797 tx_ring->total_bytes);
30efa5a3 1798 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1799 q_vector->rx_itr,
1800 rx_ring->total_packets,
1801 rx_ring->total_bytes);
f494e8fa 1802
30efa5a3 1803 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1804
1805 switch (current_itr) {
1806 /* counts and packets in update_itr are dependent on these numbers */
1807 case lowest_latency:
1808 new_itr = 100000;
1809 break;
1810 case low_latency:
1811 new_itr = 20000; /* aka hwitr = ~200 */
1812 break;
1813 case bulk_latency:
1814 new_itr = 8000;
1815 break;
1816 default:
1817 break;
1818 }
1819
1820 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1821 /* do an exponential smoothing */
1822 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1823
1824 /* save the algorithm value here, not the smoothed one */
1825 q_vector->eitr = new_itr;
fe49f04a
AD		 1826
1827 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1828 }
1829
1830 return;
1831}
1832
79aefa45
AD		 1833/**
1834 * ixgbe_irq_enable - Enable default interrupt generation settings
1835 * @adapter: board private structure
1836 **/
1837static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1838{
1839 u32 mask;
835462fc
NS		 1840
1841 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 1842 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1843 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1844 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1845 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1846 mask |= IXGBE_EIMS_GPI_SDP1;
1847 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 1848 if (adapter->num_vfs)
1849 mask |= IXGBE_EIMS_MAILBOX;
e8e26350 1850 }
c4cf55e5
PWJ		 1851 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1852 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1853 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 1854
79aefa45 1855 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 1856 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45 1857 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 1858
1859 if (adapter->num_vfs > 32) {
1860 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1861 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1862 }
79aefa45 1863}
021230d4 1864
9a799d71 1865/**
021230d4 1866 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1867 * @irq: interrupt number
1868 * @data: pointer to a network interface device structure
9a799d71
AK		 1869 **/
1870static irqreturn_t ixgbe_intr(int irq, void *data)
1871{
1872 struct net_device *netdev = data;
1873 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1874 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 1875 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 1876 u32 eicr;
1877
54037505
DS		 1878 /*
1879 * Workaround for silicon errata. Mask the interrupts
1880 * before the read of EICR.
1881 */
1882 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1883
021230d4
AV		 1884 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1885 * therefore no explict interrupt disable is necessary */
1886 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1887 if (!eicr) {
1888 /* shared interrupt alert!
1889 * make sure interrupts are enabled because the read will
1890 * have disabled interrupts due to EIAM */
1891 ixgbe_irq_enable(adapter);
9a799d71 1892 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1893 }
9a799d71 1894
cf8280ee
JB		 1895 if (eicr & IXGBE_EICR_LSC)
1896 ixgbe_check_lsc(adapter);
021230d4 1897
e8e26350
PW		 1898 if (hw->mac.type == ixgbe_mac_82599EB)
1899 ixgbe_check_sfp_event(adapter, eicr);
1900
0befdb3e
JB		 1901 ixgbe_check_fan_failure(adapter, eicr);
1902
7a921c93 1903 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 1904 adapter->tx_ring[0]->total_packets = 0;
1905 adapter->tx_ring[0]->total_bytes = 0;
1906 adapter->rx_ring[0]->total_packets = 0;
1907 adapter->rx_ring[0]->total_bytes = 0;
021230d4 1908 /* would disable interrupts here but EIAM disabled it */
7a921c93 1909 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 1910 }
1911
1912 return IRQ_HANDLED;
1913}
1914
021230d4
AV		 1915static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1916{
1917 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1918
1919 for (i = 0; i < q_vectors; i++) {
7a921c93 1920 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 1921 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1922 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1923 q_vector->rxr_count = 0;
1924 q_vector->txr_count = 0;
1925 }
1926}
1927
9a799d71
AK		 1928/**
1929 * ixgbe_request_irq - initialize interrupts
1930 * @adapter: board private structure
1931 *
1932 * Attempts to configure interrupts using the best available
1933 * capabilities of the hardware and kernel.
1934 **/
021230d4 1935static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1936{
1937 struct net_device *netdev = adapter->netdev;
021230d4 1938 int err;
9a799d71 1939
021230d4
AV		 1940 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1941 err = ixgbe_request_msix_irqs(adapter);
1942 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 1943 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
b4617240 1944 netdev->name, netdev);
021230d4 1945 } else {
a0607fd3 1946 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
b4617240 1947 netdev->name, netdev);
9a799d71
AK		 1948 }
1949
9a799d71
AK		 1950 if (err)
1951 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1952
9a799d71
AK		 1953 return err;
1954}
1955
1956static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1957{
1958 struct net_device *netdev = adapter->netdev;
1959
1960 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1961 int i, q_vectors;
9a799d71 1962
021230d4
AV		 1963 q_vectors = adapter->num_msix_vectors;
1964
1965 i = q_vectors - 1;
9a799d71 1966 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1967
021230d4
AV		 1968 i--;
1969 for (; i >= 0; i--) {
1970 free_irq(adapter->msix_entries[i].vector,
7a921c93 1971 adapter->q_vector[i]);
021230d4
AV		 1972 }
1973
1974 ixgbe_reset_q_vectors(adapter);
1975 } else {
1976 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1977 }
1978}
1979
22d5a71b
JB		 1980/**
1981 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1982 * @adapter: board private structure
1983 **/
1984static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1985{
835462fc
NS		 1986 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1987 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1988 } else {
1989 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1990 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 1991 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 1992 if (adapter->num_vfs > 32)
1993 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
22d5a71b
JB		 1994 }
1995 IXGBE_WRITE_FLUSH(&adapter->hw);
1996 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1997 int i;
1998 for (i = 0; i < adapter->num_msix_vectors; i++)
1999 synchronize_irq(adapter->msix_entries[i].vector);
2000 } else {
2001 synchronize_irq(adapter->pdev->irq);
2002 }
2003}
2004
9a799d71
AK		 2005/**
2006 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2007 *
2008 **/
2009static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2010{
9a799d71
AK		 2011 struct ixgbe_hw *hw = &adapter->hw;
2012
021230d4 2013 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
f7554a2b 2014 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2015
e8e26350
PW		 2016 ixgbe_set_ivar(adapter, 0, 0, 0);
2017 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2018
2019 map_vector_to_rxq(adapter, 0, 0);
2020 map_vector_to_txq(adapter, 0, 0);
2021
2022 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2023}
2024
2025/**
3a581073 2026 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2027 * @adapter: board private structure
2028 *
2029 * Configure the Tx unit of the MAC after a reset.
2030 **/
2031static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2032{
12207e49 2033 u64 tdba;
9a799d71 2034 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2035 u32 i, j, tdlen, txctrl;
9a799d71
AK		 2036
2037 /* Setup the HW Tx Head and Tail descriptor pointers */
2038 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2039 struct ixgbe_ring *ring = adapter->tx_ring[i];
e01c31a5
JB		 2040 j = ring->reg_idx;
2041 tdba = ring->dma;
2042 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 2043 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 2044 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 2045 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
2046 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
2047 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
2048 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
4a0b9ca0
PW		 2049 adapter->tx_ring[i]->head = IXGBE_TDH(j);
2050 adapter->tx_ring[i]->tail = IXGBE_TDT(j);
84f62d4b
PWJ		 2051 /*
2052 * Disable Tx Head Writeback RO bit, since this hoses
021230d4
AV		 2053 * bookkeeping if things aren't delivered in order.
2054 */
84f62d4b
PWJ		 2055 switch (hw->mac.type) {
2056 case ixgbe_mac_82598EB:
2057 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
2058 break;
2059 case ixgbe_mac_82599EB:
2060 default:
2061 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
2062 break;
2063 }
021230d4 2064 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
84f62d4b
PWJ		 2065 switch (hw->mac.type) {
2066 case ixgbe_mac_82598EB:
2067 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
2068 break;
2069 case ixgbe_mac_82599EB:
2070 default:
2071 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
2072 break;
2073 }
9a799d71 2074 }
ee5f784a 2075
e8e26350 2076 if (hw->mac.type == ixgbe_mac_82599EB) {
ee5f784a 2077 u32 rttdcs;
1cdd1ec8 2078 u32 mask;
ee5f784a
DS		 2079
2080 /* disable the arbiter while setting MTQC */
2081 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2082 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2083 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2084
1cdd1ec8
GR		 2085 /* set transmit pool layout */
2086 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2087 switch (adapter->flags & mask) {
2088
2089 case (IXGBE_FLAG_SRIOV_ENABLED):
2090 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2091 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2092 break;
2093
2094 case (IXGBE_FLAG_DCB_ENABLED):
2095 /* We enable 8 traffic classes, DCB only */
2096 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2097 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2098 break;
2099
2100 default:
ee5f784a 2101 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
1cdd1ec8
GR		 2102 break;
2103 }
ee5f784a
DS		 2104
2105 /* re-eable the arbiter */
2106 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2107 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
e8e26350 2108 }
9a799d71
AK		 2109}
2110
e8e26350 2111#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2112
a6616b42
YZ		 2113static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2114 struct ixgbe_ring *rx_ring)
cc41ac7c 2115{
cc41ac7c 2116 u32 srrctl;
a6616b42 2117 int index;
0cefafad 2118 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 2119
a6616b42
YZ		 2120 index = rx_ring->reg_idx;
2121 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2122 unsigned long mask;
0cefafad 2123 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 2124 index = index & mask;
cc41ac7c 2125 }
cc41ac7c
JB		 2126 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2127
2128 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2129 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2130
afafd5b0
AD		 2131 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2132 IXGBE_SRRCTL_BSIZEHDR_MASK;
2133
6e455b89 2134 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 2135#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2136 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2137#else
2138 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2139#endif
cc41ac7c 2140 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2141 } else {
afafd5b0
AD		 2142 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2143 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2144 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2145 }
e8e26350 2146
cc41ac7c
JB		 2147 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2148}
9a799d71 2149
0cefafad
JB		 2150static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2151{
2152 u32 mrqc = 0;
2153 int mask;
2154
2155 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2156 return mrqc;
2157
2158 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2159#ifdef CONFIG_IXGBE_DCB
2160 | IXGBE_FLAG_DCB_ENABLED
2161#endif
1cdd1ec8 2162 | IXGBE_FLAG_SRIOV_ENABLED
0cefafad
JB		 2163 );
2164
2165 switch (mask) {
2166 case (IXGBE_FLAG_RSS_ENABLED):
2167 mrqc = IXGBE_MRQC_RSSEN;
2168 break;
1cdd1ec8
GR		 2169 case (IXGBE_FLAG_SRIOV_ENABLED):
2170 mrqc = IXGBE_MRQC_VMDQEN;
2171 break;
0cefafad
JB		 2172#ifdef CONFIG_IXGBE_DCB
2173 case (IXGBE_FLAG_DCB_ENABLED):
2174 mrqc = IXGBE_MRQC_RT8TCEN;
2175 break;
2176#endif /* CONFIG_IXGBE_DCB */
2177 default:
2178 break;
2179 }
2180
2181 return mrqc;
2182}
2183
bb5a9ad2
NS		 2184/**
2185 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2186 * @adapter: address of board private structure
2187 * @index: index of ring to set
bb5a9ad2 2188 **/
edd2ea55 2189static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
bb5a9ad2
NS		 2190{
2191 struct ixgbe_ring *rx_ring;
2192 struct ixgbe_hw *hw = &adapter->hw;
2193 int j;
2194 u32 rscctrl;
edd2ea55 2195 int rx_buf_len;
bb5a9ad2 2196
4a0b9ca0 2197 rx_ring = adapter->rx_ring[index];
bb5a9ad2 2198 j = rx_ring->reg_idx;
edd2ea55 2199 rx_buf_len = rx_ring->rx_buf_len;
bb5a9ad2
NS		 2200 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2201 rscctrl |= IXGBE_RSCCTL_RSCEN;
2202 /*
2203 * we must limit the number of descriptors so that the
2204 * total size of max desc * buf_len is not greater
2205 * than 65535
2206 */
2207 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2208#if (MAX_SKB_FRAGS > 16)
2209 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2210#elif (MAX_SKB_FRAGS > 8)
2211 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2212#elif (MAX_SKB_FRAGS > 4)
2213 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2214#else
2215 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2216#endif
2217 } else {
2218 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2219 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2220 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2221 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2222 else
2223 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2224 }
2225 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2226}
2227
9a799d71 2228/**
3a581073 2229 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 2230 * @adapter: board private structure
2231 *
2232 * Configure the Rx unit of the MAC after a reset.
2233 **/
2234static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2235{
2236 u64 rdba;
2237 struct ixgbe_hw *hw = &adapter->hw;
a6616b42 2238 struct ixgbe_ring *rx_ring;
9a799d71
AK		 2239 struct net_device *netdev = adapter->netdev;
2240 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2241 int i, j;
9a799d71 2242 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 2243 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2244 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2245 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 2246 u32 fctrl, hlreg0;
509ee935 2247 u32 reta = 0, mrqc = 0;
cc41ac7c 2248 u32 rdrxctl;
7c6e0a43 2249 int rx_buf_len;
9a799d71
AK		 2250
2251 /* Decide whether to use packet split mode or not */
1cdd1ec8
GR		 2252 /* Do not use packet split if we're in SR-IOV Mode */
2253 if (!adapter->num_vfs)
2254 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 2255
2256 /* Set the RX buffer length according to the mode */
2257 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2258 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 2259 if (hw->mac.type == ixgbe_mac_82599EB) {
2260 /* PSRTYPE must be initialized in 82599 */
2261 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2262 IXGBE_PSRTYPE_UDPHDR |
2263 IXGBE_PSRTYPE_IPV4HDR |
dfa12f05
YZ		 2264 IXGBE_PSRTYPE_IPV6HDR |
2265 IXGBE_PSRTYPE_L2HDR;
1cdd1ec8
GR		 2266 IXGBE_WRITE_REG(hw,
2267 IXGBE_PSRTYPE(adapter->num_vfs),
2268 psrtype);
e8e26350 2269 }
9a799d71 2270 } else {
0c19d6af 2271 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2272 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2273 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2274 else
7c6e0a43 2275 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 2276 }
2277
2278 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2279 fctrl |= IXGBE_FCTRL_BAM;
021230d4 2280 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 2281 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 2282 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2283
2284 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2285 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2286 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2287 else
2288 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
63f39bd1 2289#ifdef IXGBE_FCOE
f34c5c82 2290 if (netdev->features & NETIF_F_FCOE_MTU)
63f39bd1
YZ		 2291 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2292#endif
9a799d71
AK		 2293 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2294
4a0b9ca0 2295 rdlen = adapter->rx_ring[0]->count * sizeof(union ixgbe_adv_rx_desc);
9a799d71
AK		 2296 /* disable receives while setting up the descriptors */
2297 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2298 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2299
0cefafad
JB		 2300 /*
2301 * Setup the HW Rx Head and Tail Descriptor Pointers and
2302 * the Base and Length of the Rx Descriptor Ring
2303 */
9a799d71 2304 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2305 rx_ring = adapter->rx_ring[i];
a6616b42
YZ		 2306 rdba = rx_ring->dma;
2307 j = rx_ring->reg_idx;
284901a9 2308 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 2309 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2310 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2311 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2312 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
a6616b42
YZ		 2313 rx_ring->head = IXGBE_RDH(j);
2314 rx_ring->tail = IXGBE_RDT(j);
2315 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2316
6e455b89
YZ		 2317 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2318 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
1b3ff02e
PWJ		 2319 else
2320 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2321
63f39bd1 2322#ifdef IXGBE_FCOE
f34c5c82 2323 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2324 struct ixgbe_ring_feature *f;
2325 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2326 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2327 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2328 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2329 rx_ring->rx_buf_len =
2330 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2331 }
63f39bd1
YZ		 2332 }
2333
2334#endif /* IXGBE_FCOE */
a6616b42 2335 ixgbe_configure_srrctl(adapter, rx_ring);
9a799d71
AK		 2336 }
2337
e8e26350
PW		 2338 if (hw->mac.type == ixgbe_mac_82598EB) {
2339 /*
2340 * For VMDq support of different descriptor types or
2341 * buffer sizes through the use of multiple SRRCTL
2342 * registers, RDRXCTL.MVMEN must be set to 1
2343 *
2344 * also, the manual doesn't mention it clearly but DCA hints
2345 * will only use queue 0's tags unless this bit is set. Side
2346 * effects of setting this bit are only that SRRCTL must be
2347 * fully programmed [0..15]
2348 */
2a41ff81
JB		 2349 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2350 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2351 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 2352 }
177db6ff 2353
1cdd1ec8
GR		 2354 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2355 u32 vt_reg_bits;
2356 u32 reg_offset, vf_shift;
2357 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2358 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2359 | IXGBE_VT_CTL_REPLEN;
2360 vt_reg_bits |= (adapter->num_vfs <<
2361 IXGBE_VT_CTL_POOL_SHIFT);
2362 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2363 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2364
2365 vf_shift = adapter->num_vfs % 32;
2366 reg_offset = adapter->num_vfs / 32;
2367 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2368 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2369 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2370 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2371 /* Enable only the PF's pool for Tx/Rx */
2372 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2373 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2374 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2375 ixgbe_set_vmolr(hw, adapter->num_vfs);
2376 }
2377
e8e26350 2378 /* Program MRQC for the distribution of queues */
0cefafad 2379 mrqc = ixgbe_setup_mrqc(adapter);
e8e26350 2380
021230d4 2381 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 2382 /* Fill out redirection table */
021230d4
AV		 2383 for (i = 0, j = 0; i < 128; i++, j++) {
2384 if (j == adapter->ring_feature[RING_F_RSS].indices)
2385 j = 0;
2386 /* reta = 4-byte sliding window of
2387 * 0x00..(indices-1)(indices-1)00..etc. */
2388 reta = (reta << 8) | (j * 0x11);
2389 if ((i & 3) == 3)
2390 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 2391 }
2392
2393 /* Fill out hash function seeds */
2394 for (i = 0; i < 10; i++)
7c6e0a43 2395 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 2396
2a41ff81
JB		 2397 if (hw->mac.type == ixgbe_mac_82598EB)
2398 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 2399 /* Perform hash on these packet types */
2a41ff81
JB		 2400 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2401 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2402 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2403 | IXGBE_MRQC_RSS_FIELD_IPV6
2404 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2405 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 2406 }
2a41ff81 2407 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 2408
1cdd1ec8
GR		 2409 if (adapter->num_vfs) {
2410 u32 reg;
2411
2412 /* Map PF MAC address in RAR Entry 0 to first pool
2413 * following VFs */
2414 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2415
2416 /* Set up VF register offsets for selected VT Mode, i.e.
2417 * 64 VFs for SR-IOV */
2418 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2419 reg |= IXGBE_GCR_EXT_SRIOV;
2420 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2421 }
2422
021230d4
AV		 2423 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2424
2425 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2426 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2427 /* Disable indicating checksum in descriptor, enables
2428 * RSS hash */
9a799d71 2429 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 2430 }
021230d4
AV		 2431 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2432 /* Enable IPv4 payload checksum for UDP fragments
2433 * if PCSD is not set */
2434 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2435 }
2436
2437 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 2438
2439 if (hw->mac.type == ixgbe_mac_82599EB) {
2440 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2441 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 2442 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 2443 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2444 }
f8212f97 2445
0c19d6af 2446 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 2447 /* Enable 82599 HW-RSC */
bb5a9ad2 2448 for (i = 0; i < adapter->num_rx_queues; i++)
edd2ea55 2449 ixgbe_configure_rscctl(adapter, i);
bb5a9ad2 2450
f8212f97
AD		 2451 /* Disable RSC for ACK packets */
2452 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2453 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2454 }
9a799d71
AK		 2455}
2456
068c89b0
DS		 2457static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2458{
2459 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2460 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2461 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2462
2463 /* add VID to filter table */
1ada1b1b 2464 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
068c89b0
DS		 2465}
2466
2467static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2468{
2469 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2470 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2471 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2472
2473 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2474 ixgbe_irq_disable(adapter);
2475
2476 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2477
2478 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2479 ixgbe_irq_enable(adapter);
2480
2481 /* remove VID from filter table */
1ada1b1b 2482 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
068c89b0
DS		 2483}
2484
5f6c0181
JB		 2485/**
2486 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
2487 * @adapter: driver data
2488 */
2489static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
2490{
2491 struct ixgbe_hw *hw = &adapter->hw;
2492 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2493 int i, j;
2494
2495 switch (hw->mac.type) {
2496 case ixgbe_mac_82598EB:
2497 vlnctrl &= ~(IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE);
2498 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2499 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2500 break;
2501 case ixgbe_mac_82599EB:
2502 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2503 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2504 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2505 for (i = 0; i < adapter->num_rx_queues; i++) {
2506 j = adapter->rx_ring[i]->reg_idx;
2507 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2508 vlnctrl &= ~IXGBE_RXDCTL_VME;
2509 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2510 }
2511 break;
2512 default:
2513 break;
2514 }
2515}
2516
2517/**
2518 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
2519 * @adapter: driver data
2520 */
2521static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
2522{
2523 struct ixgbe_hw *hw = &adapter->hw;
2524 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2525 int i, j;
2526
2527 switch (hw->mac.type) {
2528 case ixgbe_mac_82598EB:
2529 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2530 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2531 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2532 break;
2533 case ixgbe_mac_82599EB:
2534 vlnctrl |= IXGBE_VLNCTRL_VFE;
2535 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2536 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2537 for (i = 0; i < adapter->num_rx_queues; i++) {
2538 j = adapter->rx_ring[i]->reg_idx;
2539 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2540 vlnctrl |= IXGBE_RXDCTL_VME;
2541 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2542 }
2543 break;
2544 default:
2545 break;
2546 }
2547}
2548
9a799d71 2549static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2550 struct vlan_group *grp)
9a799d71
AK		 2551{
2552 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 2553
d4f80882
AV		 2554 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2555 ixgbe_irq_disable(adapter);
9a799d71
AK		 2556 adapter->vlgrp = grp;
2557
2f90b865
AD		 2558 /*
2559 * For a DCB driver, always enable VLAN tag stripping so we can
2560 * still receive traffic from a DCB-enabled host even if we're
2561 * not in DCB mode.
2562 */
5f6c0181 2563 ixgbe_vlan_filter_enable(adapter);
dc63d377 2564
e8e26350 2565 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2566
d4f80882
AV		 2567 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2568 ixgbe_irq_enable(adapter);
9a799d71
AK		 2569}
2570
9a799d71
AK		 2571static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2572{
2573 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2574
2575 if (adapter->vlgrp) {
2576 u16 vid;
2577 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2578 if (!vlan_group_get_device(adapter->vlgrp, vid))
2579 continue;
2580 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2581 }
2582 }
2583}
2584
2585/**
2c5645cf 2586 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2587 * @netdev: network interface device structure
2588 *
2c5645cf
CL		 2589 * The set_rx_method entry point is called whenever the unicast/multicast
2590 * address list or the network interface flags are updated. This routine is
2591 * responsible for configuring the hardware for proper unicast, multicast and
2592 * promiscuous mode.
9a799d71 2593 **/
7f870475 2594void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2595{
2596 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2597 struct ixgbe_hw *hw = &adapter->hw;
5f6c0181 2598 u32 fctrl;
9a799d71
AK		 2599
2600 /* Check for Promiscuous and All Multicast modes */
2601
2602 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2603
2604 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2605 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2606 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
5f6c0181
JB		 2607 /* don't hardware filter vlans in promisc mode */
2608 ixgbe_vlan_filter_disable(adapter);
9a799d71 2609 } else {
746b9f02
PM		 2610 if (netdev->flags & IFF_ALLMULTI) {
2611 fctrl |= IXGBE_FCTRL_MPE;
2612 fctrl &= ~IXGBE_FCTRL_UPE;
2613 } else {
2614 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2615 }
5f6c0181 2616 ixgbe_vlan_filter_enable(adapter);
2c5645cf 2617 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2618 }
2619
2620 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2621
2c5645cf 2622 /* reprogram secondary unicast list */
32e7bfc4 2623 hw->mac.ops.update_uc_addr_list(hw, netdev);
9a799d71 2624
2c5645cf 2625 /* reprogram multicast list */
2853eb89
JP		 2626 hw->mac.ops.update_mc_addr_list(hw, netdev);
2627
1cdd1ec8
GR		 2628 if (adapter->num_vfs)
2629 ixgbe_restore_vf_multicasts(adapter);
9a799d71
AK		 2630}
2631
021230d4
AV		 2632static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2633{
2634 int q_idx;
2635 struct ixgbe_q_vector *q_vector;
2636 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2637
2638 /* legacy and MSI only use one vector */
2639 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2640 q_vectors = 1;
2641
2642 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2643 struct napi_struct *napi;
7a921c93 2644 q_vector = adapter->q_vector[q_idx];
f0848276 2645 napi = &q_vector->napi;
91281fd3
AD		 2646 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2647 if (!q_vector->rxr_count || !q_vector->txr_count) {
2648 if (q_vector->txr_count == 1)
2649 napi->poll = &ixgbe_clean_txonly;
2650 else if (q_vector->rxr_count == 1)
2651 napi->poll = &ixgbe_clean_rxonly;
2652 }
2653 }
f0848276
JB		 2654
2655 napi_enable(napi);
021230d4
AV		 2656 }
2657}
2658
2659static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2660{
2661 int q_idx;
2662 struct ixgbe_q_vector *q_vector;
2663 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2664
2665 /* legacy and MSI only use one vector */
2666 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2667 q_vectors = 1;
2668
2669 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 2670 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2671 napi_disable(&q_vector->napi);
2672 }
2673}
2674
7a6b6f51 2675#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2676/*
2677 * ixgbe_configure_dcb - Configure DCB hardware
2678 * @adapter: ixgbe adapter struct
2679 *
2680 * This is called by the driver on open to configure the DCB hardware.
2681 * This is also called by the gennetlink interface when reconfiguring
2682 * the DCB state.
2683 */
2684static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2685{
2686 struct ixgbe_hw *hw = &adapter->hw;
5f6c0181 2687 u32 txdctl;
2f90b865
AD		 2688 int i, j;
2689
2690 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2691 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2692 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2693
2694 /* reconfigure the hardware */
2695 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2696
2697 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2698 j = adapter->tx_ring[i]->reg_idx;
2f90b865
AD		 2699 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2700 /* PThresh workaround for Tx hang with DFP enabled. */
2701 txdctl |= 32;
2702 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2703 }
2704 /* Enable VLAN tag insert/strip */
5f6c0181
JB		 2705 ixgbe_vlan_filter_enable(adapter);
2706
2f90b865
AD		 2707 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2708}
2709
2710#endif
9a799d71
AK		 2711static void ixgbe_configure(struct ixgbe_adapter *adapter)
2712{
2713 struct net_device *netdev = adapter->netdev;
c4cf55e5 2714 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 2715 int i;
2716
2c5645cf 2717 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2718
2719 ixgbe_restore_vlan(adapter);
7a6b6f51 2720#ifdef CONFIG_IXGBE_DCB
2f90b865 2721 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
b352e40d
YZ		 2722 if (hw->mac.type == ixgbe_mac_82598EB)
2723 netif_set_gso_max_size(netdev, 32768);
2724 else
2725 netif_set_gso_max_size(netdev, 65536);
2f90b865
AD		 2726 ixgbe_configure_dcb(adapter);
2727 } else {
2728 netif_set_gso_max_size(netdev, 65536);
2729 }
2730#else
2731 netif_set_gso_max_size(netdev, 65536);
2732#endif
9a799d71 2733
eacd73f7
YZ		 2734#ifdef IXGBE_FCOE
2735 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2736 ixgbe_configure_fcoe(adapter);
2737
2738#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 2739 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2740 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 2741 adapter->tx_ring[i]->atr_sample_rate =
c4cf55e5
PWJ		 2742 adapter->atr_sample_rate;
2743 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2744 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2745 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2746 }
2747
9a799d71
AK		 2748 ixgbe_configure_tx(adapter);
2749 ixgbe_configure_rx(adapter);
2750 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 2751 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
2752 (adapter->rx_ring[i]->count - 1));
9a799d71
AK		 2753}
2754
e8e26350
PW		 2755static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2756{
2757 switch (hw->phy.type) {
2758 case ixgbe_phy_sfp_avago:
2759 case ixgbe_phy_sfp_ftl:
2760 case ixgbe_phy_sfp_intel:
2761 case ixgbe_phy_sfp_unknown:
2762 case ixgbe_phy_tw_tyco:
2763 case ixgbe_phy_tw_unknown:
2764 return true;
2765 default:
2766 return false;
2767 }
2768}
2769
0ecc061d 2770/**
e8e26350
PW		 2771 * ixgbe_sfp_link_config - set up SFP+ link
2772 * @adapter: pointer to private adapter struct
2773 **/
2774static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2775{
2776 struct ixgbe_hw *hw = &adapter->hw;
2777
2778 if (hw->phy.multispeed_fiber) {
2779 /*
2780 * In multispeed fiber setups, the device may not have
2781 * had a physical connection when the driver loaded.
2782 * If that's the case, the initial link configuration
2783 * couldn't get the MAC into 10G or 1G mode, so we'll
2784 * never have a link status change interrupt fire.
2785 * We need to try and force an autonegotiation
2786 * session, then bring up link.
2787 */
2788 hw->mac.ops.setup_sfp(hw);
2789 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2790 schedule_work(&adapter->multispeed_fiber_task);
2791 } else {
2792 /*
2793 * Direct Attach Cu and non-multispeed fiber modules
2794 * still need to be configured properly prior to
2795 * attempting link.
2796 */
2797 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2798 schedule_work(&adapter->sfp_config_module_task);
2799 }
2800}
2801
2802/**
2803 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2804 * @hw: pointer to private hardware struct
2805 *
2806 * Returns 0 on success, negative on failure
2807 **/
e8e26350 2808static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2809{
2810 u32 autoneg;
8620a103 2811 bool negotiation, link_up = false;
0ecc061d
PWJ		 2812 u32 ret = IXGBE_ERR_LINK_SETUP;
2813
2814 if (hw->mac.ops.check_link)
2815 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2816
2817 if (ret)
2818 goto link_cfg_out;
2819
2820 if (hw->mac.ops.get_link_capabilities)
8620a103 2821 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
0ecc061d
PWJ		 2822 if (ret)
2823 goto link_cfg_out;
2824
8620a103
MC		 2825 if (hw->mac.ops.setup_link)
2826 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 2827link_cfg_out:
2828 return ret;
2829}
2830
e8e26350
PW		 2831#define IXGBE_MAX_RX_DESC_POLL 10
2832static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2833 int rxr)
2834{
4a0b9ca0 2835 int j = adapter->rx_ring[rxr]->reg_idx;
e8e26350
PW		 2836 int k;
2837
2838 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2839 if (IXGBE_READ_REG(&adapter->hw,
2840 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2841 break;
2842 else
2843 msleep(1);
2844 }
2845 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2846 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2847 "not set within the polling period\n", rxr);
2848 }
4a0b9ca0
PW		 2849 ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
2850 (adapter->rx_ring[rxr]->count - 1));
e8e26350
PW		 2851}
2852
9a799d71
AK		 2853static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2854{
2855 struct net_device *netdev = adapter->netdev;
9a799d71 2856 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2857 int i, j = 0;
e8e26350 2858 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2859 int err;
9a799d71 2860 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2861 u32 txdctl, rxdctl, mhadd;
e8e26350 2862 u32 dmatxctl;
021230d4 2863 u32 gpie;
c9205697 2864 u32 ctrl_ext;
9a799d71 2865
5eba3699
AV		 2866 ixgbe_get_hw_control(adapter);
2867
021230d4
AV		 2868 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2869 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2870 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2871 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2872 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2873 } else {
2874 /* MSI only */
021230d4 2875 gpie = 0;
9a799d71 2876 }
1cdd1ec8
GR		 2877 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2878 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
2879 gpie |= IXGBE_GPIE_VTMODE_64;
2880 }
021230d4
AV		 2881 /* XXX: to interrupt immediately for EICS writes, enable this */
2882 /* gpie |= IXGBE_GPIE_EIMEN; */
2883 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2884 }
2885
9b471446
JB		 2886 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2887 /*
2888 * use EIAM to auto-mask when MSI-X interrupt is asserted
2889 * this saves a register write for every interrupt
2890 */
2891 switch (hw->mac.type) {
2892 case ixgbe_mac_82598EB:
2893 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2894 break;
2895 default:
2896 case ixgbe_mac_82599EB:
2897 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
2898 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
2899 break;
2900 }
2901 } else {
021230d4
AV		 2902 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2903 * specifically only auto mask tx and rx interrupts */
2904 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2905 }
9a799d71 2906
0befdb3e
JB		 2907 /* Enable fan failure interrupt if media type is copper */
2908 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2909 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2910 gpie |= IXGBE_SDP1_GPIEN;
2911 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2912 }
2913
e8e26350
PW		 2914 if (hw->mac.type == ixgbe_mac_82599EB) {
2915 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2916 gpie |= IXGBE_SDP1_GPIEN;
2917 gpie |= IXGBE_SDP2_GPIEN;
2918 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2919 }
2920
63f39bd1
YZ		 2921#ifdef IXGBE_FCOE
2922 /* adjust max frame to be able to do baby jumbo for FCoE */
f34c5c82 2923 if ((netdev->features & NETIF_F_FCOE_MTU) &&
63f39bd1
YZ		 2924 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2925 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2926
2927#endif /* IXGBE_FCOE */
021230d4 2928 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2929 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2930 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2931 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2932
2933 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2934 }
2935
2936 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2937 j = adapter->tx_ring[i]->reg_idx;
021230d4 2938 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2939 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2940 txdctl |= (8 << 16);
e8e26350
PW		 2941 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2942 }
2943
2944 if (hw->mac.type == ixgbe_mac_82599EB) {
2945 /* DMATXCTL.EN must be set after all Tx queue config is done */
2946 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2947 dmatxctl |= IXGBE_DMATXCTL_TE;
2948 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2949 }
2950 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2951 j = adapter->tx_ring[i]->reg_idx;
e8e26350 2952 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2953 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2954 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
1cdd1ec8
GR		 2955 if (hw->mac.type == ixgbe_mac_82599EB) {
2956 int wait_loop = 10;
2957 /* poll for Tx Enable ready */
2958 do {
2959 msleep(1);
2960 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2961 } while (--wait_loop &&
2962 !(txdctl & IXGBE_TXDCTL_ENABLE));
2963 if (!wait_loop)
2964 DPRINTK(DRV, ERR, "Could not enable "
2965 "Tx Queue %d\n", j);
2966 }
9a799d71
AK		 2967 }
2968
e8e26350 2969 for (i = 0; i < num_rx_rings; i++) {
4a0b9ca0 2970 j = adapter->rx_ring[i]->reg_idx;
021230d4
AV		 2971 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2972 /* enable PTHRESH=32 descriptors (half the internal cache)
2973 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2974 * this also removes a pesky rx_no_buffer_count increment */
2975 rxdctl |= 0x0020;
9a799d71 2976 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2977 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2978 if (hw->mac.type == ixgbe_mac_82599EB)
2979 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2980 }
2981 /* enable all receives */
2982 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2983 if (hw->mac.type == ixgbe_mac_82598EB)
2984 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2985 else
2986 rxdctl |= IXGBE_RXCTRL_RXEN;
2987 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2988
2989 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2990 ixgbe_configure_msix(adapter);
2991 else
2992 ixgbe_configure_msi_and_legacy(adapter);
2993
61fac744
PW		 2994 /* enable the optics */
2995 if (hw->phy.multispeed_fiber)
2996 hw->mac.ops.enable_tx_laser(hw);
2997
9a799d71 2998 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2999 ixgbe_napi_enable_all(adapter);
3000
3001 /* clear any pending interrupts, may auto mask */
3002 IXGBE_READ_REG(hw, IXGBE_EICR);
3003
9a799d71
AK		 3004 ixgbe_irq_enable(adapter);
3005
bf069c97
DS		 3006 /*
3007 * If this adapter has a fan, check to see if we had a failure
3008 * before we enabled the interrupt.
3009 */
3010 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3011 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3012 if (esdp & IXGBE_ESDP_SDP1)
3013 DPRINTK(DRV, CRIT,
3014 "Fan has stopped, replace the adapter\n");
3015 }
3016
e8e26350
PW		 3017 /*
3018 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 3019 * arrived before interrupts were enabled but after probe. Such
3020 * devices wouldn't have their type identified yet. We need to
3021 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 3022 * If we're not hot-pluggable SFP+, we just need to configure link
3023 * and bring it up.
3024 */
19343de2
DS		 3025 if (hw->phy.type == ixgbe_phy_unknown) {
3026 err = hw->phy.ops.identify(hw);
3027 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 3028 /*
3029 * Take the device down and schedule the sfp tasklet
3030 * which will unregister_netdev and log it.
3031 */
19343de2 3032 ixgbe_down(adapter);
5da43c1a 3033 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 3034 return err;
3035 }
e8e26350
PW		 3036 }
3037
3038 if (ixgbe_is_sfp(hw)) {
3039 ixgbe_sfp_link_config(adapter);
3040 } else {
3041 err = ixgbe_non_sfp_link_config(hw);
3042 if (err)
3043 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
3044 }
0ecc061d 3045
c4cf55e5
PWJ		 3046 for (i = 0; i < adapter->num_tx_queues; i++)
3047 set_bit(__IXGBE_FDIR_INIT_DONE,
4a0b9ca0 3048 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5 3049
1da100bb
PWJ		 3050 /* enable transmits */
3051 netif_tx_start_all_queues(netdev);
3052
9a799d71
AK		 3053 /* bring the link up in the watchdog, this could race with our first
3054 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3055 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3056 adapter->link_check_timeout = jiffies;
9a799d71 3057 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3058
3059 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3060 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3061 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3062 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3063
9a799d71
AK		 3064 return 0;
3065}
3066
d4f80882
AV		 3067void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3068{
3069 WARN_ON(in_interrupt());
3070 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3071 msleep(1);
3072 ixgbe_down(adapter);
5809a1ae
GR		 3073 /*
3074 * If SR-IOV enabled then wait a bit before bringing the adapter
3075 * back up to give the VFs time to respond to the reset. The
3076 * two second wait is based upon the watchdog timer cycle in
3077 * the VF driver.
3078 */
3079 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3080 msleep(2000);
d4f80882
AV		 3081 ixgbe_up(adapter);
3082 clear_bit(__IXGBE_RESETTING, &adapter->state);
3083}
3084
9a799d71
AK		 3085int ixgbe_up(struct ixgbe_adapter *adapter)
3086{
3087 /* hardware has been reset, we need to reload some things */
3088 ixgbe_configure(adapter);
3089
3090 return ixgbe_up_complete(adapter);
3091}
3092
3093void ixgbe_reset(struct ixgbe_adapter *adapter)
3094{
c44ade9e 3095 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3096 int err;
3097
3098 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3099 switch (err) {
3100 case 0:
3101 case IXGBE_ERR_SFP_NOT_PRESENT:
3102 break;
3103 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3104 dev_err(&adapter->pdev->dev, "master disable timed out\n");
3105 break;
794caeb2
PWJ		 3106 case IXGBE_ERR_EEPROM_VERSION:
3107 /* We are running on a pre-production device, log a warning */
3108 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
3109 "adapter/LOM. Please be aware there may be issues "
3110 "associated with your hardware. If you are "
3111 "experiencing problems please contact your Intel or "
3112 "hardware representative who provided you with this "
3113 "hardware.\n");
3114 break;
da4dd0f7
PWJ		 3115 default:
3116 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
3117 }
9a799d71
AK		 3118
3119 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3120 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3121 IXGBE_RAH_AV);
9a799d71
AK		 3122}
3123
9a799d71
AK		 3124/**
3125 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3126 * @adapter: board private structure
3127 * @rx_ring: ring to free buffers from
3128 **/
3129static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 3130 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3131{
3132 struct pci_dev *pdev = adapter->pdev;
3133 unsigned long size;
3134 unsigned int i;
3135
3136 /* Free all the Rx ring sk_buffs */
3137
3138 for (i = 0; i < rx_ring->count; i++) {
3139 struct ixgbe_rx_buffer *rx_buffer_info;
3140
3141 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3142 if (rx_buffer_info->dma) {
3143 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 3144 rx_ring->rx_buf_len,
3145 PCI_DMA_FROMDEVICE);
9a799d71
AK		 3146 rx_buffer_info->dma = 0;
3147 }
3148 if (rx_buffer_info->skb) {
f8212f97 3149 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3150 rx_buffer_info->skb = NULL;
f8212f97
AD		 3151 do {
3152 struct sk_buff *this = skb;
fd3686a8 3153 if (IXGBE_RSC_CB(this)->dma) {
43634e82
MC		 3154 pci_unmap_single(pdev, IXGBE_RSC_CB(this)->dma,
3155 rx_ring->rx_buf_len,
3156 PCI_DMA_FROMDEVICE);
fd3686a8
MC		 3157 IXGBE_RSC_CB(this)->dma = 0;
3158 }
f8212f97
AD		 3159 skb = skb->prev;
3160 dev_kfree_skb(this);
3161 } while (skb);
9a799d71
AK		 3162 }
3163 if (!rx_buffer_info->page)
3164 continue;
4f57ca6e
JB		 3165 if (rx_buffer_info->page_dma) {
3166 pci_unmap_page(pdev, rx_buffer_info->page_dma,
3167 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
3168 rx_buffer_info->page_dma = 0;
3169 }
9a799d71
AK		 3170 put_page(rx_buffer_info->page);
3171 rx_buffer_info->page = NULL;
762f4c57 3172 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3173 }
3174
3175 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3176 memset(rx_ring->rx_buffer_info, 0, size);
3177
3178 /* Zero out the descriptor ring */
3179 memset(rx_ring->desc, 0, rx_ring->size);
3180
3181 rx_ring->next_to_clean = 0;
3182 rx_ring->next_to_use = 0;
3183
9891ca7c
JB		 3184 if (rx_ring->head)
3185 writel(0, adapter->hw.hw_addr + rx_ring->head);
3186 if (rx_ring->tail)
3187 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 3188}
3189
3190/**
3191 * ixgbe_clean_tx_ring - Free Tx Buffers
3192 * @adapter: board private structure
3193 * @tx_ring: ring to be cleaned
3194 **/
3195static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 3196 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3197{
3198 struct ixgbe_tx_buffer *tx_buffer_info;
3199 unsigned long size;
3200 unsigned int i;
3201
3202 /* Free all the Tx ring sk_buffs */
3203
3204 for (i = 0; i < tx_ring->count; i++) {
3205 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3206 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3207 }
3208
3209 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3210 memset(tx_ring->tx_buffer_info, 0, size);
3211
3212 /* Zero out the descriptor ring */
3213 memset(tx_ring->desc, 0, tx_ring->size);
3214
3215 tx_ring->next_to_use = 0;
3216 tx_ring->next_to_clean = 0;
3217
9891ca7c
JB		 3218 if (tx_ring->head)
3219 writel(0, adapter->hw.hw_addr + tx_ring->head);
3220 if (tx_ring->tail)
3221 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 3222}
3223
3224/**
021230d4 3225 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3226 * @adapter: board private structure
3227 **/
021230d4 3228static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3229{
3230 int i;
3231
021230d4 3232 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3233 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
9a799d71
AK		 3234}
3235
3236/**
021230d4 3237 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3238 * @adapter: board private structure
3239 **/
021230d4 3240static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3241{
3242 int i;
3243
021230d4 3244 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3245 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3246}
3247
3248void ixgbe_down(struct ixgbe_adapter *adapter)
3249{
3250 struct net_device *netdev = adapter->netdev;
7f821875 3251 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3252 u32 rxctrl;
7f821875
JB		 3253 u32 txdctl;
3254 int i, j;
9a799d71
AK		 3255
3256 /* signal that we are down to the interrupt handler */
3257 set_bit(__IXGBE_DOWN, &adapter->state);
3258
61fac744
PW		 3259 /* power down the optics */
3260 if (hw->phy.multispeed_fiber)
3261 hw->mac.ops.disable_tx_laser(hw);
3262
767081ad
GR		 3263 /* disable receive for all VFs and wait one second */
3264 if (adapter->num_vfs) {
767081ad
GR		 3265 /* ping all the active vfs to let them know we are going down */
3266 ixgbe_ping_all_vfs(adapter);
581d1aa7 3267
767081ad
GR		 3268 /* Disable all VFTE/VFRE TX/RX */
3269 ixgbe_disable_tx_rx(adapter);
581d1aa7
GR		 3270
3271 /* Mark all the VFs as inactive */
3272 for (i = 0 ; i < adapter->num_vfs; i++)
3273 adapter->vfinfo[i].clear_to_send = 0;
767081ad
GR		 3274 }
3275
9a799d71 3276 /* disable receives */
7f821875
JB		 3277 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3278 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 3279
3280 netif_tx_disable(netdev);
3281
7f821875 3282 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 3283 msleep(10);
3284
7f821875
JB		 3285 netif_tx_stop_all_queues(netdev);
3286
9a799d71
AK		 3287 ixgbe_irq_disable(adapter);
3288
021230d4 3289 ixgbe_napi_disable_all(adapter);
7f821875 3290
0a1f87cb
DS		 3291 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3292 del_timer_sync(&adapter->sfp_timer);
9a799d71 3293 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 3294 cancel_work_sync(&adapter->watchdog_task);
9a799d71 3295
c4cf55e5
PWJ		 3296 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3297 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3298 cancel_work_sync(&adapter->fdir_reinit_task);
3299
7f821875
JB		 3300 /* disable transmits in the hardware now that interrupts are off */
3301 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3302 j = adapter->tx_ring[i]->reg_idx;
7f821875
JB		 3303 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3304 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3305 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3306 }
88512539
PW		 3307 /* Disable the Tx DMA engine on 82599 */
3308 if (hw->mac.type == ixgbe_mac_82599EB)
3309 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3310 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3311 ~IXGBE_DMATXCTL_TE));
7f821875 3312
9a799d71 3313 netif_carrier_off(netdev);
9a799d71 3314
9a713e7c
PW		 3315 /* clear n-tuple filters that are cached */
3316 ethtool_ntuple_flush(netdev);
3317
6f4a0e45
PL		 3318 if (!pci_channel_offline(adapter->pdev))
3319 ixgbe_reset(adapter);
9a799d71
AK		 3320 ixgbe_clean_all_tx_rings(adapter);
3321 ixgbe_clean_all_rx_rings(adapter);
3322
5dd2d332 3323#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3324 /* since we reset the hardware DCA settings were cleared */
e35ec126 3325 ixgbe_setup_dca(adapter);
96b0e0f6 3326#endif
9a799d71
AK		 3327}
3328
9a799d71 3329/**
021230d4
AV		 3330 * ixgbe_poll - NAPI Rx polling callback
3331 * @napi: structure for representing this polling device
3332 * @budget: how many packets driver is allowed to clean
3333 *
3334 * This function is used for legacy and MSI, NAPI mode
9a799d71 3335 **/
021230d4 3336static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3337{
9a1a69ad
JB		 3338 struct ixgbe_q_vector *q_vector =
3339 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3340 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 3341 int tx_clean_complete, work_done = 0;
9a799d71 3342
5dd2d332 3343#ifdef CONFIG_IXGBE_DCA
bd0362dd 3344 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4a0b9ca0
PW		 3345 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3346 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
bd0362dd
JC		 3347 }
3348#endif
3349
4a0b9ca0
PW		 3350 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3351 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 3352
9a1a69ad 3353 if (!tx_clean_complete)
d2c7ddd6
DM		 3354 work_done = budget;
3355
53e52c72
DM		 3356 /* If budget not fully consumed, exit the polling mode */
3357 if (work_done < budget) {
288379f0 3358 napi_complete(napi);
f7554a2b 3359 if (adapter->rx_itr_setting & 1)
f494e8fa 3360 ixgbe_set_itr(adapter);
d4f80882 3361 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 3362 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 3363 }
9a799d71
AK		 3364 return work_done;
3365}
3366
3367/**
3368 * ixgbe_tx_timeout - Respond to a Tx Hang
3369 * @netdev: network interface device structure
3370 **/
3371static void ixgbe_tx_timeout(struct net_device *netdev)
3372{
3373 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3374
3375 /* Do the reset outside of interrupt context */
3376 schedule_work(&adapter->reset_task);
3377}
3378
3379static void ixgbe_reset_task(struct work_struct *work)
3380{
3381 struct ixgbe_adapter *adapter;
3382 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3383
2f90b865
AD		 3384 /* If we're already down or resetting, just bail */
3385 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3386 test_bit(__IXGBE_RESETTING, &adapter->state))
3387 return;
3388
9a799d71
AK		 3389 adapter->tx_timeout_count++;
3390
d4f80882 3391 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3392}
3393
bc97114d
PWJ		 3394#ifdef CONFIG_IXGBE_DCB
3395static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3396{
bc97114d 3397 bool ret = false;
0cefafad 3398 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3399
0cefafad
JB		 3400 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3401 return ret;
3402
3403 f->mask = 0x7 << 3;
3404 adapter->num_rx_queues = f->indices;
3405 adapter->num_tx_queues = f->indices;
3406 ret = true;
2f90b865 3407
bc97114d
PWJ		 3408 return ret;
3409}
3410#endif
3411
4df10466
JB		 3412/**
3413 * ixgbe_set_rss_queues: Allocate queues for RSS
3414 * @adapter: board private structure to initialize
3415 *
3416 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3417 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3418 *
3419 **/
bc97114d
PWJ		 3420static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3421{
3422 bool ret = false;
0cefafad 3423 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3424
3425 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3426 f->mask = 0xF;
3427 adapter->num_rx_queues = f->indices;
3428 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3429 ret = true;
3430 } else {
bc97114d 3431 ret = false;
b9804972
JB		 3432 }
3433
bc97114d
PWJ		 3434 return ret;
3435}
3436
c4cf55e5
PWJ		 3437/**
3438 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3439 * @adapter: board private structure to initialize
3440 *
3441 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3442 * to the original CPU that initiated the Tx session. This runs in addition
3443 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3444 * Rx load across CPUs using RSS.
3445 *
3446 **/
3447static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3448{
3449 bool ret = false;
3450 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3451
3452 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3453 f_fdir->mask = 0;
3454
3455 /* Flow Director must have RSS enabled */
3456 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3457 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3458 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3459 adapter->num_tx_queues = f_fdir->indices;
3460 adapter->num_rx_queues = f_fdir->indices;
3461 ret = true;
3462 } else {
3463 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3464 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3465 }
3466 return ret;
3467}
3468
0331a832
YZ		 3469#ifdef IXGBE_FCOE
3470/**
3471 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3472 * @adapter: board private structure to initialize
3473 *
3474 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3475 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3476 * rx queues out of the max number of rx queues, instead, it is used as the
3477 * index of the first rx queue used by FCoE.
3478 *
3479 **/
3480static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3481{
3482 bool ret = false;
3483 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3484
3485 f->indices = min((int)num_online_cpus(), f->indices);
3486 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 3487 adapter->num_rx_queues = 1;
3488 adapter->num_tx_queues = 1;
0331a832
YZ		 3489#ifdef CONFIG_IXGBE_DCB
3490 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
d6dbee86 3491 DPRINTK(PROBE, INFO, "FCoE enabled with DCB\n");
0331a832
YZ		 3492 ixgbe_set_dcb_queues(adapter);
3493 }
3494#endif
3495 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
d6dbee86 3496 DPRINTK(PROBE, INFO, "FCoE enabled with RSS\n");
8faa2a78
YZ		 3497 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3498 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3499 ixgbe_set_fdir_queues(adapter);
3500 else
3501 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 3502 }
3503 /* adding FCoE rx rings to the end */
3504 f->mask = adapter->num_rx_queues;
3505 adapter->num_rx_queues += f->indices;
8de8b2e6 3506 adapter->num_tx_queues += f->indices;
0331a832
YZ		 3507
3508 ret = true;
3509 }
3510
3511 return ret;
3512}
3513
3514#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 3515/**
3516 * ixgbe_set_sriov_queues: Allocate queues for IOV use
3517 * @adapter: board private structure to initialize
3518 *
3519 * IOV doesn't actually use anything, so just NAK the
3520 * request for now and let the other queue routines
3521 * figure out what to do.
3522 */
3523static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
3524{
3525 return false;
3526}
3527
4df10466
JB		 3528/*
3529 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3530 * @adapter: board private structure to initialize
3531 *
3532 * This is the top level queue allocation routine. The order here is very
3533 * important, starting with the "most" number of features turned on at once,
3534 * and ending with the smallest set of features. This way large combinations
3535 * can be allocated if they're turned on, and smaller combinations are the
3536 * fallthrough conditions.
3537 *
3538 **/
bc97114d
PWJ		 3539static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3540{
1cdd1ec8
GR		 3541 /* Start with base case */
3542 adapter->num_rx_queues = 1;
3543 adapter->num_tx_queues = 1;
3544 adapter->num_rx_pools = adapter->num_rx_queues;
3545 adapter->num_rx_queues_per_pool = 1;
3546
3547 if (ixgbe_set_sriov_queues(adapter))
3548 return;
3549
0331a832
YZ		 3550#ifdef IXGBE_FCOE
3551 if (ixgbe_set_fcoe_queues(adapter))
3552 goto done;
3553
3554#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3555#ifdef CONFIG_IXGBE_DCB
3556 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 3557 goto done;
bc97114d
PWJ		 3558
3559#endif
c4cf55e5
PWJ		 3560 if (ixgbe_set_fdir_queues(adapter))
3561 goto done;
3562
bc97114d 3563 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 3564 goto done;
3565
3566 /* fallback to base case */
3567 adapter->num_rx_queues = 1;
3568 adapter->num_tx_queues = 1;
3569
3570done:
3571 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3572 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 3573}
3574
021230d4 3575static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 3576 int vectors)
021230d4
AV		 3577{
3578 int err, vector_threshold;
3579
3580 /* We'll want at least 3 (vector_threshold):
3581 * 1) TxQ[0] Cleanup
3582 * 2) RxQ[0] Cleanup
3583 * 3) Other (Link Status Change, etc.)
3584 * 4) TCP Timer (optional)
3585 */
3586 vector_threshold = MIN_MSIX_COUNT;
3587
3588 /* The more we get, the more we will assign to Tx/Rx Cleanup
3589 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3590 * Right now, we simply care about how many we'll get; we'll
3591 * set them up later while requesting irq's.
3592 */
3593 while (vectors >= vector_threshold) {
3594 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 3595 vectors);
021230d4
AV		 3596 if (!err) /* Success in acquiring all requested vectors. */
3597 break;
3598 else if (err < 0)
3599 vectors = 0; /* Nasty failure, quit now */
3600 else /* err == number of vectors we should try again with */
3601 vectors = err;
3602 }
3603
3604 if (vectors < vector_threshold) {
3605 /* Can't allocate enough MSI-X interrupts? Oh well.
3606 * This just means we'll go with either a single MSI
3607 * vector or fall back to legacy interrupts.
3608 */
3609 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3610 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3611 kfree(adapter->msix_entries);
3612 adapter->msix_entries = NULL;
021230d4
AV		 3613 } else {
3614 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 3615 /*
3616 * Adjust for only the vectors we'll use, which is minimum
3617 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3618 * vectors we were allocated.
3619 */
3620 adapter->num_msix_vectors = min(vectors,
3621 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 3622 }
3623}
3624
021230d4 3625/**
bc97114d 3626 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 3627 * @adapter: board private structure to initialize
3628 *
bc97114d
PWJ		 3629 * Cache the descriptor ring offsets for RSS to the assigned rings.
3630 *
021230d4 3631 **/
bc97114d 3632static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 3633{
bc97114d
PWJ		 3634 int i;
3635 bool ret = false;
3636
3637 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3638 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3639 adapter->rx_ring[i]->reg_idx = i;
bc97114d 3640 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3641 adapter->tx_ring[i]->reg_idx = i;
bc97114d
PWJ		 3642 ret = true;
3643 } else {
3644 ret = false;
3645 }
3646
3647 return ret;
3648}
3649
3650#ifdef CONFIG_IXGBE_DCB
3651/**
3652 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3653 * @adapter: board private structure to initialize
3654 *
3655 * Cache the descriptor ring offsets for DCB to the assigned rings.
3656 *
3657 **/
3658static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3659{
3660 int i;
3661 bool ret = false;
3662 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3663
3664 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3665 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 3666 /* the number of queues is assumed to be symmetric */
3667 for (i = 0; i < dcb_i; i++) {
4a0b9ca0
PW		 3668 adapter->rx_ring[i]->reg_idx = i << 3;
3669 adapter->tx_ring[i]->reg_idx = i << 2;
2f90b865 3670 }
bc97114d 3671 ret = true;
e8e26350 3672 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 3673 if (dcb_i == 8) {
3674 /*
3675 * Tx TC0 starts at: descriptor queue 0
3676 * Tx TC1 starts at: descriptor queue 32
3677 * Tx TC2 starts at: descriptor queue 64
3678 * Tx TC3 starts at: descriptor queue 80
3679 * Tx TC4 starts at: descriptor queue 96
3680 * Tx TC5 starts at: descriptor queue 104
3681 * Tx TC6 starts at: descriptor queue 112
3682 * Tx TC7 starts at: descriptor queue 120
3683 *
3684 * Rx TC0-TC7 are offset by 16 queues each
3685 */
3686 for (i = 0; i < 3; i++) {
4a0b9ca0
PW		 3687 adapter->tx_ring[i]->reg_idx = i << 5;
3688 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 3689 }
3690 for ( ; i < 5; i++) {
4a0b9ca0 3691 adapter->tx_ring[i]->reg_idx =
f92ef202 3692 ((i + 2) << 4);
4a0b9ca0 3693 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 3694 }
3695 for ( ; i < dcb_i; i++) {
4a0b9ca0 3696 adapter->tx_ring[i]->reg_idx =
f92ef202 3697 ((i + 8) << 3);
4a0b9ca0 3698 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 3699 }
3700
3701 ret = true;
3702 } else if (dcb_i == 4) {
3703 /*
3704 * Tx TC0 starts at: descriptor queue 0
3705 * Tx TC1 starts at: descriptor queue 64
3706 * Tx TC2 starts at: descriptor queue 96
3707 * Tx TC3 starts at: descriptor queue 112
3708 *
3709 * Rx TC0-TC3 are offset by 32 queues each
3710 */
4a0b9ca0
PW		 3711 adapter->tx_ring[0]->reg_idx = 0;
3712 adapter->tx_ring[1]->reg_idx = 64;
3713 adapter->tx_ring[2]->reg_idx = 96;
3714 adapter->tx_ring[3]->reg_idx = 112;
f92ef202 3715 for (i = 0 ; i < dcb_i; i++)
4a0b9ca0 3716 adapter->rx_ring[i]->reg_idx = i << 5;
f92ef202
PW		 3717
3718 ret = true;
3719 } else {
3720 ret = false;
e8e26350 3721 }
bc97114d
PWJ		 3722 } else {
3723 ret = false;
021230d4 3724 }
bc97114d
PWJ		 3725 } else {
3726 ret = false;
021230d4 3727 }
bc97114d
PWJ		 3728
3729 return ret;
3730}
3731#endif
3732
c4cf55e5
PWJ		 3733/**
3734 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3735 * @adapter: board private structure to initialize
3736 *
3737 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3738 *
3739 **/
3740static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3741{
3742 int i;
3743 bool ret = false;
3744
3745 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3746 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3747 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3748 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3749 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 3750 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3751 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 3752 ret = true;
3753 }
3754
3755 return ret;
3756}
3757
0331a832
YZ		 3758#ifdef IXGBE_FCOE
3759/**
3760 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3761 * @adapter: board private structure to initialize
3762 *
3763 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3764 *
3765 */
3766static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3767{
8de8b2e6 3768 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 3769 bool ret = false;
3770 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3771
3772 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3773#ifdef CONFIG_IXGBE_DCB
3774 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 3775 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3776
0331a832 3777 ixgbe_cache_ring_dcb(adapter);
8de8b2e6 3778 /* find out queues in TC for FCoE */
4a0b9ca0
PW		 3779 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
3780 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
8de8b2e6
YZ		 3781 /*
3782 * In 82599, the number of Tx queues for each traffic
3783 * class for both 8-TC and 4-TC modes are:
3784 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3785 * 8 TCs: 32 32 16 16 8 8 8 8
3786 * 4 TCs: 64 64 32 32
3787 * We have max 8 queues for FCoE, where 8 the is
3788 * FCoE redirection table size. If TC for FCoE is
3789 * less than or equal to TC3, we have enough queues
3790 * to add max of 8 queues for FCoE, so we start FCoE
3791 * tx descriptor from the next one, i.e., reg_idx + 1.
3792 * If TC for FCoE is above TC3, implying 8 TC mode,
3793 * and we need 8 for FCoE, we have to take all queues
3794 * in that traffic class for FCoE.
3795 */
3796 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3797 fcoe_tx_i--;
0331a832
YZ		 3798 }
3799#endif /* CONFIG_IXGBE_DCB */
3800 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 3801 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3802 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3803 ixgbe_cache_ring_fdir(adapter);
3804 else
3805 ixgbe_cache_ring_rss(adapter);
3806
8de8b2e6
YZ		 3807 fcoe_rx_i = f->mask;
3808 fcoe_tx_i = f->mask;
3809 }
3810 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4a0b9ca0
PW		 3811 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
3812 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
0331a832 3813 }
0331a832
YZ		 3814 ret = true;
3815 }
3816 return ret;
3817}
3818
3819#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 3820/**
3821 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
3822 * @adapter: board private structure to initialize
3823 *
3824 * SR-IOV doesn't use any descriptor rings but changes the default if
3825 * no other mapping is used.
3826 *
3827 */
3828static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
3829{
4a0b9ca0
PW		 3830 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
3831 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 3832 if (adapter->num_vfs)
3833 return true;
3834 else
3835 return false;
3836}
3837
bc97114d
PWJ		 3838/**
3839 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3840 * @adapter: board private structure to initialize
3841 *
3842 * Once we know the feature-set enabled for the device, we'll cache
3843 * the register offset the descriptor ring is assigned to.
3844 *
3845 * Note, the order the various feature calls is important. It must start with
3846 * the "most" features enabled at the same time, then trickle down to the
3847 * least amount of features turned on at once.
3848 **/
3849static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3850{
3851 /* start with default case */
4a0b9ca0
PW		 3852 adapter->rx_ring[0]->reg_idx = 0;
3853 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 3854
1cdd1ec8
GR		 3855 if (ixgbe_cache_ring_sriov(adapter))
3856 return;
3857
0331a832
YZ		 3858#ifdef IXGBE_FCOE
3859 if (ixgbe_cache_ring_fcoe(adapter))
3860 return;
3861
3862#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3863#ifdef CONFIG_IXGBE_DCB
3864 if (ixgbe_cache_ring_dcb(adapter))
3865 return;
3866
3867#endif
c4cf55e5
PWJ		 3868 if (ixgbe_cache_ring_fdir(adapter))
3869 return;
3870
bc97114d
PWJ		 3871 if (ixgbe_cache_ring_rss(adapter))
3872 return;
021230d4
AV		 3873}
3874
9a799d71
AK		 3875/**
3876 * ixgbe_alloc_queues - Allocate memory for all rings
3877 * @adapter: board private structure to initialize
3878 *
3879 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 3880 * number of queues at compile-time. The polling_netdev array is
3881 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 3882 **/
2f90b865 3883static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 3884{
3885 int i;
4a0b9ca0 3886 int orig_node = adapter->node;
9a799d71 3887
021230d4 3888 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 3889 struct ixgbe_ring *ring = adapter->tx_ring[i];
3890 if (orig_node == -1) {
3891 int cur_node = next_online_node(adapter->node);
3892 if (cur_node == MAX_NUMNODES)
3893 cur_node = first_online_node;
3894 adapter->node = cur_node;
3895 }
3896 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
3897 adapter->node);
3898 if (!ring)
3899 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
3900 if (!ring)
3901 goto err_tx_ring_allocation;
3902 ring->count = adapter->tx_ring_count;
3903 ring->queue_index = i;
3904 ring->numa_node = adapter->node;
3905
3906 adapter->tx_ring[i] = ring;
021230d4 3907 }
b9804972 3908
4a0b9ca0
PW		 3909 /* Restore the adapter's original node */
3910 adapter->node = orig_node;
3911
9a799d71 3912 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 3913 struct ixgbe_ring *ring = adapter->rx_ring[i];
3914 if (orig_node == -1) {
3915 int cur_node = next_online_node(adapter->node);
3916 if (cur_node == MAX_NUMNODES)
3917 cur_node = first_online_node;
3918 adapter->node = cur_node;
3919 }
3920 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
3921 adapter->node);
3922 if (!ring)
3923 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
3924 if (!ring)
3925 goto err_rx_ring_allocation;
3926 ring->count = adapter->rx_ring_count;
3927 ring->queue_index = i;
3928 ring->numa_node = adapter->node;
3929
3930 adapter->rx_ring[i] = ring;
021230d4
AV		 3931 }
3932
4a0b9ca0
PW		 3933 /* Restore the adapter's original node */
3934 adapter->node = orig_node;
3935
021230d4
AV		 3936 ixgbe_cache_ring_register(adapter);
3937
3938 return 0;
3939
3940err_rx_ring_allocation:
4a0b9ca0
PW		 3941 for (i = 0; i < adapter->num_tx_queues; i++)
3942 kfree(adapter->tx_ring[i]);
021230d4
AV		 3943err_tx_ring_allocation:
3944 return -ENOMEM;
3945}
3946
3947/**
3948 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3949 * @adapter: board private structure to initialize
3950 *
3951 * Attempt to configure the interrupts using the best available
3952 * capabilities of the hardware and the kernel.
3953 **/
feea6a57 3954static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 3955{
8be0e467 3956 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 3957 int err = 0;
3958 int vector, v_budget;
3959
3960 /*
3961 * It's easy to be greedy for MSI-X vectors, but it really
3962 * doesn't do us much good if we have a lot more vectors
3963 * than CPU's. So let's be conservative and only ask for
342bde1b 3964 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 3965 */
3966 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
342bde1b 3967 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 3968
3969 /*
3970 * At the same time, hardware can only support a maximum of
8be0e467
PW		 3971 * hw.mac->max_msix_vectors vectors. With features
3972 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3973 * descriptor queues supported by our device. Thus, we cap it off in
3974 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3975 */
8be0e467 3976 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3977
3978 /* A failure in MSI-X entry allocation isn't fatal, but it does
3979 * mean we disable MSI-X capabilities of the adapter. */
3980 adapter->msix_entries = kcalloc(v_budget,
b4617240 3981 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 3982 if (adapter->msix_entries) {
3983 for (vector = 0; vector < v_budget; vector++)
3984 adapter->msix_entries[vector].entry = vector;
021230d4 3985
7a921c93 3986 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 3987
7a921c93
AD		 3988 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3989 goto out;
3990 }
021230d4 3991
7a921c93
AD		 3992 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3993 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 3994 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3995 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3996 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 3997 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3998 ixgbe_disable_sriov(adapter);
3999
7a921c93 4000 ixgbe_set_num_queues(adapter);
021230d4 4001
021230d4
AV		 4002 err = pci_enable_msi(adapter->pdev);
4003 if (!err) {
4004 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4005 } else {
4006 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 4007 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4008 /* reset err */
4009 err = 0;
4010 }
4011
4012out:
021230d4
AV		 4013 return err;
4014}
4015
7a921c93
AD		 4016/**
4017 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4018 * @adapter: board private structure to initialize
4019 *
4020 * We allocate one q_vector per queue interrupt. If allocation fails we
4021 * return -ENOMEM.
4022 **/
4023static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4024{
4025 int q_idx, num_q_vectors;
4026 struct ixgbe_q_vector *q_vector;
4027 int napi_vectors;
4028 int (*poll)(struct napi_struct *, int);
4029
4030 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4031 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4032 napi_vectors = adapter->num_rx_queues;
91281fd3 4033 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4034 } else {
4035 num_q_vectors = 1;
4036 napi_vectors = 1;
4037 poll = &ixgbe_poll;
4038 }
4039
4040 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2
JB		 4041 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4042 GFP_KERNEL, adapter->node);
4043 if (!q_vector)
4044 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4045 GFP_KERNEL);
7a921c93
AD		 4046 if (!q_vector)
4047 goto err_out;
4048 q_vector->adapter = adapter;
f7554a2b
NS		 4049 if (q_vector->txr_count && !q_vector->rxr_count)
4050 q_vector->eitr = adapter->tx_eitr_param;
4051 else
4052 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4053 q_vector->v_idx = q_idx;
91281fd3 4054 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4055 adapter->q_vector[q_idx] = q_vector;
4056 }
4057
4058 return 0;
4059
4060err_out:
4061 while (q_idx) {
4062 q_idx--;
4063 q_vector = adapter->q_vector[q_idx];
4064 netif_napi_del(&q_vector->napi);
4065 kfree(q_vector);
4066 adapter->q_vector[q_idx] = NULL;
4067 }
4068 return -ENOMEM;
4069}
4070
4071/**
4072 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4073 * @adapter: board private structure to initialize
4074 *
4075 * This function frees the memory allocated to the q_vectors. In addition if
4076 * NAPI is enabled it will delete any references to the NAPI struct prior
4077 * to freeing the q_vector.
4078 **/
4079static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4080{
4081 int q_idx, num_q_vectors;
7a921c93 4082
91281fd3 4083 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4084 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4085 else
7a921c93 4086 num_q_vectors = 1;
7a921c93
AD		 4087
4088 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4089 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4090 adapter->q_vector[q_idx] = NULL;
91281fd3 4091 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4092 kfree(q_vector);
4093 }
4094}
4095
7b25cdba 4096static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4097{
4098 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4099 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4100 pci_disable_msix(adapter->pdev);
4101 kfree(adapter->msix_entries);
4102 adapter->msix_entries = NULL;
4103 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4104 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4105 pci_disable_msi(adapter->pdev);
4106 }
4107 return;
4108}
4109
4110/**
4111 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4112 * @adapter: board private structure to initialize
4113 *
4114 * We determine which interrupt scheme to use based on...
4115 * - Kernel support (MSI, MSI-X)
4116 * - which can be user-defined (via MODULE_PARAM)
4117 * - Hardware queue count (num_*_queues)
4118 * - defined by miscellaneous hardware support/features (RSS, etc.)
4119 **/
2f90b865 4120int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4121{
4122 int err;
4123
4124 /* Number of supported queues */
4125 ixgbe_set_num_queues(adapter);
4126
021230d4
AV		 4127 err = ixgbe_set_interrupt_capability(adapter);
4128 if (err) {
4129 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
4130 goto err_set_interrupt;
9a799d71
AK		 4131 }
4132
7a921c93
AD		 4133 err = ixgbe_alloc_q_vectors(adapter);
4134 if (err) {
4135 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
4136 "vectors\n");
4137 goto err_alloc_q_vectors;
4138 }
4139
4140 err = ixgbe_alloc_queues(adapter);
4141 if (err) {
4142 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
4143 goto err_alloc_queues;
4144 }
4145
021230d4 4146 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 4147 "Tx Queue count = %u\n",
4148 (adapter->num_rx_queues > 1) ? "Enabled" :
4149 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4150
4151 set_bit(__IXGBE_DOWN, &adapter->state);
4152
9a799d71 4153 return 0;
021230d4 4154
7a921c93
AD		 4155err_alloc_queues:
4156 ixgbe_free_q_vectors(adapter);
4157err_alloc_q_vectors:
4158 ixgbe_reset_interrupt_capability(adapter);
021230d4 4159err_set_interrupt:
7a921c93
AD		 4160 return err;
4161}
4162
4163/**
4164 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4165 * @adapter: board private structure to clear interrupt scheme on
4166 *
4167 * We go through and clear interrupt specific resources and reset the structure
4168 * to pre-load conditions
4169 **/
4170void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4171{
4a0b9ca0
PW		 4172 int i;
4173
4174 for (i = 0; i < adapter->num_tx_queues; i++) {
4175 kfree(adapter->tx_ring[i]);
4176 adapter->tx_ring[i] = NULL;
4177 }
4178 for (i = 0; i < adapter->num_rx_queues; i++) {
4179 kfree(adapter->rx_ring[i]);
4180 adapter->rx_ring[i] = NULL;
4181 }
7a921c93
AD		 4182
4183 ixgbe_free_q_vectors(adapter);
4184 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4185}
4186
c4900be0
DS		 4187/**
4188 * ixgbe_sfp_timer - worker thread to find a missing module
4189 * @data: pointer to our adapter struct
4190 **/
4191static void ixgbe_sfp_timer(unsigned long data)
4192{
4193 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4194
4df10466
JB		 4195 /*
4196 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 4197 * delays that sfp+ detection requires
4198 */
4199 schedule_work(&adapter->sfp_task);
4200}
4201
4202/**
4203 * ixgbe_sfp_task - worker thread to find a missing module
4204 * @work: pointer to work_struct containing our data
4205 **/
4206static void ixgbe_sfp_task(struct work_struct *work)
4207{
4208 struct ixgbe_adapter *adapter = container_of(work,
4209 struct ixgbe_adapter,
4210 sfp_task);
4211 struct ixgbe_hw *hw = &adapter->hw;
4212
4213 if ((hw->phy.type == ixgbe_phy_nl) &&
4214 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4215 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4216 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 4217 goto reschedule;
4218 ret = hw->phy.ops.reset(hw);
4219 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 4220 dev_err(&adapter->pdev->dev, "failed to initialize "
4221 "because an unsupported SFP+ module type "
4222 "was detected.\n"
4223 "Reload the driver after installing a "
4224 "supported module.\n");
c4900be0
DS		 4225 unregister_netdev(adapter->netdev);
4226 } else {
4227 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
4228 hw->phy.sfp_type);
4229 }
4230 /* don't need this routine any more */
4231 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4232 }
4233 return;
4234reschedule:
4235 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4236 mod_timer(&adapter->sfp_timer,
4237 round_jiffies(jiffies + (2 * HZ)));
4238}
4239
9a799d71
AK		 4240/**
4241 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4242 * @adapter: board private structure to initialize
4243 *
4244 * ixgbe_sw_init initializes the Adapter private data structure.
4245 * Fields are initialized based on PCI device information and
4246 * OS network device settings (MTU size).
4247 **/
4248static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4249{
4250 struct ixgbe_hw *hw = &adapter->hw;
4251 struct pci_dev *pdev = adapter->pdev;
9a713e7c 4252 struct net_device *dev = adapter->netdev;
021230d4 4253 unsigned int rss;
7a6b6f51 4254#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4255 int j;
4256 struct tc_configuration *tc;
4257#endif
021230d4 4258
c44ade9e
JB		 4259 /* PCI config space info */
4260
4261 hw->vendor_id = pdev->vendor;
4262 hw->device_id = pdev->device;
4263 hw->revision_id = pdev->revision;
4264 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4265 hw->subsystem_device_id = pdev->subsystem_device;
4266
021230d4
AV		 4267 /* Set capability flags */
4268 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4269 adapter->ring_feature[RING_F_RSS].indices = rss;
4270 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 4271 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 4272 if (hw->mac.type == ixgbe_mac_82598EB) {
4273 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4274 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4275 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 4276 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 4277 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4278 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4279 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
9a713e7c
PW		 4280 if (dev->features & NETIF_F_NTUPLE) {
4281 /* Flow Director perfect filter enabled */
4282 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4283 adapter->atr_sample_rate = 0;
4284 spin_lock_init(&adapter->fdir_perfect_lock);
4285 } else {
4286 /* Flow Director hash filters enabled */
4287 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4288 adapter->atr_sample_rate = 20;
4289 }
c4cf55e5
PWJ		 4290 adapter->ring_feature[RING_F_FDIR].indices =
4291 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 4292 adapter->fdir_pballoc = 0;
eacd73f7 4293#ifdef IXGBE_FCOE
0d551589
YZ		 4294 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4295 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4296 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4297#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 4298 /* Default traffic class to use for FCoE */
4299 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
61a0f421 4300#endif
eacd73f7 4301#endif /* IXGBE_FCOE */
f8212f97 4302 }
2f90b865 4303
7a6b6f51 4304#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4305 /* Configure DCB traffic classes */
4306 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4307 tc = &adapter->dcb_cfg.tc_config[j];
4308 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4309 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4310 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4311 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4312 tc->dcb_pfc = pfc_disabled;
4313 }
4314 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4315 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4316 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 4317 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 4318 adapter->dcb_cfg.round_robin_enable = false;
4319 adapter->dcb_set_bitmap = 0x00;
4320 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4321 adapter->ring_feature[RING_F_DCB].indices);
4322
4323#endif
9a799d71
AK		 4324
4325 /* default flow control settings */
cd7664f6 4326 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4327 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 4328#ifdef CONFIG_DCB
4329 adapter->last_lfc_mode = hw->fc.current_mode;
4330#endif
2b9ade93
JB		 4331 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4332 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4333 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4334 hw->fc.send_xon = true;
71fd570b 4335 hw->fc.disable_fc_autoneg = false;
9a799d71 4336
30efa5a3 4337 /* enable itr by default in dynamic mode */
f7554a2b
NS		 4338 adapter->rx_itr_setting = 1;
4339 adapter->rx_eitr_param = 20000;
4340 adapter->tx_itr_setting = 1;
4341 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 4342
4343 /* set defaults for eitr in MegaBytes */
4344 adapter->eitr_low = 10;
4345 adapter->eitr_high = 20;
4346
4347 /* set default ring sizes */
4348 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4349 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4350
9a799d71 4351 /* initialize eeprom parameters */
c44ade9e 4352 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 4353 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4354 return -EIO;
4355 }
4356
021230d4 4357 /* enable rx csum by default */
9a799d71
AK		 4358 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4359
1a6c14a2
JB		 4360 /* get assigned NUMA node */
4361 adapter->node = dev_to_node(&pdev->dev);
4362
9a799d71
AK		 4363 set_bit(__IXGBE_DOWN, &adapter->state);
4364
4365 return 0;
4366}
4367
4368/**
4369 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4370 * @adapter: board private structure
3a581073 4371 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4372 *
4373 * Return 0 on success, negative on failure
4374 **/
4375int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 4376 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4377{
4378 struct pci_dev *pdev = adapter->pdev;
4379 int size;
4380
3a581073 4381 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4a0b9ca0 4382 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
1a6c14a2
JB		 4383 if (!tx_ring->tx_buffer_info)
4384 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 4385 if (!tx_ring->tx_buffer_info)
4386 goto err;
3a581073 4387 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 4388
4389 /* round up to nearest 4K */
12207e49 4390 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4391 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4392
3a581073
JB		 4393 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
4394 &tx_ring->dma);
e01c31a5
JB		 4395 if (!tx_ring->desc)
4396 goto err;
9a799d71 4397
3a581073
JB		 4398 tx_ring->next_to_use = 0;
4399 tx_ring->next_to_clean = 0;
4400 tx_ring->work_limit = tx_ring->count;
9a799d71 4401 return 0;
e01c31a5
JB		 4402
4403err:
4404 vfree(tx_ring->tx_buffer_info);
4405 tx_ring->tx_buffer_info = NULL;
4406 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4407 "descriptor ring\n");
4408 return -ENOMEM;
9a799d71
AK		 4409}
4410
69888674
AD		 4411/**
4412 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4413 * @adapter: board private structure
4414 *
4415 * If this function returns with an error, then it's possible one or
4416 * more of the rings is populated (while the rest are not). It is the
4417 * callers duty to clean those orphaned rings.
4418 *
4419 * Return 0 on success, negative on failure
4420 **/
4421static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4422{
4423 int i, err = 0;
4424
4425 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 4426 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
69888674
AD		 4427 if (!err)
4428 continue;
4429 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4430 break;
4431 }
4432
4433 return err;
4434}
4435
9a799d71
AK		 4436/**
4437 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4438 * @adapter: board private structure
3a581073 4439 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4440 *
4441 * Returns 0 on success, negative on failure
4442 **/
4443int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 4444 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4445{
4446 struct pci_dev *pdev = adapter->pdev;
021230d4 4447 int size;
9a799d71 4448
3a581073 4449 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
1a6c14a2
JB		 4450 rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4451 if (!rx_ring->rx_buffer_info)
4452 rx_ring->rx_buffer_info = vmalloc(size);
3a581073 4453 if (!rx_ring->rx_buffer_info) {
9a799d71 4454 DPRINTK(PROBE, ERR,
b4617240 4455 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 4456 goto alloc_failed;
9a799d71 4457 }
3a581073 4458 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 4459
9a799d71 4460 /* Round up to nearest 4K */
3a581073
JB		 4461 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4462 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4463
3a581073 4464 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 4465
3a581073 4466 if (!rx_ring->desc) {
9a799d71 4467 DPRINTK(PROBE, ERR,
b4617240 4468 "Memory allocation failed for the rx desc ring\n");
3a581073 4469 vfree(rx_ring->rx_buffer_info);
177db6ff 4470 goto alloc_failed;
9a799d71
AK		 4471 }
4472
3a581073
JB		 4473 rx_ring->next_to_clean = 0;
4474 rx_ring->next_to_use = 0;
9a799d71
AK		 4475
4476 return 0;
177db6ff
MC		 4477
4478alloc_failed:
177db6ff 4479 return -ENOMEM;
9a799d71
AK		 4480}
4481
69888674
AD		 4482/**
4483 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4484 * @adapter: board private structure
4485 *
4486 * If this function returns with an error, then it's possible one or
4487 * more of the rings is populated (while the rest are not). It is the
4488 * callers duty to clean those orphaned rings.
4489 *
4490 * Return 0 on success, negative on failure
4491 **/
4492
4493static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4494{
4495 int i, err = 0;
4496
4497 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 4498 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
69888674
AD		 4499 if (!err)
4500 continue;
4501 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4502 break;
4503 }
4504
4505 return err;
4506}
4507
9a799d71
AK		 4508/**
4509 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4510 * @adapter: board private structure
4511 * @tx_ring: Tx descriptor ring for a specific queue
4512 *
4513 * Free all transmit software resources
4514 **/
c431f97e
JB		 4515void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4516 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4517{
4518 struct pci_dev *pdev = adapter->pdev;
4519
4520 ixgbe_clean_tx_ring(adapter, tx_ring);
4521
4522 vfree(tx_ring->tx_buffer_info);
4523 tx_ring->tx_buffer_info = NULL;
4524
4525 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4526
4527 tx_ring->desc = NULL;
4528}
4529
4530/**
4531 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4532 * @adapter: board private structure
4533 *
4534 * Free all transmit software resources
4535 **/
4536static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4537{
4538 int i;
4539
4540 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0
PW		 4541 if (adapter->tx_ring[i]->desc)
4542 ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
9a799d71
AK		 4543}
4544
4545/**
b4617240 4546 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4547 * @adapter: board private structure
4548 * @rx_ring: ring to clean the resources from
4549 *
4550 * Free all receive software resources
4551 **/
c431f97e
JB		 4552void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4553 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4554{
4555 struct pci_dev *pdev = adapter->pdev;
4556
4557 ixgbe_clean_rx_ring(adapter, rx_ring);
4558
4559 vfree(rx_ring->rx_buffer_info);
4560 rx_ring->rx_buffer_info = NULL;
4561
4562 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4563
4564 rx_ring->desc = NULL;
4565}
4566
4567/**
4568 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4569 * @adapter: board private structure
4570 *
4571 * Free all receive software resources
4572 **/
4573static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4574{
4575 int i;
4576
4577 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 4578 if (adapter->rx_ring[i]->desc)
4579 ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
9a799d71
AK		 4580}
4581
9a799d71
AK		 4582/**
4583 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4584 * @netdev: network interface device structure
4585 * @new_mtu: new value for maximum frame size
4586 *
4587 * Returns 0 on success, negative on failure
4588 **/
4589static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4590{
4591 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4592 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4593
42c783c5
JB		 4594 /* MTU < 68 is an error and causes problems on some kernels */
4595 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 4596 return -EINVAL;
4597
021230d4 4598 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 4599 netdev->mtu, new_mtu);
021230d4 4600 /* must set new MTU before calling down or up */
9a799d71
AK		 4601 netdev->mtu = new_mtu;
4602
d4f80882
AV		 4603 if (netif_running(netdev))
4604 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4605
4606 return 0;
4607}
4608
4609/**
4610 * ixgbe_open - Called when a network interface is made active
4611 * @netdev: network interface device structure
4612 *
4613 * Returns 0 on success, negative value on failure
4614 *
4615 * The open entry point is called when a network interface is made
4616 * active by the system (IFF_UP). At this point all resources needed
4617 * for transmit and receive operations are allocated, the interrupt
4618 * handler is registered with the OS, the watchdog timer is started,
4619 * and the stack is notified that the interface is ready.
4620 **/
4621static int ixgbe_open(struct net_device *netdev)
4622{
4623 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4624 int err;
4bebfaa5
AK		 4625
4626 /* disallow open during test */
4627 if (test_bit(__IXGBE_TESTING, &adapter->state))
4628 return -EBUSY;
9a799d71 4629
54386467
JB		 4630 netif_carrier_off(netdev);
4631
9a799d71
AK		 4632 /* allocate transmit descriptors */
4633 err = ixgbe_setup_all_tx_resources(adapter);
4634 if (err)
4635 goto err_setup_tx;
4636
9a799d71
AK		 4637 /* allocate receive descriptors */
4638 err = ixgbe_setup_all_rx_resources(adapter);
4639 if (err)
4640 goto err_setup_rx;
4641
4642 ixgbe_configure(adapter);
4643
021230d4 4644 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4645 if (err)
4646 goto err_req_irq;
4647
9a799d71
AK		 4648 err = ixgbe_up_complete(adapter);
4649 if (err)
4650 goto err_up;
4651
d55b53ff
JK		 4652 netif_tx_start_all_queues(netdev);
4653
9a799d71
AK		 4654 return 0;
4655
4656err_up:
5eba3699 4657 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4658 ixgbe_free_irq(adapter);
4659err_req_irq:
9a799d71 4660err_setup_rx:
a20a1199 4661 ixgbe_free_all_rx_resources(adapter);
9a799d71 4662err_setup_tx:
a20a1199 4663 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 4664 ixgbe_reset(adapter);
4665
4666 return err;
4667}
4668
4669/**
4670 * ixgbe_close - Disables a network interface
4671 * @netdev: network interface device structure
4672 *
4673 * Returns 0, this is not allowed to fail
4674 *
4675 * The close entry point is called when an interface is de-activated
4676 * by the OS. The hardware is still under the drivers control, but
4677 * needs to be disabled. A global MAC reset is issued to stop the
4678 * hardware, and all transmit and receive resources are freed.
4679 **/
4680static int ixgbe_close(struct net_device *netdev)
4681{
4682 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4683
4684 ixgbe_down(adapter);
4685 ixgbe_free_irq(adapter);
4686
4687 ixgbe_free_all_tx_resources(adapter);
4688 ixgbe_free_all_rx_resources(adapter);
4689
5eba3699 4690 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4691
4692 return 0;
4693}
4694
b3c8b4ba
AD		 4695#ifdef CONFIG_PM
4696static int ixgbe_resume(struct pci_dev *pdev)
4697{
4698 struct net_device *netdev = pci_get_drvdata(pdev);
4699 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4700 u32 err;
4701
4702 pci_set_power_state(pdev, PCI_D0);
4703 pci_restore_state(pdev);
656ab817
DS		 4704 /*
4705 * pci_restore_state clears dev->state_saved so call
4706 * pci_save_state to restore it.
4707 */
4708 pci_save_state(pdev);
9ce77666 4709
4710 err = pci_enable_device_mem(pdev);
b3c8b4ba 4711 if (err) {
69888674 4712 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 4713 "suspend\n");
4714 return err;
4715 }
4716 pci_set_master(pdev);
4717
dd4d8ca6 4718 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 4719
4720 err = ixgbe_init_interrupt_scheme(adapter);
4721 if (err) {
4722 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4723 "device\n");
4724 return err;
4725 }
4726
b3c8b4ba
AD		 4727 ixgbe_reset(adapter);
4728
495dce12
WJP		 4729 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4730
b3c8b4ba
AD		 4731 if (netif_running(netdev)) {
4732 err = ixgbe_open(adapter->netdev);
4733 if (err)
4734 return err;
4735 }
4736
4737 netif_device_attach(netdev);
4738
4739 return 0;
4740}
b3c8b4ba 4741#endif /* CONFIG_PM */
9d8d05ae
RW		 4742
4743static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 4744{
4745 struct net_device *netdev = pci_get_drvdata(pdev);
4746 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 4747 struct ixgbe_hw *hw = &adapter->hw;
4748 u32 ctrl, fctrl;
4749 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4750#ifdef CONFIG_PM
4751 int retval = 0;
4752#endif
4753
4754 netif_device_detach(netdev);
4755
4756 if (netif_running(netdev)) {
4757 ixgbe_down(adapter);
4758 ixgbe_free_irq(adapter);
4759 ixgbe_free_all_tx_resources(adapter);
4760 ixgbe_free_all_rx_resources(adapter);
4761 }
7a921c93 4762 ixgbe_clear_interrupt_scheme(adapter);
b3c8b4ba
AD		 4763
4764#ifdef CONFIG_PM
4765 retval = pci_save_state(pdev);
4766 if (retval)
4767 return retval;
4df10466 4768
b3c8b4ba 4769#endif
e8e26350
PW		 4770 if (wufc) {
4771 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4772
e8e26350
PW		 4773 /* turn on all-multi mode if wake on multicast is enabled */
4774 if (wufc & IXGBE_WUFC_MC) {
4775 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4776 fctrl |= IXGBE_FCTRL_MPE;
4777 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4778 }
4779
4780 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4781 ctrl |= IXGBE_CTRL_GIO_DIS;
4782 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4783
4784 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4785 } else {
4786 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4787 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4788 }
4789
dd4d8ca6
DS		 4790 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4791 pci_wake_from_d3(pdev, true);
4792 else
4793 pci_wake_from_d3(pdev, false);
b3c8b4ba 4794
9d8d05ae
RW		 4795 *enable_wake = !!wufc;
4796
b3c8b4ba
AD		 4797 ixgbe_release_hw_control(adapter);
4798
4799 pci_disable_device(pdev);
4800
9d8d05ae
RW		 4801 return 0;
4802}
4803
4804#ifdef CONFIG_PM
4805static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4806{
4807 int retval;
4808 bool wake;
4809
4810 retval = __ixgbe_shutdown(pdev, &wake);
4811 if (retval)
4812 return retval;
4813
4814 if (wake) {
4815 pci_prepare_to_sleep(pdev);
4816 } else {
4817 pci_wake_from_d3(pdev, false);
4818 pci_set_power_state(pdev, PCI_D3hot);
4819 }
b3c8b4ba
AD		 4820
4821 return 0;
4822}
9d8d05ae 4823#endif /* CONFIG_PM */
b3c8b4ba
AD		 4824
4825static void ixgbe_shutdown(struct pci_dev *pdev)
4826{
9d8d05ae
RW		 4827 bool wake;
4828
4829 __ixgbe_shutdown(pdev, &wake);
4830
4831 if (system_state == SYSTEM_POWER_OFF) {
4832 pci_wake_from_d3(pdev, wake);
4833 pci_set_power_state(pdev, PCI_D3hot);
4834 }
b3c8b4ba
AD		 4835}
4836
9a799d71
AK		 4837/**
4838 * ixgbe_update_stats - Update the board statistics counters.
4839 * @adapter: board private structure
4840 **/
4841void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4842{
2d86f139 4843 struct net_device *netdev = adapter->netdev;
9a799d71 4844 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 4845 u64 total_mpc = 0;
4846 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
eb985f09 4847 u64 non_eop_descs = 0, restart_queue = 0;
9a799d71 4848
94b982b2 4849 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 4850 u64 rsc_count = 0;
94b982b2 4851 u64 rsc_flush = 0;
d51019a4
PW		 4852 for (i = 0; i < 16; i++)
4853 adapter->hw_rx_no_dma_resources +=
4854 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 4855 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 4856 rsc_count += adapter->rx_ring[i]->rsc_count;
4857 rsc_flush += adapter->rx_ring[i]->rsc_flush;
94b982b2
MC		 4858 }
4859 adapter->rsc_total_count = rsc_count;
4860 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 4861 }
4862
7ca3bc58
JB		 4863 /* gather some stats to the adapter struct that are per queue */
4864 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4865 restart_queue += adapter->tx_ring[i]->restart_queue;
eb985f09 4866 adapter->restart_queue = restart_queue;
7ca3bc58
JB		 4867
4868 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4869 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
eb985f09 4870 adapter->non_eop_descs = non_eop_descs;
7ca3bc58 4871
9a799d71 4872 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 4873 for (i = 0; i < 8; i++) {
4874 /* for packet buffers not used, the register should read 0 */
4875 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4876 missed_rx += mpc;
4877 adapter->stats.mpc[i] += mpc;
4878 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 4879 if (hw->mac.type == ixgbe_mac_82598EB)
4880 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 4881 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4882 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4883 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4884 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 4885 if (hw->mac.type == ixgbe_mac_82599EB) {
4886 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4887 IXGBE_PXONRXCNT(i));
4888 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4889 IXGBE_PXOFFRXCNT(i));
4890 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 4891 } else {
4892 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4893 IXGBE_PXONRXC(i));
4894 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4895 IXGBE_PXOFFRXC(i));
4896 }
2f90b865
AD		 4897 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4898 IXGBE_PXONTXC(i));
2f90b865 4899 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 4900 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 4901 }
4902 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4903 /* work around hardware counting issue */
4904 adapter->stats.gprc -= missed_rx;
4905
4906 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350 4907 if (hw->mac.type == ixgbe_mac_82599EB) {
aad71918 4908 u64 tmp;
e8e26350 4909 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
aad71918
BG		 4910 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4911 adapter->stats.gorc += (tmp << 32);
e8e26350 4912 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
aad71918
BG		 4913 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4914 adapter->stats.gotc += (tmp << 32);
e8e26350
PW		 4915 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4916 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4917 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4918 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
c4cf55e5
PWJ		 4919 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4920 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c
YZ		 4921#ifdef IXGBE_FCOE
4922 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4923 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4924 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4925 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4926 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4927 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4928#endif /* IXGBE_FCOE */
e8e26350
PW		 4929 } else {
4930 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4931 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4932 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4933 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4934 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4935 }
9a799d71
AK		 4936 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4937 adapter->stats.bprc += bprc;
4938 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 4939 if (hw->mac.type == ixgbe_mac_82598EB)
4940 adapter->stats.mprc -= bprc;
9a799d71
AK		 4941 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4942 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4943 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4944 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4945 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4946 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4947 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 4948 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 4949 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4950 adapter->stats.lxontxc += lxon;
4951 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4952 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 4953 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4954 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 4955 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4956 /*
4957 * 82598 errata - tx of flow control packets is included in tx counters
4958 */
4959 xon_off_tot = lxon + lxoff;
4960 adapter->stats.gptc -= xon_off_tot;
4961 adapter->stats.mptc -= xon_off_tot;
4962 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 4963 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4964 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4965 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 4966 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4967 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 4968 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 4969 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4970 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4971 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4972 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4973 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 4974 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4975
4976 /* Fill out the OS statistics structure */
2d86f139 4977 netdev->stats.multicast = adapter->stats.mprc;
9a799d71
AK		 4978
4979 /* Rx Errors */
2d86f139 4980 netdev->stats.rx_errors = adapter->stats.crcerrs +
b4617240 4981 adapter->stats.rlec;
2d86f139
AK		 4982 netdev->stats.rx_dropped = 0;
4983 netdev->stats.rx_length_errors = adapter->stats.rlec;
4984 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4985 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 4986}
4987
4988/**
4989 * ixgbe_watchdog - Timer Call-back
4990 * @data: pointer to adapter cast into an unsigned long
4991 **/
4992static void ixgbe_watchdog(unsigned long data)
4993{
4994 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 4995 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 4996 u64 eics = 0;
4997 int i;
cf8280ee 4998
fe49f04a
AD		 4999 /*
5000 * Do the watchdog outside of interrupt context due to the lovely
5001 * delays that some of the newer hardware requires
5002 */
22d5a71b 5003
fe49f04a
AD		 5004 if (test_bit(__IXGBE_DOWN, &adapter->state))
5005 goto watchdog_short_circuit;
22d5a71b 5006
fe49f04a
AD		 5007 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5008 /*
5009 * for legacy and MSI interrupts don't set any bits
5010 * that are enabled for EIAM, because this operation
5011 * would set *both* EIMS and EICS for any bit in EIAM
5012 */
5013 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5014 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5015 goto watchdog_reschedule;
5016 }
5017
5018 /* get one bit for every active tx/rx interrupt vector */
5019 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5020 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5021 if (qv->rxr_count || qv->txr_count)
5022 eics |= ((u64)1 << i);
cf8280ee 5023 }
9a799d71 5024
fe49f04a
AD		 5025 /* Cause software interrupt to ensure rx rings are cleaned */
5026 ixgbe_irq_rearm_queues(adapter, eics);
5027
5028watchdog_reschedule:
5029 /* Reset the timer */
5030 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5031
5032watchdog_short_circuit:
cf8280ee
JB		 5033 schedule_work(&adapter->watchdog_task);
5034}
5035
e8e26350
PW		 5036/**
5037 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5038 * @work: pointer to work_struct containing our data
5039 **/
5040static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5041{
5042 struct ixgbe_adapter *adapter = container_of(work,
5043 struct ixgbe_adapter,
5044 multispeed_fiber_task);
5045 struct ixgbe_hw *hw = &adapter->hw;
5046 u32 autoneg;
8620a103 5047 bool negotiation;
e8e26350
PW		 5048
5049 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 5050 autoneg = hw->phy.autoneg_advertised;
5051 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103 5052 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
1097cd17 5053 hw->mac.autotry_restart = false;
8620a103
MC		 5054 if (hw->mac.ops.setup_link)
5055 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 5056 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5057 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5058}
5059
5060/**
5061 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5062 * @work: pointer to work_struct containing our data
5063 **/
5064static void ixgbe_sfp_config_module_task(struct work_struct *work)
5065{
5066 struct ixgbe_adapter *adapter = container_of(work,
5067 struct ixgbe_adapter,
5068 sfp_config_module_task);
5069 struct ixgbe_hw *hw = &adapter->hw;
5070 u32 err;
5071
5072 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 5073
5074 /* Time for electrical oscillations to settle down */
5075 msleep(100);
e8e26350 5076 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5077
e8e26350 5078 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 5079 dev_err(&adapter->pdev->dev, "failed to initialize because "
5080 "an unsupported SFP+ module type was detected.\n"
5081 "Reload the driver after installing a supported "
5082 "module.\n");
63d6e1d8 5083 unregister_netdev(adapter->netdev);
e8e26350
PW		 5084 return;
5085 }
5086 hw->mac.ops.setup_sfp(hw);
5087
8d1c3c07 5088 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 5089 /* This will also work for DA Twinax connections */
5090 schedule_work(&adapter->multispeed_fiber_task);
5091 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5092}
5093
c4cf55e5
PWJ		 5094/**
5095 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5096 * @work: pointer to work_struct containing our data
5097 **/
5098static void ixgbe_fdir_reinit_task(struct work_struct *work)
5099{
5100 struct ixgbe_adapter *adapter = container_of(work,
5101 struct ixgbe_adapter,
5102 fdir_reinit_task);
5103 struct ixgbe_hw *hw = &adapter->hw;
5104 int i;
5105
5106 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5107 for (i = 0; i < adapter->num_tx_queues; i++)
5108 set_bit(__IXGBE_FDIR_INIT_DONE,
4a0b9ca0 5109 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5
PWJ		 5110 } else {
5111 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
d6dbee86 5112 "ignored adding FDIR ATR filters\n");
c4cf55e5
PWJ		 5113 }
5114 /* Done FDIR Re-initialization, enable transmits */
5115 netif_tx_start_all_queues(adapter->netdev);
5116}
5117
10eec955
JF		 5118static DEFINE_MUTEX(ixgbe_watchdog_lock);
5119
cf8280ee 5120/**
69888674
AD		 5121 * ixgbe_watchdog_task - worker thread to bring link up
5122 * @work: pointer to work_struct containing our data
cf8280ee
JB		 5123 **/
5124static void ixgbe_watchdog_task(struct work_struct *work)
5125{
5126 struct ixgbe_adapter *adapter = container_of(work,
5127 struct ixgbe_adapter,
5128 watchdog_task);
5129 struct net_device *netdev = adapter->netdev;
5130 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 5131 u32 link_speed;
5132 bool link_up;
bc59fcda
NS		 5133 int i;
5134 struct ixgbe_ring *tx_ring;
5135 int some_tx_pending = 0;
cf8280ee 5136
10eec955
JF		 5137 mutex_lock(&ixgbe_watchdog_lock);
5138
5139 link_up = adapter->link_up;
5140 link_speed = adapter->link_speed;
cf8280ee
JB		 5141
5142 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5143 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 5144 if (link_up) {
5145#ifdef CONFIG_DCB
5146 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5147 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 5148 hw->mac.ops.fc_enable(hw, i);
264857b8 5149 } else {
620fa036 5150 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5151 }
5152#else
620fa036 5153 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5154#endif
5155 }
5156
cf8280ee
JB		 5157 if (link_up ||
5158 time_after(jiffies, (adapter->link_check_timeout +
5159 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 5160 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 5161 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 5162 }
5163 adapter->link_up = link_up;
5164 adapter->link_speed = link_speed;
5165 }
9a799d71
AK		 5166
5167 if (link_up) {
5168 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 5169 bool flow_rx, flow_tx;
5170
5171 if (hw->mac.type == ixgbe_mac_82599EB) {
5172 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5173 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 5174 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5175 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 5176 } else {
5177 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5178 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 5179 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5180 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 5181 }
5182
a46e534b
JK		 5183 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
5184 "Flow Control: %s\n",
5185 netdev->name,
5186 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5187 "10 Gbps" :
5188 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5189 "1 Gbps" : "unknown speed")),
e8e26350
PW		 5190 ((flow_rx && flow_tx) ? "RX/TX" :
5191 (flow_rx ? "RX" :
5192 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 5193
5194 netif_carrier_on(netdev);
9a799d71
AK		 5195 } else {
5196 /* Force detection of hung controller */
5197 adapter->detect_tx_hung = true;
5198 }
5199 } else {
cf8280ee
JB		 5200 adapter->link_up = false;
5201 adapter->link_speed = 0;
9a799d71 5202 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 5203 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
5204 netdev->name);
9a799d71 5205 netif_carrier_off(netdev);
9a799d71
AK		 5206 }
5207 }
5208
bc59fcda
NS		 5209 if (!netif_carrier_ok(netdev)) {
5210 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 5211 tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5212 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5213 some_tx_pending = 1;
5214 break;
5215 }
5216 }
5217
5218 if (some_tx_pending) {
5219 /* We've lost link, so the controller stops DMA,
5220 * but we've got queued Tx work that's never going
5221 * to get done, so reset controller to flush Tx.
5222 * (Do the reset outside of interrupt context).
5223 */
5224 schedule_work(&adapter->reset_task);
5225 }
5226 }
5227
9a799d71 5228 ixgbe_update_stats(adapter);
10eec955 5229 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 5230}
5231
9a799d71 5232static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 5233 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5234 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 5235{
5236 struct ixgbe_adv_tx_context_desc *context_desc;
5237 unsigned int i;
5238 int err;
5239 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 5240 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5241 u32 mss_l4len_idx, l4len;
9a799d71
AK		 5242
5243 if (skb_is_gso(skb)) {
5244 if (skb_header_cloned(skb)) {
5245 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5246 if (err)
5247 return err;
5248 }
5249 l4len = tcp_hdrlen(skb);
5250 *hdr_len += l4len;
5251
8327d000 5252 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 5253 struct iphdr *iph = ip_hdr(skb);
5254 iph->tot_len = 0;
5255 iph->check = 0;
5256 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 5257 iph->daddr, 0,
5258 IPPROTO_TCP,
5259 0);
8e1e8a47 5260 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 5261 ipv6_hdr(skb)->payload_len = 0;
5262 tcp_hdr(skb)->check =
5263 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 5264 &ipv6_hdr(skb)->daddr,
5265 0, IPPROTO_TCP, 0);
9a799d71
AK		 5266 }
5267
5268 i = tx_ring->next_to_use;
5269
5270 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5271 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5272
5273 /* VLAN MACLEN IPLEN */
5274 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5275 vlan_macip_lens |=
5276 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5277 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 5278 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5279 *hdr_len += skb_network_offset(skb);
5280 vlan_macip_lens |=
5281 (skb_transport_header(skb) - skb_network_header(skb));
5282 *hdr_len +=
5283 (skb_transport_header(skb) - skb_network_header(skb));
5284 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5285 context_desc->seqnum_seed = 0;
5286
5287 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 5288 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 5289 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 5290
8327d000 5291 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 5292 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5293 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5294 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5295
5296 /* MSS L4LEN IDX */
9f8cdf4f 5297 mss_l4len_idx =
9a799d71
AK		 5298 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5299 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 5300 /* use index 1 for TSO */
5301 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5302 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5303
5304 tx_buffer_info->time_stamp = jiffies;
5305 tx_buffer_info->next_to_watch = i;
5306
5307 i++;
5308 if (i == tx_ring->count)
5309 i = 0;
5310 tx_ring->next_to_use = i;
5311
5312 return true;
5313 }
5314 return false;
5315}
5316
5317static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 5318 struct ixgbe_ring *tx_ring,
5319 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 5320{
5321 struct ixgbe_adv_tx_context_desc *context_desc;
5322 unsigned int i;
5323 struct ixgbe_tx_buffer *tx_buffer_info;
5324 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5325
5326 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5327 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5328 i = tx_ring->next_to_use;
5329 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5330 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5331
5332 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5333 vlan_macip_lens |=
5334 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5335 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 5336 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5337 if (skb->ip_summed == CHECKSUM_PARTIAL)
5338 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 5339 skb_network_header(skb));
9a799d71
AK		 5340
5341 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5342 context_desc->seqnum_seed = 0;
5343
5344 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 5345 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 5346
5347 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ca553980
GS		 5348 __be16 protocol;
5349
5350 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5351 const struct vlan_ethhdr *vhdr =
5352 (const struct vlan_ethhdr *)skb->data;
5353
5354 protocol = vhdr->h_vlan_encapsulated_proto;
5355 } else {
5356 protocol = skb->protocol;
5357 }
5358
5359 switch (protocol) {
09640e63 5360 case cpu_to_be16(ETH_P_IP):
9a799d71 5361 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 5362 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5363 type_tucmd_mlhl |=
b4617240 5364 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5365 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5366 type_tucmd_mlhl |=
5367 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5368 break;
09640e63 5369 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 5370 /* XXX what about other V6 headers?? */
5371 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5372 type_tucmd_mlhl |=
b4617240 5373 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5374 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5375 type_tucmd_mlhl |=
5376 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5377 break;
41825d71
AK		 5378 default:
5379 if (unlikely(net_ratelimit())) {
5380 DPRINTK(PROBE, WARNING,
5381 "partial checksum but proto=%x!\n",
5382 skb->protocol);
5383 }
5384 break;
5385 }
9a799d71
AK		 5386 }
5387
5388 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 5389 /* use index zero for tx checksum offload */
9a799d71
AK		 5390 context_desc->mss_l4len_idx = 0;
5391
5392 tx_buffer_info->time_stamp = jiffies;
5393 tx_buffer_info->next_to_watch = i;
9f8cdf4f 5394
9a799d71
AK		 5395 i++;
5396 if (i == tx_ring->count)
5397 i = 0;
5398 tx_ring->next_to_use = i;
5399
5400 return true;
5401 }
9f8cdf4f 5402
9a799d71
AK		 5403 return false;
5404}
5405
5406static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 5407 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 5408 struct sk_buff *skb, u32 tx_flags,
5409 unsigned int first)
9a799d71 5410{
e5a43549 5411 struct pci_dev *pdev = adapter->pdev;
9a799d71 5412 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 5413 unsigned int len;
5414 unsigned int total = skb->len;
9a799d71
AK		 5415 unsigned int offset = 0, size, count = 0, i;
5416 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5417 unsigned int f;
9a799d71
AK		 5418
5419 i = tx_ring->next_to_use;
5420
eacd73f7
YZ		 5421 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5422 /* excluding fcoe_crc_eof for FCoE */
5423 total -= sizeof(struct fcoe_crc_eof);
5424
5425 len = min(skb_headlen(skb), total);
9a799d71
AK		 5426 while (len) {
5427 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5428 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5429
5430 tx_buffer_info->length = size;
e5a43549
AD		 5431 tx_buffer_info->mapped_as_page = false;
5432 tx_buffer_info->dma = pci_map_single(pdev,
5433 skb->data + offset,
5434 size, PCI_DMA_TODEVICE);
5435 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5436 goto dma_error;
9a799d71
AK		 5437 tx_buffer_info->time_stamp = jiffies;
5438 tx_buffer_info->next_to_watch = i;
5439
5440 len -= size;
eacd73f7 5441 total -= size;
9a799d71
AK		 5442 offset += size;
5443 count++;
44df32c5
AD		 5444
5445 if (len) {
5446 i++;
5447 if (i == tx_ring->count)
5448 i = 0;
5449 }
9a799d71
AK		 5450 }
5451
5452 for (f = 0; f < nr_frags; f++) {
5453 struct skb_frag_struct *frag;
5454
5455 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 5456 len = min((unsigned int)frag->size, total);
e5a43549 5457 offset = frag->page_offset;
9a799d71
AK		 5458
5459 while (len) {
44df32c5
AD		 5460 i++;
5461 if (i == tx_ring->count)
5462 i = 0;
5463
9a799d71
AK		 5464 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5465 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5466
5467 tx_buffer_info->length = size;
e5a43549
AD		 5468 tx_buffer_info->dma = pci_map_page(adapter->pdev,
5469 frag->page,
5470 offset, size,
5471 PCI_DMA_TODEVICE);
5472 tx_buffer_info->mapped_as_page = true;
5473 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5474 goto dma_error;
9a799d71
AK		 5475 tx_buffer_info->time_stamp = jiffies;
5476 tx_buffer_info->next_to_watch = i;
5477
5478 len -= size;
eacd73f7 5479 total -= size;
9a799d71
AK		 5480 offset += size;
5481 count++;
9a799d71 5482 }
eacd73f7
YZ		 5483 if (total == 0)
5484 break;
9a799d71 5485 }
44df32c5 5486
9a799d71
AK		 5487 tx_ring->tx_buffer_info[i].skb = skb;
5488 tx_ring->tx_buffer_info[first].next_to_watch = i;
5489
e5a43549
AD		 5490 return count;
5491
5492dma_error:
5493 dev_err(&pdev->dev, "TX DMA map failed\n");
5494
5495 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5496 tx_buffer_info->dma = 0;
5497 tx_buffer_info->time_stamp = 0;
5498 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 5499 if (count)
5500 count--;
e5a43549
AD		 5501
5502 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f
RK		 5503 while (count--) {
5504 if (i==0)
e5a43549 5505 i += tx_ring->count;
c1fa347f 5506 i--;
e5a43549
AD		 5507 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5508 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5509 }
5510
e44d38e1 5511 return 0;
9a799d71
AK		 5512}
5513
5514static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 5515 struct ixgbe_ring *tx_ring,
5516 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 5517{
5518 union ixgbe_adv_tx_desc *tx_desc = NULL;
5519 struct ixgbe_tx_buffer *tx_buffer_info;
5520 u32 olinfo_status = 0, cmd_type_len = 0;
5521 unsigned int i;
5522 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5523
5524 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5525
5526 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5527
5528 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5529 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5530
5531 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5532 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5533
5534 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5535 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5536
4eeae6fd
PW		 5537 /* use index 1 context for tso */
5538 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5539 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5540 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 5541 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 5542
5543 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5544 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5545 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5546
eacd73f7
YZ		 5547 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5548 olinfo_status |= IXGBE_ADVTXD_CC;
5549 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5550 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5551 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5552 }
5553
9a799d71
AK		 5554 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5555
5556 i = tx_ring->next_to_use;
5557 while (count--) {
5558 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5559 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5560 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5561 tx_desc->read.cmd_type_len =
b4617240 5562 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 5563 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 5564 i++;
5565 if (i == tx_ring->count)
5566 i = 0;
5567 }
5568
5569 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5570
5571 /*
5572 * Force memory writes to complete before letting h/w
5573 * know there are new descriptors to fetch. (Only
5574 * applicable for weak-ordered memory model archs,
5575 * such as IA-64).
5576 */
5577 wmb();
5578
5579 tx_ring->next_to_use = i;
5580 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5581}
5582
c4cf55e5
PWJ		 5583static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5584 int queue, u32 tx_flags)
5585{
5586 /* Right now, we support IPv4 only */
5587 struct ixgbe_atr_input atr_input;
5588 struct tcphdr *th;
c4cf55e5
PWJ		 5589 struct iphdr *iph = ip_hdr(skb);
5590 struct ethhdr *eth = (struct ethhdr *)skb->data;
5591 u16 vlan_id, src_port, dst_port, flex_bytes;
5592 u32 src_ipv4_addr, dst_ipv4_addr;
5593 u8 l4type = 0;
5594
5595 /* check if we're UDP or TCP */
5596 if (iph->protocol == IPPROTO_TCP) {
5597 th = tcp_hdr(skb);
5598 src_port = th->source;
5599 dst_port = th->dest;
5600 l4type |= IXGBE_ATR_L4TYPE_TCP;
5601 /* l4type IPv4 type is 0, no need to assign */
c4cf55e5
PWJ		 5602 } else {
5603 /* Unsupported L4 header, just bail here */
5604 return;
5605 }
5606
5607 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5608
5609 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5610 IXGBE_TX_FLAGS_VLAN_SHIFT;
5611 src_ipv4_addr = iph->saddr;
5612 dst_ipv4_addr = iph->daddr;
5613 flex_bytes = eth->h_proto;
5614
5615 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5616 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5617 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5618 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5619 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5620 /* src and dst are inverted, think how the receiver sees them */
5621 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5622 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5623
5624 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5625 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5626}
5627
e092be60 5628static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5629 struct ixgbe_ring *tx_ring, int size)
e092be60 5630{
30eba97a 5631 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5632 /* Herbert's original patch had:
5633 * smp_mb__after_netif_stop_queue();
5634 * but since that doesn't exist yet, just open code it. */
5635 smp_mb();
5636
5637 /* We need to check again in a case another CPU has just
5638 * made room available. */
5639 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5640 return -EBUSY;
5641
5642 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 5643 netif_start_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 5644 ++tx_ring->restart_queue;
e092be60
AV		 5645 return 0;
5646}
5647
5648static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5649 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 5650{
5651 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5652 return 0;
5653 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5654}
5655
09a3b1f8
SH		 5656static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5657{
5658 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 5659 int txq = smp_processor_id();
09a3b1f8 5660
fdd3d631
KK		 5661 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
5662 while (unlikely(txq >= dev->real_num_tx_queues))
5663 txq -= dev->real_num_tx_queues;
5f715823 5664 return txq;
fdd3d631 5665 }
c4cf55e5 5666
5f715823
YZ		 5667#ifdef IXGBE_FCOE
5668 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
ca77cd59
RL		 5669 ((skb->protocol == htons(ETH_P_FCOE)) ||
5670 (skb->protocol == htons(ETH_P_FIP)))) {
5f715823
YZ		 5671 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5672 txq += adapter->ring_feature[RING_F_FCOE].mask;
5673 return txq;
5674 }
5675#endif
2ea186ae
JF		 5676 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5677 if (skb->priority == TC_PRIO_CONTROL)
5678 txq = adapter->ring_feature[RING_F_DCB].indices-1;
5679 else
5680 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
5681 >> 13;
5682 return txq;
5683 }
09a3b1f8
SH		 5684
5685 return skb_tx_hash(dev, skb);
5686}
5687
3b29a56d
SH		 5688static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5689 struct net_device *netdev)
9a799d71
AK		 5690{
5691 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5692 struct ixgbe_ring *tx_ring;
60d51134 5693 struct netdev_queue *txq;
9a799d71
AK		 5694 unsigned int first;
5695 unsigned int tx_flags = 0;
30eba97a 5696 u8 hdr_len = 0;
5f715823 5697 int tso;
9a799d71
AK		 5698 int count = 0;
5699 unsigned int f;
9f8cdf4f 5700
9f8cdf4f
JB		 5701 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5702 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 5703 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5704 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5f715823 5705 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
2f90b865
AD		 5706 }
5707 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5708 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5709 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2ea186ae
JF		 5710 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
5711 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5712 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 5713 }
eacd73f7 5714
4a0b9ca0 5715 tx_ring = adapter->tx_ring[skb->queue_mapping];
60127865 5716
09ad1cc0 5717#ifdef IXGBE_FCOE
ca77cd59 5718 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
61a0f421 5719#ifdef CONFIG_IXGBE_DCB
ca77cd59
RL		 5720 /* for FCoE with DCB, we force the priority to what
5721 * was specified by the switch */
5722 if ((skb->protocol == htons(ETH_P_FCOE)) ||
5723 (skb->protocol == htons(ETH_P_FIP))) {
5724 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
5725 << IXGBE_TX_FLAGS_VLAN_SHIFT);
5726 tx_flags |= ((adapter->fcoe.up << 13)
5727 << IXGBE_TX_FLAGS_VLAN_SHIFT);
5728 }
09ad1cc0 5729#endif
ca77cd59
RL		 5730 /* flag for FCoE offloads */
5731 if (skb->protocol == htons(ETH_P_FCOE))
5732 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0 5733 }
ca77cd59
RL		 5734#endif
5735
eacd73f7 5736 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 5737 if (skb_is_gso(skb) ||
5738 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 5739 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5740 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 5741 count++;
5742
9f8cdf4f
JB		 5743 count += TXD_USE_COUNT(skb_headlen(skb));
5744 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 5745 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5746
e092be60 5747 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 5748 adapter->tx_busy++;
9a799d71
AK		 5749 return NETDEV_TX_BUSY;
5750 }
9a799d71 5751
9a799d71 5752 first = tx_ring->next_to_use;
eacd73f7
YZ		 5753 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5754#ifdef IXGBE_FCOE
5755 /* setup tx offload for FCoE */
5756 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5757 if (tso < 0) {
5758 dev_kfree_skb_any(skb);
5759 return NETDEV_TX_OK;
5760 }
5761 if (tso)
5762 tx_flags |= IXGBE_TX_FLAGS_FSO;
5763#endif /* IXGBE_FCOE */
5764 } else {
5765 if (skb->protocol == htons(ETH_P_IP))
5766 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5767 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5768 if (tso < 0) {
5769 dev_kfree_skb_any(skb);
5770 return NETDEV_TX_OK;
5771 }
9a799d71 5772
eacd73f7
YZ		 5773 if (tso)
5774 tx_flags |= IXGBE_TX_FLAGS_TSO;
5775 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5776 (skb->ip_summed == CHECKSUM_PARTIAL))
5777 tx_flags |= IXGBE_TX_FLAGS_CSUM;
5778 }
9a799d71 5779
eacd73f7 5780 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 5781 if (count) {
c4cf55e5
PWJ		 5782 /* add the ATR filter if ATR is on */
5783 if (tx_ring->atr_sample_rate) {
5784 ++tx_ring->atr_count;
5785 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5786 test_bit(__IXGBE_FDIR_INIT_DONE,
5787 &tx_ring->reinit_state)) {
5788 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5789 tx_flags);
5790 tx_ring->atr_count = 0;
5791 }
5792 }
60d51134
ED		 5793 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
5794 txq->tx_bytes += skb->len;
5795 txq->tx_packets++;
44df32c5
AD		 5796 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5797 hdr_len);
44df32c5 5798 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 5799
44df32c5
AD		 5800 } else {
5801 dev_kfree_skb_any(skb);
5802 tx_ring->tx_buffer_info[first].time_stamp = 0;
5803 tx_ring->next_to_use = first;
5804 }
9a799d71
AK		 5805
5806 return NETDEV_TX_OK;
5807}
5808
9a799d71
AK		 5809/**
5810 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5811 * @netdev: network interface device structure
5812 * @p: pointer to an address structure
5813 *
5814 * Returns 0 on success, negative on failure
5815 **/
5816static int ixgbe_set_mac(struct net_device *netdev, void *p)
5817{
5818 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 5819 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5820 struct sockaddr *addr = p;
5821
5822 if (!is_valid_ether_addr(addr->sa_data))
5823 return -EADDRNOTAVAIL;
5824
5825 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 5826 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 5827
1cdd1ec8
GR		 5828 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
5829 IXGBE_RAH_AV);
9a799d71
AK		 5830
5831 return 0;
5832}
5833
6b73e10d
BH		 5834static int
5835ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5836{
5837 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5838 struct ixgbe_hw *hw = &adapter->hw;
5839 u16 value;
5840 int rc;
5841
5842 if (prtad != hw->phy.mdio.prtad)
5843 return -EINVAL;
5844 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5845 if (!rc)
5846 rc = value;
5847 return rc;
5848}
5849
5850static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5851 u16 addr, u16 value)
5852{
5853 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5854 struct ixgbe_hw *hw = &adapter->hw;
5855
5856 if (prtad != hw->phy.mdio.prtad)
5857 return -EINVAL;
5858 return hw->phy.ops.write_reg(hw, addr, devad, value);
5859}
5860
5861static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5862{
5863 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5864
5865 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5866}
5867
0365e6e4
PW		 5868/**
5869 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 5870 * netdev->dev_addrs
0365e6e4
PW		 5871 * @netdev: network interface device structure
5872 *
5873 * Returns non-zero on failure
5874 **/
5875static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5876{
5877 int err = 0;
5878 struct ixgbe_adapter *adapter = netdev_priv(dev);
5879 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5880
5881 if (is_valid_ether_addr(mac->san_addr)) {
5882 rtnl_lock();
5883 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5884 rtnl_unlock();
5885 }
5886 return err;
5887}
5888
5889/**
5890 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 5891 * netdev->dev_addrs
0365e6e4
PW		 5892 * @netdev: network interface device structure
5893 *
5894 * Returns non-zero on failure
5895 **/
5896static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5897{
5898 int err = 0;
5899 struct ixgbe_adapter *adapter = netdev_priv(dev);
5900 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5901
5902 if (is_valid_ether_addr(mac->san_addr)) {
5903 rtnl_lock();
5904 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5905 rtnl_unlock();
5906 }
5907 return err;
5908}
5909
9a799d71
AK		 5910#ifdef CONFIG_NET_POLL_CONTROLLER
5911/*
5912 * Polling 'interrupt' - used by things like netconsole to send skbs
5913 * without having to re-enable interrupts. It's not called while
5914 * the interrupt routine is executing.
5915 */
5916static void ixgbe_netpoll(struct net_device *netdev)
5917{
5918 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 5919 int i;
9a799d71 5920
1a647bd2
AD		 5921 /* if interface is down do nothing */
5922 if (test_bit(__IXGBE_DOWN, &adapter->state))
5923 return;
5924
9a799d71 5925 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 5926 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5927 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5928 for (i = 0; i < num_q_vectors; i++) {
5929 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5930 ixgbe_msix_clean_many(0, q_vector);
5931 }
5932 } else {
5933 ixgbe_intr(adapter->pdev->irq, netdev);
5934 }
9a799d71 5935 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 5936}
5937#endif
5938
0edc3527
SH		 5939static const struct net_device_ops ixgbe_netdev_ops = {
5940 .ndo_open = ixgbe_open,
5941 .ndo_stop = ixgbe_close,
00829823 5942 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 5943 .ndo_select_queue = ixgbe_select_queue,
e90d400c 5944 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 5945 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5946 .ndo_validate_addr = eth_validate_addr,
5947 .ndo_set_mac_address = ixgbe_set_mac,
5948 .ndo_change_mtu = ixgbe_change_mtu,
5949 .ndo_tx_timeout = ixgbe_tx_timeout,
5950 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5951 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5952 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 5953 .ndo_do_ioctl = ixgbe_ioctl,
0edc3527
SH		 5954#ifdef CONFIG_NET_POLL_CONTROLLER
5955 .ndo_poll_controller = ixgbe_netpoll,
5956#endif
332d4a7d
YZ		 5957#ifdef IXGBE_FCOE
5958 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5959 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 5960 .ndo_fcoe_enable = ixgbe_fcoe_enable,
5961 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 5962 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 5963#endif /* IXGBE_FCOE */
0edc3527
SH		 5964};
5965
1cdd1ec8
GR		 5966static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
5967 const struct ixgbe_info *ii)
5968{
5969#ifdef CONFIG_PCI_IOV
5970 struct ixgbe_hw *hw = &adapter->hw;
5971 int err;
5972
5973 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
5974 return;
5975
5976 /* The 82599 supports up to 64 VFs per physical function
5977 * but this implementation limits allocation to 63 so that
5978 * basic networking resources are still available to the
5979 * physical function
5980 */
5981 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
5982 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
5983 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
5984 if (err) {
5985 DPRINTK(PROBE, ERR,
5986 "Failed to enable PCI sriov: %d\n", err);
5987 goto err_novfs;
5988 }
5989 /* If call to enable VFs succeeded then allocate memory
5990 * for per VF control structures.
5991 */
5992 adapter->vfinfo =
5993 kcalloc(adapter->num_vfs,
5994 sizeof(struct vf_data_storage), GFP_KERNEL);
5995 if (adapter->vfinfo) {
5996 /* Now that we're sure SR-IOV is enabled
5997 * and memory allocated set up the mailbox parameters
5998 */
5999 ixgbe_init_mbx_params_pf(hw);
6000 memcpy(&hw->mbx.ops, ii->mbx_ops,
6001 sizeof(hw->mbx.ops));
6002
6003 /* Disable RSC when in SR-IOV mode */
6004 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6005 IXGBE_FLAG2_RSC_ENABLED);
6006 return;
6007 }
6008
6009 /* Oh oh */
6010 DPRINTK(PROBE, ERR,
6011 "Unable to allocate memory for VF "
6012 "Data Storage - SRIOV disabled\n");
6013 pci_disable_sriov(adapter->pdev);
6014
6015err_novfs:
6016 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6017 adapter->num_vfs = 0;
6018#endif /* CONFIG_PCI_IOV */
6019}
6020
9a799d71
AK		 6021/**
6022 * ixgbe_probe - Device Initialization Routine
6023 * @pdev: PCI device information struct
6024 * @ent: entry in ixgbe_pci_tbl
6025 *
6026 * Returns 0 on success, negative on failure
6027 *
6028 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6029 * The OS initialization, configuring of the adapter private structure,
6030 * and a hardware reset occur.
6031 **/
6032static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 6033 const struct pci_device_id *ent)
9a799d71
AK		 6034{
6035 struct net_device *netdev;
6036 struct ixgbe_adapter *adapter = NULL;
6037 struct ixgbe_hw *hw;
6038 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 6039 static int cards_found;
6040 int i, err, pci_using_dac;
c85a2618 6041 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 6042#ifdef IXGBE_FCOE
6043 u16 device_caps;
6044#endif
c44ade9e 6045 u32 part_num, eec;
9a799d71 6046
9ce77666 6047 err = pci_enable_device_mem(pdev);
9a799d71
AK		 6048 if (err)
6049 return err;
6050
6a35528a
YH		 6051 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
6052 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
9a799d71
AK		 6053 pci_using_dac = 1;
6054 } else {
284901a9 6055 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 6056 if (err) {
284901a9 6057 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 6058 if (err) {
b4617240
PW		 6059 dev_err(&pdev->dev, "No usable DMA "
6060 "configuration, aborting\n");
9a799d71
AK		 6061 goto err_dma;
6062 }
6063 }
6064 pci_using_dac = 0;
6065 }
6066
9ce77666 6067 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6068 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 6069 if (err) {
9ce77666 6070 dev_err(&pdev->dev,
6071 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 6072 goto err_pci_reg;
6073 }
6074
19d5afd4 6075 pci_enable_pcie_error_reporting(pdev);
6fabd715 6076
9a799d71 6077 pci_set_master(pdev);
fb3b27bc 6078 pci_save_state(pdev);
9a799d71 6079
c85a2618
JF		 6080 if (ii->mac == ixgbe_mac_82598EB)
6081 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6082 else
6083 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6084
6085 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6086#ifdef IXGBE_FCOE
6087 indices += min_t(unsigned int, num_possible_cpus(),
6088 IXGBE_MAX_FCOE_INDICES);
6089#endif
c85a2618 6090 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 6091 if (!netdev) {
6092 err = -ENOMEM;
6093 goto err_alloc_etherdev;
6094 }
6095
9a799d71
AK		 6096 SET_NETDEV_DEV(netdev, &pdev->dev);
6097
6098 pci_set_drvdata(pdev, netdev);
6099 adapter = netdev_priv(netdev);
6100
6101 adapter->netdev = netdev;
6102 adapter->pdev = pdev;
6103 hw = &adapter->hw;
6104 hw->back = adapter;
6105 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6106
05857980
JK		 6107 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6108 pci_resource_len(pdev, 0));
9a799d71
AK		 6109 if (!hw->hw_addr) {
6110 err = -EIO;
6111 goto err_ioremap;
6112 }
6113
6114 for (i = 1; i <= 5; i++) {
6115 if (pci_resource_len(pdev, i) == 0)
6116 continue;
6117 }
6118
0edc3527 6119 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 6120 ixgbe_set_ethtool_ops(netdev);
9a799d71 6121 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 6122 strcpy(netdev->name, pci_name(pdev));
6123
9a799d71
AK		 6124 adapter->bd_number = cards_found;
6125
9a799d71
AK		 6126 /* Setup hw api */
6127 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 6128 hw->mac.type = ii->mac;
9a799d71 6129
c44ade9e
JB		 6130 /* EEPROM */
6131 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6132 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6133 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6134 if (!(eec & (1 << 8)))
6135 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6136
6137 /* PHY */
6138 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 6139 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 6140 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6141 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6142 hw->phy.mdio.mmds = 0;
6143 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6144 hw->phy.mdio.dev = netdev;
6145 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6146 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 6147
6148 /* set up this timer and work struct before calling get_invariants
6149 * which might start the timer
6150 */
6151 init_timer(&adapter->sfp_timer);
6152 adapter->sfp_timer.function = &ixgbe_sfp_timer;
6153 adapter->sfp_timer.data = (unsigned long) adapter;
6154
6155 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 6156
e8e26350
PW		 6157 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6158 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6159
6160 /* a new SFP+ module arrival, called from GPI SDP2 context */
6161 INIT_WORK(&adapter->sfp_config_module_task,
6162 ixgbe_sfp_config_module_task);
6163
8ca783ab 6164 ii->get_invariants(hw);
9a799d71
AK		 6165
6166 /* setup the private structure */
6167 err = ixgbe_sw_init(adapter);
6168 if (err)
6169 goto err_sw_init;
6170
e86bff0e
DS		 6171 /* Make it possible the adapter to be woken up via WOL */
6172 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6173 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6174
bf069c97
DS		 6175 /*
6176 * If there is a fan on this device and it has failed log the
6177 * failure.
6178 */
6179 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6180 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6181 if (esdp & IXGBE_ESDP_SDP1)
6182 DPRINTK(PROBE, CRIT,
6183 "Fan has stopped, replace the adapter\n");
6184 }
6185
c44ade9e
JB		 6186 /* reset_hw fills in the perm_addr as well */
6187 err = hw->mac.ops.reset_hw(hw);
8ca783ab
DS		 6188 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6189 hw->mac.type == ixgbe_mac_82598EB) {
6190 /*
6191 * Start a kernel thread to watch for a module to arrive.
6192 * Only do this for 82598, since 82599 will generate
6193 * interrupts on module arrival.
6194 */
6195 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6196 mod_timer(&adapter->sfp_timer,
6197 round_jiffies(jiffies + (2 * HZ)));
6198 err = 0;
6199 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 6200 dev_err(&adapter->pdev->dev, "failed to initialize because "
6201 "an unsupported SFP+ module type was detected.\n"
6202 "Reload the driver after installing a supported "
6203 "module.\n");
04f165ef
PW		 6204 goto err_sw_init;
6205 } else if (err) {
c44ade9e
JB		 6206 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
6207 goto err_sw_init;
6208 }
6209
1cdd1ec8
GR		 6210 ixgbe_probe_vf(adapter, ii);
6211
9a799d71 6212 netdev->features = NETIF_F_SG |
b4617240
PW		 6213 NETIF_F_IP_CSUM |
6214 NETIF_F_HW_VLAN_TX |
6215 NETIF_F_HW_VLAN_RX |
6216 NETIF_F_HW_VLAN_FILTER;
9a799d71 6217
e9990a9c 6218 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 6219 netdev->features |= NETIF_F_TSO;
9a799d71 6220 netdev->features |= NETIF_F_TSO6;
78b6f4ce 6221 netdev->features |= NETIF_F_GRO;
ad31c402 6222
45a5ead0
JB		 6223 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6224 netdev->features |= NETIF_F_SCTP_CSUM;
6225
ad31c402
JK		 6226 netdev->vlan_features |= NETIF_F_TSO;
6227 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 6228 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 6229 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 6230 netdev->vlan_features |= NETIF_F_SG;
6231
1cdd1ec8
GR		 6232 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6233 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6234 IXGBE_FLAG_DCB_ENABLED);
2f90b865
AD		 6235 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6236 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6237
7a6b6f51 6238#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 6239 netdev->dcbnl_ops = &dcbnl_ops;
6240#endif
6241
eacd73f7 6242#ifdef IXGBE_FCOE
0d551589 6243 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 6244 if (hw->mac.ops.get_device_caps) {
6245 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 6246 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6247 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 6248 }
6249 }
6250#endif /* IXGBE_FCOE */
9a799d71
AK		 6251 if (pci_using_dac)
6252 netdev->features |= NETIF_F_HIGHDMA;
6253
0c19d6af 6254 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 6255 netdev->features |= NETIF_F_LRO;
6256
9a799d71 6257 /* make sure the EEPROM is good */
c44ade9e 6258 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 6259 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
6260 err = -EIO;
6261 goto err_eeprom;
6262 }
6263
6264 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6265 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6266
c44ade9e
JB		 6267 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6268 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 6269 err = -EIO;
6270 goto err_eeprom;
6271 }
6272
61fac744
PW		 6273 /* power down the optics */
6274 if (hw->phy.multispeed_fiber)
6275 hw->mac.ops.disable_tx_laser(hw);
6276
9a799d71
AK		 6277 init_timer(&adapter->watchdog_timer);
6278 adapter->watchdog_timer.function = &ixgbe_watchdog;
6279 adapter->watchdog_timer.data = (unsigned long)adapter;
6280
6281 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 6282 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 6283
021230d4
AV		 6284 err = ixgbe_init_interrupt_scheme(adapter);
6285 if (err)
6286 goto err_sw_init;
9a799d71 6287
e8e26350
PW		 6288 switch (pdev->device) {
6289 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 6290 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6291 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 6292 break;
6293 default:
6294 adapter->wol = 0;
6295 break;
6296 }
e8e26350
PW		 6297 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6298
04f165ef
PW		 6299 /* pick up the PCI bus settings for reporting later */
6300 hw->mac.ops.get_bus_info(hw);
6301
9a799d71 6302 /* print bus type/speed/width info */
7c510e4b 6303 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 6304 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6305 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6306 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6307 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6308 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 6309 "Unknown"),
7c510e4b 6310 netdev->dev_addr);
c44ade9e 6311 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 6312 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6313 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
6314 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6315 (part_num >> 8), (part_num & 0xff));
6316 else
6317 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6318 hw->mac.type, hw->phy.type,
6319 (part_num >> 8), (part_num & 0xff));
9a799d71 6320
e8e26350 6321 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 6322 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 6323 "this card is not sufficient for optimal "
6324 "performance.\n");
0c254d86 6325 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 6326 "PCI-Express slot is required.\n");
0c254d86
AK		 6327 }
6328
34b0368c
PWJ		 6329 /* save off EEPROM version number */
6330 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6331
9a799d71 6332 /* reset the hardware with the new settings */
794caeb2 6333 err = hw->mac.ops.start_hw(hw);
c44ade9e 6334
794caeb2
PWJ		 6335 if (err == IXGBE_ERR_EEPROM_VERSION) {
6336 /* We are running on a pre-production device, log a warning */
6337 dev_warn(&pdev->dev, "This device is a pre-production "
6338 "adapter/LOM. Please be aware there may be issues "
6339 "associated with your hardware. If you are "
6340 "experiencing problems please contact your Intel or "
6341 "hardware representative who provided you with this "
6342 "hardware.\n");
6343 }
9a799d71
AK		 6344 strcpy(netdev->name, "eth%d");
6345 err = register_netdev(netdev);
6346 if (err)
6347 goto err_register;
6348
54386467
JB		 6349 /* carrier off reporting is important to ethtool even BEFORE open */
6350 netif_carrier_off(netdev);
6351
c4cf55e5
PWJ		 6352 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6353 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6354 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6355
5dd2d332 6356#ifdef CONFIG_IXGBE_DCA
652f093f 6357 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 6358 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 6359 ixgbe_setup_dca(adapter);
6360 }
6361#endif
1cdd1ec8
GR		 6362 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6363 DPRINTK(PROBE, INFO, "IOV is enabled with %d VFs\n",
6364 adapter->num_vfs);
6365 for (i = 0; i < adapter->num_vfs; i++)
6366 ixgbe_vf_configuration(pdev, (i | 0x10000000));
6367 }
6368
0365e6e4
PW		 6369 /* add san mac addr to netdev */
6370 ixgbe_add_sanmac_netdev(netdev);
9a799d71
AK		 6371
6372 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
6373 cards_found++;
6374 return 0;
6375
6376err_register:
5eba3699 6377 ixgbe_release_hw_control(adapter);
7a921c93 6378 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 6379err_sw_init:
6380err_eeprom:
1cdd1ec8
GR		 6381 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6382 ixgbe_disable_sriov(adapter);
c4900be0
DS		 6383 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6384 del_timer_sync(&adapter->sfp_timer);
6385 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6386 cancel_work_sync(&adapter->multispeed_fiber_task);
6387 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 6388 iounmap(hw->hw_addr);
6389err_ioremap:
6390 free_netdev(netdev);
6391err_alloc_etherdev:
9ce77666 6392 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6393 IORESOURCE_MEM));
9a799d71
AK		 6394err_pci_reg:
6395err_dma:
6396 pci_disable_device(pdev);
6397 return err;
6398}
6399
6400/**
6401 * ixgbe_remove - Device Removal Routine
6402 * @pdev: PCI device information struct
6403 *
6404 * ixgbe_remove is called by the PCI subsystem to alert the driver
6405 * that it should release a PCI device. The could be caused by a
6406 * Hot-Plug event, or because the driver is going to be removed from
6407 * memory.
6408 **/
6409static void __devexit ixgbe_remove(struct pci_dev *pdev)
6410{
6411 struct net_device *netdev = pci_get_drvdata(pdev);
6412 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6413
6414 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 6415 /* clear the module not found bit to make sure the worker won't
6416 * reschedule
6417 */
6418 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 6419 del_timer_sync(&adapter->watchdog_timer);
6420
c4900be0
DS		 6421 del_timer_sync(&adapter->sfp_timer);
6422 cancel_work_sync(&adapter->watchdog_task);
6423 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6424 cancel_work_sync(&adapter->multispeed_fiber_task);
6425 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 6426 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6427 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6428 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 6429 flush_scheduled_work();
6430
5dd2d332 6431#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6432 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6433 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6434 dca_remove_requester(&pdev->dev);
6435 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6436 }
6437
6438#endif
332d4a7d
YZ		 6439#ifdef IXGBE_FCOE
6440 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6441 ixgbe_cleanup_fcoe(adapter);
6442
6443#endif /* IXGBE_FCOE */
0365e6e4
PW		 6444
6445 /* remove the added san mac */
6446 ixgbe_del_sanmac_netdev(netdev);
6447
c4900be0
DS		 6448 if (netdev->reg_state == NETREG_REGISTERED)
6449 unregister_netdev(netdev);
9a799d71 6450
1cdd1ec8
GR		 6451 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6452 ixgbe_disable_sriov(adapter);
6453
7a921c93 6454 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 6455
021230d4 6456 ixgbe_release_hw_control(adapter);
9a799d71
AK		 6457
6458 iounmap(adapter->hw.hw_addr);
9ce77666 6459 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6460 IORESOURCE_MEM));
9a799d71 6461
021230d4 6462 DPRINTK(PROBE, INFO, "complete\n");
021230d4 6463
9a799d71
AK		 6464 free_netdev(netdev);
6465
19d5afd4 6466 pci_disable_pcie_error_reporting(pdev);
6fabd715 6467
9a799d71
AK		 6468 pci_disable_device(pdev);
6469}
6470
6471/**
6472 * ixgbe_io_error_detected - called when PCI error is detected
6473 * @pdev: Pointer to PCI device
6474 * @state: The current pci connection state
6475 *
6476 * This function is called after a PCI bus error affecting
6477 * this device has been detected.
6478 */
6479static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 6480 pci_channel_state_t state)
9a799d71
AK		 6481{
6482 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6483 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6484
6485 netif_device_detach(netdev);
6486
3044b8d1
BL		 6487 if (state == pci_channel_io_perm_failure)
6488 return PCI_ERS_RESULT_DISCONNECT;
6489
9a799d71
AK		 6490 if (netif_running(netdev))
6491 ixgbe_down(adapter);
6492 pci_disable_device(pdev);
6493
b4617240 6494 /* Request a slot reset. */
9a799d71
AK		 6495 return PCI_ERS_RESULT_NEED_RESET;
6496}
6497
6498/**
6499 * ixgbe_io_slot_reset - called after the pci bus has been reset.
6500 * @pdev: Pointer to PCI device
6501 *
6502 * Restart the card from scratch, as if from a cold-boot.
6503 */
6504static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
6505{
6506 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6507 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 6508 pci_ers_result_t result;
6509 int err;
9a799d71 6510
9ce77666 6511 if (pci_enable_device_mem(pdev)) {
9a799d71 6512 DPRINTK(PROBE, ERR,
b4617240 6513 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 6514 result = PCI_ERS_RESULT_DISCONNECT;
6515 } else {
6516 pci_set_master(pdev);
6517 pci_restore_state(pdev);
c0e1f68b 6518 pci_save_state(pdev);
9a799d71 6519
dd4d8ca6 6520 pci_wake_from_d3(pdev, false);
9a799d71 6521
6fabd715 6522 ixgbe_reset(adapter);
88512539 6523 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 6524 result = PCI_ERS_RESULT_RECOVERED;
6525 }
6526
6527 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6528 if (err) {
6529 dev_err(&pdev->dev,
6530 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6531 /* non-fatal, continue */
6532 }
9a799d71 6533
6fabd715 6534 return result;
9a799d71
AK		 6535}
6536
6537/**
6538 * ixgbe_io_resume - called when traffic can start flowing again.
6539 * @pdev: Pointer to PCI device
6540 *
6541 * This callback is called when the error recovery driver tells us that
6542 * its OK to resume normal operation.
6543 */
6544static void ixgbe_io_resume(struct pci_dev *pdev)
6545{
6546 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6547 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6548
6549 if (netif_running(netdev)) {
6550 if (ixgbe_up(adapter)) {
6551 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6552 return;
6553 }
6554 }
6555
6556 netif_device_attach(netdev);
9a799d71
AK		 6557}
6558
6559static struct pci_error_handlers ixgbe_err_handler = {
6560 .error_detected = ixgbe_io_error_detected,
6561 .slot_reset = ixgbe_io_slot_reset,
6562 .resume = ixgbe_io_resume,
6563};
6564
6565static struct pci_driver ixgbe_driver = {
6566 .name = ixgbe_driver_name,
6567 .id_table = ixgbe_pci_tbl,
6568 .probe = ixgbe_probe,
6569 .remove = __devexit_p(ixgbe_remove),
6570#ifdef CONFIG_PM
6571 .suspend = ixgbe_suspend,
6572 .resume = ixgbe_resume,
6573#endif
6574 .shutdown = ixgbe_shutdown,
6575 .err_handler = &ixgbe_err_handler
6576};
6577
6578/**
6579 * ixgbe_init_module - Driver Registration Routine
6580 *
6581 * ixgbe_init_module is the first routine called when the driver is
6582 * loaded. All it does is register with the PCI subsystem.
6583 **/
6584static int __init ixgbe_init_module(void)
6585{
6586 int ret;
6587 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6588 ixgbe_driver_string, ixgbe_driver_version);
6589
6590 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6591
5dd2d332 6592#ifdef CONFIG_IXGBE_DCA
bd0362dd 6593 dca_register_notify(&dca_notifier);
bd0362dd 6594#endif
5dd2d332 6595
9a799d71
AK		 6596 ret = pci_register_driver(&ixgbe_driver);
6597 return ret;
6598}
b4617240 6599
9a799d71
AK		 6600module_init(ixgbe_init_module);
6601
6602/**
6603 * ixgbe_exit_module - Driver Exit Cleanup Routine
6604 *
6605 * ixgbe_exit_module is called just before the driver is removed
6606 * from memory.
6607 **/
6608static void __exit ixgbe_exit_module(void)
6609{
5dd2d332 6610#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6611 dca_unregister_notify(&dca_notifier);
6612#endif
9a799d71
AK		 6613 pci_unregister_driver(&ixgbe_driver);
6614}
bd0362dd 6615
5dd2d332 6616#ifdef CONFIG_IXGBE_DCA
bd0362dd 6617static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 6618 void *p)
bd0362dd
JC		 6619{
6620 int ret_val;
6621
6622 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 6623 __ixgbe_notify_dca);
bd0362dd
JC		 6624
6625 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6626}
b453368d 6627
5dd2d332 6628#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 6629#ifdef DEBUG
6630/**
6631 * ixgbe_get_hw_dev_name - return device name string
6632 * used by hardware layer to print debugging information
6633 **/
6634char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6635{
6636 struct ixgbe_adapter *adapter = hw->back;
6637 return adapter->netdev->name;
6638}
bd0362dd 6639
b453368d 6640#endif
9a799d71
AK		 6641module_exit(ixgbe_exit_module);
6642
6643/* ixgbe_main.c */
kernel source for telekom puls (alcatel/mediatek)