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ixgbe: set max desc to prevent total RSC packet size of 64K
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/ipv6.h>
38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
40#include <linux/ethtool.h>
41#include <linux/if_vlan.h>
eacd73f7 42#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 43
44#include "ixgbe.h"
45#include "ixgbe_common.h"
46
47char ixgbe_driver_name[] = "ixgbe";
9c8eb720 48static const char ixgbe_driver_string[] =
b4617240 49 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 50
04193058 51#define DRV_VERSION "2.0.16-k2"
9c8eb720 52const char ixgbe_driver_version[] = DRV_VERSION;
3efac5a0 53static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
9a799d71
AK		 54
55static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 56 [board_82598] = &ixgbe_82598_info,
e8e26350 57 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 58};
59
60/* ixgbe_pci_tbl - PCI Device ID Table
61 *
62 * Wildcard entries (PCI_ANY_ID) should come last
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
68static struct pci_device_id ixgbe_pci_tbl[] = {
1e336d0f
DS		 69 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
70 board_82598 },
9a799d71 71 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 72 board_82598 },
9a799d71 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 74 board_82598 },
0befdb3e
JB		 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
76 board_82598 },
9a799d71 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 78 board_82598 },
8d792cd9
JB		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
80 board_82598 },
c4900be0
DS		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
82 board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
84 board_82598 },
b95f5fcb
JB		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
86 board_82598 },
c4900be0
DS		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
88 board_82598 },
2f21bdd3
DS		 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
90 board_82598 },
e8e26350
PW		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
92 board_82599 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
94 board_82599 },
9a799d71
AK		 95
96 /* required last entry */
97 {0, }
98};
99MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
100
5dd2d332 101#ifdef CONFIG_IXGBE_DCA
bd0362dd 102static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 103 void *p);
bd0362dd
JC		 104static struct notifier_block dca_notifier = {
105 .notifier_call = ixgbe_notify_dca,
106 .next = NULL,
107 .priority = 0
108};
109#endif
110
9a799d71
AK		 111MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
112MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
113MODULE_LICENSE("GPL");
114MODULE_VERSION(DRV_VERSION);
115
116#define DEFAULT_DEBUG_LEVEL_SHIFT 3
117
5eba3699
AV		 118static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
119{
120 u32 ctrl_ext;
121
122 /* Let firmware take over control of h/w */
123 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
124 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 125 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 126}
127
128static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
129{
130 u32 ctrl_ext;
131
132 /* Let firmware know the driver has taken over */
133 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
134 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 135 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 136}
9a799d71 137
e8e26350
PW		 138/*
139 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
140 * @adapter: pointer to adapter struct
141 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
142 * @queue: queue to map the corresponding interrupt to
143 * @msix_vector: the vector to map to the corresponding queue
144 *
145 */
146static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
147 u8 queue, u8 msix_vector)
9a799d71
AK		 148{
149 u32 ivar, index;
e8e26350
PW		 150 struct ixgbe_hw *hw = &adapter->hw;
151 switch (hw->mac.type) {
152 case ixgbe_mac_82598EB:
153 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
154 if (direction == -1)
155 direction = 0;
156 index = (((direction * 64) + queue) >> 2) & 0x1F;
157 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
158 ivar &= ~(0xFF << (8 * (queue & 0x3)));
159 ivar |= (msix_vector << (8 * (queue & 0x3)));
160 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
161 break;
162 case ixgbe_mac_82599EB:
163 if (direction == -1) {
164 /* other causes */
165 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
166 index = ((queue & 1) * 8);
167 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
168 ivar &= ~(0xFF << index);
169 ivar |= (msix_vector << index);
170 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
171 break;
172 } else {
173 /* tx or rx causes */
174 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
175 index = ((16 * (queue & 1)) + (8 * direction));
176 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
177 ivar &= ~(0xFF << index);
178 ivar |= (msix_vector << index);
179 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
180 break;
181 }
182 default:
183 break;
184 }
9a799d71
AK		 185}
186
187static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 188 struct ixgbe_tx_buffer
189 *tx_buffer_info)
9a799d71 190{
44df32c5 191 tx_buffer_info->dma = 0;
9a799d71 192 if (tx_buffer_info->skb) {
44df32c5
AD		 193 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
194 DMA_TO_DEVICE);
9a799d71
AK		 195 dev_kfree_skb_any(tx_buffer_info->skb);
196 tx_buffer_info->skb = NULL;
197 }
44df32c5 198 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 199 /* tx_buffer_info must be completely set up in the transmit path */
200}
201
202static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 203 struct ixgbe_ring *tx_ring,
204 unsigned int eop)
9a799d71 205{
e01c31a5 206 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 207
9a799d71 208 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 209 * check with the clearing of time_stamp and movement of eop */
9a799d71 210 adapter->detect_tx_hung = false;
44df32c5 211 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 212 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
213 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
214 /* detected Tx unit hang */
e01c31a5
JB		 215 union ixgbe_adv_tx_desc *tx_desc;
216 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 217 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 218 " Tx Queue <%d>\n"
219 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 220 " next_to_use <%x>\n"
221 " next_to_clean <%x>\n"
222 "tx_buffer_info[next_to_clean]\n"
223 " time_stamp <%lx>\n"
e01c31a5
JB		 224 " jiffies <%lx>\n",
225 tx_ring->queue_index,
44df32c5
AD		 226 IXGBE_READ_REG(hw, tx_ring->head),
227 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 228 tx_ring->next_to_use, eop,
229 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 230 return true;
231 }
232
233 return false;
234}
235
b4617240
PW		 236#define IXGBE_MAX_TXD_PWR 14
237#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 238
239/* Tx Descriptors needed, worst case */
240#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
241 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
242#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 243 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 244
e01c31a5
JB		 245static void ixgbe_tx_timeout(struct net_device *netdev);
246
9a799d71
AK		 247/**
248 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
249 * @adapter: board private structure
e01c31a5 250 * @tx_ring: tx ring to clean
9a1a69ad
JB		 251 *
252 * returns true if transmit work is done
9a799d71
AK		 253 **/
254static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
e01c31a5 255 struct ixgbe_ring *tx_ring)
9a799d71 256{
e01c31a5 257 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 258 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
259 struct ixgbe_tx_buffer *tx_buffer_info;
260 unsigned int i, eop, count = 0;
e01c31a5 261 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 262
263 i = tx_ring->next_to_clean;
12207e49
PWJ		 264 eop = tx_ring->tx_buffer_info[i].next_to_watch;
265 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
266
267 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 268 (count < tx_ring->work_limit)) {
12207e49
PWJ		 269 bool cleaned = false;
270 for ( ; !cleaned; count++) {
271 struct sk_buff *skb;
9a799d71
AK		 272 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
273 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 274 cleaned = (i == eop);
e01c31a5 275 skb = tx_buffer_info->skb;
9a799d71 276
12207e49 277 if (cleaned && skb) {
e092be60 278 unsigned int segs, bytecount;
e01c31a5
JB		 279
280 /* gso_segs is currently only valid for tcp */
e092be60
AV		 281 segs = skb_shinfo(skb)->gso_segs ?: 1;
282 /* multiply data chunks by size of headers */
283 bytecount = ((segs - 1) * skb_headlen(skb)) +
e01c31a5
JB		 284 skb->len;
285 total_packets += segs;
286 total_bytes += bytecount;
e092be60 287 }
e01c31a5 288
9a799d71 289 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 290 tx_buffer_info);
9a799d71 291
12207e49
PWJ		 292 tx_desc->wb.status = 0;
293
9a799d71
AK		 294 i++;
295 if (i == tx_ring->count)
296 i = 0;
e01c31a5 297 }
12207e49
PWJ		 298
299 eop = tx_ring->tx_buffer_info[i].next_to_watch;
300 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
301 }
302
9a799d71
AK		 303 tx_ring->next_to_clean = i;
304
e092be60 305#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 306 if (unlikely(count && netif_carrier_ok(netdev) &&
307 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 308 /* Make sure that anybody stopping the queue after this
309 * sees the new next_to_clean.
310 */
311 smp_mb();
30eba97a
AV		 312 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
313 !test_bit(__IXGBE_DOWN, &adapter->state)) {
314 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 315 ++adapter->restart_queue;
30eba97a 316 }
e092be60 317 }
9a799d71 318
e01c31a5
JB		 319 if (adapter->detect_tx_hung) {
320 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
321 /* schedule immediate reset if we believe we hung */
322 DPRINTK(PROBE, INFO,
323 "tx hang %d detected, resetting adapter\n",
324 adapter->tx_timeout_count + 1);
325 ixgbe_tx_timeout(adapter->netdev);
326 }
327 }
9a799d71 328
e01c31a5 329 /* re-arm the interrupt */
835462fc
NS		 330 if (count >= tx_ring->work_limit) {
331 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
332 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
333 tx_ring->v_idx);
334 else if (tx_ring->v_idx & 0xFFFFFFFF)
335 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0),
336 tx_ring->v_idx);
337 else
338 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1),
339 (tx_ring->v_idx >> 32));
340 }
341
9a799d71 342
e01c31a5
JB		 343 tx_ring->total_bytes += total_bytes;
344 tx_ring->total_packets += total_packets;
e01c31a5 345 tx_ring->stats.packets += total_packets;
12207e49 346 tx_ring->stats.bytes += total_bytes;
e01c31a5
JB		 347 adapter->net_stats.tx_bytes += total_bytes;
348 adapter->net_stats.tx_packets += total_packets;
9a1a69ad 349 return (count < tx_ring->work_limit);
9a799d71
AK		 350}
351
5dd2d332 352#ifdef CONFIG_IXGBE_DCA
bd0362dd 353static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 354 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 355{
356 u32 rxctrl;
357 int cpu = get_cpu();
3a581073 358 int q = rx_ring - adapter->rx_ring;
bd0362dd 359
3a581073 360 if (rx_ring->cpu != cpu) {
bd0362dd 361 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 362 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
363 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
364 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
365 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
366 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
367 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
368 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
369 }
bd0362dd
JC		 370 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
371 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 372 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
373 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 374 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 375 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 376 rx_ring->cpu = cpu;
bd0362dd
JC		 377 }
378 put_cpu();
379}
380
381static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 382 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 383{
384 u32 txctrl;
385 int cpu = get_cpu();
3a581073 386 int q = tx_ring - adapter->tx_ring;
bd0362dd 387
3a581073 388 if (tx_ring->cpu != cpu) {
bd0362dd 389 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 390 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
391 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
392 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
393 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
394 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
395 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
396 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
397 }
bd0362dd
JC		 398 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
399 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 400 tx_ring->cpu = cpu;
bd0362dd
JC		 401 }
402 put_cpu();
403}
404
405static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
406{
407 int i;
408
409 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
410 return;
411
412 for (i = 0; i < adapter->num_tx_queues; i++) {
413 adapter->tx_ring[i].cpu = -1;
414 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
415 }
416 for (i = 0; i < adapter->num_rx_queues; i++) {
417 adapter->rx_ring[i].cpu = -1;
418 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
419 }
420}
421
422static int __ixgbe_notify_dca(struct device *dev, void *data)
423{
424 struct net_device *netdev = dev_get_drvdata(dev);
425 struct ixgbe_adapter *adapter = netdev_priv(netdev);
426 unsigned long event = *(unsigned long *)data;
427
428 switch (event) {
429 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 430 /* if we're already enabled, don't do it again */
431 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
432 break;
bd0362dd
JC		 433 /* Always use CB2 mode, difference is masked
434 * in the CB driver. */
435 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
652f093f 436 if (dca_add_requester(dev) == 0) {
96b0e0f6 437 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 438 ixgbe_setup_dca(adapter);
439 break;
440 }
441 /* Fall Through since DCA is disabled. */
442 case DCA_PROVIDER_REMOVE:
443 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
444 dca_remove_requester(dev);
445 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
446 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
447 }
448 break;
449 }
450
652f093f 451 return 0;
bd0362dd
JC		 452}
453
5dd2d332 454#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 455/**
456 * ixgbe_receive_skb - Send a completed packet up the stack
457 * @adapter: board private structure
458 * @skb: packet to send up
177db6ff
MC		 459 * @status: hardware indication of status of receive
460 * @rx_ring: rx descriptor ring (for a specific queue) to setup
461 * @rx_desc: rx descriptor
9a799d71 462 **/
78b6f4ce 463static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 464 struct sk_buff *skb, u8 status,
fdaff1ce 465 struct ixgbe_ring *ring,
177db6ff 466 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 467{
78b6f4ce
HX		 468 struct ixgbe_adapter *adapter = q_vector->adapter;
469 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 470 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
471 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 472
fdaff1ce 473 skb_record_rx_queue(skb, ring->queue_index);
182ff8df 474 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
2f90b865 475 if (adapter->vlgrp && is_vlan && (tag != 0))
78b6f4ce 476 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 477 else
78b6f4ce 478 napi_gro_receive(napi, skb);
177db6ff 479 } else {
182ff8df
AD		 480 if (adapter->vlgrp && is_vlan && (tag != 0))
481 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
482 else
483 netif_rx(skb);
9a799d71
AK		 484 }
485}
486
e59bd25d
AV		 487/**
488 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
489 * @adapter: address of board private structure
490 * @status_err: hardware indication of status of receive
491 * @skb: skb currently being received and modified
492 **/
9a799d71 493static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
712744be 494 u32 status_err, struct sk_buff *skb)
9a799d71
AK		 495{
496 skb->ip_summed = CHECKSUM_NONE;
497
712744be
JB		 498 /* Rx csum disabled */
499 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 500 return;
e59bd25d
AV		 501
502 /* if IP and error */
503 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
504 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 505 adapter->hw_csum_rx_error++;
506 return;
507 }
e59bd25d
AV		 508
509 if (!(status_err & IXGBE_RXD_STAT_L4CS))
510 return;
511
512 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
513 adapter->hw_csum_rx_error++;
514 return;
515 }
516
9a799d71 517 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 518 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 519 adapter->hw_csum_rx_good++;
520}
521
e8e26350
PW		 522static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
523 struct ixgbe_ring *rx_ring, u32 val)
524{
525 /*
526 * Force memory writes to complete before letting h/w
527 * know there are new descriptors to fetch. (Only
528 * applicable for weak-ordered memory model archs,
529 * such as IA-64).
530 */
531 wmb();
532 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
533}
534
9a799d71
AK		 535/**
536 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
537 * @adapter: address of board private structure
538 **/
539static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 540 struct ixgbe_ring *rx_ring,
541 int cleaned_count)
9a799d71 542{
9a799d71
AK		 543 struct pci_dev *pdev = adapter->pdev;
544 union ixgbe_adv_rx_desc *rx_desc;
3a581073 545 struct ixgbe_rx_buffer *bi;
9a799d71 546 unsigned int i;
e8e26350 547 unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
9a799d71
AK		 548
549 i = rx_ring->next_to_use;
3a581073 550 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 551
552 while (cleaned_count--) {
553 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
554
762f4c57 555 if (!bi->page_dma &&
3a581073 556 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
3a581073 557 if (!bi->page) {
762f4c57
JB		 558 bi->page = alloc_page(GFP_ATOMIC);
559 if (!bi->page) {
560 adapter->alloc_rx_page_failed++;
561 goto no_buffers;
562 }
563 bi->page_offset = 0;
564 } else {
565 /* use a half page if we're re-using */
566 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 567 }
762f4c57
JB		 568
569 bi->page_dma = pci_map_page(pdev, bi->page,
570 bi->page_offset,
571 (PAGE_SIZE / 2),
572 PCI_DMA_FROMDEVICE);
9a799d71
AK		 573 }
574
3a581073 575 if (!bi->skb) {
5ecc3614 576 struct sk_buff *skb;
e8e26350 577 skb = netdev_alloc_skb(adapter->netdev, bufsz);
9a799d71
AK		 578
579 if (!skb) {
580 adapter->alloc_rx_buff_failed++;
581 goto no_buffers;
582 }
583
584 /*
585 * Make buffer alignment 2 beyond a 16 byte boundary
586 * this will result in a 16 byte aligned IP header after
587 * the 14 byte MAC header is removed
588 */
589 skb_reserve(skb, NET_IP_ALIGN);
590
3a581073 591 bi->skb = skb;
e8e26350 592 bi->dma = pci_map_single(pdev, skb->data, bufsz,
3a581073 593 PCI_DMA_FROMDEVICE);
9a799d71
AK		 594 }
595 /* Refresh the desc even if buffer_addrs didn't change because
596 * each write-back erases this info. */
597 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3a581073
JB		 598 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
599 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 600 } else {
3a581073 601 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 602 }
603
604 i++;
605 if (i == rx_ring->count)
606 i = 0;
3a581073 607 bi = &rx_ring->rx_buffer_info[i];
9a799d71 608 }
7c6e0a43 609
9a799d71
AK		 610no_buffers:
611 if (rx_ring->next_to_use != i) {
612 rx_ring->next_to_use = i;
613 if (i-- == 0)
614 i = (rx_ring->count - 1);
615
e8e26350 616 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 617 }
618}
619
7c6e0a43
JB		 620static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
621{
622 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
623}
624
625static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
626{
627 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
628}
629
f8212f97
AD		 630static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
631{
632 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
633 IXGBE_RXDADV_RSCCNT_MASK) >>
634 IXGBE_RXDADV_RSCCNT_SHIFT;
635}
636
637/**
638 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
639 * @skb: pointer to the last skb in the rsc queue
640 *
641 * This function changes a queue full of hw rsc buffers into a completed
642 * packet. It uses the ->prev pointers to find the first packet and then
643 * turns it into the frag list owner.
644 **/
645static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
646{
647 unsigned int frag_list_size = 0;
648
649 while (skb->prev) {
650 struct sk_buff *prev = skb->prev;
651 frag_list_size += skb->len;
652 skb->prev = NULL;
653 skb = prev;
654 }
655
656 skb_shinfo(skb)->frag_list = skb->next;
657 skb->next = NULL;
658 skb->len += frag_list_size;
659 skb->data_len += frag_list_size;
660 skb->truesize += frag_list_size;
661 return skb;
662}
663
78b6f4ce 664static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 665 struct ixgbe_ring *rx_ring,
666 int *work_done, int work_to_do)
9a799d71 667{
78b6f4ce 668 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 669 struct pci_dev *pdev = adapter->pdev;
670 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
671 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
672 struct sk_buff *skb;
f8212f97 673 unsigned int i, rsc_count = 0;
7c6e0a43 674 u32 len, staterr;
177db6ff
MC		 675 u16 hdr_info;
676 bool cleaned = false;
9a799d71 677 int cleaned_count = 0;
d2f4fbe2 678 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
9a799d71
AK		 679
680 i = rx_ring->next_to_clean;
9a799d71
AK		 681 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
682 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
683 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 684
685 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 686 u32 upper_len = 0;
9a799d71
AK		 687 if (*work_done >= work_to_do)
688 break;
689 (*work_done)++;
690
691 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43
JB		 692 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
693 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 694 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 695 if (hdr_info & IXGBE_RXDADV_SPH)
696 adapter->rx_hdr_split++;
697 if (len > IXGBE_RX_HDR_SIZE)
698 len = IXGBE_RX_HDR_SIZE;
699 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 700 } else {
9a799d71 701 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 702 }
9a799d71
AK		 703
704 cleaned = true;
705 skb = rx_buffer_info->skb;
706 prefetch(skb->data - NET_IP_ALIGN);
707 rx_buffer_info->skb = NULL;
708
709 if (len && !skb_shinfo(skb)->nr_frags) {
710 pci_unmap_single(pdev, rx_buffer_info->dma,
5ecc3614 711 rx_ring->rx_buf_len,
b4617240 712 PCI_DMA_FROMDEVICE);
9a799d71
AK		 713 skb_put(skb, len);
714 }
715
716 if (upper_len) {
717 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 718 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 719 rx_buffer_info->page_dma = 0;
720 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 721 rx_buffer_info->page,
722 rx_buffer_info->page_offset,
723 upper_len);
724
725 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
726 (page_count(rx_buffer_info->page) != 1))
727 rx_buffer_info->page = NULL;
728 else
729 get_page(rx_buffer_info->page);
9a799d71
AK		 730
731 skb->len += upper_len;
732 skb->data_len += upper_len;
733 skb->truesize += upper_len;
734 }
735
736 i++;
737 if (i == rx_ring->count)
738 i = 0;
9a799d71
AK		 739
740 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
741 prefetch(next_rxd);
9a799d71 742 cleaned_count++;
f8212f97
AD		 743
744 if (adapter->flags & IXGBE_FLAG_RSC_CAPABLE)
745 rsc_count = ixgbe_get_rsc_count(rx_desc);
746
747 if (rsc_count) {
748 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
749 IXGBE_RXDADV_NEXTP_SHIFT;
750 next_buffer = &rx_ring->rx_buffer_info[nextp];
751 rx_ring->rsc_count += (rsc_count - 1);
752 } else {
753 next_buffer = &rx_ring->rx_buffer_info[i];
754 }
755
9a799d71 756 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97
AD		 757 if (skb->prev)
758 skb = ixgbe_transform_rsc_queue(skb);
9a799d71
AK		 759 rx_ring->stats.packets++;
760 rx_ring->stats.bytes += skb->len;
761 } else {
f8212f97
AD		 762 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
763 rx_buffer_info->skb = next_buffer->skb;
764 rx_buffer_info->dma = next_buffer->dma;
765 next_buffer->skb = skb;
766 next_buffer->dma = 0;
767 } else {
768 skb->next = next_buffer->skb;
769 skb->next->prev = skb;
770 }
9a799d71
AK		 771 adapter->non_eop_descs++;
772 goto next_desc;
773 }
774
775 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
776 dev_kfree_skb_irq(skb);
777 goto next_desc;
778 }
779
780 ixgbe_rx_checksum(adapter, staterr, skb);
d2f4fbe2
AV		 781
782 /* probably a little skewed due to removing CRC */
783 total_rx_bytes += skb->len;
784 total_rx_packets++;
785
74ce8dd2 786 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 787#ifdef IXGBE_FCOE
788 /* if ddp, not passing to ULD unless for FCP_RSP or error */
789 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
790 if (!ixgbe_fcoe_ddp(adapter, rx_desc, skb))
791 goto next_desc;
792#endif /* IXGBE_FCOE */
fdaff1ce 793 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 794
795next_desc:
796 rx_desc->wb.upper.status_error = 0;
797
798 /* return some buffers to hardware, one at a time is too slow */
799 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
800 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
801 cleaned_count = 0;
802 }
803
804 /* use prefetched values */
805 rx_desc = next_rxd;
f8212f97 806 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 807
808 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 809 }
810
9a799d71
AK		 811 rx_ring->next_to_clean = i;
812 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
813
814 if (cleaned_count)
815 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
816
f494e8fa
AV		 817 rx_ring->total_packets += total_rx_packets;
818 rx_ring->total_bytes += total_rx_bytes;
819 adapter->net_stats.rx_bytes += total_rx_bytes;
820 adapter->net_stats.rx_packets += total_rx_packets;
821
9a799d71
AK		 822 return cleaned;
823}
824
021230d4 825static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 826/**
827 * ixgbe_configure_msix - Configure MSI-X hardware
828 * @adapter: board private structure
829 *
830 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
831 * interrupts.
832 **/
833static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
834{
021230d4
AV		 835 struct ixgbe_q_vector *q_vector;
836 int i, j, q_vectors, v_idx, r_idx;
837 u32 mask;
9a799d71 838
021230d4 839 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 840
4df10466
JB		 841 /*
842 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 843 * corresponding register.
844 */
845 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 846 q_vector = adapter->q_vector[v_idx];
021230d4
AV		 847 /* XXX for_each_bit(...) */
848 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 849 adapter->num_rx_queues);
021230d4
AV		 850
851 for (i = 0; i < q_vector->rxr_count; i++) {
852 j = adapter->rx_ring[r_idx].reg_idx;
e8e26350 853 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 854 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 855 adapter->num_rx_queues,
856 r_idx + 1);
021230d4
AV		 857 }
858 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 859 adapter->num_tx_queues);
021230d4
AV		 860
861 for (i = 0; i < q_vector->txr_count; i++) {
862 j = adapter->tx_ring[r_idx].reg_idx;
e8e26350 863 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 864 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 865 adapter->num_tx_queues,
866 r_idx + 1);
021230d4
AV		 867 }
868
30efa5a3 869 /* if this is a tx only vector halve the interrupt rate */
021230d4 870 if (q_vector->txr_count && !q_vector->rxr_count)
30efa5a3 871 q_vector->eitr = (adapter->eitr_param >> 1);
509ee935 872 else if (q_vector->rxr_count)
30efa5a3
JB		 873 /* rx only */
874 q_vector->eitr = adapter->eitr_param;
021230d4 875
509ee935 876 /*
4df10466 877 * since this is initial set up don't need to call
509ee935
JB		 878 * ixgbe_write_eitr helper
879 */
021230d4 880 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
b4617240 881 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
9a799d71
AK		 882 }
883
e8e26350
PW		 884 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
885 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
886 v_idx);
887 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
888 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 889 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
890
41fb9248 891 /* set up to autoclear timer, and the vectors */
021230d4 892 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 893 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 894 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 895}
896
f494e8fa
AV		 897enum latency_range {
898 lowest_latency = 0,
899 low_latency = 1,
900 bulk_latency = 2,
901 latency_invalid = 255
902};
903
904/**
905 * ixgbe_update_itr - update the dynamic ITR value based on statistics
906 * @adapter: pointer to adapter
907 * @eitr: eitr setting (ints per sec) to give last timeslice
908 * @itr_setting: current throttle rate in ints/second
909 * @packets: the number of packets during this measurement interval
910 * @bytes: the number of bytes during this measurement interval
911 *
912 * Stores a new ITR value based on packets and byte
913 * counts during the last interrupt. The advantage of per interrupt
914 * computation is faster updates and more accurate ITR for the current
915 * traffic pattern. Constants in this function were computed
916 * based on theoretical maximum wire speed and thresholds were set based
917 * on testing data as well as attempting to minimize response time
918 * while increasing bulk throughput.
919 * this functionality is controlled by the InterruptThrottleRate module
920 * parameter (see ixgbe_param.c)
921 **/
922static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 923 u32 eitr, u8 itr_setting,
924 int packets, int bytes)
f494e8fa
AV		 925{
926 unsigned int retval = itr_setting;
927 u32 timepassed_us;
928 u64 bytes_perint;
929
930 if (packets == 0)
931 goto update_itr_done;
932
933
934 /* simple throttlerate management
935 * 0-20MB/s lowest (100000 ints/s)
936 * 20-100MB/s low (20000 ints/s)
937 * 100-1249MB/s bulk (8000 ints/s)
938 */
939 /* what was last interrupt timeslice? */
940 timepassed_us = 1000000/eitr;
941 bytes_perint = bytes / timepassed_us; /* bytes/usec */
942
943 switch (itr_setting) {
944 case lowest_latency:
945 if (bytes_perint > adapter->eitr_low)
946 retval = low_latency;
947 break;
948 case low_latency:
949 if (bytes_perint > adapter->eitr_high)
950 retval = bulk_latency;
951 else if (bytes_perint <= adapter->eitr_low)
952 retval = lowest_latency;
953 break;
954 case bulk_latency:
955 if (bytes_perint <= adapter->eitr_high)
956 retval = low_latency;
957 break;
958 }
959
960update_itr_done:
961 return retval;
962}
963
509ee935
JB		 964/**
965 * ixgbe_write_eitr - write EITR register in hardware specific way
966 * @adapter: pointer to adapter struct
967 * @v_idx: vector index into q_vector array
968 * @itr_reg: new value to be written in *register* format, not ints/s
969 *
970 * This function is made to be called by ethtool and by the driver
971 * when it needs to update EITR registers at runtime. Hardware
972 * specific quirks/differences are taken care of here.
973 */
974void ixgbe_write_eitr(struct ixgbe_adapter *adapter, int v_idx, u32 itr_reg)
975{
976 struct ixgbe_hw *hw = &adapter->hw;
977 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
978 /* must write high and low 16 bits to reset counter */
979 itr_reg |= (itr_reg << 16);
980 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
981 /*
982 * set the WDIS bit to not clear the timer bits and cause an
983 * immediate assertion of the interrupt
984 */
985 itr_reg |= IXGBE_EITR_CNT_WDIS;
986 }
987 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
988}
989
f494e8fa
AV		 990static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
991{
992 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 993 u32 new_itr;
994 u8 current_itr, ret_itr;
7a921c93 995 int i, r_idx, v_idx = q_vector->v_idx;
f494e8fa
AV		 996 struct ixgbe_ring *rx_ring, *tx_ring;
997
998 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
999 for (i = 0; i < q_vector->txr_count; i++) {
1000 tx_ring = &(adapter->tx_ring[r_idx]);
1001 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1002 q_vector->tx_itr,
1003 tx_ring->total_packets,
1004 tx_ring->total_bytes);
f494e8fa
AV		 1005 /* if the result for this queue would decrease interrupt
1006 * rate for this vector then use that result */
30efa5a3 1007 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1008 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1009 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1010 r_idx + 1);
f494e8fa
AV		 1011 }
1012
1013 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1014 for (i = 0; i < q_vector->rxr_count; i++) {
1015 rx_ring = &(adapter->rx_ring[r_idx]);
1016 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1017 q_vector->rx_itr,
1018 rx_ring->total_packets,
1019 rx_ring->total_bytes);
f494e8fa
AV		 1020 /* if the result for this queue would decrease interrupt
1021 * rate for this vector then use that result */
30efa5a3 1022 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1023 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1024 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1025 r_idx + 1);
f494e8fa
AV		 1026 }
1027
30efa5a3 1028 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1029
1030 switch (current_itr) {
1031 /* counts and packets in update_itr are dependent on these numbers */
1032 case lowest_latency:
1033 new_itr = 100000;
1034 break;
1035 case low_latency:
1036 new_itr = 20000; /* aka hwitr = ~200 */
1037 break;
1038 case bulk_latency:
1039 default:
1040 new_itr = 8000;
1041 break;
1042 }
1043
1044 if (new_itr != q_vector->eitr) {
1045 u32 itr_reg;
509ee935
JB		 1046
1047 /* save the algorithm value here, not the smoothed one */
1048 q_vector->eitr = new_itr;
f494e8fa
AV		 1049 /* do an exponential smoothing */
1050 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
f494e8fa 1051 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
509ee935 1052 ixgbe_write_eitr(adapter, v_idx, itr_reg);
f494e8fa
AV		 1053 }
1054
1055 return;
1056}
1057
0befdb3e
JB		 1058static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1059{
1060 struct ixgbe_hw *hw = &adapter->hw;
1061
1062 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1063 (eicr & IXGBE_EICR_GPI_SDP1)) {
1064 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1065 /* write to clear the interrupt */
1066 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1067 }
1068}
cf8280ee 1069
e8e26350
PW		 1070static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1071{
1072 struct ixgbe_hw *hw = &adapter->hw;
1073
1074 if (eicr & IXGBE_EICR_GPI_SDP1) {
1075 /* Clear the interrupt */
1076 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1077 schedule_work(&adapter->multispeed_fiber_task);
1078 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1079 /* Clear the interrupt */
1080 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1081 schedule_work(&adapter->sfp_config_module_task);
1082 } else {
1083 /* Interrupt isn't for us... */
1084 return;
1085 }
1086}
1087
cf8280ee
JB		 1088static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1089{
1090 struct ixgbe_hw *hw = &adapter->hw;
1091
1092 adapter->lsc_int++;
1093 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1094 adapter->link_check_timeout = jiffies;
1095 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1096 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1097 schedule_work(&adapter->watchdog_task);
1098 }
1099}
1100
9a799d71
AK		 1101static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1102{
1103 struct net_device *netdev = data;
1104 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1105 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1106 u32 eicr;
1107
1108 /*
1109 * Workaround for Silicon errata. Use clear-by-write instead
1110 * of clear-by-read. Reading with EICS will return the
1111 * interrupt causes without clearing, which later be done
1112 * with the write to EICR.
1113 */
1114 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1115 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1116
cf8280ee
JB		 1117 if (eicr & IXGBE_EICR_LSC)
1118 ixgbe_check_lsc(adapter);
d4f80882 1119
e8e26350
PW		 1120 if (hw->mac.type == ixgbe_mac_82598EB)
1121 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1122
e8e26350
PW		 1123 if (hw->mac.type == ixgbe_mac_82599EB)
1124 ixgbe_check_sfp_event(adapter, eicr);
d4f80882
AV		 1125 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1126 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1127
1128 return IRQ_HANDLED;
1129}
1130
1131static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1132{
021230d4
AV		 1133 struct ixgbe_q_vector *q_vector = data;
1134 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1135 struct ixgbe_ring *tx_ring;
021230d4
AV		 1136 int i, r_idx;
1137
1138 if (!q_vector->txr_count)
1139 return IRQ_HANDLED;
1140
1141 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1142 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 1143 tx_ring = &(adapter->tx_ring[r_idx]);
5dd2d332 1144#ifdef CONFIG_IXGBE_DCA
bd0362dd 1145 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1146 ixgbe_update_tx_dca(adapter, tx_ring);
bd0362dd 1147#endif
3a581073
JB		 1148 tx_ring->total_bytes = 0;
1149 tx_ring->total_packets = 0;
1150 ixgbe_clean_tx_irq(adapter, tx_ring);
021230d4 1151 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1152 r_idx + 1);
021230d4 1153 }
9a799d71 1154
9a799d71
AK		 1155 return IRQ_HANDLED;
1156}
1157
021230d4
AV		 1158/**
1159 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1160 * @irq: unused
1161 * @data: pointer to our q_vector struct for this interrupt vector
1162 **/
9a799d71
AK		 1163static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1164{
021230d4
AV		 1165 struct ixgbe_q_vector *q_vector = data;
1166 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1167 struct ixgbe_ring *rx_ring;
021230d4 1168 int r_idx;
30efa5a3 1169 int i;
021230d4
AV		 1170
1171 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 1172 for (i = 0; i < q_vector->rxr_count; i++) {
1173 rx_ring = &(adapter->rx_ring[r_idx]);
1174 rx_ring->total_bytes = 0;
1175 rx_ring->total_packets = 0;
1176 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1177 r_idx + 1);
1178 }
1179
021230d4
AV		 1180 if (!q_vector->rxr_count)
1181 return IRQ_HANDLED;
1182
30efa5a3 1183 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1184 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 1185 /* disable interrupts on this vector only */
835462fc
NS		 1186 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1187 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
1188 else if (rx_ring->v_idx & 0xFFFFFFFF)
1189 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), rx_ring->v_idx);
1190 else
1191 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1),
1192 (rx_ring->v_idx >> 32));
288379f0 1193 napi_schedule(&q_vector->napi);
021230d4
AV		 1194
1195 return IRQ_HANDLED;
1196}
1197
1198static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1199{
1200 ixgbe_msix_clean_rx(irq, data);
1201 ixgbe_msix_clean_tx(irq, data);
9a799d71 1202
9a799d71
AK		 1203 return IRQ_HANDLED;
1204}
1205
835462fc
NS		 1206static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1207 u64 qmask)
1208{
1209 u32 mask;
1210
1211 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1212 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1213 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1214 } else {
1215 mask = (qmask & 0xFFFFFFFF);
1216 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1217 mask = (qmask >> 32);
1218 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1219 }
1220 /* skip the flush */
1221}
1222
021230d4
AV		 1223/**
1224 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1225 * @napi: napi struct with our devices info in it
1226 * @budget: amount of work driver is allowed to do this pass, in packets
1227 *
f0848276
JB		 1228 * This function is optimized for cleaning one queue only on a single
1229 * q_vector!!!
021230d4 1230 **/
9a799d71
AK		 1231static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1232{
021230d4 1233 struct ixgbe_q_vector *q_vector =
b4617240 1234 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1235 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1236 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1237 int work_done = 0;
021230d4 1238 long r_idx;
9a799d71 1239
021230d4 1240 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1241 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1242#ifdef CONFIG_IXGBE_DCA
bd0362dd 1243 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1244 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1245#endif
9a799d71 1246
78b6f4ce 1247 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1248
021230d4
AV		 1249 /* If all Rx work done, exit the polling mode */
1250 if (work_done < budget) {
288379f0 1251 napi_complete(napi);
509ee935 1252 if (adapter->itr_setting & 1)
f494e8fa 1253 ixgbe_set_itr_msix(q_vector);
9a799d71 1254 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 1255 ixgbe_irq_enable_queues(adapter, rx_ring->v_idx);
9a799d71
AK		 1256 }
1257
1258 return work_done;
1259}
1260
f0848276
JB		 1261/**
1262 * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1263 * @napi: napi struct with our devices info in it
1264 * @budget: amount of work driver is allowed to do this pass, in packets
1265 *
1266 * This function will clean more than one rx queue associated with a
1267 * q_vector.
1268 **/
1269static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1270{
1271 struct ixgbe_q_vector *q_vector =
1272 container_of(napi, struct ixgbe_q_vector, napi);
1273 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276
JB		 1274 struct ixgbe_ring *rx_ring = NULL;
1275 int work_done = 0, i;
1276 long r_idx;
835462fc 1277 u64 enable_mask = 0;
f0848276
JB		 1278
1279 /* attempt to distribute budget to each queue fairly, but don't allow
1280 * the budget to go below 1 because we'll exit polling */
1281 budget /= (q_vector->rxr_count ?: 1);
1282 budget = max(budget, 1);
1283 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1284 for (i = 0; i < q_vector->rxr_count; i++) {
1285 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1286#ifdef CONFIG_IXGBE_DCA
f0848276
JB		 1287 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1288 ixgbe_update_rx_dca(adapter, rx_ring);
1289#endif
78b6f4ce 1290 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
f0848276
JB		 1291 enable_mask |= rx_ring->v_idx;
1292 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1293 r_idx + 1);
1294 }
1295
1296 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1297 rx_ring = &(adapter->rx_ring[r_idx]);
1298 /* If all Rx work done, exit the polling mode */
7f821875 1299 if (work_done < budget) {
288379f0 1300 napi_complete(napi);
509ee935 1301 if (adapter->itr_setting & 1)
f0848276
JB		 1302 ixgbe_set_itr_msix(q_vector);
1303 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 1304 ixgbe_irq_enable_queues(adapter, enable_mask);
f0848276
JB		 1305 return 0;
1306 }
1307
1308 return work_done;
1309}
021230d4 1310static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1311 int r_idx)
021230d4 1312{
7a921c93
AD		 1313 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1314
1315 set_bit(r_idx, q_vector->rxr_idx);
1316 q_vector->rxr_count++;
c9c7d2e5 1317 a->rx_ring[r_idx].v_idx = (u64)1 << v_idx;
021230d4
AV		 1318}
1319
1320static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 1321 int t_idx)
021230d4 1322{
7a921c93
AD		 1323 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1324
1325 set_bit(t_idx, q_vector->txr_idx);
1326 q_vector->txr_count++;
c9c7d2e5 1327 a->tx_ring[t_idx].v_idx = (u64)1 << v_idx;
021230d4
AV		 1328}
1329
9a799d71 1330/**
021230d4
AV		 1331 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1332 * @adapter: board private structure to initialize
1333 * @vectors: allotted vector count for descriptor rings
9a799d71 1334 *
021230d4
AV		 1335 * This function maps descriptor rings to the queue-specific vectors
1336 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1337 * one vector per ring/queue, but on a constrained vector budget, we
1338 * group the rings as "efficiently" as possible. You would add new
1339 * mapping configurations in here.
9a799d71 1340 **/
021230d4 1341static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1342 int vectors)
021230d4
AV		 1343{
1344 int v_start = 0;
1345 int rxr_idx = 0, txr_idx = 0;
1346 int rxr_remaining = adapter->num_rx_queues;
1347 int txr_remaining = adapter->num_tx_queues;
1348 int i, j;
1349 int rqpv, tqpv;
1350 int err = 0;
1351
1352 /* No mapping required if MSI-X is disabled. */
1353 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1354 goto out;
9a799d71 1355
021230d4
AV		 1356 /*
1357 * The ideal configuration...
1358 * We have enough vectors to map one per queue.
1359 */
1360 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1361 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1362 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1363
021230d4
AV		 1364 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1365 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1366
9a799d71 1367 goto out;
021230d4 1368 }
9a799d71 1369
021230d4
AV		 1370 /*
1371 * If we don't have enough vectors for a 1-to-1
1372 * mapping, we'll have to group them so there are
1373 * multiple queues per vector.
1374 */
1375 /* Re-adjusting *qpv takes care of the remainder. */
1376 for (i = v_start; i < vectors; i++) {
1377 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1378 for (j = 0; j < rqpv; j++) {
1379 map_vector_to_rxq(adapter, i, rxr_idx);
1380 rxr_idx++;
1381 rxr_remaining--;
1382 }
1383 }
1384 for (i = v_start; i < vectors; i++) {
1385 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1386 for (j = 0; j < tqpv; j++) {
1387 map_vector_to_txq(adapter, i, txr_idx);
1388 txr_idx++;
1389 txr_remaining--;
9a799d71 1390 }
9a799d71
AK		 1391 }
1392
021230d4
AV		 1393out:
1394 return err;
1395}
1396
1397/**
1398 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1399 * @adapter: board private structure
1400 *
1401 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1402 * interrupts from the kernel.
1403 **/
1404static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1405{
1406 struct net_device *netdev = adapter->netdev;
1407 irqreturn_t (*handler)(int, void *);
1408 int i, vector, q_vectors, err;
cb13fc20 1409 int ri=0, ti=0;
021230d4
AV		 1410
1411 /* Decrement for Other and TCP Timer vectors */
1412 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1413
1414 /* Map the Tx/Rx rings to the vectors we were allotted. */
1415 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1416 if (err)
1417 goto out;
1418
1419#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1420 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1421 &ixgbe_msix_clean_many)
021230d4 1422 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 1423 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 1424
1425 if(handler == &ixgbe_msix_clean_rx) {
1426 sprintf(adapter->name[vector], "%s-%s-%d",
1427 netdev->name, "rx", ri++);
1428 }
1429 else if(handler == &ixgbe_msix_clean_tx) {
1430 sprintf(adapter->name[vector], "%s-%s-%d",
1431 netdev->name, "tx", ti++);
1432 }
1433 else
1434 sprintf(adapter->name[vector], "%s-%s-%d",
1435 netdev->name, "TxRx", vector);
1436
021230d4 1437 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1438 handler, 0, adapter->name[vector],
7a921c93 1439 adapter->q_vector[vector]);
9a799d71
AK		 1440 if (err) {
1441 DPRINTK(PROBE, ERR,
b4617240
PW		 1442 "request_irq failed for MSIX interrupt "
1443 "Error: %d\n", err);
021230d4 1444 goto free_queue_irqs;
9a799d71 1445 }
9a799d71
AK		 1446 }
1447
021230d4
AV		 1448 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1449 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1450 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1451 if (err) {
1452 DPRINTK(PROBE, ERR,
1453 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1454 goto free_queue_irqs;
9a799d71
AK		 1455 }
1456
9a799d71
AK		 1457 return 0;
1458
021230d4
AV		 1459free_queue_irqs:
1460 for (i = vector - 1; i >= 0; i--)
1461 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 1462 adapter->q_vector[i]);
021230d4
AV		 1463 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1464 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1465 kfree(adapter->msix_entries);
1466 adapter->msix_entries = NULL;
021230d4 1467out:
9a799d71
AK		 1468 return err;
1469}
1470
f494e8fa
AV		 1471static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1472{
7a921c93 1473 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 1474 u8 current_itr;
1475 u32 new_itr = q_vector->eitr;
1476 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1477 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1478
30efa5a3 1479 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1480 q_vector->tx_itr,
1481 tx_ring->total_packets,
1482 tx_ring->total_bytes);
30efa5a3 1483 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1484 q_vector->rx_itr,
1485 rx_ring->total_packets,
1486 rx_ring->total_bytes);
f494e8fa 1487
30efa5a3 1488 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1489
1490 switch (current_itr) {
1491 /* counts and packets in update_itr are dependent on these numbers */
1492 case lowest_latency:
1493 new_itr = 100000;
1494 break;
1495 case low_latency:
1496 new_itr = 20000; /* aka hwitr = ~200 */
1497 break;
1498 case bulk_latency:
1499 new_itr = 8000;
1500 break;
1501 default:
1502 break;
1503 }
1504
1505 if (new_itr != q_vector->eitr) {
1506 u32 itr_reg;
509ee935
JB		 1507
1508 /* save the algorithm value here, not the smoothed one */
1509 q_vector->eitr = new_itr;
f494e8fa
AV		 1510 /* do an exponential smoothing */
1511 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
f494e8fa 1512 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
509ee935 1513 ixgbe_write_eitr(adapter, 0, itr_reg);
f494e8fa
AV		 1514 }
1515
1516 return;
1517}
1518
79aefa45
AD		 1519/**
1520 * ixgbe_irq_enable - Enable default interrupt generation settings
1521 * @adapter: board private structure
1522 **/
1523static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1524{
1525 u32 mask;
835462fc
NS		 1526
1527 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 1528 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1529 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1530 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1531 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1532 mask |= IXGBE_EIMS_GPI_SDP1;
1533 mask |= IXGBE_EIMS_GPI_SDP2;
1534 }
1535
79aefa45 1536 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 1537 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45
AD		 1538 IXGBE_WRITE_FLUSH(&adapter->hw);
1539}
021230d4 1540
9a799d71 1541/**
021230d4 1542 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1543 * @irq: interrupt number
1544 * @data: pointer to a network interface device structure
9a799d71
AK		 1545 **/
1546static irqreturn_t ixgbe_intr(int irq, void *data)
1547{
1548 struct net_device *netdev = data;
1549 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1550 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 1551 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 1552 u32 eicr;
1553
54037505
DS		 1554 /*
1555 * Workaround for silicon errata. Mask the interrupts
1556 * before the read of EICR.
1557 */
1558 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1559
021230d4
AV		 1560 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1561 * therefore no explict interrupt disable is necessary */
1562 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1563 if (!eicr) {
1564 /* shared interrupt alert!
1565 * make sure interrupts are enabled because the read will
1566 * have disabled interrupts due to EIAM */
1567 ixgbe_irq_enable(adapter);
9a799d71 1568 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1569 }
9a799d71 1570
cf8280ee
JB		 1571 if (eicr & IXGBE_EICR_LSC)
1572 ixgbe_check_lsc(adapter);
021230d4 1573
e8e26350
PW		 1574 if (hw->mac.type == ixgbe_mac_82599EB)
1575 ixgbe_check_sfp_event(adapter, eicr);
1576
0befdb3e
JB		 1577 ixgbe_check_fan_failure(adapter, eicr);
1578
7a921c93 1579 if (napi_schedule_prep(&(q_vector->napi))) {
f494e8fa
AV		 1580 adapter->tx_ring[0].total_packets = 0;
1581 adapter->tx_ring[0].total_bytes = 0;
1582 adapter->rx_ring[0].total_packets = 0;
1583 adapter->rx_ring[0].total_bytes = 0;
021230d4 1584 /* would disable interrupts here but EIAM disabled it */
7a921c93 1585 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 1586 }
1587
1588 return IRQ_HANDLED;
1589}
1590
021230d4
AV		 1591static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1592{
1593 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1594
1595 for (i = 0; i < q_vectors; i++) {
7a921c93 1596 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 1597 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1598 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1599 q_vector->rxr_count = 0;
1600 q_vector->txr_count = 0;
1601 }
1602}
1603
9a799d71
AK		 1604/**
1605 * ixgbe_request_irq - initialize interrupts
1606 * @adapter: board private structure
1607 *
1608 * Attempts to configure interrupts using the best available
1609 * capabilities of the hardware and kernel.
1610 **/
021230d4 1611static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1612{
1613 struct net_device *netdev = adapter->netdev;
021230d4 1614 int err;
9a799d71 1615
021230d4
AV		 1616 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1617 err = ixgbe_request_msix_irqs(adapter);
1618 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1619 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
b4617240 1620 netdev->name, netdev);
021230d4
AV		 1621 } else {
1622 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
b4617240 1623 netdev->name, netdev);
9a799d71
AK		 1624 }
1625
9a799d71
AK		 1626 if (err)
1627 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1628
9a799d71
AK		 1629 return err;
1630}
1631
1632static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1633{
1634 struct net_device *netdev = adapter->netdev;
1635
1636 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1637 int i, q_vectors;
9a799d71 1638
021230d4
AV		 1639 q_vectors = adapter->num_msix_vectors;
1640
1641 i = q_vectors - 1;
9a799d71 1642 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1643
021230d4
AV		 1644 i--;
1645 for (; i >= 0; i--) {
1646 free_irq(adapter->msix_entries[i].vector,
7a921c93 1647 adapter->q_vector[i]);
021230d4
AV		 1648 }
1649
1650 ixgbe_reset_q_vectors(adapter);
1651 } else {
1652 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1653 }
1654}
1655
22d5a71b
JB		 1656/**
1657 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1658 * @adapter: board private structure
1659 **/
1660static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1661{
835462fc
NS		 1662 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1663 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1664 } else {
1665 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1666 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 1667 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
22d5a71b
JB		 1668 }
1669 IXGBE_WRITE_FLUSH(&adapter->hw);
1670 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1671 int i;
1672 for (i = 0; i < adapter->num_msix_vectors; i++)
1673 synchronize_irq(adapter->msix_entries[i].vector);
1674 } else {
1675 synchronize_irq(adapter->pdev->irq);
1676 }
1677}
1678
9a799d71
AK		 1679/**
1680 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1681 *
1682 **/
1683static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1684{
9a799d71
AK		 1685 struct ixgbe_hw *hw = &adapter->hw;
1686
021230d4 1687 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
30efa5a3 1688 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
9a799d71 1689
e8e26350
PW		 1690 ixgbe_set_ivar(adapter, 0, 0, 0);
1691 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 1692
1693 map_vector_to_rxq(adapter, 0, 0);
1694 map_vector_to_txq(adapter, 0, 0);
1695
1696 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1697}
1698
1699/**
3a581073 1700 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1701 * @adapter: board private structure
1702 *
1703 * Configure the Tx unit of the MAC after a reset.
1704 **/
1705static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1706{
12207e49 1707 u64 tdba;
9a799d71 1708 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1709 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1710
1711 /* Setup the HW Tx Head and Tail descriptor pointers */
1712 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1713 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1714 j = ring->reg_idx;
1715 tdba = ring->dma;
1716 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1717 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 1718 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 1719 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1720 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1721 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1722 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1723 adapter->tx_ring[i].head = IXGBE_TDH(j);
1724 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1725 /* Disable Tx Head Writeback RO bit, since this hoses
1726 * bookkeeping if things aren't delivered in order.
1727 */
e01c31a5 1728 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1729 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1730 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1731 }
e8e26350
PW		 1732 if (hw->mac.type == ixgbe_mac_82599EB) {
1733 /* We enable 8 traffic classes, DCB only */
1734 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1735 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1736 IXGBE_MTQC_8TC_8TQ));
1737 }
9a799d71
AK		 1738}
1739
e8e26350 1740#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c
JB		 1741
1742static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1743{
1744 struct ixgbe_ring *rx_ring;
1745 u32 srrctl;
e8e26350 1746 int queue0 = 0;
3be1adfb
AD		 1747 unsigned long mask;
1748
e8e26350 1749 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
163de42e
AD		 1750 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1751 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
1752 if (dcb_i == 8)
1753 queue0 = index >> 4;
1754 else if (dcb_i == 4)
1755 queue0 = index >> 5;
1756 else
1757 dev_err(&adapter->pdev->dev, "Invalid DCB "
1758 "configuration\n");
0331a832
YZ		 1759#ifdef IXGBE_FCOE
1760 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1761 struct ixgbe_ring_feature *f;
1762
1763 rx_ring = &adapter->rx_ring[queue0];
1764 f = &adapter->ring_feature[RING_F_FCOE];
1765 if ((queue0 == 0) && (index > rx_ring->reg_idx))
1766 queue0 = f->mask + index -
1767 rx_ring->reg_idx - 1;
1768 }
1769#endif /* IXGBE_FCOE */
163de42e
AD		 1770 } else {
1771 queue0 = index;
1772 }
cc41ac7c 1773 } else {
3be1adfb
AD		 1774 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1775 queue0 = index & mask;
1776 index = index & mask;
cc41ac7c 1777 }
3be1adfb 1778
cc41ac7c
JB		 1779 rx_ring = &adapter->rx_ring[queue0];
1780
1781 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1782
1783 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1784 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1785
afafd5b0
AD		 1786 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1787 IXGBE_SRRCTL_BSIZEHDR_MASK;
1788
cc41ac7c 1789 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
afafd5b0
AD		 1790#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1791 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1792#else
1793 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1794#endif
cc41ac7c 1795 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 1796 } else {
afafd5b0
AD		 1797 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1798 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 1799 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 1800 }
e8e26350 1801
cc41ac7c
JB		 1802 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1803}
9a799d71 1804
9a799d71 1805/**
3a581073 1806 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1807 * @adapter: board private structure
1808 *
1809 * Configure the Rx unit of the MAC after a reset.
1810 **/
1811static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1812{
1813 u64 rdba;
1814 struct ixgbe_hw *hw = &adapter->hw;
1815 struct net_device *netdev = adapter->netdev;
1816 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1817 int i, j;
9a799d71 1818 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1819 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1820 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1821 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1822 u32 fctrl, hlreg0;
509ee935 1823 u32 reta = 0, mrqc = 0;
cc41ac7c 1824 u32 rdrxctl;
f8212f97 1825 u32 rscctrl;
7c6e0a43 1826 int rx_buf_len;
9a799d71
AK		 1827
1828 /* Decide whether to use packet split mode or not */
762f4c57 1829 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71 1830
eacd73f7
YZ		 1831#ifdef IXGBE_FCOE
1832 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
1833 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
1834#endif /* IXGBE_FCOE */
1835
9a799d71
AK		 1836 /* Set the RX buffer length according to the mode */
1837 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 1838 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 1839 if (hw->mac.type == ixgbe_mac_82599EB) {
1840 /* PSRTYPE must be initialized in 82599 */
1841 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
1842 IXGBE_PSRTYPE_UDPHDR |
1843 IXGBE_PSRTYPE_IPV4HDR |
dfa12f05
YZ		 1844 IXGBE_PSRTYPE_IPV6HDR |
1845 IXGBE_PSRTYPE_L2HDR;
e8e26350
PW		 1846 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
1847 }
9a799d71 1848 } else {
f8212f97
AD		 1849 if (!(adapter->flags & IXGBE_FLAG_RSC_ENABLED) &&
1850 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 1851 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 1852 else
7c6e0a43 1853 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 1854 }
1855
1856 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1857 fctrl |= IXGBE_FCTRL_BAM;
021230d4 1858 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 1859 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 1860 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1861
1862 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1863 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1864 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1865 else
1866 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
63f39bd1
YZ		 1867#ifdef IXGBE_FCOE
1868 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
1869 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1870#endif
9a799d71
AK		 1871 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1872
9a799d71
AK		 1873 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1874 /* disable receives while setting up the descriptors */
1875 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1876 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1877
1878 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1879 * the Base and Length of the Rx Descriptor Ring */
1880 for (i = 0; i < adapter->num_rx_queues; i++) {
1881 rdba = adapter->rx_ring[i].dma;
7c6e0a43 1882 j = adapter->rx_ring[i].reg_idx;
284901a9 1883 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 1884 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1885 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1886 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1887 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1888 adapter->rx_ring[i].head = IXGBE_RDH(j);
1889 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1890 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
cc41ac7c 1891
63f39bd1
YZ		 1892#ifdef IXGBE_FCOE
1893 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1894 struct ixgbe_ring_feature *f;
1895 f = &adapter->ring_feature[RING_F_FCOE];
1896 if ((rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
1897 (i >= f->mask) && (i < f->mask + f->indices))
1898 adapter->rx_ring[i].rx_buf_len =
1899 IXGBE_FCOE_JUMBO_FRAME_SIZE;
1900 }
1901
1902#endif /* IXGBE_FCOE */
cc41ac7c 1903 ixgbe_configure_srrctl(adapter, j);
9a799d71
AK		 1904 }
1905
e8e26350
PW		 1906 if (hw->mac.type == ixgbe_mac_82598EB) {
1907 /*
1908 * For VMDq support of different descriptor types or
1909 * buffer sizes through the use of multiple SRRCTL
1910 * registers, RDRXCTL.MVMEN must be set to 1
1911 *
1912 * also, the manual doesn't mention it clearly but DCA hints
1913 * will only use queue 0's tags unless this bit is set. Side
1914 * effects of setting this bit are only that SRRCTL must be
1915 * fully programmed [0..15]
1916 */
2a41ff81
JB		 1917 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1918 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1919 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 1920 }
177db6ff 1921
e8e26350
PW		 1922 /* Program MRQC for the distribution of queues */
1923 if (hw->mac.type == ixgbe_mac_82599EB) {
1924 int mask = adapter->flags & (
1925 IXGBE_FLAG_RSS_ENABLED
1926 | IXGBE_FLAG_DCB_ENABLED
1927 );
1928
1929 switch (mask) {
1930 case (IXGBE_FLAG_RSS_ENABLED):
1931 mrqc = IXGBE_MRQC_RSSEN;
1932 break;
1933 case (IXGBE_FLAG_DCB_ENABLED):
1934 mrqc = IXGBE_MRQC_RT8TCEN;
1935 break;
1936 default:
1937 break;
1938 }
1939 }
021230d4 1940 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 1941 /* Fill out redirection table */
021230d4
AV		 1942 for (i = 0, j = 0; i < 128; i++, j++) {
1943 if (j == adapter->ring_feature[RING_F_RSS].indices)
1944 j = 0;
1945 /* reta = 4-byte sliding window of
1946 * 0x00..(indices-1)(indices-1)00..etc. */
1947 reta = (reta << 8) | (j * 0x11);
1948 if ((i & 3) == 3)
1949 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 1950 }
1951
1952 /* Fill out hash function seeds */
1953 for (i = 0; i < 10; i++)
7c6e0a43 1954 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 1955
2a41ff81
JB		 1956 if (hw->mac.type == ixgbe_mac_82598EB)
1957 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 1958 /* Perform hash on these packet types */
2a41ff81
JB		 1959 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
1960 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1961 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1962 | IXGBE_MRQC_RSS_FIELD_IPV6
1963 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1964 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 1965 }
2a41ff81 1966 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 1967
021230d4
AV		 1968 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1969
1970 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1971 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1972 /* Disable indicating checksum in descriptor, enables
1973 * RSS hash */
9a799d71 1974 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 1975 }
021230d4
AV		 1976 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1977 /* Enable IPv4 payload checksum for UDP fragments
1978 * if PCSD is not set */
1979 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1980 }
1981
1982 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 1983
1984 if (hw->mac.type == ixgbe_mac_82599EB) {
1985 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1986 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 1987 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 1988 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1989 }
f8212f97
AD		 1990
1991 if (adapter->flags & IXGBE_FLAG_RSC_ENABLED) {
1992 /* Enable 82599 HW-RSC */
1993 for (i = 0; i < adapter->num_rx_queues; i++) {
1994 j = adapter->rx_ring[i].reg_idx;
1995 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
1996 rscctrl |= IXGBE_RSCCTL_RSCEN;
1997 /*
e76678dd
AD		 1998 * we must limit the number of descriptors so that the
1999 * total size of max desc * buf_len is not greater
2000 * than 65535
f8212f97 2001 */
e76678dd
AD		 2002 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2003#if (MAX_SKB_FRAGS > 16)
2004 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2005#elif (MAX_SKB_FRAGS > 8)
f8212f97 2006 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
e76678dd
AD		 2007#elif (MAX_SKB_FRAGS > 4)
2008 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
f8212f97 2009#else
e76678dd 2010 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
f8212f97 2011#endif
e76678dd
AD		 2012 } else {
2013 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2014 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2015 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2016 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2017 else
2018 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2019 }
f8212f97
AD		 2020 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2021 }
2022 /* Disable RSC for ACK packets */
2023 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2024 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2025 }
9a799d71
AK		 2026}
2027
068c89b0
DS		 2028static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2029{
2030 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2031 struct ixgbe_hw *hw = &adapter->hw;
2032
2033 /* add VID to filter table */
2034 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2035}
2036
2037static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2038{
2039 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2040 struct ixgbe_hw *hw = &adapter->hw;
2041
2042 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2043 ixgbe_irq_disable(adapter);
2044
2045 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2046
2047 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2048 ixgbe_irq_enable(adapter);
2049
2050 /* remove VID from filter table */
2051 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2052}
2053
9a799d71 2054static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2055 struct vlan_group *grp)
9a799d71
AK		 2056{
2057 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2058 u32 ctrl;
e8e26350 2059 int i, j;
9a799d71 2060
d4f80882
AV		 2061 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2062 ixgbe_irq_disable(adapter);
9a799d71
AK		 2063 adapter->vlgrp = grp;
2064
2f90b865
AD		 2065 /*
2066 * For a DCB driver, always enable VLAN tag stripping so we can
2067 * still receive traffic from a DCB-enabled host even if we're
2068 * not in DCB mode.
2069 */
2070 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
e8e26350
PW		 2071 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2072 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2073 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2074 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2075 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2076 ctrl |= IXGBE_VLNCTRL_VFE;
9a799d71
AK		 2077 /* enable VLAN tag insert/strip */
2078 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
9a799d71
AK		 2079 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2080 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
e8e26350
PW		 2081 for (i = 0; i < adapter->num_rx_queues; i++) {
2082 j = adapter->rx_ring[i].reg_idx;
2083 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2084 ctrl |= IXGBE_RXDCTL_VME;
2085 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2086 }
9a799d71 2087 }
e8e26350 2088 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2089
d4f80882
AV		 2090 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2091 ixgbe_irq_enable(adapter);
9a799d71
AK		 2092}
2093
9a799d71
AK		 2094static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2095{
2096 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2097
2098 if (adapter->vlgrp) {
2099 u16 vid;
2100 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2101 if (!vlan_group_get_device(adapter->vlgrp, vid))
2102 continue;
2103 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2104 }
2105 }
2106}
2107
2c5645cf
CL		 2108static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2109{
2110 struct dev_mc_list *mc_ptr;
2111 u8 *addr = *mc_addr_ptr;
2112 *vmdq = 0;
2113
2114 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2115 if (mc_ptr->next)
2116 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2117 else
2118 *mc_addr_ptr = NULL;
2119
2120 return addr;
2121}
2122
9a799d71 2123/**
2c5645cf 2124 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2125 * @netdev: network interface device structure
2126 *
2c5645cf
CL		 2127 * The set_rx_method entry point is called whenever the unicast/multicast
2128 * address list or the network interface flags are updated. This routine is
2129 * responsible for configuring the hardware for proper unicast, multicast and
2130 * promiscuous mode.
9a799d71 2131 **/
2c5645cf 2132static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2133{
2134 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2135 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 2136 u32 fctrl, vlnctrl;
2c5645cf
CL		 2137 u8 *addr_list = NULL;
2138 int addr_count = 0;
9a799d71
AK		 2139
2140 /* Check for Promiscuous and All Multicast modes */
2141
2142 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 2143 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 2144
2145 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2146 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2147 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 2148 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 2149 } else {
746b9f02
PM		 2150 if (netdev->flags & IFF_ALLMULTI) {
2151 fctrl |= IXGBE_FCTRL_MPE;
2152 fctrl &= ~IXGBE_FCTRL_UPE;
2153 } else {
2154 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2155 }
3d01625a 2156 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 2157 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2158 }
2159
2160 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 2161 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 2162
2c5645cf
CL		 2163 /* reprogram secondary unicast list */
2164 addr_count = netdev->uc_count;
2165 if (addr_count)
2166 addr_list = netdev->uc_list->dmi_addr;
c44ade9e
JB		 2167 hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
2168 ixgbe_addr_list_itr);
9a799d71 2169
2c5645cf
CL		 2170 /* reprogram multicast list */
2171 addr_count = netdev->mc_count;
2172 if (addr_count)
2173 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 2174 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2175 ixgbe_addr_list_itr);
9a799d71
AK		 2176}
2177
021230d4
AV		 2178static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2179{
2180 int q_idx;
2181 struct ixgbe_q_vector *q_vector;
2182 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2183
2184 /* legacy and MSI only use one vector */
2185 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2186 q_vectors = 1;
2187
2188 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2189 struct napi_struct *napi;
7a921c93 2190 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2191 if (!q_vector->rxr_count)
2192 continue;
f0848276
JB		 2193 napi = &q_vector->napi;
2194 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
2195 (q_vector->rxr_count > 1))
2196 napi->poll = &ixgbe_clean_rxonly_many;
2197
2198 napi_enable(napi);
021230d4
AV		 2199 }
2200}
2201
2202static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2203{
2204 int q_idx;
2205 struct ixgbe_q_vector *q_vector;
2206 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2207
2208 /* legacy and MSI only use one vector */
2209 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2210 q_vectors = 1;
2211
2212 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 2213 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2214 if (!q_vector->rxr_count)
2215 continue;
2216 napi_disable(&q_vector->napi);
2217 }
2218}
2219
7a6b6f51 2220#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2221/*
2222 * ixgbe_configure_dcb - Configure DCB hardware
2223 * @adapter: ixgbe adapter struct
2224 *
2225 * This is called by the driver on open to configure the DCB hardware.
2226 * This is also called by the gennetlink interface when reconfiguring
2227 * the DCB state.
2228 */
2229static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2230{
2231 struct ixgbe_hw *hw = &adapter->hw;
2232 u32 txdctl, vlnctrl;
2233 int i, j;
2234
2235 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2236 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2237 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2238
2239 /* reconfigure the hardware */
2240 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2241
2242 for (i = 0; i < adapter->num_tx_queues; i++) {
2243 j = adapter->tx_ring[i].reg_idx;
2244 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2245 /* PThresh workaround for Tx hang with DFP enabled. */
2246 txdctl |= 32;
2247 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2248 }
2249 /* Enable VLAN tag insert/strip */
2250 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
e8e26350
PW		 2251 if (hw->mac.type == ixgbe_mac_82598EB) {
2252 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2253 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2254 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2255 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2256 vlnctrl |= IXGBE_VLNCTRL_VFE;
2257 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2258 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2259 for (i = 0; i < adapter->num_rx_queues; i++) {
2260 j = adapter->rx_ring[i].reg_idx;
2261 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2262 vlnctrl |= IXGBE_RXDCTL_VME;
2263 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2264 }
2265 }
2f90b865
AD		 2266 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2267}
2268
2269#endif
9a799d71
AK		 2270static void ixgbe_configure(struct ixgbe_adapter *adapter)
2271{
2272 struct net_device *netdev = adapter->netdev;
2273 int i;
2274
2c5645cf 2275 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2276
2277 ixgbe_restore_vlan(adapter);
7a6b6f51 2278#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2279 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2280 netif_set_gso_max_size(netdev, 32768);
2281 ixgbe_configure_dcb(adapter);
2282 } else {
2283 netif_set_gso_max_size(netdev, 65536);
2284 }
2285#else
2286 netif_set_gso_max_size(netdev, 65536);
2287#endif
9a799d71 2288
eacd73f7
YZ		 2289#ifdef IXGBE_FCOE
2290 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2291 ixgbe_configure_fcoe(adapter);
2292
2293#endif /* IXGBE_FCOE */
9a799d71
AK		 2294 ixgbe_configure_tx(adapter);
2295 ixgbe_configure_rx(adapter);
2296 for (i = 0; i < adapter->num_rx_queues; i++)
2297 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 2298 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 2299}
2300
e8e26350
PW		 2301static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2302{
2303 switch (hw->phy.type) {
2304 case ixgbe_phy_sfp_avago:
2305 case ixgbe_phy_sfp_ftl:
2306 case ixgbe_phy_sfp_intel:
2307 case ixgbe_phy_sfp_unknown:
2308 case ixgbe_phy_tw_tyco:
2309 case ixgbe_phy_tw_unknown:
2310 return true;
2311 default:
2312 return false;
2313 }
2314}
2315
0ecc061d 2316/**
e8e26350
PW		 2317 * ixgbe_sfp_link_config - set up SFP+ link
2318 * @adapter: pointer to private adapter struct
2319 **/
2320static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2321{
2322 struct ixgbe_hw *hw = &adapter->hw;
2323
2324 if (hw->phy.multispeed_fiber) {
2325 /*
2326 * In multispeed fiber setups, the device may not have
2327 * had a physical connection when the driver loaded.
2328 * If that's the case, the initial link configuration
2329 * couldn't get the MAC into 10G or 1G mode, so we'll
2330 * never have a link status change interrupt fire.
2331 * We need to try and force an autonegotiation
2332 * session, then bring up link.
2333 */
2334 hw->mac.ops.setup_sfp(hw);
2335 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2336 schedule_work(&adapter->multispeed_fiber_task);
2337 } else {
2338 /*
2339 * Direct Attach Cu and non-multispeed fiber modules
2340 * still need to be configured properly prior to
2341 * attempting link.
2342 */
2343 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2344 schedule_work(&adapter->sfp_config_module_task);
2345 }
2346}
2347
2348/**
2349 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2350 * @hw: pointer to private hardware struct
2351 *
2352 * Returns 0 on success, negative on failure
2353 **/
e8e26350 2354static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2355{
2356 u32 autoneg;
2357 bool link_up = false;
2358 u32 ret = IXGBE_ERR_LINK_SETUP;
2359
2360 if (hw->mac.ops.check_link)
2361 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2362
2363 if (ret)
2364 goto link_cfg_out;
2365
2366 if (hw->mac.ops.get_link_capabilities)
2367 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2368 &hw->mac.autoneg);
2369 if (ret)
2370 goto link_cfg_out;
2371
2372 if (hw->mac.ops.setup_link_speed)
2373 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
0ecc061d
PWJ		 2374link_cfg_out:
2375 return ret;
2376}
2377
e8e26350
PW		 2378#define IXGBE_MAX_RX_DESC_POLL 10
2379static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2380 int rxr)
2381{
2382 int j = adapter->rx_ring[rxr].reg_idx;
2383 int k;
2384
2385 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2386 if (IXGBE_READ_REG(&adapter->hw,
2387 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2388 break;
2389 else
2390 msleep(1);
2391 }
2392 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2393 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2394 "not set within the polling period\n", rxr);
2395 }
2396 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2397 (adapter->rx_ring[rxr].count - 1));
2398}
2399
9a799d71
AK		 2400static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2401{
2402 struct net_device *netdev = adapter->netdev;
9a799d71 2403 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2404 int i, j = 0;
e8e26350 2405 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2406 int err;
9a799d71 2407 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2408 u32 txdctl, rxdctl, mhadd;
e8e26350 2409 u32 dmatxctl;
021230d4 2410 u32 gpie;
9a799d71 2411
5eba3699
AV		 2412 ixgbe_get_hw_control(adapter);
2413
021230d4
AV		 2414 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2415 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2416 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2417 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2418 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2419 } else {
2420 /* MSI only */
021230d4 2421 gpie = 0;
9a799d71 2422 }
021230d4
AV		 2423 /* XXX: to interrupt immediately for EICS writes, enable this */
2424 /* gpie |= IXGBE_GPIE_EIMEN; */
2425 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2426 }
2427
021230d4
AV		 2428 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2429 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2430 * specifically only auto mask tx and rx interrupts */
2431 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2432 }
9a799d71 2433
0befdb3e
JB		 2434 /* Enable fan failure interrupt if media type is copper */
2435 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2436 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2437 gpie |= IXGBE_SDP1_GPIEN;
2438 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2439 }
2440
e8e26350
PW		 2441 if (hw->mac.type == ixgbe_mac_82599EB) {
2442 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2443 gpie |= IXGBE_SDP1_GPIEN;
2444 gpie |= IXGBE_SDP2_GPIEN;
2445 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2446 }
2447
63f39bd1
YZ		 2448#ifdef IXGBE_FCOE
2449 /* adjust max frame to be able to do baby jumbo for FCoE */
2450 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2451 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2452 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2453
2454#endif /* IXGBE_FCOE */
021230d4 2455 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2456 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2457 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2458 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2459
2460 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2461 }
2462
2463 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 2464 j = adapter->tx_ring[i].reg_idx;
2465 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2466 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2467 txdctl |= (8 << 16);
e8e26350
PW		 2468 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2469 }
2470
2471 if (hw->mac.type == ixgbe_mac_82599EB) {
2472 /* DMATXCTL.EN must be set after all Tx queue config is done */
2473 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2474 dmatxctl |= IXGBE_DMATXCTL_TE;
2475 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2476 }
2477 for (i = 0; i < adapter->num_tx_queues; i++) {
2478 j = adapter->tx_ring[i].reg_idx;
2479 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2480 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2481 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 2482 }
2483
e8e26350 2484 for (i = 0; i < num_rx_rings; i++) {
021230d4
AV		 2485 j = adapter->rx_ring[i].reg_idx;
2486 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2487 /* enable PTHRESH=32 descriptors (half the internal cache)
2488 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2489 * this also removes a pesky rx_no_buffer_count increment */
2490 rxdctl |= 0x0020;
9a799d71 2491 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2492 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2493 if (hw->mac.type == ixgbe_mac_82599EB)
2494 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2495 }
2496 /* enable all receives */
2497 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2498 if (hw->mac.type == ixgbe_mac_82598EB)
2499 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2500 else
2501 rxdctl |= IXGBE_RXCTRL_RXEN;
2502 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2503
2504 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2505 ixgbe_configure_msix(adapter);
2506 else
2507 ixgbe_configure_msi_and_legacy(adapter);
2508
2509 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2510 ixgbe_napi_enable_all(adapter);
2511
2512 /* clear any pending interrupts, may auto mask */
2513 IXGBE_READ_REG(hw, IXGBE_EICR);
2514
9a799d71
AK		 2515 ixgbe_irq_enable(adapter);
2516
bf069c97
DS		 2517 /*
2518 * If this adapter has a fan, check to see if we had a failure
2519 * before we enabled the interrupt.
2520 */
2521 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2522 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2523 if (esdp & IXGBE_ESDP_SDP1)
2524 DPRINTK(DRV, CRIT,
2525 "Fan has stopped, replace the adapter\n");
2526 }
2527
e8e26350
PW		 2528 /*
2529 * For hot-pluggable SFP+ devices, a new SFP+ module may have
2530 * arrived before interrupts were enabled. We need to kick off
2531 * the SFP+ module setup first, then try to bring up link.
2532 * If we're not hot-pluggable SFP+, we just need to configure link
2533 * and bring it up.
2534 */
2535 err = hw->phy.ops.identify(hw);
2536 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2537 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
2538 ixgbe_down(adapter);
2539 return err;
2540 }
2541
2542 if (ixgbe_is_sfp(hw)) {
2543 ixgbe_sfp_link_config(adapter);
2544 } else {
2545 err = ixgbe_non_sfp_link_config(hw);
2546 if (err)
2547 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2548 }
0ecc061d 2549
1da100bb
PWJ		 2550 /* enable transmits */
2551 netif_tx_start_all_queues(netdev);
2552
9a799d71
AK		 2553 /* bring the link up in the watchdog, this could race with our first
2554 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 2555 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2556 adapter->link_check_timeout = jiffies;
9a799d71
AK		 2557 mod_timer(&adapter->watchdog_timer, jiffies);
2558 return 0;
2559}
2560
d4f80882
AV		 2561void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2562{
2563 WARN_ON(in_interrupt());
2564 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2565 msleep(1);
2566 ixgbe_down(adapter);
2567 ixgbe_up(adapter);
2568 clear_bit(__IXGBE_RESETTING, &adapter->state);
2569}
2570
9a799d71
AK		 2571int ixgbe_up(struct ixgbe_adapter *adapter)
2572{
2573 /* hardware has been reset, we need to reload some things */
2574 ixgbe_configure(adapter);
2575
2576 return ixgbe_up_complete(adapter);
2577}
2578
2579void ixgbe_reset(struct ixgbe_adapter *adapter)
2580{
c44ade9e
JB		 2581 struct ixgbe_hw *hw = &adapter->hw;
2582 if (hw->mac.ops.init_hw(hw))
2583 dev_err(&adapter->pdev->dev, "Hardware Error\n");
9a799d71
AK		 2584
2585 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2586 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2587
2588}
2589
9a799d71
AK		 2590/**
2591 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2592 * @adapter: board private structure
2593 * @rx_ring: ring to free buffers from
2594 **/
2595static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2596 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2597{
2598 struct pci_dev *pdev = adapter->pdev;
2599 unsigned long size;
2600 unsigned int i;
2601
2602 /* Free all the Rx ring sk_buffs */
2603
2604 for (i = 0; i < rx_ring->count; i++) {
2605 struct ixgbe_rx_buffer *rx_buffer_info;
2606
2607 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2608 if (rx_buffer_info->dma) {
2609 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2610 rx_ring->rx_buf_len,
2611 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2612 rx_buffer_info->dma = 0;
2613 }
2614 if (rx_buffer_info->skb) {
f8212f97 2615 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 2616 rx_buffer_info->skb = NULL;
f8212f97
AD		 2617 do {
2618 struct sk_buff *this = skb;
2619 skb = skb->prev;
2620 dev_kfree_skb(this);
2621 } while (skb);
9a799d71
AK		 2622 }
2623 if (!rx_buffer_info->page)
2624 continue;
762f4c57
JB		 2625 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2626 PCI_DMA_FROMDEVICE);
9a799d71 2627 rx_buffer_info->page_dma = 0;
9a799d71
AK		 2628 put_page(rx_buffer_info->page);
2629 rx_buffer_info->page = NULL;
762f4c57 2630 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2631 }
2632
2633 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2634 memset(rx_ring->rx_buffer_info, 0, size);
2635
2636 /* Zero out the descriptor ring */
2637 memset(rx_ring->desc, 0, rx_ring->size);
2638
2639 rx_ring->next_to_clean = 0;
2640 rx_ring->next_to_use = 0;
2641
9891ca7c
JB		 2642 if (rx_ring->head)
2643 writel(0, adapter->hw.hw_addr + rx_ring->head);
2644 if (rx_ring->tail)
2645 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 2646}
2647
2648/**
2649 * ixgbe_clean_tx_ring - Free Tx Buffers
2650 * @adapter: board private structure
2651 * @tx_ring: ring to be cleaned
2652 **/
2653static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2654 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2655{
2656 struct ixgbe_tx_buffer *tx_buffer_info;
2657 unsigned long size;
2658 unsigned int i;
2659
2660 /* Free all the Tx ring sk_buffs */
2661
2662 for (i = 0; i < tx_ring->count; i++) {
2663 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2664 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2665 }
2666
2667 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2668 memset(tx_ring->tx_buffer_info, 0, size);
2669
2670 /* Zero out the descriptor ring */
2671 memset(tx_ring->desc, 0, tx_ring->size);
2672
2673 tx_ring->next_to_use = 0;
2674 tx_ring->next_to_clean = 0;
2675
9891ca7c
JB		 2676 if (tx_ring->head)
2677 writel(0, adapter->hw.hw_addr + tx_ring->head);
2678 if (tx_ring->tail)
2679 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 2680}
2681
2682/**
021230d4 2683 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2684 * @adapter: board private structure
2685 **/
021230d4 2686static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2687{
2688 int i;
2689
021230d4
AV		 2690 for (i = 0; i < adapter->num_rx_queues; i++)
2691 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2692}
2693
2694/**
021230d4 2695 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2696 * @adapter: board private structure
2697 **/
021230d4 2698static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2699{
2700 int i;
2701
021230d4
AV		 2702 for (i = 0; i < adapter->num_tx_queues; i++)
2703 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2704}
2705
2706void ixgbe_down(struct ixgbe_adapter *adapter)
2707{
2708 struct net_device *netdev = adapter->netdev;
7f821875 2709 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2710 u32 rxctrl;
7f821875
JB		 2711 u32 txdctl;
2712 int i, j;
9a799d71
AK		 2713
2714 /* signal that we are down to the interrupt handler */
2715 set_bit(__IXGBE_DOWN, &adapter->state);
2716
2717 /* disable receives */
7f821875
JB		 2718 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2719 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 2720
2721 netif_tx_disable(netdev);
2722
7f821875 2723 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 2724 msleep(10);
2725
7f821875
JB		 2726 netif_tx_stop_all_queues(netdev);
2727
9a799d71
AK		 2728 ixgbe_irq_disable(adapter);
2729
021230d4 2730 ixgbe_napi_disable_all(adapter);
7f821875 2731
9a799d71 2732 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 2733 cancel_work_sync(&adapter->watchdog_task);
9a799d71 2734
7f821875
JB		 2735 /* disable transmits in the hardware now that interrupts are off */
2736 for (i = 0; i < adapter->num_tx_queues; i++) {
2737 j = adapter->tx_ring[i].reg_idx;
2738 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2739 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2740 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2741 }
88512539
PW		 2742 /* Disable the Tx DMA engine on 82599 */
2743 if (hw->mac.type == ixgbe_mac_82599EB)
2744 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2745 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2746 ~IXGBE_DMATXCTL_TE));
7f821875 2747
9a799d71 2748 netif_carrier_off(netdev);
9a799d71 2749
5dd2d332 2750#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2751 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2752 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2753 dca_remove_requester(&adapter->pdev->dev);
2754 }
2755
2756#endif
6f4a0e45
PL		 2757 if (!pci_channel_offline(adapter->pdev))
2758 ixgbe_reset(adapter);
9a799d71
AK		 2759 ixgbe_clean_all_tx_rings(adapter);
2760 ixgbe_clean_all_rx_rings(adapter);
2761
5dd2d332 2762#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2763 /* since we reset the hardware DCA settings were cleared */
2764 if (dca_add_requester(&adapter->pdev->dev) == 0) {
2765 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2766 /* always use CB2 mode, difference is masked
2767 * in the CB driver */
b4617240 2768 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
96b0e0f6
JB		 2769 ixgbe_setup_dca(adapter);
2770 }
2771#endif
9a799d71
AK		 2772}
2773
9a799d71 2774/**
021230d4
AV		 2775 * ixgbe_poll - NAPI Rx polling callback
2776 * @napi: structure for representing this polling device
2777 * @budget: how many packets driver is allowed to clean
2778 *
2779 * This function is used for legacy and MSI, NAPI mode
9a799d71 2780 **/
021230d4 2781static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2782{
9a1a69ad
JB		 2783 struct ixgbe_q_vector *q_vector =
2784 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2785 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 2786 int tx_clean_complete, work_done = 0;
9a799d71 2787
5dd2d332 2788#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 2789 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2790 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2791 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2792 }
2793#endif
2794
9a1a69ad 2795 tx_clean_complete = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
78b6f4ce 2796 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
9a799d71 2797
9a1a69ad 2798 if (!tx_clean_complete)
d2c7ddd6
DM		 2799 work_done = budget;
2800
53e52c72
DM		 2801 /* If budget not fully consumed, exit the polling mode */
2802 if (work_done < budget) {
288379f0 2803 napi_complete(napi);
509ee935 2804 if (adapter->itr_setting & 1)
f494e8fa 2805 ixgbe_set_itr(adapter);
d4f80882 2806 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 2807 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 2808 }
9a799d71
AK		 2809 return work_done;
2810}
2811
2812/**
2813 * ixgbe_tx_timeout - Respond to a Tx Hang
2814 * @netdev: network interface device structure
2815 **/
2816static void ixgbe_tx_timeout(struct net_device *netdev)
2817{
2818 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2819
2820 /* Do the reset outside of interrupt context */
2821 schedule_work(&adapter->reset_task);
2822}
2823
2824static void ixgbe_reset_task(struct work_struct *work)
2825{
2826 struct ixgbe_adapter *adapter;
2827 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2828
2f90b865
AD		 2829 /* If we're already down or resetting, just bail */
2830 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2831 test_bit(__IXGBE_RESETTING, &adapter->state))
2832 return;
2833
9a799d71
AK		 2834 adapter->tx_timeout_count++;
2835
d4f80882 2836 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2837}
2838
bc97114d
PWJ		 2839#ifdef CONFIG_IXGBE_DCB
2840static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 2841{
bc97114d 2842 bool ret = false;
b9804972 2843
bc97114d
PWJ		 2844 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2845 adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3;
2846 adapter->num_rx_queues =
2847 adapter->ring_feature[RING_F_DCB].indices;
2848 adapter->num_tx_queues =
2849 adapter->ring_feature[RING_F_DCB].indices;
2850 ret = true;
2851 } else {
bc97114d
PWJ		 2852 ret = false;
2853 }
2f90b865 2854
bc97114d
PWJ		 2855 return ret;
2856}
2857#endif
2858
4df10466
JB		 2859/**
2860 * ixgbe_set_rss_queues: Allocate queues for RSS
2861 * @adapter: board private structure to initialize
2862 *
2863 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
2864 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
2865 *
2866 **/
bc97114d
PWJ		 2867static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
2868{
2869 bool ret = false;
2870
2871 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2872 adapter->ring_feature[RING_F_RSS].mask = 0xF;
2873 adapter->num_rx_queues =
2874 adapter->ring_feature[RING_F_RSS].indices;
2875 adapter->num_tx_queues =
2876 adapter->ring_feature[RING_F_RSS].indices;
2877 ret = true;
2878 } else {
bc97114d 2879 ret = false;
b9804972
JB		 2880 }
2881
bc97114d
PWJ		 2882 return ret;
2883}
2884
0331a832
YZ		 2885#ifdef IXGBE_FCOE
2886/**
2887 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
2888 * @adapter: board private structure to initialize
2889 *
2890 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
2891 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
2892 * rx queues out of the max number of rx queues, instead, it is used as the
2893 * index of the first rx queue used by FCoE.
2894 *
2895 **/
2896static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
2897{
2898 bool ret = false;
2899 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
2900
2901 f->indices = min((int)num_online_cpus(), f->indices);
2902 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
2903#ifdef CONFIG_IXGBE_DCB
2904 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2905 DPRINTK(PROBE, INFO, "FCOE enabled with DCB \n");
2906 ixgbe_set_dcb_queues(adapter);
2907 }
2908#endif
2909 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2910 DPRINTK(PROBE, INFO, "FCOE enabled with RSS \n");
2911 ixgbe_set_rss_queues(adapter);
2912 }
2913 /* adding FCoE rx rings to the end */
2914 f->mask = adapter->num_rx_queues;
2915 adapter->num_rx_queues += f->indices;
2916 if (adapter->num_tx_queues == 0)
2917 adapter->num_tx_queues = f->indices;
2918
2919 ret = true;
2920 }
2921
2922 return ret;
2923}
2924
2925#endif /* IXGBE_FCOE */
4df10466
JB		 2926/*
2927 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
2928 * @adapter: board private structure to initialize
2929 *
2930 * This is the top level queue allocation routine. The order here is very
2931 * important, starting with the "most" number of features turned on at once,
2932 * and ending with the smallest set of features. This way large combinations
2933 * can be allocated if they're turned on, and smaller combinations are the
2934 * fallthrough conditions.
2935 *
2936 **/
bc97114d
PWJ		 2937static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2938{
0331a832
YZ		 2939#ifdef IXGBE_FCOE
2940 if (ixgbe_set_fcoe_queues(adapter))
2941 goto done;
2942
2943#endif /* IXGBE_FCOE */
bc97114d
PWJ		 2944#ifdef CONFIG_IXGBE_DCB
2945 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 2946 goto done;
bc97114d
PWJ		 2947
2948#endif
2949 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 2950 goto done;
2951
2952 /* fallback to base case */
2953 adapter->num_rx_queues = 1;
2954 adapter->num_tx_queues = 1;
2955
2956done:
2957 /* Notify the stack of the (possibly) reduced Tx Queue count. */
2958 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 2959}
2960
021230d4 2961static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 2962 int vectors)
021230d4
AV		 2963{
2964 int err, vector_threshold;
2965
2966 /* We'll want at least 3 (vector_threshold):
2967 * 1) TxQ[0] Cleanup
2968 * 2) RxQ[0] Cleanup
2969 * 3) Other (Link Status Change, etc.)
2970 * 4) TCP Timer (optional)
2971 */
2972 vector_threshold = MIN_MSIX_COUNT;
2973
2974 /* The more we get, the more we will assign to Tx/Rx Cleanup
2975 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2976 * Right now, we simply care about how many we'll get; we'll
2977 * set them up later while requesting irq's.
2978 */
2979 while (vectors >= vector_threshold) {
2980 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 2981 vectors);
021230d4
AV		 2982 if (!err) /* Success in acquiring all requested vectors. */
2983 break;
2984 else if (err < 0)
2985 vectors = 0; /* Nasty failure, quit now */
2986 else /* err == number of vectors we should try again with */
2987 vectors = err;
2988 }
2989
2990 if (vectors < vector_threshold) {
2991 /* Can't allocate enough MSI-X interrupts? Oh well.
2992 * This just means we'll go with either a single MSI
2993 * vector or fall back to legacy interrupts.
2994 */
2995 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2996 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2997 kfree(adapter->msix_entries);
2998 adapter->msix_entries = NULL;
021230d4
AV		 2999 } else {
3000 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 3001 /*
3002 * Adjust for only the vectors we'll use, which is minimum
3003 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3004 * vectors we were allocated.
3005 */
3006 adapter->num_msix_vectors = min(vectors,
3007 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 3008 }
3009}
3010
021230d4 3011/**
bc97114d 3012 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 3013 * @adapter: board private structure to initialize
3014 *
bc97114d
PWJ		 3015 * Cache the descriptor ring offsets for RSS to the assigned rings.
3016 *
021230d4 3017 **/
bc97114d 3018static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 3019{
bc97114d
PWJ		 3020 int i;
3021 bool ret = false;
3022
3023 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3024 for (i = 0; i < adapter->num_rx_queues; i++)
3025 adapter->rx_ring[i].reg_idx = i;
3026 for (i = 0; i < adapter->num_tx_queues; i++)
3027 adapter->tx_ring[i].reg_idx = i;
3028 ret = true;
3029 } else {
3030 ret = false;
3031 }
3032
3033 return ret;
3034}
3035
3036#ifdef CONFIG_IXGBE_DCB
3037/**
3038 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3039 * @adapter: board private structure to initialize
3040 *
3041 * Cache the descriptor ring offsets for DCB to the assigned rings.
3042 *
3043 **/
3044static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3045{
3046 int i;
3047 bool ret = false;
3048 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3049
3050 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3051 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 3052 /* the number of queues is assumed to be symmetric */
3053 for (i = 0; i < dcb_i; i++) {
3054 adapter->rx_ring[i].reg_idx = i << 3;
3055 adapter->tx_ring[i].reg_idx = i << 2;
3056 }
bc97114d 3057 ret = true;
e8e26350 3058 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 3059 if (dcb_i == 8) {
3060 /*
3061 * Tx TC0 starts at: descriptor queue 0
3062 * Tx TC1 starts at: descriptor queue 32
3063 * Tx TC2 starts at: descriptor queue 64
3064 * Tx TC3 starts at: descriptor queue 80
3065 * Tx TC4 starts at: descriptor queue 96
3066 * Tx TC5 starts at: descriptor queue 104
3067 * Tx TC6 starts at: descriptor queue 112
3068 * Tx TC7 starts at: descriptor queue 120
3069 *
3070 * Rx TC0-TC7 are offset by 16 queues each
3071 */
3072 for (i = 0; i < 3; i++) {
3073 adapter->tx_ring[i].reg_idx = i << 5;
3074 adapter->rx_ring[i].reg_idx = i << 4;
3075 }
3076 for ( ; i < 5; i++) {
3077 adapter->tx_ring[i].reg_idx =
3078 ((i + 2) << 4);
3079 adapter->rx_ring[i].reg_idx = i << 4;
3080 }
3081 for ( ; i < dcb_i; i++) {
3082 adapter->tx_ring[i].reg_idx =
3083 ((i + 8) << 3);
3084 adapter->rx_ring[i].reg_idx = i << 4;
3085 }
3086
3087 ret = true;
3088 } else if (dcb_i == 4) {
3089 /*
3090 * Tx TC0 starts at: descriptor queue 0
3091 * Tx TC1 starts at: descriptor queue 64
3092 * Tx TC2 starts at: descriptor queue 96
3093 * Tx TC3 starts at: descriptor queue 112
3094 *
3095 * Rx TC0-TC3 are offset by 32 queues each
3096 */
3097 adapter->tx_ring[0].reg_idx = 0;
3098 adapter->tx_ring[1].reg_idx = 64;
3099 adapter->tx_ring[2].reg_idx = 96;
3100 adapter->tx_ring[3].reg_idx = 112;
3101 for (i = 0 ; i < dcb_i; i++)
3102 adapter->rx_ring[i].reg_idx = i << 5;
3103
3104 ret = true;
3105 } else {
3106 ret = false;
e8e26350 3107 }
bc97114d
PWJ		 3108 } else {
3109 ret = false;
021230d4 3110 }
bc97114d
PWJ		 3111 } else {
3112 ret = false;
021230d4 3113 }
bc97114d
PWJ		 3114
3115 return ret;
3116}
3117#endif
3118
0331a832
YZ		 3119#ifdef IXGBE_FCOE
3120/**
3121 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3122 * @adapter: board private structure to initialize
3123 *
3124 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3125 *
3126 */
3127static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3128{
3129 int i, fcoe_i = 0;
3130 bool ret = false;
3131 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3132
3133 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3134#ifdef CONFIG_IXGBE_DCB
3135 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3136 ixgbe_cache_ring_dcb(adapter);
3137 fcoe_i = adapter->rx_ring[0].reg_idx + 1;
3138 }
3139#endif /* CONFIG_IXGBE_DCB */
3140 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3141 ixgbe_cache_ring_rss(adapter);
3142 fcoe_i = f->mask;
3143 }
3144 for (i = 0; i < f->indices; i++, fcoe_i++)
3145 adapter->rx_ring[f->mask + i].reg_idx = fcoe_i;
3146 ret = true;
3147 }
3148 return ret;
3149}
3150
3151#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3152/**
3153 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3154 * @adapter: board private structure to initialize
3155 *
3156 * Once we know the feature-set enabled for the device, we'll cache
3157 * the register offset the descriptor ring is assigned to.
3158 *
3159 * Note, the order the various feature calls is important. It must start with
3160 * the "most" features enabled at the same time, then trickle down to the
3161 * least amount of features turned on at once.
3162 **/
3163static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3164{
3165 /* start with default case */
3166 adapter->rx_ring[0].reg_idx = 0;
3167 adapter->tx_ring[0].reg_idx = 0;
3168
0331a832
YZ		 3169#ifdef IXGBE_FCOE
3170 if (ixgbe_cache_ring_fcoe(adapter))
3171 return;
3172
3173#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3174#ifdef CONFIG_IXGBE_DCB
3175 if (ixgbe_cache_ring_dcb(adapter))
3176 return;
3177
3178#endif
3179 if (ixgbe_cache_ring_rss(adapter))
3180 return;
021230d4
AV		 3181}
3182
9a799d71
AK		 3183/**
3184 * ixgbe_alloc_queues - Allocate memory for all rings
3185 * @adapter: board private structure to initialize
3186 *
3187 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 3188 * number of queues at compile-time. The polling_netdev array is
3189 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 3190 **/
2f90b865 3191static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 3192{
3193 int i;
3194
3195 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 3196 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 3197 if (!adapter->tx_ring)
021230d4 3198 goto err_tx_ring_allocation;
9a799d71
AK		 3199
3200 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 3201 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 3202 if (!adapter->rx_ring)
3203 goto err_rx_ring_allocation;
9a799d71 3204
021230d4 3205 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 3206 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 3207 adapter->tx_ring[i].queue_index = i;
3208 }
b9804972 3209
9a799d71 3210 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 3211 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 3212 adapter->rx_ring[i].queue_index = i;
3213 }
3214
3215 ixgbe_cache_ring_register(adapter);
3216
3217 return 0;
3218
3219err_rx_ring_allocation:
3220 kfree(adapter->tx_ring);
3221err_tx_ring_allocation:
3222 return -ENOMEM;
3223}
3224
3225/**
3226 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3227 * @adapter: board private structure to initialize
3228 *
3229 * Attempt to configure the interrupts using the best available
3230 * capabilities of the hardware and the kernel.
3231 **/
feea6a57 3232static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 3233{
8be0e467 3234 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 3235 int err = 0;
3236 int vector, v_budget;
3237
3238 /*
3239 * It's easy to be greedy for MSI-X vectors, but it really
3240 * doesn't do us much good if we have a lot more vectors
3241 * than CPU's. So let's be conservative and only ask for
3242 * (roughly) twice the number of vectors as there are CPU's.
3243 */
3244 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
b4617240 3245 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
021230d4
AV		 3246
3247 /*
3248 * At the same time, hardware can only support a maximum of
8be0e467
PW		 3249 * hw.mac->max_msix_vectors vectors. With features
3250 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3251 * descriptor queues supported by our device. Thus, we cap it off in
3252 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3253 */
8be0e467 3254 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3255
3256 /* A failure in MSI-X entry allocation isn't fatal, but it does
3257 * mean we disable MSI-X capabilities of the adapter. */
3258 adapter->msix_entries = kcalloc(v_budget,
b4617240 3259 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 3260 if (adapter->msix_entries) {
3261 for (vector = 0; vector < v_budget; vector++)
3262 adapter->msix_entries[vector].entry = vector;
021230d4 3263
7a921c93 3264 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 3265
7a921c93
AD		 3266 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3267 goto out;
3268 }
021230d4 3269
7a921c93
AD		 3270 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3271 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3272 ixgbe_set_num_queues(adapter);
021230d4 3273
021230d4
AV		 3274 err = pci_enable_msi(adapter->pdev);
3275 if (!err) {
3276 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3277 } else {
3278 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 3279 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 3280 /* reset err */
3281 err = 0;
3282 }
3283
3284out:
021230d4
AV		 3285 return err;
3286}
3287
7a921c93
AD		 3288/**
3289 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3290 * @adapter: board private structure to initialize
3291 *
3292 * We allocate one q_vector per queue interrupt. If allocation fails we
3293 * return -ENOMEM.
3294 **/
3295static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3296{
3297 int q_idx, num_q_vectors;
3298 struct ixgbe_q_vector *q_vector;
3299 int napi_vectors;
3300 int (*poll)(struct napi_struct *, int);
3301
3302 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3303 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3304 napi_vectors = adapter->num_rx_queues;
3305 poll = &ixgbe_clean_rxonly;
3306 } else {
3307 num_q_vectors = 1;
3308 napi_vectors = 1;
3309 poll = &ixgbe_poll;
3310 }
3311
3312 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3313 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3314 if (!q_vector)
3315 goto err_out;
3316 q_vector->adapter = adapter;
3317 q_vector->v_idx = q_idx;
3318 q_vector->eitr = adapter->eitr_param;
3319 if (q_idx < napi_vectors)
3320 netif_napi_add(adapter->netdev, &q_vector->napi,
3321 (*poll), 64);
3322 adapter->q_vector[q_idx] = q_vector;
3323 }
3324
3325 return 0;
3326
3327err_out:
3328 while (q_idx) {
3329 q_idx--;
3330 q_vector = adapter->q_vector[q_idx];
3331 netif_napi_del(&q_vector->napi);
3332 kfree(q_vector);
3333 adapter->q_vector[q_idx] = NULL;
3334 }
3335 return -ENOMEM;
3336}
3337
3338/**
3339 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3340 * @adapter: board private structure to initialize
3341 *
3342 * This function frees the memory allocated to the q_vectors. In addition if
3343 * NAPI is enabled it will delete any references to the NAPI struct prior
3344 * to freeing the q_vector.
3345 **/
3346static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3347{
3348 int q_idx, num_q_vectors;
3349 int napi_vectors;
3350
3351 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3352 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3353 napi_vectors = adapter->num_rx_queues;
3354 } else {
3355 num_q_vectors = 1;
3356 napi_vectors = 1;
3357 }
3358
3359 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3360 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3361
3362 adapter->q_vector[q_idx] = NULL;
3363 if (q_idx < napi_vectors)
3364 netif_napi_del(&q_vector->napi);
3365 kfree(q_vector);
3366 }
3367}
3368
2f90b865 3369void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 3370{
3371 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3372 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3373 pci_disable_msix(adapter->pdev);
3374 kfree(adapter->msix_entries);
3375 adapter->msix_entries = NULL;
3376 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3377 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3378 pci_disable_msi(adapter->pdev);
3379 }
3380 return;
3381}
3382
3383/**
3384 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3385 * @adapter: board private structure to initialize
3386 *
3387 * We determine which interrupt scheme to use based on...
3388 * - Kernel support (MSI, MSI-X)
3389 * - which can be user-defined (via MODULE_PARAM)
3390 * - Hardware queue count (num_*_queues)
3391 * - defined by miscellaneous hardware support/features (RSS, etc.)
3392 **/
2f90b865 3393int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 3394{
3395 int err;
3396
3397 /* Number of supported queues */
3398 ixgbe_set_num_queues(adapter);
3399
021230d4
AV		 3400 err = ixgbe_set_interrupt_capability(adapter);
3401 if (err) {
3402 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3403 goto err_set_interrupt;
9a799d71
AK		 3404 }
3405
7a921c93
AD		 3406 err = ixgbe_alloc_q_vectors(adapter);
3407 if (err) {
3408 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3409 "vectors\n");
3410 goto err_alloc_q_vectors;
3411 }
3412
3413 err = ixgbe_alloc_queues(adapter);
3414 if (err) {
3415 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3416 goto err_alloc_queues;
3417 }
3418
021230d4 3419 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 3420 "Tx Queue count = %u\n",
3421 (adapter->num_rx_queues > 1) ? "Enabled" :
3422 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 3423
3424 set_bit(__IXGBE_DOWN, &adapter->state);
3425
9a799d71 3426 return 0;
021230d4 3427
7a921c93
AD		 3428err_alloc_queues:
3429 ixgbe_free_q_vectors(adapter);
3430err_alloc_q_vectors:
3431 ixgbe_reset_interrupt_capability(adapter);
021230d4 3432err_set_interrupt:
7a921c93
AD		 3433 return err;
3434}
3435
3436/**
3437 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3438 * @adapter: board private structure to clear interrupt scheme on
3439 *
3440 * We go through and clear interrupt specific resources and reset the structure
3441 * to pre-load conditions
3442 **/
3443void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3444{
021230d4
AV		 3445 kfree(adapter->tx_ring);
3446 kfree(adapter->rx_ring);
7a921c93
AD		 3447 adapter->tx_ring = NULL;
3448 adapter->rx_ring = NULL;
3449
3450 ixgbe_free_q_vectors(adapter);
3451 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 3452}
3453
c4900be0
DS		 3454/**
3455 * ixgbe_sfp_timer - worker thread to find a missing module
3456 * @data: pointer to our adapter struct
3457 **/
3458static void ixgbe_sfp_timer(unsigned long data)
3459{
3460 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3461
4df10466
JB		 3462 /*
3463 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 3464 * delays that sfp+ detection requires
3465 */
3466 schedule_work(&adapter->sfp_task);
3467}
3468
3469/**
3470 * ixgbe_sfp_task - worker thread to find a missing module
3471 * @work: pointer to work_struct containing our data
3472 **/
3473static void ixgbe_sfp_task(struct work_struct *work)
3474{
3475 struct ixgbe_adapter *adapter = container_of(work,
3476 struct ixgbe_adapter,
3477 sfp_task);
3478 struct ixgbe_hw *hw = &adapter->hw;
3479
3480 if ((hw->phy.type == ixgbe_phy_nl) &&
3481 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3482 s32 ret = hw->phy.ops.identify_sfp(hw);
3483 if (ret)
3484 goto reschedule;
3485 ret = hw->phy.ops.reset(hw);
3486 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3487 DPRINTK(PROBE, ERR, "failed to initialize because an "
3488 "unsupported SFP+ module type was detected.\n"
3489 "Reload the driver after installing a "
3490 "supported module.\n");
3491 unregister_netdev(adapter->netdev);
3492 } else {
3493 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3494 hw->phy.sfp_type);
3495 }
3496 /* don't need this routine any more */
3497 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3498 }
3499 return;
3500reschedule:
3501 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3502 mod_timer(&adapter->sfp_timer,
3503 round_jiffies(jiffies + (2 * HZ)));
3504}
3505
9a799d71
AK		 3506/**
3507 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3508 * @adapter: board private structure to initialize
3509 *
3510 * ixgbe_sw_init initializes the Adapter private data structure.
3511 * Fields are initialized based on PCI device information and
3512 * OS network device settings (MTU size).
3513 **/
3514static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3515{
3516 struct ixgbe_hw *hw = &adapter->hw;
3517 struct pci_dev *pdev = adapter->pdev;
021230d4 3518 unsigned int rss;
7a6b6f51 3519#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3520 int j;
3521 struct tc_configuration *tc;
3522#endif
021230d4 3523
c44ade9e
JB		 3524 /* PCI config space info */
3525
3526 hw->vendor_id = pdev->vendor;
3527 hw->device_id = pdev->device;
3528 hw->revision_id = pdev->revision;
3529 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3530 hw->subsystem_device_id = pdev->subsystem_device;
3531
021230d4
AV		 3532 /* Set capability flags */
3533 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3534 adapter->ring_feature[RING_F_RSS].indices = rss;
3535 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 3536 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 3537 if (hw->mac.type == ixgbe_mac_82598EB) {
3538 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3539 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 3540 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 3541 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 3542 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
f8212f97
AD		 3543 adapter->flags |= IXGBE_FLAG_RSC_CAPABLE;
3544 adapter->flags |= IXGBE_FLAG_RSC_ENABLED;
eacd73f7
YZ		 3545#ifdef IXGBE_FCOE
3546 adapter->flags |= IXGBE_FLAG_FCOE_ENABLED;
0331a832 3547 adapter->ring_feature[RING_F_FCOE].indices = IXGBE_FCRETA_SIZE;
eacd73f7 3548#endif /* IXGBE_FCOE */
f8212f97 3549 }
2f90b865 3550
7a6b6f51 3551#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3552 /* Configure DCB traffic classes */
3553 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3554 tc = &adapter->dcb_cfg.tc_config[j];
3555 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3556 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3557 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3558 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3559 tc->dcb_pfc = pfc_disabled;
3560 }
3561 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3562 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3563 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 3564 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 3565 adapter->dcb_cfg.round_robin_enable = false;
3566 adapter->dcb_set_bitmap = 0x00;
3567 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3568 adapter->ring_feature[RING_F_DCB].indices);
3569
3570#endif
9a799d71
AK		 3571
3572 /* default flow control settings */
cd7664f6 3573 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 3574 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 3575#ifdef CONFIG_DCB
3576 adapter->last_lfc_mode = hw->fc.current_mode;
3577#endif
2b9ade93
JB		 3578 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3579 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3580 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3581 hw->fc.send_xon = true;
71fd570b 3582 hw->fc.disable_fc_autoneg = false;
9a799d71 3583
30efa5a3
JB		 3584 /* enable itr by default in dynamic mode */
3585 adapter->itr_setting = 1;
3586 adapter->eitr_param = 20000;
3587
3588 /* set defaults for eitr in MegaBytes */
3589 adapter->eitr_low = 10;
3590 adapter->eitr_high = 20;
3591
3592 /* set default ring sizes */
3593 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3594 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3595
9a799d71 3596 /* initialize eeprom parameters */
c44ade9e 3597 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 3598 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3599 return -EIO;
3600 }
3601
021230d4 3602 /* enable rx csum by default */
9a799d71
AK		 3603 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3604
9a799d71
AK		 3605 set_bit(__IXGBE_DOWN, &adapter->state);
3606
3607 return 0;
3608}
3609
3610/**
3611 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3612 * @adapter: board private structure
3a581073 3613 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3614 *
3615 * Return 0 on success, negative on failure
3616 **/
3617int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 3618 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3619{
3620 struct pci_dev *pdev = adapter->pdev;
3621 int size;
3622
3a581073
JB		 3623 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3624 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 3625 if (!tx_ring->tx_buffer_info)
3626 goto err;
3a581073 3627 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 3628
3629 /* round up to nearest 4K */
12207e49 3630 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 3631 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 3632
3a581073
JB		 3633 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3634 &tx_ring->dma);
e01c31a5
JB		 3635 if (!tx_ring->desc)
3636 goto err;
9a799d71 3637
3a581073
JB		 3638 tx_ring->next_to_use = 0;
3639 tx_ring->next_to_clean = 0;
3640 tx_ring->work_limit = tx_ring->count;
9a799d71 3641 return 0;
e01c31a5
JB		 3642
3643err:
3644 vfree(tx_ring->tx_buffer_info);
3645 tx_ring->tx_buffer_info = NULL;
3646 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3647 "descriptor ring\n");
3648 return -ENOMEM;
9a799d71
AK		 3649}
3650
69888674
AD		 3651/**
3652 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3653 * @adapter: board private structure
3654 *
3655 * If this function returns with an error, then it's possible one or
3656 * more of the rings is populated (while the rest are not). It is the
3657 * callers duty to clean those orphaned rings.
3658 *
3659 * Return 0 on success, negative on failure
3660 **/
3661static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3662{
3663 int i, err = 0;
3664
3665 for (i = 0; i < adapter->num_tx_queues; i++) {
3666 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3667 if (!err)
3668 continue;
3669 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3670 break;
3671 }
3672
3673 return err;
3674}
3675
9a799d71
AK		 3676/**
3677 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3678 * @adapter: board private structure
3a581073 3679 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3680 *
3681 * Returns 0 on success, negative on failure
3682 **/
3683int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 3684 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3685{
3686 struct pci_dev *pdev = adapter->pdev;
021230d4 3687 int size;
9a799d71 3688
3a581073
JB		 3689 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3690 rx_ring->rx_buffer_info = vmalloc(size);
3691 if (!rx_ring->rx_buffer_info) {
9a799d71 3692 DPRINTK(PROBE, ERR,
b4617240 3693 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 3694 goto alloc_failed;
9a799d71 3695 }
3a581073 3696 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 3697
9a799d71 3698 /* Round up to nearest 4K */
3a581073
JB		 3699 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3700 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 3701
3a581073 3702 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 3703
3a581073 3704 if (!rx_ring->desc) {
9a799d71 3705 DPRINTK(PROBE, ERR,
b4617240 3706 "Memory allocation failed for the rx desc ring\n");
3a581073 3707 vfree(rx_ring->rx_buffer_info);
177db6ff 3708 goto alloc_failed;
9a799d71
AK		 3709 }
3710
3a581073
JB		 3711 rx_ring->next_to_clean = 0;
3712 rx_ring->next_to_use = 0;
9a799d71
AK		 3713
3714 return 0;
177db6ff
MC		 3715
3716alloc_failed:
177db6ff 3717 return -ENOMEM;
9a799d71
AK		 3718}
3719
69888674
AD		 3720/**
3721 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3722 * @adapter: board private structure
3723 *
3724 * If this function returns with an error, then it's possible one or
3725 * more of the rings is populated (while the rest are not). It is the
3726 * callers duty to clean those orphaned rings.
3727 *
3728 * Return 0 on success, negative on failure
3729 **/
3730
3731static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3732{
3733 int i, err = 0;
3734
3735 for (i = 0; i < adapter->num_rx_queues; i++) {
3736 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3737 if (!err)
3738 continue;
3739 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3740 break;
3741 }
3742
3743 return err;
3744}
3745
9a799d71
AK		 3746/**
3747 * ixgbe_free_tx_resources - Free Tx Resources per Queue
3748 * @adapter: board private structure
3749 * @tx_ring: Tx descriptor ring for a specific queue
3750 *
3751 * Free all transmit software resources
3752 **/
c431f97e
JB		 3753void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
3754 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3755{
3756 struct pci_dev *pdev = adapter->pdev;
3757
3758 ixgbe_clean_tx_ring(adapter, tx_ring);
3759
3760 vfree(tx_ring->tx_buffer_info);
3761 tx_ring->tx_buffer_info = NULL;
3762
3763 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
3764
3765 tx_ring->desc = NULL;
3766}
3767
3768/**
3769 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3770 * @adapter: board private structure
3771 *
3772 * Free all transmit software resources
3773 **/
3774static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
3775{
3776 int i;
3777
3778 for (i = 0; i < adapter->num_tx_queues; i++)
9891ca7c
JB		 3779 if (adapter->tx_ring[i].desc)
3780 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 3781}
3782
3783/**
b4617240 3784 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 3785 * @adapter: board private structure
3786 * @rx_ring: ring to clean the resources from
3787 *
3788 * Free all receive software resources
3789 **/
c431f97e
JB		 3790void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
3791 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3792{
3793 struct pci_dev *pdev = adapter->pdev;
3794
3795 ixgbe_clean_rx_ring(adapter, rx_ring);
3796
3797 vfree(rx_ring->rx_buffer_info);
3798 rx_ring->rx_buffer_info = NULL;
3799
3800 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
3801
3802 rx_ring->desc = NULL;
3803}
3804
3805/**
3806 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3807 * @adapter: board private structure
3808 *
3809 * Free all receive software resources
3810 **/
3811static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3812{
3813 int i;
3814
3815 for (i = 0; i < adapter->num_rx_queues; i++)
9891ca7c
JB		 3816 if (adapter->rx_ring[i].desc)
3817 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 3818}
3819
9a799d71
AK		 3820/**
3821 * ixgbe_change_mtu - Change the Maximum Transfer Unit
3822 * @netdev: network interface device structure
3823 * @new_mtu: new value for maximum frame size
3824 *
3825 * Returns 0 on success, negative on failure
3826 **/
3827static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3828{
3829 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3830 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3831
42c783c5
JB		 3832 /* MTU < 68 is an error and causes problems on some kernels */
3833 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 3834 return -EINVAL;
3835
021230d4 3836 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 3837 netdev->mtu, new_mtu);
021230d4 3838 /* must set new MTU before calling down or up */
9a799d71
AK		 3839 netdev->mtu = new_mtu;
3840
d4f80882
AV		 3841 if (netif_running(netdev))
3842 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3843
3844 return 0;
3845}
3846
3847/**
3848 * ixgbe_open - Called when a network interface is made active
3849 * @netdev: network interface device structure
3850 *
3851 * Returns 0 on success, negative value on failure
3852 *
3853 * The open entry point is called when a network interface is made
3854 * active by the system (IFF_UP). At this point all resources needed
3855 * for transmit and receive operations are allocated, the interrupt
3856 * handler is registered with the OS, the watchdog timer is started,
3857 * and the stack is notified that the interface is ready.
3858 **/
3859static int ixgbe_open(struct net_device *netdev)
3860{
3861 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3862 int err;
4bebfaa5
AK		 3863
3864 /* disallow open during test */
3865 if (test_bit(__IXGBE_TESTING, &adapter->state))
3866 return -EBUSY;
9a799d71 3867
54386467
JB		 3868 netif_carrier_off(netdev);
3869
9a799d71
AK		 3870 /* allocate transmit descriptors */
3871 err = ixgbe_setup_all_tx_resources(adapter);
3872 if (err)
3873 goto err_setup_tx;
3874
9a799d71
AK		 3875 /* allocate receive descriptors */
3876 err = ixgbe_setup_all_rx_resources(adapter);
3877 if (err)
3878 goto err_setup_rx;
3879
3880 ixgbe_configure(adapter);
3881
021230d4 3882 err = ixgbe_request_irq(adapter);
9a799d71
AK		 3883 if (err)
3884 goto err_req_irq;
3885
9a799d71
AK		 3886 err = ixgbe_up_complete(adapter);
3887 if (err)
3888 goto err_up;
3889
d55b53ff
JK		 3890 netif_tx_start_all_queues(netdev);
3891
9a799d71
AK		 3892 return 0;
3893
3894err_up:
5eba3699 3895 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3896 ixgbe_free_irq(adapter);
3897err_req_irq:
9a799d71 3898err_setup_rx:
a20a1199 3899 ixgbe_free_all_rx_resources(adapter);
9a799d71 3900err_setup_tx:
a20a1199 3901 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 3902 ixgbe_reset(adapter);
3903
3904 return err;
3905}
3906
3907/**
3908 * ixgbe_close - Disables a network interface
3909 * @netdev: network interface device structure
3910 *
3911 * Returns 0, this is not allowed to fail
3912 *
3913 * The close entry point is called when an interface is de-activated
3914 * by the OS. The hardware is still under the drivers control, but
3915 * needs to be disabled. A global MAC reset is issued to stop the
3916 * hardware, and all transmit and receive resources are freed.
3917 **/
3918static int ixgbe_close(struct net_device *netdev)
3919{
3920 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 3921
3922 ixgbe_down(adapter);
3923 ixgbe_free_irq(adapter);
3924
3925 ixgbe_free_all_tx_resources(adapter);
3926 ixgbe_free_all_rx_resources(adapter);
3927
5eba3699 3928 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3929
3930 return 0;
3931}
3932
b3c8b4ba
AD		 3933#ifdef CONFIG_PM
3934static int ixgbe_resume(struct pci_dev *pdev)
3935{
3936 struct net_device *netdev = pci_get_drvdata(pdev);
3937 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3938 u32 err;
3939
3940 pci_set_power_state(pdev, PCI_D0);
3941 pci_restore_state(pdev);
9ce77666 3942
3943 err = pci_enable_device_mem(pdev);
b3c8b4ba 3944 if (err) {
69888674 3945 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 3946 "suspend\n");
3947 return err;
3948 }
3949 pci_set_master(pdev);
3950
dd4d8ca6 3951 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 3952
3953 err = ixgbe_init_interrupt_scheme(adapter);
3954 if (err) {
3955 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3956 "device\n");
3957 return err;
3958 }
3959
b3c8b4ba
AD		 3960 ixgbe_reset(adapter);
3961
495dce12
WJP		 3962 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
3963
b3c8b4ba
AD		 3964 if (netif_running(netdev)) {
3965 err = ixgbe_open(adapter->netdev);
3966 if (err)
3967 return err;
3968 }
3969
3970 netif_device_attach(netdev);
3971
3972 return 0;
3973}
b3c8b4ba 3974#endif /* CONFIG_PM */
9d8d05ae
RW		 3975
3976static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 3977{
3978 struct net_device *netdev = pci_get_drvdata(pdev);
3979 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 3980 struct ixgbe_hw *hw = &adapter->hw;
3981 u32 ctrl, fctrl;
3982 u32 wufc = adapter->wol;
b3c8b4ba
AD		 3983#ifdef CONFIG_PM
3984 int retval = 0;
3985#endif
3986
3987 netif_device_detach(netdev);
3988
3989 if (netif_running(netdev)) {
3990 ixgbe_down(adapter);
3991 ixgbe_free_irq(adapter);
3992 ixgbe_free_all_tx_resources(adapter);
3993 ixgbe_free_all_rx_resources(adapter);
3994 }
7a921c93 3995 ixgbe_clear_interrupt_scheme(adapter);
b3c8b4ba
AD		 3996
3997#ifdef CONFIG_PM
3998 retval = pci_save_state(pdev);
3999 if (retval)
4000 return retval;
4df10466 4001
b3c8b4ba 4002#endif
e8e26350
PW		 4003 if (wufc) {
4004 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4005
e8e26350
PW		 4006 /* turn on all-multi mode if wake on multicast is enabled */
4007 if (wufc & IXGBE_WUFC_MC) {
4008 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4009 fctrl |= IXGBE_FCTRL_MPE;
4010 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4011 }
4012
4013 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4014 ctrl |= IXGBE_CTRL_GIO_DIS;
4015 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4016
4017 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4018 } else {
4019 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4020 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4021 }
4022
dd4d8ca6
DS		 4023 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4024 pci_wake_from_d3(pdev, true);
4025 else
4026 pci_wake_from_d3(pdev, false);
b3c8b4ba 4027
9d8d05ae
RW		 4028 *enable_wake = !!wufc;
4029
b3c8b4ba
AD		 4030 ixgbe_release_hw_control(adapter);
4031
4032 pci_disable_device(pdev);
4033
9d8d05ae
RW		 4034 return 0;
4035}
4036
4037#ifdef CONFIG_PM
4038static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4039{
4040 int retval;
4041 bool wake;
4042
4043 retval = __ixgbe_shutdown(pdev, &wake);
4044 if (retval)
4045 return retval;
4046
4047 if (wake) {
4048 pci_prepare_to_sleep(pdev);
4049 } else {
4050 pci_wake_from_d3(pdev, false);
4051 pci_set_power_state(pdev, PCI_D3hot);
4052 }
b3c8b4ba
AD		 4053
4054 return 0;
4055}
9d8d05ae 4056#endif /* CONFIG_PM */
b3c8b4ba
AD		 4057
4058static void ixgbe_shutdown(struct pci_dev *pdev)
4059{
9d8d05ae
RW		 4060 bool wake;
4061
4062 __ixgbe_shutdown(pdev, &wake);
4063
4064 if (system_state == SYSTEM_POWER_OFF) {
4065 pci_wake_from_d3(pdev, wake);
4066 pci_set_power_state(pdev, PCI_D3hot);
4067 }
b3c8b4ba
AD		 4068}
4069
9a799d71
AK		 4070/**
4071 * ixgbe_update_stats - Update the board statistics counters.
4072 * @adapter: board private structure
4073 **/
4074void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4075{
4076 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 4077 u64 total_mpc = 0;
4078 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71 4079
d51019a4 4080 if (hw->mac.type == ixgbe_mac_82599EB) {
f8212f97 4081 u64 rsc_count = 0;
d51019a4
PW		 4082 for (i = 0; i < 16; i++)
4083 adapter->hw_rx_no_dma_resources +=
4084 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
f8212f97
AD		 4085 for (i = 0; i < adapter->num_rx_queues; i++)
4086 rsc_count += adapter->rx_ring[i].rsc_count;
4087 adapter->rsc_count = rsc_count;
d51019a4
PW		 4088 }
4089
9a799d71 4090 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 4091 for (i = 0; i < 8; i++) {
4092 /* for packet buffers not used, the register should read 0 */
4093 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4094 missed_rx += mpc;
4095 adapter->stats.mpc[i] += mpc;
4096 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 4097 if (hw->mac.type == ixgbe_mac_82598EB)
4098 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 4099 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4100 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4101 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4102 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 4103 if (hw->mac.type == ixgbe_mac_82599EB) {
4104 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4105 IXGBE_PXONRXCNT(i));
4106 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4107 IXGBE_PXOFFRXCNT(i));
4108 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 4109 } else {
4110 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4111 IXGBE_PXONRXC(i));
4112 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4113 IXGBE_PXOFFRXC(i));
4114 }
2f90b865
AD		 4115 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4116 IXGBE_PXONTXC(i));
2f90b865 4117 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 4118 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 4119 }
4120 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4121 /* work around hardware counting issue */
4122 adapter->stats.gprc -= missed_rx;
4123
4124 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350
PW		 4125 if (hw->mac.type == ixgbe_mac_82599EB) {
4126 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4127 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
4128 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4129 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
4130 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4131 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4132 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4133 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
6d45522c
YZ		 4134#ifdef IXGBE_FCOE
4135 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4136 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4137 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4138 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4139 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4140 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4141#endif /* IXGBE_FCOE */
e8e26350
PW		 4142 } else {
4143 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4144 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4145 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4146 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4147 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4148 }
9a799d71
AK		 4149 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4150 adapter->stats.bprc += bprc;
4151 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 4152 if (hw->mac.type == ixgbe_mac_82598EB)
4153 adapter->stats.mprc -= bprc;
9a799d71
AK		 4154 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4155 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4156 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4157 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4158 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4159 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4160 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 4161 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 4162 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4163 adapter->stats.lxontxc += lxon;
4164 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4165 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 4166 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4167 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 4168 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4169 /*
4170 * 82598 errata - tx of flow control packets is included in tx counters
4171 */
4172 xon_off_tot = lxon + lxoff;
4173 adapter->stats.gptc -= xon_off_tot;
4174 adapter->stats.mptc -= xon_off_tot;
4175 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 4176 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4177 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4178 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 4179 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4180 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 4181 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 4182 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4183 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4184 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4185 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4186 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 4187 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4188
4189 /* Fill out the OS statistics structure */
9a799d71
AK		 4190 adapter->net_stats.multicast = adapter->stats.mprc;
4191
4192 /* Rx Errors */
4193 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
b4617240 4194 adapter->stats.rlec;
9a799d71
AK		 4195 adapter->net_stats.rx_dropped = 0;
4196 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4197 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 4198 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 4199}
4200
4201/**
4202 * ixgbe_watchdog - Timer Call-back
4203 * @data: pointer to adapter cast into an unsigned long
4204 **/
4205static void ixgbe_watchdog(unsigned long data)
4206{
4207 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee
JB		 4208 struct ixgbe_hw *hw = &adapter->hw;
4209
4210 /* Do the watchdog outside of interrupt context due to the lovely
4211 * delays that some of the newer hardware requires */
4212 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
22d5a71b
JB		 4213 u64 eics = 0;
4214 int i;
4215
4216 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++)
c9c7d2e5 4217 eics |= ((u64)1 << i);
22d5a71b 4218
cf8280ee 4219 /* Cause software interrupt to ensure rx rings are cleaned */
22d5a71b
JB		 4220 switch (hw->mac.type) {
4221 case ixgbe_mac_82598EB:
4222 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4223 IXGBE_WRITE_REG(hw, IXGBE_EICS, (u32)eics);
4224 } else {
4225 /*
4226 * for legacy and MSI interrupts don't set any
4227 * bits that are enabled for EIAM, because this
4228 * operation would set *both* EIMS and EICS for
4229 * any bit in EIAM
4230 */
4231 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4232 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4233 }
4234 break;
4235 case ixgbe_mac_82599EB:
4236 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
835462fc
NS		 4237 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(0),
4238 (u32)(eics & 0xFFFFFFFF));
22d5a71b 4239 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(1),
22d5a71b
JB		 4240 (u32)(eics >> 32));
4241 } else {
4242 /*
4243 * for legacy and MSI interrupts don't set any
4244 * bits that are enabled for EIAM, because this
4245 * operation would set *both* EIMS and EICS for
4246 * any bit in EIAM
4247 */
4248 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4249 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4250 }
4251 break;
4252 default:
4253 break;
cf8280ee
JB		 4254 }
4255 /* Reset the timer */
4256 mod_timer(&adapter->watchdog_timer,
4257 round_jiffies(jiffies + 2 * HZ));
4258 }
9a799d71 4259
cf8280ee
JB		 4260 schedule_work(&adapter->watchdog_task);
4261}
4262
e8e26350
PW		 4263/**
4264 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4265 * @work: pointer to work_struct containing our data
4266 **/
4267static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4268{
4269 struct ixgbe_adapter *adapter = container_of(work,
4270 struct ixgbe_adapter,
4271 multispeed_fiber_task);
4272 struct ixgbe_hw *hw = &adapter->hw;
4273 u32 autoneg;
4274
4275 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4276 if (hw->mac.ops.get_link_capabilities)
4277 hw->mac.ops.get_link_capabilities(hw, &autoneg,
4278 &hw->mac.autoneg);
4279 if (hw->mac.ops.setup_link_speed)
4280 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
4281 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4282 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4283}
4284
4285/**
4286 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4287 * @work: pointer to work_struct containing our data
4288 **/
4289static void ixgbe_sfp_config_module_task(struct work_struct *work)
4290{
4291 struct ixgbe_adapter *adapter = container_of(work,
4292 struct ixgbe_adapter,
4293 sfp_config_module_task);
4294 struct ixgbe_hw *hw = &adapter->hw;
4295 u32 err;
4296
4297 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4298 err = hw->phy.ops.identify_sfp(hw);
4299 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4300 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
4301 ixgbe_down(adapter);
4302 return;
4303 }
4304 hw->mac.ops.setup_sfp(hw);
4305
8d1c3c07 4306 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 4307 /* This will also work for DA Twinax connections */
4308 schedule_work(&adapter->multispeed_fiber_task);
4309 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4310}
4311
cf8280ee 4312/**
69888674
AD		 4313 * ixgbe_watchdog_task - worker thread to bring link up
4314 * @work: pointer to work_struct containing our data
cf8280ee
JB		 4315 **/
4316static void ixgbe_watchdog_task(struct work_struct *work)
4317{
4318 struct ixgbe_adapter *adapter = container_of(work,
4319 struct ixgbe_adapter,
4320 watchdog_task);
4321 struct net_device *netdev = adapter->netdev;
4322 struct ixgbe_hw *hw = &adapter->hw;
4323 u32 link_speed = adapter->link_speed;
4324 bool link_up = adapter->link_up;
bc59fcda
NS		 4325 int i;
4326 struct ixgbe_ring *tx_ring;
4327 int some_tx_pending = 0;
cf8280ee
JB		 4328
4329 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4330
4331 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4332 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 4333 if (link_up) {
4334#ifdef CONFIG_DCB
4335 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4336 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4337 hw->mac.ops.setup_fc(hw, i);
4338 } else {
4339 hw->mac.ops.setup_fc(hw, 0);
4340 }
4341#else
4342 hw->mac.ops.setup_fc(hw, 0);
4343#endif
4344 }
4345
cf8280ee
JB		 4346 if (link_up ||
4347 time_after(jiffies, (adapter->link_check_timeout +
4348 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 4349 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 4350 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 4351 }
4352 adapter->link_up = link_up;
4353 adapter->link_speed = link_speed;
4354 }
9a799d71
AK		 4355
4356 if (link_up) {
4357 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 4358 bool flow_rx, flow_tx;
4359
4360 if (hw->mac.type == ixgbe_mac_82599EB) {
4361 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4362 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4363 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
4364 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
4365 } else {
4366 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4367 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4368 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
4369 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
4370 }
4371
a46e534b
JK		 4372 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4373 "Flow Control: %s\n",
4374 netdev->name,
4375 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4376 "10 Gbps" :
4377 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4378 "1 Gbps" : "unknown speed")),
e8e26350
PW		 4379 ((flow_rx && flow_tx) ? "RX/TX" :
4380 (flow_rx ? "RX" :
4381 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 4382
4383 netif_carrier_on(netdev);
9a799d71
AK		 4384 } else {
4385 /* Force detection of hung controller */
4386 adapter->detect_tx_hung = true;
4387 }
4388 } else {
cf8280ee
JB		 4389 adapter->link_up = false;
4390 adapter->link_speed = 0;
9a799d71 4391 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 4392 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4393 netdev->name);
9a799d71 4394 netif_carrier_off(netdev);
9a799d71
AK		 4395 }
4396 }
4397
bc59fcda
NS		 4398 if (!netif_carrier_ok(netdev)) {
4399 for (i = 0; i < adapter->num_tx_queues; i++) {
4400 tx_ring = &adapter->tx_ring[i];
4401 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4402 some_tx_pending = 1;
4403 break;
4404 }
4405 }
4406
4407 if (some_tx_pending) {
4408 /* We've lost link, so the controller stops DMA,
4409 * but we've got queued Tx work that's never going
4410 * to get done, so reset controller to flush Tx.
4411 * (Do the reset outside of interrupt context).
4412 */
4413 schedule_work(&adapter->reset_task);
4414 }
4415 }
4416
9a799d71 4417 ixgbe_update_stats(adapter);
cf8280ee 4418 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 4419}
4420
9a799d71 4421static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 4422 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4423 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 4424{
4425 struct ixgbe_adv_tx_context_desc *context_desc;
4426 unsigned int i;
4427 int err;
4428 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 4429 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4430 u32 mss_l4len_idx, l4len;
9a799d71
AK		 4431
4432 if (skb_is_gso(skb)) {
4433 if (skb_header_cloned(skb)) {
4434 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4435 if (err)
4436 return err;
4437 }
4438 l4len = tcp_hdrlen(skb);
4439 *hdr_len += l4len;
4440
8327d000 4441 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 4442 struct iphdr *iph = ip_hdr(skb);
4443 iph->tot_len = 0;
4444 iph->check = 0;
4445 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 4446 iph->daddr, 0,
4447 IPPROTO_TCP,
4448 0);
9a799d71
AK		 4449 adapter->hw_tso_ctxt++;
4450 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4451 ipv6_hdr(skb)->payload_len = 0;
4452 tcp_hdr(skb)->check =
4453 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 4454 &ipv6_hdr(skb)->daddr,
4455 0, IPPROTO_TCP, 0);
9a799d71
AK		 4456 adapter->hw_tso6_ctxt++;
4457 }
4458
4459 i = tx_ring->next_to_use;
4460
4461 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4462 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4463
4464 /* VLAN MACLEN IPLEN */
4465 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4466 vlan_macip_lens |=
4467 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4468 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 4469 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4470 *hdr_len += skb_network_offset(skb);
4471 vlan_macip_lens |=
4472 (skb_transport_header(skb) - skb_network_header(skb));
4473 *hdr_len +=
4474 (skb_transport_header(skb) - skb_network_header(skb));
4475 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4476 context_desc->seqnum_seed = 0;
4477
4478 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 4479 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 4480 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 4481
8327d000 4482 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4483 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4484 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4485 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4486
4487 /* MSS L4LEN IDX */
9f8cdf4f 4488 mss_l4len_idx =
9a799d71
AK		 4489 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4490 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 4491 /* use index 1 for TSO */
4492 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4493 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4494
4495 tx_buffer_info->time_stamp = jiffies;
4496 tx_buffer_info->next_to_watch = i;
4497
4498 i++;
4499 if (i == tx_ring->count)
4500 i = 0;
4501 tx_ring->next_to_use = i;
4502
4503 return true;
4504 }
4505 return false;
4506}
4507
4508static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 4509 struct ixgbe_ring *tx_ring,
4510 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 4511{
4512 struct ixgbe_adv_tx_context_desc *context_desc;
4513 unsigned int i;
4514 struct ixgbe_tx_buffer *tx_buffer_info;
4515 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4516
4517 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4518 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4519 i = tx_ring->next_to_use;
4520 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4521 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4522
4523 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4524 vlan_macip_lens |=
4525 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4526 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 4527 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4528 if (skb->ip_summed == CHECKSUM_PARTIAL)
4529 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 4530 skb_network_header(skb));
9a799d71
AK		 4531
4532 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4533 context_desc->seqnum_seed = 0;
4534
4535 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 4536 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 4537
4538 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71 4539 switch (skb->protocol) {
09640e63 4540 case cpu_to_be16(ETH_P_IP):
9a799d71 4541 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 4542 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4543 type_tucmd_mlhl |=
b4617240 4544 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4545 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4546 type_tucmd_mlhl |=
4547 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4548 break;
09640e63 4549 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 4550 /* XXX what about other V6 headers?? */
4551 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4552 type_tucmd_mlhl |=
b4617240 4553 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4554 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4555 type_tucmd_mlhl |=
4556 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4557 break;
41825d71
AK		 4558 default:
4559 if (unlikely(net_ratelimit())) {
4560 DPRINTK(PROBE, WARNING,
4561 "partial checksum but proto=%x!\n",
4562 skb->protocol);
4563 }
4564 break;
4565 }
9a799d71
AK		 4566 }
4567
4568 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 4569 /* use index zero for tx checksum offload */
9a799d71
AK		 4570 context_desc->mss_l4len_idx = 0;
4571
4572 tx_buffer_info->time_stamp = jiffies;
4573 tx_buffer_info->next_to_watch = i;
9f8cdf4f 4574
9a799d71
AK		 4575 adapter->hw_csum_tx_good++;
4576 i++;
4577 if (i == tx_ring->count)
4578 i = 0;
4579 tx_ring->next_to_use = i;
4580
4581 return true;
4582 }
9f8cdf4f 4583
9a799d71
AK		 4584 return false;
4585}
4586
4587static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 4588 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 4589 struct sk_buff *skb, u32 tx_flags,
4590 unsigned int first)
9a799d71
AK		 4591{
4592 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 4593 unsigned int len;
4594 unsigned int total = skb->len;
9a799d71
AK		 4595 unsigned int offset = 0, size, count = 0, i;
4596 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4597 unsigned int f;
44df32c5 4598 dma_addr_t *map;
9a799d71
AK		 4599
4600 i = tx_ring->next_to_use;
4601
44df32c5
AD		 4602 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4603 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4604 return 0;
4605 }
4606
4607 map = skb_shinfo(skb)->dma_maps;
4608
eacd73f7
YZ		 4609 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4610 /* excluding fcoe_crc_eof for FCoE */
4611 total -= sizeof(struct fcoe_crc_eof);
4612
4613 len = min(skb_headlen(skb), total);
9a799d71
AK		 4614 while (len) {
4615 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4616 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4617
4618 tx_buffer_info->length = size;
44df32c5 4619 tx_buffer_info->dma = map[0] + offset;
9a799d71
AK		 4620 tx_buffer_info->time_stamp = jiffies;
4621 tx_buffer_info->next_to_watch = i;
4622
4623 len -= size;
eacd73f7 4624 total -= size;
9a799d71
AK		 4625 offset += size;
4626 count++;
44df32c5
AD		 4627
4628 if (len) {
4629 i++;
4630 if (i == tx_ring->count)
4631 i = 0;
4632 }
9a799d71
AK		 4633 }
4634
4635 for (f = 0; f < nr_frags; f++) {
4636 struct skb_frag_struct *frag;
4637
4638 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 4639 len = min((unsigned int)frag->size, total);
44df32c5 4640 offset = 0;
9a799d71
AK		 4641
4642 while (len) {
44df32c5
AD		 4643 i++;
4644 if (i == tx_ring->count)
4645 i = 0;
4646
9a799d71
AK		 4647 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4648 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4649
4650 tx_buffer_info->length = size;
44df32c5 4651 tx_buffer_info->dma = map[f + 1] + offset;
9a799d71
AK		 4652 tx_buffer_info->time_stamp = jiffies;
4653 tx_buffer_info->next_to_watch = i;
4654
4655 len -= size;
eacd73f7 4656 total -= size;
9a799d71
AK		 4657 offset += size;
4658 count++;
9a799d71 4659 }
eacd73f7
YZ		 4660 if (total == 0)
4661 break;
9a799d71 4662 }
44df32c5 4663
9a799d71
AK		 4664 tx_ring->tx_buffer_info[i].skb = skb;
4665 tx_ring->tx_buffer_info[first].next_to_watch = i;
4666
4667 return count;
4668}
4669
4670static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 4671 struct ixgbe_ring *tx_ring,
4672 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 4673{
4674 union ixgbe_adv_tx_desc *tx_desc = NULL;
4675 struct ixgbe_tx_buffer *tx_buffer_info;
4676 u32 olinfo_status = 0, cmd_type_len = 0;
4677 unsigned int i;
4678 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4679
4680 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4681
4682 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4683
4684 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4685 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4686
4687 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4688 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4689
4690 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4691 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 4692
4eeae6fd
PW		 4693 /* use index 1 context for tso */
4694 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4695 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4696 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 4697 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 4698
4699 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4700 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4701 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 4702
eacd73f7
YZ		 4703 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
4704 olinfo_status |= IXGBE_ADVTXD_CC;
4705 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4706 if (tx_flags & IXGBE_TX_FLAGS_FSO)
4707 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4708 }
4709
9a799d71
AK		 4710 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4711
4712 i = tx_ring->next_to_use;
4713 while (count--) {
4714 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4715 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4716 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4717 tx_desc->read.cmd_type_len =
b4617240 4718 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 4719 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 4720 i++;
4721 if (i == tx_ring->count)
4722 i = 0;
4723 }
4724
4725 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
4726
4727 /*
4728 * Force memory writes to complete before letting h/w
4729 * know there are new descriptors to fetch. (Only
4730 * applicable for weak-ordered memory model archs,
4731 * such as IA-64).
4732 */
4733 wmb();
4734
4735 tx_ring->next_to_use = i;
4736 writel(i, adapter->hw.hw_addr + tx_ring->tail);
4737}
4738
e092be60 4739static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 4740 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 4741{
4742 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4743
30eba97a 4744 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 4745 /* Herbert's original patch had:
4746 * smp_mb__after_netif_stop_queue();
4747 * but since that doesn't exist yet, just open code it. */
4748 smp_mb();
4749
4750 /* We need to check again in a case another CPU has just
4751 * made room available. */
4752 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
4753 return -EBUSY;
4754
4755 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 4756 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 4757 ++adapter->restart_queue;
4758 return 0;
4759}
4760
4761static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 4762 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 4763{
4764 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
4765 return 0;
4766 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
4767}
4768
09a3b1f8
SH		 4769static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
4770{
4771 struct ixgbe_adapter *adapter = netdev_priv(dev);
4772
4773 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4774 return 0; /* All traffic should default to class 0 */
4775
4776 return skb_tx_hash(dev, skb);
4777}
4778
9a799d71
AK		 4779static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
4780{
4781 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4782 struct ixgbe_ring *tx_ring;
9a799d71
AK		 4783 unsigned int first;
4784 unsigned int tx_flags = 0;
30eba97a
AV		 4785 u8 hdr_len = 0;
4786 int r_idx = 0, tso;
9a799d71
AK		 4787 int count = 0;
4788 unsigned int f;
9f8cdf4f 4789
95615d90 4790 r_idx = skb->queue_mapping;
30eba97a 4791 tx_ring = &adapter->tx_ring[r_idx];
9a799d71 4792
9f8cdf4f
JB		 4793 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
4794 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 4795 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4796 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
4797 tx_flags |= (skb->queue_mapping << 13);
4798 }
4799 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4800 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4801 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4802 tx_flags |= (skb->queue_mapping << 13);
9f8cdf4f
JB		 4803 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4804 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 4805 }
eacd73f7
YZ		 4806
4807 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
4808 (skb->protocol == htons(ETH_P_FCOE)))
4809 tx_flags |= IXGBE_TX_FLAGS_FCOE;
4810
4811 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 4812 if (skb_is_gso(skb) ||
4813 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 4814 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
4815 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 4816 count++;
4817
9f8cdf4f
JB		 4818 count += TXD_USE_COUNT(skb_headlen(skb));
4819 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 4820 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4821
e092be60 4822 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 4823 adapter->tx_busy++;
9a799d71
AK		 4824 return NETDEV_TX_BUSY;
4825 }
9a799d71 4826
9a799d71 4827 first = tx_ring->next_to_use;
eacd73f7
YZ		 4828 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
4829#ifdef IXGBE_FCOE
4830 /* setup tx offload for FCoE */
4831 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4832 if (tso < 0) {
4833 dev_kfree_skb_any(skb);
4834 return NETDEV_TX_OK;
4835 }
4836 if (tso)
4837 tx_flags |= IXGBE_TX_FLAGS_FSO;
4838#endif /* IXGBE_FCOE */
4839 } else {
4840 if (skb->protocol == htons(ETH_P_IP))
4841 tx_flags |= IXGBE_TX_FLAGS_IPV4;
4842 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4843 if (tso < 0) {
4844 dev_kfree_skb_any(skb);
4845 return NETDEV_TX_OK;
4846 }
9a799d71 4847
eacd73f7
YZ		 4848 if (tso)
4849 tx_flags |= IXGBE_TX_FLAGS_TSO;
4850 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
4851 (skb->ip_summed == CHECKSUM_PARTIAL))
4852 tx_flags |= IXGBE_TX_FLAGS_CSUM;
4853 }
9a799d71 4854
eacd73f7 4855 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5
AD		 4856 if (count) {
4857 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
4858 hdr_len);
4859 netdev->trans_start = jiffies;
4860 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 4861
44df32c5
AD		 4862 } else {
4863 dev_kfree_skb_any(skb);
4864 tx_ring->tx_buffer_info[first].time_stamp = 0;
4865 tx_ring->next_to_use = first;
4866 }
9a799d71
AK		 4867
4868 return NETDEV_TX_OK;
4869}
4870
4871/**
4872 * ixgbe_get_stats - Get System Network Statistics
4873 * @netdev: network interface device structure
4874 *
4875 * Returns the address of the device statistics structure.
4876 * The statistics are actually updated from the timer callback.
4877 **/
4878static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
4879{
4880 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4881
4882 /* only return the current stats */
4883 return &adapter->net_stats;
4884}
4885
4886/**
4887 * ixgbe_set_mac - Change the Ethernet Address of the NIC
4888 * @netdev: network interface device structure
4889 * @p: pointer to an address structure
4890 *
4891 * Returns 0 on success, negative on failure
4892 **/
4893static int ixgbe_set_mac(struct net_device *netdev, void *p)
4894{
4895 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 4896 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 4897 struct sockaddr *addr = p;
4898
4899 if (!is_valid_ether_addr(addr->sa_data))
4900 return -EADDRNOTAVAIL;
4901
4902 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 4903 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 4904
b4617240 4905 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 4906
4907 return 0;
4908}
4909
6b73e10d
BH		 4910static int
4911ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
4912{
4913 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4914 struct ixgbe_hw *hw = &adapter->hw;
4915 u16 value;
4916 int rc;
4917
4918 if (prtad != hw->phy.mdio.prtad)
4919 return -EINVAL;
4920 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
4921 if (!rc)
4922 rc = value;
4923 return rc;
4924}
4925
4926static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
4927 u16 addr, u16 value)
4928{
4929 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4930 struct ixgbe_hw *hw = &adapter->hw;
4931
4932 if (prtad != hw->phy.mdio.prtad)
4933 return -EINVAL;
4934 return hw->phy.ops.write_reg(hw, addr, devad, value);
4935}
4936
4937static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
4938{
4939 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4940
4941 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
4942}
4943
0365e6e4
PW		 4944/**
4945 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
4946 * netdev->dev_addr_list
4947 * @netdev: network interface device structure
4948 *
4949 * Returns non-zero on failure
4950 **/
4951static int ixgbe_add_sanmac_netdev(struct net_device *dev)
4952{
4953 int err = 0;
4954 struct ixgbe_adapter *adapter = netdev_priv(dev);
4955 struct ixgbe_mac_info *mac = &adapter->hw.mac;
4956
4957 if (is_valid_ether_addr(mac->san_addr)) {
4958 rtnl_lock();
4959 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
4960 rtnl_unlock();
4961 }
4962 return err;
4963}
4964
4965/**
4966 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
4967 * netdev->dev_addr_list
4968 * @netdev: network interface device structure
4969 *
4970 * Returns non-zero on failure
4971 **/
4972static int ixgbe_del_sanmac_netdev(struct net_device *dev)
4973{
4974 int err = 0;
4975 struct ixgbe_adapter *adapter = netdev_priv(dev);
4976 struct ixgbe_mac_info *mac = &adapter->hw.mac;
4977
4978 if (is_valid_ether_addr(mac->san_addr)) {
4979 rtnl_lock();
4980 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
4981 rtnl_unlock();
4982 }
4983 return err;
4984}
4985
9a799d71
AK		 4986#ifdef CONFIG_NET_POLL_CONTROLLER
4987/*
4988 * Polling 'interrupt' - used by things like netconsole to send skbs
4989 * without having to re-enable interrupts. It's not called while
4990 * the interrupt routine is executing.
4991 */
4992static void ixgbe_netpoll(struct net_device *netdev)
4993{
4994 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4995
4996 disable_irq(adapter->pdev->irq);
4997 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
4998 ixgbe_intr(adapter->pdev->irq, netdev);
4999 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5000 enable_irq(adapter->pdev->irq);
5001}
5002#endif
5003
0edc3527
SH		 5004static const struct net_device_ops ixgbe_netdev_ops = {
5005 .ndo_open = ixgbe_open,
5006 .ndo_stop = ixgbe_close,
00829823 5007 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 5008 .ndo_select_queue = ixgbe_select_queue,
0edc3527 5009 .ndo_get_stats = ixgbe_get_stats,
e90d400c 5010 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 5011 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5012 .ndo_validate_addr = eth_validate_addr,
5013 .ndo_set_mac_address = ixgbe_set_mac,
5014 .ndo_change_mtu = ixgbe_change_mtu,
5015 .ndo_tx_timeout = ixgbe_tx_timeout,
5016 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5017 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5018 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 5019 .ndo_do_ioctl = ixgbe_ioctl,
0edc3527
SH		 5020#ifdef CONFIG_NET_POLL_CONTROLLER
5021 .ndo_poll_controller = ixgbe_netpoll,
5022#endif
332d4a7d
YZ		 5023#ifdef IXGBE_FCOE
5024 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5025 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5026#endif /* IXGBE_FCOE */
0edc3527
SH		 5027};
5028
9a799d71
AK		 5029/**
5030 * ixgbe_probe - Device Initialization Routine
5031 * @pdev: PCI device information struct
5032 * @ent: entry in ixgbe_pci_tbl
5033 *
5034 * Returns 0 on success, negative on failure
5035 *
5036 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5037 * The OS initialization, configuring of the adapter private structure,
5038 * and a hardware reset occur.
5039 **/
5040static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 5041 const struct pci_device_id *ent)
9a799d71
AK		 5042{
5043 struct net_device *netdev;
5044 struct ixgbe_adapter *adapter = NULL;
5045 struct ixgbe_hw *hw;
5046 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 5047 static int cards_found;
5048 int i, err, pci_using_dac;
eacd73f7
YZ		 5049#ifdef IXGBE_FCOE
5050 u16 device_caps;
5051#endif
c44ade9e 5052 u32 part_num, eec;
9a799d71 5053
9ce77666 5054 err = pci_enable_device_mem(pdev);
9a799d71
AK		 5055 if (err)
5056 return err;
5057
6a35528a
YH		 5058 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5059 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
9a799d71
AK		 5060 pci_using_dac = 1;
5061 } else {
284901a9 5062 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5063 if (err) {
284901a9 5064 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5065 if (err) {
b4617240
PW		 5066 dev_err(&pdev->dev, "No usable DMA "
5067 "configuration, aborting\n");
9a799d71
AK		 5068 goto err_dma;
5069 }
5070 }
5071 pci_using_dac = 0;
5072 }
5073
9ce77666 5074 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5075 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 5076 if (err) {
9ce77666 5077 dev_err(&pdev->dev,
5078 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 5079 goto err_pci_reg;
5080 }
5081
6fabd715
PWJ		 5082 err = pci_enable_pcie_error_reporting(pdev);
5083 if (err) {
5084 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
5085 "0x%x\n", err);
5086 /* non-fatal, continue */
5087 }
5088
9a799d71 5089 pci_set_master(pdev);
fb3b27bc 5090 pci_save_state(pdev);
9a799d71 5091
30eba97a 5092 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 5093 if (!netdev) {
5094 err = -ENOMEM;
5095 goto err_alloc_etherdev;
5096 }
5097
9a799d71
AK		 5098 SET_NETDEV_DEV(netdev, &pdev->dev);
5099
5100 pci_set_drvdata(pdev, netdev);
5101 adapter = netdev_priv(netdev);
5102
5103 adapter->netdev = netdev;
5104 adapter->pdev = pdev;
5105 hw = &adapter->hw;
5106 hw->back = adapter;
5107 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5108
05857980
JK		 5109 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5110 pci_resource_len(pdev, 0));
9a799d71
AK		 5111 if (!hw->hw_addr) {
5112 err = -EIO;
5113 goto err_ioremap;
5114 }
5115
5116 for (i = 1; i <= 5; i++) {
5117 if (pci_resource_len(pdev, i) == 0)
5118 continue;
5119 }
5120
0edc3527 5121 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 5122 ixgbe_set_ethtool_ops(netdev);
9a799d71 5123 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 5124 strcpy(netdev->name, pci_name(pdev));
5125
9a799d71
AK		 5126 adapter->bd_number = cards_found;
5127
9a799d71
AK		 5128 /* Setup hw api */
5129 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 5130 hw->mac.type = ii->mac;
9a799d71 5131
c44ade9e
JB		 5132 /* EEPROM */
5133 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5134 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5135 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5136 if (!(eec & (1 << 8)))
5137 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5138
5139 /* PHY */
5140 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 5141 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 5142 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5143 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5144 hw->phy.mdio.mmds = 0;
5145 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5146 hw->phy.mdio.dev = netdev;
5147 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5148 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 5149
5150 /* set up this timer and work struct before calling get_invariants
5151 * which might start the timer
5152 */
5153 init_timer(&adapter->sfp_timer);
5154 adapter->sfp_timer.function = &ixgbe_sfp_timer;
5155 adapter->sfp_timer.data = (unsigned long) adapter;
5156
5157 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 5158
e8e26350
PW		 5159 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5160 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5161
5162 /* a new SFP+ module arrival, called from GPI SDP2 context */
5163 INIT_WORK(&adapter->sfp_config_module_task,
5164 ixgbe_sfp_config_module_task);
5165
9a799d71 5166 err = ii->get_invariants(hw);
c4900be0
DS		 5167 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5168 /* start a kernel thread to watch for a module to arrive */
5169 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5170 mod_timer(&adapter->sfp_timer,
5171 round_jiffies(jiffies + (2 * HZ)));
5172 err = 0;
5173 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5174 DPRINTK(PROBE, ERR, "failed to load because an "
5175 "unsupported SFP+ module type was detected.\n");
9a799d71 5176 goto err_hw_init;
c4900be0
DS		 5177 } else if (err) {
5178 goto err_hw_init;
5179 }
9a799d71
AK		 5180
5181 /* setup the private structure */
5182 err = ixgbe_sw_init(adapter);
5183 if (err)
5184 goto err_sw_init;
5185
bf069c97
DS		 5186 /*
5187 * If there is a fan on this device and it has failed log the
5188 * failure.
5189 */
5190 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5191 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5192 if (esdp & IXGBE_ESDP_SDP1)
5193 DPRINTK(PROBE, CRIT,
5194 "Fan has stopped, replace the adapter\n");
5195 }
5196
c44ade9e
JB		 5197 /* reset_hw fills in the perm_addr as well */
5198 err = hw->mac.ops.reset_hw(hw);
04f165ef
PW		 5199 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5200 dev_err(&adapter->pdev->dev, "failed to load because an "
5201 "unsupported SFP+ module type was detected.\n");
5202 goto err_sw_init;
5203 } else if (err) {
c44ade9e
JB		 5204 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5205 goto err_sw_init;
5206 }
5207
9a799d71 5208 netdev->features = NETIF_F_SG |
b4617240
PW		 5209 NETIF_F_IP_CSUM |
5210 NETIF_F_HW_VLAN_TX |
5211 NETIF_F_HW_VLAN_RX |
5212 NETIF_F_HW_VLAN_FILTER;
9a799d71 5213
e9990a9c 5214 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 5215 netdev->features |= NETIF_F_TSO;
9a799d71 5216 netdev->features |= NETIF_F_TSO6;
78b6f4ce 5217 netdev->features |= NETIF_F_GRO;
ad31c402 5218
45a5ead0
JB		 5219 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5220 netdev->features |= NETIF_F_SCTP_CSUM;
5221
ad31c402
JK		 5222 netdev->vlan_features |= NETIF_F_TSO;
5223 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 5224 netdev->vlan_features |= NETIF_F_IP_CSUM;
ad31c402
JK		 5225 netdev->vlan_features |= NETIF_F_SG;
5226
2f90b865
AD		 5227 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5228 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5229
7a6b6f51 5230#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5231 netdev->dcbnl_ops = &dcbnl_ops;
5232#endif
5233
eacd73f7
YZ		 5234#ifdef IXGBE_FCOE
5235 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
5236 if (hw->mac.ops.get_device_caps) {
5237 hw->mac.ops.get_device_caps(hw, &device_caps);
5238 if (!(device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)) {
5239 netdev->features |= NETIF_F_FCOE_CRC;
5240 netdev->features |= NETIF_F_FSO;
332d4a7d 5241 netdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX - 1;
eacd73f7
YZ		 5242 } else {
5243 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5244 }
5245 }
5246 }
5247#endif /* IXGBE_FCOE */
9a799d71
AK		 5248 if (pci_using_dac)
5249 netdev->features |= NETIF_F_HIGHDMA;
5250
f8212f97
AD		 5251 if (adapter->flags & IXGBE_FLAG_RSC_ENABLED)
5252 netdev->features |= NETIF_F_LRO;
5253
9a799d71 5254 /* make sure the EEPROM is good */
c44ade9e 5255 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 5256 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5257 err = -EIO;
5258 goto err_eeprom;
5259 }
5260
5261 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5262 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5263
c44ade9e
JB		 5264 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5265 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 5266 err = -EIO;
5267 goto err_eeprom;
5268 }
5269
5270 init_timer(&adapter->watchdog_timer);
5271 adapter->watchdog_timer.function = &ixgbe_watchdog;
5272 adapter->watchdog_timer.data = (unsigned long)adapter;
5273
5274 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 5275 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 5276
021230d4
AV		 5277 err = ixgbe_init_interrupt_scheme(adapter);
5278 if (err)
5279 goto err_sw_init;
9a799d71 5280
e8e26350
PW		 5281 switch (pdev->device) {
5282 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 5283 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5284 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 5285 break;
5286 default:
5287 adapter->wol = 0;
5288 break;
5289 }
5290 device_init_wakeup(&adapter->pdev->dev, true);
5291 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5292
04f165ef
PW		 5293 /* pick up the PCI bus settings for reporting later */
5294 hw->mac.ops.get_bus_info(hw);
5295
9a799d71 5296 /* print bus type/speed/width info */
7c510e4b 5297 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 5298 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5299 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5300 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5301 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5302 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 5303 "Unknown"),
7c510e4b 5304 netdev->dev_addr);
c44ade9e 5305 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 5306 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5307 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5308 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5309 (part_num >> 8), (part_num & 0xff));
5310 else
5311 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5312 hw->mac.type, hw->phy.type,
5313 (part_num >> 8), (part_num & 0xff));
9a799d71 5314
e8e26350 5315 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 5316 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 5317 "this card is not sufficient for optimal "
5318 "performance.\n");
0c254d86 5319 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 5320 "PCI-Express slot is required.\n");
0c254d86
AK		 5321 }
5322
34b0368c
PWJ		 5323 /* save off EEPROM version number */
5324 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5325
9a799d71 5326 /* reset the hardware with the new settings */
c44ade9e
JB		 5327 hw->mac.ops.start_hw(hw);
5328
9a799d71
AK		 5329 strcpy(netdev->name, "eth%d");
5330 err = register_netdev(netdev);
5331 if (err)
5332 goto err_register;
5333
54386467
JB		 5334 /* carrier off reporting is important to ethtool even BEFORE open */
5335 netif_carrier_off(netdev);
5336
5dd2d332 5337#ifdef CONFIG_IXGBE_DCA
652f093f 5338 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd
JC		 5339 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5340 /* always use CB2 mode, difference is masked
5341 * in the CB driver */
5342 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
5343 ixgbe_setup_dca(adapter);
5344 }
5345#endif
0365e6e4
PW		 5346 /* add san mac addr to netdev */
5347 ixgbe_add_sanmac_netdev(netdev);
9a799d71
AK		 5348
5349 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5350 cards_found++;
5351 return 0;
5352
5353err_register:
5eba3699 5354 ixgbe_release_hw_control(adapter);
9a799d71 5355err_hw_init:
7a921c93 5356 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 5357err_sw_init:
5358err_eeprom:
c4900be0
DS		 5359 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5360 del_timer_sync(&adapter->sfp_timer);
5361 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5362 cancel_work_sync(&adapter->multispeed_fiber_task);
5363 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 5364 iounmap(hw->hw_addr);
5365err_ioremap:
5366 free_netdev(netdev);
5367err_alloc_etherdev:
9ce77666 5368 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5369 IORESOURCE_MEM));
9a799d71
AK		 5370err_pci_reg:
5371err_dma:
5372 pci_disable_device(pdev);
5373 return err;
5374}
5375
5376/**
5377 * ixgbe_remove - Device Removal Routine
5378 * @pdev: PCI device information struct
5379 *
5380 * ixgbe_remove is called by the PCI subsystem to alert the driver
5381 * that it should release a PCI device. The could be caused by a
5382 * Hot-Plug event, or because the driver is going to be removed from
5383 * memory.
5384 **/
5385static void __devexit ixgbe_remove(struct pci_dev *pdev)
5386{
5387 struct net_device *netdev = pci_get_drvdata(pdev);
5388 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715 5389 int err;
9a799d71
AK		 5390
5391 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 5392 /* clear the module not found bit to make sure the worker won't
5393 * reschedule
5394 */
5395 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 5396 del_timer_sync(&adapter->watchdog_timer);
5397
c4900be0
DS		 5398 del_timer_sync(&adapter->sfp_timer);
5399 cancel_work_sync(&adapter->watchdog_task);
5400 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5401 cancel_work_sync(&adapter->multispeed_fiber_task);
5402 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 5403 flush_scheduled_work();
5404
5dd2d332 5405#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5406 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5407 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5408 dca_remove_requester(&pdev->dev);
5409 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5410 }
5411
5412#endif
332d4a7d
YZ		 5413#ifdef IXGBE_FCOE
5414 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5415 ixgbe_cleanup_fcoe(adapter);
5416
5417#endif /* IXGBE_FCOE */
0365e6e4
PW		 5418
5419 /* remove the added san mac */
5420 ixgbe_del_sanmac_netdev(netdev);
5421
c4900be0
DS		 5422 if (netdev->reg_state == NETREG_REGISTERED)
5423 unregister_netdev(netdev);
9a799d71 5424
7a921c93 5425 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 5426
021230d4 5427 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5428
5429 iounmap(adapter->hw.hw_addr);
9ce77666 5430 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5431 IORESOURCE_MEM));
9a799d71 5432
021230d4 5433 DPRINTK(PROBE, INFO, "complete\n");
021230d4 5434
9a799d71
AK		 5435 free_netdev(netdev);
5436
6fabd715
PWJ		 5437 err = pci_disable_pcie_error_reporting(pdev);
5438 if (err)
5439 dev_err(&pdev->dev,
5440 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5441
9a799d71
AK		 5442 pci_disable_device(pdev);
5443}
5444
5445/**
5446 * ixgbe_io_error_detected - called when PCI error is detected
5447 * @pdev: Pointer to PCI device
5448 * @state: The current pci connection state
5449 *
5450 * This function is called after a PCI bus error affecting
5451 * this device has been detected.
5452 */
5453static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 5454 pci_channel_state_t state)
9a799d71
AK		 5455{
5456 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5457 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5458
5459 netif_device_detach(netdev);
5460
3044b8d1
BL		 5461 if (state == pci_channel_io_perm_failure)
5462 return PCI_ERS_RESULT_DISCONNECT;
5463
9a799d71
AK		 5464 if (netif_running(netdev))
5465 ixgbe_down(adapter);
5466 pci_disable_device(pdev);
5467
b4617240 5468 /* Request a slot reset. */
9a799d71
AK		 5469 return PCI_ERS_RESULT_NEED_RESET;
5470}
5471
5472/**
5473 * ixgbe_io_slot_reset - called after the pci bus has been reset.
5474 * @pdev: Pointer to PCI device
5475 *
5476 * Restart the card from scratch, as if from a cold-boot.
5477 */
5478static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5479{
5480 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5481 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 5482 pci_ers_result_t result;
5483 int err;
9a799d71 5484
9ce77666 5485 if (pci_enable_device_mem(pdev)) {
9a799d71 5486 DPRINTK(PROBE, ERR,
b4617240 5487 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 5488 result = PCI_ERS_RESULT_DISCONNECT;
5489 } else {
5490 pci_set_master(pdev);
5491 pci_restore_state(pdev);
9a799d71 5492
dd4d8ca6 5493 pci_wake_from_d3(pdev, false);
9a799d71 5494
6fabd715 5495 ixgbe_reset(adapter);
88512539 5496 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 5497 result = PCI_ERS_RESULT_RECOVERED;
5498 }
5499
5500 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5501 if (err) {
5502 dev_err(&pdev->dev,
5503 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5504 /* non-fatal, continue */
5505 }
9a799d71 5506
6fabd715 5507 return result;
9a799d71
AK		 5508}
5509
5510/**
5511 * ixgbe_io_resume - called when traffic can start flowing again.
5512 * @pdev: Pointer to PCI device
5513 *
5514 * This callback is called when the error recovery driver tells us that
5515 * its OK to resume normal operation.
5516 */
5517static void ixgbe_io_resume(struct pci_dev *pdev)
5518{
5519 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5520 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5521
5522 if (netif_running(netdev)) {
5523 if (ixgbe_up(adapter)) {
5524 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5525 return;
5526 }
5527 }
5528
5529 netif_device_attach(netdev);
9a799d71
AK		 5530}
5531
5532static struct pci_error_handlers ixgbe_err_handler = {
5533 .error_detected = ixgbe_io_error_detected,
5534 .slot_reset = ixgbe_io_slot_reset,
5535 .resume = ixgbe_io_resume,
5536};
5537
5538static struct pci_driver ixgbe_driver = {
5539 .name = ixgbe_driver_name,
5540 .id_table = ixgbe_pci_tbl,
5541 .probe = ixgbe_probe,
5542 .remove = __devexit_p(ixgbe_remove),
5543#ifdef CONFIG_PM
5544 .suspend = ixgbe_suspend,
5545 .resume = ixgbe_resume,
5546#endif
5547 .shutdown = ixgbe_shutdown,
5548 .err_handler = &ixgbe_err_handler
5549};
5550
5551/**
5552 * ixgbe_init_module - Driver Registration Routine
5553 *
5554 * ixgbe_init_module is the first routine called when the driver is
5555 * loaded. All it does is register with the PCI subsystem.
5556 **/
5557static int __init ixgbe_init_module(void)
5558{
5559 int ret;
5560 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5561 ixgbe_driver_string, ixgbe_driver_version);
5562
5563 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5564
5dd2d332 5565#ifdef CONFIG_IXGBE_DCA
bd0362dd 5566 dca_register_notify(&dca_notifier);
bd0362dd 5567#endif
5dd2d332 5568
9a799d71
AK		 5569 ret = pci_register_driver(&ixgbe_driver);
5570 return ret;
5571}
b4617240 5572
9a799d71
AK		 5573module_init(ixgbe_init_module);
5574
5575/**
5576 * ixgbe_exit_module - Driver Exit Cleanup Routine
5577 *
5578 * ixgbe_exit_module is called just before the driver is removed
5579 * from memory.
5580 **/
5581static void __exit ixgbe_exit_module(void)
5582{
5dd2d332 5583#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5584 dca_unregister_notify(&dca_notifier);
5585#endif
9a799d71
AK		 5586 pci_unregister_driver(&ixgbe_driver);
5587}
bd0362dd 5588
5dd2d332 5589#ifdef CONFIG_IXGBE_DCA
bd0362dd 5590static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 5591 void *p)
bd0362dd
JC		 5592{
5593 int ret_val;
5594
5595 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 5596 __ixgbe_notify_dca);
bd0362dd
JC		 5597
5598 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5599}
b453368d 5600
5dd2d332 5601#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 5602#ifdef DEBUG
5603/**
5604 * ixgbe_get_hw_dev_name - return device name string
5605 * used by hardware layer to print debugging information
5606 **/
5607char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5608{
5609 struct ixgbe_adapter *adapter = hw->back;
5610 return adapter->netdev->name;
5611}
bd0362dd 5612
b453368d 5613#endif
9a799d71
AK		 5614module_exit(ixgbe_exit_module);
5615
5616/* ixgbe_main.c */
kernel source for telekom puls (alcatel/mediatek)