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ipv4: __mkroute_output() speedup
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71 38#include <linux/ipv6.h>
5a0e3ad6 39#include <linux/slab.h>
9a799d71
AK		 40#include <net/checksum.h>
41#include <net/ip6_checksum.h>
42#include <linux/ethtool.h>
43#include <linux/if_vlan.h>
eacd73f7 44#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 45
46#include "ixgbe.h"
47#include "ixgbe_common.h"
ee5f784a 48#include "ixgbe_dcb_82599.h"
1cdd1ec8 49#include "ixgbe_sriov.h"
9a799d71
AK		 50
51char ixgbe_driver_name[] = "ixgbe";
9c8eb720 52static const char ixgbe_driver_string[] =
e8e9f696 53 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 54
99faf68e 55#define DRV_VERSION "2.0.84-k2"
9c8eb720 56const char ixgbe_driver_version[] = DRV_VERSION;
8c47eaa7 57static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
9a799d71
AK		 58
59static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 60 [board_82598] = &ixgbe_82598_info,
e8e26350 61 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 62};
63
64/* ixgbe_pci_tbl - PCI Device ID Table
65 *
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
a3aa1884 72static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
74 board_82598 },
9a799d71 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 76 board_82598 },
9a799d71 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 78 board_82598 },
0befdb3e
JB		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
80 board_82598 },
3845bec0
PWJ		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
82 board_82598 },
9a799d71 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 84 board_82598 },
8d792cd9
JB		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
86 board_82598 },
c4900be0
DS		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
90 board_82598 },
b95f5fcb
JB		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
92 board_82598 },
c4900be0
DS		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
94 board_82598 },
2f21bdd3
DS		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
96 board_82598 },
e8e26350
PW		 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
98 board_82599 },
1fcf03e6
PWJ		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
100 board_82599 },
74757d49
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
102 board_82599 },
e8e26350
PW		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
104 board_82599 },
38ad1c8e
DS		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
106 board_82599 },
dbfec662
DS		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
108 board_82599 },
8911184f
PWJ		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
110 board_82599 },
119fc60a
MC		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
112 board_82599 },
312eb931
DS		 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
114 board_82599 },
9a799d71
AK		 115
116 /* required last entry */
117 {0, }
118};
119MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
120
5dd2d332 121#ifdef CONFIG_IXGBE_DCA
bd0362dd 122static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 123 void *p);
bd0362dd
JC		 124static struct notifier_block dca_notifier = {
125 .notifier_call = ixgbe_notify_dca,
126 .next = NULL,
127 .priority = 0
128};
129#endif
130
1cdd1ec8
GR		 131#ifdef CONFIG_PCI_IOV
132static unsigned int max_vfs;
133module_param(max_vfs, uint, 0);
e8e9f696
JP		 134MODULE_PARM_DESC(max_vfs,
135 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 136#endif /* CONFIG_PCI_IOV */
137
9a799d71
AK		 138MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
139MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
140MODULE_LICENSE("GPL");
141MODULE_VERSION(DRV_VERSION);
142
143#define DEFAULT_DEBUG_LEVEL_SHIFT 3
144
1cdd1ec8
GR		 145static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
146{
147 struct ixgbe_hw *hw = &adapter->hw;
148 u32 gcr;
149 u32 gpie;
150 u32 vmdctl;
151
152#ifdef CONFIG_PCI_IOV
153 /* disable iov and allow time for transactions to clear */
154 pci_disable_sriov(adapter->pdev);
155#endif
156
157 /* turn off device IOV mode */
158 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
159 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
160 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
161 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
162 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
163 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
164
165 /* set default pool back to 0 */
166 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
167 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
168 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
169
170 /* take a breather then clean up driver data */
171 msleep(100);
e8e9f696
JP		 172
173 kfree(adapter->vfinfo);
1cdd1ec8
GR		 174 adapter->vfinfo = NULL;
175
176 adapter->num_vfs = 0;
177 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
178}
179
dcd79aeb
TI		 180struct ixgbe_reg_info {
181 u32 ofs;
182 char *name;
183};
184
185static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
186
187 /* General Registers */
188 {IXGBE_CTRL, "CTRL"},
189 {IXGBE_STATUS, "STATUS"},
190 {IXGBE_CTRL_EXT, "CTRL_EXT"},
191
192 /* Interrupt Registers */
193 {IXGBE_EICR, "EICR"},
194
195 /* RX Registers */
196 {IXGBE_SRRCTL(0), "SRRCTL"},
197 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
198 {IXGBE_RDLEN(0), "RDLEN"},
199 {IXGBE_RDH(0), "RDH"},
200 {IXGBE_RDT(0), "RDT"},
201 {IXGBE_RXDCTL(0), "RXDCTL"},
202 {IXGBE_RDBAL(0), "RDBAL"},
203 {IXGBE_RDBAH(0), "RDBAH"},
204
205 /* TX Registers */
206 {IXGBE_TDBAL(0), "TDBAL"},
207 {IXGBE_TDBAH(0), "TDBAH"},
208 {IXGBE_TDLEN(0), "TDLEN"},
209 {IXGBE_TDH(0), "TDH"},
210 {IXGBE_TDT(0), "TDT"},
211 {IXGBE_TXDCTL(0), "TXDCTL"},
212
213 /* List Terminator */
214 {}
215};
216
217
218/*
219 * ixgbe_regdump - register printout routine
220 */
221static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
222{
223 int i = 0, j = 0;
224 char rname[16];
225 u32 regs[64];
226
227 switch (reginfo->ofs) {
228 case IXGBE_SRRCTL(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
231 break;
232 case IXGBE_DCA_RXCTRL(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
235 break;
236 case IXGBE_RDLEN(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
239 break;
240 case IXGBE_RDH(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
243 break;
244 case IXGBE_RDT(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
247 break;
248 case IXGBE_RXDCTL(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
251 break;
252 case IXGBE_RDBAL(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
255 break;
256 case IXGBE_RDBAH(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
259 break;
260 case IXGBE_TDBAL(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
263 break;
264 case IXGBE_TDBAH(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
267 break;
268 case IXGBE_TDLEN(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
271 break;
272 case IXGBE_TDH(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
275 break;
276 case IXGBE_TDT(0):
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
279 break;
280 case IXGBE_TXDCTL(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
283 break;
284 default:
c7689578 285 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 286 IXGBE_READ_REG(hw, reginfo->ofs));
287 return;
288 }
289
290 for (i = 0; i < 8; i++) {
291 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 292 pr_err("%-15s", rname);
dcd79aeb 293 for (j = 0; j < 8; j++)
c7689578
JP		 294 pr_cont(" %08x", regs[i*8+j]);
295 pr_cont("\n");
dcd79aeb
TI		 296 }
297
298}
299
300/*
301 * ixgbe_dump - Print registers, tx-rings and rx-rings
302 */
303static void ixgbe_dump(struct ixgbe_adapter *adapter)
304{
305 struct net_device *netdev = adapter->netdev;
306 struct ixgbe_hw *hw = &adapter->hw;
307 struct ixgbe_reg_info *reginfo;
308 int n = 0;
309 struct ixgbe_ring *tx_ring;
310 struct ixgbe_tx_buffer *tx_buffer_info;
311 union ixgbe_adv_tx_desc *tx_desc;
312 struct my_u0 { u64 a; u64 b; } *u0;
313 struct ixgbe_ring *rx_ring;
314 union ixgbe_adv_rx_desc *rx_desc;
315 struct ixgbe_rx_buffer *rx_buffer_info;
316 u32 staterr;
317 int i = 0;
318
319 if (!netif_msg_hw(adapter))
320 return;
321
322 /* Print netdevice Info */
323 if (netdev) {
324 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 325 pr_info("Device Name state "
dcd79aeb 326 "trans_start last_rx\n");
c7689578
JP		 327 pr_info("%-15s %016lX %016lX %016lX\n",
328 netdev->name,
329 netdev->state,
330 netdev->trans_start,
331 netdev->last_rx);
dcd79aeb
TI		 332 }
333
334 /* Print Registers */
335 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 336 pr_info(" Register Name Value\n");
dcd79aeb
TI		 337 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
338 reginfo->name; reginfo++) {
339 ixgbe_regdump(hw, reginfo);
340 }
341
342 /* Print TX Ring Summary */
343 if (!netdev || !netif_running(netdev))
344 goto exit;
345
346 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 347 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 348 for (n = 0; n < adapter->num_tx_queues; n++) {
349 tx_ring = adapter->tx_ring[n];
350 tx_buffer_info =
351 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
c7689578 352 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
dcd79aeb
TI		 353 n, tx_ring->next_to_use, tx_ring->next_to_clean,
354 (u64)tx_buffer_info->dma,
355 tx_buffer_info->length,
356 tx_buffer_info->next_to_watch,
357 (u64)tx_buffer_info->time_stamp);
358 }
359
360 /* Print TX Rings */
361 if (!netif_msg_tx_done(adapter))
362 goto rx_ring_summary;
363
364 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
365
366 /* Transmit Descriptor Formats
367 *
368 * Advanced Transmit Descriptor
369 * +--------------------------------------------------------------+
370 * 0 | Buffer Address [63:0] |
371 * +--------------------------------------------------------------+
372 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
373 * +--------------------------------------------------------------+
374 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
375 */
376
377 for (n = 0; n < adapter->num_tx_queues; n++) {
378 tx_ring = adapter->tx_ring[n];
c7689578
JP		 379 pr_info("------------------------------------\n");
380 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
381 pr_info("------------------------------------\n");
382 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 383 "[PlPOIdStDDt Ln] [bi->dma ] "
384 "leng ntw timestamp bi->skb\n");
385
386 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 387 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 388 tx_buffer_info = &tx_ring->tx_buffer_info[i];
389 u0 = (struct my_u0 *)tx_desc;
c7689578 390 pr_info("T [0x%03X] %016llX %016llX %016llX"
dcd79aeb
TI		 391 " %04X %3X %016llX %p", i,
392 le64_to_cpu(u0->a),
393 le64_to_cpu(u0->b),
394 (u64)tx_buffer_info->dma,
395 tx_buffer_info->length,
396 tx_buffer_info->next_to_watch,
397 (u64)tx_buffer_info->time_stamp,
398 tx_buffer_info->skb);
399 if (i == tx_ring->next_to_use &&
400 i == tx_ring->next_to_clean)
c7689578 401 pr_cont(" NTC/U\n");
dcd79aeb 402 else if (i == tx_ring->next_to_use)
c7689578 403 pr_cont(" NTU\n");
dcd79aeb 404 else if (i == tx_ring->next_to_clean)
c7689578 405 pr_cont(" NTC\n");
dcd79aeb 406 else
c7689578 407 pr_cont("\n");
dcd79aeb
TI		 408
409 if (netif_msg_pktdata(adapter) &&
410 tx_buffer_info->dma != 0)
411 print_hex_dump(KERN_INFO, "",
412 DUMP_PREFIX_ADDRESS, 16, 1,
413 phys_to_virt(tx_buffer_info->dma),
414 tx_buffer_info->length, true);
415 }
416 }
417
418 /* Print RX Rings Summary */
419rx_ring_summary:
420 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 421 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 422 for (n = 0; n < adapter->num_rx_queues; n++) {
423 rx_ring = adapter->rx_ring[n];
c7689578
JP		 424 pr_info("%5d %5X %5X\n",
425 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 426 }
427
428 /* Print RX Rings */
429 if (!netif_msg_rx_status(adapter))
430 goto exit;
431
432 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
433
434 /* Advanced Receive Descriptor (Read) Format
435 * 63 1 0
436 * +-----------------------------------------------------+
437 * 0 | Packet Buffer Address [63:1] |A0/NSE|
438 * +----------------------------------------------+------+
439 * 8 | Header Buffer Address [63:1] | DD |
440 * +-----------------------------------------------------+
441 *
442 *
443 * Advanced Receive Descriptor (Write-Back) Format
444 *
445 * 63 48 47 32 31 30 21 20 16 15 4 3 0
446 * +------------------------------------------------------+
447 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
448 * | Checksum Ident | | | | Type | Type |
449 * +------------------------------------------------------+
450 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
451 * +------------------------------------------------------+
452 * 63 48 47 32 31 20 19 0
453 */
454 for (n = 0; n < adapter->num_rx_queues; n++) {
455 rx_ring = adapter->rx_ring[n];
c7689578
JP		 456 pr_info("------------------------------------\n");
457 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
458 pr_info("------------------------------------\n");
459 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 460 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
461 "<-- Adv Rx Read format\n");
c7689578 462 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 463 "[vl er S cks ln] ---------------- [bi->skb] "
464 "<-- Adv Rx Write-Back format\n");
465
466 for (i = 0; i < rx_ring->count; i++) {
467 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 468 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 469 u0 = (struct my_u0 *)rx_desc;
470 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
471 if (staterr & IXGBE_RXD_STAT_DD) {
472 /* Descriptor Done */
c7689578 473 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 474 "%016llX ---------------- %p", i,
475 le64_to_cpu(u0->a),
476 le64_to_cpu(u0->b),
477 rx_buffer_info->skb);
478 } else {
c7689578 479 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 480 "%016llX %016llX %p", i,
481 le64_to_cpu(u0->a),
482 le64_to_cpu(u0->b),
483 (u64)rx_buffer_info->dma,
484 rx_buffer_info->skb);
485
486 if (netif_msg_pktdata(adapter)) {
487 print_hex_dump(KERN_INFO, "",
488 DUMP_PREFIX_ADDRESS, 16, 1,
489 phys_to_virt(rx_buffer_info->dma),
490 rx_ring->rx_buf_len, true);
491
492 if (rx_ring->rx_buf_len
493 < IXGBE_RXBUFFER_2048)
494 print_hex_dump(KERN_INFO, "",
495 DUMP_PREFIX_ADDRESS, 16, 1,
496 phys_to_virt(
497 rx_buffer_info->page_dma +
498 rx_buffer_info->page_offset
499 ),
500 PAGE_SIZE/2, true);
501 }
502 }
503
504 if (i == rx_ring->next_to_use)
c7689578 505 pr_cont(" NTU\n");
dcd79aeb 506 else if (i == rx_ring->next_to_clean)
c7689578 507 pr_cont(" NTC\n");
dcd79aeb 508 else
c7689578 509 pr_cont("\n");
dcd79aeb
TI		 510
511 }
512 }
513
514exit:
515 return;
516}
517
5eba3699
AV		 518static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
519{
520 u32 ctrl_ext;
521
522 /* Let firmware take over control of h/w */
523 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
524 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 525 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 526}
527
528static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
529{
530 u32 ctrl_ext;
531
532 /* Let firmware know the driver has taken over */
533 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
534 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 535 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 536}
9a799d71 537
e8e26350
PW		 538/*
539 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
540 * @adapter: pointer to adapter struct
541 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
542 * @queue: queue to map the corresponding interrupt to
543 * @msix_vector: the vector to map to the corresponding queue
544 *
545 */
546static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 547 u8 queue, u8 msix_vector)
9a799d71
AK		 548{
549 u32 ivar, index;
e8e26350
PW		 550 struct ixgbe_hw *hw = &adapter->hw;
551 switch (hw->mac.type) {
552 case ixgbe_mac_82598EB:
553 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
554 if (direction == -1)
555 direction = 0;
556 index = (((direction * 64) + queue) >> 2) & 0x1F;
557 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
558 ivar &= ~(0xFF << (8 * (queue & 0x3)));
559 ivar |= (msix_vector << (8 * (queue & 0x3)));
560 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
561 break;
562 case ixgbe_mac_82599EB:
563 if (direction == -1) {
564 /* other causes */
565 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
566 index = ((queue & 1) * 8);
567 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
568 ivar &= ~(0xFF << index);
569 ivar |= (msix_vector << index);
570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
571 break;
572 } else {
573 /* tx or rx causes */
574 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
575 index = ((16 * (queue & 1)) + (8 * direction));
576 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
577 ivar &= ~(0xFF << index);
578 ivar |= (msix_vector << index);
579 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
580 break;
581 }
582 default:
583 break;
584 }
9a799d71
AK		 585}
586
fe49f04a 587static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 588 u64 qmask)
fe49f04a
AD		 589{
590 u32 mask;
591
592 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
593 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
594 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
595 } else {
596 mask = (qmask & 0xFFFFFFFF);
597 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
598 mask = (qmask >> 32);
599 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
600 }
601}
602
84418e3b 603void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
e8e9f696
JP		 604 struct ixgbe_tx_buffer
605 *tx_buffer_info)
9a799d71 606{
e5a43549
AD		 607 if (tx_buffer_info->dma) {
608 if (tx_buffer_info->mapped_as_page)
1b507730 609 dma_unmap_page(&adapter->pdev->dev,
e5a43549
AD		 610 tx_buffer_info->dma,
611 tx_buffer_info->length,
1b507730 612 DMA_TO_DEVICE);
e5a43549 613 else
1b507730 614 dma_unmap_single(&adapter->pdev->dev,
e5a43549
AD		 615 tx_buffer_info->dma,
616 tx_buffer_info->length,
1b507730 617 DMA_TO_DEVICE);
e5a43549
AD		 618 tx_buffer_info->dma = 0;
619 }
9a799d71
AK		 620 if (tx_buffer_info->skb) {
621 dev_kfree_skb_any(tx_buffer_info->skb);
622 tx_buffer_info->skb = NULL;
623 }
44df32c5 624 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 625 /* tx_buffer_info must be completely set up in the transmit path */
626}
627
26f23d82 628/**
7483d9dd 629 * ixgbe_tx_xon_state - check the tx ring xon state
26f23d82
YZ		 630 * @adapter: the ixgbe adapter
631 * @tx_ring: the corresponding tx_ring
632 *
633 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
634 * corresponding TC of this tx_ring when checking TFCS.
635 *
7483d9dd 636 * Returns : true if in xon state (currently not paused)
26f23d82 637 */
7483d9dd 638static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
e8e9f696 639 struct ixgbe_ring *tx_ring)
26f23d82 640{
26f23d82
YZ		 641 u32 txoff = IXGBE_TFCS_TXOFF;
642
643#ifdef CONFIG_IXGBE_DCB
ca739481 644 if (adapter->dcb_cfg.pfc_mode_enable) {
30b76832 645 int tc;
26f23d82
YZ		 646 int reg_idx = tx_ring->reg_idx;
647 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
648
6837e895
PW		 649 switch (adapter->hw.mac.type) {
650 case ixgbe_mac_82598EB:
26f23d82
YZ		 651 tc = reg_idx >> 2;
652 txoff = IXGBE_TFCS_TXOFF0;
6837e895
PW		 653 break;
654 case ixgbe_mac_82599EB:
26f23d82
YZ		 655 tc = 0;
656 txoff = IXGBE_TFCS_TXOFF;
657 if (dcb_i == 8) {
658 /* TC0, TC1 */
659 tc = reg_idx >> 5;
660 if (tc == 2) /* TC2, TC3 */
661 tc += (reg_idx - 64) >> 4;
662 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
663 tc += 1 + ((reg_idx - 96) >> 3);
664 } else if (dcb_i == 4) {
665 /* TC0, TC1 */
666 tc = reg_idx >> 6;
667 if (tc == 1) {
668 tc += (reg_idx - 64) >> 5;
669 if (tc == 2) /* TC2, TC3 */
670 tc += (reg_idx - 96) >> 4;
671 }
672 }
6837e895
PW		 673 break;
674 default:
675 tc = 0;
26f23d82
YZ		 676 }
677 txoff <<= tc;
678 }
679#endif
680 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
681}
682
9a799d71 683static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
e8e9f696
JP		 684 struct ixgbe_ring *tx_ring,
685 unsigned int eop)
9a799d71 686{
e01c31a5 687 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 688
9a799d71 689 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 690 * check with the clearing of time_stamp and movement of eop */
9a799d71 691 adapter->detect_tx_hung = false;
44df32c5 692 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71 693 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
7483d9dd 694 ixgbe_tx_xon_state(adapter, tx_ring)) {
9a799d71 695 /* detected Tx unit hang */
e01c31a5 696 union ixgbe_adv_tx_desc *tx_desc;
31f05a2d 697 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
396e799c 698 e_err(drv, "Detected Tx Unit Hang\n"
849c4542
ET		 699 " Tx Queue <%d>\n"
700 " TDH, TDT <%x>, <%x>\n"
701 " next_to_use <%x>\n"
702 " next_to_clean <%x>\n"
703 "tx_buffer_info[next_to_clean]\n"
704 " time_stamp <%lx>\n"
705 " jiffies <%lx>\n",
706 tx_ring->queue_index,
707 IXGBE_READ_REG(hw, tx_ring->head),
708 IXGBE_READ_REG(hw, tx_ring->tail),
709 tx_ring->next_to_use, eop,
710 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 711 return true;
712 }
713
714 return false;
715}
716
b4617240
PW		 717#define IXGBE_MAX_TXD_PWR 14
718#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 719
720/* Tx Descriptors needed, worst case */
721#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
722 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
723#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 724 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 725
e01c31a5
JB		 726static void ixgbe_tx_timeout(struct net_device *netdev);
727
9a799d71
AK		 728/**
729 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 730 * @q_vector: structure containing interrupt and ring information
e01c31a5 731 * @tx_ring: tx ring to clean
9a799d71 732 **/
fe49f04a 733static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 734 struct ixgbe_ring *tx_ring)
9a799d71 735{
fe49f04a 736 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 737 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 738 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
739 struct ixgbe_tx_buffer *tx_buffer_info;
740 unsigned int i, eop, count = 0;
e01c31a5 741 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 742
743 i = tx_ring->next_to_clean;
12207e49 744 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 745 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 746
747 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 748 (count < tx_ring->work_limit)) {
12207e49 749 bool cleaned = false;
2d0bb1c1 750 rmb(); /* read buffer_info after eop_desc */
12207e49
PWJ		 751 for ( ; !cleaned; count++) {
752 struct sk_buff *skb;
31f05a2d 753 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71 754 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 755 cleaned = (i == eop);
e01c31a5 756 skb = tx_buffer_info->skb;
9a799d71 757
12207e49 758 if (cleaned && skb) {
e092be60 759 unsigned int segs, bytecount;
3d8fd385 760 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 761
762 /* gso_segs is currently only valid for tcp */
e092be60 763 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 764#ifdef IXGBE_FCOE
765 /* adjust for FCoE Sequence Offload */
766 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
767 && (skb->protocol == htons(ETH_P_FCOE)) &&
768 skb_is_gso(skb)) {
769 hlen = skb_transport_offset(skb) +
770 sizeof(struct fc_frame_header) +
771 sizeof(struct fcoe_crc_eof);
772 segs = DIV_ROUND_UP(skb->len - hlen,
773 skb_shinfo(skb)->gso_size);
774 }
775#endif /* IXGBE_FCOE */
e092be60 776 /* multiply data chunks by size of headers */
3d8fd385 777 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 778 total_packets += segs;
779 total_bytes += bytecount;
e092be60 780 }
e01c31a5 781
9a799d71 782 ixgbe_unmap_and_free_tx_resource(adapter,
e8e9f696 783 tx_buffer_info);
9a799d71 784
12207e49
PWJ		 785 tx_desc->wb.status = 0;
786
9a799d71
AK		 787 i++;
788 if (i == tx_ring->count)
789 i = 0;
e01c31a5 790 }
12207e49
PWJ		 791
792 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 793 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 794 }
795
9a799d71
AK		 796 tx_ring->next_to_clean = i;
797
e092be60 798#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5 799 if (unlikely(count && netif_carrier_ok(netdev) &&
e8e9f696 800 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 801 /* Make sure that anybody stopping the queue after this
802 * sees the new next_to_clean.
803 */
804 smp_mb();
30eba97a
AV		 805 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
806 !test_bit(__IXGBE_DOWN, &adapter->state)) {
807 netif_wake_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 808 ++tx_ring->restart_queue;
30eba97a 809 }
e092be60 810 }
9a799d71 811
e01c31a5
JB		 812 if (adapter->detect_tx_hung) {
813 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
814 /* schedule immediate reset if we believe we hung */
396e799c
ET		 815 e_info(probe, "tx hang %d detected, resetting "
816 "adapter\n", adapter->tx_timeout_count + 1);
e01c31a5
JB		 817 ixgbe_tx_timeout(adapter->netdev);
818 }
819 }
9a799d71 820
e01c31a5 821 /* re-arm the interrupt */
fe49f04a
AD		 822 if (count >= tx_ring->work_limit)
823 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 824
e01c31a5
JB		 825 tx_ring->total_bytes += total_bytes;
826 tx_ring->total_packets += total_packets;
e01c31a5 827 tx_ring->stats.packets += total_packets;
12207e49 828 tx_ring->stats.bytes += total_bytes;
807540ba 829 return count < tx_ring->work_limit;
9a799d71
AK		 830}
831
5dd2d332 832#ifdef CONFIG_IXGBE_DCA
bd0362dd 833static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
e8e9f696 834 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 835{
836 u32 rxctrl;
837 int cpu = get_cpu();
4a0b9ca0 838 int q = rx_ring->reg_idx;
bd0362dd 839
3a581073 840 if (rx_ring->cpu != cpu) {
bd0362dd 841 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 842 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
843 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
844 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
845 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
846 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
847 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
e8e9f696 848 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
e8e26350 849 }
bd0362dd
JC		 850 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
851 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 852 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
853 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e9f696 854 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 855 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 856 rx_ring->cpu = cpu;
bd0362dd
JC		 857 }
858 put_cpu();
859}
860
861static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
e8e9f696 862 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 863{
864 u32 txctrl;
865 int cpu = get_cpu();
4a0b9ca0 866 int q = tx_ring->reg_idx;
ee5f784a 867 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 868
3a581073 869 if (tx_ring->cpu != cpu) {
e8e26350 870 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
ee5f784a 871 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 872 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
873 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
ee5f784a
DS		 874 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
875 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
e8e26350 876 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
ee5f784a 877 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
e8e26350
PW		 878 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
879 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
e8e9f696 880 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
ee5f784a
DS		 881 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
882 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
e8e26350 883 }
3a581073 884 tx_ring->cpu = cpu;
bd0362dd
JC		 885 }
886 put_cpu();
887}
888
889static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
890{
891 int i;
892
893 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
894 return;
895
e35ec126
AD		 896 /* always use CB2 mode, difference is masked in the CB driver */
897 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
898
bd0362dd 899 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 900 adapter->tx_ring[i]->cpu = -1;
901 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
bd0362dd
JC		 902 }
903 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 904 adapter->rx_ring[i]->cpu = -1;
905 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
bd0362dd
JC		 906 }
907}
908
909static int __ixgbe_notify_dca(struct device *dev, void *data)
910{
911 struct net_device *netdev = dev_get_drvdata(dev);
912 struct ixgbe_adapter *adapter = netdev_priv(netdev);
913 unsigned long event = *(unsigned long *)data;
914
915 switch (event) {
916 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 917 /* if we're already enabled, don't do it again */
918 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
919 break;
652f093f 920 if (dca_add_requester(dev) == 0) {
96b0e0f6 921 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 922 ixgbe_setup_dca(adapter);
923 break;
924 }
925 /* Fall Through since DCA is disabled. */
926 case DCA_PROVIDER_REMOVE:
927 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
928 dca_remove_requester(dev);
929 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
930 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
931 }
932 break;
933 }
934
652f093f 935 return 0;
bd0362dd
JC		 936}
937
5dd2d332 938#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 939/**
940 * ixgbe_receive_skb - Send a completed packet up the stack
941 * @adapter: board private structure
942 * @skb: packet to send up
177db6ff
MC		 943 * @status: hardware indication of status of receive
944 * @rx_ring: rx descriptor ring (for a specific queue) to setup
945 * @rx_desc: rx descriptor
9a799d71 946 **/
78b6f4ce 947static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 948 struct sk_buff *skb, u8 status,
949 struct ixgbe_ring *ring,
950 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 951{
78b6f4ce
HX		 952 struct ixgbe_adapter *adapter = q_vector->adapter;
953 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 954 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
955 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 956
182ff8df 957 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
8a62babf 958 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
78b6f4ce 959 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 960 else
78b6f4ce 961 napi_gro_receive(napi, skb);
177db6ff 962 } else {
8a62babf 963 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
182ff8df
AD		 964 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
965 else
966 netif_rx(skb);
9a799d71
AK		 967 }
968}
969
e59bd25d
AV		 970/**
971 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
972 * @adapter: address of board private structure
973 * @status_err: hardware indication of status of receive
974 * @skb: skb currently being received and modified
975 **/
9a799d71 976static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 977 union ixgbe_adv_rx_desc *rx_desc,
978 struct sk_buff *skb)
9a799d71 979{
8bae1b2b
DS		 980 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
981
bc8acf2c 982 skb_checksum_none_assert(skb);
9a799d71 983
712744be
JB		 984 /* Rx csum disabled */
985 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 986 return;
e59bd25d
AV		 987
988 /* if IP and error */
989 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
990 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 991 adapter->hw_csum_rx_error++;
992 return;
993 }
e59bd25d
AV		 994
995 if (!(status_err & IXGBE_RXD_STAT_L4CS))
996 return;
997
998 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 999 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1000
1001 /*
1002 * 82599 errata, UDP frames with a 0 checksum can be marked as
1003 * checksum errors.
1004 */
1005 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1006 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1007 return;
1008
e59bd25d
AV		 1009 adapter->hw_csum_rx_error++;
1010 return;
1011 }
1012
9a799d71 1013 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1014 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1015}
1016
e8e26350 1017static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
e8e9f696 1018 struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1019{
1020 /*
1021 * Force memory writes to complete before letting h/w
1022 * know there are new descriptors to fetch. (Only
1023 * applicable for weak-ordered memory model archs,
1024 * such as IA-64).
1025 */
1026 wmb();
1027 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1028}
1029
9a799d71
AK		 1030/**
1031 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1032 * @adapter: address of board private structure
1033 **/
84418e3b 1034void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
e8e9f696
JP		 1035 struct ixgbe_ring *rx_ring,
1036 int cleaned_count)
9a799d71 1037{
d716a7d8 1038 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 1039 struct pci_dev *pdev = adapter->pdev;
1040 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1041 struct ixgbe_rx_buffer *bi;
9a799d71 1042 unsigned int i;
d716a7d8 1043 unsigned int bufsz = rx_ring->rx_buf_len;
9a799d71
AK		 1044
1045 i = rx_ring->next_to_use;
3a581073 1046 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1047
1048 while (cleaned_count--) {
31f05a2d 1049 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1050
762f4c57 1051 if (!bi->page_dma &&
6e455b89 1052 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 1053 if (!bi->page) {
d716a7d8 1054 bi->page = netdev_alloc_page(netdev);
762f4c57
JB		 1055 if (!bi->page) {
1056 adapter->alloc_rx_page_failed++;
1057 goto no_buffers;
1058 }
1059 bi->page_offset = 0;
1060 } else {
1061 /* use a half page if we're re-using */
1062 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 1063 }
762f4c57 1064
1b507730 1065 bi->page_dma = dma_map_page(&pdev->dev, bi->page,
e8e9f696
JP		 1066 bi->page_offset,
1067 (PAGE_SIZE / 2),
1b507730 1068 DMA_FROM_DEVICE);
9a799d71
AK		 1069 }
1070
3a581073 1071 if (!bi->skb) {
d716a7d8
AD		 1072 struct sk_buff *skb = netdev_alloc_skb_ip_align(netdev,
1073 bufsz);
1074 bi->skb = skb;
9a799d71
AK		 1075
1076 if (!skb) {
1077 adapter->alloc_rx_buff_failed++;
1078 goto no_buffers;
1079 }
d716a7d8
AD		 1080 /* initialize queue mapping */
1081 skb_record_rx_queue(skb, rx_ring->queue_index);
1082 }
9a799d71 1083
d716a7d8
AD		 1084 if (!bi->dma) {
1085 bi->dma = dma_map_single(&pdev->dev,
1086 bi->skb->data,
e8e9f696 1087 rx_ring->rx_buf_len,
1b507730 1088 DMA_FROM_DEVICE);
9a799d71
AK		 1089 }
1090 /* Refresh the desc even if buffer_addrs didn't change because
1091 * each write-back erases this info. */
6e455b89 1092 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 1093 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1094 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1095 } else {
3a581073 1096 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1097 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1098 }
1099
1100 i++;
1101 if (i == rx_ring->count)
1102 i = 0;
3a581073 1103 bi = &rx_ring->rx_buffer_info[i];
9a799d71 1104 }
7c6e0a43 1105
9a799d71
AK		 1106no_buffers:
1107 if (rx_ring->next_to_use != i) {
1108 rx_ring->next_to_use = i;
1109 if (i-- == 0)
1110 i = (rx_ring->count - 1);
1111
e8e26350 1112 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 1113 }
1114}
1115
7c6e0a43
JB		 1116static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1117{
1118 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1119}
1120
1121static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1122{
1123 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1124}
1125
f8212f97
AD		 1126static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1127{
1128 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
e8e9f696
JP		 1129 IXGBE_RXDADV_RSCCNT_MASK) >>
1130 IXGBE_RXDADV_RSCCNT_SHIFT;
f8212f97
AD		 1131}
1132
1133/**
1134 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1135 * @skb: pointer to the last skb in the rsc queue
94b982b2 1136 * @count: pointer to number of packets coalesced in this context
f8212f97
AD		 1137 *
1138 * This function changes a queue full of hw rsc buffers into a completed
1139 * packet. It uses the ->prev pointers to find the first packet and then
1140 * turns it into the frag list owner.
1141 **/
94b982b2 1142static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
e8e9f696 1143 u64 *count)
f8212f97
AD		 1144{
1145 unsigned int frag_list_size = 0;
1146
1147 while (skb->prev) {
1148 struct sk_buff *prev = skb->prev;
1149 frag_list_size += skb->len;
1150 skb->prev = NULL;
1151 skb = prev;
94b982b2 1152 *count += 1;
f8212f97
AD		 1153 }
1154
1155 skb_shinfo(skb)->frag_list = skb->next;
1156 skb->next = NULL;
1157 skb->len += frag_list_size;
1158 skb->data_len += frag_list_size;
1159 skb->truesize += frag_list_size;
1160 return skb;
1161}
1162
43634e82
MC		 1163struct ixgbe_rsc_cb {
1164 dma_addr_t dma;
e8171aaa 1165 bool delay_unmap;
43634e82
MC		 1166};
1167
1168#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1169
78b6f4ce 1170static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1171 struct ixgbe_ring *rx_ring,
1172 int *work_done, int work_to_do)
9a799d71 1173{
78b6f4ce 1174 struct ixgbe_adapter *adapter = q_vector->adapter;
2d86f139 1175 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 1176 struct pci_dev *pdev = adapter->pdev;
1177 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1178 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1179 struct sk_buff *skb;
f8212f97 1180 unsigned int i, rsc_count = 0;
7c6e0a43 1181 u32 len, staterr;
177db6ff
MC		 1182 u16 hdr_info;
1183 bool cleaned = false;
9a799d71 1184 int cleaned_count = 0;
d2f4fbe2 1185 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 1186#ifdef IXGBE_FCOE
1187 int ddp_bytes = 0;
1188#endif /* IXGBE_FCOE */
9a799d71
AK		 1189
1190 i = rx_ring->next_to_clean;
31f05a2d 1191 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71
AK		 1192 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1193 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1194
1195 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1196 u32 upper_len = 0;
9a799d71
AK		 1197 if (*work_done >= work_to_do)
1198 break;
1199 (*work_done)++;
1200
3c945e5b 1201 rmb(); /* read descriptor and rx_buffer_info after status DD */
6e455b89 1202 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 1203 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1204 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 1205 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71 1206 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
0b746e08
SN		 1207 if ((len > IXGBE_RX_HDR_SIZE) ||
1208 (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1209 len = IXGBE_RX_HDR_SIZE;
7c6e0a43 1210 } else {
9a799d71 1211 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 1212 }
9a799d71
AK		 1213
1214 cleaned = true;
1215 skb = rx_buffer_info->skb;
7ca3bc58 1216 prefetch(skb->data);
9a799d71
AK		 1217 rx_buffer_info->skb = NULL;
1218
21fa4e66 1219 if (rx_buffer_info->dma) {
43634e82
MC		 1220 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1221 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
e8171aaa 1222 (!(skb->prev))) {
43634e82
MC		 1223 /*
1224 * When HWRSC is enabled, delay unmapping
1225 * of the first packet. It carries the
1226 * header information, HW may still
1227 * access the header after the writeback.
1228 * Only unmap it when EOP is reached
1229 */
e8171aaa 1230 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1231 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1232 } else {
1b507730 1233 dma_unmap_single(&pdev->dev,
e8e9f696
JP		 1234 rx_buffer_info->dma,
1235 rx_ring->rx_buf_len,
1236 DMA_FROM_DEVICE);
e8171aaa 1237 }
4f57ca6e 1238 rx_buffer_info->dma = 0;
9a799d71
AK		 1239 skb_put(skb, len);
1240 }
1241
1242 if (upper_len) {
1b507730
NN		 1243 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1244 PAGE_SIZE / 2, DMA_FROM_DEVICE);
9a799d71
AK		 1245 rx_buffer_info->page_dma = 0;
1246 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1247 rx_buffer_info->page,
1248 rx_buffer_info->page_offset,
1249 upper_len);
762f4c57
JB		 1250
1251 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1252 (page_count(rx_buffer_info->page) != 1))
1253 rx_buffer_info->page = NULL;
1254 else
1255 get_page(rx_buffer_info->page);
9a799d71
AK		 1256
1257 skb->len += upper_len;
1258 skb->data_len += upper_len;
1259 skb->truesize += upper_len;
1260 }
1261
1262 i++;
1263 if (i == rx_ring->count)
1264 i = 0;
9a799d71 1265
31f05a2d 1266 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1267 prefetch(next_rxd);
9a799d71 1268 cleaned_count++;
f8212f97 1269
0c19d6af 1270 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 1271 rsc_count = ixgbe_get_rsc_count(rx_desc);
1272
1273 if (rsc_count) {
1274 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1275 IXGBE_RXDADV_NEXTP_SHIFT;
1276 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1277 } else {
1278 next_buffer = &rx_ring->rx_buffer_info[i];
1279 }
1280
9a799d71 1281 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97 1282 if (skb->prev)
e8e9f696
JP		 1283 skb = ixgbe_transform_rsc_queue(skb,
1284 &(rx_ring->rsc_count));
94b982b2 1285 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
e8171aaa 1286 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1b507730
NN		 1287 dma_unmap_single(&pdev->dev,
1288 IXGBE_RSC_CB(skb)->dma,
e8e9f696 1289 rx_ring->rx_buf_len,
1b507730 1290 DMA_FROM_DEVICE);
fd3686a8 1291 IXGBE_RSC_CB(skb)->dma = 0;
e8171aaa 1292 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 1293 }
94b982b2 1294 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
e8e9f696
JP		 1295 rx_ring->rsc_count +=
1296 skb_shinfo(skb)->nr_frags;
94b982b2
MC		 1297 else
1298 rx_ring->rsc_count++;
1299 rx_ring->rsc_flush++;
1300 }
9a799d71
AK		 1301 rx_ring->stats.packets++;
1302 rx_ring->stats.bytes += skb->len;
1303 } else {
6e455b89 1304 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 1305 rx_buffer_info->skb = next_buffer->skb;
1306 rx_buffer_info->dma = next_buffer->dma;
1307 next_buffer->skb = skb;
1308 next_buffer->dma = 0;
1309 } else {
1310 skb->next = next_buffer->skb;
1311 skb->next->prev = skb;
1312 }
7ca3bc58 1313 rx_ring->non_eop_descs++;
9a799d71
AK		 1314 goto next_desc;
1315 }
1316
1317 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1318 dev_kfree_skb_irq(skb);
1319 goto next_desc;
1320 }
1321
8bae1b2b 1322 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 1323
1324 /* probably a little skewed due to removing CRC */
1325 total_rx_bytes += skb->len;
1326 total_rx_packets++;
1327
74ce8dd2 1328 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 1329#ifdef IXGBE_FCOE
1330 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 1331 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1332 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1333 if (!ddp_bytes)
332d4a7d 1334 goto next_desc;
3d8fd385 1335 }
332d4a7d 1336#endif /* IXGBE_FCOE */
fdaff1ce 1337 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1338
1339next_desc:
1340 rx_desc->wb.upper.status_error = 0;
1341
1342 /* return some buffers to hardware, one at a time is too slow */
1343 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1344 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1345 cleaned_count = 0;
1346 }
1347
1348 /* use prefetched values */
1349 rx_desc = next_rxd;
f8212f97 1350 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1351
1352 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1353 }
1354
9a799d71
AK		 1355 rx_ring->next_to_clean = i;
1356 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1357
1358 if (cleaned_count)
1359 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1360
3d8fd385
YZ		 1361#ifdef IXGBE_FCOE
1362 /* include DDPed FCoE data */
1363 if (ddp_bytes > 0) {
1364 unsigned int mss;
1365
1366 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1367 sizeof(struct fc_frame_header) -
1368 sizeof(struct fcoe_crc_eof);
1369 if (mss > 512)
1370 mss &= ~511;
1371 total_rx_bytes += ddp_bytes;
1372 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1373 }
1374#endif /* IXGBE_FCOE */
1375
f494e8fa
AV		 1376 rx_ring->total_packets += total_rx_packets;
1377 rx_ring->total_bytes += total_rx_bytes;
2d86f139
AK		 1378 netdev->stats.rx_bytes += total_rx_bytes;
1379 netdev->stats.rx_packets += total_rx_packets;
f494e8fa 1380
9a799d71
AK		 1381 return cleaned;
1382}
1383
021230d4 1384static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1385/**
1386 * ixgbe_configure_msix - Configure MSI-X hardware
1387 * @adapter: board private structure
1388 *
1389 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1390 * interrupts.
1391 **/
1392static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1393{
021230d4
AV		 1394 struct ixgbe_q_vector *q_vector;
1395 int i, j, q_vectors, v_idx, r_idx;
1396 u32 mask;
9a799d71 1397
021230d4 1398 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1399
4df10466
JB		 1400 /*
1401 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1402 * corresponding register.
1403 */
1404 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1405 q_vector = adapter->q_vector[v_idx];
984b3f57 1406 /* XXX for_each_set_bit(...) */
021230d4 1407 r_idx = find_first_bit(q_vector->rxr_idx,
e8e9f696 1408 adapter->num_rx_queues);
021230d4
AV		 1409
1410 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1411 j = adapter->rx_ring[r_idx]->reg_idx;
e8e26350 1412 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 1413 r_idx = find_next_bit(q_vector->rxr_idx,
e8e9f696
JP		 1414 adapter->num_rx_queues,
1415 r_idx + 1);
021230d4
AV		 1416 }
1417 r_idx = find_first_bit(q_vector->txr_idx,
e8e9f696 1418 adapter->num_tx_queues);
021230d4
AV		 1419
1420 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1421 j = adapter->tx_ring[r_idx]->reg_idx;
e8e26350 1422 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 1423 r_idx = find_next_bit(q_vector->txr_idx,
e8e9f696
JP		 1424 adapter->num_tx_queues,
1425 r_idx + 1);
021230d4
AV		 1426 }
1427
021230d4 1428 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1429 /* tx only */
1430 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1431 else if (q_vector->rxr_count)
f7554a2b
NS		 1432 /* rx or mixed */
1433 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1434
fe49f04a 1435 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1436 }
1437
e8e26350
PW		 1438 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1439 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1440 v_idx);
e8e26350
PW		 1441 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1442 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 1443 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1444
41fb9248 1445 /* set up to autoclear timer, and the vectors */
021230d4 1446 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1447 if (adapter->num_vfs)
1448 mask &= ~(IXGBE_EIMS_OTHER |
1449 IXGBE_EIMS_MAILBOX |
1450 IXGBE_EIMS_LSC);
1451 else
1452 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1453 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1454}
1455
f494e8fa
AV		 1456enum latency_range {
1457 lowest_latency = 0,
1458 low_latency = 1,
1459 bulk_latency = 2,
1460 latency_invalid = 255
1461};
1462
1463/**
1464 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1465 * @adapter: pointer to adapter
1466 * @eitr: eitr setting (ints per sec) to give last timeslice
1467 * @itr_setting: current throttle rate in ints/second
1468 * @packets: the number of packets during this measurement interval
1469 * @bytes: the number of bytes during this measurement interval
1470 *
1471 * Stores a new ITR value based on packets and byte
1472 * counts during the last interrupt. The advantage of per interrupt
1473 * computation is faster updates and more accurate ITR for the current
1474 * traffic pattern. Constants in this function were computed
1475 * based on theoretical maximum wire speed and thresholds were set based
1476 * on testing data as well as attempting to minimize response time
1477 * while increasing bulk throughput.
1478 * this functionality is controlled by the InterruptThrottleRate module
1479 * parameter (see ixgbe_param.c)
1480 **/
1481static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
e8e9f696
JP		 1482 u32 eitr, u8 itr_setting,
1483 int packets, int bytes)
f494e8fa
AV		 1484{
1485 unsigned int retval = itr_setting;
1486 u32 timepassed_us;
1487 u64 bytes_perint;
1488
1489 if (packets == 0)
1490 goto update_itr_done;
1491
1492
1493 /* simple throttlerate management
1494 * 0-20MB/s lowest (100000 ints/s)
1495 * 20-100MB/s low (20000 ints/s)
1496 * 100-1249MB/s bulk (8000 ints/s)
1497 */
1498 /* what was last interrupt timeslice? */
1499 timepassed_us = 1000000/eitr;
1500 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1501
1502 switch (itr_setting) {
1503 case lowest_latency:
1504 if (bytes_perint > adapter->eitr_low)
1505 retval = low_latency;
1506 break;
1507 case low_latency:
1508 if (bytes_perint > adapter->eitr_high)
1509 retval = bulk_latency;
1510 else if (bytes_perint <= adapter->eitr_low)
1511 retval = lowest_latency;
1512 break;
1513 case bulk_latency:
1514 if (bytes_perint <= adapter->eitr_high)
1515 retval = low_latency;
1516 break;
1517 }
1518
1519update_itr_done:
1520 return retval;
1521}
1522
509ee935
JB		 1523/**
1524 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1525 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1526 *
1527 * This function is made to be called by ethtool and by the driver
1528 * when it needs to update EITR registers at runtime. Hardware
1529 * specific quirks/differences are taken care of here.
1530 */
fe49f04a 1531void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1532{
fe49f04a 1533 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1534 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1535 int v_idx = q_vector->v_idx;
1536 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1537
509ee935
JB		 1538 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1539 /* must write high and low 16 bits to reset counter */
1540 itr_reg |= (itr_reg << 16);
1541 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f8d1dcaf
JB		 1542 /*
1543 * 82599 can support a value of zero, so allow it for
1544 * max interrupt rate, but there is an errata where it can
1545 * not be zero with RSC
1546 */
1547 if (itr_reg == 8 &&
1548 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1549 itr_reg = 0;
1550
509ee935
JB		 1551 /*
1552 * set the WDIS bit to not clear the timer bits and cause an
1553 * immediate assertion of the interrupt
1554 */
1555 itr_reg |= IXGBE_EITR_CNT_WDIS;
1556 }
1557 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1558}
1559
f494e8fa
AV		 1560static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1561{
1562 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1563 u32 new_itr;
1564 u8 current_itr, ret_itr;
fe49f04a 1565 int i, r_idx;
f494e8fa
AV		 1566 struct ixgbe_ring *rx_ring, *tx_ring;
1567
1568 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1569 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1570 tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1571 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1572 q_vector->tx_itr,
1573 tx_ring->total_packets,
1574 tx_ring->total_bytes);
f494e8fa
AV		 1575 /* if the result for this queue would decrease interrupt
1576 * rate for this vector then use that result */
30efa5a3 1577 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
e8e9f696 1578 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1579 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1580 r_idx + 1);
f494e8fa
AV		 1581 }
1582
1583 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1584 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1585 rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1586 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1587 q_vector->rx_itr,
1588 rx_ring->total_packets,
1589 rx_ring->total_bytes);
f494e8fa
AV		 1590 /* if the result for this queue would decrease interrupt
1591 * rate for this vector then use that result */
30efa5a3 1592 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
e8e9f696 1593 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1594 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1595 r_idx + 1);
f494e8fa
AV		 1596 }
1597
30efa5a3 1598 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1599
1600 switch (current_itr) {
1601 /* counts and packets in update_itr are dependent on these numbers */
1602 case lowest_latency:
1603 new_itr = 100000;
1604 break;
1605 case low_latency:
1606 new_itr = 20000; /* aka hwitr = ~200 */
1607 break;
1608 case bulk_latency:
1609 default:
1610 new_itr = 8000;
1611 break;
1612 }
1613
1614 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1615 /* do an exponential smoothing */
1616 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1617
1618 /* save the algorithm value here, not the smoothed one */
1619 q_vector->eitr = new_itr;
fe49f04a
AD		 1620
1621 ixgbe_write_eitr(q_vector);
f494e8fa 1622 }
f494e8fa
AV		 1623}
1624
119fc60a
MC		 1625/**
1626 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1627 * @work: pointer to work_struct containing our data
1628 **/
1629static void ixgbe_check_overtemp_task(struct work_struct *work)
1630{
1631 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 1632 struct ixgbe_adapter,
1633 check_overtemp_task);
119fc60a
MC		 1634 struct ixgbe_hw *hw = &adapter->hw;
1635 u32 eicr = adapter->interrupt_event;
1636
7ca647bd
JP		 1637 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1638 return;
1639
1640 switch (hw->device_id) {
1641 case IXGBE_DEV_ID_82599_T3_LOM: {
1642 u32 autoneg;
1643 bool link_up = false;
1644
1645 if (hw->mac.ops.check_link)
1646 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1647
1648 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1649 (eicr & IXGBE_EICR_LSC))
1650 /* Check if this is due to overtemp */
1651 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1652 break;
1653 return;
1654 }
1655 default:
1656 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1657 return;
7ca647bd 1658 break;
119fc60a 1659 }
7ca647bd
JP		 1660 e_crit(drv,
1661 "Network adapter has been stopped because it has over heated. "
1662 "Restart the computer. If the problem persists, "
1663 "power off the system and replace the adapter\n");
1664 /* write to clear the interrupt */
1665 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
119fc60a
MC		 1666}
1667
0befdb3e
JB		 1668static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1669{
1670 struct ixgbe_hw *hw = &adapter->hw;
1671
1672 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1673 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1674 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1675 /* write to clear the interrupt */
1676 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1677 }
1678}
cf8280ee 1679
e8e26350
PW		 1680static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1681{
1682 struct ixgbe_hw *hw = &adapter->hw;
1683
1684 if (eicr & IXGBE_EICR_GPI_SDP1) {
1685 /* Clear the interrupt */
1686 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1687 schedule_work(&adapter->multispeed_fiber_task);
1688 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1689 /* Clear the interrupt */
1690 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1691 schedule_work(&adapter->sfp_config_module_task);
1692 } else {
1693 /* Interrupt isn't for us... */
1694 return;
1695 }
1696}
1697
cf8280ee
JB		 1698static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1699{
1700 struct ixgbe_hw *hw = &adapter->hw;
1701
1702 adapter->lsc_int++;
1703 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1704 adapter->link_check_timeout = jiffies;
1705 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1706 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1707 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1708 schedule_work(&adapter->watchdog_task);
1709 }
1710}
1711
9a799d71
AK		 1712static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1713{
1714 struct net_device *netdev = data;
1715 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1716 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1717 u32 eicr;
1718
1719 /*
1720 * Workaround for Silicon errata. Use clear-by-write instead
1721 * of clear-by-read. Reading with EICS will return the
1722 * interrupt causes without clearing, which later be done
1723 * with the write to EICR.
1724 */
1725 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1726 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1727
cf8280ee
JB		 1728 if (eicr & IXGBE_EICR_LSC)
1729 ixgbe_check_lsc(adapter);
d4f80882 1730
1cdd1ec8
GR		 1731 if (eicr & IXGBE_EICR_MAILBOX)
1732 ixgbe_msg_task(adapter);
1733
e8e26350
PW		 1734 if (hw->mac.type == ixgbe_mac_82598EB)
1735 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1736
c4cf55e5 1737 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1738 ixgbe_check_sfp_event(adapter, eicr);
119fc60a
MC		 1739 adapter->interrupt_event = eicr;
1740 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1741 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1742 schedule_work(&adapter->check_overtemp_task);
c4cf55e5
PWJ		 1743
1744 /* Handle Flow Director Full threshold interrupt */
1745 if (eicr & IXGBE_EICR_FLOW_DIR) {
1746 int i;
1747 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1748 /* Disable transmits before FDIR Re-initialization */
1749 netif_tx_stop_all_queues(netdev);
1750 for (i = 0; i < adapter->num_tx_queues; i++) {
1751 struct ixgbe_ring *tx_ring =
e8e9f696 1752 adapter->tx_ring[i];
c4cf55e5 1753 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
e8e9f696 1754 &tx_ring->reinit_state))
c4cf55e5
PWJ		 1755 schedule_work(&adapter->fdir_reinit_task);
1756 }
1757 }
1758 }
d4f80882
AV		 1759 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1760 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1761
1762 return IRQ_HANDLED;
1763}
1764
fe49f04a
AD		 1765static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1766 u64 qmask)
1767{
1768 u32 mask;
1769
1770 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1771 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1772 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1773 } else {
1774 mask = (qmask & 0xFFFFFFFF);
1775 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1776 mask = (qmask >> 32);
1777 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1778 }
1779 /* skip the flush */
1780}
1781
1782static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1783 u64 qmask)
fe49f04a
AD		 1784{
1785 u32 mask;
1786
1787 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1788 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1789 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1790 } else {
1791 mask = (qmask & 0xFFFFFFFF);
1792 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1793 mask = (qmask >> 32);
1794 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1795 }
1796 /* skip the flush */
1797}
1798
9a799d71
AK		 1799static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1800{
021230d4
AV		 1801 struct ixgbe_q_vector *q_vector = data;
1802 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1803 struct ixgbe_ring *tx_ring;
021230d4
AV		 1804 int i, r_idx;
1805
1806 if (!q_vector->txr_count)
1807 return IRQ_HANDLED;
1808
1809 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1810 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1811 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 1812 tx_ring->total_bytes = 0;
1813 tx_ring->total_packets = 0;
021230d4 1814 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1815 r_idx + 1);
021230d4 1816 }
9a799d71 1817
9b471446 1818 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 1819 napi_schedule(&q_vector->napi);
1820
9a799d71
AK		 1821 return IRQ_HANDLED;
1822}
1823
021230d4
AV		 1824/**
1825 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1826 * @irq: unused
1827 * @data: pointer to our q_vector struct for this interrupt vector
1828 **/
9a799d71
AK		 1829static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1830{
021230d4
AV		 1831 struct ixgbe_q_vector *q_vector = data;
1832 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1833 struct ixgbe_ring *rx_ring;
021230d4 1834 int r_idx;
30efa5a3 1835 int i;
021230d4
AV		 1836
1837 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3 1838 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1839 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 1840 rx_ring->total_bytes = 0;
1841 rx_ring->total_packets = 0;
1842 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1843 r_idx + 1);
30efa5a3
JB		 1844 }
1845
021230d4
AV		 1846 if (!q_vector->rxr_count)
1847 return IRQ_HANDLED;
1848
021230d4 1849 /* disable interrupts on this vector only */
9b471446 1850 /* EIAM disabled interrupts (on this vector) for us */
288379f0 1851 napi_schedule(&q_vector->napi);
021230d4
AV		 1852
1853 return IRQ_HANDLED;
1854}
1855
1856static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1857{
91281fd3
AD		 1858 struct ixgbe_q_vector *q_vector = data;
1859 struct ixgbe_adapter *adapter = q_vector->adapter;
1860 struct ixgbe_ring *ring;
1861 int r_idx;
1862 int i;
1863
1864 if (!q_vector->txr_count && !q_vector->rxr_count)
1865 return IRQ_HANDLED;
1866
1867 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1868 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1869 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1870 ring->total_bytes = 0;
1871 ring->total_packets = 0;
1872 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1873 r_idx + 1);
91281fd3
AD		 1874 }
1875
1876 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1877 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1878 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 1879 ring->total_bytes = 0;
1880 ring->total_packets = 0;
1881 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1882 r_idx + 1);
91281fd3
AD		 1883 }
1884
9b471446 1885 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1886 napi_schedule(&q_vector->napi);
9a799d71 1887
9a799d71
AK		 1888 return IRQ_HANDLED;
1889}
1890
021230d4
AV		 1891/**
1892 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1893 * @napi: napi struct with our devices info in it
1894 * @budget: amount of work driver is allowed to do this pass, in packets
1895 *
f0848276
JB		 1896 * This function is optimized for cleaning one queue only on a single
1897 * q_vector!!!
021230d4 1898 **/
9a799d71
AK		 1899static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1900{
021230d4 1901 struct ixgbe_q_vector *q_vector =
e8e9f696 1902 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1903 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1904 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1905 int work_done = 0;
021230d4 1906 long r_idx;
9a799d71 1907
021230d4 1908 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1909 rx_ring = adapter->rx_ring[r_idx];
5dd2d332 1910#ifdef CONFIG_IXGBE_DCA
bd0362dd 1911 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1912 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1913#endif
9a799d71 1914
78b6f4ce 1915 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1916
021230d4
AV		 1917 /* If all Rx work done, exit the polling mode */
1918 if (work_done < budget) {
288379f0 1919 napi_complete(napi);
f7554a2b 1920 if (adapter->rx_itr_setting & 1)
f494e8fa 1921 ixgbe_set_itr_msix(q_vector);
9a799d71 1922 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 1923 ixgbe_irq_enable_queues(adapter,
e8e9f696 1924 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1925 }
1926
1927 return work_done;
1928}
1929
f0848276 1930/**
91281fd3 1931 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1932 * @napi: napi struct with our devices info in it
1933 * @budget: amount of work driver is allowed to do this pass, in packets
1934 *
1935 * This function will clean more than one rx queue associated with a
1936 * q_vector.
1937 **/
91281fd3 1938static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1939{
1940 struct ixgbe_q_vector *q_vector =
e8e9f696 1941 container_of(napi, struct ixgbe_q_vector, napi);
f0848276 1942 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1943 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1944 int work_done = 0, i;
1945 long r_idx;
91281fd3
AD		 1946 bool tx_clean_complete = true;
1947
1948 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1949 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1950 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1951#ifdef CONFIG_IXGBE_DCA
1952 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1953 ixgbe_update_tx_dca(adapter, ring);
1954#endif
1955 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1956 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1957 r_idx + 1);
91281fd3 1958 }
f0848276
JB		 1959
1960 /* attempt to distribute budget to each queue fairly, but don't allow
1961 * the budget to go below 1 because we'll exit polling */
1962 budget /= (q_vector->rxr_count ?: 1);
1963 budget = max(budget, 1);
1964 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1965 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1966 ring = adapter->rx_ring[r_idx];
5dd2d332 1967#ifdef CONFIG_IXGBE_DCA
f0848276 1968 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1969 ixgbe_update_rx_dca(adapter, ring);
f0848276 1970#endif
91281fd3 1971 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276 1972 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1973 r_idx + 1);
f0848276
JB		 1974 }
1975
1976 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1977 ring = adapter->rx_ring[r_idx];
f0848276 1978 /* If all Rx work done, exit the polling mode */
7f821875 1979 if (work_done < budget) {
288379f0 1980 napi_complete(napi);
f7554a2b 1981 if (adapter->rx_itr_setting & 1)
f0848276
JB		 1982 ixgbe_set_itr_msix(q_vector);
1983 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 1984 ixgbe_irq_enable_queues(adapter,
e8e9f696 1985 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1986 return 0;
1987 }
1988
1989 return work_done;
1990}
91281fd3
AD		 1991
1992/**
1993 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1994 * @napi: napi struct with our devices info in it
1995 * @budget: amount of work driver is allowed to do this pass, in packets
1996 *
1997 * This function is optimized for cleaning one queue only on a single
1998 * q_vector!!!
1999 **/
2000static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2001{
2002 struct ixgbe_q_vector *q_vector =
e8e9f696 2003 container_of(napi, struct ixgbe_q_vector, napi);
91281fd3
AD		 2004 struct ixgbe_adapter *adapter = q_vector->adapter;
2005 struct ixgbe_ring *tx_ring = NULL;
2006 int work_done = 0;
2007 long r_idx;
2008
2009 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
4a0b9ca0 2010 tx_ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2011#ifdef CONFIG_IXGBE_DCA
2012 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2013 ixgbe_update_tx_dca(adapter, tx_ring);
2014#endif
2015
2016 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2017 work_done = budget;
2018
f7554a2b 2019 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 2020 if (work_done < budget) {
2021 napi_complete(napi);
f7554a2b 2022 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 2023 ixgbe_set_itr_msix(q_vector);
2024 if (!test_bit(__IXGBE_DOWN, &adapter->state))
e8e9f696
JP		 2025 ixgbe_irq_enable_queues(adapter,
2026 ((u64)1 << q_vector->v_idx));
91281fd3
AD		 2027 }
2028
2029 return work_done;
2030}
2031
021230d4 2032static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2033 int r_idx)
021230d4 2034{
7a921c93
AD		 2035 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2036
2037 set_bit(r_idx, q_vector->rxr_idx);
2038 q_vector->rxr_count++;
021230d4
AV		 2039}
2040
2041static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2042 int t_idx)
021230d4 2043{
7a921c93
AD		 2044 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2045
2046 set_bit(t_idx, q_vector->txr_idx);
2047 q_vector->txr_count++;
021230d4
AV		 2048}
2049
9a799d71 2050/**
021230d4
AV		 2051 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2052 * @adapter: board private structure to initialize
2053 * @vectors: allotted vector count for descriptor rings
9a799d71 2054 *
021230d4
AV		 2055 * This function maps descriptor rings to the queue-specific vectors
2056 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2057 * one vector per ring/queue, but on a constrained vector budget, we
2058 * group the rings as "efficiently" as possible. You would add new
2059 * mapping configurations in here.
9a799d71 2060 **/
021230d4 2061static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
e8e9f696 2062 int vectors)
021230d4
AV		 2063{
2064 int v_start = 0;
2065 int rxr_idx = 0, txr_idx = 0;
2066 int rxr_remaining = adapter->num_rx_queues;
2067 int txr_remaining = adapter->num_tx_queues;
2068 int i, j;
2069 int rqpv, tqpv;
2070 int err = 0;
2071
2072 /* No mapping required if MSI-X is disabled. */
2073 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2074 goto out;
9a799d71 2075
021230d4
AV		 2076 /*
2077 * The ideal configuration...
2078 * We have enough vectors to map one per queue.
2079 */
2080 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2081 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2082 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2083
021230d4
AV		 2084 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2085 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2086
9a799d71 2087 goto out;
021230d4 2088 }
9a799d71 2089
021230d4
AV		 2090 /*
2091 * If we don't have enough vectors for a 1-to-1
2092 * mapping, we'll have to group them so there are
2093 * multiple queues per vector.
2094 */
2095 /* Re-adjusting *qpv takes care of the remainder. */
2096 for (i = v_start; i < vectors; i++) {
2097 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2098 for (j = 0; j < rqpv; j++) {
2099 map_vector_to_rxq(adapter, i, rxr_idx);
2100 rxr_idx++;
2101 rxr_remaining--;
2102 }
2103 }
2104 for (i = v_start; i < vectors; i++) {
2105 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2106 for (j = 0; j < tqpv; j++) {
2107 map_vector_to_txq(adapter, i, txr_idx);
2108 txr_idx++;
2109 txr_remaining--;
9a799d71 2110 }
9a799d71
AK		 2111 }
2112
021230d4
AV		 2113out:
2114 return err;
2115}
2116
2117/**
2118 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2119 * @adapter: board private structure
2120 *
2121 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2122 * interrupts from the kernel.
2123 **/
2124static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2125{
2126 struct net_device *netdev = adapter->netdev;
2127 irqreturn_t (*handler)(int, void *);
2128 int i, vector, q_vectors, err;
e8e9f696 2129 int ri = 0, ti = 0;
021230d4
AV		 2130
2131 /* Decrement for Other and TCP Timer vectors */
2132 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2133
2134 /* Map the Tx/Rx rings to the vectors we were allotted. */
2135 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2136 if (err)
2137 goto out;
2138
2139#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
e8e9f696
JP		 2140 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2141 &ixgbe_msix_clean_many)
021230d4 2142 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 2143 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20 2144
e8e9f696 2145 if (handler == &ixgbe_msix_clean_rx) {
cb13fc20
RO		 2146 sprintf(adapter->name[vector], "%s-%s-%d",
2147 netdev->name, "rx", ri++);
e8e9f696 2148 } else if (handler == &ixgbe_msix_clean_tx) {
cb13fc20
RO		 2149 sprintf(adapter->name[vector], "%s-%s-%d",
2150 netdev->name, "tx", ti++);
e8e9f696 2151 } else
cb13fc20
RO		 2152 sprintf(adapter->name[vector], "%s-%s-%d",
2153 netdev->name, "TxRx", vector);
2154
021230d4 2155 err = request_irq(adapter->msix_entries[vector].vector,
e8e9f696
JP		 2156 handler, 0, adapter->name[vector],
2157 adapter->q_vector[vector]);
9a799d71 2158 if (err) {
396e799c 2159 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2160 "Error: %d\n", err);
021230d4 2161 goto free_queue_irqs;
9a799d71 2162 }
9a799d71
AK		 2163 }
2164
021230d4
AV		 2165 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2166 err = request_irq(adapter->msix_entries[vector].vector,
e8e9f696 2167 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71 2168 if (err) {
396e799c 2169 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2170 goto free_queue_irqs;
9a799d71
AK		 2171 }
2172
9a799d71
AK		 2173 return 0;
2174
021230d4
AV		 2175free_queue_irqs:
2176 for (i = vector - 1; i >= 0; i--)
2177 free_irq(adapter->msix_entries[--vector].vector,
e8e9f696 2178 adapter->q_vector[i]);
021230d4
AV		 2179 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2180 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2181 kfree(adapter->msix_entries);
2182 adapter->msix_entries = NULL;
021230d4 2183out:
9a799d71
AK		 2184 return err;
2185}
2186
f494e8fa
AV		 2187static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2188{
7a921c93 2189 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 2190 u8 current_itr;
2191 u32 new_itr = q_vector->eitr;
4a0b9ca0
PW		 2192 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2193 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
f494e8fa 2194
30efa5a3 2195 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2196 q_vector->tx_itr,
2197 tx_ring->total_packets,
2198 tx_ring->total_bytes);
30efa5a3 2199 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2200 q_vector->rx_itr,
2201 rx_ring->total_packets,
2202 rx_ring->total_bytes);
f494e8fa 2203
30efa5a3 2204 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 2205
2206 switch (current_itr) {
2207 /* counts and packets in update_itr are dependent on these numbers */
2208 case lowest_latency:
2209 new_itr = 100000;
2210 break;
2211 case low_latency:
2212 new_itr = 20000; /* aka hwitr = ~200 */
2213 break;
2214 case bulk_latency:
2215 new_itr = 8000;
2216 break;
2217 default:
2218 break;
2219 }
2220
2221 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 2222 /* do an exponential smoothing */
2223 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 2224
2225 /* save the algorithm value here, not the smoothed one */
2226 q_vector->eitr = new_itr;
fe49f04a
AD		 2227
2228 ixgbe_write_eitr(q_vector);
f494e8fa 2229 }
f494e8fa
AV		 2230}
2231
79aefa45
AD		 2232/**
2233 * ixgbe_irq_enable - Enable default interrupt generation settings
2234 * @adapter: board private structure
2235 **/
2236static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
2237{
2238 u32 mask;
835462fc
NS		 2239
2240 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
119fc60a
MC		 2241 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2242 mask |= IXGBE_EIMS_GPI_SDP0;
6ab33d51
DM		 2243 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2244 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 2245 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 2246 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2247 mask |= IXGBE_EIMS_GPI_SDP1;
2248 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2249 if (adapter->num_vfs)
2250 mask |= IXGBE_EIMS_MAILBOX;
e8e26350 2251 }
c4cf55e5
PWJ		 2252 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2253 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2254 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2255
79aefa45 2256 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 2257 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45 2258 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2259
2260 if (adapter->num_vfs > 32) {
2261 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2262 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2263 }
79aefa45 2264}
021230d4 2265
9a799d71 2266/**
021230d4 2267 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2268 * @irq: interrupt number
2269 * @data: pointer to a network interface device structure
9a799d71
AK		 2270 **/
2271static irqreturn_t ixgbe_intr(int irq, void *data)
2272{
2273 struct net_device *netdev = data;
2274 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2275 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2276 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2277 u32 eicr;
2278
54037505
DS		 2279 /*
2280 * Workaround for silicon errata. Mask the interrupts
2281 * before the read of EICR.
2282 */
2283 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2284
021230d4
AV		 2285 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2286 * therefore no explict interrupt disable is necessary */
2287 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 2288 if (!eicr) {
2289 /* shared interrupt alert!
2290 * make sure interrupts are enabled because the read will
2291 * have disabled interrupts due to EIAM */
2292 ixgbe_irq_enable(adapter);
9a799d71 2293 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2294 }
9a799d71 2295
cf8280ee
JB		 2296 if (eicr & IXGBE_EICR_LSC)
2297 ixgbe_check_lsc(adapter);
021230d4 2298
e8e26350
PW		 2299 if (hw->mac.type == ixgbe_mac_82599EB)
2300 ixgbe_check_sfp_event(adapter, eicr);
2301
0befdb3e 2302 ixgbe_check_fan_failure(adapter, eicr);
119fc60a
MC		 2303 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2304 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2305 schedule_work(&adapter->check_overtemp_task);
0befdb3e 2306
7a921c93 2307 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 2308 adapter->tx_ring[0]->total_packets = 0;
2309 adapter->tx_ring[0]->total_bytes = 0;
2310 adapter->rx_ring[0]->total_packets = 0;
2311 adapter->rx_ring[0]->total_bytes = 0;
021230d4 2312 /* would disable interrupts here but EIAM disabled it */
7a921c93 2313 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2314 }
2315
2316 return IRQ_HANDLED;
2317}
2318
021230d4
AV		 2319static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2320{
2321 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2322
2323 for (i = 0; i < q_vectors; i++) {
7a921c93 2324 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 2325 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2326 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2327 q_vector->rxr_count = 0;
2328 q_vector->txr_count = 0;
2329 }
2330}
2331
9a799d71
AK		 2332/**
2333 * ixgbe_request_irq - initialize interrupts
2334 * @adapter: board private structure
2335 *
2336 * Attempts to configure interrupts using the best available
2337 * capabilities of the hardware and kernel.
2338 **/
021230d4 2339static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2340{
2341 struct net_device *netdev = adapter->netdev;
021230d4 2342 int err;
9a799d71 2343
021230d4
AV		 2344 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2345 err = ixgbe_request_msix_irqs(adapter);
2346 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2347 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
e8e9f696 2348 netdev->name, netdev);
021230d4 2349 } else {
a0607fd3 2350 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
e8e9f696 2351 netdev->name, netdev);
9a799d71
AK		 2352 }
2353
9a799d71 2354 if (err)
396e799c 2355 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2356
9a799d71
AK		 2357 return err;
2358}
2359
2360static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2361{
2362 struct net_device *netdev = adapter->netdev;
2363
2364 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2365 int i, q_vectors;
9a799d71 2366
021230d4
AV		 2367 q_vectors = adapter->num_msix_vectors;
2368
2369 i = q_vectors - 1;
9a799d71 2370 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 2371
021230d4
AV		 2372 i--;
2373 for (; i >= 0; i--) {
2374 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2375 adapter->q_vector[i]);
021230d4
AV		 2376 }
2377
2378 ixgbe_reset_q_vectors(adapter);
2379 } else {
2380 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 2381 }
2382}
2383
22d5a71b
JB		 2384/**
2385 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2386 * @adapter: board private structure
2387 **/
2388static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2389{
835462fc
NS		 2390 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2391 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2392 } else {
2393 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2394 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2395 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2396 if (adapter->num_vfs > 32)
2397 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
22d5a71b
JB		 2398 }
2399 IXGBE_WRITE_FLUSH(&adapter->hw);
2400 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2401 int i;
2402 for (i = 0; i < adapter->num_msix_vectors; i++)
2403 synchronize_irq(adapter->msix_entries[i].vector);
2404 } else {
2405 synchronize_irq(adapter->pdev->irq);
2406 }
2407}
2408
9a799d71
AK		 2409/**
2410 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2411 *
2412 **/
2413static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2414{
9a799d71
AK		 2415 struct ixgbe_hw *hw = &adapter->hw;
2416
021230d4 2417 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
e8e9f696 2418 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2419
e8e26350
PW		 2420 ixgbe_set_ivar(adapter, 0, 0, 0);
2421 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2422
2423 map_vector_to_rxq(adapter, 0, 0);
2424 map_vector_to_txq(adapter, 0, 0);
2425
396e799c 2426 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2427}
2428
43e69bf0
AD		 2429/**
2430 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2431 * @adapter: board private structure
2432 * @ring: structure containing ring specific data
2433 *
2434 * Configure the Tx descriptor ring after a reset.
2435 **/
84418e3b
AD		 2436void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2437 struct ixgbe_ring *ring)
43e69bf0
AD		 2438{
2439 struct ixgbe_hw *hw = &adapter->hw;
2440 u64 tdba = ring->dma;
2f1860b8
AD		 2441 int wait_loop = 10;
2442 u32 txdctl;
43e69bf0
AD		 2443 u16 reg_idx = ring->reg_idx;
2444
2f1860b8
AD		 2445 /* disable queue to avoid issues while updating state */
2446 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2447 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2448 txdctl & ~IXGBE_TXDCTL_ENABLE);
2449 IXGBE_WRITE_FLUSH(hw);
2450
43e69bf0 2451 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2452 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2453 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2454 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2455 ring->count * sizeof(union ixgbe_adv_tx_desc));
2456 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2457 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2458 ring->head = IXGBE_TDH(reg_idx);
2459 ring->tail = IXGBE_TDT(reg_idx);
2460
2f1860b8
AD		 2461 /* configure fetching thresholds */
2462 if (adapter->rx_itr_setting == 0) {
2463 /* cannot set wthresh when itr==0 */
2464 txdctl &= ~0x007F0000;
2465 } else {
2466 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2467 txdctl |= (8 << 16);
2468 }
2469 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2470 /* PThresh workaround for Tx hang with DFP enabled. */
2471 txdctl |= 32;
2472 }
2473
2474 /* reinitialize flowdirector state */
2475 set_bit(__IXGBE_FDIR_INIT_DONE, &ring->reinit_state);
2476
2477 /* enable queue */
2478 txdctl |= IXGBE_TXDCTL_ENABLE;
2479 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2480
2481 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2482 if (hw->mac.type == ixgbe_mac_82598EB &&
2483 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2484 return;
2485
2486 /* poll to verify queue is enabled */
2487 do {
2488 msleep(1);
2489 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2490 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2491 if (!wait_loop)
2492 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2493}
2494
120ff942
AD		 2495static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2496{
2497 struct ixgbe_hw *hw = &adapter->hw;
2498 u32 rttdcs;
2499 u32 mask;
2500
2501 if (hw->mac.type == ixgbe_mac_82598EB)
2502 return;
2503
2504 /* disable the arbiter while setting MTQC */
2505 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2506 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2507 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2508
2509 /* set transmit pool layout */
2510 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2511 switch (adapter->flags & mask) {
2512
2513 case (IXGBE_FLAG_SRIOV_ENABLED):
2514 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2515 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2516 break;
2517
2518 case (IXGBE_FLAG_DCB_ENABLED):
2519 /* We enable 8 traffic classes, DCB only */
2520 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2521 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2522 break;
2523
2524 default:
2525 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2526 break;
2527 }
2528
2529 /* re-enable the arbiter */
2530 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2531 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2532}
2533
9a799d71 2534/**
3a581073 2535 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2536 * @adapter: board private structure
2537 *
2538 * Configure the Tx unit of the MAC after a reset.
2539 **/
2540static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2541{
2f1860b8
AD		 2542 struct ixgbe_hw *hw = &adapter->hw;
2543 u32 dmatxctl;
43e69bf0 2544 u32 i;
9a799d71 2545
2f1860b8
AD		 2546 ixgbe_setup_mtqc(adapter);
2547
2548 if (hw->mac.type != ixgbe_mac_82598EB) {
2549 /* DMATXCTL.EN must be before Tx queues are enabled */
2550 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2551 dmatxctl |= IXGBE_DMATXCTL_TE;
2552 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2553 }
2554
9a799d71 2555 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2556 for (i = 0; i < adapter->num_tx_queues; i++)
2557 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2558}
2559
e8e26350 2560#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2561
a6616b42 2562static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2563 struct ixgbe_ring *rx_ring)
cc41ac7c 2564{
cc41ac7c 2565 u32 srrctl;
a6616b42 2566 int index;
0cefafad 2567 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 2568
a6616b42
YZ		 2569 index = rx_ring->reg_idx;
2570 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2571 unsigned long mask;
0cefafad 2572 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 2573 index = index & mask;
cc41ac7c 2574 }
cc41ac7c
JB		 2575 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2576
2577 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2578 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2579 if (adapter->num_vfs)
2580 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2581
afafd5b0
AD		 2582 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2583 IXGBE_SRRCTL_BSIZEHDR_MASK;
2584
6e455b89 2585 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 2586#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2587 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2588#else
2589 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2590#endif
cc41ac7c 2591 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2592 } else {
afafd5b0
AD		 2593 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2594 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2595 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2596 }
e8e26350 2597
cc41ac7c
JB		 2598 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2599}
9a799d71 2600
05abb126 2601static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2602{
05abb126
AD		 2603 struct ixgbe_hw *hw = &adapter->hw;
2604 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2605 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2606 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2607 u32 mrqc = 0, reta = 0;
2608 u32 rxcsum;
2609 int i, j;
0cefafad
JB		 2610 int mask;
2611
05abb126
AD		 2612 /* Fill out hash function seeds */
2613 for (i = 0; i < 10; i++)
2614 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2615
2616 /* Fill out redirection table */
2617 for (i = 0, j = 0; i < 128; i++, j++) {
2618 if (j == adapter->ring_feature[RING_F_RSS].indices)
2619 j = 0;
2620 /* reta = 4-byte sliding window of
2621 * 0x00..(indices-1)(indices-1)00..etc. */
2622 reta = (reta << 8) | (j * 0x11);
2623 if ((i & 3) == 3)
2624 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2625 }
0cefafad 2626
05abb126
AD		 2627 /* Disable indicating checksum in descriptor, enables RSS hash */
2628 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2629 rxcsum |= IXGBE_RXCSUM_PCSD;
2630 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2631
2632 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2633 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2634 else
2635 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
0cefafad 2636#ifdef CONFIG_IXGBE_DCB
05abb126 2637 | IXGBE_FLAG_DCB_ENABLED
0cefafad 2638#endif
05abb126
AD		 2639 | IXGBE_FLAG_SRIOV_ENABLED
2640 );
0cefafad
JB		 2641
2642 switch (mask) {
2643 case (IXGBE_FLAG_RSS_ENABLED):
2644 mrqc = IXGBE_MRQC_RSSEN;
2645 break;
1cdd1ec8
GR		 2646 case (IXGBE_FLAG_SRIOV_ENABLED):
2647 mrqc = IXGBE_MRQC_VMDQEN;
2648 break;
0cefafad
JB		 2649#ifdef CONFIG_IXGBE_DCB
2650 case (IXGBE_FLAG_DCB_ENABLED):
2651 mrqc = IXGBE_MRQC_RT8TCEN;
2652 break;
2653#endif /* CONFIG_IXGBE_DCB */
2654 default:
2655 break;
2656 }
2657
05abb126
AD		 2658 /* Perform hash on these packet types */
2659 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2660 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2661 | IXGBE_MRQC_RSS_FIELD_IPV6
2662 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2663
2664 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2665}
2666
bb5a9ad2
NS		 2667/**
2668 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2669 * @adapter: address of board private structure
2670 * @index: index of ring to set
bb5a9ad2 2671 **/
7367096a
AD		 2672static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2673 struct ixgbe_ring *ring)
bb5a9ad2 2674{
bb5a9ad2 2675 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2676 u32 rscctrl;
edd2ea55 2677 int rx_buf_len;
7367096a
AD		 2678 u16 reg_idx = ring->reg_idx;
2679
2680 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
2681 return;
bb5a9ad2 2682
7367096a
AD		 2683 rx_buf_len = ring->rx_buf_len;
2684 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2685 rscctrl |= IXGBE_RSCCTL_RSCEN;
2686 /*
2687 * we must limit the number of descriptors so that the
2688 * total size of max desc * buf_len is not greater
2689 * than 65535
2690 */
7367096a 2691 if (ring->flags & IXGBE_RING_RX_PS_ENABLED) {
bb5a9ad2
NS		 2692#if (MAX_SKB_FRAGS > 16)
2693 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2694#elif (MAX_SKB_FRAGS > 8)
2695 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2696#elif (MAX_SKB_FRAGS > 4)
2697 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2698#else
2699 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2700#endif
2701 } else {
2702 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2703 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2704 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2705 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2706 else
2707 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2708 }
7367096a 2709 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2710}
2711
9e10e045
AD		 2712/**
2713 * ixgbe_set_uta - Set unicast filter table address
2714 * @adapter: board private structure
2715 *
2716 * The unicast table address is a register array of 32-bit registers.
2717 * The table is meant to be used in a way similar to how the MTA is used
2718 * however due to certain limitations in the hardware it is necessary to
2719 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2720 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2721 **/
2722static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2723{
2724 struct ixgbe_hw *hw = &adapter->hw;
2725 int i;
2726
2727 /* The UTA table only exists on 82599 hardware and newer */
2728 if (hw->mac.type < ixgbe_mac_82599EB)
2729 return;
2730
2731 /* we only need to do this if VMDq is enabled */
2732 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2733 return;
2734
2735 for (i = 0; i < 128; i++)
2736 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2737}
2738
2739#define IXGBE_MAX_RX_DESC_POLL 10
2740static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2741 struct ixgbe_ring *ring)
2742{
2743 struct ixgbe_hw *hw = &adapter->hw;
2744 int reg_idx = ring->reg_idx;
2745 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2746 u32 rxdctl;
2747
2748 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2749 if (hw->mac.type == ixgbe_mac_82598EB &&
2750 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2751 return;
2752
2753 do {
2754 msleep(1);
2755 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2756 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2757
2758 if (!wait_loop) {
2759 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2760 "the polling period\n", reg_idx);
2761 }
2762}
2763
84418e3b
AD		 2764void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2765 struct ixgbe_ring *ring)
acd37177
AD		 2766{
2767 struct ixgbe_hw *hw = &adapter->hw;
2768 u64 rdba = ring->dma;
9e10e045 2769 u32 rxdctl;
acd37177
AD		 2770 u16 reg_idx = ring->reg_idx;
2771
9e10e045
AD		 2772 /* disable queue to avoid issues while updating state */
2773 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2774 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
2775 rxdctl & ~IXGBE_RXDCTL_ENABLE);
2776 IXGBE_WRITE_FLUSH(hw);
2777
acd37177
AD		 2778 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2779 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2780 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2781 ring->count * sizeof(union ixgbe_adv_rx_desc));
2782 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2783 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2784 ring->head = IXGBE_RDH(reg_idx);
2785 ring->tail = IXGBE_RDT(reg_idx);
9e10e045
AD		 2786
2787 ixgbe_configure_srrctl(adapter, ring);
2788 ixgbe_configure_rscctl(adapter, ring);
2789
2790 if (hw->mac.type == ixgbe_mac_82598EB) {
2791 /*
2792 * enable cache line friendly hardware writes:
2793 * PTHRESH=32 descriptors (half the internal cache),
2794 * this also removes ugly rx_no_buffer_count increment
2795 * HTHRESH=4 descriptors (to minimize latency on fetch)
2796 * WTHRESH=8 burst writeback up to two cache lines
2797 */
2798 rxdctl &= ~0x3FFFFF;
2799 rxdctl |= 0x080420;
2800 }
2801
2802 /* enable receive descriptor ring */
2803 rxdctl |= IXGBE_RXDCTL_ENABLE;
2804 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2805
2806 ixgbe_rx_desc_queue_enable(adapter, ring);
2807 ixgbe_alloc_rx_buffers(adapter, ring, IXGBE_DESC_UNUSED(ring));
acd37177
AD		 2808}
2809
48654521
AD		 2810static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2811{
2812 struct ixgbe_hw *hw = &adapter->hw;
2813 int p;
2814
2815 /* PSRTYPE must be initialized in non 82598 adapters */
2816 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 2817 IXGBE_PSRTYPE_UDPHDR |
2818 IXGBE_PSRTYPE_IPV4HDR |
48654521 2819 IXGBE_PSRTYPE_L2HDR |
e8e9f696 2820 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 2821
2822 if (hw->mac.type == ixgbe_mac_82598EB)
2823 return;
2824
2825 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2826 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2827
2828 for (p = 0; p < adapter->num_rx_pools; p++)
2829 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2830 psrtype);
2831}
2832
f5b4a52e
AD		 2833static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2834{
2835 struct ixgbe_hw *hw = &adapter->hw;
2836 u32 gcr_ext;
2837 u32 vt_reg_bits;
2838 u32 reg_offset, vf_shift;
2839 u32 vmdctl;
2840
2841 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2842 return;
2843
2844 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2845 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2846 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2847 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2848
2849 vf_shift = adapter->num_vfs % 32;
2850 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2851
2852 /* Enable only the PF's pool for Tx/Rx */
2853 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2854 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2855 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2856 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2857 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2858
2859 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2860 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2861
2862 /*
2863 * Set up VF register offsets for selected VT Mode,
2864 * i.e. 32 or 64 VFs for SR-IOV
2865 */
2866 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2867 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2868 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2869 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2870
2871 /* enable Tx loopback for VF/PF communication */
2872 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2873}
2874
477de6ed 2875static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 2876{
9a799d71
AK		 2877 struct ixgbe_hw *hw = &adapter->hw;
2878 struct net_device *netdev = adapter->netdev;
2879 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 2880 int rx_buf_len;
477de6ed
AD		 2881 struct ixgbe_ring *rx_ring;
2882 int i;
2883 u32 mhadd, hlreg0;
48654521 2884
9a799d71 2885 /* Decide whether to use packet split mode or not */
1cdd1ec8
GR		 2886 /* Do not use packet split if we're in SR-IOV Mode */
2887 if (!adapter->num_vfs)
2888 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 2889
2890 /* Set the RX buffer length according to the mode */
2891 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2892 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71 2893 } else {
0c19d6af 2894 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2895 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2896 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2897 else
477de6ed 2898 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
9a799d71
AK		 2899 }
2900
63f39bd1 2901#ifdef IXGBE_FCOE
477de6ed
AD		 2902 /* adjust max frame to be able to do baby jumbo for FCoE */
2903 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2904 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2905 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 2906
477de6ed
AD		 2907#endif /* IXGBE_FCOE */
2908 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2909 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2910 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2911 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2912
2913 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2914 }
2915
2916 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2917 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2918 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2919 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 2920
0cefafad
JB		 2921 /*
2922 * Setup the HW Rx Head and Tail Descriptor Pointers and
2923 * the Base and Length of the Rx Descriptor Ring
2924 */
9a799d71 2925 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2926 rx_ring = adapter->rx_ring[i];
a6616b42 2927 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2928
6e455b89
YZ		 2929 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2930 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
1b3ff02e
PWJ		 2931 else
2932 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2933
63f39bd1 2934#ifdef IXGBE_FCOE
e8e9f696 2935 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2936 struct ixgbe_ring_feature *f;
2937 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2938 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2939 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2940 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2941 rx_ring->rx_buf_len =
e8e9f696 2942 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 2943 }
63f39bd1 2944 }
63f39bd1 2945#endif /* IXGBE_FCOE */
477de6ed
AD		 2946 }
2947
2948}
2949
7367096a
AD		 2950static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2951{
2952 struct ixgbe_hw *hw = &adapter->hw;
2953 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2954
2955 switch (hw->mac.type) {
2956 case ixgbe_mac_82598EB:
2957 /*
2958 * For VMDq support of different descriptor types or
2959 * buffer sizes through the use of multiple SRRCTL
2960 * registers, RDRXCTL.MVMEN must be set to 1
2961 *
2962 * also, the manual doesn't mention it clearly but DCA hints
2963 * will only use queue 0's tags unless this bit is set. Side
2964 * effects of setting this bit are only that SRRCTL must be
2965 * fully programmed [0..15]
2966 */
2967 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2968 break;
2969 case ixgbe_mac_82599EB:
2970 /* Disable RSC for ACK packets */
2971 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2972 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2973 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2974 /* hardware requires some bits to be set by default */
2975 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
2976 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2977 break;
2978 default:
2979 /* We should do nothing since we don't know this hardware */
2980 return;
2981 }
2982
2983 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2984}
2985
477de6ed
AD		 2986/**
2987 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2988 * @adapter: board private structure
2989 *
2990 * Configure the Rx unit of the MAC after a reset.
2991 **/
2992static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2993{
2994 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 2995 int i;
2996 u32 rxctrl;
477de6ed
AD		 2997
2998 /* disable receives while setting up the descriptors */
2999 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3000 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3001
3002 ixgbe_setup_psrtype(adapter);
7367096a 3003 ixgbe_setup_rdrxctl(adapter);
477de6ed 3004
9e10e045 3005 /* Program registers for the distribution of queues */
f5b4a52e 3006 ixgbe_setup_mrqc(adapter);
f5b4a52e 3007
9e10e045
AD		 3008 ixgbe_set_uta(adapter);
3009
477de6ed
AD		 3010 /* set_rx_buffer_len must be called before ring initialization */
3011 ixgbe_set_rx_buffer_len(adapter);
3012
3013 /*
3014 * Setup the HW Rx Head and Tail Descriptor Pointers and
3015 * the Base and Length of the Rx Descriptor Ring
3016 */
9e10e045
AD		 3017 for (i = 0; i < adapter->num_rx_queues; i++)
3018 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3019
9e10e045
AD		 3020 /* disable drop enable for 82598 parts */
3021 if (hw->mac.type == ixgbe_mac_82598EB)
3022 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3023
3024 /* enable all receives */
3025 rxctrl |= IXGBE_RXCTRL_RXEN;
3026 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3027}
3028
068c89b0
DS		 3029static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3030{
3031 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3032 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3033 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3034
3035 /* add VID to filter table */
1ada1b1b 3036 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
068c89b0
DS		 3037}
3038
3039static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3040{
3041 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3042 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3043 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3044
3045 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3046 ixgbe_irq_disable(adapter);
3047
3048 vlan_group_set_device(adapter->vlgrp, vid, NULL);
3049
3050 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3051 ixgbe_irq_enable(adapter);
3052
3053 /* remove VID from filter table */
1ada1b1b 3054 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
068c89b0
DS		 3055}
3056
5f6c0181
JB		 3057/**
3058 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3059 * @adapter: driver data
3060 */
3061static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3062{
3063 struct ixgbe_hw *hw = &adapter->hw;
3064 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3065 int i, j;
3066
3067 switch (hw->mac.type) {
3068 case ixgbe_mac_82598EB:
38e0bd98
YZ		 3069 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
3070#ifdef CONFIG_IXGBE_DCB
3071 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3072 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3073#endif
5f6c0181
JB		 3074 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3075 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3076 break;
3077 case ixgbe_mac_82599EB:
3078 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
3079 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3080 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
38e0bd98
YZ		 3081#ifdef CONFIG_IXGBE_DCB
3082 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
3083 break;
3084#endif
5f6c0181
JB		 3085 for (i = 0; i < adapter->num_rx_queues; i++) {
3086 j = adapter->rx_ring[i]->reg_idx;
3087 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3088 vlnctrl &= ~IXGBE_RXDCTL_VME;
3089 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3090 }
3091 break;
3092 default:
3093 break;
3094 }
3095}
3096
3097/**
3098 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3099 * @adapter: driver data
3100 */
3101static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3102{
3103 struct ixgbe_hw *hw = &adapter->hw;
3104 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3105 int i, j;
3106
3107 switch (hw->mac.type) {
3108 case ixgbe_mac_82598EB:
3109 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
3110 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3111 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3112 break;
3113 case ixgbe_mac_82599EB:
3114 vlnctrl |= IXGBE_VLNCTRL_VFE;
3115 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3116 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3117 for (i = 0; i < adapter->num_rx_queues; i++) {
3118 j = adapter->rx_ring[i]->reg_idx;
3119 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3120 vlnctrl |= IXGBE_RXDCTL_VME;
3121 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3122 }
3123 break;
3124 default:
3125 break;
3126 }
3127}
3128
9a799d71 3129static void ixgbe_vlan_rx_register(struct net_device *netdev,
e8e9f696 3130 struct vlan_group *grp)
9a799d71
AK		 3131{
3132 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 3133
d4f80882
AV		 3134 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3135 ixgbe_irq_disable(adapter);
9a799d71
AK		 3136 adapter->vlgrp = grp;
3137
2f90b865
AD		 3138 /*
3139 * For a DCB driver, always enable VLAN tag stripping so we can
3140 * still receive traffic from a DCB-enabled host even if we're
3141 * not in DCB mode.
3142 */
5f6c0181 3143 ixgbe_vlan_filter_enable(adapter);
dc63d377 3144
e8e26350 3145 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 3146
d4f80882
AV		 3147 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3148 ixgbe_irq_enable(adapter);
9a799d71
AK		 3149}
3150
9a799d71
AK		 3151static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3152{
3153 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
3154
3155 if (adapter->vlgrp) {
3156 u16 vid;
3157 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
3158 if (!vlan_group_get_device(adapter->vlgrp, vid))
3159 continue;
3160 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3161 }
3162 }
3163}
3164
2850062a
AD		 3165/**
3166 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3167 * @netdev: network interface device structure
3168 *
3169 * Writes unicast address list to the RAR table.
3170 * Returns: -ENOMEM on failure/insufficient address space
3171 * 0 on no addresses written
3172 * X on writing X addresses to the RAR table
3173 **/
3174static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3175{
3176 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3177 struct ixgbe_hw *hw = &adapter->hw;
3178 unsigned int vfn = adapter->num_vfs;
3179 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3180 int count = 0;
3181
3182 /* return ENOMEM indicating insufficient memory for addresses */
3183 if (netdev_uc_count(netdev) > rar_entries)
3184 return -ENOMEM;
3185
3186 if (!netdev_uc_empty(netdev) && rar_entries) {
3187 struct netdev_hw_addr *ha;
3188 /* return error if we do not support writing to RAR table */
3189 if (!hw->mac.ops.set_rar)
3190 return -ENOMEM;
3191
3192 netdev_for_each_uc_addr(ha, netdev) {
3193 if (!rar_entries)
3194 break;
3195 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3196 vfn, IXGBE_RAH_AV);
3197 count++;
3198 }
3199 }
3200 /* write the addresses in reverse order to avoid write combining */
3201 for (; rar_entries > 0 ; rar_entries--)
3202 hw->mac.ops.clear_rar(hw, rar_entries);
3203
3204 return count;
3205}
3206
9a799d71 3207/**
2c5645cf 3208 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3209 * @netdev: network interface device structure
3210 *
2c5645cf
CL		 3211 * The set_rx_method entry point is called whenever the unicast/multicast
3212 * address list or the network interface flags are updated. This routine is
3213 * responsible for configuring the hardware for proper unicast, multicast and
3214 * promiscuous mode.
9a799d71 3215 **/
7f870475 3216void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3217{
3218 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3219 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3220 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3221 int count;
9a799d71
AK		 3222
3223 /* Check for Promiscuous and All Multicast modes */
3224
3225 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3226
f5dc442b
AD		 3227 /* set all bits that we expect to always be set */
3228 fctrl |= IXGBE_FCTRL_BAM;
3229 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3230 fctrl |= IXGBE_FCTRL_PMCF;
3231
2850062a
AD		 3232 /* clear the bits we are changing the status of */
3233 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3234
9a799d71 3235 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3236 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3237 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3238 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3239 /* don't hardware filter vlans in promisc mode */
3240 ixgbe_vlan_filter_disable(adapter);
9a799d71 3241 } else {
746b9f02
PM		 3242 if (netdev->flags & IFF_ALLMULTI) {
3243 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3244 vmolr |= IXGBE_VMOLR_MPE;
3245 } else {
3246 /*
3247 * Write addresses to the MTA, if the attempt fails
3248 * then we should just turn on promiscous mode so
3249 * that we can at least receive multicast traffic
3250 */
3251 hw->mac.ops.update_mc_addr_list(hw, netdev);
3252 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3253 }
5f6c0181 3254 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3255 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3256 /*
3257 * Write addresses to available RAR registers, if there is not
3258 * sufficient space to store all the addresses then enable
3259 * unicast promiscous mode
3260 */
3261 count = ixgbe_write_uc_addr_list(netdev);
3262 if (count < 0) {
3263 fctrl |= IXGBE_FCTRL_UPE;
3264 vmolr |= IXGBE_VMOLR_ROPE;
3265 }
9a799d71
AK		 3266 }
3267
2850062a 3268 if (adapter->num_vfs) {
1cdd1ec8 3269 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3270 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3271 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3272 IXGBE_VMOLR_ROPE);
3273 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3274 }
3275
3276 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
9a799d71
AK		 3277}
3278
021230d4
AV		 3279static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3280{
3281 int q_idx;
3282 struct ixgbe_q_vector *q_vector;
3283 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3284
3285 /* legacy and MSI only use one vector */
3286 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3287 q_vectors = 1;
3288
3289 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 3290 struct napi_struct *napi;
7a921c93 3291 q_vector = adapter->q_vector[q_idx];
f0848276 3292 napi = &q_vector->napi;
91281fd3
AD		 3293 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3294 if (!q_vector->rxr_count || !q_vector->txr_count) {
3295 if (q_vector->txr_count == 1)
3296 napi->poll = &ixgbe_clean_txonly;
3297 else if (q_vector->rxr_count == 1)
3298 napi->poll = &ixgbe_clean_rxonly;
3299 }
3300 }
f0848276
JB		 3301
3302 napi_enable(napi);
021230d4
AV		 3303 }
3304}
3305
3306static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3307{
3308 int q_idx;
3309 struct ixgbe_q_vector *q_vector;
3310 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3311
3312 /* legacy and MSI only use one vector */
3313 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3314 q_vectors = 1;
3315
3316 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3317 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3318 napi_disable(&q_vector->napi);
3319 }
3320}
3321
7a6b6f51 3322#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3323/*
3324 * ixgbe_configure_dcb - Configure DCB hardware
3325 * @adapter: ixgbe adapter struct
3326 *
3327 * This is called by the driver on open to configure the DCB hardware.
3328 * This is also called by the gennetlink interface when reconfiguring
3329 * the DCB state.
3330 */
3331static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3332{
3333 struct ixgbe_hw *hw = &adapter->hw;
5f6c0181 3334 u32 txdctl;
2f90b865
AD		 3335 int i, j;
3336
67ebd791
AD		 3337 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3338 if (hw->mac.type == ixgbe_mac_82598EB)
3339 netif_set_gso_max_size(adapter->netdev, 65536);
3340 return;
3341 }
3342
3343 if (hw->mac.type == ixgbe_mac_82598EB)
3344 netif_set_gso_max_size(adapter->netdev, 32768);
3345
2f90b865
AD		 3346 ixgbe_dcb_check_config(&adapter->dcb_cfg);
3347 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
3348 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
3349
3350 /* reconfigure the hardware */
3351 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3352
3353 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3354 j = adapter->tx_ring[i]->reg_idx;
2f90b865
AD		 3355 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3356 /* PThresh workaround for Tx hang with DFP enabled. */
3357 txdctl |= 32;
3358 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3359 }
3360 /* Enable VLAN tag insert/strip */
5f6c0181
JB		 3361 ixgbe_vlan_filter_enable(adapter);
3362
2f90b865
AD		 3363 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3364}
3365
3366#endif
9a799d71
AK		 3367static void ixgbe_configure(struct ixgbe_adapter *adapter)
3368{
3369 struct net_device *netdev = adapter->netdev;
c4cf55e5 3370 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3371 int i;
3372
2c5645cf 3373 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 3374
3375 ixgbe_restore_vlan(adapter);
7a6b6f51 3376#ifdef CONFIG_IXGBE_DCB
67ebd791 3377 ixgbe_configure_dcb(adapter);
2f90b865 3378#endif
9a799d71 3379
eacd73f7
YZ		 3380#ifdef IXGBE_FCOE
3381 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3382 ixgbe_configure_fcoe(adapter);
3383
3384#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3385 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3386 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3387 adapter->tx_ring[i]->atr_sample_rate =
e8e9f696 3388 adapter->atr_sample_rate;
c4cf55e5
PWJ		 3389 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3390 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3391 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3392 }
933d41f1 3393 ixgbe_configure_virtualization(adapter);
c4cf55e5 3394
9a799d71
AK		 3395 ixgbe_configure_tx(adapter);
3396 ixgbe_configure_rx(adapter);
9a799d71
AK		 3397}
3398
e8e26350
PW		 3399static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3400{
3401 switch (hw->phy.type) {
3402 case ixgbe_phy_sfp_avago:
3403 case ixgbe_phy_sfp_ftl:
3404 case ixgbe_phy_sfp_intel:
3405 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3406 case ixgbe_phy_sfp_passive_tyco:
3407 case ixgbe_phy_sfp_passive_unknown:
3408 case ixgbe_phy_sfp_active_unknown:
3409 case ixgbe_phy_sfp_ftl_active:
e8e26350
PW		 3410 return true;
3411 default:
3412 return false;
3413 }
3414}
3415
0ecc061d 3416/**
e8e26350
PW		 3417 * ixgbe_sfp_link_config - set up SFP+ link
3418 * @adapter: pointer to private adapter struct
3419 **/
3420static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3421{
3422 struct ixgbe_hw *hw = &adapter->hw;
3423
3424 if (hw->phy.multispeed_fiber) {
3425 /*
3426 * In multispeed fiber setups, the device may not have
3427 * had a physical connection when the driver loaded.
3428 * If that's the case, the initial link configuration
3429 * couldn't get the MAC into 10G or 1G mode, so we'll
3430 * never have a link status change interrupt fire.
3431 * We need to try and force an autonegotiation
3432 * session, then bring up link.
3433 */
3434 hw->mac.ops.setup_sfp(hw);
3435 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3436 schedule_work(&adapter->multispeed_fiber_task);
3437 } else {
3438 /*
3439 * Direct Attach Cu and non-multispeed fiber modules
3440 * still need to be configured properly prior to
3441 * attempting link.
3442 */
3443 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3444 schedule_work(&adapter->sfp_config_module_task);
3445 }
3446}
3447
3448/**
3449 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3450 * @hw: pointer to private hardware struct
3451 *
3452 * Returns 0 on success, negative on failure
3453 **/
e8e26350 3454static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3455{
3456 u32 autoneg;
8620a103 3457 bool negotiation, link_up = false;
0ecc061d
PWJ		 3458 u32 ret = IXGBE_ERR_LINK_SETUP;
3459
3460 if (hw->mac.ops.check_link)
3461 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3462
3463 if (ret)
3464 goto link_cfg_out;
3465
3466 if (hw->mac.ops.get_link_capabilities)
e8e9f696
JP		 3467 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3468 &negotiation);
0ecc061d
PWJ		 3469 if (ret)
3470 goto link_cfg_out;
3471
8620a103
MC		 3472 if (hw->mac.ops.setup_link)
3473 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3474link_cfg_out:
3475 return ret;
3476}
3477
a34bcfff 3478static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3479{
9a799d71 3480 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3481 u32 gpie = 0;
9a799d71 3482
9b471446 3483 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3484 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3485 IXGBE_GPIE_OCD;
3486 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3487 /*
3488 * use EIAM to auto-mask when MSI-X interrupt is asserted
3489 * this saves a register write for every interrupt
3490 */
3491 switch (hw->mac.type) {
3492 case ixgbe_mac_82598EB:
3493 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3494 break;
3495 default:
3496 case ixgbe_mac_82599EB:
3497 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3498 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3499 break;
3500 }
3501 } else {
021230d4
AV		 3502 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3503 * specifically only auto mask tx and rx interrupts */
3504 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3505 }
9a799d71 3506
a34bcfff
AD		 3507 /* XXX: to interrupt immediately for EICS writes, enable this */
3508 /* gpie |= IXGBE_GPIE_EIMEN; */
3509
3510 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3511 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3512 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3513 }
3514
a34bcfff
AD		 3515 /* Enable fan failure interrupt */
3516 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3517 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3518
a34bcfff 3519 if (hw->mac.type == ixgbe_mac_82599EB)
e8e26350
PW		 3520 gpie |= IXGBE_SDP1_GPIEN;
3521 gpie |= IXGBE_SDP2_GPIEN;
a34bcfff
AD		 3522
3523 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3524}
3525
3526static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3527{
3528 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3529 int err;
a34bcfff
AD		 3530 u32 ctrl_ext;
3531
3532 ixgbe_get_hw_control(adapter);
3533 ixgbe_setup_gpie(adapter);
e8e26350 3534
9a799d71
AK		 3535 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3536 ixgbe_configure_msix(adapter);
3537 else
3538 ixgbe_configure_msi_and_legacy(adapter);
3539
61fac744
PW		 3540 /* enable the optics */
3541 if (hw->phy.multispeed_fiber)
3542 hw->mac.ops.enable_tx_laser(hw);
3543
9a799d71 3544 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3545 ixgbe_napi_enable_all(adapter);
3546
3547 /* clear any pending interrupts, may auto mask */
3548 IXGBE_READ_REG(hw, IXGBE_EICR);
9a799d71
AK		 3549 ixgbe_irq_enable(adapter);
3550
bf069c97
DS		 3551 /*
3552 * If this adapter has a fan, check to see if we had a failure
3553 * before we enabled the interrupt.
3554 */
3555 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3556 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3557 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3558 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3559 }
3560
e8e26350
PW		 3561 /*
3562 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 3563 * arrived before interrupts were enabled but after probe. Such
3564 * devices wouldn't have their type identified yet. We need to
3565 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 3566 * If we're not hot-pluggable SFP+, we just need to configure link
3567 * and bring it up.
3568 */
19343de2
DS		 3569 if (hw->phy.type == ixgbe_phy_unknown) {
3570 err = hw->phy.ops.identify(hw);
3571 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 3572 /*
3573 * Take the device down and schedule the sfp tasklet
3574 * which will unregister_netdev and log it.
3575 */
19343de2 3576 ixgbe_down(adapter);
5da43c1a 3577 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 3578 return err;
3579 }
e8e26350
PW		 3580 }
3581
3582 if (ixgbe_is_sfp(hw)) {
3583 ixgbe_sfp_link_config(adapter);
3584 } else {
3585 err = ixgbe_non_sfp_link_config(hw);
3586 if (err)
396e799c 3587 e_err(probe, "link_config FAILED %d\n", err);
e8e26350 3588 }
0ecc061d 3589
1da100bb 3590 /* enable transmits */
477de6ed 3591 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3592
9a799d71
AK		 3593 /* bring the link up in the watchdog, this could race with our first
3594 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3595 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3596 adapter->link_check_timeout = jiffies;
9a799d71 3597 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3598
3599 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3600 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3601 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3602 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3603
9a799d71
AK		 3604 return 0;
3605}
3606
d4f80882
AV		 3607void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3608{
3609 WARN_ON(in_interrupt());
3610 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3611 msleep(1);
3612 ixgbe_down(adapter);
5809a1ae
GR		 3613 /*
3614 * If SR-IOV enabled then wait a bit before bringing the adapter
3615 * back up to give the VFs time to respond to the reset. The
3616 * two second wait is based upon the watchdog timer cycle in
3617 * the VF driver.
3618 */
3619 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3620 msleep(2000);
d4f80882
AV		 3621 ixgbe_up(adapter);
3622 clear_bit(__IXGBE_RESETTING, &adapter->state);
3623}
3624
9a799d71
AK		 3625int ixgbe_up(struct ixgbe_adapter *adapter)
3626{
3627 /* hardware has been reset, we need to reload some things */
3628 ixgbe_configure(adapter);
3629
3630 return ixgbe_up_complete(adapter);
3631}
3632
3633void ixgbe_reset(struct ixgbe_adapter *adapter)
3634{
c44ade9e 3635 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3636 int err;
3637
3638 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3639 switch (err) {
3640 case 0:
3641 case IXGBE_ERR_SFP_NOT_PRESENT:
3642 break;
3643 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3644 e_dev_err("master disable timed out\n");
da4dd0f7 3645 break;
794caeb2
PWJ		 3646 case IXGBE_ERR_EEPROM_VERSION:
3647 /* We are running on a pre-production device, log a warning */
849c4542
ET		 3648 e_dev_warn("This device is a pre-production adapter/LOM. "
3649 "Please be aware there may be issuesassociated with "
3650 "your hardware. If you are experiencing problems "
3651 "please contact your Intel or hardware "
3652 "representative who provided you with this "
3653 "hardware.\n");
794caeb2 3654 break;
da4dd0f7 3655 default:
849c4542 3656 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3657 }
9a799d71
AK		 3658
3659 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3660 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3661 IXGBE_RAH_AV);
9a799d71
AK		 3662}
3663
9a799d71
AK		 3664/**
3665 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3666 * @adapter: board private structure
3667 * @rx_ring: ring to free buffers from
3668 **/
3669static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
e8e9f696 3670 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3671{
3672 struct pci_dev *pdev = adapter->pdev;
3673 unsigned long size;
3674 unsigned int i;
3675
84418e3b
AD		 3676 /* ring already cleared, nothing to do */
3677 if (!rx_ring->rx_buffer_info)
3678 return;
9a799d71 3679
84418e3b 3680 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 3681 for (i = 0; i < rx_ring->count; i++) {
3682 struct ixgbe_rx_buffer *rx_buffer_info;
3683
3684 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3685 if (rx_buffer_info->dma) {
1b507730 3686 dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
e8e9f696 3687 rx_ring->rx_buf_len,
1b507730 3688 DMA_FROM_DEVICE);
9a799d71
AK		 3689 rx_buffer_info->dma = 0;
3690 }
3691 if (rx_buffer_info->skb) {
f8212f97 3692 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3693 rx_buffer_info->skb = NULL;
f8212f97
AD		 3694 do {
3695 struct sk_buff *this = skb;
e8171aaa 3696 if (IXGBE_RSC_CB(this)->delay_unmap) {
1b507730
NN		 3697 dma_unmap_single(&pdev->dev,
3698 IXGBE_RSC_CB(this)->dma,
e8e9f696 3699 rx_ring->rx_buf_len,
1b507730 3700 DMA_FROM_DEVICE);
fd3686a8 3701 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 3702 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 3703 }
f8212f97
AD		 3704 skb = skb->prev;
3705 dev_kfree_skb(this);
3706 } while (skb);
9a799d71
AK		 3707 }
3708 if (!rx_buffer_info->page)
3709 continue;
4f57ca6e 3710 if (rx_buffer_info->page_dma) {
1b507730
NN		 3711 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3712 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 3713 rx_buffer_info->page_dma = 0;
3714 }
9a799d71
AK		 3715 put_page(rx_buffer_info->page);
3716 rx_buffer_info->page = NULL;
762f4c57 3717 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3718 }
3719
3720 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3721 memset(rx_ring->rx_buffer_info, 0, size);
3722
3723 /* Zero out the descriptor ring */
3724 memset(rx_ring->desc, 0, rx_ring->size);
3725
3726 rx_ring->next_to_clean = 0;
3727 rx_ring->next_to_use = 0;
3728
9891ca7c
JB		 3729 if (rx_ring->head)
3730 writel(0, adapter->hw.hw_addr + rx_ring->head);
3731 if (rx_ring->tail)
3732 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 3733}
3734
3735/**
3736 * ixgbe_clean_tx_ring - Free Tx Buffers
3737 * @adapter: board private structure
3738 * @tx_ring: ring to be cleaned
3739 **/
3740static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
e8e9f696 3741 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3742{
3743 struct ixgbe_tx_buffer *tx_buffer_info;
3744 unsigned long size;
3745 unsigned int i;
3746
84418e3b
AD		 3747 /* ring already cleared, nothing to do */
3748 if (!tx_ring->tx_buffer_info)
3749 return;
9a799d71 3750
84418e3b 3751 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 3752 for (i = 0; i < tx_ring->count; i++) {
3753 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3754 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3755 }
3756
3757 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3758 memset(tx_ring->tx_buffer_info, 0, size);
3759
3760 /* Zero out the descriptor ring */
3761 memset(tx_ring->desc, 0, tx_ring->size);
3762
3763 tx_ring->next_to_use = 0;
3764 tx_ring->next_to_clean = 0;
3765
9891ca7c
JB		 3766 if (tx_ring->head)
3767 writel(0, adapter->hw.hw_addr + tx_ring->head);
3768 if (tx_ring->tail)
3769 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 3770}
3771
3772/**
021230d4 3773 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3774 * @adapter: board private structure
3775 **/
021230d4 3776static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3777{
3778 int i;
3779
021230d4 3780 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3781 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
9a799d71
AK		 3782}
3783
3784/**
021230d4 3785 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3786 * @adapter: board private structure
3787 **/
021230d4 3788static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3789{
3790 int i;
3791
021230d4 3792 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3793 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3794}
3795
3796void ixgbe_down(struct ixgbe_adapter *adapter)
3797{
3798 struct net_device *netdev = adapter->netdev;
7f821875 3799 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3800 u32 rxctrl;
7f821875
JB		 3801 u32 txdctl;
3802 int i, j;
9a799d71
AK		 3803
3804 /* signal that we are down to the interrupt handler */
3805 set_bit(__IXGBE_DOWN, &adapter->state);
3806
767081ad
GR		 3807 /* disable receive for all VFs and wait one second */
3808 if (adapter->num_vfs) {
767081ad
GR		 3809 /* ping all the active vfs to let them know we are going down */
3810 ixgbe_ping_all_vfs(adapter);
581d1aa7 3811
767081ad
GR		 3812 /* Disable all VFTE/VFRE TX/RX */
3813 ixgbe_disable_tx_rx(adapter);
581d1aa7
GR		 3814
3815 /* Mark all the VFs as inactive */
3816 for (i = 0 ; i < adapter->num_vfs; i++)
3817 adapter->vfinfo[i].clear_to_send = 0;
767081ad
GR		 3818 }
3819
9a799d71 3820 /* disable receives */
7f821875
JB		 3821 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3822 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 3823
7f821875 3824 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 3825 msleep(10);
3826
7f821875
JB		 3827 netif_tx_stop_all_queues(netdev);
3828
0a1f87cb
DS		 3829 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3830 del_timer_sync(&adapter->sfp_timer);
9a799d71 3831 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 3832 cancel_work_sync(&adapter->watchdog_task);
9a799d71 3833
c0dfb90e
JF		 3834 netif_carrier_off(netdev);
3835 netif_tx_disable(netdev);
3836
3837 ixgbe_irq_disable(adapter);
3838
3839 ixgbe_napi_disable_all(adapter);
3840
c4cf55e5
PWJ		 3841 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3842 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3843 cancel_work_sync(&adapter->fdir_reinit_task);
3844
119fc60a
MC		 3845 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3846 cancel_work_sync(&adapter->check_overtemp_task);
3847
7f821875
JB		 3848 /* disable transmits in the hardware now that interrupts are off */
3849 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3850 j = adapter->tx_ring[i]->reg_idx;
7f821875
JB		 3851 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3852 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
e8e9f696 3853 (txdctl & ~IXGBE_TXDCTL_ENABLE));
7f821875 3854 }
88512539
PW		 3855 /* Disable the Tx DMA engine on 82599 */
3856 if (hw->mac.type == ixgbe_mac_82599EB)
3857 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 3858 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3859 ~IXGBE_DMATXCTL_TE));
7f821875 3860
9f756f01
JF		 3861 /* power down the optics */
3862 if (hw->phy.multispeed_fiber)
3863 hw->mac.ops.disable_tx_laser(hw);
3864
9a713e7c
PW		 3865 /* clear n-tuple filters that are cached */
3866 ethtool_ntuple_flush(netdev);
3867
6f4a0e45
PL		 3868 if (!pci_channel_offline(adapter->pdev))
3869 ixgbe_reset(adapter);
9a799d71
AK		 3870 ixgbe_clean_all_tx_rings(adapter);
3871 ixgbe_clean_all_rx_rings(adapter);
3872
5dd2d332 3873#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3874 /* since we reset the hardware DCA settings were cleared */
e35ec126 3875 ixgbe_setup_dca(adapter);
96b0e0f6 3876#endif
9a799d71
AK		 3877}
3878
9a799d71 3879/**
021230d4
AV		 3880 * ixgbe_poll - NAPI Rx polling callback
3881 * @napi: structure for representing this polling device
3882 * @budget: how many packets driver is allowed to clean
3883 *
3884 * This function is used for legacy and MSI, NAPI mode
9a799d71 3885 **/
021230d4 3886static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3887{
9a1a69ad 3888 struct ixgbe_q_vector *q_vector =
e8e9f696 3889 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3890 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 3891 int tx_clean_complete, work_done = 0;
9a799d71 3892
5dd2d332 3893#ifdef CONFIG_IXGBE_DCA
bd0362dd 3894 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4a0b9ca0
PW		 3895 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3896 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
bd0362dd
JC		 3897 }
3898#endif
3899
4a0b9ca0
PW		 3900 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3901 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 3902
9a1a69ad 3903 if (!tx_clean_complete)
d2c7ddd6
DM		 3904 work_done = budget;
3905
53e52c72
DM		 3906 /* If budget not fully consumed, exit the polling mode */
3907 if (work_done < budget) {
288379f0 3908 napi_complete(napi);
f7554a2b 3909 if (adapter->rx_itr_setting & 1)
f494e8fa 3910 ixgbe_set_itr(adapter);
d4f80882 3911 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 3912 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 3913 }
9a799d71
AK		 3914 return work_done;
3915}
3916
3917/**
3918 * ixgbe_tx_timeout - Respond to a Tx Hang
3919 * @netdev: network interface device structure
3920 **/
3921static void ixgbe_tx_timeout(struct net_device *netdev)
3922{
3923 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3924
3925 /* Do the reset outside of interrupt context */
3926 schedule_work(&adapter->reset_task);
3927}
3928
3929static void ixgbe_reset_task(struct work_struct *work)
3930{
3931 struct ixgbe_adapter *adapter;
3932 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3933
2f90b865
AD		 3934 /* If we're already down or resetting, just bail */
3935 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3936 test_bit(__IXGBE_RESETTING, &adapter->state))
3937 return;
3938
9a799d71
AK		 3939 adapter->tx_timeout_count++;
3940
dcd79aeb
TI		 3941 ixgbe_dump(adapter);
3942 netdev_err(adapter->netdev, "Reset adapter\n");
d4f80882 3943 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3944}
3945
bc97114d
PWJ		 3946#ifdef CONFIG_IXGBE_DCB
3947static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3948{
bc97114d 3949 bool ret = false;
0cefafad 3950 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3951
0cefafad
JB		 3952 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3953 return ret;
3954
3955 f->mask = 0x7 << 3;
3956 adapter->num_rx_queues = f->indices;
3957 adapter->num_tx_queues = f->indices;
3958 ret = true;
2f90b865 3959
bc97114d
PWJ		 3960 return ret;
3961}
3962#endif
3963
4df10466
JB		 3964/**
3965 * ixgbe_set_rss_queues: Allocate queues for RSS
3966 * @adapter: board private structure to initialize
3967 *
3968 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3969 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3970 *
3971 **/
bc97114d
PWJ		 3972static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3973{
3974 bool ret = false;
0cefafad 3975 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3976
3977 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3978 f->mask = 0xF;
3979 adapter->num_rx_queues = f->indices;
3980 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3981 ret = true;
3982 } else {
bc97114d 3983 ret = false;
b9804972
JB		 3984 }
3985
bc97114d
PWJ		 3986 return ret;
3987}
3988
c4cf55e5
PWJ		 3989/**
3990 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3991 * @adapter: board private structure to initialize
3992 *
3993 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3994 * to the original CPU that initiated the Tx session. This runs in addition
3995 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3996 * Rx load across CPUs using RSS.
3997 *
3998 **/
e8e9f696 3999static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4000{
4001 bool ret = false;
4002 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4003
4004 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4005 f_fdir->mask = 0;
4006
4007 /* Flow Director must have RSS enabled */
4008 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4009 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4010 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4011 adapter->num_tx_queues = f_fdir->indices;
4012 adapter->num_rx_queues = f_fdir->indices;
4013 ret = true;
4014 } else {
4015 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4016 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4017 }
4018 return ret;
4019}
4020
0331a832
YZ		 4021#ifdef IXGBE_FCOE
4022/**
4023 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4024 * @adapter: board private structure to initialize
4025 *
4026 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4027 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4028 * rx queues out of the max number of rx queues, instead, it is used as the
4029 * index of the first rx queue used by FCoE.
4030 *
4031 **/
4032static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4033{
4034 bool ret = false;
4035 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4036
4037 f->indices = min((int)num_online_cpus(), f->indices);
4038 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 4039 adapter->num_rx_queues = 1;
4040 adapter->num_tx_queues = 1;
0331a832
YZ		 4041#ifdef CONFIG_IXGBE_DCB
4042 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
396e799c 4043 e_info(probe, "FCoE enabled with DCB\n");
0331a832
YZ		 4044 ixgbe_set_dcb_queues(adapter);
4045 }
4046#endif
4047 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
396e799c 4048 e_info(probe, "FCoE enabled with RSS\n");
8faa2a78
YZ		 4049 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4050 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4051 ixgbe_set_fdir_queues(adapter);
4052 else
4053 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 4054 }
4055 /* adding FCoE rx rings to the end */
4056 f->mask = adapter->num_rx_queues;
4057 adapter->num_rx_queues += f->indices;
8de8b2e6 4058 adapter->num_tx_queues += f->indices;
0331a832
YZ		 4059
4060 ret = true;
4061 }
4062
4063 return ret;
4064}
4065
4066#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4067/**
4068 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4069 * @adapter: board private structure to initialize
4070 *
4071 * IOV doesn't actually use anything, so just NAK the
4072 * request for now and let the other queue routines
4073 * figure out what to do.
4074 */
4075static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4076{
4077 return false;
4078}
4079
4df10466
JB		 4080/*
4081 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4082 * @adapter: board private structure to initialize
4083 *
4084 * This is the top level queue allocation routine. The order here is very
4085 * important, starting with the "most" number of features turned on at once,
4086 * and ending with the smallest set of features. This way large combinations
4087 * can be allocated if they're turned on, and smaller combinations are the
4088 * fallthrough conditions.
4089 *
4090 **/
847f53ff 4091static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4092{
1cdd1ec8
GR		 4093 /* Start with base case */
4094 adapter->num_rx_queues = 1;
4095 adapter->num_tx_queues = 1;
4096 adapter->num_rx_pools = adapter->num_rx_queues;
4097 adapter->num_rx_queues_per_pool = 1;
4098
4099 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4100 goto done;
1cdd1ec8 4101
0331a832
YZ		 4102#ifdef IXGBE_FCOE
4103 if (ixgbe_set_fcoe_queues(adapter))
4104 goto done;
4105
4106#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4107#ifdef CONFIG_IXGBE_DCB
4108 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4109 goto done;
bc97114d
PWJ		 4110
4111#endif
c4cf55e5
PWJ		 4112 if (ixgbe_set_fdir_queues(adapter))
4113 goto done;
4114
bc97114d 4115 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4116 goto done;
4117
4118 /* fallback to base case */
4119 adapter->num_rx_queues = 1;
4120 adapter->num_tx_queues = 1;
4121
4122done:
847f53ff 4123 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4124 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4125 return netif_set_real_num_rx_queues(adapter->netdev,
4126 adapter->num_rx_queues);
b9804972
JB		 4127}
4128
021230d4 4129static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4130 int vectors)
021230d4
AV		 4131{
4132 int err, vector_threshold;
4133
4134 /* We'll want at least 3 (vector_threshold):
4135 * 1) TxQ[0] Cleanup
4136 * 2) RxQ[0] Cleanup
4137 * 3) Other (Link Status Change, etc.)
4138 * 4) TCP Timer (optional)
4139 */
4140 vector_threshold = MIN_MSIX_COUNT;
4141
4142 /* The more we get, the more we will assign to Tx/Rx Cleanup
4143 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4144 * Right now, we simply care about how many we'll get; we'll
4145 * set them up later while requesting irq's.
4146 */
4147 while (vectors >= vector_threshold) {
4148 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4149 vectors);
021230d4
AV		 4150 if (!err) /* Success in acquiring all requested vectors. */
4151 break;
4152 else if (err < 0)
4153 vectors = 0; /* Nasty failure, quit now */
4154 else /* err == number of vectors we should try again with */
4155 vectors = err;
4156 }
4157
4158 if (vectors < vector_threshold) {
4159 /* Can't allocate enough MSI-X interrupts? Oh well.
4160 * This just means we'll go with either a single MSI
4161 * vector or fall back to legacy interrupts.
4162 */
849c4542
ET		 4163 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4164 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4165 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4166 kfree(adapter->msix_entries);
4167 adapter->msix_entries = NULL;
021230d4
AV		 4168 } else {
4169 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4170 /*
4171 * Adjust for only the vectors we'll use, which is minimum
4172 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4173 * vectors we were allocated.
4174 */
4175 adapter->num_msix_vectors = min(vectors,
e8e9f696 4176 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4177 }
4178}
4179
021230d4 4180/**
bc97114d 4181 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4182 * @adapter: board private structure to initialize
4183 *
bc97114d
PWJ		 4184 * Cache the descriptor ring offsets for RSS to the assigned rings.
4185 *
021230d4 4186 **/
bc97114d 4187static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4188{
bc97114d
PWJ		 4189 int i;
4190 bool ret = false;
4191
4192 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4193 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4194 adapter->rx_ring[i]->reg_idx = i;
bc97114d 4195 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4196 adapter->tx_ring[i]->reg_idx = i;
bc97114d
PWJ		 4197 ret = true;
4198 } else {
4199 ret = false;
4200 }
4201
4202 return ret;
4203}
4204
4205#ifdef CONFIG_IXGBE_DCB
4206/**
4207 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4208 * @adapter: board private structure to initialize
4209 *
4210 * Cache the descriptor ring offsets for DCB to the assigned rings.
4211 *
4212 **/
4213static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4214{
4215 int i;
4216 bool ret = false;
4217 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4218
4219 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4220 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 4221 /* the number of queues is assumed to be symmetric */
4222 for (i = 0; i < dcb_i; i++) {
4a0b9ca0
PW		 4223 adapter->rx_ring[i]->reg_idx = i << 3;
4224 adapter->tx_ring[i]->reg_idx = i << 2;
2f90b865 4225 }
bc97114d 4226 ret = true;
e8e26350 4227 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 4228 if (dcb_i == 8) {
4229 /*
4230 * Tx TC0 starts at: descriptor queue 0
4231 * Tx TC1 starts at: descriptor queue 32
4232 * Tx TC2 starts at: descriptor queue 64
4233 * Tx TC3 starts at: descriptor queue 80
4234 * Tx TC4 starts at: descriptor queue 96
4235 * Tx TC5 starts at: descriptor queue 104
4236 * Tx TC6 starts at: descriptor queue 112
4237 * Tx TC7 starts at: descriptor queue 120
4238 *
4239 * Rx TC0-TC7 are offset by 16 queues each
4240 */
4241 for (i = 0; i < 3; i++) {
4a0b9ca0
PW		 4242 adapter->tx_ring[i]->reg_idx = i << 5;
4243 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4244 }
4245 for ( ; i < 5; i++) {
4a0b9ca0 4246 adapter->tx_ring[i]->reg_idx =
e8e9f696 4247 ((i + 2) << 4);
4a0b9ca0 4248 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4249 }
4250 for ( ; i < dcb_i; i++) {
4a0b9ca0 4251 adapter->tx_ring[i]->reg_idx =
e8e9f696 4252 ((i + 8) << 3);
4a0b9ca0 4253 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4254 }
4255
4256 ret = true;
4257 } else if (dcb_i == 4) {
4258 /*
4259 * Tx TC0 starts at: descriptor queue 0
4260 * Tx TC1 starts at: descriptor queue 64
4261 * Tx TC2 starts at: descriptor queue 96
4262 * Tx TC3 starts at: descriptor queue 112
4263 *
4264 * Rx TC0-TC3 are offset by 32 queues each
4265 */
4a0b9ca0
PW		 4266 adapter->tx_ring[0]->reg_idx = 0;
4267 adapter->tx_ring[1]->reg_idx = 64;
4268 adapter->tx_ring[2]->reg_idx = 96;
4269 adapter->tx_ring[3]->reg_idx = 112;
f92ef202 4270 for (i = 0 ; i < dcb_i; i++)
4a0b9ca0 4271 adapter->rx_ring[i]->reg_idx = i << 5;
f92ef202
PW		 4272
4273 ret = true;
4274 } else {
4275 ret = false;
e8e26350 4276 }
bc97114d
PWJ		 4277 } else {
4278 ret = false;
021230d4 4279 }
bc97114d
PWJ		 4280 } else {
4281 ret = false;
021230d4 4282 }
bc97114d
PWJ		 4283
4284 return ret;
4285}
4286#endif
4287
c4cf55e5
PWJ		 4288/**
4289 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4290 * @adapter: board private structure to initialize
4291 *
4292 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4293 *
4294 **/
e8e9f696 4295static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4296{
4297 int i;
4298 bool ret = false;
4299
4300 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4301 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4302 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4303 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4304 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4305 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4306 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4307 ret = true;
4308 }
4309
4310 return ret;
4311}
4312
0331a832
YZ		 4313#ifdef IXGBE_FCOE
4314/**
4315 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4316 * @adapter: board private structure to initialize
4317 *
4318 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4319 *
4320 */
4321static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4322{
8de8b2e6 4323 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 4324 bool ret = false;
4325 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4326
4327 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4328#ifdef CONFIG_IXGBE_DCB
4329 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 4330 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4331
0331a832 4332 ixgbe_cache_ring_dcb(adapter);
8de8b2e6 4333 /* find out queues in TC for FCoE */
4a0b9ca0
PW		 4334 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4335 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
8de8b2e6
YZ		 4336 /*
4337 * In 82599, the number of Tx queues for each traffic
4338 * class for both 8-TC and 4-TC modes are:
4339 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4340 * 8 TCs: 32 32 16 16 8 8 8 8
4341 * 4 TCs: 64 64 32 32
4342 * We have max 8 queues for FCoE, where 8 the is
4343 * FCoE redirection table size. If TC for FCoE is
4344 * less than or equal to TC3, we have enough queues
4345 * to add max of 8 queues for FCoE, so we start FCoE
4346 * tx descriptor from the next one, i.e., reg_idx + 1.
4347 * If TC for FCoE is above TC3, implying 8 TC mode,
4348 * and we need 8 for FCoE, we have to take all queues
4349 * in that traffic class for FCoE.
4350 */
4351 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4352 fcoe_tx_i--;
0331a832
YZ		 4353 }
4354#endif /* CONFIG_IXGBE_DCB */
4355 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 4356 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4357 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4358 ixgbe_cache_ring_fdir(adapter);
4359 else
4360 ixgbe_cache_ring_rss(adapter);
4361
8de8b2e6
YZ		 4362 fcoe_rx_i = f->mask;
4363 fcoe_tx_i = f->mask;
4364 }
4365 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4a0b9ca0
PW		 4366 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4367 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
0331a832 4368 }
0331a832
YZ		 4369 ret = true;
4370 }
4371 return ret;
4372}
4373
4374#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4375/**
4376 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4377 * @adapter: board private structure to initialize
4378 *
4379 * SR-IOV doesn't use any descriptor rings but changes the default if
4380 * no other mapping is used.
4381 *
4382 */
4383static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4384{
4a0b9ca0
PW		 4385 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4386 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4387 if (adapter->num_vfs)
4388 return true;
4389 else
4390 return false;
4391}
4392
bc97114d
PWJ		 4393/**
4394 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4395 * @adapter: board private structure to initialize
4396 *
4397 * Once we know the feature-set enabled for the device, we'll cache
4398 * the register offset the descriptor ring is assigned to.
4399 *
4400 * Note, the order the various feature calls is important. It must start with
4401 * the "most" features enabled at the same time, then trickle down to the
4402 * least amount of features turned on at once.
4403 **/
4404static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4405{
4406 /* start with default case */
4a0b9ca0
PW		 4407 adapter->rx_ring[0]->reg_idx = 0;
4408 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4409
1cdd1ec8
GR		 4410 if (ixgbe_cache_ring_sriov(adapter))
4411 return;
4412
0331a832
YZ		 4413#ifdef IXGBE_FCOE
4414 if (ixgbe_cache_ring_fcoe(adapter))
4415 return;
4416
4417#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4418#ifdef CONFIG_IXGBE_DCB
4419 if (ixgbe_cache_ring_dcb(adapter))
4420 return;
4421
4422#endif
c4cf55e5
PWJ		 4423 if (ixgbe_cache_ring_fdir(adapter))
4424 return;
4425
bc97114d
PWJ		 4426 if (ixgbe_cache_ring_rss(adapter))
4427 return;
021230d4
AV		 4428}
4429
9a799d71
AK		 4430/**
4431 * ixgbe_alloc_queues - Allocate memory for all rings
4432 * @adapter: board private structure to initialize
4433 *
4434 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4435 * number of queues at compile-time. The polling_netdev array is
4436 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4437 **/
2f90b865 4438static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 4439{
4440 int i;
4a0b9ca0 4441 int orig_node = adapter->node;
9a799d71 4442
021230d4 4443 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 4444 struct ixgbe_ring *ring = adapter->tx_ring[i];
4445 if (orig_node == -1) {
4446 int cur_node = next_online_node(adapter->node);
4447 if (cur_node == MAX_NUMNODES)
4448 cur_node = first_online_node;
4449 adapter->node = cur_node;
4450 }
4451 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
e8e9f696 4452 adapter->node);
4a0b9ca0
PW		 4453 if (!ring)
4454 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4455 if (!ring)
4456 goto err_tx_ring_allocation;
4457 ring->count = adapter->tx_ring_count;
4458 ring->queue_index = i;
4459 ring->numa_node = adapter->node;
4460
4461 adapter->tx_ring[i] = ring;
021230d4 4462 }
b9804972 4463
4a0b9ca0
PW		 4464 /* Restore the adapter's original node */
4465 adapter->node = orig_node;
4466
9a799d71 4467 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 4468 struct ixgbe_ring *ring = adapter->rx_ring[i];
4469 if (orig_node == -1) {
4470 int cur_node = next_online_node(adapter->node);
4471 if (cur_node == MAX_NUMNODES)
4472 cur_node = first_online_node;
4473 adapter->node = cur_node;
4474 }
4475 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
e8e9f696 4476 adapter->node);
4a0b9ca0
PW		 4477 if (!ring)
4478 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4479 if (!ring)
4480 goto err_rx_ring_allocation;
4481 ring->count = adapter->rx_ring_count;
4482 ring->queue_index = i;
4483 ring->numa_node = adapter->node;
4484
4485 adapter->rx_ring[i] = ring;
021230d4
AV		 4486 }
4487
4a0b9ca0
PW		 4488 /* Restore the adapter's original node */
4489 adapter->node = orig_node;
4490
021230d4
AV		 4491 ixgbe_cache_ring_register(adapter);
4492
4493 return 0;
4494
4495err_rx_ring_allocation:
4a0b9ca0
PW		 4496 for (i = 0; i < adapter->num_tx_queues; i++)
4497 kfree(adapter->tx_ring[i]);
021230d4
AV		 4498err_tx_ring_allocation:
4499 return -ENOMEM;
4500}
4501
4502/**
4503 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4504 * @adapter: board private structure to initialize
4505 *
4506 * Attempt to configure the interrupts using the best available
4507 * capabilities of the hardware and the kernel.
4508 **/
feea6a57 4509static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4510{
8be0e467 4511 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4512 int err = 0;
4513 int vector, v_budget;
4514
4515 /*
4516 * It's easy to be greedy for MSI-X vectors, but it really
4517 * doesn't do us much good if we have a lot more vectors
4518 * than CPU's. So let's be conservative and only ask for
342bde1b 4519 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4520 */
4521 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4522 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4523
4524 /*
4525 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4526 * hw.mac->max_msix_vectors vectors. With features
4527 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4528 * descriptor queues supported by our device. Thus, we cap it off in
4529 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4530 */
8be0e467 4531 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4532
4533 /* A failure in MSI-X entry allocation isn't fatal, but it does
4534 * mean we disable MSI-X capabilities of the adapter. */
4535 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4536 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4537 if (adapter->msix_entries) {
4538 for (vector = 0; vector < v_budget; vector++)
4539 adapter->msix_entries[vector].entry = vector;
021230d4 4540
7a921c93 4541 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4542
7a921c93
AD		 4543 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4544 goto out;
4545 }
26d27844 4546
7a921c93
AD		 4547 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4548 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 4549 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4550 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4551 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4552 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4553 ixgbe_disable_sriov(adapter);
4554
847f53ff
BH		 4555 err = ixgbe_set_num_queues(adapter);
4556 if (err)
4557 return err;
021230d4 4558
021230d4
AV		 4559 err = pci_enable_msi(adapter->pdev);
4560 if (!err) {
4561 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4562 } else {
849c4542
ET		 4563 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4564 "Unable to allocate MSI interrupt, "
4565 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4566 /* reset err */
4567 err = 0;
4568 }
4569
4570out:
021230d4
AV		 4571 return err;
4572}
4573
7a921c93
AD		 4574/**
4575 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4576 * @adapter: board private structure to initialize
4577 *
4578 * We allocate one q_vector per queue interrupt. If allocation fails we
4579 * return -ENOMEM.
4580 **/
4581static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4582{
4583 int q_idx, num_q_vectors;
4584 struct ixgbe_q_vector *q_vector;
4585 int napi_vectors;
4586 int (*poll)(struct napi_struct *, int);
4587
4588 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4589 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4590 napi_vectors = adapter->num_rx_queues;
91281fd3 4591 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4592 } else {
4593 num_q_vectors = 1;
4594 napi_vectors = 1;
4595 poll = &ixgbe_poll;
4596 }
4597
4598 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2 4599 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4600 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4601 if (!q_vector)
4602 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4603 GFP_KERNEL);
7a921c93
AD		 4604 if (!q_vector)
4605 goto err_out;
4606 q_vector->adapter = adapter;
f7554a2b
NS		 4607 if (q_vector->txr_count && !q_vector->rxr_count)
4608 q_vector->eitr = adapter->tx_eitr_param;
4609 else
4610 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4611 q_vector->v_idx = q_idx;
91281fd3 4612 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4613 adapter->q_vector[q_idx] = q_vector;
4614 }
4615
4616 return 0;
4617
4618err_out:
4619 while (q_idx) {
4620 q_idx--;
4621 q_vector = adapter->q_vector[q_idx];
4622 netif_napi_del(&q_vector->napi);
4623 kfree(q_vector);
4624 adapter->q_vector[q_idx] = NULL;
4625 }
4626 return -ENOMEM;
4627}
4628
4629/**
4630 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4631 * @adapter: board private structure to initialize
4632 *
4633 * This function frees the memory allocated to the q_vectors. In addition if
4634 * NAPI is enabled it will delete any references to the NAPI struct prior
4635 * to freeing the q_vector.
4636 **/
4637static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4638{
4639 int q_idx, num_q_vectors;
7a921c93 4640
91281fd3 4641 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4642 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4643 else
7a921c93 4644 num_q_vectors = 1;
7a921c93
AD		 4645
4646 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4647 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4648 adapter->q_vector[q_idx] = NULL;
91281fd3 4649 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4650 kfree(q_vector);
4651 }
4652}
4653
7b25cdba 4654static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4655{
4656 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4657 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4658 pci_disable_msix(adapter->pdev);
4659 kfree(adapter->msix_entries);
4660 adapter->msix_entries = NULL;
4661 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4662 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4663 pci_disable_msi(adapter->pdev);
4664 }
021230d4
AV		 4665}
4666
4667/**
4668 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4669 * @adapter: board private structure to initialize
4670 *
4671 * We determine which interrupt scheme to use based on...
4672 * - Kernel support (MSI, MSI-X)
4673 * - which can be user-defined (via MODULE_PARAM)
4674 * - Hardware queue count (num_*_queues)
4675 * - defined by miscellaneous hardware support/features (RSS, etc.)
4676 **/
2f90b865 4677int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4678{
4679 int err;
4680
4681 /* Number of supported queues */
847f53ff
BH		 4682 err = ixgbe_set_num_queues(adapter);
4683 if (err)
4684 return err;
021230d4 4685
021230d4
AV		 4686 err = ixgbe_set_interrupt_capability(adapter);
4687 if (err) {
849c4542 4688 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 4689 goto err_set_interrupt;
9a799d71
AK		 4690 }
4691
7a921c93
AD		 4692 err = ixgbe_alloc_q_vectors(adapter);
4693 if (err) {
849c4542 4694 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 4695 goto err_alloc_q_vectors;
4696 }
4697
4698 err = ixgbe_alloc_queues(adapter);
4699 if (err) {
849c4542 4700 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 4701 goto err_alloc_queues;
4702 }
4703
849c4542 4704 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 4705 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4706 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4707
4708 set_bit(__IXGBE_DOWN, &adapter->state);
4709
9a799d71 4710 return 0;
021230d4 4711
7a921c93
AD		 4712err_alloc_queues:
4713 ixgbe_free_q_vectors(adapter);
4714err_alloc_q_vectors:
4715 ixgbe_reset_interrupt_capability(adapter);
021230d4 4716err_set_interrupt:
7a921c93
AD		 4717 return err;
4718}
4719
4720/**
4721 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4722 * @adapter: board private structure to clear interrupt scheme on
4723 *
4724 * We go through and clear interrupt specific resources and reset the structure
4725 * to pre-load conditions
4726 **/
4727void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4728{
4a0b9ca0
PW		 4729 int i;
4730
4731 for (i = 0; i < adapter->num_tx_queues; i++) {
4732 kfree(adapter->tx_ring[i]);
4733 adapter->tx_ring[i] = NULL;
4734 }
4735 for (i = 0; i < adapter->num_rx_queues; i++) {
4736 kfree(adapter->rx_ring[i]);
4737 adapter->rx_ring[i] = NULL;
4738 }
7a921c93
AD		 4739
4740 ixgbe_free_q_vectors(adapter);
4741 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4742}
4743
c4900be0
DS		 4744/**
4745 * ixgbe_sfp_timer - worker thread to find a missing module
4746 * @data: pointer to our adapter struct
4747 **/
4748static void ixgbe_sfp_timer(unsigned long data)
4749{
4750 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4751
4df10466
JB		 4752 /*
4753 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 4754 * delays that sfp+ detection requires
4755 */
4756 schedule_work(&adapter->sfp_task);
4757}
4758
4759/**
4760 * ixgbe_sfp_task - worker thread to find a missing module
4761 * @work: pointer to work_struct containing our data
4762 **/
4763static void ixgbe_sfp_task(struct work_struct *work)
4764{
4765 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 4766 struct ixgbe_adapter,
4767 sfp_task);
c4900be0
DS		 4768 struct ixgbe_hw *hw = &adapter->hw;
4769
4770 if ((hw->phy.type == ixgbe_phy_nl) &&
4771 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4772 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4773 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 4774 goto reschedule;
4775 ret = hw->phy.ops.reset(hw);
4776 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 4777 e_dev_err("failed to initialize because an unsupported "
4778 "SFP+ module type was detected.\n");
4779 e_dev_err("Reload the driver after installing a "
4780 "supported module.\n");
c4900be0
DS		 4781 unregister_netdev(adapter->netdev);
4782 } else {
396e799c 4783 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
c4900be0
DS		 4784 }
4785 /* don't need this routine any more */
4786 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4787 }
4788 return;
4789reschedule:
4790 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4791 mod_timer(&adapter->sfp_timer,
e8e9f696 4792 round_jiffies(jiffies + (2 * HZ)));
c4900be0
DS		 4793}
4794
9a799d71
AK		 4795/**
4796 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4797 * @adapter: board private structure to initialize
4798 *
4799 * ixgbe_sw_init initializes the Adapter private data structure.
4800 * Fields are initialized based on PCI device information and
4801 * OS network device settings (MTU size).
4802 **/
4803static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4804{
4805 struct ixgbe_hw *hw = &adapter->hw;
4806 struct pci_dev *pdev = adapter->pdev;
9a713e7c 4807 struct net_device *dev = adapter->netdev;
021230d4 4808 unsigned int rss;
7a6b6f51 4809#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4810 int j;
4811 struct tc_configuration *tc;
4812#endif
021230d4 4813
c44ade9e
JB		 4814 /* PCI config space info */
4815
4816 hw->vendor_id = pdev->vendor;
4817 hw->device_id = pdev->device;
4818 hw->revision_id = pdev->revision;
4819 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4820 hw->subsystem_device_id = pdev->subsystem_device;
4821
021230d4
AV		 4822 /* Set capability flags */
4823 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4824 adapter->ring_feature[RING_F_RSS].indices = rss;
4825 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 4826 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 4827 if (hw->mac.type == ixgbe_mac_82598EB) {
4828 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4829 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4830 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 4831 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 4832 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4833 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4834 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4835 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4836 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
9a713e7c
PW		 4837 if (dev->features & NETIF_F_NTUPLE) {
4838 /* Flow Director perfect filter enabled */
4839 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4840 adapter->atr_sample_rate = 0;
4841 spin_lock_init(&adapter->fdir_perfect_lock);
4842 } else {
4843 /* Flow Director hash filters enabled */
4844 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4845 adapter->atr_sample_rate = 20;
4846 }
c4cf55e5 4847 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 4848 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 4849 adapter->fdir_pballoc = 0;
eacd73f7 4850#ifdef IXGBE_FCOE
0d551589
YZ		 4851 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4852 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4853 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4854#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 4855 /* Default traffic class to use for FCoE */
4856 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
56075a98 4857 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4858#endif
eacd73f7 4859#endif /* IXGBE_FCOE */
f8212f97 4860 }
2f90b865 4861
7a6b6f51 4862#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4863 /* Configure DCB traffic classes */
4864 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4865 tc = &adapter->dcb_cfg.tc_config[j];
4866 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4867 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4868 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4869 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4870 tc->dcb_pfc = pfc_disabled;
4871 }
4872 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4873 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4874 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 4875 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 4876 adapter->dcb_cfg.round_robin_enable = false;
4877 adapter->dcb_set_bitmap = 0x00;
4878 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e8e9f696 4879 adapter->ring_feature[RING_F_DCB].indices);
2f90b865
AD		 4880
4881#endif
9a799d71
AK		 4882
4883 /* default flow control settings */
cd7664f6 4884 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4885 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 4886#ifdef CONFIG_DCB
4887 adapter->last_lfc_mode = hw->fc.current_mode;
4888#endif
2b9ade93
JB		 4889 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4890 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4891 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4892 hw->fc.send_xon = true;
71fd570b 4893 hw->fc.disable_fc_autoneg = false;
9a799d71 4894
30efa5a3 4895 /* enable itr by default in dynamic mode */
f7554a2b
NS		 4896 adapter->rx_itr_setting = 1;
4897 adapter->rx_eitr_param = 20000;
4898 adapter->tx_itr_setting = 1;
4899 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 4900
4901 /* set defaults for eitr in MegaBytes */
4902 adapter->eitr_low = 10;
4903 adapter->eitr_high = 20;
4904
4905 /* set default ring sizes */
4906 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4907 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4908
9a799d71 4909 /* initialize eeprom parameters */
c44ade9e 4910 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4911 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4912 return -EIO;
4913 }
4914
021230d4 4915 /* enable rx csum by default */
9a799d71
AK		 4916 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4917
1a6c14a2
JB		 4918 /* get assigned NUMA node */
4919 adapter->node = dev_to_node(&pdev->dev);
4920
9a799d71
AK		 4921 set_bit(__IXGBE_DOWN, &adapter->state);
4922
4923 return 0;
4924}
4925
4926/**
4927 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4928 * @adapter: board private structure
3a581073 4929 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4930 *
4931 * Return 0 on success, negative on failure
4932 **/
4933int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e8e9f696 4934 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4935{
4936 struct pci_dev *pdev = adapter->pdev;
4937 int size;
4938
3a581073 4939 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4a0b9ca0 4940 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
1a6c14a2
JB		 4941 if (!tx_ring->tx_buffer_info)
4942 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 4943 if (!tx_ring->tx_buffer_info)
4944 goto err;
3a581073 4945 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 4946
4947 /* round up to nearest 4K */
12207e49 4948 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4949 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4950
1b507730
NN		 4951 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4952 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4953 if (!tx_ring->desc)
4954 goto err;
9a799d71 4955
3a581073
JB		 4956 tx_ring->next_to_use = 0;
4957 tx_ring->next_to_clean = 0;
4958 tx_ring->work_limit = tx_ring->count;
9a799d71 4959 return 0;
e01c31a5
JB		 4960
4961err:
4962 vfree(tx_ring->tx_buffer_info);
4963 tx_ring->tx_buffer_info = NULL;
396e799c 4964 e_err(probe, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4965 return -ENOMEM;
9a799d71
AK		 4966}
4967
69888674
AD		 4968/**
4969 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4970 * @adapter: board private structure
4971 *
4972 * If this function returns with an error, then it's possible one or
4973 * more of the rings is populated (while the rest are not). It is the
4974 * callers duty to clean those orphaned rings.
4975 *
4976 * Return 0 on success, negative on failure
4977 **/
4978static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4979{
4980 int i, err = 0;
4981
4982 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 4983 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
69888674
AD		 4984 if (!err)
4985 continue;
396e799c 4986 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 4987 break;
4988 }
4989
4990 return err;
4991}
4992
9a799d71
AK		 4993/**
4994 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4995 * @adapter: board private structure
3a581073 4996 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4997 *
4998 * Returns 0 on success, negative on failure
4999 **/
5000int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
e8e9f696 5001 struct ixgbe_ring *rx_ring)
9a799d71
AK		 5002{
5003 struct pci_dev *pdev = adapter->pdev;
021230d4 5004 int size;
9a799d71 5005
3a581073 5006 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
1a6c14a2
JB		 5007 rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
5008 if (!rx_ring->rx_buffer_info)
5009 rx_ring->rx_buffer_info = vmalloc(size);
3a581073 5010 if (!rx_ring->rx_buffer_info) {
396e799c
ET		 5011 e_err(probe, "vmalloc allocation failed for the Rx "
5012 "descriptor ring\n");
177db6ff 5013 goto alloc_failed;
9a799d71 5014 }
3a581073 5015 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 5016
9a799d71 5017 /* Round up to nearest 4K */
3a581073
JB		 5018 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5019 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5020
1b507730
NN		 5021 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
5022 &rx_ring->dma, GFP_KERNEL);
9a799d71 5023
3a581073 5024 if (!rx_ring->desc) {
396e799c
ET		 5025 e_err(probe, "Memory allocation failed for the Rx "
5026 "descriptor ring\n");
3a581073 5027 vfree(rx_ring->rx_buffer_info);
177db6ff 5028 goto alloc_failed;
9a799d71
AK		 5029 }
5030
3a581073
JB		 5031 rx_ring->next_to_clean = 0;
5032 rx_ring->next_to_use = 0;
9a799d71
AK		 5033
5034 return 0;
177db6ff
MC		 5035
5036alloc_failed:
177db6ff 5037 return -ENOMEM;
9a799d71
AK		 5038}
5039
69888674
AD		 5040/**
5041 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5042 * @adapter: board private structure
5043 *
5044 * If this function returns with an error, then it's possible one or
5045 * more of the rings is populated (while the rest are not). It is the
5046 * callers duty to clean those orphaned rings.
5047 *
5048 * Return 0 on success, negative on failure
5049 **/
5050
5051static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5052{
5053 int i, err = 0;
5054
5055 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 5056 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
69888674
AD		 5057 if (!err)
5058 continue;
396e799c 5059 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5060 break;
5061 }
5062
5063 return err;
5064}
5065
9a799d71
AK		 5066/**
5067 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5068 * @adapter: board private structure
5069 * @tx_ring: Tx descriptor ring for a specific queue
5070 *
5071 * Free all transmit software resources
5072 **/
c431f97e 5073void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
e8e9f696 5074 struct ixgbe_ring *tx_ring)
9a799d71
AK		 5075{
5076 struct pci_dev *pdev = adapter->pdev;
5077
5078 ixgbe_clean_tx_ring(adapter, tx_ring);
5079
5080 vfree(tx_ring->tx_buffer_info);
5081 tx_ring->tx_buffer_info = NULL;
5082
1b507730
NN		 5083 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
5084 tx_ring->dma);
9a799d71
AK		 5085
5086 tx_ring->desc = NULL;
5087}
5088
5089/**
5090 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5091 * @adapter: board private structure
5092 *
5093 * Free all transmit software resources
5094 **/
5095static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5096{
5097 int i;
5098
5099 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0
PW		 5100 if (adapter->tx_ring[i]->desc)
5101 ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
9a799d71
AK		 5102}
5103
5104/**
b4617240 5105 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5106 * @adapter: board private structure
5107 * @rx_ring: ring to clean the resources from
5108 *
5109 * Free all receive software resources
5110 **/
c431f97e 5111void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
e8e9f696 5112 struct ixgbe_ring *rx_ring)
9a799d71
AK		 5113{
5114 struct pci_dev *pdev = adapter->pdev;
5115
5116 ixgbe_clean_rx_ring(adapter, rx_ring);
5117
5118 vfree(rx_ring->rx_buffer_info);
5119 rx_ring->rx_buffer_info = NULL;
5120
1b507730
NN		 5121 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
5122 rx_ring->dma);
9a799d71
AK		 5123
5124 rx_ring->desc = NULL;
5125}
5126
5127/**
5128 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5129 * @adapter: board private structure
5130 *
5131 * Free all receive software resources
5132 **/
5133static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5134{
5135 int i;
5136
5137 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 5138 if (adapter->rx_ring[i]->desc)
5139 ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
9a799d71
AK		 5140}
5141
9a799d71
AK		 5142/**
5143 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5144 * @netdev: network interface device structure
5145 * @new_mtu: new value for maximum frame size
5146 *
5147 * Returns 0 on success, negative on failure
5148 **/
5149static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5150{
5151 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5152 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5153
42c783c5
JB		 5154 /* MTU < 68 is an error and causes problems on some kernels */
5155 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 5156 return -EINVAL;
5157
396e799c 5158 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5159 /* must set new MTU before calling down or up */
9a799d71
AK		 5160 netdev->mtu = new_mtu;
5161
d4f80882
AV		 5162 if (netif_running(netdev))
5163 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5164
5165 return 0;
5166}
5167
5168/**
5169 * ixgbe_open - Called when a network interface is made active
5170 * @netdev: network interface device structure
5171 *
5172 * Returns 0 on success, negative value on failure
5173 *
5174 * The open entry point is called when a network interface is made
5175 * active by the system (IFF_UP). At this point all resources needed
5176 * for transmit and receive operations are allocated, the interrupt
5177 * handler is registered with the OS, the watchdog timer is started,
5178 * and the stack is notified that the interface is ready.
5179 **/
5180static int ixgbe_open(struct net_device *netdev)
5181{
5182 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5183 int err;
4bebfaa5
AK		 5184
5185 /* disallow open during test */
5186 if (test_bit(__IXGBE_TESTING, &adapter->state))
5187 return -EBUSY;
9a799d71 5188
54386467
JB		 5189 netif_carrier_off(netdev);
5190
9a799d71
AK		 5191 /* allocate transmit descriptors */
5192 err = ixgbe_setup_all_tx_resources(adapter);
5193 if (err)
5194 goto err_setup_tx;
5195
9a799d71
AK		 5196 /* allocate receive descriptors */
5197 err = ixgbe_setup_all_rx_resources(adapter);
5198 if (err)
5199 goto err_setup_rx;
5200
5201 ixgbe_configure(adapter);
5202
021230d4 5203 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5204 if (err)
5205 goto err_req_irq;
5206
9a799d71
AK		 5207 err = ixgbe_up_complete(adapter);
5208 if (err)
5209 goto err_up;
5210
d55b53ff
JK		 5211 netif_tx_start_all_queues(netdev);
5212
9a799d71
AK		 5213 return 0;
5214
5215err_up:
5eba3699 5216 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5217 ixgbe_free_irq(adapter);
5218err_req_irq:
9a799d71 5219err_setup_rx:
a20a1199 5220 ixgbe_free_all_rx_resources(adapter);
9a799d71 5221err_setup_tx:
a20a1199 5222 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5223 ixgbe_reset(adapter);
5224
5225 return err;
5226}
5227
5228/**
5229 * ixgbe_close - Disables a network interface
5230 * @netdev: network interface device structure
5231 *
5232 * Returns 0, this is not allowed to fail
5233 *
5234 * The close entry point is called when an interface is de-activated
5235 * by the OS. The hardware is still under the drivers control, but
5236 * needs to be disabled. A global MAC reset is issued to stop the
5237 * hardware, and all transmit and receive resources are freed.
5238 **/
5239static int ixgbe_close(struct net_device *netdev)
5240{
5241 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5242
5243 ixgbe_down(adapter);
5244 ixgbe_free_irq(adapter);
5245
5246 ixgbe_free_all_tx_resources(adapter);
5247 ixgbe_free_all_rx_resources(adapter);
5248
5eba3699 5249 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5250
5251 return 0;
5252}
5253
b3c8b4ba
AD		 5254#ifdef CONFIG_PM
5255static int ixgbe_resume(struct pci_dev *pdev)
5256{
5257 struct net_device *netdev = pci_get_drvdata(pdev);
5258 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5259 u32 err;
5260
5261 pci_set_power_state(pdev, PCI_D0);
5262 pci_restore_state(pdev);
656ab817
DS		 5263 /*
5264 * pci_restore_state clears dev->state_saved so call
5265 * pci_save_state to restore it.
5266 */
5267 pci_save_state(pdev);
9ce77666 5268
5269 err = pci_enable_device_mem(pdev);
b3c8b4ba 5270 if (err) {
849c4542 5271 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5272 return err;
5273 }
5274 pci_set_master(pdev);
5275
dd4d8ca6 5276 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5277
5278 err = ixgbe_init_interrupt_scheme(adapter);
5279 if (err) {
849c4542 5280 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5281 return err;
5282 }
5283
b3c8b4ba
AD		 5284 ixgbe_reset(adapter);
5285
495dce12
WJP		 5286 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5287
b3c8b4ba
AD		 5288 if (netif_running(netdev)) {
5289 err = ixgbe_open(adapter->netdev);
5290 if (err)
5291 return err;
5292 }
5293
5294 netif_device_attach(netdev);
5295
5296 return 0;
5297}
b3c8b4ba 5298#endif /* CONFIG_PM */
9d8d05ae
RW		 5299
5300static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 5301{
5302 struct net_device *netdev = pci_get_drvdata(pdev);
5303 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 5304 struct ixgbe_hw *hw = &adapter->hw;
5305 u32 ctrl, fctrl;
5306 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5307#ifdef CONFIG_PM
5308 int retval = 0;
5309#endif
5310
5311 netif_device_detach(netdev);
5312
5313 if (netif_running(netdev)) {
5314 ixgbe_down(adapter);
5315 ixgbe_free_irq(adapter);
5316 ixgbe_free_all_tx_resources(adapter);
5317 ixgbe_free_all_rx_resources(adapter);
5318 }
b3c8b4ba
AD		 5319
5320#ifdef CONFIG_PM
5321 retval = pci_save_state(pdev);
5322 if (retval)
5323 return retval;
4df10466 5324
b3c8b4ba 5325#endif
e8e26350
PW		 5326 if (wufc) {
5327 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5328
e8e26350
PW		 5329 /* turn on all-multi mode if wake on multicast is enabled */
5330 if (wufc & IXGBE_WUFC_MC) {
5331 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5332 fctrl |= IXGBE_FCTRL_MPE;
5333 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5334 }
5335
5336 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5337 ctrl |= IXGBE_CTRL_GIO_DIS;
5338 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5339
5340 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5341 } else {
5342 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5343 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5344 }
5345
dd4d8ca6
DS		 5346 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5347 pci_wake_from_d3(pdev, true);
5348 else
5349 pci_wake_from_d3(pdev, false);
b3c8b4ba 5350
9d8d05ae
RW		 5351 *enable_wake = !!wufc;
5352
fa378134
AG		 5353 ixgbe_clear_interrupt_scheme(adapter);
5354
b3c8b4ba
AD		 5355 ixgbe_release_hw_control(adapter);
5356
5357 pci_disable_device(pdev);
5358
9d8d05ae
RW		 5359 return 0;
5360}
5361
5362#ifdef CONFIG_PM
5363static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5364{
5365 int retval;
5366 bool wake;
5367
5368 retval = __ixgbe_shutdown(pdev, &wake);
5369 if (retval)
5370 return retval;
5371
5372 if (wake) {
5373 pci_prepare_to_sleep(pdev);
5374 } else {
5375 pci_wake_from_d3(pdev, false);
5376 pci_set_power_state(pdev, PCI_D3hot);
5377 }
b3c8b4ba
AD		 5378
5379 return 0;
5380}
9d8d05ae 5381#endif /* CONFIG_PM */
b3c8b4ba
AD		 5382
5383static void ixgbe_shutdown(struct pci_dev *pdev)
5384{
9d8d05ae
RW		 5385 bool wake;
5386
5387 __ixgbe_shutdown(pdev, &wake);
5388
5389 if (system_state == SYSTEM_POWER_OFF) {
5390 pci_wake_from_d3(pdev, wake);
5391 pci_set_power_state(pdev, PCI_D3hot);
5392 }
b3c8b4ba
AD		 5393}
5394
9a799d71
AK		 5395/**
5396 * ixgbe_update_stats - Update the board statistics counters.
5397 * @adapter: board private structure
5398 **/
5399void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5400{
2d86f139 5401 struct net_device *netdev = adapter->netdev;
9a799d71 5402 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 5403 u64 total_mpc = 0;
5404 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
eb985f09 5405 u64 non_eop_descs = 0, restart_queue = 0;
7ca647bd 5406 struct ixgbe_hw_stats *hwstats = &adapter->stats;
9a799d71 5407
d08935c2
DS		 5408 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5409 test_bit(__IXGBE_RESETTING, &adapter->state))
5410 return;
5411
94b982b2 5412 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5413 u64 rsc_count = 0;
94b982b2 5414 u64 rsc_flush = 0;
d51019a4
PW		 5415 for (i = 0; i < 16; i++)
5416 adapter->hw_rx_no_dma_resources +=
7ca647bd 5417 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5418 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 5419 rsc_count += adapter->rx_ring[i]->rsc_count;
5420 rsc_flush += adapter->rx_ring[i]->rsc_flush;
94b982b2
MC		 5421 }
5422 adapter->rsc_total_count = rsc_count;
5423 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5424 }
5425
7ca3bc58
JB		 5426 /* gather some stats to the adapter struct that are per queue */
5427 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5428 restart_queue += adapter->tx_ring[i]->restart_queue;
eb985f09 5429 adapter->restart_queue = restart_queue;
7ca3bc58
JB		 5430
5431 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5432 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
eb985f09 5433 adapter->non_eop_descs = non_eop_descs;
7ca3bc58 5434
7ca647bd 5435 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5436 for (i = 0; i < 8; i++) {
5437 /* for packet buffers not used, the register should read 0 */
5438 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5439 missed_rx += mpc;
7ca647bd
JP		 5440 hwstats->mpc[i] += mpc;
5441 total_mpc += hwstats->mpc[i];
e8e26350 5442 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5443 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5444 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5445 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5446 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5447 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350 5448 if (hw->mac.type == ixgbe_mac_82599EB) {
7ca647bd
JP		 5449 hwstats->pxonrxc[i] +=
5450 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5451 hwstats->pxoffrxc[i] +=
5452 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
5453 hwstats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350 5454 } else {
7ca647bd
JP		 5455 hwstats->pxonrxc[i] +=
5456 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5457 hwstats->pxoffrxc[i] +=
5458 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
e8e26350 5459 }
7ca647bd
JP		 5460 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5461 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6f11eef7 5462 }
7ca647bd 5463 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5464 /* work around hardware counting issue */
7ca647bd 5465 hwstats->gprc -= missed_rx;
6f11eef7
AV		 5466
5467 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350 5468 if (hw->mac.type == ixgbe_mac_82599EB) {
aad71918 5469 u64 tmp;
7ca647bd 5470 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
e8e9f696
JP		 5471 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF;
5472 /* 4 high bits of GORC */
7ca647bd
JP		 5473 hwstats->gorc += (tmp << 32);
5474 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
e8e9f696
JP		 5475 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF;
5476 /* 4 high bits of GOTC */
7ca647bd
JP		 5477 hwstats->gotc += (tmp << 32);
5478 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
e8e9f696 5479 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd
JP		 5480 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5481 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5482 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5483 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5484#ifdef IXGBE_FCOE
7ca647bd
JP		 5485 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5486 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5487 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5488 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5489 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5490 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6d45522c 5491#endif /* IXGBE_FCOE */
e8e26350 5492 } else {
7ca647bd
JP		 5493 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5494 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5495 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5496 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5497 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
e8e26350 5498 }
9a799d71 5499 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5500 hwstats->bprc += bprc;
5501 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5502 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5503 hwstats->mprc -= bprc;
5504 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5505 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5506 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5507 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5508 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5509 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5510 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5511 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5512 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5513 hwstats->lxontxc += lxon;
6f11eef7 5514 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd
JP		 5515 hwstats->lxofftxc += lxoff;
5516 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5517 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5518 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5519 /*
5520 * 82598 errata - tx of flow control packets is included in tx counters
5521 */
5522 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5523 hwstats->gptc -= xon_off_tot;
5524 hwstats->mptc -= xon_off_tot;
5525 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5526 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5527 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5528 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5529 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5530 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5531 hwstats->ptc64 -= xon_off_tot;
5532 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5533 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5534 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5535 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5536 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5537 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5538
5539 /* Fill out the OS statistics structure */
7ca647bd 5540 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5541
5542 /* Rx Errors */
7ca647bd 5543 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5544 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5545 netdev->stats.rx_length_errors = hwstats->rlec;
5546 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5547 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5548}
5549
5550/**
5551 * ixgbe_watchdog - Timer Call-back
5552 * @data: pointer to adapter cast into an unsigned long
5553 **/
5554static void ixgbe_watchdog(unsigned long data)
5555{
5556 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 5557 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5558 u64 eics = 0;
5559 int i;
cf8280ee 5560
fe49f04a
AD		 5561 /*
5562 * Do the watchdog outside of interrupt context due to the lovely
5563 * delays that some of the newer hardware requires
5564 */
22d5a71b 5565
fe49f04a
AD		 5566 if (test_bit(__IXGBE_DOWN, &adapter->state))
5567 goto watchdog_short_circuit;
22d5a71b 5568
fe49f04a
AD		 5569 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5570 /*
5571 * for legacy and MSI interrupts don't set any bits
5572 * that are enabled for EIAM, because this operation
5573 * would set *both* EIMS and EICS for any bit in EIAM
5574 */
5575 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5576 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5577 goto watchdog_reschedule;
5578 }
5579
5580 /* get one bit for every active tx/rx interrupt vector */
5581 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5582 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5583 if (qv->rxr_count || qv->txr_count)
5584 eics |= ((u64)1 << i);
cf8280ee 5585 }
9a799d71 5586
fe49f04a
AD		 5587 /* Cause software interrupt to ensure rx rings are cleaned */
5588 ixgbe_irq_rearm_queues(adapter, eics);
5589
5590watchdog_reschedule:
5591 /* Reset the timer */
5592 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5593
5594watchdog_short_circuit:
cf8280ee
JB		 5595 schedule_work(&adapter->watchdog_task);
5596}
5597
e8e26350
PW		 5598/**
5599 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5600 * @work: pointer to work_struct containing our data
5601 **/
5602static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5603{
5604 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5605 struct ixgbe_adapter,
5606 multispeed_fiber_task);
e8e26350
PW		 5607 struct ixgbe_hw *hw = &adapter->hw;
5608 u32 autoneg;
8620a103 5609 bool negotiation;
e8e26350
PW		 5610
5611 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 5612 autoneg = hw->phy.autoneg_advertised;
5613 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103 5614 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
1097cd17 5615 hw->mac.autotry_restart = false;
8620a103
MC		 5616 if (hw->mac.ops.setup_link)
5617 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 5618 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5619 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5620}
5621
5622/**
5623 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5624 * @work: pointer to work_struct containing our data
5625 **/
5626static void ixgbe_sfp_config_module_task(struct work_struct *work)
5627{
5628 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5629 struct ixgbe_adapter,
5630 sfp_config_module_task);
e8e26350
PW		 5631 struct ixgbe_hw *hw = &adapter->hw;
5632 u32 err;
5633
5634 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 5635
5636 /* Time for electrical oscillations to settle down */
5637 msleep(100);
e8e26350 5638 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5639
e8e26350 5640 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 5641 e_dev_err("failed to initialize because an unsupported SFP+ "
5642 "module type was detected.\n");
5643 e_dev_err("Reload the driver after installing a supported "
5644 "module.\n");
63d6e1d8 5645 unregister_netdev(adapter->netdev);
e8e26350
PW		 5646 return;
5647 }
5648 hw->mac.ops.setup_sfp(hw);
5649
8d1c3c07 5650 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 5651 /* This will also work for DA Twinax connections */
5652 schedule_work(&adapter->multispeed_fiber_task);
5653 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5654}
5655
c4cf55e5
PWJ		 5656/**
5657 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5658 * @work: pointer to work_struct containing our data
5659 **/
5660static void ixgbe_fdir_reinit_task(struct work_struct *work)
5661{
5662 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5663 struct ixgbe_adapter,
5664 fdir_reinit_task);
c4cf55e5
PWJ		 5665 struct ixgbe_hw *hw = &adapter->hw;
5666 int i;
5667
5668 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5669 for (i = 0; i < adapter->num_tx_queues; i++)
5670 set_bit(__IXGBE_FDIR_INIT_DONE,
e8e9f696 5671 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5 5672 } else {
396e799c 5673 e_err(probe, "failed to finish FDIR re-initialization, "
849c4542 5674 "ignored adding FDIR ATR filters\n");
c4cf55e5
PWJ		 5675 }
5676 /* Done FDIR Re-initialization, enable transmits */
5677 netif_tx_start_all_queues(adapter->netdev);
5678}
5679
10eec955
JF		 5680static DEFINE_MUTEX(ixgbe_watchdog_lock);
5681
cf8280ee 5682/**
69888674
AD		 5683 * ixgbe_watchdog_task - worker thread to bring link up
5684 * @work: pointer to work_struct containing our data
cf8280ee
JB		 5685 **/
5686static void ixgbe_watchdog_task(struct work_struct *work)
5687{
5688 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5689 struct ixgbe_adapter,
5690 watchdog_task);
cf8280ee
JB		 5691 struct net_device *netdev = adapter->netdev;
5692 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 5693 u32 link_speed;
5694 bool link_up;
bc59fcda
NS		 5695 int i;
5696 struct ixgbe_ring *tx_ring;
5697 int some_tx_pending = 0;
cf8280ee 5698
10eec955
JF		 5699 mutex_lock(&ixgbe_watchdog_lock);
5700
5701 link_up = adapter->link_up;
5702 link_speed = adapter->link_speed;
cf8280ee
JB		 5703
5704 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5705 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 5706 if (link_up) {
5707#ifdef CONFIG_DCB
5708 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5709 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 5710 hw->mac.ops.fc_enable(hw, i);
264857b8 5711 } else {
620fa036 5712 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5713 }
5714#else
620fa036 5715 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5716#endif
5717 }
5718
cf8280ee
JB		 5719 if (link_up ||
5720 time_after(jiffies, (adapter->link_check_timeout +
e8e9f696 5721 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 5722 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 5723 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 5724 }
5725 adapter->link_up = link_up;
5726 adapter->link_speed = link_speed;
5727 }
9a799d71
AK		 5728
5729 if (link_up) {
5730 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 5731 bool flow_rx, flow_tx;
5732
5733 if (hw->mac.type == ixgbe_mac_82599EB) {
5734 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5735 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 5736 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5737 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 5738 } else {
5739 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5740 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 5741 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5742 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 5743 }
5744
396e799c 5745 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
a46e534b 5746 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
849c4542
ET		 5747 "10 Gbps" :
5748 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5749 "1 Gbps" : "unknown speed")),
e8e26350 5750 ((flow_rx && flow_tx) ? "RX/TX" :
849c4542
ET		 5751 (flow_rx ? "RX" :
5752 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 5753
5754 netif_carrier_on(netdev);
9a799d71
AK		 5755 } else {
5756 /* Force detection of hung controller */
5757 adapter->detect_tx_hung = true;
5758 }
5759 } else {
cf8280ee
JB		 5760 adapter->link_up = false;
5761 adapter->link_speed = 0;
9a799d71 5762 if (netif_carrier_ok(netdev)) {
396e799c 5763 e_info(drv, "NIC Link is Down\n");
9a799d71 5764 netif_carrier_off(netdev);
9a799d71
AK		 5765 }
5766 }
5767
bc59fcda
NS		 5768 if (!netif_carrier_ok(netdev)) {
5769 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 5770 tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5771 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5772 some_tx_pending = 1;
5773 break;
5774 }
5775 }
5776
5777 if (some_tx_pending) {
5778 /* We've lost link, so the controller stops DMA,
5779 * but we've got queued Tx work that's never going
5780 * to get done, so reset controller to flush Tx.
5781 * (Do the reset outside of interrupt context).
5782 */
5783 schedule_work(&adapter->reset_task);
5784 }
5785 }
5786
9a799d71 5787 ixgbe_update_stats(adapter);
10eec955 5788 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 5789}
5790
9a799d71 5791static int ixgbe_tso(struct ixgbe_adapter *adapter,
e8e9f696
JP		 5792 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5793 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 5794{
5795 struct ixgbe_adv_tx_context_desc *context_desc;
5796 unsigned int i;
5797 int err;
5798 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 5799 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5800 u32 mss_l4len_idx, l4len;
9a799d71
AK		 5801
5802 if (skb_is_gso(skb)) {
5803 if (skb_header_cloned(skb)) {
5804 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5805 if (err)
5806 return err;
5807 }
5808 l4len = tcp_hdrlen(skb);
5809 *hdr_len += l4len;
5810
8327d000 5811 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 5812 struct iphdr *iph = ip_hdr(skb);
5813 iph->tot_len = 0;
5814 iph->check = 0;
5815 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
e8e9f696
JP		 5816 iph->daddr, 0,
5817 IPPROTO_TCP,
5818 0);
8e1e8a47 5819 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 5820 ipv6_hdr(skb)->payload_len = 0;
5821 tcp_hdr(skb)->check =
5822 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
e8e9f696
JP		 5823 &ipv6_hdr(skb)->daddr,
5824 0, IPPROTO_TCP, 0);
9a799d71
AK		 5825 }
5826
5827 i = tx_ring->next_to_use;
5828
5829 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 5830 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 5831
5832 /* VLAN MACLEN IPLEN */
5833 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5834 vlan_macip_lens |=
5835 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5836 vlan_macip_lens |= ((skb_network_offset(skb)) <<
e8e9f696 5837 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5838 *hdr_len += skb_network_offset(skb);
5839 vlan_macip_lens |=
5840 (skb_transport_header(skb) - skb_network_header(skb));
5841 *hdr_len +=
5842 (skb_transport_header(skb) - skb_network_header(skb));
5843 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5844 context_desc->seqnum_seed = 0;
5845
5846 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 5847 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
e8e9f696 5848 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 5849
8327d000 5850 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 5851 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5852 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5853 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5854
5855 /* MSS L4LEN IDX */
9f8cdf4f 5856 mss_l4len_idx =
9a799d71
AK		 5857 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5858 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 5859 /* use index 1 for TSO */
5860 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5861 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5862
5863 tx_buffer_info->time_stamp = jiffies;
5864 tx_buffer_info->next_to_watch = i;
5865
5866 i++;
5867 if (i == tx_ring->count)
5868 i = 0;
5869 tx_ring->next_to_use = i;
5870
5871 return true;
5872 }
5873 return false;
5874}
5875
7ca647bd
JP		 5876static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb)
5877{
5878 u32 rtn = 0;
5879 __be16 protocol;
5880
5881 if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
5882 protocol = ((const struct vlan_ethhdr *)skb->data)->
5883 h_vlan_encapsulated_proto;
5884 else
5885 protocol = skb->protocol;
5886
5887 switch (protocol) {
5888 case cpu_to_be16(ETH_P_IP):
5889 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
5890 switch (ip_hdr(skb)->protocol) {
5891 case IPPROTO_TCP:
5892 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5893 break;
5894 case IPPROTO_SCTP:
5895 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5896 break;
5897 }
5898 break;
5899 case cpu_to_be16(ETH_P_IPV6):
5900 /* XXX what about other V6 headers?? */
5901 switch (ipv6_hdr(skb)->nexthdr) {
5902 case IPPROTO_TCP:
5903 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5904 break;
5905 case IPPROTO_SCTP:
5906 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5907 break;
5908 }
5909 break;
5910 default:
5911 if (unlikely(net_ratelimit()))
5912 e_warn(probe, "partial checksum but proto=%x!\n",
5913 skb->protocol);
5914 break;
5915 }
5916
5917 return rtn;
5918}
5919
9a799d71 5920static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
e8e9f696
JP		 5921 struct ixgbe_ring *tx_ring,
5922 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 5923{
5924 struct ixgbe_adv_tx_context_desc *context_desc;
5925 unsigned int i;
5926 struct ixgbe_tx_buffer *tx_buffer_info;
5927 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5928
5929 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5930 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5931 i = tx_ring->next_to_use;
5932 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 5933 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 5934
5935 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5936 vlan_macip_lens |=
5937 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5938 vlan_macip_lens |= (skb_network_offset(skb) <<
e8e9f696 5939 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5940 if (skb->ip_summed == CHECKSUM_PARTIAL)
5941 vlan_macip_lens |= (skb_transport_header(skb) -
e8e9f696 5942 skb_network_header(skb));
9a799d71
AK		 5943
5944 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5945 context_desc->seqnum_seed = 0;
5946
5947 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
e8e9f696 5948 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 5949
7ca647bd
JP		 5950 if (skb->ip_summed == CHECKSUM_PARTIAL)
5951 type_tucmd_mlhl |= ixgbe_psum(adapter, skb);
9a799d71
AK		 5952
5953 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 5954 /* use index zero for tx checksum offload */
9a799d71
AK		 5955 context_desc->mss_l4len_idx = 0;
5956
5957 tx_buffer_info->time_stamp = jiffies;
5958 tx_buffer_info->next_to_watch = i;
9f8cdf4f 5959
9a799d71
AK		 5960 i++;
5961 if (i == tx_ring->count)
5962 i = 0;
5963 tx_ring->next_to_use = i;
5964
5965 return true;
5966 }
9f8cdf4f 5967
9a799d71
AK		 5968 return false;
5969}
5970
5971static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
e8e9f696
JP		 5972 struct ixgbe_ring *tx_ring,
5973 struct sk_buff *skb, u32 tx_flags,
5974 unsigned int first)
9a799d71 5975{
e5a43549 5976 struct pci_dev *pdev = adapter->pdev;
9a799d71 5977 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 5978 unsigned int len;
5979 unsigned int total = skb->len;
9a799d71
AK		 5980 unsigned int offset = 0, size, count = 0, i;
5981 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5982 unsigned int f;
9a799d71
AK		 5983
5984 i = tx_ring->next_to_use;
5985
eacd73f7
YZ		 5986 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5987 /* excluding fcoe_crc_eof for FCoE */
5988 total -= sizeof(struct fcoe_crc_eof);
5989
5990 len = min(skb_headlen(skb), total);
9a799d71
AK		 5991 while (len) {
5992 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5993 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5994
5995 tx_buffer_info->length = size;
e5a43549 5996 tx_buffer_info->mapped_as_page = false;
1b507730 5997 tx_buffer_info->dma = dma_map_single(&pdev->dev,
e5a43549 5998 skb->data + offset,
1b507730
NN		 5999 size, DMA_TO_DEVICE);
6000 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
e5a43549 6001 goto dma_error;
9a799d71
AK		 6002 tx_buffer_info->time_stamp = jiffies;
6003 tx_buffer_info->next_to_watch = i;
6004
6005 len -= size;
eacd73f7 6006 total -= size;
9a799d71
AK		 6007 offset += size;
6008 count++;
44df32c5
AD		 6009
6010 if (len) {
6011 i++;
6012 if (i == tx_ring->count)
6013 i = 0;
6014 }
9a799d71
AK		 6015 }
6016
6017 for (f = 0; f < nr_frags; f++) {
6018 struct skb_frag_struct *frag;
6019
6020 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 6021 len = min((unsigned int)frag->size, total);
e5a43549 6022 offset = frag->page_offset;
9a799d71
AK		 6023
6024 while (len) {
44df32c5
AD		 6025 i++;
6026 if (i == tx_ring->count)
6027 i = 0;
6028
9a799d71
AK		 6029 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6030 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6031
6032 tx_buffer_info->length = size;
1b507730 6033 tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
e5a43549
AD		 6034 frag->page,
6035 offset, size,
1b507730 6036 DMA_TO_DEVICE);
e5a43549 6037 tx_buffer_info->mapped_as_page = true;
1b507730 6038 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
e5a43549 6039 goto dma_error;
9a799d71
AK		 6040 tx_buffer_info->time_stamp = jiffies;
6041 tx_buffer_info->next_to_watch = i;
6042
6043 len -= size;
eacd73f7 6044 total -= size;
9a799d71
AK		 6045 offset += size;
6046 count++;
9a799d71 6047 }
eacd73f7
YZ		 6048 if (total == 0)
6049 break;
9a799d71 6050 }
44df32c5 6051
9a799d71
AK		 6052 tx_ring->tx_buffer_info[i].skb = skb;
6053 tx_ring->tx_buffer_info[first].next_to_watch = i;
6054
e5a43549
AD		 6055 return count;
6056
6057dma_error:
849c4542 6058 e_dev_err("TX DMA map failed\n");
e5a43549
AD		 6059
6060 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6061 tx_buffer_info->dma = 0;
6062 tx_buffer_info->time_stamp = 0;
6063 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 6064 if (count)
6065 count--;
e5a43549
AD		 6066
6067 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f 6068 while (count--) {
e8e9f696 6069 if (i == 0)
e5a43549 6070 i += tx_ring->count;
c1fa347f 6071 i--;
e5a43549
AD		 6072 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6073 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
6074 }
6075
e44d38e1 6076 return 0;
9a799d71
AK		 6077}
6078
6079static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
e8e9f696
JP		 6080 struct ixgbe_ring *tx_ring,
6081 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 6082{
6083 union ixgbe_adv_tx_desc *tx_desc = NULL;
6084 struct ixgbe_tx_buffer *tx_buffer_info;
6085 u32 olinfo_status = 0, cmd_type_len = 0;
6086 unsigned int i;
6087 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6088
6089 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6090
6091 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6092
6093 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6094 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6095
6096 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6097 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6098
6099 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6100 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6101
4eeae6fd
PW		 6102 /* use index 1 context for tso */
6103 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6104 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6105 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
e8e9f696 6106 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 6107
6108 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6109 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6110 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6111
eacd73f7
YZ		 6112 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6113 olinfo_status |= IXGBE_ADVTXD_CC;
6114 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6115 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6116 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6117 }
6118
9a799d71
AK		 6119 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6120
6121 i = tx_ring->next_to_use;
6122 while (count--) {
6123 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6124 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71
AK		 6125 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6126 tx_desc->read.cmd_type_len =
e8e9f696 6127 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 6128 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 6129 i++;
6130 if (i == tx_ring->count)
6131 i = 0;
6132 }
6133
6134 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6135
6136 /*
6137 * Force memory writes to complete before letting h/w
6138 * know there are new descriptors to fetch. (Only
6139 * applicable for weak-ordered memory model archs,
6140 * such as IA-64).
6141 */
6142 wmb();
6143
6144 tx_ring->next_to_use = i;
6145 writel(i, adapter->hw.hw_addr + tx_ring->tail);
6146}
6147
c4cf55e5 6148static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
e8e9f696 6149 int queue, u32 tx_flags)
c4cf55e5 6150{
c4cf55e5
PWJ		 6151 struct ixgbe_atr_input atr_input;
6152 struct tcphdr *th;
c4cf55e5
PWJ		 6153 struct iphdr *iph = ip_hdr(skb);
6154 struct ethhdr *eth = (struct ethhdr *)skb->data;
6155 u16 vlan_id, src_port, dst_port, flex_bytes;
6156 u32 src_ipv4_addr, dst_ipv4_addr;
6157 u8 l4type = 0;
6158
d3ead241
GG		 6159 /* Right now, we support IPv4 only */
6160 if (skb->protocol != htons(ETH_P_IP))
6161 return;
c4cf55e5
PWJ		 6162 /* check if we're UDP or TCP */
6163 if (iph->protocol == IPPROTO_TCP) {
6164 th = tcp_hdr(skb);
6165 src_port = th->source;
6166 dst_port = th->dest;
6167 l4type |= IXGBE_ATR_L4TYPE_TCP;
6168 /* l4type IPv4 type is 0, no need to assign */
c4cf55e5
PWJ		 6169 } else {
6170 /* Unsupported L4 header, just bail here */
6171 return;
6172 }
6173
6174 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6175
6176 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
e8e9f696 6177 IXGBE_TX_FLAGS_VLAN_SHIFT;
c4cf55e5
PWJ		 6178 src_ipv4_addr = iph->saddr;
6179 dst_ipv4_addr = iph->daddr;
6180 flex_bytes = eth->h_proto;
6181
6182 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6183 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6184 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6185 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6186 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6187 /* src and dst are inverted, think how the receiver sees them */
6188 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6189 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6190
6191 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6192 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6193}
6194
e092be60 6195static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
e8e9f696 6196 struct ixgbe_ring *tx_ring, int size)
e092be60 6197{
30eba97a 6198 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 6199 /* Herbert's original patch had:
6200 * smp_mb__after_netif_stop_queue();
6201 * but since that doesn't exist yet, just open code it. */
6202 smp_mb();
6203
6204 /* We need to check again in a case another CPU has just
6205 * made room available. */
6206 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6207 return -EBUSY;
6208
6209 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 6210 netif_start_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 6211 ++tx_ring->restart_queue;
e092be60
AV		 6212 return 0;
6213}
6214
6215static int ixgbe_maybe_stop_tx(struct net_device *netdev,
e8e9f696 6216 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 6217{
6218 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6219 return 0;
6220 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6221}
6222
09a3b1f8
SH		 6223static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6224{
6225 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 6226 int txq = smp_processor_id();
09a3b1f8 6227
56075a98
JF		 6228#ifdef IXGBE_FCOE
6229 if ((skb->protocol == htons(ETH_P_FCOE)) ||
6230 (skb->protocol == htons(ETH_P_FIP))) {
6231 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6232 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6233 txq += adapter->ring_feature[RING_F_FCOE].mask;
6234 return txq;
4bc091d8 6235#ifdef CONFIG_IXGBE_DCB
56075a98
JF		 6236 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6237 txq = adapter->fcoe.up;
6238 return txq;
4bc091d8 6239#endif
56075a98
JF		 6240 }
6241 }
6242#endif
6243
fdd3d631
KK		 6244 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6245 while (unlikely(txq >= dev->real_num_tx_queues))
6246 txq -= dev->real_num_tx_queues;
5f715823 6247 return txq;
fdd3d631 6248 }
c4cf55e5 6249
2ea186ae
JF		 6250 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6251 if (skb->priority == TC_PRIO_CONTROL)
6252 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6253 else
6254 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6255 >> 13;
6256 return txq;
6257 }
09a3b1f8
SH		 6258
6259 return skb_tx_hash(dev, skb);
6260}
6261
84418e3b
AD		 6262netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, struct net_device *netdev,
6263 struct ixgbe_adapter *adapter,
6264 struct ixgbe_ring *tx_ring)
9a799d71 6265{
60d51134 6266 struct netdev_queue *txq;
9a799d71
AK		 6267 unsigned int first;
6268 unsigned int tx_flags = 0;
30eba97a 6269 u8 hdr_len = 0;
5f715823 6270 int tso;
9a799d71
AK		 6271 int count = 0;
6272 unsigned int f;
9f8cdf4f 6273
9f8cdf4f
JB		 6274 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
6275 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 6276 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6277 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5f715823 6278 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
2f90b865
AD		 6279 }
6280 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6281 tx_flags |= IXGBE_TX_FLAGS_VLAN;
33c66bd1
JF		 6282 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6283 skb->priority != TC_PRIO_CONTROL) {
2ea186ae
JF		 6284 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6285 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6286 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 6287 }
eacd73f7 6288
09ad1cc0 6289#ifdef IXGBE_FCOE
56075a98
JF		 6290 /* for FCoE with DCB, we force the priority to what
6291 * was specified by the switch */
6292 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6293 (skb->protocol == htons(ETH_P_FCOE) ||
6294 skb->protocol == htons(ETH_P_FIP))) {
4bc091d8
JF		 6295#ifdef CONFIG_IXGBE_DCB
6296 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6297 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6298 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6299 tx_flags |= ((adapter->fcoe.up << 13)
6300 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6301 }
6302#endif
ca77cd59
RL		 6303 /* flag for FCoE offloads */
6304 if (skb->protocol == htons(ETH_P_FCOE))
6305 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0 6306 }
ca77cd59
RL		 6307#endif
6308
eacd73f7 6309 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 6310 if (skb_is_gso(skb) ||
6311 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 6312 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6313 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 6314 count++;
6315
9f8cdf4f
JB		 6316 count += TXD_USE_COUNT(skb_headlen(skb));
6317 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 6318 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6319
e092be60 6320 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 6321 adapter->tx_busy++;
9a799d71
AK		 6322 return NETDEV_TX_BUSY;
6323 }
9a799d71 6324
9a799d71 6325 first = tx_ring->next_to_use;
eacd73f7
YZ		 6326 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6327#ifdef IXGBE_FCOE
6328 /* setup tx offload for FCoE */
6329 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6330 if (tso < 0) {
6331 dev_kfree_skb_any(skb);
6332 return NETDEV_TX_OK;
6333 }
6334 if (tso)
6335 tx_flags |= IXGBE_TX_FLAGS_FSO;
6336#endif /* IXGBE_FCOE */
6337 } else {
6338 if (skb->protocol == htons(ETH_P_IP))
6339 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6340 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6341 if (tso < 0) {
6342 dev_kfree_skb_any(skb);
6343 return NETDEV_TX_OK;
6344 }
9a799d71 6345
eacd73f7
YZ		 6346 if (tso)
6347 tx_flags |= IXGBE_TX_FLAGS_TSO;
6348 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
6349 (skb->ip_summed == CHECKSUM_PARTIAL))
6350 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6351 }
9a799d71 6352
eacd73f7 6353 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 6354 if (count) {
c4cf55e5
PWJ		 6355 /* add the ATR filter if ATR is on */
6356 if (tx_ring->atr_sample_rate) {
6357 ++tx_ring->atr_count;
6358 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
e8e9f696
JP		 6359 test_bit(__IXGBE_FDIR_INIT_DONE,
6360 &tx_ring->reinit_state)) {
c4cf55e5 6361 ixgbe_atr(adapter, skb, tx_ring->queue_index,
e8e9f696 6362 tx_flags);
c4cf55e5
PWJ		 6363 tx_ring->atr_count = 0;
6364 }
6365 }
60d51134
ED		 6366 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6367 txq->tx_bytes += skb->len;
6368 txq->tx_packets++;
44df32c5 6369 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
e8e9f696 6370 hdr_len);
44df32c5 6371 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 6372
44df32c5
AD		 6373 } else {
6374 dev_kfree_skb_any(skb);
6375 tx_ring->tx_buffer_info[first].time_stamp = 0;
6376 tx_ring->next_to_use = first;
6377 }
9a799d71
AK		 6378
6379 return NETDEV_TX_OK;
6380}
6381
84418e3b
AD		 6382static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6383{
6384 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6385 struct ixgbe_ring *tx_ring;
6386
6387 tx_ring = adapter->tx_ring[skb->queue_mapping];
6388 return ixgbe_xmit_frame_ring(skb, netdev, adapter, tx_ring);
6389}
6390
9a799d71
AK		 6391/**
6392 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6393 * @netdev: network interface device structure
6394 * @p: pointer to an address structure
6395 *
6396 * Returns 0 on success, negative on failure
6397 **/
6398static int ixgbe_set_mac(struct net_device *netdev, void *p)
6399{
6400 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6401 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6402 struct sockaddr *addr = p;
6403
6404 if (!is_valid_ether_addr(addr->sa_data))
6405 return -EADDRNOTAVAIL;
6406
6407 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6408 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6409
1cdd1ec8
GR		 6410 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6411 IXGBE_RAH_AV);
9a799d71
AK		 6412
6413 return 0;
6414}
6415
6b73e10d
BH		 6416static int
6417ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6418{
6419 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6420 struct ixgbe_hw *hw = &adapter->hw;
6421 u16 value;
6422 int rc;
6423
6424 if (prtad != hw->phy.mdio.prtad)
6425 return -EINVAL;
6426 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6427 if (!rc)
6428 rc = value;
6429 return rc;
6430}
6431
6432static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6433 u16 addr, u16 value)
6434{
6435 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6436 struct ixgbe_hw *hw = &adapter->hw;
6437
6438 if (prtad != hw->phy.mdio.prtad)
6439 return -EINVAL;
6440 return hw->phy.ops.write_reg(hw, addr, devad, value);
6441}
6442
6443static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6444{
6445 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6446
6447 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6448}
6449
0365e6e4
PW		 6450/**
6451 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6452 * netdev->dev_addrs
0365e6e4
PW		 6453 * @netdev: network interface device structure
6454 *
6455 * Returns non-zero on failure
6456 **/
6457static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6458{
6459 int err = 0;
6460 struct ixgbe_adapter *adapter = netdev_priv(dev);
6461 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6462
6463 if (is_valid_ether_addr(mac->san_addr)) {
6464 rtnl_lock();
6465 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6466 rtnl_unlock();
6467 }
6468 return err;
6469}
6470
6471/**
6472 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6473 * netdev->dev_addrs
0365e6e4
PW		 6474 * @netdev: network interface device structure
6475 *
6476 * Returns non-zero on failure
6477 **/
6478static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6479{
6480 int err = 0;
6481 struct ixgbe_adapter *adapter = netdev_priv(dev);
6482 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6483
6484 if (is_valid_ether_addr(mac->san_addr)) {
6485 rtnl_lock();
6486 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6487 rtnl_unlock();
6488 }
6489 return err;
6490}
6491
9a799d71
AK		 6492#ifdef CONFIG_NET_POLL_CONTROLLER
6493/*
6494 * Polling 'interrupt' - used by things like netconsole to send skbs
6495 * without having to re-enable interrupts. It's not called while
6496 * the interrupt routine is executing.
6497 */
6498static void ixgbe_netpoll(struct net_device *netdev)
6499{
6500 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6501 int i;
9a799d71 6502
1a647bd2
AD		 6503 /* if interface is down do nothing */
6504 if (test_bit(__IXGBE_DOWN, &adapter->state))
6505 return;
6506
9a799d71 6507 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 6508 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6509 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6510 for (i = 0; i < num_q_vectors; i++) {
6511 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6512 ixgbe_msix_clean_many(0, q_vector);
6513 }
6514 } else {
6515 ixgbe_intr(adapter->pdev->irq, netdev);
6516 }
9a799d71 6517 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 6518}
6519#endif
6520
0edc3527 6521static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 6522 .ndo_open = ixgbe_open,
0edc3527 6523 .ndo_stop = ixgbe_close,
00829823 6524 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 6525 .ndo_select_queue = ixgbe_select_queue,
e90d400c 6526 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 6527 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6528 .ndo_validate_addr = eth_validate_addr,
6529 .ndo_set_mac_address = ixgbe_set_mac,
6530 .ndo_change_mtu = ixgbe_change_mtu,
6531 .ndo_tx_timeout = ixgbe_tx_timeout,
6532 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
6533 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6534 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 6535 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 6536 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6537 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6538 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6539 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
0edc3527
SH		 6540#ifdef CONFIG_NET_POLL_CONTROLLER
6541 .ndo_poll_controller = ixgbe_netpoll,
6542#endif
332d4a7d
YZ		 6543#ifdef IXGBE_FCOE
6544 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6545 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 6546 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6547 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 6548 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 6549#endif /* IXGBE_FCOE */
0edc3527
SH		 6550};
6551
1cdd1ec8
GR		 6552static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6553 const struct ixgbe_info *ii)
6554{
6555#ifdef CONFIG_PCI_IOV
6556 struct ixgbe_hw *hw = &adapter->hw;
6557 int err;
6558
6559 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6560 return;
6561
6562 /* The 82599 supports up to 64 VFs per physical function
6563 * but this implementation limits allocation to 63 so that
6564 * basic networking resources are still available to the
6565 * physical function
6566 */
6567 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6568 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6569 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6570 if (err) {
396e799c 6571 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
1cdd1ec8
GR		 6572 goto err_novfs;
6573 }
6574 /* If call to enable VFs succeeded then allocate memory
6575 * for per VF control structures.
6576 */
6577 adapter->vfinfo =
6578 kcalloc(adapter->num_vfs,
6579 sizeof(struct vf_data_storage), GFP_KERNEL);
6580 if (adapter->vfinfo) {
6581 /* Now that we're sure SR-IOV is enabled
6582 * and memory allocated set up the mailbox parameters
6583 */
6584 ixgbe_init_mbx_params_pf(hw);
6585 memcpy(&hw->mbx.ops, ii->mbx_ops,
6586 sizeof(hw->mbx.ops));
6587
6588 /* Disable RSC when in SR-IOV mode */
6589 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6590 IXGBE_FLAG2_RSC_ENABLED);
6591 return;
6592 }
6593
6594 /* Oh oh */
396e799c
ET		 6595 e_err(probe, "Unable to allocate memory for VF Data Storage - "
6596 "SRIOV disabled\n");
1cdd1ec8
GR		 6597 pci_disable_sriov(adapter->pdev);
6598
6599err_novfs:
6600 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6601 adapter->num_vfs = 0;
6602#endif /* CONFIG_PCI_IOV */
6603}
6604
9a799d71
AK		 6605/**
6606 * ixgbe_probe - Device Initialization Routine
6607 * @pdev: PCI device information struct
6608 * @ent: entry in ixgbe_pci_tbl
6609 *
6610 * Returns 0 on success, negative on failure
6611 *
6612 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6613 * The OS initialization, configuring of the adapter private structure,
6614 * and a hardware reset occur.
6615 **/
6616static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 6617 const struct pci_device_id *ent)
9a799d71
AK		 6618{
6619 struct net_device *netdev;
6620 struct ixgbe_adapter *adapter = NULL;
6621 struct ixgbe_hw *hw;
6622 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 6623 static int cards_found;
6624 int i, err, pci_using_dac;
c85a2618 6625 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 6626#ifdef IXGBE_FCOE
6627 u16 device_caps;
6628#endif
c44ade9e 6629 u32 part_num, eec;
9a799d71 6630
bded64a7
AG		 6631 /* Catch broken hardware that put the wrong VF device ID in
6632 * the PCIe SR-IOV capability.
6633 */
6634 if (pdev->is_virtfn) {
6635 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6636 pci_name(pdev), pdev->vendor, pdev->device);
6637 return -EINVAL;
6638 }
6639
9ce77666 6640 err = pci_enable_device_mem(pdev);
9a799d71
AK		 6641 if (err)
6642 return err;
6643
1b507730
NN		 6644 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6645 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 6646 pci_using_dac = 1;
6647 } else {
1b507730 6648 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 6649 if (err) {
1b507730
NN		 6650 err = dma_set_coherent_mask(&pdev->dev,
6651 DMA_BIT_MASK(32));
9a799d71 6652 if (err) {
b8bc0421
DC		 6653 dev_err(&pdev->dev,
6654 "No usable DMA configuration, aborting\n");
9a799d71
AK		 6655 goto err_dma;
6656 }
6657 }
6658 pci_using_dac = 0;
6659 }
6660
9ce77666 6661 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 6662 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 6663 if (err) {
b8bc0421
DC		 6664 dev_err(&pdev->dev,
6665 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 6666 goto err_pci_reg;
6667 }
6668
19d5afd4 6669 pci_enable_pcie_error_reporting(pdev);
6fabd715 6670
9a799d71 6671 pci_set_master(pdev);
fb3b27bc 6672 pci_save_state(pdev);
9a799d71 6673
c85a2618
JF		 6674 if (ii->mac == ixgbe_mac_82598EB)
6675 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6676 else
6677 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6678
6679 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6680#ifdef IXGBE_FCOE
6681 indices += min_t(unsigned int, num_possible_cpus(),
6682 IXGBE_MAX_FCOE_INDICES);
6683#endif
c85a2618 6684 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 6685 if (!netdev) {
6686 err = -ENOMEM;
6687 goto err_alloc_etherdev;
6688 }
6689
9a799d71
AK		 6690 SET_NETDEV_DEV(netdev, &pdev->dev);
6691
6692 pci_set_drvdata(pdev, netdev);
6693 adapter = netdev_priv(netdev);
6694
6695 adapter->netdev = netdev;
6696 adapter->pdev = pdev;
6697 hw = &adapter->hw;
6698 hw->back = adapter;
6699 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6700
05857980 6701 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 6702 pci_resource_len(pdev, 0));
9a799d71
AK		 6703 if (!hw->hw_addr) {
6704 err = -EIO;
6705 goto err_ioremap;
6706 }
6707
6708 for (i = 1; i <= 5; i++) {
6709 if (pci_resource_len(pdev, i) == 0)
6710 continue;
6711 }
6712
0edc3527 6713 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 6714 ixgbe_set_ethtool_ops(netdev);
9a799d71 6715 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 6716 strcpy(netdev->name, pci_name(pdev));
6717
9a799d71
AK		 6718 adapter->bd_number = cards_found;
6719
9a799d71
AK		 6720 /* Setup hw api */
6721 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 6722 hw->mac.type = ii->mac;
9a799d71 6723
c44ade9e
JB		 6724 /* EEPROM */
6725 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6726 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6727 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6728 if (!(eec & (1 << 8)))
6729 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6730
6731 /* PHY */
6732 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 6733 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 6734 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6735 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6736 hw->phy.mdio.mmds = 0;
6737 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6738 hw->phy.mdio.dev = netdev;
6739 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6740 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 6741
6742 /* set up this timer and work struct before calling get_invariants
6743 * which might start the timer
6744 */
6745 init_timer(&adapter->sfp_timer);
c061b18d 6746 adapter->sfp_timer.function = ixgbe_sfp_timer;
c4900be0
DS		 6747 adapter->sfp_timer.data = (unsigned long) adapter;
6748
6749 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 6750
e8e26350
PW		 6751 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6752 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6753
6754 /* a new SFP+ module arrival, called from GPI SDP2 context */
6755 INIT_WORK(&adapter->sfp_config_module_task,
e8e9f696 6756 ixgbe_sfp_config_module_task);
e8e26350 6757
8ca783ab 6758 ii->get_invariants(hw);
9a799d71
AK		 6759
6760 /* setup the private structure */
6761 err = ixgbe_sw_init(adapter);
6762 if (err)
6763 goto err_sw_init;
6764
e86bff0e
DS		 6765 /* Make it possible the adapter to be woken up via WOL */
6766 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6767 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6768
bf069c97
DS		 6769 /*
6770 * If there is a fan on this device and it has failed log the
6771 * failure.
6772 */
6773 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6774 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6775 if (esdp & IXGBE_ESDP_SDP1)
396e799c 6776 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 6777 }
6778
c44ade9e 6779 /* reset_hw fills in the perm_addr as well */
119fc60a 6780 hw->phy.reset_if_overtemp = true;
c44ade9e 6781 err = hw->mac.ops.reset_hw(hw);
119fc60a 6782 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 6783 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6784 hw->mac.type == ixgbe_mac_82598EB) {
6785 /*
6786 * Start a kernel thread to watch for a module to arrive.
6787 * Only do this for 82598, since 82599 will generate
6788 * interrupts on module arrival.
6789 */
6790 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6791 mod_timer(&adapter->sfp_timer,
6792 round_jiffies(jiffies + (2 * HZ)));
6793 err = 0;
6794 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 6795 e_dev_err("failed to initialize because an unsupported SFP+ "
6796 "module type was detected.\n");
6797 e_dev_err("Reload the driver after installing a supported "
6798 "module.\n");
04f165ef
PW		 6799 goto err_sw_init;
6800 } else if (err) {
849c4542 6801 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 6802 goto err_sw_init;
6803 }
6804
1cdd1ec8
GR		 6805 ixgbe_probe_vf(adapter, ii);
6806
396e799c 6807 netdev->features = NETIF_F_SG |
e8e9f696
JP		 6808 NETIF_F_IP_CSUM |
6809 NETIF_F_HW_VLAN_TX |
6810 NETIF_F_HW_VLAN_RX |
6811 NETIF_F_HW_VLAN_FILTER;
9a799d71 6812
e9990a9c 6813 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 6814 netdev->features |= NETIF_F_TSO;
9a799d71 6815 netdev->features |= NETIF_F_TSO6;
78b6f4ce 6816 netdev->features |= NETIF_F_GRO;
ad31c402 6817
45a5ead0
JB		 6818 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6819 netdev->features |= NETIF_F_SCTP_CSUM;
6820
ad31c402
JK		 6821 netdev->vlan_features |= NETIF_F_TSO;
6822 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 6823 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 6824 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 6825 netdev->vlan_features |= NETIF_F_SG;
6826
1cdd1ec8
GR		 6827 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6828 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6829 IXGBE_FLAG_DCB_ENABLED);
2f90b865
AD		 6830 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6831 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6832
7a6b6f51 6833#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 6834 netdev->dcbnl_ops = &dcbnl_ops;
6835#endif
6836
eacd73f7 6837#ifdef IXGBE_FCOE
0d551589 6838 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 6839 if (hw->mac.ops.get_device_caps) {
6840 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 6841 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6842 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 6843 }
6844 }
5e09d7f6
YZ		 6845 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6846 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6847 netdev->vlan_features |= NETIF_F_FSO;
6848 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6849 }
eacd73f7 6850#endif /* IXGBE_FCOE */
7b872a55 6851 if (pci_using_dac) {
9a799d71 6852 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6853 netdev->vlan_features |= NETIF_F_HIGHDMA;
6854 }
9a799d71 6855
0c19d6af 6856 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 6857 netdev->features |= NETIF_F_LRO;
6858
9a799d71 6859 /* make sure the EEPROM is good */
c44ade9e 6860 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 6861 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 6862 err = -EIO;
6863 goto err_eeprom;
6864 }
6865
6866 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6867 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6868
c44ade9e 6869 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 6870 e_dev_err("invalid MAC address\n");
9a799d71
AK		 6871 err = -EIO;
6872 goto err_eeprom;
6873 }
6874
61fac744
PW		 6875 /* power down the optics */
6876 if (hw->phy.multispeed_fiber)
6877 hw->mac.ops.disable_tx_laser(hw);
6878
9a799d71 6879 init_timer(&adapter->watchdog_timer);
c061b18d 6880 adapter->watchdog_timer.function = ixgbe_watchdog;
9a799d71
AK		 6881 adapter->watchdog_timer.data = (unsigned long)adapter;
6882
6883 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 6884 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 6885
021230d4
AV		 6886 err = ixgbe_init_interrupt_scheme(adapter);
6887 if (err)
6888 goto err_sw_init;
9a799d71 6889
e8e26350
PW		 6890 switch (pdev->device) {
6891 case IXGBE_DEV_ID_82599_KX4:
495dce12 6892 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
e8e9f696 6893 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 6894 break;
6895 default:
6896 adapter->wol = 0;
6897 break;
6898 }
e8e26350
PW		 6899 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6900
04f165ef
PW		 6901 /* pick up the PCI bus settings for reporting later */
6902 hw->mac.ops.get_bus_info(hw);
6903
9a799d71 6904 /* print bus type/speed/width info */
849c4542 6905 e_dev_info("(PCI Express:%s:%s) %pM\n",
e8e9f696
JP		 6906 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
6907 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
6908 "Unknown"),
6909 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
6910 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
6911 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
6912 "Unknown"),
6913 netdev->dev_addr);
c44ade9e 6914 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350 6915 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
849c4542
ET		 6916 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
6917 "PBA No: %06x-%03x\n",
6918 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6919 (part_num >> 8), (part_num & 0xff));
e8e26350 6920 else
849c4542
ET		 6921 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6922 hw->mac.type, hw->phy.type,
6923 (part_num >> 8), (part_num & 0xff));
9a799d71 6924
e8e26350 6925 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 6926 e_dev_warn("PCI-Express bandwidth available for this card is "
6927 "not sufficient for optimal performance.\n");
6928 e_dev_warn("For optimal performance a x8 PCI-Express slot "
6929 "is required.\n");
0c254d86
AK		 6930 }
6931
34b0368c
PWJ		 6932 /* save off EEPROM version number */
6933 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6934
9a799d71 6935 /* reset the hardware with the new settings */
794caeb2 6936 err = hw->mac.ops.start_hw(hw);
c44ade9e 6937
794caeb2
PWJ		 6938 if (err == IXGBE_ERR_EEPROM_VERSION) {
6939 /* We are running on a pre-production device, log a warning */
849c4542
ET		 6940 e_dev_warn("This device is a pre-production adapter/LOM. "
6941 "Please be aware there may be issues associated "
6942 "with your hardware. If you are experiencing "
6943 "problems please contact your Intel or hardware "
6944 "representative who provided you with this "
6945 "hardware.\n");
794caeb2 6946 }
9a799d71
AK		 6947 strcpy(netdev->name, "eth%d");
6948 err = register_netdev(netdev);
6949 if (err)
6950 goto err_register;
6951
54386467
JB		 6952 /* carrier off reporting is important to ethtool even BEFORE open */
6953 netif_carrier_off(netdev);
6954
c4cf55e5
PWJ		 6955 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6956 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6957 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6958
119fc60a 6959 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
e8e9f696
JP		 6960 INIT_WORK(&adapter->check_overtemp_task,
6961 ixgbe_check_overtemp_task);
5dd2d332 6962#ifdef CONFIG_IXGBE_DCA
652f093f 6963 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 6964 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 6965 ixgbe_setup_dca(adapter);
6966 }
6967#endif
1cdd1ec8 6968 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 6969 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 6970 for (i = 0; i < adapter->num_vfs; i++)
6971 ixgbe_vf_configuration(pdev, (i | 0x10000000));
6972 }
6973
0365e6e4
PW		 6974 /* add san mac addr to netdev */
6975 ixgbe_add_sanmac_netdev(netdev);
9a799d71 6976
849c4542 6977 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 6978 cards_found++;
6979 return 0;
6980
6981err_register:
5eba3699 6982 ixgbe_release_hw_control(adapter);
7a921c93 6983 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 6984err_sw_init:
6985err_eeprom:
1cdd1ec8
GR		 6986 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6987 ixgbe_disable_sriov(adapter);
c4900be0
DS		 6988 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6989 del_timer_sync(&adapter->sfp_timer);
6990 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6991 cancel_work_sync(&adapter->multispeed_fiber_task);
6992 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 6993 iounmap(hw->hw_addr);
6994err_ioremap:
6995 free_netdev(netdev);
6996err_alloc_etherdev:
e8e9f696
JP		 6997 pci_release_selected_regions(pdev,
6998 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 6999err_pci_reg:
7000err_dma:
7001 pci_disable_device(pdev);
7002 return err;
7003}
7004
7005/**
7006 * ixgbe_remove - Device Removal Routine
7007 * @pdev: PCI device information struct
7008 *
7009 * ixgbe_remove is called by the PCI subsystem to alert the driver
7010 * that it should release a PCI device. The could be caused by a
7011 * Hot-Plug event, or because the driver is going to be removed from
7012 * memory.
7013 **/
7014static void __devexit ixgbe_remove(struct pci_dev *pdev)
7015{
7016 struct net_device *netdev = pci_get_drvdata(pdev);
7017 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7018
7019 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 7020 /* clear the module not found bit to make sure the worker won't
7021 * reschedule
7022 */
7023 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 7024 del_timer_sync(&adapter->watchdog_timer);
7025
c4900be0
DS		 7026 del_timer_sync(&adapter->sfp_timer);
7027 cancel_work_sync(&adapter->watchdog_task);
7028 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 7029 cancel_work_sync(&adapter->multispeed_fiber_task);
7030 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 7031 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7032 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7033 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 7034 flush_scheduled_work();
7035
5dd2d332 7036#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7037 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7038 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7039 dca_remove_requester(&pdev->dev);
7040 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7041 }
7042
7043#endif
332d4a7d
YZ		 7044#ifdef IXGBE_FCOE
7045 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7046 ixgbe_cleanup_fcoe(adapter);
7047
7048#endif /* IXGBE_FCOE */
0365e6e4
PW		 7049
7050 /* remove the added san mac */
7051 ixgbe_del_sanmac_netdev(netdev);
7052
c4900be0
DS		 7053 if (netdev->reg_state == NETREG_REGISTERED)
7054 unregister_netdev(netdev);
9a799d71 7055
1cdd1ec8
GR		 7056 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7057 ixgbe_disable_sriov(adapter);
7058
7a921c93 7059 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7060
021230d4 7061 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7062
7063 iounmap(adapter->hw.hw_addr);
9ce77666 7064 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7065 IORESOURCE_MEM));
9a799d71 7066
849c4542 7067 e_dev_info("complete\n");
021230d4 7068
9a799d71
AK		 7069 free_netdev(netdev);
7070
19d5afd4 7071 pci_disable_pcie_error_reporting(pdev);
6fabd715 7072
9a799d71
AK		 7073 pci_disable_device(pdev);
7074}
7075
7076/**
7077 * ixgbe_io_error_detected - called when PCI error is detected
7078 * @pdev: Pointer to PCI device
7079 * @state: The current pci connection state
7080 *
7081 * This function is called after a PCI bus error affecting
7082 * this device has been detected.
7083 */
7084static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7085 pci_channel_state_t state)
9a799d71
AK		 7086{
7087 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7088 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 7089
7090 netif_device_detach(netdev);
7091
3044b8d1
BL		 7092 if (state == pci_channel_io_perm_failure)
7093 return PCI_ERS_RESULT_DISCONNECT;
7094
9a799d71
AK		 7095 if (netif_running(netdev))
7096 ixgbe_down(adapter);
7097 pci_disable_device(pdev);
7098
b4617240 7099 /* Request a slot reset. */
9a799d71
AK		 7100 return PCI_ERS_RESULT_NEED_RESET;
7101}
7102
7103/**
7104 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7105 * @pdev: Pointer to PCI device
7106 *
7107 * Restart the card from scratch, as if from a cold-boot.
7108 */
7109static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7110{
7111 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7112 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 7113 pci_ers_result_t result;
7114 int err;
9a799d71 7115
9ce77666 7116 if (pci_enable_device_mem(pdev)) {
396e799c 7117 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7118 result = PCI_ERS_RESULT_DISCONNECT;
7119 } else {
7120 pci_set_master(pdev);
7121 pci_restore_state(pdev);
c0e1f68b 7122 pci_save_state(pdev);
9a799d71 7123
dd4d8ca6 7124 pci_wake_from_d3(pdev, false);
9a799d71 7125
6fabd715 7126 ixgbe_reset(adapter);
88512539 7127 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7128 result = PCI_ERS_RESULT_RECOVERED;
7129 }
7130
7131 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7132 if (err) {
849c4542
ET		 7133 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7134 "failed 0x%0x\n", err);
6fabd715
PWJ		 7135 /* non-fatal, continue */
7136 }
9a799d71 7137
6fabd715 7138 return result;
9a799d71
AK		 7139}
7140
7141/**
7142 * ixgbe_io_resume - called when traffic can start flowing again.
7143 * @pdev: Pointer to PCI device
7144 *
7145 * This callback is called when the error recovery driver tells us that
7146 * its OK to resume normal operation.
7147 */
7148static void ixgbe_io_resume(struct pci_dev *pdev)
7149{
7150 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7151 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 7152
7153 if (netif_running(netdev)) {
7154 if (ixgbe_up(adapter)) {
396e799c 7155 e_info(probe, "ixgbe_up failed after reset\n");
9a799d71
AK		 7156 return;
7157 }
7158 }
7159
7160 netif_device_attach(netdev);
9a799d71
AK		 7161}
7162
7163static struct pci_error_handlers ixgbe_err_handler = {
7164 .error_detected = ixgbe_io_error_detected,
7165 .slot_reset = ixgbe_io_slot_reset,
7166 .resume = ixgbe_io_resume,
7167};
7168
7169static struct pci_driver ixgbe_driver = {
7170 .name = ixgbe_driver_name,
7171 .id_table = ixgbe_pci_tbl,
7172 .probe = ixgbe_probe,
7173 .remove = __devexit_p(ixgbe_remove),
7174#ifdef CONFIG_PM
7175 .suspend = ixgbe_suspend,
7176 .resume = ixgbe_resume,
7177#endif
7178 .shutdown = ixgbe_shutdown,
7179 .err_handler = &ixgbe_err_handler
7180};
7181
7182/**
7183 * ixgbe_init_module - Driver Registration Routine
7184 *
7185 * ixgbe_init_module is the first routine called when the driver is
7186 * loaded. All it does is register with the PCI subsystem.
7187 **/
7188static int __init ixgbe_init_module(void)
7189{
7190 int ret;
c7689578 7191 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7192 pr_info("%s\n", ixgbe_copyright);
9a799d71 7193
5dd2d332 7194#ifdef CONFIG_IXGBE_DCA
bd0362dd 7195 dca_register_notify(&dca_notifier);
bd0362dd 7196#endif
5dd2d332 7197
9a799d71
AK		 7198 ret = pci_register_driver(&ixgbe_driver);
7199 return ret;
7200}
b4617240 7201
9a799d71
AK		 7202module_init(ixgbe_init_module);
7203
7204/**
7205 * ixgbe_exit_module - Driver Exit Cleanup Routine
7206 *
7207 * ixgbe_exit_module is called just before the driver is removed
7208 * from memory.
7209 **/
7210static void __exit ixgbe_exit_module(void)
7211{
5dd2d332 7212#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7213 dca_unregister_notify(&dca_notifier);
7214#endif
9a799d71
AK		 7215 pci_unregister_driver(&ixgbe_driver);
7216}
bd0362dd 7217
5dd2d332 7218#ifdef CONFIG_IXGBE_DCA
bd0362dd 7219static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7220 void *p)
bd0362dd
JC		 7221{
7222 int ret_val;
7223
7224 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7225 __ixgbe_notify_dca);
bd0362dd
JC		 7226
7227 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7228}
b453368d 7229
5dd2d332 7230#endif /* CONFIG_IXGBE_DCA */
849c4542 7231
b453368d 7232/**
849c4542 7233 * ixgbe_get_hw_dev return device
b453368d
AD		 7234 * used by hardware layer to print debugging information
7235 **/
849c4542 7236struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
b453368d
AD		 7237{
7238 struct ixgbe_adapter *adapter = hw->back;
849c4542 7239 return adapter->netdev;
b453368d 7240}
bd0362dd 7241
9a799d71
AK		 7242module_exit(ixgbe_exit_module);
7243
7244/* ixgbe_main.c */
kernel source for telekom puls (alcatel/mediatek)