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skbuff: align sk_buff::cb to 64 bit and close some potential holes
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71
AK		 38#include <linux/ipv6.h>
39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
41#include <linux/ethtool.h>
42#include <linux/if_vlan.h>
eacd73f7 43#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 44
45#include "ixgbe.h"
46#include "ixgbe_common.h"
ee5f784a 47#include "ixgbe_dcb_82599.h"
1cdd1ec8 48#include "ixgbe_sriov.h"
9a799d71
AK		 49
50char ixgbe_driver_name[] = "ixgbe";
9c8eb720 51static const char ixgbe_driver_string[] =
b4617240 52 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 53
92eb879f 54#define DRV_VERSION "2.0.62-k2"
9c8eb720 55const char ixgbe_driver_version[] = DRV_VERSION;
8c47eaa7 56static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
9a799d71
AK		 57
58static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 59 [board_82598] = &ixgbe_82598_info,
e8e26350 60 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 61};
62
63/* ixgbe_pci_tbl - PCI Device ID Table
64 *
65 * Wildcard entries (PCI_ANY_ID) should come last
66 * Last entry must be all 0s
67 *
68 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
69 * Class, Class Mask, private data (not used) }
70 */
a3aa1884 71static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
73 board_82598 },
9a799d71 74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 75 board_82598 },
9a799d71 76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 77 board_82598 },
0befdb3e
JB		 78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
79 board_82598 },
3845bec0
PWJ		 80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
81 board_82598 },
9a799d71 82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 83 board_82598 },
8d792cd9
JB		 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
85 board_82598 },
c4900be0
DS		 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
87 board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
89 board_82598 },
b95f5fcb
JB		 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
91 board_82598 },
c4900be0
DS		 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
93 board_82598 },
2f21bdd3
DS		 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
95 board_82598 },
e8e26350
PW		 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
97 board_82599 },
1fcf03e6
PWJ		 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
99 board_82599 },
74757d49
DS		 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
101 board_82599 },
e8e26350
PW		 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
103 board_82599 },
38ad1c8e
DS		 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
105 board_82599 },
dbfec662
DS		 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
107 board_82599 },
8911184f
PWJ		 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
109 board_82599 },
312eb931
DS		 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
111 board_82599 },
9a799d71
AK		 112
113 /* required last entry */
114 {0, }
115};
116MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
117
5dd2d332 118#ifdef CONFIG_IXGBE_DCA
bd0362dd 119static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 120 void *p);
bd0362dd
JC		 121static struct notifier_block dca_notifier = {
122 .notifier_call = ixgbe_notify_dca,
123 .next = NULL,
124 .priority = 0
125};
126#endif
127
1cdd1ec8
GR		 128#ifdef CONFIG_PCI_IOV
129static unsigned int max_vfs;
130module_param(max_vfs, uint, 0);
131MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
132 "per physical function");
133#endif /* CONFIG_PCI_IOV */
134
9a799d71
AK		 135MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
136MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
137MODULE_LICENSE("GPL");
138MODULE_VERSION(DRV_VERSION);
139
140#define DEFAULT_DEBUG_LEVEL_SHIFT 3
141
1cdd1ec8
GR		 142static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
143{
144 struct ixgbe_hw *hw = &adapter->hw;
145 u32 gcr;
146 u32 gpie;
147 u32 vmdctl;
148
149#ifdef CONFIG_PCI_IOV
150 /* disable iov and allow time for transactions to clear */
151 pci_disable_sriov(adapter->pdev);
152#endif
153
154 /* turn off device IOV mode */
155 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
156 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
157 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
158 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
159 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
160 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
161
162 /* set default pool back to 0 */
163 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
164 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
165 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
166
167 /* take a breather then clean up driver data */
168 msleep(100);
169 if (adapter->vfinfo)
170 kfree(adapter->vfinfo);
171 adapter->vfinfo = NULL;
172
173 adapter->num_vfs = 0;
174 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
175}
176
5eba3699
AV		 177static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
178{
179 u32 ctrl_ext;
180
181 /* Let firmware take over control of h/w */
182 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
183 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 184 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 185}
186
187static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
188{
189 u32 ctrl_ext;
190
191 /* Let firmware know the driver has taken over */
192 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
193 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 194 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 195}
9a799d71 196
e8e26350
PW		 197/*
198 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
199 * @adapter: pointer to adapter struct
200 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
201 * @queue: queue to map the corresponding interrupt to
202 * @msix_vector: the vector to map to the corresponding queue
203 *
204 */
205static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
206 u8 queue, u8 msix_vector)
9a799d71
AK		 207{
208 u32 ivar, index;
e8e26350
PW		 209 struct ixgbe_hw *hw = &adapter->hw;
210 switch (hw->mac.type) {
211 case ixgbe_mac_82598EB:
212 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
213 if (direction == -1)
214 direction = 0;
215 index = (((direction * 64) + queue) >> 2) & 0x1F;
216 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
217 ivar &= ~(0xFF << (8 * (queue & 0x3)));
218 ivar |= (msix_vector << (8 * (queue & 0x3)));
219 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
220 break;
221 case ixgbe_mac_82599EB:
222 if (direction == -1) {
223 /* other causes */
224 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
225 index = ((queue & 1) * 8);
226 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
227 ivar &= ~(0xFF << index);
228 ivar |= (msix_vector << index);
229 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
230 break;
231 } else {
232 /* tx or rx causes */
233 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
234 index = ((16 * (queue & 1)) + (8 * direction));
235 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
236 ivar &= ~(0xFF << index);
237 ivar |= (msix_vector << index);
238 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
239 break;
240 }
241 default:
242 break;
243 }
9a799d71
AK		 244}
245
fe49f04a
AD		 246static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
247 u64 qmask)
248{
249 u32 mask;
250
251 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
252 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
253 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
254 } else {
255 mask = (qmask & 0xFFFFFFFF);
256 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
257 mask = (qmask >> 32);
258 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
259 }
260}
261
9a799d71 262static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 263 struct ixgbe_tx_buffer
264 *tx_buffer_info)
9a799d71 265{
e5a43549
AD		 266 if (tx_buffer_info->dma) {
267 if (tx_buffer_info->mapped_as_page)
268 pci_unmap_page(adapter->pdev,
269 tx_buffer_info->dma,
270 tx_buffer_info->length,
271 PCI_DMA_TODEVICE);
272 else
273 pci_unmap_single(adapter->pdev,
274 tx_buffer_info->dma,
275 tx_buffer_info->length,
276 PCI_DMA_TODEVICE);
277 tx_buffer_info->dma = 0;
278 }
9a799d71
AK		 279 if (tx_buffer_info->skb) {
280 dev_kfree_skb_any(tx_buffer_info->skb);
281 tx_buffer_info->skb = NULL;
282 }
44df32c5 283 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 284 /* tx_buffer_info must be completely set up in the transmit path */
285}
286
26f23d82
YZ		 287/**
288 * ixgbe_tx_is_paused - check if the tx ring is paused
289 * @adapter: the ixgbe adapter
290 * @tx_ring: the corresponding tx_ring
291 *
292 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
293 * corresponding TC of this tx_ring when checking TFCS.
294 *
295 * Returns : true if paused
296 */
297static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
298 struct ixgbe_ring *tx_ring)
299{
26f23d82
YZ		 300 u32 txoff = IXGBE_TFCS_TXOFF;
301
302#ifdef CONFIG_IXGBE_DCB
303 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
30b76832 304 int tc;
26f23d82
YZ		 305 int reg_idx = tx_ring->reg_idx;
306 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
307
6837e895
PW		 308 switch (adapter->hw.mac.type) {
309 case ixgbe_mac_82598EB:
26f23d82
YZ		 310 tc = reg_idx >> 2;
311 txoff = IXGBE_TFCS_TXOFF0;
6837e895
PW		 312 break;
313 case ixgbe_mac_82599EB:
26f23d82
YZ		 314 tc = 0;
315 txoff = IXGBE_TFCS_TXOFF;
316 if (dcb_i == 8) {
317 /* TC0, TC1 */
318 tc = reg_idx >> 5;
319 if (tc == 2) /* TC2, TC3 */
320 tc += (reg_idx - 64) >> 4;
321 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
322 tc += 1 + ((reg_idx - 96) >> 3);
323 } else if (dcb_i == 4) {
324 /* TC0, TC1 */
325 tc = reg_idx >> 6;
326 if (tc == 1) {
327 tc += (reg_idx - 64) >> 5;
328 if (tc == 2) /* TC2, TC3 */
329 tc += (reg_idx - 96) >> 4;
330 }
331 }
6837e895
PW		 332 break;
333 default:
334 tc = 0;
26f23d82
YZ		 335 }
336 txoff <<= tc;
337 }
338#endif
339 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
340}
341
9a799d71 342static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 343 struct ixgbe_ring *tx_ring,
344 unsigned int eop)
9a799d71 345{
e01c31a5 346 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 347
9a799d71 348 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 349 * check with the clearing of time_stamp and movement of eop */
9a799d71 350 adapter->detect_tx_hung = false;
44df32c5 351 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71 352 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
26f23d82 353 !ixgbe_tx_is_paused(adapter, tx_ring)) {
9a799d71 354 /* detected Tx unit hang */
e01c31a5
JB		 355 union ixgbe_adv_tx_desc *tx_desc;
356 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 357 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 358 " Tx Queue <%d>\n"
359 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 360 " next_to_use <%x>\n"
361 " next_to_clean <%x>\n"
362 "tx_buffer_info[next_to_clean]\n"
363 " time_stamp <%lx>\n"
e01c31a5
JB		 364 " jiffies <%lx>\n",
365 tx_ring->queue_index,
44df32c5
AD		 366 IXGBE_READ_REG(hw, tx_ring->head),
367 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 368 tx_ring->next_to_use, eop,
369 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 370 return true;
371 }
372
373 return false;
374}
375
b4617240
PW		 376#define IXGBE_MAX_TXD_PWR 14
377#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 378
379/* Tx Descriptors needed, worst case */
380#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
381 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
382#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 383 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 384
e01c31a5
JB		 385static void ixgbe_tx_timeout(struct net_device *netdev);
386
9a799d71
AK		 387/**
388 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 389 * @q_vector: structure containing interrupt and ring information
e01c31a5 390 * @tx_ring: tx ring to clean
9a799d71 391 **/
fe49f04a 392static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e01c31a5 393 struct ixgbe_ring *tx_ring)
9a799d71 394{
fe49f04a 395 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 396 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 397 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
398 struct ixgbe_tx_buffer *tx_buffer_info;
399 unsigned int i, eop, count = 0;
e01c31a5 400 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 401
402 i = tx_ring->next_to_clean;
12207e49
PWJ		 403 eop = tx_ring->tx_buffer_info[i].next_to_watch;
404 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
405
406 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 407 (count < tx_ring->work_limit)) {
12207e49
PWJ		 408 bool cleaned = false;
409 for ( ; !cleaned; count++) {
410 struct sk_buff *skb;
9a799d71
AK		 411 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
412 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 413 cleaned = (i == eop);
e01c31a5 414 skb = tx_buffer_info->skb;
9a799d71 415
12207e49 416 if (cleaned && skb) {
e092be60 417 unsigned int segs, bytecount;
3d8fd385 418 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 419
420 /* gso_segs is currently only valid for tcp */
e092be60 421 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 422#ifdef IXGBE_FCOE
423 /* adjust for FCoE Sequence Offload */
424 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
425 && (skb->protocol == htons(ETH_P_FCOE)) &&
426 skb_is_gso(skb)) {
427 hlen = skb_transport_offset(skb) +
428 sizeof(struct fc_frame_header) +
429 sizeof(struct fcoe_crc_eof);
430 segs = DIV_ROUND_UP(skb->len - hlen,
431 skb_shinfo(skb)->gso_size);
432 }
433#endif /* IXGBE_FCOE */
e092be60 434 /* multiply data chunks by size of headers */
3d8fd385 435 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 436 total_packets += segs;
437 total_bytes += bytecount;
e092be60 438 }
e01c31a5 439
9a799d71 440 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 441 tx_buffer_info);
9a799d71 442
12207e49
PWJ		 443 tx_desc->wb.status = 0;
444
9a799d71
AK		 445 i++;
446 if (i == tx_ring->count)
447 i = 0;
e01c31a5 448 }
12207e49
PWJ		 449
450 eop = tx_ring->tx_buffer_info[i].next_to_watch;
451 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
452 }
453
9a799d71
AK		 454 tx_ring->next_to_clean = i;
455
e092be60 456#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 457 if (unlikely(count && netif_carrier_ok(netdev) &&
458 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 459 /* Make sure that anybody stopping the queue after this
460 * sees the new next_to_clean.
461 */
462 smp_mb();
30eba97a
AV		 463 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
464 !test_bit(__IXGBE_DOWN, &adapter->state)) {
465 netif_wake_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 466 ++tx_ring->restart_queue;
30eba97a 467 }
e092be60 468 }
9a799d71 469
e01c31a5
JB		 470 if (adapter->detect_tx_hung) {
471 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
472 /* schedule immediate reset if we believe we hung */
473 DPRINTK(PROBE, INFO,
474 "tx hang %d detected, resetting adapter\n",
475 adapter->tx_timeout_count + 1);
476 ixgbe_tx_timeout(adapter->netdev);
477 }
478 }
9a799d71 479
e01c31a5 480 /* re-arm the interrupt */
fe49f04a
AD		 481 if (count >= tx_ring->work_limit)
482 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 483
e01c31a5
JB		 484 tx_ring->total_bytes += total_bytes;
485 tx_ring->total_packets += total_packets;
e01c31a5 486 tx_ring->stats.packets += total_packets;
12207e49 487 tx_ring->stats.bytes += total_bytes;
9a1a69ad 488 return (count < tx_ring->work_limit);
9a799d71
AK		 489}
490
5dd2d332 491#ifdef CONFIG_IXGBE_DCA
bd0362dd 492static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 493 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 494{
495 u32 rxctrl;
496 int cpu = get_cpu();
4a0b9ca0 497 int q = rx_ring->reg_idx;
bd0362dd 498
3a581073 499 if (rx_ring->cpu != cpu) {
bd0362dd 500 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 501 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
502 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
503 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
504 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
505 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
506 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
507 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
508 }
bd0362dd
JC		 509 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
510 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 511 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
512 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 513 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 514 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 515 rx_ring->cpu = cpu;
bd0362dd
JC		 516 }
517 put_cpu();
518}
519
520static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 521 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 522{
523 u32 txctrl;
524 int cpu = get_cpu();
4a0b9ca0 525 int q = tx_ring->reg_idx;
ee5f784a 526 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 527
3a581073 528 if (tx_ring->cpu != cpu) {
e8e26350 529 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
ee5f784a 530 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 531 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
532 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
ee5f784a
DS		 533 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
534 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
e8e26350 535 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
ee5f784a 536 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
e8e26350
PW		 537 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
538 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
ee5f784a
DS		 539 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
540 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
541 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
e8e26350 542 }
3a581073 543 tx_ring->cpu = cpu;
bd0362dd
JC		 544 }
545 put_cpu();
546}
547
548static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
549{
550 int i;
551
552 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
553 return;
554
e35ec126
AD		 555 /* always use CB2 mode, difference is masked in the CB driver */
556 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
557
bd0362dd 558 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 559 adapter->tx_ring[i]->cpu = -1;
560 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
bd0362dd
JC		 561 }
562 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 563 adapter->rx_ring[i]->cpu = -1;
564 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
bd0362dd
JC		 565 }
566}
567
568static int __ixgbe_notify_dca(struct device *dev, void *data)
569{
570 struct net_device *netdev = dev_get_drvdata(dev);
571 struct ixgbe_adapter *adapter = netdev_priv(netdev);
572 unsigned long event = *(unsigned long *)data;
573
574 switch (event) {
575 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 576 /* if we're already enabled, don't do it again */
577 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
578 break;
652f093f 579 if (dca_add_requester(dev) == 0) {
96b0e0f6 580 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 581 ixgbe_setup_dca(adapter);
582 break;
583 }
584 /* Fall Through since DCA is disabled. */
585 case DCA_PROVIDER_REMOVE:
586 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
587 dca_remove_requester(dev);
588 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
589 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
590 }
591 break;
592 }
593
652f093f 594 return 0;
bd0362dd
JC		 595}
596
5dd2d332 597#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 598/**
599 * ixgbe_receive_skb - Send a completed packet up the stack
600 * @adapter: board private structure
601 * @skb: packet to send up
177db6ff
MC		 602 * @status: hardware indication of status of receive
603 * @rx_ring: rx descriptor ring (for a specific queue) to setup
604 * @rx_desc: rx descriptor
9a799d71 605 **/
78b6f4ce 606static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 607 struct sk_buff *skb, u8 status,
fdaff1ce 608 struct ixgbe_ring *ring,
177db6ff 609 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 610{
78b6f4ce
HX		 611 struct ixgbe_adapter *adapter = q_vector->adapter;
612 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 613 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
614 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 615
fdaff1ce 616 skb_record_rx_queue(skb, ring->queue_index);
182ff8df 617 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
8a62babf 618 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
78b6f4ce 619 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 620 else
78b6f4ce 621 napi_gro_receive(napi, skb);
177db6ff 622 } else {
8a62babf 623 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
182ff8df
AD		 624 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
625 else
626 netif_rx(skb);
9a799d71
AK		 627 }
628}
629
e59bd25d
AV		 630/**
631 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
632 * @adapter: address of board private structure
633 * @status_err: hardware indication of status of receive
634 * @skb: skb currently being received and modified
635 **/
9a799d71 636static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 637 union ixgbe_adv_rx_desc *rx_desc,
638 struct sk_buff *skb)
9a799d71 639{
8bae1b2b
DS		 640 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
641
9a799d71
AK		 642 skb->ip_summed = CHECKSUM_NONE;
643
712744be
JB		 644 /* Rx csum disabled */
645 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 646 return;
e59bd25d
AV		 647
648 /* if IP and error */
649 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
650 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 651 adapter->hw_csum_rx_error++;
652 return;
653 }
e59bd25d
AV		 654
655 if (!(status_err & IXGBE_RXD_STAT_L4CS))
656 return;
657
658 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 659 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
660
661 /*
662 * 82599 errata, UDP frames with a 0 checksum can be marked as
663 * checksum errors.
664 */
665 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
666 (adapter->hw.mac.type == ixgbe_mac_82599EB))
667 return;
668
e59bd25d
AV		 669 adapter->hw_csum_rx_error++;
670 return;
671 }
672
9a799d71 673 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 674 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 675}
676
e8e26350
PW		 677static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
678 struct ixgbe_ring *rx_ring, u32 val)
679{
680 /*
681 * Force memory writes to complete before letting h/w
682 * know there are new descriptors to fetch. (Only
683 * applicable for weak-ordered memory model archs,
684 * such as IA-64).
685 */
686 wmb();
687 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
688}
689
9a799d71
AK		 690/**
691 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
692 * @adapter: address of board private structure
693 **/
694static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 695 struct ixgbe_ring *rx_ring,
696 int cleaned_count)
9a799d71 697{
9a799d71
AK		 698 struct pci_dev *pdev = adapter->pdev;
699 union ixgbe_adv_rx_desc *rx_desc;
3a581073 700 struct ixgbe_rx_buffer *bi;
9a799d71 701 unsigned int i;
9a799d71
AK		 702
703 i = rx_ring->next_to_use;
3a581073 704 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 705
706 while (cleaned_count--) {
707 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
708
762f4c57 709 if (!bi->page_dma &&
6e455b89 710 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 711 if (!bi->page) {
762f4c57
JB		 712 bi->page = alloc_page(GFP_ATOMIC);
713 if (!bi->page) {
714 adapter->alloc_rx_page_failed++;
715 goto no_buffers;
716 }
717 bi->page_offset = 0;
718 } else {
719 /* use a half page if we're re-using */
720 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 721 }
762f4c57
JB		 722
723 bi->page_dma = pci_map_page(pdev, bi->page,
724 bi->page_offset,
725 (PAGE_SIZE / 2),
726 PCI_DMA_FROMDEVICE);
9a799d71
AK		 727 }
728
3a581073 729 if (!bi->skb) {
5ecc3614 730 struct sk_buff *skb;
7ca3bc58
JB		 731 /* netdev_alloc_skb reserves 32 bytes up front!! */
732 uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES;
733 skb = netdev_alloc_skb(adapter->netdev, bufsz);
9a799d71
AK		 734
735 if (!skb) {
736 adapter->alloc_rx_buff_failed++;
737 goto no_buffers;
738 }
739
7ca3bc58
JB		 740 /* advance the data pointer to the next cache line */
741 skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES)
742 - skb->data));
743
3a581073 744 bi->skb = skb;
4f57ca6e
JB		 745 bi->dma = pci_map_single(pdev, skb->data,
746 rx_ring->rx_buf_len,
3a581073 747 PCI_DMA_FROMDEVICE);
9a799d71
AK		 748 }
749 /* Refresh the desc even if buffer_addrs didn't change because
750 * each write-back erases this info. */
6e455b89 751 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 752 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
753 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 754 } else {
3a581073 755 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 756 }
757
758 i++;
759 if (i == rx_ring->count)
760 i = 0;
3a581073 761 bi = &rx_ring->rx_buffer_info[i];
9a799d71 762 }
7c6e0a43 763
9a799d71
AK		 764no_buffers:
765 if (rx_ring->next_to_use != i) {
766 rx_ring->next_to_use = i;
767 if (i-- == 0)
768 i = (rx_ring->count - 1);
769
e8e26350 770 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 771 }
772}
773
7c6e0a43
JB		 774static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
775{
776 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
777}
778
779static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
780{
781 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
782}
783
f8212f97
AD		 784static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
785{
786 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
787 IXGBE_RXDADV_RSCCNT_MASK) >>
788 IXGBE_RXDADV_RSCCNT_SHIFT;
789}
790
791/**
792 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
793 * @skb: pointer to the last skb in the rsc queue
94b982b2 794 * @count: pointer to number of packets coalesced in this context
f8212f97
AD		 795 *
796 * This function changes a queue full of hw rsc buffers into a completed
797 * packet. It uses the ->prev pointers to find the first packet and then
798 * turns it into the frag list owner.
799 **/
94b982b2
MC		 800static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
801 u64 *count)
f8212f97
AD		 802{
803 unsigned int frag_list_size = 0;
804
805 while (skb->prev) {
806 struct sk_buff *prev = skb->prev;
807 frag_list_size += skb->len;
808 skb->prev = NULL;
809 skb = prev;
94b982b2 810 *count += 1;
f8212f97
AD		 811 }
812
813 skb_shinfo(skb)->frag_list = skb->next;
814 skb->next = NULL;
815 skb->len += frag_list_size;
816 skb->data_len += frag_list_size;
817 skb->truesize += frag_list_size;
818 return skb;
819}
820
43634e82
MC		 821struct ixgbe_rsc_cb {
822 dma_addr_t dma;
823};
824
825#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
826
78b6f4ce 827static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 828 struct ixgbe_ring *rx_ring,
829 int *work_done, int work_to_do)
9a799d71 830{
78b6f4ce 831 struct ixgbe_adapter *adapter = q_vector->adapter;
2d86f139 832 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 833 struct pci_dev *pdev = adapter->pdev;
834 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
835 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
836 struct sk_buff *skb;
f8212f97 837 unsigned int i, rsc_count = 0;
7c6e0a43 838 u32 len, staterr;
177db6ff
MC		 839 u16 hdr_info;
840 bool cleaned = false;
9a799d71 841 int cleaned_count = 0;
d2f4fbe2 842 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 843#ifdef IXGBE_FCOE
844 int ddp_bytes = 0;
845#endif /* IXGBE_FCOE */
9a799d71
AK		 846
847 i = rx_ring->next_to_clean;
9a799d71
AK		 848 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
849 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
850 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 851
852 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 853 u32 upper_len = 0;
9a799d71
AK		 854 if (*work_done >= work_to_do)
855 break;
856 (*work_done)++;
857
3c945e5b 858 rmb(); /* read descriptor and rx_buffer_info after status DD */
6e455b89 859 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 860 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
861 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 862 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 863 if (len > IXGBE_RX_HDR_SIZE)
864 len = IXGBE_RX_HDR_SIZE;
865 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 866 } else {
9a799d71 867 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 868 }
9a799d71
AK		 869
870 cleaned = true;
871 skb = rx_buffer_info->skb;
7ca3bc58 872 prefetch(skb->data);
9a799d71
AK		 873 rx_buffer_info->skb = NULL;
874
21fa4e66 875 if (rx_buffer_info->dma) {
43634e82
MC		 876 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
877 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
878 (!(skb->prev)))
879 /*
880 * When HWRSC is enabled, delay unmapping
881 * of the first packet. It carries the
882 * header information, HW may still
883 * access the header after the writeback.
884 * Only unmap it when EOP is reached
885 */
886 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
887 else
888 pci_unmap_single(pdev, rx_buffer_info->dma,
889 rx_ring->rx_buf_len,
890 PCI_DMA_FROMDEVICE);
4f57ca6e 891 rx_buffer_info->dma = 0;
9a799d71
AK		 892 skb_put(skb, len);
893 }
894
895 if (upper_len) {
896 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 897 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 898 rx_buffer_info->page_dma = 0;
899 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 900 rx_buffer_info->page,
901 rx_buffer_info->page_offset,
902 upper_len);
903
904 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
905 (page_count(rx_buffer_info->page) != 1))
906 rx_buffer_info->page = NULL;
907 else
908 get_page(rx_buffer_info->page);
9a799d71
AK		 909
910 skb->len += upper_len;
911 skb->data_len += upper_len;
912 skb->truesize += upper_len;
913 }
914
915 i++;
916 if (i == rx_ring->count)
917 i = 0;
9a799d71
AK		 918
919 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
920 prefetch(next_rxd);
9a799d71 921 cleaned_count++;
f8212f97 922
0c19d6af 923 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 924 rsc_count = ixgbe_get_rsc_count(rx_desc);
925
926 if (rsc_count) {
927 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
928 IXGBE_RXDADV_NEXTP_SHIFT;
929 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 930 } else {
931 next_buffer = &rx_ring->rx_buffer_info[i];
932 }
933
9a799d71 934 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97 935 if (skb->prev)
94b982b2
MC		 936 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
937 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
43634e82
MC		 938 if (IXGBE_RSC_CB(skb)->dma)
939 pci_unmap_single(pdev, IXGBE_RSC_CB(skb)->dma,
940 rx_ring->rx_buf_len,
941 PCI_DMA_FROMDEVICE);
94b982b2
MC		 942 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
943 rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
944 else
945 rx_ring->rsc_count++;
946 rx_ring->rsc_flush++;
947 }
9a799d71
AK		 948 rx_ring->stats.packets++;
949 rx_ring->stats.bytes += skb->len;
950 } else {
6e455b89 951 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 952 rx_buffer_info->skb = next_buffer->skb;
953 rx_buffer_info->dma = next_buffer->dma;
954 next_buffer->skb = skb;
955 next_buffer->dma = 0;
956 } else {
957 skb->next = next_buffer->skb;
958 skb->next->prev = skb;
959 }
7ca3bc58 960 rx_ring->non_eop_descs++;
9a799d71
AK		 961 goto next_desc;
962 }
963
964 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
965 dev_kfree_skb_irq(skb);
966 goto next_desc;
967 }
968
8bae1b2b 969 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 970
971 /* probably a little skewed due to removing CRC */
972 total_rx_bytes += skb->len;
973 total_rx_packets++;
974
74ce8dd2 975 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 976#ifdef IXGBE_FCOE
977 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 978 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
979 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
980 if (!ddp_bytes)
332d4a7d 981 goto next_desc;
3d8fd385 982 }
332d4a7d 983#endif /* IXGBE_FCOE */
fdaff1ce 984 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 985
986next_desc:
987 rx_desc->wb.upper.status_error = 0;
988
989 /* return some buffers to hardware, one at a time is too slow */
990 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
991 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
992 cleaned_count = 0;
993 }
994
995 /* use prefetched values */
996 rx_desc = next_rxd;
f8212f97 997 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 998
999 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1000 }
1001
9a799d71
AK		 1002 rx_ring->next_to_clean = i;
1003 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1004
1005 if (cleaned_count)
1006 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1007
3d8fd385
YZ		 1008#ifdef IXGBE_FCOE
1009 /* include DDPed FCoE data */
1010 if (ddp_bytes > 0) {
1011 unsigned int mss;
1012
1013 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1014 sizeof(struct fc_frame_header) -
1015 sizeof(struct fcoe_crc_eof);
1016 if (mss > 512)
1017 mss &= ~511;
1018 total_rx_bytes += ddp_bytes;
1019 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1020 }
1021#endif /* IXGBE_FCOE */
1022
f494e8fa
AV		 1023 rx_ring->total_packets += total_rx_packets;
1024 rx_ring->total_bytes += total_rx_bytes;
2d86f139
AK		 1025 netdev->stats.rx_bytes += total_rx_bytes;
1026 netdev->stats.rx_packets += total_rx_packets;
f494e8fa 1027
9a799d71
AK		 1028 return cleaned;
1029}
1030
021230d4 1031static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1032/**
1033 * ixgbe_configure_msix - Configure MSI-X hardware
1034 * @adapter: board private structure
1035 *
1036 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1037 * interrupts.
1038 **/
1039static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1040{
021230d4
AV		 1041 struct ixgbe_q_vector *q_vector;
1042 int i, j, q_vectors, v_idx, r_idx;
1043 u32 mask;
9a799d71 1044
021230d4 1045 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1046
4df10466
JB		 1047 /*
1048 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1049 * corresponding register.
1050 */
1051 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1052 q_vector = adapter->q_vector[v_idx];
021230d4
AV		 1053 /* XXX for_each_bit(...) */
1054 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 1055 adapter->num_rx_queues);
021230d4
AV		 1056
1057 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1058 j = adapter->rx_ring[r_idx]->reg_idx;
e8e26350 1059 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 1060 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 1061 adapter->num_rx_queues,
1062 r_idx + 1);
021230d4
AV		 1063 }
1064 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 1065 adapter->num_tx_queues);
021230d4
AV		 1066
1067 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1068 j = adapter->tx_ring[r_idx]->reg_idx;
e8e26350 1069 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 1070 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 1071 adapter->num_tx_queues,
1072 r_idx + 1);
021230d4
AV		 1073 }
1074
021230d4 1075 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1076 /* tx only */
1077 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1078 else if (q_vector->rxr_count)
f7554a2b
NS		 1079 /* rx or mixed */
1080 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1081
fe49f04a 1082 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1083 }
1084
e8e26350
PW		 1085 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1086 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1087 v_idx);
1088 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1089 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 1090 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1091
41fb9248 1092 /* set up to autoclear timer, and the vectors */
021230d4 1093 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1094 if (adapter->num_vfs)
1095 mask &= ~(IXGBE_EIMS_OTHER |
1096 IXGBE_EIMS_MAILBOX |
1097 IXGBE_EIMS_LSC);
1098 else
1099 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1100 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1101}
1102
f494e8fa
AV		 1103enum latency_range {
1104 lowest_latency = 0,
1105 low_latency = 1,
1106 bulk_latency = 2,
1107 latency_invalid = 255
1108};
1109
1110/**
1111 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1112 * @adapter: pointer to adapter
1113 * @eitr: eitr setting (ints per sec) to give last timeslice
1114 * @itr_setting: current throttle rate in ints/second
1115 * @packets: the number of packets during this measurement interval
1116 * @bytes: the number of bytes during this measurement interval
1117 *
1118 * Stores a new ITR value based on packets and byte
1119 * counts during the last interrupt. The advantage of per interrupt
1120 * computation is faster updates and more accurate ITR for the current
1121 * traffic pattern. Constants in this function were computed
1122 * based on theoretical maximum wire speed and thresholds were set based
1123 * on testing data as well as attempting to minimize response time
1124 * while increasing bulk throughput.
1125 * this functionality is controlled by the InterruptThrottleRate module
1126 * parameter (see ixgbe_param.c)
1127 **/
1128static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 1129 u32 eitr, u8 itr_setting,
1130 int packets, int bytes)
f494e8fa
AV		 1131{
1132 unsigned int retval = itr_setting;
1133 u32 timepassed_us;
1134 u64 bytes_perint;
1135
1136 if (packets == 0)
1137 goto update_itr_done;
1138
1139
1140 /* simple throttlerate management
1141 * 0-20MB/s lowest (100000 ints/s)
1142 * 20-100MB/s low (20000 ints/s)
1143 * 100-1249MB/s bulk (8000 ints/s)
1144 */
1145 /* what was last interrupt timeslice? */
1146 timepassed_us = 1000000/eitr;
1147 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1148
1149 switch (itr_setting) {
1150 case lowest_latency:
1151 if (bytes_perint > adapter->eitr_low)
1152 retval = low_latency;
1153 break;
1154 case low_latency:
1155 if (bytes_perint > adapter->eitr_high)
1156 retval = bulk_latency;
1157 else if (bytes_perint <= adapter->eitr_low)
1158 retval = lowest_latency;
1159 break;
1160 case bulk_latency:
1161 if (bytes_perint <= adapter->eitr_high)
1162 retval = low_latency;
1163 break;
1164 }
1165
1166update_itr_done:
1167 return retval;
1168}
1169
509ee935
JB		 1170/**
1171 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1172 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1173 *
1174 * This function is made to be called by ethtool and by the driver
1175 * when it needs to update EITR registers at runtime. Hardware
1176 * specific quirks/differences are taken care of here.
1177 */
fe49f04a 1178void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1179{
fe49f04a 1180 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1181 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1182 int v_idx = q_vector->v_idx;
1183 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1184
509ee935
JB		 1185 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1186 /* must write high and low 16 bits to reset counter */
1187 itr_reg |= (itr_reg << 16);
1188 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1189 /*
1190 * set the WDIS bit to not clear the timer bits and cause an
1191 * immediate assertion of the interrupt
1192 */
1193 itr_reg |= IXGBE_EITR_CNT_WDIS;
1194 }
1195 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1196}
1197
f494e8fa
AV		 1198static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1199{
1200 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1201 u32 new_itr;
1202 u8 current_itr, ret_itr;
fe49f04a 1203 int i, r_idx;
f494e8fa
AV		 1204 struct ixgbe_ring *rx_ring, *tx_ring;
1205
1206 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1207 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1208 tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1209 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1210 q_vector->tx_itr,
1211 tx_ring->total_packets,
1212 tx_ring->total_bytes);
f494e8fa
AV		 1213 /* if the result for this queue would decrease interrupt
1214 * rate for this vector then use that result */
30efa5a3 1215 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1216 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1217 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1218 r_idx + 1);
f494e8fa
AV		 1219 }
1220
1221 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1222 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1223 rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1224 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1225 q_vector->rx_itr,
1226 rx_ring->total_packets,
1227 rx_ring->total_bytes);
f494e8fa
AV		 1228 /* if the result for this queue would decrease interrupt
1229 * rate for this vector then use that result */
30efa5a3 1230 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1231 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1232 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1233 r_idx + 1);
f494e8fa
AV		 1234 }
1235
30efa5a3 1236 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1237
1238 switch (current_itr) {
1239 /* counts and packets in update_itr are dependent on these numbers */
1240 case lowest_latency:
1241 new_itr = 100000;
1242 break;
1243 case low_latency:
1244 new_itr = 20000; /* aka hwitr = ~200 */
1245 break;
1246 case bulk_latency:
1247 default:
1248 new_itr = 8000;
1249 break;
1250 }
1251
1252 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1253 /* do an exponential smoothing */
1254 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1255
1256 /* save the algorithm value here, not the smoothed one */
1257 q_vector->eitr = new_itr;
fe49f04a
AD		 1258
1259 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1260 }
1261
1262 return;
1263}
1264
0befdb3e
JB		 1265static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1266{
1267 struct ixgbe_hw *hw = &adapter->hw;
1268
1269 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1270 (eicr & IXGBE_EICR_GPI_SDP1)) {
1271 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1272 /* write to clear the interrupt */
1273 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1274 }
1275}
cf8280ee 1276
e8e26350
PW		 1277static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1278{
1279 struct ixgbe_hw *hw = &adapter->hw;
1280
1281 if (eicr & IXGBE_EICR_GPI_SDP1) {
1282 /* Clear the interrupt */
1283 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1284 schedule_work(&adapter->multispeed_fiber_task);
1285 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1286 /* Clear the interrupt */
1287 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1288 schedule_work(&adapter->sfp_config_module_task);
1289 } else {
1290 /* Interrupt isn't for us... */
1291 return;
1292 }
1293}
1294
cf8280ee
JB		 1295static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1296{
1297 struct ixgbe_hw *hw = &adapter->hw;
1298
1299 adapter->lsc_int++;
1300 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1301 adapter->link_check_timeout = jiffies;
1302 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1303 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1304 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1305 schedule_work(&adapter->watchdog_task);
1306 }
1307}
1308
9a799d71
AK		 1309static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1310{
1311 struct net_device *netdev = data;
1312 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1313 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1314 u32 eicr;
1315
1316 /*
1317 * Workaround for Silicon errata. Use clear-by-write instead
1318 * of clear-by-read. Reading with EICS will return the
1319 * interrupt causes without clearing, which later be done
1320 * with the write to EICR.
1321 */
1322 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1323 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1324
cf8280ee
JB		 1325 if (eicr & IXGBE_EICR_LSC)
1326 ixgbe_check_lsc(adapter);
d4f80882 1327
1cdd1ec8
GR		 1328 if (eicr & IXGBE_EICR_MAILBOX)
1329 ixgbe_msg_task(adapter);
1330
e8e26350
PW		 1331 if (hw->mac.type == ixgbe_mac_82598EB)
1332 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1333
c4cf55e5 1334 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1335 ixgbe_check_sfp_event(adapter, eicr);
c4cf55e5
PWJ		 1336
1337 /* Handle Flow Director Full threshold interrupt */
1338 if (eicr & IXGBE_EICR_FLOW_DIR) {
1339 int i;
1340 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1341 /* Disable transmits before FDIR Re-initialization */
1342 netif_tx_stop_all_queues(netdev);
1343 for (i = 0; i < adapter->num_tx_queues; i++) {
1344 struct ixgbe_ring *tx_ring =
4a0b9ca0 1345 adapter->tx_ring[i];
c4cf55e5
PWJ		 1346 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1347 &tx_ring->reinit_state))
1348 schedule_work(&adapter->fdir_reinit_task);
1349 }
1350 }
1351 }
d4f80882
AV		 1352 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1353 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1354
1355 return IRQ_HANDLED;
1356}
1357
fe49f04a
AD		 1358static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1359 u64 qmask)
1360{
1361 u32 mask;
1362
1363 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1364 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1365 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1366 } else {
1367 mask = (qmask & 0xFFFFFFFF);
1368 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1369 mask = (qmask >> 32);
1370 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1371 }
1372 /* skip the flush */
1373}
1374
1375static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1376 u64 qmask)
1377{
1378 u32 mask;
1379
1380 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1381 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1382 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1383 } else {
1384 mask = (qmask & 0xFFFFFFFF);
1385 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1386 mask = (qmask >> 32);
1387 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1388 }
1389 /* skip the flush */
1390}
1391
9a799d71
AK		 1392static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1393{
021230d4
AV		 1394 struct ixgbe_q_vector *q_vector = data;
1395 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1396 struct ixgbe_ring *tx_ring;
021230d4
AV		 1397 int i, r_idx;
1398
1399 if (!q_vector->txr_count)
1400 return IRQ_HANDLED;
1401
1402 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1403 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1404 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 1405 tx_ring->total_bytes = 0;
1406 tx_ring->total_packets = 0;
021230d4 1407 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1408 r_idx + 1);
021230d4 1409 }
9a799d71 1410
9b471446 1411 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 1412 napi_schedule(&q_vector->napi);
1413
9a799d71
AK		 1414 return IRQ_HANDLED;
1415}
1416
021230d4
AV		 1417/**
1418 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1419 * @irq: unused
1420 * @data: pointer to our q_vector struct for this interrupt vector
1421 **/
9a799d71
AK		 1422static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1423{
021230d4
AV		 1424 struct ixgbe_q_vector *q_vector = data;
1425 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1426 struct ixgbe_ring *rx_ring;
021230d4 1427 int r_idx;
30efa5a3 1428 int i;
021230d4
AV		 1429
1430 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3 1431 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1432 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 1433 rx_ring->total_bytes = 0;
1434 rx_ring->total_packets = 0;
1435 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1436 r_idx + 1);
1437 }
1438
021230d4
AV		 1439 if (!q_vector->rxr_count)
1440 return IRQ_HANDLED;
1441
021230d4 1442 /* disable interrupts on this vector only */
9b471446 1443 /* EIAM disabled interrupts (on this vector) for us */
288379f0 1444 napi_schedule(&q_vector->napi);
021230d4
AV		 1445
1446 return IRQ_HANDLED;
1447}
1448
1449static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1450{
91281fd3
AD		 1451 struct ixgbe_q_vector *q_vector = data;
1452 struct ixgbe_adapter *adapter = q_vector->adapter;
1453 struct ixgbe_ring *ring;
1454 int r_idx;
1455 int i;
1456
1457 if (!q_vector->txr_count && !q_vector->rxr_count)
1458 return IRQ_HANDLED;
1459
1460 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1461 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1462 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1463 ring->total_bytes = 0;
1464 ring->total_packets = 0;
1465 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1466 r_idx + 1);
1467 }
1468
1469 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1470 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1471 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 1472 ring->total_bytes = 0;
1473 ring->total_packets = 0;
1474 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1475 r_idx + 1);
1476 }
1477
9b471446 1478 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1479 napi_schedule(&q_vector->napi);
9a799d71 1480
9a799d71
AK		 1481 return IRQ_HANDLED;
1482}
1483
021230d4
AV		 1484/**
1485 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1486 * @napi: napi struct with our devices info in it
1487 * @budget: amount of work driver is allowed to do this pass, in packets
1488 *
f0848276
JB		 1489 * This function is optimized for cleaning one queue only on a single
1490 * q_vector!!!
021230d4 1491 **/
9a799d71
AK		 1492static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1493{
021230d4 1494 struct ixgbe_q_vector *q_vector =
b4617240 1495 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1496 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1497 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1498 int work_done = 0;
021230d4 1499 long r_idx;
9a799d71 1500
021230d4 1501 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1502 rx_ring = adapter->rx_ring[r_idx];
5dd2d332 1503#ifdef CONFIG_IXGBE_DCA
bd0362dd 1504 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1505 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1506#endif
9a799d71 1507
78b6f4ce 1508 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1509
021230d4
AV		 1510 /* If all Rx work done, exit the polling mode */
1511 if (work_done < budget) {
288379f0 1512 napi_complete(napi);
f7554a2b 1513 if (adapter->rx_itr_setting & 1)
f494e8fa 1514 ixgbe_set_itr_msix(q_vector);
9a799d71 1515 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1516 ixgbe_irq_enable_queues(adapter,
1517 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1518 }
1519
1520 return work_done;
1521}
1522
f0848276 1523/**
91281fd3 1524 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1525 * @napi: napi struct with our devices info in it
1526 * @budget: amount of work driver is allowed to do this pass, in packets
1527 *
1528 * This function will clean more than one rx queue associated with a
1529 * q_vector.
1530 **/
91281fd3 1531static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1532{
1533 struct ixgbe_q_vector *q_vector =
1534 container_of(napi, struct ixgbe_q_vector, napi);
1535 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1536 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1537 int work_done = 0, i;
1538 long r_idx;
91281fd3
AD		 1539 bool tx_clean_complete = true;
1540
1541 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1542 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1543 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1544#ifdef CONFIG_IXGBE_DCA
1545 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1546 ixgbe_update_tx_dca(adapter, ring);
1547#endif
1548 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1549 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1550 r_idx + 1);
1551 }
f0848276
JB		 1552
1553 /* attempt to distribute budget to each queue fairly, but don't allow
1554 * the budget to go below 1 because we'll exit polling */
1555 budget /= (q_vector->rxr_count ?: 1);
1556 budget = max(budget, 1);
1557 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1558 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1559 ring = adapter->rx_ring[r_idx];
5dd2d332 1560#ifdef CONFIG_IXGBE_DCA
f0848276 1561 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1562 ixgbe_update_rx_dca(adapter, ring);
f0848276 1563#endif
91281fd3 1564 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276
JB		 1565 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1566 r_idx + 1);
1567 }
1568
1569 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1570 ring = adapter->rx_ring[r_idx];
f0848276 1571 /* If all Rx work done, exit the polling mode */
7f821875 1572 if (work_done < budget) {
288379f0 1573 napi_complete(napi);
f7554a2b 1574 if (adapter->rx_itr_setting & 1)
f0848276
JB		 1575 ixgbe_set_itr_msix(q_vector);
1576 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1577 ixgbe_irq_enable_queues(adapter,
1578 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1579 return 0;
1580 }
1581
1582 return work_done;
1583}
91281fd3
AD		 1584
1585/**
1586 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1587 * @napi: napi struct with our devices info in it
1588 * @budget: amount of work driver is allowed to do this pass, in packets
1589 *
1590 * This function is optimized for cleaning one queue only on a single
1591 * q_vector!!!
1592 **/
1593static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1594{
1595 struct ixgbe_q_vector *q_vector =
1596 container_of(napi, struct ixgbe_q_vector, napi);
1597 struct ixgbe_adapter *adapter = q_vector->adapter;
1598 struct ixgbe_ring *tx_ring = NULL;
1599 int work_done = 0;
1600 long r_idx;
1601
1602 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
4a0b9ca0 1603 tx_ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1604#ifdef CONFIG_IXGBE_DCA
1605 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1606 ixgbe_update_tx_dca(adapter, tx_ring);
1607#endif
1608
1609 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1610 work_done = budget;
1611
f7554a2b 1612 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 1613 if (work_done < budget) {
1614 napi_complete(napi);
f7554a2b 1615 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 1616 ixgbe_set_itr_msix(q_vector);
1617 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1618 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1619 }
1620
1621 return work_done;
1622}
1623
021230d4 1624static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1625 int r_idx)
021230d4 1626{
7a921c93
AD		 1627 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1628
1629 set_bit(r_idx, q_vector->rxr_idx);
1630 q_vector->rxr_count++;
021230d4
AV		 1631}
1632
1633static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 1634 int t_idx)
021230d4 1635{
7a921c93
AD		 1636 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1637
1638 set_bit(t_idx, q_vector->txr_idx);
1639 q_vector->txr_count++;
021230d4
AV		 1640}
1641
9a799d71 1642/**
021230d4
AV		 1643 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1644 * @adapter: board private structure to initialize
1645 * @vectors: allotted vector count for descriptor rings
9a799d71 1646 *
021230d4
AV		 1647 * This function maps descriptor rings to the queue-specific vectors
1648 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1649 * one vector per ring/queue, but on a constrained vector budget, we
1650 * group the rings as "efficiently" as possible. You would add new
1651 * mapping configurations in here.
9a799d71 1652 **/
021230d4 1653static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1654 int vectors)
021230d4
AV		 1655{
1656 int v_start = 0;
1657 int rxr_idx = 0, txr_idx = 0;
1658 int rxr_remaining = adapter->num_rx_queues;
1659 int txr_remaining = adapter->num_tx_queues;
1660 int i, j;
1661 int rqpv, tqpv;
1662 int err = 0;
1663
1664 /* No mapping required if MSI-X is disabled. */
1665 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1666 goto out;
9a799d71 1667
021230d4
AV		 1668 /*
1669 * The ideal configuration...
1670 * We have enough vectors to map one per queue.
1671 */
1672 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1673 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1674 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1675
021230d4
AV		 1676 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1677 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1678
9a799d71 1679 goto out;
021230d4 1680 }
9a799d71 1681
021230d4
AV		 1682 /*
1683 * If we don't have enough vectors for a 1-to-1
1684 * mapping, we'll have to group them so there are
1685 * multiple queues per vector.
1686 */
1687 /* Re-adjusting *qpv takes care of the remainder. */
1688 for (i = v_start; i < vectors; i++) {
1689 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1690 for (j = 0; j < rqpv; j++) {
1691 map_vector_to_rxq(adapter, i, rxr_idx);
1692 rxr_idx++;
1693 rxr_remaining--;
1694 }
1695 }
1696 for (i = v_start; i < vectors; i++) {
1697 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1698 for (j = 0; j < tqpv; j++) {
1699 map_vector_to_txq(adapter, i, txr_idx);
1700 txr_idx++;
1701 txr_remaining--;
9a799d71 1702 }
9a799d71
AK		 1703 }
1704
021230d4
AV		 1705out:
1706 return err;
1707}
1708
1709/**
1710 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1711 * @adapter: board private structure
1712 *
1713 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1714 * interrupts from the kernel.
1715 **/
1716static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1717{
1718 struct net_device *netdev = adapter->netdev;
1719 irqreturn_t (*handler)(int, void *);
1720 int i, vector, q_vectors, err;
cb13fc20 1721 int ri=0, ti=0;
021230d4
AV		 1722
1723 /* Decrement for Other and TCP Timer vectors */
1724 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1725
1726 /* Map the Tx/Rx rings to the vectors we were allotted. */
1727 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1728 if (err)
1729 goto out;
1730
1731#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1732 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1733 &ixgbe_msix_clean_many)
021230d4 1734 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 1735 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 1736
1737 if(handler == &ixgbe_msix_clean_rx) {
1738 sprintf(adapter->name[vector], "%s-%s-%d",
1739 netdev->name, "rx", ri++);
1740 }
1741 else if(handler == &ixgbe_msix_clean_tx) {
1742 sprintf(adapter->name[vector], "%s-%s-%d",
1743 netdev->name, "tx", ti++);
1744 }
1745 else
1746 sprintf(adapter->name[vector], "%s-%s-%d",
1747 netdev->name, "TxRx", vector);
1748
021230d4 1749 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1750 handler, 0, adapter->name[vector],
7a921c93 1751 adapter->q_vector[vector]);
9a799d71
AK		 1752 if (err) {
1753 DPRINTK(PROBE, ERR,
b4617240
PW		 1754 "request_irq failed for MSIX interrupt "
1755 "Error: %d\n", err);
021230d4 1756 goto free_queue_irqs;
9a799d71 1757 }
9a799d71
AK		 1758 }
1759
021230d4
AV		 1760 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1761 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1762 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1763 if (err) {
1764 DPRINTK(PROBE, ERR,
1765 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1766 goto free_queue_irqs;
9a799d71
AK		 1767 }
1768
9a799d71
AK		 1769 return 0;
1770
021230d4
AV		 1771free_queue_irqs:
1772 for (i = vector - 1; i >= 0; i--)
1773 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 1774 adapter->q_vector[i]);
021230d4
AV		 1775 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1776 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1777 kfree(adapter->msix_entries);
1778 adapter->msix_entries = NULL;
021230d4 1779out:
9a799d71
AK		 1780 return err;
1781}
1782
f494e8fa
AV		 1783static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1784{
7a921c93 1785 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 1786 u8 current_itr;
1787 u32 new_itr = q_vector->eitr;
4a0b9ca0
PW		 1788 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
1789 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
f494e8fa 1790
30efa5a3 1791 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1792 q_vector->tx_itr,
1793 tx_ring->total_packets,
1794 tx_ring->total_bytes);
30efa5a3 1795 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1796 q_vector->rx_itr,
1797 rx_ring->total_packets,
1798 rx_ring->total_bytes);
f494e8fa 1799
30efa5a3 1800 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1801
1802 switch (current_itr) {
1803 /* counts and packets in update_itr are dependent on these numbers */
1804 case lowest_latency:
1805 new_itr = 100000;
1806 break;
1807 case low_latency:
1808 new_itr = 20000; /* aka hwitr = ~200 */
1809 break;
1810 case bulk_latency:
1811 new_itr = 8000;
1812 break;
1813 default:
1814 break;
1815 }
1816
1817 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1818 /* do an exponential smoothing */
1819 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1820
1821 /* save the algorithm value here, not the smoothed one */
1822 q_vector->eitr = new_itr;
fe49f04a
AD		 1823
1824 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1825 }
1826
1827 return;
1828}
1829
79aefa45
AD		 1830/**
1831 * ixgbe_irq_enable - Enable default interrupt generation settings
1832 * @adapter: board private structure
1833 **/
1834static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1835{
1836 u32 mask;
835462fc
NS		 1837
1838 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 1839 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1840 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1841 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1842 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1843 mask |= IXGBE_EIMS_GPI_SDP1;
1844 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 1845 if (adapter->num_vfs)
1846 mask |= IXGBE_EIMS_MAILBOX;
e8e26350 1847 }
c4cf55e5
PWJ		 1848 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1849 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1850 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 1851
79aefa45 1852 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 1853 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45 1854 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 1855
1856 if (adapter->num_vfs > 32) {
1857 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1858 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1859 }
79aefa45 1860}
021230d4 1861
9a799d71 1862/**
021230d4 1863 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1864 * @irq: interrupt number
1865 * @data: pointer to a network interface device structure
9a799d71
AK		 1866 **/
1867static irqreturn_t ixgbe_intr(int irq, void *data)
1868{
1869 struct net_device *netdev = data;
1870 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1871 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 1872 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 1873 u32 eicr;
1874
54037505
DS		 1875 /*
1876 * Workaround for silicon errata. Mask the interrupts
1877 * before the read of EICR.
1878 */
1879 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1880
021230d4
AV		 1881 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1882 * therefore no explict interrupt disable is necessary */
1883 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1884 if (!eicr) {
1885 /* shared interrupt alert!
1886 * make sure interrupts are enabled because the read will
1887 * have disabled interrupts due to EIAM */
1888 ixgbe_irq_enable(adapter);
9a799d71 1889 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1890 }
9a799d71 1891
cf8280ee
JB		 1892 if (eicr & IXGBE_EICR_LSC)
1893 ixgbe_check_lsc(adapter);
021230d4 1894
e8e26350
PW		 1895 if (hw->mac.type == ixgbe_mac_82599EB)
1896 ixgbe_check_sfp_event(adapter, eicr);
1897
0befdb3e
JB		 1898 ixgbe_check_fan_failure(adapter, eicr);
1899
7a921c93 1900 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 1901 adapter->tx_ring[0]->total_packets = 0;
1902 adapter->tx_ring[0]->total_bytes = 0;
1903 adapter->rx_ring[0]->total_packets = 0;
1904 adapter->rx_ring[0]->total_bytes = 0;
021230d4 1905 /* would disable interrupts here but EIAM disabled it */
7a921c93 1906 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 1907 }
1908
1909 return IRQ_HANDLED;
1910}
1911
021230d4
AV		 1912static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1913{
1914 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1915
1916 for (i = 0; i < q_vectors; i++) {
7a921c93 1917 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 1918 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1919 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1920 q_vector->rxr_count = 0;
1921 q_vector->txr_count = 0;
1922 }
1923}
1924
9a799d71
AK		 1925/**
1926 * ixgbe_request_irq - initialize interrupts
1927 * @adapter: board private structure
1928 *
1929 * Attempts to configure interrupts using the best available
1930 * capabilities of the hardware and kernel.
1931 **/
021230d4 1932static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1933{
1934 struct net_device *netdev = adapter->netdev;
021230d4 1935 int err;
9a799d71 1936
021230d4
AV		 1937 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1938 err = ixgbe_request_msix_irqs(adapter);
1939 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 1940 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
b4617240 1941 netdev->name, netdev);
021230d4 1942 } else {
a0607fd3 1943 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
b4617240 1944 netdev->name, netdev);
9a799d71
AK		 1945 }
1946
9a799d71
AK		 1947 if (err)
1948 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1949
9a799d71
AK		 1950 return err;
1951}
1952
1953static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1954{
1955 struct net_device *netdev = adapter->netdev;
1956
1957 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1958 int i, q_vectors;
9a799d71 1959
021230d4
AV		 1960 q_vectors = adapter->num_msix_vectors;
1961
1962 i = q_vectors - 1;
9a799d71 1963 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1964
021230d4
AV		 1965 i--;
1966 for (; i >= 0; i--) {
1967 free_irq(adapter->msix_entries[i].vector,
7a921c93 1968 adapter->q_vector[i]);
021230d4
AV		 1969 }
1970
1971 ixgbe_reset_q_vectors(adapter);
1972 } else {
1973 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1974 }
1975}
1976
22d5a71b
JB		 1977/**
1978 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1979 * @adapter: board private structure
1980 **/
1981static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1982{
835462fc
NS		 1983 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1984 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1985 } else {
1986 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1987 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 1988 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 1989 if (adapter->num_vfs > 32)
1990 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
22d5a71b
JB		 1991 }
1992 IXGBE_WRITE_FLUSH(&adapter->hw);
1993 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1994 int i;
1995 for (i = 0; i < adapter->num_msix_vectors; i++)
1996 synchronize_irq(adapter->msix_entries[i].vector);
1997 } else {
1998 synchronize_irq(adapter->pdev->irq);
1999 }
2000}
2001
9a799d71
AK		 2002/**
2003 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2004 *
2005 **/
2006static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2007{
9a799d71
AK		 2008 struct ixgbe_hw *hw = &adapter->hw;
2009
021230d4 2010 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
f7554a2b 2011 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2012
e8e26350
PW		 2013 ixgbe_set_ivar(adapter, 0, 0, 0);
2014 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2015
2016 map_vector_to_rxq(adapter, 0, 0);
2017 map_vector_to_txq(adapter, 0, 0);
2018
2019 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2020}
2021
2022/**
3a581073 2023 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2024 * @adapter: board private structure
2025 *
2026 * Configure the Tx unit of the MAC after a reset.
2027 **/
2028static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2029{
12207e49 2030 u64 tdba;
9a799d71 2031 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2032 u32 i, j, tdlen, txctrl;
9a799d71
AK		 2033
2034 /* Setup the HW Tx Head and Tail descriptor pointers */
2035 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2036 struct ixgbe_ring *ring = adapter->tx_ring[i];
e01c31a5
JB		 2037 j = ring->reg_idx;
2038 tdba = ring->dma;
2039 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 2040 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 2041 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 2042 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
2043 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
2044 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
2045 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
4a0b9ca0
PW		 2046 adapter->tx_ring[i]->head = IXGBE_TDH(j);
2047 adapter->tx_ring[i]->tail = IXGBE_TDT(j);
84f62d4b
PWJ		 2048 /*
2049 * Disable Tx Head Writeback RO bit, since this hoses
021230d4
AV		 2050 * bookkeeping if things aren't delivered in order.
2051 */
84f62d4b
PWJ		 2052 switch (hw->mac.type) {
2053 case ixgbe_mac_82598EB:
2054 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
2055 break;
2056 case ixgbe_mac_82599EB:
2057 default:
2058 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
2059 break;
2060 }
021230d4 2061 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
84f62d4b
PWJ		 2062 switch (hw->mac.type) {
2063 case ixgbe_mac_82598EB:
2064 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
2065 break;
2066 case ixgbe_mac_82599EB:
2067 default:
2068 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
2069 break;
2070 }
9a799d71 2071 }
ee5f784a 2072
e8e26350 2073 if (hw->mac.type == ixgbe_mac_82599EB) {
ee5f784a 2074 u32 rttdcs;
1cdd1ec8 2075 u32 mask;
ee5f784a
DS		 2076
2077 /* disable the arbiter while setting MTQC */
2078 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2079 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2080 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2081
1cdd1ec8
GR		 2082 /* set transmit pool layout */
2083 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2084 switch (adapter->flags & mask) {
2085
2086 case (IXGBE_FLAG_SRIOV_ENABLED):
2087 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2088 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2089 break;
2090
2091 case (IXGBE_FLAG_DCB_ENABLED):
2092 /* We enable 8 traffic classes, DCB only */
2093 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2094 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2095 break;
2096
2097 default:
ee5f784a 2098 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
1cdd1ec8
GR		 2099 break;
2100 }
ee5f784a
DS		 2101
2102 /* re-eable the arbiter */
2103 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2104 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
e8e26350 2105 }
9a799d71
AK		 2106}
2107
e8e26350 2108#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2109
a6616b42
YZ		 2110static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2111 struct ixgbe_ring *rx_ring)
cc41ac7c 2112{
cc41ac7c 2113 u32 srrctl;
a6616b42 2114 int index;
0cefafad 2115 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 2116
a6616b42
YZ		 2117 index = rx_ring->reg_idx;
2118 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2119 unsigned long mask;
0cefafad 2120 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 2121 index = index & mask;
cc41ac7c 2122 }
cc41ac7c
JB		 2123 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2124
2125 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2126 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2127
afafd5b0
AD		 2128 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2129 IXGBE_SRRCTL_BSIZEHDR_MASK;
2130
6e455b89 2131 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 2132#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2133 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2134#else
2135 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2136#endif
cc41ac7c 2137 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2138 } else {
afafd5b0
AD		 2139 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2140 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2141 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2142 }
e8e26350 2143
cc41ac7c
JB		 2144 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2145}
9a799d71 2146
0cefafad
JB		 2147static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2148{
2149 u32 mrqc = 0;
2150 int mask;
2151
2152 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2153 return mrqc;
2154
2155 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2156#ifdef CONFIG_IXGBE_DCB
2157 | IXGBE_FLAG_DCB_ENABLED
2158#endif
1cdd1ec8 2159 | IXGBE_FLAG_SRIOV_ENABLED
0cefafad
JB		 2160 );
2161
2162 switch (mask) {
2163 case (IXGBE_FLAG_RSS_ENABLED):
2164 mrqc = IXGBE_MRQC_RSSEN;
2165 break;
1cdd1ec8
GR		 2166 case (IXGBE_FLAG_SRIOV_ENABLED):
2167 mrqc = IXGBE_MRQC_VMDQEN;
2168 break;
0cefafad
JB		 2169#ifdef CONFIG_IXGBE_DCB
2170 case (IXGBE_FLAG_DCB_ENABLED):
2171 mrqc = IXGBE_MRQC_RT8TCEN;
2172 break;
2173#endif /* CONFIG_IXGBE_DCB */
2174 default:
2175 break;
2176 }
2177
2178 return mrqc;
2179}
2180
bb5a9ad2
NS		 2181/**
2182 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2183 * @adapter: address of board private structure
2184 * @index: index of ring to set
bb5a9ad2 2185 **/
edd2ea55 2186static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
bb5a9ad2
NS		 2187{
2188 struct ixgbe_ring *rx_ring;
2189 struct ixgbe_hw *hw = &adapter->hw;
2190 int j;
2191 u32 rscctrl;
edd2ea55 2192 int rx_buf_len;
bb5a9ad2 2193
4a0b9ca0 2194 rx_ring = adapter->rx_ring[index];
bb5a9ad2 2195 j = rx_ring->reg_idx;
edd2ea55 2196 rx_buf_len = rx_ring->rx_buf_len;
bb5a9ad2
NS		 2197 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2198 rscctrl |= IXGBE_RSCCTL_RSCEN;
2199 /*
2200 * we must limit the number of descriptors so that the
2201 * total size of max desc * buf_len is not greater
2202 * than 65535
2203 */
2204 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2205#if (MAX_SKB_FRAGS > 16)
2206 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2207#elif (MAX_SKB_FRAGS > 8)
2208 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2209#elif (MAX_SKB_FRAGS > 4)
2210 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2211#else
2212 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2213#endif
2214 } else {
2215 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2216 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2217 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2218 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2219 else
2220 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2221 }
2222 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2223}
2224
9a799d71 2225/**
3a581073 2226 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 2227 * @adapter: board private structure
2228 *
2229 * Configure the Rx unit of the MAC after a reset.
2230 **/
2231static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2232{
2233 u64 rdba;
2234 struct ixgbe_hw *hw = &adapter->hw;
a6616b42 2235 struct ixgbe_ring *rx_ring;
9a799d71
AK		 2236 struct net_device *netdev = adapter->netdev;
2237 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2238 int i, j;
9a799d71 2239 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 2240 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2241 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2242 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 2243 u32 fctrl, hlreg0;
509ee935 2244 u32 reta = 0, mrqc = 0;
cc41ac7c 2245 u32 rdrxctl;
7c6e0a43 2246 int rx_buf_len;
9a799d71
AK		 2247
2248 /* Decide whether to use packet split mode or not */
1cdd1ec8
GR		 2249 /* Do not use packet split if we're in SR-IOV Mode */
2250 if (!adapter->num_vfs)
2251 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 2252
2253 /* Set the RX buffer length according to the mode */
2254 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2255 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 2256 if (hw->mac.type == ixgbe_mac_82599EB) {
2257 /* PSRTYPE must be initialized in 82599 */
2258 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2259 IXGBE_PSRTYPE_UDPHDR |
2260 IXGBE_PSRTYPE_IPV4HDR |
dfa12f05
YZ		 2261 IXGBE_PSRTYPE_IPV6HDR |
2262 IXGBE_PSRTYPE_L2HDR;
1cdd1ec8
GR		 2263 IXGBE_WRITE_REG(hw,
2264 IXGBE_PSRTYPE(adapter->num_vfs),
2265 psrtype);
e8e26350 2266 }
9a799d71 2267 } else {
0c19d6af 2268 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2269 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2270 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2271 else
7c6e0a43 2272 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 2273 }
2274
2275 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2276 fctrl |= IXGBE_FCTRL_BAM;
021230d4 2277 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 2278 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 2279 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2280
2281 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2282 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2283 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2284 else
2285 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
63f39bd1 2286#ifdef IXGBE_FCOE
f34c5c82 2287 if (netdev->features & NETIF_F_FCOE_MTU)
63f39bd1
YZ		 2288 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2289#endif
9a799d71
AK		 2290 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2291
4a0b9ca0 2292 rdlen = adapter->rx_ring[0]->count * sizeof(union ixgbe_adv_rx_desc);
9a799d71
AK		 2293 /* disable receives while setting up the descriptors */
2294 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2295 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2296
0cefafad
JB		 2297 /*
2298 * Setup the HW Rx Head and Tail Descriptor Pointers and
2299 * the Base and Length of the Rx Descriptor Ring
2300 */
9a799d71 2301 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2302 rx_ring = adapter->rx_ring[i];
a6616b42
YZ		 2303 rdba = rx_ring->dma;
2304 j = rx_ring->reg_idx;
284901a9 2305 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 2306 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2307 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2308 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2309 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
a6616b42
YZ		 2310 rx_ring->head = IXGBE_RDH(j);
2311 rx_ring->tail = IXGBE_RDT(j);
2312 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2313
6e455b89
YZ		 2314 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2315 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
1b3ff02e
PWJ		 2316 else
2317 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2318
63f39bd1 2319#ifdef IXGBE_FCOE
f34c5c82 2320 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2321 struct ixgbe_ring_feature *f;
2322 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2323 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2324 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2325 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2326 rx_ring->rx_buf_len =
2327 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2328 }
63f39bd1
YZ		 2329 }
2330
2331#endif /* IXGBE_FCOE */
a6616b42 2332 ixgbe_configure_srrctl(adapter, rx_ring);
9a799d71
AK		 2333 }
2334
e8e26350
PW		 2335 if (hw->mac.type == ixgbe_mac_82598EB) {
2336 /*
2337 * For VMDq support of different descriptor types or
2338 * buffer sizes through the use of multiple SRRCTL
2339 * registers, RDRXCTL.MVMEN must be set to 1
2340 *
2341 * also, the manual doesn't mention it clearly but DCA hints
2342 * will only use queue 0's tags unless this bit is set. Side
2343 * effects of setting this bit are only that SRRCTL must be
2344 * fully programmed [0..15]
2345 */
2a41ff81
JB		 2346 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2347 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2348 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 2349 }
177db6ff 2350
1cdd1ec8
GR		 2351 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2352 u32 vt_reg_bits;
2353 u32 reg_offset, vf_shift;
2354 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2355 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2356 | IXGBE_VT_CTL_REPLEN;
2357 vt_reg_bits |= (adapter->num_vfs <<
2358 IXGBE_VT_CTL_POOL_SHIFT);
2359 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2360 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2361
2362 vf_shift = adapter->num_vfs % 32;
2363 reg_offset = adapter->num_vfs / 32;
2364 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2365 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2366 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2367 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2368 /* Enable only the PF's pool for Tx/Rx */
2369 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2370 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2371 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2372 ixgbe_set_vmolr(hw, adapter->num_vfs);
2373 }
2374
e8e26350 2375 /* Program MRQC for the distribution of queues */
0cefafad 2376 mrqc = ixgbe_setup_mrqc(adapter);
e8e26350 2377
021230d4 2378 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 2379 /* Fill out redirection table */
021230d4
AV		 2380 for (i = 0, j = 0; i < 128; i++, j++) {
2381 if (j == adapter->ring_feature[RING_F_RSS].indices)
2382 j = 0;
2383 /* reta = 4-byte sliding window of
2384 * 0x00..(indices-1)(indices-1)00..etc. */
2385 reta = (reta << 8) | (j * 0x11);
2386 if ((i & 3) == 3)
2387 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 2388 }
2389
2390 /* Fill out hash function seeds */
2391 for (i = 0; i < 10; i++)
7c6e0a43 2392 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 2393
2a41ff81
JB		 2394 if (hw->mac.type == ixgbe_mac_82598EB)
2395 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 2396 /* Perform hash on these packet types */
2a41ff81
JB		 2397 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2398 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2399 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2400 | IXGBE_MRQC_RSS_FIELD_IPV6
2401 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2402 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 2403 }
2a41ff81 2404 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 2405
1cdd1ec8
GR		 2406 if (adapter->num_vfs) {
2407 u32 reg;
2408
2409 /* Map PF MAC address in RAR Entry 0 to first pool
2410 * following VFs */
2411 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2412
2413 /* Set up VF register offsets for selected VT Mode, i.e.
2414 * 64 VFs for SR-IOV */
2415 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2416 reg |= IXGBE_GCR_EXT_SRIOV;
2417 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2418 }
2419
021230d4
AV		 2420 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2421
2422 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2423 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2424 /* Disable indicating checksum in descriptor, enables
2425 * RSS hash */
9a799d71 2426 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 2427 }
021230d4
AV		 2428 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2429 /* Enable IPv4 payload checksum for UDP fragments
2430 * if PCSD is not set */
2431 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2432 }
2433
2434 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 2435
2436 if (hw->mac.type == ixgbe_mac_82599EB) {
2437 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2438 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 2439 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 2440 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2441 }
f8212f97 2442
0c19d6af 2443 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 2444 /* Enable 82599 HW-RSC */
bb5a9ad2 2445 for (i = 0; i < adapter->num_rx_queues; i++)
edd2ea55 2446 ixgbe_configure_rscctl(adapter, i);
bb5a9ad2 2447
f8212f97
AD		 2448 /* Disable RSC for ACK packets */
2449 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2450 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2451 }
9a799d71
AK		 2452}
2453
068c89b0
DS		 2454static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2455{
2456 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2457 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2458 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2459
2460 /* add VID to filter table */
1ada1b1b 2461 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
068c89b0
DS		 2462}
2463
2464static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2465{
2466 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2467 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2468 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2469
2470 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2471 ixgbe_irq_disable(adapter);
2472
2473 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2474
2475 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2476 ixgbe_irq_enable(adapter);
2477
2478 /* remove VID from filter table */
1ada1b1b 2479 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
068c89b0
DS		 2480}
2481
9a799d71 2482static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2483 struct vlan_group *grp)
9a799d71
AK		 2484{
2485 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2486 u32 ctrl;
e8e26350 2487 int i, j;
9a799d71 2488
d4f80882
AV		 2489 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2490 ixgbe_irq_disable(adapter);
9a799d71
AK		 2491 adapter->vlgrp = grp;
2492
2f90b865
AD		 2493 /*
2494 * For a DCB driver, always enable VLAN tag stripping so we can
2495 * still receive traffic from a DCB-enabled host even if we're
2496 * not in DCB mode.
2497 */
2498 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
dc63d377
AD		 2499
2500 /* Disable CFI check */
2501 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2502
2503 /* enable VLAN tag stripping */
e8e26350 2504 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
dc63d377 2505 ctrl |= IXGBE_VLNCTRL_VME;
e8e26350 2506 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
e8e26350 2507 for (i = 0; i < adapter->num_rx_queues; i++) {
dc63d377 2508 u32 ctrl;
4a0b9ca0 2509 j = adapter->rx_ring[i]->reg_idx;
e8e26350
PW		 2510 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2511 ctrl |= IXGBE_RXDCTL_VME;
2512 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2513 }
9a799d71 2514 }
dc63d377
AD		 2515
2516 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2517
e8e26350 2518 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2519
d4f80882
AV		 2520 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2521 ixgbe_irq_enable(adapter);
9a799d71
AK		 2522}
2523
9a799d71
AK		 2524static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2525{
2526 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2527
2528 if (adapter->vlgrp) {
2529 u16 vid;
2530 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2531 if (!vlan_group_get_device(adapter->vlgrp, vid))
2532 continue;
2533 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2534 }
2535 }
2536}
2537
2c5645cf
CL		 2538static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2539{
2540 struct dev_mc_list *mc_ptr;
2541 u8 *addr = *mc_addr_ptr;
2542 *vmdq = 0;
2543
2544 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2545 if (mc_ptr->next)
2546 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2547 else
2548 *mc_addr_ptr = NULL;
2549
2550 return addr;
2551}
2552
9a799d71 2553/**
2c5645cf 2554 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2555 * @netdev: network interface device structure
2556 *
2c5645cf
CL		 2557 * The set_rx_method entry point is called whenever the unicast/multicast
2558 * address list or the network interface flags are updated. This routine is
2559 * responsible for configuring the hardware for proper unicast, multicast and
2560 * promiscuous mode.
9a799d71 2561 **/
7f870475 2562void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2563{
2564 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2565 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 2566 u32 fctrl, vlnctrl;
2c5645cf
CL		 2567 u8 *addr_list = NULL;
2568 int addr_count = 0;
9a799d71
AK		 2569
2570 /* Check for Promiscuous and All Multicast modes */
2571
2572 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 2573 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 2574
2575 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2576 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2577 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 2578 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 2579 } else {
746b9f02
PM		 2580 if (netdev->flags & IFF_ALLMULTI) {
2581 fctrl |= IXGBE_FCTRL_MPE;
2582 fctrl &= ~IXGBE_FCTRL_UPE;
2583 } else {
2584 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2585 }
3d01625a 2586 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 2587 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2588 }
2589
2590 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 2591 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 2592
2c5645cf 2593 /* reprogram secondary unicast list */
32e7bfc4 2594 hw->mac.ops.update_uc_addr_list(hw, netdev);
9a799d71 2595
2c5645cf 2596 /* reprogram multicast list */
4cd24eaf 2597 addr_count = netdev_mc_count(netdev);
2c5645cf
CL		 2598 if (addr_count)
2599 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 2600 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2601 ixgbe_addr_list_itr);
1cdd1ec8
GR		 2602 if (adapter->num_vfs)
2603 ixgbe_restore_vf_multicasts(adapter);
9a799d71
AK		 2604}
2605
021230d4
AV		 2606static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2607{
2608 int q_idx;
2609 struct ixgbe_q_vector *q_vector;
2610 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2611
2612 /* legacy and MSI only use one vector */
2613 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2614 q_vectors = 1;
2615
2616 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2617 struct napi_struct *napi;
7a921c93 2618 q_vector = adapter->q_vector[q_idx];
f0848276 2619 napi = &q_vector->napi;
91281fd3
AD		 2620 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2621 if (!q_vector->rxr_count || !q_vector->txr_count) {
2622 if (q_vector->txr_count == 1)
2623 napi->poll = &ixgbe_clean_txonly;
2624 else if (q_vector->rxr_count == 1)
2625 napi->poll = &ixgbe_clean_rxonly;
2626 }
2627 }
f0848276
JB		 2628
2629 napi_enable(napi);
021230d4
AV		 2630 }
2631}
2632
2633static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2634{
2635 int q_idx;
2636 struct ixgbe_q_vector *q_vector;
2637 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2638
2639 /* legacy and MSI only use one vector */
2640 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2641 q_vectors = 1;
2642
2643 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 2644 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2645 napi_disable(&q_vector->napi);
2646 }
2647}
2648
7a6b6f51 2649#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2650/*
2651 * ixgbe_configure_dcb - Configure DCB hardware
2652 * @adapter: ixgbe adapter struct
2653 *
2654 * This is called by the driver on open to configure the DCB hardware.
2655 * This is also called by the gennetlink interface when reconfiguring
2656 * the DCB state.
2657 */
2658static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2659{
2660 struct ixgbe_hw *hw = &adapter->hw;
2661 u32 txdctl, vlnctrl;
2662 int i, j;
2663
2664 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2665 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2666 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2667
2668 /* reconfigure the hardware */
2669 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2670
2671 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2672 j = adapter->tx_ring[i]->reg_idx;
2f90b865
AD		 2673 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2674 /* PThresh workaround for Tx hang with DFP enabled. */
2675 txdctl |= 32;
2676 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2677 }
2678 /* Enable VLAN tag insert/strip */
2679 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
e8e26350
PW		 2680 if (hw->mac.type == ixgbe_mac_82598EB) {
2681 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2682 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2683 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2684 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2685 vlnctrl |= IXGBE_VLNCTRL_VFE;
2686 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2687 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2688 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2689 j = adapter->rx_ring[i]->reg_idx;
e8e26350
PW		 2690 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2691 vlnctrl |= IXGBE_RXDCTL_VME;
2692 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2693 }
2694 }
2f90b865
AD		 2695 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2696}
2697
2698#endif
9a799d71
AK		 2699static void ixgbe_configure(struct ixgbe_adapter *adapter)
2700{
2701 struct net_device *netdev = adapter->netdev;
c4cf55e5 2702 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 2703 int i;
2704
2c5645cf 2705 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2706
2707 ixgbe_restore_vlan(adapter);
7a6b6f51 2708#ifdef CONFIG_IXGBE_DCB
2f90b865 2709 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
b352e40d
YZ		 2710 if (hw->mac.type == ixgbe_mac_82598EB)
2711 netif_set_gso_max_size(netdev, 32768);
2712 else
2713 netif_set_gso_max_size(netdev, 65536);
2f90b865
AD		 2714 ixgbe_configure_dcb(adapter);
2715 } else {
2716 netif_set_gso_max_size(netdev, 65536);
2717 }
2718#else
2719 netif_set_gso_max_size(netdev, 65536);
2720#endif
9a799d71 2721
eacd73f7
YZ		 2722#ifdef IXGBE_FCOE
2723 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2724 ixgbe_configure_fcoe(adapter);
2725
2726#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 2727 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2728 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 2729 adapter->tx_ring[i]->atr_sample_rate =
c4cf55e5
PWJ		 2730 adapter->atr_sample_rate;
2731 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2732 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2733 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2734 }
2735
9a799d71
AK		 2736 ixgbe_configure_tx(adapter);
2737 ixgbe_configure_rx(adapter);
2738 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 2739 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
2740 (adapter->rx_ring[i]->count - 1));
9a799d71
AK		 2741}
2742
e8e26350
PW		 2743static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2744{
2745 switch (hw->phy.type) {
2746 case ixgbe_phy_sfp_avago:
2747 case ixgbe_phy_sfp_ftl:
2748 case ixgbe_phy_sfp_intel:
2749 case ixgbe_phy_sfp_unknown:
2750 case ixgbe_phy_tw_tyco:
2751 case ixgbe_phy_tw_unknown:
2752 return true;
2753 default:
2754 return false;
2755 }
2756}
2757
0ecc061d 2758/**
e8e26350
PW		 2759 * ixgbe_sfp_link_config - set up SFP+ link
2760 * @adapter: pointer to private adapter struct
2761 **/
2762static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2763{
2764 struct ixgbe_hw *hw = &adapter->hw;
2765
2766 if (hw->phy.multispeed_fiber) {
2767 /*
2768 * In multispeed fiber setups, the device may not have
2769 * had a physical connection when the driver loaded.
2770 * If that's the case, the initial link configuration
2771 * couldn't get the MAC into 10G or 1G mode, so we'll
2772 * never have a link status change interrupt fire.
2773 * We need to try and force an autonegotiation
2774 * session, then bring up link.
2775 */
2776 hw->mac.ops.setup_sfp(hw);
2777 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2778 schedule_work(&adapter->multispeed_fiber_task);
2779 } else {
2780 /*
2781 * Direct Attach Cu and non-multispeed fiber modules
2782 * still need to be configured properly prior to
2783 * attempting link.
2784 */
2785 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2786 schedule_work(&adapter->sfp_config_module_task);
2787 }
2788}
2789
2790/**
2791 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2792 * @hw: pointer to private hardware struct
2793 *
2794 * Returns 0 on success, negative on failure
2795 **/
e8e26350 2796static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2797{
2798 u32 autoneg;
8620a103 2799 bool negotiation, link_up = false;
0ecc061d
PWJ		 2800 u32 ret = IXGBE_ERR_LINK_SETUP;
2801
2802 if (hw->mac.ops.check_link)
2803 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2804
2805 if (ret)
2806 goto link_cfg_out;
2807
2808 if (hw->mac.ops.get_link_capabilities)
8620a103 2809 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
0ecc061d
PWJ		 2810 if (ret)
2811 goto link_cfg_out;
2812
8620a103
MC		 2813 if (hw->mac.ops.setup_link)
2814 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 2815link_cfg_out:
2816 return ret;
2817}
2818
e8e26350
PW		 2819#define IXGBE_MAX_RX_DESC_POLL 10
2820static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2821 int rxr)
2822{
4a0b9ca0 2823 int j = adapter->rx_ring[rxr]->reg_idx;
e8e26350
PW		 2824 int k;
2825
2826 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2827 if (IXGBE_READ_REG(&adapter->hw,
2828 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2829 break;
2830 else
2831 msleep(1);
2832 }
2833 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2834 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2835 "not set within the polling period\n", rxr);
2836 }
4a0b9ca0
PW		 2837 ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
2838 (adapter->rx_ring[rxr]->count - 1));
e8e26350
PW		 2839}
2840
9a799d71
AK		 2841static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2842{
2843 struct net_device *netdev = adapter->netdev;
9a799d71 2844 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2845 int i, j = 0;
e8e26350 2846 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2847 int err;
9a799d71 2848 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2849 u32 txdctl, rxdctl, mhadd;
e8e26350 2850 u32 dmatxctl;
021230d4 2851 u32 gpie;
c9205697 2852 u32 ctrl_ext;
9a799d71 2853
5eba3699
AV		 2854 ixgbe_get_hw_control(adapter);
2855
021230d4
AV		 2856 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2857 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2858 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2859 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2860 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2861 } else {
2862 /* MSI only */
021230d4 2863 gpie = 0;
9a799d71 2864 }
1cdd1ec8
GR		 2865 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2866 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
2867 gpie |= IXGBE_GPIE_VTMODE_64;
2868 }
021230d4
AV		 2869 /* XXX: to interrupt immediately for EICS writes, enable this */
2870 /* gpie |= IXGBE_GPIE_EIMEN; */
2871 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2872 }
2873
9b471446
JB		 2874 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2875 /*
2876 * use EIAM to auto-mask when MSI-X interrupt is asserted
2877 * this saves a register write for every interrupt
2878 */
2879 switch (hw->mac.type) {
2880 case ixgbe_mac_82598EB:
2881 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2882 break;
2883 default:
2884 case ixgbe_mac_82599EB:
2885 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
2886 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
2887 break;
2888 }
2889 } else {
021230d4
AV		 2890 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2891 * specifically only auto mask tx and rx interrupts */
2892 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2893 }
9a799d71 2894
0befdb3e
JB		 2895 /* Enable fan failure interrupt if media type is copper */
2896 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2897 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2898 gpie |= IXGBE_SDP1_GPIEN;
2899 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2900 }
2901
e8e26350
PW		 2902 if (hw->mac.type == ixgbe_mac_82599EB) {
2903 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2904 gpie |= IXGBE_SDP1_GPIEN;
2905 gpie |= IXGBE_SDP2_GPIEN;
2906 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2907 }
2908
63f39bd1
YZ		 2909#ifdef IXGBE_FCOE
2910 /* adjust max frame to be able to do baby jumbo for FCoE */
f34c5c82 2911 if ((netdev->features & NETIF_F_FCOE_MTU) &&
63f39bd1
YZ		 2912 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2913 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2914
2915#endif /* IXGBE_FCOE */
021230d4 2916 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2917 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2918 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2919 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2920
2921 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2922 }
2923
2924 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2925 j = adapter->tx_ring[i]->reg_idx;
021230d4 2926 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2927 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2928 txdctl |= (8 << 16);
e8e26350
PW		 2929 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2930 }
2931
2932 if (hw->mac.type == ixgbe_mac_82599EB) {
2933 /* DMATXCTL.EN must be set after all Tx queue config is done */
2934 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2935 dmatxctl |= IXGBE_DMATXCTL_TE;
2936 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2937 }
2938 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2939 j = adapter->tx_ring[i]->reg_idx;
e8e26350 2940 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2941 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2942 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
1cdd1ec8
GR		 2943 if (hw->mac.type == ixgbe_mac_82599EB) {
2944 int wait_loop = 10;
2945 /* poll for Tx Enable ready */
2946 do {
2947 msleep(1);
2948 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2949 } while (--wait_loop &&
2950 !(txdctl & IXGBE_TXDCTL_ENABLE));
2951 if (!wait_loop)
2952 DPRINTK(DRV, ERR, "Could not enable "
2953 "Tx Queue %d\n", j);
2954 }
9a799d71
AK		 2955 }
2956
e8e26350 2957 for (i = 0; i < num_rx_rings; i++) {
4a0b9ca0 2958 j = adapter->rx_ring[i]->reg_idx;
021230d4
AV		 2959 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2960 /* enable PTHRESH=32 descriptors (half the internal cache)
2961 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2962 * this also removes a pesky rx_no_buffer_count increment */
2963 rxdctl |= 0x0020;
9a799d71 2964 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2965 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2966 if (hw->mac.type == ixgbe_mac_82599EB)
2967 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2968 }
2969 /* enable all receives */
2970 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2971 if (hw->mac.type == ixgbe_mac_82598EB)
2972 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2973 else
2974 rxdctl |= IXGBE_RXCTRL_RXEN;
2975 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2976
2977 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2978 ixgbe_configure_msix(adapter);
2979 else
2980 ixgbe_configure_msi_and_legacy(adapter);
2981
2982 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2983 ixgbe_napi_enable_all(adapter);
2984
2985 /* clear any pending interrupts, may auto mask */
2986 IXGBE_READ_REG(hw, IXGBE_EICR);
2987
9a799d71
AK		 2988 ixgbe_irq_enable(adapter);
2989
bf069c97
DS		 2990 /*
2991 * If this adapter has a fan, check to see if we had a failure
2992 * before we enabled the interrupt.
2993 */
2994 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2995 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2996 if (esdp & IXGBE_ESDP_SDP1)
2997 DPRINTK(DRV, CRIT,
2998 "Fan has stopped, replace the adapter\n");
2999 }
3000
e8e26350
PW		 3001 /*
3002 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 3003 * arrived before interrupts were enabled but after probe. Such
3004 * devices wouldn't have their type identified yet. We need to
3005 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 3006 * If we're not hot-pluggable SFP+, we just need to configure link
3007 * and bring it up.
3008 */
19343de2
DS		 3009 if (hw->phy.type == ixgbe_phy_unknown) {
3010 err = hw->phy.ops.identify(hw);
3011 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 3012 /*
3013 * Take the device down and schedule the sfp tasklet
3014 * which will unregister_netdev and log it.
3015 */
19343de2 3016 ixgbe_down(adapter);
5da43c1a 3017 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 3018 return err;
3019 }
e8e26350
PW		 3020 }
3021
3022 if (ixgbe_is_sfp(hw)) {
3023 ixgbe_sfp_link_config(adapter);
3024 } else {
3025 err = ixgbe_non_sfp_link_config(hw);
3026 if (err)
3027 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
3028 }
0ecc061d 3029
c4cf55e5
PWJ		 3030 for (i = 0; i < adapter->num_tx_queues; i++)
3031 set_bit(__IXGBE_FDIR_INIT_DONE,
4a0b9ca0 3032 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5 3033
1da100bb
PWJ		 3034 /* enable transmits */
3035 netif_tx_start_all_queues(netdev);
3036
9a799d71
AK		 3037 /* bring the link up in the watchdog, this could race with our first
3038 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3039 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3040 adapter->link_check_timeout = jiffies;
9a799d71 3041 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3042
3043 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3044 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3045 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3046 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3047
9a799d71
AK		 3048 return 0;
3049}
3050
d4f80882
AV		 3051void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3052{
3053 WARN_ON(in_interrupt());
3054 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3055 msleep(1);
3056 ixgbe_down(adapter);
3057 ixgbe_up(adapter);
3058 clear_bit(__IXGBE_RESETTING, &adapter->state);
3059}
3060
9a799d71
AK		 3061int ixgbe_up(struct ixgbe_adapter *adapter)
3062{
3063 /* hardware has been reset, we need to reload some things */
3064 ixgbe_configure(adapter);
3065
3066 return ixgbe_up_complete(adapter);
3067}
3068
3069void ixgbe_reset(struct ixgbe_adapter *adapter)
3070{
c44ade9e 3071 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3072 int err;
3073
3074 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3075 switch (err) {
3076 case 0:
3077 case IXGBE_ERR_SFP_NOT_PRESENT:
3078 break;
3079 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3080 dev_err(&adapter->pdev->dev, "master disable timed out\n");
3081 break;
794caeb2
PWJ		 3082 case IXGBE_ERR_EEPROM_VERSION:
3083 /* We are running on a pre-production device, log a warning */
3084 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
3085 "adapter/LOM. Please be aware there may be issues "
3086 "associated with your hardware. If you are "
3087 "experiencing problems please contact your Intel or "
3088 "hardware representative who provided you with this "
3089 "hardware.\n");
3090 break;
da4dd0f7
PWJ		 3091 default:
3092 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
3093 }
9a799d71
AK		 3094
3095 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3096 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3097 IXGBE_RAH_AV);
9a799d71
AK		 3098}
3099
9a799d71
AK		 3100/**
3101 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3102 * @adapter: board private structure
3103 * @rx_ring: ring to free buffers from
3104 **/
3105static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 3106 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3107{
3108 struct pci_dev *pdev = adapter->pdev;
3109 unsigned long size;
3110 unsigned int i;
3111
3112 /* Free all the Rx ring sk_buffs */
3113
3114 for (i = 0; i < rx_ring->count; i++) {
3115 struct ixgbe_rx_buffer *rx_buffer_info;
3116
3117 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3118 if (rx_buffer_info->dma) {
3119 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 3120 rx_ring->rx_buf_len,
3121 PCI_DMA_FROMDEVICE);
9a799d71
AK		 3122 rx_buffer_info->dma = 0;
3123 }
3124 if (rx_buffer_info->skb) {
f8212f97 3125 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3126 rx_buffer_info->skb = NULL;
f8212f97
AD		 3127 do {
3128 struct sk_buff *this = skb;
43634e82
MC		 3129 if (IXGBE_RSC_CB(this)->dma)
3130 pci_unmap_single(pdev, IXGBE_RSC_CB(this)->dma,
3131 rx_ring->rx_buf_len,
3132 PCI_DMA_FROMDEVICE);
f8212f97
AD		 3133 skb = skb->prev;
3134 dev_kfree_skb(this);
3135 } while (skb);
9a799d71
AK		 3136 }
3137 if (!rx_buffer_info->page)
3138 continue;
4f57ca6e
JB		 3139 if (rx_buffer_info->page_dma) {
3140 pci_unmap_page(pdev, rx_buffer_info->page_dma,
3141 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
3142 rx_buffer_info->page_dma = 0;
3143 }
9a799d71
AK		 3144 put_page(rx_buffer_info->page);
3145 rx_buffer_info->page = NULL;
762f4c57 3146 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3147 }
3148
3149 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3150 memset(rx_ring->rx_buffer_info, 0, size);
3151
3152 /* Zero out the descriptor ring */
3153 memset(rx_ring->desc, 0, rx_ring->size);
3154
3155 rx_ring->next_to_clean = 0;
3156 rx_ring->next_to_use = 0;
3157
9891ca7c
JB		 3158 if (rx_ring->head)
3159 writel(0, adapter->hw.hw_addr + rx_ring->head);
3160 if (rx_ring->tail)
3161 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 3162}
3163
3164/**
3165 * ixgbe_clean_tx_ring - Free Tx Buffers
3166 * @adapter: board private structure
3167 * @tx_ring: ring to be cleaned
3168 **/
3169static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 3170 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3171{
3172 struct ixgbe_tx_buffer *tx_buffer_info;
3173 unsigned long size;
3174 unsigned int i;
3175
3176 /* Free all the Tx ring sk_buffs */
3177
3178 for (i = 0; i < tx_ring->count; i++) {
3179 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3180 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3181 }
3182
3183 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3184 memset(tx_ring->tx_buffer_info, 0, size);
3185
3186 /* Zero out the descriptor ring */
3187 memset(tx_ring->desc, 0, tx_ring->size);
3188
3189 tx_ring->next_to_use = 0;
3190 tx_ring->next_to_clean = 0;
3191
9891ca7c
JB		 3192 if (tx_ring->head)
3193 writel(0, adapter->hw.hw_addr + tx_ring->head);
3194 if (tx_ring->tail)
3195 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 3196}
3197
3198/**
021230d4 3199 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3200 * @adapter: board private structure
3201 **/
021230d4 3202static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3203{
3204 int i;
3205
021230d4 3206 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3207 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
9a799d71
AK		 3208}
3209
3210/**
021230d4 3211 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3212 * @adapter: board private structure
3213 **/
021230d4 3214static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3215{
3216 int i;
3217
021230d4 3218 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3219 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3220}
3221
3222void ixgbe_down(struct ixgbe_adapter *adapter)
3223{
3224 struct net_device *netdev = adapter->netdev;
7f821875 3225 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3226 u32 rxctrl;
7f821875
JB		 3227 u32 txdctl;
3228 int i, j;
9a799d71
AK		 3229
3230 /* signal that we are down to the interrupt handler */
3231 set_bit(__IXGBE_DOWN, &adapter->state);
3232
767081ad
GR		 3233 /* disable receive for all VFs and wait one second */
3234 if (adapter->num_vfs) {
3235 for (i = 0 ; i < adapter->num_vfs; i++)
3236 adapter->vfinfo[i].clear_to_send = 0;
3237
3238 /* ping all the active vfs to let them know we are going down */
3239 ixgbe_ping_all_vfs(adapter);
3240 /* Disable all VFTE/VFRE TX/RX */
3241 ixgbe_disable_tx_rx(adapter);
3242 }
3243
9a799d71 3244 /* disable receives */
7f821875
JB		 3245 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3246 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 3247
3248 netif_tx_disable(netdev);
3249
7f821875 3250 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 3251 msleep(10);
3252
7f821875
JB		 3253 netif_tx_stop_all_queues(netdev);
3254
9a799d71
AK		 3255 ixgbe_irq_disable(adapter);
3256
021230d4 3257 ixgbe_napi_disable_all(adapter);
7f821875 3258
0a1f87cb
DS		 3259 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3260 del_timer_sync(&adapter->sfp_timer);
9a799d71 3261 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 3262 cancel_work_sync(&adapter->watchdog_task);
9a799d71 3263
c4cf55e5
PWJ		 3264 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3265 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3266 cancel_work_sync(&adapter->fdir_reinit_task);
3267
7f821875
JB		 3268 /* disable transmits in the hardware now that interrupts are off */
3269 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3270 j = adapter->tx_ring[i]->reg_idx;
7f821875
JB		 3271 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3272 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3273 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3274 }
88512539
PW		 3275 /* Disable the Tx DMA engine on 82599 */
3276 if (hw->mac.type == ixgbe_mac_82599EB)
3277 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3278 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3279 ~IXGBE_DMATXCTL_TE));
7f821875 3280
9a799d71 3281 netif_carrier_off(netdev);
9a799d71 3282
9a713e7c
PW		 3283 /* clear n-tuple filters that are cached */
3284 ethtool_ntuple_flush(netdev);
3285
6f4a0e45
PL		 3286 if (!pci_channel_offline(adapter->pdev))
3287 ixgbe_reset(adapter);
9a799d71
AK		 3288 ixgbe_clean_all_tx_rings(adapter);
3289 ixgbe_clean_all_rx_rings(adapter);
3290
5dd2d332 3291#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3292 /* since we reset the hardware DCA settings were cleared */
e35ec126 3293 ixgbe_setup_dca(adapter);
96b0e0f6 3294#endif
9a799d71
AK		 3295}
3296
9a799d71 3297/**
021230d4
AV		 3298 * ixgbe_poll - NAPI Rx polling callback
3299 * @napi: structure for representing this polling device
3300 * @budget: how many packets driver is allowed to clean
3301 *
3302 * This function is used for legacy and MSI, NAPI mode
9a799d71 3303 **/
021230d4 3304static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3305{
9a1a69ad
JB		 3306 struct ixgbe_q_vector *q_vector =
3307 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3308 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 3309 int tx_clean_complete, work_done = 0;
9a799d71 3310
5dd2d332 3311#ifdef CONFIG_IXGBE_DCA
bd0362dd 3312 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4a0b9ca0
PW		 3313 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3314 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
bd0362dd
JC		 3315 }
3316#endif
3317
4a0b9ca0
PW		 3318 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3319 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 3320
9a1a69ad 3321 if (!tx_clean_complete)
d2c7ddd6
DM		 3322 work_done = budget;
3323
53e52c72
DM		 3324 /* If budget not fully consumed, exit the polling mode */
3325 if (work_done < budget) {
288379f0 3326 napi_complete(napi);
f7554a2b 3327 if (adapter->rx_itr_setting & 1)
f494e8fa 3328 ixgbe_set_itr(adapter);
d4f80882 3329 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 3330 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 3331 }
9a799d71
AK		 3332 return work_done;
3333}
3334
3335/**
3336 * ixgbe_tx_timeout - Respond to a Tx Hang
3337 * @netdev: network interface device structure
3338 **/
3339static void ixgbe_tx_timeout(struct net_device *netdev)
3340{
3341 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3342
3343 /* Do the reset outside of interrupt context */
3344 schedule_work(&adapter->reset_task);
3345}
3346
3347static void ixgbe_reset_task(struct work_struct *work)
3348{
3349 struct ixgbe_adapter *adapter;
3350 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3351
2f90b865
AD		 3352 /* If we're already down or resetting, just bail */
3353 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3354 test_bit(__IXGBE_RESETTING, &adapter->state))
3355 return;
3356
9a799d71
AK		 3357 adapter->tx_timeout_count++;
3358
d4f80882 3359 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3360}
3361
bc97114d
PWJ		 3362#ifdef CONFIG_IXGBE_DCB
3363static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3364{
bc97114d 3365 bool ret = false;
0cefafad 3366 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3367
0cefafad
JB		 3368 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3369 return ret;
3370
3371 f->mask = 0x7 << 3;
3372 adapter->num_rx_queues = f->indices;
3373 adapter->num_tx_queues = f->indices;
3374 ret = true;
2f90b865 3375
bc97114d
PWJ		 3376 return ret;
3377}
3378#endif
3379
4df10466
JB		 3380/**
3381 * ixgbe_set_rss_queues: Allocate queues for RSS
3382 * @adapter: board private structure to initialize
3383 *
3384 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3385 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3386 *
3387 **/
bc97114d
PWJ		 3388static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3389{
3390 bool ret = false;
0cefafad 3391 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3392
3393 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3394 f->mask = 0xF;
3395 adapter->num_rx_queues = f->indices;
3396 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3397 ret = true;
3398 } else {
bc97114d 3399 ret = false;
b9804972
JB		 3400 }
3401
bc97114d
PWJ		 3402 return ret;
3403}
3404
c4cf55e5
PWJ		 3405/**
3406 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3407 * @adapter: board private structure to initialize
3408 *
3409 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3410 * to the original CPU that initiated the Tx session. This runs in addition
3411 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3412 * Rx load across CPUs using RSS.
3413 *
3414 **/
3415static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3416{
3417 bool ret = false;
3418 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3419
3420 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3421 f_fdir->mask = 0;
3422
3423 /* Flow Director must have RSS enabled */
3424 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3425 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3426 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3427 adapter->num_tx_queues = f_fdir->indices;
3428 adapter->num_rx_queues = f_fdir->indices;
3429 ret = true;
3430 } else {
3431 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3432 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3433 }
3434 return ret;
3435}
3436
0331a832
YZ		 3437#ifdef IXGBE_FCOE
3438/**
3439 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3440 * @adapter: board private structure to initialize
3441 *
3442 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3443 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3444 * rx queues out of the max number of rx queues, instead, it is used as the
3445 * index of the first rx queue used by FCoE.
3446 *
3447 **/
3448static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3449{
3450 bool ret = false;
3451 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3452
3453 f->indices = min((int)num_online_cpus(), f->indices);
3454 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 3455 adapter->num_rx_queues = 1;
3456 adapter->num_tx_queues = 1;
0331a832
YZ		 3457#ifdef CONFIG_IXGBE_DCB
3458 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6 3459 DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
0331a832
YZ		 3460 ixgbe_set_dcb_queues(adapter);
3461 }
3462#endif
3463 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8de8b2e6 3464 DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
8faa2a78
YZ		 3465 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3466 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3467 ixgbe_set_fdir_queues(adapter);
3468 else
3469 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 3470 }
3471 /* adding FCoE rx rings to the end */
3472 f->mask = adapter->num_rx_queues;
3473 adapter->num_rx_queues += f->indices;
8de8b2e6 3474 adapter->num_tx_queues += f->indices;
0331a832
YZ		 3475
3476 ret = true;
3477 }
3478
3479 return ret;
3480}
3481
3482#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 3483/**
3484 * ixgbe_set_sriov_queues: Allocate queues for IOV use
3485 * @adapter: board private structure to initialize
3486 *
3487 * IOV doesn't actually use anything, so just NAK the
3488 * request for now and let the other queue routines
3489 * figure out what to do.
3490 */
3491static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
3492{
3493 return false;
3494}
3495
4df10466
JB		 3496/*
3497 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3498 * @adapter: board private structure to initialize
3499 *
3500 * This is the top level queue allocation routine. The order here is very
3501 * important, starting with the "most" number of features turned on at once,
3502 * and ending with the smallest set of features. This way large combinations
3503 * can be allocated if they're turned on, and smaller combinations are the
3504 * fallthrough conditions.
3505 *
3506 **/
bc97114d
PWJ		 3507static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3508{
1cdd1ec8
GR		 3509 /* Start with base case */
3510 adapter->num_rx_queues = 1;
3511 adapter->num_tx_queues = 1;
3512 adapter->num_rx_pools = adapter->num_rx_queues;
3513 adapter->num_rx_queues_per_pool = 1;
3514
3515 if (ixgbe_set_sriov_queues(adapter))
3516 return;
3517
0331a832
YZ		 3518#ifdef IXGBE_FCOE
3519 if (ixgbe_set_fcoe_queues(adapter))
3520 goto done;
3521
3522#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3523#ifdef CONFIG_IXGBE_DCB
3524 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 3525 goto done;
bc97114d
PWJ		 3526
3527#endif
c4cf55e5
PWJ		 3528 if (ixgbe_set_fdir_queues(adapter))
3529 goto done;
3530
bc97114d 3531 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 3532 goto done;
3533
3534 /* fallback to base case */
3535 adapter->num_rx_queues = 1;
3536 adapter->num_tx_queues = 1;
3537
3538done:
3539 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3540 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 3541}
3542
021230d4 3543static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 3544 int vectors)
021230d4
AV		 3545{
3546 int err, vector_threshold;
3547
3548 /* We'll want at least 3 (vector_threshold):
3549 * 1) TxQ[0] Cleanup
3550 * 2) RxQ[0] Cleanup
3551 * 3) Other (Link Status Change, etc.)
3552 * 4) TCP Timer (optional)
3553 */
3554 vector_threshold = MIN_MSIX_COUNT;
3555
3556 /* The more we get, the more we will assign to Tx/Rx Cleanup
3557 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3558 * Right now, we simply care about how many we'll get; we'll
3559 * set them up later while requesting irq's.
3560 */
3561 while (vectors >= vector_threshold) {
3562 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 3563 vectors);
021230d4
AV		 3564 if (!err) /* Success in acquiring all requested vectors. */
3565 break;
3566 else if (err < 0)
3567 vectors = 0; /* Nasty failure, quit now */
3568 else /* err == number of vectors we should try again with */
3569 vectors = err;
3570 }
3571
3572 if (vectors < vector_threshold) {
3573 /* Can't allocate enough MSI-X interrupts? Oh well.
3574 * This just means we'll go with either a single MSI
3575 * vector or fall back to legacy interrupts.
3576 */
3577 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3578 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3579 kfree(adapter->msix_entries);
3580 adapter->msix_entries = NULL;
021230d4
AV		 3581 } else {
3582 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 3583 /*
3584 * Adjust for only the vectors we'll use, which is minimum
3585 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3586 * vectors we were allocated.
3587 */
3588 adapter->num_msix_vectors = min(vectors,
3589 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 3590 }
3591}
3592
021230d4 3593/**
bc97114d 3594 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 3595 * @adapter: board private structure to initialize
3596 *
bc97114d
PWJ		 3597 * Cache the descriptor ring offsets for RSS to the assigned rings.
3598 *
021230d4 3599 **/
bc97114d 3600static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 3601{
bc97114d
PWJ		 3602 int i;
3603 bool ret = false;
3604
3605 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3606 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3607 adapter->rx_ring[i]->reg_idx = i;
bc97114d 3608 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3609 adapter->tx_ring[i]->reg_idx = i;
bc97114d
PWJ		 3610 ret = true;
3611 } else {
3612 ret = false;
3613 }
3614
3615 return ret;
3616}
3617
3618#ifdef CONFIG_IXGBE_DCB
3619/**
3620 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3621 * @adapter: board private structure to initialize
3622 *
3623 * Cache the descriptor ring offsets for DCB to the assigned rings.
3624 *
3625 **/
3626static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3627{
3628 int i;
3629 bool ret = false;
3630 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3631
3632 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3633 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 3634 /* the number of queues is assumed to be symmetric */
3635 for (i = 0; i < dcb_i; i++) {
4a0b9ca0
PW		 3636 adapter->rx_ring[i]->reg_idx = i << 3;
3637 adapter->tx_ring[i]->reg_idx = i << 2;
2f90b865 3638 }
bc97114d 3639 ret = true;
e8e26350 3640 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 3641 if (dcb_i == 8) {
3642 /*
3643 * Tx TC0 starts at: descriptor queue 0
3644 * Tx TC1 starts at: descriptor queue 32
3645 * Tx TC2 starts at: descriptor queue 64
3646 * Tx TC3 starts at: descriptor queue 80
3647 * Tx TC4 starts at: descriptor queue 96
3648 * Tx TC5 starts at: descriptor queue 104
3649 * Tx TC6 starts at: descriptor queue 112
3650 * Tx TC7 starts at: descriptor queue 120
3651 *
3652 * Rx TC0-TC7 are offset by 16 queues each
3653 */
3654 for (i = 0; i < 3; i++) {
4a0b9ca0
PW		 3655 adapter->tx_ring[i]->reg_idx = i << 5;
3656 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 3657 }
3658 for ( ; i < 5; i++) {
4a0b9ca0 3659 adapter->tx_ring[i]->reg_idx =
f92ef202 3660 ((i + 2) << 4);
4a0b9ca0 3661 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 3662 }
3663 for ( ; i < dcb_i; i++) {
4a0b9ca0 3664 adapter->tx_ring[i]->reg_idx =
f92ef202 3665 ((i + 8) << 3);
4a0b9ca0 3666 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 3667 }
3668
3669 ret = true;
3670 } else if (dcb_i == 4) {
3671 /*
3672 * Tx TC0 starts at: descriptor queue 0
3673 * Tx TC1 starts at: descriptor queue 64
3674 * Tx TC2 starts at: descriptor queue 96
3675 * Tx TC3 starts at: descriptor queue 112
3676 *
3677 * Rx TC0-TC3 are offset by 32 queues each
3678 */
4a0b9ca0
PW		 3679 adapter->tx_ring[0]->reg_idx = 0;
3680 adapter->tx_ring[1]->reg_idx = 64;
3681 adapter->tx_ring[2]->reg_idx = 96;
3682 adapter->tx_ring[3]->reg_idx = 112;
f92ef202 3683 for (i = 0 ; i < dcb_i; i++)
4a0b9ca0 3684 adapter->rx_ring[i]->reg_idx = i << 5;
f92ef202
PW		 3685
3686 ret = true;
3687 } else {
3688 ret = false;
e8e26350 3689 }
bc97114d
PWJ		 3690 } else {
3691 ret = false;
021230d4 3692 }
bc97114d
PWJ		 3693 } else {
3694 ret = false;
021230d4 3695 }
bc97114d
PWJ		 3696
3697 return ret;
3698}
3699#endif
3700
c4cf55e5
PWJ		 3701/**
3702 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3703 * @adapter: board private structure to initialize
3704 *
3705 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3706 *
3707 **/
3708static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3709{
3710 int i;
3711 bool ret = false;
3712
3713 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3714 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3715 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3716 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3717 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 3718 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3719 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 3720 ret = true;
3721 }
3722
3723 return ret;
3724}
3725
0331a832
YZ		 3726#ifdef IXGBE_FCOE
3727/**
3728 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3729 * @adapter: board private structure to initialize
3730 *
3731 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3732 *
3733 */
3734static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3735{
8de8b2e6 3736 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 3737 bool ret = false;
3738 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3739
3740 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3741#ifdef CONFIG_IXGBE_DCB
3742 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 3743 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3744
0331a832 3745 ixgbe_cache_ring_dcb(adapter);
8de8b2e6 3746 /* find out queues in TC for FCoE */
4a0b9ca0
PW		 3747 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
3748 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
8de8b2e6
YZ		 3749 /*
3750 * In 82599, the number of Tx queues for each traffic
3751 * class for both 8-TC and 4-TC modes are:
3752 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3753 * 8 TCs: 32 32 16 16 8 8 8 8
3754 * 4 TCs: 64 64 32 32
3755 * We have max 8 queues for FCoE, where 8 the is
3756 * FCoE redirection table size. If TC for FCoE is
3757 * less than or equal to TC3, we have enough queues
3758 * to add max of 8 queues for FCoE, so we start FCoE
3759 * tx descriptor from the next one, i.e., reg_idx + 1.
3760 * If TC for FCoE is above TC3, implying 8 TC mode,
3761 * and we need 8 for FCoE, we have to take all queues
3762 * in that traffic class for FCoE.
3763 */
3764 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3765 fcoe_tx_i--;
0331a832
YZ		 3766 }
3767#endif /* CONFIG_IXGBE_DCB */
3768 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 3769 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3770 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3771 ixgbe_cache_ring_fdir(adapter);
3772 else
3773 ixgbe_cache_ring_rss(adapter);
3774
8de8b2e6
YZ		 3775 fcoe_rx_i = f->mask;
3776 fcoe_tx_i = f->mask;
3777 }
3778 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4a0b9ca0
PW		 3779 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
3780 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
0331a832 3781 }
0331a832
YZ		 3782 ret = true;
3783 }
3784 return ret;
3785}
3786
3787#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 3788/**
3789 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
3790 * @adapter: board private structure to initialize
3791 *
3792 * SR-IOV doesn't use any descriptor rings but changes the default if
3793 * no other mapping is used.
3794 *
3795 */
3796static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
3797{
4a0b9ca0
PW		 3798 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
3799 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 3800 if (adapter->num_vfs)
3801 return true;
3802 else
3803 return false;
3804}
3805
bc97114d
PWJ		 3806/**
3807 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3808 * @adapter: board private structure to initialize
3809 *
3810 * Once we know the feature-set enabled for the device, we'll cache
3811 * the register offset the descriptor ring is assigned to.
3812 *
3813 * Note, the order the various feature calls is important. It must start with
3814 * the "most" features enabled at the same time, then trickle down to the
3815 * least amount of features turned on at once.
3816 **/
3817static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3818{
3819 /* start with default case */
4a0b9ca0
PW		 3820 adapter->rx_ring[0]->reg_idx = 0;
3821 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 3822
1cdd1ec8
GR		 3823 if (ixgbe_cache_ring_sriov(adapter))
3824 return;
3825
0331a832
YZ		 3826#ifdef IXGBE_FCOE
3827 if (ixgbe_cache_ring_fcoe(adapter))
3828 return;
3829
3830#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3831#ifdef CONFIG_IXGBE_DCB
3832 if (ixgbe_cache_ring_dcb(adapter))
3833 return;
3834
3835#endif
c4cf55e5
PWJ		 3836 if (ixgbe_cache_ring_fdir(adapter))
3837 return;
3838
bc97114d
PWJ		 3839 if (ixgbe_cache_ring_rss(adapter))
3840 return;
021230d4
AV		 3841}
3842
9a799d71
AK		 3843/**
3844 * ixgbe_alloc_queues - Allocate memory for all rings
3845 * @adapter: board private structure to initialize
3846 *
3847 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 3848 * number of queues at compile-time. The polling_netdev array is
3849 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 3850 **/
2f90b865 3851static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 3852{
3853 int i;
4a0b9ca0 3854 int orig_node = adapter->node;
9a799d71 3855
021230d4 3856 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 3857 struct ixgbe_ring *ring = adapter->tx_ring[i];
3858 if (orig_node == -1) {
3859 int cur_node = next_online_node(adapter->node);
3860 if (cur_node == MAX_NUMNODES)
3861 cur_node = first_online_node;
3862 adapter->node = cur_node;
3863 }
3864 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
3865 adapter->node);
3866 if (!ring)
3867 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
3868 if (!ring)
3869 goto err_tx_ring_allocation;
3870 ring->count = adapter->tx_ring_count;
3871 ring->queue_index = i;
3872 ring->numa_node = adapter->node;
3873
3874 adapter->tx_ring[i] = ring;
021230d4 3875 }
b9804972 3876
4a0b9ca0
PW		 3877 /* Restore the adapter's original node */
3878 adapter->node = orig_node;
3879
9a799d71 3880 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 3881 struct ixgbe_ring *ring = adapter->rx_ring[i];
3882 if (orig_node == -1) {
3883 int cur_node = next_online_node(adapter->node);
3884 if (cur_node == MAX_NUMNODES)
3885 cur_node = first_online_node;
3886 adapter->node = cur_node;
3887 }
3888 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
3889 adapter->node);
3890 if (!ring)
3891 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
3892 if (!ring)
3893 goto err_rx_ring_allocation;
3894 ring->count = adapter->rx_ring_count;
3895 ring->queue_index = i;
3896 ring->numa_node = adapter->node;
3897
3898 adapter->rx_ring[i] = ring;
021230d4
AV		 3899 }
3900
4a0b9ca0
PW		 3901 /* Restore the adapter's original node */
3902 adapter->node = orig_node;
3903
021230d4
AV		 3904 ixgbe_cache_ring_register(adapter);
3905
3906 return 0;
3907
3908err_rx_ring_allocation:
4a0b9ca0
PW		 3909 for (i = 0; i < adapter->num_tx_queues; i++)
3910 kfree(adapter->tx_ring[i]);
021230d4
AV		 3911err_tx_ring_allocation:
3912 return -ENOMEM;
3913}
3914
3915/**
3916 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3917 * @adapter: board private structure to initialize
3918 *
3919 * Attempt to configure the interrupts using the best available
3920 * capabilities of the hardware and the kernel.
3921 **/
feea6a57 3922static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 3923{
8be0e467 3924 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 3925 int err = 0;
3926 int vector, v_budget;
3927
3928 /*
3929 * It's easy to be greedy for MSI-X vectors, but it really
3930 * doesn't do us much good if we have a lot more vectors
3931 * than CPU's. So let's be conservative and only ask for
342bde1b 3932 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 3933 */
3934 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
342bde1b 3935 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 3936
3937 /*
3938 * At the same time, hardware can only support a maximum of
8be0e467
PW		 3939 * hw.mac->max_msix_vectors vectors. With features
3940 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3941 * descriptor queues supported by our device. Thus, we cap it off in
3942 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3943 */
8be0e467 3944 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3945
3946 /* A failure in MSI-X entry allocation isn't fatal, but it does
3947 * mean we disable MSI-X capabilities of the adapter. */
3948 adapter->msix_entries = kcalloc(v_budget,
b4617240 3949 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 3950 if (adapter->msix_entries) {
3951 for (vector = 0; vector < v_budget; vector++)
3952 adapter->msix_entries[vector].entry = vector;
021230d4 3953
7a921c93 3954 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 3955
7a921c93
AD		 3956 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3957 goto out;
3958 }
021230d4 3959
7a921c93
AD		 3960 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3961 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 3962 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3963 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3964 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 3965 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3966 ixgbe_disable_sriov(adapter);
3967
7a921c93 3968 ixgbe_set_num_queues(adapter);
021230d4 3969
021230d4
AV		 3970 err = pci_enable_msi(adapter->pdev);
3971 if (!err) {
3972 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3973 } else {
3974 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 3975 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 3976 /* reset err */
3977 err = 0;
3978 }
3979
3980out:
021230d4
AV		 3981 return err;
3982}
3983
7a921c93
AD		 3984/**
3985 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3986 * @adapter: board private structure to initialize
3987 *
3988 * We allocate one q_vector per queue interrupt. If allocation fails we
3989 * return -ENOMEM.
3990 **/
3991static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3992{
3993 int q_idx, num_q_vectors;
3994 struct ixgbe_q_vector *q_vector;
3995 int napi_vectors;
3996 int (*poll)(struct napi_struct *, int);
3997
3998 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3999 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4000 napi_vectors = adapter->num_rx_queues;
91281fd3 4001 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4002 } else {
4003 num_q_vectors = 1;
4004 napi_vectors = 1;
4005 poll = &ixgbe_poll;
4006 }
4007
4008 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2
JB		 4009 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4010 GFP_KERNEL, adapter->node);
4011 if (!q_vector)
4012 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4013 GFP_KERNEL);
7a921c93
AD		 4014 if (!q_vector)
4015 goto err_out;
4016 q_vector->adapter = adapter;
f7554a2b
NS		 4017 if (q_vector->txr_count && !q_vector->rxr_count)
4018 q_vector->eitr = adapter->tx_eitr_param;
4019 else
4020 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4021 q_vector->v_idx = q_idx;
91281fd3 4022 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4023 adapter->q_vector[q_idx] = q_vector;
4024 }
4025
4026 return 0;
4027
4028err_out:
4029 while (q_idx) {
4030 q_idx--;
4031 q_vector = adapter->q_vector[q_idx];
4032 netif_napi_del(&q_vector->napi);
4033 kfree(q_vector);
4034 adapter->q_vector[q_idx] = NULL;
4035 }
4036 return -ENOMEM;
4037}
4038
4039/**
4040 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4041 * @adapter: board private structure to initialize
4042 *
4043 * This function frees the memory allocated to the q_vectors. In addition if
4044 * NAPI is enabled it will delete any references to the NAPI struct prior
4045 * to freeing the q_vector.
4046 **/
4047static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4048{
4049 int q_idx, num_q_vectors;
7a921c93 4050
91281fd3 4051 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4052 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4053 else
7a921c93 4054 num_q_vectors = 1;
7a921c93
AD		 4055
4056 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4057 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4058 adapter->q_vector[q_idx] = NULL;
91281fd3 4059 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4060 kfree(q_vector);
4061 }
4062}
4063
7b25cdba 4064static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4065{
4066 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4067 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4068 pci_disable_msix(adapter->pdev);
4069 kfree(adapter->msix_entries);
4070 adapter->msix_entries = NULL;
4071 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4072 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4073 pci_disable_msi(adapter->pdev);
4074 }
4075 return;
4076}
4077
4078/**
4079 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4080 * @adapter: board private structure to initialize
4081 *
4082 * We determine which interrupt scheme to use based on...
4083 * - Kernel support (MSI, MSI-X)
4084 * - which can be user-defined (via MODULE_PARAM)
4085 * - Hardware queue count (num_*_queues)
4086 * - defined by miscellaneous hardware support/features (RSS, etc.)
4087 **/
2f90b865 4088int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4089{
4090 int err;
4091
4092 /* Number of supported queues */
4093 ixgbe_set_num_queues(adapter);
4094
021230d4
AV		 4095 err = ixgbe_set_interrupt_capability(adapter);
4096 if (err) {
4097 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
4098 goto err_set_interrupt;
9a799d71
AK		 4099 }
4100
7a921c93
AD		 4101 err = ixgbe_alloc_q_vectors(adapter);
4102 if (err) {
4103 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
4104 "vectors\n");
4105 goto err_alloc_q_vectors;
4106 }
4107
4108 err = ixgbe_alloc_queues(adapter);
4109 if (err) {
4110 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
4111 goto err_alloc_queues;
4112 }
4113
021230d4 4114 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 4115 "Tx Queue count = %u\n",
4116 (adapter->num_rx_queues > 1) ? "Enabled" :
4117 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4118
4119 set_bit(__IXGBE_DOWN, &adapter->state);
4120
9a799d71 4121 return 0;
021230d4 4122
7a921c93
AD		 4123err_alloc_queues:
4124 ixgbe_free_q_vectors(adapter);
4125err_alloc_q_vectors:
4126 ixgbe_reset_interrupt_capability(adapter);
021230d4 4127err_set_interrupt:
7a921c93
AD		 4128 return err;
4129}
4130
4131/**
4132 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4133 * @adapter: board private structure to clear interrupt scheme on
4134 *
4135 * We go through and clear interrupt specific resources and reset the structure
4136 * to pre-load conditions
4137 **/
4138void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4139{
4a0b9ca0
PW		 4140 int i;
4141
4142 for (i = 0; i < adapter->num_tx_queues; i++) {
4143 kfree(adapter->tx_ring[i]);
4144 adapter->tx_ring[i] = NULL;
4145 }
4146 for (i = 0; i < adapter->num_rx_queues; i++) {
4147 kfree(adapter->rx_ring[i]);
4148 adapter->rx_ring[i] = NULL;
4149 }
7a921c93
AD		 4150
4151 ixgbe_free_q_vectors(adapter);
4152 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4153}
4154
c4900be0
DS		 4155/**
4156 * ixgbe_sfp_timer - worker thread to find a missing module
4157 * @data: pointer to our adapter struct
4158 **/
4159static void ixgbe_sfp_timer(unsigned long data)
4160{
4161 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4162
4df10466
JB		 4163 /*
4164 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 4165 * delays that sfp+ detection requires
4166 */
4167 schedule_work(&adapter->sfp_task);
4168}
4169
4170/**
4171 * ixgbe_sfp_task - worker thread to find a missing module
4172 * @work: pointer to work_struct containing our data
4173 **/
4174static void ixgbe_sfp_task(struct work_struct *work)
4175{
4176 struct ixgbe_adapter *adapter = container_of(work,
4177 struct ixgbe_adapter,
4178 sfp_task);
4179 struct ixgbe_hw *hw = &adapter->hw;
4180
4181 if ((hw->phy.type == ixgbe_phy_nl) &&
4182 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4183 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4184 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 4185 goto reschedule;
4186 ret = hw->phy.ops.reset(hw);
4187 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 4188 dev_err(&adapter->pdev->dev, "failed to initialize "
4189 "because an unsupported SFP+ module type "
4190 "was detected.\n"
4191 "Reload the driver after installing a "
4192 "supported module.\n");
c4900be0
DS		 4193 unregister_netdev(adapter->netdev);
4194 } else {
4195 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
4196 hw->phy.sfp_type);
4197 }
4198 /* don't need this routine any more */
4199 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4200 }
4201 return;
4202reschedule:
4203 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4204 mod_timer(&adapter->sfp_timer,
4205 round_jiffies(jiffies + (2 * HZ)));
4206}
4207
9a799d71
AK		 4208/**
4209 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4210 * @adapter: board private structure to initialize
4211 *
4212 * ixgbe_sw_init initializes the Adapter private data structure.
4213 * Fields are initialized based on PCI device information and
4214 * OS network device settings (MTU size).
4215 **/
4216static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4217{
4218 struct ixgbe_hw *hw = &adapter->hw;
4219 struct pci_dev *pdev = adapter->pdev;
9a713e7c 4220 struct net_device *dev = adapter->netdev;
021230d4 4221 unsigned int rss;
7a6b6f51 4222#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4223 int j;
4224 struct tc_configuration *tc;
4225#endif
021230d4 4226
c44ade9e
JB		 4227 /* PCI config space info */
4228
4229 hw->vendor_id = pdev->vendor;
4230 hw->device_id = pdev->device;
4231 hw->revision_id = pdev->revision;
4232 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4233 hw->subsystem_device_id = pdev->subsystem_device;
4234
021230d4
AV		 4235 /* Set capability flags */
4236 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4237 adapter->ring_feature[RING_F_RSS].indices = rss;
4238 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 4239 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 4240 if (hw->mac.type == ixgbe_mac_82598EB) {
4241 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4242 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4243 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 4244 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 4245 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4246 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4247 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
9a713e7c
PW		 4248 if (dev->features & NETIF_F_NTUPLE) {
4249 /* Flow Director perfect filter enabled */
4250 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4251 adapter->atr_sample_rate = 0;
4252 spin_lock_init(&adapter->fdir_perfect_lock);
4253 } else {
4254 /* Flow Director hash filters enabled */
4255 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4256 adapter->atr_sample_rate = 20;
4257 }
c4cf55e5
PWJ		 4258 adapter->ring_feature[RING_F_FDIR].indices =
4259 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 4260 adapter->fdir_pballoc = 0;
eacd73f7 4261#ifdef IXGBE_FCOE
0d551589
YZ		 4262 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4263 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4264 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4265#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 4266 /* Default traffic class to use for FCoE */
4267 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
61a0f421 4268#endif
eacd73f7 4269#endif /* IXGBE_FCOE */
f8212f97 4270 }
2f90b865 4271
7a6b6f51 4272#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4273 /* Configure DCB traffic classes */
4274 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4275 tc = &adapter->dcb_cfg.tc_config[j];
4276 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4277 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4278 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4279 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4280 tc->dcb_pfc = pfc_disabled;
4281 }
4282 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4283 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4284 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 4285 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 4286 adapter->dcb_cfg.round_robin_enable = false;
4287 adapter->dcb_set_bitmap = 0x00;
4288 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4289 adapter->ring_feature[RING_F_DCB].indices);
4290
4291#endif
9a799d71
AK		 4292
4293 /* default flow control settings */
cd7664f6 4294 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4295 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 4296#ifdef CONFIG_DCB
4297 adapter->last_lfc_mode = hw->fc.current_mode;
4298#endif
2b9ade93
JB		 4299 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4300 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4301 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4302 hw->fc.send_xon = true;
71fd570b 4303 hw->fc.disable_fc_autoneg = false;
9a799d71 4304
30efa5a3 4305 /* enable itr by default in dynamic mode */
f7554a2b
NS		 4306 adapter->rx_itr_setting = 1;
4307 adapter->rx_eitr_param = 20000;
4308 adapter->tx_itr_setting = 1;
4309 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 4310
4311 /* set defaults for eitr in MegaBytes */
4312 adapter->eitr_low = 10;
4313 adapter->eitr_high = 20;
4314
4315 /* set default ring sizes */
4316 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4317 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4318
9a799d71 4319 /* initialize eeprom parameters */
c44ade9e 4320 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 4321 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4322 return -EIO;
4323 }
4324
021230d4 4325 /* enable rx csum by default */
9a799d71
AK		 4326 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4327
1a6c14a2
JB		 4328 /* get assigned NUMA node */
4329 adapter->node = dev_to_node(&pdev->dev);
4330
9a799d71
AK		 4331 set_bit(__IXGBE_DOWN, &adapter->state);
4332
4333 return 0;
4334}
4335
4336/**
4337 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4338 * @adapter: board private structure
3a581073 4339 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4340 *
4341 * Return 0 on success, negative on failure
4342 **/
4343int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 4344 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4345{
4346 struct pci_dev *pdev = adapter->pdev;
4347 int size;
4348
3a581073 4349 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4a0b9ca0 4350 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
1a6c14a2
JB		 4351 if (!tx_ring->tx_buffer_info)
4352 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 4353 if (!tx_ring->tx_buffer_info)
4354 goto err;
3a581073 4355 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 4356
4357 /* round up to nearest 4K */
12207e49 4358 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4359 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4360
3a581073
JB		 4361 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
4362 &tx_ring->dma);
e01c31a5
JB		 4363 if (!tx_ring->desc)
4364 goto err;
9a799d71 4365
3a581073
JB		 4366 tx_ring->next_to_use = 0;
4367 tx_ring->next_to_clean = 0;
4368 tx_ring->work_limit = tx_ring->count;
9a799d71 4369 return 0;
e01c31a5
JB		 4370
4371err:
4372 vfree(tx_ring->tx_buffer_info);
4373 tx_ring->tx_buffer_info = NULL;
4374 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4375 "descriptor ring\n");
4376 return -ENOMEM;
9a799d71
AK		 4377}
4378
69888674
AD		 4379/**
4380 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4381 * @adapter: board private structure
4382 *
4383 * If this function returns with an error, then it's possible one or
4384 * more of the rings is populated (while the rest are not). It is the
4385 * callers duty to clean those orphaned rings.
4386 *
4387 * Return 0 on success, negative on failure
4388 **/
4389static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4390{
4391 int i, err = 0;
4392
4393 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 4394 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
69888674
AD		 4395 if (!err)
4396 continue;
4397 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4398 break;
4399 }
4400
4401 return err;
4402}
4403
9a799d71
AK		 4404/**
4405 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4406 * @adapter: board private structure
3a581073 4407 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4408 *
4409 * Returns 0 on success, negative on failure
4410 **/
4411int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 4412 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4413{
4414 struct pci_dev *pdev = adapter->pdev;
021230d4 4415 int size;
9a799d71 4416
3a581073 4417 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
1a6c14a2
JB		 4418 rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4419 if (!rx_ring->rx_buffer_info)
4420 rx_ring->rx_buffer_info = vmalloc(size);
3a581073 4421 if (!rx_ring->rx_buffer_info) {
9a799d71 4422 DPRINTK(PROBE, ERR,
b4617240 4423 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 4424 goto alloc_failed;
9a799d71 4425 }
3a581073 4426 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 4427
9a799d71 4428 /* Round up to nearest 4K */
3a581073
JB		 4429 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4430 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4431
3a581073 4432 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 4433
3a581073 4434 if (!rx_ring->desc) {
9a799d71 4435 DPRINTK(PROBE, ERR,
b4617240 4436 "Memory allocation failed for the rx desc ring\n");
3a581073 4437 vfree(rx_ring->rx_buffer_info);
177db6ff 4438 goto alloc_failed;
9a799d71
AK		 4439 }
4440
3a581073
JB		 4441 rx_ring->next_to_clean = 0;
4442 rx_ring->next_to_use = 0;
9a799d71
AK		 4443
4444 return 0;
177db6ff
MC		 4445
4446alloc_failed:
177db6ff 4447 return -ENOMEM;
9a799d71
AK		 4448}
4449
69888674
AD		 4450/**
4451 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4452 * @adapter: board private structure
4453 *
4454 * If this function returns with an error, then it's possible one or
4455 * more of the rings is populated (while the rest are not). It is the
4456 * callers duty to clean those orphaned rings.
4457 *
4458 * Return 0 on success, negative on failure
4459 **/
4460
4461static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4462{
4463 int i, err = 0;
4464
4465 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 4466 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
69888674
AD		 4467 if (!err)
4468 continue;
4469 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4470 break;
4471 }
4472
4473 return err;
4474}
4475
9a799d71
AK		 4476/**
4477 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4478 * @adapter: board private structure
4479 * @tx_ring: Tx descriptor ring for a specific queue
4480 *
4481 * Free all transmit software resources
4482 **/
c431f97e
JB		 4483void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4484 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4485{
4486 struct pci_dev *pdev = adapter->pdev;
4487
4488 ixgbe_clean_tx_ring(adapter, tx_ring);
4489
4490 vfree(tx_ring->tx_buffer_info);
4491 tx_ring->tx_buffer_info = NULL;
4492
4493 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4494
4495 tx_ring->desc = NULL;
4496}
4497
4498/**
4499 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4500 * @adapter: board private structure
4501 *
4502 * Free all transmit software resources
4503 **/
4504static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4505{
4506 int i;
4507
4508 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0
PW		 4509 if (adapter->tx_ring[i]->desc)
4510 ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
9a799d71
AK		 4511}
4512
4513/**
b4617240 4514 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4515 * @adapter: board private structure
4516 * @rx_ring: ring to clean the resources from
4517 *
4518 * Free all receive software resources
4519 **/
c431f97e
JB		 4520void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4521 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4522{
4523 struct pci_dev *pdev = adapter->pdev;
4524
4525 ixgbe_clean_rx_ring(adapter, rx_ring);
4526
4527 vfree(rx_ring->rx_buffer_info);
4528 rx_ring->rx_buffer_info = NULL;
4529
4530 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4531
4532 rx_ring->desc = NULL;
4533}
4534
4535/**
4536 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4537 * @adapter: board private structure
4538 *
4539 * Free all receive software resources
4540 **/
4541static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4542{
4543 int i;
4544
4545 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 4546 if (adapter->rx_ring[i]->desc)
4547 ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
9a799d71
AK		 4548}
4549
9a799d71
AK		 4550/**
4551 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4552 * @netdev: network interface device structure
4553 * @new_mtu: new value for maximum frame size
4554 *
4555 * Returns 0 on success, negative on failure
4556 **/
4557static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4558{
4559 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4560 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4561
42c783c5
JB		 4562 /* MTU < 68 is an error and causes problems on some kernels */
4563 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 4564 return -EINVAL;
4565
021230d4 4566 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 4567 netdev->mtu, new_mtu);
021230d4 4568 /* must set new MTU before calling down or up */
9a799d71
AK		 4569 netdev->mtu = new_mtu;
4570
d4f80882
AV		 4571 if (netif_running(netdev))
4572 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4573
4574 return 0;
4575}
4576
4577/**
4578 * ixgbe_open - Called when a network interface is made active
4579 * @netdev: network interface device structure
4580 *
4581 * Returns 0 on success, negative value on failure
4582 *
4583 * The open entry point is called when a network interface is made
4584 * active by the system (IFF_UP). At this point all resources needed
4585 * for transmit and receive operations are allocated, the interrupt
4586 * handler is registered with the OS, the watchdog timer is started,
4587 * and the stack is notified that the interface is ready.
4588 **/
4589static int ixgbe_open(struct net_device *netdev)
4590{
4591 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4592 int err;
4bebfaa5
AK		 4593
4594 /* disallow open during test */
4595 if (test_bit(__IXGBE_TESTING, &adapter->state))
4596 return -EBUSY;
9a799d71 4597
54386467
JB		 4598 netif_carrier_off(netdev);
4599
9a799d71
AK		 4600 /* allocate transmit descriptors */
4601 err = ixgbe_setup_all_tx_resources(adapter);
4602 if (err)
4603 goto err_setup_tx;
4604
9a799d71
AK		 4605 /* allocate receive descriptors */
4606 err = ixgbe_setup_all_rx_resources(adapter);
4607 if (err)
4608 goto err_setup_rx;
4609
4610 ixgbe_configure(adapter);
4611
021230d4 4612 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4613 if (err)
4614 goto err_req_irq;
4615
9a799d71
AK		 4616 err = ixgbe_up_complete(adapter);
4617 if (err)
4618 goto err_up;
4619
d55b53ff
JK		 4620 netif_tx_start_all_queues(netdev);
4621
9a799d71
AK		 4622 return 0;
4623
4624err_up:
5eba3699 4625 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4626 ixgbe_free_irq(adapter);
4627err_req_irq:
9a799d71 4628err_setup_rx:
a20a1199 4629 ixgbe_free_all_rx_resources(adapter);
9a799d71 4630err_setup_tx:
a20a1199 4631 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 4632 ixgbe_reset(adapter);
4633
4634 return err;
4635}
4636
4637/**
4638 * ixgbe_close - Disables a network interface
4639 * @netdev: network interface device structure
4640 *
4641 * Returns 0, this is not allowed to fail
4642 *
4643 * The close entry point is called when an interface is de-activated
4644 * by the OS. The hardware is still under the drivers control, but
4645 * needs to be disabled. A global MAC reset is issued to stop the
4646 * hardware, and all transmit and receive resources are freed.
4647 **/
4648static int ixgbe_close(struct net_device *netdev)
4649{
4650 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4651
4652 ixgbe_down(adapter);
4653 ixgbe_free_irq(adapter);
4654
4655 ixgbe_free_all_tx_resources(adapter);
4656 ixgbe_free_all_rx_resources(adapter);
4657
5eba3699 4658 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4659
4660 return 0;
4661}
4662
b3c8b4ba
AD		 4663#ifdef CONFIG_PM
4664static int ixgbe_resume(struct pci_dev *pdev)
4665{
4666 struct net_device *netdev = pci_get_drvdata(pdev);
4667 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4668 u32 err;
4669
4670 pci_set_power_state(pdev, PCI_D0);
4671 pci_restore_state(pdev);
656ab817
DS		 4672 /*
4673 * pci_restore_state clears dev->state_saved so call
4674 * pci_save_state to restore it.
4675 */
4676 pci_save_state(pdev);
9ce77666 4677
4678 err = pci_enable_device_mem(pdev);
b3c8b4ba 4679 if (err) {
69888674 4680 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 4681 "suspend\n");
4682 return err;
4683 }
4684 pci_set_master(pdev);
4685
dd4d8ca6 4686 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 4687
4688 err = ixgbe_init_interrupt_scheme(adapter);
4689 if (err) {
4690 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4691 "device\n");
4692 return err;
4693 }
4694
b3c8b4ba
AD		 4695 ixgbe_reset(adapter);
4696
495dce12
WJP		 4697 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4698
b3c8b4ba
AD		 4699 if (netif_running(netdev)) {
4700 err = ixgbe_open(adapter->netdev);
4701 if (err)
4702 return err;
4703 }
4704
4705 netif_device_attach(netdev);
4706
4707 return 0;
4708}
b3c8b4ba 4709#endif /* CONFIG_PM */
9d8d05ae
RW		 4710
4711static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 4712{
4713 struct net_device *netdev = pci_get_drvdata(pdev);
4714 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 4715 struct ixgbe_hw *hw = &adapter->hw;
4716 u32 ctrl, fctrl;
4717 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4718#ifdef CONFIG_PM
4719 int retval = 0;
4720#endif
4721
4722 netif_device_detach(netdev);
4723
4724 if (netif_running(netdev)) {
4725 ixgbe_down(adapter);
4726 ixgbe_free_irq(adapter);
4727 ixgbe_free_all_tx_resources(adapter);
4728 ixgbe_free_all_rx_resources(adapter);
4729 }
7a921c93 4730 ixgbe_clear_interrupt_scheme(adapter);
b3c8b4ba
AD		 4731
4732#ifdef CONFIG_PM
4733 retval = pci_save_state(pdev);
4734 if (retval)
4735 return retval;
4df10466 4736
b3c8b4ba 4737#endif
e8e26350
PW		 4738 if (wufc) {
4739 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4740
e8e26350
PW		 4741 /* turn on all-multi mode if wake on multicast is enabled */
4742 if (wufc & IXGBE_WUFC_MC) {
4743 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4744 fctrl |= IXGBE_FCTRL_MPE;
4745 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4746 }
4747
4748 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4749 ctrl |= IXGBE_CTRL_GIO_DIS;
4750 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4751
4752 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4753 } else {
4754 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4755 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4756 }
4757
dd4d8ca6
DS		 4758 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4759 pci_wake_from_d3(pdev, true);
4760 else
4761 pci_wake_from_d3(pdev, false);
b3c8b4ba 4762
9d8d05ae
RW		 4763 *enable_wake = !!wufc;
4764
b3c8b4ba
AD		 4765 ixgbe_release_hw_control(adapter);
4766
4767 pci_disable_device(pdev);
4768
9d8d05ae
RW		 4769 return 0;
4770}
4771
4772#ifdef CONFIG_PM
4773static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4774{
4775 int retval;
4776 bool wake;
4777
4778 retval = __ixgbe_shutdown(pdev, &wake);
4779 if (retval)
4780 return retval;
4781
4782 if (wake) {
4783 pci_prepare_to_sleep(pdev);
4784 } else {
4785 pci_wake_from_d3(pdev, false);
4786 pci_set_power_state(pdev, PCI_D3hot);
4787 }
b3c8b4ba
AD		 4788
4789 return 0;
4790}
9d8d05ae 4791#endif /* CONFIG_PM */
b3c8b4ba
AD		 4792
4793static void ixgbe_shutdown(struct pci_dev *pdev)
4794{
9d8d05ae
RW		 4795 bool wake;
4796
4797 __ixgbe_shutdown(pdev, &wake);
4798
4799 if (system_state == SYSTEM_POWER_OFF) {
4800 pci_wake_from_d3(pdev, wake);
4801 pci_set_power_state(pdev, PCI_D3hot);
4802 }
b3c8b4ba
AD		 4803}
4804
9a799d71
AK		 4805/**
4806 * ixgbe_update_stats - Update the board statistics counters.
4807 * @adapter: board private structure
4808 **/
4809void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4810{
2d86f139 4811 struct net_device *netdev = adapter->netdev;
9a799d71 4812 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 4813 u64 total_mpc = 0;
4814 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
eb985f09 4815 u64 non_eop_descs = 0, restart_queue = 0;
9a799d71 4816
94b982b2 4817 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 4818 u64 rsc_count = 0;
94b982b2 4819 u64 rsc_flush = 0;
d51019a4
PW		 4820 for (i = 0; i < 16; i++)
4821 adapter->hw_rx_no_dma_resources +=
4822 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 4823 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 4824 rsc_count += adapter->rx_ring[i]->rsc_count;
4825 rsc_flush += adapter->rx_ring[i]->rsc_flush;
94b982b2
MC		 4826 }
4827 adapter->rsc_total_count = rsc_count;
4828 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 4829 }
4830
7ca3bc58
JB		 4831 /* gather some stats to the adapter struct that are per queue */
4832 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4833 restart_queue += adapter->tx_ring[i]->restart_queue;
eb985f09 4834 adapter->restart_queue = restart_queue;
7ca3bc58
JB		 4835
4836 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4837 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
eb985f09 4838 adapter->non_eop_descs = non_eop_descs;
7ca3bc58 4839
9a799d71 4840 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 4841 for (i = 0; i < 8; i++) {
4842 /* for packet buffers not used, the register should read 0 */
4843 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4844 missed_rx += mpc;
4845 adapter->stats.mpc[i] += mpc;
4846 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 4847 if (hw->mac.type == ixgbe_mac_82598EB)
4848 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 4849 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4850 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4851 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4852 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 4853 if (hw->mac.type == ixgbe_mac_82599EB) {
4854 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4855 IXGBE_PXONRXCNT(i));
4856 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4857 IXGBE_PXOFFRXCNT(i));
4858 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 4859 } else {
4860 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4861 IXGBE_PXONRXC(i));
4862 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4863 IXGBE_PXOFFRXC(i));
4864 }
2f90b865
AD		 4865 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4866 IXGBE_PXONTXC(i));
2f90b865 4867 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 4868 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 4869 }
4870 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4871 /* work around hardware counting issue */
4872 adapter->stats.gprc -= missed_rx;
4873
4874 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350 4875 if (hw->mac.type == ixgbe_mac_82599EB) {
aad71918 4876 u64 tmp;
e8e26350 4877 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
aad71918
BG		 4878 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4879 adapter->stats.gorc += (tmp << 32);
e8e26350 4880 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
aad71918
BG		 4881 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4882 adapter->stats.gotc += (tmp << 32);
e8e26350
PW		 4883 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4884 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4885 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4886 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
c4cf55e5
PWJ		 4887 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4888 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c
YZ		 4889#ifdef IXGBE_FCOE
4890 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4891 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4892 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4893 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4894 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4895 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4896#endif /* IXGBE_FCOE */
e8e26350
PW		 4897 } else {
4898 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4899 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4900 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4901 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4902 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4903 }
9a799d71
AK		 4904 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4905 adapter->stats.bprc += bprc;
4906 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 4907 if (hw->mac.type == ixgbe_mac_82598EB)
4908 adapter->stats.mprc -= bprc;
9a799d71
AK		 4909 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4910 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4911 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4912 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4913 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4914 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4915 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 4916 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 4917 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4918 adapter->stats.lxontxc += lxon;
4919 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4920 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 4921 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4922 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 4923 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4924 /*
4925 * 82598 errata - tx of flow control packets is included in tx counters
4926 */
4927 xon_off_tot = lxon + lxoff;
4928 adapter->stats.gptc -= xon_off_tot;
4929 adapter->stats.mptc -= xon_off_tot;
4930 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 4931 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4932 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4933 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 4934 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4935 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 4936 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 4937 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4938 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4939 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4940 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4941 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 4942 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4943
4944 /* Fill out the OS statistics structure */
2d86f139 4945 netdev->stats.multicast = adapter->stats.mprc;
9a799d71
AK		 4946
4947 /* Rx Errors */
2d86f139 4948 netdev->stats.rx_errors = adapter->stats.crcerrs +
b4617240 4949 adapter->stats.rlec;
2d86f139
AK		 4950 netdev->stats.rx_dropped = 0;
4951 netdev->stats.rx_length_errors = adapter->stats.rlec;
4952 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4953 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 4954}
4955
4956/**
4957 * ixgbe_watchdog - Timer Call-back
4958 * @data: pointer to adapter cast into an unsigned long
4959 **/
4960static void ixgbe_watchdog(unsigned long data)
4961{
4962 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 4963 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 4964 u64 eics = 0;
4965 int i;
cf8280ee 4966
fe49f04a
AD		 4967 /*
4968 * Do the watchdog outside of interrupt context due to the lovely
4969 * delays that some of the newer hardware requires
4970 */
22d5a71b 4971
fe49f04a
AD		 4972 if (test_bit(__IXGBE_DOWN, &adapter->state))
4973 goto watchdog_short_circuit;
22d5a71b 4974
fe49f04a
AD		 4975 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4976 /*
4977 * for legacy and MSI interrupts don't set any bits
4978 * that are enabled for EIAM, because this operation
4979 * would set *both* EIMS and EICS for any bit in EIAM
4980 */
4981 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4982 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4983 goto watchdog_reschedule;
4984 }
4985
4986 /* get one bit for every active tx/rx interrupt vector */
4987 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4988 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4989 if (qv->rxr_count || qv->txr_count)
4990 eics |= ((u64)1 << i);
cf8280ee 4991 }
9a799d71 4992
fe49f04a
AD		 4993 /* Cause software interrupt to ensure rx rings are cleaned */
4994 ixgbe_irq_rearm_queues(adapter, eics);
4995
4996watchdog_reschedule:
4997 /* Reset the timer */
4998 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4999
5000watchdog_short_circuit:
cf8280ee
JB		 5001 schedule_work(&adapter->watchdog_task);
5002}
5003
e8e26350
PW		 5004/**
5005 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5006 * @work: pointer to work_struct containing our data
5007 **/
5008static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5009{
5010 struct ixgbe_adapter *adapter = container_of(work,
5011 struct ixgbe_adapter,
5012 multispeed_fiber_task);
5013 struct ixgbe_hw *hw = &adapter->hw;
5014 u32 autoneg;
8620a103 5015 bool negotiation;
e8e26350
PW		 5016
5017 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 5018 autoneg = hw->phy.autoneg_advertised;
5019 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103
MC		 5020 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5021 if (hw->mac.ops.setup_link)
5022 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 5023 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5024 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5025}
5026
5027/**
5028 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5029 * @work: pointer to work_struct containing our data
5030 **/
5031static void ixgbe_sfp_config_module_task(struct work_struct *work)
5032{
5033 struct ixgbe_adapter *adapter = container_of(work,
5034 struct ixgbe_adapter,
5035 sfp_config_module_task);
5036 struct ixgbe_hw *hw = &adapter->hw;
5037 u32 err;
5038
5039 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 5040
5041 /* Time for electrical oscillations to settle down */
5042 msleep(100);
e8e26350 5043 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5044
e8e26350 5045 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 5046 dev_err(&adapter->pdev->dev, "failed to initialize because "
5047 "an unsupported SFP+ module type was detected.\n"
5048 "Reload the driver after installing a supported "
5049 "module.\n");
63d6e1d8 5050 unregister_netdev(adapter->netdev);
e8e26350
PW		 5051 return;
5052 }
5053 hw->mac.ops.setup_sfp(hw);
5054
8d1c3c07 5055 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 5056 /* This will also work for DA Twinax connections */
5057 schedule_work(&adapter->multispeed_fiber_task);
5058 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5059}
5060
c4cf55e5
PWJ		 5061/**
5062 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5063 * @work: pointer to work_struct containing our data
5064 **/
5065static void ixgbe_fdir_reinit_task(struct work_struct *work)
5066{
5067 struct ixgbe_adapter *adapter = container_of(work,
5068 struct ixgbe_adapter,
5069 fdir_reinit_task);
5070 struct ixgbe_hw *hw = &adapter->hw;
5071 int i;
5072
5073 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5074 for (i = 0; i < adapter->num_tx_queues; i++)
5075 set_bit(__IXGBE_FDIR_INIT_DONE,
4a0b9ca0 5076 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5
PWJ		 5077 } else {
5078 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
5079 "ignored adding FDIR ATR filters \n");
5080 }
5081 /* Done FDIR Re-initialization, enable transmits */
5082 netif_tx_start_all_queues(adapter->netdev);
5083}
5084
10eec955
JF		 5085static DEFINE_MUTEX(ixgbe_watchdog_lock);
5086
cf8280ee 5087/**
69888674
AD		 5088 * ixgbe_watchdog_task - worker thread to bring link up
5089 * @work: pointer to work_struct containing our data
cf8280ee
JB		 5090 **/
5091static void ixgbe_watchdog_task(struct work_struct *work)
5092{
5093 struct ixgbe_adapter *adapter = container_of(work,
5094 struct ixgbe_adapter,
5095 watchdog_task);
5096 struct net_device *netdev = adapter->netdev;
5097 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 5098 u32 link_speed;
5099 bool link_up;
bc59fcda
NS		 5100 int i;
5101 struct ixgbe_ring *tx_ring;
5102 int some_tx_pending = 0;
cf8280ee 5103
10eec955
JF		 5104 mutex_lock(&ixgbe_watchdog_lock);
5105
5106 link_up = adapter->link_up;
5107 link_speed = adapter->link_speed;
cf8280ee
JB		 5108
5109 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5110 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 5111 if (link_up) {
5112#ifdef CONFIG_DCB
5113 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5114 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 5115 hw->mac.ops.fc_enable(hw, i);
264857b8 5116 } else {
620fa036 5117 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5118 }
5119#else
620fa036 5120 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5121#endif
5122 }
5123
cf8280ee
JB		 5124 if (link_up ||
5125 time_after(jiffies, (adapter->link_check_timeout +
5126 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 5127 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 5128 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 5129 }
5130 adapter->link_up = link_up;
5131 adapter->link_speed = link_speed;
5132 }
9a799d71
AK		 5133
5134 if (link_up) {
5135 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 5136 bool flow_rx, flow_tx;
5137
5138 if (hw->mac.type == ixgbe_mac_82599EB) {
5139 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5140 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 5141 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5142 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 5143 } else {
5144 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5145 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 5146 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5147 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 5148 }
5149
a46e534b
JK		 5150 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
5151 "Flow Control: %s\n",
5152 netdev->name,
5153 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5154 "10 Gbps" :
5155 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5156 "1 Gbps" : "unknown speed")),
e8e26350
PW		 5157 ((flow_rx && flow_tx) ? "RX/TX" :
5158 (flow_rx ? "RX" :
5159 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 5160
5161 netif_carrier_on(netdev);
9a799d71
AK		 5162 } else {
5163 /* Force detection of hung controller */
5164 adapter->detect_tx_hung = true;
5165 }
5166 } else {
cf8280ee
JB		 5167 adapter->link_up = false;
5168 adapter->link_speed = 0;
9a799d71 5169 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 5170 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
5171 netdev->name);
9a799d71 5172 netif_carrier_off(netdev);
9a799d71
AK		 5173 }
5174 }
5175
bc59fcda
NS		 5176 if (!netif_carrier_ok(netdev)) {
5177 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 5178 tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5179 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5180 some_tx_pending = 1;
5181 break;
5182 }
5183 }
5184
5185 if (some_tx_pending) {
5186 /* We've lost link, so the controller stops DMA,
5187 * but we've got queued Tx work that's never going
5188 * to get done, so reset controller to flush Tx.
5189 * (Do the reset outside of interrupt context).
5190 */
5191 schedule_work(&adapter->reset_task);
5192 }
5193 }
5194
9a799d71 5195 ixgbe_update_stats(adapter);
10eec955 5196 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 5197}
5198
9a799d71 5199static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 5200 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5201 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 5202{
5203 struct ixgbe_adv_tx_context_desc *context_desc;
5204 unsigned int i;
5205 int err;
5206 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 5207 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5208 u32 mss_l4len_idx, l4len;
9a799d71
AK		 5209
5210 if (skb_is_gso(skb)) {
5211 if (skb_header_cloned(skb)) {
5212 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5213 if (err)
5214 return err;
5215 }
5216 l4len = tcp_hdrlen(skb);
5217 *hdr_len += l4len;
5218
8327d000 5219 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 5220 struct iphdr *iph = ip_hdr(skb);
5221 iph->tot_len = 0;
5222 iph->check = 0;
5223 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 5224 iph->daddr, 0,
5225 IPPROTO_TCP,
5226 0);
8e1e8a47 5227 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 5228 ipv6_hdr(skb)->payload_len = 0;
5229 tcp_hdr(skb)->check =
5230 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 5231 &ipv6_hdr(skb)->daddr,
5232 0, IPPROTO_TCP, 0);
9a799d71
AK		 5233 }
5234
5235 i = tx_ring->next_to_use;
5236
5237 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5238 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5239
5240 /* VLAN MACLEN IPLEN */
5241 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5242 vlan_macip_lens |=
5243 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5244 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 5245 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5246 *hdr_len += skb_network_offset(skb);
5247 vlan_macip_lens |=
5248 (skb_transport_header(skb) - skb_network_header(skb));
5249 *hdr_len +=
5250 (skb_transport_header(skb) - skb_network_header(skb));
5251 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5252 context_desc->seqnum_seed = 0;
5253
5254 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 5255 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 5256 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 5257
8327d000 5258 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 5259 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5260 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5261 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5262
5263 /* MSS L4LEN IDX */
9f8cdf4f 5264 mss_l4len_idx =
9a799d71
AK		 5265 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5266 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 5267 /* use index 1 for TSO */
5268 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5269 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5270
5271 tx_buffer_info->time_stamp = jiffies;
5272 tx_buffer_info->next_to_watch = i;
5273
5274 i++;
5275 if (i == tx_ring->count)
5276 i = 0;
5277 tx_ring->next_to_use = i;
5278
5279 return true;
5280 }
5281 return false;
5282}
5283
5284static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 5285 struct ixgbe_ring *tx_ring,
5286 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 5287{
5288 struct ixgbe_adv_tx_context_desc *context_desc;
5289 unsigned int i;
5290 struct ixgbe_tx_buffer *tx_buffer_info;
5291 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5292
5293 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5294 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5295 i = tx_ring->next_to_use;
5296 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5297 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5298
5299 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5300 vlan_macip_lens |=
5301 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5302 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 5303 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5304 if (skb->ip_summed == CHECKSUM_PARTIAL)
5305 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 5306 skb_network_header(skb));
9a799d71
AK		 5307
5308 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5309 context_desc->seqnum_seed = 0;
5310
5311 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 5312 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 5313
5314 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ca553980
GS		 5315 __be16 protocol;
5316
5317 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5318 const struct vlan_ethhdr *vhdr =
5319 (const struct vlan_ethhdr *)skb->data;
5320
5321 protocol = vhdr->h_vlan_encapsulated_proto;
5322 } else {
5323 protocol = skb->protocol;
5324 }
5325
5326 switch (protocol) {
09640e63 5327 case cpu_to_be16(ETH_P_IP):
9a799d71 5328 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 5329 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5330 type_tucmd_mlhl |=
b4617240 5331 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5332 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5333 type_tucmd_mlhl |=
5334 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5335 break;
09640e63 5336 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 5337 /* XXX what about other V6 headers?? */
5338 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5339 type_tucmd_mlhl |=
b4617240 5340 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5341 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5342 type_tucmd_mlhl |=
5343 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5344 break;
41825d71
AK		 5345 default:
5346 if (unlikely(net_ratelimit())) {
5347 DPRINTK(PROBE, WARNING,
5348 "partial checksum but proto=%x!\n",
5349 skb->protocol);
5350 }
5351 break;
5352 }
9a799d71
AK		 5353 }
5354
5355 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 5356 /* use index zero for tx checksum offload */
9a799d71
AK		 5357 context_desc->mss_l4len_idx = 0;
5358
5359 tx_buffer_info->time_stamp = jiffies;
5360 tx_buffer_info->next_to_watch = i;
9f8cdf4f 5361
9a799d71
AK		 5362 i++;
5363 if (i == tx_ring->count)
5364 i = 0;
5365 tx_ring->next_to_use = i;
5366
5367 return true;
5368 }
9f8cdf4f 5369
9a799d71
AK		 5370 return false;
5371}
5372
5373static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 5374 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 5375 struct sk_buff *skb, u32 tx_flags,
5376 unsigned int first)
9a799d71 5377{
e5a43549 5378 struct pci_dev *pdev = adapter->pdev;
9a799d71 5379 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 5380 unsigned int len;
5381 unsigned int total = skb->len;
9a799d71
AK		 5382 unsigned int offset = 0, size, count = 0, i;
5383 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5384 unsigned int f;
9a799d71
AK		 5385
5386 i = tx_ring->next_to_use;
5387
eacd73f7
YZ		 5388 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5389 /* excluding fcoe_crc_eof for FCoE */
5390 total -= sizeof(struct fcoe_crc_eof);
5391
5392 len = min(skb_headlen(skb), total);
9a799d71
AK		 5393 while (len) {
5394 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5395 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5396
5397 tx_buffer_info->length = size;
e5a43549
AD		 5398 tx_buffer_info->mapped_as_page = false;
5399 tx_buffer_info->dma = pci_map_single(pdev,
5400 skb->data + offset,
5401 size, PCI_DMA_TODEVICE);
5402 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5403 goto dma_error;
9a799d71
AK		 5404 tx_buffer_info->time_stamp = jiffies;
5405 tx_buffer_info->next_to_watch = i;
5406
5407 len -= size;
eacd73f7 5408 total -= size;
9a799d71
AK		 5409 offset += size;
5410 count++;
44df32c5
AD		 5411
5412 if (len) {
5413 i++;
5414 if (i == tx_ring->count)
5415 i = 0;
5416 }
9a799d71
AK		 5417 }
5418
5419 for (f = 0; f < nr_frags; f++) {
5420 struct skb_frag_struct *frag;
5421
5422 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 5423 len = min((unsigned int)frag->size, total);
e5a43549 5424 offset = frag->page_offset;
9a799d71
AK		 5425
5426 while (len) {
44df32c5
AD		 5427 i++;
5428 if (i == tx_ring->count)
5429 i = 0;
5430
9a799d71
AK		 5431 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5432 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5433
5434 tx_buffer_info->length = size;
e5a43549
AD		 5435 tx_buffer_info->dma = pci_map_page(adapter->pdev,
5436 frag->page,
5437 offset, size,
5438 PCI_DMA_TODEVICE);
5439 tx_buffer_info->mapped_as_page = true;
5440 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5441 goto dma_error;
9a799d71
AK		 5442 tx_buffer_info->time_stamp = jiffies;
5443 tx_buffer_info->next_to_watch = i;
5444
5445 len -= size;
eacd73f7 5446 total -= size;
9a799d71
AK		 5447 offset += size;
5448 count++;
9a799d71 5449 }
eacd73f7
YZ		 5450 if (total == 0)
5451 break;
9a799d71 5452 }
44df32c5 5453
9a799d71
AK		 5454 tx_ring->tx_buffer_info[i].skb = skb;
5455 tx_ring->tx_buffer_info[first].next_to_watch = i;
5456
e5a43549
AD		 5457 return count;
5458
5459dma_error:
5460 dev_err(&pdev->dev, "TX DMA map failed\n");
5461
5462 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5463 tx_buffer_info->dma = 0;
5464 tx_buffer_info->time_stamp = 0;
5465 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 5466 if (count)
5467 count--;
e5a43549
AD		 5468
5469 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f
RK		 5470 while (count--) {
5471 if (i==0)
e5a43549 5472 i += tx_ring->count;
c1fa347f 5473 i--;
e5a43549
AD		 5474 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5475 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5476 }
5477
e44d38e1 5478 return 0;
9a799d71
AK		 5479}
5480
5481static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 5482 struct ixgbe_ring *tx_ring,
5483 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 5484{
5485 union ixgbe_adv_tx_desc *tx_desc = NULL;
5486 struct ixgbe_tx_buffer *tx_buffer_info;
5487 u32 olinfo_status = 0, cmd_type_len = 0;
5488 unsigned int i;
5489 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5490
5491 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5492
5493 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5494
5495 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5496 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5497
5498 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5499 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5500
5501 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5502 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5503
4eeae6fd
PW		 5504 /* use index 1 context for tso */
5505 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5506 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5507 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 5508 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 5509
5510 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5511 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5512 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5513
eacd73f7
YZ		 5514 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5515 olinfo_status |= IXGBE_ADVTXD_CC;
5516 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5517 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5518 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5519 }
5520
9a799d71
AK		 5521 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5522
5523 i = tx_ring->next_to_use;
5524 while (count--) {
5525 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5526 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5527 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5528 tx_desc->read.cmd_type_len =
b4617240 5529 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 5530 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 5531 i++;
5532 if (i == tx_ring->count)
5533 i = 0;
5534 }
5535
5536 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5537
5538 /*
5539 * Force memory writes to complete before letting h/w
5540 * know there are new descriptors to fetch. (Only
5541 * applicable for weak-ordered memory model archs,
5542 * such as IA-64).
5543 */
5544 wmb();
5545
5546 tx_ring->next_to_use = i;
5547 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5548}
5549
c4cf55e5
PWJ		 5550static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5551 int queue, u32 tx_flags)
5552{
5553 /* Right now, we support IPv4 only */
5554 struct ixgbe_atr_input atr_input;
5555 struct tcphdr *th;
c4cf55e5
PWJ		 5556 struct iphdr *iph = ip_hdr(skb);
5557 struct ethhdr *eth = (struct ethhdr *)skb->data;
5558 u16 vlan_id, src_port, dst_port, flex_bytes;
5559 u32 src_ipv4_addr, dst_ipv4_addr;
5560 u8 l4type = 0;
5561
5562 /* check if we're UDP or TCP */
5563 if (iph->protocol == IPPROTO_TCP) {
5564 th = tcp_hdr(skb);
5565 src_port = th->source;
5566 dst_port = th->dest;
5567 l4type |= IXGBE_ATR_L4TYPE_TCP;
5568 /* l4type IPv4 type is 0, no need to assign */
c4cf55e5
PWJ		 5569 } else {
5570 /* Unsupported L4 header, just bail here */
5571 return;
5572 }
5573
5574 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5575
5576 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5577 IXGBE_TX_FLAGS_VLAN_SHIFT;
5578 src_ipv4_addr = iph->saddr;
5579 dst_ipv4_addr = iph->daddr;
5580 flex_bytes = eth->h_proto;
5581
5582 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5583 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5584 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5585 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5586 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5587 /* src and dst are inverted, think how the receiver sees them */
5588 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5589 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5590
5591 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5592 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5593}
5594
e092be60 5595static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5596 struct ixgbe_ring *tx_ring, int size)
e092be60 5597{
30eba97a 5598 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5599 /* Herbert's original patch had:
5600 * smp_mb__after_netif_stop_queue();
5601 * but since that doesn't exist yet, just open code it. */
5602 smp_mb();
5603
5604 /* We need to check again in a case another CPU has just
5605 * made room available. */
5606 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5607 return -EBUSY;
5608
5609 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 5610 netif_start_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 5611 ++tx_ring->restart_queue;
e092be60
AV		 5612 return 0;
5613}
5614
5615static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5616 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 5617{
5618 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5619 return 0;
5620 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5621}
5622
09a3b1f8
SH		 5623static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5624{
5625 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 5626 int txq = smp_processor_id();
09a3b1f8 5627
fdd3d631
KK		 5628 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
5629 while (unlikely(txq >= dev->real_num_tx_queues))
5630 txq -= dev->real_num_tx_queues;
5f715823 5631 return txq;
fdd3d631 5632 }
c4cf55e5 5633
5f715823
YZ		 5634#ifdef IXGBE_FCOE
5635 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5636 (skb->protocol == htons(ETH_P_FCOE))) {
5637 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5638 txq += adapter->ring_feature[RING_F_FCOE].mask;
5639 return txq;
5640 }
5641#endif
09a3b1f8 5642 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
36e89d73 5643 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
09a3b1f8
SH		 5644
5645 return skb_tx_hash(dev, skb);
5646}
5647
3b29a56d
SH		 5648static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5649 struct net_device *netdev)
9a799d71
AK		 5650{
5651 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5652 struct ixgbe_ring *tx_ring;
60d51134 5653 struct netdev_queue *txq;
9a799d71
AK		 5654 unsigned int first;
5655 unsigned int tx_flags = 0;
30eba97a 5656 u8 hdr_len = 0;
5f715823 5657 int tso;
9a799d71
AK		 5658 int count = 0;
5659 unsigned int f;
9f8cdf4f 5660
9f8cdf4f
JB		 5661 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5662 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 5663 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5664 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5f715823 5665 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
2f90b865
AD		 5666 }
5667 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5668 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5669 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
60127865 5670 if (skb->priority != TC_PRIO_CONTROL) {
5f715823 5671 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
60127865
LL		 5672 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5673 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5674 } else {
5675 skb->queue_mapping =
5676 adapter->ring_feature[RING_F_DCB].indices-1;
5677 }
9a799d71 5678 }
eacd73f7 5679
4a0b9ca0 5680 tx_ring = adapter->tx_ring[skb->queue_mapping];
60127865 5681
eacd73f7 5682 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
09ad1cc0 5683 (skb->protocol == htons(ETH_P_FCOE))) {
eacd73f7 5684 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0 5685#ifdef IXGBE_FCOE
61a0f421
YZ		 5686#ifdef CONFIG_IXGBE_DCB
5687 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
5688 << IXGBE_TX_FLAGS_VLAN_SHIFT);
5689 tx_flags |= ((adapter->fcoe.up << 13)
5690 << IXGBE_TX_FLAGS_VLAN_SHIFT);
5691#endif
09ad1cc0
YZ		 5692#endif
5693 }
eacd73f7 5694 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 5695 if (skb_is_gso(skb) ||
5696 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 5697 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5698 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 5699 count++;
5700
9f8cdf4f
JB		 5701 count += TXD_USE_COUNT(skb_headlen(skb));
5702 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 5703 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5704
e092be60 5705 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 5706 adapter->tx_busy++;
9a799d71
AK		 5707 return NETDEV_TX_BUSY;
5708 }
9a799d71 5709
9a799d71 5710 first = tx_ring->next_to_use;
eacd73f7
YZ		 5711 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5712#ifdef IXGBE_FCOE
5713 /* setup tx offload for FCoE */
5714 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5715 if (tso < 0) {
5716 dev_kfree_skb_any(skb);
5717 return NETDEV_TX_OK;
5718 }
5719 if (tso)
5720 tx_flags |= IXGBE_TX_FLAGS_FSO;
5721#endif /* IXGBE_FCOE */
5722 } else {
5723 if (skb->protocol == htons(ETH_P_IP))
5724 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5725 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5726 if (tso < 0) {
5727 dev_kfree_skb_any(skb);
5728 return NETDEV_TX_OK;
5729 }
9a799d71 5730
eacd73f7
YZ		 5731 if (tso)
5732 tx_flags |= IXGBE_TX_FLAGS_TSO;
5733 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5734 (skb->ip_summed == CHECKSUM_PARTIAL))
5735 tx_flags |= IXGBE_TX_FLAGS_CSUM;
5736 }
9a799d71 5737
eacd73f7 5738 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 5739 if (count) {
c4cf55e5
PWJ		 5740 /* add the ATR filter if ATR is on */
5741 if (tx_ring->atr_sample_rate) {
5742 ++tx_ring->atr_count;
5743 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5744 test_bit(__IXGBE_FDIR_INIT_DONE,
5745 &tx_ring->reinit_state)) {
5746 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5747 tx_flags);
5748 tx_ring->atr_count = 0;
5749 }
5750 }
60d51134
ED		 5751 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
5752 txq->tx_bytes += skb->len;
5753 txq->tx_packets++;
44df32c5
AD		 5754 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5755 hdr_len);
44df32c5 5756 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 5757
44df32c5
AD		 5758 } else {
5759 dev_kfree_skb_any(skb);
5760 tx_ring->tx_buffer_info[first].time_stamp = 0;
5761 tx_ring->next_to_use = first;
5762 }
9a799d71
AK		 5763
5764 return NETDEV_TX_OK;
5765}
5766
9a799d71
AK		 5767/**
5768 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5769 * @netdev: network interface device structure
5770 * @p: pointer to an address structure
5771 *
5772 * Returns 0 on success, negative on failure
5773 **/
5774static int ixgbe_set_mac(struct net_device *netdev, void *p)
5775{
5776 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 5777 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5778 struct sockaddr *addr = p;
5779
5780 if (!is_valid_ether_addr(addr->sa_data))
5781 return -EADDRNOTAVAIL;
5782
5783 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 5784 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 5785
1cdd1ec8
GR		 5786 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
5787 IXGBE_RAH_AV);
9a799d71
AK		 5788
5789 return 0;
5790}
5791
6b73e10d
BH		 5792static int
5793ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5794{
5795 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5796 struct ixgbe_hw *hw = &adapter->hw;
5797 u16 value;
5798 int rc;
5799
5800 if (prtad != hw->phy.mdio.prtad)
5801 return -EINVAL;
5802 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5803 if (!rc)
5804 rc = value;
5805 return rc;
5806}
5807
5808static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5809 u16 addr, u16 value)
5810{
5811 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5812 struct ixgbe_hw *hw = &adapter->hw;
5813
5814 if (prtad != hw->phy.mdio.prtad)
5815 return -EINVAL;
5816 return hw->phy.ops.write_reg(hw, addr, devad, value);
5817}
5818
5819static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5820{
5821 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5822
5823 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5824}
5825
0365e6e4
PW		 5826/**
5827 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 5828 * netdev->dev_addrs
0365e6e4
PW		 5829 * @netdev: network interface device structure
5830 *
5831 * Returns non-zero on failure
5832 **/
5833static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5834{
5835 int err = 0;
5836 struct ixgbe_adapter *adapter = netdev_priv(dev);
5837 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5838
5839 if (is_valid_ether_addr(mac->san_addr)) {
5840 rtnl_lock();
5841 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5842 rtnl_unlock();
5843 }
5844 return err;
5845}
5846
5847/**
5848 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 5849 * netdev->dev_addrs
0365e6e4
PW		 5850 * @netdev: network interface device structure
5851 *
5852 * Returns non-zero on failure
5853 **/
5854static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5855{
5856 int err = 0;
5857 struct ixgbe_adapter *adapter = netdev_priv(dev);
5858 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5859
5860 if (is_valid_ether_addr(mac->san_addr)) {
5861 rtnl_lock();
5862 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5863 rtnl_unlock();
5864 }
5865 return err;
5866}
5867
9a799d71
AK		 5868#ifdef CONFIG_NET_POLL_CONTROLLER
5869/*
5870 * Polling 'interrupt' - used by things like netconsole to send skbs
5871 * without having to re-enable interrupts. It's not called while
5872 * the interrupt routine is executing.
5873 */
5874static void ixgbe_netpoll(struct net_device *netdev)
5875{
5876 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 5877 int i;
9a799d71 5878
1a647bd2
AD		 5879 /* if interface is down do nothing */
5880 if (test_bit(__IXGBE_DOWN, &adapter->state))
5881 return;
5882
9a799d71 5883 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 5884 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5885 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5886 for (i = 0; i < num_q_vectors; i++) {
5887 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5888 ixgbe_msix_clean_many(0, q_vector);
5889 }
5890 } else {
5891 ixgbe_intr(adapter->pdev->irq, netdev);
5892 }
9a799d71 5893 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 5894}
5895#endif
5896
0edc3527
SH		 5897static const struct net_device_ops ixgbe_netdev_ops = {
5898 .ndo_open = ixgbe_open,
5899 .ndo_stop = ixgbe_close,
00829823 5900 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 5901 .ndo_select_queue = ixgbe_select_queue,
e90d400c 5902 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 5903 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5904 .ndo_validate_addr = eth_validate_addr,
5905 .ndo_set_mac_address = ixgbe_set_mac,
5906 .ndo_change_mtu = ixgbe_change_mtu,
5907 .ndo_tx_timeout = ixgbe_tx_timeout,
5908 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5909 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5910 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 5911 .ndo_do_ioctl = ixgbe_ioctl,
0edc3527
SH		 5912#ifdef CONFIG_NET_POLL_CONTROLLER
5913 .ndo_poll_controller = ixgbe_netpoll,
5914#endif
332d4a7d
YZ		 5915#ifdef IXGBE_FCOE
5916 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5917 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 5918 .ndo_fcoe_enable = ixgbe_fcoe_enable,
5919 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 5920 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 5921#endif /* IXGBE_FCOE */
0edc3527
SH		 5922};
5923
1cdd1ec8
GR		 5924static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
5925 const struct ixgbe_info *ii)
5926{
5927#ifdef CONFIG_PCI_IOV
5928 struct ixgbe_hw *hw = &adapter->hw;
5929 int err;
5930
5931 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
5932 return;
5933
5934 /* The 82599 supports up to 64 VFs per physical function
5935 * but this implementation limits allocation to 63 so that
5936 * basic networking resources are still available to the
5937 * physical function
5938 */
5939 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
5940 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
5941 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
5942 if (err) {
5943 DPRINTK(PROBE, ERR,
5944 "Failed to enable PCI sriov: %d\n", err);
5945 goto err_novfs;
5946 }
5947 /* If call to enable VFs succeeded then allocate memory
5948 * for per VF control structures.
5949 */
5950 adapter->vfinfo =
5951 kcalloc(adapter->num_vfs,
5952 sizeof(struct vf_data_storage), GFP_KERNEL);
5953 if (adapter->vfinfo) {
5954 /* Now that we're sure SR-IOV is enabled
5955 * and memory allocated set up the mailbox parameters
5956 */
5957 ixgbe_init_mbx_params_pf(hw);
5958 memcpy(&hw->mbx.ops, ii->mbx_ops,
5959 sizeof(hw->mbx.ops));
5960
5961 /* Disable RSC when in SR-IOV mode */
5962 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
5963 IXGBE_FLAG2_RSC_ENABLED);
5964 return;
5965 }
5966
5967 /* Oh oh */
5968 DPRINTK(PROBE, ERR,
5969 "Unable to allocate memory for VF "
5970 "Data Storage - SRIOV disabled\n");
5971 pci_disable_sriov(adapter->pdev);
5972
5973err_novfs:
5974 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
5975 adapter->num_vfs = 0;
5976#endif /* CONFIG_PCI_IOV */
5977}
5978
9a799d71
AK		 5979/**
5980 * ixgbe_probe - Device Initialization Routine
5981 * @pdev: PCI device information struct
5982 * @ent: entry in ixgbe_pci_tbl
5983 *
5984 * Returns 0 on success, negative on failure
5985 *
5986 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5987 * The OS initialization, configuring of the adapter private structure,
5988 * and a hardware reset occur.
5989 **/
5990static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 5991 const struct pci_device_id *ent)
9a799d71
AK		 5992{
5993 struct net_device *netdev;
5994 struct ixgbe_adapter *adapter = NULL;
5995 struct ixgbe_hw *hw;
5996 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 5997 static int cards_found;
5998 int i, err, pci_using_dac;
c85a2618 5999 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 6000#ifdef IXGBE_FCOE
6001 u16 device_caps;
6002#endif
c44ade9e 6003 u32 part_num, eec;
9a799d71 6004
9ce77666 6005 err = pci_enable_device_mem(pdev);
9a799d71
AK		 6006 if (err)
6007 return err;
6008
6a35528a
YH		 6009 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
6010 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
9a799d71
AK		 6011 pci_using_dac = 1;
6012 } else {
284901a9 6013 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 6014 if (err) {
284901a9 6015 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 6016 if (err) {
b4617240
PW		 6017 dev_err(&pdev->dev, "No usable DMA "
6018 "configuration, aborting\n");
9a799d71
AK		 6019 goto err_dma;
6020 }
6021 }
6022 pci_using_dac = 0;
6023 }
6024
9ce77666 6025 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6026 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 6027 if (err) {
9ce77666 6028 dev_err(&pdev->dev,
6029 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 6030 goto err_pci_reg;
6031 }
6032
19d5afd4 6033 pci_enable_pcie_error_reporting(pdev);
6fabd715 6034
9a799d71 6035 pci_set_master(pdev);
fb3b27bc 6036 pci_save_state(pdev);
9a799d71 6037
c85a2618
JF		 6038 if (ii->mac == ixgbe_mac_82598EB)
6039 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6040 else
6041 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6042
6043 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6044#ifdef IXGBE_FCOE
6045 indices += min_t(unsigned int, num_possible_cpus(),
6046 IXGBE_MAX_FCOE_INDICES);
6047#endif
6048 indices = min_t(unsigned int, indices, MAX_TX_QUEUES);
6049 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 6050 if (!netdev) {
6051 err = -ENOMEM;
6052 goto err_alloc_etherdev;
6053 }
6054
9a799d71
AK		 6055 SET_NETDEV_DEV(netdev, &pdev->dev);
6056
6057 pci_set_drvdata(pdev, netdev);
6058 adapter = netdev_priv(netdev);
6059
6060 adapter->netdev = netdev;
6061 adapter->pdev = pdev;
6062 hw = &adapter->hw;
6063 hw->back = adapter;
6064 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6065
05857980
JK		 6066 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6067 pci_resource_len(pdev, 0));
9a799d71
AK		 6068 if (!hw->hw_addr) {
6069 err = -EIO;
6070 goto err_ioremap;
6071 }
6072
6073 for (i = 1; i <= 5; i++) {
6074 if (pci_resource_len(pdev, i) == 0)
6075 continue;
6076 }
6077
0edc3527 6078 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 6079 ixgbe_set_ethtool_ops(netdev);
9a799d71 6080 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 6081 strcpy(netdev->name, pci_name(pdev));
6082
9a799d71
AK		 6083 adapter->bd_number = cards_found;
6084
9a799d71
AK		 6085 /* Setup hw api */
6086 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 6087 hw->mac.type = ii->mac;
9a799d71 6088
c44ade9e
JB		 6089 /* EEPROM */
6090 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6091 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6092 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6093 if (!(eec & (1 << 8)))
6094 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6095
6096 /* PHY */
6097 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 6098 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 6099 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6100 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6101 hw->phy.mdio.mmds = 0;
6102 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6103 hw->phy.mdio.dev = netdev;
6104 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6105 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 6106
6107 /* set up this timer and work struct before calling get_invariants
6108 * which might start the timer
6109 */
6110 init_timer(&adapter->sfp_timer);
6111 adapter->sfp_timer.function = &ixgbe_sfp_timer;
6112 adapter->sfp_timer.data = (unsigned long) adapter;
6113
6114 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 6115
e8e26350
PW		 6116 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6117 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6118
6119 /* a new SFP+ module arrival, called from GPI SDP2 context */
6120 INIT_WORK(&adapter->sfp_config_module_task,
6121 ixgbe_sfp_config_module_task);
6122
8ca783ab 6123 ii->get_invariants(hw);
9a799d71
AK		 6124
6125 /* setup the private structure */
6126 err = ixgbe_sw_init(adapter);
6127 if (err)
6128 goto err_sw_init;
6129
e86bff0e
DS		 6130 /* Make it possible the adapter to be woken up via WOL */
6131 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6132 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6133
bf069c97
DS		 6134 /*
6135 * If there is a fan on this device and it has failed log the
6136 * failure.
6137 */
6138 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6139 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6140 if (esdp & IXGBE_ESDP_SDP1)
6141 DPRINTK(PROBE, CRIT,
6142 "Fan has stopped, replace the adapter\n");
6143 }
6144
c44ade9e
JB		 6145 /* reset_hw fills in the perm_addr as well */
6146 err = hw->mac.ops.reset_hw(hw);
8ca783ab
DS		 6147 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6148 hw->mac.type == ixgbe_mac_82598EB) {
6149 /*
6150 * Start a kernel thread to watch for a module to arrive.
6151 * Only do this for 82598, since 82599 will generate
6152 * interrupts on module arrival.
6153 */
6154 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6155 mod_timer(&adapter->sfp_timer,
6156 round_jiffies(jiffies + (2 * HZ)));
6157 err = 0;
6158 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 6159 dev_err(&adapter->pdev->dev, "failed to initialize because "
6160 "an unsupported SFP+ module type was detected.\n"
6161 "Reload the driver after installing a supported "
6162 "module.\n");
04f165ef
PW		 6163 goto err_sw_init;
6164 } else if (err) {
c44ade9e
JB		 6165 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
6166 goto err_sw_init;
6167 }
6168
1cdd1ec8
GR		 6169 ixgbe_probe_vf(adapter, ii);
6170
9a799d71 6171 netdev->features = NETIF_F_SG |
b4617240
PW		 6172 NETIF_F_IP_CSUM |
6173 NETIF_F_HW_VLAN_TX |
6174 NETIF_F_HW_VLAN_RX |
6175 NETIF_F_HW_VLAN_FILTER;
9a799d71 6176
e9990a9c 6177 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 6178 netdev->features |= NETIF_F_TSO;
9a799d71 6179 netdev->features |= NETIF_F_TSO6;
78b6f4ce 6180 netdev->features |= NETIF_F_GRO;
ad31c402 6181
45a5ead0
JB		 6182 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6183 netdev->features |= NETIF_F_SCTP_CSUM;
6184
ad31c402
JK		 6185 netdev->vlan_features |= NETIF_F_TSO;
6186 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 6187 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 6188 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 6189 netdev->vlan_features |= NETIF_F_SG;
6190
1cdd1ec8
GR		 6191 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6192 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6193 IXGBE_FLAG_DCB_ENABLED);
2f90b865
AD		 6194 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6195 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6196
7a6b6f51 6197#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 6198 netdev->dcbnl_ops = &dcbnl_ops;
6199#endif
6200
eacd73f7 6201#ifdef IXGBE_FCOE
0d551589 6202 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 6203 if (hw->mac.ops.get_device_caps) {
6204 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 6205 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6206 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 6207 }
6208 }
6209#endif /* IXGBE_FCOE */
9a799d71
AK		 6210 if (pci_using_dac)
6211 netdev->features |= NETIF_F_HIGHDMA;
6212
0c19d6af 6213 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 6214 netdev->features |= NETIF_F_LRO;
6215
9a799d71 6216 /* make sure the EEPROM is good */
c44ade9e 6217 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 6218 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
6219 err = -EIO;
6220 goto err_eeprom;
6221 }
6222
6223 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6224 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6225
c44ade9e
JB		 6226 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6227 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 6228 err = -EIO;
6229 goto err_eeprom;
6230 }
6231
6232 init_timer(&adapter->watchdog_timer);
6233 adapter->watchdog_timer.function = &ixgbe_watchdog;
6234 adapter->watchdog_timer.data = (unsigned long)adapter;
6235
6236 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 6237 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 6238
021230d4
AV		 6239 err = ixgbe_init_interrupt_scheme(adapter);
6240 if (err)
6241 goto err_sw_init;
9a799d71 6242
e8e26350
PW		 6243 switch (pdev->device) {
6244 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 6245 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6246 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
bdf0a550
PWJ		 6247 /* Enable ACPI wakeup in GRC */
6248 IXGBE_WRITE_REG(hw, IXGBE_GRC,
6249 (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
e8e26350
PW		 6250 break;
6251 default:
6252 adapter->wol = 0;
6253 break;
6254 }
e8e26350
PW		 6255 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6256
04f165ef
PW		 6257 /* pick up the PCI bus settings for reporting later */
6258 hw->mac.ops.get_bus_info(hw);
6259
9a799d71 6260 /* print bus type/speed/width info */
7c510e4b 6261 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 6262 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6263 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6264 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6265 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6266 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 6267 "Unknown"),
7c510e4b 6268 netdev->dev_addr);
c44ade9e 6269 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 6270 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6271 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
6272 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6273 (part_num >> 8), (part_num & 0xff));
6274 else
6275 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6276 hw->mac.type, hw->phy.type,
6277 (part_num >> 8), (part_num & 0xff));
9a799d71 6278
e8e26350 6279 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 6280 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 6281 "this card is not sufficient for optimal "
6282 "performance.\n");
0c254d86 6283 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 6284 "PCI-Express slot is required.\n");
0c254d86
AK		 6285 }
6286
34b0368c
PWJ		 6287 /* save off EEPROM version number */
6288 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6289
9a799d71 6290 /* reset the hardware with the new settings */
794caeb2 6291 err = hw->mac.ops.start_hw(hw);
c44ade9e 6292
794caeb2
PWJ		 6293 if (err == IXGBE_ERR_EEPROM_VERSION) {
6294 /* We are running on a pre-production device, log a warning */
6295 dev_warn(&pdev->dev, "This device is a pre-production "
6296 "adapter/LOM. Please be aware there may be issues "
6297 "associated with your hardware. If you are "
6298 "experiencing problems please contact your Intel or "
6299 "hardware representative who provided you with this "
6300 "hardware.\n");
6301 }
9a799d71
AK		 6302 strcpy(netdev->name, "eth%d");
6303 err = register_netdev(netdev);
6304 if (err)
6305 goto err_register;
6306
54386467
JB		 6307 /* carrier off reporting is important to ethtool even BEFORE open */
6308 netif_carrier_off(netdev);
6309
c4cf55e5
PWJ		 6310 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6311 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6312 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6313
5dd2d332 6314#ifdef CONFIG_IXGBE_DCA
652f093f 6315 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 6316 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 6317 ixgbe_setup_dca(adapter);
6318 }
6319#endif
1cdd1ec8
GR		 6320 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6321 DPRINTK(PROBE, INFO, "IOV is enabled with %d VFs\n",
6322 adapter->num_vfs);
6323 for (i = 0; i < adapter->num_vfs; i++)
6324 ixgbe_vf_configuration(pdev, (i | 0x10000000));
6325 }
6326
0365e6e4
PW		 6327 /* add san mac addr to netdev */
6328 ixgbe_add_sanmac_netdev(netdev);
9a799d71
AK		 6329
6330 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
6331 cards_found++;
6332 return 0;
6333
6334err_register:
5eba3699 6335 ixgbe_release_hw_control(adapter);
7a921c93 6336 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 6337err_sw_init:
6338err_eeprom:
1cdd1ec8
GR		 6339 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6340 ixgbe_disable_sriov(adapter);
c4900be0
DS		 6341 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6342 del_timer_sync(&adapter->sfp_timer);
6343 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6344 cancel_work_sync(&adapter->multispeed_fiber_task);
6345 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 6346 iounmap(hw->hw_addr);
6347err_ioremap:
6348 free_netdev(netdev);
6349err_alloc_etherdev:
9ce77666 6350 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6351 IORESOURCE_MEM));
9a799d71
AK		 6352err_pci_reg:
6353err_dma:
6354 pci_disable_device(pdev);
6355 return err;
6356}
6357
6358/**
6359 * ixgbe_remove - Device Removal Routine
6360 * @pdev: PCI device information struct
6361 *
6362 * ixgbe_remove is called by the PCI subsystem to alert the driver
6363 * that it should release a PCI device. The could be caused by a
6364 * Hot-Plug event, or because the driver is going to be removed from
6365 * memory.
6366 **/
6367static void __devexit ixgbe_remove(struct pci_dev *pdev)
6368{
6369 struct net_device *netdev = pci_get_drvdata(pdev);
6370 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6371
6372 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 6373 /* clear the module not found bit to make sure the worker won't
6374 * reschedule
6375 */
6376 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 6377 del_timer_sync(&adapter->watchdog_timer);
6378
c4900be0
DS		 6379 del_timer_sync(&adapter->sfp_timer);
6380 cancel_work_sync(&adapter->watchdog_task);
6381 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6382 cancel_work_sync(&adapter->multispeed_fiber_task);
6383 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 6384 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6385 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6386 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 6387 flush_scheduled_work();
6388
5dd2d332 6389#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6390 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6391 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6392 dca_remove_requester(&pdev->dev);
6393 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6394 }
6395
6396#endif
332d4a7d
YZ		 6397#ifdef IXGBE_FCOE
6398 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6399 ixgbe_cleanup_fcoe(adapter);
6400
6401#endif /* IXGBE_FCOE */
0365e6e4
PW		 6402
6403 /* remove the added san mac */
6404 ixgbe_del_sanmac_netdev(netdev);
6405
c4900be0
DS		 6406 if (netdev->reg_state == NETREG_REGISTERED)
6407 unregister_netdev(netdev);
9a799d71 6408
1cdd1ec8
GR		 6409 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6410 ixgbe_disable_sriov(adapter);
6411
7a921c93 6412 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 6413
021230d4 6414 ixgbe_release_hw_control(adapter);
9a799d71
AK		 6415
6416 iounmap(adapter->hw.hw_addr);
9ce77666 6417 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6418 IORESOURCE_MEM));
9a799d71 6419
021230d4 6420 DPRINTK(PROBE, INFO, "complete\n");
021230d4 6421
9a799d71
AK		 6422 free_netdev(netdev);
6423
19d5afd4 6424 pci_disable_pcie_error_reporting(pdev);
6fabd715 6425
9a799d71
AK		 6426 pci_disable_device(pdev);
6427}
6428
6429/**
6430 * ixgbe_io_error_detected - called when PCI error is detected
6431 * @pdev: Pointer to PCI device
6432 * @state: The current pci connection state
6433 *
6434 * This function is called after a PCI bus error affecting
6435 * this device has been detected.
6436 */
6437static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 6438 pci_channel_state_t state)
9a799d71
AK		 6439{
6440 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6441 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6442
6443 netif_device_detach(netdev);
6444
3044b8d1
BL		 6445 if (state == pci_channel_io_perm_failure)
6446 return PCI_ERS_RESULT_DISCONNECT;
6447
9a799d71
AK		 6448 if (netif_running(netdev))
6449 ixgbe_down(adapter);
6450 pci_disable_device(pdev);
6451
b4617240 6452 /* Request a slot reset. */
9a799d71
AK		 6453 return PCI_ERS_RESULT_NEED_RESET;
6454}
6455
6456/**
6457 * ixgbe_io_slot_reset - called after the pci bus has been reset.
6458 * @pdev: Pointer to PCI device
6459 *
6460 * Restart the card from scratch, as if from a cold-boot.
6461 */
6462static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
6463{
6464 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6465 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 6466 pci_ers_result_t result;
6467 int err;
9a799d71 6468
9ce77666 6469 if (pci_enable_device_mem(pdev)) {
9a799d71 6470 DPRINTK(PROBE, ERR,
b4617240 6471 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 6472 result = PCI_ERS_RESULT_DISCONNECT;
6473 } else {
6474 pci_set_master(pdev);
6475 pci_restore_state(pdev);
c0e1f68b 6476 pci_save_state(pdev);
9a799d71 6477
dd4d8ca6 6478 pci_wake_from_d3(pdev, false);
9a799d71 6479
6fabd715 6480 ixgbe_reset(adapter);
88512539 6481 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 6482 result = PCI_ERS_RESULT_RECOVERED;
6483 }
6484
6485 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6486 if (err) {
6487 dev_err(&pdev->dev,
6488 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6489 /* non-fatal, continue */
6490 }
9a799d71 6491
6fabd715 6492 return result;
9a799d71
AK		 6493}
6494
6495/**
6496 * ixgbe_io_resume - called when traffic can start flowing again.
6497 * @pdev: Pointer to PCI device
6498 *
6499 * This callback is called when the error recovery driver tells us that
6500 * its OK to resume normal operation.
6501 */
6502static void ixgbe_io_resume(struct pci_dev *pdev)
6503{
6504 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6505 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6506
6507 if (netif_running(netdev)) {
6508 if (ixgbe_up(adapter)) {
6509 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6510 return;
6511 }
6512 }
6513
6514 netif_device_attach(netdev);
9a799d71
AK		 6515}
6516
6517static struct pci_error_handlers ixgbe_err_handler = {
6518 .error_detected = ixgbe_io_error_detected,
6519 .slot_reset = ixgbe_io_slot_reset,
6520 .resume = ixgbe_io_resume,
6521};
6522
6523static struct pci_driver ixgbe_driver = {
6524 .name = ixgbe_driver_name,
6525 .id_table = ixgbe_pci_tbl,
6526 .probe = ixgbe_probe,
6527 .remove = __devexit_p(ixgbe_remove),
6528#ifdef CONFIG_PM
6529 .suspend = ixgbe_suspend,
6530 .resume = ixgbe_resume,
6531#endif
6532 .shutdown = ixgbe_shutdown,
6533 .err_handler = &ixgbe_err_handler
6534};
6535
6536/**
6537 * ixgbe_init_module - Driver Registration Routine
6538 *
6539 * ixgbe_init_module is the first routine called when the driver is
6540 * loaded. All it does is register with the PCI subsystem.
6541 **/
6542static int __init ixgbe_init_module(void)
6543{
6544 int ret;
6545 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6546 ixgbe_driver_string, ixgbe_driver_version);
6547
6548 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6549
5dd2d332 6550#ifdef CONFIG_IXGBE_DCA
bd0362dd 6551 dca_register_notify(&dca_notifier);
bd0362dd 6552#endif
5dd2d332 6553
9a799d71
AK		 6554 ret = pci_register_driver(&ixgbe_driver);
6555 return ret;
6556}
b4617240 6557
9a799d71
AK		 6558module_init(ixgbe_init_module);
6559
6560/**
6561 * ixgbe_exit_module - Driver Exit Cleanup Routine
6562 *
6563 * ixgbe_exit_module is called just before the driver is removed
6564 * from memory.
6565 **/
6566static void __exit ixgbe_exit_module(void)
6567{
5dd2d332 6568#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6569 dca_unregister_notify(&dca_notifier);
6570#endif
9a799d71
AK		 6571 pci_unregister_driver(&ixgbe_driver);
6572}
bd0362dd 6573
5dd2d332 6574#ifdef CONFIG_IXGBE_DCA
bd0362dd 6575static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 6576 void *p)
bd0362dd
JC		 6577{
6578 int ret_val;
6579
6580 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 6581 __ixgbe_notify_dca);
bd0362dd
JC		 6582
6583 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6584}
b453368d 6585
5dd2d332 6586#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 6587#ifdef DEBUG
6588/**
6589 * ixgbe_get_hw_dev_name - return device name string
6590 * used by hardware layer to print debugging information
6591 **/
6592char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6593{
6594 struct ixgbe_adapter *adapter = hw->back;
6595 return adapter->netdev->name;
6596}
bd0362dd 6597
b453368d 6598#endif
9a799d71
AK		 6599module_exit(ixgbe_exit_module);
6600
6601/* ixgbe_main.c */
kernel source for telekom puls (alcatel/mediatek)