projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ixgbe: fix dca hints going to wrong processor
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/ipv6.h>
39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
41#include <linux/ethtool.h>
42#include <linux/if_vlan.h>
43
44#include "ixgbe.h"
45#include "ixgbe_common.h"
46
47char ixgbe_driver_name[] = "ixgbe";
9c8eb720
SH		 48static const char ixgbe_driver_string[] =
49 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 50
8d792cd9 51#define DRV_VERSION "1.3.18-k4"
9c8eb720
SH		 52const char ixgbe_driver_version[] = DRV_VERSION;
53static const char ixgbe_copyright[] =
54 "Copyright (c) 1999-2007 Intel Corporation.";
9a799d71
AK		 55
56static const struct ixgbe_info *ixgbe_info_tbl[] = {
3957d63d 57 [board_82598] = &ixgbe_82598_info,
9a799d71
AK		 58};
59
60/* ixgbe_pci_tbl - PCI Device ID Table
61 *
62 * Wildcard entries (PCI_ANY_ID) should come last
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
68static struct pci_device_id ixgbe_pci_tbl[] = {
69 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 70 board_82598 },
9a799d71 71 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 72 board_82598 },
9a799d71 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 74 board_82598 },
8d792cd9
JB		 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
76 board_82598 },
9a799d71
AK		 77
78 /* required last entry */
79 {0, }
80};
81MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
82
96b0e0f6 83#if defined(CONFIG_DCA) || defined (CONFIG_DCA_MODULE)
bd0362dd
JC		 84static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
85 void *p);
86static struct notifier_block dca_notifier = {
87 .notifier_call = ixgbe_notify_dca,
88 .next = NULL,
89 .priority = 0
90};
91#endif
92
9a799d71
AK		 93MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
94MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
95MODULE_LICENSE("GPL");
96MODULE_VERSION(DRV_VERSION);
97
98#define DEFAULT_DEBUG_LEVEL_SHIFT 3
99
5eba3699
AV		 100static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
101{
102 u32 ctrl_ext;
103
104 /* Let firmware take over control of h/w */
105 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
106 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
107 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
108}
109
110static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
111{
112 u32 ctrl_ext;
113
114 /* Let firmware know the driver has taken over */
115 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
116 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
117 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
118}
9a799d71
AK		 119
120#ifdef DEBUG
121/**
122 * ixgbe_get_hw_dev_name - return device name string
123 * used by hardware layer to print debugging information
124 **/
125char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
126{
127 struct ixgbe_adapter *adapter = hw->back;
128 struct net_device *netdev = adapter->netdev;
129 return netdev->name;
130}
131#endif
132
133static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, u16 int_alloc_entry,
134 u8 msix_vector)
135{
136 u32 ivar, index;
137
138 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
139 index = (int_alloc_entry >> 2) & 0x1F;
140 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR(index));
141 ivar &= ~(0xFF << (8 * (int_alloc_entry & 0x3)));
142 ivar |= (msix_vector << (8 * (int_alloc_entry & 0x3)));
143 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR(index), ivar);
144}
145
146static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
147 struct ixgbe_tx_buffer
148 *tx_buffer_info)
149{
150 if (tx_buffer_info->dma) {
e01c31a5 151 pci_unmap_page(adapter->pdev, tx_buffer_info->dma,
9a799d71
AK		 152 tx_buffer_info->length, PCI_DMA_TODEVICE);
153 tx_buffer_info->dma = 0;
154 }
155 if (tx_buffer_info->skb) {
156 dev_kfree_skb_any(tx_buffer_info->skb);
157 tx_buffer_info->skb = NULL;
158 }
159 /* tx_buffer_info must be completely set up in the transmit path */
160}
161
162static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
163 struct ixgbe_ring *tx_ring,
e01c31a5 164 unsigned int eop)
9a799d71 165{
e01c31a5
JB		 166 struct ixgbe_hw *hw = &adapter->hw;
167 u32 head, tail;
168
9a799d71 169 /* Detect a transmit hang in hardware, this serializes the
e01c31a5
JB		 170 * check with the clearing of time_stamp and movement of eop */
171 head = IXGBE_READ_REG(hw, tx_ring->head);
172 tail = IXGBE_READ_REG(hw, tx_ring->tail);
9a799d71 173 adapter->detect_tx_hung = false;
e01c31a5
JB		 174 if ((head != tail) &&
175 tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 176 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
177 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
178 /* detected Tx unit hang */
e01c31a5
JB		 179 union ixgbe_adv_tx_desc *tx_desc;
180 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 181 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 182 " Tx Queue <%d>\n"
183 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 184 " next_to_use <%x>\n"
185 " next_to_clean <%x>\n"
186 "tx_buffer_info[next_to_clean]\n"
187 " time_stamp <%lx>\n"
e01c31a5
JB		 188 " jiffies <%lx>\n",
189 tx_ring->queue_index,
190 head, tail,
191 tx_ring->next_to_use, eop,
192 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 193 return true;
194 }
195
196 return false;
197}
198
e092be60
AV		 199#define IXGBE_MAX_TXD_PWR 14
200#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
201
202/* Tx Descriptors needed, worst case */
203#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
204 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
205#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
206 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
207
e01c31a5
JB		 208#define GET_TX_HEAD_FROM_RING(ring) (\
209 *(volatile u32 *) \
210 ((union ixgbe_adv_tx_desc *)(ring)->desc + (ring)->count))
211static void ixgbe_tx_timeout(struct net_device *netdev);
212
9a799d71
AK		 213/**
214 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
215 * @adapter: board private structure
e01c31a5 216 * @tx_ring: tx ring to clean
9a799d71
AK		 217 **/
218static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
e01c31a5 219 struct ixgbe_ring *tx_ring)
9a799d71 220{
e01c31a5 221 union ixgbe_adv_tx_desc *tx_desc;
9a799d71 222 struct ixgbe_tx_buffer *tx_buffer_info;
e01c31a5
JB		 223 struct net_device *netdev = adapter->netdev;
224 struct sk_buff *skb;
225 unsigned int i;
226 u32 head, oldhead;
227 unsigned int count = 0;
228 unsigned int total_bytes = 0, total_packets = 0;
9a799d71 229
e01c31a5
JB		 230 rmb();
231 head = GET_TX_HEAD_FROM_RING(tx_ring);
232 head = le32_to_cpu(head);
9a799d71 233 i = tx_ring->next_to_clean;
e01c31a5
JB		 234 while (1) {
235 while (i != head) {
9a799d71
AK		 236 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
237 tx_buffer_info = &tx_ring->tx_buffer_info[i];
e01c31a5 238 skb = tx_buffer_info->skb;
9a799d71 239
e01c31a5 240 if (skb) {
e092be60 241 unsigned int segs, bytecount;
e01c31a5
JB		 242
243 /* gso_segs is currently only valid for tcp */
e092be60
AV		 244 segs = skb_shinfo(skb)->gso_segs ?: 1;
245 /* multiply data chunks by size of headers */
246 bytecount = ((segs - 1) * skb_headlen(skb)) +
e01c31a5
JB		 247 skb->len;
248 total_packets += segs;
249 total_bytes += bytecount;
e092be60 250 }
e01c31a5 251
9a799d71 252 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 253 tx_buffer_info);
9a799d71
AK		 254
255 i++;
256 if (i == tx_ring->count)
257 i = 0;
9a799d71 258
e01c31a5
JB		 259 count++;
260 if (count == tx_ring->count)
261 goto done_cleaning;
262 }
263 oldhead = head;
264 rmb();
265 head = GET_TX_HEAD_FROM_RING(tx_ring);
266 head = le32_to_cpu(head);
267 if (head == oldhead)
268 goto done_cleaning;
269 } /* while (1) */
270
271done_cleaning:
9a799d71
AK		 272 tx_ring->next_to_clean = i;
273
e092be60 274#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 275 if (unlikely(count && netif_carrier_ok(netdev) &&
276 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 277 /* Make sure that anybody stopping the queue after this
278 * sees the new next_to_clean.
279 */
280 smp_mb();
30eba97a
AV		 281 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
282 !test_bit(__IXGBE_DOWN, &adapter->state)) {
283 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 284 ++adapter->restart_queue;
30eba97a 285 }
e092be60 286 }
9a799d71 287
e01c31a5
JB		 288 if (adapter->detect_tx_hung) {
289 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
290 /* schedule immediate reset if we believe we hung */
291 DPRINTK(PROBE, INFO,
292 "tx hang %d detected, resetting adapter\n",
293 adapter->tx_timeout_count + 1);
294 ixgbe_tx_timeout(adapter->netdev);
295 }
296 }
9a799d71 297
e01c31a5
JB		 298 /* re-arm the interrupt */
299 if ((total_packets >= tx_ring->work_limit) ||
300 (count == tx_ring->count))
301 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx);
9a799d71 302
e01c31a5
JB		 303 tx_ring->total_bytes += total_bytes;
304 tx_ring->total_packets += total_packets;
305 tx_ring->stats.bytes += total_bytes;
306 tx_ring->stats.packets += total_packets;
307 adapter->net_stats.tx_bytes += total_bytes;
308 adapter->net_stats.tx_packets += total_packets;
309 return (total_packets ? true : false);
9a799d71
AK		 310}
311
96b0e0f6 312#if defined(CONFIG_DCA) || defined (CONFIG_DCA_MODULE)
bd0362dd 313static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
3a581073 314 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 315{
316 u32 rxctrl;
317 int cpu = get_cpu();
3a581073 318 int q = rx_ring - adapter->rx_ring;
bd0362dd 319
3a581073 320 if (rx_ring->cpu != cpu) {
bd0362dd
JC		 321 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
322 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
96b0e0f6 323 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
bd0362dd
JC		 324 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
325 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
326 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 327 rx_ring->cpu = cpu;
bd0362dd
JC		 328 }
329 put_cpu();
330}
331
332static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
3a581073 333 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 334{
335 u32 txctrl;
336 int cpu = get_cpu();
3a581073 337 int q = tx_ring - adapter->tx_ring;
bd0362dd 338
3a581073 339 if (tx_ring->cpu != cpu) {
bd0362dd
JC		 340 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
341 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
96b0e0f6 342 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
bd0362dd
JC		 343 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
344 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 345 tx_ring->cpu = cpu;
bd0362dd
JC		 346 }
347 put_cpu();
348}
349
350static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
351{
352 int i;
353
354 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
355 return;
356
357 for (i = 0; i < adapter->num_tx_queues; i++) {
358 adapter->tx_ring[i].cpu = -1;
359 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
360 }
361 for (i = 0; i < adapter->num_rx_queues; i++) {
362 adapter->rx_ring[i].cpu = -1;
363 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
364 }
365}
366
367static int __ixgbe_notify_dca(struct device *dev, void *data)
368{
369 struct net_device *netdev = dev_get_drvdata(dev);
370 struct ixgbe_adapter *adapter = netdev_priv(netdev);
371 unsigned long event = *(unsigned long *)data;
372
373 switch (event) {
374 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 375 /* if we're already enabled, don't do it again */
376 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
377 break;
bd0362dd
JC		 378 /* Always use CB2 mode, difference is masked
379 * in the CB driver. */
380 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
652f093f 381 if (dca_add_requester(dev) == 0) {
96b0e0f6 382 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 383 ixgbe_setup_dca(adapter);
384 break;
385 }
386 /* Fall Through since DCA is disabled. */
387 case DCA_PROVIDER_REMOVE:
388 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
389 dca_remove_requester(dev);
390 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
391 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
392 }
393 break;
394 }
395
652f093f 396 return 0;
bd0362dd
JC		 397}
398
96b0e0f6 399#endif /* CONFIG_DCA or CONFIG_DCA_MODULE */
9a799d71
AK		 400/**
401 * ixgbe_receive_skb - Send a completed packet up the stack
402 * @adapter: board private structure
403 * @skb: packet to send up
177db6ff
MC		 404 * @status: hardware indication of status of receive
405 * @rx_ring: rx descriptor ring (for a specific queue) to setup
406 * @rx_desc: rx descriptor
9a799d71
AK		 407 **/
408static void ixgbe_receive_skb(struct ixgbe_adapter *adapter,
177db6ff
MC		 409 struct sk_buff *skb, u8 status,
410 struct ixgbe_ring *ring,
411 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 412{
177db6ff
MC		 413 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
414 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 415
177db6ff
MC		 416 if (adapter->netdev->features & NETIF_F_LRO &&
417 skb->ip_summed == CHECKSUM_UNNECESSARY) {
9a799d71 418 if (adapter->vlgrp && is_vlan)
177db6ff
MC		 419 lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb,
420 adapter->vlgrp, tag,
421 rx_desc);
9a799d71 422 else
177db6ff
MC		 423 lro_receive_skb(&ring->lro_mgr, skb, rx_desc);
424 ring->lro_used = true;
425 } else {
426 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
427 if (adapter->vlgrp && is_vlan)
428 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
429 else
430 netif_receive_skb(skb);
431 } else {
432 if (adapter->vlgrp && is_vlan)
433 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
434 else
435 netif_rx(skb);
436 }
9a799d71
AK		 437 }
438}
439
e59bd25d
AV		 440/**
441 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
442 * @adapter: address of board private structure
443 * @status_err: hardware indication of status of receive
444 * @skb: skb currently being received and modified
445 **/
9a799d71 446static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
712744be 447 u32 status_err, struct sk_buff *skb)
9a799d71
AK		 448{
449 skb->ip_summed = CHECKSUM_NONE;
450
712744be
JB		 451 /* Rx csum disabled */
452 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 453 return;
e59bd25d
AV		 454
455 /* if IP and error */
456 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
457 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 458 adapter->hw_csum_rx_error++;
459 return;
460 }
e59bd25d
AV		 461
462 if (!(status_err & IXGBE_RXD_STAT_L4CS))
463 return;
464
465 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
466 adapter->hw_csum_rx_error++;
467 return;
468 }
469
9a799d71 470 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 471 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 472 adapter->hw_csum_rx_good++;
473}
474
475/**
476 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
477 * @adapter: address of board private structure
478 **/
479static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 480 struct ixgbe_ring *rx_ring,
481 int cleaned_count)
9a799d71
AK		 482{
483 struct net_device *netdev = adapter->netdev;
484 struct pci_dev *pdev = adapter->pdev;
485 union ixgbe_adv_rx_desc *rx_desc;
3a581073 486 struct ixgbe_rx_buffer *bi;
9a799d71 487 unsigned int i;
7c6e0a43 488 unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
9a799d71
AK		 489
490 i = rx_ring->next_to_use;
3a581073 491 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 492
493 while (cleaned_count--) {
494 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
495
3a581073
JB		 496 if (!bi->page &&
497 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
498 bi->page = alloc_page(GFP_ATOMIC);
499 if (!bi->page) {
9a799d71
AK		 500 adapter->alloc_rx_page_failed++;
501 goto no_buffers;
502 }
3a581073 503 bi->page_dma = pci_map_page(pdev, bi->page, 0,
7c6e0a43
JB		 504 PAGE_SIZE,
505 PCI_DMA_FROMDEVICE);
9a799d71
AK		 506 }
507
3a581073
JB		 508 if (!bi->skb) {
509 struct sk_buff *skb = netdev_alloc_skb(netdev, bufsz);
9a799d71
AK		 510
511 if (!skb) {
512 adapter->alloc_rx_buff_failed++;
513 goto no_buffers;
514 }
515
516 /*
517 * Make buffer alignment 2 beyond a 16 byte boundary
518 * this will result in a 16 byte aligned IP header after
519 * the 14 byte MAC header is removed
520 */
521 skb_reserve(skb, NET_IP_ALIGN);
522
3a581073
JB		 523 bi->skb = skb;
524 bi->dma = pci_map_single(pdev, skb->data, bufsz,
525 PCI_DMA_FROMDEVICE);
9a799d71
AK		 526 }
527 /* Refresh the desc even if buffer_addrs didn't change because
528 * each write-back erases this info. */
529 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3a581073
JB		 530 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
531 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 532 } else {
3a581073 533 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 534 }
535
536 i++;
537 if (i == rx_ring->count)
538 i = 0;
3a581073 539 bi = &rx_ring->rx_buffer_info[i];
9a799d71 540 }
7c6e0a43 541
9a799d71
AK		 542no_buffers:
543 if (rx_ring->next_to_use != i) {
544 rx_ring->next_to_use = i;
545 if (i-- == 0)
546 i = (rx_ring->count - 1);
547
548 /*
549 * Force memory writes to complete before letting h/w
550 * know there are new descriptors to fetch. (Only
551 * applicable for weak-ordered memory model archs,
552 * such as IA-64).
553 */
554 wmb();
555 writel(i, adapter->hw.hw_addr + rx_ring->tail);
556 }
557}
558
7c6e0a43
JB		 559static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
560{
561 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
562}
563
564static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
565{
566 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
567}
568
9a799d71 569static bool ixgbe_clean_rx_irq(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 570 struct ixgbe_ring *rx_ring,
571 int *work_done, int work_to_do)
9a799d71
AK		 572{
573 struct net_device *netdev = adapter->netdev;
574 struct pci_dev *pdev = adapter->pdev;
575 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
576 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
577 struct sk_buff *skb;
578 unsigned int i;
7c6e0a43 579 u32 len, staterr;
177db6ff
MC		 580 u16 hdr_info;
581 bool cleaned = false;
9a799d71 582 int cleaned_count = 0;
d2f4fbe2 583 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
9a799d71
AK		 584
585 i = rx_ring->next_to_clean;
9a799d71
AK		 586 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
587 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
588 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 589
590 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 591 u32 upper_len = 0;
9a799d71
AK		 592 if (*work_done >= work_to_do)
593 break;
594 (*work_done)++;
595
596 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43
JB		 597 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
598 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
599 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 600 if (hdr_info & IXGBE_RXDADV_SPH)
601 adapter->rx_hdr_split++;
602 if (len > IXGBE_RX_HDR_SIZE)
603 len = IXGBE_RX_HDR_SIZE;
604 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 605 } else {
9a799d71 606 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 607 }
9a799d71
AK		 608
609 cleaned = true;
610 skb = rx_buffer_info->skb;
611 prefetch(skb->data - NET_IP_ALIGN);
612 rx_buffer_info->skb = NULL;
613
614 if (len && !skb_shinfo(skb)->nr_frags) {
615 pci_unmap_single(pdev, rx_buffer_info->dma,
7c6e0a43
JB		 616 rx_ring->rx_buf_len + NET_IP_ALIGN,
617 PCI_DMA_FROMDEVICE);
9a799d71
AK		 618 skb_put(skb, len);
619 }
620
621 if (upper_len) {
622 pci_unmap_page(pdev, rx_buffer_info->page_dma,
623 PAGE_SIZE, PCI_DMA_FROMDEVICE);
624 rx_buffer_info->page_dma = 0;
625 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
626 rx_buffer_info->page, 0, upper_len);
627 rx_buffer_info->page = NULL;
628
629 skb->len += upper_len;
630 skb->data_len += upper_len;
631 skb->truesize += upper_len;
632 }
633
634 i++;
635 if (i == rx_ring->count)
636 i = 0;
637 next_buffer = &rx_ring->rx_buffer_info[i];
638
639 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
640 prefetch(next_rxd);
641
642 cleaned_count++;
643 if (staterr & IXGBE_RXD_STAT_EOP) {
644 rx_ring->stats.packets++;
645 rx_ring->stats.bytes += skb->len;
646 } else {
647 rx_buffer_info->skb = next_buffer->skb;
648 rx_buffer_info->dma = next_buffer->dma;
649 next_buffer->skb = skb;
650 adapter->non_eop_descs++;
651 goto next_desc;
652 }
653
654 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
655 dev_kfree_skb_irq(skb);
656 goto next_desc;
657 }
658
659 ixgbe_rx_checksum(adapter, staterr, skb);
d2f4fbe2
AV		 660
661 /* probably a little skewed due to removing CRC */
662 total_rx_bytes += skb->len;
663 total_rx_packets++;
664
9a799d71 665 skb->protocol = eth_type_trans(skb, netdev);
177db6ff 666 ixgbe_receive_skb(adapter, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 667 netdev->last_rx = jiffies;
668
669next_desc:
670 rx_desc->wb.upper.status_error = 0;
671
672 /* return some buffers to hardware, one at a time is too slow */
673 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
674 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
675 cleaned_count = 0;
676 }
677
678 /* use prefetched values */
679 rx_desc = next_rxd;
680 rx_buffer_info = next_buffer;
681
682 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 683 }
684
685 if (rx_ring->lro_used) {
686 lro_flush_all(&rx_ring->lro_mgr);
687 rx_ring->lro_used = false;
9a799d71
AK		 688 }
689
690 rx_ring->next_to_clean = i;
691 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
692
693 if (cleaned_count)
694 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
695
f494e8fa
AV		 696 rx_ring->total_packets += total_rx_packets;
697 rx_ring->total_bytes += total_rx_bytes;
698 adapter->net_stats.rx_bytes += total_rx_bytes;
699 adapter->net_stats.rx_packets += total_rx_packets;
700
9a799d71
AK		 701 return cleaned;
702}
703
021230d4 704static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 705/**
706 * ixgbe_configure_msix - Configure MSI-X hardware
707 * @adapter: board private structure
708 *
709 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
710 * interrupts.
711 **/
712static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
713{
021230d4
AV		 714 struct ixgbe_q_vector *q_vector;
715 int i, j, q_vectors, v_idx, r_idx;
716 u32 mask;
9a799d71 717
021230d4 718 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 719
021230d4
AV		 720 /* Populate the IVAR table and set the ITR values to the
721 * corresponding register.
722 */
723 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
724 q_vector = &adapter->q_vector[v_idx];
725 /* XXX for_each_bit(...) */
726 r_idx = find_first_bit(q_vector->rxr_idx,
727 adapter->num_rx_queues);
728
729 for (i = 0; i < q_vector->rxr_count; i++) {
730 j = adapter->rx_ring[r_idx].reg_idx;
731 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(j), v_idx);
732 r_idx = find_next_bit(q_vector->rxr_idx,
733 adapter->num_rx_queues,
734 r_idx + 1);
735 }
736 r_idx = find_first_bit(q_vector->txr_idx,
737 adapter->num_tx_queues);
738
739 for (i = 0; i < q_vector->txr_count; i++) {
740 j = adapter->tx_ring[r_idx].reg_idx;
741 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(j), v_idx);
742 r_idx = find_next_bit(q_vector->txr_idx,
743 adapter->num_tx_queues,
744 r_idx + 1);
745 }
746
747 /* if this is a tx only vector use half the irq (tx) rate */
748 if (q_vector->txr_count && !q_vector->rxr_count)
749 q_vector->eitr = adapter->tx_eitr;
750 else
751 /* rx only or mixed */
752 q_vector->eitr = adapter->rx_eitr;
753
754 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
755 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
9a799d71
AK		 756 }
757
021230d4
AV		 758 ixgbe_set_ivar(adapter, IXGBE_IVAR_OTHER_CAUSES_INDEX, v_idx);
759 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
760
761 /* set up to autoclear timer, lsc, and the vectors */
762 mask = IXGBE_EIMS_ENABLE_MASK;
763 mask &= ~IXGBE_EIMS_OTHER;
764 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 765}
766
f494e8fa
AV		 767enum latency_range {
768 lowest_latency = 0,
769 low_latency = 1,
770 bulk_latency = 2,
771 latency_invalid = 255
772};
773
774/**
775 * ixgbe_update_itr - update the dynamic ITR value based on statistics
776 * @adapter: pointer to adapter
777 * @eitr: eitr setting (ints per sec) to give last timeslice
778 * @itr_setting: current throttle rate in ints/second
779 * @packets: the number of packets during this measurement interval
780 * @bytes: the number of bytes during this measurement interval
781 *
782 * Stores a new ITR value based on packets and byte
783 * counts during the last interrupt. The advantage of per interrupt
784 * computation is faster updates and more accurate ITR for the current
785 * traffic pattern. Constants in this function were computed
786 * based on theoretical maximum wire speed and thresholds were set based
787 * on testing data as well as attempting to minimize response time
788 * while increasing bulk throughput.
789 * this functionality is controlled by the InterruptThrottleRate module
790 * parameter (see ixgbe_param.c)
791 **/
792static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
793 u32 eitr, u8 itr_setting,
794 int packets, int bytes)
795{
796 unsigned int retval = itr_setting;
797 u32 timepassed_us;
798 u64 bytes_perint;
799
800 if (packets == 0)
801 goto update_itr_done;
802
803
804 /* simple throttlerate management
805 * 0-20MB/s lowest (100000 ints/s)
806 * 20-100MB/s low (20000 ints/s)
807 * 100-1249MB/s bulk (8000 ints/s)
808 */
809 /* what was last interrupt timeslice? */
810 timepassed_us = 1000000/eitr;
811 bytes_perint = bytes / timepassed_us; /* bytes/usec */
812
813 switch (itr_setting) {
814 case lowest_latency:
815 if (bytes_perint > adapter->eitr_low)
816 retval = low_latency;
817 break;
818 case low_latency:
819 if (bytes_perint > adapter->eitr_high)
820 retval = bulk_latency;
821 else if (bytes_perint <= adapter->eitr_low)
822 retval = lowest_latency;
823 break;
824 case bulk_latency:
825 if (bytes_perint <= adapter->eitr_high)
826 retval = low_latency;
827 break;
828 }
829
830update_itr_done:
831 return retval;
832}
833
834static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
835{
836 struct ixgbe_adapter *adapter = q_vector->adapter;
837 struct ixgbe_hw *hw = &adapter->hw;
838 u32 new_itr;
839 u8 current_itr, ret_itr;
840 int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
841 sizeof(struct ixgbe_q_vector);
842 struct ixgbe_ring *rx_ring, *tx_ring;
843
844 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
845 for (i = 0; i < q_vector->txr_count; i++) {
846 tx_ring = &(adapter->tx_ring[r_idx]);
847 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
848 q_vector->tx_eitr,
849 tx_ring->total_packets,
850 tx_ring->total_bytes);
851 /* if the result for this queue would decrease interrupt
852 * rate for this vector then use that result */
853 q_vector->tx_eitr = ((q_vector->tx_eitr > ret_itr) ?
854 q_vector->tx_eitr - 1 : ret_itr);
855 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
856 r_idx + 1);
857 }
858
859 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
860 for (i = 0; i < q_vector->rxr_count; i++) {
861 rx_ring = &(adapter->rx_ring[r_idx]);
862 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
863 q_vector->rx_eitr,
864 rx_ring->total_packets,
865 rx_ring->total_bytes);
866 /* if the result for this queue would decrease interrupt
867 * rate for this vector then use that result */
868 q_vector->rx_eitr = ((q_vector->rx_eitr > ret_itr) ?
869 q_vector->rx_eitr - 1 : ret_itr);
870 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
871 r_idx + 1);
872 }
873
874 current_itr = max(q_vector->rx_eitr, q_vector->tx_eitr);
875
876 switch (current_itr) {
877 /* counts and packets in update_itr are dependent on these numbers */
878 case lowest_latency:
879 new_itr = 100000;
880 break;
881 case low_latency:
882 new_itr = 20000; /* aka hwitr = ~200 */
883 break;
884 case bulk_latency:
885 default:
886 new_itr = 8000;
887 break;
888 }
889
890 if (new_itr != q_vector->eitr) {
891 u32 itr_reg;
892 /* do an exponential smoothing */
893 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
894 q_vector->eitr = new_itr;
895 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
896 /* must write high and low 16 bits to reset counter */
897 DPRINTK(TX_ERR, DEBUG, "writing eitr(%d): %08X\n", v_idx,
898 itr_reg);
899 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg | (itr_reg)<<16);
900 }
901
902 return;
903}
904
9a799d71
AK		 905static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
906{
907 struct net_device *netdev = data;
908 struct ixgbe_adapter *adapter = netdev_priv(netdev);
909 struct ixgbe_hw *hw = &adapter->hw;
910 u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
911
912 if (eicr & IXGBE_EICR_LSC) {
913 adapter->lsc_int++;
914 if (!test_bit(__IXGBE_DOWN, &adapter->state))
915 mod_timer(&adapter->watchdog_timer, jiffies);
916 }
d4f80882
AV		 917
918 if (!test_bit(__IXGBE_DOWN, &adapter->state))
919 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 920
921 return IRQ_HANDLED;
922}
923
924static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
925{
021230d4
AV		 926 struct ixgbe_q_vector *q_vector = data;
927 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 928 struct ixgbe_ring *tx_ring;
021230d4
AV		 929 int i, r_idx;
930
931 if (!q_vector->txr_count)
932 return IRQ_HANDLED;
933
934 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
935 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 936 tx_ring = &(adapter->tx_ring[r_idx]);
96b0e0f6 937#if defined(CONFIG_DCA) || defined (CONFIG_DCA_MODULE)
bd0362dd 938 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 939 ixgbe_update_tx_dca(adapter, tx_ring);
bd0362dd 940#endif
3a581073
JB		 941 tx_ring->total_bytes = 0;
942 tx_ring->total_packets = 0;
943 ixgbe_clean_tx_irq(adapter, tx_ring);
021230d4
AV		 944 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
945 r_idx + 1);
946 }
9a799d71 947
9a799d71
AK		 948 return IRQ_HANDLED;
949}
950
021230d4
AV		 951/**
952 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
953 * @irq: unused
954 * @data: pointer to our q_vector struct for this interrupt vector
955 **/
9a799d71
AK		 956static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
957{
021230d4
AV		 958 struct ixgbe_q_vector *q_vector = data;
959 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 960 struct ixgbe_ring *rx_ring;
021230d4
AV		 961 int r_idx;
962
963 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
964 if (!q_vector->rxr_count)
965 return IRQ_HANDLED;
966
3a581073 967 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 968 /* disable interrupts on this vector only */
3a581073
JB		 969 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
970 rx_ring->total_bytes = 0;
971 rx_ring->total_packets = 0;
021230d4
AV		 972 netif_rx_schedule(adapter->netdev, &q_vector->napi);
973
974 return IRQ_HANDLED;
975}
976
977static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
978{
979 ixgbe_msix_clean_rx(irq, data);
980 ixgbe_msix_clean_tx(irq, data);
9a799d71 981
9a799d71
AK		 982 return IRQ_HANDLED;
983}
984
021230d4
AV		 985/**
986 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
987 * @napi: napi struct with our devices info in it
988 * @budget: amount of work driver is allowed to do this pass, in packets
989 *
990 **/
9a799d71
AK		 991static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
992{
021230d4
AV		 993 struct ixgbe_q_vector *q_vector =
994 container_of(napi, struct ixgbe_q_vector, napi);
995 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 996 struct ixgbe_ring *rx_ring;
9a799d71 997 int work_done = 0;
021230d4 998 long r_idx;
9a799d71 999
021230d4 1000 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1001 rx_ring = &(adapter->rx_ring[r_idx]);
96b0e0f6 1002#if defined(CONFIG_DCA) || defined (CONFIG_DCA_MODULE)
bd0362dd 1003 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1004 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1005#endif
9a799d71 1006
3a581073 1007 ixgbe_clean_rx_irq(adapter, rx_ring, &work_done, budget);
9a799d71 1008
021230d4
AV		 1009 /* If all Rx work done, exit the polling mode */
1010 if (work_done < budget) {
1011 netif_rx_complete(adapter->netdev, napi);
f494e8fa
AV		 1012 if (adapter->rx_eitr < IXGBE_MIN_ITR_USECS)
1013 ixgbe_set_itr_msix(q_vector);
9a799d71 1014 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3a581073 1015 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx);
9a799d71
AK		 1016 }
1017
1018 return work_done;
1019}
1020
021230d4
AV		 1021static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1022 int r_idx)
1023{
1024 a->q_vector[v_idx].adapter = a;
1025 set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1026 a->q_vector[v_idx].rxr_count++;
1027 a->rx_ring[r_idx].v_idx = 1 << v_idx;
1028}
1029
1030static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1031 int r_idx)
1032{
1033 a->q_vector[v_idx].adapter = a;
1034 set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1035 a->q_vector[v_idx].txr_count++;
1036 a->tx_ring[r_idx].v_idx = 1 << v_idx;
1037}
1038
9a799d71 1039/**
021230d4
AV		 1040 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1041 * @adapter: board private structure to initialize
1042 * @vectors: allotted vector count for descriptor rings
9a799d71 1043 *
021230d4
AV		 1044 * This function maps descriptor rings to the queue-specific vectors
1045 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1046 * one vector per ring/queue, but on a constrained vector budget, we
1047 * group the rings as "efficiently" as possible. You would add new
1048 * mapping configurations in here.
9a799d71 1049 **/
021230d4
AV		 1050static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1051 int vectors)
1052{
1053 int v_start = 0;
1054 int rxr_idx = 0, txr_idx = 0;
1055 int rxr_remaining = adapter->num_rx_queues;
1056 int txr_remaining = adapter->num_tx_queues;
1057 int i, j;
1058 int rqpv, tqpv;
1059 int err = 0;
1060
1061 /* No mapping required if MSI-X is disabled. */
1062 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1063 goto out;
9a799d71 1064
021230d4
AV		 1065 /*
1066 * The ideal configuration...
1067 * We have enough vectors to map one per queue.
1068 */
1069 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1070 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1071 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1072
021230d4
AV		 1073 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1074 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1075
9a799d71 1076 goto out;
021230d4 1077 }
9a799d71 1078
021230d4
AV		 1079 /*
1080 * If we don't have enough vectors for a 1-to-1
1081 * mapping, we'll have to group them so there are
1082 * multiple queues per vector.
1083 */
1084 /* Re-adjusting *qpv takes care of the remainder. */
1085 for (i = v_start; i < vectors; i++) {
1086 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1087 for (j = 0; j < rqpv; j++) {
1088 map_vector_to_rxq(adapter, i, rxr_idx);
1089 rxr_idx++;
1090 rxr_remaining--;
1091 }
1092 }
1093 for (i = v_start; i < vectors; i++) {
1094 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1095 for (j = 0; j < tqpv; j++) {
1096 map_vector_to_txq(adapter, i, txr_idx);
1097 txr_idx++;
1098 txr_remaining--;
9a799d71 1099 }
9a799d71
AK		 1100 }
1101
021230d4
AV		 1102out:
1103 return err;
1104}
1105
1106/**
1107 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1108 * @adapter: board private structure
1109 *
1110 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1111 * interrupts from the kernel.
1112 **/
1113static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1114{
1115 struct net_device *netdev = adapter->netdev;
1116 irqreturn_t (*handler)(int, void *);
1117 int i, vector, q_vectors, err;
1118
1119 /* Decrement for Other and TCP Timer vectors */
1120 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1121
1122 /* Map the Tx/Rx rings to the vectors we were allotted. */
1123 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1124 if (err)
1125 goto out;
1126
1127#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1128 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1129 &ixgbe_msix_clean_many)
1130 for (vector = 0; vector < q_vectors; vector++) {
1131 handler = SET_HANDLER(&adapter->q_vector[vector]);
1132 sprintf(adapter->name[vector], "%s:v%d-%s",
1133 netdev->name, vector,
1134 (handler == &ixgbe_msix_clean_rx) ? "Rx" :
1135 ((handler == &ixgbe_msix_clean_tx) ? "Tx" : "TxRx"));
1136 err = request_irq(adapter->msix_entries[vector].vector,
1137 handler, 0, adapter->name[vector],
1138 &(adapter->q_vector[vector]));
9a799d71
AK		 1139 if (err) {
1140 DPRINTK(PROBE, ERR,
1141 "request_irq failed for MSIX interrupt "
1142 "Error: %d\n", err);
021230d4 1143 goto free_queue_irqs;
9a799d71 1144 }
9a799d71
AK		 1145 }
1146
021230d4
AV		 1147 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1148 err = request_irq(adapter->msix_entries[vector].vector,
1149 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1150 if (err) {
1151 DPRINTK(PROBE, ERR,
1152 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1153 goto free_queue_irqs;
9a799d71
AK		 1154 }
1155
9a799d71
AK		 1156 return 0;
1157
021230d4
AV		 1158free_queue_irqs:
1159 for (i = vector - 1; i >= 0; i--)
1160 free_irq(adapter->msix_entries[--vector].vector,
1161 &(adapter->q_vector[i]));
1162 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1163 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1164 kfree(adapter->msix_entries);
1165 adapter->msix_entries = NULL;
021230d4 1166out:
9a799d71
AK		 1167 return err;
1168}
1169
f494e8fa
AV		 1170static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1171{
1172 struct ixgbe_hw *hw = &adapter->hw;
1173 struct ixgbe_q_vector *q_vector = adapter->q_vector;
1174 u8 current_itr;
1175 u32 new_itr = q_vector->eitr;
1176 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1177 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1178
1179 q_vector->tx_eitr = ixgbe_update_itr(adapter, new_itr,
1180 q_vector->tx_eitr,
1181 tx_ring->total_packets,
1182 tx_ring->total_bytes);
1183 q_vector->rx_eitr = ixgbe_update_itr(adapter, new_itr,
1184 q_vector->rx_eitr,
1185 rx_ring->total_packets,
1186 rx_ring->total_bytes);
1187
1188 current_itr = max(q_vector->rx_eitr, q_vector->tx_eitr);
1189
1190 switch (current_itr) {
1191 /* counts and packets in update_itr are dependent on these numbers */
1192 case lowest_latency:
1193 new_itr = 100000;
1194 break;
1195 case low_latency:
1196 new_itr = 20000; /* aka hwitr = ~200 */
1197 break;
1198 case bulk_latency:
1199 new_itr = 8000;
1200 break;
1201 default:
1202 break;
1203 }
1204
1205 if (new_itr != q_vector->eitr) {
1206 u32 itr_reg;
1207 /* do an exponential smoothing */
1208 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1209 q_vector->eitr = new_itr;
1210 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1211 /* must write high and low 16 bits to reset counter */
1212 IXGBE_WRITE_REG(hw, IXGBE_EITR(0), itr_reg | (itr_reg)<<16);
1213 }
1214
1215 return;
1216}
1217
021230d4
AV		 1218static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter);
1219
9a799d71 1220/**
021230d4 1221 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1222 * @irq: interrupt number
1223 * @data: pointer to a network interface device structure
1224 * @pt_regs: CPU registers structure
1225 **/
1226static irqreturn_t ixgbe_intr(int irq, void *data)
1227{
1228 struct net_device *netdev = data;
1229 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1230 struct ixgbe_hw *hw = &adapter->hw;
1231 u32 eicr;
1232
9a799d71 1233
021230d4
AV		 1234 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1235 * therefore no explict interrupt disable is necessary */
1236 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
9a799d71
AK		 1237 if (!eicr)
1238 return IRQ_NONE; /* Not our interrupt */
1239
1240 if (eicr & IXGBE_EICR_LSC) {
1241 adapter->lsc_int++;
1242 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1243 mod_timer(&adapter->watchdog_timer, jiffies);
1244 }
021230d4
AV		 1245
1246
1247 if (netif_rx_schedule_prep(netdev, &adapter->q_vector[0].napi)) {
f494e8fa
AV		 1248 adapter->tx_ring[0].total_packets = 0;
1249 adapter->tx_ring[0].total_bytes = 0;
1250 adapter->rx_ring[0].total_packets = 0;
1251 adapter->rx_ring[0].total_bytes = 0;
021230d4
AV		 1252 /* would disable interrupts here but EIAM disabled it */
1253 __netif_rx_schedule(netdev, &adapter->q_vector[0].napi);
9a799d71
AK		 1254 }
1255
1256 return IRQ_HANDLED;
1257}
1258
021230d4
AV		 1259static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1260{
1261 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1262
1263 for (i = 0; i < q_vectors; i++) {
1264 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1265 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1266 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1267 q_vector->rxr_count = 0;
1268 q_vector->txr_count = 0;
1269 }
1270}
1271
9a799d71
AK		 1272/**
1273 * ixgbe_request_irq - initialize interrupts
1274 * @adapter: board private structure
1275 *
1276 * Attempts to configure interrupts using the best available
1277 * capabilities of the hardware and kernel.
1278 **/
021230d4 1279static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1280{
1281 struct net_device *netdev = adapter->netdev;
021230d4 1282 int err;
9a799d71 1283
021230d4
AV		 1284 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1285 err = ixgbe_request_msix_irqs(adapter);
1286 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1287 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1288 netdev->name, netdev);
1289 } else {
1290 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1291 netdev->name, netdev);
9a799d71
AK		 1292 }
1293
9a799d71
AK		 1294 if (err)
1295 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1296
9a799d71
AK		 1297 return err;
1298}
1299
1300static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1301{
1302 struct net_device *netdev = adapter->netdev;
1303
1304 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1305 int i, q_vectors;
9a799d71 1306
021230d4
AV		 1307 q_vectors = adapter->num_msix_vectors;
1308
1309 i = q_vectors - 1;
9a799d71 1310 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1311
021230d4
AV		 1312 i--;
1313 for (; i >= 0; i--) {
1314 free_irq(adapter->msix_entries[i].vector,
1315 &(adapter->q_vector[i]));
1316 }
1317
1318 ixgbe_reset_q_vectors(adapter);
1319 } else {
1320 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1321 }
1322}
1323
1324/**
1325 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1326 * @adapter: board private structure
1327 **/
1328static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1329{
9a799d71
AK		 1330 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1331 IXGBE_WRITE_FLUSH(&adapter->hw);
021230d4
AV		 1332 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1333 int i;
1334 for (i = 0; i < adapter->num_msix_vectors; i++)
1335 synchronize_irq(adapter->msix_entries[i].vector);
1336 } else {
1337 synchronize_irq(adapter->pdev->irq);
1338 }
9a799d71
AK		 1339}
1340
1341/**
1342 * ixgbe_irq_enable - Enable default interrupt generation settings
1343 * @adapter: board private structure
1344 **/
1345static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1346{
021230d4
AV		 1347 u32 mask;
1348 mask = IXGBE_EIMS_ENABLE_MASK;
1349 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
d4f80882 1350 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 1351}
1352
1353/**
1354 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1355 *
1356 **/
1357static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1358{
9a799d71
AK		 1359 struct ixgbe_hw *hw = &adapter->hw;
1360
021230d4
AV		 1361 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1362 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr));
9a799d71
AK		 1363
1364 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(0), 0);
021230d4
AV		 1365 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(0), 0);
1366
1367 map_vector_to_rxq(adapter, 0, 0);
1368 map_vector_to_txq(adapter, 0, 0);
1369
1370 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1371}
1372
1373/**
3a581073 1374 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1375 * @adapter: board private structure
1376 *
1377 * Configure the Tx unit of the MAC after a reset.
1378 **/
1379static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1380{
e01c31a5 1381 u64 tdba, tdwba;
9a799d71 1382 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1383 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1384
1385 /* Setup the HW Tx Head and Tail descriptor pointers */
1386 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1387 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1388 j = ring->reg_idx;
1389 tdba = ring->dma;
1390 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1391 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
e01c31a5 1392 (tdba & DMA_32BIT_MASK));
021230d4 1393 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
e01c31a5
JB		 1394 tdwba = ring->dma +
1395 (ring->count * sizeof(union ixgbe_adv_tx_desc));
1396 tdwba |= IXGBE_TDWBAL_HEAD_WB_ENABLE;
1397 IXGBE_WRITE_REG(hw, IXGBE_TDWBAL(j), tdwba & DMA_32BIT_MASK);
1398 IXGBE_WRITE_REG(hw, IXGBE_TDWBAH(j), (tdwba >> 32));
021230d4
AV		 1399 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1400 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1401 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1402 adapter->tx_ring[i].head = IXGBE_TDH(j);
1403 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1404 /* Disable Tx Head Writeback RO bit, since this hoses
1405 * bookkeeping if things aren't delivered in order.
1406 */
e01c31a5 1407 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1408 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1409 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1410 }
9a799d71
AK		 1411}
1412
cc41ac7c
JB		 1413#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1414
1415static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1416{
1417 struct ixgbe_ring *rx_ring;
1418 u32 srrctl;
1419 int queue0;
1420 unsigned long *mask, maskval = 1;
1421 long shift, len;
1422
1423 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
1424 mask = (unsigned long *) &adapter->ring_feature[RING_F_RSS].mask;
1425 len = sizeof(adapter->ring_feature[RING_F_RSS].mask) * 8;
1426 } else {
1427 mask = &maskval;
1428 len = 1;
1429 }
1430 shift = find_first_bit(mask, len);
1431 queue0 = index << shift;
1432 rx_ring = &adapter->rx_ring[queue0];
1433
1434 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1435
1436 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1437 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1438
1439 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1440 srrctl |= IXGBE_RXBUFFER_2048 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1441 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1442 srrctl |= ((IXGBE_RX_HDR_SIZE <<
1443 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1444 IXGBE_SRRCTL_BSIZEHDR_MASK);
1445 } else {
1446 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1447
1448 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1449 srrctl |= IXGBE_RXBUFFER_2048 >>
1450 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1451 else
1452 srrctl |= rx_ring->rx_buf_len >>
1453 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1454 }
1455 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1456}
9a799d71 1457
177db6ff
MC		 1458/**
1459 * ixgbe_get_skb_hdr - helper function for LRO header processing
1460 * @skb: pointer to sk_buff to be added to LRO packet
1461 * @iphdr: pointer to tcp header structure
1462 * @tcph: pointer to tcp header structure
1463 * @hdr_flags: pointer to header flags
1464 * @priv: private data
1465 **/
1466static int ixgbe_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
1467 u64 *hdr_flags, void *priv)
1468{
1469 union ixgbe_adv_rx_desc *rx_desc = priv;
1470
1471 /* Verify that this is a valid IPv4 TCP packet */
e9990a9c
JB		 1472 if (!((ixgbe_get_pkt_info(rx_desc) & IXGBE_RXDADV_PKTTYPE_IPV4) &&
1473 (ixgbe_get_pkt_info(rx_desc) & IXGBE_RXDADV_PKTTYPE_TCP)))
177db6ff
MC		 1474 return -1;
1475
1476 /* Set network headers */
1477 skb_reset_network_header(skb);
1478 skb_set_transport_header(skb, ip_hdrlen(skb));
1479 *iphdr = ip_hdr(skb);
1480 *tcph = tcp_hdr(skb);
1481 *hdr_flags = LRO_IPV4 | LRO_TCP;
1482 return 0;
1483}
1484
cc41ac7c
JB		 1485#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1486 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1487
9a799d71 1488/**
3a581073 1489 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1490 * @adapter: board private structure
1491 *
1492 * Configure the Rx unit of the MAC after a reset.
1493 **/
1494static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1495{
1496 u64 rdba;
1497 struct ixgbe_hw *hw = &adapter->hw;
1498 struct net_device *netdev = adapter->netdev;
1499 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1500 int i, j;
9a799d71 1501 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1502 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1503 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1504 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1505 u32 fctrl, hlreg0;
9a799d71 1506 u32 pages;
cc41ac7c
JB		 1507 u32 reta = 0, mrqc;
1508 u32 rdrxctl;
7c6e0a43 1509 int rx_buf_len;
9a799d71
AK		 1510
1511 /* Decide whether to use packet split mode or not */
1512 if (netdev->mtu > ETH_DATA_LEN)
1513 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1514 else
1515 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
1516
1517 /* Set the RX buffer length according to the mode */
1518 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 1519 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71
AK		 1520 } else {
1521 if (netdev->mtu <= ETH_DATA_LEN)
7c6e0a43 1522 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 1523 else
7c6e0a43 1524 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 1525 }
1526
1527 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1528 fctrl |= IXGBE_FCTRL_BAM;
021230d4 1529 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
9a799d71
AK		 1530 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1531
1532 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1533 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1534 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1535 else
1536 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1537 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1538
1539 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1540
9a799d71
AK		 1541 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1542 /* disable receives while setting up the descriptors */
1543 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1544 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1545
1546 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1547 * the Base and Length of the Rx Descriptor Ring */
1548 for (i = 0; i < adapter->num_rx_queues; i++) {
1549 rdba = adapter->rx_ring[i].dma;
7c6e0a43
JB		 1550 j = adapter->rx_ring[i].reg_idx;
1551 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK));
1552 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1553 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1554 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1555 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1556 adapter->rx_ring[i].head = IXGBE_RDH(j);
1557 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1558 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
e9990a9c
JB		 1559 /* Intitial LRO Settings */
1560 adapter->rx_ring[i].lro_mgr.max_aggr = IXGBE_MAX_LRO_AGGREGATE;
1561 adapter->rx_ring[i].lro_mgr.max_desc = IXGBE_MAX_LRO_DESCRIPTORS;
1562 adapter->rx_ring[i].lro_mgr.get_skb_header = ixgbe_get_skb_hdr;
1563 adapter->rx_ring[i].lro_mgr.features = LRO_F_EXTRACT_VLAN_ID;
1564 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1565 adapter->rx_ring[i].lro_mgr.features |= LRO_F_NAPI;
1566 adapter->rx_ring[i].lro_mgr.dev = adapter->netdev;
1567 adapter->rx_ring[i].lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1568 adapter->rx_ring[i].lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
cc41ac7c
JB		 1569
1570 ixgbe_configure_srrctl(adapter, j);
9a799d71
AK		 1571 }
1572
cc41ac7c
JB		 1573 /*
1574 * For VMDq support of different descriptor types or
1575 * buffer sizes through the use of multiple SRRCTL
1576 * registers, RDRXCTL.MVMEN must be set to 1
1577 *
1578 * also, the manual doesn't mention it clearly but DCA hints
1579 * will only use queue 0's tags unless this bit is set. Side
1580 * effects of setting this bit are only that SRRCTL must be
1581 * fully programmed [0..15]
1582 */
1583 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1584 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1585 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1586
177db6ff 1587
021230d4 1588 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 1589 /* Fill out redirection table */
021230d4
AV		 1590 for (i = 0, j = 0; i < 128; i++, j++) {
1591 if (j == adapter->ring_feature[RING_F_RSS].indices)
1592 j = 0;
1593 /* reta = 4-byte sliding window of
1594 * 0x00..(indices-1)(indices-1)00..etc. */
1595 reta = (reta << 8) | (j * 0x11);
1596 if ((i & 3) == 3)
1597 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 1598 }
1599
1600 /* Fill out hash function seeds */
1601 for (i = 0; i < 10; i++)
7c6e0a43 1602 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71
AK		 1603
1604 mrqc = IXGBE_MRQC_RSSEN
1605 /* Perform hash on these packet types */
7c6e0a43
JB		 1606 | IXGBE_MRQC_RSS_FIELD_IPV4
1607 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1608 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1609 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
1610 | IXGBE_MRQC_RSS_FIELD_IPV6_EX
1611 | IXGBE_MRQC_RSS_FIELD_IPV6
1612 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1613 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
1614 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
9a799d71 1615 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
021230d4 1616 }
9a799d71 1617
021230d4
AV		 1618 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1619
1620 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1621 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1622 /* Disable indicating checksum in descriptor, enables
1623 * RSS hash */
9a799d71 1624 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 1625 }
021230d4
AV		 1626 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1627 /* Enable IPv4 payload checksum for UDP fragments
1628 * if PCSD is not set */
1629 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1630 }
1631
1632 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
9a799d71
AK		 1633}
1634
1635static void ixgbe_vlan_rx_register(struct net_device *netdev,
1636 struct vlan_group *grp)
1637{
1638 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1639 u32 ctrl;
1640
d4f80882
AV		 1641 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1642 ixgbe_irq_disable(adapter);
9a799d71
AK		 1643 adapter->vlgrp = grp;
1644
1645 if (grp) {
1646 /* enable VLAN tag insert/strip */
1647 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
746b9f02 1648 ctrl |= IXGBE_VLNCTRL_VME;
9a799d71
AK		 1649 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1650 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1651 }
1652
d4f80882
AV		 1653 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1654 ixgbe_irq_enable(adapter);
9a799d71
AK		 1655}
1656
1657static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1658{
1659 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1660
1661 /* add VID to filter table */
1662 ixgbe_set_vfta(&adapter->hw, vid, 0, true);
1663}
1664
1665static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1666{
1667 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1668
d4f80882
AV		 1669 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1670 ixgbe_irq_disable(adapter);
1671
9a799d71 1672 vlan_group_set_device(adapter->vlgrp, vid, NULL);
d4f80882
AV		 1673
1674 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1675 ixgbe_irq_enable(adapter);
9a799d71
AK		 1676
1677 /* remove VID from filter table */
1678 ixgbe_set_vfta(&adapter->hw, vid, 0, false);
1679}
1680
1681static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1682{
1683 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1684
1685 if (adapter->vlgrp) {
1686 u16 vid;
1687 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1688 if (!vlan_group_get_device(adapter->vlgrp, vid))
1689 continue;
1690 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1691 }
1692 }
1693}
1694
2c5645cf
CL		 1695static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
1696{
1697 struct dev_mc_list *mc_ptr;
1698 u8 *addr = *mc_addr_ptr;
1699 *vmdq = 0;
1700
1701 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
1702 if (mc_ptr->next)
1703 *mc_addr_ptr = mc_ptr->next->dmi_addr;
1704 else
1705 *mc_addr_ptr = NULL;
1706
1707 return addr;
1708}
1709
9a799d71 1710/**
2c5645cf 1711 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 1712 * @netdev: network interface device structure
1713 *
2c5645cf
CL		 1714 * The set_rx_method entry point is called whenever the unicast/multicast
1715 * address list or the network interface flags are updated. This routine is
1716 * responsible for configuring the hardware for proper unicast, multicast and
1717 * promiscuous mode.
9a799d71 1718 **/
2c5645cf 1719static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 1720{
1721 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1722 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 1723 u32 fctrl, vlnctrl;
2c5645cf
CL		 1724 u8 *addr_list = NULL;
1725 int addr_count = 0;
9a799d71
AK		 1726
1727 /* Check for Promiscuous and All Multicast modes */
1728
1729 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 1730 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 1731
1732 if (netdev->flags & IFF_PROMISC) {
2c5645cf 1733 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 1734 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 1735 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 1736 } else {
746b9f02
PM		 1737 if (netdev->flags & IFF_ALLMULTI) {
1738 fctrl |= IXGBE_FCTRL_MPE;
1739 fctrl &= ~IXGBE_FCTRL_UPE;
1740 } else {
1741 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1742 }
3d01625a 1743 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 1744 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 1745 }
1746
1747 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 1748 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 1749
2c5645cf
CL		 1750 /* reprogram secondary unicast list */
1751 addr_count = netdev->uc_count;
1752 if (addr_count)
1753 addr_list = netdev->uc_list->dmi_addr;
1754 ixgbe_update_uc_addr_list(hw, addr_list, addr_count,
1755 ixgbe_addr_list_itr);
9a799d71 1756
2c5645cf
CL		 1757 /* reprogram multicast list */
1758 addr_count = netdev->mc_count;
1759 if (addr_count)
1760 addr_list = netdev->mc_list->dmi_addr;
1761 ixgbe_update_mc_addr_list(hw, addr_list, addr_count,
1762 ixgbe_addr_list_itr);
9a799d71
AK		 1763}
1764
021230d4
AV		 1765static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
1766{
1767 int q_idx;
1768 struct ixgbe_q_vector *q_vector;
1769 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1770
1771 /* legacy and MSI only use one vector */
1772 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1773 q_vectors = 1;
1774
1775 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1776 q_vector = &adapter->q_vector[q_idx];
1777 if (!q_vector->rxr_count)
1778 continue;
1779 napi_enable(&q_vector->napi);
1780 }
1781}
1782
1783static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
1784{
1785 int q_idx;
1786 struct ixgbe_q_vector *q_vector;
1787 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1788
1789 /* legacy and MSI only use one vector */
1790 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1791 q_vectors = 1;
1792
1793 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1794 q_vector = &adapter->q_vector[q_idx];
1795 if (!q_vector->rxr_count)
1796 continue;
1797 napi_disable(&q_vector->napi);
1798 }
1799}
1800
9a799d71
AK		 1801static void ixgbe_configure(struct ixgbe_adapter *adapter)
1802{
1803 struct net_device *netdev = adapter->netdev;
1804 int i;
1805
2c5645cf 1806 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 1807
1808 ixgbe_restore_vlan(adapter);
1809
1810 ixgbe_configure_tx(adapter);
1811 ixgbe_configure_rx(adapter);
1812 for (i = 0; i < adapter->num_rx_queues; i++)
1813 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
1814 (adapter->rx_ring[i].count - 1));
1815}
1816
1817static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
1818{
1819 struct net_device *netdev = adapter->netdev;
9a799d71 1820 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1821 int i, j = 0;
9a799d71 1822 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4
AV		 1823 u32 txdctl, rxdctl, mhadd;
1824 u32 gpie;
9a799d71 1825
5eba3699
AV		 1826 ixgbe_get_hw_control(adapter);
1827
021230d4
AV		 1828 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
1829 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 1830 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1831 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
1832 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
1833 } else {
1834 /* MSI only */
021230d4 1835 gpie = 0;
9a799d71 1836 }
021230d4
AV		 1837 /* XXX: to interrupt immediately for EICS writes, enable this */
1838 /* gpie |= IXGBE_GPIE_EIMEN; */
1839 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 1840 }
1841
021230d4
AV		 1842 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
1843 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
1844 * specifically only auto mask tx and rx interrupts */
1845 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
1846 }
9a799d71 1847
021230d4 1848 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 1849 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
1850 mhadd &= ~IXGBE_MHADD_MFS_MASK;
1851 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
1852
1853 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
1854 }
1855
1856 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 1857 j = adapter->tx_ring[i].reg_idx;
1858 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 1859 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
1860 txdctl |= (8 << 16);
9a799d71 1861 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 1862 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 1863 }
1864
1865 for (i = 0; i < adapter->num_rx_queues; i++) {
021230d4
AV		 1866 j = adapter->rx_ring[i].reg_idx;
1867 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
1868 /* enable PTHRESH=32 descriptors (half the internal cache)
1869 * and HTHRESH=0 descriptors (to minimize latency on fetch),
1870 * this also removes a pesky rx_no_buffer_count increment */
1871 rxdctl |= 0x0020;
9a799d71 1872 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 1873 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
9a799d71
AK		 1874 }
1875 /* enable all receives */
1876 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1877 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
1878 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxdctl);
1879
1880 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1881 ixgbe_configure_msix(adapter);
1882 else
1883 ixgbe_configure_msi_and_legacy(adapter);
1884
1885 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 1886 ixgbe_napi_enable_all(adapter);
1887
1888 /* clear any pending interrupts, may auto mask */
1889 IXGBE_READ_REG(hw, IXGBE_EICR);
1890
9a799d71
AK		 1891 ixgbe_irq_enable(adapter);
1892
1893 /* bring the link up in the watchdog, this could race with our first
1894 * link up interrupt but shouldn't be a problem */
1895 mod_timer(&adapter->watchdog_timer, jiffies);
1896 return 0;
1897}
1898
d4f80882
AV		 1899void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
1900{
1901 WARN_ON(in_interrupt());
1902 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
1903 msleep(1);
1904 ixgbe_down(adapter);
1905 ixgbe_up(adapter);
1906 clear_bit(__IXGBE_RESETTING, &adapter->state);
1907}
1908
9a799d71
AK		 1909int ixgbe_up(struct ixgbe_adapter *adapter)
1910{
1911 /* hardware has been reset, we need to reload some things */
1912 ixgbe_configure(adapter);
1913
1914 return ixgbe_up_complete(adapter);
1915}
1916
1917void ixgbe_reset(struct ixgbe_adapter *adapter)
1918{
1919 if (ixgbe_init_hw(&adapter->hw))
1920 DPRINTK(PROBE, ERR, "Hardware Error\n");
1921
1922 /* reprogram the RAR[0] in case user changed it. */
1923 ixgbe_set_rar(&adapter->hw, 0, adapter->hw.mac.addr, 0, IXGBE_RAH_AV);
1924
1925}
1926
1927#ifdef CONFIG_PM
1928static int ixgbe_resume(struct pci_dev *pdev)
1929{
1930 struct net_device *netdev = pci_get_drvdata(pdev);
1931 struct ixgbe_adapter *adapter = netdev_priv(netdev);
021230d4 1932 u32 err;
9a799d71
AK		 1933
1934 pci_set_power_state(pdev, PCI_D0);
1935 pci_restore_state(pdev);
1936 err = pci_enable_device(pdev);
1937 if (err) {
1938 printk(KERN_ERR "ixgbe: Cannot enable PCI device from " \
1939 "suspend\n");
1940 return err;
1941 }
1942 pci_set_master(pdev);
1943
1944 pci_enable_wake(pdev, PCI_D3hot, 0);
1945 pci_enable_wake(pdev, PCI_D3cold, 0);
1946
1947 if (netif_running(netdev)) {
021230d4 1948 err = ixgbe_request_irq(adapter);
9a799d71
AK		 1949 if (err)
1950 return err;
1951 }
1952
1953 ixgbe_reset(adapter);
1954
1955 if (netif_running(netdev))
1956 ixgbe_up(adapter);
1957
1958 netif_device_attach(netdev);
1959
1960 return 0;
1961}
1962#endif
1963
1964/**
1965 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
1966 * @adapter: board private structure
1967 * @rx_ring: ring to free buffers from
1968 **/
1969static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
1970 struct ixgbe_ring *rx_ring)
1971{
1972 struct pci_dev *pdev = adapter->pdev;
1973 unsigned long size;
1974 unsigned int i;
1975
1976 /* Free all the Rx ring sk_buffs */
1977
1978 for (i = 0; i < rx_ring->count; i++) {
1979 struct ixgbe_rx_buffer *rx_buffer_info;
1980
1981 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1982 if (rx_buffer_info->dma) {
1983 pci_unmap_single(pdev, rx_buffer_info->dma,
7c6e0a43 1984 rx_ring->rx_buf_len,
9a799d71
AK		 1985 PCI_DMA_FROMDEVICE);
1986 rx_buffer_info->dma = 0;
1987 }
1988 if (rx_buffer_info->skb) {
1989 dev_kfree_skb(rx_buffer_info->skb);
1990 rx_buffer_info->skb = NULL;
1991 }
1992 if (!rx_buffer_info->page)
1993 continue;
1994 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE,
1995 PCI_DMA_FROMDEVICE);
1996 rx_buffer_info->page_dma = 0;
1997
1998 put_page(rx_buffer_info->page);
1999 rx_buffer_info->page = NULL;
2000 }
2001
2002 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2003 memset(rx_ring->rx_buffer_info, 0, size);
2004
2005 /* Zero out the descriptor ring */
2006 memset(rx_ring->desc, 0, rx_ring->size);
2007
2008 rx_ring->next_to_clean = 0;
2009 rx_ring->next_to_use = 0;
2010
2011 writel(0, adapter->hw.hw_addr + rx_ring->head);
2012 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2013}
2014
2015/**
2016 * ixgbe_clean_tx_ring - Free Tx Buffers
2017 * @adapter: board private structure
2018 * @tx_ring: ring to be cleaned
2019 **/
2020static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2021 struct ixgbe_ring *tx_ring)
2022{
2023 struct ixgbe_tx_buffer *tx_buffer_info;
2024 unsigned long size;
2025 unsigned int i;
2026
2027 /* Free all the Tx ring sk_buffs */
2028
2029 for (i = 0; i < tx_ring->count; i++) {
2030 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2031 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2032 }
2033
2034 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2035 memset(tx_ring->tx_buffer_info, 0, size);
2036
2037 /* Zero out the descriptor ring */
2038 memset(tx_ring->desc, 0, tx_ring->size);
2039
2040 tx_ring->next_to_use = 0;
2041 tx_ring->next_to_clean = 0;
2042
2043 writel(0, adapter->hw.hw_addr + tx_ring->head);
2044 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2045}
2046
2047/**
021230d4 2048 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2049 * @adapter: board private structure
2050 **/
021230d4 2051static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2052{
2053 int i;
2054
021230d4
AV		 2055 for (i = 0; i < adapter->num_rx_queues; i++)
2056 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2057}
2058
2059/**
021230d4 2060 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2061 * @adapter: board private structure
2062 **/
021230d4 2063static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2064{
2065 int i;
2066
021230d4
AV		 2067 for (i = 0; i < adapter->num_tx_queues; i++)
2068 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2069}
2070
2071void ixgbe_down(struct ixgbe_adapter *adapter)
2072{
2073 struct net_device *netdev = adapter->netdev;
2074 u32 rxctrl;
2075
2076 /* signal that we are down to the interrupt handler */
2077 set_bit(__IXGBE_DOWN, &adapter->state);
2078
2079 /* disable receives */
2080 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
2081 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL,
2082 rxctrl & ~IXGBE_RXCTRL_RXEN);
2083
2084 netif_tx_disable(netdev);
2085
2086 /* disable transmits in the hardware */
2087
2088 /* flush both disables */
2089 IXGBE_WRITE_FLUSH(&adapter->hw);
2090 msleep(10);
2091
2092 ixgbe_irq_disable(adapter);
2093
021230d4 2094 ixgbe_napi_disable_all(adapter);
9a799d71
AK		 2095 del_timer_sync(&adapter->watchdog_timer);
2096
2097 netif_carrier_off(netdev);
fd2ea0a7 2098 netif_tx_stop_all_queues(netdev);
9a799d71 2099
96b0e0f6
JB		 2100#if defined(CONFIG_DCA) || defined (CONFIG_DCA_MODULE)
2101 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2102 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2103 dca_remove_requester(&adapter->pdev->dev);
2104 }
2105
2106#endif
6f4a0e45
PL		 2107 if (!pci_channel_offline(adapter->pdev))
2108 ixgbe_reset(adapter);
9a799d71
AK		 2109 ixgbe_clean_all_tx_rings(adapter);
2110 ixgbe_clean_all_rx_rings(adapter);
2111
96b0e0f6
JB		 2112#if defined(CONFIG_DCA) || defined (CONFIG_DCA_MODULE)
2113 /* since we reset the hardware DCA settings were cleared */
2114 if (dca_add_requester(&adapter->pdev->dev) == 0) {
2115 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2116 /* always use CB2 mode, difference is masked
2117 * in the CB driver */
2118 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
2119 ixgbe_setup_dca(adapter);
2120 }
2121#endif
9a799d71
AK		 2122}
2123
2124static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
2125{
2126 struct net_device *netdev = pci_get_drvdata(pdev);
2127 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2128#ifdef CONFIG_PM
2129 int retval = 0;
2130#endif
2131
2132 netif_device_detach(netdev);
2133
2134 if (netif_running(netdev)) {
2135 ixgbe_down(adapter);
2136 ixgbe_free_irq(adapter);
2137 }
2138
2139#ifdef CONFIG_PM
2140 retval = pci_save_state(pdev);
2141 if (retval)
2142 return retval;
2143#endif
2144
2145 pci_enable_wake(pdev, PCI_D3hot, 0);
2146 pci_enable_wake(pdev, PCI_D3cold, 0);
2147
5eba3699
AV		 2148 ixgbe_release_hw_control(adapter);
2149
9a799d71
AK		 2150 pci_disable_device(pdev);
2151
2152 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2153
2154 return 0;
2155}
2156
2157static void ixgbe_shutdown(struct pci_dev *pdev)
2158{
2159 ixgbe_suspend(pdev, PMSG_SUSPEND);
2160}
2161
2162/**
021230d4
AV		 2163 * ixgbe_poll - NAPI Rx polling callback
2164 * @napi: structure for representing this polling device
2165 * @budget: how many packets driver is allowed to clean
2166 *
2167 * This function is used for legacy and MSI, NAPI mode
9a799d71 2168 **/
021230d4 2169static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2170{
021230d4
AV		 2171 struct ixgbe_q_vector *q_vector = container_of(napi,
2172 struct ixgbe_q_vector, napi);
2173 struct ixgbe_adapter *adapter = q_vector->adapter;
d2c7ddd6 2174 int tx_cleaned = 0, work_done = 0;
9a799d71 2175
96b0e0f6 2176#if defined(CONFIG_DCA) || defined (CONFIG_DCA_MODULE)
bd0362dd
JC		 2177 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2178 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2179 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2180 }
2181#endif
2182
d2c7ddd6 2183 tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
021230d4 2184 ixgbe_clean_rx_irq(adapter, adapter->rx_ring, &work_done, budget);
9a799d71 2185
d2c7ddd6
DM		 2186 if (tx_cleaned)
2187 work_done = budget;
2188
53e52c72
DM		 2189 /* If budget not fully consumed, exit the polling mode */
2190 if (work_done < budget) {
021230d4 2191 netif_rx_complete(adapter->netdev, napi);
f494e8fa
AV		 2192 if (adapter->rx_eitr < IXGBE_MIN_ITR_USECS)
2193 ixgbe_set_itr(adapter);
d4f80882
AV		 2194 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2195 ixgbe_irq_enable(adapter);
9a799d71
AK		 2196 }
2197
2198 return work_done;
2199}
2200
2201/**
2202 * ixgbe_tx_timeout - Respond to a Tx Hang
2203 * @netdev: network interface device structure
2204 **/
2205static void ixgbe_tx_timeout(struct net_device *netdev)
2206{
2207 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2208
2209 /* Do the reset outside of interrupt context */
2210 schedule_work(&adapter->reset_task);
2211}
2212
2213static void ixgbe_reset_task(struct work_struct *work)
2214{
2215 struct ixgbe_adapter *adapter;
2216 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2217
2218 adapter->tx_timeout_count++;
2219
d4f80882 2220 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2221}
2222
021230d4
AV		 2223static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
2224 int vectors)
2225{
2226 int err, vector_threshold;
2227
2228 /* We'll want at least 3 (vector_threshold):
2229 * 1) TxQ[0] Cleanup
2230 * 2) RxQ[0] Cleanup
2231 * 3) Other (Link Status Change, etc.)
2232 * 4) TCP Timer (optional)
2233 */
2234 vector_threshold = MIN_MSIX_COUNT;
2235
2236 /* The more we get, the more we will assign to Tx/Rx Cleanup
2237 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2238 * Right now, we simply care about how many we'll get; we'll
2239 * set them up later while requesting irq's.
2240 */
2241 while (vectors >= vector_threshold) {
2242 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
2243 vectors);
2244 if (!err) /* Success in acquiring all requested vectors. */
2245 break;
2246 else if (err < 0)
2247 vectors = 0; /* Nasty failure, quit now */
2248 else /* err == number of vectors we should try again with */
2249 vectors = err;
2250 }
2251
2252 if (vectors < vector_threshold) {
2253 /* Can't allocate enough MSI-X interrupts? Oh well.
2254 * This just means we'll go with either a single MSI
2255 * vector or fall back to legacy interrupts.
2256 */
2257 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2258 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2259 kfree(adapter->msix_entries);
2260 adapter->msix_entries = NULL;
2261 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2262 adapter->num_tx_queues = 1;
2263 adapter->num_rx_queues = 1;
2264 } else {
2265 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
2266 adapter->num_msix_vectors = vectors;
2267 }
2268}
2269
2270static void __devinit ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2271{
2272 int nrq, ntq;
2273 int feature_mask = 0, rss_i, rss_m;
2274
2275 /* Number of supported queues */
2276 switch (adapter->hw.mac.type) {
2277 case ixgbe_mac_82598EB:
2278 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2279 rss_m = 0;
2280 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2281
2282 switch (adapter->flags & feature_mask) {
2283 case (IXGBE_FLAG_RSS_ENABLED):
2284 rss_m = 0xF;
2285 nrq = rss_i;
30eba97a 2286 ntq = rss_i;
021230d4
AV		 2287 break;
2288 case 0:
2289 default:
2290 rss_i = 0;
2291 rss_m = 0;
2292 nrq = 1;
2293 ntq = 1;
2294 break;
2295 }
2296
2297 adapter->ring_feature[RING_F_RSS].indices = rss_i;
2298 adapter->ring_feature[RING_F_RSS].mask = rss_m;
2299 break;
2300 default:
2301 nrq = 1;
2302 ntq = 1;
2303 break;
2304 }
2305
2306 adapter->num_rx_queues = nrq;
2307 adapter->num_tx_queues = ntq;
2308}
2309
2310/**
2311 * ixgbe_cache_ring_register - Descriptor ring to register mapping
2312 * @adapter: board private structure to initialize
2313 *
2314 * Once we know the feature-set enabled for the device, we'll cache
2315 * the register offset the descriptor ring is assigned to.
2316 **/
2317static void __devinit ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2318{
2319 /* TODO: Remove all uses of the indices in the cases where multiple
2320 * features are OR'd together, if the feature set makes sense.
2321 */
2322 int feature_mask = 0, rss_i;
2323 int i, txr_idx, rxr_idx;
2324
2325 /* Number of supported queues */
2326 switch (adapter->hw.mac.type) {
2327 case ixgbe_mac_82598EB:
2328 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2329 txr_idx = 0;
2330 rxr_idx = 0;
2331 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2332 switch (adapter->flags & feature_mask) {
2333 case (IXGBE_FLAG_RSS_ENABLED):
2334 for (i = 0; i < adapter->num_rx_queues; i++)
2335 adapter->rx_ring[i].reg_idx = i;
2336 for (i = 0; i < adapter->num_tx_queues; i++)
2337 adapter->tx_ring[i].reg_idx = i;
2338 break;
2339 case 0:
2340 default:
2341 break;
2342 }
2343 break;
2344 default:
2345 break;
2346 }
2347}
2348
9a799d71
AK		 2349/**
2350 * ixgbe_alloc_queues - Allocate memory for all rings
2351 * @adapter: board private structure to initialize
2352 *
2353 * We allocate one ring per queue at run-time since we don't know the
2354 * number of queues at compile-time. The polling_netdev array is
2355 * intended for Multiqueue, but should work fine with a single queue.
2356 **/
2357static int __devinit ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
2358{
2359 int i;
2360
2361 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
2362 sizeof(struct ixgbe_ring), GFP_KERNEL);
2363 if (!adapter->tx_ring)
021230d4 2364 goto err_tx_ring_allocation;
9a799d71
AK		 2365
2366 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
2367 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 2368 if (!adapter->rx_ring)
2369 goto err_rx_ring_allocation;
9a799d71 2370
021230d4
AV		 2371 for (i = 0; i < adapter->num_tx_queues; i++) {
2372 adapter->tx_ring[i].count = IXGBE_DEFAULT_TXD;
2373 adapter->tx_ring[i].queue_index = i;
2374 }
9a799d71 2375 for (i = 0; i < adapter->num_rx_queues; i++) {
9a799d71 2376 adapter->rx_ring[i].count = IXGBE_DEFAULT_RXD;
021230d4
AV		 2377 adapter->rx_ring[i].queue_index = i;
2378 }
2379
2380 ixgbe_cache_ring_register(adapter);
2381
2382 return 0;
2383
2384err_rx_ring_allocation:
2385 kfree(adapter->tx_ring);
2386err_tx_ring_allocation:
2387 return -ENOMEM;
2388}
2389
2390/**
2391 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2392 * @adapter: board private structure to initialize
2393 *
2394 * Attempt to configure the interrupts using the best available
2395 * capabilities of the hardware and the kernel.
2396 **/
2397static int __devinit ixgbe_set_interrupt_capability(struct ixgbe_adapter
2398 *adapter)
2399{
2400 int err = 0;
2401 int vector, v_budget;
2402
2403 /*
2404 * It's easy to be greedy for MSI-X vectors, but it really
2405 * doesn't do us much good if we have a lot more vectors
2406 * than CPU's. So let's be conservative and only ask for
2407 * (roughly) twice the number of vectors as there are CPU's.
2408 */
2409 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
2410 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
2411
2412 /*
2413 * At the same time, hardware can only support a maximum of
2414 * MAX_MSIX_COUNT vectors. With features such as RSS and VMDq,
2415 * we can easily reach upwards of 64 Rx descriptor queues and
2416 * 32 Tx queues. Thus, we cap it off in those rare cases where
2417 * the cpu count also exceeds our vector limit.
2418 */
2419 v_budget = min(v_budget, MAX_MSIX_COUNT);
2420
2421 /* A failure in MSI-X entry allocation isn't fatal, but it does
2422 * mean we disable MSI-X capabilities of the adapter. */
2423 adapter->msix_entries = kcalloc(v_budget,
2424 sizeof(struct msix_entry), GFP_KERNEL);
2425 if (!adapter->msix_entries) {
2426 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2427 ixgbe_set_num_queues(adapter);
2428 kfree(adapter->tx_ring);
2429 kfree(adapter->rx_ring);
2430 err = ixgbe_alloc_queues(adapter);
2431 if (err) {
2432 DPRINTK(PROBE, ERR, "Unable to allocate memory "
2433 "for queues\n");
2434 goto out;
2435 }
2436
2437 goto try_msi;
2438 }
2439
2440 for (vector = 0; vector < v_budget; vector++)
2441 adapter->msix_entries[vector].entry = vector;
2442
2443 ixgbe_acquire_msix_vectors(adapter, v_budget);
2444
2445 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2446 goto out;
2447
2448try_msi:
2449 err = pci_enable_msi(adapter->pdev);
2450 if (!err) {
2451 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
2452 } else {
2453 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
2454 "falling back to legacy. Error: %d\n", err);
2455 /* reset err */
2456 err = 0;
2457 }
2458
2459out:
30eba97a 2460 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 2461 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
021230d4
AV		 2462
2463 return err;
2464}
2465
2466static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
2467{
2468 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2469 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2470 pci_disable_msix(adapter->pdev);
2471 kfree(adapter->msix_entries);
2472 adapter->msix_entries = NULL;
2473 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2474 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
2475 pci_disable_msi(adapter->pdev);
2476 }
2477 return;
2478}
2479
2480/**
2481 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
2482 * @adapter: board private structure to initialize
2483 *
2484 * We determine which interrupt scheme to use based on...
2485 * - Kernel support (MSI, MSI-X)
2486 * - which can be user-defined (via MODULE_PARAM)
2487 * - Hardware queue count (num_*_queues)
2488 * - defined by miscellaneous hardware support/features (RSS, etc.)
2489 **/
2490static int __devinit ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
2491{
2492 int err;
2493
2494 /* Number of supported queues */
2495 ixgbe_set_num_queues(adapter);
2496
2497 err = ixgbe_alloc_queues(adapter);
2498 if (err) {
2499 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
2500 goto err_alloc_queues;
2501 }
2502
2503 err = ixgbe_set_interrupt_capability(adapter);
2504 if (err) {
2505 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
2506 goto err_set_interrupt;
9a799d71
AK		 2507 }
2508
021230d4
AV		 2509 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
2510 "Tx Queue count = %u\n",
2511 (adapter->num_rx_queues > 1) ? "Enabled" :
2512 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
2513
2514 set_bit(__IXGBE_DOWN, &adapter->state);
2515
9a799d71 2516 return 0;
021230d4
AV		 2517
2518err_set_interrupt:
2519 kfree(adapter->tx_ring);
2520 kfree(adapter->rx_ring);
2521err_alloc_queues:
2522 return err;
9a799d71
AK		 2523}
2524
2525/**
2526 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
2527 * @adapter: board private structure to initialize
2528 *
2529 * ixgbe_sw_init initializes the Adapter private data structure.
2530 * Fields are initialized based on PCI device information and
2531 * OS network device settings (MTU size).
2532 **/
2533static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
2534{
2535 struct ixgbe_hw *hw = &adapter->hw;
2536 struct pci_dev *pdev = adapter->pdev;
021230d4
AV		 2537 unsigned int rss;
2538
2539 /* Set capability flags */
2540 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
2541 adapter->ring_feature[RING_F_RSS].indices = rss;
2542 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
9a799d71 2543
f494e8fa
AV		 2544 /* Enable Dynamic interrupt throttling by default */
2545 adapter->rx_eitr = 1;
2546 adapter->tx_eitr = 1;
2547
9a799d71 2548 /* default flow control settings */
2b9ade93
JB		 2549 hw->fc.original_type = ixgbe_fc_none;
2550 hw->fc.type = ixgbe_fc_none;
2551 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
2552 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
2553 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
2554 hw->fc.send_xon = true;
9a799d71 2555
021230d4 2556 /* select 10G link by default */
9a799d71
AK		 2557 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
2558 if (hw->mac.ops.reset(hw)) {
2559 dev_err(&pdev->dev, "HW Init failed\n");
2560 return -EIO;
2561 }
3957d63d
AK		 2562 if (hw->mac.ops.setup_link_speed(hw, IXGBE_LINK_SPEED_10GB_FULL, true,
2563 false)) {
9a799d71
AK		 2564 dev_err(&pdev->dev, "Link Speed setup failed\n");
2565 return -EIO;
2566 }
2567
2568 /* initialize eeprom parameters */
2569 if (ixgbe_init_eeprom(hw)) {
2570 dev_err(&pdev->dev, "EEPROM initialization failed\n");
2571 return -EIO;
2572 }
2573
021230d4 2574 /* enable rx csum by default */
9a799d71
AK		 2575 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
2576
9a799d71
AK		 2577 set_bit(__IXGBE_DOWN, &adapter->state);
2578
2579 return 0;
2580}
2581
2582/**
2583 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
2584 * @adapter: board private structure
3a581073 2585 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 2586 *
2587 * Return 0 on success, negative on failure
2588 **/
2589int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 2590 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2591{
2592 struct pci_dev *pdev = adapter->pdev;
2593 int size;
2594
3a581073
JB		 2595 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2596 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 2597 if (!tx_ring->tx_buffer_info)
2598 goto err;
3a581073 2599 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 2600
2601 /* round up to nearest 4K */
e01c31a5
JB		 2602 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc) +
2603 sizeof(u32);
3a581073 2604 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 2605
3a581073
JB		 2606 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
2607 &tx_ring->dma);
e01c31a5
JB		 2608 if (!tx_ring->desc)
2609 goto err;
9a799d71 2610
3a581073
JB		 2611 tx_ring->next_to_use = 0;
2612 tx_ring->next_to_clean = 0;
2613 tx_ring->work_limit = tx_ring->count;
9a799d71 2614 return 0;
e01c31a5
JB		 2615
2616err:
2617 vfree(tx_ring->tx_buffer_info);
2618 tx_ring->tx_buffer_info = NULL;
2619 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
2620 "descriptor ring\n");
2621 return -ENOMEM;
9a799d71
AK		 2622}
2623
2624/**
2625 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
2626 * @adapter: board private structure
3a581073 2627 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 2628 *
2629 * Returns 0 on success, negative on failure
2630 **/
2631int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
3a581073 2632 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2633{
2634 struct pci_dev *pdev = adapter->pdev;
021230d4 2635 int size;
9a799d71 2636
177db6ff 2637 size = sizeof(struct net_lro_desc) * IXGBE_MAX_LRO_DESCRIPTORS;
3a581073
JB		 2638 rx_ring->lro_mgr.lro_arr = vmalloc(size);
2639 if (!rx_ring->lro_mgr.lro_arr)
177db6ff 2640 return -ENOMEM;
3a581073 2641 memset(rx_ring->lro_mgr.lro_arr, 0, size);
177db6ff 2642
3a581073
JB		 2643 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2644 rx_ring->rx_buffer_info = vmalloc(size);
2645 if (!rx_ring->rx_buffer_info) {
9a799d71
AK		 2646 DPRINTK(PROBE, ERR,
2647 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 2648 goto alloc_failed;
9a799d71 2649 }
3a581073 2650 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 2651
9a799d71 2652 /* Round up to nearest 4K */
3a581073
JB		 2653 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
2654 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 2655
3a581073 2656 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 2657
3a581073 2658 if (!rx_ring->desc) {
9a799d71
AK		 2659 DPRINTK(PROBE, ERR,
2660 "Memory allocation failed for the rx desc ring\n");
3a581073 2661 vfree(rx_ring->rx_buffer_info);
177db6ff 2662 goto alloc_failed;
9a799d71
AK		 2663 }
2664
3a581073
JB		 2665 rx_ring->next_to_clean = 0;
2666 rx_ring->next_to_use = 0;
9a799d71
AK		 2667
2668 return 0;
177db6ff
MC		 2669
2670alloc_failed:
3a581073
JB		 2671 vfree(rx_ring->lro_mgr.lro_arr);
2672 rx_ring->lro_mgr.lro_arr = NULL;
177db6ff 2673 return -ENOMEM;
9a799d71
AK		 2674}
2675
2676/**
2677 * ixgbe_free_tx_resources - Free Tx Resources per Queue
2678 * @adapter: board private structure
2679 * @tx_ring: Tx descriptor ring for a specific queue
2680 *
2681 * Free all transmit software resources
2682 **/
2683static void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 2684 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2685{
2686 struct pci_dev *pdev = adapter->pdev;
2687
2688 ixgbe_clean_tx_ring(adapter, tx_ring);
2689
2690 vfree(tx_ring->tx_buffer_info);
2691 tx_ring->tx_buffer_info = NULL;
2692
2693 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2694
2695 tx_ring->desc = NULL;
2696}
2697
2698/**
2699 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
2700 * @adapter: board private structure
2701 *
2702 * Free all transmit software resources
2703 **/
2704static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
2705{
2706 int i;
2707
2708 for (i = 0; i < adapter->num_tx_queues; i++)
2709 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
2710}
2711
2712/**
2713 * ixgbe_free_rx_resources - Free Rx Resources
2714 * @adapter: board private structure
2715 * @rx_ring: ring to clean the resources from
2716 *
2717 * Free all receive software resources
2718 **/
2719static void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
2720 struct ixgbe_ring *rx_ring)
2721{
2722 struct pci_dev *pdev = adapter->pdev;
2723
177db6ff
MC		 2724 vfree(rx_ring->lro_mgr.lro_arr);
2725 rx_ring->lro_mgr.lro_arr = NULL;
2726
9a799d71
AK		 2727 ixgbe_clean_rx_ring(adapter, rx_ring);
2728
2729 vfree(rx_ring->rx_buffer_info);
2730 rx_ring->rx_buffer_info = NULL;
2731
2732 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2733
2734 rx_ring->desc = NULL;
2735}
2736
2737/**
2738 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
2739 * @adapter: board private structure
2740 *
2741 * Free all receive software resources
2742 **/
2743static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
2744{
2745 int i;
2746
2747 for (i = 0; i < adapter->num_rx_queues; i++)
2748 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
2749}
2750
2751/**
021230d4 2752 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
9a799d71
AK		 2753 * @adapter: board private structure
2754 *
2755 * If this function returns with an error, then it's possible one or
2756 * more of the rings is populated (while the rest are not). It is the
2757 * callers duty to clean those orphaned rings.
2758 *
2759 * Return 0 on success, negative on failure
2760 **/
2761static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
2762{
2763 int i, err = 0;
2764
2765 for (i = 0; i < adapter->num_tx_queues; i++) {
2766 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
2767 if (err) {
2768 DPRINTK(PROBE, ERR,
2769 "Allocation for Tx Queue %u failed\n", i);
2770 break;
2771 }
2772 }
2773
2774 return err;
2775}
2776
2777/**
021230d4 2778 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
9a799d71
AK		 2779 * @adapter: board private structure
2780 *
2781 * If this function returns with an error, then it's possible one or
2782 * more of the rings is populated (while the rest are not). It is the
2783 * callers duty to clean those orphaned rings.
2784 *
2785 * Return 0 on success, negative on failure
2786 **/
2787
2788static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
2789{
2790 int i, err = 0;
2791
2792 for (i = 0; i < adapter->num_rx_queues; i++) {
2793 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2794 if (err) {
2795 DPRINTK(PROBE, ERR,
2796 "Allocation for Rx Queue %u failed\n", i);
2797 break;
2798 }
2799 }
2800
2801 return err;
2802}
2803
2804/**
2805 * ixgbe_change_mtu - Change the Maximum Transfer Unit
2806 * @netdev: network interface device structure
2807 * @new_mtu: new value for maximum frame size
2808 *
2809 * Returns 0 on success, negative on failure
2810 **/
2811static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
2812{
2813 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2814 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2815
2816 if ((max_frame < (ETH_ZLEN + ETH_FCS_LEN)) ||
2817 (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
2818 return -EINVAL;
2819
021230d4
AV		 2820 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
2821 netdev->mtu, new_mtu);
2822 /* must set new MTU before calling down or up */
9a799d71
AK		 2823 netdev->mtu = new_mtu;
2824
d4f80882
AV		 2825 if (netif_running(netdev))
2826 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2827
2828 return 0;
2829}
2830
2831/**
2832 * ixgbe_open - Called when a network interface is made active
2833 * @netdev: network interface device structure
2834 *
2835 * Returns 0 on success, negative value on failure
2836 *
2837 * The open entry point is called when a network interface is made
2838 * active by the system (IFF_UP). At this point all resources needed
2839 * for transmit and receive operations are allocated, the interrupt
2840 * handler is registered with the OS, the watchdog timer is started,
2841 * and the stack is notified that the interface is ready.
2842 **/
2843static int ixgbe_open(struct net_device *netdev)
2844{
2845 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2846 int err;
4bebfaa5
AK		 2847
2848 /* disallow open during test */
2849 if (test_bit(__IXGBE_TESTING, &adapter->state))
2850 return -EBUSY;
9a799d71 2851
9a799d71
AK		 2852 /* allocate transmit descriptors */
2853 err = ixgbe_setup_all_tx_resources(adapter);
2854 if (err)
2855 goto err_setup_tx;
2856
9a799d71
AK		 2857 /* allocate receive descriptors */
2858 err = ixgbe_setup_all_rx_resources(adapter);
2859 if (err)
2860 goto err_setup_rx;
2861
2862 ixgbe_configure(adapter);
2863
021230d4 2864 err = ixgbe_request_irq(adapter);
9a799d71
AK		 2865 if (err)
2866 goto err_req_irq;
2867
9a799d71
AK		 2868 err = ixgbe_up_complete(adapter);
2869 if (err)
2870 goto err_up;
2871
d55b53ff
JK		 2872 netif_tx_start_all_queues(netdev);
2873
9a799d71
AK		 2874 return 0;
2875
2876err_up:
5eba3699 2877 ixgbe_release_hw_control(adapter);
9a799d71
AK		 2878 ixgbe_free_irq(adapter);
2879err_req_irq:
2880 ixgbe_free_all_rx_resources(adapter);
2881err_setup_rx:
2882 ixgbe_free_all_tx_resources(adapter);
2883err_setup_tx:
2884 ixgbe_reset(adapter);
2885
2886 return err;
2887}
2888
2889/**
2890 * ixgbe_close - Disables a network interface
2891 * @netdev: network interface device structure
2892 *
2893 * Returns 0, this is not allowed to fail
2894 *
2895 * The close entry point is called when an interface is de-activated
2896 * by the OS. The hardware is still under the drivers control, but
2897 * needs to be disabled. A global MAC reset is issued to stop the
2898 * hardware, and all transmit and receive resources are freed.
2899 **/
2900static int ixgbe_close(struct net_device *netdev)
2901{
2902 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 2903
2904 ixgbe_down(adapter);
2905 ixgbe_free_irq(adapter);
2906
2907 ixgbe_free_all_tx_resources(adapter);
2908 ixgbe_free_all_rx_resources(adapter);
2909
5eba3699 2910 ixgbe_release_hw_control(adapter);
9a799d71
AK		 2911
2912 return 0;
2913}
2914
2915/**
2916 * ixgbe_update_stats - Update the board statistics counters.
2917 * @adapter: board private structure
2918 **/
2919void ixgbe_update_stats(struct ixgbe_adapter *adapter)
2920{
2921 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 2922 u64 total_mpc = 0;
2923 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71
AK		 2924
2925 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 2926 for (i = 0; i < 8; i++) {
2927 /* for packet buffers not used, the register should read 0 */
2928 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2929 missed_rx += mpc;
2930 adapter->stats.mpc[i] += mpc;
2931 total_mpc += adapter->stats.mpc[i];
2932 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2933 }
2934 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2935 /* work around hardware counting issue */
2936 adapter->stats.gprc -= missed_rx;
2937
2938 /* 82598 hardware only has a 32 bit counter in the high register */
9a799d71 2939 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6f11eef7
AV		 2940 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2941 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
9a799d71
AK		 2942 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2943 adapter->stats.bprc += bprc;
2944 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2945 adapter->stats.mprc -= bprc;
2946 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2947 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2948 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2949 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2950 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2951 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2952 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71
AK		 2953 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2954 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
9a799d71 2955 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6f11eef7
AV		 2956 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2957 adapter->stats.lxontxc += lxon;
2958 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2959 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 2960 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2961 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 2962 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2963 /*
2964 * 82598 errata - tx of flow control packets is included in tx counters
2965 */
2966 xon_off_tot = lxon + lxoff;
2967 adapter->stats.gptc -= xon_off_tot;
2968 adapter->stats.mptc -= xon_off_tot;
2969 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 2970 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2971 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2972 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 2973 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2974 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 2975 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 2976 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2977 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2978 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2979 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2980 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 2981 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2982
2983 /* Fill out the OS statistics structure */
9a799d71
AK		 2984 adapter->net_stats.multicast = adapter->stats.mprc;
2985
2986 /* Rx Errors */
2987 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
2988 adapter->stats.rlec;
2989 adapter->net_stats.rx_dropped = 0;
2990 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
2991 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 2992 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 2993}
2994
2995/**
2996 * ixgbe_watchdog - Timer Call-back
2997 * @data: pointer to adapter cast into an unsigned long
2998 **/
2999static void ixgbe_watchdog(unsigned long data)
3000{
3001 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3002 struct net_device *netdev = adapter->netdev;
3003 bool link_up;
3004 u32 link_speed = 0;
3005
3957d63d 3006 adapter->hw.mac.ops.check_link(&adapter->hw, &(link_speed), &link_up);
9a799d71
AK		 3007
3008 if (link_up) {
3009 if (!netif_carrier_ok(netdev)) {
3010 u32 frctl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
3011 u32 rmcs = IXGBE_READ_REG(&adapter->hw, IXGBE_RMCS);
3012#define FLOW_RX (frctl & IXGBE_FCTRL_RFCE)
3013#define FLOW_TX (rmcs & IXGBE_RMCS_TFCE_802_3X)
3014 DPRINTK(LINK, INFO, "NIC Link is Up %s, "
3015 "Flow Control: %s\n",
3016 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
3017 "10 Gbps" :
3018 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5a059e9d 3019 "1 Gbps" : "unknown speed")),
9a799d71
AK		 3020 ((FLOW_RX && FLOW_TX) ? "RX/TX" :
3021 (FLOW_RX ? "RX" :
3022 (FLOW_TX ? "TX" : "None"))));
3023
3024 netif_carrier_on(netdev);
fd2ea0a7 3025 netif_tx_wake_all_queues(netdev);
9a799d71
AK		 3026 } else {
3027 /* Force detection of hung controller */
3028 adapter->detect_tx_hung = true;
3029 }
3030 } else {
3031 if (netif_carrier_ok(netdev)) {
3032 DPRINTK(LINK, INFO, "NIC Link is Down\n");
3033 netif_carrier_off(netdev);
fd2ea0a7 3034 netif_tx_stop_all_queues(netdev);
9a799d71
AK		 3035 }
3036 }
3037
3038 ixgbe_update_stats(adapter);
3039
021230d4
AV		 3040 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
3041 /* Cause software interrupt to ensure rx rings are cleaned */
3042 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3043 u32 eics =
3044 (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1;
3045 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, eics);
3046 } else {
3047 /* for legacy and MSI interrupts don't set any bits that
3048 * are enabled for EIAM, because this operation would
3049 * set *both* EIMS and EICS for any bit in EIAM */
3050 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
3051 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3052 }
3053 /* Reset the timer */
9a799d71
AK		 3054 mod_timer(&adapter->watchdog_timer,
3055 round_jiffies(jiffies + 2 * HZ));
021230d4 3056 }
9a799d71
AK		 3057}
3058
9a799d71
AK		 3059static int ixgbe_tso(struct ixgbe_adapter *adapter,
3060 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
3061 u32 tx_flags, u8 *hdr_len)
3062{
3063 struct ixgbe_adv_tx_context_desc *context_desc;
3064 unsigned int i;
3065 int err;
3066 struct ixgbe_tx_buffer *tx_buffer_info;
3067 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
3068 u32 mss_l4len_idx = 0, l4len;
9a799d71
AK		 3069
3070 if (skb_is_gso(skb)) {
3071 if (skb_header_cloned(skb)) {
3072 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3073 if (err)
3074 return err;
3075 }
3076 l4len = tcp_hdrlen(skb);
3077 *hdr_len += l4len;
3078
8327d000 3079 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 3080 struct iphdr *iph = ip_hdr(skb);
3081 iph->tot_len = 0;
3082 iph->check = 0;
3083 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3084 iph->daddr, 0,
3085 IPPROTO_TCP,
3086 0);
3087 adapter->hw_tso_ctxt++;
3088 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3089 ipv6_hdr(skb)->payload_len = 0;
3090 tcp_hdr(skb)->check =
3091 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3092 &ipv6_hdr(skb)->daddr,
3093 0, IPPROTO_TCP, 0);
3094 adapter->hw_tso6_ctxt++;
3095 }
3096
3097 i = tx_ring->next_to_use;
3098
3099 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3100 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3101
3102 /* VLAN MACLEN IPLEN */
3103 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3104 vlan_macip_lens |=
3105 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3106 vlan_macip_lens |= ((skb_network_offset(skb)) <<
3107 IXGBE_ADVTXD_MACLEN_SHIFT);
3108 *hdr_len += skb_network_offset(skb);
3109 vlan_macip_lens |=
3110 (skb_transport_header(skb) - skb_network_header(skb));
3111 *hdr_len +=
3112 (skb_transport_header(skb) - skb_network_header(skb));
3113 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3114 context_desc->seqnum_seed = 0;
3115
3116 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3117 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
3118 IXGBE_ADVTXD_DTYP_CTXT);
3119
8327d000 3120 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 3121 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3122 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
3123 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3124
3125 /* MSS L4LEN IDX */
3126 mss_l4len_idx |=
3127 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
3128 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
3129 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3130
3131 tx_buffer_info->time_stamp = jiffies;
3132 tx_buffer_info->next_to_watch = i;
3133
3134 i++;
3135 if (i == tx_ring->count)
3136 i = 0;
3137 tx_ring->next_to_use = i;
3138
3139 return true;
3140 }
3141 return false;
3142}
3143
3144static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
3145 struct ixgbe_ring *tx_ring,
3146 struct sk_buff *skb, u32 tx_flags)
3147{
3148 struct ixgbe_adv_tx_context_desc *context_desc;
3149 unsigned int i;
3150 struct ixgbe_tx_buffer *tx_buffer_info;
3151 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
3152
3153 if (skb->ip_summed == CHECKSUM_PARTIAL ||
3154 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
3155 i = tx_ring->next_to_use;
3156 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3157 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3158
3159 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3160 vlan_macip_lens |=
3161 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3162 vlan_macip_lens |= (skb_network_offset(skb) <<
3163 IXGBE_ADVTXD_MACLEN_SHIFT);
3164 if (skb->ip_summed == CHECKSUM_PARTIAL)
3165 vlan_macip_lens |= (skb_transport_header(skb) -
3166 skb_network_header(skb));
3167
3168 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3169 context_desc->seqnum_seed = 0;
3170
3171 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
3172 IXGBE_ADVTXD_DTYP_CTXT);
3173
3174 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71
AK		 3175 switch (skb->protocol) {
3176 case __constant_htons(ETH_P_IP):
9a799d71 3177 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 3178 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3179 type_tucmd_mlhl |=
3180 IXGBE_ADVTXD_TUCMD_L4T_TCP;
3181 break;
3182
3183 case __constant_htons(ETH_P_IPV6):
3184 /* XXX what about other V6 headers?? */
3185 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3186 type_tucmd_mlhl |=
3187 IXGBE_ADVTXD_TUCMD_L4T_TCP;
3188 break;
9a799d71 3189
41825d71
AK		 3190 default:
3191 if (unlikely(net_ratelimit())) {
3192 DPRINTK(PROBE, WARNING,
3193 "partial checksum but proto=%x!\n",
3194 skb->protocol);
3195 }
3196 break;
3197 }
9a799d71
AK		 3198 }
3199
3200 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3201 context_desc->mss_l4len_idx = 0;
3202
3203 tx_buffer_info->time_stamp = jiffies;
3204 tx_buffer_info->next_to_watch = i;
3205 adapter->hw_csum_tx_good++;
3206 i++;
3207 if (i == tx_ring->count)
3208 i = 0;
3209 tx_ring->next_to_use = i;
3210
3211 return true;
3212 }
3213 return false;
3214}
3215
3216static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
3217 struct ixgbe_ring *tx_ring,
3218 struct sk_buff *skb, unsigned int first)
3219{
3220 struct ixgbe_tx_buffer *tx_buffer_info;
3221 unsigned int len = skb->len;
3222 unsigned int offset = 0, size, count = 0, i;
3223 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3224 unsigned int f;
3225
3226 len -= skb->data_len;
3227
3228 i = tx_ring->next_to_use;
3229
3230 while (len) {
3231 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3232 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3233
3234 tx_buffer_info->length = size;
3235 tx_buffer_info->dma = pci_map_single(adapter->pdev,
3236 skb->data + offset,
3237 size, PCI_DMA_TODEVICE);
3238 tx_buffer_info->time_stamp = jiffies;
3239 tx_buffer_info->next_to_watch = i;
3240
3241 len -= size;
3242 offset += size;
3243 count++;
3244 i++;
3245 if (i == tx_ring->count)
3246 i = 0;
3247 }
3248
3249 for (f = 0; f < nr_frags; f++) {
3250 struct skb_frag_struct *frag;
3251
3252 frag = &skb_shinfo(skb)->frags[f];
3253 len = frag->size;
3254 offset = frag->page_offset;
3255
3256 while (len) {
3257 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3258 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3259
3260 tx_buffer_info->length = size;
3261 tx_buffer_info->dma = pci_map_page(adapter->pdev,
3262 frag->page,
3263 offset,
3264 size, PCI_DMA_TODEVICE);
3265 tx_buffer_info->time_stamp = jiffies;
3266 tx_buffer_info->next_to_watch = i;
3267
3268 len -= size;
3269 offset += size;
3270 count++;
3271 i++;
3272 if (i == tx_ring->count)
3273 i = 0;
3274 }
3275 }
3276 if (i == 0)
3277 i = tx_ring->count - 1;
3278 else
3279 i = i - 1;
3280 tx_ring->tx_buffer_info[i].skb = skb;
3281 tx_ring->tx_buffer_info[first].next_to_watch = i;
3282
3283 return count;
3284}
3285
3286static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
3287 struct ixgbe_ring *tx_ring,
3288 int tx_flags, int count, u32 paylen, u8 hdr_len)
3289{
3290 union ixgbe_adv_tx_desc *tx_desc = NULL;
3291 struct ixgbe_tx_buffer *tx_buffer_info;
3292 u32 olinfo_status = 0, cmd_type_len = 0;
3293 unsigned int i;
3294 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
3295
3296 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
3297
3298 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
3299
3300 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3301 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
3302
3303 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
3304 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
3305
3306 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3307 IXGBE_ADVTXD_POPTS_SHIFT;
3308
3309 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
3310 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
3311 IXGBE_ADVTXD_POPTS_SHIFT;
3312
3313 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
3314 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3315 IXGBE_ADVTXD_POPTS_SHIFT;
3316
3317 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
3318
3319 i = tx_ring->next_to_use;
3320 while (count--) {
3321 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3322 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
3323 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
3324 tx_desc->read.cmd_type_len =
3325 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
3326 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3327
3328 i++;
3329 if (i == tx_ring->count)
3330 i = 0;
3331 }
3332
3333 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
3334
3335 /*
3336 * Force memory writes to complete before letting h/w
3337 * know there are new descriptors to fetch. (Only
3338 * applicable for weak-ordered memory model archs,
3339 * such as IA-64).
3340 */
3341 wmb();
3342
3343 tx_ring->next_to_use = i;
3344 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3345}
3346
e092be60
AV		 3347static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
3348 struct ixgbe_ring *tx_ring, int size)
3349{
3350 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3351
30eba97a 3352 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 3353 /* Herbert's original patch had:
3354 * smp_mb__after_netif_stop_queue();
3355 * but since that doesn't exist yet, just open code it. */
3356 smp_mb();
3357
3358 /* We need to check again in a case another CPU has just
3359 * made room available. */
3360 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
3361 return -EBUSY;
3362
3363 /* A reprieve! - use start_queue because it doesn't call schedule */
30eba97a 3364 netif_wake_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 3365 ++adapter->restart_queue;
3366 return 0;
3367}
3368
3369static int ixgbe_maybe_stop_tx(struct net_device *netdev,
3370 struct ixgbe_ring *tx_ring, int size)
3371{
3372 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
3373 return 0;
3374 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
3375}
3376
3377
9a799d71
AK		 3378static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3379{
3380 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3381 struct ixgbe_ring *tx_ring;
3382 unsigned int len = skb->len;
3383 unsigned int first;
3384 unsigned int tx_flags = 0;
30eba97a
AV		 3385 u8 hdr_len = 0;
3386 int r_idx = 0, tso;
9a799d71
AK		 3387 unsigned int mss = 0;
3388 int count = 0;
3389 unsigned int f;
3390 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3391 len -= skb->data_len;
30eba97a 3392 r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
30eba97a 3393 tx_ring = &adapter->tx_ring[r_idx];
9a799d71 3394
9a799d71
AK		 3395
3396 if (skb->len <= 0) {
3397 dev_kfree_skb(skb);
3398 return NETDEV_TX_OK;
3399 }
3400 mss = skb_shinfo(skb)->gso_size;
3401
3402 if (mss)
3403 count++;
3404 else if (skb->ip_summed == CHECKSUM_PARTIAL)
3405 count++;
3406
3407 count += TXD_USE_COUNT(len);
3408 for (f = 0; f < nr_frags; f++)
3409 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
3410
e092be60 3411 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 3412 adapter->tx_busy++;
9a799d71
AK		 3413 return NETDEV_TX_BUSY;
3414 }
9a799d71
AK		 3415 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3416 tx_flags |= IXGBE_TX_FLAGS_VLAN;
3417 tx_flags |= (vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT);
3418 }
3419
8327d000 3420 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 3421 tx_flags |= IXGBE_TX_FLAGS_IPV4;
3422 first = tx_ring->next_to_use;
3423 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
3424 if (tso < 0) {
3425 dev_kfree_skb_any(skb);
3426 return NETDEV_TX_OK;
3427 }
3428
3429 if (tso)
3430 tx_flags |= IXGBE_TX_FLAGS_TSO;
3431 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
3432 (skb->ip_summed == CHECKSUM_PARTIAL))
3433 tx_flags |= IXGBE_TX_FLAGS_CSUM;
3434
3435 ixgbe_tx_queue(adapter, tx_ring, tx_flags,
3436 ixgbe_tx_map(adapter, tx_ring, skb, first),
3437 skb->len, hdr_len);
3438
3439 netdev->trans_start = jiffies;
3440
e092be60 3441 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71
AK		 3442
3443 return NETDEV_TX_OK;
3444}
3445
3446/**
3447 * ixgbe_get_stats - Get System Network Statistics
3448 * @netdev: network interface device structure
3449 *
3450 * Returns the address of the device statistics structure.
3451 * The statistics are actually updated from the timer callback.
3452 **/
3453static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
3454{
3455 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3456
3457 /* only return the current stats */
3458 return &adapter->net_stats;
3459}
3460
3461/**
3462 * ixgbe_set_mac - Change the Ethernet Address of the NIC
3463 * @netdev: network interface device structure
3464 * @p: pointer to an address structure
3465 *
3466 * Returns 0 on success, negative on failure
3467 **/
3468static int ixgbe_set_mac(struct net_device *netdev, void *p)
3469{
3470 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3471 struct sockaddr *addr = p;
3472
3473 if (!is_valid_ether_addr(addr->sa_data))
3474 return -EADDRNOTAVAIL;
3475
3476 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3477 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
3478
3479 ixgbe_set_rar(&adapter->hw, 0, adapter->hw.mac.addr, 0, IXGBE_RAH_AV);
3480
3481 return 0;
3482}
3483
3484#ifdef CONFIG_NET_POLL_CONTROLLER
3485/*
3486 * Polling 'interrupt' - used by things like netconsole to send skbs
3487 * without having to re-enable interrupts. It's not called while
3488 * the interrupt routine is executing.
3489 */
3490static void ixgbe_netpoll(struct net_device *netdev)
3491{
3492 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3493
3494 disable_irq(adapter->pdev->irq);
3495 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
3496 ixgbe_intr(adapter->pdev->irq, netdev);
3497 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
3498 enable_irq(adapter->pdev->irq);
3499}
3500#endif
3501
021230d4
AV		 3502/**
3503 * ixgbe_napi_add_all - prep napi structs for use
3504 * @adapter: private struct
3505 * helper function to napi_add each possible q_vector->napi
3506 */
3507static void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
3508{
3509 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3510 int (*poll)(struct napi_struct *, int);
3511
3512 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3513 poll = &ixgbe_clean_rxonly;
3514 } else {
3515 poll = &ixgbe_poll;
3516 /* only one q_vector for legacy modes */
3517 q_vectors = 1;
3518 }
3519
3520 for (i = 0; i < q_vectors; i++) {
3521 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
3522 netif_napi_add(adapter->netdev, &q_vector->napi,
3523 (*poll), 64);
3524 }
3525}
3526
9a799d71
AK		 3527/**
3528 * ixgbe_probe - Device Initialization Routine
3529 * @pdev: PCI device information struct
3530 * @ent: entry in ixgbe_pci_tbl
3531 *
3532 * Returns 0 on success, negative on failure
3533 *
3534 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
3535 * The OS initialization, configuring of the adapter private structure,
3536 * and a hardware reset occur.
3537 **/
3538static int __devinit ixgbe_probe(struct pci_dev *pdev,
3539 const struct pci_device_id *ent)
3540{
3541 struct net_device *netdev;
3542 struct ixgbe_adapter *adapter = NULL;
3543 struct ixgbe_hw *hw;
3544 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
3545 unsigned long mmio_start, mmio_len;
3546 static int cards_found;
3547 int i, err, pci_using_dac;
3548 u16 link_status, link_speed, link_width;
3549 u32 part_num;
3550
3551 err = pci_enable_device(pdev);
3552 if (err)
3553 return err;
3554
3555 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
3556 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
3557 pci_using_dac = 1;
3558 } else {
3559 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3560 if (err) {
3561 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3562 if (err) {
3563 dev_err(&pdev->dev, "No usable DMA "
3564 "configuration, aborting\n");
3565 goto err_dma;
3566 }
3567 }
3568 pci_using_dac = 0;
3569 }
3570
3571 err = pci_request_regions(pdev, ixgbe_driver_name);
3572 if (err) {
3573 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
3574 goto err_pci_reg;
3575 }
3576
3577 pci_set_master(pdev);
fb3b27bc 3578 pci_save_state(pdev);
9a799d71 3579
30eba97a 3580 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 3581 if (!netdev) {
3582 err = -ENOMEM;
3583 goto err_alloc_etherdev;
3584 }
3585
9a799d71
AK		 3586 SET_NETDEV_DEV(netdev, &pdev->dev);
3587
3588 pci_set_drvdata(pdev, netdev);
3589 adapter = netdev_priv(netdev);
3590
3591 adapter->netdev = netdev;
3592 adapter->pdev = pdev;
3593 hw = &adapter->hw;
3594 hw->back = adapter;
3595 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
3596
3597 mmio_start = pci_resource_start(pdev, 0);
3598 mmio_len = pci_resource_len(pdev, 0);
3599
3600 hw->hw_addr = ioremap(mmio_start, mmio_len);
3601 if (!hw->hw_addr) {
3602 err = -EIO;
3603 goto err_ioremap;
3604 }
3605
3606 for (i = 1; i <= 5; i++) {
3607 if (pci_resource_len(pdev, i) == 0)
3608 continue;
3609 }
3610
3611 netdev->open = &ixgbe_open;
3612 netdev->stop = &ixgbe_close;
3613 netdev->hard_start_xmit = &ixgbe_xmit_frame;
3614 netdev->get_stats = &ixgbe_get_stats;
2c5645cf
CL		 3615 netdev->set_rx_mode = &ixgbe_set_rx_mode;
3616 netdev->set_multicast_list = &ixgbe_set_rx_mode;
9a799d71
AK		 3617 netdev->set_mac_address = &ixgbe_set_mac;
3618 netdev->change_mtu = &ixgbe_change_mtu;
3619 ixgbe_set_ethtool_ops(netdev);
3620 netdev->tx_timeout = &ixgbe_tx_timeout;
3621 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 3622 netdev->vlan_rx_register = ixgbe_vlan_rx_register;
3623 netdev->vlan_rx_add_vid = ixgbe_vlan_rx_add_vid;
3624 netdev->vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid;
3625#ifdef CONFIG_NET_POLL_CONTROLLER
3626 netdev->poll_controller = ixgbe_netpoll;
3627#endif
3628 strcpy(netdev->name, pci_name(pdev));
3629
3630 netdev->mem_start = mmio_start;
3631 netdev->mem_end = mmio_start + mmio_len;
3632
3633 adapter->bd_number = cards_found;
3634
3635 /* PCI config space info */
3636 hw->vendor_id = pdev->vendor;
3637 hw->device_id = pdev->device;
3638 hw->revision_id = pdev->revision;
3639 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3640 hw->subsystem_device_id = pdev->subsystem_device;
3641
3642 /* Setup hw api */
3643 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 3644 hw->mac.type = ii->mac;
9a799d71
AK		 3645
3646 err = ii->get_invariants(hw);
3647 if (err)
3648 goto err_hw_init;
3649
3650 /* setup the private structure */
3651 err = ixgbe_sw_init(adapter);
3652 if (err)
3653 goto err_sw_init;
3654
3655 netdev->features = NETIF_F_SG |
22f32b7a 3656 NETIF_F_IP_CSUM |
9a799d71
AK		 3657 NETIF_F_HW_VLAN_TX |
3658 NETIF_F_HW_VLAN_RX |
3659 NETIF_F_HW_VLAN_FILTER;
3660
e9990a9c 3661 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 3662 netdev->features |= NETIF_F_TSO;
9a799d71 3663 netdev->features |= NETIF_F_TSO6;
e9990a9c 3664 netdev->features |= NETIF_F_LRO;
ad31c402
JK		 3665
3666 netdev->vlan_features |= NETIF_F_TSO;
3667 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 3668 netdev->vlan_features |= NETIF_F_IP_CSUM;
ad31c402
JK		 3669 netdev->vlan_features |= NETIF_F_SG;
3670
9a799d71
AK		 3671 if (pci_using_dac)
3672 netdev->features |= NETIF_F_HIGHDMA;
3673
9a799d71
AK		 3674 /* make sure the EEPROM is good */
3675 if (ixgbe_validate_eeprom_checksum(hw, NULL) < 0) {
3676 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
3677 err = -EIO;
3678 goto err_eeprom;
3679 }
3680
3681 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
3682 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
3683
3684 if (ixgbe_validate_mac_addr(netdev->dev_addr)) {
3685 err = -EIO;
3686 goto err_eeprom;
3687 }
3688
3689 init_timer(&adapter->watchdog_timer);
3690 adapter->watchdog_timer.function = &ixgbe_watchdog;
3691 adapter->watchdog_timer.data = (unsigned long)adapter;
3692
3693 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
3694
021230d4
AV		 3695 err = ixgbe_init_interrupt_scheme(adapter);
3696 if (err)
3697 goto err_sw_init;
9a799d71
AK		 3698
3699 /* print bus type/speed/width info */
3700 pci_read_config_word(pdev, IXGBE_PCI_LINK_STATUS, &link_status);
3701 link_speed = link_status & IXGBE_PCI_LINK_SPEED;
3702 link_width = link_status & IXGBE_PCI_LINK_WIDTH;
3703 dev_info(&pdev->dev, "(PCI Express:%s:%s) "
3704 "%02x:%02x:%02x:%02x:%02x:%02x\n",
3705 ((link_speed == IXGBE_PCI_LINK_SPEED_5000) ? "5.0Gb/s" :
3706 (link_speed == IXGBE_PCI_LINK_SPEED_2500) ? "2.5Gb/s" :
3707 "Unknown"),
3708 ((link_width == IXGBE_PCI_LINK_WIDTH_8) ? "Width x8" :
3709 (link_width == IXGBE_PCI_LINK_WIDTH_4) ? "Width x4" :
3710 (link_width == IXGBE_PCI_LINK_WIDTH_2) ? "Width x2" :
3711 (link_width == IXGBE_PCI_LINK_WIDTH_1) ? "Width x1" :
3712 "Unknown"),
3713 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
3714 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
3715 ixgbe_read_part_num(hw, &part_num);
3716 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
3717 hw->mac.type, hw->phy.type,
3718 (part_num >> 8), (part_num & 0xff));
3719
0c254d86
AK		 3720 if (link_width <= IXGBE_PCI_LINK_WIDTH_4) {
3721 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
3722 "this card is not sufficient for optimal "
3723 "performance.\n");
3724 dev_warn(&pdev->dev, "For optimal performance a x8 "
3725 "PCI-Express slot is required.\n");
3726 }
3727
9a799d71
AK		 3728 /* reset the hardware with the new settings */
3729 ixgbe_start_hw(hw);
3730
3731 netif_carrier_off(netdev);
fd2ea0a7 3732 netif_tx_stop_all_queues(netdev);
9a799d71 3733
021230d4
AV		 3734 ixgbe_napi_add_all(adapter);
3735
9a799d71
AK		 3736 strcpy(netdev->name, "eth%d");
3737 err = register_netdev(netdev);
3738 if (err)
3739 goto err_register;
3740
96b0e0f6 3741#if defined(CONFIG_DCA) || defined (CONFIG_DCA_MODULE)
652f093f 3742 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd
JC		 3743 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
3744 /* always use CB2 mode, difference is masked
3745 * in the CB driver */
3746 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
3747 ixgbe_setup_dca(adapter);
3748 }
3749#endif
9a799d71
AK		 3750
3751 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
3752 cards_found++;
3753 return 0;
3754
3755err_register:
5eba3699 3756 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3757err_hw_init:
3758err_sw_init:
021230d4 3759 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 3760err_eeprom:
3761 iounmap(hw->hw_addr);
3762err_ioremap:
3763 free_netdev(netdev);
3764err_alloc_etherdev:
3765 pci_release_regions(pdev);
3766err_pci_reg:
3767err_dma:
3768 pci_disable_device(pdev);
3769 return err;
3770}
3771
3772/**
3773 * ixgbe_remove - Device Removal Routine
3774 * @pdev: PCI device information struct
3775 *
3776 * ixgbe_remove is called by the PCI subsystem to alert the driver
3777 * that it should release a PCI device. The could be caused by a
3778 * Hot-Plug event, or because the driver is going to be removed from
3779 * memory.
3780 **/
3781static void __devexit ixgbe_remove(struct pci_dev *pdev)
3782{
3783 struct net_device *netdev = pci_get_drvdata(pdev);
3784 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3785
3786 set_bit(__IXGBE_DOWN, &adapter->state);
3787 del_timer_sync(&adapter->watchdog_timer);
3788
3789 flush_scheduled_work();
3790
96b0e0f6 3791#if defined(CONFIG_DCA) || defined (CONFIG_DCA_MODULE)
bd0362dd
JC		 3792 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3793 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
3794 dca_remove_requester(&pdev->dev);
3795 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
3796 }
3797
3798#endif
9a799d71
AK		 3799 unregister_netdev(netdev);
3800
021230d4 3801 ixgbe_reset_interrupt_capability(adapter);
5eba3699 3802
021230d4 3803 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3804
3805 iounmap(adapter->hw.hw_addr);
3806 pci_release_regions(pdev);
3807
021230d4
AV		 3808 DPRINTK(PROBE, INFO, "complete\n");
3809 kfree(adapter->tx_ring);
3810 kfree(adapter->rx_ring);
3811
9a799d71
AK		 3812 free_netdev(netdev);
3813
3814 pci_disable_device(pdev);
3815}
3816
3817/**
3818 * ixgbe_io_error_detected - called when PCI error is detected
3819 * @pdev: Pointer to PCI device
3820 * @state: The current pci connection state
3821 *
3822 * This function is called after a PCI bus error affecting
3823 * this device has been detected.
3824 */
3825static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
3826 pci_channel_state_t state)
3827{
3828 struct net_device *netdev = pci_get_drvdata(pdev);
3829 struct ixgbe_adapter *adapter = netdev->priv;
3830
3831 netif_device_detach(netdev);
3832
3833 if (netif_running(netdev))
3834 ixgbe_down(adapter);
3835 pci_disable_device(pdev);
3836
3837 /* Request a slot slot reset. */
3838 return PCI_ERS_RESULT_NEED_RESET;
3839}
3840
3841/**
3842 * ixgbe_io_slot_reset - called after the pci bus has been reset.
3843 * @pdev: Pointer to PCI device
3844 *
3845 * Restart the card from scratch, as if from a cold-boot.
3846 */
3847static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
3848{
3849 struct net_device *netdev = pci_get_drvdata(pdev);
3850 struct ixgbe_adapter *adapter = netdev->priv;
3851
3852 if (pci_enable_device(pdev)) {
3853 DPRINTK(PROBE, ERR,
3854 "Cannot re-enable PCI device after reset.\n");
3855 return PCI_ERS_RESULT_DISCONNECT;
3856 }
3857 pci_set_master(pdev);
fb3b27bc 3858 pci_restore_state(pdev);
9a799d71
AK		 3859
3860 pci_enable_wake(pdev, PCI_D3hot, 0);
3861 pci_enable_wake(pdev, PCI_D3cold, 0);
3862
3863 ixgbe_reset(adapter);
3864
3865 return PCI_ERS_RESULT_RECOVERED;
3866}
3867
3868/**
3869 * ixgbe_io_resume - called when traffic can start flowing again.
3870 * @pdev: Pointer to PCI device
3871 *
3872 * This callback is called when the error recovery driver tells us that
3873 * its OK to resume normal operation.
3874 */
3875static void ixgbe_io_resume(struct pci_dev *pdev)
3876{
3877 struct net_device *netdev = pci_get_drvdata(pdev);
3878 struct ixgbe_adapter *adapter = netdev->priv;
3879
3880 if (netif_running(netdev)) {
3881 if (ixgbe_up(adapter)) {
3882 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
3883 return;
3884 }
3885 }
3886
3887 netif_device_attach(netdev);
3888
3889}
3890
3891static struct pci_error_handlers ixgbe_err_handler = {
3892 .error_detected = ixgbe_io_error_detected,
3893 .slot_reset = ixgbe_io_slot_reset,
3894 .resume = ixgbe_io_resume,
3895};
3896
3897static struct pci_driver ixgbe_driver = {
3898 .name = ixgbe_driver_name,
3899 .id_table = ixgbe_pci_tbl,
3900 .probe = ixgbe_probe,
3901 .remove = __devexit_p(ixgbe_remove),
3902#ifdef CONFIG_PM
3903 .suspend = ixgbe_suspend,
3904 .resume = ixgbe_resume,
3905#endif
3906 .shutdown = ixgbe_shutdown,
3907 .err_handler = &ixgbe_err_handler
3908};
3909
3910/**
3911 * ixgbe_init_module - Driver Registration Routine
3912 *
3913 * ixgbe_init_module is the first routine called when the driver is
3914 * loaded. All it does is register with the PCI subsystem.
3915 **/
3916static int __init ixgbe_init_module(void)
3917{
3918 int ret;
3919 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
3920 ixgbe_driver_string, ixgbe_driver_version);
3921
3922 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
3923
96b0e0f6 3924#if defined(CONFIG_DCA) || defined (CONFIG_DCA_MODULE)
bd0362dd
JC		 3925 dca_register_notify(&dca_notifier);
3926
3927#endif
9a799d71
AK		 3928 ret = pci_register_driver(&ixgbe_driver);
3929 return ret;
3930}
3931module_init(ixgbe_init_module);
3932
3933/**
3934 * ixgbe_exit_module - Driver Exit Cleanup Routine
3935 *
3936 * ixgbe_exit_module is called just before the driver is removed
3937 * from memory.
3938 **/
3939static void __exit ixgbe_exit_module(void)
3940{
96b0e0f6 3941#if defined(CONFIG_DCA) || defined (CONFIG_DCA_MODULE)
bd0362dd
JC		 3942 dca_unregister_notify(&dca_notifier);
3943#endif
9a799d71
AK		 3944 pci_unregister_driver(&ixgbe_driver);
3945}
bd0362dd 3946
96b0e0f6 3947#if defined(CONFIG_DCA) || defined (CONFIG_DCA_MODULE)
bd0362dd
JC		 3948static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
3949 void *p)
3950{
3951 int ret_val;
3952
3953 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
3954 __ixgbe_notify_dca);
3955
3956 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3957}
96b0e0f6 3958#endif /* CONFIG_DCA or CONFIG_DCA_MODULE */
bd0362dd 3959
9a799d71
AK		 3960module_exit(ixgbe_exit_module);
3961
3962/* ixgbe_main.c */
kernel source for telekom puls (alcatel/mediatek)