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ixgbe: fix failing to log fan failures
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/ipv6.h>
38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
40#include <linux/ethtool.h>
41#include <linux/if_vlan.h>
42
43#include "ixgbe.h"
44#include "ixgbe_common.h"
45
46char ixgbe_driver_name[] = "ixgbe";
9c8eb720 47static const char ixgbe_driver_string[] =
b4617240 48 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 49
04193058 50#define DRV_VERSION "2.0.16-k2"
9c8eb720 51const char ixgbe_driver_version[] = DRV_VERSION;
3efac5a0 52static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
9a799d71
AK		 53
54static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 55 [board_82598] = &ixgbe_82598_info,
e8e26350 56 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 57};
58
59/* ixgbe_pci_tbl - PCI Device ID Table
60 *
61 * Wildcard entries (PCI_ANY_ID) should come last
62 * Last entry must be all 0s
63 *
64 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
65 * Class, Class Mask, private data (not used) }
66 */
67static struct pci_device_id ixgbe_pci_tbl[] = {
1e336d0f
DS		 68 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
69 board_82598 },
9a799d71 70 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 71 board_82598 },
9a799d71 72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 73 board_82598 },
0befdb3e
JB		 74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
75 board_82598 },
9a799d71 76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 77 board_82598 },
8d792cd9
JB		 78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
79 board_82598 },
c4900be0
DS		 80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
81 board_82598 },
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
83 board_82598 },
b95f5fcb
JB		 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
85 board_82598 },
c4900be0
DS		 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
87 board_82598 },
2f21bdd3
DS		 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
89 board_82598 },
e8e26350
PW		 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
91 board_82599 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
93 board_82599 },
9a799d71
AK		 94
95 /* required last entry */
96 {0, }
97};
98MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
99
5dd2d332 100#ifdef CONFIG_IXGBE_DCA
bd0362dd 101static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 102 void *p);
bd0362dd
JC		 103static struct notifier_block dca_notifier = {
104 .notifier_call = ixgbe_notify_dca,
105 .next = NULL,
106 .priority = 0
107};
108#endif
109
9a799d71
AK		 110MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
111MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
112MODULE_LICENSE("GPL");
113MODULE_VERSION(DRV_VERSION);
114
115#define DEFAULT_DEBUG_LEVEL_SHIFT 3
116
5eba3699
AV		 117static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
118{
119 u32 ctrl_ext;
120
121 /* Let firmware take over control of h/w */
122 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
123 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 124 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 125}
126
127static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
128{
129 u32 ctrl_ext;
130
131 /* Let firmware know the driver has taken over */
132 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
133 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 134 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 135}
9a799d71 136
e8e26350
PW		 137/*
138 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
139 * @adapter: pointer to adapter struct
140 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
141 * @queue: queue to map the corresponding interrupt to
142 * @msix_vector: the vector to map to the corresponding queue
143 *
144 */
145static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
146 u8 queue, u8 msix_vector)
9a799d71
AK		 147{
148 u32 ivar, index;
e8e26350
PW		 149 struct ixgbe_hw *hw = &adapter->hw;
150 switch (hw->mac.type) {
151 case ixgbe_mac_82598EB:
152 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
153 if (direction == -1)
154 direction = 0;
155 index = (((direction * 64) + queue) >> 2) & 0x1F;
156 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
157 ivar &= ~(0xFF << (8 * (queue & 0x3)));
158 ivar |= (msix_vector << (8 * (queue & 0x3)));
159 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
160 break;
161 case ixgbe_mac_82599EB:
162 if (direction == -1) {
163 /* other causes */
164 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
165 index = ((queue & 1) * 8);
166 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
167 ivar &= ~(0xFF << index);
168 ivar |= (msix_vector << index);
169 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
170 break;
171 } else {
172 /* tx or rx causes */
173 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
174 index = ((16 * (queue & 1)) + (8 * direction));
175 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
176 ivar &= ~(0xFF << index);
177 ivar |= (msix_vector << index);
178 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
179 break;
180 }
181 default:
182 break;
183 }
9a799d71
AK		 184}
185
186static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 187 struct ixgbe_tx_buffer
188 *tx_buffer_info)
9a799d71 189{
44df32c5 190 tx_buffer_info->dma = 0;
9a799d71 191 if (tx_buffer_info->skb) {
44df32c5
AD		 192 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
193 DMA_TO_DEVICE);
9a799d71
AK		 194 dev_kfree_skb_any(tx_buffer_info->skb);
195 tx_buffer_info->skb = NULL;
196 }
44df32c5 197 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 198 /* tx_buffer_info must be completely set up in the transmit path */
199}
200
201static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 202 struct ixgbe_ring *tx_ring,
203 unsigned int eop)
9a799d71 204{
e01c31a5 205 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 206
9a799d71 207 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 208 * check with the clearing of time_stamp and movement of eop */
9a799d71 209 adapter->detect_tx_hung = false;
44df32c5 210 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 211 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
212 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
213 /* detected Tx unit hang */
e01c31a5
JB		 214 union ixgbe_adv_tx_desc *tx_desc;
215 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 216 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 217 " Tx Queue <%d>\n"
218 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 219 " next_to_use <%x>\n"
220 " next_to_clean <%x>\n"
221 "tx_buffer_info[next_to_clean]\n"
222 " time_stamp <%lx>\n"
e01c31a5
JB		 223 " jiffies <%lx>\n",
224 tx_ring->queue_index,
44df32c5
AD		 225 IXGBE_READ_REG(hw, tx_ring->head),
226 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 227 tx_ring->next_to_use, eop,
228 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 229 return true;
230 }
231
232 return false;
233}
234
b4617240
PW		 235#define IXGBE_MAX_TXD_PWR 14
236#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 237
238/* Tx Descriptors needed, worst case */
239#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
240 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
241#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 242 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 243
e01c31a5
JB		 244static void ixgbe_tx_timeout(struct net_device *netdev);
245
9a799d71
AK		 246/**
247 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
248 * @adapter: board private structure
e01c31a5 249 * @tx_ring: tx ring to clean
9a1a69ad
JB		 250 *
251 * returns true if transmit work is done
9a799d71
AK		 252 **/
253static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
e01c31a5 254 struct ixgbe_ring *tx_ring)
9a799d71 255{
e01c31a5 256 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 257 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
258 struct ixgbe_tx_buffer *tx_buffer_info;
259 unsigned int i, eop, count = 0;
e01c31a5 260 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 261
262 i = tx_ring->next_to_clean;
12207e49
PWJ		 263 eop = tx_ring->tx_buffer_info[i].next_to_watch;
264 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
265
266 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 267 (count < tx_ring->work_limit)) {
12207e49
PWJ		 268 bool cleaned = false;
269 for ( ; !cleaned; count++) {
270 struct sk_buff *skb;
9a799d71
AK		 271 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
272 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 273 cleaned = (i == eop);
e01c31a5 274 skb = tx_buffer_info->skb;
9a799d71 275
12207e49 276 if (cleaned && skb) {
e092be60 277 unsigned int segs, bytecount;
e01c31a5
JB		 278
279 /* gso_segs is currently only valid for tcp */
e092be60
AV		 280 segs = skb_shinfo(skb)->gso_segs ?: 1;
281 /* multiply data chunks by size of headers */
282 bytecount = ((segs - 1) * skb_headlen(skb)) +
e01c31a5
JB		 283 skb->len;
284 total_packets += segs;
285 total_bytes += bytecount;
e092be60 286 }
e01c31a5 287
9a799d71 288 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 289 tx_buffer_info);
9a799d71 290
12207e49
PWJ		 291 tx_desc->wb.status = 0;
292
9a799d71
AK		 293 i++;
294 if (i == tx_ring->count)
295 i = 0;
e01c31a5 296 }
12207e49
PWJ		 297
298 eop = tx_ring->tx_buffer_info[i].next_to_watch;
299 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
300 }
301
9a799d71
AK		 302 tx_ring->next_to_clean = i;
303
e092be60 304#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 305 if (unlikely(count && netif_carrier_ok(netdev) &&
306 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 307 /* Make sure that anybody stopping the queue after this
308 * sees the new next_to_clean.
309 */
310 smp_mb();
30eba97a
AV		 311 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
312 !test_bit(__IXGBE_DOWN, &adapter->state)) {
313 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 314 ++adapter->restart_queue;
30eba97a 315 }
e092be60 316 }
9a799d71 317
e01c31a5
JB		 318 if (adapter->detect_tx_hung) {
319 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
320 /* schedule immediate reset if we believe we hung */
321 DPRINTK(PROBE, INFO,
322 "tx hang %d detected, resetting adapter\n",
323 adapter->tx_timeout_count + 1);
324 ixgbe_tx_timeout(adapter->netdev);
325 }
326 }
9a799d71 327
e01c31a5 328 /* re-arm the interrupt */
835462fc
NS		 329 if (count >= tx_ring->work_limit) {
330 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
331 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
332 tx_ring->v_idx);
333 else if (tx_ring->v_idx & 0xFFFFFFFF)
334 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0),
335 tx_ring->v_idx);
336 else
337 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1),
338 (tx_ring->v_idx >> 32));
339 }
340
9a799d71 341
e01c31a5
JB		 342 tx_ring->total_bytes += total_bytes;
343 tx_ring->total_packets += total_packets;
e01c31a5 344 tx_ring->stats.packets += total_packets;
12207e49 345 tx_ring->stats.bytes += total_bytes;
e01c31a5
JB		 346 adapter->net_stats.tx_bytes += total_bytes;
347 adapter->net_stats.tx_packets += total_packets;
9a1a69ad 348 return (count < tx_ring->work_limit);
9a799d71
AK		 349}
350
5dd2d332 351#ifdef CONFIG_IXGBE_DCA
bd0362dd 352static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 353 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 354{
355 u32 rxctrl;
356 int cpu = get_cpu();
3a581073 357 int q = rx_ring - adapter->rx_ring;
bd0362dd 358
3a581073 359 if (rx_ring->cpu != cpu) {
bd0362dd 360 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 361 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
362 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
363 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
364 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
365 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
366 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
367 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
368 }
bd0362dd
JC		 369 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
370 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 371 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
372 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 373 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 374 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 375 rx_ring->cpu = cpu;
bd0362dd
JC		 376 }
377 put_cpu();
378}
379
380static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 381 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 382{
383 u32 txctrl;
384 int cpu = get_cpu();
3a581073 385 int q = tx_ring - adapter->tx_ring;
bd0362dd 386
3a581073 387 if (tx_ring->cpu != cpu) {
bd0362dd 388 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 389 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
390 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
391 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
392 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
393 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
394 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
395 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
396 }
bd0362dd
JC		 397 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
398 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 399 tx_ring->cpu = cpu;
bd0362dd
JC		 400 }
401 put_cpu();
402}
403
404static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
405{
406 int i;
407
408 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
409 return;
410
411 for (i = 0; i < adapter->num_tx_queues; i++) {
412 adapter->tx_ring[i].cpu = -1;
413 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
414 }
415 for (i = 0; i < adapter->num_rx_queues; i++) {
416 adapter->rx_ring[i].cpu = -1;
417 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
418 }
419}
420
421static int __ixgbe_notify_dca(struct device *dev, void *data)
422{
423 struct net_device *netdev = dev_get_drvdata(dev);
424 struct ixgbe_adapter *adapter = netdev_priv(netdev);
425 unsigned long event = *(unsigned long *)data;
426
427 switch (event) {
428 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 429 /* if we're already enabled, don't do it again */
430 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
431 break;
bd0362dd
JC		 432 /* Always use CB2 mode, difference is masked
433 * in the CB driver. */
434 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
652f093f 435 if (dca_add_requester(dev) == 0) {
96b0e0f6 436 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 437 ixgbe_setup_dca(adapter);
438 break;
439 }
440 /* Fall Through since DCA is disabled. */
441 case DCA_PROVIDER_REMOVE:
442 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
443 dca_remove_requester(dev);
444 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
445 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
446 }
447 break;
448 }
449
652f093f 450 return 0;
bd0362dd
JC		 451}
452
5dd2d332 453#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 454/**
455 * ixgbe_receive_skb - Send a completed packet up the stack
456 * @adapter: board private structure
457 * @skb: packet to send up
177db6ff
MC		 458 * @status: hardware indication of status of receive
459 * @rx_ring: rx descriptor ring (for a specific queue) to setup
460 * @rx_desc: rx descriptor
9a799d71 461 **/
78b6f4ce 462static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 463 struct sk_buff *skb, u8 status,
fdaff1ce 464 struct ixgbe_ring *ring,
177db6ff 465 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 466{
78b6f4ce
HX		 467 struct ixgbe_adapter *adapter = q_vector->adapter;
468 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 469 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
470 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 471
fdaff1ce 472 skb_record_rx_queue(skb, ring->queue_index);
182ff8df 473 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
2f90b865 474 if (adapter->vlgrp && is_vlan && (tag != 0))
78b6f4ce 475 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 476 else
78b6f4ce 477 napi_gro_receive(napi, skb);
177db6ff 478 } else {
182ff8df
AD		 479 if (adapter->vlgrp && is_vlan && (tag != 0))
480 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
481 else
482 netif_rx(skb);
9a799d71
AK		 483 }
484}
485
e59bd25d
AV		 486/**
487 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
488 * @adapter: address of board private structure
489 * @status_err: hardware indication of status of receive
490 * @skb: skb currently being received and modified
491 **/
9a799d71 492static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
712744be 493 u32 status_err, struct sk_buff *skb)
9a799d71
AK		 494{
495 skb->ip_summed = CHECKSUM_NONE;
496
712744be
JB		 497 /* Rx csum disabled */
498 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 499 return;
e59bd25d
AV		 500
501 /* if IP and error */
502 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
503 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 504 adapter->hw_csum_rx_error++;
505 return;
506 }
e59bd25d
AV		 507
508 if (!(status_err & IXGBE_RXD_STAT_L4CS))
509 return;
510
511 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
512 adapter->hw_csum_rx_error++;
513 return;
514 }
515
9a799d71 516 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 517 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 518 adapter->hw_csum_rx_good++;
519}
520
e8e26350
PW		 521static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
522 struct ixgbe_ring *rx_ring, u32 val)
523{
524 /*
525 * Force memory writes to complete before letting h/w
526 * know there are new descriptors to fetch. (Only
527 * applicable for weak-ordered memory model archs,
528 * such as IA-64).
529 */
530 wmb();
531 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
532}
533
9a799d71
AK		 534/**
535 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
536 * @adapter: address of board private structure
537 **/
538static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 539 struct ixgbe_ring *rx_ring,
540 int cleaned_count)
9a799d71 541{
9a799d71
AK		 542 struct pci_dev *pdev = adapter->pdev;
543 union ixgbe_adv_rx_desc *rx_desc;
3a581073 544 struct ixgbe_rx_buffer *bi;
9a799d71 545 unsigned int i;
e8e26350 546 unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
9a799d71
AK		 547
548 i = rx_ring->next_to_use;
3a581073 549 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 550
551 while (cleaned_count--) {
552 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
553
762f4c57 554 if (!bi->page_dma &&
3a581073 555 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
3a581073 556 if (!bi->page) {
762f4c57
JB		 557 bi->page = alloc_page(GFP_ATOMIC);
558 if (!bi->page) {
559 adapter->alloc_rx_page_failed++;
560 goto no_buffers;
561 }
562 bi->page_offset = 0;
563 } else {
564 /* use a half page if we're re-using */
565 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 566 }
762f4c57
JB		 567
568 bi->page_dma = pci_map_page(pdev, bi->page,
569 bi->page_offset,
570 (PAGE_SIZE / 2),
571 PCI_DMA_FROMDEVICE);
9a799d71
AK		 572 }
573
3a581073 574 if (!bi->skb) {
5ecc3614 575 struct sk_buff *skb;
e8e26350 576 skb = netdev_alloc_skb(adapter->netdev, bufsz);
9a799d71
AK		 577
578 if (!skb) {
579 adapter->alloc_rx_buff_failed++;
580 goto no_buffers;
581 }
582
583 /*
584 * Make buffer alignment 2 beyond a 16 byte boundary
585 * this will result in a 16 byte aligned IP header after
586 * the 14 byte MAC header is removed
587 */
588 skb_reserve(skb, NET_IP_ALIGN);
589
3a581073 590 bi->skb = skb;
e8e26350 591 bi->dma = pci_map_single(pdev, skb->data, bufsz,
3a581073 592 PCI_DMA_FROMDEVICE);
9a799d71
AK		 593 }
594 /* Refresh the desc even if buffer_addrs didn't change because
595 * each write-back erases this info. */
596 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3a581073
JB		 597 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
598 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 599 } else {
3a581073 600 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 601 }
602
603 i++;
604 if (i == rx_ring->count)
605 i = 0;
3a581073 606 bi = &rx_ring->rx_buffer_info[i];
9a799d71 607 }
7c6e0a43 608
9a799d71
AK		 609no_buffers:
610 if (rx_ring->next_to_use != i) {
611 rx_ring->next_to_use = i;
612 if (i-- == 0)
613 i = (rx_ring->count - 1);
614
e8e26350 615 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 616 }
617}
618
7c6e0a43
JB		 619static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
620{
621 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
622}
623
624static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
625{
626 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
627}
628
f8212f97
AD		 629static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
630{
631 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
632 IXGBE_RXDADV_RSCCNT_MASK) >>
633 IXGBE_RXDADV_RSCCNT_SHIFT;
634}
635
636/**
637 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
638 * @skb: pointer to the last skb in the rsc queue
639 *
640 * This function changes a queue full of hw rsc buffers into a completed
641 * packet. It uses the ->prev pointers to find the first packet and then
642 * turns it into the frag list owner.
643 **/
644static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
645{
646 unsigned int frag_list_size = 0;
647
648 while (skb->prev) {
649 struct sk_buff *prev = skb->prev;
650 frag_list_size += skb->len;
651 skb->prev = NULL;
652 skb = prev;
653 }
654
655 skb_shinfo(skb)->frag_list = skb->next;
656 skb->next = NULL;
657 skb->len += frag_list_size;
658 skb->data_len += frag_list_size;
659 skb->truesize += frag_list_size;
660 return skb;
661}
662
78b6f4ce 663static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 664 struct ixgbe_ring *rx_ring,
665 int *work_done, int work_to_do)
9a799d71 666{
78b6f4ce 667 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 668 struct pci_dev *pdev = adapter->pdev;
669 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
670 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
671 struct sk_buff *skb;
f8212f97 672 unsigned int i, rsc_count = 0;
7c6e0a43 673 u32 len, staterr;
177db6ff
MC		 674 u16 hdr_info;
675 bool cleaned = false;
9a799d71 676 int cleaned_count = 0;
d2f4fbe2 677 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
9a799d71
AK		 678
679 i = rx_ring->next_to_clean;
9a799d71
AK		 680 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
681 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
682 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 683
684 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 685 u32 upper_len = 0;
9a799d71
AK		 686 if (*work_done >= work_to_do)
687 break;
688 (*work_done)++;
689
690 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43
JB		 691 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
692 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 693 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 694 if (hdr_info & IXGBE_RXDADV_SPH)
695 adapter->rx_hdr_split++;
696 if (len > IXGBE_RX_HDR_SIZE)
697 len = IXGBE_RX_HDR_SIZE;
698 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 699 } else {
9a799d71 700 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 701 }
9a799d71
AK		 702
703 cleaned = true;
704 skb = rx_buffer_info->skb;
705 prefetch(skb->data - NET_IP_ALIGN);
706 rx_buffer_info->skb = NULL;
707
708 if (len && !skb_shinfo(skb)->nr_frags) {
709 pci_unmap_single(pdev, rx_buffer_info->dma,
5ecc3614 710 rx_ring->rx_buf_len,
b4617240 711 PCI_DMA_FROMDEVICE);
9a799d71
AK		 712 skb_put(skb, len);
713 }
714
715 if (upper_len) {
716 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 717 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 718 rx_buffer_info->page_dma = 0;
719 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 720 rx_buffer_info->page,
721 rx_buffer_info->page_offset,
722 upper_len);
723
724 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
725 (page_count(rx_buffer_info->page) != 1))
726 rx_buffer_info->page = NULL;
727 else
728 get_page(rx_buffer_info->page);
9a799d71
AK		 729
730 skb->len += upper_len;
731 skb->data_len += upper_len;
732 skb->truesize += upper_len;
733 }
734
735 i++;
736 if (i == rx_ring->count)
737 i = 0;
9a799d71
AK		 738
739 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
740 prefetch(next_rxd);
9a799d71 741 cleaned_count++;
f8212f97
AD		 742
743 if (adapter->flags & IXGBE_FLAG_RSC_CAPABLE)
744 rsc_count = ixgbe_get_rsc_count(rx_desc);
745
746 if (rsc_count) {
747 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
748 IXGBE_RXDADV_NEXTP_SHIFT;
749 next_buffer = &rx_ring->rx_buffer_info[nextp];
750 rx_ring->rsc_count += (rsc_count - 1);
751 } else {
752 next_buffer = &rx_ring->rx_buffer_info[i];
753 }
754
9a799d71 755 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97
AD		 756 if (skb->prev)
757 skb = ixgbe_transform_rsc_queue(skb);
9a799d71
AK		 758 rx_ring->stats.packets++;
759 rx_ring->stats.bytes += skb->len;
760 } else {
f8212f97
AD		 761 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
762 rx_buffer_info->skb = next_buffer->skb;
763 rx_buffer_info->dma = next_buffer->dma;
764 next_buffer->skb = skb;
765 next_buffer->dma = 0;
766 } else {
767 skb->next = next_buffer->skb;
768 skb->next->prev = skb;
769 }
9a799d71
AK		 770 adapter->non_eop_descs++;
771 goto next_desc;
772 }
773
774 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
775 dev_kfree_skb_irq(skb);
776 goto next_desc;
777 }
778
779 ixgbe_rx_checksum(adapter, staterr, skb);
d2f4fbe2
AV		 780
781 /* probably a little skewed due to removing CRC */
782 total_rx_bytes += skb->len;
783 total_rx_packets++;
784
74ce8dd2 785 skb->protocol = eth_type_trans(skb, adapter->netdev);
fdaff1ce 786 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 787
788next_desc:
789 rx_desc->wb.upper.status_error = 0;
790
791 /* return some buffers to hardware, one at a time is too slow */
792 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
793 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
794 cleaned_count = 0;
795 }
796
797 /* use prefetched values */
798 rx_desc = next_rxd;
f8212f97 799 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 800
801 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 802 }
803
9a799d71
AK		 804 rx_ring->next_to_clean = i;
805 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
806
807 if (cleaned_count)
808 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
809
f494e8fa
AV		 810 rx_ring->total_packets += total_rx_packets;
811 rx_ring->total_bytes += total_rx_bytes;
812 adapter->net_stats.rx_bytes += total_rx_bytes;
813 adapter->net_stats.rx_packets += total_rx_packets;
814
9a799d71
AK		 815 return cleaned;
816}
817
021230d4 818static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 819/**
820 * ixgbe_configure_msix - Configure MSI-X hardware
821 * @adapter: board private structure
822 *
823 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
824 * interrupts.
825 **/
826static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
827{
021230d4
AV		 828 struct ixgbe_q_vector *q_vector;
829 int i, j, q_vectors, v_idx, r_idx;
830 u32 mask;
9a799d71 831
021230d4 832 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 833
4df10466
JB		 834 /*
835 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 836 * corresponding register.
837 */
838 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 839 q_vector = adapter->q_vector[v_idx];
021230d4
AV		 840 /* XXX for_each_bit(...) */
841 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 842 adapter->num_rx_queues);
021230d4
AV		 843
844 for (i = 0; i < q_vector->rxr_count; i++) {
845 j = adapter->rx_ring[r_idx].reg_idx;
e8e26350 846 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 847 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 848 adapter->num_rx_queues,
849 r_idx + 1);
021230d4
AV		 850 }
851 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 852 adapter->num_tx_queues);
021230d4
AV		 853
854 for (i = 0; i < q_vector->txr_count; i++) {
855 j = adapter->tx_ring[r_idx].reg_idx;
e8e26350 856 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 857 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 858 adapter->num_tx_queues,
859 r_idx + 1);
021230d4
AV		 860 }
861
30efa5a3 862 /* if this is a tx only vector halve the interrupt rate */
021230d4 863 if (q_vector->txr_count && !q_vector->rxr_count)
30efa5a3 864 q_vector->eitr = (adapter->eitr_param >> 1);
509ee935 865 else if (q_vector->rxr_count)
30efa5a3
JB		 866 /* rx only */
867 q_vector->eitr = adapter->eitr_param;
021230d4 868
509ee935 869 /*
4df10466 870 * since this is initial set up don't need to call
509ee935
JB		 871 * ixgbe_write_eitr helper
872 */
021230d4 873 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
b4617240 874 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
9a799d71
AK		 875 }
876
e8e26350
PW		 877 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
878 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
879 v_idx);
880 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
881 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 882 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
883
41fb9248 884 /* set up to autoclear timer, and the vectors */
021230d4 885 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 886 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 887 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 888}
889
f494e8fa
AV		 890enum latency_range {
891 lowest_latency = 0,
892 low_latency = 1,
893 bulk_latency = 2,
894 latency_invalid = 255
895};
896
897/**
898 * ixgbe_update_itr - update the dynamic ITR value based on statistics
899 * @adapter: pointer to adapter
900 * @eitr: eitr setting (ints per sec) to give last timeslice
901 * @itr_setting: current throttle rate in ints/second
902 * @packets: the number of packets during this measurement interval
903 * @bytes: the number of bytes during this measurement interval
904 *
905 * Stores a new ITR value based on packets and byte
906 * counts during the last interrupt. The advantage of per interrupt
907 * computation is faster updates and more accurate ITR for the current
908 * traffic pattern. Constants in this function were computed
909 * based on theoretical maximum wire speed and thresholds were set based
910 * on testing data as well as attempting to minimize response time
911 * while increasing bulk throughput.
912 * this functionality is controlled by the InterruptThrottleRate module
913 * parameter (see ixgbe_param.c)
914 **/
915static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 916 u32 eitr, u8 itr_setting,
917 int packets, int bytes)
f494e8fa
AV		 918{
919 unsigned int retval = itr_setting;
920 u32 timepassed_us;
921 u64 bytes_perint;
922
923 if (packets == 0)
924 goto update_itr_done;
925
926
927 /* simple throttlerate management
928 * 0-20MB/s lowest (100000 ints/s)
929 * 20-100MB/s low (20000 ints/s)
930 * 100-1249MB/s bulk (8000 ints/s)
931 */
932 /* what was last interrupt timeslice? */
933 timepassed_us = 1000000/eitr;
934 bytes_perint = bytes / timepassed_us; /* bytes/usec */
935
936 switch (itr_setting) {
937 case lowest_latency:
938 if (bytes_perint > adapter->eitr_low)
939 retval = low_latency;
940 break;
941 case low_latency:
942 if (bytes_perint > adapter->eitr_high)
943 retval = bulk_latency;
944 else if (bytes_perint <= adapter->eitr_low)
945 retval = lowest_latency;
946 break;
947 case bulk_latency:
948 if (bytes_perint <= adapter->eitr_high)
949 retval = low_latency;
950 break;
951 }
952
953update_itr_done:
954 return retval;
955}
956
509ee935
JB		 957/**
958 * ixgbe_write_eitr - write EITR register in hardware specific way
959 * @adapter: pointer to adapter struct
960 * @v_idx: vector index into q_vector array
961 * @itr_reg: new value to be written in *register* format, not ints/s
962 *
963 * This function is made to be called by ethtool and by the driver
964 * when it needs to update EITR registers at runtime. Hardware
965 * specific quirks/differences are taken care of here.
966 */
967void ixgbe_write_eitr(struct ixgbe_adapter *adapter, int v_idx, u32 itr_reg)
968{
969 struct ixgbe_hw *hw = &adapter->hw;
970 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
971 /* must write high and low 16 bits to reset counter */
972 itr_reg |= (itr_reg << 16);
973 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
974 /*
975 * set the WDIS bit to not clear the timer bits and cause an
976 * immediate assertion of the interrupt
977 */
978 itr_reg |= IXGBE_EITR_CNT_WDIS;
979 }
980 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
981}
982
f494e8fa
AV		 983static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
984{
985 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 986 u32 new_itr;
987 u8 current_itr, ret_itr;
7a921c93 988 int i, r_idx, v_idx = q_vector->v_idx;
f494e8fa
AV		 989 struct ixgbe_ring *rx_ring, *tx_ring;
990
991 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
992 for (i = 0; i < q_vector->txr_count; i++) {
993 tx_ring = &(adapter->tx_ring[r_idx]);
994 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 995 q_vector->tx_itr,
996 tx_ring->total_packets,
997 tx_ring->total_bytes);
f494e8fa
AV		 998 /* if the result for this queue would decrease interrupt
999 * rate for this vector then use that result */
30efa5a3 1000 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1001 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1002 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1003 r_idx + 1);
f494e8fa
AV		 1004 }
1005
1006 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1007 for (i = 0; i < q_vector->rxr_count; i++) {
1008 rx_ring = &(adapter->rx_ring[r_idx]);
1009 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1010 q_vector->rx_itr,
1011 rx_ring->total_packets,
1012 rx_ring->total_bytes);
f494e8fa
AV		 1013 /* if the result for this queue would decrease interrupt
1014 * rate for this vector then use that result */
30efa5a3 1015 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1016 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1017 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1018 r_idx + 1);
f494e8fa
AV		 1019 }
1020
30efa5a3 1021 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1022
1023 switch (current_itr) {
1024 /* counts and packets in update_itr are dependent on these numbers */
1025 case lowest_latency:
1026 new_itr = 100000;
1027 break;
1028 case low_latency:
1029 new_itr = 20000; /* aka hwitr = ~200 */
1030 break;
1031 case bulk_latency:
1032 default:
1033 new_itr = 8000;
1034 break;
1035 }
1036
1037 if (new_itr != q_vector->eitr) {
1038 u32 itr_reg;
509ee935
JB		 1039
1040 /* save the algorithm value here, not the smoothed one */
1041 q_vector->eitr = new_itr;
f494e8fa
AV		 1042 /* do an exponential smoothing */
1043 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
f494e8fa 1044 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
509ee935 1045 ixgbe_write_eitr(adapter, v_idx, itr_reg);
f494e8fa
AV		 1046 }
1047
1048 return;
1049}
1050
0befdb3e
JB		 1051static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1052{
1053 struct ixgbe_hw *hw = &adapter->hw;
1054
1055 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1056 (eicr & IXGBE_EICR_GPI_SDP1)) {
1057 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1058 /* write to clear the interrupt */
1059 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1060 }
1061}
cf8280ee 1062
e8e26350
PW		 1063static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1064{
1065 struct ixgbe_hw *hw = &adapter->hw;
1066
1067 if (eicr & IXGBE_EICR_GPI_SDP1) {
1068 /* Clear the interrupt */
1069 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1070 schedule_work(&adapter->multispeed_fiber_task);
1071 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1072 /* Clear the interrupt */
1073 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1074 schedule_work(&adapter->sfp_config_module_task);
1075 } else {
1076 /* Interrupt isn't for us... */
1077 return;
1078 }
1079}
1080
cf8280ee
JB		 1081static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1082{
1083 struct ixgbe_hw *hw = &adapter->hw;
1084
1085 adapter->lsc_int++;
1086 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1087 adapter->link_check_timeout = jiffies;
1088 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1089 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1090 schedule_work(&adapter->watchdog_task);
1091 }
1092}
1093
9a799d71
AK		 1094static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1095{
1096 struct net_device *netdev = data;
1097 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1098 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1099 u32 eicr;
1100
1101 /*
1102 * Workaround for Silicon errata. Use clear-by-write instead
1103 * of clear-by-read. Reading with EICS will return the
1104 * interrupt causes without clearing, which later be done
1105 * with the write to EICR.
1106 */
1107 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1108 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1109
cf8280ee
JB		 1110 if (eicr & IXGBE_EICR_LSC)
1111 ixgbe_check_lsc(adapter);
d4f80882 1112
e8e26350
PW		 1113 if (hw->mac.type == ixgbe_mac_82598EB)
1114 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1115
e8e26350
PW		 1116 if (hw->mac.type == ixgbe_mac_82599EB)
1117 ixgbe_check_sfp_event(adapter, eicr);
d4f80882
AV		 1118 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1119 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1120
1121 return IRQ_HANDLED;
1122}
1123
1124static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1125{
021230d4
AV		 1126 struct ixgbe_q_vector *q_vector = data;
1127 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1128 struct ixgbe_ring *tx_ring;
021230d4
AV		 1129 int i, r_idx;
1130
1131 if (!q_vector->txr_count)
1132 return IRQ_HANDLED;
1133
1134 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1135 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 1136 tx_ring = &(adapter->tx_ring[r_idx]);
5dd2d332 1137#ifdef CONFIG_IXGBE_DCA
bd0362dd 1138 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1139 ixgbe_update_tx_dca(adapter, tx_ring);
bd0362dd 1140#endif
3a581073
JB		 1141 tx_ring->total_bytes = 0;
1142 tx_ring->total_packets = 0;
1143 ixgbe_clean_tx_irq(adapter, tx_ring);
021230d4 1144 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1145 r_idx + 1);
021230d4 1146 }
9a799d71 1147
9a799d71
AK		 1148 return IRQ_HANDLED;
1149}
1150
021230d4
AV		 1151/**
1152 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1153 * @irq: unused
1154 * @data: pointer to our q_vector struct for this interrupt vector
1155 **/
9a799d71
AK		 1156static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1157{
021230d4
AV		 1158 struct ixgbe_q_vector *q_vector = data;
1159 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1160 struct ixgbe_ring *rx_ring;
021230d4 1161 int r_idx;
30efa5a3 1162 int i;
021230d4
AV		 1163
1164 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 1165 for (i = 0; i < q_vector->rxr_count; i++) {
1166 rx_ring = &(adapter->rx_ring[r_idx]);
1167 rx_ring->total_bytes = 0;
1168 rx_ring->total_packets = 0;
1169 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1170 r_idx + 1);
1171 }
1172
021230d4
AV		 1173 if (!q_vector->rxr_count)
1174 return IRQ_HANDLED;
1175
30efa5a3 1176 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1177 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 1178 /* disable interrupts on this vector only */
835462fc
NS		 1179 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1180 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
1181 else if (rx_ring->v_idx & 0xFFFFFFFF)
1182 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), rx_ring->v_idx);
1183 else
1184 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1),
1185 (rx_ring->v_idx >> 32));
288379f0 1186 napi_schedule(&q_vector->napi);
021230d4
AV		 1187
1188 return IRQ_HANDLED;
1189}
1190
1191static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1192{
1193 ixgbe_msix_clean_rx(irq, data);
1194 ixgbe_msix_clean_tx(irq, data);
9a799d71 1195
9a799d71
AK		 1196 return IRQ_HANDLED;
1197}
1198
835462fc
NS		 1199static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1200 u64 qmask)
1201{
1202 u32 mask;
1203
1204 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1205 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1206 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1207 } else {
1208 mask = (qmask & 0xFFFFFFFF);
1209 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1210 mask = (qmask >> 32);
1211 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1212 }
1213 /* skip the flush */
1214}
1215
021230d4
AV		 1216/**
1217 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1218 * @napi: napi struct with our devices info in it
1219 * @budget: amount of work driver is allowed to do this pass, in packets
1220 *
f0848276
JB		 1221 * This function is optimized for cleaning one queue only on a single
1222 * q_vector!!!
021230d4 1223 **/
9a799d71
AK		 1224static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1225{
021230d4 1226 struct ixgbe_q_vector *q_vector =
b4617240 1227 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1228 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1229 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1230 int work_done = 0;
021230d4 1231 long r_idx;
9a799d71 1232
021230d4 1233 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1234 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1235#ifdef CONFIG_IXGBE_DCA
bd0362dd 1236 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1237 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1238#endif
9a799d71 1239
78b6f4ce 1240 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1241
021230d4
AV		 1242 /* If all Rx work done, exit the polling mode */
1243 if (work_done < budget) {
288379f0 1244 napi_complete(napi);
509ee935 1245 if (adapter->itr_setting & 1)
f494e8fa 1246 ixgbe_set_itr_msix(q_vector);
9a799d71 1247 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 1248 ixgbe_irq_enable_queues(adapter, rx_ring->v_idx);
9a799d71
AK		 1249 }
1250
1251 return work_done;
1252}
1253
f0848276
JB		 1254/**
1255 * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1256 * @napi: napi struct with our devices info in it
1257 * @budget: amount of work driver is allowed to do this pass, in packets
1258 *
1259 * This function will clean more than one rx queue associated with a
1260 * q_vector.
1261 **/
1262static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1263{
1264 struct ixgbe_q_vector *q_vector =
1265 container_of(napi, struct ixgbe_q_vector, napi);
1266 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276
JB		 1267 struct ixgbe_ring *rx_ring = NULL;
1268 int work_done = 0, i;
1269 long r_idx;
835462fc 1270 u64 enable_mask = 0;
f0848276
JB		 1271
1272 /* attempt to distribute budget to each queue fairly, but don't allow
1273 * the budget to go below 1 because we'll exit polling */
1274 budget /= (q_vector->rxr_count ?: 1);
1275 budget = max(budget, 1);
1276 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1277 for (i = 0; i < q_vector->rxr_count; i++) {
1278 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1279#ifdef CONFIG_IXGBE_DCA
f0848276
JB		 1280 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1281 ixgbe_update_rx_dca(adapter, rx_ring);
1282#endif
78b6f4ce 1283 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
f0848276
JB		 1284 enable_mask |= rx_ring->v_idx;
1285 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1286 r_idx + 1);
1287 }
1288
1289 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1290 rx_ring = &(adapter->rx_ring[r_idx]);
1291 /* If all Rx work done, exit the polling mode */
7f821875 1292 if (work_done < budget) {
288379f0 1293 napi_complete(napi);
509ee935 1294 if (adapter->itr_setting & 1)
f0848276
JB		 1295 ixgbe_set_itr_msix(q_vector);
1296 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 1297 ixgbe_irq_enable_queues(adapter, enable_mask);
f0848276
JB		 1298 return 0;
1299 }
1300
1301 return work_done;
1302}
021230d4 1303static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1304 int r_idx)
021230d4 1305{
7a921c93
AD		 1306 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1307
1308 set_bit(r_idx, q_vector->rxr_idx);
1309 q_vector->rxr_count++;
021230d4
AV		 1310 a->rx_ring[r_idx].v_idx = 1 << v_idx;
1311}
1312
1313static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 1314 int t_idx)
021230d4 1315{
7a921c93
AD		 1316 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1317
1318 set_bit(t_idx, q_vector->txr_idx);
1319 q_vector->txr_count++;
1320 a->tx_ring[t_idx].v_idx = 1 << v_idx;
021230d4
AV		 1321}
1322
9a799d71 1323/**
021230d4
AV		 1324 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1325 * @adapter: board private structure to initialize
1326 * @vectors: allotted vector count for descriptor rings
9a799d71 1327 *
021230d4
AV		 1328 * This function maps descriptor rings to the queue-specific vectors
1329 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1330 * one vector per ring/queue, but on a constrained vector budget, we
1331 * group the rings as "efficiently" as possible. You would add new
1332 * mapping configurations in here.
9a799d71 1333 **/
021230d4 1334static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1335 int vectors)
021230d4
AV		 1336{
1337 int v_start = 0;
1338 int rxr_idx = 0, txr_idx = 0;
1339 int rxr_remaining = adapter->num_rx_queues;
1340 int txr_remaining = adapter->num_tx_queues;
1341 int i, j;
1342 int rqpv, tqpv;
1343 int err = 0;
1344
1345 /* No mapping required if MSI-X is disabled. */
1346 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1347 goto out;
9a799d71 1348
021230d4
AV		 1349 /*
1350 * The ideal configuration...
1351 * We have enough vectors to map one per queue.
1352 */
1353 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1354 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1355 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1356
021230d4
AV		 1357 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1358 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1359
9a799d71 1360 goto out;
021230d4 1361 }
9a799d71 1362
021230d4
AV		 1363 /*
1364 * If we don't have enough vectors for a 1-to-1
1365 * mapping, we'll have to group them so there are
1366 * multiple queues per vector.
1367 */
1368 /* Re-adjusting *qpv takes care of the remainder. */
1369 for (i = v_start; i < vectors; i++) {
1370 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1371 for (j = 0; j < rqpv; j++) {
1372 map_vector_to_rxq(adapter, i, rxr_idx);
1373 rxr_idx++;
1374 rxr_remaining--;
1375 }
1376 }
1377 for (i = v_start; i < vectors; i++) {
1378 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1379 for (j = 0; j < tqpv; j++) {
1380 map_vector_to_txq(adapter, i, txr_idx);
1381 txr_idx++;
1382 txr_remaining--;
9a799d71 1383 }
9a799d71
AK		 1384 }
1385
021230d4
AV		 1386out:
1387 return err;
1388}
1389
1390/**
1391 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1392 * @adapter: board private structure
1393 *
1394 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1395 * interrupts from the kernel.
1396 **/
1397static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1398{
1399 struct net_device *netdev = adapter->netdev;
1400 irqreturn_t (*handler)(int, void *);
1401 int i, vector, q_vectors, err;
cb13fc20 1402 int ri=0, ti=0;
021230d4
AV		 1403
1404 /* Decrement for Other and TCP Timer vectors */
1405 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1406
1407 /* Map the Tx/Rx rings to the vectors we were allotted. */
1408 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1409 if (err)
1410 goto out;
1411
1412#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1413 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1414 &ixgbe_msix_clean_many)
021230d4 1415 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 1416 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 1417
1418 if(handler == &ixgbe_msix_clean_rx) {
1419 sprintf(adapter->name[vector], "%s-%s-%d",
1420 netdev->name, "rx", ri++);
1421 }
1422 else if(handler == &ixgbe_msix_clean_tx) {
1423 sprintf(adapter->name[vector], "%s-%s-%d",
1424 netdev->name, "tx", ti++);
1425 }
1426 else
1427 sprintf(adapter->name[vector], "%s-%s-%d",
1428 netdev->name, "TxRx", vector);
1429
021230d4 1430 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1431 handler, 0, adapter->name[vector],
7a921c93 1432 adapter->q_vector[vector]);
9a799d71
AK		 1433 if (err) {
1434 DPRINTK(PROBE, ERR,
b4617240
PW		 1435 "request_irq failed for MSIX interrupt "
1436 "Error: %d\n", err);
021230d4 1437 goto free_queue_irqs;
9a799d71 1438 }
9a799d71
AK		 1439 }
1440
021230d4
AV		 1441 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1442 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1443 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1444 if (err) {
1445 DPRINTK(PROBE, ERR,
1446 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1447 goto free_queue_irqs;
9a799d71
AK		 1448 }
1449
9a799d71
AK		 1450 return 0;
1451
021230d4
AV		 1452free_queue_irqs:
1453 for (i = vector - 1; i >= 0; i--)
1454 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 1455 adapter->q_vector[i]);
021230d4
AV		 1456 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1457 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1458 kfree(adapter->msix_entries);
1459 adapter->msix_entries = NULL;
021230d4 1460out:
9a799d71
AK		 1461 return err;
1462}
1463
f494e8fa
AV		 1464static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1465{
7a921c93 1466 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 1467 u8 current_itr;
1468 u32 new_itr = q_vector->eitr;
1469 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1470 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1471
30efa5a3 1472 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1473 q_vector->tx_itr,
1474 tx_ring->total_packets,
1475 tx_ring->total_bytes);
30efa5a3 1476 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1477 q_vector->rx_itr,
1478 rx_ring->total_packets,
1479 rx_ring->total_bytes);
f494e8fa 1480
30efa5a3 1481 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1482
1483 switch (current_itr) {
1484 /* counts and packets in update_itr are dependent on these numbers */
1485 case lowest_latency:
1486 new_itr = 100000;
1487 break;
1488 case low_latency:
1489 new_itr = 20000; /* aka hwitr = ~200 */
1490 break;
1491 case bulk_latency:
1492 new_itr = 8000;
1493 break;
1494 default:
1495 break;
1496 }
1497
1498 if (new_itr != q_vector->eitr) {
1499 u32 itr_reg;
509ee935
JB		 1500
1501 /* save the algorithm value here, not the smoothed one */
1502 q_vector->eitr = new_itr;
f494e8fa
AV		 1503 /* do an exponential smoothing */
1504 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
f494e8fa 1505 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
509ee935 1506 ixgbe_write_eitr(adapter, 0, itr_reg);
f494e8fa
AV		 1507 }
1508
1509 return;
1510}
1511
79aefa45
AD		 1512/**
1513 * ixgbe_irq_enable - Enable default interrupt generation settings
1514 * @adapter: board private structure
1515 **/
1516static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1517{
1518 u32 mask;
835462fc
NS		 1519
1520 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 1521 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1522 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1523 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1524 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1525 mask |= IXGBE_EIMS_GPI_SDP1;
1526 mask |= IXGBE_EIMS_GPI_SDP2;
1527 }
1528
79aefa45 1529 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 1530 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45
AD		 1531 IXGBE_WRITE_FLUSH(&adapter->hw);
1532}
021230d4 1533
9a799d71 1534/**
021230d4 1535 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1536 * @irq: interrupt number
1537 * @data: pointer to a network interface device structure
9a799d71
AK		 1538 **/
1539static irqreturn_t ixgbe_intr(int irq, void *data)
1540{
1541 struct net_device *netdev = data;
1542 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1543 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 1544 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 1545 u32 eicr;
1546
54037505
DS		 1547 /*
1548 * Workaround for silicon errata. Mask the interrupts
1549 * before the read of EICR.
1550 */
1551 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1552
021230d4
AV		 1553 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1554 * therefore no explict interrupt disable is necessary */
1555 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1556 if (!eicr) {
1557 /* shared interrupt alert!
1558 * make sure interrupts are enabled because the read will
1559 * have disabled interrupts due to EIAM */
1560 ixgbe_irq_enable(adapter);
9a799d71 1561 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1562 }
9a799d71 1563
cf8280ee
JB		 1564 if (eicr & IXGBE_EICR_LSC)
1565 ixgbe_check_lsc(adapter);
021230d4 1566
e8e26350
PW		 1567 if (hw->mac.type == ixgbe_mac_82599EB)
1568 ixgbe_check_sfp_event(adapter, eicr);
1569
0befdb3e
JB		 1570 ixgbe_check_fan_failure(adapter, eicr);
1571
7a921c93 1572 if (napi_schedule_prep(&(q_vector->napi))) {
f494e8fa
AV		 1573 adapter->tx_ring[0].total_packets = 0;
1574 adapter->tx_ring[0].total_bytes = 0;
1575 adapter->rx_ring[0].total_packets = 0;
1576 adapter->rx_ring[0].total_bytes = 0;
021230d4 1577 /* would disable interrupts here but EIAM disabled it */
7a921c93 1578 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 1579 }
1580
1581 return IRQ_HANDLED;
1582}
1583
021230d4
AV		 1584static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1585{
1586 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1587
1588 for (i = 0; i < q_vectors; i++) {
7a921c93 1589 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 1590 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1591 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1592 q_vector->rxr_count = 0;
1593 q_vector->txr_count = 0;
1594 }
1595}
1596
9a799d71
AK		 1597/**
1598 * ixgbe_request_irq - initialize interrupts
1599 * @adapter: board private structure
1600 *
1601 * Attempts to configure interrupts using the best available
1602 * capabilities of the hardware and kernel.
1603 **/
021230d4 1604static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1605{
1606 struct net_device *netdev = adapter->netdev;
021230d4 1607 int err;
9a799d71 1608
021230d4
AV		 1609 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1610 err = ixgbe_request_msix_irqs(adapter);
1611 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1612 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
b4617240 1613 netdev->name, netdev);
021230d4
AV		 1614 } else {
1615 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
b4617240 1616 netdev->name, netdev);
9a799d71
AK		 1617 }
1618
9a799d71
AK		 1619 if (err)
1620 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1621
9a799d71
AK		 1622 return err;
1623}
1624
1625static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1626{
1627 struct net_device *netdev = adapter->netdev;
1628
1629 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1630 int i, q_vectors;
9a799d71 1631
021230d4
AV		 1632 q_vectors = adapter->num_msix_vectors;
1633
1634 i = q_vectors - 1;
9a799d71 1635 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1636
021230d4
AV		 1637 i--;
1638 for (; i >= 0; i--) {
1639 free_irq(adapter->msix_entries[i].vector,
7a921c93 1640 adapter->q_vector[i]);
021230d4
AV		 1641 }
1642
1643 ixgbe_reset_q_vectors(adapter);
1644 } else {
1645 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1646 }
1647}
1648
22d5a71b
JB		 1649/**
1650 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1651 * @adapter: board private structure
1652 **/
1653static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1654{
835462fc
NS		 1655 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1656 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1657 } else {
1658 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1659 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 1660 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
22d5a71b
JB		 1661 }
1662 IXGBE_WRITE_FLUSH(&adapter->hw);
1663 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1664 int i;
1665 for (i = 0; i < adapter->num_msix_vectors; i++)
1666 synchronize_irq(adapter->msix_entries[i].vector);
1667 } else {
1668 synchronize_irq(adapter->pdev->irq);
1669 }
1670}
1671
9a799d71
AK		 1672/**
1673 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1674 *
1675 **/
1676static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1677{
9a799d71
AK		 1678 struct ixgbe_hw *hw = &adapter->hw;
1679
021230d4 1680 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
30efa5a3 1681 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
9a799d71 1682
e8e26350
PW		 1683 ixgbe_set_ivar(adapter, 0, 0, 0);
1684 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 1685
1686 map_vector_to_rxq(adapter, 0, 0);
1687 map_vector_to_txq(adapter, 0, 0);
1688
1689 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1690}
1691
1692/**
3a581073 1693 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1694 * @adapter: board private structure
1695 *
1696 * Configure the Tx unit of the MAC after a reset.
1697 **/
1698static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1699{
12207e49 1700 u64 tdba;
9a799d71 1701 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1702 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1703
1704 /* Setup the HW Tx Head and Tail descriptor pointers */
1705 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1706 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1707 j = ring->reg_idx;
1708 tdba = ring->dma;
1709 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1710 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 1711 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 1712 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1713 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1714 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1715 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1716 adapter->tx_ring[i].head = IXGBE_TDH(j);
1717 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1718 /* Disable Tx Head Writeback RO bit, since this hoses
1719 * bookkeeping if things aren't delivered in order.
1720 */
e01c31a5 1721 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1722 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1723 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1724 }
e8e26350
PW		 1725 if (hw->mac.type == ixgbe_mac_82599EB) {
1726 /* We enable 8 traffic classes, DCB only */
1727 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1728 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1729 IXGBE_MTQC_8TC_8TQ));
1730 }
9a799d71
AK		 1731}
1732
e8e26350 1733#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c
JB		 1734
1735static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1736{
1737 struct ixgbe_ring *rx_ring;
1738 u32 srrctl;
e8e26350 1739 int queue0 = 0;
3be1adfb
AD		 1740 unsigned long mask;
1741
e8e26350 1742 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
163de42e
AD		 1743 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1744 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
1745 if (dcb_i == 8)
1746 queue0 = index >> 4;
1747 else if (dcb_i == 4)
1748 queue0 = index >> 5;
1749 else
1750 dev_err(&adapter->pdev->dev, "Invalid DCB "
1751 "configuration\n");
1752 } else {
1753 queue0 = index;
1754 }
cc41ac7c 1755 } else {
3be1adfb
AD		 1756 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1757 queue0 = index & mask;
1758 index = index & mask;
cc41ac7c 1759 }
3be1adfb 1760
cc41ac7c
JB		 1761 rx_ring = &adapter->rx_ring[queue0];
1762
1763 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1764
1765 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1766 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1767
afafd5b0
AD		 1768 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1769 IXGBE_SRRCTL_BSIZEHDR_MASK;
1770
cc41ac7c 1771 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
afafd5b0
AD		 1772#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1773 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1774#else
1775 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1776#endif
cc41ac7c 1777 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 1778 } else {
afafd5b0
AD		 1779 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1780 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 1781 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 1782 }
e8e26350 1783
cc41ac7c
JB		 1784 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1785}
9a799d71 1786
9a799d71 1787/**
3a581073 1788 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1789 * @adapter: board private structure
1790 *
1791 * Configure the Rx unit of the MAC after a reset.
1792 **/
1793static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1794{
1795 u64 rdba;
1796 struct ixgbe_hw *hw = &adapter->hw;
1797 struct net_device *netdev = adapter->netdev;
1798 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1799 int i, j;
9a799d71 1800 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1801 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1802 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1803 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1804 u32 fctrl, hlreg0;
509ee935 1805 u32 reta = 0, mrqc = 0;
cc41ac7c 1806 u32 rdrxctl;
f8212f97 1807 u32 rscctrl;
7c6e0a43 1808 int rx_buf_len;
9a799d71
AK		 1809
1810 /* Decide whether to use packet split mode or not */
762f4c57 1811 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 1812
1813 /* Set the RX buffer length according to the mode */
1814 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 1815 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 1816 if (hw->mac.type == ixgbe_mac_82599EB) {
1817 /* PSRTYPE must be initialized in 82599 */
1818 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
1819 IXGBE_PSRTYPE_UDPHDR |
1820 IXGBE_PSRTYPE_IPV4HDR |
dfa12f05
YZ		 1821 IXGBE_PSRTYPE_IPV6HDR |
1822 IXGBE_PSRTYPE_L2HDR;
e8e26350
PW		 1823 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
1824 }
9a799d71 1825 } else {
f8212f97
AD		 1826 if (!(adapter->flags & IXGBE_FLAG_RSC_ENABLED) &&
1827 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 1828 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 1829 else
7c6e0a43 1830 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 1831 }
1832
1833 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1834 fctrl |= IXGBE_FCTRL_BAM;
021230d4 1835 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 1836 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 1837 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1838
1839 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1840 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1841 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1842 else
1843 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1844 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1845
9a799d71
AK		 1846 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1847 /* disable receives while setting up the descriptors */
1848 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1849 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1850
1851 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1852 * the Base and Length of the Rx Descriptor Ring */
1853 for (i = 0; i < adapter->num_rx_queues; i++) {
1854 rdba = adapter->rx_ring[i].dma;
7c6e0a43 1855 j = adapter->rx_ring[i].reg_idx;
284901a9 1856 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 1857 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1858 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1859 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1860 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1861 adapter->rx_ring[i].head = IXGBE_RDH(j);
1862 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1863 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
cc41ac7c
JB		 1864
1865 ixgbe_configure_srrctl(adapter, j);
9a799d71
AK		 1866 }
1867
e8e26350
PW		 1868 if (hw->mac.type == ixgbe_mac_82598EB) {
1869 /*
1870 * For VMDq support of different descriptor types or
1871 * buffer sizes through the use of multiple SRRCTL
1872 * registers, RDRXCTL.MVMEN must be set to 1
1873 *
1874 * also, the manual doesn't mention it clearly but DCA hints
1875 * will only use queue 0's tags unless this bit is set. Side
1876 * effects of setting this bit are only that SRRCTL must be
1877 * fully programmed [0..15]
1878 */
2a41ff81
JB		 1879 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1880 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1881 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 1882 }
177db6ff 1883
e8e26350
PW		 1884 /* Program MRQC for the distribution of queues */
1885 if (hw->mac.type == ixgbe_mac_82599EB) {
1886 int mask = adapter->flags & (
1887 IXGBE_FLAG_RSS_ENABLED
1888 | IXGBE_FLAG_DCB_ENABLED
1889 );
1890
1891 switch (mask) {
1892 case (IXGBE_FLAG_RSS_ENABLED):
1893 mrqc = IXGBE_MRQC_RSSEN;
1894 break;
1895 case (IXGBE_FLAG_DCB_ENABLED):
1896 mrqc = IXGBE_MRQC_RT8TCEN;
1897 break;
1898 default:
1899 break;
1900 }
1901 }
021230d4 1902 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 1903 /* Fill out redirection table */
021230d4
AV		 1904 for (i = 0, j = 0; i < 128; i++, j++) {
1905 if (j == adapter->ring_feature[RING_F_RSS].indices)
1906 j = 0;
1907 /* reta = 4-byte sliding window of
1908 * 0x00..(indices-1)(indices-1)00..etc. */
1909 reta = (reta << 8) | (j * 0x11);
1910 if ((i & 3) == 3)
1911 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 1912 }
1913
1914 /* Fill out hash function seeds */
1915 for (i = 0; i < 10; i++)
7c6e0a43 1916 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 1917
2a41ff81
JB		 1918 if (hw->mac.type == ixgbe_mac_82598EB)
1919 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 1920 /* Perform hash on these packet types */
2a41ff81
JB		 1921 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
1922 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1923 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1924 | IXGBE_MRQC_RSS_FIELD_IPV6
1925 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1926 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 1927 }
2a41ff81 1928 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 1929
021230d4
AV		 1930 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1931
1932 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1933 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1934 /* Disable indicating checksum in descriptor, enables
1935 * RSS hash */
9a799d71 1936 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 1937 }
021230d4
AV		 1938 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1939 /* Enable IPv4 payload checksum for UDP fragments
1940 * if PCSD is not set */
1941 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1942 }
1943
1944 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 1945
1946 if (hw->mac.type == ixgbe_mac_82599EB) {
1947 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1948 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 1949 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 1950 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1951 }
f8212f97
AD		 1952
1953 if (adapter->flags & IXGBE_FLAG_RSC_ENABLED) {
1954 /* Enable 82599 HW-RSC */
1955 for (i = 0; i < adapter->num_rx_queues; i++) {
1956 j = adapter->rx_ring[i].reg_idx;
1957 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
1958 rscctrl |= IXGBE_RSCCTL_RSCEN;
1959 /*
1960 * if packet split is enabled we can only support up
1961 * to max frags + 1 descriptors.
1962 */
1963 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
1964#if (MAX_SKB_FRAGS < 3)
1965 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
1966#elif (MAX_SKB_FRAGS < 7)
1967 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
1968#elif (MAX_SKB_FRAGS < 15)
1969 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
1970#else
1971 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
1972#endif
1973 else
1974 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
1975 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
1976 }
1977 /* Disable RSC for ACK packets */
1978 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
1979 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
1980 }
9a799d71
AK		 1981}
1982
068c89b0
DS		 1983static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1984{
1985 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1986 struct ixgbe_hw *hw = &adapter->hw;
1987
1988 /* add VID to filter table */
1989 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
1990}
1991
1992static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1993{
1994 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1995 struct ixgbe_hw *hw = &adapter->hw;
1996
1997 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1998 ixgbe_irq_disable(adapter);
1999
2000 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2001
2002 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2003 ixgbe_irq_enable(adapter);
2004
2005 /* remove VID from filter table */
2006 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2007}
2008
9a799d71 2009static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2010 struct vlan_group *grp)
9a799d71
AK		 2011{
2012 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2013 u32 ctrl;
e8e26350 2014 int i, j;
9a799d71 2015
d4f80882
AV		 2016 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2017 ixgbe_irq_disable(adapter);
9a799d71
AK		 2018 adapter->vlgrp = grp;
2019
2f90b865
AD		 2020 /*
2021 * For a DCB driver, always enable VLAN tag stripping so we can
2022 * still receive traffic from a DCB-enabled host even if we're
2023 * not in DCB mode.
2024 */
2025 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
e8e26350
PW		 2026 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2027 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2028 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2029 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2030 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2031 ctrl |= IXGBE_VLNCTRL_VFE;
9a799d71
AK		 2032 /* enable VLAN tag insert/strip */
2033 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
9a799d71
AK		 2034 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2035 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
e8e26350
PW		 2036 for (i = 0; i < adapter->num_rx_queues; i++) {
2037 j = adapter->rx_ring[i].reg_idx;
2038 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2039 ctrl |= IXGBE_RXDCTL_VME;
2040 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2041 }
9a799d71 2042 }
e8e26350 2043 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2044
d4f80882
AV		 2045 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2046 ixgbe_irq_enable(adapter);
9a799d71
AK		 2047}
2048
9a799d71
AK		 2049static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2050{
2051 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2052
2053 if (adapter->vlgrp) {
2054 u16 vid;
2055 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2056 if (!vlan_group_get_device(adapter->vlgrp, vid))
2057 continue;
2058 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2059 }
2060 }
2061}
2062
2c5645cf
CL		 2063static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2064{
2065 struct dev_mc_list *mc_ptr;
2066 u8 *addr = *mc_addr_ptr;
2067 *vmdq = 0;
2068
2069 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2070 if (mc_ptr->next)
2071 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2072 else
2073 *mc_addr_ptr = NULL;
2074
2075 return addr;
2076}
2077
9a799d71 2078/**
2c5645cf 2079 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2080 * @netdev: network interface device structure
2081 *
2c5645cf
CL		 2082 * The set_rx_method entry point is called whenever the unicast/multicast
2083 * address list or the network interface flags are updated. This routine is
2084 * responsible for configuring the hardware for proper unicast, multicast and
2085 * promiscuous mode.
9a799d71 2086 **/
2c5645cf 2087static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2088{
2089 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2090 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 2091 u32 fctrl, vlnctrl;
2c5645cf
CL		 2092 u8 *addr_list = NULL;
2093 int addr_count = 0;
9a799d71
AK		 2094
2095 /* Check for Promiscuous and All Multicast modes */
2096
2097 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 2098 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 2099
2100 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2101 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2102 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 2103 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 2104 } else {
746b9f02
PM		 2105 if (netdev->flags & IFF_ALLMULTI) {
2106 fctrl |= IXGBE_FCTRL_MPE;
2107 fctrl &= ~IXGBE_FCTRL_UPE;
2108 } else {
2109 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2110 }
3d01625a 2111 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 2112 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2113 }
2114
2115 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 2116 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 2117
2c5645cf
CL		 2118 /* reprogram secondary unicast list */
2119 addr_count = netdev->uc_count;
2120 if (addr_count)
2121 addr_list = netdev->uc_list->dmi_addr;
c44ade9e
JB		 2122 hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
2123 ixgbe_addr_list_itr);
9a799d71 2124
2c5645cf
CL		 2125 /* reprogram multicast list */
2126 addr_count = netdev->mc_count;
2127 if (addr_count)
2128 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 2129 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2130 ixgbe_addr_list_itr);
9a799d71
AK		 2131}
2132
021230d4
AV		 2133static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2134{
2135 int q_idx;
2136 struct ixgbe_q_vector *q_vector;
2137 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2138
2139 /* legacy and MSI only use one vector */
2140 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2141 q_vectors = 1;
2142
2143 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2144 struct napi_struct *napi;
7a921c93 2145 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2146 if (!q_vector->rxr_count)
2147 continue;
f0848276
JB		 2148 napi = &q_vector->napi;
2149 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
2150 (q_vector->rxr_count > 1))
2151 napi->poll = &ixgbe_clean_rxonly_many;
2152
2153 napi_enable(napi);
021230d4
AV		 2154 }
2155}
2156
2157static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2158{
2159 int q_idx;
2160 struct ixgbe_q_vector *q_vector;
2161 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2162
2163 /* legacy and MSI only use one vector */
2164 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2165 q_vectors = 1;
2166
2167 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 2168 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2169 if (!q_vector->rxr_count)
2170 continue;
2171 napi_disable(&q_vector->napi);
2172 }
2173}
2174
7a6b6f51 2175#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2176/*
2177 * ixgbe_configure_dcb - Configure DCB hardware
2178 * @adapter: ixgbe adapter struct
2179 *
2180 * This is called by the driver on open to configure the DCB hardware.
2181 * This is also called by the gennetlink interface when reconfiguring
2182 * the DCB state.
2183 */
2184static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2185{
2186 struct ixgbe_hw *hw = &adapter->hw;
2187 u32 txdctl, vlnctrl;
2188 int i, j;
2189
2190 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2191 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2192 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2193
2194 /* reconfigure the hardware */
2195 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2196
2197 for (i = 0; i < adapter->num_tx_queues; i++) {
2198 j = adapter->tx_ring[i].reg_idx;
2199 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2200 /* PThresh workaround for Tx hang with DFP enabled. */
2201 txdctl |= 32;
2202 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2203 }
2204 /* Enable VLAN tag insert/strip */
2205 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
e8e26350
PW		 2206 if (hw->mac.type == ixgbe_mac_82598EB) {
2207 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2208 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2209 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2210 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2211 vlnctrl |= IXGBE_VLNCTRL_VFE;
2212 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2213 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2214 for (i = 0; i < adapter->num_rx_queues; i++) {
2215 j = adapter->rx_ring[i].reg_idx;
2216 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2217 vlnctrl |= IXGBE_RXDCTL_VME;
2218 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2219 }
2220 }
2f90b865
AD		 2221 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2222}
2223
2224#endif
9a799d71
AK		 2225static void ixgbe_configure(struct ixgbe_adapter *adapter)
2226{
2227 struct net_device *netdev = adapter->netdev;
2228 int i;
2229
2c5645cf 2230 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2231
2232 ixgbe_restore_vlan(adapter);
7a6b6f51 2233#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2234 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2235 netif_set_gso_max_size(netdev, 32768);
2236 ixgbe_configure_dcb(adapter);
2237 } else {
2238 netif_set_gso_max_size(netdev, 65536);
2239 }
2240#else
2241 netif_set_gso_max_size(netdev, 65536);
2242#endif
9a799d71
AK		 2243
2244 ixgbe_configure_tx(adapter);
2245 ixgbe_configure_rx(adapter);
2246 for (i = 0; i < adapter->num_rx_queues; i++)
2247 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 2248 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 2249}
2250
e8e26350
PW		 2251static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2252{
2253 switch (hw->phy.type) {
2254 case ixgbe_phy_sfp_avago:
2255 case ixgbe_phy_sfp_ftl:
2256 case ixgbe_phy_sfp_intel:
2257 case ixgbe_phy_sfp_unknown:
2258 case ixgbe_phy_tw_tyco:
2259 case ixgbe_phy_tw_unknown:
2260 return true;
2261 default:
2262 return false;
2263 }
2264}
2265
0ecc061d 2266/**
e8e26350
PW		 2267 * ixgbe_sfp_link_config - set up SFP+ link
2268 * @adapter: pointer to private adapter struct
2269 **/
2270static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2271{
2272 struct ixgbe_hw *hw = &adapter->hw;
2273
2274 if (hw->phy.multispeed_fiber) {
2275 /*
2276 * In multispeed fiber setups, the device may not have
2277 * had a physical connection when the driver loaded.
2278 * If that's the case, the initial link configuration
2279 * couldn't get the MAC into 10G or 1G mode, so we'll
2280 * never have a link status change interrupt fire.
2281 * We need to try and force an autonegotiation
2282 * session, then bring up link.
2283 */
2284 hw->mac.ops.setup_sfp(hw);
2285 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2286 schedule_work(&adapter->multispeed_fiber_task);
2287 } else {
2288 /*
2289 * Direct Attach Cu and non-multispeed fiber modules
2290 * still need to be configured properly prior to
2291 * attempting link.
2292 */
2293 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2294 schedule_work(&adapter->sfp_config_module_task);
2295 }
2296}
2297
2298/**
2299 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2300 * @hw: pointer to private hardware struct
2301 *
2302 * Returns 0 on success, negative on failure
2303 **/
e8e26350 2304static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2305{
2306 u32 autoneg;
2307 bool link_up = false;
2308 u32 ret = IXGBE_ERR_LINK_SETUP;
2309
2310 if (hw->mac.ops.check_link)
2311 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2312
2313 if (ret)
2314 goto link_cfg_out;
2315
2316 if (hw->mac.ops.get_link_capabilities)
2317 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2318 &hw->mac.autoneg);
2319 if (ret)
2320 goto link_cfg_out;
2321
2322 if (hw->mac.ops.setup_link_speed)
2323 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
0ecc061d
PWJ		 2324link_cfg_out:
2325 return ret;
2326}
2327
e8e26350
PW		 2328#define IXGBE_MAX_RX_DESC_POLL 10
2329static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2330 int rxr)
2331{
2332 int j = adapter->rx_ring[rxr].reg_idx;
2333 int k;
2334
2335 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2336 if (IXGBE_READ_REG(&adapter->hw,
2337 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2338 break;
2339 else
2340 msleep(1);
2341 }
2342 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2343 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2344 "not set within the polling period\n", rxr);
2345 }
2346 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2347 (adapter->rx_ring[rxr].count - 1));
2348}
2349
9a799d71
AK		 2350static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2351{
2352 struct net_device *netdev = adapter->netdev;
9a799d71 2353 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2354 int i, j = 0;
e8e26350 2355 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2356 int err;
9a799d71 2357 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2358 u32 txdctl, rxdctl, mhadd;
e8e26350 2359 u32 dmatxctl;
021230d4 2360 u32 gpie;
9a799d71 2361
5eba3699
AV		 2362 ixgbe_get_hw_control(adapter);
2363
021230d4
AV		 2364 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2365 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2366 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2367 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2368 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2369 } else {
2370 /* MSI only */
021230d4 2371 gpie = 0;
9a799d71 2372 }
021230d4
AV		 2373 /* XXX: to interrupt immediately for EICS writes, enable this */
2374 /* gpie |= IXGBE_GPIE_EIMEN; */
2375 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2376 }
2377
021230d4
AV		 2378 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2379 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2380 * specifically only auto mask tx and rx interrupts */
2381 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2382 }
9a799d71 2383
0befdb3e
JB		 2384 /* Enable fan failure interrupt if media type is copper */
2385 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2386 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2387 gpie |= IXGBE_SDP1_GPIEN;
2388 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2389 }
2390
e8e26350
PW		 2391 if (hw->mac.type == ixgbe_mac_82599EB) {
2392 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2393 gpie |= IXGBE_SDP1_GPIEN;
2394 gpie |= IXGBE_SDP2_GPIEN;
2395 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2396 }
2397
021230d4 2398 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2399 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2400 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2401 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2402
2403 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2404 }
2405
2406 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 2407 j = adapter->tx_ring[i].reg_idx;
2408 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2409 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2410 txdctl |= (8 << 16);
e8e26350
PW		 2411 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2412 }
2413
2414 if (hw->mac.type == ixgbe_mac_82599EB) {
2415 /* DMATXCTL.EN must be set after all Tx queue config is done */
2416 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2417 dmatxctl |= IXGBE_DMATXCTL_TE;
2418 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2419 }
2420 for (i = 0; i < adapter->num_tx_queues; i++) {
2421 j = adapter->tx_ring[i].reg_idx;
2422 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2423 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2424 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 2425 }
2426
e8e26350 2427 for (i = 0; i < num_rx_rings; i++) {
021230d4
AV		 2428 j = adapter->rx_ring[i].reg_idx;
2429 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2430 /* enable PTHRESH=32 descriptors (half the internal cache)
2431 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2432 * this also removes a pesky rx_no_buffer_count increment */
2433 rxdctl |= 0x0020;
9a799d71 2434 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2435 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2436 if (hw->mac.type == ixgbe_mac_82599EB)
2437 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2438 }
2439 /* enable all receives */
2440 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2441 if (hw->mac.type == ixgbe_mac_82598EB)
2442 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2443 else
2444 rxdctl |= IXGBE_RXCTRL_RXEN;
2445 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2446
2447 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2448 ixgbe_configure_msix(adapter);
2449 else
2450 ixgbe_configure_msi_and_legacy(adapter);
2451
2452 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2453 ixgbe_napi_enable_all(adapter);
2454
2455 /* clear any pending interrupts, may auto mask */
2456 IXGBE_READ_REG(hw, IXGBE_EICR);
2457
9a799d71
AK		 2458 ixgbe_irq_enable(adapter);
2459
bf069c97
DS		 2460 /*
2461 * If this adapter has a fan, check to see if we had a failure
2462 * before we enabled the interrupt.
2463 */
2464 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2465 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2466 if (esdp & IXGBE_ESDP_SDP1)
2467 DPRINTK(DRV, CRIT,
2468 "Fan has stopped, replace the adapter\n");
2469 }
2470
e8e26350
PW		 2471 /*
2472 * For hot-pluggable SFP+ devices, a new SFP+ module may have
2473 * arrived before interrupts were enabled. We need to kick off
2474 * the SFP+ module setup first, then try to bring up link.
2475 * If we're not hot-pluggable SFP+, we just need to configure link
2476 * and bring it up.
2477 */
2478 err = hw->phy.ops.identify(hw);
2479 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2480 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
2481 ixgbe_down(adapter);
2482 return err;
2483 }
2484
2485 if (ixgbe_is_sfp(hw)) {
2486 ixgbe_sfp_link_config(adapter);
2487 } else {
2488 err = ixgbe_non_sfp_link_config(hw);
2489 if (err)
2490 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2491 }
0ecc061d 2492
1da100bb
PWJ		 2493 /* enable transmits */
2494 netif_tx_start_all_queues(netdev);
2495
9a799d71
AK		 2496 /* bring the link up in the watchdog, this could race with our first
2497 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 2498 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2499 adapter->link_check_timeout = jiffies;
9a799d71
AK		 2500 mod_timer(&adapter->watchdog_timer, jiffies);
2501 return 0;
2502}
2503
d4f80882
AV		 2504void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2505{
2506 WARN_ON(in_interrupt());
2507 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2508 msleep(1);
2509 ixgbe_down(adapter);
2510 ixgbe_up(adapter);
2511 clear_bit(__IXGBE_RESETTING, &adapter->state);
2512}
2513
9a799d71
AK		 2514int ixgbe_up(struct ixgbe_adapter *adapter)
2515{
2516 /* hardware has been reset, we need to reload some things */
2517 ixgbe_configure(adapter);
2518
2519 return ixgbe_up_complete(adapter);
2520}
2521
2522void ixgbe_reset(struct ixgbe_adapter *adapter)
2523{
c44ade9e
JB		 2524 struct ixgbe_hw *hw = &adapter->hw;
2525 if (hw->mac.ops.init_hw(hw))
2526 dev_err(&adapter->pdev->dev, "Hardware Error\n");
9a799d71
AK		 2527
2528 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2529 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2530
2531}
2532
9a799d71
AK		 2533/**
2534 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2535 * @adapter: board private structure
2536 * @rx_ring: ring to free buffers from
2537 **/
2538static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2539 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2540{
2541 struct pci_dev *pdev = adapter->pdev;
2542 unsigned long size;
2543 unsigned int i;
2544
2545 /* Free all the Rx ring sk_buffs */
2546
2547 for (i = 0; i < rx_ring->count; i++) {
2548 struct ixgbe_rx_buffer *rx_buffer_info;
2549
2550 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2551 if (rx_buffer_info->dma) {
2552 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2553 rx_ring->rx_buf_len,
2554 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2555 rx_buffer_info->dma = 0;
2556 }
2557 if (rx_buffer_info->skb) {
f8212f97 2558 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 2559 rx_buffer_info->skb = NULL;
f8212f97
AD		 2560 do {
2561 struct sk_buff *this = skb;
2562 skb = skb->prev;
2563 dev_kfree_skb(this);
2564 } while (skb);
9a799d71
AK		 2565 }
2566 if (!rx_buffer_info->page)
2567 continue;
762f4c57
JB		 2568 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2569 PCI_DMA_FROMDEVICE);
9a799d71 2570 rx_buffer_info->page_dma = 0;
9a799d71
AK		 2571 put_page(rx_buffer_info->page);
2572 rx_buffer_info->page = NULL;
762f4c57 2573 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2574 }
2575
2576 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2577 memset(rx_ring->rx_buffer_info, 0, size);
2578
2579 /* Zero out the descriptor ring */
2580 memset(rx_ring->desc, 0, rx_ring->size);
2581
2582 rx_ring->next_to_clean = 0;
2583 rx_ring->next_to_use = 0;
2584
9891ca7c
JB		 2585 if (rx_ring->head)
2586 writel(0, adapter->hw.hw_addr + rx_ring->head);
2587 if (rx_ring->tail)
2588 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 2589}
2590
2591/**
2592 * ixgbe_clean_tx_ring - Free Tx Buffers
2593 * @adapter: board private structure
2594 * @tx_ring: ring to be cleaned
2595 **/
2596static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2597 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2598{
2599 struct ixgbe_tx_buffer *tx_buffer_info;
2600 unsigned long size;
2601 unsigned int i;
2602
2603 /* Free all the Tx ring sk_buffs */
2604
2605 for (i = 0; i < tx_ring->count; i++) {
2606 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2607 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2608 }
2609
2610 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2611 memset(tx_ring->tx_buffer_info, 0, size);
2612
2613 /* Zero out the descriptor ring */
2614 memset(tx_ring->desc, 0, tx_ring->size);
2615
2616 tx_ring->next_to_use = 0;
2617 tx_ring->next_to_clean = 0;
2618
9891ca7c
JB		 2619 if (tx_ring->head)
2620 writel(0, adapter->hw.hw_addr + tx_ring->head);
2621 if (tx_ring->tail)
2622 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 2623}
2624
2625/**
021230d4 2626 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2627 * @adapter: board private structure
2628 **/
021230d4 2629static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2630{
2631 int i;
2632
021230d4
AV		 2633 for (i = 0; i < adapter->num_rx_queues; i++)
2634 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2635}
2636
2637/**
021230d4 2638 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2639 * @adapter: board private structure
2640 **/
021230d4 2641static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2642{
2643 int i;
2644
021230d4
AV		 2645 for (i = 0; i < adapter->num_tx_queues; i++)
2646 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2647}
2648
2649void ixgbe_down(struct ixgbe_adapter *adapter)
2650{
2651 struct net_device *netdev = adapter->netdev;
7f821875 2652 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2653 u32 rxctrl;
7f821875
JB		 2654 u32 txdctl;
2655 int i, j;
9a799d71
AK		 2656
2657 /* signal that we are down to the interrupt handler */
2658 set_bit(__IXGBE_DOWN, &adapter->state);
2659
2660 /* disable receives */
7f821875
JB		 2661 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2662 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 2663
2664 netif_tx_disable(netdev);
2665
7f821875 2666 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 2667 msleep(10);
2668
7f821875
JB		 2669 netif_tx_stop_all_queues(netdev);
2670
9a799d71
AK		 2671 ixgbe_irq_disable(adapter);
2672
021230d4 2673 ixgbe_napi_disable_all(adapter);
7f821875 2674
9a799d71 2675 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 2676 cancel_work_sync(&adapter->watchdog_task);
9a799d71 2677
7f821875
JB		 2678 /* disable transmits in the hardware now that interrupts are off */
2679 for (i = 0; i < adapter->num_tx_queues; i++) {
2680 j = adapter->tx_ring[i].reg_idx;
2681 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2682 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2683 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2684 }
88512539
PW		 2685 /* Disable the Tx DMA engine on 82599 */
2686 if (hw->mac.type == ixgbe_mac_82599EB)
2687 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2688 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2689 ~IXGBE_DMATXCTL_TE));
7f821875 2690
9a799d71 2691 netif_carrier_off(netdev);
9a799d71 2692
5dd2d332 2693#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2694 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2695 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2696 dca_remove_requester(&adapter->pdev->dev);
2697 }
2698
2699#endif
6f4a0e45
PL		 2700 if (!pci_channel_offline(adapter->pdev))
2701 ixgbe_reset(adapter);
9a799d71
AK		 2702 ixgbe_clean_all_tx_rings(adapter);
2703 ixgbe_clean_all_rx_rings(adapter);
2704
5dd2d332 2705#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2706 /* since we reset the hardware DCA settings were cleared */
2707 if (dca_add_requester(&adapter->pdev->dev) == 0) {
2708 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2709 /* always use CB2 mode, difference is masked
2710 * in the CB driver */
b4617240 2711 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
96b0e0f6
JB		 2712 ixgbe_setup_dca(adapter);
2713 }
2714#endif
9a799d71
AK		 2715}
2716
9a799d71 2717/**
021230d4
AV		 2718 * ixgbe_poll - NAPI Rx polling callback
2719 * @napi: structure for representing this polling device
2720 * @budget: how many packets driver is allowed to clean
2721 *
2722 * This function is used for legacy and MSI, NAPI mode
9a799d71 2723 **/
021230d4 2724static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2725{
9a1a69ad
JB		 2726 struct ixgbe_q_vector *q_vector =
2727 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2728 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 2729 int tx_clean_complete, work_done = 0;
9a799d71 2730
5dd2d332 2731#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 2732 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2733 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2734 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2735 }
2736#endif
2737
9a1a69ad 2738 tx_clean_complete = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
78b6f4ce 2739 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
9a799d71 2740
9a1a69ad 2741 if (!tx_clean_complete)
d2c7ddd6
DM		 2742 work_done = budget;
2743
53e52c72
DM		 2744 /* If budget not fully consumed, exit the polling mode */
2745 if (work_done < budget) {
288379f0 2746 napi_complete(napi);
509ee935 2747 if (adapter->itr_setting & 1)
f494e8fa 2748 ixgbe_set_itr(adapter);
d4f80882 2749 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 2750 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 2751 }
9a799d71
AK		 2752 return work_done;
2753}
2754
2755/**
2756 * ixgbe_tx_timeout - Respond to a Tx Hang
2757 * @netdev: network interface device structure
2758 **/
2759static void ixgbe_tx_timeout(struct net_device *netdev)
2760{
2761 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2762
2763 /* Do the reset outside of interrupt context */
2764 schedule_work(&adapter->reset_task);
2765}
2766
2767static void ixgbe_reset_task(struct work_struct *work)
2768{
2769 struct ixgbe_adapter *adapter;
2770 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2771
2f90b865
AD		 2772 /* If we're already down or resetting, just bail */
2773 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2774 test_bit(__IXGBE_RESETTING, &adapter->state))
2775 return;
2776
9a799d71
AK		 2777 adapter->tx_timeout_count++;
2778
d4f80882 2779 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2780}
2781
bc97114d
PWJ		 2782#ifdef CONFIG_IXGBE_DCB
2783static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 2784{
bc97114d 2785 bool ret = false;
b9804972 2786
bc97114d
PWJ		 2787 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2788 adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3;
2789 adapter->num_rx_queues =
2790 adapter->ring_feature[RING_F_DCB].indices;
2791 adapter->num_tx_queues =
2792 adapter->ring_feature[RING_F_DCB].indices;
2793 ret = true;
2794 } else {
bc97114d
PWJ		 2795 ret = false;
2796 }
2f90b865 2797
bc97114d
PWJ		 2798 return ret;
2799}
2800#endif
2801
4df10466
JB		 2802/**
2803 * ixgbe_set_rss_queues: Allocate queues for RSS
2804 * @adapter: board private structure to initialize
2805 *
2806 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
2807 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
2808 *
2809 **/
bc97114d
PWJ		 2810static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
2811{
2812 bool ret = false;
2813
2814 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2815 adapter->ring_feature[RING_F_RSS].mask = 0xF;
2816 adapter->num_rx_queues =
2817 adapter->ring_feature[RING_F_RSS].indices;
2818 adapter->num_tx_queues =
2819 adapter->ring_feature[RING_F_RSS].indices;
2820 ret = true;
2821 } else {
bc97114d 2822 ret = false;
b9804972
JB		 2823 }
2824
bc97114d
PWJ		 2825 return ret;
2826}
2827
4df10466
JB		 2828/*
2829 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
2830 * @adapter: board private structure to initialize
2831 *
2832 * This is the top level queue allocation routine. The order here is very
2833 * important, starting with the "most" number of features turned on at once,
2834 * and ending with the smallest set of features. This way large combinations
2835 * can be allocated if they're turned on, and smaller combinations are the
2836 * fallthrough conditions.
2837 *
2838 **/
bc97114d
PWJ		 2839static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2840{
bc97114d
PWJ		 2841#ifdef CONFIG_IXGBE_DCB
2842 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 2843 goto done;
bc97114d
PWJ		 2844
2845#endif
2846 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 2847 goto done;
2848
2849 /* fallback to base case */
2850 adapter->num_rx_queues = 1;
2851 adapter->num_tx_queues = 1;
2852
2853done:
2854 /* Notify the stack of the (possibly) reduced Tx Queue count. */
2855 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 2856}
2857
021230d4 2858static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 2859 int vectors)
021230d4
AV		 2860{
2861 int err, vector_threshold;
2862
2863 /* We'll want at least 3 (vector_threshold):
2864 * 1) TxQ[0] Cleanup
2865 * 2) RxQ[0] Cleanup
2866 * 3) Other (Link Status Change, etc.)
2867 * 4) TCP Timer (optional)
2868 */
2869 vector_threshold = MIN_MSIX_COUNT;
2870
2871 /* The more we get, the more we will assign to Tx/Rx Cleanup
2872 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2873 * Right now, we simply care about how many we'll get; we'll
2874 * set them up later while requesting irq's.
2875 */
2876 while (vectors >= vector_threshold) {
2877 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 2878 vectors);
021230d4
AV		 2879 if (!err) /* Success in acquiring all requested vectors. */
2880 break;
2881 else if (err < 0)
2882 vectors = 0; /* Nasty failure, quit now */
2883 else /* err == number of vectors we should try again with */
2884 vectors = err;
2885 }
2886
2887 if (vectors < vector_threshold) {
2888 /* Can't allocate enough MSI-X interrupts? Oh well.
2889 * This just means we'll go with either a single MSI
2890 * vector or fall back to legacy interrupts.
2891 */
2892 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2893 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2894 kfree(adapter->msix_entries);
2895 adapter->msix_entries = NULL;
021230d4
AV		 2896 } else {
2897 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 2898 /*
2899 * Adjust for only the vectors we'll use, which is minimum
2900 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
2901 * vectors we were allocated.
2902 */
2903 adapter->num_msix_vectors = min(vectors,
2904 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 2905 }
2906}
2907
021230d4 2908/**
bc97114d 2909 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 2910 * @adapter: board private structure to initialize
2911 *
bc97114d
PWJ		 2912 * Cache the descriptor ring offsets for RSS to the assigned rings.
2913 *
021230d4 2914 **/
bc97114d 2915static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 2916{
bc97114d
PWJ		 2917 int i;
2918 bool ret = false;
2919
2920 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2921 for (i = 0; i < adapter->num_rx_queues; i++)
2922 adapter->rx_ring[i].reg_idx = i;
2923 for (i = 0; i < adapter->num_tx_queues; i++)
2924 adapter->tx_ring[i].reg_idx = i;
2925 ret = true;
2926 } else {
2927 ret = false;
2928 }
2929
2930 return ret;
2931}
2932
2933#ifdef CONFIG_IXGBE_DCB
2934/**
2935 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
2936 * @adapter: board private structure to initialize
2937 *
2938 * Cache the descriptor ring offsets for DCB to the assigned rings.
2939 *
2940 **/
2941static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
2942{
2943 int i;
2944 bool ret = false;
2945 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
2946
2947 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2948 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 2949 /* the number of queues is assumed to be symmetric */
2950 for (i = 0; i < dcb_i; i++) {
2951 adapter->rx_ring[i].reg_idx = i << 3;
2952 adapter->tx_ring[i].reg_idx = i << 2;
2953 }
bc97114d 2954 ret = true;
e8e26350 2955 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 2956 if (dcb_i == 8) {
2957 /*
2958 * Tx TC0 starts at: descriptor queue 0
2959 * Tx TC1 starts at: descriptor queue 32
2960 * Tx TC2 starts at: descriptor queue 64
2961 * Tx TC3 starts at: descriptor queue 80
2962 * Tx TC4 starts at: descriptor queue 96
2963 * Tx TC5 starts at: descriptor queue 104
2964 * Tx TC6 starts at: descriptor queue 112
2965 * Tx TC7 starts at: descriptor queue 120
2966 *
2967 * Rx TC0-TC7 are offset by 16 queues each
2968 */
2969 for (i = 0; i < 3; i++) {
2970 adapter->tx_ring[i].reg_idx = i << 5;
2971 adapter->rx_ring[i].reg_idx = i << 4;
2972 }
2973 for ( ; i < 5; i++) {
2974 adapter->tx_ring[i].reg_idx =
2975 ((i + 2) << 4);
2976 adapter->rx_ring[i].reg_idx = i << 4;
2977 }
2978 for ( ; i < dcb_i; i++) {
2979 adapter->tx_ring[i].reg_idx =
2980 ((i + 8) << 3);
2981 adapter->rx_ring[i].reg_idx = i << 4;
2982 }
2983
2984 ret = true;
2985 } else if (dcb_i == 4) {
2986 /*
2987 * Tx TC0 starts at: descriptor queue 0
2988 * Tx TC1 starts at: descriptor queue 64
2989 * Tx TC2 starts at: descriptor queue 96
2990 * Tx TC3 starts at: descriptor queue 112
2991 *
2992 * Rx TC0-TC3 are offset by 32 queues each
2993 */
2994 adapter->tx_ring[0].reg_idx = 0;
2995 adapter->tx_ring[1].reg_idx = 64;
2996 adapter->tx_ring[2].reg_idx = 96;
2997 adapter->tx_ring[3].reg_idx = 112;
2998 for (i = 0 ; i < dcb_i; i++)
2999 adapter->rx_ring[i].reg_idx = i << 5;
3000
3001 ret = true;
3002 } else {
3003 ret = false;
e8e26350 3004 }
bc97114d
PWJ		 3005 } else {
3006 ret = false;
021230d4 3007 }
bc97114d
PWJ		 3008 } else {
3009 ret = false;
021230d4 3010 }
bc97114d
PWJ		 3011
3012 return ret;
3013}
3014#endif
3015
3016/**
3017 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3018 * @adapter: board private structure to initialize
3019 *
3020 * Once we know the feature-set enabled for the device, we'll cache
3021 * the register offset the descriptor ring is assigned to.
3022 *
3023 * Note, the order the various feature calls is important. It must start with
3024 * the "most" features enabled at the same time, then trickle down to the
3025 * least amount of features turned on at once.
3026 **/
3027static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3028{
3029 /* start with default case */
3030 adapter->rx_ring[0].reg_idx = 0;
3031 adapter->tx_ring[0].reg_idx = 0;
3032
3033#ifdef CONFIG_IXGBE_DCB
3034 if (ixgbe_cache_ring_dcb(adapter))
3035 return;
3036
3037#endif
3038 if (ixgbe_cache_ring_rss(adapter))
3039 return;
021230d4
AV		 3040}
3041
9a799d71
AK		 3042/**
3043 * ixgbe_alloc_queues - Allocate memory for all rings
3044 * @adapter: board private structure to initialize
3045 *
3046 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 3047 * number of queues at compile-time. The polling_netdev array is
3048 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 3049 **/
2f90b865 3050static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 3051{
3052 int i;
3053
3054 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 3055 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 3056 if (!adapter->tx_ring)
021230d4 3057 goto err_tx_ring_allocation;
9a799d71
AK		 3058
3059 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 3060 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 3061 if (!adapter->rx_ring)
3062 goto err_rx_ring_allocation;
9a799d71 3063
021230d4 3064 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 3065 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 3066 adapter->tx_ring[i].queue_index = i;
3067 }
b9804972 3068
9a799d71 3069 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 3070 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 3071 adapter->rx_ring[i].queue_index = i;
3072 }
3073
3074 ixgbe_cache_ring_register(adapter);
3075
3076 return 0;
3077
3078err_rx_ring_allocation:
3079 kfree(adapter->tx_ring);
3080err_tx_ring_allocation:
3081 return -ENOMEM;
3082}
3083
3084/**
3085 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3086 * @adapter: board private structure to initialize
3087 *
3088 * Attempt to configure the interrupts using the best available
3089 * capabilities of the hardware and the kernel.
3090 **/
feea6a57 3091static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 3092{
8be0e467 3093 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 3094 int err = 0;
3095 int vector, v_budget;
3096
3097 /*
3098 * It's easy to be greedy for MSI-X vectors, but it really
3099 * doesn't do us much good if we have a lot more vectors
3100 * than CPU's. So let's be conservative and only ask for
3101 * (roughly) twice the number of vectors as there are CPU's.
3102 */
3103 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
b4617240 3104 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
021230d4
AV		 3105
3106 /*
3107 * At the same time, hardware can only support a maximum of
8be0e467
PW		 3108 * hw.mac->max_msix_vectors vectors. With features
3109 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3110 * descriptor queues supported by our device. Thus, we cap it off in
3111 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3112 */
8be0e467 3113 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3114
3115 /* A failure in MSI-X entry allocation isn't fatal, but it does
3116 * mean we disable MSI-X capabilities of the adapter. */
3117 adapter->msix_entries = kcalloc(v_budget,
b4617240 3118 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 3119 if (adapter->msix_entries) {
3120 for (vector = 0; vector < v_budget; vector++)
3121 adapter->msix_entries[vector].entry = vector;
021230d4 3122
7a921c93 3123 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 3124
7a921c93
AD		 3125 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3126 goto out;
3127 }
021230d4 3128
7a921c93
AD		 3129 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3130 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3131 ixgbe_set_num_queues(adapter);
021230d4 3132
021230d4
AV		 3133 err = pci_enable_msi(adapter->pdev);
3134 if (!err) {
3135 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3136 } else {
3137 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 3138 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 3139 /* reset err */
3140 err = 0;
3141 }
3142
3143out:
021230d4
AV		 3144 return err;
3145}
3146
7a921c93
AD		 3147/**
3148 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3149 * @adapter: board private structure to initialize
3150 *
3151 * We allocate one q_vector per queue interrupt. If allocation fails we
3152 * return -ENOMEM.
3153 **/
3154static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3155{
3156 int q_idx, num_q_vectors;
3157 struct ixgbe_q_vector *q_vector;
3158 int napi_vectors;
3159 int (*poll)(struct napi_struct *, int);
3160
3161 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3162 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3163 napi_vectors = adapter->num_rx_queues;
3164 poll = &ixgbe_clean_rxonly;
3165 } else {
3166 num_q_vectors = 1;
3167 napi_vectors = 1;
3168 poll = &ixgbe_poll;
3169 }
3170
3171 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3172 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3173 if (!q_vector)
3174 goto err_out;
3175 q_vector->adapter = adapter;
3176 q_vector->v_idx = q_idx;
3177 q_vector->eitr = adapter->eitr_param;
3178 if (q_idx < napi_vectors)
3179 netif_napi_add(adapter->netdev, &q_vector->napi,
3180 (*poll), 64);
3181 adapter->q_vector[q_idx] = q_vector;
3182 }
3183
3184 return 0;
3185
3186err_out:
3187 while (q_idx) {
3188 q_idx--;
3189 q_vector = adapter->q_vector[q_idx];
3190 netif_napi_del(&q_vector->napi);
3191 kfree(q_vector);
3192 adapter->q_vector[q_idx] = NULL;
3193 }
3194 return -ENOMEM;
3195}
3196
3197/**
3198 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3199 * @adapter: board private structure to initialize
3200 *
3201 * This function frees the memory allocated to the q_vectors. In addition if
3202 * NAPI is enabled it will delete any references to the NAPI struct prior
3203 * to freeing the q_vector.
3204 **/
3205static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3206{
3207 int q_idx, num_q_vectors;
3208 int napi_vectors;
3209
3210 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3211 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3212 napi_vectors = adapter->num_rx_queues;
3213 } else {
3214 num_q_vectors = 1;
3215 napi_vectors = 1;
3216 }
3217
3218 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3219 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3220
3221 adapter->q_vector[q_idx] = NULL;
3222 if (q_idx < napi_vectors)
3223 netif_napi_del(&q_vector->napi);
3224 kfree(q_vector);
3225 }
3226}
3227
2f90b865 3228void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 3229{
3230 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3231 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3232 pci_disable_msix(adapter->pdev);
3233 kfree(adapter->msix_entries);
3234 adapter->msix_entries = NULL;
3235 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3236 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3237 pci_disable_msi(adapter->pdev);
3238 }
3239 return;
3240}
3241
3242/**
3243 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3244 * @adapter: board private structure to initialize
3245 *
3246 * We determine which interrupt scheme to use based on...
3247 * - Kernel support (MSI, MSI-X)
3248 * - which can be user-defined (via MODULE_PARAM)
3249 * - Hardware queue count (num_*_queues)
3250 * - defined by miscellaneous hardware support/features (RSS, etc.)
3251 **/
2f90b865 3252int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 3253{
3254 int err;
3255
3256 /* Number of supported queues */
3257 ixgbe_set_num_queues(adapter);
3258
021230d4
AV		 3259 err = ixgbe_set_interrupt_capability(adapter);
3260 if (err) {
3261 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3262 goto err_set_interrupt;
9a799d71
AK		 3263 }
3264
7a921c93
AD		 3265 err = ixgbe_alloc_q_vectors(adapter);
3266 if (err) {
3267 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3268 "vectors\n");
3269 goto err_alloc_q_vectors;
3270 }
3271
3272 err = ixgbe_alloc_queues(adapter);
3273 if (err) {
3274 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3275 goto err_alloc_queues;
3276 }
3277
021230d4 3278 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 3279 "Tx Queue count = %u\n",
3280 (adapter->num_rx_queues > 1) ? "Enabled" :
3281 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 3282
3283 set_bit(__IXGBE_DOWN, &adapter->state);
3284
9a799d71 3285 return 0;
021230d4 3286
7a921c93
AD		 3287err_alloc_queues:
3288 ixgbe_free_q_vectors(adapter);
3289err_alloc_q_vectors:
3290 ixgbe_reset_interrupt_capability(adapter);
021230d4 3291err_set_interrupt:
7a921c93
AD		 3292 return err;
3293}
3294
3295/**
3296 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3297 * @adapter: board private structure to clear interrupt scheme on
3298 *
3299 * We go through and clear interrupt specific resources and reset the structure
3300 * to pre-load conditions
3301 **/
3302void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3303{
021230d4
AV		 3304 kfree(adapter->tx_ring);
3305 kfree(adapter->rx_ring);
7a921c93
AD		 3306 adapter->tx_ring = NULL;
3307 adapter->rx_ring = NULL;
3308
3309 ixgbe_free_q_vectors(adapter);
3310 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 3311}
3312
c4900be0
DS		 3313/**
3314 * ixgbe_sfp_timer - worker thread to find a missing module
3315 * @data: pointer to our adapter struct
3316 **/
3317static void ixgbe_sfp_timer(unsigned long data)
3318{
3319 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3320
4df10466
JB		 3321 /*
3322 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 3323 * delays that sfp+ detection requires
3324 */
3325 schedule_work(&adapter->sfp_task);
3326}
3327
3328/**
3329 * ixgbe_sfp_task - worker thread to find a missing module
3330 * @work: pointer to work_struct containing our data
3331 **/
3332static void ixgbe_sfp_task(struct work_struct *work)
3333{
3334 struct ixgbe_adapter *adapter = container_of(work,
3335 struct ixgbe_adapter,
3336 sfp_task);
3337 struct ixgbe_hw *hw = &adapter->hw;
3338
3339 if ((hw->phy.type == ixgbe_phy_nl) &&
3340 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3341 s32 ret = hw->phy.ops.identify_sfp(hw);
3342 if (ret)
3343 goto reschedule;
3344 ret = hw->phy.ops.reset(hw);
3345 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3346 DPRINTK(PROBE, ERR, "failed to initialize because an "
3347 "unsupported SFP+ module type was detected.\n"
3348 "Reload the driver after installing a "
3349 "supported module.\n");
3350 unregister_netdev(adapter->netdev);
3351 } else {
3352 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3353 hw->phy.sfp_type);
3354 }
3355 /* don't need this routine any more */
3356 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3357 }
3358 return;
3359reschedule:
3360 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3361 mod_timer(&adapter->sfp_timer,
3362 round_jiffies(jiffies + (2 * HZ)));
3363}
3364
9a799d71
AK		 3365/**
3366 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3367 * @adapter: board private structure to initialize
3368 *
3369 * ixgbe_sw_init initializes the Adapter private data structure.
3370 * Fields are initialized based on PCI device information and
3371 * OS network device settings (MTU size).
3372 **/
3373static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3374{
3375 struct ixgbe_hw *hw = &adapter->hw;
3376 struct pci_dev *pdev = adapter->pdev;
021230d4 3377 unsigned int rss;
7a6b6f51 3378#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3379 int j;
3380 struct tc_configuration *tc;
3381#endif
021230d4 3382
c44ade9e
JB		 3383 /* PCI config space info */
3384
3385 hw->vendor_id = pdev->vendor;
3386 hw->device_id = pdev->device;
3387 hw->revision_id = pdev->revision;
3388 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3389 hw->subsystem_device_id = pdev->subsystem_device;
3390
021230d4
AV		 3391 /* Set capability flags */
3392 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3393 adapter->ring_feature[RING_F_RSS].indices = rss;
3394 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 3395 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 3396 if (hw->mac.type == ixgbe_mac_82598EB) {
3397 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3398 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 3399 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 3400 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 3401 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
f8212f97
AD		 3402 adapter->flags |= IXGBE_FLAG_RSC_CAPABLE;
3403 adapter->flags |= IXGBE_FLAG_RSC_ENABLED;
3404 }
2f90b865 3405
7a6b6f51 3406#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3407 /* Configure DCB traffic classes */
3408 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3409 tc = &adapter->dcb_cfg.tc_config[j];
3410 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3411 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3412 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3413 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3414 tc->dcb_pfc = pfc_disabled;
3415 }
3416 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3417 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3418 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3419 adapter->dcb_cfg.round_robin_enable = false;
3420 adapter->dcb_set_bitmap = 0x00;
3421 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3422 adapter->ring_feature[RING_F_DCB].indices);
3423
3424#endif
9a799d71
AK		 3425
3426 /* default flow control settings */
cd7664f6 3427 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 3428 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
2b9ade93
JB		 3429 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3430 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3431 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3432 hw->fc.send_xon = true;
71fd570b 3433 hw->fc.disable_fc_autoneg = false;
9a799d71 3434
30efa5a3
JB		 3435 /* enable itr by default in dynamic mode */
3436 adapter->itr_setting = 1;
3437 adapter->eitr_param = 20000;
3438
3439 /* set defaults for eitr in MegaBytes */
3440 adapter->eitr_low = 10;
3441 adapter->eitr_high = 20;
3442
3443 /* set default ring sizes */
3444 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3445 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3446
9a799d71 3447 /* initialize eeprom parameters */
c44ade9e 3448 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 3449 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3450 return -EIO;
3451 }
3452
021230d4 3453 /* enable rx csum by default */
9a799d71
AK		 3454 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3455
9a799d71
AK		 3456 set_bit(__IXGBE_DOWN, &adapter->state);
3457
3458 return 0;
3459}
3460
3461/**
3462 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3463 * @adapter: board private structure
3a581073 3464 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3465 *
3466 * Return 0 on success, negative on failure
3467 **/
3468int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 3469 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3470{
3471 struct pci_dev *pdev = adapter->pdev;
3472 int size;
3473
3a581073
JB		 3474 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3475 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 3476 if (!tx_ring->tx_buffer_info)
3477 goto err;
3a581073 3478 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 3479
3480 /* round up to nearest 4K */
12207e49 3481 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 3482 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 3483
3a581073
JB		 3484 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3485 &tx_ring->dma);
e01c31a5
JB		 3486 if (!tx_ring->desc)
3487 goto err;
9a799d71 3488
3a581073
JB		 3489 tx_ring->next_to_use = 0;
3490 tx_ring->next_to_clean = 0;
3491 tx_ring->work_limit = tx_ring->count;
9a799d71 3492 return 0;
e01c31a5
JB		 3493
3494err:
3495 vfree(tx_ring->tx_buffer_info);
3496 tx_ring->tx_buffer_info = NULL;
3497 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3498 "descriptor ring\n");
3499 return -ENOMEM;
9a799d71
AK		 3500}
3501
69888674
AD		 3502/**
3503 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3504 * @adapter: board private structure
3505 *
3506 * If this function returns with an error, then it's possible one or
3507 * more of the rings is populated (while the rest are not). It is the
3508 * callers duty to clean those orphaned rings.
3509 *
3510 * Return 0 on success, negative on failure
3511 **/
3512static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3513{
3514 int i, err = 0;
3515
3516 for (i = 0; i < adapter->num_tx_queues; i++) {
3517 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3518 if (!err)
3519 continue;
3520 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3521 break;
3522 }
3523
3524 return err;
3525}
3526
9a799d71
AK		 3527/**
3528 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3529 * @adapter: board private structure
3a581073 3530 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3531 *
3532 * Returns 0 on success, negative on failure
3533 **/
3534int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 3535 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3536{
3537 struct pci_dev *pdev = adapter->pdev;
021230d4 3538 int size;
9a799d71 3539
3a581073
JB		 3540 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3541 rx_ring->rx_buffer_info = vmalloc(size);
3542 if (!rx_ring->rx_buffer_info) {
9a799d71 3543 DPRINTK(PROBE, ERR,
b4617240 3544 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 3545 goto alloc_failed;
9a799d71 3546 }
3a581073 3547 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 3548
9a799d71 3549 /* Round up to nearest 4K */
3a581073
JB		 3550 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3551 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 3552
3a581073 3553 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 3554
3a581073 3555 if (!rx_ring->desc) {
9a799d71 3556 DPRINTK(PROBE, ERR,
b4617240 3557 "Memory allocation failed for the rx desc ring\n");
3a581073 3558 vfree(rx_ring->rx_buffer_info);
177db6ff 3559 goto alloc_failed;
9a799d71
AK		 3560 }
3561
3a581073
JB		 3562 rx_ring->next_to_clean = 0;
3563 rx_ring->next_to_use = 0;
9a799d71
AK		 3564
3565 return 0;
177db6ff
MC		 3566
3567alloc_failed:
177db6ff 3568 return -ENOMEM;
9a799d71
AK		 3569}
3570
69888674
AD		 3571/**
3572 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3573 * @adapter: board private structure
3574 *
3575 * If this function returns with an error, then it's possible one or
3576 * more of the rings is populated (while the rest are not). It is the
3577 * callers duty to clean those orphaned rings.
3578 *
3579 * Return 0 on success, negative on failure
3580 **/
3581
3582static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3583{
3584 int i, err = 0;
3585
3586 for (i = 0; i < adapter->num_rx_queues; i++) {
3587 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3588 if (!err)
3589 continue;
3590 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3591 break;
3592 }
3593
3594 return err;
3595}
3596
9a799d71
AK		 3597/**
3598 * ixgbe_free_tx_resources - Free Tx Resources per Queue
3599 * @adapter: board private structure
3600 * @tx_ring: Tx descriptor ring for a specific queue
3601 *
3602 * Free all transmit software resources
3603 **/
c431f97e
JB		 3604void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
3605 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3606{
3607 struct pci_dev *pdev = adapter->pdev;
3608
3609 ixgbe_clean_tx_ring(adapter, tx_ring);
3610
3611 vfree(tx_ring->tx_buffer_info);
3612 tx_ring->tx_buffer_info = NULL;
3613
3614 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
3615
3616 tx_ring->desc = NULL;
3617}
3618
3619/**
3620 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3621 * @adapter: board private structure
3622 *
3623 * Free all transmit software resources
3624 **/
3625static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
3626{
3627 int i;
3628
3629 for (i = 0; i < adapter->num_tx_queues; i++)
9891ca7c
JB		 3630 if (adapter->tx_ring[i].desc)
3631 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 3632}
3633
3634/**
b4617240 3635 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 3636 * @adapter: board private structure
3637 * @rx_ring: ring to clean the resources from
3638 *
3639 * Free all receive software resources
3640 **/
c431f97e
JB		 3641void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
3642 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3643{
3644 struct pci_dev *pdev = adapter->pdev;
3645
3646 ixgbe_clean_rx_ring(adapter, rx_ring);
3647
3648 vfree(rx_ring->rx_buffer_info);
3649 rx_ring->rx_buffer_info = NULL;
3650
3651 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
3652
3653 rx_ring->desc = NULL;
3654}
3655
3656/**
3657 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3658 * @adapter: board private structure
3659 *
3660 * Free all receive software resources
3661 **/
3662static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3663{
3664 int i;
3665
3666 for (i = 0; i < adapter->num_rx_queues; i++)
9891ca7c
JB		 3667 if (adapter->rx_ring[i].desc)
3668 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 3669}
3670
9a799d71
AK		 3671/**
3672 * ixgbe_change_mtu - Change the Maximum Transfer Unit
3673 * @netdev: network interface device structure
3674 * @new_mtu: new value for maximum frame size
3675 *
3676 * Returns 0 on success, negative on failure
3677 **/
3678static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3679{
3680 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3681 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3682
42c783c5
JB		 3683 /* MTU < 68 is an error and causes problems on some kernels */
3684 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 3685 return -EINVAL;
3686
021230d4 3687 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 3688 netdev->mtu, new_mtu);
021230d4 3689 /* must set new MTU before calling down or up */
9a799d71
AK		 3690 netdev->mtu = new_mtu;
3691
d4f80882
AV		 3692 if (netif_running(netdev))
3693 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3694
3695 return 0;
3696}
3697
3698/**
3699 * ixgbe_open - Called when a network interface is made active
3700 * @netdev: network interface device structure
3701 *
3702 * Returns 0 on success, negative value on failure
3703 *
3704 * The open entry point is called when a network interface is made
3705 * active by the system (IFF_UP). At this point all resources needed
3706 * for transmit and receive operations are allocated, the interrupt
3707 * handler is registered with the OS, the watchdog timer is started,
3708 * and the stack is notified that the interface is ready.
3709 **/
3710static int ixgbe_open(struct net_device *netdev)
3711{
3712 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3713 int err;
4bebfaa5
AK		 3714
3715 /* disallow open during test */
3716 if (test_bit(__IXGBE_TESTING, &adapter->state))
3717 return -EBUSY;
9a799d71 3718
54386467
JB		 3719 netif_carrier_off(netdev);
3720
9a799d71
AK		 3721 /* allocate transmit descriptors */
3722 err = ixgbe_setup_all_tx_resources(adapter);
3723 if (err)
3724 goto err_setup_tx;
3725
9a799d71
AK		 3726 /* allocate receive descriptors */
3727 err = ixgbe_setup_all_rx_resources(adapter);
3728 if (err)
3729 goto err_setup_rx;
3730
3731 ixgbe_configure(adapter);
3732
021230d4 3733 err = ixgbe_request_irq(adapter);
9a799d71
AK		 3734 if (err)
3735 goto err_req_irq;
3736
9a799d71
AK		 3737 err = ixgbe_up_complete(adapter);
3738 if (err)
3739 goto err_up;
3740
d55b53ff
JK		 3741 netif_tx_start_all_queues(netdev);
3742
9a799d71
AK		 3743 return 0;
3744
3745err_up:
5eba3699 3746 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3747 ixgbe_free_irq(adapter);
3748err_req_irq:
9a799d71 3749err_setup_rx:
a20a1199 3750 ixgbe_free_all_rx_resources(adapter);
9a799d71 3751err_setup_tx:
a20a1199 3752 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 3753 ixgbe_reset(adapter);
3754
3755 return err;
3756}
3757
3758/**
3759 * ixgbe_close - Disables a network interface
3760 * @netdev: network interface device structure
3761 *
3762 * Returns 0, this is not allowed to fail
3763 *
3764 * The close entry point is called when an interface is de-activated
3765 * by the OS. The hardware is still under the drivers control, but
3766 * needs to be disabled. A global MAC reset is issued to stop the
3767 * hardware, and all transmit and receive resources are freed.
3768 **/
3769static int ixgbe_close(struct net_device *netdev)
3770{
3771 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 3772
3773 ixgbe_down(adapter);
3774 ixgbe_free_irq(adapter);
3775
3776 ixgbe_free_all_tx_resources(adapter);
3777 ixgbe_free_all_rx_resources(adapter);
3778
5eba3699 3779 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3780
3781 return 0;
3782}
3783
b3c8b4ba
AD		 3784#ifdef CONFIG_PM
3785static int ixgbe_resume(struct pci_dev *pdev)
3786{
3787 struct net_device *netdev = pci_get_drvdata(pdev);
3788 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3789 u32 err;
3790
3791 pci_set_power_state(pdev, PCI_D0);
3792 pci_restore_state(pdev);
9ce77666 3793
3794 err = pci_enable_device_mem(pdev);
b3c8b4ba 3795 if (err) {
69888674 3796 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 3797 "suspend\n");
3798 return err;
3799 }
3800 pci_set_master(pdev);
3801
dd4d8ca6 3802 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 3803
3804 err = ixgbe_init_interrupt_scheme(adapter);
3805 if (err) {
3806 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3807 "device\n");
3808 return err;
3809 }
3810
b3c8b4ba
AD		 3811 ixgbe_reset(adapter);
3812
495dce12
WJP		 3813 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
3814
b3c8b4ba
AD		 3815 if (netif_running(netdev)) {
3816 err = ixgbe_open(adapter->netdev);
3817 if (err)
3818 return err;
3819 }
3820
3821 netif_device_attach(netdev);
3822
3823 return 0;
3824}
b3c8b4ba 3825#endif /* CONFIG_PM */
9d8d05ae
RW		 3826
3827static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 3828{
3829 struct net_device *netdev = pci_get_drvdata(pdev);
3830 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 3831 struct ixgbe_hw *hw = &adapter->hw;
3832 u32 ctrl, fctrl;
3833 u32 wufc = adapter->wol;
b3c8b4ba
AD		 3834#ifdef CONFIG_PM
3835 int retval = 0;
3836#endif
3837
3838 netif_device_detach(netdev);
3839
3840 if (netif_running(netdev)) {
3841 ixgbe_down(adapter);
3842 ixgbe_free_irq(adapter);
3843 ixgbe_free_all_tx_resources(adapter);
3844 ixgbe_free_all_rx_resources(adapter);
3845 }
7a921c93 3846 ixgbe_clear_interrupt_scheme(adapter);
b3c8b4ba
AD		 3847
3848#ifdef CONFIG_PM
3849 retval = pci_save_state(pdev);
3850 if (retval)
3851 return retval;
4df10466 3852
b3c8b4ba 3853#endif
e8e26350
PW		 3854 if (wufc) {
3855 ixgbe_set_rx_mode(netdev);
b3c8b4ba 3856
e8e26350
PW		 3857 /* turn on all-multi mode if wake on multicast is enabled */
3858 if (wufc & IXGBE_WUFC_MC) {
3859 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3860 fctrl |= IXGBE_FCTRL_MPE;
3861 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3862 }
3863
3864 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
3865 ctrl |= IXGBE_CTRL_GIO_DIS;
3866 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
3867
3868 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
3869 } else {
3870 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
3871 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
3872 }
3873
dd4d8ca6
DS		 3874 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
3875 pci_wake_from_d3(pdev, true);
3876 else
3877 pci_wake_from_d3(pdev, false);
b3c8b4ba 3878
9d8d05ae
RW		 3879 *enable_wake = !!wufc;
3880
b3c8b4ba
AD		 3881 ixgbe_release_hw_control(adapter);
3882
3883 pci_disable_device(pdev);
3884
9d8d05ae
RW		 3885 return 0;
3886}
3887
3888#ifdef CONFIG_PM
3889static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
3890{
3891 int retval;
3892 bool wake;
3893
3894 retval = __ixgbe_shutdown(pdev, &wake);
3895 if (retval)
3896 return retval;
3897
3898 if (wake) {
3899 pci_prepare_to_sleep(pdev);
3900 } else {
3901 pci_wake_from_d3(pdev, false);
3902 pci_set_power_state(pdev, PCI_D3hot);
3903 }
b3c8b4ba
AD		 3904
3905 return 0;
3906}
9d8d05ae 3907#endif /* CONFIG_PM */
b3c8b4ba
AD		 3908
3909static void ixgbe_shutdown(struct pci_dev *pdev)
3910{
9d8d05ae
RW		 3911 bool wake;
3912
3913 __ixgbe_shutdown(pdev, &wake);
3914
3915 if (system_state == SYSTEM_POWER_OFF) {
3916 pci_wake_from_d3(pdev, wake);
3917 pci_set_power_state(pdev, PCI_D3hot);
3918 }
b3c8b4ba
AD		 3919}
3920
9a799d71
AK		 3921/**
3922 * ixgbe_update_stats - Update the board statistics counters.
3923 * @adapter: board private structure
3924 **/
3925void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3926{
3927 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 3928 u64 total_mpc = 0;
3929 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71 3930
d51019a4 3931 if (hw->mac.type == ixgbe_mac_82599EB) {
f8212f97 3932 u64 rsc_count = 0;
d51019a4
PW		 3933 for (i = 0; i < 16; i++)
3934 adapter->hw_rx_no_dma_resources +=
3935 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
f8212f97
AD		 3936 for (i = 0; i < adapter->num_rx_queues; i++)
3937 rsc_count += adapter->rx_ring[i].rsc_count;
3938 adapter->rsc_count = rsc_count;
d51019a4
PW		 3939 }
3940
9a799d71 3941 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 3942 for (i = 0; i < 8; i++) {
3943 /* for packet buffers not used, the register should read 0 */
3944 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3945 missed_rx += mpc;
3946 adapter->stats.mpc[i] += mpc;
3947 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 3948 if (hw->mac.type == ixgbe_mac_82598EB)
3949 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 3950 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3951 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
3952 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3953 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 3954 if (hw->mac.type == ixgbe_mac_82599EB) {
3955 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3956 IXGBE_PXONRXCNT(i));
3957 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3958 IXGBE_PXOFFRXCNT(i));
3959 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 3960 } else {
3961 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3962 IXGBE_PXONRXC(i));
3963 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3964 IXGBE_PXOFFRXC(i));
3965 }
2f90b865
AD		 3966 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
3967 IXGBE_PXONTXC(i));
2f90b865 3968 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 3969 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 3970 }
3971 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3972 /* work around hardware counting issue */
3973 adapter->stats.gprc -= missed_rx;
3974
3975 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350
PW		 3976 if (hw->mac.type == ixgbe_mac_82599EB) {
3977 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3978 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
3979 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3980 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
3981 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3982 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
3983 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3984 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3985 } else {
3986 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3987 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3988 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3989 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3990 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3991 }
9a799d71
AK		 3992 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3993 adapter->stats.bprc += bprc;
3994 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 3995 if (hw->mac.type == ixgbe_mac_82598EB)
3996 adapter->stats.mprc -= bprc;
9a799d71
AK		 3997 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3998 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3999 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4000 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4001 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4002 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4003 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 4004 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 4005 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4006 adapter->stats.lxontxc += lxon;
4007 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4008 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 4009 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4010 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 4011 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4012 /*
4013 * 82598 errata - tx of flow control packets is included in tx counters
4014 */
4015 xon_off_tot = lxon + lxoff;
4016 adapter->stats.gptc -= xon_off_tot;
4017 adapter->stats.mptc -= xon_off_tot;
4018 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 4019 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4020 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4021 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 4022 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4023 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 4024 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 4025 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4026 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4027 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4028 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4029 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 4030 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4031
4032 /* Fill out the OS statistics structure */
9a799d71
AK		 4033 adapter->net_stats.multicast = adapter->stats.mprc;
4034
4035 /* Rx Errors */
4036 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
b4617240 4037 adapter->stats.rlec;
9a799d71
AK		 4038 adapter->net_stats.rx_dropped = 0;
4039 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4040 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 4041 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 4042}
4043
4044/**
4045 * ixgbe_watchdog - Timer Call-back
4046 * @data: pointer to adapter cast into an unsigned long
4047 **/
4048static void ixgbe_watchdog(unsigned long data)
4049{
4050 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee
JB		 4051 struct ixgbe_hw *hw = &adapter->hw;
4052
4053 /* Do the watchdog outside of interrupt context due to the lovely
4054 * delays that some of the newer hardware requires */
4055 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
22d5a71b
JB		 4056 u64 eics = 0;
4057 int i;
4058
4059 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++)
4060 eics |= (1 << i);
4061
cf8280ee 4062 /* Cause software interrupt to ensure rx rings are cleaned */
22d5a71b
JB		 4063 switch (hw->mac.type) {
4064 case ixgbe_mac_82598EB:
4065 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4066 IXGBE_WRITE_REG(hw, IXGBE_EICS, (u32)eics);
4067 } else {
4068 /*
4069 * for legacy and MSI interrupts don't set any
4070 * bits that are enabled for EIAM, because this
4071 * operation would set *both* EIMS and EICS for
4072 * any bit in EIAM
4073 */
4074 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4075 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4076 }
4077 break;
4078 case ixgbe_mac_82599EB:
4079 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
835462fc
NS		 4080 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(0),
4081 (u32)(eics & 0xFFFFFFFF));
22d5a71b 4082 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(1),
22d5a71b
JB		 4083 (u32)(eics >> 32));
4084 } else {
4085 /*
4086 * for legacy and MSI interrupts don't set any
4087 * bits that are enabled for EIAM, because this
4088 * operation would set *both* EIMS and EICS for
4089 * any bit in EIAM
4090 */
4091 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4092 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4093 }
4094 break;
4095 default:
4096 break;
cf8280ee
JB		 4097 }
4098 /* Reset the timer */
4099 mod_timer(&adapter->watchdog_timer,
4100 round_jiffies(jiffies + 2 * HZ));
4101 }
9a799d71 4102
cf8280ee
JB		 4103 schedule_work(&adapter->watchdog_task);
4104}
4105
e8e26350
PW		 4106/**
4107 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4108 * @work: pointer to work_struct containing our data
4109 **/
4110static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4111{
4112 struct ixgbe_adapter *adapter = container_of(work,
4113 struct ixgbe_adapter,
4114 multispeed_fiber_task);
4115 struct ixgbe_hw *hw = &adapter->hw;
4116 u32 autoneg;
4117
4118 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4119 if (hw->mac.ops.get_link_capabilities)
4120 hw->mac.ops.get_link_capabilities(hw, &autoneg,
4121 &hw->mac.autoneg);
4122 if (hw->mac.ops.setup_link_speed)
4123 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
4124 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4125 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4126}
4127
4128/**
4129 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4130 * @work: pointer to work_struct containing our data
4131 **/
4132static void ixgbe_sfp_config_module_task(struct work_struct *work)
4133{
4134 struct ixgbe_adapter *adapter = container_of(work,
4135 struct ixgbe_adapter,
4136 sfp_config_module_task);
4137 struct ixgbe_hw *hw = &adapter->hw;
4138 u32 err;
4139
4140 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4141 err = hw->phy.ops.identify_sfp(hw);
4142 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4143 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
4144 ixgbe_down(adapter);
4145 return;
4146 }
4147 hw->mac.ops.setup_sfp(hw);
4148
8d1c3c07 4149 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 4150 /* This will also work for DA Twinax connections */
4151 schedule_work(&adapter->multispeed_fiber_task);
4152 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4153}
4154
cf8280ee 4155/**
69888674
AD		 4156 * ixgbe_watchdog_task - worker thread to bring link up
4157 * @work: pointer to work_struct containing our data
cf8280ee
JB		 4158 **/
4159static void ixgbe_watchdog_task(struct work_struct *work)
4160{
4161 struct ixgbe_adapter *adapter = container_of(work,
4162 struct ixgbe_adapter,
4163 watchdog_task);
4164 struct net_device *netdev = adapter->netdev;
4165 struct ixgbe_hw *hw = &adapter->hw;
4166 u32 link_speed = adapter->link_speed;
4167 bool link_up = adapter->link_up;
bc59fcda
NS		 4168 int i;
4169 struct ixgbe_ring *tx_ring;
4170 int some_tx_pending = 0;
cf8280ee
JB		 4171
4172 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4173
4174 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4175 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4176 if (link_up ||
4177 time_after(jiffies, (adapter->link_check_timeout +
4178 IXGBE_TRY_LINK_TIMEOUT))) {
4179 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4180 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4181 }
4182 adapter->link_up = link_up;
4183 adapter->link_speed = link_speed;
4184 }
9a799d71
AK		 4185
4186 if (link_up) {
4187 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 4188 bool flow_rx, flow_tx;
4189
4190 if (hw->mac.type == ixgbe_mac_82599EB) {
4191 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4192 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4193 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
4194 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
4195 } else {
4196 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4197 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4198 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
4199 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
4200 }
4201
a46e534b
JK		 4202 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4203 "Flow Control: %s\n",
4204 netdev->name,
4205 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4206 "10 Gbps" :
4207 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4208 "1 Gbps" : "unknown speed")),
e8e26350
PW		 4209 ((flow_rx && flow_tx) ? "RX/TX" :
4210 (flow_rx ? "RX" :
4211 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 4212
4213 netif_carrier_on(netdev);
9a799d71
AK		 4214 } else {
4215 /* Force detection of hung controller */
4216 adapter->detect_tx_hung = true;
4217 }
4218 } else {
cf8280ee
JB		 4219 adapter->link_up = false;
4220 adapter->link_speed = 0;
9a799d71 4221 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 4222 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4223 netdev->name);
9a799d71 4224 netif_carrier_off(netdev);
9a799d71
AK		 4225 }
4226 }
4227
bc59fcda
NS		 4228 if (!netif_carrier_ok(netdev)) {
4229 for (i = 0; i < adapter->num_tx_queues; i++) {
4230 tx_ring = &adapter->tx_ring[i];
4231 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4232 some_tx_pending = 1;
4233 break;
4234 }
4235 }
4236
4237 if (some_tx_pending) {
4238 /* We've lost link, so the controller stops DMA,
4239 * but we've got queued Tx work that's never going
4240 * to get done, so reset controller to flush Tx.
4241 * (Do the reset outside of interrupt context).
4242 */
4243 schedule_work(&adapter->reset_task);
4244 }
4245 }
4246
9a799d71 4247 ixgbe_update_stats(adapter);
cf8280ee 4248 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 4249}
4250
9a799d71 4251static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 4252 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4253 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 4254{
4255 struct ixgbe_adv_tx_context_desc *context_desc;
4256 unsigned int i;
4257 int err;
4258 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 4259 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4260 u32 mss_l4len_idx, l4len;
9a799d71
AK		 4261
4262 if (skb_is_gso(skb)) {
4263 if (skb_header_cloned(skb)) {
4264 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4265 if (err)
4266 return err;
4267 }
4268 l4len = tcp_hdrlen(skb);
4269 *hdr_len += l4len;
4270
8327d000 4271 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 4272 struct iphdr *iph = ip_hdr(skb);
4273 iph->tot_len = 0;
4274 iph->check = 0;
4275 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 4276 iph->daddr, 0,
4277 IPPROTO_TCP,
4278 0);
9a799d71
AK		 4279 adapter->hw_tso_ctxt++;
4280 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4281 ipv6_hdr(skb)->payload_len = 0;
4282 tcp_hdr(skb)->check =
4283 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 4284 &ipv6_hdr(skb)->daddr,
4285 0, IPPROTO_TCP, 0);
9a799d71
AK		 4286 adapter->hw_tso6_ctxt++;
4287 }
4288
4289 i = tx_ring->next_to_use;
4290
4291 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4292 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4293
4294 /* VLAN MACLEN IPLEN */
4295 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4296 vlan_macip_lens |=
4297 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4298 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 4299 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4300 *hdr_len += skb_network_offset(skb);
4301 vlan_macip_lens |=
4302 (skb_transport_header(skb) - skb_network_header(skb));
4303 *hdr_len +=
4304 (skb_transport_header(skb) - skb_network_header(skb));
4305 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4306 context_desc->seqnum_seed = 0;
4307
4308 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 4309 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 4310 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 4311
8327d000 4312 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4313 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4314 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4315 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4316
4317 /* MSS L4LEN IDX */
9f8cdf4f 4318 mss_l4len_idx =
9a799d71
AK		 4319 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4320 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 4321 /* use index 1 for TSO */
4322 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4323 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4324
4325 tx_buffer_info->time_stamp = jiffies;
4326 tx_buffer_info->next_to_watch = i;
4327
4328 i++;
4329 if (i == tx_ring->count)
4330 i = 0;
4331 tx_ring->next_to_use = i;
4332
4333 return true;
4334 }
4335 return false;
4336}
4337
4338static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 4339 struct ixgbe_ring *tx_ring,
4340 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 4341{
4342 struct ixgbe_adv_tx_context_desc *context_desc;
4343 unsigned int i;
4344 struct ixgbe_tx_buffer *tx_buffer_info;
4345 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4346
4347 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4348 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4349 i = tx_ring->next_to_use;
4350 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4351 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4352
4353 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4354 vlan_macip_lens |=
4355 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4356 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 4357 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4358 if (skb->ip_summed == CHECKSUM_PARTIAL)
4359 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 4360 skb_network_header(skb));
9a799d71
AK		 4361
4362 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4363 context_desc->seqnum_seed = 0;
4364
4365 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 4366 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 4367
4368 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71 4369 switch (skb->protocol) {
09640e63 4370 case cpu_to_be16(ETH_P_IP):
9a799d71 4371 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 4372 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4373 type_tucmd_mlhl |=
b4617240 4374 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4375 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4376 type_tucmd_mlhl |=
4377 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4378 break;
09640e63 4379 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 4380 /* XXX what about other V6 headers?? */
4381 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4382 type_tucmd_mlhl |=
b4617240 4383 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4384 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4385 type_tucmd_mlhl |=
4386 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4387 break;
41825d71
AK		 4388 default:
4389 if (unlikely(net_ratelimit())) {
4390 DPRINTK(PROBE, WARNING,
4391 "partial checksum but proto=%x!\n",
4392 skb->protocol);
4393 }
4394 break;
4395 }
9a799d71
AK		 4396 }
4397
4398 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 4399 /* use index zero for tx checksum offload */
9a799d71
AK		 4400 context_desc->mss_l4len_idx = 0;
4401
4402 tx_buffer_info->time_stamp = jiffies;
4403 tx_buffer_info->next_to_watch = i;
9f8cdf4f 4404
9a799d71
AK		 4405 adapter->hw_csum_tx_good++;
4406 i++;
4407 if (i == tx_ring->count)
4408 i = 0;
4409 tx_ring->next_to_use = i;
4410
4411 return true;
4412 }
9f8cdf4f 4413
9a799d71
AK		 4414 return false;
4415}
4416
4417static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240
PW		 4418 struct ixgbe_ring *tx_ring,
4419 struct sk_buff *skb, unsigned int first)
9a799d71
AK		 4420{
4421 struct ixgbe_tx_buffer *tx_buffer_info;
44df32c5 4422 unsigned int len = skb_headlen(skb);
9a799d71
AK		 4423 unsigned int offset = 0, size, count = 0, i;
4424 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4425 unsigned int f;
44df32c5 4426 dma_addr_t *map;
9a799d71
AK		 4427
4428 i = tx_ring->next_to_use;
4429
44df32c5
AD		 4430 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4431 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4432 return 0;
4433 }
4434
4435 map = skb_shinfo(skb)->dma_maps;
4436
9a799d71
AK		 4437 while (len) {
4438 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4439 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4440
4441 tx_buffer_info->length = size;
44df32c5 4442 tx_buffer_info->dma = map[0] + offset;
9a799d71
AK		 4443 tx_buffer_info->time_stamp = jiffies;
4444 tx_buffer_info->next_to_watch = i;
4445
4446 len -= size;
4447 offset += size;
4448 count++;
44df32c5
AD		 4449
4450 if (len) {
4451 i++;
4452 if (i == tx_ring->count)
4453 i = 0;
4454 }
9a799d71
AK		 4455 }
4456
4457 for (f = 0; f < nr_frags; f++) {
4458 struct skb_frag_struct *frag;
4459
4460 frag = &skb_shinfo(skb)->frags[f];
4461 len = frag->size;
44df32c5 4462 offset = 0;
9a799d71
AK		 4463
4464 while (len) {
44df32c5
AD		 4465 i++;
4466 if (i == tx_ring->count)
4467 i = 0;
4468
9a799d71
AK		 4469 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4470 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4471
4472 tx_buffer_info->length = size;
44df32c5 4473 tx_buffer_info->dma = map[f + 1] + offset;
9a799d71
AK		 4474 tx_buffer_info->time_stamp = jiffies;
4475 tx_buffer_info->next_to_watch = i;
4476
4477 len -= size;
4478 offset += size;
4479 count++;
9a799d71
AK		 4480 }
4481 }
44df32c5 4482
9a799d71
AK		 4483 tx_ring->tx_buffer_info[i].skb = skb;
4484 tx_ring->tx_buffer_info[first].next_to_watch = i;
4485
4486 return count;
4487}
4488
4489static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 4490 struct ixgbe_ring *tx_ring,
4491 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 4492{
4493 union ixgbe_adv_tx_desc *tx_desc = NULL;
4494 struct ixgbe_tx_buffer *tx_buffer_info;
4495 u32 olinfo_status = 0, cmd_type_len = 0;
4496 unsigned int i;
4497 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4498
4499 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4500
4501 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4502
4503 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4504 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4505
4506 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4507 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4508
4509 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4510 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 4511
4eeae6fd
PW		 4512 /* use index 1 context for tso */
4513 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4514 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4515 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 4516 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 4517
4518 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4519 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4520 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 4521
4522 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4523
4524 i = tx_ring->next_to_use;
4525 while (count--) {
4526 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4527 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4528 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4529 tx_desc->read.cmd_type_len =
b4617240 4530 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 4531 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 4532 i++;
4533 if (i == tx_ring->count)
4534 i = 0;
4535 }
4536
4537 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
4538
4539 /*
4540 * Force memory writes to complete before letting h/w
4541 * know there are new descriptors to fetch. (Only
4542 * applicable for weak-ordered memory model archs,
4543 * such as IA-64).
4544 */
4545 wmb();
4546
4547 tx_ring->next_to_use = i;
4548 writel(i, adapter->hw.hw_addr + tx_ring->tail);
4549}
4550
e092be60 4551static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 4552 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 4553{
4554 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4555
30eba97a 4556 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 4557 /* Herbert's original patch had:
4558 * smp_mb__after_netif_stop_queue();
4559 * but since that doesn't exist yet, just open code it. */
4560 smp_mb();
4561
4562 /* We need to check again in a case another CPU has just
4563 * made room available. */
4564 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
4565 return -EBUSY;
4566
4567 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 4568 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 4569 ++adapter->restart_queue;
4570 return 0;
4571}
4572
4573static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 4574 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 4575{
4576 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
4577 return 0;
4578 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
4579}
4580
09a3b1f8
SH		 4581static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
4582{
4583 struct ixgbe_adapter *adapter = netdev_priv(dev);
4584
4585 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4586 return 0; /* All traffic should default to class 0 */
4587
4588 return skb_tx_hash(dev, skb);
4589}
4590
9a799d71
AK		 4591static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
4592{
4593 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4594 struct ixgbe_ring *tx_ring;
9a799d71
AK		 4595 unsigned int first;
4596 unsigned int tx_flags = 0;
30eba97a
AV		 4597 u8 hdr_len = 0;
4598 int r_idx = 0, tso;
9a799d71
AK		 4599 int count = 0;
4600 unsigned int f;
9f8cdf4f 4601
95615d90 4602 r_idx = skb->queue_mapping;
30eba97a 4603 tx_ring = &adapter->tx_ring[r_idx];
9a799d71 4604
9f8cdf4f
JB		 4605 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
4606 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 4607 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4608 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
4609 tx_flags |= (skb->queue_mapping << 13);
4610 }
4611 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4612 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4613 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4614 tx_flags |= (skb->queue_mapping << 13);
9f8cdf4f
JB		 4615 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4616 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 4617 }
9f8cdf4f
JB		 4618 /* three things can cause us to need a context descriptor */
4619 if (skb_is_gso(skb) ||
4620 (skb->ip_summed == CHECKSUM_PARTIAL) ||
4621 (tx_flags & IXGBE_TX_FLAGS_VLAN))
9a799d71
AK		 4622 count++;
4623
9f8cdf4f
JB		 4624 count += TXD_USE_COUNT(skb_headlen(skb));
4625 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 4626 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4627
e092be60 4628 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 4629 adapter->tx_busy++;
9a799d71
AK		 4630 return NETDEV_TX_BUSY;
4631 }
9a799d71 4632
8327d000 4633 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4634 tx_flags |= IXGBE_TX_FLAGS_IPV4;
4635 first = tx_ring->next_to_use;
4636 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4637 if (tso < 0) {
4638 dev_kfree_skb_any(skb);
4639 return NETDEV_TX_OK;
4640 }
4641
4642 if (tso)
4643 tx_flags |= IXGBE_TX_FLAGS_TSO;
4644 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
b4617240 4645 (skb->ip_summed == CHECKSUM_PARTIAL))
9a799d71
AK		 4646 tx_flags |= IXGBE_TX_FLAGS_CSUM;
4647
44df32c5 4648 count = ixgbe_tx_map(adapter, tx_ring, skb, first);
9a799d71 4649
44df32c5
AD		 4650 if (count) {
4651 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
4652 hdr_len);
4653 netdev->trans_start = jiffies;
4654 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 4655
44df32c5
AD		 4656 } else {
4657 dev_kfree_skb_any(skb);
4658 tx_ring->tx_buffer_info[first].time_stamp = 0;
4659 tx_ring->next_to_use = first;
4660 }
9a799d71
AK		 4661
4662 return NETDEV_TX_OK;
4663}
4664
4665/**
4666 * ixgbe_get_stats - Get System Network Statistics
4667 * @netdev: network interface device structure
4668 *
4669 * Returns the address of the device statistics structure.
4670 * The statistics are actually updated from the timer callback.
4671 **/
4672static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
4673{
4674 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4675
4676 /* only return the current stats */
4677 return &adapter->net_stats;
4678}
4679
4680/**
4681 * ixgbe_set_mac - Change the Ethernet Address of the NIC
4682 * @netdev: network interface device structure
4683 * @p: pointer to an address structure
4684 *
4685 * Returns 0 on success, negative on failure
4686 **/
4687static int ixgbe_set_mac(struct net_device *netdev, void *p)
4688{
4689 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 4690 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 4691 struct sockaddr *addr = p;
4692
4693 if (!is_valid_ether_addr(addr->sa_data))
4694 return -EADDRNOTAVAIL;
4695
4696 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 4697 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 4698
b4617240 4699 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 4700
4701 return 0;
4702}
4703
6b73e10d
BH		 4704static int
4705ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
4706{
4707 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4708 struct ixgbe_hw *hw = &adapter->hw;
4709 u16 value;
4710 int rc;
4711
4712 if (prtad != hw->phy.mdio.prtad)
4713 return -EINVAL;
4714 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
4715 if (!rc)
4716 rc = value;
4717 return rc;
4718}
4719
4720static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
4721 u16 addr, u16 value)
4722{
4723 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4724 struct ixgbe_hw *hw = &adapter->hw;
4725
4726 if (prtad != hw->phy.mdio.prtad)
4727 return -EINVAL;
4728 return hw->phy.ops.write_reg(hw, addr, devad, value);
4729}
4730
4731static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
4732{
4733 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4734
4735 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
4736}
4737
9a799d71
AK		 4738#ifdef CONFIG_NET_POLL_CONTROLLER
4739/*
4740 * Polling 'interrupt' - used by things like netconsole to send skbs
4741 * without having to re-enable interrupts. It's not called while
4742 * the interrupt routine is executing.
4743 */
4744static void ixgbe_netpoll(struct net_device *netdev)
4745{
4746 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4747
4748 disable_irq(adapter->pdev->irq);
4749 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
4750 ixgbe_intr(adapter->pdev->irq, netdev);
4751 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
4752 enable_irq(adapter->pdev->irq);
4753}
4754#endif
4755
0edc3527
SH		 4756static const struct net_device_ops ixgbe_netdev_ops = {
4757 .ndo_open = ixgbe_open,
4758 .ndo_stop = ixgbe_close,
00829823 4759 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 4760 .ndo_select_queue = ixgbe_select_queue,
0edc3527 4761 .ndo_get_stats = ixgbe_get_stats,
e90d400c 4762 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 4763 .ndo_set_multicast_list = ixgbe_set_rx_mode,
4764 .ndo_validate_addr = eth_validate_addr,
4765 .ndo_set_mac_address = ixgbe_set_mac,
4766 .ndo_change_mtu = ixgbe_change_mtu,
4767 .ndo_tx_timeout = ixgbe_tx_timeout,
4768 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
4769 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
4770 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 4771 .ndo_do_ioctl = ixgbe_ioctl,
0edc3527
SH		 4772#ifdef CONFIG_NET_POLL_CONTROLLER
4773 .ndo_poll_controller = ixgbe_netpoll,
4774#endif
4775};
4776
9a799d71
AK		 4777/**
4778 * ixgbe_probe - Device Initialization Routine
4779 * @pdev: PCI device information struct
4780 * @ent: entry in ixgbe_pci_tbl
4781 *
4782 * Returns 0 on success, negative on failure
4783 *
4784 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
4785 * The OS initialization, configuring of the adapter private structure,
4786 * and a hardware reset occur.
4787 **/
4788static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 4789 const struct pci_device_id *ent)
9a799d71
AK		 4790{
4791 struct net_device *netdev;
4792 struct ixgbe_adapter *adapter = NULL;
4793 struct ixgbe_hw *hw;
4794 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 4795 static int cards_found;
4796 int i, err, pci_using_dac;
c44ade9e 4797 u32 part_num, eec;
9a799d71 4798
9ce77666 4799 err = pci_enable_device_mem(pdev);
9a799d71
AK		 4800 if (err)
4801 return err;
4802
6a35528a
YH		 4803 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
4804 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
9a799d71
AK		 4805 pci_using_dac = 1;
4806 } else {
284901a9 4807 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 4808 if (err) {
284901a9 4809 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 4810 if (err) {
b4617240
PW		 4811 dev_err(&pdev->dev, "No usable DMA "
4812 "configuration, aborting\n");
9a799d71
AK		 4813 goto err_dma;
4814 }
4815 }
4816 pci_using_dac = 0;
4817 }
4818
9ce77666 4819 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
4820 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 4821 if (err) {
9ce77666 4822 dev_err(&pdev->dev,
4823 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 4824 goto err_pci_reg;
4825 }
4826
6fabd715
PWJ		 4827 err = pci_enable_pcie_error_reporting(pdev);
4828 if (err) {
4829 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
4830 "0x%x\n", err);
4831 /* non-fatal, continue */
4832 }
4833
9a799d71 4834 pci_set_master(pdev);
fb3b27bc 4835 pci_save_state(pdev);
9a799d71 4836
30eba97a 4837 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 4838 if (!netdev) {
4839 err = -ENOMEM;
4840 goto err_alloc_etherdev;
4841 }
4842
9a799d71
AK		 4843 SET_NETDEV_DEV(netdev, &pdev->dev);
4844
4845 pci_set_drvdata(pdev, netdev);
4846 adapter = netdev_priv(netdev);
4847
4848 adapter->netdev = netdev;
4849 adapter->pdev = pdev;
4850 hw = &adapter->hw;
4851 hw->back = adapter;
4852 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
4853
05857980
JK		 4854 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
4855 pci_resource_len(pdev, 0));
9a799d71
AK		 4856 if (!hw->hw_addr) {
4857 err = -EIO;
4858 goto err_ioremap;
4859 }
4860
4861 for (i = 1; i <= 5; i++) {
4862 if (pci_resource_len(pdev, i) == 0)
4863 continue;
4864 }
4865
0edc3527 4866 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 4867 ixgbe_set_ethtool_ops(netdev);
9a799d71 4868 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 4869 strcpy(netdev->name, pci_name(pdev));
4870
9a799d71
AK		 4871 adapter->bd_number = cards_found;
4872
9a799d71
AK		 4873 /* Setup hw api */
4874 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 4875 hw->mac.type = ii->mac;
9a799d71 4876
c44ade9e
JB		 4877 /* EEPROM */
4878 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
4879 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
4880 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
4881 if (!(eec & (1 << 8)))
4882 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
4883
4884 /* PHY */
4885 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 4886 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 4887 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
4888 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
4889 hw->phy.mdio.mmds = 0;
4890 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
4891 hw->phy.mdio.dev = netdev;
4892 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
4893 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 4894
4895 /* set up this timer and work struct before calling get_invariants
4896 * which might start the timer
4897 */
4898 init_timer(&adapter->sfp_timer);
4899 adapter->sfp_timer.function = &ixgbe_sfp_timer;
4900 adapter->sfp_timer.data = (unsigned long) adapter;
4901
4902 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 4903
e8e26350
PW		 4904 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
4905 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
4906
4907 /* a new SFP+ module arrival, called from GPI SDP2 context */
4908 INIT_WORK(&adapter->sfp_config_module_task,
4909 ixgbe_sfp_config_module_task);
4910
9a799d71 4911 err = ii->get_invariants(hw);
c4900be0
DS		 4912 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
4913 /* start a kernel thread to watch for a module to arrive */
4914 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4915 mod_timer(&adapter->sfp_timer,
4916 round_jiffies(jiffies + (2 * HZ)));
4917 err = 0;
4918 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4919 DPRINTK(PROBE, ERR, "failed to load because an "
4920 "unsupported SFP+ module type was detected.\n");
9a799d71 4921 goto err_hw_init;
c4900be0
DS		 4922 } else if (err) {
4923 goto err_hw_init;
4924 }
9a799d71
AK		 4925
4926 /* setup the private structure */
4927 err = ixgbe_sw_init(adapter);
4928 if (err)
4929 goto err_sw_init;
4930
bf069c97
DS		 4931 /*
4932 * If there is a fan on this device and it has failed log the
4933 * failure.
4934 */
4935 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4936 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4937 if (esdp & IXGBE_ESDP_SDP1)
4938 DPRINTK(PROBE, CRIT,
4939 "Fan has stopped, replace the adapter\n");
4940 }
4941
c44ade9e
JB		 4942 /* reset_hw fills in the perm_addr as well */
4943 err = hw->mac.ops.reset_hw(hw);
04f165ef
PW		 4944 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4945 dev_err(&adapter->pdev->dev, "failed to load because an "
4946 "unsupported SFP+ module type was detected.\n");
4947 goto err_sw_init;
4948 } else if (err) {
c44ade9e
JB		 4949 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
4950 goto err_sw_init;
4951 }
4952
9a799d71 4953 netdev->features = NETIF_F_SG |
b4617240
PW		 4954 NETIF_F_IP_CSUM |
4955 NETIF_F_HW_VLAN_TX |
4956 NETIF_F_HW_VLAN_RX |
4957 NETIF_F_HW_VLAN_FILTER;
9a799d71 4958
e9990a9c 4959 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 4960 netdev->features |= NETIF_F_TSO;
9a799d71 4961 netdev->features |= NETIF_F_TSO6;
78b6f4ce 4962 netdev->features |= NETIF_F_GRO;
ad31c402 4963
45a5ead0
JB		 4964 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
4965 netdev->features |= NETIF_F_SCTP_CSUM;
4966
ad31c402
JK		 4967 netdev->vlan_features |= NETIF_F_TSO;
4968 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 4969 netdev->vlan_features |= NETIF_F_IP_CSUM;
ad31c402
JK		 4970 netdev->vlan_features |= NETIF_F_SG;
4971
2f90b865
AD		 4972 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4973 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4974
7a6b6f51 4975#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4976 netdev->dcbnl_ops = &dcbnl_ops;
4977#endif
4978
9a799d71
AK		 4979 if (pci_using_dac)
4980 netdev->features |= NETIF_F_HIGHDMA;
4981
f8212f97
AD		 4982 if (adapter->flags & IXGBE_FLAG_RSC_ENABLED)
4983 netdev->features |= NETIF_F_LRO;
4984
9a799d71 4985 /* make sure the EEPROM is good */
c44ade9e 4986 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 4987 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
4988 err = -EIO;
4989 goto err_eeprom;
4990 }
4991
4992 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
4993 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
4994
c44ade9e
JB		 4995 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
4996 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 4997 err = -EIO;
4998 goto err_eeprom;
4999 }
5000
5001 init_timer(&adapter->watchdog_timer);
5002 adapter->watchdog_timer.function = &ixgbe_watchdog;
5003 adapter->watchdog_timer.data = (unsigned long)adapter;
5004
5005 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 5006 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 5007
021230d4
AV		 5008 err = ixgbe_init_interrupt_scheme(adapter);
5009 if (err)
5010 goto err_sw_init;
9a799d71 5011
e8e26350
PW		 5012 switch (pdev->device) {
5013 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 5014 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5015 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 5016 break;
5017 default:
5018 adapter->wol = 0;
5019 break;
5020 }
5021 device_init_wakeup(&adapter->pdev->dev, true);
5022 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5023
04f165ef
PW		 5024 /* pick up the PCI bus settings for reporting later */
5025 hw->mac.ops.get_bus_info(hw);
5026
9a799d71 5027 /* print bus type/speed/width info */
7c510e4b 5028 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 5029 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5030 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5031 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5032 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5033 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 5034 "Unknown"),
7c510e4b 5035 netdev->dev_addr);
c44ade9e 5036 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 5037 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5038 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5039 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5040 (part_num >> 8), (part_num & 0xff));
5041 else
5042 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5043 hw->mac.type, hw->phy.type,
5044 (part_num >> 8), (part_num & 0xff));
9a799d71 5045
e8e26350 5046 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 5047 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 5048 "this card is not sufficient for optimal "
5049 "performance.\n");
0c254d86 5050 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 5051 "PCI-Express slot is required.\n");
0c254d86
AK		 5052 }
5053
34b0368c
PWJ		 5054 /* save off EEPROM version number */
5055 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5056
9a799d71 5057 /* reset the hardware with the new settings */
c44ade9e
JB		 5058 hw->mac.ops.start_hw(hw);
5059
9a799d71
AK		 5060 strcpy(netdev->name, "eth%d");
5061 err = register_netdev(netdev);
5062 if (err)
5063 goto err_register;
5064
54386467
JB		 5065 /* carrier off reporting is important to ethtool even BEFORE open */
5066 netif_carrier_off(netdev);
5067
5dd2d332 5068#ifdef CONFIG_IXGBE_DCA
652f093f 5069 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd
JC		 5070 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5071 /* always use CB2 mode, difference is masked
5072 * in the CB driver */
5073 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
5074 ixgbe_setup_dca(adapter);
5075 }
5076#endif
9a799d71
AK		 5077
5078 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5079 cards_found++;
5080 return 0;
5081
5082err_register:
5eba3699 5083 ixgbe_release_hw_control(adapter);
9a799d71 5084err_hw_init:
7a921c93 5085 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 5086err_sw_init:
5087err_eeprom:
c4900be0
DS		 5088 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5089 del_timer_sync(&adapter->sfp_timer);
5090 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5091 cancel_work_sync(&adapter->multispeed_fiber_task);
5092 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 5093 iounmap(hw->hw_addr);
5094err_ioremap:
5095 free_netdev(netdev);
5096err_alloc_etherdev:
9ce77666 5097 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5098 IORESOURCE_MEM));
9a799d71
AK		 5099err_pci_reg:
5100err_dma:
5101 pci_disable_device(pdev);
5102 return err;
5103}
5104
5105/**
5106 * ixgbe_remove - Device Removal Routine
5107 * @pdev: PCI device information struct
5108 *
5109 * ixgbe_remove is called by the PCI subsystem to alert the driver
5110 * that it should release a PCI device. The could be caused by a
5111 * Hot-Plug event, or because the driver is going to be removed from
5112 * memory.
5113 **/
5114static void __devexit ixgbe_remove(struct pci_dev *pdev)
5115{
5116 struct net_device *netdev = pci_get_drvdata(pdev);
5117 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715 5118 int err;
9a799d71
AK		 5119
5120 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 5121 /* clear the module not found bit to make sure the worker won't
5122 * reschedule
5123 */
5124 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 5125 del_timer_sync(&adapter->watchdog_timer);
5126
c4900be0
DS		 5127 del_timer_sync(&adapter->sfp_timer);
5128 cancel_work_sync(&adapter->watchdog_task);
5129 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5130 cancel_work_sync(&adapter->multispeed_fiber_task);
5131 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 5132 flush_scheduled_work();
5133
5dd2d332 5134#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5135 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5136 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5137 dca_remove_requester(&pdev->dev);
5138 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5139 }
5140
5141#endif
c4900be0
DS		 5142 if (netdev->reg_state == NETREG_REGISTERED)
5143 unregister_netdev(netdev);
9a799d71 5144
7a921c93 5145 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 5146
021230d4 5147 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5148
5149 iounmap(adapter->hw.hw_addr);
9ce77666 5150 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5151 IORESOURCE_MEM));
9a799d71 5152
021230d4 5153 DPRINTK(PROBE, INFO, "complete\n");
021230d4 5154
9a799d71
AK		 5155 free_netdev(netdev);
5156
6fabd715
PWJ		 5157 err = pci_disable_pcie_error_reporting(pdev);
5158 if (err)
5159 dev_err(&pdev->dev,
5160 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5161
9a799d71
AK		 5162 pci_disable_device(pdev);
5163}
5164
5165/**
5166 * ixgbe_io_error_detected - called when PCI error is detected
5167 * @pdev: Pointer to PCI device
5168 * @state: The current pci connection state
5169 *
5170 * This function is called after a PCI bus error affecting
5171 * this device has been detected.
5172 */
5173static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 5174 pci_channel_state_t state)
9a799d71
AK		 5175{
5176 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5177 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5178
5179 netif_device_detach(netdev);
5180
3044b8d1
BL		 5181 if (state == pci_channel_io_perm_failure)
5182 return PCI_ERS_RESULT_DISCONNECT;
5183
9a799d71
AK		 5184 if (netif_running(netdev))
5185 ixgbe_down(adapter);
5186 pci_disable_device(pdev);
5187
b4617240 5188 /* Request a slot reset. */
9a799d71
AK		 5189 return PCI_ERS_RESULT_NEED_RESET;
5190}
5191
5192/**
5193 * ixgbe_io_slot_reset - called after the pci bus has been reset.
5194 * @pdev: Pointer to PCI device
5195 *
5196 * Restart the card from scratch, as if from a cold-boot.
5197 */
5198static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5199{
5200 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5201 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 5202 pci_ers_result_t result;
5203 int err;
9a799d71 5204
9ce77666 5205 if (pci_enable_device_mem(pdev)) {
9a799d71 5206 DPRINTK(PROBE, ERR,
b4617240 5207 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 5208 result = PCI_ERS_RESULT_DISCONNECT;
5209 } else {
5210 pci_set_master(pdev);
5211 pci_restore_state(pdev);
9a799d71 5212
dd4d8ca6 5213 pci_wake_from_d3(pdev, false);
9a799d71 5214
6fabd715 5215 ixgbe_reset(adapter);
88512539 5216 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 5217 result = PCI_ERS_RESULT_RECOVERED;
5218 }
5219
5220 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5221 if (err) {
5222 dev_err(&pdev->dev,
5223 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5224 /* non-fatal, continue */
5225 }
9a799d71 5226
6fabd715 5227 return result;
9a799d71
AK		 5228}
5229
5230/**
5231 * ixgbe_io_resume - called when traffic can start flowing again.
5232 * @pdev: Pointer to PCI device
5233 *
5234 * This callback is called when the error recovery driver tells us that
5235 * its OK to resume normal operation.
5236 */
5237static void ixgbe_io_resume(struct pci_dev *pdev)
5238{
5239 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5240 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5241
5242 if (netif_running(netdev)) {
5243 if (ixgbe_up(adapter)) {
5244 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5245 return;
5246 }
5247 }
5248
5249 netif_device_attach(netdev);
9a799d71
AK		 5250}
5251
5252static struct pci_error_handlers ixgbe_err_handler = {
5253 .error_detected = ixgbe_io_error_detected,
5254 .slot_reset = ixgbe_io_slot_reset,
5255 .resume = ixgbe_io_resume,
5256};
5257
5258static struct pci_driver ixgbe_driver = {
5259 .name = ixgbe_driver_name,
5260 .id_table = ixgbe_pci_tbl,
5261 .probe = ixgbe_probe,
5262 .remove = __devexit_p(ixgbe_remove),
5263#ifdef CONFIG_PM
5264 .suspend = ixgbe_suspend,
5265 .resume = ixgbe_resume,
5266#endif
5267 .shutdown = ixgbe_shutdown,
5268 .err_handler = &ixgbe_err_handler
5269};
5270
5271/**
5272 * ixgbe_init_module - Driver Registration Routine
5273 *
5274 * ixgbe_init_module is the first routine called when the driver is
5275 * loaded. All it does is register with the PCI subsystem.
5276 **/
5277static int __init ixgbe_init_module(void)
5278{
5279 int ret;
5280 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5281 ixgbe_driver_string, ixgbe_driver_version);
5282
5283 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5284
5dd2d332 5285#ifdef CONFIG_IXGBE_DCA
bd0362dd 5286 dca_register_notify(&dca_notifier);
bd0362dd 5287#endif
5dd2d332 5288
9a799d71
AK		 5289 ret = pci_register_driver(&ixgbe_driver);
5290 return ret;
5291}
b4617240 5292
9a799d71
AK		 5293module_init(ixgbe_init_module);
5294
5295/**
5296 * ixgbe_exit_module - Driver Exit Cleanup Routine
5297 *
5298 * ixgbe_exit_module is called just before the driver is removed
5299 * from memory.
5300 **/
5301static void __exit ixgbe_exit_module(void)
5302{
5dd2d332 5303#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5304 dca_unregister_notify(&dca_notifier);
5305#endif
9a799d71
AK		 5306 pci_unregister_driver(&ixgbe_driver);
5307}
bd0362dd 5308
5dd2d332 5309#ifdef CONFIG_IXGBE_DCA
bd0362dd 5310static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 5311 void *p)
bd0362dd
JC		 5312{
5313 int ret_val;
5314
5315 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 5316 __ixgbe_notify_dca);
bd0362dd
JC		 5317
5318 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5319}
b453368d 5320
5dd2d332 5321#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 5322#ifdef DEBUG
5323/**
5324 * ixgbe_get_hw_dev_name - return device name string
5325 * used by hardware layer to print debugging information
5326 **/
5327char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5328{
5329 struct ixgbe_adapter *adapter = hw->back;
5330 return adapter->netdev->name;
5331}
bd0362dd 5332
b453368d 5333#endif
9a799d71
AK		 5334module_exit(ixgbe_exit_module);
5335
5336/* ixgbe_main.c */
kernel source for telekom puls (alcatel/mediatek)