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igb: set vf rlpml wasn't taking vlan tag into account
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71
AK		 38#include <linux/ipv6.h>
39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
41#include <linux/ethtool.h>
42#include <linux/if_vlan.h>
eacd73f7 43#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 44
45#include "ixgbe.h"
46#include "ixgbe_common.h"
47
48char ixgbe_driver_name[] = "ixgbe";
9c8eb720 49static const char ixgbe_driver_string[] =
b4617240 50 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 51
bbf50e4d 52#define DRV_VERSION "2.0.37-k2"
9c8eb720 53const char ixgbe_driver_version[] = DRV_VERSION;
3efac5a0 54static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
9a799d71
AK		 55
56static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 57 [board_82598] = &ixgbe_82598_info,
e8e26350 58 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 59};
60
61/* ixgbe_pci_tbl - PCI Device ID Table
62 *
63 * Wildcard entries (PCI_ANY_ID) should come last
64 * Last entry must be all 0s
65 *
66 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
67 * Class, Class Mask, private data (not used) }
68 */
69static struct pci_device_id ixgbe_pci_tbl[] = {
1e336d0f
DS		 70 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
71 board_82598 },
9a799d71 72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 73 board_82598 },
9a799d71 74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 75 board_82598 },
0befdb3e
JB		 76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
77 board_82598 },
3845bec0
PWJ		 78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
79 board_82598 },
9a799d71 80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 81 board_82598 },
8d792cd9
JB		 82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
83 board_82598 },
c4900be0
DS		 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
85 board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
87 board_82598 },
b95f5fcb
JB		 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
89 board_82598 },
c4900be0
DS		 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
91 board_82598 },
2f21bdd3
DS		 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
93 board_82598 },
e8e26350
PW		 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
95 board_82599 },
1fcf03e6
PWJ		 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
97 board_82599 },
e8e26350
PW		 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
99 board_82599 },
9a799d71
AK		 100
101 /* required last entry */
102 {0, }
103};
104MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
105
5dd2d332 106#ifdef CONFIG_IXGBE_DCA
bd0362dd 107static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 108 void *p);
bd0362dd
JC		 109static struct notifier_block dca_notifier = {
110 .notifier_call = ixgbe_notify_dca,
111 .next = NULL,
112 .priority = 0
113};
114#endif
115
9a799d71
AK		 116MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
117MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
118MODULE_LICENSE("GPL");
119MODULE_VERSION(DRV_VERSION);
120
121#define DEFAULT_DEBUG_LEVEL_SHIFT 3
122
5eba3699
AV		 123static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
124{
125 u32 ctrl_ext;
126
127 /* Let firmware take over control of h/w */
128 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
129 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 130 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 131}
132
133static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
134{
135 u32 ctrl_ext;
136
137 /* Let firmware know the driver has taken over */
138 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
139 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 140 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 141}
9a799d71 142
e8e26350
PW		 143/*
144 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
145 * @adapter: pointer to adapter struct
146 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
147 * @queue: queue to map the corresponding interrupt to
148 * @msix_vector: the vector to map to the corresponding queue
149 *
150 */
151static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
152 u8 queue, u8 msix_vector)
9a799d71
AK		 153{
154 u32 ivar, index;
e8e26350
PW		 155 struct ixgbe_hw *hw = &adapter->hw;
156 switch (hw->mac.type) {
157 case ixgbe_mac_82598EB:
158 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
159 if (direction == -1)
160 direction = 0;
161 index = (((direction * 64) + queue) >> 2) & 0x1F;
162 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
163 ivar &= ~(0xFF << (8 * (queue & 0x3)));
164 ivar |= (msix_vector << (8 * (queue & 0x3)));
165 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
166 break;
167 case ixgbe_mac_82599EB:
168 if (direction == -1) {
169 /* other causes */
170 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
171 index = ((queue & 1) * 8);
172 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
173 ivar &= ~(0xFF << index);
174 ivar |= (msix_vector << index);
175 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
176 break;
177 } else {
178 /* tx or rx causes */
179 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
180 index = ((16 * (queue & 1)) + (8 * direction));
181 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
182 ivar &= ~(0xFF << index);
183 ivar |= (msix_vector << index);
184 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
185 break;
186 }
187 default:
188 break;
189 }
9a799d71
AK		 190}
191
fe49f04a
AD		 192static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
193 u64 qmask)
194{
195 u32 mask;
196
197 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
198 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
199 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
200 } else {
201 mask = (qmask & 0xFFFFFFFF);
202 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
203 mask = (qmask >> 32);
204 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
205 }
206}
207
9a799d71 208static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 209 struct ixgbe_tx_buffer
210 *tx_buffer_info)
9a799d71 211{
44df32c5 212 tx_buffer_info->dma = 0;
9a799d71 213 if (tx_buffer_info->skb) {
44df32c5
AD		 214 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
215 DMA_TO_DEVICE);
9a799d71
AK		 216 dev_kfree_skb_any(tx_buffer_info->skb);
217 tx_buffer_info->skb = NULL;
218 }
44df32c5 219 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 220 /* tx_buffer_info must be completely set up in the transmit path */
221}
222
223static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 224 struct ixgbe_ring *tx_ring,
225 unsigned int eop)
9a799d71 226{
e01c31a5 227 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 228
9a799d71 229 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 230 * check with the clearing of time_stamp and movement of eop */
9a799d71 231 adapter->detect_tx_hung = false;
44df32c5 232 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 233 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
234 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
235 /* detected Tx unit hang */
e01c31a5
JB		 236 union ixgbe_adv_tx_desc *tx_desc;
237 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 238 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 239 " Tx Queue <%d>\n"
240 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 241 " next_to_use <%x>\n"
242 " next_to_clean <%x>\n"
243 "tx_buffer_info[next_to_clean]\n"
244 " time_stamp <%lx>\n"
e01c31a5
JB		 245 " jiffies <%lx>\n",
246 tx_ring->queue_index,
44df32c5
AD		 247 IXGBE_READ_REG(hw, tx_ring->head),
248 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 249 tx_ring->next_to_use, eop,
250 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 251 return true;
252 }
253
254 return false;
255}
256
b4617240
PW		 257#define IXGBE_MAX_TXD_PWR 14
258#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 259
260/* Tx Descriptors needed, worst case */
261#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
262 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
263#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 264 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 265
e01c31a5
JB		 266static void ixgbe_tx_timeout(struct net_device *netdev);
267
9a799d71
AK		 268/**
269 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 270 * @q_vector: structure containing interrupt and ring information
e01c31a5 271 * @tx_ring: tx ring to clean
9a799d71 272 **/
fe49f04a 273static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e01c31a5 274 struct ixgbe_ring *tx_ring)
9a799d71 275{
fe49f04a 276 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 277 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 278 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
279 struct ixgbe_tx_buffer *tx_buffer_info;
280 unsigned int i, eop, count = 0;
e01c31a5 281 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 282
283 i = tx_ring->next_to_clean;
12207e49
PWJ		 284 eop = tx_ring->tx_buffer_info[i].next_to_watch;
285 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
286
287 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 288 (count < tx_ring->work_limit)) {
12207e49
PWJ		 289 bool cleaned = false;
290 for ( ; !cleaned; count++) {
291 struct sk_buff *skb;
9a799d71
AK		 292 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
293 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 294 cleaned = (i == eop);
e01c31a5 295 skb = tx_buffer_info->skb;
9a799d71 296
12207e49 297 if (cleaned && skb) {
e092be60 298 unsigned int segs, bytecount;
3d8fd385 299 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 300
301 /* gso_segs is currently only valid for tcp */
e092be60 302 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 303#ifdef IXGBE_FCOE
304 /* adjust for FCoE Sequence Offload */
305 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
306 && (skb->protocol == htons(ETH_P_FCOE)) &&
307 skb_is_gso(skb)) {
308 hlen = skb_transport_offset(skb) +
309 sizeof(struct fc_frame_header) +
310 sizeof(struct fcoe_crc_eof);
311 segs = DIV_ROUND_UP(skb->len - hlen,
312 skb_shinfo(skb)->gso_size);
313 }
314#endif /* IXGBE_FCOE */
e092be60 315 /* multiply data chunks by size of headers */
3d8fd385 316 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 317 total_packets += segs;
318 total_bytes += bytecount;
e092be60 319 }
e01c31a5 320
9a799d71 321 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 322 tx_buffer_info);
9a799d71 323
12207e49
PWJ		 324 tx_desc->wb.status = 0;
325
9a799d71
AK		 326 i++;
327 if (i == tx_ring->count)
328 i = 0;
e01c31a5 329 }
12207e49
PWJ		 330
331 eop = tx_ring->tx_buffer_info[i].next_to_watch;
332 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
333 }
334
9a799d71
AK		 335 tx_ring->next_to_clean = i;
336
e092be60 337#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 338 if (unlikely(count && netif_carrier_ok(netdev) &&
339 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 340 /* Make sure that anybody stopping the queue after this
341 * sees the new next_to_clean.
342 */
343 smp_mb();
30eba97a
AV		 344 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
345 !test_bit(__IXGBE_DOWN, &adapter->state)) {
346 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 347 ++adapter->restart_queue;
30eba97a 348 }
e092be60 349 }
9a799d71 350
e01c31a5
JB		 351 if (adapter->detect_tx_hung) {
352 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
353 /* schedule immediate reset if we believe we hung */
354 DPRINTK(PROBE, INFO,
355 "tx hang %d detected, resetting adapter\n",
356 adapter->tx_timeout_count + 1);
357 ixgbe_tx_timeout(adapter->netdev);
358 }
359 }
9a799d71 360
e01c31a5 361 /* re-arm the interrupt */
fe49f04a
AD		 362 if (count >= tx_ring->work_limit)
363 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 364
e01c31a5
JB		 365 tx_ring->total_bytes += total_bytes;
366 tx_ring->total_packets += total_packets;
e01c31a5 367 tx_ring->stats.packets += total_packets;
12207e49 368 tx_ring->stats.bytes += total_bytes;
e01c31a5
JB		 369 adapter->net_stats.tx_bytes += total_bytes;
370 adapter->net_stats.tx_packets += total_packets;
9a1a69ad 371 return (count < tx_ring->work_limit);
9a799d71
AK		 372}
373
5dd2d332 374#ifdef CONFIG_IXGBE_DCA
bd0362dd 375static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 376 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 377{
378 u32 rxctrl;
379 int cpu = get_cpu();
3a581073 380 int q = rx_ring - adapter->rx_ring;
bd0362dd 381
3a581073 382 if (rx_ring->cpu != cpu) {
bd0362dd 383 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 384 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
385 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
386 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
387 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
388 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
389 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
390 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
391 }
bd0362dd
JC		 392 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
393 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 394 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
395 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 396 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 397 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 398 rx_ring->cpu = cpu;
bd0362dd
JC		 399 }
400 put_cpu();
401}
402
403static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 404 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 405{
406 u32 txctrl;
407 int cpu = get_cpu();
3a581073 408 int q = tx_ring - adapter->tx_ring;
bd0362dd 409
3a581073 410 if (tx_ring->cpu != cpu) {
bd0362dd 411 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 412 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
413 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
414 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
415 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
416 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
417 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
418 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
419 }
bd0362dd
JC		 420 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
421 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 422 tx_ring->cpu = cpu;
bd0362dd
JC		 423 }
424 put_cpu();
425}
426
427static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
428{
429 int i;
430
431 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
432 return;
433
e35ec126
AD		 434 /* always use CB2 mode, difference is masked in the CB driver */
435 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
436
bd0362dd
JC		 437 for (i = 0; i < adapter->num_tx_queues; i++) {
438 adapter->tx_ring[i].cpu = -1;
439 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
440 }
441 for (i = 0; i < adapter->num_rx_queues; i++) {
442 adapter->rx_ring[i].cpu = -1;
443 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
444 }
445}
446
447static int __ixgbe_notify_dca(struct device *dev, void *data)
448{
449 struct net_device *netdev = dev_get_drvdata(dev);
450 struct ixgbe_adapter *adapter = netdev_priv(netdev);
451 unsigned long event = *(unsigned long *)data;
452
453 switch (event) {
454 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 455 /* if we're already enabled, don't do it again */
456 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
457 break;
652f093f 458 if (dca_add_requester(dev) == 0) {
96b0e0f6 459 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 460 ixgbe_setup_dca(adapter);
461 break;
462 }
463 /* Fall Through since DCA is disabled. */
464 case DCA_PROVIDER_REMOVE:
465 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
466 dca_remove_requester(dev);
467 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
468 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
469 }
470 break;
471 }
472
652f093f 473 return 0;
bd0362dd
JC		 474}
475
5dd2d332 476#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 477/**
478 * ixgbe_receive_skb - Send a completed packet up the stack
479 * @adapter: board private structure
480 * @skb: packet to send up
177db6ff
MC		 481 * @status: hardware indication of status of receive
482 * @rx_ring: rx descriptor ring (for a specific queue) to setup
483 * @rx_desc: rx descriptor
9a799d71 484 **/
78b6f4ce 485static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 486 struct sk_buff *skb, u8 status,
fdaff1ce 487 struct ixgbe_ring *ring,
177db6ff 488 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 489{
78b6f4ce
HX		 490 struct ixgbe_adapter *adapter = q_vector->adapter;
491 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 492 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
493 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 494
fdaff1ce 495 skb_record_rx_queue(skb, ring->queue_index);
182ff8df 496 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
8a62babf 497 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
78b6f4ce 498 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 499 else
78b6f4ce 500 napi_gro_receive(napi, skb);
177db6ff 501 } else {
8a62babf 502 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
182ff8df
AD		 503 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
504 else
505 netif_rx(skb);
9a799d71
AK		 506 }
507}
508
e59bd25d
AV		 509/**
510 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
511 * @adapter: address of board private structure
512 * @status_err: hardware indication of status of receive
513 * @skb: skb currently being received and modified
514 **/
9a799d71 515static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 516 union ixgbe_adv_rx_desc *rx_desc,
517 struct sk_buff *skb)
9a799d71 518{
8bae1b2b
DS		 519 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
520
9a799d71
AK		 521 skb->ip_summed = CHECKSUM_NONE;
522
712744be
JB		 523 /* Rx csum disabled */
524 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 525 return;
e59bd25d
AV		 526
527 /* if IP and error */
528 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
529 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 530 adapter->hw_csum_rx_error++;
531 return;
532 }
e59bd25d
AV		 533
534 if (!(status_err & IXGBE_RXD_STAT_L4CS))
535 return;
536
537 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 538 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
539
540 /*
541 * 82599 errata, UDP frames with a 0 checksum can be marked as
542 * checksum errors.
543 */
544 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
545 (adapter->hw.mac.type == ixgbe_mac_82599EB))
546 return;
547
e59bd25d
AV		 548 adapter->hw_csum_rx_error++;
549 return;
550 }
551
9a799d71 552 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 553 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 554 adapter->hw_csum_rx_good++;
555}
556
e8e26350
PW		 557static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
558 struct ixgbe_ring *rx_ring, u32 val)
559{
560 /*
561 * Force memory writes to complete before letting h/w
562 * know there are new descriptors to fetch. (Only
563 * applicable for weak-ordered memory model archs,
564 * such as IA-64).
565 */
566 wmb();
567 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
568}
569
9a799d71
AK		 570/**
571 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
572 * @adapter: address of board private structure
573 **/
574static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 575 struct ixgbe_ring *rx_ring,
576 int cleaned_count)
9a799d71 577{
9a799d71
AK		 578 struct pci_dev *pdev = adapter->pdev;
579 union ixgbe_adv_rx_desc *rx_desc;
3a581073 580 struct ixgbe_rx_buffer *bi;
9a799d71 581 unsigned int i;
9a799d71
AK		 582
583 i = rx_ring->next_to_use;
3a581073 584 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 585
586 while (cleaned_count--) {
587 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
588
762f4c57 589 if (!bi->page_dma &&
6e455b89 590 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 591 if (!bi->page) {
762f4c57
JB		 592 bi->page = alloc_page(GFP_ATOMIC);
593 if (!bi->page) {
594 adapter->alloc_rx_page_failed++;
595 goto no_buffers;
596 }
597 bi->page_offset = 0;
598 } else {
599 /* use a half page if we're re-using */
600 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 601 }
762f4c57
JB		 602
603 bi->page_dma = pci_map_page(pdev, bi->page,
604 bi->page_offset,
605 (PAGE_SIZE / 2),
606 PCI_DMA_FROMDEVICE);
9a799d71
AK		 607 }
608
3a581073 609 if (!bi->skb) {
5ecc3614 610 struct sk_buff *skb;
4f57ca6e
JB		 611 skb = netdev_alloc_skb(adapter->netdev,
612 (rx_ring->rx_buf_len +
613 NET_IP_ALIGN));
9a799d71
AK		 614
615 if (!skb) {
616 adapter->alloc_rx_buff_failed++;
617 goto no_buffers;
618 }
619
620 /*
621 * Make buffer alignment 2 beyond a 16 byte boundary
622 * this will result in a 16 byte aligned IP header after
623 * the 14 byte MAC header is removed
624 */
625 skb_reserve(skb, NET_IP_ALIGN);
626
3a581073 627 bi->skb = skb;
4f57ca6e
JB		 628 bi->dma = pci_map_single(pdev, skb->data,
629 rx_ring->rx_buf_len,
3a581073 630 PCI_DMA_FROMDEVICE);
9a799d71
AK		 631 }
632 /* Refresh the desc even if buffer_addrs didn't change because
633 * each write-back erases this info. */
6e455b89 634 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 635 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
636 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 637 } else {
3a581073 638 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 639 }
640
641 i++;
642 if (i == rx_ring->count)
643 i = 0;
3a581073 644 bi = &rx_ring->rx_buffer_info[i];
9a799d71 645 }
7c6e0a43 646
9a799d71
AK		 647no_buffers:
648 if (rx_ring->next_to_use != i) {
649 rx_ring->next_to_use = i;
650 if (i-- == 0)
651 i = (rx_ring->count - 1);
652
e8e26350 653 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 654 }
655}
656
7c6e0a43
JB		 657static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
658{
659 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
660}
661
662static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
663{
664 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
665}
666
f8212f97
AD		 667static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
668{
669 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
670 IXGBE_RXDADV_RSCCNT_MASK) >>
671 IXGBE_RXDADV_RSCCNT_SHIFT;
672}
673
674/**
675 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
676 * @skb: pointer to the last skb in the rsc queue
677 *
678 * This function changes a queue full of hw rsc buffers into a completed
679 * packet. It uses the ->prev pointers to find the first packet and then
680 * turns it into the frag list owner.
681 **/
682static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
683{
684 unsigned int frag_list_size = 0;
685
686 while (skb->prev) {
687 struct sk_buff *prev = skb->prev;
688 frag_list_size += skb->len;
689 skb->prev = NULL;
690 skb = prev;
691 }
692
693 skb_shinfo(skb)->frag_list = skb->next;
694 skb->next = NULL;
695 skb->len += frag_list_size;
696 skb->data_len += frag_list_size;
697 skb->truesize += frag_list_size;
698 return skb;
699}
700
78b6f4ce 701static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 702 struct ixgbe_ring *rx_ring,
703 int *work_done, int work_to_do)
9a799d71 704{
78b6f4ce 705 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 706 struct pci_dev *pdev = adapter->pdev;
707 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
708 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
709 struct sk_buff *skb;
f8212f97 710 unsigned int i, rsc_count = 0;
7c6e0a43 711 u32 len, staterr;
177db6ff
MC		 712 u16 hdr_info;
713 bool cleaned = false;
9a799d71 714 int cleaned_count = 0;
d2f4fbe2 715 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 716#ifdef IXGBE_FCOE
717 int ddp_bytes = 0;
718#endif /* IXGBE_FCOE */
9a799d71
AK		 719
720 i = rx_ring->next_to_clean;
9a799d71
AK		 721 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
722 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
723 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 724
725 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 726 u32 upper_len = 0;
9a799d71
AK		 727 if (*work_done >= work_to_do)
728 break;
729 (*work_done)++;
730
6e455b89 731 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 732 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
733 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 734 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 735 if (hdr_info & IXGBE_RXDADV_SPH)
736 adapter->rx_hdr_split++;
737 if (len > IXGBE_RX_HDR_SIZE)
738 len = IXGBE_RX_HDR_SIZE;
739 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 740 } else {
9a799d71 741 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 742 }
9a799d71
AK		 743
744 cleaned = true;
745 skb = rx_buffer_info->skb;
746 prefetch(skb->data - NET_IP_ALIGN);
747 rx_buffer_info->skb = NULL;
748
21fa4e66 749 if (rx_buffer_info->dma) {
9a799d71 750 pci_unmap_single(pdev, rx_buffer_info->dma,
5ecc3614 751 rx_ring->rx_buf_len,
b4617240 752 PCI_DMA_FROMDEVICE);
4f57ca6e 753 rx_buffer_info->dma = 0;
9a799d71
AK		 754 skb_put(skb, len);
755 }
756
757 if (upper_len) {
758 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 759 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 760 rx_buffer_info->page_dma = 0;
761 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 762 rx_buffer_info->page,
763 rx_buffer_info->page_offset,
764 upper_len);
765
766 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
767 (page_count(rx_buffer_info->page) != 1))
768 rx_buffer_info->page = NULL;
769 else
770 get_page(rx_buffer_info->page);
9a799d71
AK		 771
772 skb->len += upper_len;
773 skb->data_len += upper_len;
774 skb->truesize += upper_len;
775 }
776
777 i++;
778 if (i == rx_ring->count)
779 i = 0;
9a799d71
AK		 780
781 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
782 prefetch(next_rxd);
9a799d71 783 cleaned_count++;
f8212f97 784
0c19d6af 785 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 786 rsc_count = ixgbe_get_rsc_count(rx_desc);
787
788 if (rsc_count) {
789 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
790 IXGBE_RXDADV_NEXTP_SHIFT;
791 next_buffer = &rx_ring->rx_buffer_info[nextp];
792 rx_ring->rsc_count += (rsc_count - 1);
793 } else {
794 next_buffer = &rx_ring->rx_buffer_info[i];
795 }
796
9a799d71 797 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97
AD		 798 if (skb->prev)
799 skb = ixgbe_transform_rsc_queue(skb);
9a799d71
AK		 800 rx_ring->stats.packets++;
801 rx_ring->stats.bytes += skb->len;
802 } else {
6e455b89 803 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 804 rx_buffer_info->skb = next_buffer->skb;
805 rx_buffer_info->dma = next_buffer->dma;
806 next_buffer->skb = skb;
807 next_buffer->dma = 0;
808 } else {
809 skb->next = next_buffer->skb;
810 skb->next->prev = skb;
811 }
9a799d71
AK		 812 adapter->non_eop_descs++;
813 goto next_desc;
814 }
815
816 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
817 dev_kfree_skb_irq(skb);
818 goto next_desc;
819 }
820
8bae1b2b 821 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 822
823 /* probably a little skewed due to removing CRC */
824 total_rx_bytes += skb->len;
825 total_rx_packets++;
826
74ce8dd2 827 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 828#ifdef IXGBE_FCOE
829 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 830 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
831 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
832 if (!ddp_bytes)
332d4a7d 833 goto next_desc;
3d8fd385 834 }
332d4a7d 835#endif /* IXGBE_FCOE */
fdaff1ce 836 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 837
838next_desc:
839 rx_desc->wb.upper.status_error = 0;
840
841 /* return some buffers to hardware, one at a time is too slow */
842 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
843 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
844 cleaned_count = 0;
845 }
846
847 /* use prefetched values */
848 rx_desc = next_rxd;
f8212f97 849 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 850
851 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 852 }
853
9a799d71
AK		 854 rx_ring->next_to_clean = i;
855 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
856
857 if (cleaned_count)
858 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
859
3d8fd385
YZ		 860#ifdef IXGBE_FCOE
861 /* include DDPed FCoE data */
862 if (ddp_bytes > 0) {
863 unsigned int mss;
864
865 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
866 sizeof(struct fc_frame_header) -
867 sizeof(struct fcoe_crc_eof);
868 if (mss > 512)
869 mss &= ~511;
870 total_rx_bytes += ddp_bytes;
871 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
872 }
873#endif /* IXGBE_FCOE */
874
f494e8fa
AV		 875 rx_ring->total_packets += total_rx_packets;
876 rx_ring->total_bytes += total_rx_bytes;
877 adapter->net_stats.rx_bytes += total_rx_bytes;
878 adapter->net_stats.rx_packets += total_rx_packets;
879
9a799d71
AK		 880 return cleaned;
881}
882
021230d4 883static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 884/**
885 * ixgbe_configure_msix - Configure MSI-X hardware
886 * @adapter: board private structure
887 *
888 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
889 * interrupts.
890 **/
891static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
892{
021230d4
AV		 893 struct ixgbe_q_vector *q_vector;
894 int i, j, q_vectors, v_idx, r_idx;
895 u32 mask;
9a799d71 896
021230d4 897 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 898
4df10466
JB		 899 /*
900 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 901 * corresponding register.
902 */
903 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 904 q_vector = adapter->q_vector[v_idx];
021230d4
AV		 905 /* XXX for_each_bit(...) */
906 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 907 adapter->num_rx_queues);
021230d4
AV		 908
909 for (i = 0; i < q_vector->rxr_count; i++) {
910 j = adapter->rx_ring[r_idx].reg_idx;
e8e26350 911 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 912 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 913 adapter->num_rx_queues,
914 r_idx + 1);
021230d4
AV		 915 }
916 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 917 adapter->num_tx_queues);
021230d4
AV		 918
919 for (i = 0; i < q_vector->txr_count; i++) {
920 j = adapter->tx_ring[r_idx].reg_idx;
e8e26350 921 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 922 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 923 adapter->num_tx_queues,
924 r_idx + 1);
021230d4
AV		 925 }
926
30efa5a3 927 /* if this is a tx only vector halve the interrupt rate */
021230d4 928 if (q_vector->txr_count && !q_vector->rxr_count)
30efa5a3 929 q_vector->eitr = (adapter->eitr_param >> 1);
509ee935 930 else if (q_vector->rxr_count)
30efa5a3
JB		 931 /* rx only */
932 q_vector->eitr = adapter->eitr_param;
021230d4 933
fe49f04a 934 ixgbe_write_eitr(q_vector);
9a799d71
AK		 935 }
936
e8e26350
PW		 937 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
938 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
939 v_idx);
940 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
941 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 942 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
943
41fb9248 944 /* set up to autoclear timer, and the vectors */
021230d4 945 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 946 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 947 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 948}
949
f494e8fa
AV		 950enum latency_range {
951 lowest_latency = 0,
952 low_latency = 1,
953 bulk_latency = 2,
954 latency_invalid = 255
955};
956
957/**
958 * ixgbe_update_itr - update the dynamic ITR value based on statistics
959 * @adapter: pointer to adapter
960 * @eitr: eitr setting (ints per sec) to give last timeslice
961 * @itr_setting: current throttle rate in ints/second
962 * @packets: the number of packets during this measurement interval
963 * @bytes: the number of bytes during this measurement interval
964 *
965 * Stores a new ITR value based on packets and byte
966 * counts during the last interrupt. The advantage of per interrupt
967 * computation is faster updates and more accurate ITR for the current
968 * traffic pattern. Constants in this function were computed
969 * based on theoretical maximum wire speed and thresholds were set based
970 * on testing data as well as attempting to minimize response time
971 * while increasing bulk throughput.
972 * this functionality is controlled by the InterruptThrottleRate module
973 * parameter (see ixgbe_param.c)
974 **/
975static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 976 u32 eitr, u8 itr_setting,
977 int packets, int bytes)
f494e8fa
AV		 978{
979 unsigned int retval = itr_setting;
980 u32 timepassed_us;
981 u64 bytes_perint;
982
983 if (packets == 0)
984 goto update_itr_done;
985
986
987 /* simple throttlerate management
988 * 0-20MB/s lowest (100000 ints/s)
989 * 20-100MB/s low (20000 ints/s)
990 * 100-1249MB/s bulk (8000 ints/s)
991 */
992 /* what was last interrupt timeslice? */
993 timepassed_us = 1000000/eitr;
994 bytes_perint = bytes / timepassed_us; /* bytes/usec */
995
996 switch (itr_setting) {
997 case lowest_latency:
998 if (bytes_perint > adapter->eitr_low)
999 retval = low_latency;
1000 break;
1001 case low_latency:
1002 if (bytes_perint > adapter->eitr_high)
1003 retval = bulk_latency;
1004 else if (bytes_perint <= adapter->eitr_low)
1005 retval = lowest_latency;
1006 break;
1007 case bulk_latency:
1008 if (bytes_perint <= adapter->eitr_high)
1009 retval = low_latency;
1010 break;
1011 }
1012
1013update_itr_done:
1014 return retval;
1015}
1016
509ee935
JB		 1017/**
1018 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1019 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1020 *
1021 * This function is made to be called by ethtool and by the driver
1022 * when it needs to update EITR registers at runtime. Hardware
1023 * specific quirks/differences are taken care of here.
1024 */
fe49f04a 1025void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1026{
fe49f04a 1027 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1028 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1029 int v_idx = q_vector->v_idx;
1030 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1031
509ee935
JB		 1032 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1033 /* must write high and low 16 bits to reset counter */
1034 itr_reg |= (itr_reg << 16);
1035 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1036 /*
1037 * set the WDIS bit to not clear the timer bits and cause an
1038 * immediate assertion of the interrupt
1039 */
1040 itr_reg |= IXGBE_EITR_CNT_WDIS;
1041 }
1042 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1043}
1044
f494e8fa
AV		 1045static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1046{
1047 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1048 u32 new_itr;
1049 u8 current_itr, ret_itr;
fe49f04a 1050 int i, r_idx;
f494e8fa
AV		 1051 struct ixgbe_ring *rx_ring, *tx_ring;
1052
1053 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1054 for (i = 0; i < q_vector->txr_count; i++) {
1055 tx_ring = &(adapter->tx_ring[r_idx]);
1056 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1057 q_vector->tx_itr,
1058 tx_ring->total_packets,
1059 tx_ring->total_bytes);
f494e8fa
AV		 1060 /* if the result for this queue would decrease interrupt
1061 * rate for this vector then use that result */
30efa5a3 1062 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1063 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1064 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1065 r_idx + 1);
f494e8fa
AV		 1066 }
1067
1068 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1069 for (i = 0; i < q_vector->rxr_count; i++) {
1070 rx_ring = &(adapter->rx_ring[r_idx]);
1071 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1072 q_vector->rx_itr,
1073 rx_ring->total_packets,
1074 rx_ring->total_bytes);
f494e8fa
AV		 1075 /* if the result for this queue would decrease interrupt
1076 * rate for this vector then use that result */
30efa5a3 1077 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1078 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1079 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1080 r_idx + 1);
f494e8fa
AV		 1081 }
1082
30efa5a3 1083 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1084
1085 switch (current_itr) {
1086 /* counts and packets in update_itr are dependent on these numbers */
1087 case lowest_latency:
1088 new_itr = 100000;
1089 break;
1090 case low_latency:
1091 new_itr = 20000; /* aka hwitr = ~200 */
1092 break;
1093 case bulk_latency:
1094 default:
1095 new_itr = 8000;
1096 break;
1097 }
1098
1099 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1100 /* do an exponential smoothing */
1101 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1102
1103 /* save the algorithm value here, not the smoothed one */
1104 q_vector->eitr = new_itr;
fe49f04a
AD		 1105
1106 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1107 }
1108
1109 return;
1110}
1111
0befdb3e
JB		 1112static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1113{
1114 struct ixgbe_hw *hw = &adapter->hw;
1115
1116 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1117 (eicr & IXGBE_EICR_GPI_SDP1)) {
1118 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1119 /* write to clear the interrupt */
1120 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1121 }
1122}
cf8280ee 1123
e8e26350
PW		 1124static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1125{
1126 struct ixgbe_hw *hw = &adapter->hw;
1127
1128 if (eicr & IXGBE_EICR_GPI_SDP1) {
1129 /* Clear the interrupt */
1130 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1131 schedule_work(&adapter->multispeed_fiber_task);
1132 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1133 /* Clear the interrupt */
1134 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1135 schedule_work(&adapter->sfp_config_module_task);
1136 } else {
1137 /* Interrupt isn't for us... */
1138 return;
1139 }
1140}
1141
cf8280ee
JB		 1142static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1143{
1144 struct ixgbe_hw *hw = &adapter->hw;
1145
1146 adapter->lsc_int++;
1147 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1148 adapter->link_check_timeout = jiffies;
1149 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1150 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1151 schedule_work(&adapter->watchdog_task);
1152 }
1153}
1154
9a799d71
AK		 1155static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1156{
1157 struct net_device *netdev = data;
1158 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1159 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1160 u32 eicr;
1161
1162 /*
1163 * Workaround for Silicon errata. Use clear-by-write instead
1164 * of clear-by-read. Reading with EICS will return the
1165 * interrupt causes without clearing, which later be done
1166 * with the write to EICR.
1167 */
1168 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1169 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1170
cf8280ee
JB		 1171 if (eicr & IXGBE_EICR_LSC)
1172 ixgbe_check_lsc(adapter);
d4f80882 1173
e8e26350
PW		 1174 if (hw->mac.type == ixgbe_mac_82598EB)
1175 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1176
c4cf55e5 1177 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1178 ixgbe_check_sfp_event(adapter, eicr);
c4cf55e5
PWJ		 1179
1180 /* Handle Flow Director Full threshold interrupt */
1181 if (eicr & IXGBE_EICR_FLOW_DIR) {
1182 int i;
1183 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1184 /* Disable transmits before FDIR Re-initialization */
1185 netif_tx_stop_all_queues(netdev);
1186 for (i = 0; i < adapter->num_tx_queues; i++) {
1187 struct ixgbe_ring *tx_ring =
1188 &adapter->tx_ring[i];
1189 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1190 &tx_ring->reinit_state))
1191 schedule_work(&adapter->fdir_reinit_task);
1192 }
1193 }
1194 }
d4f80882
AV		 1195 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1196 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1197
1198 return IRQ_HANDLED;
1199}
1200
fe49f04a
AD		 1201static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1202 u64 qmask)
1203{
1204 u32 mask;
1205
1206 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1207 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1208 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1209 } else {
1210 mask = (qmask & 0xFFFFFFFF);
1211 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1212 mask = (qmask >> 32);
1213 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1214 }
1215 /* skip the flush */
1216}
1217
1218static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1219 u64 qmask)
1220{
1221 u32 mask;
1222
1223 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1224 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1225 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1226 } else {
1227 mask = (qmask & 0xFFFFFFFF);
1228 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1229 mask = (qmask >> 32);
1230 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1231 }
1232 /* skip the flush */
1233}
1234
9a799d71
AK		 1235static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1236{
021230d4
AV		 1237 struct ixgbe_q_vector *q_vector = data;
1238 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1239 struct ixgbe_ring *tx_ring;
021230d4
AV		 1240 int i, r_idx;
1241
1242 if (!q_vector->txr_count)
1243 return IRQ_HANDLED;
1244
1245 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1246 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 1247 tx_ring = &(adapter->tx_ring[r_idx]);
3a581073
JB		 1248 tx_ring->total_bytes = 0;
1249 tx_ring->total_packets = 0;
021230d4 1250 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1251 r_idx + 1);
021230d4 1252 }
9a799d71 1253
91281fd3
AD		 1254 /* disable interrupts on this vector only */
1255 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1256 napi_schedule(&q_vector->napi);
1257
9a799d71
AK		 1258 return IRQ_HANDLED;
1259}
1260
021230d4
AV		 1261/**
1262 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1263 * @irq: unused
1264 * @data: pointer to our q_vector struct for this interrupt vector
1265 **/
9a799d71
AK		 1266static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1267{
021230d4
AV		 1268 struct ixgbe_q_vector *q_vector = data;
1269 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1270 struct ixgbe_ring *rx_ring;
021230d4 1271 int r_idx;
30efa5a3 1272 int i;
021230d4
AV		 1273
1274 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 1275 for (i = 0; i < q_vector->rxr_count; i++) {
1276 rx_ring = &(adapter->rx_ring[r_idx]);
1277 rx_ring->total_bytes = 0;
1278 rx_ring->total_packets = 0;
1279 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1280 r_idx + 1);
1281 }
1282
021230d4
AV		 1283 if (!q_vector->rxr_count)
1284 return IRQ_HANDLED;
1285
30efa5a3 1286 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1287 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 1288 /* disable interrupts on this vector only */
fe49f04a 1289 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
288379f0 1290 napi_schedule(&q_vector->napi);
021230d4
AV		 1291
1292 return IRQ_HANDLED;
1293}
1294
1295static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1296{
91281fd3
AD		 1297 struct ixgbe_q_vector *q_vector = data;
1298 struct ixgbe_adapter *adapter = q_vector->adapter;
1299 struct ixgbe_ring *ring;
1300 int r_idx;
1301 int i;
1302
1303 if (!q_vector->txr_count && !q_vector->rxr_count)
1304 return IRQ_HANDLED;
1305
1306 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1307 for (i = 0; i < q_vector->txr_count; i++) {
1308 ring = &(adapter->tx_ring[r_idx]);
1309 ring->total_bytes = 0;
1310 ring->total_packets = 0;
1311 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1312 r_idx + 1);
1313 }
1314
1315 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1316 for (i = 0; i < q_vector->rxr_count; i++) {
1317 ring = &(adapter->rx_ring[r_idx]);
1318 ring->total_bytes = 0;
1319 ring->total_packets = 0;
1320 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1321 r_idx + 1);
1322 }
1323
1324 /* disable interrupts on this vector only */
1325 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1326 napi_schedule(&q_vector->napi);
9a799d71 1327
9a799d71
AK		 1328 return IRQ_HANDLED;
1329}
1330
021230d4
AV		 1331/**
1332 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1333 * @napi: napi struct with our devices info in it
1334 * @budget: amount of work driver is allowed to do this pass, in packets
1335 *
f0848276
JB		 1336 * This function is optimized for cleaning one queue only on a single
1337 * q_vector!!!
021230d4 1338 **/
9a799d71
AK		 1339static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1340{
021230d4 1341 struct ixgbe_q_vector *q_vector =
b4617240 1342 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1343 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1344 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1345 int work_done = 0;
021230d4 1346 long r_idx;
9a799d71 1347
021230d4 1348 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1349 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1350#ifdef CONFIG_IXGBE_DCA
bd0362dd 1351 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1352 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1353#endif
9a799d71 1354
78b6f4ce 1355 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1356
021230d4
AV		 1357 /* If all Rx work done, exit the polling mode */
1358 if (work_done < budget) {
288379f0 1359 napi_complete(napi);
509ee935 1360 if (adapter->itr_setting & 1)
f494e8fa 1361 ixgbe_set_itr_msix(q_vector);
9a799d71 1362 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1363 ixgbe_irq_enable_queues(adapter,
1364 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1365 }
1366
1367 return work_done;
1368}
1369
f0848276 1370/**
91281fd3 1371 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1372 * @napi: napi struct with our devices info in it
1373 * @budget: amount of work driver is allowed to do this pass, in packets
1374 *
1375 * This function will clean more than one rx queue associated with a
1376 * q_vector.
1377 **/
91281fd3 1378static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1379{
1380 struct ixgbe_q_vector *q_vector =
1381 container_of(napi, struct ixgbe_q_vector, napi);
1382 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1383 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1384 int work_done = 0, i;
1385 long r_idx;
91281fd3
AD		 1386 bool tx_clean_complete = true;
1387
1388 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1389 for (i = 0; i < q_vector->txr_count; i++) {
1390 ring = &(adapter->tx_ring[r_idx]);
1391#ifdef CONFIG_IXGBE_DCA
1392 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1393 ixgbe_update_tx_dca(adapter, ring);
1394#endif
1395 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1396 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1397 r_idx + 1);
1398 }
f0848276
JB		 1399
1400 /* attempt to distribute budget to each queue fairly, but don't allow
1401 * the budget to go below 1 because we'll exit polling */
1402 budget /= (q_vector->rxr_count ?: 1);
1403 budget = max(budget, 1);
1404 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1405 for (i = 0; i < q_vector->rxr_count; i++) {
91281fd3 1406 ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1407#ifdef CONFIG_IXGBE_DCA
f0848276 1408 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1409 ixgbe_update_rx_dca(adapter, ring);
f0848276 1410#endif
91281fd3 1411 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276
JB		 1412 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1413 r_idx + 1);
1414 }
1415
1416 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
91281fd3 1417 ring = &(adapter->rx_ring[r_idx]);
f0848276 1418 /* If all Rx work done, exit the polling mode */
7f821875 1419 if (work_done < budget) {
288379f0 1420 napi_complete(napi);
509ee935 1421 if (adapter->itr_setting & 1)
f0848276
JB		 1422 ixgbe_set_itr_msix(q_vector);
1423 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1424 ixgbe_irq_enable_queues(adapter,
1425 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1426 return 0;
1427 }
1428
1429 return work_done;
1430}
91281fd3
AD		 1431
1432/**
1433 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1434 * @napi: napi struct with our devices info in it
1435 * @budget: amount of work driver is allowed to do this pass, in packets
1436 *
1437 * This function is optimized for cleaning one queue only on a single
1438 * q_vector!!!
1439 **/
1440static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1441{
1442 struct ixgbe_q_vector *q_vector =
1443 container_of(napi, struct ixgbe_q_vector, napi);
1444 struct ixgbe_adapter *adapter = q_vector->adapter;
1445 struct ixgbe_ring *tx_ring = NULL;
1446 int work_done = 0;
1447 long r_idx;
1448
1449 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1450 tx_ring = &(adapter->tx_ring[r_idx]);
1451#ifdef CONFIG_IXGBE_DCA
1452 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1453 ixgbe_update_tx_dca(adapter, tx_ring);
1454#endif
1455
1456 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1457 work_done = budget;
1458
1459 /* If all Rx work done, exit the polling mode */
1460 if (work_done < budget) {
1461 napi_complete(napi);
1462 if (adapter->itr_setting & 1)
1463 ixgbe_set_itr_msix(q_vector);
1464 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1465 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1466 }
1467
1468 return work_done;
1469}
1470
021230d4 1471static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1472 int r_idx)
021230d4 1473{
7a921c93
AD		 1474 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1475
1476 set_bit(r_idx, q_vector->rxr_idx);
1477 q_vector->rxr_count++;
021230d4
AV		 1478}
1479
1480static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 1481 int t_idx)
021230d4 1482{
7a921c93
AD		 1483 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1484
1485 set_bit(t_idx, q_vector->txr_idx);
1486 q_vector->txr_count++;
021230d4
AV		 1487}
1488
9a799d71 1489/**
021230d4
AV		 1490 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1491 * @adapter: board private structure to initialize
1492 * @vectors: allotted vector count for descriptor rings
9a799d71 1493 *
021230d4
AV		 1494 * This function maps descriptor rings to the queue-specific vectors
1495 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1496 * one vector per ring/queue, but on a constrained vector budget, we
1497 * group the rings as "efficiently" as possible. You would add new
1498 * mapping configurations in here.
9a799d71 1499 **/
021230d4 1500static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1501 int vectors)
021230d4
AV		 1502{
1503 int v_start = 0;
1504 int rxr_idx = 0, txr_idx = 0;
1505 int rxr_remaining = adapter->num_rx_queues;
1506 int txr_remaining = adapter->num_tx_queues;
1507 int i, j;
1508 int rqpv, tqpv;
1509 int err = 0;
1510
1511 /* No mapping required if MSI-X is disabled. */
1512 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1513 goto out;
9a799d71 1514
021230d4
AV		 1515 /*
1516 * The ideal configuration...
1517 * We have enough vectors to map one per queue.
1518 */
1519 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1520 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1521 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1522
021230d4
AV		 1523 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1524 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1525
9a799d71 1526 goto out;
021230d4 1527 }
9a799d71 1528
021230d4
AV		 1529 /*
1530 * If we don't have enough vectors for a 1-to-1
1531 * mapping, we'll have to group them so there are
1532 * multiple queues per vector.
1533 */
1534 /* Re-adjusting *qpv takes care of the remainder. */
1535 for (i = v_start; i < vectors; i++) {
1536 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1537 for (j = 0; j < rqpv; j++) {
1538 map_vector_to_rxq(adapter, i, rxr_idx);
1539 rxr_idx++;
1540 rxr_remaining--;
1541 }
1542 }
1543 for (i = v_start; i < vectors; i++) {
1544 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1545 for (j = 0; j < tqpv; j++) {
1546 map_vector_to_txq(adapter, i, txr_idx);
1547 txr_idx++;
1548 txr_remaining--;
9a799d71 1549 }
9a799d71
AK		 1550 }
1551
021230d4
AV		 1552out:
1553 return err;
1554}
1555
1556/**
1557 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1558 * @adapter: board private structure
1559 *
1560 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1561 * interrupts from the kernel.
1562 **/
1563static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1564{
1565 struct net_device *netdev = adapter->netdev;
1566 irqreturn_t (*handler)(int, void *);
1567 int i, vector, q_vectors, err;
cb13fc20 1568 int ri=0, ti=0;
021230d4
AV		 1569
1570 /* Decrement for Other and TCP Timer vectors */
1571 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1572
1573 /* Map the Tx/Rx rings to the vectors we were allotted. */
1574 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1575 if (err)
1576 goto out;
1577
1578#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1579 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1580 &ixgbe_msix_clean_many)
021230d4 1581 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 1582 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 1583
1584 if(handler == &ixgbe_msix_clean_rx) {
1585 sprintf(adapter->name[vector], "%s-%s-%d",
1586 netdev->name, "rx", ri++);
1587 }
1588 else if(handler == &ixgbe_msix_clean_tx) {
1589 sprintf(adapter->name[vector], "%s-%s-%d",
1590 netdev->name, "tx", ti++);
1591 }
1592 else
1593 sprintf(adapter->name[vector], "%s-%s-%d",
1594 netdev->name, "TxRx", vector);
1595
021230d4 1596 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1597 handler, 0, adapter->name[vector],
7a921c93 1598 adapter->q_vector[vector]);
9a799d71
AK		 1599 if (err) {
1600 DPRINTK(PROBE, ERR,
b4617240
PW		 1601 "request_irq failed for MSIX interrupt "
1602 "Error: %d\n", err);
021230d4 1603 goto free_queue_irqs;
9a799d71 1604 }
9a799d71
AK		 1605 }
1606
021230d4
AV		 1607 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1608 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1609 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1610 if (err) {
1611 DPRINTK(PROBE, ERR,
1612 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1613 goto free_queue_irqs;
9a799d71
AK		 1614 }
1615
9a799d71
AK		 1616 return 0;
1617
021230d4
AV		 1618free_queue_irqs:
1619 for (i = vector - 1; i >= 0; i--)
1620 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 1621 adapter->q_vector[i]);
021230d4
AV		 1622 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1623 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1624 kfree(adapter->msix_entries);
1625 adapter->msix_entries = NULL;
021230d4 1626out:
9a799d71
AK		 1627 return err;
1628}
1629
f494e8fa
AV		 1630static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1631{
7a921c93 1632 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 1633 u8 current_itr;
1634 u32 new_itr = q_vector->eitr;
1635 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1636 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1637
30efa5a3 1638 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1639 q_vector->tx_itr,
1640 tx_ring->total_packets,
1641 tx_ring->total_bytes);
30efa5a3 1642 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1643 q_vector->rx_itr,
1644 rx_ring->total_packets,
1645 rx_ring->total_bytes);
f494e8fa 1646
30efa5a3 1647 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1648
1649 switch (current_itr) {
1650 /* counts and packets in update_itr are dependent on these numbers */
1651 case lowest_latency:
1652 new_itr = 100000;
1653 break;
1654 case low_latency:
1655 new_itr = 20000; /* aka hwitr = ~200 */
1656 break;
1657 case bulk_latency:
1658 new_itr = 8000;
1659 break;
1660 default:
1661 break;
1662 }
1663
1664 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1665 /* do an exponential smoothing */
1666 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1667
1668 /* save the algorithm value here, not the smoothed one */
1669 q_vector->eitr = new_itr;
fe49f04a
AD		 1670
1671 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1672 }
1673
1674 return;
1675}
1676
79aefa45
AD		 1677/**
1678 * ixgbe_irq_enable - Enable default interrupt generation settings
1679 * @adapter: board private structure
1680 **/
1681static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1682{
1683 u32 mask;
835462fc
NS		 1684
1685 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 1686 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1687 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1688 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1689 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1690 mask |= IXGBE_EIMS_GPI_SDP1;
1691 mask |= IXGBE_EIMS_GPI_SDP2;
1692 }
c4cf55e5
PWJ		 1693 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1694 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1695 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 1696
79aefa45 1697 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 1698 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45
AD		 1699 IXGBE_WRITE_FLUSH(&adapter->hw);
1700}
021230d4 1701
9a799d71 1702/**
021230d4 1703 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1704 * @irq: interrupt number
1705 * @data: pointer to a network interface device structure
9a799d71
AK		 1706 **/
1707static irqreturn_t ixgbe_intr(int irq, void *data)
1708{
1709 struct net_device *netdev = data;
1710 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1711 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 1712 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 1713 u32 eicr;
1714
54037505
DS		 1715 /*
1716 * Workaround for silicon errata. Mask the interrupts
1717 * before the read of EICR.
1718 */
1719 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1720
021230d4
AV		 1721 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1722 * therefore no explict interrupt disable is necessary */
1723 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1724 if (!eicr) {
1725 /* shared interrupt alert!
1726 * make sure interrupts are enabled because the read will
1727 * have disabled interrupts due to EIAM */
1728 ixgbe_irq_enable(adapter);
9a799d71 1729 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1730 }
9a799d71 1731
cf8280ee
JB		 1732 if (eicr & IXGBE_EICR_LSC)
1733 ixgbe_check_lsc(adapter);
021230d4 1734
e8e26350
PW		 1735 if (hw->mac.type == ixgbe_mac_82599EB)
1736 ixgbe_check_sfp_event(adapter, eicr);
1737
0befdb3e
JB		 1738 ixgbe_check_fan_failure(adapter, eicr);
1739
7a921c93 1740 if (napi_schedule_prep(&(q_vector->napi))) {
f494e8fa
AV		 1741 adapter->tx_ring[0].total_packets = 0;
1742 adapter->tx_ring[0].total_bytes = 0;
1743 adapter->rx_ring[0].total_packets = 0;
1744 adapter->rx_ring[0].total_bytes = 0;
021230d4 1745 /* would disable interrupts here but EIAM disabled it */
7a921c93 1746 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 1747 }
1748
1749 return IRQ_HANDLED;
1750}
1751
021230d4
AV		 1752static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1753{
1754 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1755
1756 for (i = 0; i < q_vectors; i++) {
7a921c93 1757 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 1758 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1759 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1760 q_vector->rxr_count = 0;
1761 q_vector->txr_count = 0;
1762 }
1763}
1764
9a799d71
AK		 1765/**
1766 * ixgbe_request_irq - initialize interrupts
1767 * @adapter: board private structure
1768 *
1769 * Attempts to configure interrupts using the best available
1770 * capabilities of the hardware and kernel.
1771 **/
021230d4 1772static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1773{
1774 struct net_device *netdev = adapter->netdev;
021230d4 1775 int err;
9a799d71 1776
021230d4
AV		 1777 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1778 err = ixgbe_request_msix_irqs(adapter);
1779 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1780 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
b4617240 1781 netdev->name, netdev);
021230d4
AV		 1782 } else {
1783 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
b4617240 1784 netdev->name, netdev);
9a799d71
AK		 1785 }
1786
9a799d71
AK		 1787 if (err)
1788 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1789
9a799d71
AK		 1790 return err;
1791}
1792
1793static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1794{
1795 struct net_device *netdev = adapter->netdev;
1796
1797 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1798 int i, q_vectors;
9a799d71 1799
021230d4
AV		 1800 q_vectors = adapter->num_msix_vectors;
1801
1802 i = q_vectors - 1;
9a799d71 1803 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1804
021230d4
AV		 1805 i--;
1806 for (; i >= 0; i--) {
1807 free_irq(adapter->msix_entries[i].vector,
7a921c93 1808 adapter->q_vector[i]);
021230d4
AV		 1809 }
1810
1811 ixgbe_reset_q_vectors(adapter);
1812 } else {
1813 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1814 }
1815}
1816
22d5a71b
JB		 1817/**
1818 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1819 * @adapter: board private structure
1820 **/
1821static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1822{
835462fc
NS		 1823 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1824 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1825 } else {
1826 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1827 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 1828 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
22d5a71b
JB		 1829 }
1830 IXGBE_WRITE_FLUSH(&adapter->hw);
1831 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1832 int i;
1833 for (i = 0; i < adapter->num_msix_vectors; i++)
1834 synchronize_irq(adapter->msix_entries[i].vector);
1835 } else {
1836 synchronize_irq(adapter->pdev->irq);
1837 }
1838}
1839
9a799d71
AK		 1840/**
1841 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1842 *
1843 **/
1844static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1845{
9a799d71
AK		 1846 struct ixgbe_hw *hw = &adapter->hw;
1847
021230d4 1848 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
30efa5a3 1849 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
9a799d71 1850
e8e26350
PW		 1851 ixgbe_set_ivar(adapter, 0, 0, 0);
1852 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 1853
1854 map_vector_to_rxq(adapter, 0, 0);
1855 map_vector_to_txq(adapter, 0, 0);
1856
1857 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1858}
1859
1860/**
3a581073 1861 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1862 * @adapter: board private structure
1863 *
1864 * Configure the Tx unit of the MAC after a reset.
1865 **/
1866static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1867{
12207e49 1868 u64 tdba;
9a799d71 1869 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1870 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1871
1872 /* Setup the HW Tx Head and Tail descriptor pointers */
1873 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1874 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1875 j = ring->reg_idx;
1876 tdba = ring->dma;
1877 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1878 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 1879 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 1880 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1881 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1882 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1883 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1884 adapter->tx_ring[i].head = IXGBE_TDH(j);
1885 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1886 /* Disable Tx Head Writeback RO bit, since this hoses
1887 * bookkeeping if things aren't delivered in order.
1888 */
e01c31a5 1889 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1890 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1891 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1892 }
e8e26350
PW		 1893 if (hw->mac.type == ixgbe_mac_82599EB) {
1894 /* We enable 8 traffic classes, DCB only */
1895 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1896 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1897 IXGBE_MTQC_8TC_8TQ));
1898 }
9a799d71
AK		 1899}
1900
e8e26350 1901#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 1902
a6616b42
YZ		 1903static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
1904 struct ixgbe_ring *rx_ring)
cc41ac7c 1905{
cc41ac7c 1906 u32 srrctl;
a6616b42 1907 int index;
0cefafad 1908 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 1909
a6616b42
YZ		 1910 index = rx_ring->reg_idx;
1911 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1912 unsigned long mask;
0cefafad 1913 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 1914 index = index & mask;
cc41ac7c 1915 }
cc41ac7c
JB		 1916 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1917
1918 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1919 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1920
afafd5b0
AD		 1921 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1922 IXGBE_SRRCTL_BSIZEHDR_MASK;
1923
6e455b89 1924 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 1925#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1926 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1927#else
1928 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1929#endif
cc41ac7c 1930 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 1931 } else {
afafd5b0
AD		 1932 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1933 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 1934 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 1935 }
e8e26350 1936
cc41ac7c
JB		 1937 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1938}
9a799d71 1939
0cefafad
JB		 1940static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1941{
1942 u32 mrqc = 0;
1943 int mask;
1944
1945 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1946 return mrqc;
1947
1948 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1949#ifdef CONFIG_IXGBE_DCB
1950 | IXGBE_FLAG_DCB_ENABLED
1951#endif
1952 );
1953
1954 switch (mask) {
1955 case (IXGBE_FLAG_RSS_ENABLED):
1956 mrqc = IXGBE_MRQC_RSSEN;
1957 break;
1958#ifdef CONFIG_IXGBE_DCB
1959 case (IXGBE_FLAG_DCB_ENABLED):
1960 mrqc = IXGBE_MRQC_RT8TCEN;
1961 break;
1962#endif /* CONFIG_IXGBE_DCB */
1963 default:
1964 break;
1965 }
1966
1967 return mrqc;
1968}
1969
9a799d71 1970/**
3a581073 1971 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1972 * @adapter: board private structure
1973 *
1974 * Configure the Rx unit of the MAC after a reset.
1975 **/
1976static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1977{
1978 u64 rdba;
1979 struct ixgbe_hw *hw = &adapter->hw;
a6616b42 1980 struct ixgbe_ring *rx_ring;
9a799d71
AK		 1981 struct net_device *netdev = adapter->netdev;
1982 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1983 int i, j;
9a799d71 1984 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1985 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1986 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1987 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1988 u32 fctrl, hlreg0;
509ee935 1989 u32 reta = 0, mrqc = 0;
cc41ac7c 1990 u32 rdrxctl;
f8212f97 1991 u32 rscctrl;
7c6e0a43 1992 int rx_buf_len;
9a799d71
AK		 1993
1994 /* Decide whether to use packet split mode or not */
762f4c57 1995 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 1996
1997 /* Set the RX buffer length according to the mode */
1998 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 1999 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 2000 if (hw->mac.type == ixgbe_mac_82599EB) {
2001 /* PSRTYPE must be initialized in 82599 */
2002 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2003 IXGBE_PSRTYPE_UDPHDR |
2004 IXGBE_PSRTYPE_IPV4HDR |
dfa12f05
YZ		 2005 IXGBE_PSRTYPE_IPV6HDR |
2006 IXGBE_PSRTYPE_L2HDR;
e8e26350
PW		 2007 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2008 }
9a799d71 2009 } else {
0c19d6af 2010 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2011 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2012 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2013 else
7c6e0a43 2014 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 2015 }
2016
2017 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2018 fctrl |= IXGBE_FCTRL_BAM;
021230d4 2019 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 2020 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 2021 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2022
2023 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2024 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2025 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2026 else
2027 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
63f39bd1 2028#ifdef IXGBE_FCOE
f34c5c82 2029 if (netdev->features & NETIF_F_FCOE_MTU)
63f39bd1
YZ		 2030 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2031#endif
9a799d71
AK		 2032 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2033
9a799d71
AK		 2034 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2035 /* disable receives while setting up the descriptors */
2036 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2037 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2038
0cefafad
JB		 2039 /*
2040 * Setup the HW Rx Head and Tail Descriptor Pointers and
2041 * the Base and Length of the Rx Descriptor Ring
2042 */
9a799d71 2043 for (i = 0; i < adapter->num_rx_queues; i++) {
a6616b42
YZ		 2044 rx_ring = &adapter->rx_ring[i];
2045 rdba = rx_ring->dma;
2046 j = rx_ring->reg_idx;
284901a9 2047 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 2048 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2049 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2050 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2051 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
a6616b42
YZ		 2052 rx_ring->head = IXGBE_RDH(j);
2053 rx_ring->tail = IXGBE_RDT(j);
2054 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2055
6e455b89
YZ		 2056 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2057 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2058
63f39bd1 2059#ifdef IXGBE_FCOE
f34c5c82 2060 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2061 struct ixgbe_ring_feature *f;
2062 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2063 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2064 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2065 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2066 rx_ring->rx_buf_len =
2067 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2068 }
63f39bd1
YZ		 2069 }
2070
2071#endif /* IXGBE_FCOE */
a6616b42 2072 ixgbe_configure_srrctl(adapter, rx_ring);
9a799d71
AK		 2073 }
2074
e8e26350
PW		 2075 if (hw->mac.type == ixgbe_mac_82598EB) {
2076 /*
2077 * For VMDq support of different descriptor types or
2078 * buffer sizes through the use of multiple SRRCTL
2079 * registers, RDRXCTL.MVMEN must be set to 1
2080 *
2081 * also, the manual doesn't mention it clearly but DCA hints
2082 * will only use queue 0's tags unless this bit is set. Side
2083 * effects of setting this bit are only that SRRCTL must be
2084 * fully programmed [0..15]
2085 */
2a41ff81
JB		 2086 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2087 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2088 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 2089 }
177db6ff 2090
e8e26350 2091 /* Program MRQC for the distribution of queues */
0cefafad 2092 mrqc = ixgbe_setup_mrqc(adapter);
e8e26350 2093
021230d4 2094 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 2095 /* Fill out redirection table */
021230d4
AV		 2096 for (i = 0, j = 0; i < 128; i++, j++) {
2097 if (j == adapter->ring_feature[RING_F_RSS].indices)
2098 j = 0;
2099 /* reta = 4-byte sliding window of
2100 * 0x00..(indices-1)(indices-1)00..etc. */
2101 reta = (reta << 8) | (j * 0x11);
2102 if ((i & 3) == 3)
2103 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 2104 }
2105
2106 /* Fill out hash function seeds */
2107 for (i = 0; i < 10; i++)
7c6e0a43 2108 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 2109
2a41ff81
JB		 2110 if (hw->mac.type == ixgbe_mac_82598EB)
2111 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 2112 /* Perform hash on these packet types */
2a41ff81
JB		 2113 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2114 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2115 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2116 | IXGBE_MRQC_RSS_FIELD_IPV6
2117 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2118 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 2119 }
2a41ff81 2120 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 2121
021230d4
AV		 2122 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2123
2124 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2125 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2126 /* Disable indicating checksum in descriptor, enables
2127 * RSS hash */
9a799d71 2128 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 2129 }
021230d4
AV		 2130 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2131 /* Enable IPv4 payload checksum for UDP fragments
2132 * if PCSD is not set */
2133 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2134 }
2135
2136 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 2137
2138 if (hw->mac.type == ixgbe_mac_82599EB) {
2139 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2140 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 2141 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 2142 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2143 }
f8212f97 2144
0c19d6af 2145 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97
AD		 2146 /* Enable 82599 HW-RSC */
2147 for (i = 0; i < adapter->num_rx_queues; i++) {
6e455b89
YZ		 2148 rx_ring = &adapter->rx_ring[i];
2149 j = rx_ring->reg_idx;
f8212f97
AD		 2150 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2151 rscctrl |= IXGBE_RSCCTL_RSCEN;
2152 /*
e76678dd
AD		 2153 * we must limit the number of descriptors so that the
2154 * total size of max desc * buf_len is not greater
2155 * than 65535
f8212f97 2156 */
6e455b89 2157 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
e76678dd
AD		 2158#if (MAX_SKB_FRAGS > 16)
2159 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2160#elif (MAX_SKB_FRAGS > 8)
f8212f97 2161 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
e76678dd
AD		 2162#elif (MAX_SKB_FRAGS > 4)
2163 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
f8212f97 2164#else
e76678dd 2165 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
f8212f97 2166#endif
e76678dd
AD		 2167 } else {
2168 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2169 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2170 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2171 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2172 else
2173 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2174 }
f8212f97
AD		 2175 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2176 }
2177 /* Disable RSC for ACK packets */
2178 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2179 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2180 }
9a799d71
AK		 2181}
2182
068c89b0
DS		 2183static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2184{
2185 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2186 struct ixgbe_hw *hw = &adapter->hw;
2187
2188 /* add VID to filter table */
2189 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2190}
2191
2192static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2193{
2194 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2195 struct ixgbe_hw *hw = &adapter->hw;
2196
2197 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2198 ixgbe_irq_disable(adapter);
2199
2200 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2201
2202 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2203 ixgbe_irq_enable(adapter);
2204
2205 /* remove VID from filter table */
2206 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2207}
2208
9a799d71 2209static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2210 struct vlan_group *grp)
9a799d71
AK		 2211{
2212 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2213 u32 ctrl;
e8e26350 2214 int i, j;
9a799d71 2215
d4f80882
AV		 2216 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2217 ixgbe_irq_disable(adapter);
9a799d71
AK		 2218 adapter->vlgrp = grp;
2219
2f90b865
AD		 2220 /*
2221 * For a DCB driver, always enable VLAN tag stripping so we can
2222 * still receive traffic from a DCB-enabled host even if we're
2223 * not in DCB mode.
2224 */
2225 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
e8e26350
PW		 2226 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2227 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2228 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2229 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2230 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2231 ctrl |= IXGBE_VLNCTRL_VFE;
9a799d71
AK		 2232 /* enable VLAN tag insert/strip */
2233 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
9a799d71
AK		 2234 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2235 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
e8e26350
PW		 2236 for (i = 0; i < adapter->num_rx_queues; i++) {
2237 j = adapter->rx_ring[i].reg_idx;
2238 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2239 ctrl |= IXGBE_RXDCTL_VME;
2240 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2241 }
9a799d71 2242 }
e8e26350 2243 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2244
d4f80882
AV		 2245 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2246 ixgbe_irq_enable(adapter);
9a799d71
AK		 2247}
2248
9a799d71
AK		 2249static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2250{
2251 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2252
2253 if (adapter->vlgrp) {
2254 u16 vid;
2255 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2256 if (!vlan_group_get_device(adapter->vlgrp, vid))
2257 continue;
2258 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2259 }
2260 }
2261}
2262
2c5645cf
CL		 2263static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2264{
2265 struct dev_mc_list *mc_ptr;
2266 u8 *addr = *mc_addr_ptr;
2267 *vmdq = 0;
2268
2269 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2270 if (mc_ptr->next)
2271 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2272 else
2273 *mc_addr_ptr = NULL;
2274
2275 return addr;
2276}
2277
9a799d71 2278/**
2c5645cf 2279 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2280 * @netdev: network interface device structure
2281 *
2c5645cf
CL		 2282 * The set_rx_method entry point is called whenever the unicast/multicast
2283 * address list or the network interface flags are updated. This routine is
2284 * responsible for configuring the hardware for proper unicast, multicast and
2285 * promiscuous mode.
9a799d71 2286 **/
2c5645cf 2287static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2288{
2289 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2290 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 2291 u32 fctrl, vlnctrl;
2c5645cf
CL		 2292 u8 *addr_list = NULL;
2293 int addr_count = 0;
9a799d71
AK		 2294
2295 /* Check for Promiscuous and All Multicast modes */
2296
2297 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 2298 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 2299
2300 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2301 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2302 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 2303 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 2304 } else {
746b9f02
PM		 2305 if (netdev->flags & IFF_ALLMULTI) {
2306 fctrl |= IXGBE_FCTRL_MPE;
2307 fctrl &= ~IXGBE_FCTRL_UPE;
2308 } else {
2309 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2310 }
3d01625a 2311 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 2312 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2313 }
2314
2315 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 2316 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 2317
2c5645cf 2318 /* reprogram secondary unicast list */
31278e71 2319 hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
9a799d71 2320
2c5645cf
CL		 2321 /* reprogram multicast list */
2322 addr_count = netdev->mc_count;
2323 if (addr_count)
2324 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 2325 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2326 ixgbe_addr_list_itr);
9a799d71
AK		 2327}
2328
021230d4
AV		 2329static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2330{
2331 int q_idx;
2332 struct ixgbe_q_vector *q_vector;
2333 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2334
2335 /* legacy and MSI only use one vector */
2336 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2337 q_vectors = 1;
2338
2339 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2340 struct napi_struct *napi;
7a921c93 2341 q_vector = adapter->q_vector[q_idx];
f0848276 2342 napi = &q_vector->napi;
91281fd3
AD		 2343 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2344 if (!q_vector->rxr_count || !q_vector->txr_count) {
2345 if (q_vector->txr_count == 1)
2346 napi->poll = &ixgbe_clean_txonly;
2347 else if (q_vector->rxr_count == 1)
2348 napi->poll = &ixgbe_clean_rxonly;
2349 }
2350 }
f0848276
JB		 2351
2352 napi_enable(napi);
021230d4
AV		 2353 }
2354}
2355
2356static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2357{
2358 int q_idx;
2359 struct ixgbe_q_vector *q_vector;
2360 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2361
2362 /* legacy and MSI only use one vector */
2363 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2364 q_vectors = 1;
2365
2366 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 2367 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2368 napi_disable(&q_vector->napi);
2369 }
2370}
2371
7a6b6f51 2372#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2373/*
2374 * ixgbe_configure_dcb - Configure DCB hardware
2375 * @adapter: ixgbe adapter struct
2376 *
2377 * This is called by the driver on open to configure the DCB hardware.
2378 * This is also called by the gennetlink interface when reconfiguring
2379 * the DCB state.
2380 */
2381static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2382{
2383 struct ixgbe_hw *hw = &adapter->hw;
2384 u32 txdctl, vlnctrl;
2385 int i, j;
2386
2387 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2388 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2389 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2390
2391 /* reconfigure the hardware */
2392 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2393
2394 for (i = 0; i < adapter->num_tx_queues; i++) {
2395 j = adapter->tx_ring[i].reg_idx;
2396 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2397 /* PThresh workaround for Tx hang with DFP enabled. */
2398 txdctl |= 32;
2399 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2400 }
2401 /* Enable VLAN tag insert/strip */
2402 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
e8e26350
PW		 2403 if (hw->mac.type == ixgbe_mac_82598EB) {
2404 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2405 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2406 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2407 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2408 vlnctrl |= IXGBE_VLNCTRL_VFE;
2409 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2410 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2411 for (i = 0; i < adapter->num_rx_queues; i++) {
2412 j = adapter->rx_ring[i].reg_idx;
2413 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2414 vlnctrl |= IXGBE_RXDCTL_VME;
2415 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2416 }
2417 }
2f90b865
AD		 2418 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2419}
2420
2421#endif
9a799d71
AK		 2422static void ixgbe_configure(struct ixgbe_adapter *adapter)
2423{
2424 struct net_device *netdev = adapter->netdev;
c4cf55e5 2425 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 2426 int i;
2427
2c5645cf 2428 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2429
2430 ixgbe_restore_vlan(adapter);
7a6b6f51 2431#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2432 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2433 netif_set_gso_max_size(netdev, 32768);
2434 ixgbe_configure_dcb(adapter);
2435 } else {
2436 netif_set_gso_max_size(netdev, 65536);
2437 }
2438#else
2439 netif_set_gso_max_size(netdev, 65536);
2440#endif
9a799d71 2441
eacd73f7
YZ		 2442#ifdef IXGBE_FCOE
2443 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2444 ixgbe_configure_fcoe(adapter);
2445
2446#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 2447 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2448 for (i = 0; i < adapter->num_tx_queues; i++)
2449 adapter->tx_ring[i].atr_sample_rate =
2450 adapter->atr_sample_rate;
2451 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2452 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2453 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2454 }
2455
9a799d71
AK		 2456 ixgbe_configure_tx(adapter);
2457 ixgbe_configure_rx(adapter);
2458 for (i = 0; i < adapter->num_rx_queues; i++)
2459 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 2460 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 2461}
2462
e8e26350
PW		 2463static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2464{
2465 switch (hw->phy.type) {
2466 case ixgbe_phy_sfp_avago:
2467 case ixgbe_phy_sfp_ftl:
2468 case ixgbe_phy_sfp_intel:
2469 case ixgbe_phy_sfp_unknown:
2470 case ixgbe_phy_tw_tyco:
2471 case ixgbe_phy_tw_unknown:
2472 return true;
2473 default:
2474 return false;
2475 }
2476}
2477
0ecc061d 2478/**
e8e26350
PW		 2479 * ixgbe_sfp_link_config - set up SFP+ link
2480 * @adapter: pointer to private adapter struct
2481 **/
2482static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2483{
2484 struct ixgbe_hw *hw = &adapter->hw;
2485
2486 if (hw->phy.multispeed_fiber) {
2487 /*
2488 * In multispeed fiber setups, the device may not have
2489 * had a physical connection when the driver loaded.
2490 * If that's the case, the initial link configuration
2491 * couldn't get the MAC into 10G or 1G mode, so we'll
2492 * never have a link status change interrupt fire.
2493 * We need to try and force an autonegotiation
2494 * session, then bring up link.
2495 */
2496 hw->mac.ops.setup_sfp(hw);
2497 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2498 schedule_work(&adapter->multispeed_fiber_task);
2499 } else {
2500 /*
2501 * Direct Attach Cu and non-multispeed fiber modules
2502 * still need to be configured properly prior to
2503 * attempting link.
2504 */
2505 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2506 schedule_work(&adapter->sfp_config_module_task);
2507 }
2508}
2509
2510/**
2511 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2512 * @hw: pointer to private hardware struct
2513 *
2514 * Returns 0 on success, negative on failure
2515 **/
e8e26350 2516static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2517{
2518 u32 autoneg;
8620a103 2519 bool negotiation, link_up = false;
0ecc061d
PWJ		 2520 u32 ret = IXGBE_ERR_LINK_SETUP;
2521
2522 if (hw->mac.ops.check_link)
2523 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2524
2525 if (ret)
2526 goto link_cfg_out;
2527
2528 if (hw->mac.ops.get_link_capabilities)
8620a103 2529 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
0ecc061d
PWJ		 2530 if (ret)
2531 goto link_cfg_out;
2532
8620a103
MC		 2533 if (hw->mac.ops.setup_link)
2534 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 2535link_cfg_out:
2536 return ret;
2537}
2538
e8e26350
PW		 2539#define IXGBE_MAX_RX_DESC_POLL 10
2540static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2541 int rxr)
2542{
2543 int j = adapter->rx_ring[rxr].reg_idx;
2544 int k;
2545
2546 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2547 if (IXGBE_READ_REG(&adapter->hw,
2548 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2549 break;
2550 else
2551 msleep(1);
2552 }
2553 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2554 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2555 "not set within the polling period\n", rxr);
2556 }
2557 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2558 (adapter->rx_ring[rxr].count - 1));
2559}
2560
9a799d71
AK		 2561static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2562{
2563 struct net_device *netdev = adapter->netdev;
9a799d71 2564 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2565 int i, j = 0;
e8e26350 2566 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2567 int err;
9a799d71 2568 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2569 u32 txdctl, rxdctl, mhadd;
e8e26350 2570 u32 dmatxctl;
021230d4 2571 u32 gpie;
9a799d71 2572
5eba3699
AV		 2573 ixgbe_get_hw_control(adapter);
2574
021230d4
AV		 2575 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2576 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2577 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2578 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2579 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2580 } else {
2581 /* MSI only */
021230d4 2582 gpie = 0;
9a799d71 2583 }
021230d4
AV		 2584 /* XXX: to interrupt immediately for EICS writes, enable this */
2585 /* gpie |= IXGBE_GPIE_EIMEN; */
2586 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2587 }
2588
021230d4
AV		 2589 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2590 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2591 * specifically only auto mask tx and rx interrupts */
2592 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2593 }
9a799d71 2594
0befdb3e
JB		 2595 /* Enable fan failure interrupt if media type is copper */
2596 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2597 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2598 gpie |= IXGBE_SDP1_GPIEN;
2599 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2600 }
2601
e8e26350
PW		 2602 if (hw->mac.type == ixgbe_mac_82599EB) {
2603 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2604 gpie |= IXGBE_SDP1_GPIEN;
2605 gpie |= IXGBE_SDP2_GPIEN;
2606 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2607 }
2608
63f39bd1
YZ		 2609#ifdef IXGBE_FCOE
2610 /* adjust max frame to be able to do baby jumbo for FCoE */
f34c5c82 2611 if ((netdev->features & NETIF_F_FCOE_MTU) &&
63f39bd1
YZ		 2612 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2613 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2614
2615#endif /* IXGBE_FCOE */
021230d4 2616 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2617 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2618 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2619 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2620
2621 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2622 }
2623
2624 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 2625 j = adapter->tx_ring[i].reg_idx;
2626 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2627 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2628 txdctl |= (8 << 16);
e8e26350
PW		 2629 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2630 }
2631
2632 if (hw->mac.type == ixgbe_mac_82599EB) {
2633 /* DMATXCTL.EN must be set after all Tx queue config is done */
2634 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2635 dmatxctl |= IXGBE_DMATXCTL_TE;
2636 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2637 }
2638 for (i = 0; i < adapter->num_tx_queues; i++) {
2639 j = adapter->tx_ring[i].reg_idx;
2640 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2641 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2642 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 2643 }
2644
e8e26350 2645 for (i = 0; i < num_rx_rings; i++) {
021230d4
AV		 2646 j = adapter->rx_ring[i].reg_idx;
2647 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2648 /* enable PTHRESH=32 descriptors (half the internal cache)
2649 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2650 * this also removes a pesky rx_no_buffer_count increment */
2651 rxdctl |= 0x0020;
9a799d71 2652 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2653 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2654 if (hw->mac.type == ixgbe_mac_82599EB)
2655 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2656 }
2657 /* enable all receives */
2658 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2659 if (hw->mac.type == ixgbe_mac_82598EB)
2660 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2661 else
2662 rxdctl |= IXGBE_RXCTRL_RXEN;
2663 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2664
2665 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2666 ixgbe_configure_msix(adapter);
2667 else
2668 ixgbe_configure_msi_and_legacy(adapter);
2669
2670 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2671 ixgbe_napi_enable_all(adapter);
2672
2673 /* clear any pending interrupts, may auto mask */
2674 IXGBE_READ_REG(hw, IXGBE_EICR);
2675
9a799d71
AK		 2676 ixgbe_irq_enable(adapter);
2677
bf069c97
DS		 2678 /*
2679 * If this adapter has a fan, check to see if we had a failure
2680 * before we enabled the interrupt.
2681 */
2682 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2683 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2684 if (esdp & IXGBE_ESDP_SDP1)
2685 DPRINTK(DRV, CRIT,
2686 "Fan has stopped, replace the adapter\n");
2687 }
2688
e8e26350
PW		 2689 /*
2690 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 2691 * arrived before interrupts were enabled but after probe. Such
2692 * devices wouldn't have their type identified yet. We need to
2693 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 2694 * If we're not hot-pluggable SFP+, we just need to configure link
2695 * and bring it up.
2696 */
19343de2
DS		 2697 if (hw->phy.type == ixgbe_phy_unknown) {
2698 err = hw->phy.ops.identify(hw);
2699 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 2700 /*
2701 * Take the device down and schedule the sfp tasklet
2702 * which will unregister_netdev and log it.
2703 */
19343de2 2704 ixgbe_down(adapter);
5da43c1a 2705 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 2706 return err;
2707 }
e8e26350
PW		 2708 }
2709
2710 if (ixgbe_is_sfp(hw)) {
2711 ixgbe_sfp_link_config(adapter);
2712 } else {
2713 err = ixgbe_non_sfp_link_config(hw);
2714 if (err)
2715 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2716 }
0ecc061d 2717
c4cf55e5
PWJ		 2718 for (i = 0; i < adapter->num_tx_queues; i++)
2719 set_bit(__IXGBE_FDIR_INIT_DONE,
2720 &(adapter->tx_ring[i].reinit_state));
2721
1da100bb
PWJ		 2722 /* enable transmits */
2723 netif_tx_start_all_queues(netdev);
2724
9a799d71
AK		 2725 /* bring the link up in the watchdog, this could race with our first
2726 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 2727 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2728 adapter->link_check_timeout = jiffies;
9a799d71
AK		 2729 mod_timer(&adapter->watchdog_timer, jiffies);
2730 return 0;
2731}
2732
d4f80882
AV		 2733void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2734{
2735 WARN_ON(in_interrupt());
2736 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2737 msleep(1);
2738 ixgbe_down(adapter);
2739 ixgbe_up(adapter);
2740 clear_bit(__IXGBE_RESETTING, &adapter->state);
2741}
2742
9a799d71
AK		 2743int ixgbe_up(struct ixgbe_adapter *adapter)
2744{
2745 /* hardware has been reset, we need to reload some things */
2746 ixgbe_configure(adapter);
2747
2748 return ixgbe_up_complete(adapter);
2749}
2750
2751void ixgbe_reset(struct ixgbe_adapter *adapter)
2752{
c44ade9e 2753 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 2754 int err;
2755
2756 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 2757 switch (err) {
2758 case 0:
2759 case IXGBE_ERR_SFP_NOT_PRESENT:
2760 break;
2761 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2762 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2763 break;
794caeb2
PWJ		 2764 case IXGBE_ERR_EEPROM_VERSION:
2765 /* We are running on a pre-production device, log a warning */
2766 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2767 "adapter/LOM. Please be aware there may be issues "
2768 "associated with your hardware. If you are "
2769 "experiencing problems please contact your Intel or "
2770 "hardware representative who provided you with this "
2771 "hardware.\n");
2772 break;
da4dd0f7
PWJ		 2773 default:
2774 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2775 }
9a799d71
AK		 2776
2777 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2778 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2779}
2780
9a799d71
AK		 2781/**
2782 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2783 * @adapter: board private structure
2784 * @rx_ring: ring to free buffers from
2785 **/
2786static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2787 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2788{
2789 struct pci_dev *pdev = adapter->pdev;
2790 unsigned long size;
2791 unsigned int i;
2792
2793 /* Free all the Rx ring sk_buffs */
2794
2795 for (i = 0; i < rx_ring->count; i++) {
2796 struct ixgbe_rx_buffer *rx_buffer_info;
2797
2798 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2799 if (rx_buffer_info->dma) {
2800 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2801 rx_ring->rx_buf_len,
2802 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2803 rx_buffer_info->dma = 0;
2804 }
2805 if (rx_buffer_info->skb) {
f8212f97 2806 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 2807 rx_buffer_info->skb = NULL;
f8212f97
AD		 2808 do {
2809 struct sk_buff *this = skb;
2810 skb = skb->prev;
2811 dev_kfree_skb(this);
2812 } while (skb);
9a799d71
AK		 2813 }
2814 if (!rx_buffer_info->page)
2815 continue;
4f57ca6e
JB		 2816 if (rx_buffer_info->page_dma) {
2817 pci_unmap_page(pdev, rx_buffer_info->page_dma,
2818 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2819 rx_buffer_info->page_dma = 0;
2820 }
9a799d71
AK		 2821 put_page(rx_buffer_info->page);
2822 rx_buffer_info->page = NULL;
762f4c57 2823 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2824 }
2825
2826 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2827 memset(rx_ring->rx_buffer_info, 0, size);
2828
2829 /* Zero out the descriptor ring */
2830 memset(rx_ring->desc, 0, rx_ring->size);
2831
2832 rx_ring->next_to_clean = 0;
2833 rx_ring->next_to_use = 0;
2834
9891ca7c
JB		 2835 if (rx_ring->head)
2836 writel(0, adapter->hw.hw_addr + rx_ring->head);
2837 if (rx_ring->tail)
2838 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 2839}
2840
2841/**
2842 * ixgbe_clean_tx_ring - Free Tx Buffers
2843 * @adapter: board private structure
2844 * @tx_ring: ring to be cleaned
2845 **/
2846static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2847 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2848{
2849 struct ixgbe_tx_buffer *tx_buffer_info;
2850 unsigned long size;
2851 unsigned int i;
2852
2853 /* Free all the Tx ring sk_buffs */
2854
2855 for (i = 0; i < tx_ring->count; i++) {
2856 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2857 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2858 }
2859
2860 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2861 memset(tx_ring->tx_buffer_info, 0, size);
2862
2863 /* Zero out the descriptor ring */
2864 memset(tx_ring->desc, 0, tx_ring->size);
2865
2866 tx_ring->next_to_use = 0;
2867 tx_ring->next_to_clean = 0;
2868
9891ca7c
JB		 2869 if (tx_ring->head)
2870 writel(0, adapter->hw.hw_addr + tx_ring->head);
2871 if (tx_ring->tail)
2872 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 2873}
2874
2875/**
021230d4 2876 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2877 * @adapter: board private structure
2878 **/
021230d4 2879static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2880{
2881 int i;
2882
021230d4
AV		 2883 for (i = 0; i < adapter->num_rx_queues; i++)
2884 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2885}
2886
2887/**
021230d4 2888 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2889 * @adapter: board private structure
2890 **/
021230d4 2891static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2892{
2893 int i;
2894
021230d4
AV		 2895 for (i = 0; i < adapter->num_tx_queues; i++)
2896 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2897}
2898
2899void ixgbe_down(struct ixgbe_adapter *adapter)
2900{
2901 struct net_device *netdev = adapter->netdev;
7f821875 2902 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2903 u32 rxctrl;
7f821875
JB		 2904 u32 txdctl;
2905 int i, j;
9a799d71
AK		 2906
2907 /* signal that we are down to the interrupt handler */
2908 set_bit(__IXGBE_DOWN, &adapter->state);
2909
2910 /* disable receives */
7f821875
JB		 2911 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2912 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 2913
2914 netif_tx_disable(netdev);
2915
7f821875 2916 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 2917 msleep(10);
2918
7f821875
JB		 2919 netif_tx_stop_all_queues(netdev);
2920
9a799d71
AK		 2921 ixgbe_irq_disable(adapter);
2922
021230d4 2923 ixgbe_napi_disable_all(adapter);
7f821875 2924
9a799d71 2925 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 2926 cancel_work_sync(&adapter->watchdog_task);
9a799d71 2927
c4cf55e5
PWJ		 2928 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2929 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2930 cancel_work_sync(&adapter->fdir_reinit_task);
2931
7f821875
JB		 2932 /* disable transmits in the hardware now that interrupts are off */
2933 for (i = 0; i < adapter->num_tx_queues; i++) {
2934 j = adapter->tx_ring[i].reg_idx;
2935 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2936 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2937 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2938 }
88512539
PW		 2939 /* Disable the Tx DMA engine on 82599 */
2940 if (hw->mac.type == ixgbe_mac_82599EB)
2941 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2942 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2943 ~IXGBE_DMATXCTL_TE));
7f821875 2944
9a799d71 2945 netif_carrier_off(netdev);
9a799d71 2946
6f4a0e45
PL		 2947 if (!pci_channel_offline(adapter->pdev))
2948 ixgbe_reset(adapter);
9a799d71
AK		 2949 ixgbe_clean_all_tx_rings(adapter);
2950 ixgbe_clean_all_rx_rings(adapter);
2951
5dd2d332 2952#ifdef CONFIG_IXGBE_DCA
96b0e0f6 2953 /* since we reset the hardware DCA settings were cleared */
e35ec126 2954 ixgbe_setup_dca(adapter);
96b0e0f6 2955#endif
9a799d71
AK		 2956}
2957
9a799d71 2958/**
021230d4
AV		 2959 * ixgbe_poll - NAPI Rx polling callback
2960 * @napi: structure for representing this polling device
2961 * @budget: how many packets driver is allowed to clean
2962 *
2963 * This function is used for legacy and MSI, NAPI mode
9a799d71 2964 **/
021230d4 2965static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2966{
9a1a69ad
JB		 2967 struct ixgbe_q_vector *q_vector =
2968 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2969 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 2970 int tx_clean_complete, work_done = 0;
9a799d71 2971
5dd2d332 2972#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 2973 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2974 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2975 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2976 }
2977#endif
2978
fe49f04a 2979 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
78b6f4ce 2980 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
9a799d71 2981
9a1a69ad 2982 if (!tx_clean_complete)
d2c7ddd6
DM		 2983 work_done = budget;
2984
53e52c72
DM		 2985 /* If budget not fully consumed, exit the polling mode */
2986 if (work_done < budget) {
288379f0 2987 napi_complete(napi);
509ee935 2988 if (adapter->itr_setting & 1)
f494e8fa 2989 ixgbe_set_itr(adapter);
d4f80882 2990 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 2991 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 2992 }
9a799d71
AK		 2993 return work_done;
2994}
2995
2996/**
2997 * ixgbe_tx_timeout - Respond to a Tx Hang
2998 * @netdev: network interface device structure
2999 **/
3000static void ixgbe_tx_timeout(struct net_device *netdev)
3001{
3002 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3003
3004 /* Do the reset outside of interrupt context */
3005 schedule_work(&adapter->reset_task);
3006}
3007
3008static void ixgbe_reset_task(struct work_struct *work)
3009{
3010 struct ixgbe_adapter *adapter;
3011 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3012
2f90b865
AD		 3013 /* If we're already down or resetting, just bail */
3014 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3015 test_bit(__IXGBE_RESETTING, &adapter->state))
3016 return;
3017
9a799d71
AK		 3018 adapter->tx_timeout_count++;
3019
d4f80882 3020 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3021}
3022
bc97114d
PWJ		 3023#ifdef CONFIG_IXGBE_DCB
3024static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3025{
bc97114d 3026 bool ret = false;
0cefafad 3027 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3028
0cefafad
JB		 3029 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3030 return ret;
3031
3032 f->mask = 0x7 << 3;
3033 adapter->num_rx_queues = f->indices;
3034 adapter->num_tx_queues = f->indices;
3035 ret = true;
2f90b865 3036
bc97114d
PWJ		 3037 return ret;
3038}
3039#endif
3040
4df10466
JB		 3041/**
3042 * ixgbe_set_rss_queues: Allocate queues for RSS
3043 * @adapter: board private structure to initialize
3044 *
3045 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3046 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3047 *
3048 **/
bc97114d
PWJ		 3049static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3050{
3051 bool ret = false;
0cefafad 3052 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3053
3054 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3055 f->mask = 0xF;
3056 adapter->num_rx_queues = f->indices;
3057 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3058 ret = true;
3059 } else {
bc97114d 3060 ret = false;
b9804972
JB		 3061 }
3062
bc97114d
PWJ		 3063 return ret;
3064}
3065
c4cf55e5
PWJ		 3066/**
3067 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3068 * @adapter: board private structure to initialize
3069 *
3070 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3071 * to the original CPU that initiated the Tx session. This runs in addition
3072 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3073 * Rx load across CPUs using RSS.
3074 *
3075 **/
3076static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3077{
3078 bool ret = false;
3079 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3080
3081 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3082 f_fdir->mask = 0;
3083
3084 /* Flow Director must have RSS enabled */
3085 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3086 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3087 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3088 adapter->num_tx_queues = f_fdir->indices;
3089 adapter->num_rx_queues = f_fdir->indices;
3090 ret = true;
3091 } else {
3092 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3093 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3094 }
3095 return ret;
3096}
3097
0331a832
YZ		 3098#ifdef IXGBE_FCOE
3099/**
3100 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3101 * @adapter: board private structure to initialize
3102 *
3103 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3104 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3105 * rx queues out of the max number of rx queues, instead, it is used as the
3106 * index of the first rx queue used by FCoE.
3107 *
3108 **/
3109static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3110{
3111 bool ret = false;
3112 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3113
3114 f->indices = min((int)num_online_cpus(), f->indices);
3115 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3116#ifdef CONFIG_IXGBE_DCB
3117 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3118 DPRINTK(PROBE, INFO, "FCOE enabled with DCB \n");
3119 ixgbe_set_dcb_queues(adapter);
3120 }
3121#endif
3122 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3123 DPRINTK(PROBE, INFO, "FCOE enabled with RSS \n");
8faa2a78
YZ		 3124 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3125 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3126 ixgbe_set_fdir_queues(adapter);
3127 else
3128 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 3129 }
3130 /* adding FCoE rx rings to the end */
3131 f->mask = adapter->num_rx_queues;
3132 adapter->num_rx_queues += f->indices;
3133 if (adapter->num_tx_queues == 0)
3134 adapter->num_tx_queues = f->indices;
3135
3136 ret = true;
3137 }
3138
3139 return ret;
3140}
3141
3142#endif /* IXGBE_FCOE */
4df10466
JB		 3143/*
3144 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3145 * @adapter: board private structure to initialize
3146 *
3147 * This is the top level queue allocation routine. The order here is very
3148 * important, starting with the "most" number of features turned on at once,
3149 * and ending with the smallest set of features. This way large combinations
3150 * can be allocated if they're turned on, and smaller combinations are the
3151 * fallthrough conditions.
3152 *
3153 **/
bc97114d
PWJ		 3154static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3155{
0331a832
YZ		 3156#ifdef IXGBE_FCOE
3157 if (ixgbe_set_fcoe_queues(adapter))
3158 goto done;
3159
3160#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3161#ifdef CONFIG_IXGBE_DCB
3162 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 3163 goto done;
bc97114d
PWJ		 3164
3165#endif
c4cf55e5
PWJ		 3166 if (ixgbe_set_fdir_queues(adapter))
3167 goto done;
3168
bc97114d 3169 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 3170 goto done;
3171
3172 /* fallback to base case */
3173 adapter->num_rx_queues = 1;
3174 adapter->num_tx_queues = 1;
3175
3176done:
3177 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3178 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 3179}
3180
021230d4 3181static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 3182 int vectors)
021230d4
AV		 3183{
3184 int err, vector_threshold;
3185
3186 /* We'll want at least 3 (vector_threshold):
3187 * 1) TxQ[0] Cleanup
3188 * 2) RxQ[0] Cleanup
3189 * 3) Other (Link Status Change, etc.)
3190 * 4) TCP Timer (optional)
3191 */
3192 vector_threshold = MIN_MSIX_COUNT;
3193
3194 /* The more we get, the more we will assign to Tx/Rx Cleanup
3195 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3196 * Right now, we simply care about how many we'll get; we'll
3197 * set them up later while requesting irq's.
3198 */
3199 while (vectors >= vector_threshold) {
3200 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 3201 vectors);
021230d4
AV		 3202 if (!err) /* Success in acquiring all requested vectors. */
3203 break;
3204 else if (err < 0)
3205 vectors = 0; /* Nasty failure, quit now */
3206 else /* err == number of vectors we should try again with */
3207 vectors = err;
3208 }
3209
3210 if (vectors < vector_threshold) {
3211 /* Can't allocate enough MSI-X interrupts? Oh well.
3212 * This just means we'll go with either a single MSI
3213 * vector or fall back to legacy interrupts.
3214 */
3215 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3216 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3217 kfree(adapter->msix_entries);
3218 adapter->msix_entries = NULL;
021230d4
AV		 3219 } else {
3220 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 3221 /*
3222 * Adjust for only the vectors we'll use, which is minimum
3223 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3224 * vectors we were allocated.
3225 */
3226 adapter->num_msix_vectors = min(vectors,
3227 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 3228 }
3229}
3230
021230d4 3231/**
bc97114d 3232 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 3233 * @adapter: board private structure to initialize
3234 *
bc97114d
PWJ		 3235 * Cache the descriptor ring offsets for RSS to the assigned rings.
3236 *
021230d4 3237 **/
bc97114d 3238static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 3239{
bc97114d
PWJ		 3240 int i;
3241 bool ret = false;
3242
3243 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3244 for (i = 0; i < adapter->num_rx_queues; i++)
3245 adapter->rx_ring[i].reg_idx = i;
3246 for (i = 0; i < adapter->num_tx_queues; i++)
3247 adapter->tx_ring[i].reg_idx = i;
3248 ret = true;
3249 } else {
3250 ret = false;
3251 }
3252
3253 return ret;
3254}
3255
3256#ifdef CONFIG_IXGBE_DCB
3257/**
3258 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3259 * @adapter: board private structure to initialize
3260 *
3261 * Cache the descriptor ring offsets for DCB to the assigned rings.
3262 *
3263 **/
3264static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3265{
3266 int i;
3267 bool ret = false;
3268 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3269
3270 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3271 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 3272 /* the number of queues is assumed to be symmetric */
3273 for (i = 0; i < dcb_i; i++) {
3274 adapter->rx_ring[i].reg_idx = i << 3;
3275 adapter->tx_ring[i].reg_idx = i << 2;
3276 }
bc97114d 3277 ret = true;
e8e26350 3278 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 3279 if (dcb_i == 8) {
3280 /*
3281 * Tx TC0 starts at: descriptor queue 0
3282 * Tx TC1 starts at: descriptor queue 32
3283 * Tx TC2 starts at: descriptor queue 64
3284 * Tx TC3 starts at: descriptor queue 80
3285 * Tx TC4 starts at: descriptor queue 96
3286 * Tx TC5 starts at: descriptor queue 104
3287 * Tx TC6 starts at: descriptor queue 112
3288 * Tx TC7 starts at: descriptor queue 120
3289 *
3290 * Rx TC0-TC7 are offset by 16 queues each
3291 */
3292 for (i = 0; i < 3; i++) {
3293 adapter->tx_ring[i].reg_idx = i << 5;
3294 adapter->rx_ring[i].reg_idx = i << 4;
3295 }
3296 for ( ; i < 5; i++) {
3297 adapter->tx_ring[i].reg_idx =
3298 ((i + 2) << 4);
3299 adapter->rx_ring[i].reg_idx = i << 4;
3300 }
3301 for ( ; i < dcb_i; i++) {
3302 adapter->tx_ring[i].reg_idx =
3303 ((i + 8) << 3);
3304 adapter->rx_ring[i].reg_idx = i << 4;
3305 }
3306
3307 ret = true;
3308 } else if (dcb_i == 4) {
3309 /*
3310 * Tx TC0 starts at: descriptor queue 0
3311 * Tx TC1 starts at: descriptor queue 64
3312 * Tx TC2 starts at: descriptor queue 96
3313 * Tx TC3 starts at: descriptor queue 112
3314 *
3315 * Rx TC0-TC3 are offset by 32 queues each
3316 */
3317 adapter->tx_ring[0].reg_idx = 0;
3318 adapter->tx_ring[1].reg_idx = 64;
3319 adapter->tx_ring[2].reg_idx = 96;
3320 adapter->tx_ring[3].reg_idx = 112;
3321 for (i = 0 ; i < dcb_i; i++)
3322 adapter->rx_ring[i].reg_idx = i << 5;
3323
3324 ret = true;
3325 } else {
3326 ret = false;
e8e26350 3327 }
bc97114d
PWJ		 3328 } else {
3329 ret = false;
021230d4 3330 }
bc97114d
PWJ		 3331 } else {
3332 ret = false;
021230d4 3333 }
bc97114d
PWJ		 3334
3335 return ret;
3336}
3337#endif
3338
c4cf55e5
PWJ		 3339/**
3340 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3341 * @adapter: board private structure to initialize
3342 *
3343 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3344 *
3345 **/
3346static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3347{
3348 int i;
3349 bool ret = false;
3350
3351 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3352 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3353 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3354 for (i = 0; i < adapter->num_rx_queues; i++)
3355 adapter->rx_ring[i].reg_idx = i;
3356 for (i = 0; i < adapter->num_tx_queues; i++)
3357 adapter->tx_ring[i].reg_idx = i;
3358 ret = true;
3359 }
3360
3361 return ret;
3362}
3363
0331a832
YZ		 3364#ifdef IXGBE_FCOE
3365/**
3366 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3367 * @adapter: board private structure to initialize
3368 *
3369 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3370 *
3371 */
3372static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3373{
3374 int i, fcoe_i = 0;
3375 bool ret = false;
3376 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3377
3378 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3379#ifdef CONFIG_IXGBE_DCB
3380 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3381 ixgbe_cache_ring_dcb(adapter);
3382 fcoe_i = adapter->rx_ring[0].reg_idx + 1;
3383 }
3384#endif /* CONFIG_IXGBE_DCB */
3385 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 3386 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3387 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3388 ixgbe_cache_ring_fdir(adapter);
3389 else
3390 ixgbe_cache_ring_rss(adapter);
3391
0331a832
YZ		 3392 fcoe_i = f->mask;
3393 }
3394 for (i = 0; i < f->indices; i++, fcoe_i++)
3395 adapter->rx_ring[f->mask + i].reg_idx = fcoe_i;
3396 ret = true;
3397 }
3398 return ret;
3399}
3400
3401#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3402/**
3403 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3404 * @adapter: board private structure to initialize
3405 *
3406 * Once we know the feature-set enabled for the device, we'll cache
3407 * the register offset the descriptor ring is assigned to.
3408 *
3409 * Note, the order the various feature calls is important. It must start with
3410 * the "most" features enabled at the same time, then trickle down to the
3411 * least amount of features turned on at once.
3412 **/
3413static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3414{
3415 /* start with default case */
3416 adapter->rx_ring[0].reg_idx = 0;
3417 adapter->tx_ring[0].reg_idx = 0;
3418
0331a832
YZ		 3419#ifdef IXGBE_FCOE
3420 if (ixgbe_cache_ring_fcoe(adapter))
3421 return;
3422
3423#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3424#ifdef CONFIG_IXGBE_DCB
3425 if (ixgbe_cache_ring_dcb(adapter))
3426 return;
3427
3428#endif
c4cf55e5
PWJ		 3429 if (ixgbe_cache_ring_fdir(adapter))
3430 return;
3431
bc97114d
PWJ		 3432 if (ixgbe_cache_ring_rss(adapter))
3433 return;
021230d4
AV		 3434}
3435
9a799d71
AK		 3436/**
3437 * ixgbe_alloc_queues - Allocate memory for all rings
3438 * @adapter: board private structure to initialize
3439 *
3440 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 3441 * number of queues at compile-time. The polling_netdev array is
3442 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 3443 **/
2f90b865 3444static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 3445{
3446 int i;
3447
3448 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 3449 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 3450 if (!adapter->tx_ring)
021230d4 3451 goto err_tx_ring_allocation;
9a799d71
AK		 3452
3453 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 3454 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 3455 if (!adapter->rx_ring)
3456 goto err_rx_ring_allocation;
9a799d71 3457
021230d4 3458 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 3459 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 3460 adapter->tx_ring[i].queue_index = i;
3461 }
b9804972 3462
9a799d71 3463 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 3464 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 3465 adapter->rx_ring[i].queue_index = i;
3466 }
3467
3468 ixgbe_cache_ring_register(adapter);
3469
3470 return 0;
3471
3472err_rx_ring_allocation:
3473 kfree(adapter->tx_ring);
3474err_tx_ring_allocation:
3475 return -ENOMEM;
3476}
3477
3478/**
3479 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3480 * @adapter: board private structure to initialize
3481 *
3482 * Attempt to configure the interrupts using the best available
3483 * capabilities of the hardware and the kernel.
3484 **/
feea6a57 3485static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 3486{
8be0e467 3487 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 3488 int err = 0;
3489 int vector, v_budget;
3490
3491 /*
3492 * It's easy to be greedy for MSI-X vectors, but it really
3493 * doesn't do us much good if we have a lot more vectors
3494 * than CPU's. So let's be conservative and only ask for
3495 * (roughly) twice the number of vectors as there are CPU's.
3496 */
3497 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
b4617240 3498 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
021230d4
AV		 3499
3500 /*
3501 * At the same time, hardware can only support a maximum of
8be0e467
PW		 3502 * hw.mac->max_msix_vectors vectors. With features
3503 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3504 * descriptor queues supported by our device. Thus, we cap it off in
3505 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3506 */
8be0e467 3507 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3508
3509 /* A failure in MSI-X entry allocation isn't fatal, but it does
3510 * mean we disable MSI-X capabilities of the adapter. */
3511 adapter->msix_entries = kcalloc(v_budget,
b4617240 3512 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 3513 if (adapter->msix_entries) {
3514 for (vector = 0; vector < v_budget; vector++)
3515 adapter->msix_entries[vector].entry = vector;
021230d4 3516
7a921c93 3517 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 3518
7a921c93
AD		 3519 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3520 goto out;
3521 }
021230d4 3522
7a921c93
AD		 3523 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3524 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 3525 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3526 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3527 adapter->atr_sample_rate = 0;
7a921c93 3528 ixgbe_set_num_queues(adapter);
021230d4 3529
021230d4
AV		 3530 err = pci_enable_msi(adapter->pdev);
3531 if (!err) {
3532 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3533 } else {
3534 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 3535 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 3536 /* reset err */
3537 err = 0;
3538 }
3539
3540out:
021230d4
AV		 3541 return err;
3542}
3543
7a921c93
AD		 3544/**
3545 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3546 * @adapter: board private structure to initialize
3547 *
3548 * We allocate one q_vector per queue interrupt. If allocation fails we
3549 * return -ENOMEM.
3550 **/
3551static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3552{
3553 int q_idx, num_q_vectors;
3554 struct ixgbe_q_vector *q_vector;
3555 int napi_vectors;
3556 int (*poll)(struct napi_struct *, int);
3557
3558 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3559 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3560 napi_vectors = adapter->num_rx_queues;
91281fd3 3561 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 3562 } else {
3563 num_q_vectors = 1;
3564 napi_vectors = 1;
3565 poll = &ixgbe_poll;
3566 }
3567
3568 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3569 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3570 if (!q_vector)
3571 goto err_out;
3572 q_vector->adapter = adapter;
7a921c93 3573 q_vector->eitr = adapter->eitr_param;
fe49f04a 3574 q_vector->v_idx = q_idx;
91281fd3 3575 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 3576 adapter->q_vector[q_idx] = q_vector;
3577 }
3578
3579 return 0;
3580
3581err_out:
3582 while (q_idx) {
3583 q_idx--;
3584 q_vector = adapter->q_vector[q_idx];
3585 netif_napi_del(&q_vector->napi);
3586 kfree(q_vector);
3587 adapter->q_vector[q_idx] = NULL;
3588 }
3589 return -ENOMEM;
3590}
3591
3592/**
3593 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3594 * @adapter: board private structure to initialize
3595 *
3596 * This function frees the memory allocated to the q_vectors. In addition if
3597 * NAPI is enabled it will delete any references to the NAPI struct prior
3598 * to freeing the q_vector.
3599 **/
3600static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3601{
3602 int q_idx, num_q_vectors;
7a921c93 3603
91281fd3 3604 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 3605 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 3606 else
7a921c93 3607 num_q_vectors = 1;
7a921c93
AD		 3608
3609 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3610 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 3611 adapter->q_vector[q_idx] = NULL;
91281fd3 3612 netif_napi_del(&q_vector->napi);
7a921c93
AD		 3613 kfree(q_vector);
3614 }
3615}
3616
7b25cdba 3617static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 3618{
3619 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3620 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3621 pci_disable_msix(adapter->pdev);
3622 kfree(adapter->msix_entries);
3623 adapter->msix_entries = NULL;
3624 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3625 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3626 pci_disable_msi(adapter->pdev);
3627 }
3628 return;
3629}
3630
3631/**
3632 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3633 * @adapter: board private structure to initialize
3634 *
3635 * We determine which interrupt scheme to use based on...
3636 * - Kernel support (MSI, MSI-X)
3637 * - which can be user-defined (via MODULE_PARAM)
3638 * - Hardware queue count (num_*_queues)
3639 * - defined by miscellaneous hardware support/features (RSS, etc.)
3640 **/
2f90b865 3641int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 3642{
3643 int err;
3644
3645 /* Number of supported queues */
3646 ixgbe_set_num_queues(adapter);
3647
021230d4
AV		 3648 err = ixgbe_set_interrupt_capability(adapter);
3649 if (err) {
3650 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3651 goto err_set_interrupt;
9a799d71
AK		 3652 }
3653
7a921c93
AD		 3654 err = ixgbe_alloc_q_vectors(adapter);
3655 if (err) {
3656 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3657 "vectors\n");
3658 goto err_alloc_q_vectors;
3659 }
3660
3661 err = ixgbe_alloc_queues(adapter);
3662 if (err) {
3663 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3664 goto err_alloc_queues;
3665 }
3666
021230d4 3667 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 3668 "Tx Queue count = %u\n",
3669 (adapter->num_rx_queues > 1) ? "Enabled" :
3670 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 3671
3672 set_bit(__IXGBE_DOWN, &adapter->state);
3673
9a799d71 3674 return 0;
021230d4 3675
7a921c93
AD		 3676err_alloc_queues:
3677 ixgbe_free_q_vectors(adapter);
3678err_alloc_q_vectors:
3679 ixgbe_reset_interrupt_capability(adapter);
021230d4 3680err_set_interrupt:
7a921c93
AD		 3681 return err;
3682}
3683
3684/**
3685 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3686 * @adapter: board private structure to clear interrupt scheme on
3687 *
3688 * We go through and clear interrupt specific resources and reset the structure
3689 * to pre-load conditions
3690 **/
3691void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3692{
021230d4
AV		 3693 kfree(adapter->tx_ring);
3694 kfree(adapter->rx_ring);
7a921c93
AD		 3695 adapter->tx_ring = NULL;
3696 adapter->rx_ring = NULL;
3697
3698 ixgbe_free_q_vectors(adapter);
3699 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 3700}
3701
c4900be0
DS		 3702/**
3703 * ixgbe_sfp_timer - worker thread to find a missing module
3704 * @data: pointer to our adapter struct
3705 **/
3706static void ixgbe_sfp_timer(unsigned long data)
3707{
3708 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3709
4df10466
JB		 3710 /*
3711 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 3712 * delays that sfp+ detection requires
3713 */
3714 schedule_work(&adapter->sfp_task);
3715}
3716
3717/**
3718 * ixgbe_sfp_task - worker thread to find a missing module
3719 * @work: pointer to work_struct containing our data
3720 **/
3721static void ixgbe_sfp_task(struct work_struct *work)
3722{
3723 struct ixgbe_adapter *adapter = container_of(work,
3724 struct ixgbe_adapter,
3725 sfp_task);
3726 struct ixgbe_hw *hw = &adapter->hw;
3727
3728 if ((hw->phy.type == ixgbe_phy_nl) &&
3729 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3730 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 3731 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 3732 goto reschedule;
3733 ret = hw->phy.ops.reset(hw);
3734 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 3735 dev_err(&adapter->pdev->dev, "failed to initialize "
3736 "because an unsupported SFP+ module type "
3737 "was detected.\n"
3738 "Reload the driver after installing a "
3739 "supported module.\n");
c4900be0
DS		 3740 unregister_netdev(adapter->netdev);
3741 } else {
3742 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3743 hw->phy.sfp_type);
3744 }
3745 /* don't need this routine any more */
3746 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3747 }
3748 return;
3749reschedule:
3750 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3751 mod_timer(&adapter->sfp_timer,
3752 round_jiffies(jiffies + (2 * HZ)));
3753}
3754
9a799d71
AK		 3755/**
3756 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3757 * @adapter: board private structure to initialize
3758 *
3759 * ixgbe_sw_init initializes the Adapter private data structure.
3760 * Fields are initialized based on PCI device information and
3761 * OS network device settings (MTU size).
3762 **/
3763static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3764{
3765 struct ixgbe_hw *hw = &adapter->hw;
3766 struct pci_dev *pdev = adapter->pdev;
021230d4 3767 unsigned int rss;
7a6b6f51 3768#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3769 int j;
3770 struct tc_configuration *tc;
3771#endif
021230d4 3772
c44ade9e
JB		 3773 /* PCI config space info */
3774
3775 hw->vendor_id = pdev->vendor;
3776 hw->device_id = pdev->device;
3777 hw->revision_id = pdev->revision;
3778 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3779 hw->subsystem_device_id = pdev->subsystem_device;
3780
021230d4
AV		 3781 /* Set capability flags */
3782 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3783 adapter->ring_feature[RING_F_RSS].indices = rss;
3784 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 3785 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 3786 if (hw->mac.type == ixgbe_mac_82598EB) {
3787 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3788 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 3789 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 3790 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 3791 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 3792 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3793 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
c4cf55e5
PWJ		 3794 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3795 adapter->ring_feature[RING_F_FDIR].indices =
3796 IXGBE_MAX_FDIR_INDICES;
3797 adapter->atr_sample_rate = 20;
3798 adapter->fdir_pballoc = 0;
eacd73f7 3799#ifdef IXGBE_FCOE
0d551589
YZ		 3800 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3801 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3802 adapter->ring_feature[RING_F_FCOE].indices = 0;
6ee16520
YZ		 3803 /* Default traffic class to use for FCoE */
3804 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
eacd73f7 3805#endif /* IXGBE_FCOE */
f8212f97 3806 }
2f90b865 3807
7a6b6f51 3808#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3809 /* Configure DCB traffic classes */
3810 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3811 tc = &adapter->dcb_cfg.tc_config[j];
3812 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3813 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3814 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3815 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3816 tc->dcb_pfc = pfc_disabled;
3817 }
3818 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3819 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3820 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 3821 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 3822 adapter->dcb_cfg.round_robin_enable = false;
3823 adapter->dcb_set_bitmap = 0x00;
3824 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3825 adapter->ring_feature[RING_F_DCB].indices);
3826
3827#endif
9a799d71
AK		 3828
3829 /* default flow control settings */
cd7664f6 3830 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 3831 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 3832#ifdef CONFIG_DCB
3833 adapter->last_lfc_mode = hw->fc.current_mode;
3834#endif
2b9ade93
JB		 3835 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3836 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3837 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3838 hw->fc.send_xon = true;
71fd570b 3839 hw->fc.disable_fc_autoneg = false;
9a799d71 3840
30efa5a3
JB		 3841 /* enable itr by default in dynamic mode */
3842 adapter->itr_setting = 1;
3843 adapter->eitr_param = 20000;
3844
3845 /* set defaults for eitr in MegaBytes */
3846 adapter->eitr_low = 10;
3847 adapter->eitr_high = 20;
3848
3849 /* set default ring sizes */
3850 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3851 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3852
9a799d71 3853 /* initialize eeprom parameters */
c44ade9e 3854 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 3855 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3856 return -EIO;
3857 }
3858
021230d4 3859 /* enable rx csum by default */
9a799d71
AK		 3860 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3861
9a799d71
AK		 3862 set_bit(__IXGBE_DOWN, &adapter->state);
3863
3864 return 0;
3865}
3866
3867/**
3868 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3869 * @adapter: board private structure
3a581073 3870 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3871 *
3872 * Return 0 on success, negative on failure
3873 **/
3874int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 3875 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3876{
3877 struct pci_dev *pdev = adapter->pdev;
3878 int size;
3879
3a581073
JB		 3880 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3881 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 3882 if (!tx_ring->tx_buffer_info)
3883 goto err;
3a581073 3884 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 3885
3886 /* round up to nearest 4K */
12207e49 3887 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 3888 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 3889
3a581073
JB		 3890 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3891 &tx_ring->dma);
e01c31a5
JB		 3892 if (!tx_ring->desc)
3893 goto err;
9a799d71 3894
3a581073
JB		 3895 tx_ring->next_to_use = 0;
3896 tx_ring->next_to_clean = 0;
3897 tx_ring->work_limit = tx_ring->count;
9a799d71 3898 return 0;
e01c31a5
JB		 3899
3900err:
3901 vfree(tx_ring->tx_buffer_info);
3902 tx_ring->tx_buffer_info = NULL;
3903 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3904 "descriptor ring\n");
3905 return -ENOMEM;
9a799d71
AK		 3906}
3907
69888674
AD		 3908/**
3909 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3910 * @adapter: board private structure
3911 *
3912 * If this function returns with an error, then it's possible one or
3913 * more of the rings is populated (while the rest are not). It is the
3914 * callers duty to clean those orphaned rings.
3915 *
3916 * Return 0 on success, negative on failure
3917 **/
3918static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3919{
3920 int i, err = 0;
3921
3922 for (i = 0; i < adapter->num_tx_queues; i++) {
3923 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3924 if (!err)
3925 continue;
3926 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3927 break;
3928 }
3929
3930 return err;
3931}
3932
9a799d71
AK		 3933/**
3934 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3935 * @adapter: board private structure
3a581073 3936 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3937 *
3938 * Returns 0 on success, negative on failure
3939 **/
3940int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 3941 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3942{
3943 struct pci_dev *pdev = adapter->pdev;
021230d4 3944 int size;
9a799d71 3945
3a581073
JB		 3946 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3947 rx_ring->rx_buffer_info = vmalloc(size);
3948 if (!rx_ring->rx_buffer_info) {
9a799d71 3949 DPRINTK(PROBE, ERR,
b4617240 3950 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 3951 goto alloc_failed;
9a799d71 3952 }
3a581073 3953 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 3954
9a799d71 3955 /* Round up to nearest 4K */
3a581073
JB		 3956 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3957 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 3958
3a581073 3959 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 3960
3a581073 3961 if (!rx_ring->desc) {
9a799d71 3962 DPRINTK(PROBE, ERR,
b4617240 3963 "Memory allocation failed for the rx desc ring\n");
3a581073 3964 vfree(rx_ring->rx_buffer_info);
177db6ff 3965 goto alloc_failed;
9a799d71
AK		 3966 }
3967
3a581073
JB		 3968 rx_ring->next_to_clean = 0;
3969 rx_ring->next_to_use = 0;
9a799d71
AK		 3970
3971 return 0;
177db6ff
MC		 3972
3973alloc_failed:
177db6ff 3974 return -ENOMEM;
9a799d71
AK		 3975}
3976
69888674
AD		 3977/**
3978 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3979 * @adapter: board private structure
3980 *
3981 * If this function returns with an error, then it's possible one or
3982 * more of the rings is populated (while the rest are not). It is the
3983 * callers duty to clean those orphaned rings.
3984 *
3985 * Return 0 on success, negative on failure
3986 **/
3987
3988static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3989{
3990 int i, err = 0;
3991
3992 for (i = 0; i < adapter->num_rx_queues; i++) {
3993 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3994 if (!err)
3995 continue;
3996 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3997 break;
3998 }
3999
4000 return err;
4001}
4002
9a799d71
AK		 4003/**
4004 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4005 * @adapter: board private structure
4006 * @tx_ring: Tx descriptor ring for a specific queue
4007 *
4008 * Free all transmit software resources
4009 **/
c431f97e
JB		 4010void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4011 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4012{
4013 struct pci_dev *pdev = adapter->pdev;
4014
4015 ixgbe_clean_tx_ring(adapter, tx_ring);
4016
4017 vfree(tx_ring->tx_buffer_info);
4018 tx_ring->tx_buffer_info = NULL;
4019
4020 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4021
4022 tx_ring->desc = NULL;
4023}
4024
4025/**
4026 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4027 * @adapter: board private structure
4028 *
4029 * Free all transmit software resources
4030 **/
4031static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4032{
4033 int i;
4034
4035 for (i = 0; i < adapter->num_tx_queues; i++)
9891ca7c
JB		 4036 if (adapter->tx_ring[i].desc)
4037 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 4038}
4039
4040/**
b4617240 4041 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4042 * @adapter: board private structure
4043 * @rx_ring: ring to clean the resources from
4044 *
4045 * Free all receive software resources
4046 **/
c431f97e
JB		 4047void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4048 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4049{
4050 struct pci_dev *pdev = adapter->pdev;
4051
4052 ixgbe_clean_rx_ring(adapter, rx_ring);
4053
4054 vfree(rx_ring->rx_buffer_info);
4055 rx_ring->rx_buffer_info = NULL;
4056
4057 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4058
4059 rx_ring->desc = NULL;
4060}
4061
4062/**
4063 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4064 * @adapter: board private structure
4065 *
4066 * Free all receive software resources
4067 **/
4068static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4069{
4070 int i;
4071
4072 for (i = 0; i < adapter->num_rx_queues; i++)
9891ca7c
JB		 4073 if (adapter->rx_ring[i].desc)
4074 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 4075}
4076
9a799d71
AK		 4077/**
4078 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4079 * @netdev: network interface device structure
4080 * @new_mtu: new value for maximum frame size
4081 *
4082 * Returns 0 on success, negative on failure
4083 **/
4084static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4085{
4086 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4087 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4088
42c783c5
JB		 4089 /* MTU < 68 is an error and causes problems on some kernels */
4090 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 4091 return -EINVAL;
4092
021230d4 4093 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 4094 netdev->mtu, new_mtu);
021230d4 4095 /* must set new MTU before calling down or up */
9a799d71
AK		 4096 netdev->mtu = new_mtu;
4097
d4f80882
AV		 4098 if (netif_running(netdev))
4099 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4100
4101 return 0;
4102}
4103
4104/**
4105 * ixgbe_open - Called when a network interface is made active
4106 * @netdev: network interface device structure
4107 *
4108 * Returns 0 on success, negative value on failure
4109 *
4110 * The open entry point is called when a network interface is made
4111 * active by the system (IFF_UP). At this point all resources needed
4112 * for transmit and receive operations are allocated, the interrupt
4113 * handler is registered with the OS, the watchdog timer is started,
4114 * and the stack is notified that the interface is ready.
4115 **/
4116static int ixgbe_open(struct net_device *netdev)
4117{
4118 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4119 int err;
4bebfaa5
AK		 4120
4121 /* disallow open during test */
4122 if (test_bit(__IXGBE_TESTING, &adapter->state))
4123 return -EBUSY;
9a799d71 4124
54386467
JB		 4125 netif_carrier_off(netdev);
4126
9a799d71
AK		 4127 /* allocate transmit descriptors */
4128 err = ixgbe_setup_all_tx_resources(adapter);
4129 if (err)
4130 goto err_setup_tx;
4131
9a799d71
AK		 4132 /* allocate receive descriptors */
4133 err = ixgbe_setup_all_rx_resources(adapter);
4134 if (err)
4135 goto err_setup_rx;
4136
4137 ixgbe_configure(adapter);
4138
021230d4 4139 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4140 if (err)
4141 goto err_req_irq;
4142
9a799d71
AK		 4143 err = ixgbe_up_complete(adapter);
4144 if (err)
4145 goto err_up;
4146
d55b53ff
JK		 4147 netif_tx_start_all_queues(netdev);
4148
9a799d71
AK		 4149 return 0;
4150
4151err_up:
5eba3699 4152 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4153 ixgbe_free_irq(adapter);
4154err_req_irq:
9a799d71 4155err_setup_rx:
a20a1199 4156 ixgbe_free_all_rx_resources(adapter);
9a799d71 4157err_setup_tx:
a20a1199 4158 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 4159 ixgbe_reset(adapter);
4160
4161 return err;
4162}
4163
4164/**
4165 * ixgbe_close - Disables a network interface
4166 * @netdev: network interface device structure
4167 *
4168 * Returns 0, this is not allowed to fail
4169 *
4170 * The close entry point is called when an interface is de-activated
4171 * by the OS. The hardware is still under the drivers control, but
4172 * needs to be disabled. A global MAC reset is issued to stop the
4173 * hardware, and all transmit and receive resources are freed.
4174 **/
4175static int ixgbe_close(struct net_device *netdev)
4176{
4177 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4178
4179 ixgbe_down(adapter);
4180 ixgbe_free_irq(adapter);
4181
4182 ixgbe_free_all_tx_resources(adapter);
4183 ixgbe_free_all_rx_resources(adapter);
4184
5eba3699 4185 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4186
4187 return 0;
4188}
4189
b3c8b4ba
AD		 4190#ifdef CONFIG_PM
4191static int ixgbe_resume(struct pci_dev *pdev)
4192{
4193 struct net_device *netdev = pci_get_drvdata(pdev);
4194 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4195 u32 err;
4196
4197 pci_set_power_state(pdev, PCI_D0);
4198 pci_restore_state(pdev);
9ce77666 4199
4200 err = pci_enable_device_mem(pdev);
b3c8b4ba 4201 if (err) {
69888674 4202 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 4203 "suspend\n");
4204 return err;
4205 }
4206 pci_set_master(pdev);
4207
dd4d8ca6 4208 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 4209
4210 err = ixgbe_init_interrupt_scheme(adapter);
4211 if (err) {
4212 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4213 "device\n");
4214 return err;
4215 }
4216
b3c8b4ba
AD		 4217 ixgbe_reset(adapter);
4218
495dce12
WJP		 4219 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4220
b3c8b4ba
AD		 4221 if (netif_running(netdev)) {
4222 err = ixgbe_open(adapter->netdev);
4223 if (err)
4224 return err;
4225 }
4226
4227 netif_device_attach(netdev);
4228
4229 return 0;
4230}
b3c8b4ba 4231#endif /* CONFIG_PM */
9d8d05ae
RW		 4232
4233static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 4234{
4235 struct net_device *netdev = pci_get_drvdata(pdev);
4236 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 4237 struct ixgbe_hw *hw = &adapter->hw;
4238 u32 ctrl, fctrl;
4239 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4240#ifdef CONFIG_PM
4241 int retval = 0;
4242#endif
4243
4244 netif_device_detach(netdev);
4245
4246 if (netif_running(netdev)) {
4247 ixgbe_down(adapter);
4248 ixgbe_free_irq(adapter);
4249 ixgbe_free_all_tx_resources(adapter);
4250 ixgbe_free_all_rx_resources(adapter);
4251 }
7a921c93 4252 ixgbe_clear_interrupt_scheme(adapter);
b3c8b4ba
AD		 4253
4254#ifdef CONFIG_PM
4255 retval = pci_save_state(pdev);
4256 if (retval)
4257 return retval;
4df10466 4258
b3c8b4ba 4259#endif
e8e26350
PW		 4260 if (wufc) {
4261 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4262
e8e26350
PW		 4263 /* turn on all-multi mode if wake on multicast is enabled */
4264 if (wufc & IXGBE_WUFC_MC) {
4265 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4266 fctrl |= IXGBE_FCTRL_MPE;
4267 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4268 }
4269
4270 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4271 ctrl |= IXGBE_CTRL_GIO_DIS;
4272 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4273
4274 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4275 } else {
4276 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4277 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4278 }
4279
dd4d8ca6
DS		 4280 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4281 pci_wake_from_d3(pdev, true);
4282 else
4283 pci_wake_from_d3(pdev, false);
b3c8b4ba 4284
9d8d05ae
RW		 4285 *enable_wake = !!wufc;
4286
b3c8b4ba
AD		 4287 ixgbe_release_hw_control(adapter);
4288
4289 pci_disable_device(pdev);
4290
9d8d05ae
RW		 4291 return 0;
4292}
4293
4294#ifdef CONFIG_PM
4295static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4296{
4297 int retval;
4298 bool wake;
4299
4300 retval = __ixgbe_shutdown(pdev, &wake);
4301 if (retval)
4302 return retval;
4303
4304 if (wake) {
4305 pci_prepare_to_sleep(pdev);
4306 } else {
4307 pci_wake_from_d3(pdev, false);
4308 pci_set_power_state(pdev, PCI_D3hot);
4309 }
b3c8b4ba
AD		 4310
4311 return 0;
4312}
9d8d05ae 4313#endif /* CONFIG_PM */
b3c8b4ba
AD		 4314
4315static void ixgbe_shutdown(struct pci_dev *pdev)
4316{
9d8d05ae
RW		 4317 bool wake;
4318
4319 __ixgbe_shutdown(pdev, &wake);
4320
4321 if (system_state == SYSTEM_POWER_OFF) {
4322 pci_wake_from_d3(pdev, wake);
4323 pci_set_power_state(pdev, PCI_D3hot);
4324 }
b3c8b4ba
AD		 4325}
4326
9a799d71
AK		 4327/**
4328 * ixgbe_update_stats - Update the board statistics counters.
4329 * @adapter: board private structure
4330 **/
4331void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4332{
4333 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 4334 u64 total_mpc = 0;
4335 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71 4336
d51019a4 4337 if (hw->mac.type == ixgbe_mac_82599EB) {
f8212f97 4338 u64 rsc_count = 0;
d51019a4
PW		 4339 for (i = 0; i < 16; i++)
4340 adapter->hw_rx_no_dma_resources +=
4341 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
f8212f97
AD		 4342 for (i = 0; i < adapter->num_rx_queues; i++)
4343 rsc_count += adapter->rx_ring[i].rsc_count;
4344 adapter->rsc_count = rsc_count;
d51019a4
PW		 4345 }
4346
9a799d71 4347 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 4348 for (i = 0; i < 8; i++) {
4349 /* for packet buffers not used, the register should read 0 */
4350 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4351 missed_rx += mpc;
4352 adapter->stats.mpc[i] += mpc;
4353 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 4354 if (hw->mac.type == ixgbe_mac_82598EB)
4355 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 4356 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4357 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4358 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4359 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 4360 if (hw->mac.type == ixgbe_mac_82599EB) {
4361 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4362 IXGBE_PXONRXCNT(i));
4363 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4364 IXGBE_PXOFFRXCNT(i));
4365 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 4366 } else {
4367 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4368 IXGBE_PXONRXC(i));
4369 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4370 IXGBE_PXOFFRXC(i));
4371 }
2f90b865
AD		 4372 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4373 IXGBE_PXONTXC(i));
2f90b865 4374 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 4375 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 4376 }
4377 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4378 /* work around hardware counting issue */
4379 adapter->stats.gprc -= missed_rx;
4380
4381 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350
PW		 4382 if (hw->mac.type == ixgbe_mac_82599EB) {
4383 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4384 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
4385 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4386 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
4387 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4388 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4389 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4390 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
c4cf55e5
PWJ		 4391 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4392 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c
YZ		 4393#ifdef IXGBE_FCOE
4394 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4395 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4396 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4397 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4398 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4399 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4400#endif /* IXGBE_FCOE */
e8e26350
PW		 4401 } else {
4402 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4403 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4404 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4405 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4406 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4407 }
9a799d71
AK		 4408 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4409 adapter->stats.bprc += bprc;
4410 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 4411 if (hw->mac.type == ixgbe_mac_82598EB)
4412 adapter->stats.mprc -= bprc;
9a799d71
AK		 4413 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4414 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4415 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4416 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4417 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4418 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4419 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 4420 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 4421 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4422 adapter->stats.lxontxc += lxon;
4423 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4424 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 4425 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4426 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 4427 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4428 /*
4429 * 82598 errata - tx of flow control packets is included in tx counters
4430 */
4431 xon_off_tot = lxon + lxoff;
4432 adapter->stats.gptc -= xon_off_tot;
4433 adapter->stats.mptc -= xon_off_tot;
4434 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 4435 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4436 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4437 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 4438 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4439 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 4440 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 4441 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4442 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4443 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4444 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4445 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 4446 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4447
4448 /* Fill out the OS statistics structure */
9a799d71
AK		 4449 adapter->net_stats.multicast = adapter->stats.mprc;
4450
4451 /* Rx Errors */
4452 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
b4617240 4453 adapter->stats.rlec;
9a799d71
AK		 4454 adapter->net_stats.rx_dropped = 0;
4455 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4456 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 4457 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 4458}
4459
4460/**
4461 * ixgbe_watchdog - Timer Call-back
4462 * @data: pointer to adapter cast into an unsigned long
4463 **/
4464static void ixgbe_watchdog(unsigned long data)
4465{
4466 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 4467 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 4468 u64 eics = 0;
4469 int i;
cf8280ee 4470
fe49f04a
AD		 4471 /*
4472 * Do the watchdog outside of interrupt context due to the lovely
4473 * delays that some of the newer hardware requires
4474 */
22d5a71b 4475
fe49f04a
AD		 4476 if (test_bit(__IXGBE_DOWN, &adapter->state))
4477 goto watchdog_short_circuit;
22d5a71b 4478
fe49f04a
AD		 4479 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4480 /*
4481 * for legacy and MSI interrupts don't set any bits
4482 * that are enabled for EIAM, because this operation
4483 * would set *both* EIMS and EICS for any bit in EIAM
4484 */
4485 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4486 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4487 goto watchdog_reschedule;
4488 }
4489
4490 /* get one bit for every active tx/rx interrupt vector */
4491 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4492 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4493 if (qv->rxr_count || qv->txr_count)
4494 eics |= ((u64)1 << i);
cf8280ee 4495 }
9a799d71 4496
fe49f04a
AD		 4497 /* Cause software interrupt to ensure rx rings are cleaned */
4498 ixgbe_irq_rearm_queues(adapter, eics);
4499
4500watchdog_reschedule:
4501 /* Reset the timer */
4502 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4503
4504watchdog_short_circuit:
cf8280ee
JB		 4505 schedule_work(&adapter->watchdog_task);
4506}
4507
e8e26350
PW		 4508/**
4509 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4510 * @work: pointer to work_struct containing our data
4511 **/
4512static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4513{
4514 struct ixgbe_adapter *adapter = container_of(work,
4515 struct ixgbe_adapter,
4516 multispeed_fiber_task);
4517 struct ixgbe_hw *hw = &adapter->hw;
4518 u32 autoneg;
8620a103 4519 bool negotiation;
e8e26350
PW		 4520
4521 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 4522 autoneg = hw->phy.autoneg_advertised;
4523 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103
MC		 4524 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4525 if (hw->mac.ops.setup_link)
4526 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 4527 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4528 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4529}
4530
4531/**
4532 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4533 * @work: pointer to work_struct containing our data
4534 **/
4535static void ixgbe_sfp_config_module_task(struct work_struct *work)
4536{
4537 struct ixgbe_adapter *adapter = container_of(work,
4538 struct ixgbe_adapter,
4539 sfp_config_module_task);
4540 struct ixgbe_hw *hw = &adapter->hw;
4541 u32 err;
4542
4543 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 4544
4545 /* Time for electrical oscillations to settle down */
4546 msleep(100);
e8e26350 4547 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4548
e8e26350 4549 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 4550 dev_err(&adapter->pdev->dev, "failed to initialize because "
4551 "an unsupported SFP+ module type was detected.\n"
4552 "Reload the driver after installing a supported "
4553 "module.\n");
63d6e1d8 4554 unregister_netdev(adapter->netdev);
e8e26350
PW		 4555 return;
4556 }
4557 hw->mac.ops.setup_sfp(hw);
4558
8d1c3c07 4559 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 4560 /* This will also work for DA Twinax connections */
4561 schedule_work(&adapter->multispeed_fiber_task);
4562 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4563}
4564
c4cf55e5
PWJ		 4565/**
4566 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4567 * @work: pointer to work_struct containing our data
4568 **/
4569static void ixgbe_fdir_reinit_task(struct work_struct *work)
4570{
4571 struct ixgbe_adapter *adapter = container_of(work,
4572 struct ixgbe_adapter,
4573 fdir_reinit_task);
4574 struct ixgbe_hw *hw = &adapter->hw;
4575 int i;
4576
4577 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4578 for (i = 0; i < adapter->num_tx_queues; i++)
4579 set_bit(__IXGBE_FDIR_INIT_DONE,
4580 &(adapter->tx_ring[i].reinit_state));
4581 } else {
4582 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4583 "ignored adding FDIR ATR filters \n");
4584 }
4585 /* Done FDIR Re-initialization, enable transmits */
4586 netif_tx_start_all_queues(adapter->netdev);
4587}
4588
cf8280ee 4589/**
69888674
AD		 4590 * ixgbe_watchdog_task - worker thread to bring link up
4591 * @work: pointer to work_struct containing our data
cf8280ee
JB		 4592 **/
4593static void ixgbe_watchdog_task(struct work_struct *work)
4594{
4595 struct ixgbe_adapter *adapter = container_of(work,
4596 struct ixgbe_adapter,
4597 watchdog_task);
4598 struct net_device *netdev = adapter->netdev;
4599 struct ixgbe_hw *hw = &adapter->hw;
4600 u32 link_speed = adapter->link_speed;
4601 bool link_up = adapter->link_up;
bc59fcda
NS		 4602 int i;
4603 struct ixgbe_ring *tx_ring;
4604 int some_tx_pending = 0;
cf8280ee
JB		 4605
4606 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4607
4608 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4609 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 4610 if (link_up) {
4611#ifdef CONFIG_DCB
4612 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4613 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 4614 hw->mac.ops.fc_enable(hw, i);
264857b8 4615 } else {
620fa036 4616 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 4617 }
4618#else
620fa036 4619 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 4620#endif
4621 }
4622
cf8280ee
JB		 4623 if (link_up ||
4624 time_after(jiffies, (adapter->link_check_timeout +
4625 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 4626 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 4627 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 4628 }
4629 adapter->link_up = link_up;
4630 adapter->link_speed = link_speed;
4631 }
9a799d71
AK		 4632
4633 if (link_up) {
4634 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 4635 bool flow_rx, flow_tx;
4636
4637 if (hw->mac.type == ixgbe_mac_82599EB) {
4638 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4639 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 4640 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
4641 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 4642 } else {
4643 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4644 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 4645 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
4646 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 4647 }
4648
a46e534b
JK		 4649 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4650 "Flow Control: %s\n",
4651 netdev->name,
4652 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4653 "10 Gbps" :
4654 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4655 "1 Gbps" : "unknown speed")),
e8e26350
PW		 4656 ((flow_rx && flow_tx) ? "RX/TX" :
4657 (flow_rx ? "RX" :
4658 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 4659
4660 netif_carrier_on(netdev);
9a799d71
AK		 4661 } else {
4662 /* Force detection of hung controller */
4663 adapter->detect_tx_hung = true;
4664 }
4665 } else {
cf8280ee
JB		 4666 adapter->link_up = false;
4667 adapter->link_speed = 0;
9a799d71 4668 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 4669 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4670 netdev->name);
9a799d71 4671 netif_carrier_off(netdev);
9a799d71
AK		 4672 }
4673 }
4674
bc59fcda
NS		 4675 if (!netif_carrier_ok(netdev)) {
4676 for (i = 0; i < adapter->num_tx_queues; i++) {
4677 tx_ring = &adapter->tx_ring[i];
4678 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4679 some_tx_pending = 1;
4680 break;
4681 }
4682 }
4683
4684 if (some_tx_pending) {
4685 /* We've lost link, so the controller stops DMA,
4686 * but we've got queued Tx work that's never going
4687 * to get done, so reset controller to flush Tx.
4688 * (Do the reset outside of interrupt context).
4689 */
4690 schedule_work(&adapter->reset_task);
4691 }
4692 }
4693
9a799d71 4694 ixgbe_update_stats(adapter);
cf8280ee 4695 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 4696}
4697
9a799d71 4698static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 4699 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4700 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 4701{
4702 struct ixgbe_adv_tx_context_desc *context_desc;
4703 unsigned int i;
4704 int err;
4705 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 4706 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4707 u32 mss_l4len_idx, l4len;
9a799d71
AK		 4708
4709 if (skb_is_gso(skb)) {
4710 if (skb_header_cloned(skb)) {
4711 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4712 if (err)
4713 return err;
4714 }
4715 l4len = tcp_hdrlen(skb);
4716 *hdr_len += l4len;
4717
8327d000 4718 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 4719 struct iphdr *iph = ip_hdr(skb);
4720 iph->tot_len = 0;
4721 iph->check = 0;
4722 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 4723 iph->daddr, 0,
4724 IPPROTO_TCP,
4725 0);
9a799d71
AK		 4726 adapter->hw_tso_ctxt++;
4727 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4728 ipv6_hdr(skb)->payload_len = 0;
4729 tcp_hdr(skb)->check =
4730 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 4731 &ipv6_hdr(skb)->daddr,
4732 0, IPPROTO_TCP, 0);
9a799d71
AK		 4733 adapter->hw_tso6_ctxt++;
4734 }
4735
4736 i = tx_ring->next_to_use;
4737
4738 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4739 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4740
4741 /* VLAN MACLEN IPLEN */
4742 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4743 vlan_macip_lens |=
4744 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4745 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 4746 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4747 *hdr_len += skb_network_offset(skb);
4748 vlan_macip_lens |=
4749 (skb_transport_header(skb) - skb_network_header(skb));
4750 *hdr_len +=
4751 (skb_transport_header(skb) - skb_network_header(skb));
4752 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4753 context_desc->seqnum_seed = 0;
4754
4755 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 4756 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 4757 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 4758
8327d000 4759 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4760 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4761 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4762 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4763
4764 /* MSS L4LEN IDX */
9f8cdf4f 4765 mss_l4len_idx =
9a799d71
AK		 4766 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4767 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 4768 /* use index 1 for TSO */
4769 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4770 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4771
4772 tx_buffer_info->time_stamp = jiffies;
4773 tx_buffer_info->next_to_watch = i;
4774
4775 i++;
4776 if (i == tx_ring->count)
4777 i = 0;
4778 tx_ring->next_to_use = i;
4779
4780 return true;
4781 }
4782 return false;
4783}
4784
4785static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 4786 struct ixgbe_ring *tx_ring,
4787 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 4788{
4789 struct ixgbe_adv_tx_context_desc *context_desc;
4790 unsigned int i;
4791 struct ixgbe_tx_buffer *tx_buffer_info;
4792 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4793
4794 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4795 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4796 i = tx_ring->next_to_use;
4797 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4798 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4799
4800 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4801 vlan_macip_lens |=
4802 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4803 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 4804 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4805 if (skb->ip_summed == CHECKSUM_PARTIAL)
4806 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 4807 skb_network_header(skb));
9a799d71
AK		 4808
4809 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4810 context_desc->seqnum_seed = 0;
4811
4812 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 4813 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 4814
4815 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71 4816 switch (skb->protocol) {
09640e63 4817 case cpu_to_be16(ETH_P_IP):
9a799d71 4818 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 4819 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4820 type_tucmd_mlhl |=
b4617240 4821 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4822 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4823 type_tucmd_mlhl |=
4824 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4825 break;
09640e63 4826 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 4827 /* XXX what about other V6 headers?? */
4828 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4829 type_tucmd_mlhl |=
b4617240 4830 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4831 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4832 type_tucmd_mlhl |=
4833 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4834 break;
41825d71
AK		 4835 default:
4836 if (unlikely(net_ratelimit())) {
4837 DPRINTK(PROBE, WARNING,
4838 "partial checksum but proto=%x!\n",
4839 skb->protocol);
4840 }
4841 break;
4842 }
9a799d71
AK		 4843 }
4844
4845 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 4846 /* use index zero for tx checksum offload */
9a799d71
AK		 4847 context_desc->mss_l4len_idx = 0;
4848
4849 tx_buffer_info->time_stamp = jiffies;
4850 tx_buffer_info->next_to_watch = i;
9f8cdf4f 4851
9a799d71
AK		 4852 adapter->hw_csum_tx_good++;
4853 i++;
4854 if (i == tx_ring->count)
4855 i = 0;
4856 tx_ring->next_to_use = i;
4857
4858 return true;
4859 }
9f8cdf4f 4860
9a799d71
AK		 4861 return false;
4862}
4863
4864static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 4865 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 4866 struct sk_buff *skb, u32 tx_flags,
4867 unsigned int first)
9a799d71
AK		 4868{
4869 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 4870 unsigned int len;
4871 unsigned int total = skb->len;
9a799d71
AK		 4872 unsigned int offset = 0, size, count = 0, i;
4873 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4874 unsigned int f;
44df32c5 4875 dma_addr_t *map;
9a799d71
AK		 4876
4877 i = tx_ring->next_to_use;
4878
44df32c5
AD		 4879 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4880 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4881 return 0;
4882 }
4883
4884 map = skb_shinfo(skb)->dma_maps;
4885
eacd73f7
YZ		 4886 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4887 /* excluding fcoe_crc_eof for FCoE */
4888 total -= sizeof(struct fcoe_crc_eof);
4889
4890 len = min(skb_headlen(skb), total);
9a799d71
AK		 4891 while (len) {
4892 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4893 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4894
4895 tx_buffer_info->length = size;
042a53a9 4896 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
9a799d71
AK		 4897 tx_buffer_info->time_stamp = jiffies;
4898 tx_buffer_info->next_to_watch = i;
4899
4900 len -= size;
eacd73f7 4901 total -= size;
9a799d71
AK		 4902 offset += size;
4903 count++;
44df32c5
AD		 4904
4905 if (len) {
4906 i++;
4907 if (i == tx_ring->count)
4908 i = 0;
4909 }
9a799d71
AK		 4910 }
4911
4912 for (f = 0; f < nr_frags; f++) {
4913 struct skb_frag_struct *frag;
4914
4915 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 4916 len = min((unsigned int)frag->size, total);
44df32c5 4917 offset = 0;
9a799d71
AK		 4918
4919 while (len) {
44df32c5
AD		 4920 i++;
4921 if (i == tx_ring->count)
4922 i = 0;
4923
9a799d71
AK		 4924 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4925 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4926
4927 tx_buffer_info->length = size;
042a53a9 4928 tx_buffer_info->dma = map[f] + offset;
9a799d71
AK		 4929 tx_buffer_info->time_stamp = jiffies;
4930 tx_buffer_info->next_to_watch = i;
4931
4932 len -= size;
eacd73f7 4933 total -= size;
9a799d71
AK		 4934 offset += size;
4935 count++;
9a799d71 4936 }
eacd73f7
YZ		 4937 if (total == 0)
4938 break;
9a799d71 4939 }
44df32c5 4940
9a799d71
AK		 4941 tx_ring->tx_buffer_info[i].skb = skb;
4942 tx_ring->tx_buffer_info[first].next_to_watch = i;
4943
4944 return count;
4945}
4946
4947static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 4948 struct ixgbe_ring *tx_ring,
4949 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 4950{
4951 union ixgbe_adv_tx_desc *tx_desc = NULL;
4952 struct ixgbe_tx_buffer *tx_buffer_info;
4953 u32 olinfo_status = 0, cmd_type_len = 0;
4954 unsigned int i;
4955 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4956
4957 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4958
4959 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4960
4961 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4962 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4963
4964 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4965 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4966
4967 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4968 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 4969
4eeae6fd
PW		 4970 /* use index 1 context for tso */
4971 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4972 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4973 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 4974 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 4975
4976 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4977 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4978 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 4979
eacd73f7
YZ		 4980 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
4981 olinfo_status |= IXGBE_ADVTXD_CC;
4982 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4983 if (tx_flags & IXGBE_TX_FLAGS_FSO)
4984 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4985 }
4986
9a799d71
AK		 4987 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4988
4989 i = tx_ring->next_to_use;
4990 while (count--) {
4991 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4992 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4993 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4994 tx_desc->read.cmd_type_len =
b4617240 4995 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 4996 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 4997 i++;
4998 if (i == tx_ring->count)
4999 i = 0;
5000 }
5001
5002 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5003
5004 /*
5005 * Force memory writes to complete before letting h/w
5006 * know there are new descriptors to fetch. (Only
5007 * applicable for weak-ordered memory model archs,
5008 * such as IA-64).
5009 */
5010 wmb();
5011
5012 tx_ring->next_to_use = i;
5013 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5014}
5015
c4cf55e5
PWJ		 5016static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5017 int queue, u32 tx_flags)
5018{
5019 /* Right now, we support IPv4 only */
5020 struct ixgbe_atr_input atr_input;
5021 struct tcphdr *th;
5022 struct udphdr *uh;
5023 struct iphdr *iph = ip_hdr(skb);
5024 struct ethhdr *eth = (struct ethhdr *)skb->data;
5025 u16 vlan_id, src_port, dst_port, flex_bytes;
5026 u32 src_ipv4_addr, dst_ipv4_addr;
5027 u8 l4type = 0;
5028
5029 /* check if we're UDP or TCP */
5030 if (iph->protocol == IPPROTO_TCP) {
5031 th = tcp_hdr(skb);
5032 src_port = th->source;
5033 dst_port = th->dest;
5034 l4type |= IXGBE_ATR_L4TYPE_TCP;
5035 /* l4type IPv4 type is 0, no need to assign */
5036 } else if(iph->protocol == IPPROTO_UDP) {
5037 uh = udp_hdr(skb);
5038 src_port = uh->source;
5039 dst_port = uh->dest;
5040 l4type |= IXGBE_ATR_L4TYPE_UDP;
5041 /* l4type IPv4 type is 0, no need to assign */
5042 } else {
5043 /* Unsupported L4 header, just bail here */
5044 return;
5045 }
5046
5047 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5048
5049 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5050 IXGBE_TX_FLAGS_VLAN_SHIFT;
5051 src_ipv4_addr = iph->saddr;
5052 dst_ipv4_addr = iph->daddr;
5053 flex_bytes = eth->h_proto;
5054
5055 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5056 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5057 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5058 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5059 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5060 /* src and dst are inverted, think how the receiver sees them */
5061 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5062 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5063
5064 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5065 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5066}
5067
e092be60 5068static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5069 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 5070{
5071 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5072
30eba97a 5073 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5074 /* Herbert's original patch had:
5075 * smp_mb__after_netif_stop_queue();
5076 * but since that doesn't exist yet, just open code it. */
5077 smp_mb();
5078
5079 /* We need to check again in a case another CPU has just
5080 * made room available. */
5081 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5082 return -EBUSY;
5083
5084 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 5085 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5086 ++adapter->restart_queue;
5087 return 0;
5088}
5089
5090static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5091 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 5092{
5093 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5094 return 0;
5095 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5096}
5097
09a3b1f8
SH		 5098static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5099{
5100 struct ixgbe_adapter *adapter = netdev_priv(dev);
5101
c4cf55e5
PWJ		 5102 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5103 return smp_processor_id();
5104
09a3b1f8 5105 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
36e89d73 5106 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
09a3b1f8
SH		 5107
5108 return skb_tx_hash(dev, skb);
5109}
5110
3b29a56d
SH		 5111static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5112 struct net_device *netdev)
9a799d71
AK		 5113{
5114 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5115 struct ixgbe_ring *tx_ring;
9a799d71
AK		 5116 unsigned int first;
5117 unsigned int tx_flags = 0;
30eba97a
AV		 5118 u8 hdr_len = 0;
5119 int r_idx = 0, tso;
9a799d71
AK		 5120 int count = 0;
5121 unsigned int f;
9f8cdf4f 5122
9f8cdf4f
JB		 5123 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5124 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 5125 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5126 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5127 tx_flags |= (skb->queue_mapping << 13);
5128 }
5129 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5130 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5131 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
60127865
LL		 5132 if (skb->priority != TC_PRIO_CONTROL) {
5133 tx_flags |= (skb->queue_mapping << 13);
5134 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5135 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5136 } else {
5137 skb->queue_mapping =
5138 adapter->ring_feature[RING_F_DCB].indices-1;
5139 }
9a799d71 5140 }
eacd73f7 5141
60127865
LL		 5142 r_idx = skb->queue_mapping;
5143 tx_ring = &adapter->tx_ring[r_idx];
5144
eacd73f7
YZ		 5145 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5146 (skb->protocol == htons(ETH_P_FCOE)))
5147 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5148
5149 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 5150 if (skb_is_gso(skb) ||
5151 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 5152 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5153 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 5154 count++;
5155
9f8cdf4f
JB		 5156 count += TXD_USE_COUNT(skb_headlen(skb));
5157 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 5158 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5159
e092be60 5160 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 5161 adapter->tx_busy++;
9a799d71
AK		 5162 return NETDEV_TX_BUSY;
5163 }
9a799d71 5164
9a799d71 5165 first = tx_ring->next_to_use;
eacd73f7
YZ		 5166 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5167#ifdef IXGBE_FCOE
5168 /* setup tx offload for FCoE */
5169 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5170 if (tso < 0) {
5171 dev_kfree_skb_any(skb);
5172 return NETDEV_TX_OK;
5173 }
5174 if (tso)
5175 tx_flags |= IXGBE_TX_FLAGS_FSO;
5176#endif /* IXGBE_FCOE */
5177 } else {
5178 if (skb->protocol == htons(ETH_P_IP))
5179 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5180 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5181 if (tso < 0) {
5182 dev_kfree_skb_any(skb);
5183 return NETDEV_TX_OK;
5184 }
9a799d71 5185
eacd73f7
YZ		 5186 if (tso)
5187 tx_flags |= IXGBE_TX_FLAGS_TSO;
5188 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5189 (skb->ip_summed == CHECKSUM_PARTIAL))
5190 tx_flags |= IXGBE_TX_FLAGS_CSUM;
5191 }
9a799d71 5192
eacd73f7 5193 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 5194 if (count) {
c4cf55e5
PWJ		 5195 /* add the ATR filter if ATR is on */
5196 if (tx_ring->atr_sample_rate) {
5197 ++tx_ring->atr_count;
5198 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5199 test_bit(__IXGBE_FDIR_INIT_DONE,
5200 &tx_ring->reinit_state)) {
5201 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5202 tx_flags);
5203 tx_ring->atr_count = 0;
5204 }
5205 }
44df32c5
AD		 5206 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5207 hdr_len);
44df32c5 5208 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 5209
44df32c5
AD		 5210 } else {
5211 dev_kfree_skb_any(skb);
5212 tx_ring->tx_buffer_info[first].time_stamp = 0;
5213 tx_ring->next_to_use = first;
5214 }
9a799d71
AK		 5215
5216 return NETDEV_TX_OK;
5217}
5218
5219/**
5220 * ixgbe_get_stats - Get System Network Statistics
5221 * @netdev: network interface device structure
5222 *
5223 * Returns the address of the device statistics structure.
5224 * The statistics are actually updated from the timer callback.
5225 **/
5226static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5227{
5228 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5229
5230 /* only return the current stats */
5231 return &adapter->net_stats;
5232}
5233
5234/**
5235 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5236 * @netdev: network interface device structure
5237 * @p: pointer to an address structure
5238 *
5239 * Returns 0 on success, negative on failure
5240 **/
5241static int ixgbe_set_mac(struct net_device *netdev, void *p)
5242{
5243 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 5244 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5245 struct sockaddr *addr = p;
5246
5247 if (!is_valid_ether_addr(addr->sa_data))
5248 return -EADDRNOTAVAIL;
5249
5250 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 5251 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 5252
b4617240 5253 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 5254
5255 return 0;
5256}
5257
6b73e10d
BH		 5258static int
5259ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5260{
5261 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5262 struct ixgbe_hw *hw = &adapter->hw;
5263 u16 value;
5264 int rc;
5265
5266 if (prtad != hw->phy.mdio.prtad)
5267 return -EINVAL;
5268 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5269 if (!rc)
5270 rc = value;
5271 return rc;
5272}
5273
5274static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5275 u16 addr, u16 value)
5276{
5277 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5278 struct ixgbe_hw *hw = &adapter->hw;
5279
5280 if (prtad != hw->phy.mdio.prtad)
5281 return -EINVAL;
5282 return hw->phy.ops.write_reg(hw, addr, devad, value);
5283}
5284
5285static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5286{
5287 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5288
5289 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5290}
5291
0365e6e4
PW		 5292/**
5293 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 5294 * netdev->dev_addrs
0365e6e4
PW		 5295 * @netdev: network interface device structure
5296 *
5297 * Returns non-zero on failure
5298 **/
5299static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5300{
5301 int err = 0;
5302 struct ixgbe_adapter *adapter = netdev_priv(dev);
5303 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5304
5305 if (is_valid_ether_addr(mac->san_addr)) {
5306 rtnl_lock();
5307 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5308 rtnl_unlock();
5309 }
5310 return err;
5311}
5312
5313/**
5314 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 5315 * netdev->dev_addrs
0365e6e4
PW		 5316 * @netdev: network interface device structure
5317 *
5318 * Returns non-zero on failure
5319 **/
5320static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5321{
5322 int err = 0;
5323 struct ixgbe_adapter *adapter = netdev_priv(dev);
5324 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5325
5326 if (is_valid_ether_addr(mac->san_addr)) {
5327 rtnl_lock();
5328 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5329 rtnl_unlock();
5330 }
5331 return err;
5332}
5333
9a799d71
AK		 5334#ifdef CONFIG_NET_POLL_CONTROLLER
5335/*
5336 * Polling 'interrupt' - used by things like netconsole to send skbs
5337 * without having to re-enable interrupts. It's not called while
5338 * the interrupt routine is executing.
5339 */
5340static void ixgbe_netpoll(struct net_device *netdev)
5341{
5342 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 5343 int i;
9a799d71 5344
9a799d71 5345 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 5346 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5347 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5348 for (i = 0; i < num_q_vectors; i++) {
5349 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5350 ixgbe_msix_clean_many(0, q_vector);
5351 }
5352 } else {
5353 ixgbe_intr(adapter->pdev->irq, netdev);
5354 }
9a799d71 5355 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 5356}
5357#endif
5358
0edc3527
SH		 5359static const struct net_device_ops ixgbe_netdev_ops = {
5360 .ndo_open = ixgbe_open,
5361 .ndo_stop = ixgbe_close,
00829823 5362 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 5363 .ndo_select_queue = ixgbe_select_queue,
0edc3527 5364 .ndo_get_stats = ixgbe_get_stats,
e90d400c 5365 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 5366 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5367 .ndo_validate_addr = eth_validate_addr,
5368 .ndo_set_mac_address = ixgbe_set_mac,
5369 .ndo_change_mtu = ixgbe_change_mtu,
5370 .ndo_tx_timeout = ixgbe_tx_timeout,
5371 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5372 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5373 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 5374 .ndo_do_ioctl = ixgbe_ioctl,
0edc3527
SH		 5375#ifdef CONFIG_NET_POLL_CONTROLLER
5376 .ndo_poll_controller = ixgbe_netpoll,
5377#endif
332d4a7d
YZ		 5378#ifdef IXGBE_FCOE
5379 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5380 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 5381 .ndo_fcoe_enable = ixgbe_fcoe_enable,
5382 .ndo_fcoe_disable = ixgbe_fcoe_disable,
332d4a7d 5383#endif /* IXGBE_FCOE */
0edc3527
SH		 5384};
5385
9a799d71
AK		 5386/**
5387 * ixgbe_probe - Device Initialization Routine
5388 * @pdev: PCI device information struct
5389 * @ent: entry in ixgbe_pci_tbl
5390 *
5391 * Returns 0 on success, negative on failure
5392 *
5393 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5394 * The OS initialization, configuring of the adapter private structure,
5395 * and a hardware reset occur.
5396 **/
5397static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 5398 const struct pci_device_id *ent)
9a799d71
AK		 5399{
5400 struct net_device *netdev;
5401 struct ixgbe_adapter *adapter = NULL;
5402 struct ixgbe_hw *hw;
5403 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 5404 static int cards_found;
5405 int i, err, pci_using_dac;
eacd73f7
YZ		 5406#ifdef IXGBE_FCOE
5407 u16 device_caps;
5408#endif
c44ade9e 5409 u32 part_num, eec;
9a799d71 5410
9ce77666 5411 err = pci_enable_device_mem(pdev);
9a799d71
AK		 5412 if (err)
5413 return err;
5414
6a35528a
YH		 5415 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5416 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
9a799d71
AK		 5417 pci_using_dac = 1;
5418 } else {
284901a9 5419 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5420 if (err) {
284901a9 5421 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5422 if (err) {
b4617240
PW		 5423 dev_err(&pdev->dev, "No usable DMA "
5424 "configuration, aborting\n");
9a799d71
AK		 5425 goto err_dma;
5426 }
5427 }
5428 pci_using_dac = 0;
5429 }
5430
9ce77666 5431 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5432 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 5433 if (err) {
9ce77666 5434 dev_err(&pdev->dev,
5435 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 5436 goto err_pci_reg;
5437 }
5438
6fabd715
PWJ		 5439 err = pci_enable_pcie_error_reporting(pdev);
5440 if (err) {
5441 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
5442 "0x%x\n", err);
5443 /* non-fatal, continue */
5444 }
5445
9a799d71 5446 pci_set_master(pdev);
fb3b27bc 5447 pci_save_state(pdev);
9a799d71 5448
30eba97a 5449 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 5450 if (!netdev) {
5451 err = -ENOMEM;
5452 goto err_alloc_etherdev;
5453 }
5454
9a799d71
AK		 5455 SET_NETDEV_DEV(netdev, &pdev->dev);
5456
5457 pci_set_drvdata(pdev, netdev);
5458 adapter = netdev_priv(netdev);
5459
5460 adapter->netdev = netdev;
5461 adapter->pdev = pdev;
5462 hw = &adapter->hw;
5463 hw->back = adapter;
5464 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5465
05857980
JK		 5466 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5467 pci_resource_len(pdev, 0));
9a799d71
AK		 5468 if (!hw->hw_addr) {
5469 err = -EIO;
5470 goto err_ioremap;
5471 }
5472
5473 for (i = 1; i <= 5; i++) {
5474 if (pci_resource_len(pdev, i) == 0)
5475 continue;
5476 }
5477
0edc3527 5478 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 5479 ixgbe_set_ethtool_ops(netdev);
9a799d71 5480 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 5481 strcpy(netdev->name, pci_name(pdev));
5482
9a799d71
AK		 5483 adapter->bd_number = cards_found;
5484
9a799d71
AK		 5485 /* Setup hw api */
5486 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 5487 hw->mac.type = ii->mac;
9a799d71 5488
c44ade9e
JB		 5489 /* EEPROM */
5490 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5491 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5492 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5493 if (!(eec & (1 << 8)))
5494 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5495
5496 /* PHY */
5497 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 5498 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 5499 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5500 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5501 hw->phy.mdio.mmds = 0;
5502 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5503 hw->phy.mdio.dev = netdev;
5504 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5505 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 5506
5507 /* set up this timer and work struct before calling get_invariants
5508 * which might start the timer
5509 */
5510 init_timer(&adapter->sfp_timer);
5511 adapter->sfp_timer.function = &ixgbe_sfp_timer;
5512 adapter->sfp_timer.data = (unsigned long) adapter;
5513
5514 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 5515
e8e26350
PW		 5516 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5517 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5518
5519 /* a new SFP+ module arrival, called from GPI SDP2 context */
5520 INIT_WORK(&adapter->sfp_config_module_task,
5521 ixgbe_sfp_config_module_task);
5522
8ca783ab 5523 ii->get_invariants(hw);
9a799d71
AK		 5524
5525 /* setup the private structure */
5526 err = ixgbe_sw_init(adapter);
5527 if (err)
5528 goto err_sw_init;
5529
bf069c97
DS		 5530 /*
5531 * If there is a fan on this device and it has failed log the
5532 * failure.
5533 */
5534 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5535 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5536 if (esdp & IXGBE_ESDP_SDP1)
5537 DPRINTK(PROBE, CRIT,
5538 "Fan has stopped, replace the adapter\n");
5539 }
5540
c44ade9e
JB		 5541 /* reset_hw fills in the perm_addr as well */
5542 err = hw->mac.ops.reset_hw(hw);
8ca783ab
DS		 5543 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5544 hw->mac.type == ixgbe_mac_82598EB) {
5545 /*
5546 * Start a kernel thread to watch for a module to arrive.
5547 * Only do this for 82598, since 82599 will generate
5548 * interrupts on module arrival.
5549 */
5550 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5551 mod_timer(&adapter->sfp_timer,
5552 round_jiffies(jiffies + (2 * HZ)));
5553 err = 0;
5554 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 5555 dev_err(&adapter->pdev->dev, "failed to initialize because "
5556 "an unsupported SFP+ module type was detected.\n"
5557 "Reload the driver after installing a supported "
5558 "module.\n");
04f165ef
PW		 5559 goto err_sw_init;
5560 } else if (err) {
c44ade9e
JB		 5561 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5562 goto err_sw_init;
5563 }
5564
9a799d71 5565 netdev->features = NETIF_F_SG |
b4617240
PW		 5566 NETIF_F_IP_CSUM |
5567 NETIF_F_HW_VLAN_TX |
5568 NETIF_F_HW_VLAN_RX |
5569 NETIF_F_HW_VLAN_FILTER;
9a799d71 5570
e9990a9c 5571 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 5572 netdev->features |= NETIF_F_TSO;
9a799d71 5573 netdev->features |= NETIF_F_TSO6;
78b6f4ce 5574 netdev->features |= NETIF_F_GRO;
ad31c402 5575
45a5ead0
JB		 5576 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5577 netdev->features |= NETIF_F_SCTP_CSUM;
5578
ad31c402
JK		 5579 netdev->vlan_features |= NETIF_F_TSO;
5580 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 5581 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 5582 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 5583 netdev->vlan_features |= NETIF_F_SG;
5584
2f90b865
AD		 5585 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5586 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5587
7a6b6f51 5588#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5589 netdev->dcbnl_ops = &dcbnl_ops;
5590#endif
5591
eacd73f7 5592#ifdef IXGBE_FCOE
0d551589 5593 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 5594 if (hw->mac.ops.get_device_caps) {
5595 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 5596 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5597 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 5598 }
5599 }
5600#endif /* IXGBE_FCOE */
9a799d71
AK		 5601 if (pci_using_dac)
5602 netdev->features |= NETIF_F_HIGHDMA;
5603
0c19d6af 5604 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 5605 netdev->features |= NETIF_F_LRO;
5606
9a799d71 5607 /* make sure the EEPROM is good */
c44ade9e 5608 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 5609 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5610 err = -EIO;
5611 goto err_eeprom;
5612 }
5613
5614 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5615 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5616
c44ade9e
JB		 5617 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5618 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 5619 err = -EIO;
5620 goto err_eeprom;
5621 }
5622
5623 init_timer(&adapter->watchdog_timer);
5624 adapter->watchdog_timer.function = &ixgbe_watchdog;
5625 adapter->watchdog_timer.data = (unsigned long)adapter;
5626
5627 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 5628 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 5629
021230d4
AV		 5630 err = ixgbe_init_interrupt_scheme(adapter);
5631 if (err)
5632 goto err_sw_init;
9a799d71 5633
e8e26350
PW		 5634 switch (pdev->device) {
5635 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 5636 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5637 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
bdf0a550
PWJ		 5638 /* Enable ACPI wakeup in GRC */
5639 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5640 (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
e8e26350
PW		 5641 break;
5642 default:
5643 adapter->wol = 0;
5644 break;
5645 }
e8e26350
PW		 5646 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5647
04f165ef
PW		 5648 /* pick up the PCI bus settings for reporting later */
5649 hw->mac.ops.get_bus_info(hw);
5650
9a799d71 5651 /* print bus type/speed/width info */
7c510e4b 5652 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 5653 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5654 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5655 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5656 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5657 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 5658 "Unknown"),
7c510e4b 5659 netdev->dev_addr);
c44ade9e 5660 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 5661 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5662 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5663 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5664 (part_num >> 8), (part_num & 0xff));
5665 else
5666 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5667 hw->mac.type, hw->phy.type,
5668 (part_num >> 8), (part_num & 0xff));
9a799d71 5669
e8e26350 5670 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 5671 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 5672 "this card is not sufficient for optimal "
5673 "performance.\n");
0c254d86 5674 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 5675 "PCI-Express slot is required.\n");
0c254d86
AK		 5676 }
5677
34b0368c
PWJ		 5678 /* save off EEPROM version number */
5679 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5680
9a799d71 5681 /* reset the hardware with the new settings */
794caeb2 5682 err = hw->mac.ops.start_hw(hw);
c44ade9e 5683
794caeb2
PWJ		 5684 if (err == IXGBE_ERR_EEPROM_VERSION) {
5685 /* We are running on a pre-production device, log a warning */
5686 dev_warn(&pdev->dev, "This device is a pre-production "
5687 "adapter/LOM. Please be aware there may be issues "
5688 "associated with your hardware. If you are "
5689 "experiencing problems please contact your Intel or "
5690 "hardware representative who provided you with this "
5691 "hardware.\n");
5692 }
9a799d71
AK		 5693 strcpy(netdev->name, "eth%d");
5694 err = register_netdev(netdev);
5695 if (err)
5696 goto err_register;
5697
54386467
JB		 5698 /* carrier off reporting is important to ethtool even BEFORE open */
5699 netif_carrier_off(netdev);
5700
c4cf55e5
PWJ		 5701 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5702 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5703 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5704
5dd2d332 5705#ifdef CONFIG_IXGBE_DCA
652f093f 5706 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 5707 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 5708 ixgbe_setup_dca(adapter);
5709 }
5710#endif
0365e6e4
PW		 5711 /* add san mac addr to netdev */
5712 ixgbe_add_sanmac_netdev(netdev);
9a799d71
AK		 5713
5714 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5715 cards_found++;
5716 return 0;
5717
5718err_register:
5eba3699 5719 ixgbe_release_hw_control(adapter);
7a921c93 5720 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 5721err_sw_init:
5722err_eeprom:
c4900be0
DS		 5723 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5724 del_timer_sync(&adapter->sfp_timer);
5725 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5726 cancel_work_sync(&adapter->multispeed_fiber_task);
5727 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 5728 iounmap(hw->hw_addr);
5729err_ioremap:
5730 free_netdev(netdev);
5731err_alloc_etherdev:
9ce77666 5732 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5733 IORESOURCE_MEM));
9a799d71
AK		 5734err_pci_reg:
5735err_dma:
5736 pci_disable_device(pdev);
5737 return err;
5738}
5739
5740/**
5741 * ixgbe_remove - Device Removal Routine
5742 * @pdev: PCI device information struct
5743 *
5744 * ixgbe_remove is called by the PCI subsystem to alert the driver
5745 * that it should release a PCI device. The could be caused by a
5746 * Hot-Plug event, or because the driver is going to be removed from
5747 * memory.
5748 **/
5749static void __devexit ixgbe_remove(struct pci_dev *pdev)
5750{
5751 struct net_device *netdev = pci_get_drvdata(pdev);
5752 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715 5753 int err;
9a799d71
AK		 5754
5755 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 5756 /* clear the module not found bit to make sure the worker won't
5757 * reschedule
5758 */
5759 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 5760 del_timer_sync(&adapter->watchdog_timer);
5761
c4900be0
DS		 5762 del_timer_sync(&adapter->sfp_timer);
5763 cancel_work_sync(&adapter->watchdog_task);
5764 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5765 cancel_work_sync(&adapter->multispeed_fiber_task);
5766 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 5767 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5768 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5769 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 5770 flush_scheduled_work();
5771
5dd2d332 5772#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5773 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5774 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5775 dca_remove_requester(&pdev->dev);
5776 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5777 }
5778
5779#endif
332d4a7d
YZ		 5780#ifdef IXGBE_FCOE
5781 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5782 ixgbe_cleanup_fcoe(adapter);
5783
5784#endif /* IXGBE_FCOE */
0365e6e4
PW		 5785
5786 /* remove the added san mac */
5787 ixgbe_del_sanmac_netdev(netdev);
5788
c4900be0
DS		 5789 if (netdev->reg_state == NETREG_REGISTERED)
5790 unregister_netdev(netdev);
9a799d71 5791
7a921c93 5792 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 5793
021230d4 5794 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5795
5796 iounmap(adapter->hw.hw_addr);
9ce77666 5797 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5798 IORESOURCE_MEM));
9a799d71 5799
021230d4 5800 DPRINTK(PROBE, INFO, "complete\n");
021230d4 5801
9a799d71
AK		 5802 free_netdev(netdev);
5803
6fabd715
PWJ		 5804 err = pci_disable_pcie_error_reporting(pdev);
5805 if (err)
5806 dev_err(&pdev->dev,
5807 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5808
9a799d71
AK		 5809 pci_disable_device(pdev);
5810}
5811
5812/**
5813 * ixgbe_io_error_detected - called when PCI error is detected
5814 * @pdev: Pointer to PCI device
5815 * @state: The current pci connection state
5816 *
5817 * This function is called after a PCI bus error affecting
5818 * this device has been detected.
5819 */
5820static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 5821 pci_channel_state_t state)
9a799d71
AK		 5822{
5823 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5824 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5825
5826 netif_device_detach(netdev);
5827
3044b8d1
BL		 5828 if (state == pci_channel_io_perm_failure)
5829 return PCI_ERS_RESULT_DISCONNECT;
5830
9a799d71
AK		 5831 if (netif_running(netdev))
5832 ixgbe_down(adapter);
5833 pci_disable_device(pdev);
5834
b4617240 5835 /* Request a slot reset. */
9a799d71
AK		 5836 return PCI_ERS_RESULT_NEED_RESET;
5837}
5838
5839/**
5840 * ixgbe_io_slot_reset - called after the pci bus has been reset.
5841 * @pdev: Pointer to PCI device
5842 *
5843 * Restart the card from scratch, as if from a cold-boot.
5844 */
5845static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5846{
5847 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5848 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 5849 pci_ers_result_t result;
5850 int err;
9a799d71 5851
9ce77666 5852 if (pci_enable_device_mem(pdev)) {
9a799d71 5853 DPRINTK(PROBE, ERR,
b4617240 5854 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 5855 result = PCI_ERS_RESULT_DISCONNECT;
5856 } else {
5857 pci_set_master(pdev);
5858 pci_restore_state(pdev);
9a799d71 5859
dd4d8ca6 5860 pci_wake_from_d3(pdev, false);
9a799d71 5861
6fabd715 5862 ixgbe_reset(adapter);
88512539 5863 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 5864 result = PCI_ERS_RESULT_RECOVERED;
5865 }
5866
5867 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5868 if (err) {
5869 dev_err(&pdev->dev,
5870 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5871 /* non-fatal, continue */
5872 }
9a799d71 5873
6fabd715 5874 return result;
9a799d71
AK		 5875}
5876
5877/**
5878 * ixgbe_io_resume - called when traffic can start flowing again.
5879 * @pdev: Pointer to PCI device
5880 *
5881 * This callback is called when the error recovery driver tells us that
5882 * its OK to resume normal operation.
5883 */
5884static void ixgbe_io_resume(struct pci_dev *pdev)
5885{
5886 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5887 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5888
5889 if (netif_running(netdev)) {
5890 if (ixgbe_up(adapter)) {
5891 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5892 return;
5893 }
5894 }
5895
5896 netif_device_attach(netdev);
9a799d71
AK		 5897}
5898
5899static struct pci_error_handlers ixgbe_err_handler = {
5900 .error_detected = ixgbe_io_error_detected,
5901 .slot_reset = ixgbe_io_slot_reset,
5902 .resume = ixgbe_io_resume,
5903};
5904
5905static struct pci_driver ixgbe_driver = {
5906 .name = ixgbe_driver_name,
5907 .id_table = ixgbe_pci_tbl,
5908 .probe = ixgbe_probe,
5909 .remove = __devexit_p(ixgbe_remove),
5910#ifdef CONFIG_PM
5911 .suspend = ixgbe_suspend,
5912 .resume = ixgbe_resume,
5913#endif
5914 .shutdown = ixgbe_shutdown,
5915 .err_handler = &ixgbe_err_handler
5916};
5917
5918/**
5919 * ixgbe_init_module - Driver Registration Routine
5920 *
5921 * ixgbe_init_module is the first routine called when the driver is
5922 * loaded. All it does is register with the PCI subsystem.
5923 **/
5924static int __init ixgbe_init_module(void)
5925{
5926 int ret;
5927 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5928 ixgbe_driver_string, ixgbe_driver_version);
5929
5930 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5931
5dd2d332 5932#ifdef CONFIG_IXGBE_DCA
bd0362dd 5933 dca_register_notify(&dca_notifier);
bd0362dd 5934#endif
5dd2d332 5935
9a799d71
AK		 5936 ret = pci_register_driver(&ixgbe_driver);
5937 return ret;
5938}
b4617240 5939
9a799d71
AK		 5940module_init(ixgbe_init_module);
5941
5942/**
5943 * ixgbe_exit_module - Driver Exit Cleanup Routine
5944 *
5945 * ixgbe_exit_module is called just before the driver is removed
5946 * from memory.
5947 **/
5948static void __exit ixgbe_exit_module(void)
5949{
5dd2d332 5950#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5951 dca_unregister_notify(&dca_notifier);
5952#endif
9a799d71
AK		 5953 pci_unregister_driver(&ixgbe_driver);
5954}
bd0362dd 5955
5dd2d332 5956#ifdef CONFIG_IXGBE_DCA
bd0362dd 5957static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 5958 void *p)
bd0362dd
JC		 5959{
5960 int ret_val;
5961
5962 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 5963 __ixgbe_notify_dca);
bd0362dd
JC		 5964
5965 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5966}
b453368d 5967
5dd2d332 5968#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 5969#ifdef DEBUG
5970/**
5971 * ixgbe_get_hw_dev_name - return device name string
5972 * used by hardware layer to print debugging information
5973 **/
5974char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5975{
5976 struct ixgbe_adapter *adapter = hw->back;
5977 return adapter->netdev->name;
5978}
bd0362dd 5979
b453368d 5980#endif
9a799d71
AK		 5981module_exit(ixgbe_exit_module);
5982
5983/* ixgbe_main.c */
kernel source for telekom puls (alcatel/mediatek)