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memory barrier: adding smp_mb__after_lock
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/ipv6.h>
38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
40#include <linux/ethtool.h>
41#include <linux/if_vlan.h>
eacd73f7 42#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 43
44#include "ixgbe.h"
45#include "ixgbe_common.h"
46
47char ixgbe_driver_name[] = "ixgbe";
9c8eb720 48static const char ixgbe_driver_string[] =
b4617240 49 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 50
a1c1db39 51#define DRV_VERSION "2.0.34-k2"
9c8eb720 52const char ixgbe_driver_version[] = DRV_VERSION;
3efac5a0 53static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
9a799d71
AK		 54
55static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 56 [board_82598] = &ixgbe_82598_info,
e8e26350 57 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 58};
59
60/* ixgbe_pci_tbl - PCI Device ID Table
61 *
62 * Wildcard entries (PCI_ANY_ID) should come last
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
68static struct pci_device_id ixgbe_pci_tbl[] = {
1e336d0f
DS		 69 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
70 board_82598 },
9a799d71 71 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 72 board_82598 },
9a799d71 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 74 board_82598 },
0befdb3e
JB		 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
76 board_82598 },
9a799d71 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 78 board_82598 },
8d792cd9
JB		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
80 board_82598 },
c4900be0
DS		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
82 board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
84 board_82598 },
b95f5fcb
JB		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
86 board_82598 },
c4900be0
DS		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
88 board_82598 },
2f21bdd3
DS		 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
90 board_82598 },
e8e26350
PW		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
92 board_82599 },
1fcf03e6
PWJ		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
94 board_82599 },
e8e26350
PW		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
96 board_82599 },
9a799d71
AK		 97
98 /* required last entry */
99 {0, }
100};
101MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
102
5dd2d332 103#ifdef CONFIG_IXGBE_DCA
bd0362dd 104static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 105 void *p);
bd0362dd
JC		 106static struct notifier_block dca_notifier = {
107 .notifier_call = ixgbe_notify_dca,
108 .next = NULL,
109 .priority = 0
110};
111#endif
112
9a799d71
AK		 113MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
114MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
115MODULE_LICENSE("GPL");
116MODULE_VERSION(DRV_VERSION);
117
118#define DEFAULT_DEBUG_LEVEL_SHIFT 3
119
5eba3699
AV		 120static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
121{
122 u32 ctrl_ext;
123
124 /* Let firmware take over control of h/w */
125 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
126 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 127 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 128}
129
130static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
131{
132 u32 ctrl_ext;
133
134 /* Let firmware know the driver has taken over */
135 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
136 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 137 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 138}
9a799d71 139
e8e26350
PW		 140/*
141 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
142 * @adapter: pointer to adapter struct
143 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
144 * @queue: queue to map the corresponding interrupt to
145 * @msix_vector: the vector to map to the corresponding queue
146 *
147 */
148static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
149 u8 queue, u8 msix_vector)
9a799d71
AK		 150{
151 u32 ivar, index;
e8e26350
PW		 152 struct ixgbe_hw *hw = &adapter->hw;
153 switch (hw->mac.type) {
154 case ixgbe_mac_82598EB:
155 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
156 if (direction == -1)
157 direction = 0;
158 index = (((direction * 64) + queue) >> 2) & 0x1F;
159 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
160 ivar &= ~(0xFF << (8 * (queue & 0x3)));
161 ivar |= (msix_vector << (8 * (queue & 0x3)));
162 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
163 break;
164 case ixgbe_mac_82599EB:
165 if (direction == -1) {
166 /* other causes */
167 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
168 index = ((queue & 1) * 8);
169 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
170 ivar &= ~(0xFF << index);
171 ivar |= (msix_vector << index);
172 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
173 break;
174 } else {
175 /* tx or rx causes */
176 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
177 index = ((16 * (queue & 1)) + (8 * direction));
178 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
179 ivar &= ~(0xFF << index);
180 ivar |= (msix_vector << index);
181 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
182 break;
183 }
184 default:
185 break;
186 }
9a799d71
AK		 187}
188
fe49f04a
AD		 189static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
190 u64 qmask)
191{
192 u32 mask;
193
194 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
195 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
196 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
197 } else {
198 mask = (qmask & 0xFFFFFFFF);
199 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
200 mask = (qmask >> 32);
201 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
202 }
203}
204
9a799d71 205static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 206 struct ixgbe_tx_buffer
207 *tx_buffer_info)
9a799d71 208{
44df32c5 209 tx_buffer_info->dma = 0;
9a799d71 210 if (tx_buffer_info->skb) {
44df32c5
AD		 211 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
212 DMA_TO_DEVICE);
9a799d71
AK		 213 dev_kfree_skb_any(tx_buffer_info->skb);
214 tx_buffer_info->skb = NULL;
215 }
44df32c5 216 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 217 /* tx_buffer_info must be completely set up in the transmit path */
218}
219
220static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 221 struct ixgbe_ring *tx_ring,
222 unsigned int eop)
9a799d71 223{
e01c31a5 224 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 225
9a799d71 226 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 227 * check with the clearing of time_stamp and movement of eop */
9a799d71 228 adapter->detect_tx_hung = false;
44df32c5 229 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 230 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
231 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
232 /* detected Tx unit hang */
e01c31a5
JB		 233 union ixgbe_adv_tx_desc *tx_desc;
234 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 235 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 236 " Tx Queue <%d>\n"
237 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 238 " next_to_use <%x>\n"
239 " next_to_clean <%x>\n"
240 "tx_buffer_info[next_to_clean]\n"
241 " time_stamp <%lx>\n"
e01c31a5
JB		 242 " jiffies <%lx>\n",
243 tx_ring->queue_index,
44df32c5
AD		 244 IXGBE_READ_REG(hw, tx_ring->head),
245 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 246 tx_ring->next_to_use, eop,
247 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 248 return true;
249 }
250
251 return false;
252}
253
b4617240
PW		 254#define IXGBE_MAX_TXD_PWR 14
255#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 256
257/* Tx Descriptors needed, worst case */
258#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
259 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
260#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 261 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 262
e01c31a5
JB		 263static void ixgbe_tx_timeout(struct net_device *netdev);
264
9a799d71
AK		 265/**
266 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 267 * @q_vector: structure containing interrupt and ring information
e01c31a5 268 * @tx_ring: tx ring to clean
9a799d71 269 **/
fe49f04a 270static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e01c31a5 271 struct ixgbe_ring *tx_ring)
9a799d71 272{
fe49f04a 273 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 274 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 275 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
276 struct ixgbe_tx_buffer *tx_buffer_info;
277 unsigned int i, eop, count = 0;
e01c31a5 278 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 279
280 i = tx_ring->next_to_clean;
12207e49
PWJ		 281 eop = tx_ring->tx_buffer_info[i].next_to_watch;
282 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
283
284 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 285 (count < tx_ring->work_limit)) {
12207e49
PWJ		 286 bool cleaned = false;
287 for ( ; !cleaned; count++) {
288 struct sk_buff *skb;
9a799d71
AK		 289 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
290 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 291 cleaned = (i == eop);
e01c31a5 292 skb = tx_buffer_info->skb;
9a799d71 293
12207e49 294 if (cleaned && skb) {
e092be60 295 unsigned int segs, bytecount;
3d8fd385 296 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 297
298 /* gso_segs is currently only valid for tcp */
e092be60 299 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 300#ifdef IXGBE_FCOE
301 /* adjust for FCoE Sequence Offload */
302 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
303 && (skb->protocol == htons(ETH_P_FCOE)) &&
304 skb_is_gso(skb)) {
305 hlen = skb_transport_offset(skb) +
306 sizeof(struct fc_frame_header) +
307 sizeof(struct fcoe_crc_eof);
308 segs = DIV_ROUND_UP(skb->len - hlen,
309 skb_shinfo(skb)->gso_size);
310 }
311#endif /* IXGBE_FCOE */
e092be60 312 /* multiply data chunks by size of headers */
3d8fd385 313 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 314 total_packets += segs;
315 total_bytes += bytecount;
e092be60 316 }
e01c31a5 317
9a799d71 318 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 319 tx_buffer_info);
9a799d71 320
12207e49
PWJ		 321 tx_desc->wb.status = 0;
322
9a799d71
AK		 323 i++;
324 if (i == tx_ring->count)
325 i = 0;
e01c31a5 326 }
12207e49
PWJ		 327
328 eop = tx_ring->tx_buffer_info[i].next_to_watch;
329 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
330 }
331
9a799d71
AK		 332 tx_ring->next_to_clean = i;
333
e092be60 334#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 335 if (unlikely(count && netif_carrier_ok(netdev) &&
336 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 337 /* Make sure that anybody stopping the queue after this
338 * sees the new next_to_clean.
339 */
340 smp_mb();
30eba97a
AV		 341 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
342 !test_bit(__IXGBE_DOWN, &adapter->state)) {
343 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 344 ++adapter->restart_queue;
30eba97a 345 }
e092be60 346 }
9a799d71 347
e01c31a5
JB		 348 if (adapter->detect_tx_hung) {
349 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
350 /* schedule immediate reset if we believe we hung */
351 DPRINTK(PROBE, INFO,
352 "tx hang %d detected, resetting adapter\n",
353 adapter->tx_timeout_count + 1);
354 ixgbe_tx_timeout(adapter->netdev);
355 }
356 }
9a799d71 357
e01c31a5 358 /* re-arm the interrupt */
fe49f04a
AD		 359 if (count >= tx_ring->work_limit)
360 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 361
e01c31a5
JB		 362 tx_ring->total_bytes += total_bytes;
363 tx_ring->total_packets += total_packets;
e01c31a5 364 tx_ring->stats.packets += total_packets;
12207e49 365 tx_ring->stats.bytes += total_bytes;
e01c31a5
JB		 366 adapter->net_stats.tx_bytes += total_bytes;
367 adapter->net_stats.tx_packets += total_packets;
9a1a69ad 368 return (count < tx_ring->work_limit);
9a799d71
AK		 369}
370
5dd2d332 371#ifdef CONFIG_IXGBE_DCA
bd0362dd 372static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 373 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 374{
375 u32 rxctrl;
376 int cpu = get_cpu();
3a581073 377 int q = rx_ring - adapter->rx_ring;
bd0362dd 378
3a581073 379 if (rx_ring->cpu != cpu) {
bd0362dd 380 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 381 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
382 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
383 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
384 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
385 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
386 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
387 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
388 }
bd0362dd
JC		 389 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
390 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 391 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
392 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 393 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 394 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 395 rx_ring->cpu = cpu;
bd0362dd
JC		 396 }
397 put_cpu();
398}
399
400static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 401 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 402{
403 u32 txctrl;
404 int cpu = get_cpu();
3a581073 405 int q = tx_ring - adapter->tx_ring;
bd0362dd 406
3a581073 407 if (tx_ring->cpu != cpu) {
bd0362dd 408 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 409 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
410 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
411 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
412 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
413 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
414 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
415 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
416 }
bd0362dd
JC		 417 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
418 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 419 tx_ring->cpu = cpu;
bd0362dd
JC		 420 }
421 put_cpu();
422}
423
424static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
425{
426 int i;
427
428 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
429 return;
430
e35ec126
AD		 431 /* always use CB2 mode, difference is masked in the CB driver */
432 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
433
bd0362dd
JC		 434 for (i = 0; i < adapter->num_tx_queues; i++) {
435 adapter->tx_ring[i].cpu = -1;
436 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
437 }
438 for (i = 0; i < adapter->num_rx_queues; i++) {
439 adapter->rx_ring[i].cpu = -1;
440 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
441 }
442}
443
444static int __ixgbe_notify_dca(struct device *dev, void *data)
445{
446 struct net_device *netdev = dev_get_drvdata(dev);
447 struct ixgbe_adapter *adapter = netdev_priv(netdev);
448 unsigned long event = *(unsigned long *)data;
449
450 switch (event) {
451 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 452 /* if we're already enabled, don't do it again */
453 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
454 break;
652f093f 455 if (dca_add_requester(dev) == 0) {
96b0e0f6 456 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 457 ixgbe_setup_dca(adapter);
458 break;
459 }
460 /* Fall Through since DCA is disabled. */
461 case DCA_PROVIDER_REMOVE:
462 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
463 dca_remove_requester(dev);
464 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
465 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
466 }
467 break;
468 }
469
652f093f 470 return 0;
bd0362dd
JC		 471}
472
5dd2d332 473#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 474/**
475 * ixgbe_receive_skb - Send a completed packet up the stack
476 * @adapter: board private structure
477 * @skb: packet to send up
177db6ff
MC		 478 * @status: hardware indication of status of receive
479 * @rx_ring: rx descriptor ring (for a specific queue) to setup
480 * @rx_desc: rx descriptor
9a799d71 481 **/
78b6f4ce 482static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 483 struct sk_buff *skb, u8 status,
fdaff1ce 484 struct ixgbe_ring *ring,
177db6ff 485 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 486{
78b6f4ce
HX		 487 struct ixgbe_adapter *adapter = q_vector->adapter;
488 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 489 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
490 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 491
fdaff1ce 492 skb_record_rx_queue(skb, ring->queue_index);
182ff8df 493 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
2f90b865 494 if (adapter->vlgrp && is_vlan && (tag != 0))
78b6f4ce 495 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 496 else
78b6f4ce 497 napi_gro_receive(napi, skb);
177db6ff 498 } else {
182ff8df
AD		 499 if (adapter->vlgrp && is_vlan && (tag != 0))
500 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
501 else
502 netif_rx(skb);
9a799d71
AK		 503 }
504}
505
e59bd25d
AV		 506/**
507 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
508 * @adapter: address of board private structure
509 * @status_err: hardware indication of status of receive
510 * @skb: skb currently being received and modified
511 **/
9a799d71 512static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
712744be 513 u32 status_err, struct sk_buff *skb)
9a799d71
AK		 514{
515 skb->ip_summed = CHECKSUM_NONE;
516
712744be
JB		 517 /* Rx csum disabled */
518 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 519 return;
e59bd25d
AV		 520
521 /* if IP and error */
522 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
523 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 524 adapter->hw_csum_rx_error++;
525 return;
526 }
e59bd25d
AV		 527
528 if (!(status_err & IXGBE_RXD_STAT_L4CS))
529 return;
530
531 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
532 adapter->hw_csum_rx_error++;
533 return;
534 }
535
9a799d71 536 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 537 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 538 adapter->hw_csum_rx_good++;
539}
540
e8e26350
PW		 541static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
542 struct ixgbe_ring *rx_ring, u32 val)
543{
544 /*
545 * Force memory writes to complete before letting h/w
546 * know there are new descriptors to fetch. (Only
547 * applicable for weak-ordered memory model archs,
548 * such as IA-64).
549 */
550 wmb();
551 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
552}
553
9a799d71
AK		 554/**
555 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
556 * @adapter: address of board private structure
557 **/
558static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 559 struct ixgbe_ring *rx_ring,
560 int cleaned_count)
9a799d71 561{
9a799d71
AK		 562 struct pci_dev *pdev = adapter->pdev;
563 union ixgbe_adv_rx_desc *rx_desc;
3a581073 564 struct ixgbe_rx_buffer *bi;
9a799d71 565 unsigned int i;
9a799d71
AK		 566
567 i = rx_ring->next_to_use;
3a581073 568 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 569
570 while (cleaned_count--) {
571 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
572
762f4c57 573 if (!bi->page_dma &&
3a581073 574 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
3a581073 575 if (!bi->page) {
762f4c57
JB		 576 bi->page = alloc_page(GFP_ATOMIC);
577 if (!bi->page) {
578 adapter->alloc_rx_page_failed++;
579 goto no_buffers;
580 }
581 bi->page_offset = 0;
582 } else {
583 /* use a half page if we're re-using */
584 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 585 }
762f4c57
JB		 586
587 bi->page_dma = pci_map_page(pdev, bi->page,
588 bi->page_offset,
589 (PAGE_SIZE / 2),
590 PCI_DMA_FROMDEVICE);
9a799d71
AK		 591 }
592
3a581073 593 if (!bi->skb) {
5ecc3614 594 struct sk_buff *skb;
4f57ca6e
JB		 595 skb = netdev_alloc_skb(adapter->netdev,
596 (rx_ring->rx_buf_len +
597 NET_IP_ALIGN));
9a799d71
AK		 598
599 if (!skb) {
600 adapter->alloc_rx_buff_failed++;
601 goto no_buffers;
602 }
603
604 /*
605 * Make buffer alignment 2 beyond a 16 byte boundary
606 * this will result in a 16 byte aligned IP header after
607 * the 14 byte MAC header is removed
608 */
609 skb_reserve(skb, NET_IP_ALIGN);
610
3a581073 611 bi->skb = skb;
4f57ca6e
JB		 612 bi->dma = pci_map_single(pdev, skb->data,
613 rx_ring->rx_buf_len,
3a581073 614 PCI_DMA_FROMDEVICE);
9a799d71
AK		 615 }
616 /* Refresh the desc even if buffer_addrs didn't change because
617 * each write-back erases this info. */
618 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3a581073
JB		 619 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
620 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 621 } else {
3a581073 622 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 623 }
624
625 i++;
626 if (i == rx_ring->count)
627 i = 0;
3a581073 628 bi = &rx_ring->rx_buffer_info[i];
9a799d71 629 }
7c6e0a43 630
9a799d71
AK		 631no_buffers:
632 if (rx_ring->next_to_use != i) {
633 rx_ring->next_to_use = i;
634 if (i-- == 0)
635 i = (rx_ring->count - 1);
636
e8e26350 637 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 638 }
639}
640
7c6e0a43
JB		 641static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
642{
643 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
644}
645
646static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
647{
648 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
649}
650
f8212f97
AD		 651static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
652{
653 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
654 IXGBE_RXDADV_RSCCNT_MASK) >>
655 IXGBE_RXDADV_RSCCNT_SHIFT;
656}
657
658/**
659 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
660 * @skb: pointer to the last skb in the rsc queue
661 *
662 * This function changes a queue full of hw rsc buffers into a completed
663 * packet. It uses the ->prev pointers to find the first packet and then
664 * turns it into the frag list owner.
665 **/
666static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
667{
668 unsigned int frag_list_size = 0;
669
670 while (skb->prev) {
671 struct sk_buff *prev = skb->prev;
672 frag_list_size += skb->len;
673 skb->prev = NULL;
674 skb = prev;
675 }
676
677 skb_shinfo(skb)->frag_list = skb->next;
678 skb->next = NULL;
679 skb->len += frag_list_size;
680 skb->data_len += frag_list_size;
681 skb->truesize += frag_list_size;
682 return skb;
683}
684
78b6f4ce 685static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 686 struct ixgbe_ring *rx_ring,
687 int *work_done, int work_to_do)
9a799d71 688{
78b6f4ce 689 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 690 struct pci_dev *pdev = adapter->pdev;
691 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
692 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
693 struct sk_buff *skb;
f8212f97 694 unsigned int i, rsc_count = 0;
7c6e0a43 695 u32 len, staterr;
177db6ff
MC		 696 u16 hdr_info;
697 bool cleaned = false;
9a799d71 698 int cleaned_count = 0;
d2f4fbe2 699 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 700#ifdef IXGBE_FCOE
701 int ddp_bytes = 0;
702#endif /* IXGBE_FCOE */
9a799d71
AK		 703
704 i = rx_ring->next_to_clean;
9a799d71
AK		 705 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
706 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
707 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 708
709 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 710 u32 upper_len = 0;
9a799d71
AK		 711 if (*work_done >= work_to_do)
712 break;
713 (*work_done)++;
714
715 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43
JB		 716 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
717 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 718 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 719 if (hdr_info & IXGBE_RXDADV_SPH)
720 adapter->rx_hdr_split++;
721 if (len > IXGBE_RX_HDR_SIZE)
722 len = IXGBE_RX_HDR_SIZE;
723 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 724 } else {
9a799d71 725 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 726 }
9a799d71
AK		 727
728 cleaned = true;
729 skb = rx_buffer_info->skb;
730 prefetch(skb->data - NET_IP_ALIGN);
731 rx_buffer_info->skb = NULL;
732
21fa4e66 733 if (rx_buffer_info->dma) {
9a799d71 734 pci_unmap_single(pdev, rx_buffer_info->dma,
5ecc3614 735 rx_ring->rx_buf_len,
b4617240 736 PCI_DMA_FROMDEVICE);
4f57ca6e 737 rx_buffer_info->dma = 0;
9a799d71
AK		 738 skb_put(skb, len);
739 }
740
741 if (upper_len) {
742 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 743 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 744 rx_buffer_info->page_dma = 0;
745 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 746 rx_buffer_info->page,
747 rx_buffer_info->page_offset,
748 upper_len);
749
750 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
751 (page_count(rx_buffer_info->page) != 1))
752 rx_buffer_info->page = NULL;
753 else
754 get_page(rx_buffer_info->page);
9a799d71
AK		 755
756 skb->len += upper_len;
757 skb->data_len += upper_len;
758 skb->truesize += upper_len;
759 }
760
761 i++;
762 if (i == rx_ring->count)
763 i = 0;
9a799d71
AK		 764
765 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
766 prefetch(next_rxd);
9a799d71 767 cleaned_count++;
f8212f97 768
df647b5c 769 if (adapter->flags & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 770 rsc_count = ixgbe_get_rsc_count(rx_desc);
771
772 if (rsc_count) {
773 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
774 IXGBE_RXDADV_NEXTP_SHIFT;
775 next_buffer = &rx_ring->rx_buffer_info[nextp];
776 rx_ring->rsc_count += (rsc_count - 1);
777 } else {
778 next_buffer = &rx_ring->rx_buffer_info[i];
779 }
780
9a799d71 781 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97
AD		 782 if (skb->prev)
783 skb = ixgbe_transform_rsc_queue(skb);
9a799d71
AK		 784 rx_ring->stats.packets++;
785 rx_ring->stats.bytes += skb->len;
786 } else {
f8212f97
AD		 787 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
788 rx_buffer_info->skb = next_buffer->skb;
789 rx_buffer_info->dma = next_buffer->dma;
790 next_buffer->skb = skb;
791 next_buffer->dma = 0;
792 } else {
793 skb->next = next_buffer->skb;
794 skb->next->prev = skb;
795 }
9a799d71
AK		 796 adapter->non_eop_descs++;
797 goto next_desc;
798 }
799
800 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
801 dev_kfree_skb_irq(skb);
802 goto next_desc;
803 }
804
805 ixgbe_rx_checksum(adapter, staterr, skb);
d2f4fbe2
AV		 806
807 /* probably a little skewed due to removing CRC */
808 total_rx_bytes += skb->len;
809 total_rx_packets++;
810
74ce8dd2 811 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 812#ifdef IXGBE_FCOE
813 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 814 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
815 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
816 if (!ddp_bytes)
332d4a7d 817 goto next_desc;
3d8fd385 818 }
332d4a7d 819#endif /* IXGBE_FCOE */
fdaff1ce 820 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 821
822next_desc:
823 rx_desc->wb.upper.status_error = 0;
824
825 /* return some buffers to hardware, one at a time is too slow */
826 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
827 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
828 cleaned_count = 0;
829 }
830
831 /* use prefetched values */
832 rx_desc = next_rxd;
f8212f97 833 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 834
835 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 836 }
837
9a799d71
AK		 838 rx_ring->next_to_clean = i;
839 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
840
841 if (cleaned_count)
842 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
843
3d8fd385
YZ		 844#ifdef IXGBE_FCOE
845 /* include DDPed FCoE data */
846 if (ddp_bytes > 0) {
847 unsigned int mss;
848
849 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
850 sizeof(struct fc_frame_header) -
851 sizeof(struct fcoe_crc_eof);
852 if (mss > 512)
853 mss &= ~511;
854 total_rx_bytes += ddp_bytes;
855 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
856 }
857#endif /* IXGBE_FCOE */
858
f494e8fa
AV		 859 rx_ring->total_packets += total_rx_packets;
860 rx_ring->total_bytes += total_rx_bytes;
861 adapter->net_stats.rx_bytes += total_rx_bytes;
862 adapter->net_stats.rx_packets += total_rx_packets;
863
9a799d71
AK		 864 return cleaned;
865}
866
021230d4 867static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 868/**
869 * ixgbe_configure_msix - Configure MSI-X hardware
870 * @adapter: board private structure
871 *
872 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
873 * interrupts.
874 **/
875static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
876{
021230d4
AV		 877 struct ixgbe_q_vector *q_vector;
878 int i, j, q_vectors, v_idx, r_idx;
879 u32 mask;
9a799d71 880
021230d4 881 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 882
4df10466
JB		 883 /*
884 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 885 * corresponding register.
886 */
887 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 888 q_vector = adapter->q_vector[v_idx];
021230d4
AV		 889 /* XXX for_each_bit(...) */
890 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 891 adapter->num_rx_queues);
021230d4
AV		 892
893 for (i = 0; i < q_vector->rxr_count; i++) {
894 j = adapter->rx_ring[r_idx].reg_idx;
e8e26350 895 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 896 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 897 adapter->num_rx_queues,
898 r_idx + 1);
021230d4
AV		 899 }
900 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 901 adapter->num_tx_queues);
021230d4
AV		 902
903 for (i = 0; i < q_vector->txr_count; i++) {
904 j = adapter->tx_ring[r_idx].reg_idx;
e8e26350 905 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 906 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 907 adapter->num_tx_queues,
908 r_idx + 1);
021230d4
AV		 909 }
910
30efa5a3 911 /* if this is a tx only vector halve the interrupt rate */
021230d4 912 if (q_vector->txr_count && !q_vector->rxr_count)
30efa5a3 913 q_vector->eitr = (adapter->eitr_param >> 1);
509ee935 914 else if (q_vector->rxr_count)
30efa5a3
JB		 915 /* rx only */
916 q_vector->eitr = adapter->eitr_param;
021230d4 917
fe49f04a 918 ixgbe_write_eitr(q_vector);
9a799d71
AK		 919 }
920
e8e26350
PW		 921 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
922 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
923 v_idx);
924 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
925 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 926 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
927
41fb9248 928 /* set up to autoclear timer, and the vectors */
021230d4 929 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 930 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 931 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 932}
933
f494e8fa
AV		 934enum latency_range {
935 lowest_latency = 0,
936 low_latency = 1,
937 bulk_latency = 2,
938 latency_invalid = 255
939};
940
941/**
942 * ixgbe_update_itr - update the dynamic ITR value based on statistics
943 * @adapter: pointer to adapter
944 * @eitr: eitr setting (ints per sec) to give last timeslice
945 * @itr_setting: current throttle rate in ints/second
946 * @packets: the number of packets during this measurement interval
947 * @bytes: the number of bytes during this measurement interval
948 *
949 * Stores a new ITR value based on packets and byte
950 * counts during the last interrupt. The advantage of per interrupt
951 * computation is faster updates and more accurate ITR for the current
952 * traffic pattern. Constants in this function were computed
953 * based on theoretical maximum wire speed and thresholds were set based
954 * on testing data as well as attempting to minimize response time
955 * while increasing bulk throughput.
956 * this functionality is controlled by the InterruptThrottleRate module
957 * parameter (see ixgbe_param.c)
958 **/
959static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 960 u32 eitr, u8 itr_setting,
961 int packets, int bytes)
f494e8fa
AV		 962{
963 unsigned int retval = itr_setting;
964 u32 timepassed_us;
965 u64 bytes_perint;
966
967 if (packets == 0)
968 goto update_itr_done;
969
970
971 /* simple throttlerate management
972 * 0-20MB/s lowest (100000 ints/s)
973 * 20-100MB/s low (20000 ints/s)
974 * 100-1249MB/s bulk (8000 ints/s)
975 */
976 /* what was last interrupt timeslice? */
977 timepassed_us = 1000000/eitr;
978 bytes_perint = bytes / timepassed_us; /* bytes/usec */
979
980 switch (itr_setting) {
981 case lowest_latency:
982 if (bytes_perint > adapter->eitr_low)
983 retval = low_latency;
984 break;
985 case low_latency:
986 if (bytes_perint > adapter->eitr_high)
987 retval = bulk_latency;
988 else if (bytes_perint <= adapter->eitr_low)
989 retval = lowest_latency;
990 break;
991 case bulk_latency:
992 if (bytes_perint <= adapter->eitr_high)
993 retval = low_latency;
994 break;
995 }
996
997update_itr_done:
998 return retval;
999}
1000
509ee935
JB		 1001/**
1002 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1003 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1004 *
1005 * This function is made to be called by ethtool and by the driver
1006 * when it needs to update EITR registers at runtime. Hardware
1007 * specific quirks/differences are taken care of here.
1008 */
fe49f04a 1009void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1010{
fe49f04a 1011 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1012 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1013 int v_idx = q_vector->v_idx;
1014 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1015
509ee935
JB		 1016 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1017 /* must write high and low 16 bits to reset counter */
1018 itr_reg |= (itr_reg << 16);
1019 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1020 /*
1021 * set the WDIS bit to not clear the timer bits and cause an
1022 * immediate assertion of the interrupt
1023 */
1024 itr_reg |= IXGBE_EITR_CNT_WDIS;
1025 }
1026 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1027}
1028
f494e8fa
AV		 1029static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1030{
1031 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1032 u32 new_itr;
1033 u8 current_itr, ret_itr;
fe49f04a 1034 int i, r_idx;
f494e8fa
AV		 1035 struct ixgbe_ring *rx_ring, *tx_ring;
1036
1037 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1038 for (i = 0; i < q_vector->txr_count; i++) {
1039 tx_ring = &(adapter->tx_ring[r_idx]);
1040 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1041 q_vector->tx_itr,
1042 tx_ring->total_packets,
1043 tx_ring->total_bytes);
f494e8fa
AV		 1044 /* if the result for this queue would decrease interrupt
1045 * rate for this vector then use that result */
30efa5a3 1046 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1047 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1048 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1049 r_idx + 1);
f494e8fa
AV		 1050 }
1051
1052 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1053 for (i = 0; i < q_vector->rxr_count; i++) {
1054 rx_ring = &(adapter->rx_ring[r_idx]);
1055 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1056 q_vector->rx_itr,
1057 rx_ring->total_packets,
1058 rx_ring->total_bytes);
f494e8fa
AV		 1059 /* if the result for this queue would decrease interrupt
1060 * rate for this vector then use that result */
30efa5a3 1061 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1062 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1063 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1064 r_idx + 1);
f494e8fa
AV		 1065 }
1066
30efa5a3 1067 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1068
1069 switch (current_itr) {
1070 /* counts and packets in update_itr are dependent on these numbers */
1071 case lowest_latency:
1072 new_itr = 100000;
1073 break;
1074 case low_latency:
1075 new_itr = 20000; /* aka hwitr = ~200 */
1076 break;
1077 case bulk_latency:
1078 default:
1079 new_itr = 8000;
1080 break;
1081 }
1082
1083 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1084 /* do an exponential smoothing */
1085 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1086
1087 /* save the algorithm value here, not the smoothed one */
1088 q_vector->eitr = new_itr;
fe49f04a
AD		 1089
1090 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1091 }
1092
1093 return;
1094}
1095
0befdb3e
JB		 1096static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1097{
1098 struct ixgbe_hw *hw = &adapter->hw;
1099
1100 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1101 (eicr & IXGBE_EICR_GPI_SDP1)) {
1102 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1103 /* write to clear the interrupt */
1104 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1105 }
1106}
cf8280ee 1107
e8e26350
PW		 1108static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1109{
1110 struct ixgbe_hw *hw = &adapter->hw;
1111
1112 if (eicr & IXGBE_EICR_GPI_SDP1) {
1113 /* Clear the interrupt */
1114 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1115 schedule_work(&adapter->multispeed_fiber_task);
1116 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1117 /* Clear the interrupt */
1118 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1119 schedule_work(&adapter->sfp_config_module_task);
1120 } else {
1121 /* Interrupt isn't for us... */
1122 return;
1123 }
1124}
1125
cf8280ee
JB		 1126static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1127{
1128 struct ixgbe_hw *hw = &adapter->hw;
1129
1130 adapter->lsc_int++;
1131 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1132 adapter->link_check_timeout = jiffies;
1133 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1134 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1135 schedule_work(&adapter->watchdog_task);
1136 }
1137}
1138
9a799d71
AK		 1139static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1140{
1141 struct net_device *netdev = data;
1142 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1143 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1144 u32 eicr;
1145
1146 /*
1147 * Workaround for Silicon errata. Use clear-by-write instead
1148 * of clear-by-read. Reading with EICS will return the
1149 * interrupt causes without clearing, which later be done
1150 * with the write to EICR.
1151 */
1152 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1153 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1154
cf8280ee
JB		 1155 if (eicr & IXGBE_EICR_LSC)
1156 ixgbe_check_lsc(adapter);
d4f80882 1157
e8e26350
PW		 1158 if (hw->mac.type == ixgbe_mac_82598EB)
1159 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1160
c4cf55e5 1161 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1162 ixgbe_check_sfp_event(adapter, eicr);
c4cf55e5
PWJ		 1163
1164 /* Handle Flow Director Full threshold interrupt */
1165 if (eicr & IXGBE_EICR_FLOW_DIR) {
1166 int i;
1167 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1168 /* Disable transmits before FDIR Re-initialization */
1169 netif_tx_stop_all_queues(netdev);
1170 for (i = 0; i < adapter->num_tx_queues; i++) {
1171 struct ixgbe_ring *tx_ring =
1172 &adapter->tx_ring[i];
1173 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1174 &tx_ring->reinit_state))
1175 schedule_work(&adapter->fdir_reinit_task);
1176 }
1177 }
1178 }
d4f80882
AV		 1179 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1180 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1181
1182 return IRQ_HANDLED;
1183}
1184
fe49f04a
AD		 1185static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1186 u64 qmask)
1187{
1188 u32 mask;
1189
1190 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1191 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1192 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1193 } else {
1194 mask = (qmask & 0xFFFFFFFF);
1195 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1196 mask = (qmask >> 32);
1197 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1198 }
1199 /* skip the flush */
1200}
1201
1202static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1203 u64 qmask)
1204{
1205 u32 mask;
1206
1207 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1208 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1209 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1210 } else {
1211 mask = (qmask & 0xFFFFFFFF);
1212 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1213 mask = (qmask >> 32);
1214 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1215 }
1216 /* skip the flush */
1217}
1218
9a799d71
AK		 1219static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1220{
021230d4
AV		 1221 struct ixgbe_q_vector *q_vector = data;
1222 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1223 struct ixgbe_ring *tx_ring;
021230d4
AV		 1224 int i, r_idx;
1225
1226 if (!q_vector->txr_count)
1227 return IRQ_HANDLED;
1228
1229 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1230 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 1231 tx_ring = &(adapter->tx_ring[r_idx]);
3a581073
JB		 1232 tx_ring->total_bytes = 0;
1233 tx_ring->total_packets = 0;
021230d4 1234 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1235 r_idx + 1);
021230d4 1236 }
9a799d71 1237
91281fd3
AD		 1238 /* disable interrupts on this vector only */
1239 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1240 napi_schedule(&q_vector->napi);
1241
9a799d71
AK		 1242 return IRQ_HANDLED;
1243}
1244
021230d4
AV		 1245/**
1246 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1247 * @irq: unused
1248 * @data: pointer to our q_vector struct for this interrupt vector
1249 **/
9a799d71
AK		 1250static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1251{
021230d4
AV		 1252 struct ixgbe_q_vector *q_vector = data;
1253 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1254 struct ixgbe_ring *rx_ring;
021230d4 1255 int r_idx;
30efa5a3 1256 int i;
021230d4
AV		 1257
1258 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 1259 for (i = 0; i < q_vector->rxr_count; i++) {
1260 rx_ring = &(adapter->rx_ring[r_idx]);
1261 rx_ring->total_bytes = 0;
1262 rx_ring->total_packets = 0;
1263 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1264 r_idx + 1);
1265 }
1266
021230d4
AV		 1267 if (!q_vector->rxr_count)
1268 return IRQ_HANDLED;
1269
30efa5a3 1270 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1271 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 1272 /* disable interrupts on this vector only */
fe49f04a 1273 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
288379f0 1274 napi_schedule(&q_vector->napi);
021230d4
AV		 1275
1276 return IRQ_HANDLED;
1277}
1278
1279static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1280{
91281fd3
AD		 1281 struct ixgbe_q_vector *q_vector = data;
1282 struct ixgbe_adapter *adapter = q_vector->adapter;
1283 struct ixgbe_ring *ring;
1284 int r_idx;
1285 int i;
1286
1287 if (!q_vector->txr_count && !q_vector->rxr_count)
1288 return IRQ_HANDLED;
1289
1290 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1291 for (i = 0; i < q_vector->txr_count; i++) {
1292 ring = &(adapter->tx_ring[r_idx]);
1293 ring->total_bytes = 0;
1294 ring->total_packets = 0;
1295 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1296 r_idx + 1);
1297 }
1298
1299 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1300 for (i = 0; i < q_vector->rxr_count; i++) {
1301 ring = &(adapter->rx_ring[r_idx]);
1302 ring->total_bytes = 0;
1303 ring->total_packets = 0;
1304 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1305 r_idx + 1);
1306 }
1307
1308 /* disable interrupts on this vector only */
1309 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1310 napi_schedule(&q_vector->napi);
9a799d71 1311
9a799d71
AK		 1312 return IRQ_HANDLED;
1313}
1314
021230d4
AV		 1315/**
1316 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1317 * @napi: napi struct with our devices info in it
1318 * @budget: amount of work driver is allowed to do this pass, in packets
1319 *
f0848276
JB		 1320 * This function is optimized for cleaning one queue only on a single
1321 * q_vector!!!
021230d4 1322 **/
9a799d71
AK		 1323static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1324{
021230d4 1325 struct ixgbe_q_vector *q_vector =
b4617240 1326 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1327 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1328 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1329 int work_done = 0;
021230d4 1330 long r_idx;
9a799d71 1331
021230d4 1332 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1333 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1334#ifdef CONFIG_IXGBE_DCA
bd0362dd 1335 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1336 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1337#endif
9a799d71 1338
78b6f4ce 1339 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1340
021230d4
AV		 1341 /* If all Rx work done, exit the polling mode */
1342 if (work_done < budget) {
288379f0 1343 napi_complete(napi);
509ee935 1344 if (adapter->itr_setting & 1)
f494e8fa 1345 ixgbe_set_itr_msix(q_vector);
9a799d71 1346 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1347 ixgbe_irq_enable_queues(adapter,
1348 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1349 }
1350
1351 return work_done;
1352}
1353
f0848276 1354/**
91281fd3 1355 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1356 * @napi: napi struct with our devices info in it
1357 * @budget: amount of work driver is allowed to do this pass, in packets
1358 *
1359 * This function will clean more than one rx queue associated with a
1360 * q_vector.
1361 **/
91281fd3 1362static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1363{
1364 struct ixgbe_q_vector *q_vector =
1365 container_of(napi, struct ixgbe_q_vector, napi);
1366 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1367 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1368 int work_done = 0, i;
1369 long r_idx;
91281fd3
AD		 1370 bool tx_clean_complete = true;
1371
1372 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1373 for (i = 0; i < q_vector->txr_count; i++) {
1374 ring = &(adapter->tx_ring[r_idx]);
1375#ifdef CONFIG_IXGBE_DCA
1376 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1377 ixgbe_update_tx_dca(adapter, ring);
1378#endif
1379 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1380 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1381 r_idx + 1);
1382 }
f0848276
JB		 1383
1384 /* attempt to distribute budget to each queue fairly, but don't allow
1385 * the budget to go below 1 because we'll exit polling */
1386 budget /= (q_vector->rxr_count ?: 1);
1387 budget = max(budget, 1);
1388 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1389 for (i = 0; i < q_vector->rxr_count; i++) {
91281fd3 1390 ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1391#ifdef CONFIG_IXGBE_DCA
f0848276 1392 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1393 ixgbe_update_rx_dca(adapter, ring);
f0848276 1394#endif
91281fd3 1395 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276
JB		 1396 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1397 r_idx + 1);
1398 }
1399
1400 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
91281fd3 1401 ring = &(adapter->rx_ring[r_idx]);
f0848276 1402 /* If all Rx work done, exit the polling mode */
7f821875 1403 if (work_done < budget) {
288379f0 1404 napi_complete(napi);
509ee935 1405 if (adapter->itr_setting & 1)
f0848276
JB		 1406 ixgbe_set_itr_msix(q_vector);
1407 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1408 ixgbe_irq_enable_queues(adapter,
1409 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1410 return 0;
1411 }
1412
1413 return work_done;
1414}
91281fd3
AD		 1415
1416/**
1417 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1418 * @napi: napi struct with our devices info in it
1419 * @budget: amount of work driver is allowed to do this pass, in packets
1420 *
1421 * This function is optimized for cleaning one queue only on a single
1422 * q_vector!!!
1423 **/
1424static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1425{
1426 struct ixgbe_q_vector *q_vector =
1427 container_of(napi, struct ixgbe_q_vector, napi);
1428 struct ixgbe_adapter *adapter = q_vector->adapter;
1429 struct ixgbe_ring *tx_ring = NULL;
1430 int work_done = 0;
1431 long r_idx;
1432
1433 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1434 tx_ring = &(adapter->tx_ring[r_idx]);
1435#ifdef CONFIG_IXGBE_DCA
1436 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1437 ixgbe_update_tx_dca(adapter, tx_ring);
1438#endif
1439
1440 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1441 work_done = budget;
1442
1443 /* If all Rx work done, exit the polling mode */
1444 if (work_done < budget) {
1445 napi_complete(napi);
1446 if (adapter->itr_setting & 1)
1447 ixgbe_set_itr_msix(q_vector);
1448 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1449 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1450 }
1451
1452 return work_done;
1453}
1454
021230d4 1455static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1456 int r_idx)
021230d4 1457{
7a921c93
AD		 1458 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1459
1460 set_bit(r_idx, q_vector->rxr_idx);
1461 q_vector->rxr_count++;
021230d4
AV		 1462}
1463
1464static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 1465 int t_idx)
021230d4 1466{
7a921c93
AD		 1467 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1468
1469 set_bit(t_idx, q_vector->txr_idx);
1470 q_vector->txr_count++;
021230d4
AV		 1471}
1472
9a799d71 1473/**
021230d4
AV		 1474 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1475 * @adapter: board private structure to initialize
1476 * @vectors: allotted vector count for descriptor rings
9a799d71 1477 *
021230d4
AV		 1478 * This function maps descriptor rings to the queue-specific vectors
1479 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1480 * one vector per ring/queue, but on a constrained vector budget, we
1481 * group the rings as "efficiently" as possible. You would add new
1482 * mapping configurations in here.
9a799d71 1483 **/
021230d4 1484static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1485 int vectors)
021230d4
AV		 1486{
1487 int v_start = 0;
1488 int rxr_idx = 0, txr_idx = 0;
1489 int rxr_remaining = adapter->num_rx_queues;
1490 int txr_remaining = adapter->num_tx_queues;
1491 int i, j;
1492 int rqpv, tqpv;
1493 int err = 0;
1494
1495 /* No mapping required if MSI-X is disabled. */
1496 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1497 goto out;
9a799d71 1498
021230d4
AV		 1499 /*
1500 * The ideal configuration...
1501 * We have enough vectors to map one per queue.
1502 */
1503 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1504 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1505 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1506
021230d4
AV		 1507 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1508 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1509
9a799d71 1510 goto out;
021230d4 1511 }
9a799d71 1512
021230d4
AV		 1513 /*
1514 * If we don't have enough vectors for a 1-to-1
1515 * mapping, we'll have to group them so there are
1516 * multiple queues per vector.
1517 */
1518 /* Re-adjusting *qpv takes care of the remainder. */
1519 for (i = v_start; i < vectors; i++) {
1520 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1521 for (j = 0; j < rqpv; j++) {
1522 map_vector_to_rxq(adapter, i, rxr_idx);
1523 rxr_idx++;
1524 rxr_remaining--;
1525 }
1526 }
1527 for (i = v_start; i < vectors; i++) {
1528 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1529 for (j = 0; j < tqpv; j++) {
1530 map_vector_to_txq(adapter, i, txr_idx);
1531 txr_idx++;
1532 txr_remaining--;
9a799d71 1533 }
9a799d71
AK		 1534 }
1535
021230d4
AV		 1536out:
1537 return err;
1538}
1539
1540/**
1541 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1542 * @adapter: board private structure
1543 *
1544 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1545 * interrupts from the kernel.
1546 **/
1547static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1548{
1549 struct net_device *netdev = adapter->netdev;
1550 irqreturn_t (*handler)(int, void *);
1551 int i, vector, q_vectors, err;
cb13fc20 1552 int ri=0, ti=0;
021230d4
AV		 1553
1554 /* Decrement for Other and TCP Timer vectors */
1555 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1556
1557 /* Map the Tx/Rx rings to the vectors we were allotted. */
1558 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1559 if (err)
1560 goto out;
1561
1562#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1563 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1564 &ixgbe_msix_clean_many)
021230d4 1565 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 1566 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 1567
1568 if(handler == &ixgbe_msix_clean_rx) {
1569 sprintf(adapter->name[vector], "%s-%s-%d",
1570 netdev->name, "rx", ri++);
1571 }
1572 else if(handler == &ixgbe_msix_clean_tx) {
1573 sprintf(adapter->name[vector], "%s-%s-%d",
1574 netdev->name, "tx", ti++);
1575 }
1576 else
1577 sprintf(adapter->name[vector], "%s-%s-%d",
1578 netdev->name, "TxRx", vector);
1579
021230d4 1580 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1581 handler, 0, adapter->name[vector],
7a921c93 1582 adapter->q_vector[vector]);
9a799d71
AK		 1583 if (err) {
1584 DPRINTK(PROBE, ERR,
b4617240
PW		 1585 "request_irq failed for MSIX interrupt "
1586 "Error: %d\n", err);
021230d4 1587 goto free_queue_irqs;
9a799d71 1588 }
9a799d71
AK		 1589 }
1590
021230d4
AV		 1591 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1592 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1593 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1594 if (err) {
1595 DPRINTK(PROBE, ERR,
1596 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1597 goto free_queue_irqs;
9a799d71
AK		 1598 }
1599
9a799d71
AK		 1600 return 0;
1601
021230d4
AV		 1602free_queue_irqs:
1603 for (i = vector - 1; i >= 0; i--)
1604 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 1605 adapter->q_vector[i]);
021230d4
AV		 1606 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1607 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1608 kfree(adapter->msix_entries);
1609 adapter->msix_entries = NULL;
021230d4 1610out:
9a799d71
AK		 1611 return err;
1612}
1613
f494e8fa
AV		 1614static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1615{
7a921c93 1616 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 1617 u8 current_itr;
1618 u32 new_itr = q_vector->eitr;
1619 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1620 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1621
30efa5a3 1622 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1623 q_vector->tx_itr,
1624 tx_ring->total_packets,
1625 tx_ring->total_bytes);
30efa5a3 1626 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1627 q_vector->rx_itr,
1628 rx_ring->total_packets,
1629 rx_ring->total_bytes);
f494e8fa 1630
30efa5a3 1631 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1632
1633 switch (current_itr) {
1634 /* counts and packets in update_itr are dependent on these numbers */
1635 case lowest_latency:
1636 new_itr = 100000;
1637 break;
1638 case low_latency:
1639 new_itr = 20000; /* aka hwitr = ~200 */
1640 break;
1641 case bulk_latency:
1642 new_itr = 8000;
1643 break;
1644 default:
1645 break;
1646 }
1647
1648 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1649 /* do an exponential smoothing */
1650 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1651
1652 /* save the algorithm value here, not the smoothed one */
1653 q_vector->eitr = new_itr;
fe49f04a
AD		 1654
1655 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1656 }
1657
1658 return;
1659}
1660
79aefa45
AD		 1661/**
1662 * ixgbe_irq_enable - Enable default interrupt generation settings
1663 * @adapter: board private structure
1664 **/
1665static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1666{
1667 u32 mask;
835462fc
NS		 1668
1669 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 1670 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1671 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1672 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1673 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1674 mask |= IXGBE_EIMS_GPI_SDP1;
1675 mask |= IXGBE_EIMS_GPI_SDP2;
1676 }
c4cf55e5
PWJ		 1677 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1678 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1679 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 1680
79aefa45 1681 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 1682 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45
AD		 1683 IXGBE_WRITE_FLUSH(&adapter->hw);
1684}
021230d4 1685
9a799d71 1686/**
021230d4 1687 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1688 * @irq: interrupt number
1689 * @data: pointer to a network interface device structure
9a799d71
AK		 1690 **/
1691static irqreturn_t ixgbe_intr(int irq, void *data)
1692{
1693 struct net_device *netdev = data;
1694 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1695 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 1696 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 1697 u32 eicr;
1698
54037505
DS		 1699 /*
1700 * Workaround for silicon errata. Mask the interrupts
1701 * before the read of EICR.
1702 */
1703 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1704
021230d4
AV		 1705 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1706 * therefore no explict interrupt disable is necessary */
1707 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1708 if (!eicr) {
1709 /* shared interrupt alert!
1710 * make sure interrupts are enabled because the read will
1711 * have disabled interrupts due to EIAM */
1712 ixgbe_irq_enable(adapter);
9a799d71 1713 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1714 }
9a799d71 1715
cf8280ee
JB		 1716 if (eicr & IXGBE_EICR_LSC)
1717 ixgbe_check_lsc(adapter);
021230d4 1718
e8e26350
PW		 1719 if (hw->mac.type == ixgbe_mac_82599EB)
1720 ixgbe_check_sfp_event(adapter, eicr);
1721
0befdb3e
JB		 1722 ixgbe_check_fan_failure(adapter, eicr);
1723
7a921c93 1724 if (napi_schedule_prep(&(q_vector->napi))) {
f494e8fa
AV		 1725 adapter->tx_ring[0].total_packets = 0;
1726 adapter->tx_ring[0].total_bytes = 0;
1727 adapter->rx_ring[0].total_packets = 0;
1728 adapter->rx_ring[0].total_bytes = 0;
021230d4 1729 /* would disable interrupts here but EIAM disabled it */
7a921c93 1730 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 1731 }
1732
1733 return IRQ_HANDLED;
1734}
1735
021230d4
AV		 1736static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1737{
1738 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1739
1740 for (i = 0; i < q_vectors; i++) {
7a921c93 1741 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 1742 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1743 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1744 q_vector->rxr_count = 0;
1745 q_vector->txr_count = 0;
1746 }
1747}
1748
9a799d71
AK		 1749/**
1750 * ixgbe_request_irq - initialize interrupts
1751 * @adapter: board private structure
1752 *
1753 * Attempts to configure interrupts using the best available
1754 * capabilities of the hardware and kernel.
1755 **/
021230d4 1756static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1757{
1758 struct net_device *netdev = adapter->netdev;
021230d4 1759 int err;
9a799d71 1760
021230d4
AV		 1761 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1762 err = ixgbe_request_msix_irqs(adapter);
1763 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1764 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
b4617240 1765 netdev->name, netdev);
021230d4
AV		 1766 } else {
1767 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
b4617240 1768 netdev->name, netdev);
9a799d71
AK		 1769 }
1770
9a799d71
AK		 1771 if (err)
1772 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1773
9a799d71
AK		 1774 return err;
1775}
1776
1777static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1778{
1779 struct net_device *netdev = adapter->netdev;
1780
1781 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1782 int i, q_vectors;
9a799d71 1783
021230d4
AV		 1784 q_vectors = adapter->num_msix_vectors;
1785
1786 i = q_vectors - 1;
9a799d71 1787 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1788
021230d4
AV		 1789 i--;
1790 for (; i >= 0; i--) {
1791 free_irq(adapter->msix_entries[i].vector,
7a921c93 1792 adapter->q_vector[i]);
021230d4
AV		 1793 }
1794
1795 ixgbe_reset_q_vectors(adapter);
1796 } else {
1797 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1798 }
1799}
1800
22d5a71b
JB		 1801/**
1802 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1803 * @adapter: board private structure
1804 **/
1805static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1806{
835462fc
NS		 1807 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1808 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1809 } else {
1810 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1811 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 1812 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
22d5a71b
JB		 1813 }
1814 IXGBE_WRITE_FLUSH(&adapter->hw);
1815 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1816 int i;
1817 for (i = 0; i < adapter->num_msix_vectors; i++)
1818 synchronize_irq(adapter->msix_entries[i].vector);
1819 } else {
1820 synchronize_irq(adapter->pdev->irq);
1821 }
1822}
1823
9a799d71
AK		 1824/**
1825 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1826 *
1827 **/
1828static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1829{
9a799d71
AK		 1830 struct ixgbe_hw *hw = &adapter->hw;
1831
021230d4 1832 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
30efa5a3 1833 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
9a799d71 1834
e8e26350
PW		 1835 ixgbe_set_ivar(adapter, 0, 0, 0);
1836 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 1837
1838 map_vector_to_rxq(adapter, 0, 0);
1839 map_vector_to_txq(adapter, 0, 0);
1840
1841 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1842}
1843
1844/**
3a581073 1845 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1846 * @adapter: board private structure
1847 *
1848 * Configure the Tx unit of the MAC after a reset.
1849 **/
1850static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1851{
12207e49 1852 u64 tdba;
9a799d71 1853 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1854 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1855
1856 /* Setup the HW Tx Head and Tail descriptor pointers */
1857 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1858 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1859 j = ring->reg_idx;
1860 tdba = ring->dma;
1861 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1862 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 1863 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 1864 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1865 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1866 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1867 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1868 adapter->tx_ring[i].head = IXGBE_TDH(j);
1869 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1870 /* Disable Tx Head Writeback RO bit, since this hoses
1871 * bookkeeping if things aren't delivered in order.
1872 */
e01c31a5 1873 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1874 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1875 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1876 }
e8e26350
PW		 1877 if (hw->mac.type == ixgbe_mac_82599EB) {
1878 /* We enable 8 traffic classes, DCB only */
1879 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1880 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1881 IXGBE_MTQC_8TC_8TQ));
1882 }
9a799d71
AK		 1883}
1884
e8e26350 1885#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c
JB		 1886
1887static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1888{
1889 struct ixgbe_ring *rx_ring;
1890 u32 srrctl;
e8e26350 1891 int queue0 = 0;
3be1adfb 1892 unsigned long mask;
0cefafad 1893 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 1894
e8e26350 1895 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
163de42e 1896 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
0cefafad 1897 int dcb_i = feature[RING_F_DCB].indices;
163de42e
AD		 1898 if (dcb_i == 8)
1899 queue0 = index >> 4;
1900 else if (dcb_i == 4)
1901 queue0 = index >> 5;
1902 else
1903 dev_err(&adapter->pdev->dev, "Invalid DCB "
1904 "configuration\n");
0331a832
YZ		 1905#ifdef IXGBE_FCOE
1906 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1907 struct ixgbe_ring_feature *f;
1908
1909 rx_ring = &adapter->rx_ring[queue0];
1910 f = &adapter->ring_feature[RING_F_FCOE];
1911 if ((queue0 == 0) && (index > rx_ring->reg_idx))
1912 queue0 = f->mask + index -
1913 rx_ring->reg_idx - 1;
1914 }
1915#endif /* IXGBE_FCOE */
163de42e
AD		 1916 } else {
1917 queue0 = index;
1918 }
cc41ac7c 1919 } else {
0cefafad 1920 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb
AD		 1921 queue0 = index & mask;
1922 index = index & mask;
cc41ac7c 1923 }
3be1adfb 1924
cc41ac7c
JB		 1925 rx_ring = &adapter->rx_ring[queue0];
1926
1927 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1928
1929 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1930 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1931
afafd5b0
AD		 1932 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1933 IXGBE_SRRCTL_BSIZEHDR_MASK;
1934
cc41ac7c 1935 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
afafd5b0
AD		 1936#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1937 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1938#else
1939 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1940#endif
cc41ac7c 1941 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 1942 } else {
afafd5b0
AD		 1943 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1944 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 1945 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 1946 }
e8e26350 1947
cc41ac7c
JB		 1948 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1949}
9a799d71 1950
0cefafad
JB		 1951static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1952{
1953 u32 mrqc = 0;
1954 int mask;
1955
1956 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1957 return mrqc;
1958
1959 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1960#ifdef CONFIG_IXGBE_DCB
1961 | IXGBE_FLAG_DCB_ENABLED
1962#endif
1963 );
1964
1965 switch (mask) {
1966 case (IXGBE_FLAG_RSS_ENABLED):
1967 mrqc = IXGBE_MRQC_RSSEN;
1968 break;
1969#ifdef CONFIG_IXGBE_DCB
1970 case (IXGBE_FLAG_DCB_ENABLED):
1971 mrqc = IXGBE_MRQC_RT8TCEN;
1972 break;
1973#endif /* CONFIG_IXGBE_DCB */
1974 default:
1975 break;
1976 }
1977
1978 return mrqc;
1979}
1980
9a799d71 1981/**
3a581073 1982 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1983 * @adapter: board private structure
1984 *
1985 * Configure the Rx unit of the MAC after a reset.
1986 **/
1987static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1988{
1989 u64 rdba;
1990 struct ixgbe_hw *hw = &adapter->hw;
1991 struct net_device *netdev = adapter->netdev;
1992 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1993 int i, j;
9a799d71 1994 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1995 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1996 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1997 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1998 u32 fctrl, hlreg0;
509ee935 1999 u32 reta = 0, mrqc = 0;
cc41ac7c 2000 u32 rdrxctl;
f8212f97 2001 u32 rscctrl;
7c6e0a43 2002 int rx_buf_len;
9a799d71
AK		 2003
2004 /* Decide whether to use packet split mode or not */
762f4c57 2005 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71 2006
eacd73f7
YZ		 2007#ifdef IXGBE_FCOE
2008 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2009 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2010#endif /* IXGBE_FCOE */
2011
9a799d71
AK		 2012 /* Set the RX buffer length according to the mode */
2013 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2014 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 2015 if (hw->mac.type == ixgbe_mac_82599EB) {
2016 /* PSRTYPE must be initialized in 82599 */
2017 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2018 IXGBE_PSRTYPE_UDPHDR |
2019 IXGBE_PSRTYPE_IPV4HDR |
dfa12f05
YZ		 2020 IXGBE_PSRTYPE_IPV6HDR |
2021 IXGBE_PSRTYPE_L2HDR;
e8e26350
PW		 2022 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2023 }
9a799d71 2024 } else {
df647b5c 2025 if (!(adapter->flags & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2026 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2027 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2028 else
7c6e0a43 2029 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 2030 }
2031
2032 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2033 fctrl |= IXGBE_FCTRL_BAM;
021230d4 2034 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 2035 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 2036 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2037
2038 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2039 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2040 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2041 else
2042 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
63f39bd1
YZ		 2043#ifdef IXGBE_FCOE
2044 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2045 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2046#endif
9a799d71
AK		 2047 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2048
9a799d71
AK		 2049 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2050 /* disable receives while setting up the descriptors */
2051 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2052 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2053
0cefafad
JB		 2054 /*
2055 * Setup the HW Rx Head and Tail Descriptor Pointers and
2056 * the Base and Length of the Rx Descriptor Ring
2057 */
9a799d71
AK		 2058 for (i = 0; i < adapter->num_rx_queues; i++) {
2059 rdba = adapter->rx_ring[i].dma;
7c6e0a43 2060 j = adapter->rx_ring[i].reg_idx;
284901a9 2061 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 2062 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2063 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2064 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2065 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2066 adapter->rx_ring[i].head = IXGBE_RDH(j);
2067 adapter->rx_ring[i].tail = IXGBE_RDT(j);
2068 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
cc41ac7c 2069
63f39bd1
YZ		 2070#ifdef IXGBE_FCOE
2071 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
2072 struct ixgbe_ring_feature *f;
2073 f = &adapter->ring_feature[RING_F_FCOE];
2074 if ((rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
2075 (i >= f->mask) && (i < f->mask + f->indices))
2076 adapter->rx_ring[i].rx_buf_len =
2077 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2078 }
2079
2080#endif /* IXGBE_FCOE */
cc41ac7c 2081 ixgbe_configure_srrctl(adapter, j);
9a799d71
AK		 2082 }
2083
e8e26350
PW		 2084 if (hw->mac.type == ixgbe_mac_82598EB) {
2085 /*
2086 * For VMDq support of different descriptor types or
2087 * buffer sizes through the use of multiple SRRCTL
2088 * registers, RDRXCTL.MVMEN must be set to 1
2089 *
2090 * also, the manual doesn't mention it clearly but DCA hints
2091 * will only use queue 0's tags unless this bit is set. Side
2092 * effects of setting this bit are only that SRRCTL must be
2093 * fully programmed [0..15]
2094 */
2a41ff81
JB		 2095 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2096 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2097 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 2098 }
177db6ff 2099
e8e26350 2100 /* Program MRQC for the distribution of queues */
0cefafad 2101 mrqc = ixgbe_setup_mrqc(adapter);
e8e26350 2102
021230d4 2103 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 2104 /* Fill out redirection table */
021230d4
AV		 2105 for (i = 0, j = 0; i < 128; i++, j++) {
2106 if (j == adapter->ring_feature[RING_F_RSS].indices)
2107 j = 0;
2108 /* reta = 4-byte sliding window of
2109 * 0x00..(indices-1)(indices-1)00..etc. */
2110 reta = (reta << 8) | (j * 0x11);
2111 if ((i & 3) == 3)
2112 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 2113 }
2114
2115 /* Fill out hash function seeds */
2116 for (i = 0; i < 10; i++)
7c6e0a43 2117 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 2118
2a41ff81
JB		 2119 if (hw->mac.type == ixgbe_mac_82598EB)
2120 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 2121 /* Perform hash on these packet types */
2a41ff81
JB		 2122 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2123 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2124 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2125 | IXGBE_MRQC_RSS_FIELD_IPV6
2126 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2127 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 2128 }
2a41ff81 2129 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 2130
021230d4
AV		 2131 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2132
2133 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2134 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2135 /* Disable indicating checksum in descriptor, enables
2136 * RSS hash */
9a799d71 2137 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 2138 }
021230d4
AV		 2139 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2140 /* Enable IPv4 payload checksum for UDP fragments
2141 * if PCSD is not set */
2142 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2143 }
2144
2145 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 2146
2147 if (hw->mac.type == ixgbe_mac_82599EB) {
2148 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2149 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 2150 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 2151 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2152 }
f8212f97 2153
df647b5c 2154 if (adapter->flags & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97
AD		 2155 /* Enable 82599 HW-RSC */
2156 for (i = 0; i < adapter->num_rx_queues; i++) {
2157 j = adapter->rx_ring[i].reg_idx;
2158 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2159 rscctrl |= IXGBE_RSCCTL_RSCEN;
2160 /*
e76678dd
AD		 2161 * we must limit the number of descriptors so that the
2162 * total size of max desc * buf_len is not greater
2163 * than 65535
f8212f97 2164 */
e76678dd
AD		 2165 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2166#if (MAX_SKB_FRAGS > 16)
2167 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2168#elif (MAX_SKB_FRAGS > 8)
f8212f97 2169 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
e76678dd
AD		 2170#elif (MAX_SKB_FRAGS > 4)
2171 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
f8212f97 2172#else
e76678dd 2173 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
f8212f97 2174#endif
e76678dd
AD		 2175 } else {
2176 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2177 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2178 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2179 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2180 else
2181 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2182 }
f8212f97
AD		 2183 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2184 }
2185 /* Disable RSC for ACK packets */
2186 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2187 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2188 }
9a799d71
AK		 2189}
2190
068c89b0
DS		 2191static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2192{
2193 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2194 struct ixgbe_hw *hw = &adapter->hw;
2195
2196 /* add VID to filter table */
2197 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2198}
2199
2200static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2201{
2202 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2203 struct ixgbe_hw *hw = &adapter->hw;
2204
2205 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2206 ixgbe_irq_disable(adapter);
2207
2208 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2209
2210 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2211 ixgbe_irq_enable(adapter);
2212
2213 /* remove VID from filter table */
2214 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2215}
2216
9a799d71 2217static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2218 struct vlan_group *grp)
9a799d71
AK		 2219{
2220 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2221 u32 ctrl;
e8e26350 2222 int i, j;
9a799d71 2223
d4f80882
AV		 2224 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2225 ixgbe_irq_disable(adapter);
9a799d71
AK		 2226 adapter->vlgrp = grp;
2227
2f90b865
AD		 2228 /*
2229 * For a DCB driver, always enable VLAN tag stripping so we can
2230 * still receive traffic from a DCB-enabled host even if we're
2231 * not in DCB mode.
2232 */
2233 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
e8e26350
PW		 2234 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2235 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2236 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2237 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2238 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2239 ctrl |= IXGBE_VLNCTRL_VFE;
9a799d71
AK		 2240 /* enable VLAN tag insert/strip */
2241 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
9a799d71
AK		 2242 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2243 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
e8e26350
PW		 2244 for (i = 0; i < adapter->num_rx_queues; i++) {
2245 j = adapter->rx_ring[i].reg_idx;
2246 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2247 ctrl |= IXGBE_RXDCTL_VME;
2248 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2249 }
9a799d71 2250 }
e8e26350 2251 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2252
d4f80882
AV		 2253 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2254 ixgbe_irq_enable(adapter);
9a799d71
AK		 2255}
2256
9a799d71
AK		 2257static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2258{
2259 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2260
2261 if (adapter->vlgrp) {
2262 u16 vid;
2263 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2264 if (!vlan_group_get_device(adapter->vlgrp, vid))
2265 continue;
2266 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2267 }
2268 }
2269}
2270
2c5645cf
CL		 2271static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2272{
2273 struct dev_mc_list *mc_ptr;
2274 u8 *addr = *mc_addr_ptr;
2275 *vmdq = 0;
2276
2277 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2278 if (mc_ptr->next)
2279 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2280 else
2281 *mc_addr_ptr = NULL;
2282
2283 return addr;
2284}
2285
9a799d71 2286/**
2c5645cf 2287 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2288 * @netdev: network interface device structure
2289 *
2c5645cf
CL		 2290 * The set_rx_method entry point is called whenever the unicast/multicast
2291 * address list or the network interface flags are updated. This routine is
2292 * responsible for configuring the hardware for proper unicast, multicast and
2293 * promiscuous mode.
9a799d71 2294 **/
2c5645cf 2295static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2296{
2297 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2298 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 2299 u32 fctrl, vlnctrl;
2c5645cf
CL		 2300 u8 *addr_list = NULL;
2301 int addr_count = 0;
9a799d71
AK		 2302
2303 /* Check for Promiscuous and All Multicast modes */
2304
2305 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 2306 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 2307
2308 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2309 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2310 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 2311 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 2312 } else {
746b9f02
PM		 2313 if (netdev->flags & IFF_ALLMULTI) {
2314 fctrl |= IXGBE_FCTRL_MPE;
2315 fctrl &= ~IXGBE_FCTRL_UPE;
2316 } else {
2317 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2318 }
3d01625a 2319 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 2320 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2321 }
2322
2323 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 2324 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 2325
2c5645cf 2326 /* reprogram secondary unicast list */
31278e71 2327 hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
9a799d71 2328
2c5645cf
CL		 2329 /* reprogram multicast list */
2330 addr_count = netdev->mc_count;
2331 if (addr_count)
2332 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 2333 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2334 ixgbe_addr_list_itr);
9a799d71
AK		 2335}
2336
021230d4
AV		 2337static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2338{
2339 int q_idx;
2340 struct ixgbe_q_vector *q_vector;
2341 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2342
2343 /* legacy and MSI only use one vector */
2344 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2345 q_vectors = 1;
2346
2347 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2348 struct napi_struct *napi;
7a921c93 2349 q_vector = adapter->q_vector[q_idx];
f0848276 2350 napi = &q_vector->napi;
91281fd3
AD		 2351 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2352 if (!q_vector->rxr_count || !q_vector->txr_count) {
2353 if (q_vector->txr_count == 1)
2354 napi->poll = &ixgbe_clean_txonly;
2355 else if (q_vector->rxr_count == 1)
2356 napi->poll = &ixgbe_clean_rxonly;
2357 }
2358 }
f0848276
JB		 2359
2360 napi_enable(napi);
021230d4
AV		 2361 }
2362}
2363
2364static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2365{
2366 int q_idx;
2367 struct ixgbe_q_vector *q_vector;
2368 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2369
2370 /* legacy and MSI only use one vector */
2371 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2372 q_vectors = 1;
2373
2374 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 2375 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2376 napi_disable(&q_vector->napi);
2377 }
2378}
2379
7a6b6f51 2380#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2381/*
2382 * ixgbe_configure_dcb - Configure DCB hardware
2383 * @adapter: ixgbe adapter struct
2384 *
2385 * This is called by the driver on open to configure the DCB hardware.
2386 * This is also called by the gennetlink interface when reconfiguring
2387 * the DCB state.
2388 */
2389static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2390{
2391 struct ixgbe_hw *hw = &adapter->hw;
2392 u32 txdctl, vlnctrl;
2393 int i, j;
2394
2395 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2396 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2397 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2398
2399 /* reconfigure the hardware */
2400 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2401
2402 for (i = 0; i < adapter->num_tx_queues; i++) {
2403 j = adapter->tx_ring[i].reg_idx;
2404 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2405 /* PThresh workaround for Tx hang with DFP enabled. */
2406 txdctl |= 32;
2407 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2408 }
2409 /* Enable VLAN tag insert/strip */
2410 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
e8e26350
PW		 2411 if (hw->mac.type == ixgbe_mac_82598EB) {
2412 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2413 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2414 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2415 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2416 vlnctrl |= IXGBE_VLNCTRL_VFE;
2417 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2418 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2419 for (i = 0; i < adapter->num_rx_queues; i++) {
2420 j = adapter->rx_ring[i].reg_idx;
2421 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2422 vlnctrl |= IXGBE_RXDCTL_VME;
2423 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2424 }
2425 }
2f90b865
AD		 2426 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2427}
2428
2429#endif
9a799d71
AK		 2430static void ixgbe_configure(struct ixgbe_adapter *adapter)
2431{
2432 struct net_device *netdev = adapter->netdev;
c4cf55e5 2433 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 2434 int i;
2435
2c5645cf 2436 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2437
2438 ixgbe_restore_vlan(adapter);
7a6b6f51 2439#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2440 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2441 netif_set_gso_max_size(netdev, 32768);
2442 ixgbe_configure_dcb(adapter);
2443 } else {
2444 netif_set_gso_max_size(netdev, 65536);
2445 }
2446#else
2447 netif_set_gso_max_size(netdev, 65536);
2448#endif
9a799d71 2449
eacd73f7
YZ		 2450#ifdef IXGBE_FCOE
2451 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2452 ixgbe_configure_fcoe(adapter);
2453
2454#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 2455 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2456 for (i = 0; i < adapter->num_tx_queues; i++)
2457 adapter->tx_ring[i].atr_sample_rate =
2458 adapter->atr_sample_rate;
2459 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2460 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2461 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2462 }
2463
9a799d71
AK		 2464 ixgbe_configure_tx(adapter);
2465 ixgbe_configure_rx(adapter);
2466 for (i = 0; i < adapter->num_rx_queues; i++)
2467 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 2468 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 2469}
2470
e8e26350
PW		 2471static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2472{
2473 switch (hw->phy.type) {
2474 case ixgbe_phy_sfp_avago:
2475 case ixgbe_phy_sfp_ftl:
2476 case ixgbe_phy_sfp_intel:
2477 case ixgbe_phy_sfp_unknown:
2478 case ixgbe_phy_tw_tyco:
2479 case ixgbe_phy_tw_unknown:
2480 return true;
2481 default:
2482 return false;
2483 }
2484}
2485
0ecc061d 2486/**
e8e26350
PW		 2487 * ixgbe_sfp_link_config - set up SFP+ link
2488 * @adapter: pointer to private adapter struct
2489 **/
2490static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2491{
2492 struct ixgbe_hw *hw = &adapter->hw;
2493
2494 if (hw->phy.multispeed_fiber) {
2495 /*
2496 * In multispeed fiber setups, the device may not have
2497 * had a physical connection when the driver loaded.
2498 * If that's the case, the initial link configuration
2499 * couldn't get the MAC into 10G or 1G mode, so we'll
2500 * never have a link status change interrupt fire.
2501 * We need to try and force an autonegotiation
2502 * session, then bring up link.
2503 */
2504 hw->mac.ops.setup_sfp(hw);
2505 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2506 schedule_work(&adapter->multispeed_fiber_task);
2507 } else {
2508 /*
2509 * Direct Attach Cu and non-multispeed fiber modules
2510 * still need to be configured properly prior to
2511 * attempting link.
2512 */
2513 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2514 schedule_work(&adapter->sfp_config_module_task);
2515 }
2516}
2517
2518/**
2519 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2520 * @hw: pointer to private hardware struct
2521 *
2522 * Returns 0 on success, negative on failure
2523 **/
e8e26350 2524static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2525{
2526 u32 autoneg;
2527 bool link_up = false;
2528 u32 ret = IXGBE_ERR_LINK_SETUP;
2529
2530 if (hw->mac.ops.check_link)
2531 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2532
2533 if (ret)
2534 goto link_cfg_out;
2535
2536 if (hw->mac.ops.get_link_capabilities)
2537 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2538 &hw->mac.autoneg);
2539 if (ret)
2540 goto link_cfg_out;
2541
2542 if (hw->mac.ops.setup_link_speed)
2543 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
0ecc061d
PWJ		 2544link_cfg_out:
2545 return ret;
2546}
2547
e8e26350
PW		 2548#define IXGBE_MAX_RX_DESC_POLL 10
2549static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2550 int rxr)
2551{
2552 int j = adapter->rx_ring[rxr].reg_idx;
2553 int k;
2554
2555 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2556 if (IXGBE_READ_REG(&adapter->hw,
2557 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2558 break;
2559 else
2560 msleep(1);
2561 }
2562 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2563 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2564 "not set within the polling period\n", rxr);
2565 }
2566 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2567 (adapter->rx_ring[rxr].count - 1));
2568}
2569
9a799d71
AK		 2570static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2571{
2572 struct net_device *netdev = adapter->netdev;
9a799d71 2573 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2574 int i, j = 0;
e8e26350 2575 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2576 int err;
9a799d71 2577 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2578 u32 txdctl, rxdctl, mhadd;
e8e26350 2579 u32 dmatxctl;
021230d4 2580 u32 gpie;
9a799d71 2581
5eba3699
AV		 2582 ixgbe_get_hw_control(adapter);
2583
021230d4
AV		 2584 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2585 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2586 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2587 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2588 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2589 } else {
2590 /* MSI only */
021230d4 2591 gpie = 0;
9a799d71 2592 }
021230d4
AV		 2593 /* XXX: to interrupt immediately for EICS writes, enable this */
2594 /* gpie |= IXGBE_GPIE_EIMEN; */
2595 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2596 }
2597
021230d4
AV		 2598 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2599 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2600 * specifically only auto mask tx and rx interrupts */
2601 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2602 }
9a799d71 2603
0befdb3e
JB		 2604 /* Enable fan failure interrupt if media type is copper */
2605 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2606 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2607 gpie |= IXGBE_SDP1_GPIEN;
2608 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2609 }
2610
e8e26350
PW		 2611 if (hw->mac.type == ixgbe_mac_82599EB) {
2612 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2613 gpie |= IXGBE_SDP1_GPIEN;
2614 gpie |= IXGBE_SDP2_GPIEN;
2615 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2616 }
2617
63f39bd1
YZ		 2618#ifdef IXGBE_FCOE
2619 /* adjust max frame to be able to do baby jumbo for FCoE */
2620 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2621 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2622 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2623
2624#endif /* IXGBE_FCOE */
021230d4 2625 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2626 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2627 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2628 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2629
2630 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2631 }
2632
2633 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 2634 j = adapter->tx_ring[i].reg_idx;
2635 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2636 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2637 txdctl |= (8 << 16);
e8e26350
PW		 2638 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2639 }
2640
2641 if (hw->mac.type == ixgbe_mac_82599EB) {
2642 /* DMATXCTL.EN must be set after all Tx queue config is done */
2643 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2644 dmatxctl |= IXGBE_DMATXCTL_TE;
2645 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2646 }
2647 for (i = 0; i < adapter->num_tx_queues; i++) {
2648 j = adapter->tx_ring[i].reg_idx;
2649 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2650 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2651 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 2652 }
2653
e8e26350 2654 for (i = 0; i < num_rx_rings; i++) {
021230d4
AV		 2655 j = adapter->rx_ring[i].reg_idx;
2656 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2657 /* enable PTHRESH=32 descriptors (half the internal cache)
2658 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2659 * this also removes a pesky rx_no_buffer_count increment */
2660 rxdctl |= 0x0020;
9a799d71 2661 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2662 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2663 if (hw->mac.type == ixgbe_mac_82599EB)
2664 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2665 }
2666 /* enable all receives */
2667 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2668 if (hw->mac.type == ixgbe_mac_82598EB)
2669 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2670 else
2671 rxdctl |= IXGBE_RXCTRL_RXEN;
2672 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2673
2674 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2675 ixgbe_configure_msix(adapter);
2676 else
2677 ixgbe_configure_msi_and_legacy(adapter);
2678
2679 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2680 ixgbe_napi_enable_all(adapter);
2681
2682 /* clear any pending interrupts, may auto mask */
2683 IXGBE_READ_REG(hw, IXGBE_EICR);
2684
9a799d71
AK		 2685 ixgbe_irq_enable(adapter);
2686
bf069c97
DS		 2687 /*
2688 * If this adapter has a fan, check to see if we had a failure
2689 * before we enabled the interrupt.
2690 */
2691 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2692 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2693 if (esdp & IXGBE_ESDP_SDP1)
2694 DPRINTK(DRV, CRIT,
2695 "Fan has stopped, replace the adapter\n");
2696 }
2697
e8e26350
PW		 2698 /*
2699 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 2700 * arrived before interrupts were enabled but after probe. Such
2701 * devices wouldn't have their type identified yet. We need to
2702 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 2703 * If we're not hot-pluggable SFP+, we just need to configure link
2704 * and bring it up.
2705 */
19343de2
DS		 2706 if (hw->phy.type == ixgbe_phy_unknown) {
2707 err = hw->phy.ops.identify(hw);
2708 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 2709 /*
2710 * Take the device down and schedule the sfp tasklet
2711 * which will unregister_netdev and log it.
2712 */
19343de2 2713 ixgbe_down(adapter);
5da43c1a 2714 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 2715 return err;
2716 }
e8e26350
PW		 2717 }
2718
2719 if (ixgbe_is_sfp(hw)) {
2720 ixgbe_sfp_link_config(adapter);
2721 } else {
2722 err = ixgbe_non_sfp_link_config(hw);
2723 if (err)
2724 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2725 }
0ecc061d 2726
c4cf55e5
PWJ		 2727 for (i = 0; i < adapter->num_tx_queues; i++)
2728 set_bit(__IXGBE_FDIR_INIT_DONE,
2729 &(adapter->tx_ring[i].reinit_state));
2730
1da100bb
PWJ		 2731 /* enable transmits */
2732 netif_tx_start_all_queues(netdev);
2733
9a799d71
AK		 2734 /* bring the link up in the watchdog, this could race with our first
2735 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 2736 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2737 adapter->link_check_timeout = jiffies;
9a799d71
AK		 2738 mod_timer(&adapter->watchdog_timer, jiffies);
2739 return 0;
2740}
2741
d4f80882
AV		 2742void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2743{
2744 WARN_ON(in_interrupt());
2745 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2746 msleep(1);
2747 ixgbe_down(adapter);
2748 ixgbe_up(adapter);
2749 clear_bit(__IXGBE_RESETTING, &adapter->state);
2750}
2751
9a799d71
AK		 2752int ixgbe_up(struct ixgbe_adapter *adapter)
2753{
2754 /* hardware has been reset, we need to reload some things */
2755 ixgbe_configure(adapter);
2756
2757 return ixgbe_up_complete(adapter);
2758}
2759
2760void ixgbe_reset(struct ixgbe_adapter *adapter)
2761{
c44ade9e 2762 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 2763 int err;
2764
2765 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 2766 switch (err) {
2767 case 0:
2768 case IXGBE_ERR_SFP_NOT_PRESENT:
2769 break;
2770 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2771 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2772 break;
794caeb2
PWJ		 2773 case IXGBE_ERR_EEPROM_VERSION:
2774 /* We are running on a pre-production device, log a warning */
2775 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2776 "adapter/LOM. Please be aware there may be issues "
2777 "associated with your hardware. If you are "
2778 "experiencing problems please contact your Intel or "
2779 "hardware representative who provided you with this "
2780 "hardware.\n");
2781 break;
da4dd0f7
PWJ		 2782 default:
2783 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2784 }
9a799d71
AK		 2785
2786 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2787 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2788}
2789
9a799d71
AK		 2790/**
2791 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2792 * @adapter: board private structure
2793 * @rx_ring: ring to free buffers from
2794 **/
2795static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2796 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2797{
2798 struct pci_dev *pdev = adapter->pdev;
2799 unsigned long size;
2800 unsigned int i;
2801
2802 /* Free all the Rx ring sk_buffs */
2803
2804 for (i = 0; i < rx_ring->count; i++) {
2805 struct ixgbe_rx_buffer *rx_buffer_info;
2806
2807 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2808 if (rx_buffer_info->dma) {
2809 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2810 rx_ring->rx_buf_len,
2811 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2812 rx_buffer_info->dma = 0;
2813 }
2814 if (rx_buffer_info->skb) {
f8212f97 2815 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 2816 rx_buffer_info->skb = NULL;
f8212f97
AD		 2817 do {
2818 struct sk_buff *this = skb;
2819 skb = skb->prev;
2820 dev_kfree_skb(this);
2821 } while (skb);
9a799d71
AK		 2822 }
2823 if (!rx_buffer_info->page)
2824 continue;
4f57ca6e
JB		 2825 if (rx_buffer_info->page_dma) {
2826 pci_unmap_page(pdev, rx_buffer_info->page_dma,
2827 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2828 rx_buffer_info->page_dma = 0;
2829 }
9a799d71
AK		 2830 put_page(rx_buffer_info->page);
2831 rx_buffer_info->page = NULL;
762f4c57 2832 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2833 }
2834
2835 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2836 memset(rx_ring->rx_buffer_info, 0, size);
2837
2838 /* Zero out the descriptor ring */
2839 memset(rx_ring->desc, 0, rx_ring->size);
2840
2841 rx_ring->next_to_clean = 0;
2842 rx_ring->next_to_use = 0;
2843
9891ca7c
JB		 2844 if (rx_ring->head)
2845 writel(0, adapter->hw.hw_addr + rx_ring->head);
2846 if (rx_ring->tail)
2847 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 2848}
2849
2850/**
2851 * ixgbe_clean_tx_ring - Free Tx Buffers
2852 * @adapter: board private structure
2853 * @tx_ring: ring to be cleaned
2854 **/
2855static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2856 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2857{
2858 struct ixgbe_tx_buffer *tx_buffer_info;
2859 unsigned long size;
2860 unsigned int i;
2861
2862 /* Free all the Tx ring sk_buffs */
2863
2864 for (i = 0; i < tx_ring->count; i++) {
2865 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2866 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2867 }
2868
2869 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2870 memset(tx_ring->tx_buffer_info, 0, size);
2871
2872 /* Zero out the descriptor ring */
2873 memset(tx_ring->desc, 0, tx_ring->size);
2874
2875 tx_ring->next_to_use = 0;
2876 tx_ring->next_to_clean = 0;
2877
9891ca7c
JB		 2878 if (tx_ring->head)
2879 writel(0, adapter->hw.hw_addr + tx_ring->head);
2880 if (tx_ring->tail)
2881 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 2882}
2883
2884/**
021230d4 2885 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2886 * @adapter: board private structure
2887 **/
021230d4 2888static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2889{
2890 int i;
2891
021230d4
AV		 2892 for (i = 0; i < adapter->num_rx_queues; i++)
2893 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2894}
2895
2896/**
021230d4 2897 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2898 * @adapter: board private structure
2899 **/
021230d4 2900static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2901{
2902 int i;
2903
021230d4
AV		 2904 for (i = 0; i < adapter->num_tx_queues; i++)
2905 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2906}
2907
2908void ixgbe_down(struct ixgbe_adapter *adapter)
2909{
2910 struct net_device *netdev = adapter->netdev;
7f821875 2911 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2912 u32 rxctrl;
7f821875
JB		 2913 u32 txdctl;
2914 int i, j;
9a799d71
AK		 2915
2916 /* signal that we are down to the interrupt handler */
2917 set_bit(__IXGBE_DOWN, &adapter->state);
2918
2919 /* disable receives */
7f821875
JB		 2920 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2921 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 2922
2923 netif_tx_disable(netdev);
2924
7f821875 2925 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 2926 msleep(10);
2927
7f821875
JB		 2928 netif_tx_stop_all_queues(netdev);
2929
9a799d71
AK		 2930 ixgbe_irq_disable(adapter);
2931
021230d4 2932 ixgbe_napi_disable_all(adapter);
7f821875 2933
9a799d71 2934 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 2935 cancel_work_sync(&adapter->watchdog_task);
9a799d71 2936
c4cf55e5
PWJ		 2937 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2938 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2939 cancel_work_sync(&adapter->fdir_reinit_task);
2940
7f821875
JB		 2941 /* disable transmits in the hardware now that interrupts are off */
2942 for (i = 0; i < adapter->num_tx_queues; i++) {
2943 j = adapter->tx_ring[i].reg_idx;
2944 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2945 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2946 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2947 }
88512539
PW		 2948 /* Disable the Tx DMA engine on 82599 */
2949 if (hw->mac.type == ixgbe_mac_82599EB)
2950 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2951 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2952 ~IXGBE_DMATXCTL_TE));
7f821875 2953
9a799d71 2954 netif_carrier_off(netdev);
9a799d71 2955
6f4a0e45
PL		 2956 if (!pci_channel_offline(adapter->pdev))
2957 ixgbe_reset(adapter);
9a799d71
AK		 2958 ixgbe_clean_all_tx_rings(adapter);
2959 ixgbe_clean_all_rx_rings(adapter);
2960
5dd2d332 2961#ifdef CONFIG_IXGBE_DCA
96b0e0f6 2962 /* since we reset the hardware DCA settings were cleared */
e35ec126 2963 ixgbe_setup_dca(adapter);
96b0e0f6 2964#endif
9a799d71
AK		 2965}
2966
9a799d71 2967/**
021230d4
AV		 2968 * ixgbe_poll - NAPI Rx polling callback
2969 * @napi: structure for representing this polling device
2970 * @budget: how many packets driver is allowed to clean
2971 *
2972 * This function is used for legacy and MSI, NAPI mode
9a799d71 2973 **/
021230d4 2974static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2975{
9a1a69ad
JB		 2976 struct ixgbe_q_vector *q_vector =
2977 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2978 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 2979 int tx_clean_complete, work_done = 0;
9a799d71 2980
5dd2d332 2981#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 2982 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2983 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2984 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2985 }
2986#endif
2987
fe49f04a 2988 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
78b6f4ce 2989 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
9a799d71 2990
9a1a69ad 2991 if (!tx_clean_complete)
d2c7ddd6
DM		 2992 work_done = budget;
2993
53e52c72
DM		 2994 /* If budget not fully consumed, exit the polling mode */
2995 if (work_done < budget) {
288379f0 2996 napi_complete(napi);
509ee935 2997 if (adapter->itr_setting & 1)
f494e8fa 2998 ixgbe_set_itr(adapter);
d4f80882 2999 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 3000 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 3001 }
9a799d71
AK		 3002 return work_done;
3003}
3004
3005/**
3006 * ixgbe_tx_timeout - Respond to a Tx Hang
3007 * @netdev: network interface device structure
3008 **/
3009static void ixgbe_tx_timeout(struct net_device *netdev)
3010{
3011 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3012
3013 /* Do the reset outside of interrupt context */
3014 schedule_work(&adapter->reset_task);
3015}
3016
3017static void ixgbe_reset_task(struct work_struct *work)
3018{
3019 struct ixgbe_adapter *adapter;
3020 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3021
2f90b865
AD		 3022 /* If we're already down or resetting, just bail */
3023 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3024 test_bit(__IXGBE_RESETTING, &adapter->state))
3025 return;
3026
9a799d71
AK		 3027 adapter->tx_timeout_count++;
3028
d4f80882 3029 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3030}
3031
bc97114d
PWJ		 3032#ifdef CONFIG_IXGBE_DCB
3033static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3034{
bc97114d 3035 bool ret = false;
0cefafad 3036 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3037
0cefafad
JB		 3038 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3039 return ret;
3040
3041 f->mask = 0x7 << 3;
3042 adapter->num_rx_queues = f->indices;
3043 adapter->num_tx_queues = f->indices;
3044 ret = true;
2f90b865 3045
bc97114d
PWJ		 3046 return ret;
3047}
3048#endif
3049
4df10466
JB		 3050/**
3051 * ixgbe_set_rss_queues: Allocate queues for RSS
3052 * @adapter: board private structure to initialize
3053 *
3054 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3055 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3056 *
3057 **/
bc97114d
PWJ		 3058static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3059{
3060 bool ret = false;
0cefafad 3061 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3062
3063 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3064 f->mask = 0xF;
3065 adapter->num_rx_queues = f->indices;
3066 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3067 ret = true;
3068 } else {
bc97114d 3069 ret = false;
b9804972
JB		 3070 }
3071
bc97114d
PWJ		 3072 return ret;
3073}
3074
c4cf55e5
PWJ		 3075/**
3076 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3077 * @adapter: board private structure to initialize
3078 *
3079 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3080 * to the original CPU that initiated the Tx session. This runs in addition
3081 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3082 * Rx load across CPUs using RSS.
3083 *
3084 **/
3085static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3086{
3087 bool ret = false;
3088 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3089
3090 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3091 f_fdir->mask = 0;
3092
3093 /* Flow Director must have RSS enabled */
3094 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3095 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3096 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3097 adapter->num_tx_queues = f_fdir->indices;
3098 adapter->num_rx_queues = f_fdir->indices;
3099 ret = true;
3100 } else {
3101 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3102 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3103 }
3104 return ret;
3105}
3106
0331a832
YZ		 3107#ifdef IXGBE_FCOE
3108/**
3109 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3110 * @adapter: board private structure to initialize
3111 *
3112 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3113 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3114 * rx queues out of the max number of rx queues, instead, it is used as the
3115 * index of the first rx queue used by FCoE.
3116 *
3117 **/
3118static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3119{
3120 bool ret = false;
3121 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3122
3123 f->indices = min((int)num_online_cpus(), f->indices);
3124 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3125#ifdef CONFIG_IXGBE_DCB
3126 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3127 DPRINTK(PROBE, INFO, "FCOE enabled with DCB \n");
3128 ixgbe_set_dcb_queues(adapter);
3129 }
3130#endif
3131 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3132 DPRINTK(PROBE, INFO, "FCOE enabled with RSS \n");
3133 ixgbe_set_rss_queues(adapter);
3134 }
3135 /* adding FCoE rx rings to the end */
3136 f->mask = adapter->num_rx_queues;
3137 adapter->num_rx_queues += f->indices;
3138 if (adapter->num_tx_queues == 0)
3139 adapter->num_tx_queues = f->indices;
3140
3141 ret = true;
3142 }
3143
3144 return ret;
3145}
3146
3147#endif /* IXGBE_FCOE */
4df10466
JB		 3148/*
3149 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3150 * @adapter: board private structure to initialize
3151 *
3152 * This is the top level queue allocation routine. The order here is very
3153 * important, starting with the "most" number of features turned on at once,
3154 * and ending with the smallest set of features. This way large combinations
3155 * can be allocated if they're turned on, and smaller combinations are the
3156 * fallthrough conditions.
3157 *
3158 **/
bc97114d
PWJ		 3159static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3160{
0331a832
YZ		 3161#ifdef IXGBE_FCOE
3162 if (ixgbe_set_fcoe_queues(adapter))
3163 goto done;
3164
3165#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3166#ifdef CONFIG_IXGBE_DCB
3167 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 3168 goto done;
bc97114d
PWJ		 3169
3170#endif
c4cf55e5
PWJ		 3171 if (ixgbe_set_fdir_queues(adapter))
3172 goto done;
3173
bc97114d 3174 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 3175 goto done;
3176
3177 /* fallback to base case */
3178 adapter->num_rx_queues = 1;
3179 adapter->num_tx_queues = 1;
3180
3181done:
3182 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3183 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 3184}
3185
021230d4 3186static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 3187 int vectors)
021230d4
AV		 3188{
3189 int err, vector_threshold;
3190
3191 /* We'll want at least 3 (vector_threshold):
3192 * 1) TxQ[0] Cleanup
3193 * 2) RxQ[0] Cleanup
3194 * 3) Other (Link Status Change, etc.)
3195 * 4) TCP Timer (optional)
3196 */
3197 vector_threshold = MIN_MSIX_COUNT;
3198
3199 /* The more we get, the more we will assign to Tx/Rx Cleanup
3200 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3201 * Right now, we simply care about how many we'll get; we'll
3202 * set them up later while requesting irq's.
3203 */
3204 while (vectors >= vector_threshold) {
3205 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 3206 vectors);
021230d4
AV		 3207 if (!err) /* Success in acquiring all requested vectors. */
3208 break;
3209 else if (err < 0)
3210 vectors = 0; /* Nasty failure, quit now */
3211 else /* err == number of vectors we should try again with */
3212 vectors = err;
3213 }
3214
3215 if (vectors < vector_threshold) {
3216 /* Can't allocate enough MSI-X interrupts? Oh well.
3217 * This just means we'll go with either a single MSI
3218 * vector or fall back to legacy interrupts.
3219 */
3220 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3221 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3222 kfree(adapter->msix_entries);
3223 adapter->msix_entries = NULL;
021230d4
AV		 3224 } else {
3225 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 3226 /*
3227 * Adjust for only the vectors we'll use, which is minimum
3228 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3229 * vectors we were allocated.
3230 */
3231 adapter->num_msix_vectors = min(vectors,
3232 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 3233 }
3234}
3235
021230d4 3236/**
bc97114d 3237 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 3238 * @adapter: board private structure to initialize
3239 *
bc97114d
PWJ		 3240 * Cache the descriptor ring offsets for RSS to the assigned rings.
3241 *
021230d4 3242 **/
bc97114d 3243static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 3244{
bc97114d
PWJ		 3245 int i;
3246 bool ret = false;
3247
3248 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3249 for (i = 0; i < adapter->num_rx_queues; i++)
3250 adapter->rx_ring[i].reg_idx = i;
3251 for (i = 0; i < adapter->num_tx_queues; i++)
3252 adapter->tx_ring[i].reg_idx = i;
3253 ret = true;
3254 } else {
3255 ret = false;
3256 }
3257
3258 return ret;
3259}
3260
3261#ifdef CONFIG_IXGBE_DCB
3262/**
3263 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3264 * @adapter: board private structure to initialize
3265 *
3266 * Cache the descriptor ring offsets for DCB to the assigned rings.
3267 *
3268 **/
3269static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3270{
3271 int i;
3272 bool ret = false;
3273 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3274
3275 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3276 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 3277 /* the number of queues is assumed to be symmetric */
3278 for (i = 0; i < dcb_i; i++) {
3279 adapter->rx_ring[i].reg_idx = i << 3;
3280 adapter->tx_ring[i].reg_idx = i << 2;
3281 }
bc97114d 3282 ret = true;
e8e26350 3283 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 3284 if (dcb_i == 8) {
3285 /*
3286 * Tx TC0 starts at: descriptor queue 0
3287 * Tx TC1 starts at: descriptor queue 32
3288 * Tx TC2 starts at: descriptor queue 64
3289 * Tx TC3 starts at: descriptor queue 80
3290 * Tx TC4 starts at: descriptor queue 96
3291 * Tx TC5 starts at: descriptor queue 104
3292 * Tx TC6 starts at: descriptor queue 112
3293 * Tx TC7 starts at: descriptor queue 120
3294 *
3295 * Rx TC0-TC7 are offset by 16 queues each
3296 */
3297 for (i = 0; i < 3; i++) {
3298 adapter->tx_ring[i].reg_idx = i << 5;
3299 adapter->rx_ring[i].reg_idx = i << 4;
3300 }
3301 for ( ; i < 5; i++) {
3302 adapter->tx_ring[i].reg_idx =
3303 ((i + 2) << 4);
3304 adapter->rx_ring[i].reg_idx = i << 4;
3305 }
3306 for ( ; i < dcb_i; i++) {
3307 adapter->tx_ring[i].reg_idx =
3308 ((i + 8) << 3);
3309 adapter->rx_ring[i].reg_idx = i << 4;
3310 }
3311
3312 ret = true;
3313 } else if (dcb_i == 4) {
3314 /*
3315 * Tx TC0 starts at: descriptor queue 0
3316 * Tx TC1 starts at: descriptor queue 64
3317 * Tx TC2 starts at: descriptor queue 96
3318 * Tx TC3 starts at: descriptor queue 112
3319 *
3320 * Rx TC0-TC3 are offset by 32 queues each
3321 */
3322 adapter->tx_ring[0].reg_idx = 0;
3323 adapter->tx_ring[1].reg_idx = 64;
3324 adapter->tx_ring[2].reg_idx = 96;
3325 adapter->tx_ring[3].reg_idx = 112;
3326 for (i = 0 ; i < dcb_i; i++)
3327 adapter->rx_ring[i].reg_idx = i << 5;
3328
3329 ret = true;
3330 } else {
3331 ret = false;
e8e26350 3332 }
bc97114d
PWJ		 3333 } else {
3334 ret = false;
021230d4 3335 }
bc97114d
PWJ		 3336 } else {
3337 ret = false;
021230d4 3338 }
bc97114d
PWJ		 3339
3340 return ret;
3341}
3342#endif
3343
c4cf55e5
PWJ		 3344/**
3345 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3346 * @adapter: board private structure to initialize
3347 *
3348 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3349 *
3350 **/
3351static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3352{
3353 int i;
3354 bool ret = false;
3355
3356 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3357 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3358 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3359 for (i = 0; i < adapter->num_rx_queues; i++)
3360 adapter->rx_ring[i].reg_idx = i;
3361 for (i = 0; i < adapter->num_tx_queues; i++)
3362 adapter->tx_ring[i].reg_idx = i;
3363 ret = true;
3364 }
3365
3366 return ret;
3367}
3368
0331a832
YZ		 3369#ifdef IXGBE_FCOE
3370/**
3371 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3372 * @adapter: board private structure to initialize
3373 *
3374 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3375 *
3376 */
3377static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3378{
3379 int i, fcoe_i = 0;
3380 bool ret = false;
3381 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3382
3383 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3384#ifdef CONFIG_IXGBE_DCB
3385 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3386 ixgbe_cache_ring_dcb(adapter);
3387 fcoe_i = adapter->rx_ring[0].reg_idx + 1;
3388 }
3389#endif /* CONFIG_IXGBE_DCB */
3390 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3391 ixgbe_cache_ring_rss(adapter);
3392 fcoe_i = f->mask;
3393 }
3394 for (i = 0; i < f->indices; i++, fcoe_i++)
3395 adapter->rx_ring[f->mask + i].reg_idx = fcoe_i;
3396 ret = true;
3397 }
3398 return ret;
3399}
3400
3401#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3402/**
3403 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3404 * @adapter: board private structure to initialize
3405 *
3406 * Once we know the feature-set enabled for the device, we'll cache
3407 * the register offset the descriptor ring is assigned to.
3408 *
3409 * Note, the order the various feature calls is important. It must start with
3410 * the "most" features enabled at the same time, then trickle down to the
3411 * least amount of features turned on at once.
3412 **/
3413static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3414{
3415 /* start with default case */
3416 adapter->rx_ring[0].reg_idx = 0;
3417 adapter->tx_ring[0].reg_idx = 0;
3418
0331a832
YZ		 3419#ifdef IXGBE_FCOE
3420 if (ixgbe_cache_ring_fcoe(adapter))
3421 return;
3422
3423#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3424#ifdef CONFIG_IXGBE_DCB
3425 if (ixgbe_cache_ring_dcb(adapter))
3426 return;
3427
3428#endif
c4cf55e5
PWJ		 3429 if (ixgbe_cache_ring_fdir(adapter))
3430 return;
3431
bc97114d
PWJ		 3432 if (ixgbe_cache_ring_rss(adapter))
3433 return;
021230d4
AV		 3434}
3435
9a799d71
AK		 3436/**
3437 * ixgbe_alloc_queues - Allocate memory for all rings
3438 * @adapter: board private structure to initialize
3439 *
3440 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 3441 * number of queues at compile-time. The polling_netdev array is
3442 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 3443 **/
2f90b865 3444static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 3445{
3446 int i;
3447
3448 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 3449 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 3450 if (!adapter->tx_ring)
021230d4 3451 goto err_tx_ring_allocation;
9a799d71
AK		 3452
3453 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 3454 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 3455 if (!adapter->rx_ring)
3456 goto err_rx_ring_allocation;
9a799d71 3457
021230d4 3458 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 3459 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 3460 adapter->tx_ring[i].queue_index = i;
3461 }
b9804972 3462
9a799d71 3463 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 3464 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 3465 adapter->rx_ring[i].queue_index = i;
3466 }
3467
3468 ixgbe_cache_ring_register(adapter);
3469
3470 return 0;
3471
3472err_rx_ring_allocation:
3473 kfree(adapter->tx_ring);
3474err_tx_ring_allocation:
3475 return -ENOMEM;
3476}
3477
3478/**
3479 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3480 * @adapter: board private structure to initialize
3481 *
3482 * Attempt to configure the interrupts using the best available
3483 * capabilities of the hardware and the kernel.
3484 **/
feea6a57 3485static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 3486{
8be0e467 3487 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 3488 int err = 0;
3489 int vector, v_budget;
3490
3491 /*
3492 * It's easy to be greedy for MSI-X vectors, but it really
3493 * doesn't do us much good if we have a lot more vectors
3494 * than CPU's. So let's be conservative and only ask for
3495 * (roughly) twice the number of vectors as there are CPU's.
3496 */
3497 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
b4617240 3498 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
021230d4
AV		 3499
3500 /*
3501 * At the same time, hardware can only support a maximum of
8be0e467
PW		 3502 * hw.mac->max_msix_vectors vectors. With features
3503 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3504 * descriptor queues supported by our device. Thus, we cap it off in
3505 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3506 */
8be0e467 3507 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3508
3509 /* A failure in MSI-X entry allocation isn't fatal, but it does
3510 * mean we disable MSI-X capabilities of the adapter. */
3511 adapter->msix_entries = kcalloc(v_budget,
b4617240 3512 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 3513 if (adapter->msix_entries) {
3514 for (vector = 0; vector < v_budget; vector++)
3515 adapter->msix_entries[vector].entry = vector;
021230d4 3516
7a921c93 3517 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 3518
7a921c93
AD		 3519 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3520 goto out;
3521 }
021230d4 3522
7a921c93
AD		 3523 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3524 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 3525 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3526 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3527 adapter->atr_sample_rate = 0;
7a921c93 3528 ixgbe_set_num_queues(adapter);
021230d4 3529
021230d4
AV		 3530 err = pci_enable_msi(adapter->pdev);
3531 if (!err) {
3532 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3533 } else {
3534 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 3535 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 3536 /* reset err */
3537 err = 0;
3538 }
3539
3540out:
021230d4
AV		 3541 return err;
3542}
3543
7a921c93
AD		 3544/**
3545 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3546 * @adapter: board private structure to initialize
3547 *
3548 * We allocate one q_vector per queue interrupt. If allocation fails we
3549 * return -ENOMEM.
3550 **/
3551static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3552{
3553 int q_idx, num_q_vectors;
3554 struct ixgbe_q_vector *q_vector;
3555 int napi_vectors;
3556 int (*poll)(struct napi_struct *, int);
3557
3558 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3559 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3560 napi_vectors = adapter->num_rx_queues;
91281fd3 3561 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 3562 } else {
3563 num_q_vectors = 1;
3564 napi_vectors = 1;
3565 poll = &ixgbe_poll;
3566 }
3567
3568 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3569 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3570 if (!q_vector)
3571 goto err_out;
3572 q_vector->adapter = adapter;
7a921c93 3573 q_vector->eitr = adapter->eitr_param;
fe49f04a 3574 q_vector->v_idx = q_idx;
91281fd3 3575 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 3576 adapter->q_vector[q_idx] = q_vector;
3577 }
3578
3579 return 0;
3580
3581err_out:
3582 while (q_idx) {
3583 q_idx--;
3584 q_vector = adapter->q_vector[q_idx];
3585 netif_napi_del(&q_vector->napi);
3586 kfree(q_vector);
3587 adapter->q_vector[q_idx] = NULL;
3588 }
3589 return -ENOMEM;
3590}
3591
3592/**
3593 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3594 * @adapter: board private structure to initialize
3595 *
3596 * This function frees the memory allocated to the q_vectors. In addition if
3597 * NAPI is enabled it will delete any references to the NAPI struct prior
3598 * to freeing the q_vector.
3599 **/
3600static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3601{
3602 int q_idx, num_q_vectors;
7a921c93 3603
91281fd3 3604 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 3605 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 3606 else
7a921c93 3607 num_q_vectors = 1;
7a921c93
AD		 3608
3609 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3610 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 3611 adapter->q_vector[q_idx] = NULL;
91281fd3 3612 netif_napi_del(&q_vector->napi);
7a921c93
AD		 3613 kfree(q_vector);
3614 }
3615}
3616
2f90b865 3617void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 3618{
3619 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3620 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3621 pci_disable_msix(adapter->pdev);
3622 kfree(adapter->msix_entries);
3623 adapter->msix_entries = NULL;
3624 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3625 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3626 pci_disable_msi(adapter->pdev);
3627 }
3628 return;
3629}
3630
3631/**
3632 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3633 * @adapter: board private structure to initialize
3634 *
3635 * We determine which interrupt scheme to use based on...
3636 * - Kernel support (MSI, MSI-X)
3637 * - which can be user-defined (via MODULE_PARAM)
3638 * - Hardware queue count (num_*_queues)
3639 * - defined by miscellaneous hardware support/features (RSS, etc.)
3640 **/
2f90b865 3641int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 3642{
3643 int err;
3644
3645 /* Number of supported queues */
3646 ixgbe_set_num_queues(adapter);
3647
021230d4
AV		 3648 err = ixgbe_set_interrupt_capability(adapter);
3649 if (err) {
3650 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3651 goto err_set_interrupt;
9a799d71
AK		 3652 }
3653
7a921c93
AD		 3654 err = ixgbe_alloc_q_vectors(adapter);
3655 if (err) {
3656 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3657 "vectors\n");
3658 goto err_alloc_q_vectors;
3659 }
3660
3661 err = ixgbe_alloc_queues(adapter);
3662 if (err) {
3663 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3664 goto err_alloc_queues;
3665 }
3666
021230d4 3667 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 3668 "Tx Queue count = %u\n",
3669 (adapter->num_rx_queues > 1) ? "Enabled" :
3670 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 3671
3672 set_bit(__IXGBE_DOWN, &adapter->state);
3673
9a799d71 3674 return 0;
021230d4 3675
7a921c93
AD		 3676err_alloc_queues:
3677 ixgbe_free_q_vectors(adapter);
3678err_alloc_q_vectors:
3679 ixgbe_reset_interrupt_capability(adapter);
021230d4 3680err_set_interrupt:
7a921c93
AD		 3681 return err;
3682}
3683
3684/**
3685 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3686 * @adapter: board private structure to clear interrupt scheme on
3687 *
3688 * We go through and clear interrupt specific resources and reset the structure
3689 * to pre-load conditions
3690 **/
3691void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3692{
021230d4
AV		 3693 kfree(adapter->tx_ring);
3694 kfree(adapter->rx_ring);
7a921c93
AD		 3695 adapter->tx_ring = NULL;
3696 adapter->rx_ring = NULL;
3697
3698 ixgbe_free_q_vectors(adapter);
3699 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 3700}
3701
c4900be0
DS		 3702/**
3703 * ixgbe_sfp_timer - worker thread to find a missing module
3704 * @data: pointer to our adapter struct
3705 **/
3706static void ixgbe_sfp_timer(unsigned long data)
3707{
3708 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3709
4df10466
JB		 3710 /*
3711 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 3712 * delays that sfp+ detection requires
3713 */
3714 schedule_work(&adapter->sfp_task);
3715}
3716
3717/**
3718 * ixgbe_sfp_task - worker thread to find a missing module
3719 * @work: pointer to work_struct containing our data
3720 **/
3721static void ixgbe_sfp_task(struct work_struct *work)
3722{
3723 struct ixgbe_adapter *adapter = container_of(work,
3724 struct ixgbe_adapter,
3725 sfp_task);
3726 struct ixgbe_hw *hw = &adapter->hw;
3727
3728 if ((hw->phy.type == ixgbe_phy_nl) &&
3729 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3730 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 3731 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 3732 goto reschedule;
3733 ret = hw->phy.ops.reset(hw);
3734 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 3735 dev_err(&adapter->pdev->dev, "failed to initialize "
3736 "because an unsupported SFP+ module type "
3737 "was detected.\n"
3738 "Reload the driver after installing a "
3739 "supported module.\n");
c4900be0
DS		 3740 unregister_netdev(adapter->netdev);
3741 } else {
3742 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3743 hw->phy.sfp_type);
3744 }
3745 /* don't need this routine any more */
3746 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3747 }
3748 return;
3749reschedule:
3750 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3751 mod_timer(&adapter->sfp_timer,
3752 round_jiffies(jiffies + (2 * HZ)));
3753}
3754
9a799d71
AK		 3755/**
3756 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3757 * @adapter: board private structure to initialize
3758 *
3759 * ixgbe_sw_init initializes the Adapter private data structure.
3760 * Fields are initialized based on PCI device information and
3761 * OS network device settings (MTU size).
3762 **/
3763static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3764{
3765 struct ixgbe_hw *hw = &adapter->hw;
3766 struct pci_dev *pdev = adapter->pdev;
021230d4 3767 unsigned int rss;
7a6b6f51 3768#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3769 int j;
3770 struct tc_configuration *tc;
3771#endif
021230d4 3772
c44ade9e
JB		 3773 /* PCI config space info */
3774
3775 hw->vendor_id = pdev->vendor;
3776 hw->device_id = pdev->device;
3777 hw->revision_id = pdev->revision;
3778 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3779 hw->subsystem_device_id = pdev->subsystem_device;
3780
021230d4
AV		 3781 /* Set capability flags */
3782 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3783 adapter->ring_feature[RING_F_RSS].indices = rss;
3784 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 3785 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 3786 if (hw->mac.type == ixgbe_mac_82598EB) {
3787 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3788 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 3789 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 3790 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 3791 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
df647b5c
PWJ		 3792 adapter->flags |= IXGBE_FLAG2_RSC_CAPABLE;
3793 adapter->flags |= IXGBE_FLAG2_RSC_ENABLED;
c4cf55e5
PWJ		 3794 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3795 adapter->ring_feature[RING_F_FDIR].indices =
3796 IXGBE_MAX_FDIR_INDICES;
3797 adapter->atr_sample_rate = 20;
3798 adapter->fdir_pballoc = 0;
eacd73f7
YZ		 3799#ifdef IXGBE_FCOE
3800 adapter->flags |= IXGBE_FLAG_FCOE_ENABLED;
0331a832 3801 adapter->ring_feature[RING_F_FCOE].indices = IXGBE_FCRETA_SIZE;
eacd73f7 3802#endif /* IXGBE_FCOE */
f8212f97 3803 }
2f90b865 3804
7a6b6f51 3805#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3806 /* Configure DCB traffic classes */
3807 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3808 tc = &adapter->dcb_cfg.tc_config[j];
3809 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3810 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3811 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3812 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3813 tc->dcb_pfc = pfc_disabled;
3814 }
3815 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3816 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3817 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 3818 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 3819 adapter->dcb_cfg.round_robin_enable = false;
3820 adapter->dcb_set_bitmap = 0x00;
3821 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3822 adapter->ring_feature[RING_F_DCB].indices);
3823
3824#endif
9a799d71
AK		 3825
3826 /* default flow control settings */
cd7664f6 3827 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 3828 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 3829#ifdef CONFIG_DCB
3830 adapter->last_lfc_mode = hw->fc.current_mode;
3831#endif
2b9ade93
JB		 3832 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3833 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3834 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3835 hw->fc.send_xon = true;
71fd570b 3836 hw->fc.disable_fc_autoneg = false;
9a799d71 3837
30efa5a3
JB		 3838 /* enable itr by default in dynamic mode */
3839 adapter->itr_setting = 1;
3840 adapter->eitr_param = 20000;
3841
3842 /* set defaults for eitr in MegaBytes */
3843 adapter->eitr_low = 10;
3844 adapter->eitr_high = 20;
3845
3846 /* set default ring sizes */
3847 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3848 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3849
9a799d71 3850 /* initialize eeprom parameters */
c44ade9e 3851 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 3852 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3853 return -EIO;
3854 }
3855
021230d4 3856 /* enable rx csum by default */
9a799d71
AK		 3857 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3858
9a799d71
AK		 3859 set_bit(__IXGBE_DOWN, &adapter->state);
3860
3861 return 0;
3862}
3863
3864/**
3865 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3866 * @adapter: board private structure
3a581073 3867 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3868 *
3869 * Return 0 on success, negative on failure
3870 **/
3871int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 3872 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3873{
3874 struct pci_dev *pdev = adapter->pdev;
3875 int size;
3876
3a581073
JB		 3877 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3878 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 3879 if (!tx_ring->tx_buffer_info)
3880 goto err;
3a581073 3881 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 3882
3883 /* round up to nearest 4K */
12207e49 3884 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 3885 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 3886
3a581073
JB		 3887 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3888 &tx_ring->dma);
e01c31a5
JB		 3889 if (!tx_ring->desc)
3890 goto err;
9a799d71 3891
3a581073
JB		 3892 tx_ring->next_to_use = 0;
3893 tx_ring->next_to_clean = 0;
3894 tx_ring->work_limit = tx_ring->count;
9a799d71 3895 return 0;
e01c31a5
JB		 3896
3897err:
3898 vfree(tx_ring->tx_buffer_info);
3899 tx_ring->tx_buffer_info = NULL;
3900 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3901 "descriptor ring\n");
3902 return -ENOMEM;
9a799d71
AK		 3903}
3904
69888674
AD		 3905/**
3906 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3907 * @adapter: board private structure
3908 *
3909 * If this function returns with an error, then it's possible one or
3910 * more of the rings is populated (while the rest are not). It is the
3911 * callers duty to clean those orphaned rings.
3912 *
3913 * Return 0 on success, negative on failure
3914 **/
3915static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3916{
3917 int i, err = 0;
3918
3919 for (i = 0; i < adapter->num_tx_queues; i++) {
3920 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3921 if (!err)
3922 continue;
3923 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3924 break;
3925 }
3926
3927 return err;
3928}
3929
9a799d71
AK		 3930/**
3931 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3932 * @adapter: board private structure
3a581073 3933 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3934 *
3935 * Returns 0 on success, negative on failure
3936 **/
3937int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 3938 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3939{
3940 struct pci_dev *pdev = adapter->pdev;
021230d4 3941 int size;
9a799d71 3942
3a581073
JB		 3943 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3944 rx_ring->rx_buffer_info = vmalloc(size);
3945 if (!rx_ring->rx_buffer_info) {
9a799d71 3946 DPRINTK(PROBE, ERR,
b4617240 3947 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 3948 goto alloc_failed;
9a799d71 3949 }
3a581073 3950 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 3951
9a799d71 3952 /* Round up to nearest 4K */
3a581073
JB		 3953 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3954 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 3955
3a581073 3956 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 3957
3a581073 3958 if (!rx_ring->desc) {
9a799d71 3959 DPRINTK(PROBE, ERR,
b4617240 3960 "Memory allocation failed for the rx desc ring\n");
3a581073 3961 vfree(rx_ring->rx_buffer_info);
177db6ff 3962 goto alloc_failed;
9a799d71
AK		 3963 }
3964
3a581073
JB		 3965 rx_ring->next_to_clean = 0;
3966 rx_ring->next_to_use = 0;
9a799d71
AK		 3967
3968 return 0;
177db6ff
MC		 3969
3970alloc_failed:
177db6ff 3971 return -ENOMEM;
9a799d71
AK		 3972}
3973
69888674
AD		 3974/**
3975 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3976 * @adapter: board private structure
3977 *
3978 * If this function returns with an error, then it's possible one or
3979 * more of the rings is populated (while the rest are not). It is the
3980 * callers duty to clean those orphaned rings.
3981 *
3982 * Return 0 on success, negative on failure
3983 **/
3984
3985static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3986{
3987 int i, err = 0;
3988
3989 for (i = 0; i < adapter->num_rx_queues; i++) {
3990 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3991 if (!err)
3992 continue;
3993 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3994 break;
3995 }
3996
3997 return err;
3998}
3999
9a799d71
AK		 4000/**
4001 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4002 * @adapter: board private structure
4003 * @tx_ring: Tx descriptor ring for a specific queue
4004 *
4005 * Free all transmit software resources
4006 **/
c431f97e
JB		 4007void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4008 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4009{
4010 struct pci_dev *pdev = adapter->pdev;
4011
4012 ixgbe_clean_tx_ring(adapter, tx_ring);
4013
4014 vfree(tx_ring->tx_buffer_info);
4015 tx_ring->tx_buffer_info = NULL;
4016
4017 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4018
4019 tx_ring->desc = NULL;
4020}
4021
4022/**
4023 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4024 * @adapter: board private structure
4025 *
4026 * Free all transmit software resources
4027 **/
4028static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4029{
4030 int i;
4031
4032 for (i = 0; i < adapter->num_tx_queues; i++)
9891ca7c
JB		 4033 if (adapter->tx_ring[i].desc)
4034 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 4035}
4036
4037/**
b4617240 4038 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4039 * @adapter: board private structure
4040 * @rx_ring: ring to clean the resources from
4041 *
4042 * Free all receive software resources
4043 **/
c431f97e
JB		 4044void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4045 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4046{
4047 struct pci_dev *pdev = adapter->pdev;
4048
4049 ixgbe_clean_rx_ring(adapter, rx_ring);
4050
4051 vfree(rx_ring->rx_buffer_info);
4052 rx_ring->rx_buffer_info = NULL;
4053
4054 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4055
4056 rx_ring->desc = NULL;
4057}
4058
4059/**
4060 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4061 * @adapter: board private structure
4062 *
4063 * Free all receive software resources
4064 **/
4065static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4066{
4067 int i;
4068
4069 for (i = 0; i < adapter->num_rx_queues; i++)
9891ca7c
JB		 4070 if (adapter->rx_ring[i].desc)
4071 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 4072}
4073
9a799d71
AK		 4074/**
4075 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4076 * @netdev: network interface device structure
4077 * @new_mtu: new value for maximum frame size
4078 *
4079 * Returns 0 on success, negative on failure
4080 **/
4081static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4082{
4083 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4084 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4085
42c783c5
JB		 4086 /* MTU < 68 is an error and causes problems on some kernels */
4087 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 4088 return -EINVAL;
4089
021230d4 4090 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 4091 netdev->mtu, new_mtu);
021230d4 4092 /* must set new MTU before calling down or up */
9a799d71
AK		 4093 netdev->mtu = new_mtu;
4094
d4f80882
AV		 4095 if (netif_running(netdev))
4096 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4097
4098 return 0;
4099}
4100
4101/**
4102 * ixgbe_open - Called when a network interface is made active
4103 * @netdev: network interface device structure
4104 *
4105 * Returns 0 on success, negative value on failure
4106 *
4107 * The open entry point is called when a network interface is made
4108 * active by the system (IFF_UP). At this point all resources needed
4109 * for transmit and receive operations are allocated, the interrupt
4110 * handler is registered with the OS, the watchdog timer is started,
4111 * and the stack is notified that the interface is ready.
4112 **/
4113static int ixgbe_open(struct net_device *netdev)
4114{
4115 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4116 int err;
4bebfaa5
AK		 4117
4118 /* disallow open during test */
4119 if (test_bit(__IXGBE_TESTING, &adapter->state))
4120 return -EBUSY;
9a799d71 4121
54386467
JB		 4122 netif_carrier_off(netdev);
4123
9a799d71
AK		 4124 /* allocate transmit descriptors */
4125 err = ixgbe_setup_all_tx_resources(adapter);
4126 if (err)
4127 goto err_setup_tx;
4128
9a799d71
AK		 4129 /* allocate receive descriptors */
4130 err = ixgbe_setup_all_rx_resources(adapter);
4131 if (err)
4132 goto err_setup_rx;
4133
4134 ixgbe_configure(adapter);
4135
021230d4 4136 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4137 if (err)
4138 goto err_req_irq;
4139
9a799d71
AK		 4140 err = ixgbe_up_complete(adapter);
4141 if (err)
4142 goto err_up;
4143
d55b53ff
JK		 4144 netif_tx_start_all_queues(netdev);
4145
9a799d71
AK		 4146 return 0;
4147
4148err_up:
5eba3699 4149 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4150 ixgbe_free_irq(adapter);
4151err_req_irq:
9a799d71 4152err_setup_rx:
a20a1199 4153 ixgbe_free_all_rx_resources(adapter);
9a799d71 4154err_setup_tx:
a20a1199 4155 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 4156 ixgbe_reset(adapter);
4157
4158 return err;
4159}
4160
4161/**
4162 * ixgbe_close - Disables a network interface
4163 * @netdev: network interface device structure
4164 *
4165 * Returns 0, this is not allowed to fail
4166 *
4167 * The close entry point is called when an interface is de-activated
4168 * by the OS. The hardware is still under the drivers control, but
4169 * needs to be disabled. A global MAC reset is issued to stop the
4170 * hardware, and all transmit and receive resources are freed.
4171 **/
4172static int ixgbe_close(struct net_device *netdev)
4173{
4174 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4175
4176 ixgbe_down(adapter);
4177 ixgbe_free_irq(adapter);
4178
4179 ixgbe_free_all_tx_resources(adapter);
4180 ixgbe_free_all_rx_resources(adapter);
4181
5eba3699 4182 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4183
4184 return 0;
4185}
4186
b3c8b4ba
AD		 4187#ifdef CONFIG_PM
4188static int ixgbe_resume(struct pci_dev *pdev)
4189{
4190 struct net_device *netdev = pci_get_drvdata(pdev);
4191 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4192 u32 err;
4193
4194 pci_set_power_state(pdev, PCI_D0);
4195 pci_restore_state(pdev);
9ce77666 4196
4197 err = pci_enable_device_mem(pdev);
b3c8b4ba 4198 if (err) {
69888674 4199 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 4200 "suspend\n");
4201 return err;
4202 }
4203 pci_set_master(pdev);
4204
dd4d8ca6 4205 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 4206
4207 err = ixgbe_init_interrupt_scheme(adapter);
4208 if (err) {
4209 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4210 "device\n");
4211 return err;
4212 }
4213
b3c8b4ba
AD		 4214 ixgbe_reset(adapter);
4215
495dce12
WJP		 4216 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4217
b3c8b4ba
AD		 4218 if (netif_running(netdev)) {
4219 err = ixgbe_open(adapter->netdev);
4220 if (err)
4221 return err;
4222 }
4223
4224 netif_device_attach(netdev);
4225
4226 return 0;
4227}
b3c8b4ba 4228#endif /* CONFIG_PM */
9d8d05ae
RW		 4229
4230static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 4231{
4232 struct net_device *netdev = pci_get_drvdata(pdev);
4233 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 4234 struct ixgbe_hw *hw = &adapter->hw;
4235 u32 ctrl, fctrl;
4236 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4237#ifdef CONFIG_PM
4238 int retval = 0;
4239#endif
4240
4241 netif_device_detach(netdev);
4242
4243 if (netif_running(netdev)) {
4244 ixgbe_down(adapter);
4245 ixgbe_free_irq(adapter);
4246 ixgbe_free_all_tx_resources(adapter);
4247 ixgbe_free_all_rx_resources(adapter);
4248 }
7a921c93 4249 ixgbe_clear_interrupt_scheme(adapter);
b3c8b4ba
AD		 4250
4251#ifdef CONFIG_PM
4252 retval = pci_save_state(pdev);
4253 if (retval)
4254 return retval;
4df10466 4255
b3c8b4ba 4256#endif
e8e26350
PW		 4257 if (wufc) {
4258 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4259
e8e26350
PW		 4260 /* turn on all-multi mode if wake on multicast is enabled */
4261 if (wufc & IXGBE_WUFC_MC) {
4262 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4263 fctrl |= IXGBE_FCTRL_MPE;
4264 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4265 }
4266
4267 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4268 ctrl |= IXGBE_CTRL_GIO_DIS;
4269 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4270
4271 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4272 } else {
4273 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4274 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4275 }
4276
dd4d8ca6
DS		 4277 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4278 pci_wake_from_d3(pdev, true);
4279 else
4280 pci_wake_from_d3(pdev, false);
b3c8b4ba 4281
9d8d05ae
RW		 4282 *enable_wake = !!wufc;
4283
b3c8b4ba
AD		 4284 ixgbe_release_hw_control(adapter);
4285
4286 pci_disable_device(pdev);
4287
9d8d05ae
RW		 4288 return 0;
4289}
4290
4291#ifdef CONFIG_PM
4292static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4293{
4294 int retval;
4295 bool wake;
4296
4297 retval = __ixgbe_shutdown(pdev, &wake);
4298 if (retval)
4299 return retval;
4300
4301 if (wake) {
4302 pci_prepare_to_sleep(pdev);
4303 } else {
4304 pci_wake_from_d3(pdev, false);
4305 pci_set_power_state(pdev, PCI_D3hot);
4306 }
b3c8b4ba
AD		 4307
4308 return 0;
4309}
9d8d05ae 4310#endif /* CONFIG_PM */
b3c8b4ba
AD		 4311
4312static void ixgbe_shutdown(struct pci_dev *pdev)
4313{
9d8d05ae
RW		 4314 bool wake;
4315
4316 __ixgbe_shutdown(pdev, &wake);
4317
4318 if (system_state == SYSTEM_POWER_OFF) {
4319 pci_wake_from_d3(pdev, wake);
4320 pci_set_power_state(pdev, PCI_D3hot);
4321 }
b3c8b4ba
AD		 4322}
4323
9a799d71
AK		 4324/**
4325 * ixgbe_update_stats - Update the board statistics counters.
4326 * @adapter: board private structure
4327 **/
4328void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4329{
4330 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 4331 u64 total_mpc = 0;
4332 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71 4333
d51019a4 4334 if (hw->mac.type == ixgbe_mac_82599EB) {
f8212f97 4335 u64 rsc_count = 0;
d51019a4
PW		 4336 for (i = 0; i < 16; i++)
4337 adapter->hw_rx_no_dma_resources +=
4338 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
f8212f97
AD		 4339 for (i = 0; i < adapter->num_rx_queues; i++)
4340 rsc_count += adapter->rx_ring[i].rsc_count;
4341 adapter->rsc_count = rsc_count;
d51019a4
PW		 4342 }
4343
9a799d71 4344 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 4345 for (i = 0; i < 8; i++) {
4346 /* for packet buffers not used, the register should read 0 */
4347 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4348 missed_rx += mpc;
4349 adapter->stats.mpc[i] += mpc;
4350 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 4351 if (hw->mac.type == ixgbe_mac_82598EB)
4352 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 4353 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4354 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4355 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4356 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 4357 if (hw->mac.type == ixgbe_mac_82599EB) {
4358 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4359 IXGBE_PXONRXCNT(i));
4360 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4361 IXGBE_PXOFFRXCNT(i));
4362 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 4363 } else {
4364 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4365 IXGBE_PXONRXC(i));
4366 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4367 IXGBE_PXOFFRXC(i));
4368 }
2f90b865
AD		 4369 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4370 IXGBE_PXONTXC(i));
2f90b865 4371 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 4372 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 4373 }
4374 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4375 /* work around hardware counting issue */
4376 adapter->stats.gprc -= missed_rx;
4377
4378 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350
PW		 4379 if (hw->mac.type == ixgbe_mac_82599EB) {
4380 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4381 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
4382 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4383 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
4384 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4385 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4386 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4387 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
c4cf55e5
PWJ		 4388 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4389 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c
YZ		 4390#ifdef IXGBE_FCOE
4391 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4392 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4393 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4394 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4395 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4396 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4397#endif /* IXGBE_FCOE */
e8e26350
PW		 4398 } else {
4399 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4400 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4401 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4402 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4403 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4404 }
9a799d71
AK		 4405 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4406 adapter->stats.bprc += bprc;
4407 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 4408 if (hw->mac.type == ixgbe_mac_82598EB)
4409 adapter->stats.mprc -= bprc;
9a799d71
AK		 4410 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4411 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4412 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4413 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4414 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4415 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4416 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 4417 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 4418 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4419 adapter->stats.lxontxc += lxon;
4420 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4421 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 4422 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4423 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 4424 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4425 /*
4426 * 82598 errata - tx of flow control packets is included in tx counters
4427 */
4428 xon_off_tot = lxon + lxoff;
4429 adapter->stats.gptc -= xon_off_tot;
4430 adapter->stats.mptc -= xon_off_tot;
4431 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 4432 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4433 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4434 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 4435 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4436 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 4437 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 4438 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4439 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4440 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4441 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4442 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 4443 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4444
4445 /* Fill out the OS statistics structure */
9a799d71
AK		 4446 adapter->net_stats.multicast = adapter->stats.mprc;
4447
4448 /* Rx Errors */
4449 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
b4617240 4450 adapter->stats.rlec;
9a799d71
AK		 4451 adapter->net_stats.rx_dropped = 0;
4452 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4453 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 4454 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 4455}
4456
4457/**
4458 * ixgbe_watchdog - Timer Call-back
4459 * @data: pointer to adapter cast into an unsigned long
4460 **/
4461static void ixgbe_watchdog(unsigned long data)
4462{
4463 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 4464 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 4465 u64 eics = 0;
4466 int i;
cf8280ee 4467
fe49f04a
AD		 4468 /*
4469 * Do the watchdog outside of interrupt context due to the lovely
4470 * delays that some of the newer hardware requires
4471 */
22d5a71b 4472
fe49f04a
AD		 4473 if (test_bit(__IXGBE_DOWN, &adapter->state))
4474 goto watchdog_short_circuit;
22d5a71b 4475
fe49f04a
AD		 4476 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4477 /*
4478 * for legacy and MSI interrupts don't set any bits
4479 * that are enabled for EIAM, because this operation
4480 * would set *both* EIMS and EICS for any bit in EIAM
4481 */
4482 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4483 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4484 goto watchdog_reschedule;
4485 }
4486
4487 /* get one bit for every active tx/rx interrupt vector */
4488 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4489 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4490 if (qv->rxr_count || qv->txr_count)
4491 eics |= ((u64)1 << i);
cf8280ee 4492 }
9a799d71 4493
fe49f04a
AD		 4494 /* Cause software interrupt to ensure rx rings are cleaned */
4495 ixgbe_irq_rearm_queues(adapter, eics);
4496
4497watchdog_reschedule:
4498 /* Reset the timer */
4499 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4500
4501watchdog_short_circuit:
cf8280ee
JB		 4502 schedule_work(&adapter->watchdog_task);
4503}
4504
e8e26350
PW		 4505/**
4506 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4507 * @work: pointer to work_struct containing our data
4508 **/
4509static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4510{
4511 struct ixgbe_adapter *adapter = container_of(work,
4512 struct ixgbe_adapter,
4513 multispeed_fiber_task);
4514 struct ixgbe_hw *hw = &adapter->hw;
4515 u32 autoneg;
4516
4517 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 4518 autoneg = hw->phy.autoneg_advertised;
4519 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e26350
PW		 4520 hw->mac.ops.get_link_capabilities(hw, &autoneg,
4521 &hw->mac.autoneg);
4522 if (hw->mac.ops.setup_link_speed)
4523 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
4524 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4525 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4526}
4527
4528/**
4529 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4530 * @work: pointer to work_struct containing our data
4531 **/
4532static void ixgbe_sfp_config_module_task(struct work_struct *work)
4533{
4534 struct ixgbe_adapter *adapter = container_of(work,
4535 struct ixgbe_adapter,
4536 sfp_config_module_task);
4537 struct ixgbe_hw *hw = &adapter->hw;
4538 u32 err;
4539
4540 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 4541
4542 /* Time for electrical oscillations to settle down */
4543 msleep(100);
e8e26350 4544 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4545
e8e26350 4546 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 4547 dev_err(&adapter->pdev->dev, "failed to initialize because "
4548 "an unsupported SFP+ module type was detected.\n"
4549 "Reload the driver after installing a supported "
4550 "module.\n");
63d6e1d8 4551 unregister_netdev(adapter->netdev);
e8e26350
PW		 4552 return;
4553 }
4554 hw->mac.ops.setup_sfp(hw);
4555
8d1c3c07 4556 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 4557 /* This will also work for DA Twinax connections */
4558 schedule_work(&adapter->multispeed_fiber_task);
4559 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4560}
4561
c4cf55e5
PWJ		 4562/**
4563 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4564 * @work: pointer to work_struct containing our data
4565 **/
4566static void ixgbe_fdir_reinit_task(struct work_struct *work)
4567{
4568 struct ixgbe_adapter *adapter = container_of(work,
4569 struct ixgbe_adapter,
4570 fdir_reinit_task);
4571 struct ixgbe_hw *hw = &adapter->hw;
4572 int i;
4573
4574 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4575 for (i = 0; i < adapter->num_tx_queues; i++)
4576 set_bit(__IXGBE_FDIR_INIT_DONE,
4577 &(adapter->tx_ring[i].reinit_state));
4578 } else {
4579 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4580 "ignored adding FDIR ATR filters \n");
4581 }
4582 /* Done FDIR Re-initialization, enable transmits */
4583 netif_tx_start_all_queues(adapter->netdev);
4584}
4585
cf8280ee 4586/**
69888674
AD		 4587 * ixgbe_watchdog_task - worker thread to bring link up
4588 * @work: pointer to work_struct containing our data
cf8280ee
JB		 4589 **/
4590static void ixgbe_watchdog_task(struct work_struct *work)
4591{
4592 struct ixgbe_adapter *adapter = container_of(work,
4593 struct ixgbe_adapter,
4594 watchdog_task);
4595 struct net_device *netdev = adapter->netdev;
4596 struct ixgbe_hw *hw = &adapter->hw;
4597 u32 link_speed = adapter->link_speed;
4598 bool link_up = adapter->link_up;
bc59fcda
NS		 4599 int i;
4600 struct ixgbe_ring *tx_ring;
4601 int some_tx_pending = 0;
cf8280ee
JB		 4602
4603 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4604
4605 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4606 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 4607 if (link_up) {
4608#ifdef CONFIG_DCB
4609 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4610 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 4611 hw->mac.ops.fc_enable(hw, i);
264857b8 4612 } else {
620fa036 4613 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 4614 }
4615#else
620fa036 4616 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 4617#endif
4618 }
4619
cf8280ee
JB		 4620 if (link_up ||
4621 time_after(jiffies, (adapter->link_check_timeout +
4622 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 4623 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 4624 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 4625 }
4626 adapter->link_up = link_up;
4627 adapter->link_speed = link_speed;
4628 }
9a799d71
AK		 4629
4630 if (link_up) {
4631 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 4632 bool flow_rx, flow_tx;
4633
4634 if (hw->mac.type == ixgbe_mac_82599EB) {
4635 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4636 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4637 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
4638 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
4639 } else {
4640 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4641 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4642 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
4643 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
4644 }
4645
a46e534b
JK		 4646 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4647 "Flow Control: %s\n",
4648 netdev->name,
4649 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4650 "10 Gbps" :
4651 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4652 "1 Gbps" : "unknown speed")),
e8e26350
PW		 4653 ((flow_rx && flow_tx) ? "RX/TX" :
4654 (flow_rx ? "RX" :
4655 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 4656
4657 netif_carrier_on(netdev);
9a799d71
AK		 4658 } else {
4659 /* Force detection of hung controller */
4660 adapter->detect_tx_hung = true;
4661 }
4662 } else {
cf8280ee
JB		 4663 adapter->link_up = false;
4664 adapter->link_speed = 0;
9a799d71 4665 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 4666 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4667 netdev->name);
9a799d71 4668 netif_carrier_off(netdev);
9a799d71
AK		 4669 }
4670 }
4671
bc59fcda
NS		 4672 if (!netif_carrier_ok(netdev)) {
4673 for (i = 0; i < adapter->num_tx_queues; i++) {
4674 tx_ring = &adapter->tx_ring[i];
4675 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4676 some_tx_pending = 1;
4677 break;
4678 }
4679 }
4680
4681 if (some_tx_pending) {
4682 /* We've lost link, so the controller stops DMA,
4683 * but we've got queued Tx work that's never going
4684 * to get done, so reset controller to flush Tx.
4685 * (Do the reset outside of interrupt context).
4686 */
4687 schedule_work(&adapter->reset_task);
4688 }
4689 }
4690
9a799d71 4691 ixgbe_update_stats(adapter);
cf8280ee 4692 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 4693}
4694
9a799d71 4695static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 4696 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4697 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 4698{
4699 struct ixgbe_adv_tx_context_desc *context_desc;
4700 unsigned int i;
4701 int err;
4702 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 4703 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4704 u32 mss_l4len_idx, l4len;
9a799d71
AK		 4705
4706 if (skb_is_gso(skb)) {
4707 if (skb_header_cloned(skb)) {
4708 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4709 if (err)
4710 return err;
4711 }
4712 l4len = tcp_hdrlen(skb);
4713 *hdr_len += l4len;
4714
8327d000 4715 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 4716 struct iphdr *iph = ip_hdr(skb);
4717 iph->tot_len = 0;
4718 iph->check = 0;
4719 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 4720 iph->daddr, 0,
4721 IPPROTO_TCP,
4722 0);
9a799d71
AK		 4723 adapter->hw_tso_ctxt++;
4724 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4725 ipv6_hdr(skb)->payload_len = 0;
4726 tcp_hdr(skb)->check =
4727 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 4728 &ipv6_hdr(skb)->daddr,
4729 0, IPPROTO_TCP, 0);
9a799d71
AK		 4730 adapter->hw_tso6_ctxt++;
4731 }
4732
4733 i = tx_ring->next_to_use;
4734
4735 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4736 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4737
4738 /* VLAN MACLEN IPLEN */
4739 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4740 vlan_macip_lens |=
4741 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4742 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 4743 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4744 *hdr_len += skb_network_offset(skb);
4745 vlan_macip_lens |=
4746 (skb_transport_header(skb) - skb_network_header(skb));
4747 *hdr_len +=
4748 (skb_transport_header(skb) - skb_network_header(skb));
4749 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4750 context_desc->seqnum_seed = 0;
4751
4752 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 4753 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 4754 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 4755
8327d000 4756 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4757 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4758 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4759 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4760
4761 /* MSS L4LEN IDX */
9f8cdf4f 4762 mss_l4len_idx =
9a799d71
AK		 4763 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4764 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 4765 /* use index 1 for TSO */
4766 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4767 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4768
4769 tx_buffer_info->time_stamp = jiffies;
4770 tx_buffer_info->next_to_watch = i;
4771
4772 i++;
4773 if (i == tx_ring->count)
4774 i = 0;
4775 tx_ring->next_to_use = i;
4776
4777 return true;
4778 }
4779 return false;
4780}
4781
4782static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 4783 struct ixgbe_ring *tx_ring,
4784 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 4785{
4786 struct ixgbe_adv_tx_context_desc *context_desc;
4787 unsigned int i;
4788 struct ixgbe_tx_buffer *tx_buffer_info;
4789 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4790
4791 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4792 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4793 i = tx_ring->next_to_use;
4794 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4795 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4796
4797 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4798 vlan_macip_lens |=
4799 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4800 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 4801 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4802 if (skb->ip_summed == CHECKSUM_PARTIAL)
4803 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 4804 skb_network_header(skb));
9a799d71
AK		 4805
4806 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4807 context_desc->seqnum_seed = 0;
4808
4809 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 4810 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 4811
4812 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71 4813 switch (skb->protocol) {
09640e63 4814 case cpu_to_be16(ETH_P_IP):
9a799d71 4815 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 4816 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4817 type_tucmd_mlhl |=
b4617240 4818 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4819 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4820 type_tucmd_mlhl |=
4821 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4822 break;
09640e63 4823 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 4824 /* XXX what about other V6 headers?? */
4825 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4826 type_tucmd_mlhl |=
b4617240 4827 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4828 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4829 type_tucmd_mlhl |=
4830 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4831 break;
41825d71
AK		 4832 default:
4833 if (unlikely(net_ratelimit())) {
4834 DPRINTK(PROBE, WARNING,
4835 "partial checksum but proto=%x!\n",
4836 skb->protocol);
4837 }
4838 break;
4839 }
9a799d71
AK		 4840 }
4841
4842 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 4843 /* use index zero for tx checksum offload */
9a799d71
AK		 4844 context_desc->mss_l4len_idx = 0;
4845
4846 tx_buffer_info->time_stamp = jiffies;
4847 tx_buffer_info->next_to_watch = i;
9f8cdf4f 4848
9a799d71
AK		 4849 adapter->hw_csum_tx_good++;
4850 i++;
4851 if (i == tx_ring->count)
4852 i = 0;
4853 tx_ring->next_to_use = i;
4854
4855 return true;
4856 }
9f8cdf4f 4857
9a799d71
AK		 4858 return false;
4859}
4860
4861static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 4862 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 4863 struct sk_buff *skb, u32 tx_flags,
4864 unsigned int first)
9a799d71
AK		 4865{
4866 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 4867 unsigned int len;
4868 unsigned int total = skb->len;
9a799d71
AK		 4869 unsigned int offset = 0, size, count = 0, i;
4870 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4871 unsigned int f;
44df32c5 4872 dma_addr_t *map;
9a799d71
AK		 4873
4874 i = tx_ring->next_to_use;
4875
44df32c5
AD		 4876 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4877 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4878 return 0;
4879 }
4880
4881 map = skb_shinfo(skb)->dma_maps;
4882
eacd73f7
YZ		 4883 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4884 /* excluding fcoe_crc_eof for FCoE */
4885 total -= sizeof(struct fcoe_crc_eof);
4886
4887 len = min(skb_headlen(skb), total);
9a799d71
AK		 4888 while (len) {
4889 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4890 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4891
4892 tx_buffer_info->length = size;
042a53a9 4893 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
9a799d71
AK		 4894 tx_buffer_info->time_stamp = jiffies;
4895 tx_buffer_info->next_to_watch = i;
4896
4897 len -= size;
eacd73f7 4898 total -= size;
9a799d71
AK		 4899 offset += size;
4900 count++;
44df32c5
AD		 4901
4902 if (len) {
4903 i++;
4904 if (i == tx_ring->count)
4905 i = 0;
4906 }
9a799d71
AK		 4907 }
4908
4909 for (f = 0; f < nr_frags; f++) {
4910 struct skb_frag_struct *frag;
4911
4912 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 4913 len = min((unsigned int)frag->size, total);
44df32c5 4914 offset = 0;
9a799d71
AK		 4915
4916 while (len) {
44df32c5
AD		 4917 i++;
4918 if (i == tx_ring->count)
4919 i = 0;
4920
9a799d71
AK		 4921 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4922 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4923
4924 tx_buffer_info->length = size;
042a53a9 4925 tx_buffer_info->dma = map[f] + offset;
9a799d71
AK		 4926 tx_buffer_info->time_stamp = jiffies;
4927 tx_buffer_info->next_to_watch = i;
4928
4929 len -= size;
eacd73f7 4930 total -= size;
9a799d71
AK		 4931 offset += size;
4932 count++;
9a799d71 4933 }
eacd73f7
YZ		 4934 if (total == 0)
4935 break;
9a799d71 4936 }
44df32c5 4937
9a799d71
AK		 4938 tx_ring->tx_buffer_info[i].skb = skb;
4939 tx_ring->tx_buffer_info[first].next_to_watch = i;
4940
4941 return count;
4942}
4943
4944static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 4945 struct ixgbe_ring *tx_ring,
4946 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 4947{
4948 union ixgbe_adv_tx_desc *tx_desc = NULL;
4949 struct ixgbe_tx_buffer *tx_buffer_info;
4950 u32 olinfo_status = 0, cmd_type_len = 0;
4951 unsigned int i;
4952 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4953
4954 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4955
4956 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4957
4958 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4959 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4960
4961 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4962 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4963
4964 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4965 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 4966
4eeae6fd
PW		 4967 /* use index 1 context for tso */
4968 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4969 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4970 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 4971 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 4972
4973 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4974 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4975 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 4976
eacd73f7
YZ		 4977 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
4978 olinfo_status |= IXGBE_ADVTXD_CC;
4979 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4980 if (tx_flags & IXGBE_TX_FLAGS_FSO)
4981 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4982 }
4983
9a799d71
AK		 4984 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4985
4986 i = tx_ring->next_to_use;
4987 while (count--) {
4988 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4989 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4990 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4991 tx_desc->read.cmd_type_len =
b4617240 4992 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 4993 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 4994 i++;
4995 if (i == tx_ring->count)
4996 i = 0;
4997 }
4998
4999 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5000
5001 /*
5002 * Force memory writes to complete before letting h/w
5003 * know there are new descriptors to fetch. (Only
5004 * applicable for weak-ordered memory model archs,
5005 * such as IA-64).
5006 */
5007 wmb();
5008
5009 tx_ring->next_to_use = i;
5010 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5011}
5012
c4cf55e5
PWJ		 5013static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5014 int queue, u32 tx_flags)
5015{
5016 /* Right now, we support IPv4 only */
5017 struct ixgbe_atr_input atr_input;
5018 struct tcphdr *th;
5019 struct udphdr *uh;
5020 struct iphdr *iph = ip_hdr(skb);
5021 struct ethhdr *eth = (struct ethhdr *)skb->data;
5022 u16 vlan_id, src_port, dst_port, flex_bytes;
5023 u32 src_ipv4_addr, dst_ipv4_addr;
5024 u8 l4type = 0;
5025
5026 /* check if we're UDP or TCP */
5027 if (iph->protocol == IPPROTO_TCP) {
5028 th = tcp_hdr(skb);
5029 src_port = th->source;
5030 dst_port = th->dest;
5031 l4type |= IXGBE_ATR_L4TYPE_TCP;
5032 /* l4type IPv4 type is 0, no need to assign */
5033 } else if(iph->protocol == IPPROTO_UDP) {
5034 uh = udp_hdr(skb);
5035 src_port = uh->source;
5036 dst_port = uh->dest;
5037 l4type |= IXGBE_ATR_L4TYPE_UDP;
5038 /* l4type IPv4 type is 0, no need to assign */
5039 } else {
5040 /* Unsupported L4 header, just bail here */
5041 return;
5042 }
5043
5044 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5045
5046 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5047 IXGBE_TX_FLAGS_VLAN_SHIFT;
5048 src_ipv4_addr = iph->saddr;
5049 dst_ipv4_addr = iph->daddr;
5050 flex_bytes = eth->h_proto;
5051
5052 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5053 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5054 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5055 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5056 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5057 /* src and dst are inverted, think how the receiver sees them */
5058 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5059 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5060
5061 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5062 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5063}
5064
e092be60 5065static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5066 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 5067{
5068 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5069
30eba97a 5070 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5071 /* Herbert's original patch had:
5072 * smp_mb__after_netif_stop_queue();
5073 * but since that doesn't exist yet, just open code it. */
5074 smp_mb();
5075
5076 /* We need to check again in a case another CPU has just
5077 * made room available. */
5078 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5079 return -EBUSY;
5080
5081 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 5082 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5083 ++adapter->restart_queue;
5084 return 0;
5085}
5086
5087static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5088 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 5089{
5090 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5091 return 0;
5092 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5093}
5094
09a3b1f8
SH		 5095static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5096{
5097 struct ixgbe_adapter *adapter = netdev_priv(dev);
5098
c4cf55e5
PWJ		 5099 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5100 return smp_processor_id();
5101
09a3b1f8
SH		 5102 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5103 return 0; /* All traffic should default to class 0 */
5104
5105 return skb_tx_hash(dev, skb);
5106}
5107
9a799d71
AK		 5108static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
5109{
5110 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5111 struct ixgbe_ring *tx_ring;
9a799d71
AK		 5112 unsigned int first;
5113 unsigned int tx_flags = 0;
30eba97a
AV		 5114 u8 hdr_len = 0;
5115 int r_idx = 0, tso;
9a799d71
AK		 5116 int count = 0;
5117 unsigned int f;
9f8cdf4f 5118
95615d90 5119 r_idx = skb->queue_mapping;
30eba97a 5120 tx_ring = &adapter->tx_ring[r_idx];
9a799d71 5121
9f8cdf4f
JB		 5122 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5123 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 5124 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5125 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5126 tx_flags |= (skb->queue_mapping << 13);
5127 }
5128 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5129 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5130 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5131 tx_flags |= (skb->queue_mapping << 13);
9f8cdf4f
JB		 5132 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5133 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 5134 }
eacd73f7
YZ		 5135
5136 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5137 (skb->protocol == htons(ETH_P_FCOE)))
5138 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5139
5140 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 5141 if (skb_is_gso(skb) ||
5142 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 5143 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5144 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 5145 count++;
5146
9f8cdf4f
JB		 5147 count += TXD_USE_COUNT(skb_headlen(skb));
5148 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 5149 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5150
e092be60 5151 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 5152 adapter->tx_busy++;
9a799d71
AK		 5153 return NETDEV_TX_BUSY;
5154 }
9a799d71 5155
9a799d71 5156 first = tx_ring->next_to_use;
eacd73f7
YZ		 5157 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5158#ifdef IXGBE_FCOE
5159 /* setup tx offload for FCoE */
5160 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5161 if (tso < 0) {
5162 dev_kfree_skb_any(skb);
5163 return NETDEV_TX_OK;
5164 }
5165 if (tso)
5166 tx_flags |= IXGBE_TX_FLAGS_FSO;
5167#endif /* IXGBE_FCOE */
5168 } else {
5169 if (skb->protocol == htons(ETH_P_IP))
5170 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5171 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5172 if (tso < 0) {
5173 dev_kfree_skb_any(skb);
5174 return NETDEV_TX_OK;
5175 }
9a799d71 5176
eacd73f7
YZ		 5177 if (tso)
5178 tx_flags |= IXGBE_TX_FLAGS_TSO;
5179 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5180 (skb->ip_summed == CHECKSUM_PARTIAL))
5181 tx_flags |= IXGBE_TX_FLAGS_CSUM;
5182 }
9a799d71 5183
eacd73f7 5184 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 5185 if (count) {
c4cf55e5
PWJ		 5186 /* add the ATR filter if ATR is on */
5187 if (tx_ring->atr_sample_rate) {
5188 ++tx_ring->atr_count;
5189 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5190 test_bit(__IXGBE_FDIR_INIT_DONE,
5191 &tx_ring->reinit_state)) {
5192 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5193 tx_flags);
5194 tx_ring->atr_count = 0;
5195 }
5196 }
44df32c5
AD		 5197 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5198 hdr_len);
44df32c5 5199 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 5200
44df32c5
AD		 5201 } else {
5202 dev_kfree_skb_any(skb);
5203 tx_ring->tx_buffer_info[first].time_stamp = 0;
5204 tx_ring->next_to_use = first;
5205 }
9a799d71
AK		 5206
5207 return NETDEV_TX_OK;
5208}
5209
5210/**
5211 * ixgbe_get_stats - Get System Network Statistics
5212 * @netdev: network interface device structure
5213 *
5214 * Returns the address of the device statistics structure.
5215 * The statistics are actually updated from the timer callback.
5216 **/
5217static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5218{
5219 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5220
5221 /* only return the current stats */
5222 return &adapter->net_stats;
5223}
5224
5225/**
5226 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5227 * @netdev: network interface device structure
5228 * @p: pointer to an address structure
5229 *
5230 * Returns 0 on success, negative on failure
5231 **/
5232static int ixgbe_set_mac(struct net_device *netdev, void *p)
5233{
5234 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 5235 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5236 struct sockaddr *addr = p;
5237
5238 if (!is_valid_ether_addr(addr->sa_data))
5239 return -EADDRNOTAVAIL;
5240
5241 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 5242 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 5243
b4617240 5244 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 5245
5246 return 0;
5247}
5248
6b73e10d
BH		 5249static int
5250ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5251{
5252 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5253 struct ixgbe_hw *hw = &adapter->hw;
5254 u16 value;
5255 int rc;
5256
5257 if (prtad != hw->phy.mdio.prtad)
5258 return -EINVAL;
5259 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5260 if (!rc)
5261 rc = value;
5262 return rc;
5263}
5264
5265static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5266 u16 addr, u16 value)
5267{
5268 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5269 struct ixgbe_hw *hw = &adapter->hw;
5270
5271 if (prtad != hw->phy.mdio.prtad)
5272 return -EINVAL;
5273 return hw->phy.ops.write_reg(hw, addr, devad, value);
5274}
5275
5276static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5277{
5278 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5279
5280 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5281}
5282
0365e6e4
PW		 5283/**
5284 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 5285 * netdev->dev_addrs
0365e6e4
PW		 5286 * @netdev: network interface device structure
5287 *
5288 * Returns non-zero on failure
5289 **/
5290static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5291{
5292 int err = 0;
5293 struct ixgbe_adapter *adapter = netdev_priv(dev);
5294 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5295
5296 if (is_valid_ether_addr(mac->san_addr)) {
5297 rtnl_lock();
5298 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5299 rtnl_unlock();
5300 }
5301 return err;
5302}
5303
5304/**
5305 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 5306 * netdev->dev_addrs
0365e6e4
PW		 5307 * @netdev: network interface device structure
5308 *
5309 * Returns non-zero on failure
5310 **/
5311static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5312{
5313 int err = 0;
5314 struct ixgbe_adapter *adapter = netdev_priv(dev);
5315 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5316
5317 if (is_valid_ether_addr(mac->san_addr)) {
5318 rtnl_lock();
5319 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5320 rtnl_unlock();
5321 }
5322 return err;
5323}
5324
9a799d71
AK		 5325#ifdef CONFIG_NET_POLL_CONTROLLER
5326/*
5327 * Polling 'interrupt' - used by things like netconsole to send skbs
5328 * without having to re-enable interrupts. It's not called while
5329 * the interrupt routine is executing.
5330 */
5331static void ixgbe_netpoll(struct net_device *netdev)
5332{
5333 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5334
5335 disable_irq(adapter->pdev->irq);
5336 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5337 ixgbe_intr(adapter->pdev->irq, netdev);
5338 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5339 enable_irq(adapter->pdev->irq);
5340}
5341#endif
5342
0edc3527
SH		 5343static const struct net_device_ops ixgbe_netdev_ops = {
5344 .ndo_open = ixgbe_open,
5345 .ndo_stop = ixgbe_close,
00829823 5346 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 5347 .ndo_select_queue = ixgbe_select_queue,
0edc3527 5348 .ndo_get_stats = ixgbe_get_stats,
e90d400c 5349 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 5350 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5351 .ndo_validate_addr = eth_validate_addr,
5352 .ndo_set_mac_address = ixgbe_set_mac,
5353 .ndo_change_mtu = ixgbe_change_mtu,
5354 .ndo_tx_timeout = ixgbe_tx_timeout,
5355 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5356 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5357 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 5358 .ndo_do_ioctl = ixgbe_ioctl,
0edc3527
SH		 5359#ifdef CONFIG_NET_POLL_CONTROLLER
5360 .ndo_poll_controller = ixgbe_netpoll,
5361#endif
332d4a7d
YZ		 5362#ifdef IXGBE_FCOE
5363 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5364 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5365#endif /* IXGBE_FCOE */
0edc3527
SH		 5366};
5367
9a799d71
AK		 5368/**
5369 * ixgbe_probe - Device Initialization Routine
5370 * @pdev: PCI device information struct
5371 * @ent: entry in ixgbe_pci_tbl
5372 *
5373 * Returns 0 on success, negative on failure
5374 *
5375 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5376 * The OS initialization, configuring of the adapter private structure,
5377 * and a hardware reset occur.
5378 **/
5379static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 5380 const struct pci_device_id *ent)
9a799d71
AK		 5381{
5382 struct net_device *netdev;
5383 struct ixgbe_adapter *adapter = NULL;
5384 struct ixgbe_hw *hw;
5385 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 5386 static int cards_found;
5387 int i, err, pci_using_dac;
eacd73f7
YZ		 5388#ifdef IXGBE_FCOE
5389 u16 device_caps;
5390#endif
c44ade9e 5391 u32 part_num, eec;
9a799d71 5392
9ce77666 5393 err = pci_enable_device_mem(pdev);
9a799d71
AK		 5394 if (err)
5395 return err;
5396
6a35528a
YH		 5397 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5398 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
9a799d71
AK		 5399 pci_using_dac = 1;
5400 } else {
284901a9 5401 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5402 if (err) {
284901a9 5403 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5404 if (err) {
b4617240
PW		 5405 dev_err(&pdev->dev, "No usable DMA "
5406 "configuration, aborting\n");
9a799d71
AK		 5407 goto err_dma;
5408 }
5409 }
5410 pci_using_dac = 0;
5411 }
5412
9ce77666 5413 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5414 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 5415 if (err) {
9ce77666 5416 dev_err(&pdev->dev,
5417 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 5418 goto err_pci_reg;
5419 }
5420
6fabd715
PWJ		 5421 err = pci_enable_pcie_error_reporting(pdev);
5422 if (err) {
5423 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
5424 "0x%x\n", err);
5425 /* non-fatal, continue */
5426 }
5427
9a799d71 5428 pci_set_master(pdev);
fb3b27bc 5429 pci_save_state(pdev);
9a799d71 5430
30eba97a 5431 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 5432 if (!netdev) {
5433 err = -ENOMEM;
5434 goto err_alloc_etherdev;
5435 }
5436
9a799d71
AK		 5437 SET_NETDEV_DEV(netdev, &pdev->dev);
5438
5439 pci_set_drvdata(pdev, netdev);
5440 adapter = netdev_priv(netdev);
5441
5442 adapter->netdev = netdev;
5443 adapter->pdev = pdev;
5444 hw = &adapter->hw;
5445 hw->back = adapter;
5446 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5447
05857980
JK		 5448 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5449 pci_resource_len(pdev, 0));
9a799d71
AK		 5450 if (!hw->hw_addr) {
5451 err = -EIO;
5452 goto err_ioremap;
5453 }
5454
5455 for (i = 1; i <= 5; i++) {
5456 if (pci_resource_len(pdev, i) == 0)
5457 continue;
5458 }
5459
0edc3527 5460 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 5461 ixgbe_set_ethtool_ops(netdev);
9a799d71 5462 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 5463 strcpy(netdev->name, pci_name(pdev));
5464
9a799d71
AK		 5465 adapter->bd_number = cards_found;
5466
9a799d71
AK		 5467 /* Setup hw api */
5468 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 5469 hw->mac.type = ii->mac;
9a799d71 5470
c44ade9e
JB		 5471 /* EEPROM */
5472 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5473 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5474 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5475 if (!(eec & (1 << 8)))
5476 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5477
5478 /* PHY */
5479 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 5480 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 5481 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5482 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5483 hw->phy.mdio.mmds = 0;
5484 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5485 hw->phy.mdio.dev = netdev;
5486 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5487 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 5488
5489 /* set up this timer and work struct before calling get_invariants
5490 * which might start the timer
5491 */
5492 init_timer(&adapter->sfp_timer);
5493 adapter->sfp_timer.function = &ixgbe_sfp_timer;
5494 adapter->sfp_timer.data = (unsigned long) adapter;
5495
5496 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 5497
e8e26350
PW		 5498 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5499 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5500
5501 /* a new SFP+ module arrival, called from GPI SDP2 context */
5502 INIT_WORK(&adapter->sfp_config_module_task,
5503 ixgbe_sfp_config_module_task);
5504
8ca783ab 5505 ii->get_invariants(hw);
9a799d71
AK		 5506
5507 /* setup the private structure */
5508 err = ixgbe_sw_init(adapter);
5509 if (err)
5510 goto err_sw_init;
5511
bf069c97
DS		 5512 /*
5513 * If there is a fan on this device and it has failed log the
5514 * failure.
5515 */
5516 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5517 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5518 if (esdp & IXGBE_ESDP_SDP1)
5519 DPRINTK(PROBE, CRIT,
5520 "Fan has stopped, replace the adapter\n");
5521 }
5522
c44ade9e
JB		 5523 /* reset_hw fills in the perm_addr as well */
5524 err = hw->mac.ops.reset_hw(hw);
8ca783ab
DS		 5525 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5526 hw->mac.type == ixgbe_mac_82598EB) {
5527 /*
5528 * Start a kernel thread to watch for a module to arrive.
5529 * Only do this for 82598, since 82599 will generate
5530 * interrupts on module arrival.
5531 */
5532 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5533 mod_timer(&adapter->sfp_timer,
5534 round_jiffies(jiffies + (2 * HZ)));
5535 err = 0;
5536 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 5537 dev_err(&adapter->pdev->dev, "failed to initialize because "
5538 "an unsupported SFP+ module type was detected.\n"
5539 "Reload the driver after installing a supported "
5540 "module.\n");
04f165ef
PW		 5541 goto err_sw_init;
5542 } else if (err) {
c44ade9e
JB		 5543 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5544 goto err_sw_init;
5545 }
5546
9a799d71 5547 netdev->features = NETIF_F_SG |
b4617240
PW		 5548 NETIF_F_IP_CSUM |
5549 NETIF_F_HW_VLAN_TX |
5550 NETIF_F_HW_VLAN_RX |
5551 NETIF_F_HW_VLAN_FILTER;
9a799d71 5552
e9990a9c 5553 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 5554 netdev->features |= NETIF_F_TSO;
9a799d71 5555 netdev->features |= NETIF_F_TSO6;
78b6f4ce 5556 netdev->features |= NETIF_F_GRO;
ad31c402 5557
45a5ead0
JB		 5558 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5559 netdev->features |= NETIF_F_SCTP_CSUM;
5560
ad31c402
JK		 5561 netdev->vlan_features |= NETIF_F_TSO;
5562 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 5563 netdev->vlan_features |= NETIF_F_IP_CSUM;
ad31c402
JK		 5564 netdev->vlan_features |= NETIF_F_SG;
5565
2f90b865
AD		 5566 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5567 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5568
7a6b6f51 5569#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5570 netdev->dcbnl_ops = &dcbnl_ops;
5571#endif
5572
eacd73f7
YZ		 5573#ifdef IXGBE_FCOE
5574 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
5575 if (hw->mac.ops.get_device_caps) {
5576 hw->mac.ops.get_device_caps(hw, &device_caps);
5577 if (!(device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)) {
5578 netdev->features |= NETIF_F_FCOE_CRC;
5579 netdev->features |= NETIF_F_FSO;
332d4a7d 5580 netdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX - 1;
c4cf55e5
PWJ		 5581 DPRINTK(DRV, INFO, "FCoE enabled, "
5582 "disabling Flow Director\n");
5583 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
5584 adapter->flags &=
5585 ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
5586 adapter->atr_sample_rate = 0;
eacd73f7
YZ		 5587 } else {
5588 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5589 }
5590 }
5591 }
5592#endif /* IXGBE_FCOE */
9a799d71
AK		 5593 if (pci_using_dac)
5594 netdev->features |= NETIF_F_HIGHDMA;
5595
df647b5c 5596 if (adapter->flags & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 5597 netdev->features |= NETIF_F_LRO;
5598
9a799d71 5599 /* make sure the EEPROM is good */
c44ade9e 5600 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 5601 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5602 err = -EIO;
5603 goto err_eeprom;
5604 }
5605
5606 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5607 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5608
c44ade9e
JB		 5609 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5610 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 5611 err = -EIO;
5612 goto err_eeprom;
5613 }
5614
5615 init_timer(&adapter->watchdog_timer);
5616 adapter->watchdog_timer.function = &ixgbe_watchdog;
5617 adapter->watchdog_timer.data = (unsigned long)adapter;
5618
5619 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 5620 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 5621
021230d4
AV		 5622 err = ixgbe_init_interrupt_scheme(adapter);
5623 if (err)
5624 goto err_sw_init;
9a799d71 5625
e8e26350
PW		 5626 switch (pdev->device) {
5627 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 5628 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5629 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
bdf0a550
PWJ		 5630 /* Enable ACPI wakeup in GRC */
5631 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5632 (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
e8e26350
PW		 5633 break;
5634 default:
5635 adapter->wol = 0;
5636 break;
5637 }
5638 device_init_wakeup(&adapter->pdev->dev, true);
5639 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5640
04f165ef
PW		 5641 /* pick up the PCI bus settings for reporting later */
5642 hw->mac.ops.get_bus_info(hw);
5643
9a799d71 5644 /* print bus type/speed/width info */
7c510e4b 5645 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 5646 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5647 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5648 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5649 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5650 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 5651 "Unknown"),
7c510e4b 5652 netdev->dev_addr);
c44ade9e 5653 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 5654 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5655 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5656 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5657 (part_num >> 8), (part_num & 0xff));
5658 else
5659 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5660 hw->mac.type, hw->phy.type,
5661 (part_num >> 8), (part_num & 0xff));
9a799d71 5662
e8e26350 5663 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 5664 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 5665 "this card is not sufficient for optimal "
5666 "performance.\n");
0c254d86 5667 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 5668 "PCI-Express slot is required.\n");
0c254d86
AK		 5669 }
5670
34b0368c
PWJ		 5671 /* save off EEPROM version number */
5672 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5673
9a799d71 5674 /* reset the hardware with the new settings */
794caeb2 5675 err = hw->mac.ops.start_hw(hw);
c44ade9e 5676
794caeb2
PWJ		 5677 if (err == IXGBE_ERR_EEPROM_VERSION) {
5678 /* We are running on a pre-production device, log a warning */
5679 dev_warn(&pdev->dev, "This device is a pre-production "
5680 "adapter/LOM. Please be aware there may be issues "
5681 "associated with your hardware. If you are "
5682 "experiencing problems please contact your Intel or "
5683 "hardware representative who provided you with this "
5684 "hardware.\n");
5685 }
9a799d71
AK		 5686 strcpy(netdev->name, "eth%d");
5687 err = register_netdev(netdev);
5688 if (err)
5689 goto err_register;
5690
54386467
JB		 5691 /* carrier off reporting is important to ethtool even BEFORE open */
5692 netif_carrier_off(netdev);
5693
c4cf55e5
PWJ		 5694 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5695 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5696 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5697
5dd2d332 5698#ifdef CONFIG_IXGBE_DCA
652f093f 5699 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 5700 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 5701 ixgbe_setup_dca(adapter);
5702 }
5703#endif
0365e6e4
PW		 5704 /* add san mac addr to netdev */
5705 ixgbe_add_sanmac_netdev(netdev);
9a799d71
AK		 5706
5707 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5708 cards_found++;
5709 return 0;
5710
5711err_register:
5eba3699 5712 ixgbe_release_hw_control(adapter);
7a921c93 5713 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 5714err_sw_init:
5715err_eeprom:
c4900be0
DS		 5716 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5717 del_timer_sync(&adapter->sfp_timer);
5718 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5719 cancel_work_sync(&adapter->multispeed_fiber_task);
5720 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 5721 iounmap(hw->hw_addr);
5722err_ioremap:
5723 free_netdev(netdev);
5724err_alloc_etherdev:
9ce77666 5725 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5726 IORESOURCE_MEM));
9a799d71
AK		 5727err_pci_reg:
5728err_dma:
5729 pci_disable_device(pdev);
5730 return err;
5731}
5732
5733/**
5734 * ixgbe_remove - Device Removal Routine
5735 * @pdev: PCI device information struct
5736 *
5737 * ixgbe_remove is called by the PCI subsystem to alert the driver
5738 * that it should release a PCI device. The could be caused by a
5739 * Hot-Plug event, or because the driver is going to be removed from
5740 * memory.
5741 **/
5742static void __devexit ixgbe_remove(struct pci_dev *pdev)
5743{
5744 struct net_device *netdev = pci_get_drvdata(pdev);
5745 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715 5746 int err;
9a799d71
AK		 5747
5748 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 5749 /* clear the module not found bit to make sure the worker won't
5750 * reschedule
5751 */
5752 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 5753 del_timer_sync(&adapter->watchdog_timer);
5754
c4900be0
DS		 5755 del_timer_sync(&adapter->sfp_timer);
5756 cancel_work_sync(&adapter->watchdog_task);
5757 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5758 cancel_work_sync(&adapter->multispeed_fiber_task);
5759 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 5760 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5761 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5762 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 5763 flush_scheduled_work();
5764
5dd2d332 5765#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5766 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5767 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5768 dca_remove_requester(&pdev->dev);
5769 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5770 }
5771
5772#endif
332d4a7d
YZ		 5773#ifdef IXGBE_FCOE
5774 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5775 ixgbe_cleanup_fcoe(adapter);
5776
5777#endif /* IXGBE_FCOE */
0365e6e4
PW		 5778
5779 /* remove the added san mac */
5780 ixgbe_del_sanmac_netdev(netdev);
5781
c4900be0
DS		 5782 if (netdev->reg_state == NETREG_REGISTERED)
5783 unregister_netdev(netdev);
9a799d71 5784
7a921c93 5785 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 5786
021230d4 5787 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5788
5789 iounmap(adapter->hw.hw_addr);
9ce77666 5790 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5791 IORESOURCE_MEM));
9a799d71 5792
021230d4 5793 DPRINTK(PROBE, INFO, "complete\n");
021230d4 5794
9a799d71
AK		 5795 free_netdev(netdev);
5796
6fabd715
PWJ		 5797 err = pci_disable_pcie_error_reporting(pdev);
5798 if (err)
5799 dev_err(&pdev->dev,
5800 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5801
9a799d71
AK		 5802 pci_disable_device(pdev);
5803}
5804
5805/**
5806 * ixgbe_io_error_detected - called when PCI error is detected
5807 * @pdev: Pointer to PCI device
5808 * @state: The current pci connection state
5809 *
5810 * This function is called after a PCI bus error affecting
5811 * this device has been detected.
5812 */
5813static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 5814 pci_channel_state_t state)
9a799d71
AK		 5815{
5816 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5817 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5818
5819 netif_device_detach(netdev);
5820
3044b8d1
BL		 5821 if (state == pci_channel_io_perm_failure)
5822 return PCI_ERS_RESULT_DISCONNECT;
5823
9a799d71
AK		 5824 if (netif_running(netdev))
5825 ixgbe_down(adapter);
5826 pci_disable_device(pdev);
5827
b4617240 5828 /* Request a slot reset. */
9a799d71
AK		 5829 return PCI_ERS_RESULT_NEED_RESET;
5830}
5831
5832/**
5833 * ixgbe_io_slot_reset - called after the pci bus has been reset.
5834 * @pdev: Pointer to PCI device
5835 *
5836 * Restart the card from scratch, as if from a cold-boot.
5837 */
5838static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5839{
5840 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5841 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 5842 pci_ers_result_t result;
5843 int err;
9a799d71 5844
9ce77666 5845 if (pci_enable_device_mem(pdev)) {
9a799d71 5846 DPRINTK(PROBE, ERR,
b4617240 5847 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 5848 result = PCI_ERS_RESULT_DISCONNECT;
5849 } else {
5850 pci_set_master(pdev);
5851 pci_restore_state(pdev);
9a799d71 5852
dd4d8ca6 5853 pci_wake_from_d3(pdev, false);
9a799d71 5854
6fabd715 5855 ixgbe_reset(adapter);
88512539 5856 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 5857 result = PCI_ERS_RESULT_RECOVERED;
5858 }
5859
5860 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5861 if (err) {
5862 dev_err(&pdev->dev,
5863 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5864 /* non-fatal, continue */
5865 }
9a799d71 5866
6fabd715 5867 return result;
9a799d71
AK		 5868}
5869
5870/**
5871 * ixgbe_io_resume - called when traffic can start flowing again.
5872 * @pdev: Pointer to PCI device
5873 *
5874 * This callback is called when the error recovery driver tells us that
5875 * its OK to resume normal operation.
5876 */
5877static void ixgbe_io_resume(struct pci_dev *pdev)
5878{
5879 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5880 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5881
5882 if (netif_running(netdev)) {
5883 if (ixgbe_up(adapter)) {
5884 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5885 return;
5886 }
5887 }
5888
5889 netif_device_attach(netdev);
9a799d71
AK		 5890}
5891
5892static struct pci_error_handlers ixgbe_err_handler = {
5893 .error_detected = ixgbe_io_error_detected,
5894 .slot_reset = ixgbe_io_slot_reset,
5895 .resume = ixgbe_io_resume,
5896};
5897
5898static struct pci_driver ixgbe_driver = {
5899 .name = ixgbe_driver_name,
5900 .id_table = ixgbe_pci_tbl,
5901 .probe = ixgbe_probe,
5902 .remove = __devexit_p(ixgbe_remove),
5903#ifdef CONFIG_PM
5904 .suspend = ixgbe_suspend,
5905 .resume = ixgbe_resume,
5906#endif
5907 .shutdown = ixgbe_shutdown,
5908 .err_handler = &ixgbe_err_handler
5909};
5910
5911/**
5912 * ixgbe_init_module - Driver Registration Routine
5913 *
5914 * ixgbe_init_module is the first routine called when the driver is
5915 * loaded. All it does is register with the PCI subsystem.
5916 **/
5917static int __init ixgbe_init_module(void)
5918{
5919 int ret;
5920 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5921 ixgbe_driver_string, ixgbe_driver_version);
5922
5923 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5924
5dd2d332 5925#ifdef CONFIG_IXGBE_DCA
bd0362dd 5926 dca_register_notify(&dca_notifier);
bd0362dd 5927#endif
5dd2d332 5928
9a799d71
AK		 5929 ret = pci_register_driver(&ixgbe_driver);
5930 return ret;
5931}
b4617240 5932
9a799d71
AK		 5933module_init(ixgbe_init_module);
5934
5935/**
5936 * ixgbe_exit_module - Driver Exit Cleanup Routine
5937 *
5938 * ixgbe_exit_module is called just before the driver is removed
5939 * from memory.
5940 **/
5941static void __exit ixgbe_exit_module(void)
5942{
5dd2d332 5943#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5944 dca_unregister_notify(&dca_notifier);
5945#endif
9a799d71
AK		 5946 pci_unregister_driver(&ixgbe_driver);
5947}
bd0362dd 5948
5dd2d332 5949#ifdef CONFIG_IXGBE_DCA
bd0362dd 5950static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 5951 void *p)
bd0362dd
JC		 5952{
5953 int ret_val;
5954
5955 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 5956 __ixgbe_notify_dca);
bd0362dd
JC		 5957
5958 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5959}
b453368d 5960
5dd2d332 5961#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 5962#ifdef DEBUG
5963/**
5964 * ixgbe_get_hw_dev_name - return device name string
5965 * used by hardware layer to print debugging information
5966 **/
5967char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5968{
5969 struct ixgbe_adapter *adapter = hw->back;
5970 return adapter->netdev->name;
5971}
bd0362dd 5972
b453368d 5973#endif
9a799d71
AK		 5974module_exit(ixgbe_exit_module);
5975
5976/* ixgbe_main.c */
kernel source for telekom puls (alcatel/mediatek)