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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
8c47eaa7 | 4 | Copyright(c) 1999 - 2010 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
35 | #include <linux/ip.h> | |
36 | #include <linux/tcp.h> | |
60127865 | 37 | #include <linux/pkt_sched.h> |
9a799d71 AK |
38 | #include <linux/ipv6.h> |
39 | #include <net/checksum.h> | |
40 | #include <net/ip6_checksum.h> | |
41 | #include <linux/ethtool.h> | |
42 | #include <linux/if_vlan.h> | |
eacd73f7 | 43 | #include <scsi/fc/fc_fcoe.h> |
9a799d71 AK |
44 | |
45 | #include "ixgbe.h" | |
46 | #include "ixgbe_common.h" | |
ee5f784a | 47 | #include "ixgbe_dcb_82599.h" |
1cdd1ec8 | 48 | #include "ixgbe_sriov.h" |
9a799d71 AK |
49 | |
50 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 51 | static const char ixgbe_driver_string[] = |
b4617240 | 52 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
9a799d71 | 53 | |
92eb879f | 54 | #define DRV_VERSION "2.0.62-k2" |
9c8eb720 | 55 | const char ixgbe_driver_version[] = DRV_VERSION; |
8c47eaa7 | 56 | static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation."; |
9a799d71 AK |
57 | |
58 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 59 | [board_82598] = &ixgbe_82598_info, |
e8e26350 | 60 | [board_82599] = &ixgbe_82599_info, |
9a799d71 AK |
61 | }; |
62 | ||
63 | /* ixgbe_pci_tbl - PCI Device ID Table | |
64 | * | |
65 | * Wildcard entries (PCI_ANY_ID) should come last | |
66 | * Last entry must be all 0s | |
67 | * | |
68 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
69 | * Class, Class Mask, private data (not used) } | |
70 | */ | |
a3aa1884 | 71 | static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = { |
1e336d0f DS |
72 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), |
73 | board_82598 }, | |
9a799d71 | 74 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), |
3957d63d | 75 | board_82598 }, |
9a799d71 | 76 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), |
3957d63d | 77 | board_82598 }, |
0befdb3e JB |
78 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), |
79 | board_82598 }, | |
3845bec0 PWJ |
80 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), |
81 | board_82598 }, | |
9a799d71 | 82 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), |
3957d63d | 83 | board_82598 }, |
8d792cd9 JB |
84 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), |
85 | board_82598 }, | |
c4900be0 DS |
86 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), |
87 | board_82598 }, | |
88 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), | |
89 | board_82598 }, | |
b95f5fcb JB |
90 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), |
91 | board_82598 }, | |
c4900be0 DS |
92 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), |
93 | board_82598 }, | |
2f21bdd3 DS |
94 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), |
95 | board_82598 }, | |
e8e26350 PW |
96 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), |
97 | board_82599 }, | |
1fcf03e6 PWJ |
98 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), |
99 | board_82599 }, | |
74757d49 DS |
100 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), |
101 | board_82599 }, | |
e8e26350 PW |
102 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), |
103 | board_82599 }, | |
38ad1c8e DS |
104 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), |
105 | board_82599 }, | |
dbfec662 DS |
106 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), |
107 | board_82599 }, | |
8911184f PWJ |
108 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), |
109 | board_82599 }, | |
312eb931 DS |
110 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), |
111 | board_82599 }, | |
9a799d71 AK |
112 | |
113 | /* required last entry */ | |
114 | {0, } | |
115 | }; | |
116 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
117 | ||
5dd2d332 | 118 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 119 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
b4617240 | 120 | void *p); |
bd0362dd JC |
121 | static struct notifier_block dca_notifier = { |
122 | .notifier_call = ixgbe_notify_dca, | |
123 | .next = NULL, | |
124 | .priority = 0 | |
125 | }; | |
126 | #endif | |
127 | ||
1cdd1ec8 GR |
128 | #ifdef CONFIG_PCI_IOV |
129 | static unsigned int max_vfs; | |
130 | module_param(max_vfs, uint, 0); | |
131 | MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate " | |
132 | "per physical function"); | |
133 | #endif /* CONFIG_PCI_IOV */ | |
134 | ||
9a799d71 AK |
135 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
136 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
137 | MODULE_LICENSE("GPL"); | |
138 | MODULE_VERSION(DRV_VERSION); | |
139 | ||
140 | #define DEFAULT_DEBUG_LEVEL_SHIFT 3 | |
141 | ||
1cdd1ec8 GR |
142 | static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter) |
143 | { | |
144 | struct ixgbe_hw *hw = &adapter->hw; | |
145 | u32 gcr; | |
146 | u32 gpie; | |
147 | u32 vmdctl; | |
148 | ||
149 | #ifdef CONFIG_PCI_IOV | |
150 | /* disable iov and allow time for transactions to clear */ | |
151 | pci_disable_sriov(adapter->pdev); | |
152 | #endif | |
153 | ||
154 | /* turn off device IOV mode */ | |
155 | gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); | |
156 | gcr &= ~(IXGBE_GCR_EXT_SRIOV); | |
157 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr); | |
158 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
159 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
160 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
161 | ||
162 | /* set default pool back to 0 */ | |
163 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
164 | vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; | |
165 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); | |
166 | ||
167 | /* take a breather then clean up driver data */ | |
168 | msleep(100); | |
169 | if (adapter->vfinfo) | |
170 | kfree(adapter->vfinfo); | |
171 | adapter->vfinfo = NULL; | |
172 | ||
173 | adapter->num_vfs = 0; | |
174 | adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED; | |
175 | } | |
176 | ||
5eba3699 AV |
177 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
178 | { | |
179 | u32 ctrl_ext; | |
180 | ||
181 | /* Let firmware take over control of h/w */ | |
182 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
183 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 184 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
185 | } |
186 | ||
187 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
188 | { | |
189 | u32 ctrl_ext; | |
190 | ||
191 | /* Let firmware know the driver has taken over */ | |
192 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
193 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 194 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 195 | } |
9a799d71 | 196 | |
e8e26350 PW |
197 | /* |
198 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors | |
199 | * @adapter: pointer to adapter struct | |
200 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
201 | * @queue: queue to map the corresponding interrupt to | |
202 | * @msix_vector: the vector to map to the corresponding queue | |
203 | * | |
204 | */ | |
205 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
206 | u8 queue, u8 msix_vector) | |
9a799d71 AK |
207 | { |
208 | u32 ivar, index; | |
e8e26350 PW |
209 | struct ixgbe_hw *hw = &adapter->hw; |
210 | switch (hw->mac.type) { | |
211 | case ixgbe_mac_82598EB: | |
212 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
213 | if (direction == -1) | |
214 | direction = 0; | |
215 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
216 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
217 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
218 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
219 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
220 | break; | |
221 | case ixgbe_mac_82599EB: | |
222 | if (direction == -1) { | |
223 | /* other causes */ | |
224 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
225 | index = ((queue & 1) * 8); | |
226 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
227 | ivar &= ~(0xFF << index); | |
228 | ivar |= (msix_vector << index); | |
229 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
230 | break; | |
231 | } else { | |
232 | /* tx or rx causes */ | |
233 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
234 | index = ((16 * (queue & 1)) + (8 * direction)); | |
235 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
236 | ivar &= ~(0xFF << index); | |
237 | ivar |= (msix_vector << index); | |
238 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
239 | break; | |
240 | } | |
241 | default: | |
242 | break; | |
243 | } | |
9a799d71 AK |
244 | } |
245 | ||
fe49f04a AD |
246 | static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, |
247 | u64 qmask) | |
248 | { | |
249 | u32 mask; | |
250 | ||
251 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
252 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); | |
253 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); | |
254 | } else { | |
255 | mask = (qmask & 0xFFFFFFFF); | |
256 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); | |
257 | mask = (qmask >> 32); | |
258 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); | |
259 | } | |
260 | } | |
261 | ||
9a799d71 | 262 | static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter, |
b4617240 PW |
263 | struct ixgbe_tx_buffer |
264 | *tx_buffer_info) | |
9a799d71 | 265 | { |
e5a43549 AD |
266 | if (tx_buffer_info->dma) { |
267 | if (tx_buffer_info->mapped_as_page) | |
268 | pci_unmap_page(adapter->pdev, | |
269 | tx_buffer_info->dma, | |
270 | tx_buffer_info->length, | |
271 | PCI_DMA_TODEVICE); | |
272 | else | |
273 | pci_unmap_single(adapter->pdev, | |
274 | tx_buffer_info->dma, | |
275 | tx_buffer_info->length, | |
276 | PCI_DMA_TODEVICE); | |
277 | tx_buffer_info->dma = 0; | |
278 | } | |
9a799d71 AK |
279 | if (tx_buffer_info->skb) { |
280 | dev_kfree_skb_any(tx_buffer_info->skb); | |
281 | tx_buffer_info->skb = NULL; | |
282 | } | |
44df32c5 | 283 | tx_buffer_info->time_stamp = 0; |
9a799d71 AK |
284 | /* tx_buffer_info must be completely set up in the transmit path */ |
285 | } | |
286 | ||
26f23d82 YZ |
287 | /** |
288 | * ixgbe_tx_is_paused - check if the tx ring is paused | |
289 | * @adapter: the ixgbe adapter | |
290 | * @tx_ring: the corresponding tx_ring | |
291 | * | |
292 | * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the | |
293 | * corresponding TC of this tx_ring when checking TFCS. | |
294 | * | |
295 | * Returns : true if paused | |
296 | */ | |
297 | static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter, | |
298 | struct ixgbe_ring *tx_ring) | |
299 | { | |
26f23d82 YZ |
300 | u32 txoff = IXGBE_TFCS_TXOFF; |
301 | ||
302 | #ifdef CONFIG_IXGBE_DCB | |
303 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
30b76832 | 304 | int tc; |
26f23d82 YZ |
305 | int reg_idx = tx_ring->reg_idx; |
306 | int dcb_i = adapter->ring_feature[RING_F_DCB].indices; | |
307 | ||
6837e895 PW |
308 | switch (adapter->hw.mac.type) { |
309 | case ixgbe_mac_82598EB: | |
26f23d82 YZ |
310 | tc = reg_idx >> 2; |
311 | txoff = IXGBE_TFCS_TXOFF0; | |
6837e895 PW |
312 | break; |
313 | case ixgbe_mac_82599EB: | |
26f23d82 YZ |
314 | tc = 0; |
315 | txoff = IXGBE_TFCS_TXOFF; | |
316 | if (dcb_i == 8) { | |
317 | /* TC0, TC1 */ | |
318 | tc = reg_idx >> 5; | |
319 | if (tc == 2) /* TC2, TC3 */ | |
320 | tc += (reg_idx - 64) >> 4; | |
321 | else if (tc == 3) /* TC4, TC5, TC6, TC7 */ | |
322 | tc += 1 + ((reg_idx - 96) >> 3); | |
323 | } else if (dcb_i == 4) { | |
324 | /* TC0, TC1 */ | |
325 | tc = reg_idx >> 6; | |
326 | if (tc == 1) { | |
327 | tc += (reg_idx - 64) >> 5; | |
328 | if (tc == 2) /* TC2, TC3 */ | |
329 | tc += (reg_idx - 96) >> 4; | |
330 | } | |
331 | } | |
6837e895 PW |
332 | break; |
333 | default: | |
334 | tc = 0; | |
26f23d82 YZ |
335 | } |
336 | txoff <<= tc; | |
337 | } | |
338 | #endif | |
339 | return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff; | |
340 | } | |
341 | ||
9a799d71 | 342 | static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter, |
b4617240 PW |
343 | struct ixgbe_ring *tx_ring, |
344 | unsigned int eop) | |
9a799d71 | 345 | { |
e01c31a5 | 346 | struct ixgbe_hw *hw = &adapter->hw; |
e01c31a5 | 347 | |
9a799d71 | 348 | /* Detect a transmit hang in hardware, this serializes the |
e01c31a5 | 349 | * check with the clearing of time_stamp and movement of eop */ |
9a799d71 | 350 | adapter->detect_tx_hung = false; |
44df32c5 | 351 | if (tx_ring->tx_buffer_info[eop].time_stamp && |
9a799d71 | 352 | time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) && |
26f23d82 | 353 | !ixgbe_tx_is_paused(adapter, tx_ring)) { |
9a799d71 | 354 | /* detected Tx unit hang */ |
e01c31a5 JB |
355 | union ixgbe_adv_tx_desc *tx_desc; |
356 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
9a799d71 | 357 | DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n" |
e01c31a5 JB |
358 | " Tx Queue <%d>\n" |
359 | " TDH, TDT <%x>, <%x>\n" | |
9a799d71 AK |
360 | " next_to_use <%x>\n" |
361 | " next_to_clean <%x>\n" | |
362 | "tx_buffer_info[next_to_clean]\n" | |
363 | " time_stamp <%lx>\n" | |
e01c31a5 JB |
364 | " jiffies <%lx>\n", |
365 | tx_ring->queue_index, | |
44df32c5 AD |
366 | IXGBE_READ_REG(hw, tx_ring->head), |
367 | IXGBE_READ_REG(hw, tx_ring->tail), | |
e01c31a5 JB |
368 | tx_ring->next_to_use, eop, |
369 | tx_ring->tx_buffer_info[eop].time_stamp, jiffies); | |
9a799d71 AK |
370 | return true; |
371 | } | |
372 | ||
373 | return false; | |
374 | } | |
375 | ||
b4617240 PW |
376 | #define IXGBE_MAX_TXD_PWR 14 |
377 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
e092be60 AV |
378 | |
379 | /* Tx Descriptors needed, worst case */ | |
380 | #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \ | |
381 | (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0)) | |
382 | #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \ | |
b4617240 | 383 | MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */ |
e092be60 | 384 | |
e01c31a5 JB |
385 | static void ixgbe_tx_timeout(struct net_device *netdev); |
386 | ||
9a799d71 AK |
387 | /** |
388 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
fe49f04a | 389 | * @q_vector: structure containing interrupt and ring information |
e01c31a5 | 390 | * @tx_ring: tx ring to clean |
9a799d71 | 391 | **/ |
fe49f04a | 392 | static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, |
e01c31a5 | 393 | struct ixgbe_ring *tx_ring) |
9a799d71 | 394 | { |
fe49f04a | 395 | struct ixgbe_adapter *adapter = q_vector->adapter; |
e01c31a5 | 396 | struct net_device *netdev = adapter->netdev; |
12207e49 PWJ |
397 | union ixgbe_adv_tx_desc *tx_desc, *eop_desc; |
398 | struct ixgbe_tx_buffer *tx_buffer_info; | |
399 | unsigned int i, eop, count = 0; | |
e01c31a5 | 400 | unsigned int total_bytes = 0, total_packets = 0; |
9a799d71 AK |
401 | |
402 | i = tx_ring->next_to_clean; | |
12207e49 PWJ |
403 | eop = tx_ring->tx_buffer_info[i].next_to_watch; |
404 | eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
405 | ||
406 | while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) && | |
9a1a69ad | 407 | (count < tx_ring->work_limit)) { |
12207e49 PWJ |
408 | bool cleaned = false; |
409 | for ( ; !cleaned; count++) { | |
410 | struct sk_buff *skb; | |
9a799d71 AK |
411 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); |
412 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
12207e49 | 413 | cleaned = (i == eop); |
e01c31a5 | 414 | skb = tx_buffer_info->skb; |
9a799d71 | 415 | |
12207e49 | 416 | if (cleaned && skb) { |
e092be60 | 417 | unsigned int segs, bytecount; |
3d8fd385 | 418 | unsigned int hlen = skb_headlen(skb); |
e01c31a5 JB |
419 | |
420 | /* gso_segs is currently only valid for tcp */ | |
e092be60 | 421 | segs = skb_shinfo(skb)->gso_segs ?: 1; |
3d8fd385 YZ |
422 | #ifdef IXGBE_FCOE |
423 | /* adjust for FCoE Sequence Offload */ | |
424 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
425 | && (skb->protocol == htons(ETH_P_FCOE)) && | |
426 | skb_is_gso(skb)) { | |
427 | hlen = skb_transport_offset(skb) + | |
428 | sizeof(struct fc_frame_header) + | |
429 | sizeof(struct fcoe_crc_eof); | |
430 | segs = DIV_ROUND_UP(skb->len - hlen, | |
431 | skb_shinfo(skb)->gso_size); | |
432 | } | |
433 | #endif /* IXGBE_FCOE */ | |
e092be60 | 434 | /* multiply data chunks by size of headers */ |
3d8fd385 | 435 | bytecount = ((segs - 1) * hlen) + skb->len; |
e01c31a5 JB |
436 | total_packets += segs; |
437 | total_bytes += bytecount; | |
e092be60 | 438 | } |
e01c31a5 | 439 | |
9a799d71 | 440 | ixgbe_unmap_and_free_tx_resource(adapter, |
e01c31a5 | 441 | tx_buffer_info); |
9a799d71 | 442 | |
12207e49 PWJ |
443 | tx_desc->wb.status = 0; |
444 | ||
9a799d71 AK |
445 | i++; |
446 | if (i == tx_ring->count) | |
447 | i = 0; | |
e01c31a5 | 448 | } |
12207e49 PWJ |
449 | |
450 | eop = tx_ring->tx_buffer_info[i].next_to_watch; | |
451 | eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
452 | } | |
453 | ||
9a799d71 AK |
454 | tx_ring->next_to_clean = i; |
455 | ||
e092be60 | 456 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
e01c31a5 JB |
457 | if (unlikely(count && netif_carrier_ok(netdev) && |
458 | (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { | |
e092be60 AV |
459 | /* Make sure that anybody stopping the queue after this |
460 | * sees the new next_to_clean. | |
461 | */ | |
462 | smp_mb(); | |
30eba97a AV |
463 | if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && |
464 | !test_bit(__IXGBE_DOWN, &adapter->state)) { | |
465 | netif_wake_subqueue(netdev, tx_ring->queue_index); | |
7ca3bc58 | 466 | ++tx_ring->restart_queue; |
30eba97a | 467 | } |
e092be60 | 468 | } |
9a799d71 | 469 | |
e01c31a5 JB |
470 | if (adapter->detect_tx_hung) { |
471 | if (ixgbe_check_tx_hang(adapter, tx_ring, i)) { | |
472 | /* schedule immediate reset if we believe we hung */ | |
473 | DPRINTK(PROBE, INFO, | |
474 | "tx hang %d detected, resetting adapter\n", | |
475 | adapter->tx_timeout_count + 1); | |
476 | ixgbe_tx_timeout(adapter->netdev); | |
477 | } | |
478 | } | |
9a799d71 | 479 | |
e01c31a5 | 480 | /* re-arm the interrupt */ |
fe49f04a AD |
481 | if (count >= tx_ring->work_limit) |
482 | ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
9a799d71 | 483 | |
e01c31a5 JB |
484 | tx_ring->total_bytes += total_bytes; |
485 | tx_ring->total_packets += total_packets; | |
e01c31a5 | 486 | tx_ring->stats.packets += total_packets; |
12207e49 | 487 | tx_ring->stats.bytes += total_bytes; |
9a1a69ad | 488 | return (count < tx_ring->work_limit); |
9a799d71 AK |
489 | } |
490 | ||
5dd2d332 | 491 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 492 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
b4617240 | 493 | struct ixgbe_ring *rx_ring) |
bd0362dd JC |
494 | { |
495 | u32 rxctrl; | |
496 | int cpu = get_cpu(); | |
4a0b9ca0 | 497 | int q = rx_ring->reg_idx; |
bd0362dd | 498 | |
3a581073 | 499 | if (rx_ring->cpu != cpu) { |
bd0362dd | 500 | rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q)); |
e8e26350 PW |
501 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
502 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK; | |
503 | rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
504 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
505 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599; | |
506 | rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
507 | IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599); | |
508 | } | |
bd0362dd JC |
509 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN; |
510 | rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN; | |
15005a32 DS |
511 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN); |
512 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN | | |
e8e26350 | 513 | IXGBE_DCA_RXCTRL_DESC_HSRO_EN); |
bd0362dd | 514 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl); |
3a581073 | 515 | rx_ring->cpu = cpu; |
bd0362dd JC |
516 | } |
517 | put_cpu(); | |
518 | } | |
519 | ||
520 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, | |
b4617240 | 521 | struct ixgbe_ring *tx_ring) |
bd0362dd JC |
522 | { |
523 | u32 txctrl; | |
524 | int cpu = get_cpu(); | |
4a0b9ca0 | 525 | int q = tx_ring->reg_idx; |
ee5f784a | 526 | struct ixgbe_hw *hw = &adapter->hw; |
bd0362dd | 527 | |
3a581073 | 528 | if (tx_ring->cpu != cpu) { |
e8e26350 | 529 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
ee5f784a | 530 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q)); |
e8e26350 PW |
531 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK; |
532 | txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
ee5f784a DS |
533 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; |
534 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl); | |
e8e26350 | 535 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
ee5f784a | 536 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q)); |
e8e26350 PW |
537 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599; |
538 | txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
ee5f784a DS |
539 | IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599); |
540 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; | |
541 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl); | |
e8e26350 | 542 | } |
3a581073 | 543 | tx_ring->cpu = cpu; |
bd0362dd JC |
544 | } |
545 | put_cpu(); | |
546 | } | |
547 | ||
548 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
549 | { | |
550 | int i; | |
551 | ||
552 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
553 | return; | |
554 | ||
e35ec126 AD |
555 | /* always use CB2 mode, difference is masked in the CB driver */ |
556 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
557 | ||
bd0362dd | 558 | for (i = 0; i < adapter->num_tx_queues; i++) { |
4a0b9ca0 PW |
559 | adapter->tx_ring[i]->cpu = -1; |
560 | ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]); | |
bd0362dd JC |
561 | } |
562 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
4a0b9ca0 PW |
563 | adapter->rx_ring[i]->cpu = -1; |
564 | ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]); | |
bd0362dd JC |
565 | } |
566 | } | |
567 | ||
568 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
569 | { | |
570 | struct net_device *netdev = dev_get_drvdata(dev); | |
571 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
572 | unsigned long event = *(unsigned long *)data; | |
573 | ||
574 | switch (event) { | |
575 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
576 | /* if we're already enabled, don't do it again */ |
577 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
578 | break; | |
652f093f | 579 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 580 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
581 | ixgbe_setup_dca(adapter); |
582 | break; | |
583 | } | |
584 | /* Fall Through since DCA is disabled. */ | |
585 | case DCA_PROVIDER_REMOVE: | |
586 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
587 | dca_remove_requester(dev); | |
588 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
589 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
590 | } | |
591 | break; | |
592 | } | |
593 | ||
652f093f | 594 | return 0; |
bd0362dd JC |
595 | } |
596 | ||
5dd2d332 | 597 | #endif /* CONFIG_IXGBE_DCA */ |
9a799d71 AK |
598 | /** |
599 | * ixgbe_receive_skb - Send a completed packet up the stack | |
600 | * @adapter: board private structure | |
601 | * @skb: packet to send up | |
177db6ff MC |
602 | * @status: hardware indication of status of receive |
603 | * @rx_ring: rx descriptor ring (for a specific queue) to setup | |
604 | * @rx_desc: rx descriptor | |
9a799d71 | 605 | **/ |
78b6f4ce | 606 | static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector, |
b4617240 | 607 | struct sk_buff *skb, u8 status, |
fdaff1ce | 608 | struct ixgbe_ring *ring, |
177db6ff | 609 | union ixgbe_adv_rx_desc *rx_desc) |
9a799d71 | 610 | { |
78b6f4ce HX |
611 | struct ixgbe_adapter *adapter = q_vector->adapter; |
612 | struct napi_struct *napi = &q_vector->napi; | |
177db6ff MC |
613 | bool is_vlan = (status & IXGBE_RXD_STAT_VP); |
614 | u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan); | |
9a799d71 | 615 | |
fdaff1ce | 616 | skb_record_rx_queue(skb, ring->queue_index); |
182ff8df | 617 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) { |
8a62babf | 618 | if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK)) |
78b6f4ce | 619 | vlan_gro_receive(napi, adapter->vlgrp, tag, skb); |
9a799d71 | 620 | else |
78b6f4ce | 621 | napi_gro_receive(napi, skb); |
177db6ff | 622 | } else { |
8a62babf | 623 | if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK)) |
182ff8df AD |
624 | vlan_hwaccel_rx(skb, adapter->vlgrp, tag); |
625 | else | |
626 | netif_rx(skb); | |
9a799d71 AK |
627 | } |
628 | } | |
629 | ||
e59bd25d AV |
630 | /** |
631 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
632 | * @adapter: address of board private structure | |
633 | * @status_err: hardware indication of status of receive | |
634 | * @skb: skb currently being received and modified | |
635 | **/ | |
9a799d71 | 636 | static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter, |
8bae1b2b DS |
637 | union ixgbe_adv_rx_desc *rx_desc, |
638 | struct sk_buff *skb) | |
9a799d71 | 639 | { |
8bae1b2b DS |
640 | u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error); |
641 | ||
9a799d71 AK |
642 | skb->ip_summed = CHECKSUM_NONE; |
643 | ||
712744be JB |
644 | /* Rx csum disabled */ |
645 | if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED)) | |
9a799d71 | 646 | return; |
e59bd25d AV |
647 | |
648 | /* if IP and error */ | |
649 | if ((status_err & IXGBE_RXD_STAT_IPCS) && | |
650 | (status_err & IXGBE_RXDADV_ERR_IPE)) { | |
9a799d71 AK |
651 | adapter->hw_csum_rx_error++; |
652 | return; | |
653 | } | |
e59bd25d AV |
654 | |
655 | if (!(status_err & IXGBE_RXD_STAT_L4CS)) | |
656 | return; | |
657 | ||
658 | if (status_err & IXGBE_RXDADV_ERR_TCPE) { | |
8bae1b2b DS |
659 | u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; |
660 | ||
661 | /* | |
662 | * 82599 errata, UDP frames with a 0 checksum can be marked as | |
663 | * checksum errors. | |
664 | */ | |
665 | if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) && | |
666 | (adapter->hw.mac.type == ixgbe_mac_82599EB)) | |
667 | return; | |
668 | ||
e59bd25d AV |
669 | adapter->hw_csum_rx_error++; |
670 | return; | |
671 | } | |
672 | ||
9a799d71 | 673 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 674 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
675 | } |
676 | ||
e8e26350 PW |
677 | static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw, |
678 | struct ixgbe_ring *rx_ring, u32 val) | |
679 | { | |
680 | /* | |
681 | * Force memory writes to complete before letting h/w | |
682 | * know there are new descriptors to fetch. (Only | |
683 | * applicable for weak-ordered memory model archs, | |
684 | * such as IA-64). | |
685 | */ | |
686 | wmb(); | |
687 | IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val); | |
688 | } | |
689 | ||
9a799d71 AK |
690 | /** |
691 | * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split | |
692 | * @adapter: address of board private structure | |
693 | **/ | |
694 | static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter, | |
7c6e0a43 JB |
695 | struct ixgbe_ring *rx_ring, |
696 | int cleaned_count) | |
9a799d71 | 697 | { |
9a799d71 AK |
698 | struct pci_dev *pdev = adapter->pdev; |
699 | union ixgbe_adv_rx_desc *rx_desc; | |
3a581073 | 700 | struct ixgbe_rx_buffer *bi; |
9a799d71 | 701 | unsigned int i; |
9a799d71 AK |
702 | |
703 | i = rx_ring->next_to_use; | |
3a581073 | 704 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 AK |
705 | |
706 | while (cleaned_count--) { | |
707 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
708 | ||
762f4c57 | 709 | if (!bi->page_dma && |
6e455b89 | 710 | (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) { |
3a581073 | 711 | if (!bi->page) { |
762f4c57 JB |
712 | bi->page = alloc_page(GFP_ATOMIC); |
713 | if (!bi->page) { | |
714 | adapter->alloc_rx_page_failed++; | |
715 | goto no_buffers; | |
716 | } | |
717 | bi->page_offset = 0; | |
718 | } else { | |
719 | /* use a half page if we're re-using */ | |
720 | bi->page_offset ^= (PAGE_SIZE / 2); | |
9a799d71 | 721 | } |
762f4c57 JB |
722 | |
723 | bi->page_dma = pci_map_page(pdev, bi->page, | |
724 | bi->page_offset, | |
725 | (PAGE_SIZE / 2), | |
726 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
727 | } |
728 | ||
3a581073 | 729 | if (!bi->skb) { |
5ecc3614 | 730 | struct sk_buff *skb; |
7ca3bc58 JB |
731 | /* netdev_alloc_skb reserves 32 bytes up front!! */ |
732 | uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES; | |
733 | skb = netdev_alloc_skb(adapter->netdev, bufsz); | |
9a799d71 AK |
734 | |
735 | if (!skb) { | |
736 | adapter->alloc_rx_buff_failed++; | |
737 | goto no_buffers; | |
738 | } | |
739 | ||
7ca3bc58 JB |
740 | /* advance the data pointer to the next cache line */ |
741 | skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES) | |
742 | - skb->data)); | |
743 | ||
3a581073 | 744 | bi->skb = skb; |
4f57ca6e JB |
745 | bi->dma = pci_map_single(pdev, skb->data, |
746 | rx_ring->rx_buf_len, | |
3a581073 | 747 | PCI_DMA_FROMDEVICE); |
9a799d71 AK |
748 | } |
749 | /* Refresh the desc even if buffer_addrs didn't change because | |
750 | * each write-back erases this info. */ | |
6e455b89 | 751 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) { |
3a581073 JB |
752 | rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma); |
753 | rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); | |
9a799d71 | 754 | } else { |
3a581073 | 755 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma); |
9a799d71 AK |
756 | } |
757 | ||
758 | i++; | |
759 | if (i == rx_ring->count) | |
760 | i = 0; | |
3a581073 | 761 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 | 762 | } |
7c6e0a43 | 763 | |
9a799d71 AK |
764 | no_buffers: |
765 | if (rx_ring->next_to_use != i) { | |
766 | rx_ring->next_to_use = i; | |
767 | if (i-- == 0) | |
768 | i = (rx_ring->count - 1); | |
769 | ||
e8e26350 | 770 | ixgbe_release_rx_desc(&adapter->hw, rx_ring, i); |
9a799d71 AK |
771 | } |
772 | } | |
773 | ||
7c6e0a43 JB |
774 | static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc) |
775 | { | |
776 | return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info; | |
777 | } | |
778 | ||
779 | static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc) | |
780 | { | |
781 | return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
782 | } | |
783 | ||
f8212f97 AD |
784 | static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc) |
785 | { | |
786 | return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) & | |
787 | IXGBE_RXDADV_RSCCNT_MASK) >> | |
788 | IXGBE_RXDADV_RSCCNT_SHIFT; | |
789 | } | |
790 | ||
791 | /** | |
792 | * ixgbe_transform_rsc_queue - change rsc queue into a full packet | |
793 | * @skb: pointer to the last skb in the rsc queue | |
94b982b2 | 794 | * @count: pointer to number of packets coalesced in this context |
f8212f97 AD |
795 | * |
796 | * This function changes a queue full of hw rsc buffers into a completed | |
797 | * packet. It uses the ->prev pointers to find the first packet and then | |
798 | * turns it into the frag list owner. | |
799 | **/ | |
94b982b2 MC |
800 | static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb, |
801 | u64 *count) | |
f8212f97 AD |
802 | { |
803 | unsigned int frag_list_size = 0; | |
804 | ||
805 | while (skb->prev) { | |
806 | struct sk_buff *prev = skb->prev; | |
807 | frag_list_size += skb->len; | |
808 | skb->prev = NULL; | |
809 | skb = prev; | |
94b982b2 | 810 | *count += 1; |
f8212f97 AD |
811 | } |
812 | ||
813 | skb_shinfo(skb)->frag_list = skb->next; | |
814 | skb->next = NULL; | |
815 | skb->len += frag_list_size; | |
816 | skb->data_len += frag_list_size; | |
817 | skb->truesize += frag_list_size; | |
818 | return skb; | |
819 | } | |
820 | ||
43634e82 MC |
821 | struct ixgbe_rsc_cb { |
822 | dma_addr_t dma; | |
823 | }; | |
824 | ||
825 | #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb) | |
826 | ||
78b6f4ce | 827 | static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
b4617240 PW |
828 | struct ixgbe_ring *rx_ring, |
829 | int *work_done, int work_to_do) | |
9a799d71 | 830 | { |
78b6f4ce | 831 | struct ixgbe_adapter *adapter = q_vector->adapter; |
2d86f139 | 832 | struct net_device *netdev = adapter->netdev; |
9a799d71 AK |
833 | struct pci_dev *pdev = adapter->pdev; |
834 | union ixgbe_adv_rx_desc *rx_desc, *next_rxd; | |
835 | struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer; | |
836 | struct sk_buff *skb; | |
f8212f97 | 837 | unsigned int i, rsc_count = 0; |
7c6e0a43 | 838 | u32 len, staterr; |
177db6ff MC |
839 | u16 hdr_info; |
840 | bool cleaned = false; | |
9a799d71 | 841 | int cleaned_count = 0; |
d2f4fbe2 | 842 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
3d8fd385 YZ |
843 | #ifdef IXGBE_FCOE |
844 | int ddp_bytes = 0; | |
845 | #endif /* IXGBE_FCOE */ | |
9a799d71 AK |
846 | |
847 | i = rx_ring->next_to_clean; | |
9a799d71 AK |
848 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); |
849 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
850 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
9a799d71 AK |
851 | |
852 | while (staterr & IXGBE_RXD_STAT_DD) { | |
7c6e0a43 | 853 | u32 upper_len = 0; |
9a799d71 AK |
854 | if (*work_done >= work_to_do) |
855 | break; | |
856 | (*work_done)++; | |
857 | ||
3c945e5b | 858 | rmb(); /* read descriptor and rx_buffer_info after status DD */ |
6e455b89 | 859 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) { |
7c6e0a43 JB |
860 | hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc)); |
861 | len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >> | |
762f4c57 | 862 | IXGBE_RXDADV_HDRBUFLEN_SHIFT; |
9a799d71 AK |
863 | if (len > IXGBE_RX_HDR_SIZE) |
864 | len = IXGBE_RX_HDR_SIZE; | |
865 | upper_len = le16_to_cpu(rx_desc->wb.upper.length); | |
7c6e0a43 | 866 | } else { |
9a799d71 | 867 | len = le16_to_cpu(rx_desc->wb.upper.length); |
7c6e0a43 | 868 | } |
9a799d71 AK |
869 | |
870 | cleaned = true; | |
871 | skb = rx_buffer_info->skb; | |
7ca3bc58 | 872 | prefetch(skb->data); |
9a799d71 AK |
873 | rx_buffer_info->skb = NULL; |
874 | ||
21fa4e66 | 875 | if (rx_buffer_info->dma) { |
43634e82 MC |
876 | if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) && |
877 | (!(staterr & IXGBE_RXD_STAT_EOP)) && | |
878 | (!(skb->prev))) | |
879 | /* | |
880 | * When HWRSC is enabled, delay unmapping | |
881 | * of the first packet. It carries the | |
882 | * header information, HW may still | |
883 | * access the header after the writeback. | |
884 | * Only unmap it when EOP is reached | |
885 | */ | |
886 | IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma; | |
887 | else | |
888 | pci_unmap_single(pdev, rx_buffer_info->dma, | |
889 | rx_ring->rx_buf_len, | |
890 | PCI_DMA_FROMDEVICE); | |
4f57ca6e | 891 | rx_buffer_info->dma = 0; |
9a799d71 AK |
892 | skb_put(skb, len); |
893 | } | |
894 | ||
895 | if (upper_len) { | |
896 | pci_unmap_page(pdev, rx_buffer_info->page_dma, | |
762f4c57 | 897 | PAGE_SIZE / 2, PCI_DMA_FROMDEVICE); |
9a799d71 AK |
898 | rx_buffer_info->page_dma = 0; |
899 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
762f4c57 JB |
900 | rx_buffer_info->page, |
901 | rx_buffer_info->page_offset, | |
902 | upper_len); | |
903 | ||
904 | if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) || | |
905 | (page_count(rx_buffer_info->page) != 1)) | |
906 | rx_buffer_info->page = NULL; | |
907 | else | |
908 | get_page(rx_buffer_info->page); | |
9a799d71 AK |
909 | |
910 | skb->len += upper_len; | |
911 | skb->data_len += upper_len; | |
912 | skb->truesize += upper_len; | |
913 | } | |
914 | ||
915 | i++; | |
916 | if (i == rx_ring->count) | |
917 | i = 0; | |
9a799d71 AK |
918 | |
919 | next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
920 | prefetch(next_rxd); | |
9a799d71 | 921 | cleaned_count++; |
f8212f97 | 922 | |
0c19d6af | 923 | if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) |
f8212f97 AD |
924 | rsc_count = ixgbe_get_rsc_count(rx_desc); |
925 | ||
926 | if (rsc_count) { | |
927 | u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >> | |
928 | IXGBE_RXDADV_NEXTP_SHIFT; | |
929 | next_buffer = &rx_ring->rx_buffer_info[nextp]; | |
f8212f97 AD |
930 | } else { |
931 | next_buffer = &rx_ring->rx_buffer_info[i]; | |
932 | } | |
933 | ||
9a799d71 | 934 | if (staterr & IXGBE_RXD_STAT_EOP) { |
f8212f97 | 935 | if (skb->prev) |
94b982b2 MC |
936 | skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count)); |
937 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { | |
fd3686a8 | 938 | if (IXGBE_RSC_CB(skb)->dma) { |
43634e82 MC |
939 | pci_unmap_single(pdev, IXGBE_RSC_CB(skb)->dma, |
940 | rx_ring->rx_buf_len, | |
941 | PCI_DMA_FROMDEVICE); | |
fd3686a8 MC |
942 | IXGBE_RSC_CB(skb)->dma = 0; |
943 | } | |
94b982b2 MC |
944 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) |
945 | rx_ring->rsc_count += skb_shinfo(skb)->nr_frags; | |
946 | else | |
947 | rx_ring->rsc_count++; | |
948 | rx_ring->rsc_flush++; | |
949 | } | |
9a799d71 AK |
950 | rx_ring->stats.packets++; |
951 | rx_ring->stats.bytes += skb->len; | |
952 | } else { | |
6e455b89 | 953 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) { |
f8212f97 AD |
954 | rx_buffer_info->skb = next_buffer->skb; |
955 | rx_buffer_info->dma = next_buffer->dma; | |
956 | next_buffer->skb = skb; | |
957 | next_buffer->dma = 0; | |
958 | } else { | |
959 | skb->next = next_buffer->skb; | |
960 | skb->next->prev = skb; | |
961 | } | |
7ca3bc58 | 962 | rx_ring->non_eop_descs++; |
9a799d71 AK |
963 | goto next_desc; |
964 | } | |
965 | ||
966 | if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) { | |
967 | dev_kfree_skb_irq(skb); | |
968 | goto next_desc; | |
969 | } | |
970 | ||
8bae1b2b | 971 | ixgbe_rx_checksum(adapter, rx_desc, skb); |
d2f4fbe2 AV |
972 | |
973 | /* probably a little skewed due to removing CRC */ | |
974 | total_rx_bytes += skb->len; | |
975 | total_rx_packets++; | |
976 | ||
74ce8dd2 | 977 | skb->protocol = eth_type_trans(skb, adapter->netdev); |
332d4a7d YZ |
978 | #ifdef IXGBE_FCOE |
979 | /* if ddp, not passing to ULD unless for FCP_RSP or error */ | |
3d8fd385 YZ |
980 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { |
981 | ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); | |
982 | if (!ddp_bytes) | |
332d4a7d | 983 | goto next_desc; |
3d8fd385 | 984 | } |
332d4a7d | 985 | #endif /* IXGBE_FCOE */ |
fdaff1ce | 986 | ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc); |
9a799d71 AK |
987 | |
988 | next_desc: | |
989 | rx_desc->wb.upper.status_error = 0; | |
990 | ||
991 | /* return some buffers to hardware, one at a time is too slow */ | |
992 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
993 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
994 | cleaned_count = 0; | |
995 | } | |
996 | ||
997 | /* use prefetched values */ | |
998 | rx_desc = next_rxd; | |
f8212f97 | 999 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; |
9a799d71 AK |
1000 | |
1001 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
177db6ff MC |
1002 | } |
1003 | ||
9a799d71 AK |
1004 | rx_ring->next_to_clean = i; |
1005 | cleaned_count = IXGBE_DESC_UNUSED(rx_ring); | |
1006 | ||
1007 | if (cleaned_count) | |
1008 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
1009 | ||
3d8fd385 YZ |
1010 | #ifdef IXGBE_FCOE |
1011 | /* include DDPed FCoE data */ | |
1012 | if (ddp_bytes > 0) { | |
1013 | unsigned int mss; | |
1014 | ||
1015 | mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) - | |
1016 | sizeof(struct fc_frame_header) - | |
1017 | sizeof(struct fcoe_crc_eof); | |
1018 | if (mss > 512) | |
1019 | mss &= ~511; | |
1020 | total_rx_bytes += ddp_bytes; | |
1021 | total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss); | |
1022 | } | |
1023 | #endif /* IXGBE_FCOE */ | |
1024 | ||
f494e8fa AV |
1025 | rx_ring->total_packets += total_rx_packets; |
1026 | rx_ring->total_bytes += total_rx_bytes; | |
2d86f139 AK |
1027 | netdev->stats.rx_bytes += total_rx_bytes; |
1028 | netdev->stats.rx_packets += total_rx_packets; | |
f494e8fa | 1029 | |
9a799d71 AK |
1030 | return cleaned; |
1031 | } | |
1032 | ||
021230d4 | 1033 | static int ixgbe_clean_rxonly(struct napi_struct *, int); |
9a799d71 AK |
1034 | /** |
1035 | * ixgbe_configure_msix - Configure MSI-X hardware | |
1036 | * @adapter: board private structure | |
1037 | * | |
1038 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
1039 | * interrupts. | |
1040 | **/ | |
1041 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
1042 | { | |
021230d4 AV |
1043 | struct ixgbe_q_vector *q_vector; |
1044 | int i, j, q_vectors, v_idx, r_idx; | |
1045 | u32 mask; | |
9a799d71 | 1046 | |
021230d4 | 1047 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 | 1048 | |
4df10466 JB |
1049 | /* |
1050 | * Populate the IVAR table and set the ITR values to the | |
021230d4 AV |
1051 | * corresponding register. |
1052 | */ | |
1053 | for (v_idx = 0; v_idx < q_vectors; v_idx++) { | |
7a921c93 | 1054 | q_vector = adapter->q_vector[v_idx]; |
984b3f57 | 1055 | /* XXX for_each_set_bit(...) */ |
021230d4 | 1056 | r_idx = find_first_bit(q_vector->rxr_idx, |
b4617240 | 1057 | adapter->num_rx_queues); |
021230d4 AV |
1058 | |
1059 | for (i = 0; i < q_vector->rxr_count; i++) { | |
4a0b9ca0 | 1060 | j = adapter->rx_ring[r_idx]->reg_idx; |
e8e26350 | 1061 | ixgbe_set_ivar(adapter, 0, j, v_idx); |
021230d4 | 1062 | r_idx = find_next_bit(q_vector->rxr_idx, |
b4617240 PW |
1063 | adapter->num_rx_queues, |
1064 | r_idx + 1); | |
021230d4 AV |
1065 | } |
1066 | r_idx = find_first_bit(q_vector->txr_idx, | |
b4617240 | 1067 | adapter->num_tx_queues); |
021230d4 AV |
1068 | |
1069 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 1070 | j = adapter->tx_ring[r_idx]->reg_idx; |
e8e26350 | 1071 | ixgbe_set_ivar(adapter, 1, j, v_idx); |
021230d4 | 1072 | r_idx = find_next_bit(q_vector->txr_idx, |
b4617240 PW |
1073 | adapter->num_tx_queues, |
1074 | r_idx + 1); | |
021230d4 AV |
1075 | } |
1076 | ||
021230d4 | 1077 | if (q_vector->txr_count && !q_vector->rxr_count) |
f7554a2b NS |
1078 | /* tx only */ |
1079 | q_vector->eitr = adapter->tx_eitr_param; | |
509ee935 | 1080 | else if (q_vector->rxr_count) |
f7554a2b NS |
1081 | /* rx or mixed */ |
1082 | q_vector->eitr = adapter->rx_eitr_param; | |
021230d4 | 1083 | |
fe49f04a | 1084 | ixgbe_write_eitr(q_vector); |
9a799d71 AK |
1085 | } |
1086 | ||
e8e26350 PW |
1087 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) |
1088 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, | |
1089 | v_idx); | |
1090 | else if (adapter->hw.mac.type == ixgbe_mac_82599EB) | |
1091 | ixgbe_set_ivar(adapter, -1, 1, v_idx); | |
021230d4 AV |
1092 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
1093 | ||
41fb9248 | 1094 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 1095 | mask = IXGBE_EIMS_ENABLE_MASK; |
1cdd1ec8 GR |
1096 | if (adapter->num_vfs) |
1097 | mask &= ~(IXGBE_EIMS_OTHER | | |
1098 | IXGBE_EIMS_MAILBOX | | |
1099 | IXGBE_EIMS_LSC); | |
1100 | else | |
1101 | mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC); | |
021230d4 | 1102 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
1103 | } |
1104 | ||
f494e8fa AV |
1105 | enum latency_range { |
1106 | lowest_latency = 0, | |
1107 | low_latency = 1, | |
1108 | bulk_latency = 2, | |
1109 | latency_invalid = 255 | |
1110 | }; | |
1111 | ||
1112 | /** | |
1113 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
1114 | * @adapter: pointer to adapter | |
1115 | * @eitr: eitr setting (ints per sec) to give last timeslice | |
1116 | * @itr_setting: current throttle rate in ints/second | |
1117 | * @packets: the number of packets during this measurement interval | |
1118 | * @bytes: the number of bytes during this measurement interval | |
1119 | * | |
1120 | * Stores a new ITR value based on packets and byte | |
1121 | * counts during the last interrupt. The advantage of per interrupt | |
1122 | * computation is faster updates and more accurate ITR for the current | |
1123 | * traffic pattern. Constants in this function were computed | |
1124 | * based on theoretical maximum wire speed and thresholds were set based | |
1125 | * on testing data as well as attempting to minimize response time | |
1126 | * while increasing bulk throughput. | |
1127 | * this functionality is controlled by the InterruptThrottleRate module | |
1128 | * parameter (see ixgbe_param.c) | |
1129 | **/ | |
1130 | static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter, | |
b4617240 PW |
1131 | u32 eitr, u8 itr_setting, |
1132 | int packets, int bytes) | |
f494e8fa AV |
1133 | { |
1134 | unsigned int retval = itr_setting; | |
1135 | u32 timepassed_us; | |
1136 | u64 bytes_perint; | |
1137 | ||
1138 | if (packets == 0) | |
1139 | goto update_itr_done; | |
1140 | ||
1141 | ||
1142 | /* simple throttlerate management | |
1143 | * 0-20MB/s lowest (100000 ints/s) | |
1144 | * 20-100MB/s low (20000 ints/s) | |
1145 | * 100-1249MB/s bulk (8000 ints/s) | |
1146 | */ | |
1147 | /* what was last interrupt timeslice? */ | |
1148 | timepassed_us = 1000000/eitr; | |
1149 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ | |
1150 | ||
1151 | switch (itr_setting) { | |
1152 | case lowest_latency: | |
1153 | if (bytes_perint > adapter->eitr_low) | |
1154 | retval = low_latency; | |
1155 | break; | |
1156 | case low_latency: | |
1157 | if (bytes_perint > adapter->eitr_high) | |
1158 | retval = bulk_latency; | |
1159 | else if (bytes_perint <= adapter->eitr_low) | |
1160 | retval = lowest_latency; | |
1161 | break; | |
1162 | case bulk_latency: | |
1163 | if (bytes_perint <= adapter->eitr_high) | |
1164 | retval = low_latency; | |
1165 | break; | |
1166 | } | |
1167 | ||
1168 | update_itr_done: | |
1169 | return retval; | |
1170 | } | |
1171 | ||
509ee935 JB |
1172 | /** |
1173 | * ixgbe_write_eitr - write EITR register in hardware specific way | |
fe49f04a | 1174 | * @q_vector: structure containing interrupt and ring information |
509ee935 JB |
1175 | * |
1176 | * This function is made to be called by ethtool and by the driver | |
1177 | * when it needs to update EITR registers at runtime. Hardware | |
1178 | * specific quirks/differences are taken care of here. | |
1179 | */ | |
fe49f04a | 1180 | void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) |
509ee935 | 1181 | { |
fe49f04a | 1182 | struct ixgbe_adapter *adapter = q_vector->adapter; |
509ee935 | 1183 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
1184 | int v_idx = q_vector->v_idx; |
1185 | u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr); | |
1186 | ||
509ee935 JB |
1187 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
1188 | /* must write high and low 16 bits to reset counter */ | |
1189 | itr_reg |= (itr_reg << 16); | |
1190 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
1191 | /* | |
1192 | * set the WDIS bit to not clear the timer bits and cause an | |
1193 | * immediate assertion of the interrupt | |
1194 | */ | |
1195 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
1196 | } | |
1197 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); | |
1198 | } | |
1199 | ||
f494e8fa AV |
1200 | static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector) |
1201 | { | |
1202 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
f494e8fa AV |
1203 | u32 new_itr; |
1204 | u8 current_itr, ret_itr; | |
fe49f04a | 1205 | int i, r_idx; |
f494e8fa AV |
1206 | struct ixgbe_ring *rx_ring, *tx_ring; |
1207 | ||
1208 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1209 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 1210 | tx_ring = adapter->tx_ring[r_idx]; |
f494e8fa | 1211 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, |
b4617240 PW |
1212 | q_vector->tx_itr, |
1213 | tx_ring->total_packets, | |
1214 | tx_ring->total_bytes); | |
f494e8fa AV |
1215 | /* if the result for this queue would decrease interrupt |
1216 | * rate for this vector then use that result */ | |
30efa5a3 | 1217 | q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ? |
b4617240 | 1218 | q_vector->tx_itr - 1 : ret_itr); |
f494e8fa | 1219 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 1220 | r_idx + 1); |
f494e8fa AV |
1221 | } |
1222 | ||
1223 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1224 | for (i = 0; i < q_vector->rxr_count; i++) { | |
4a0b9ca0 | 1225 | rx_ring = adapter->rx_ring[r_idx]; |
f494e8fa | 1226 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, |
b4617240 PW |
1227 | q_vector->rx_itr, |
1228 | rx_ring->total_packets, | |
1229 | rx_ring->total_bytes); | |
f494e8fa AV |
1230 | /* if the result for this queue would decrease interrupt |
1231 | * rate for this vector then use that result */ | |
30efa5a3 | 1232 | q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ? |
b4617240 | 1233 | q_vector->rx_itr - 1 : ret_itr); |
f494e8fa | 1234 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
b4617240 | 1235 | r_idx + 1); |
f494e8fa AV |
1236 | } |
1237 | ||
30efa5a3 | 1238 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1239 | |
1240 | switch (current_itr) { | |
1241 | /* counts and packets in update_itr are dependent on these numbers */ | |
1242 | case lowest_latency: | |
1243 | new_itr = 100000; | |
1244 | break; | |
1245 | case low_latency: | |
1246 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1247 | break; | |
1248 | case bulk_latency: | |
1249 | default: | |
1250 | new_itr = 8000; | |
1251 | break; | |
1252 | } | |
1253 | ||
1254 | if (new_itr != q_vector->eitr) { | |
fe49f04a AD |
1255 | /* do an exponential smoothing */ |
1256 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
509ee935 JB |
1257 | |
1258 | /* save the algorithm value here, not the smoothed one */ | |
1259 | q_vector->eitr = new_itr; | |
fe49f04a AD |
1260 | |
1261 | ixgbe_write_eitr(q_vector); | |
f494e8fa AV |
1262 | } |
1263 | ||
1264 | return; | |
1265 | } | |
1266 | ||
0befdb3e JB |
1267 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
1268 | { | |
1269 | struct ixgbe_hw *hw = &adapter->hw; | |
1270 | ||
1271 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
1272 | (eicr & IXGBE_EICR_GPI_SDP1)) { | |
1273 | DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n"); | |
1274 | /* write to clear the interrupt */ | |
1275 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
1276 | } | |
1277 | } | |
cf8280ee | 1278 | |
e8e26350 PW |
1279 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
1280 | { | |
1281 | struct ixgbe_hw *hw = &adapter->hw; | |
1282 | ||
1283 | if (eicr & IXGBE_EICR_GPI_SDP1) { | |
1284 | /* Clear the interrupt */ | |
1285 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
1286 | schedule_work(&adapter->multispeed_fiber_task); | |
1287 | } else if (eicr & IXGBE_EICR_GPI_SDP2) { | |
1288 | /* Clear the interrupt */ | |
1289 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); | |
1290 | schedule_work(&adapter->sfp_config_module_task); | |
1291 | } else { | |
1292 | /* Interrupt isn't for us... */ | |
1293 | return; | |
1294 | } | |
1295 | } | |
1296 | ||
cf8280ee JB |
1297 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
1298 | { | |
1299 | struct ixgbe_hw *hw = &adapter->hw; | |
1300 | ||
1301 | adapter->lsc_int++; | |
1302 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
1303 | adapter->link_check_timeout = jiffies; | |
1304 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
1305 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
8a0717f3 | 1306 | IXGBE_WRITE_FLUSH(hw); |
cf8280ee JB |
1307 | schedule_work(&adapter->watchdog_task); |
1308 | } | |
1309 | } | |
1310 | ||
9a799d71 AK |
1311 | static irqreturn_t ixgbe_msix_lsc(int irq, void *data) |
1312 | { | |
1313 | struct net_device *netdev = data; | |
1314 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1315 | struct ixgbe_hw *hw = &adapter->hw; | |
54037505 DS |
1316 | u32 eicr; |
1317 | ||
1318 | /* | |
1319 | * Workaround for Silicon errata. Use clear-by-write instead | |
1320 | * of clear-by-read. Reading with EICS will return the | |
1321 | * interrupt causes without clearing, which later be done | |
1322 | * with the write to EICR. | |
1323 | */ | |
1324 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
1325 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); | |
9a799d71 | 1326 | |
cf8280ee JB |
1327 | if (eicr & IXGBE_EICR_LSC) |
1328 | ixgbe_check_lsc(adapter); | |
d4f80882 | 1329 | |
1cdd1ec8 GR |
1330 | if (eicr & IXGBE_EICR_MAILBOX) |
1331 | ixgbe_msg_task(adapter); | |
1332 | ||
e8e26350 PW |
1333 | if (hw->mac.type == ixgbe_mac_82598EB) |
1334 | ixgbe_check_fan_failure(adapter, eicr); | |
0befdb3e | 1335 | |
c4cf55e5 | 1336 | if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 | 1337 | ixgbe_check_sfp_event(adapter, eicr); |
c4cf55e5 PWJ |
1338 | |
1339 | /* Handle Flow Director Full threshold interrupt */ | |
1340 | if (eicr & IXGBE_EICR_FLOW_DIR) { | |
1341 | int i; | |
1342 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR); | |
1343 | /* Disable transmits before FDIR Re-initialization */ | |
1344 | netif_tx_stop_all_queues(netdev); | |
1345 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
1346 | struct ixgbe_ring *tx_ring = | |
4a0b9ca0 | 1347 | adapter->tx_ring[i]; |
c4cf55e5 PWJ |
1348 | if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE, |
1349 | &tx_ring->reinit_state)) | |
1350 | schedule_work(&adapter->fdir_reinit_task); | |
1351 | } | |
1352 | } | |
1353 | } | |
d4f80882 AV |
1354 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
1355 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER); | |
9a799d71 AK |
1356 | |
1357 | return IRQ_HANDLED; | |
1358 | } | |
1359 | ||
fe49f04a AD |
1360 | static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, |
1361 | u64 qmask) | |
1362 | { | |
1363 | u32 mask; | |
1364 | ||
1365 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
1366 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); | |
1367 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); | |
1368 | } else { | |
1369 | mask = (qmask & 0xFFFFFFFF); | |
1370 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask); | |
1371 | mask = (qmask >> 32); | |
1372 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask); | |
1373 | } | |
1374 | /* skip the flush */ | |
1375 | } | |
1376 | ||
1377 | static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, | |
1378 | u64 qmask) | |
1379 | { | |
1380 | u32 mask; | |
1381 | ||
1382 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
1383 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); | |
1384 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask); | |
1385 | } else { | |
1386 | mask = (qmask & 0xFFFFFFFF); | |
1387 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask); | |
1388 | mask = (qmask >> 32); | |
1389 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask); | |
1390 | } | |
1391 | /* skip the flush */ | |
1392 | } | |
1393 | ||
9a799d71 AK |
1394 | static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data) |
1395 | { | |
021230d4 AV |
1396 | struct ixgbe_q_vector *q_vector = data; |
1397 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 1398 | struct ixgbe_ring *tx_ring; |
021230d4 AV |
1399 | int i, r_idx; |
1400 | ||
1401 | if (!q_vector->txr_count) | |
1402 | return IRQ_HANDLED; | |
1403 | ||
1404 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1405 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 1406 | tx_ring = adapter->tx_ring[r_idx]; |
3a581073 JB |
1407 | tx_ring->total_bytes = 0; |
1408 | tx_ring->total_packets = 0; | |
021230d4 | 1409 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 1410 | r_idx + 1); |
021230d4 | 1411 | } |
9a799d71 | 1412 | |
9b471446 | 1413 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 AD |
1414 | napi_schedule(&q_vector->napi); |
1415 | ||
9a799d71 AK |
1416 | return IRQ_HANDLED; |
1417 | } | |
1418 | ||
021230d4 AV |
1419 | /** |
1420 | * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues) | |
1421 | * @irq: unused | |
1422 | * @data: pointer to our q_vector struct for this interrupt vector | |
1423 | **/ | |
9a799d71 AK |
1424 | static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data) |
1425 | { | |
021230d4 AV |
1426 | struct ixgbe_q_vector *q_vector = data; |
1427 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 1428 | struct ixgbe_ring *rx_ring; |
021230d4 | 1429 | int r_idx; |
30efa5a3 | 1430 | int i; |
021230d4 AV |
1431 | |
1432 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
30efa5a3 | 1433 | for (i = 0; i < q_vector->rxr_count; i++) { |
4a0b9ca0 | 1434 | rx_ring = adapter->rx_ring[r_idx]; |
30efa5a3 JB |
1435 | rx_ring->total_bytes = 0; |
1436 | rx_ring->total_packets = 0; | |
1437 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1438 | r_idx + 1); | |
1439 | } | |
1440 | ||
021230d4 AV |
1441 | if (!q_vector->rxr_count) |
1442 | return IRQ_HANDLED; | |
1443 | ||
021230d4 | 1444 | /* disable interrupts on this vector only */ |
9b471446 | 1445 | /* EIAM disabled interrupts (on this vector) for us */ |
288379f0 | 1446 | napi_schedule(&q_vector->napi); |
021230d4 AV |
1447 | |
1448 | return IRQ_HANDLED; | |
1449 | } | |
1450 | ||
1451 | static irqreturn_t ixgbe_msix_clean_many(int irq, void *data) | |
1452 | { | |
91281fd3 AD |
1453 | struct ixgbe_q_vector *q_vector = data; |
1454 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
1455 | struct ixgbe_ring *ring; | |
1456 | int r_idx; | |
1457 | int i; | |
1458 | ||
1459 | if (!q_vector->txr_count && !q_vector->rxr_count) | |
1460 | return IRQ_HANDLED; | |
1461 | ||
1462 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1463 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 1464 | ring = adapter->tx_ring[r_idx]; |
91281fd3 AD |
1465 | ring->total_bytes = 0; |
1466 | ring->total_packets = 0; | |
1467 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, | |
1468 | r_idx + 1); | |
1469 | } | |
1470 | ||
1471 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1472 | for (i = 0; i < q_vector->rxr_count; i++) { | |
4a0b9ca0 | 1473 | ring = adapter->rx_ring[r_idx]; |
91281fd3 AD |
1474 | ring->total_bytes = 0; |
1475 | ring->total_packets = 0; | |
1476 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1477 | r_idx + 1); | |
1478 | } | |
1479 | ||
9b471446 | 1480 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 | 1481 | napi_schedule(&q_vector->napi); |
9a799d71 | 1482 | |
9a799d71 AK |
1483 | return IRQ_HANDLED; |
1484 | } | |
1485 | ||
021230d4 AV |
1486 | /** |
1487 | * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine | |
1488 | * @napi: napi struct with our devices info in it | |
1489 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1490 | * | |
f0848276 JB |
1491 | * This function is optimized for cleaning one queue only on a single |
1492 | * q_vector!!! | |
021230d4 | 1493 | **/ |
9a799d71 AK |
1494 | static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget) |
1495 | { | |
021230d4 | 1496 | struct ixgbe_q_vector *q_vector = |
b4617240 | 1497 | container_of(napi, struct ixgbe_q_vector, napi); |
021230d4 | 1498 | struct ixgbe_adapter *adapter = q_vector->adapter; |
f0848276 | 1499 | struct ixgbe_ring *rx_ring = NULL; |
9a799d71 | 1500 | int work_done = 0; |
021230d4 | 1501 | long r_idx; |
9a799d71 | 1502 | |
021230d4 | 1503 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
4a0b9ca0 | 1504 | rx_ring = adapter->rx_ring[r_idx]; |
5dd2d332 | 1505 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 1506 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
3a581073 | 1507 | ixgbe_update_rx_dca(adapter, rx_ring); |
bd0362dd | 1508 | #endif |
9a799d71 | 1509 | |
78b6f4ce | 1510 | ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget); |
9a799d71 | 1511 | |
021230d4 AV |
1512 | /* If all Rx work done, exit the polling mode */ |
1513 | if (work_done < budget) { | |
288379f0 | 1514 | napi_complete(napi); |
f7554a2b | 1515 | if (adapter->rx_itr_setting & 1) |
f494e8fa | 1516 | ixgbe_set_itr_msix(q_vector); |
9a799d71 | 1517 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
fe49f04a AD |
1518 | ixgbe_irq_enable_queues(adapter, |
1519 | ((u64)1 << q_vector->v_idx)); | |
9a799d71 AK |
1520 | } |
1521 | ||
1522 | return work_done; | |
1523 | } | |
1524 | ||
f0848276 | 1525 | /** |
91281fd3 | 1526 | * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine |
f0848276 JB |
1527 | * @napi: napi struct with our devices info in it |
1528 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1529 | * | |
1530 | * This function will clean more than one rx queue associated with a | |
1531 | * q_vector. | |
1532 | **/ | |
91281fd3 | 1533 | static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget) |
f0848276 JB |
1534 | { |
1535 | struct ixgbe_q_vector *q_vector = | |
1536 | container_of(napi, struct ixgbe_q_vector, napi); | |
1537 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
91281fd3 | 1538 | struct ixgbe_ring *ring = NULL; |
f0848276 JB |
1539 | int work_done = 0, i; |
1540 | long r_idx; | |
91281fd3 AD |
1541 | bool tx_clean_complete = true; |
1542 | ||
1543 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1544 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 1545 | ring = adapter->tx_ring[r_idx]; |
91281fd3 AD |
1546 | #ifdef CONFIG_IXGBE_DCA |
1547 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
1548 | ixgbe_update_tx_dca(adapter, ring); | |
1549 | #endif | |
1550 | tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring); | |
1551 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, | |
1552 | r_idx + 1); | |
1553 | } | |
f0848276 JB |
1554 | |
1555 | /* attempt to distribute budget to each queue fairly, but don't allow | |
1556 | * the budget to go below 1 because we'll exit polling */ | |
1557 | budget /= (q_vector->rxr_count ?: 1); | |
1558 | budget = max(budget, 1); | |
1559 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1560 | for (i = 0; i < q_vector->rxr_count; i++) { | |
4a0b9ca0 | 1561 | ring = adapter->rx_ring[r_idx]; |
5dd2d332 | 1562 | #ifdef CONFIG_IXGBE_DCA |
f0848276 | 1563 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
91281fd3 | 1564 | ixgbe_update_rx_dca(adapter, ring); |
f0848276 | 1565 | #endif |
91281fd3 | 1566 | ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget); |
f0848276 JB |
1567 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
1568 | r_idx + 1); | |
1569 | } | |
1570 | ||
1571 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
4a0b9ca0 | 1572 | ring = adapter->rx_ring[r_idx]; |
f0848276 | 1573 | /* If all Rx work done, exit the polling mode */ |
7f821875 | 1574 | if (work_done < budget) { |
288379f0 | 1575 | napi_complete(napi); |
f7554a2b | 1576 | if (adapter->rx_itr_setting & 1) |
f0848276 JB |
1577 | ixgbe_set_itr_msix(q_vector); |
1578 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
fe49f04a AD |
1579 | ixgbe_irq_enable_queues(adapter, |
1580 | ((u64)1 << q_vector->v_idx)); | |
f0848276 JB |
1581 | return 0; |
1582 | } | |
1583 | ||
1584 | return work_done; | |
1585 | } | |
91281fd3 AD |
1586 | |
1587 | /** | |
1588 | * ixgbe_clean_txonly - msix (aka one shot) tx clean routine | |
1589 | * @napi: napi struct with our devices info in it | |
1590 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1591 | * | |
1592 | * This function is optimized for cleaning one queue only on a single | |
1593 | * q_vector!!! | |
1594 | **/ | |
1595 | static int ixgbe_clean_txonly(struct napi_struct *napi, int budget) | |
1596 | { | |
1597 | struct ixgbe_q_vector *q_vector = | |
1598 | container_of(napi, struct ixgbe_q_vector, napi); | |
1599 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
1600 | struct ixgbe_ring *tx_ring = NULL; | |
1601 | int work_done = 0; | |
1602 | long r_idx; | |
1603 | ||
1604 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
4a0b9ca0 | 1605 | tx_ring = adapter->tx_ring[r_idx]; |
91281fd3 AD |
1606 | #ifdef CONFIG_IXGBE_DCA |
1607 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
1608 | ixgbe_update_tx_dca(adapter, tx_ring); | |
1609 | #endif | |
1610 | ||
1611 | if (!ixgbe_clean_tx_irq(q_vector, tx_ring)) | |
1612 | work_done = budget; | |
1613 | ||
f7554a2b | 1614 | /* If all Tx work done, exit the polling mode */ |
91281fd3 AD |
1615 | if (work_done < budget) { |
1616 | napi_complete(napi); | |
f7554a2b | 1617 | if (adapter->tx_itr_setting & 1) |
91281fd3 AD |
1618 | ixgbe_set_itr_msix(q_vector); |
1619 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
1620 | ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
1621 | } | |
1622 | ||
1623 | return work_done; | |
1624 | } | |
1625 | ||
021230d4 | 1626 | static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx, |
b4617240 | 1627 | int r_idx) |
021230d4 | 1628 | { |
7a921c93 AD |
1629 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
1630 | ||
1631 | set_bit(r_idx, q_vector->rxr_idx); | |
1632 | q_vector->rxr_count++; | |
021230d4 AV |
1633 | } |
1634 | ||
1635 | static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx, | |
7a921c93 | 1636 | int t_idx) |
021230d4 | 1637 | { |
7a921c93 AD |
1638 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
1639 | ||
1640 | set_bit(t_idx, q_vector->txr_idx); | |
1641 | q_vector->txr_count++; | |
021230d4 AV |
1642 | } |
1643 | ||
9a799d71 | 1644 | /** |
021230d4 AV |
1645 | * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors |
1646 | * @adapter: board private structure to initialize | |
1647 | * @vectors: allotted vector count for descriptor rings | |
9a799d71 | 1648 | * |
021230d4 AV |
1649 | * This function maps descriptor rings to the queue-specific vectors |
1650 | * we were allotted through the MSI-X enabling code. Ideally, we'd have | |
1651 | * one vector per ring/queue, but on a constrained vector budget, we | |
1652 | * group the rings as "efficiently" as possible. You would add new | |
1653 | * mapping configurations in here. | |
9a799d71 | 1654 | **/ |
021230d4 | 1655 | static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 1656 | int vectors) |
021230d4 AV |
1657 | { |
1658 | int v_start = 0; | |
1659 | int rxr_idx = 0, txr_idx = 0; | |
1660 | int rxr_remaining = adapter->num_rx_queues; | |
1661 | int txr_remaining = adapter->num_tx_queues; | |
1662 | int i, j; | |
1663 | int rqpv, tqpv; | |
1664 | int err = 0; | |
1665 | ||
1666 | /* No mapping required if MSI-X is disabled. */ | |
1667 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
1668 | goto out; | |
9a799d71 | 1669 | |
021230d4 AV |
1670 | /* |
1671 | * The ideal configuration... | |
1672 | * We have enough vectors to map one per queue. | |
1673 | */ | |
1674 | if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) { | |
1675 | for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++) | |
1676 | map_vector_to_rxq(adapter, v_start, rxr_idx); | |
9a799d71 | 1677 | |
021230d4 AV |
1678 | for (; txr_idx < txr_remaining; v_start++, txr_idx++) |
1679 | map_vector_to_txq(adapter, v_start, txr_idx); | |
9a799d71 | 1680 | |
9a799d71 | 1681 | goto out; |
021230d4 | 1682 | } |
9a799d71 | 1683 | |
021230d4 AV |
1684 | /* |
1685 | * If we don't have enough vectors for a 1-to-1 | |
1686 | * mapping, we'll have to group them so there are | |
1687 | * multiple queues per vector. | |
1688 | */ | |
1689 | /* Re-adjusting *qpv takes care of the remainder. */ | |
1690 | for (i = v_start; i < vectors; i++) { | |
1691 | rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i); | |
1692 | for (j = 0; j < rqpv; j++) { | |
1693 | map_vector_to_rxq(adapter, i, rxr_idx); | |
1694 | rxr_idx++; | |
1695 | rxr_remaining--; | |
1696 | } | |
1697 | } | |
1698 | for (i = v_start; i < vectors; i++) { | |
1699 | tqpv = DIV_ROUND_UP(txr_remaining, vectors - i); | |
1700 | for (j = 0; j < tqpv; j++) { | |
1701 | map_vector_to_txq(adapter, i, txr_idx); | |
1702 | txr_idx++; | |
1703 | txr_remaining--; | |
9a799d71 | 1704 | } |
9a799d71 AK |
1705 | } |
1706 | ||
021230d4 AV |
1707 | out: |
1708 | return err; | |
1709 | } | |
1710 | ||
1711 | /** | |
1712 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
1713 | * @adapter: board private structure | |
1714 | * | |
1715 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
1716 | * interrupts from the kernel. | |
1717 | **/ | |
1718 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
1719 | { | |
1720 | struct net_device *netdev = adapter->netdev; | |
1721 | irqreturn_t (*handler)(int, void *); | |
1722 | int i, vector, q_vectors, err; | |
cb13fc20 | 1723 | int ri=0, ti=0; |
021230d4 AV |
1724 | |
1725 | /* Decrement for Other and TCP Timer vectors */ | |
1726 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1727 | ||
1728 | /* Map the Tx/Rx rings to the vectors we were allotted. */ | |
1729 | err = ixgbe_map_rings_to_vectors(adapter, q_vectors); | |
1730 | if (err) | |
1731 | goto out; | |
1732 | ||
1733 | #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \ | |
b4617240 PW |
1734 | (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \ |
1735 | &ixgbe_msix_clean_many) | |
021230d4 | 1736 | for (vector = 0; vector < q_vectors; vector++) { |
7a921c93 | 1737 | handler = SET_HANDLER(adapter->q_vector[vector]); |
cb13fc20 RO |
1738 | |
1739 | if(handler == &ixgbe_msix_clean_rx) { | |
1740 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1741 | netdev->name, "rx", ri++); | |
1742 | } | |
1743 | else if(handler == &ixgbe_msix_clean_tx) { | |
1744 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1745 | netdev->name, "tx", ti++); | |
1746 | } | |
1747 | else | |
1748 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1749 | netdev->name, "TxRx", vector); | |
1750 | ||
021230d4 | 1751 | err = request_irq(adapter->msix_entries[vector].vector, |
b4617240 | 1752 | handler, 0, adapter->name[vector], |
7a921c93 | 1753 | adapter->q_vector[vector]); |
9a799d71 AK |
1754 | if (err) { |
1755 | DPRINTK(PROBE, ERR, | |
b4617240 PW |
1756 | "request_irq failed for MSIX interrupt " |
1757 | "Error: %d\n", err); | |
021230d4 | 1758 | goto free_queue_irqs; |
9a799d71 | 1759 | } |
9a799d71 AK |
1760 | } |
1761 | ||
021230d4 AV |
1762 | sprintf(adapter->name[vector], "%s:lsc", netdev->name); |
1763 | err = request_irq(adapter->msix_entries[vector].vector, | |
a0607fd3 | 1764 | ixgbe_msix_lsc, 0, adapter->name[vector], netdev); |
9a799d71 AK |
1765 | if (err) { |
1766 | DPRINTK(PROBE, ERR, | |
1767 | "request_irq for msix_lsc failed: %d\n", err); | |
021230d4 | 1768 | goto free_queue_irqs; |
9a799d71 AK |
1769 | } |
1770 | ||
9a799d71 AK |
1771 | return 0; |
1772 | ||
021230d4 AV |
1773 | free_queue_irqs: |
1774 | for (i = vector - 1; i >= 0; i--) | |
1775 | free_irq(adapter->msix_entries[--vector].vector, | |
7a921c93 | 1776 | adapter->q_vector[i]); |
021230d4 AV |
1777 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
1778 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
1779 | kfree(adapter->msix_entries); |
1780 | adapter->msix_entries = NULL; | |
021230d4 | 1781 | out: |
9a799d71 AK |
1782 | return err; |
1783 | } | |
1784 | ||
f494e8fa AV |
1785 | static void ixgbe_set_itr(struct ixgbe_adapter *adapter) |
1786 | { | |
7a921c93 | 1787 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
f494e8fa AV |
1788 | u8 current_itr; |
1789 | u32 new_itr = q_vector->eitr; | |
4a0b9ca0 PW |
1790 | struct ixgbe_ring *rx_ring = adapter->rx_ring[0]; |
1791 | struct ixgbe_ring *tx_ring = adapter->tx_ring[0]; | |
f494e8fa | 1792 | |
30efa5a3 | 1793 | q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
1794 | q_vector->tx_itr, |
1795 | tx_ring->total_packets, | |
1796 | tx_ring->total_bytes); | |
30efa5a3 | 1797 | q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
1798 | q_vector->rx_itr, |
1799 | rx_ring->total_packets, | |
1800 | rx_ring->total_bytes); | |
f494e8fa | 1801 | |
30efa5a3 | 1802 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1803 | |
1804 | switch (current_itr) { | |
1805 | /* counts and packets in update_itr are dependent on these numbers */ | |
1806 | case lowest_latency: | |
1807 | new_itr = 100000; | |
1808 | break; | |
1809 | case low_latency: | |
1810 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1811 | break; | |
1812 | case bulk_latency: | |
1813 | new_itr = 8000; | |
1814 | break; | |
1815 | default: | |
1816 | break; | |
1817 | } | |
1818 | ||
1819 | if (new_itr != q_vector->eitr) { | |
fe49f04a AD |
1820 | /* do an exponential smoothing */ |
1821 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
509ee935 JB |
1822 | |
1823 | /* save the algorithm value here, not the smoothed one */ | |
1824 | q_vector->eitr = new_itr; | |
fe49f04a AD |
1825 | |
1826 | ixgbe_write_eitr(q_vector); | |
f494e8fa AV |
1827 | } |
1828 | ||
1829 | return; | |
1830 | } | |
1831 | ||
79aefa45 AD |
1832 | /** |
1833 | * ixgbe_irq_enable - Enable default interrupt generation settings | |
1834 | * @adapter: board private structure | |
1835 | **/ | |
1836 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter) | |
1837 | { | |
1838 | u32 mask; | |
835462fc NS |
1839 | |
1840 | mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); | |
6ab33d51 DM |
1841 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
1842 | mask |= IXGBE_EIMS_GPI_SDP1; | |
e8e26350 | 1843 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
2a41ff81 | 1844 | mask |= IXGBE_EIMS_ECC; |
e8e26350 PW |
1845 | mask |= IXGBE_EIMS_GPI_SDP1; |
1846 | mask |= IXGBE_EIMS_GPI_SDP2; | |
1cdd1ec8 GR |
1847 | if (adapter->num_vfs) |
1848 | mask |= IXGBE_EIMS_MAILBOX; | |
e8e26350 | 1849 | } |
c4cf55e5 PWJ |
1850 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
1851 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
1852 | mask |= IXGBE_EIMS_FLOW_DIR; | |
e8e26350 | 1853 | |
79aefa45 | 1854 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
835462fc | 1855 | ixgbe_irq_enable_queues(adapter, ~0); |
79aefa45 | 1856 | IXGBE_WRITE_FLUSH(&adapter->hw); |
1cdd1ec8 GR |
1857 | |
1858 | if (adapter->num_vfs > 32) { | |
1859 | u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1; | |
1860 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); | |
1861 | } | |
79aefa45 | 1862 | } |
021230d4 | 1863 | |
9a799d71 | 1864 | /** |
021230d4 | 1865 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
1866 | * @irq: interrupt number |
1867 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
1868 | **/ |
1869 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
1870 | { | |
1871 | struct net_device *netdev = data; | |
1872 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1873 | struct ixgbe_hw *hw = &adapter->hw; | |
7a921c93 | 1874 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 AK |
1875 | u32 eicr; |
1876 | ||
54037505 DS |
1877 | /* |
1878 | * Workaround for silicon errata. Mask the interrupts | |
1879 | * before the read of EICR. | |
1880 | */ | |
1881 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
1882 | ||
021230d4 AV |
1883 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
1884 | * therefore no explict interrupt disable is necessary */ | |
1885 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); | |
f47cf66e JB |
1886 | if (!eicr) { |
1887 | /* shared interrupt alert! | |
1888 | * make sure interrupts are enabled because the read will | |
1889 | * have disabled interrupts due to EIAM */ | |
1890 | ixgbe_irq_enable(adapter); | |
9a799d71 | 1891 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 1892 | } |
9a799d71 | 1893 | |
cf8280ee JB |
1894 | if (eicr & IXGBE_EICR_LSC) |
1895 | ixgbe_check_lsc(adapter); | |
021230d4 | 1896 | |
e8e26350 PW |
1897 | if (hw->mac.type == ixgbe_mac_82599EB) |
1898 | ixgbe_check_sfp_event(adapter, eicr); | |
1899 | ||
0befdb3e JB |
1900 | ixgbe_check_fan_failure(adapter, eicr); |
1901 | ||
7a921c93 | 1902 | if (napi_schedule_prep(&(q_vector->napi))) { |
4a0b9ca0 PW |
1903 | adapter->tx_ring[0]->total_packets = 0; |
1904 | adapter->tx_ring[0]->total_bytes = 0; | |
1905 | adapter->rx_ring[0]->total_packets = 0; | |
1906 | adapter->rx_ring[0]->total_bytes = 0; | |
021230d4 | 1907 | /* would disable interrupts here but EIAM disabled it */ |
7a921c93 | 1908 | __napi_schedule(&(q_vector->napi)); |
9a799d71 AK |
1909 | } |
1910 | ||
1911 | return IRQ_HANDLED; | |
1912 | } | |
1913 | ||
021230d4 AV |
1914 | static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter) |
1915 | { | |
1916 | int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1917 | ||
1918 | for (i = 0; i < q_vectors; i++) { | |
7a921c93 | 1919 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; |
021230d4 AV |
1920 | bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES); |
1921 | bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES); | |
1922 | q_vector->rxr_count = 0; | |
1923 | q_vector->txr_count = 0; | |
1924 | } | |
1925 | } | |
1926 | ||
9a799d71 AK |
1927 | /** |
1928 | * ixgbe_request_irq - initialize interrupts | |
1929 | * @adapter: board private structure | |
1930 | * | |
1931 | * Attempts to configure interrupts using the best available | |
1932 | * capabilities of the hardware and kernel. | |
1933 | **/ | |
021230d4 | 1934 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
1935 | { |
1936 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 1937 | int err; |
9a799d71 | 1938 | |
021230d4 AV |
1939 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
1940 | err = ixgbe_request_msix_irqs(adapter); | |
1941 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
a0607fd3 | 1942 | err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, |
b4617240 | 1943 | netdev->name, netdev); |
021230d4 | 1944 | } else { |
a0607fd3 | 1945 | err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, |
b4617240 | 1946 | netdev->name, netdev); |
9a799d71 AK |
1947 | } |
1948 | ||
9a799d71 AK |
1949 | if (err) |
1950 | DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err); | |
1951 | ||
9a799d71 AK |
1952 | return err; |
1953 | } | |
1954 | ||
1955 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
1956 | { | |
1957 | struct net_device *netdev = adapter->netdev; | |
1958 | ||
1959 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
021230d4 | 1960 | int i, q_vectors; |
9a799d71 | 1961 | |
021230d4 AV |
1962 | q_vectors = adapter->num_msix_vectors; |
1963 | ||
1964 | i = q_vectors - 1; | |
9a799d71 | 1965 | free_irq(adapter->msix_entries[i].vector, netdev); |
9a799d71 | 1966 | |
021230d4 AV |
1967 | i--; |
1968 | for (; i >= 0; i--) { | |
1969 | free_irq(adapter->msix_entries[i].vector, | |
7a921c93 | 1970 | adapter->q_vector[i]); |
021230d4 AV |
1971 | } |
1972 | ||
1973 | ixgbe_reset_q_vectors(adapter); | |
1974 | } else { | |
1975 | free_irq(adapter->pdev->irq, netdev); | |
9a799d71 AK |
1976 | } |
1977 | } | |
1978 | ||
22d5a71b JB |
1979 | /** |
1980 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
1981 | * @adapter: board private structure | |
1982 | **/ | |
1983 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
1984 | { | |
835462fc NS |
1985 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
1986 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); | |
1987 | } else { | |
1988 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); | |
1989 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); | |
22d5a71b | 1990 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); |
1cdd1ec8 GR |
1991 | if (adapter->num_vfs > 32) |
1992 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); | |
22d5a71b JB |
1993 | } |
1994 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
1995 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
1996 | int i; | |
1997 | for (i = 0; i < adapter->num_msix_vectors; i++) | |
1998 | synchronize_irq(adapter->msix_entries[i].vector); | |
1999 | } else { | |
2000 | synchronize_irq(adapter->pdev->irq); | |
2001 | } | |
2002 | } | |
2003 | ||
9a799d71 AK |
2004 | /** |
2005 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
2006 | * | |
2007 | **/ | |
2008 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
2009 | { | |
9a799d71 AK |
2010 | struct ixgbe_hw *hw = &adapter->hw; |
2011 | ||
021230d4 | 2012 | IXGBE_WRITE_REG(hw, IXGBE_EITR(0), |
f7554a2b | 2013 | EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param)); |
9a799d71 | 2014 | |
e8e26350 PW |
2015 | ixgbe_set_ivar(adapter, 0, 0, 0); |
2016 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 AV |
2017 | |
2018 | map_vector_to_rxq(adapter, 0, 0); | |
2019 | map_vector_to_txq(adapter, 0, 0); | |
2020 | ||
2021 | DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n"); | |
9a799d71 AK |
2022 | } |
2023 | ||
2024 | /** | |
3a581073 | 2025 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
2026 | * @adapter: board private structure |
2027 | * | |
2028 | * Configure the Tx unit of the MAC after a reset. | |
2029 | **/ | |
2030 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
2031 | { | |
12207e49 | 2032 | u64 tdba; |
9a799d71 | 2033 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 2034 | u32 i, j, tdlen, txctrl; |
9a799d71 AK |
2035 | |
2036 | /* Setup the HW Tx Head and Tail descriptor pointers */ | |
2037 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 2038 | struct ixgbe_ring *ring = adapter->tx_ring[i]; |
e01c31a5 JB |
2039 | j = ring->reg_idx; |
2040 | tdba = ring->dma; | |
2041 | tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc); | |
021230d4 | 2042 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j), |
284901a9 | 2043 | (tdba & DMA_BIT_MASK(32))); |
021230d4 AV |
2044 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32)); |
2045 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen); | |
2046 | IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0); | |
2047 | IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0); | |
4a0b9ca0 PW |
2048 | adapter->tx_ring[i]->head = IXGBE_TDH(j); |
2049 | adapter->tx_ring[i]->tail = IXGBE_TDT(j); | |
84f62d4b PWJ |
2050 | /* |
2051 | * Disable Tx Head Writeback RO bit, since this hoses | |
021230d4 AV |
2052 | * bookkeeping if things aren't delivered in order. |
2053 | */ | |
84f62d4b PWJ |
2054 | switch (hw->mac.type) { |
2055 | case ixgbe_mac_82598EB: | |
2056 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j)); | |
2057 | break; | |
2058 | case ixgbe_mac_82599EB: | |
2059 | default: | |
2060 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j)); | |
2061 | break; | |
2062 | } | |
021230d4 | 2063 | txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; |
84f62d4b PWJ |
2064 | switch (hw->mac.type) { |
2065 | case ixgbe_mac_82598EB: | |
2066 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl); | |
2067 | break; | |
2068 | case ixgbe_mac_82599EB: | |
2069 | default: | |
2070 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl); | |
2071 | break; | |
2072 | } | |
9a799d71 | 2073 | } |
ee5f784a | 2074 | |
e8e26350 | 2075 | if (hw->mac.type == ixgbe_mac_82599EB) { |
ee5f784a | 2076 | u32 rttdcs; |
1cdd1ec8 | 2077 | u32 mask; |
ee5f784a DS |
2078 | |
2079 | /* disable the arbiter while setting MTQC */ | |
2080 | rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); | |
2081 | rttdcs |= IXGBE_RTTDCS_ARBDIS; | |
2082 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2083 | ||
1cdd1ec8 GR |
2084 | /* set transmit pool layout */ |
2085 | mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED); | |
2086 | switch (adapter->flags & mask) { | |
2087 | ||
2088 | case (IXGBE_FLAG_SRIOV_ENABLED): | |
2089 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, | |
2090 | (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF)); | |
2091 | break; | |
2092 | ||
2093 | case (IXGBE_FLAG_DCB_ENABLED): | |
2094 | /* We enable 8 traffic classes, DCB only */ | |
2095 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, | |
2096 | (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ)); | |
2097 | break; | |
2098 | ||
2099 | default: | |
ee5f784a | 2100 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB); |
1cdd1ec8 GR |
2101 | break; |
2102 | } | |
ee5f784a DS |
2103 | |
2104 | /* re-eable the arbiter */ | |
2105 | rttdcs &= ~IXGBE_RTTDCS_ARBDIS; | |
2106 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
e8e26350 | 2107 | } |
9a799d71 AK |
2108 | } |
2109 | ||
e8e26350 | 2110 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c | 2111 | |
a6616b42 YZ |
2112 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, |
2113 | struct ixgbe_ring *rx_ring) | |
cc41ac7c | 2114 | { |
cc41ac7c | 2115 | u32 srrctl; |
a6616b42 | 2116 | int index; |
0cefafad | 2117 | struct ixgbe_ring_feature *feature = adapter->ring_feature; |
3be1adfb | 2118 | |
a6616b42 YZ |
2119 | index = rx_ring->reg_idx; |
2120 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
2121 | unsigned long mask; | |
0cefafad | 2122 | mask = (unsigned long) feature[RING_F_RSS].mask; |
3be1adfb | 2123 | index = index & mask; |
cc41ac7c | 2124 | } |
cc41ac7c JB |
2125 | srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index)); |
2126 | ||
2127 | srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; | |
2128 | srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; | |
2129 | ||
afafd5b0 AD |
2130 | srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & |
2131 | IXGBE_SRRCTL_BSIZEHDR_MASK; | |
2132 | ||
6e455b89 | 2133 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) { |
afafd5b0 AD |
2134 | #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER |
2135 | srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
2136 | #else | |
2137 | srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
2138 | #endif | |
cc41ac7c | 2139 | srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; |
cc41ac7c | 2140 | } else { |
afafd5b0 AD |
2141 | srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >> |
2142 | IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
cc41ac7c | 2143 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
cc41ac7c | 2144 | } |
e8e26350 | 2145 | |
cc41ac7c JB |
2146 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl); |
2147 | } | |
9a799d71 | 2148 | |
0cefafad JB |
2149 | static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) |
2150 | { | |
2151 | u32 mrqc = 0; | |
2152 | int mask; | |
2153 | ||
2154 | if (!(adapter->hw.mac.type == ixgbe_mac_82599EB)) | |
2155 | return mrqc; | |
2156 | ||
2157 | mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED | |
2158 | #ifdef CONFIG_IXGBE_DCB | |
2159 | | IXGBE_FLAG_DCB_ENABLED | |
2160 | #endif | |
1cdd1ec8 | 2161 | | IXGBE_FLAG_SRIOV_ENABLED |
0cefafad JB |
2162 | ); |
2163 | ||
2164 | switch (mask) { | |
2165 | case (IXGBE_FLAG_RSS_ENABLED): | |
2166 | mrqc = IXGBE_MRQC_RSSEN; | |
2167 | break; | |
1cdd1ec8 GR |
2168 | case (IXGBE_FLAG_SRIOV_ENABLED): |
2169 | mrqc = IXGBE_MRQC_VMDQEN; | |
2170 | break; | |
0cefafad JB |
2171 | #ifdef CONFIG_IXGBE_DCB |
2172 | case (IXGBE_FLAG_DCB_ENABLED): | |
2173 | mrqc = IXGBE_MRQC_RT8TCEN; | |
2174 | break; | |
2175 | #endif /* CONFIG_IXGBE_DCB */ | |
2176 | default: | |
2177 | break; | |
2178 | } | |
2179 | ||
2180 | return mrqc; | |
2181 | } | |
2182 | ||
bb5a9ad2 NS |
2183 | /** |
2184 | * ixgbe_configure_rscctl - enable RSC for the indicated ring | |
2185 | * @adapter: address of board private structure | |
2186 | * @index: index of ring to set | |
bb5a9ad2 | 2187 | **/ |
edd2ea55 | 2188 | static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index) |
bb5a9ad2 NS |
2189 | { |
2190 | struct ixgbe_ring *rx_ring; | |
2191 | struct ixgbe_hw *hw = &adapter->hw; | |
2192 | int j; | |
2193 | u32 rscctrl; | |
edd2ea55 | 2194 | int rx_buf_len; |
bb5a9ad2 | 2195 | |
4a0b9ca0 | 2196 | rx_ring = adapter->rx_ring[index]; |
bb5a9ad2 | 2197 | j = rx_ring->reg_idx; |
edd2ea55 | 2198 | rx_buf_len = rx_ring->rx_buf_len; |
bb5a9ad2 NS |
2199 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j)); |
2200 | rscctrl |= IXGBE_RSCCTL_RSCEN; | |
2201 | /* | |
2202 | * we must limit the number of descriptors so that the | |
2203 | * total size of max desc * buf_len is not greater | |
2204 | * than 65535 | |
2205 | */ | |
2206 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) { | |
2207 | #if (MAX_SKB_FRAGS > 16) | |
2208 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2209 | #elif (MAX_SKB_FRAGS > 8) | |
2210 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
2211 | #elif (MAX_SKB_FRAGS > 4) | |
2212 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
2213 | #else | |
2214 | rscctrl |= IXGBE_RSCCTL_MAXDESC_1; | |
2215 | #endif | |
2216 | } else { | |
2217 | if (rx_buf_len < IXGBE_RXBUFFER_4096) | |
2218 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2219 | else if (rx_buf_len < IXGBE_RXBUFFER_8192) | |
2220 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
2221 | else | |
2222 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
2223 | } | |
2224 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl); | |
2225 | } | |
2226 | ||
9a799d71 | 2227 | /** |
3a581073 | 2228 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset |
9a799d71 AK |
2229 | * @adapter: board private structure |
2230 | * | |
2231 | * Configure the Rx unit of the MAC after a reset. | |
2232 | **/ | |
2233 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
2234 | { | |
2235 | u64 rdba; | |
2236 | struct ixgbe_hw *hw = &adapter->hw; | |
a6616b42 | 2237 | struct ixgbe_ring *rx_ring; |
9a799d71 AK |
2238 | struct net_device *netdev = adapter->netdev; |
2239 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
021230d4 | 2240 | int i, j; |
9a799d71 | 2241 | u32 rdlen, rxctrl, rxcsum; |
7c6e0a43 JB |
2242 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, |
2243 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, | |
2244 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
9a799d71 | 2245 | u32 fctrl, hlreg0; |
509ee935 | 2246 | u32 reta = 0, mrqc = 0; |
cc41ac7c | 2247 | u32 rdrxctl; |
7c6e0a43 | 2248 | int rx_buf_len; |
9a799d71 AK |
2249 | |
2250 | /* Decide whether to use packet split mode or not */ | |
1cdd1ec8 GR |
2251 | /* Do not use packet split if we're in SR-IOV Mode */ |
2252 | if (!adapter->num_vfs) | |
2253 | adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED; | |
9a799d71 AK |
2254 | |
2255 | /* Set the RX buffer length according to the mode */ | |
2256 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 | 2257 | rx_buf_len = IXGBE_RX_HDR_SIZE; |
e8e26350 PW |
2258 | if (hw->mac.type == ixgbe_mac_82599EB) { |
2259 | /* PSRTYPE must be initialized in 82599 */ | |
2260 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
2261 | IXGBE_PSRTYPE_UDPHDR | | |
2262 | IXGBE_PSRTYPE_IPV4HDR | | |
dfa12f05 YZ |
2263 | IXGBE_PSRTYPE_IPV6HDR | |
2264 | IXGBE_PSRTYPE_L2HDR; | |
1cdd1ec8 GR |
2265 | IXGBE_WRITE_REG(hw, |
2266 | IXGBE_PSRTYPE(adapter->num_vfs), | |
2267 | psrtype); | |
e8e26350 | 2268 | } |
9a799d71 | 2269 | } else { |
0c19d6af | 2270 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) && |
f8212f97 | 2271 | (netdev->mtu <= ETH_DATA_LEN)) |
7c6e0a43 | 2272 | rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
9a799d71 | 2273 | else |
7c6e0a43 | 2274 | rx_buf_len = ALIGN(max_frame, 1024); |
9a799d71 AK |
2275 | } |
2276 | ||
2277 | fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL); | |
2278 | fctrl |= IXGBE_FCTRL_BAM; | |
021230d4 | 2279 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ |
e8e26350 | 2280 | fctrl |= IXGBE_FCTRL_PMCF; |
9a799d71 AK |
2281 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl); |
2282 | ||
2283 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |
2284 | if (adapter->netdev->mtu <= ETH_DATA_LEN) | |
2285 | hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; | |
2286 | else | |
2287 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
63f39bd1 | 2288 | #ifdef IXGBE_FCOE |
f34c5c82 | 2289 | if (netdev->features & NETIF_F_FCOE_MTU) |
63f39bd1 YZ |
2290 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; |
2291 | #endif | |
9a799d71 AK |
2292 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); |
2293 | ||
4a0b9ca0 | 2294 | rdlen = adapter->rx_ring[0]->count * sizeof(union ixgbe_adv_rx_desc); |
9a799d71 AK |
2295 | /* disable receives while setting up the descriptors */ |
2296 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
2297 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
2298 | ||
0cefafad JB |
2299 | /* |
2300 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
2301 | * the Base and Length of the Rx Descriptor Ring | |
2302 | */ | |
9a799d71 | 2303 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 | 2304 | rx_ring = adapter->rx_ring[i]; |
a6616b42 YZ |
2305 | rdba = rx_ring->dma; |
2306 | j = rx_ring->reg_idx; | |
284901a9 | 2307 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32))); |
7c6e0a43 JB |
2308 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32)); |
2309 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen); | |
2310 | IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0); | |
2311 | IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0); | |
a6616b42 YZ |
2312 | rx_ring->head = IXGBE_RDH(j); |
2313 | rx_ring->tail = IXGBE_RDT(j); | |
2314 | rx_ring->rx_buf_len = rx_buf_len; | |
cc41ac7c | 2315 | |
6e455b89 YZ |
2316 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) |
2317 | rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED; | |
1b3ff02e PWJ |
2318 | else |
2319 | rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED; | |
cc41ac7c | 2320 | |
63f39bd1 | 2321 | #ifdef IXGBE_FCOE |
f34c5c82 | 2322 | if (netdev->features & NETIF_F_FCOE_MTU) { |
63f39bd1 YZ |
2323 | struct ixgbe_ring_feature *f; |
2324 | f = &adapter->ring_feature[RING_F_FCOE]; | |
6e455b89 YZ |
2325 | if ((i >= f->mask) && (i < f->mask + f->indices)) { |
2326 | rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED; | |
2327 | if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) | |
2328 | rx_ring->rx_buf_len = | |
2329 | IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
2330 | } | |
63f39bd1 YZ |
2331 | } |
2332 | ||
2333 | #endif /* IXGBE_FCOE */ | |
a6616b42 | 2334 | ixgbe_configure_srrctl(adapter, rx_ring); |
9a799d71 AK |
2335 | } |
2336 | ||
e8e26350 PW |
2337 | if (hw->mac.type == ixgbe_mac_82598EB) { |
2338 | /* | |
2339 | * For VMDq support of different descriptor types or | |
2340 | * buffer sizes through the use of multiple SRRCTL | |
2341 | * registers, RDRXCTL.MVMEN must be set to 1 | |
2342 | * | |
2343 | * also, the manual doesn't mention it clearly but DCA hints | |
2344 | * will only use queue 0's tags unless this bit is set. Side | |
2345 | * effects of setting this bit are only that SRRCTL must be | |
2346 | * fully programmed [0..15] | |
2347 | */ | |
2a41ff81 JB |
2348 | rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); |
2349 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
2350 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
2f90b865 | 2351 | } |
177db6ff | 2352 | |
1cdd1ec8 GR |
2353 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
2354 | u32 vt_reg_bits; | |
2355 | u32 reg_offset, vf_shift; | |
2356 | u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
2357 | vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | |
2358 | | IXGBE_VT_CTL_REPLEN; | |
2359 | vt_reg_bits |= (adapter->num_vfs << | |
2360 | IXGBE_VT_CTL_POOL_SHIFT); | |
2361 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits); | |
2362 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0); | |
2363 | ||
2364 | vf_shift = adapter->num_vfs % 32; | |
2365 | reg_offset = adapter->num_vfs / 32; | |
2366 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0); | |
2367 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0); | |
2368 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0); | |
2369 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0); | |
2370 | /* Enable only the PF's pool for Tx/Rx */ | |
2371 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift)); | |
2372 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift)); | |
2373 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); | |
2374 | ixgbe_set_vmolr(hw, adapter->num_vfs); | |
2375 | } | |
2376 | ||
e8e26350 | 2377 | /* Program MRQC for the distribution of queues */ |
0cefafad | 2378 | mrqc = ixgbe_setup_mrqc(adapter); |
e8e26350 | 2379 | |
021230d4 | 2380 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { |
9a799d71 | 2381 | /* Fill out redirection table */ |
021230d4 AV |
2382 | for (i = 0, j = 0; i < 128; i++, j++) { |
2383 | if (j == adapter->ring_feature[RING_F_RSS].indices) | |
2384 | j = 0; | |
2385 | /* reta = 4-byte sliding window of | |
2386 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
2387 | reta = (reta << 8) | (j * 0x11); | |
2388 | if ((i & 3) == 3) | |
2389 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
9a799d71 AK |
2390 | } |
2391 | ||
2392 | /* Fill out hash function seeds */ | |
2393 | for (i = 0; i < 10; i++) | |
7c6e0a43 | 2394 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); |
9a799d71 | 2395 | |
2a41ff81 JB |
2396 | if (hw->mac.type == ixgbe_mac_82598EB) |
2397 | mrqc |= IXGBE_MRQC_RSSEN; | |
9a799d71 | 2398 | /* Perform hash on these packet types */ |
2a41ff81 JB |
2399 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
2400 | | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | |
2401 | | IXGBE_MRQC_RSS_FIELD_IPV4_UDP | |
2402 | | IXGBE_MRQC_RSS_FIELD_IPV6 | |
2403 | | IXGBE_MRQC_RSS_FIELD_IPV6_TCP | |
2404 | | IXGBE_MRQC_RSS_FIELD_IPV6_UDP; | |
021230d4 | 2405 | } |
2a41ff81 | 2406 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); |
9a799d71 | 2407 | |
1cdd1ec8 GR |
2408 | if (adapter->num_vfs) { |
2409 | u32 reg; | |
2410 | ||
2411 | /* Map PF MAC address in RAR Entry 0 to first pool | |
2412 | * following VFs */ | |
2413 | hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs); | |
2414 | ||
2415 | /* Set up VF register offsets for selected VT Mode, i.e. | |
2416 | * 64 VFs for SR-IOV */ | |
2417 | reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); | |
2418 | reg |= IXGBE_GCR_EXT_SRIOV; | |
2419 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg); | |
2420 | } | |
2421 | ||
021230d4 AV |
2422 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); |
2423 | ||
2424 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED || | |
2425 | adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) { | |
2426 | /* Disable indicating checksum in descriptor, enables | |
2427 | * RSS hash */ | |
9a799d71 | 2428 | rxcsum |= IXGBE_RXCSUM_PCSD; |
9a799d71 | 2429 | } |
021230d4 AV |
2430 | if (!(rxcsum & IXGBE_RXCSUM_PCSD)) { |
2431 | /* Enable IPv4 payload checksum for UDP fragments | |
2432 | * if PCSD is not set */ | |
2433 | rxcsum |= IXGBE_RXCSUM_IPPCSE; | |
2434 | } | |
2435 | ||
2436 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
e8e26350 PW |
2437 | |
2438 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
2439 | rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
2440 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
f8212f97 | 2441 | rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; |
e8e26350 PW |
2442 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); |
2443 | } | |
f8212f97 | 2444 | |
0c19d6af | 2445 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { |
f8212f97 | 2446 | /* Enable 82599 HW-RSC */ |
bb5a9ad2 | 2447 | for (i = 0; i < adapter->num_rx_queues; i++) |
edd2ea55 | 2448 | ixgbe_configure_rscctl(adapter, i); |
bb5a9ad2 | 2449 | |
f8212f97 AD |
2450 | /* Disable RSC for ACK packets */ |
2451 | IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, | |
2452 | (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); | |
2453 | } | |
9a799d71 AK |
2454 | } |
2455 | ||
068c89b0 DS |
2456 | static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
2457 | { | |
2458 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2459 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 2460 | int pool_ndx = adapter->num_vfs; |
068c89b0 DS |
2461 | |
2462 | /* add VID to filter table */ | |
1ada1b1b | 2463 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true); |
068c89b0 DS |
2464 | } |
2465 | ||
2466 | static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |
2467 | { | |
2468 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2469 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 2470 | int pool_ndx = adapter->num_vfs; |
068c89b0 DS |
2471 | |
2472 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2473 | ixgbe_irq_disable(adapter); | |
2474 | ||
2475 | vlan_group_set_device(adapter->vlgrp, vid, NULL); | |
2476 | ||
2477 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2478 | ixgbe_irq_enable(adapter); | |
2479 | ||
2480 | /* remove VID from filter table */ | |
1ada1b1b | 2481 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false); |
068c89b0 DS |
2482 | } |
2483 | ||
9a799d71 | 2484 | static void ixgbe_vlan_rx_register(struct net_device *netdev, |
b4617240 | 2485 | struct vlan_group *grp) |
9a799d71 AK |
2486 | { |
2487 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2488 | u32 ctrl; | |
e8e26350 | 2489 | int i, j; |
9a799d71 | 2490 | |
d4f80882 AV |
2491 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2492 | ixgbe_irq_disable(adapter); | |
9a799d71 AK |
2493 | adapter->vlgrp = grp; |
2494 | ||
2f90b865 AD |
2495 | /* |
2496 | * For a DCB driver, always enable VLAN tag stripping so we can | |
2497 | * still receive traffic from a DCB-enabled host even if we're | |
2498 | * not in DCB mode. | |
2499 | */ | |
2500 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL); | |
dc63d377 AD |
2501 | |
2502 | /* Disable CFI check */ | |
2503 | ctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2504 | ||
2505 | /* enable VLAN tag stripping */ | |
e8e26350 | 2506 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
dc63d377 | 2507 | ctrl |= IXGBE_VLNCTRL_VME; |
e8e26350 | 2508 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
e8e26350 | 2509 | for (i = 0; i < adapter->num_rx_queues; i++) { |
dc63d377 | 2510 | u32 ctrl; |
4a0b9ca0 | 2511 | j = adapter->rx_ring[i]->reg_idx; |
e8e26350 PW |
2512 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j)); |
2513 | ctrl |= IXGBE_RXDCTL_VME; | |
2514 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl); | |
2515 | } | |
9a799d71 | 2516 | } |
dc63d377 AD |
2517 | |
2518 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl); | |
2519 | ||
e8e26350 | 2520 | ixgbe_vlan_rx_add_vid(netdev, 0); |
9a799d71 | 2521 | |
d4f80882 AV |
2522 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2523 | ixgbe_irq_enable(adapter); | |
9a799d71 AK |
2524 | } |
2525 | ||
9a799d71 AK |
2526 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
2527 | { | |
2528 | ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp); | |
2529 | ||
2530 | if (adapter->vlgrp) { | |
2531 | u16 vid; | |
2532 | for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) { | |
2533 | if (!vlan_group_get_device(adapter->vlgrp, vid)) | |
2534 | continue; | |
2535 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
2536 | } | |
2537 | } | |
2538 | } | |
2539 | ||
2c5645cf CL |
2540 | static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq) |
2541 | { | |
2542 | struct dev_mc_list *mc_ptr; | |
2543 | u8 *addr = *mc_addr_ptr; | |
2544 | *vmdq = 0; | |
2545 | ||
2546 | mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]); | |
2547 | if (mc_ptr->next) | |
2548 | *mc_addr_ptr = mc_ptr->next->dmi_addr; | |
2549 | else | |
2550 | *mc_addr_ptr = NULL; | |
2551 | ||
2552 | return addr; | |
2553 | } | |
2554 | ||
9a799d71 | 2555 | /** |
2c5645cf | 2556 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
2557 | * @netdev: network interface device structure |
2558 | * | |
2c5645cf CL |
2559 | * The set_rx_method entry point is called whenever the unicast/multicast |
2560 | * address list or the network interface flags are updated. This routine is | |
2561 | * responsible for configuring the hardware for proper unicast, multicast and | |
2562 | * promiscuous mode. | |
9a799d71 | 2563 | **/ |
7f870475 | 2564 | void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
2565 | { |
2566 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2567 | struct ixgbe_hw *hw = &adapter->hw; | |
3d01625a | 2568 | u32 fctrl, vlnctrl; |
2c5645cf CL |
2569 | u8 *addr_list = NULL; |
2570 | int addr_count = 0; | |
9a799d71 AK |
2571 | |
2572 | /* Check for Promiscuous and All Multicast modes */ | |
2573 | ||
2574 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3d01625a | 2575 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
9a799d71 AK |
2576 | |
2577 | if (netdev->flags & IFF_PROMISC) { | |
2c5645cf | 2578 | hw->addr_ctrl.user_set_promisc = 1; |
9a799d71 | 2579 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
3d01625a | 2580 | vlnctrl &= ~IXGBE_VLNCTRL_VFE; |
9a799d71 | 2581 | } else { |
746b9f02 PM |
2582 | if (netdev->flags & IFF_ALLMULTI) { |
2583 | fctrl |= IXGBE_FCTRL_MPE; | |
2584 | fctrl &= ~IXGBE_FCTRL_UPE; | |
2585 | } else { | |
2586 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
2587 | } | |
3d01625a | 2588 | vlnctrl |= IXGBE_VLNCTRL_VFE; |
2c5645cf | 2589 | hw->addr_ctrl.user_set_promisc = 0; |
9a799d71 AK |
2590 | } |
2591 | ||
2592 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
3d01625a | 2593 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
9a799d71 | 2594 | |
2c5645cf | 2595 | /* reprogram secondary unicast list */ |
32e7bfc4 | 2596 | hw->mac.ops.update_uc_addr_list(hw, netdev); |
9a799d71 | 2597 | |
2c5645cf | 2598 | /* reprogram multicast list */ |
4cd24eaf | 2599 | addr_count = netdev_mc_count(netdev); |
2c5645cf CL |
2600 | if (addr_count) |
2601 | addr_list = netdev->mc_list->dmi_addr; | |
c44ade9e JB |
2602 | hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count, |
2603 | ixgbe_addr_list_itr); | |
1cdd1ec8 GR |
2604 | if (adapter->num_vfs) |
2605 | ixgbe_restore_vf_multicasts(adapter); | |
9a799d71 AK |
2606 | } |
2607 | ||
021230d4 AV |
2608 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
2609 | { | |
2610 | int q_idx; | |
2611 | struct ixgbe_q_vector *q_vector; | |
2612 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2613 | ||
2614 | /* legacy and MSI only use one vector */ | |
2615 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2616 | q_vectors = 1; | |
2617 | ||
2618 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
f0848276 | 2619 | struct napi_struct *napi; |
7a921c93 | 2620 | q_vector = adapter->q_vector[q_idx]; |
f0848276 | 2621 | napi = &q_vector->napi; |
91281fd3 AD |
2622 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
2623 | if (!q_vector->rxr_count || !q_vector->txr_count) { | |
2624 | if (q_vector->txr_count == 1) | |
2625 | napi->poll = &ixgbe_clean_txonly; | |
2626 | else if (q_vector->rxr_count == 1) | |
2627 | napi->poll = &ixgbe_clean_rxonly; | |
2628 | } | |
2629 | } | |
f0848276 JB |
2630 | |
2631 | napi_enable(napi); | |
021230d4 AV |
2632 | } |
2633 | } | |
2634 | ||
2635 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
2636 | { | |
2637 | int q_idx; | |
2638 | struct ixgbe_q_vector *q_vector; | |
2639 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2640 | ||
2641 | /* legacy and MSI only use one vector */ | |
2642 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2643 | q_vectors = 1; | |
2644 | ||
2645 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
7a921c93 | 2646 | q_vector = adapter->q_vector[q_idx]; |
021230d4 AV |
2647 | napi_disable(&q_vector->napi); |
2648 | } | |
2649 | } | |
2650 | ||
7a6b6f51 | 2651 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
2652 | /* |
2653 | * ixgbe_configure_dcb - Configure DCB hardware | |
2654 | * @adapter: ixgbe adapter struct | |
2655 | * | |
2656 | * This is called by the driver on open to configure the DCB hardware. | |
2657 | * This is also called by the gennetlink interface when reconfiguring | |
2658 | * the DCB state. | |
2659 | */ | |
2660 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
2661 | { | |
2662 | struct ixgbe_hw *hw = &adapter->hw; | |
2663 | u32 txdctl, vlnctrl; | |
2664 | int i, j; | |
2665 | ||
2666 | ixgbe_dcb_check_config(&adapter->dcb_cfg); | |
2667 | ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG); | |
2668 | ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG); | |
2669 | ||
2670 | /* reconfigure the hardware */ | |
2671 | ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg); | |
2672 | ||
2673 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 2674 | j = adapter->tx_ring[i]->reg_idx; |
2f90b865 AD |
2675 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); |
2676 | /* PThresh workaround for Tx hang with DFP enabled. */ | |
2677 | txdctl |= 32; | |
2678 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); | |
2679 | } | |
2680 | /* Enable VLAN tag insert/strip */ | |
2681 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
e8e26350 PW |
2682 | if (hw->mac.type == ixgbe_mac_82598EB) { |
2683 | vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE; | |
2684 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2685 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
2686 | } else if (hw->mac.type == ixgbe_mac_82599EB) { | |
2687 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
2688 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2689 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
2690 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
4a0b9ca0 | 2691 | j = adapter->rx_ring[i]->reg_idx; |
e8e26350 PW |
2692 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); |
2693 | vlnctrl |= IXGBE_RXDCTL_VME; | |
2694 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
2695 | } | |
2696 | } | |
2f90b865 AD |
2697 | hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); |
2698 | } | |
2699 | ||
2700 | #endif | |
9a799d71 AK |
2701 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
2702 | { | |
2703 | struct net_device *netdev = adapter->netdev; | |
c4cf55e5 | 2704 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
2705 | int i; |
2706 | ||
2c5645cf | 2707 | ixgbe_set_rx_mode(netdev); |
9a799d71 AK |
2708 | |
2709 | ixgbe_restore_vlan(adapter); | |
7a6b6f51 | 2710 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 | 2711 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
b352e40d YZ |
2712 | if (hw->mac.type == ixgbe_mac_82598EB) |
2713 | netif_set_gso_max_size(netdev, 32768); | |
2714 | else | |
2715 | netif_set_gso_max_size(netdev, 65536); | |
2f90b865 AD |
2716 | ixgbe_configure_dcb(adapter); |
2717 | } else { | |
2718 | netif_set_gso_max_size(netdev, 65536); | |
2719 | } | |
2720 | #else | |
2721 | netif_set_gso_max_size(netdev, 65536); | |
2722 | #endif | |
9a799d71 | 2723 | |
eacd73f7 YZ |
2724 | #ifdef IXGBE_FCOE |
2725 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
2726 | ixgbe_configure_fcoe(adapter); | |
2727 | ||
2728 | #endif /* IXGBE_FCOE */ | |
c4cf55e5 PWJ |
2729 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
2730 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 2731 | adapter->tx_ring[i]->atr_sample_rate = |
c4cf55e5 PWJ |
2732 | adapter->atr_sample_rate; |
2733 | ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc); | |
2734 | } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { | |
2735 | ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc); | |
2736 | } | |
2737 | ||
9a799d71 AK |
2738 | ixgbe_configure_tx(adapter); |
2739 | ixgbe_configure_rx(adapter); | |
2740 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 PW |
2741 | ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i], |
2742 | (adapter->rx_ring[i]->count - 1)); | |
9a799d71 AK |
2743 | } |
2744 | ||
e8e26350 PW |
2745 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
2746 | { | |
2747 | switch (hw->phy.type) { | |
2748 | case ixgbe_phy_sfp_avago: | |
2749 | case ixgbe_phy_sfp_ftl: | |
2750 | case ixgbe_phy_sfp_intel: | |
2751 | case ixgbe_phy_sfp_unknown: | |
2752 | case ixgbe_phy_tw_tyco: | |
2753 | case ixgbe_phy_tw_unknown: | |
2754 | return true; | |
2755 | default: | |
2756 | return false; | |
2757 | } | |
2758 | } | |
2759 | ||
0ecc061d | 2760 | /** |
e8e26350 PW |
2761 | * ixgbe_sfp_link_config - set up SFP+ link |
2762 | * @adapter: pointer to private adapter struct | |
2763 | **/ | |
2764 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
2765 | { | |
2766 | struct ixgbe_hw *hw = &adapter->hw; | |
2767 | ||
2768 | if (hw->phy.multispeed_fiber) { | |
2769 | /* | |
2770 | * In multispeed fiber setups, the device may not have | |
2771 | * had a physical connection when the driver loaded. | |
2772 | * If that's the case, the initial link configuration | |
2773 | * couldn't get the MAC into 10G or 1G mode, so we'll | |
2774 | * never have a link status change interrupt fire. | |
2775 | * We need to try and force an autonegotiation | |
2776 | * session, then bring up link. | |
2777 | */ | |
2778 | hw->mac.ops.setup_sfp(hw); | |
2779 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) | |
2780 | schedule_work(&adapter->multispeed_fiber_task); | |
2781 | } else { | |
2782 | /* | |
2783 | * Direct Attach Cu and non-multispeed fiber modules | |
2784 | * still need to be configured properly prior to | |
2785 | * attempting link. | |
2786 | */ | |
2787 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK)) | |
2788 | schedule_work(&adapter->sfp_config_module_task); | |
2789 | } | |
2790 | } | |
2791 | ||
2792 | /** | |
2793 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
2794 | * @hw: pointer to private hardware struct |
2795 | * | |
2796 | * Returns 0 on success, negative on failure | |
2797 | **/ | |
e8e26350 | 2798 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d PWJ |
2799 | { |
2800 | u32 autoneg; | |
8620a103 | 2801 | bool negotiation, link_up = false; |
0ecc061d PWJ |
2802 | u32 ret = IXGBE_ERR_LINK_SETUP; |
2803 | ||
2804 | if (hw->mac.ops.check_link) | |
2805 | ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
2806 | ||
2807 | if (ret) | |
2808 | goto link_cfg_out; | |
2809 | ||
2810 | if (hw->mac.ops.get_link_capabilities) | |
8620a103 | 2811 | ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation); |
0ecc061d PWJ |
2812 | if (ret) |
2813 | goto link_cfg_out; | |
2814 | ||
8620a103 MC |
2815 | if (hw->mac.ops.setup_link) |
2816 | ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up); | |
0ecc061d PWJ |
2817 | link_cfg_out: |
2818 | return ret; | |
2819 | } | |
2820 | ||
e8e26350 PW |
2821 | #define IXGBE_MAX_RX_DESC_POLL 10 |
2822 | static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
2823 | int rxr) | |
2824 | { | |
4a0b9ca0 | 2825 | int j = adapter->rx_ring[rxr]->reg_idx; |
e8e26350 PW |
2826 | int k; |
2827 | ||
2828 | for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) { | |
2829 | if (IXGBE_READ_REG(&adapter->hw, | |
2830 | IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE) | |
2831 | break; | |
2832 | else | |
2833 | msleep(1); | |
2834 | } | |
2835 | if (k >= IXGBE_MAX_RX_DESC_POLL) { | |
2836 | DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d " | |
2837 | "not set within the polling period\n", rxr); | |
2838 | } | |
4a0b9ca0 PW |
2839 | ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr], |
2840 | (adapter->rx_ring[rxr]->count - 1)); | |
e8e26350 PW |
2841 | } |
2842 | ||
9a799d71 AK |
2843 | static int ixgbe_up_complete(struct ixgbe_adapter *adapter) |
2844 | { | |
2845 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 2846 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 2847 | int i, j = 0; |
e8e26350 | 2848 | int num_rx_rings = adapter->num_rx_queues; |
0ecc061d | 2849 | int err; |
9a799d71 | 2850 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
021230d4 | 2851 | u32 txdctl, rxdctl, mhadd; |
e8e26350 | 2852 | u32 dmatxctl; |
021230d4 | 2853 | u32 gpie; |
c9205697 | 2854 | u32 ctrl_ext; |
9a799d71 | 2855 | |
5eba3699 AV |
2856 | ixgbe_get_hw_control(adapter); |
2857 | ||
021230d4 AV |
2858 | if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) || |
2859 | (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) { | |
9a799d71 AK |
2860 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
2861 | gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME | | |
b4617240 | 2862 | IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD); |
9a799d71 AK |
2863 | } else { |
2864 | /* MSI only */ | |
021230d4 | 2865 | gpie = 0; |
9a799d71 | 2866 | } |
1cdd1ec8 GR |
2867 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
2868 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
2869 | gpie |= IXGBE_GPIE_VTMODE_64; | |
2870 | } | |
021230d4 AV |
2871 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
2872 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
2873 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
9a799d71 AK |
2874 | } |
2875 | ||
9b471446 JB |
2876 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
2877 | /* | |
2878 | * use EIAM to auto-mask when MSI-X interrupt is asserted | |
2879 | * this saves a register write for every interrupt | |
2880 | */ | |
2881 | switch (hw->mac.type) { | |
2882 | case ixgbe_mac_82598EB: | |
2883 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
2884 | break; | |
2885 | default: | |
2886 | case ixgbe_mac_82599EB: | |
2887 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); | |
2888 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); | |
2889 | break; | |
2890 | } | |
2891 | } else { | |
021230d4 AV |
2892 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, |
2893 | * specifically only auto mask tx and rx interrupts */ | |
2894 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
2895 | } | |
9a799d71 | 2896 | |
0befdb3e JB |
2897 | /* Enable fan failure interrupt if media type is copper */ |
2898 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
2899 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
2900 | gpie |= IXGBE_SDP1_GPIEN; | |
2901 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
2902 | } | |
2903 | ||
e8e26350 PW |
2904 | if (hw->mac.type == ixgbe_mac_82599EB) { |
2905 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
2906 | gpie |= IXGBE_SDP1_GPIEN; | |
2907 | gpie |= IXGBE_SDP2_GPIEN; | |
2908 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
2909 | } | |
2910 | ||
63f39bd1 YZ |
2911 | #ifdef IXGBE_FCOE |
2912 | /* adjust max frame to be able to do baby jumbo for FCoE */ | |
f34c5c82 | 2913 | if ((netdev->features & NETIF_F_FCOE_MTU) && |
63f39bd1 YZ |
2914 | (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) |
2915 | max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
2916 | ||
2917 | #endif /* IXGBE_FCOE */ | |
021230d4 | 2918 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); |
9a799d71 AK |
2919 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { |
2920 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
2921 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
2922 | ||
2923 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
2924 | } | |
2925 | ||
2926 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 2927 | j = adapter->tx_ring[i]->reg_idx; |
021230d4 | 2928 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); |
e01c31a5 JB |
2929 | /* enable WTHRESH=8 descriptors, to encourage burst writeback */ |
2930 | txdctl |= (8 << 16); | |
e8e26350 PW |
2931 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); |
2932 | } | |
2933 | ||
2934 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
2935 | /* DMATXCTL.EN must be set after all Tx queue config is done */ | |
2936 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
2937 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
2938 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
2939 | } | |
2940 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 2941 | j = adapter->tx_ring[i]->reg_idx; |
e8e26350 | 2942 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); |
9a799d71 | 2943 | txdctl |= IXGBE_TXDCTL_ENABLE; |
021230d4 | 2944 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); |
1cdd1ec8 GR |
2945 | if (hw->mac.type == ixgbe_mac_82599EB) { |
2946 | int wait_loop = 10; | |
2947 | /* poll for Tx Enable ready */ | |
2948 | do { | |
2949 | msleep(1); | |
2950 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
2951 | } while (--wait_loop && | |
2952 | !(txdctl & IXGBE_TXDCTL_ENABLE)); | |
2953 | if (!wait_loop) | |
2954 | DPRINTK(DRV, ERR, "Could not enable " | |
2955 | "Tx Queue %d\n", j); | |
2956 | } | |
9a799d71 AK |
2957 | } |
2958 | ||
e8e26350 | 2959 | for (i = 0; i < num_rx_rings; i++) { |
4a0b9ca0 | 2960 | j = adapter->rx_ring[i]->reg_idx; |
021230d4 AV |
2961 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); |
2962 | /* enable PTHRESH=32 descriptors (half the internal cache) | |
2963 | * and HTHRESH=0 descriptors (to minimize latency on fetch), | |
2964 | * this also removes a pesky rx_no_buffer_count increment */ | |
2965 | rxdctl |= 0x0020; | |
9a799d71 | 2966 | rxdctl |= IXGBE_RXDCTL_ENABLE; |
021230d4 | 2967 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl); |
e8e26350 PW |
2968 | if (hw->mac.type == ixgbe_mac_82599EB) |
2969 | ixgbe_rx_desc_queue_enable(adapter, i); | |
9a799d71 AK |
2970 | } |
2971 | /* enable all receives */ | |
2972 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
e8e26350 PW |
2973 | if (hw->mac.type == ixgbe_mac_82598EB) |
2974 | rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN); | |
2975 | else | |
2976 | rxdctl |= IXGBE_RXCTRL_RXEN; | |
2977 | hw->mac.ops.enable_rx_dma(hw, rxdctl); | |
9a799d71 AK |
2978 | |
2979 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) | |
2980 | ixgbe_configure_msix(adapter); | |
2981 | else | |
2982 | ixgbe_configure_msi_and_legacy(adapter); | |
2983 | ||
2984 | clear_bit(__IXGBE_DOWN, &adapter->state); | |
021230d4 AV |
2985 | ixgbe_napi_enable_all(adapter); |
2986 | ||
2987 | /* clear any pending interrupts, may auto mask */ | |
2988 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
2989 | ||
9a799d71 AK |
2990 | ixgbe_irq_enable(adapter); |
2991 | ||
bf069c97 DS |
2992 | /* |
2993 | * If this adapter has a fan, check to see if we had a failure | |
2994 | * before we enabled the interrupt. | |
2995 | */ | |
2996 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
2997 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
2998 | if (esdp & IXGBE_ESDP_SDP1) | |
2999 | DPRINTK(DRV, CRIT, | |
3000 | "Fan has stopped, replace the adapter\n"); | |
3001 | } | |
3002 | ||
e8e26350 PW |
3003 | /* |
3004 | * For hot-pluggable SFP+ devices, a new SFP+ module may have | |
19343de2 DS |
3005 | * arrived before interrupts were enabled but after probe. Such |
3006 | * devices wouldn't have their type identified yet. We need to | |
3007 | * kick off the SFP+ module setup first, then try to bring up link. | |
e8e26350 PW |
3008 | * If we're not hot-pluggable SFP+, we just need to configure link |
3009 | * and bring it up. | |
3010 | */ | |
19343de2 DS |
3011 | if (hw->phy.type == ixgbe_phy_unknown) { |
3012 | err = hw->phy.ops.identify(hw); | |
3013 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
5da43c1a DS |
3014 | /* |
3015 | * Take the device down and schedule the sfp tasklet | |
3016 | * which will unregister_netdev and log it. | |
3017 | */ | |
19343de2 | 3018 | ixgbe_down(adapter); |
5da43c1a | 3019 | schedule_work(&adapter->sfp_config_module_task); |
19343de2 DS |
3020 | return err; |
3021 | } | |
e8e26350 PW |
3022 | } |
3023 | ||
3024 | if (ixgbe_is_sfp(hw)) { | |
3025 | ixgbe_sfp_link_config(adapter); | |
3026 | } else { | |
3027 | err = ixgbe_non_sfp_link_config(hw); | |
3028 | if (err) | |
3029 | DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err); | |
3030 | } | |
0ecc061d | 3031 | |
c4cf55e5 PWJ |
3032 | for (i = 0; i < adapter->num_tx_queues; i++) |
3033 | set_bit(__IXGBE_FDIR_INIT_DONE, | |
4a0b9ca0 | 3034 | &(adapter->tx_ring[i]->reinit_state)); |
c4cf55e5 | 3035 | |
1da100bb PWJ |
3036 | /* enable transmits */ |
3037 | netif_tx_start_all_queues(netdev); | |
3038 | ||
9a799d71 AK |
3039 | /* bring the link up in the watchdog, this could race with our first |
3040 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
3041 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
3042 | adapter->link_check_timeout = jiffies; | |
9a799d71 | 3043 | mod_timer(&adapter->watchdog_timer, jiffies); |
c9205697 GR |
3044 | |
3045 | /* Set PF Reset Done bit so PF/VF Mail Ops can work */ | |
3046 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
3047 | ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; | |
3048 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); | |
3049 | ||
9a799d71 AK |
3050 | return 0; |
3051 | } | |
3052 | ||
d4f80882 AV |
3053 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
3054 | { | |
3055 | WARN_ON(in_interrupt()); | |
3056 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) | |
3057 | msleep(1); | |
3058 | ixgbe_down(adapter); | |
5809a1ae GR |
3059 | /* |
3060 | * If SR-IOV enabled then wait a bit before bringing the adapter | |
3061 | * back up to give the VFs time to respond to the reset. The | |
3062 | * two second wait is based upon the watchdog timer cycle in | |
3063 | * the VF driver. | |
3064 | */ | |
3065 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
3066 | msleep(2000); | |
d4f80882 AV |
3067 | ixgbe_up(adapter); |
3068 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
3069 | } | |
3070 | ||
9a799d71 AK |
3071 | int ixgbe_up(struct ixgbe_adapter *adapter) |
3072 | { | |
3073 | /* hardware has been reset, we need to reload some things */ | |
3074 | ixgbe_configure(adapter); | |
3075 | ||
3076 | return ixgbe_up_complete(adapter); | |
3077 | } | |
3078 | ||
3079 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
3080 | { | |
c44ade9e | 3081 | struct ixgbe_hw *hw = &adapter->hw; |
8ca783ab DS |
3082 | int err; |
3083 | ||
3084 | err = hw->mac.ops.init_hw(hw); | |
da4dd0f7 PWJ |
3085 | switch (err) { |
3086 | case 0: | |
3087 | case IXGBE_ERR_SFP_NOT_PRESENT: | |
3088 | break; | |
3089 | case IXGBE_ERR_MASTER_REQUESTS_PENDING: | |
3090 | dev_err(&adapter->pdev->dev, "master disable timed out\n"); | |
3091 | break; | |
794caeb2 PWJ |
3092 | case IXGBE_ERR_EEPROM_VERSION: |
3093 | /* We are running on a pre-production device, log a warning */ | |
3094 | dev_warn(&adapter->pdev->dev, "This device is a pre-production " | |
3095 | "adapter/LOM. Please be aware there may be issues " | |
3096 | "associated with your hardware. If you are " | |
3097 | "experiencing problems please contact your Intel or " | |
3098 | "hardware representative who provided you with this " | |
3099 | "hardware.\n"); | |
3100 | break; | |
da4dd0f7 PWJ |
3101 | default: |
3102 | dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err); | |
3103 | } | |
9a799d71 AK |
3104 | |
3105 | /* reprogram the RAR[0] in case user changed it. */ | |
1cdd1ec8 GR |
3106 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
3107 | IXGBE_RAH_AV); | |
9a799d71 AK |
3108 | } |
3109 | ||
9a799d71 AK |
3110 | /** |
3111 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
3112 | * @adapter: board private structure | |
3113 | * @rx_ring: ring to free buffers from | |
3114 | **/ | |
3115 | static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 3116 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
3117 | { |
3118 | struct pci_dev *pdev = adapter->pdev; | |
3119 | unsigned long size; | |
3120 | unsigned int i; | |
3121 | ||
3122 | /* Free all the Rx ring sk_buffs */ | |
3123 | ||
3124 | for (i = 0; i < rx_ring->count; i++) { | |
3125 | struct ixgbe_rx_buffer *rx_buffer_info; | |
3126 | ||
3127 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
3128 | if (rx_buffer_info->dma) { | |
3129 | pci_unmap_single(pdev, rx_buffer_info->dma, | |
b4617240 PW |
3130 | rx_ring->rx_buf_len, |
3131 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
3132 | rx_buffer_info->dma = 0; |
3133 | } | |
3134 | if (rx_buffer_info->skb) { | |
f8212f97 | 3135 | struct sk_buff *skb = rx_buffer_info->skb; |
9a799d71 | 3136 | rx_buffer_info->skb = NULL; |
f8212f97 AD |
3137 | do { |
3138 | struct sk_buff *this = skb; | |
fd3686a8 | 3139 | if (IXGBE_RSC_CB(this)->dma) { |
43634e82 MC |
3140 | pci_unmap_single(pdev, IXGBE_RSC_CB(this)->dma, |
3141 | rx_ring->rx_buf_len, | |
3142 | PCI_DMA_FROMDEVICE); | |
fd3686a8 MC |
3143 | IXGBE_RSC_CB(this)->dma = 0; |
3144 | } | |
f8212f97 AD |
3145 | skb = skb->prev; |
3146 | dev_kfree_skb(this); | |
3147 | } while (skb); | |
9a799d71 AK |
3148 | } |
3149 | if (!rx_buffer_info->page) | |
3150 | continue; | |
4f57ca6e JB |
3151 | if (rx_buffer_info->page_dma) { |
3152 | pci_unmap_page(pdev, rx_buffer_info->page_dma, | |
3153 | PAGE_SIZE / 2, PCI_DMA_FROMDEVICE); | |
3154 | rx_buffer_info->page_dma = 0; | |
3155 | } | |
9a799d71 AK |
3156 | put_page(rx_buffer_info->page); |
3157 | rx_buffer_info->page = NULL; | |
762f4c57 | 3158 | rx_buffer_info->page_offset = 0; |
9a799d71 AK |
3159 | } |
3160 | ||
3161 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
3162 | memset(rx_ring->rx_buffer_info, 0, size); | |
3163 | ||
3164 | /* Zero out the descriptor ring */ | |
3165 | memset(rx_ring->desc, 0, rx_ring->size); | |
3166 | ||
3167 | rx_ring->next_to_clean = 0; | |
3168 | rx_ring->next_to_use = 0; | |
3169 | ||
9891ca7c JB |
3170 | if (rx_ring->head) |
3171 | writel(0, adapter->hw.hw_addr + rx_ring->head); | |
3172 | if (rx_ring->tail) | |
3173 | writel(0, adapter->hw.hw_addr + rx_ring->tail); | |
9a799d71 AK |
3174 | } |
3175 | ||
3176 | /** | |
3177 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
3178 | * @adapter: board private structure | |
3179 | * @tx_ring: ring to be cleaned | |
3180 | **/ | |
3181 | static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 3182 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
3183 | { |
3184 | struct ixgbe_tx_buffer *tx_buffer_info; | |
3185 | unsigned long size; | |
3186 | unsigned int i; | |
3187 | ||
3188 | /* Free all the Tx ring sk_buffs */ | |
3189 | ||
3190 | for (i = 0; i < tx_ring->count; i++) { | |
3191 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
3192 | ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info); | |
3193 | } | |
3194 | ||
3195 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; | |
3196 | memset(tx_ring->tx_buffer_info, 0, size); | |
3197 | ||
3198 | /* Zero out the descriptor ring */ | |
3199 | memset(tx_ring->desc, 0, tx_ring->size); | |
3200 | ||
3201 | tx_ring->next_to_use = 0; | |
3202 | tx_ring->next_to_clean = 0; | |
3203 | ||
9891ca7c JB |
3204 | if (tx_ring->head) |
3205 | writel(0, adapter->hw.hw_addr + tx_ring->head); | |
3206 | if (tx_ring->tail) | |
3207 | writel(0, adapter->hw.hw_addr + tx_ring->tail); | |
9a799d71 AK |
3208 | } |
3209 | ||
3210 | /** | |
021230d4 | 3211 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
3212 | * @adapter: board private structure |
3213 | **/ | |
021230d4 | 3214 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
3215 | { |
3216 | int i; | |
3217 | ||
021230d4 | 3218 | for (i = 0; i < adapter->num_rx_queues; i++) |
4a0b9ca0 | 3219 | ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]); |
9a799d71 AK |
3220 | } |
3221 | ||
3222 | /** | |
021230d4 | 3223 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
3224 | * @adapter: board private structure |
3225 | **/ | |
021230d4 | 3226 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
3227 | { |
3228 | int i; | |
3229 | ||
021230d4 | 3230 | for (i = 0; i < adapter->num_tx_queues; i++) |
4a0b9ca0 | 3231 | ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]); |
9a799d71 AK |
3232 | } |
3233 | ||
3234 | void ixgbe_down(struct ixgbe_adapter *adapter) | |
3235 | { | |
3236 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 3237 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 3238 | u32 rxctrl; |
7f821875 JB |
3239 | u32 txdctl; |
3240 | int i, j; | |
9a799d71 AK |
3241 | |
3242 | /* signal that we are down to the interrupt handler */ | |
3243 | set_bit(__IXGBE_DOWN, &adapter->state); | |
3244 | ||
767081ad GR |
3245 | /* disable receive for all VFs and wait one second */ |
3246 | if (adapter->num_vfs) { | |
767081ad GR |
3247 | /* ping all the active vfs to let them know we are going down */ |
3248 | ixgbe_ping_all_vfs(adapter); | |
581d1aa7 | 3249 | |
767081ad GR |
3250 | /* Disable all VFTE/VFRE TX/RX */ |
3251 | ixgbe_disable_tx_rx(adapter); | |
581d1aa7 GR |
3252 | |
3253 | /* Mark all the VFs as inactive */ | |
3254 | for (i = 0 ; i < adapter->num_vfs; i++) | |
3255 | adapter->vfinfo[i].clear_to_send = 0; | |
767081ad GR |
3256 | } |
3257 | ||
9a799d71 | 3258 | /* disable receives */ |
7f821875 JB |
3259 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
3260 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 AK |
3261 | |
3262 | netif_tx_disable(netdev); | |
3263 | ||
7f821875 | 3264 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
3265 | msleep(10); |
3266 | ||
7f821875 JB |
3267 | netif_tx_stop_all_queues(netdev); |
3268 | ||
9a799d71 AK |
3269 | ixgbe_irq_disable(adapter); |
3270 | ||
021230d4 | 3271 | ixgbe_napi_disable_all(adapter); |
7f821875 | 3272 | |
0a1f87cb DS |
3273 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); |
3274 | del_timer_sync(&adapter->sfp_timer); | |
9a799d71 | 3275 | del_timer_sync(&adapter->watchdog_timer); |
cf8280ee | 3276 | cancel_work_sync(&adapter->watchdog_task); |
9a799d71 | 3277 | |
c4cf55e5 PWJ |
3278 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
3279 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
3280 | cancel_work_sync(&adapter->fdir_reinit_task); | |
3281 | ||
7f821875 JB |
3282 | /* disable transmits in the hardware now that interrupts are off */ |
3283 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 3284 | j = adapter->tx_ring[i]->reg_idx; |
7f821875 JB |
3285 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); |
3286 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), | |
3287 | (txdctl & ~IXGBE_TXDCTL_ENABLE)); | |
3288 | } | |
88512539 PW |
3289 | /* Disable the Tx DMA engine on 82599 */ |
3290 | if (hw->mac.type == ixgbe_mac_82599EB) | |
3291 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, | |
3292 | (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & | |
3293 | ~IXGBE_DMATXCTL_TE)); | |
7f821875 | 3294 | |
9a799d71 | 3295 | netif_carrier_off(netdev); |
9a799d71 | 3296 | |
9a713e7c PW |
3297 | /* clear n-tuple filters that are cached */ |
3298 | ethtool_ntuple_flush(netdev); | |
3299 | ||
6f4a0e45 PL |
3300 | if (!pci_channel_offline(adapter->pdev)) |
3301 | ixgbe_reset(adapter); | |
9a799d71 AK |
3302 | ixgbe_clean_all_tx_rings(adapter); |
3303 | ixgbe_clean_all_rx_rings(adapter); | |
3304 | ||
5dd2d332 | 3305 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 | 3306 | /* since we reset the hardware DCA settings were cleared */ |
e35ec126 | 3307 | ixgbe_setup_dca(adapter); |
96b0e0f6 | 3308 | #endif |
9a799d71 AK |
3309 | } |
3310 | ||
9a799d71 | 3311 | /** |
021230d4 AV |
3312 | * ixgbe_poll - NAPI Rx polling callback |
3313 | * @napi: structure for representing this polling device | |
3314 | * @budget: how many packets driver is allowed to clean | |
3315 | * | |
3316 | * This function is used for legacy and MSI, NAPI mode | |
9a799d71 | 3317 | **/ |
021230d4 | 3318 | static int ixgbe_poll(struct napi_struct *napi, int budget) |
9a799d71 | 3319 | { |
9a1a69ad JB |
3320 | struct ixgbe_q_vector *q_vector = |
3321 | container_of(napi, struct ixgbe_q_vector, napi); | |
021230d4 | 3322 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a1a69ad | 3323 | int tx_clean_complete, work_done = 0; |
9a799d71 | 3324 | |
5dd2d332 | 3325 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 3326 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
4a0b9ca0 PW |
3327 | ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]); |
3328 | ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]); | |
bd0362dd JC |
3329 | } |
3330 | #endif | |
3331 | ||
4a0b9ca0 PW |
3332 | tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]); |
3333 | ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget); | |
9a799d71 | 3334 | |
9a1a69ad | 3335 | if (!tx_clean_complete) |
d2c7ddd6 DM |
3336 | work_done = budget; |
3337 | ||
53e52c72 DM |
3338 | /* If budget not fully consumed, exit the polling mode */ |
3339 | if (work_done < budget) { | |
288379f0 | 3340 | napi_complete(napi); |
f7554a2b | 3341 | if (adapter->rx_itr_setting & 1) |
f494e8fa | 3342 | ixgbe_set_itr(adapter); |
d4f80882 | 3343 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
835462fc | 3344 | ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE); |
9a799d71 | 3345 | } |
9a799d71 AK |
3346 | return work_done; |
3347 | } | |
3348 | ||
3349 | /** | |
3350 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
3351 | * @netdev: network interface device structure | |
3352 | **/ | |
3353 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
3354 | { | |
3355 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3356 | ||
3357 | /* Do the reset outside of interrupt context */ | |
3358 | schedule_work(&adapter->reset_task); | |
3359 | } | |
3360 | ||
3361 | static void ixgbe_reset_task(struct work_struct *work) | |
3362 | { | |
3363 | struct ixgbe_adapter *adapter; | |
3364 | adapter = container_of(work, struct ixgbe_adapter, reset_task); | |
3365 | ||
2f90b865 AD |
3366 | /* If we're already down or resetting, just bail */ |
3367 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
3368 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
3369 | return; | |
3370 | ||
9a799d71 AK |
3371 | adapter->tx_timeout_count++; |
3372 | ||
d4f80882 | 3373 | ixgbe_reinit_locked(adapter); |
9a799d71 AK |
3374 | } |
3375 | ||
bc97114d PWJ |
3376 | #ifdef CONFIG_IXGBE_DCB |
3377 | static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter) | |
b9804972 | 3378 | { |
bc97114d | 3379 | bool ret = false; |
0cefafad | 3380 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB]; |
b9804972 | 3381 | |
0cefafad JB |
3382 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) |
3383 | return ret; | |
3384 | ||
3385 | f->mask = 0x7 << 3; | |
3386 | adapter->num_rx_queues = f->indices; | |
3387 | adapter->num_tx_queues = f->indices; | |
3388 | ret = true; | |
2f90b865 | 3389 | |
bc97114d PWJ |
3390 | return ret; |
3391 | } | |
3392 | #endif | |
3393 | ||
4df10466 JB |
3394 | /** |
3395 | * ixgbe_set_rss_queues: Allocate queues for RSS | |
3396 | * @adapter: board private structure to initialize | |
3397 | * | |
3398 | * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try | |
3399 | * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. | |
3400 | * | |
3401 | **/ | |
bc97114d PWJ |
3402 | static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter) |
3403 | { | |
3404 | bool ret = false; | |
0cefafad | 3405 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS]; |
bc97114d PWJ |
3406 | |
3407 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
0cefafad JB |
3408 | f->mask = 0xF; |
3409 | adapter->num_rx_queues = f->indices; | |
3410 | adapter->num_tx_queues = f->indices; | |
bc97114d PWJ |
3411 | ret = true; |
3412 | } else { | |
bc97114d | 3413 | ret = false; |
b9804972 JB |
3414 | } |
3415 | ||
bc97114d PWJ |
3416 | return ret; |
3417 | } | |
3418 | ||
c4cf55e5 PWJ |
3419 | /** |
3420 | * ixgbe_set_fdir_queues: Allocate queues for Flow Director | |
3421 | * @adapter: board private structure to initialize | |
3422 | * | |
3423 | * Flow Director is an advanced Rx filter, attempting to get Rx flows back | |
3424 | * to the original CPU that initiated the Tx session. This runs in addition | |
3425 | * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the | |
3426 | * Rx load across CPUs using RSS. | |
3427 | * | |
3428 | **/ | |
3429 | static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter) | |
3430 | { | |
3431 | bool ret = false; | |
3432 | struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR]; | |
3433 | ||
3434 | f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices); | |
3435 | f_fdir->mask = 0; | |
3436 | ||
3437 | /* Flow Director must have RSS enabled */ | |
3438 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED && | |
3439 | ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || | |
3440 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) { | |
3441 | adapter->num_tx_queues = f_fdir->indices; | |
3442 | adapter->num_rx_queues = f_fdir->indices; | |
3443 | ret = true; | |
3444 | } else { | |
3445 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
3446 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
3447 | } | |
3448 | return ret; | |
3449 | } | |
3450 | ||
0331a832 YZ |
3451 | #ifdef IXGBE_FCOE |
3452 | /** | |
3453 | * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE) | |
3454 | * @adapter: board private structure to initialize | |
3455 | * | |
3456 | * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges. | |
3457 | * The ring feature mask is not used as a mask for FCoE, as it can take any 8 | |
3458 | * rx queues out of the max number of rx queues, instead, it is used as the | |
3459 | * index of the first rx queue used by FCoE. | |
3460 | * | |
3461 | **/ | |
3462 | static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter) | |
3463 | { | |
3464 | bool ret = false; | |
3465 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; | |
3466 | ||
3467 | f->indices = min((int)num_online_cpus(), f->indices); | |
3468 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
8de8b2e6 YZ |
3469 | adapter->num_rx_queues = 1; |
3470 | adapter->num_tx_queues = 1; | |
0331a832 YZ |
3471 | #ifdef CONFIG_IXGBE_DCB |
3472 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
8de8b2e6 | 3473 | DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n"); |
0331a832 YZ |
3474 | ixgbe_set_dcb_queues(adapter); |
3475 | } | |
3476 | #endif | |
3477 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
8de8b2e6 | 3478 | DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n"); |
8faa2a78 YZ |
3479 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || |
3480 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) | |
3481 | ixgbe_set_fdir_queues(adapter); | |
3482 | else | |
3483 | ixgbe_set_rss_queues(adapter); | |
0331a832 YZ |
3484 | } |
3485 | /* adding FCoE rx rings to the end */ | |
3486 | f->mask = adapter->num_rx_queues; | |
3487 | adapter->num_rx_queues += f->indices; | |
8de8b2e6 | 3488 | adapter->num_tx_queues += f->indices; |
0331a832 YZ |
3489 | |
3490 | ret = true; | |
3491 | } | |
3492 | ||
3493 | return ret; | |
3494 | } | |
3495 | ||
3496 | #endif /* IXGBE_FCOE */ | |
1cdd1ec8 GR |
3497 | /** |
3498 | * ixgbe_set_sriov_queues: Allocate queues for IOV use | |
3499 | * @adapter: board private structure to initialize | |
3500 | * | |
3501 | * IOV doesn't actually use anything, so just NAK the | |
3502 | * request for now and let the other queue routines | |
3503 | * figure out what to do. | |
3504 | */ | |
3505 | static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter) | |
3506 | { | |
3507 | return false; | |
3508 | } | |
3509 | ||
4df10466 JB |
3510 | /* |
3511 | * ixgbe_set_num_queues: Allocate queues for device, feature dependant | |
3512 | * @adapter: board private structure to initialize | |
3513 | * | |
3514 | * This is the top level queue allocation routine. The order here is very | |
3515 | * important, starting with the "most" number of features turned on at once, | |
3516 | * and ending with the smallest set of features. This way large combinations | |
3517 | * can be allocated if they're turned on, and smaller combinations are the | |
3518 | * fallthrough conditions. | |
3519 | * | |
3520 | **/ | |
bc97114d PWJ |
3521 | static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter) |
3522 | { | |
1cdd1ec8 GR |
3523 | /* Start with base case */ |
3524 | adapter->num_rx_queues = 1; | |
3525 | adapter->num_tx_queues = 1; | |
3526 | adapter->num_rx_pools = adapter->num_rx_queues; | |
3527 | adapter->num_rx_queues_per_pool = 1; | |
3528 | ||
3529 | if (ixgbe_set_sriov_queues(adapter)) | |
3530 | return; | |
3531 | ||
0331a832 YZ |
3532 | #ifdef IXGBE_FCOE |
3533 | if (ixgbe_set_fcoe_queues(adapter)) | |
3534 | goto done; | |
3535 | ||
3536 | #endif /* IXGBE_FCOE */ | |
bc97114d PWJ |
3537 | #ifdef CONFIG_IXGBE_DCB |
3538 | if (ixgbe_set_dcb_queues(adapter)) | |
af22ab1b | 3539 | goto done; |
bc97114d PWJ |
3540 | |
3541 | #endif | |
c4cf55e5 PWJ |
3542 | if (ixgbe_set_fdir_queues(adapter)) |
3543 | goto done; | |
3544 | ||
bc97114d | 3545 | if (ixgbe_set_rss_queues(adapter)) |
af22ab1b WF |
3546 | goto done; |
3547 | ||
3548 | /* fallback to base case */ | |
3549 | adapter->num_rx_queues = 1; | |
3550 | adapter->num_tx_queues = 1; | |
3551 | ||
3552 | done: | |
3553 | /* Notify the stack of the (possibly) reduced Tx Queue count. */ | |
3554 | adapter->netdev->real_num_tx_queues = adapter->num_tx_queues; | |
b9804972 JB |
3555 | } |
3556 | ||
021230d4 | 3557 | static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 3558 | int vectors) |
021230d4 AV |
3559 | { |
3560 | int err, vector_threshold; | |
3561 | ||
3562 | /* We'll want at least 3 (vector_threshold): | |
3563 | * 1) TxQ[0] Cleanup | |
3564 | * 2) RxQ[0] Cleanup | |
3565 | * 3) Other (Link Status Change, etc.) | |
3566 | * 4) TCP Timer (optional) | |
3567 | */ | |
3568 | vector_threshold = MIN_MSIX_COUNT; | |
3569 | ||
3570 | /* The more we get, the more we will assign to Tx/Rx Cleanup | |
3571 | * for the separate queues...where Rx Cleanup >= Tx Cleanup. | |
3572 | * Right now, we simply care about how many we'll get; we'll | |
3573 | * set them up later while requesting irq's. | |
3574 | */ | |
3575 | while (vectors >= vector_threshold) { | |
3576 | err = pci_enable_msix(adapter->pdev, adapter->msix_entries, | |
b4617240 | 3577 | vectors); |
021230d4 AV |
3578 | if (!err) /* Success in acquiring all requested vectors. */ |
3579 | break; | |
3580 | else if (err < 0) | |
3581 | vectors = 0; /* Nasty failure, quit now */ | |
3582 | else /* err == number of vectors we should try again with */ | |
3583 | vectors = err; | |
3584 | } | |
3585 | ||
3586 | if (vectors < vector_threshold) { | |
3587 | /* Can't allocate enough MSI-X interrupts? Oh well. | |
3588 | * This just means we'll go with either a single MSI | |
3589 | * vector or fall back to legacy interrupts. | |
3590 | */ | |
3591 | DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n"); | |
3592 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
3593 | kfree(adapter->msix_entries); | |
3594 | adapter->msix_entries = NULL; | |
021230d4 AV |
3595 | } else { |
3596 | adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */ | |
eb7f139c PWJ |
3597 | /* |
3598 | * Adjust for only the vectors we'll use, which is minimum | |
3599 | * of max_msix_q_vectors + NON_Q_VECTORS, or the number of | |
3600 | * vectors we were allocated. | |
3601 | */ | |
3602 | adapter->num_msix_vectors = min(vectors, | |
3603 | adapter->max_msix_q_vectors + NON_Q_VECTORS); | |
021230d4 AV |
3604 | } |
3605 | } | |
3606 | ||
021230d4 | 3607 | /** |
bc97114d | 3608 | * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS |
021230d4 AV |
3609 | * @adapter: board private structure to initialize |
3610 | * | |
bc97114d PWJ |
3611 | * Cache the descriptor ring offsets for RSS to the assigned rings. |
3612 | * | |
021230d4 | 3613 | **/ |
bc97114d | 3614 | static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter) |
021230d4 | 3615 | { |
bc97114d PWJ |
3616 | int i; |
3617 | bool ret = false; | |
3618 | ||
3619 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
3620 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 | 3621 | adapter->rx_ring[i]->reg_idx = i; |
bc97114d | 3622 | for (i = 0; i < adapter->num_tx_queues; i++) |
4a0b9ca0 | 3623 | adapter->tx_ring[i]->reg_idx = i; |
bc97114d PWJ |
3624 | ret = true; |
3625 | } else { | |
3626 | ret = false; | |
3627 | } | |
3628 | ||
3629 | return ret; | |
3630 | } | |
3631 | ||
3632 | #ifdef CONFIG_IXGBE_DCB | |
3633 | /** | |
3634 | * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB | |
3635 | * @adapter: board private structure to initialize | |
3636 | * | |
3637 | * Cache the descriptor ring offsets for DCB to the assigned rings. | |
3638 | * | |
3639 | **/ | |
3640 | static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) | |
3641 | { | |
3642 | int i; | |
3643 | bool ret = false; | |
3644 | int dcb_i = adapter->ring_feature[RING_F_DCB].indices; | |
3645 | ||
3646 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
3647 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
2f90b865 AD |
3648 | /* the number of queues is assumed to be symmetric */ |
3649 | for (i = 0; i < dcb_i; i++) { | |
4a0b9ca0 PW |
3650 | adapter->rx_ring[i]->reg_idx = i << 3; |
3651 | adapter->tx_ring[i]->reg_idx = i << 2; | |
2f90b865 | 3652 | } |
bc97114d | 3653 | ret = true; |
e8e26350 | 3654 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
f92ef202 PW |
3655 | if (dcb_i == 8) { |
3656 | /* | |
3657 | * Tx TC0 starts at: descriptor queue 0 | |
3658 | * Tx TC1 starts at: descriptor queue 32 | |
3659 | * Tx TC2 starts at: descriptor queue 64 | |
3660 | * Tx TC3 starts at: descriptor queue 80 | |
3661 | * Tx TC4 starts at: descriptor queue 96 | |
3662 | * Tx TC5 starts at: descriptor queue 104 | |
3663 | * Tx TC6 starts at: descriptor queue 112 | |
3664 | * Tx TC7 starts at: descriptor queue 120 | |
3665 | * | |
3666 | * Rx TC0-TC7 are offset by 16 queues each | |
3667 | */ | |
3668 | for (i = 0; i < 3; i++) { | |
4a0b9ca0 PW |
3669 | adapter->tx_ring[i]->reg_idx = i << 5; |
3670 | adapter->rx_ring[i]->reg_idx = i << 4; | |
f92ef202 PW |
3671 | } |
3672 | for ( ; i < 5; i++) { | |
4a0b9ca0 | 3673 | adapter->tx_ring[i]->reg_idx = |
f92ef202 | 3674 | ((i + 2) << 4); |
4a0b9ca0 | 3675 | adapter->rx_ring[i]->reg_idx = i << 4; |
f92ef202 PW |
3676 | } |
3677 | for ( ; i < dcb_i; i++) { | |
4a0b9ca0 | 3678 | adapter->tx_ring[i]->reg_idx = |
f92ef202 | 3679 | ((i + 8) << 3); |
4a0b9ca0 | 3680 | adapter->rx_ring[i]->reg_idx = i << 4; |
f92ef202 PW |
3681 | } |
3682 | ||
3683 | ret = true; | |
3684 | } else if (dcb_i == 4) { | |
3685 | /* | |
3686 | * Tx TC0 starts at: descriptor queue 0 | |
3687 | * Tx TC1 starts at: descriptor queue 64 | |
3688 | * Tx TC2 starts at: descriptor queue 96 | |
3689 | * Tx TC3 starts at: descriptor queue 112 | |
3690 | * | |
3691 | * Rx TC0-TC3 are offset by 32 queues each | |
3692 | */ | |
4a0b9ca0 PW |
3693 | adapter->tx_ring[0]->reg_idx = 0; |
3694 | adapter->tx_ring[1]->reg_idx = 64; | |
3695 | adapter->tx_ring[2]->reg_idx = 96; | |
3696 | adapter->tx_ring[3]->reg_idx = 112; | |
f92ef202 | 3697 | for (i = 0 ; i < dcb_i; i++) |
4a0b9ca0 | 3698 | adapter->rx_ring[i]->reg_idx = i << 5; |
f92ef202 PW |
3699 | |
3700 | ret = true; | |
3701 | } else { | |
3702 | ret = false; | |
e8e26350 | 3703 | } |
bc97114d PWJ |
3704 | } else { |
3705 | ret = false; | |
021230d4 | 3706 | } |
bc97114d PWJ |
3707 | } else { |
3708 | ret = false; | |
021230d4 | 3709 | } |
bc97114d PWJ |
3710 | |
3711 | return ret; | |
3712 | } | |
3713 | #endif | |
3714 | ||
c4cf55e5 PWJ |
3715 | /** |
3716 | * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director | |
3717 | * @adapter: board private structure to initialize | |
3718 | * | |
3719 | * Cache the descriptor ring offsets for Flow Director to the assigned rings. | |
3720 | * | |
3721 | **/ | |
3722 | static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter) | |
3723 | { | |
3724 | int i; | |
3725 | bool ret = false; | |
3726 | ||
3727 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED && | |
3728 | ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || | |
3729 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) { | |
3730 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 | 3731 | adapter->rx_ring[i]->reg_idx = i; |
c4cf55e5 | 3732 | for (i = 0; i < adapter->num_tx_queues; i++) |
4a0b9ca0 | 3733 | adapter->tx_ring[i]->reg_idx = i; |
c4cf55e5 PWJ |
3734 | ret = true; |
3735 | } | |
3736 | ||
3737 | return ret; | |
3738 | } | |
3739 | ||
0331a832 YZ |
3740 | #ifdef IXGBE_FCOE |
3741 | /** | |
3742 | * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE | |
3743 | * @adapter: board private structure to initialize | |
3744 | * | |
3745 | * Cache the descriptor ring offsets for FCoE mode to the assigned rings. | |
3746 | * | |
3747 | */ | |
3748 | static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter) | |
3749 | { | |
8de8b2e6 | 3750 | int i, fcoe_rx_i = 0, fcoe_tx_i = 0; |
0331a832 YZ |
3751 | bool ret = false; |
3752 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; | |
3753 | ||
3754 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
3755 | #ifdef CONFIG_IXGBE_DCB | |
3756 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
8de8b2e6 YZ |
3757 | struct ixgbe_fcoe *fcoe = &adapter->fcoe; |
3758 | ||
0331a832 | 3759 | ixgbe_cache_ring_dcb(adapter); |
8de8b2e6 | 3760 | /* find out queues in TC for FCoE */ |
4a0b9ca0 PW |
3761 | fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1; |
3762 | fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1; | |
8de8b2e6 YZ |
3763 | /* |
3764 | * In 82599, the number of Tx queues for each traffic | |
3765 | * class for both 8-TC and 4-TC modes are: | |
3766 | * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 | |
3767 | * 8 TCs: 32 32 16 16 8 8 8 8 | |
3768 | * 4 TCs: 64 64 32 32 | |
3769 | * We have max 8 queues for FCoE, where 8 the is | |
3770 | * FCoE redirection table size. If TC for FCoE is | |
3771 | * less than or equal to TC3, we have enough queues | |
3772 | * to add max of 8 queues for FCoE, so we start FCoE | |
3773 | * tx descriptor from the next one, i.e., reg_idx + 1. | |
3774 | * If TC for FCoE is above TC3, implying 8 TC mode, | |
3775 | * and we need 8 for FCoE, we have to take all queues | |
3776 | * in that traffic class for FCoE. | |
3777 | */ | |
3778 | if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3)) | |
3779 | fcoe_tx_i--; | |
0331a832 YZ |
3780 | } |
3781 | #endif /* CONFIG_IXGBE_DCB */ | |
3782 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
8faa2a78 YZ |
3783 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || |
3784 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) | |
3785 | ixgbe_cache_ring_fdir(adapter); | |
3786 | else | |
3787 | ixgbe_cache_ring_rss(adapter); | |
3788 | ||
8de8b2e6 YZ |
3789 | fcoe_rx_i = f->mask; |
3790 | fcoe_tx_i = f->mask; | |
3791 | } | |
3792 | for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) { | |
4a0b9ca0 PW |
3793 | adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i; |
3794 | adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i; | |
0331a832 | 3795 | } |
0331a832 YZ |
3796 | ret = true; |
3797 | } | |
3798 | return ret; | |
3799 | } | |
3800 | ||
3801 | #endif /* IXGBE_FCOE */ | |
1cdd1ec8 GR |
3802 | /** |
3803 | * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov | |
3804 | * @adapter: board private structure to initialize | |
3805 | * | |
3806 | * SR-IOV doesn't use any descriptor rings but changes the default if | |
3807 | * no other mapping is used. | |
3808 | * | |
3809 | */ | |
3810 | static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter) | |
3811 | { | |
4a0b9ca0 PW |
3812 | adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2; |
3813 | adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2; | |
1cdd1ec8 GR |
3814 | if (adapter->num_vfs) |
3815 | return true; | |
3816 | else | |
3817 | return false; | |
3818 | } | |
3819 | ||
bc97114d PWJ |
3820 | /** |
3821 | * ixgbe_cache_ring_register - Descriptor ring to register mapping | |
3822 | * @adapter: board private structure to initialize | |
3823 | * | |
3824 | * Once we know the feature-set enabled for the device, we'll cache | |
3825 | * the register offset the descriptor ring is assigned to. | |
3826 | * | |
3827 | * Note, the order the various feature calls is important. It must start with | |
3828 | * the "most" features enabled at the same time, then trickle down to the | |
3829 | * least amount of features turned on at once. | |
3830 | **/ | |
3831 | static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) | |
3832 | { | |
3833 | /* start with default case */ | |
4a0b9ca0 PW |
3834 | adapter->rx_ring[0]->reg_idx = 0; |
3835 | adapter->tx_ring[0]->reg_idx = 0; | |
bc97114d | 3836 | |
1cdd1ec8 GR |
3837 | if (ixgbe_cache_ring_sriov(adapter)) |
3838 | return; | |
3839 | ||
0331a832 YZ |
3840 | #ifdef IXGBE_FCOE |
3841 | if (ixgbe_cache_ring_fcoe(adapter)) | |
3842 | return; | |
3843 | ||
3844 | #endif /* IXGBE_FCOE */ | |
bc97114d PWJ |
3845 | #ifdef CONFIG_IXGBE_DCB |
3846 | if (ixgbe_cache_ring_dcb(adapter)) | |
3847 | return; | |
3848 | ||
3849 | #endif | |
c4cf55e5 PWJ |
3850 | if (ixgbe_cache_ring_fdir(adapter)) |
3851 | return; | |
3852 | ||
bc97114d PWJ |
3853 | if (ixgbe_cache_ring_rss(adapter)) |
3854 | return; | |
021230d4 AV |
3855 | } |
3856 | ||
9a799d71 AK |
3857 | /** |
3858 | * ixgbe_alloc_queues - Allocate memory for all rings | |
3859 | * @adapter: board private structure to initialize | |
3860 | * | |
3861 | * We allocate one ring per queue at run-time since we don't know the | |
4df10466 JB |
3862 | * number of queues at compile-time. The polling_netdev array is |
3863 | * intended for Multiqueue, but should work fine with a single queue. | |
9a799d71 | 3864 | **/ |
2f90b865 | 3865 | static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter) |
9a799d71 AK |
3866 | { |
3867 | int i; | |
4a0b9ca0 | 3868 | int orig_node = adapter->node; |
9a799d71 | 3869 | |
021230d4 | 3870 | for (i = 0; i < adapter->num_tx_queues; i++) { |
4a0b9ca0 PW |
3871 | struct ixgbe_ring *ring = adapter->tx_ring[i]; |
3872 | if (orig_node == -1) { | |
3873 | int cur_node = next_online_node(adapter->node); | |
3874 | if (cur_node == MAX_NUMNODES) | |
3875 | cur_node = first_online_node; | |
3876 | adapter->node = cur_node; | |
3877 | } | |
3878 | ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL, | |
3879 | adapter->node); | |
3880 | if (!ring) | |
3881 | ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL); | |
3882 | if (!ring) | |
3883 | goto err_tx_ring_allocation; | |
3884 | ring->count = adapter->tx_ring_count; | |
3885 | ring->queue_index = i; | |
3886 | ring->numa_node = adapter->node; | |
3887 | ||
3888 | adapter->tx_ring[i] = ring; | |
021230d4 | 3889 | } |
b9804972 | 3890 | |
4a0b9ca0 PW |
3891 | /* Restore the adapter's original node */ |
3892 | adapter->node = orig_node; | |
3893 | ||
9a799d71 | 3894 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 PW |
3895 | struct ixgbe_ring *ring = adapter->rx_ring[i]; |
3896 | if (orig_node == -1) { | |
3897 | int cur_node = next_online_node(adapter->node); | |
3898 | if (cur_node == MAX_NUMNODES) | |
3899 | cur_node = first_online_node; | |
3900 | adapter->node = cur_node; | |
3901 | } | |
3902 | ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL, | |
3903 | adapter->node); | |
3904 | if (!ring) | |
3905 | ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL); | |
3906 | if (!ring) | |
3907 | goto err_rx_ring_allocation; | |
3908 | ring->count = adapter->rx_ring_count; | |
3909 | ring->queue_index = i; | |
3910 | ring->numa_node = adapter->node; | |
3911 | ||
3912 | adapter->rx_ring[i] = ring; | |
021230d4 AV |
3913 | } |
3914 | ||
4a0b9ca0 PW |
3915 | /* Restore the adapter's original node */ |
3916 | adapter->node = orig_node; | |
3917 | ||
021230d4 AV |
3918 | ixgbe_cache_ring_register(adapter); |
3919 | ||
3920 | return 0; | |
3921 | ||
3922 | err_rx_ring_allocation: | |
4a0b9ca0 PW |
3923 | for (i = 0; i < adapter->num_tx_queues; i++) |
3924 | kfree(adapter->tx_ring[i]); | |
021230d4 AV |
3925 | err_tx_ring_allocation: |
3926 | return -ENOMEM; | |
3927 | } | |
3928 | ||
3929 | /** | |
3930 | * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported | |
3931 | * @adapter: board private structure to initialize | |
3932 | * | |
3933 | * Attempt to configure the interrupts using the best available | |
3934 | * capabilities of the hardware and the kernel. | |
3935 | **/ | |
feea6a57 | 3936 | static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 | 3937 | { |
8be0e467 | 3938 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 AV |
3939 | int err = 0; |
3940 | int vector, v_budget; | |
3941 | ||
3942 | /* | |
3943 | * It's easy to be greedy for MSI-X vectors, but it really | |
3944 | * doesn't do us much good if we have a lot more vectors | |
3945 | * than CPU's. So let's be conservative and only ask for | |
342bde1b | 3946 | * (roughly) the same number of vectors as there are CPU's. |
021230d4 AV |
3947 | */ |
3948 | v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues, | |
342bde1b | 3949 | (int)num_online_cpus()) + NON_Q_VECTORS; |
021230d4 AV |
3950 | |
3951 | /* | |
3952 | * At the same time, hardware can only support a maximum of | |
8be0e467 PW |
3953 | * hw.mac->max_msix_vectors vectors. With features |
3954 | * such as RSS and VMDq, we can easily surpass the number of Rx and Tx | |
3955 | * descriptor queues supported by our device. Thus, we cap it off in | |
3956 | * those rare cases where the cpu count also exceeds our vector limit. | |
021230d4 | 3957 | */ |
8be0e467 | 3958 | v_budget = min(v_budget, (int)hw->mac.max_msix_vectors); |
021230d4 AV |
3959 | |
3960 | /* A failure in MSI-X entry allocation isn't fatal, but it does | |
3961 | * mean we disable MSI-X capabilities of the adapter. */ | |
3962 | adapter->msix_entries = kcalloc(v_budget, | |
b4617240 | 3963 | sizeof(struct msix_entry), GFP_KERNEL); |
7a921c93 AD |
3964 | if (adapter->msix_entries) { |
3965 | for (vector = 0; vector < v_budget; vector++) | |
3966 | adapter->msix_entries[vector].entry = vector; | |
021230d4 | 3967 | |
7a921c93 | 3968 | ixgbe_acquire_msix_vectors(adapter, v_budget); |
021230d4 | 3969 | |
7a921c93 AD |
3970 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
3971 | goto out; | |
3972 | } | |
021230d4 | 3973 | |
7a921c93 AD |
3974 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; |
3975 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
c4cf55e5 PWJ |
3976 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; |
3977 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
3978 | adapter->atr_sample_rate = 0; | |
1cdd1ec8 GR |
3979 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
3980 | ixgbe_disable_sriov(adapter); | |
3981 | ||
7a921c93 | 3982 | ixgbe_set_num_queues(adapter); |
021230d4 | 3983 | |
021230d4 AV |
3984 | err = pci_enable_msi(adapter->pdev); |
3985 | if (!err) { | |
3986 | adapter->flags |= IXGBE_FLAG_MSI_ENABLED; | |
3987 | } else { | |
3988 | DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, " | |
b4617240 | 3989 | "falling back to legacy. Error: %d\n", err); |
021230d4 AV |
3990 | /* reset err */ |
3991 | err = 0; | |
3992 | } | |
3993 | ||
3994 | out: | |
021230d4 AV |
3995 | return err; |
3996 | } | |
3997 | ||
7a921c93 AD |
3998 | /** |
3999 | * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors | |
4000 | * @adapter: board private structure to initialize | |
4001 | * | |
4002 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
4003 | * return -ENOMEM. | |
4004 | **/ | |
4005 | static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter) | |
4006 | { | |
4007 | int q_idx, num_q_vectors; | |
4008 | struct ixgbe_q_vector *q_vector; | |
4009 | int napi_vectors; | |
4010 | int (*poll)(struct napi_struct *, int); | |
4011 | ||
4012 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
4013 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
4014 | napi_vectors = adapter->num_rx_queues; | |
91281fd3 | 4015 | poll = &ixgbe_clean_rxtx_many; |
7a921c93 AD |
4016 | } else { |
4017 | num_q_vectors = 1; | |
4018 | napi_vectors = 1; | |
4019 | poll = &ixgbe_poll; | |
4020 | } | |
4021 | ||
4022 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
1a6c14a2 JB |
4023 | q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector), |
4024 | GFP_KERNEL, adapter->node); | |
4025 | if (!q_vector) | |
4026 | q_vector = kzalloc(sizeof(struct ixgbe_q_vector), | |
4027 | GFP_KERNEL); | |
7a921c93 AD |
4028 | if (!q_vector) |
4029 | goto err_out; | |
4030 | q_vector->adapter = adapter; | |
f7554a2b NS |
4031 | if (q_vector->txr_count && !q_vector->rxr_count) |
4032 | q_vector->eitr = adapter->tx_eitr_param; | |
4033 | else | |
4034 | q_vector->eitr = adapter->rx_eitr_param; | |
fe49f04a | 4035 | q_vector->v_idx = q_idx; |
91281fd3 | 4036 | netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64); |
7a921c93 AD |
4037 | adapter->q_vector[q_idx] = q_vector; |
4038 | } | |
4039 | ||
4040 | return 0; | |
4041 | ||
4042 | err_out: | |
4043 | while (q_idx) { | |
4044 | q_idx--; | |
4045 | q_vector = adapter->q_vector[q_idx]; | |
4046 | netif_napi_del(&q_vector->napi); | |
4047 | kfree(q_vector); | |
4048 | adapter->q_vector[q_idx] = NULL; | |
4049 | } | |
4050 | return -ENOMEM; | |
4051 | } | |
4052 | ||
4053 | /** | |
4054 | * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors | |
4055 | * @adapter: board private structure to initialize | |
4056 | * | |
4057 | * This function frees the memory allocated to the q_vectors. In addition if | |
4058 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
4059 | * to freeing the q_vector. | |
4060 | **/ | |
4061 | static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter) | |
4062 | { | |
4063 | int q_idx, num_q_vectors; | |
7a921c93 | 4064 | |
91281fd3 | 4065 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
7a921c93 | 4066 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
91281fd3 | 4067 | else |
7a921c93 | 4068 | num_q_vectors = 1; |
7a921c93 AD |
4069 | |
4070 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
4071 | struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx]; | |
7a921c93 | 4072 | adapter->q_vector[q_idx] = NULL; |
91281fd3 | 4073 | netif_napi_del(&q_vector->napi); |
7a921c93 AD |
4074 | kfree(q_vector); |
4075 | } | |
4076 | } | |
4077 | ||
7b25cdba | 4078 | static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 AV |
4079 | { |
4080 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
4081 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
4082 | pci_disable_msix(adapter->pdev); | |
4083 | kfree(adapter->msix_entries); | |
4084 | adapter->msix_entries = NULL; | |
4085 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
4086 | adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; | |
4087 | pci_disable_msi(adapter->pdev); | |
4088 | } | |
4089 | return; | |
4090 | } | |
4091 | ||
4092 | /** | |
4093 | * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme | |
4094 | * @adapter: board private structure to initialize | |
4095 | * | |
4096 | * We determine which interrupt scheme to use based on... | |
4097 | * - Kernel support (MSI, MSI-X) | |
4098 | * - which can be user-defined (via MODULE_PARAM) | |
4099 | * - Hardware queue count (num_*_queues) | |
4100 | * - defined by miscellaneous hardware support/features (RSS, etc.) | |
4101 | **/ | |
2f90b865 | 4102 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) |
021230d4 AV |
4103 | { |
4104 | int err; | |
4105 | ||
4106 | /* Number of supported queues */ | |
4107 | ixgbe_set_num_queues(adapter); | |
4108 | ||
021230d4 AV |
4109 | err = ixgbe_set_interrupt_capability(adapter); |
4110 | if (err) { | |
4111 | DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n"); | |
4112 | goto err_set_interrupt; | |
9a799d71 AK |
4113 | } |
4114 | ||
7a921c93 AD |
4115 | err = ixgbe_alloc_q_vectors(adapter); |
4116 | if (err) { | |
4117 | DPRINTK(PROBE, ERR, "Unable to allocate memory for queue " | |
4118 | "vectors\n"); | |
4119 | goto err_alloc_q_vectors; | |
4120 | } | |
4121 | ||
4122 | err = ixgbe_alloc_queues(adapter); | |
4123 | if (err) { | |
4124 | DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n"); | |
4125 | goto err_alloc_queues; | |
4126 | } | |
4127 | ||
021230d4 | 4128 | DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, " |
b4617240 PW |
4129 | "Tx Queue count = %u\n", |
4130 | (adapter->num_rx_queues > 1) ? "Enabled" : | |
4131 | "Disabled", adapter->num_rx_queues, adapter->num_tx_queues); | |
021230d4 AV |
4132 | |
4133 | set_bit(__IXGBE_DOWN, &adapter->state); | |
4134 | ||
9a799d71 | 4135 | return 0; |
021230d4 | 4136 | |
7a921c93 AD |
4137 | err_alloc_queues: |
4138 | ixgbe_free_q_vectors(adapter); | |
4139 | err_alloc_q_vectors: | |
4140 | ixgbe_reset_interrupt_capability(adapter); | |
021230d4 | 4141 | err_set_interrupt: |
7a921c93 AD |
4142 | return err; |
4143 | } | |
4144 | ||
4145 | /** | |
4146 | * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings | |
4147 | * @adapter: board private structure to clear interrupt scheme on | |
4148 | * | |
4149 | * We go through and clear interrupt specific resources and reset the structure | |
4150 | * to pre-load conditions | |
4151 | **/ | |
4152 | void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter) | |
4153 | { | |
4a0b9ca0 PW |
4154 | int i; |
4155 | ||
4156 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4157 | kfree(adapter->tx_ring[i]); | |
4158 | adapter->tx_ring[i] = NULL; | |
4159 | } | |
4160 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
4161 | kfree(adapter->rx_ring[i]); | |
4162 | adapter->rx_ring[i] = NULL; | |
4163 | } | |
7a921c93 AD |
4164 | |
4165 | ixgbe_free_q_vectors(adapter); | |
4166 | ixgbe_reset_interrupt_capability(adapter); | |
9a799d71 AK |
4167 | } |
4168 | ||
c4900be0 DS |
4169 | /** |
4170 | * ixgbe_sfp_timer - worker thread to find a missing module | |
4171 | * @data: pointer to our adapter struct | |
4172 | **/ | |
4173 | static void ixgbe_sfp_timer(unsigned long data) | |
4174 | { | |
4175 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
4176 | ||
4df10466 JB |
4177 | /* |
4178 | * Do the sfp_timer outside of interrupt context due to the | |
c4900be0 DS |
4179 | * delays that sfp+ detection requires |
4180 | */ | |
4181 | schedule_work(&adapter->sfp_task); | |
4182 | } | |
4183 | ||
4184 | /** | |
4185 | * ixgbe_sfp_task - worker thread to find a missing module | |
4186 | * @work: pointer to work_struct containing our data | |
4187 | **/ | |
4188 | static void ixgbe_sfp_task(struct work_struct *work) | |
4189 | { | |
4190 | struct ixgbe_adapter *adapter = container_of(work, | |
4191 | struct ixgbe_adapter, | |
4192 | sfp_task); | |
4193 | struct ixgbe_hw *hw = &adapter->hw; | |
4194 | ||
4195 | if ((hw->phy.type == ixgbe_phy_nl) && | |
4196 | (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) { | |
4197 | s32 ret = hw->phy.ops.identify_sfp(hw); | |
63d6e1d8 | 4198 | if (ret == IXGBE_ERR_SFP_NOT_PRESENT) |
c4900be0 DS |
4199 | goto reschedule; |
4200 | ret = hw->phy.ops.reset(hw); | |
4201 | if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
88d2b81f DS |
4202 | dev_err(&adapter->pdev->dev, "failed to initialize " |
4203 | "because an unsupported SFP+ module type " | |
4204 | "was detected.\n" | |
4205 | "Reload the driver after installing a " | |
4206 | "supported module.\n"); | |
c4900be0 DS |
4207 | unregister_netdev(adapter->netdev); |
4208 | } else { | |
4209 | DPRINTK(PROBE, INFO, "detected SFP+: %d\n", | |
4210 | hw->phy.sfp_type); | |
4211 | } | |
4212 | /* don't need this routine any more */ | |
4213 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
4214 | } | |
4215 | return; | |
4216 | reschedule: | |
4217 | if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state)) | |
4218 | mod_timer(&adapter->sfp_timer, | |
4219 | round_jiffies(jiffies + (2 * HZ))); | |
4220 | } | |
4221 | ||
9a799d71 AK |
4222 | /** |
4223 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
4224 | * @adapter: board private structure to initialize | |
4225 | * | |
4226 | * ixgbe_sw_init initializes the Adapter private data structure. | |
4227 | * Fields are initialized based on PCI device information and | |
4228 | * OS network device settings (MTU size). | |
4229 | **/ | |
4230 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
4231 | { | |
4232 | struct ixgbe_hw *hw = &adapter->hw; | |
4233 | struct pci_dev *pdev = adapter->pdev; | |
9a713e7c | 4234 | struct net_device *dev = adapter->netdev; |
021230d4 | 4235 | unsigned int rss; |
7a6b6f51 | 4236 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
4237 | int j; |
4238 | struct tc_configuration *tc; | |
4239 | #endif | |
021230d4 | 4240 | |
c44ade9e JB |
4241 | /* PCI config space info */ |
4242 | ||
4243 | hw->vendor_id = pdev->vendor; | |
4244 | hw->device_id = pdev->device; | |
4245 | hw->revision_id = pdev->revision; | |
4246 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
4247 | hw->subsystem_device_id = pdev->subsystem_device; | |
4248 | ||
021230d4 AV |
4249 | /* Set capability flags */ |
4250 | rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus()); | |
4251 | adapter->ring_feature[RING_F_RSS].indices = rss; | |
4252 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; | |
2f90b865 | 4253 | adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES; |
bf069c97 DS |
4254 | if (hw->mac.type == ixgbe_mac_82598EB) { |
4255 | if (hw->device_id == IXGBE_DEV_ID_82598AT) | |
4256 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
e8e26350 | 4257 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598; |
bf069c97 | 4258 | } else if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 | 4259 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599; |
0c19d6af PWJ |
4260 | adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; |
4261 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
9a713e7c PW |
4262 | if (dev->features & NETIF_F_NTUPLE) { |
4263 | /* Flow Director perfect filter enabled */ | |
4264 | adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
4265 | adapter->atr_sample_rate = 0; | |
4266 | spin_lock_init(&adapter->fdir_perfect_lock); | |
4267 | } else { | |
4268 | /* Flow Director hash filters enabled */ | |
4269 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
4270 | adapter->atr_sample_rate = 20; | |
4271 | } | |
c4cf55e5 PWJ |
4272 | adapter->ring_feature[RING_F_FDIR].indices = |
4273 | IXGBE_MAX_FDIR_INDICES; | |
c4cf55e5 | 4274 | adapter->fdir_pballoc = 0; |
eacd73f7 | 4275 | #ifdef IXGBE_FCOE |
0d551589 YZ |
4276 | adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; |
4277 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
4278 | adapter->ring_feature[RING_F_FCOE].indices = 0; | |
61a0f421 | 4279 | #ifdef CONFIG_IXGBE_DCB |
6ee16520 YZ |
4280 | /* Default traffic class to use for FCoE */ |
4281 | adapter->fcoe.tc = IXGBE_FCOE_DEFTC; | |
61a0f421 | 4282 | #endif |
eacd73f7 | 4283 | #endif /* IXGBE_FCOE */ |
f8212f97 | 4284 | } |
2f90b865 | 4285 | |
7a6b6f51 | 4286 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
4287 | /* Configure DCB traffic classes */ |
4288 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
4289 | tc = &adapter->dcb_cfg.tc_config[j]; | |
4290 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
4291 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
4292 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
4293 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
4294 | tc->dcb_pfc = pfc_disabled; | |
4295 | } | |
4296 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; | |
4297 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
4298 | adapter->dcb_cfg.rx_pba_cfg = pba_equal; | |
264857b8 | 4299 | adapter->dcb_cfg.pfc_mode_enable = false; |
2f90b865 AD |
4300 | adapter->dcb_cfg.round_robin_enable = false; |
4301 | adapter->dcb_set_bitmap = 0x00; | |
4302 | ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, | |
4303 | adapter->ring_feature[RING_F_DCB].indices); | |
4304 | ||
4305 | #endif | |
9a799d71 AK |
4306 | |
4307 | /* default flow control settings */ | |
cd7664f6 | 4308 | hw->fc.requested_mode = ixgbe_fc_full; |
71fd570b | 4309 | hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ |
264857b8 PWJ |
4310 | #ifdef CONFIG_DCB |
4311 | adapter->last_lfc_mode = hw->fc.current_mode; | |
4312 | #endif | |
2b9ade93 JB |
4313 | hw->fc.high_water = IXGBE_DEFAULT_FCRTH; |
4314 | hw->fc.low_water = IXGBE_DEFAULT_FCRTL; | |
4315 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; | |
4316 | hw->fc.send_xon = true; | |
71fd570b | 4317 | hw->fc.disable_fc_autoneg = false; |
9a799d71 | 4318 | |
30efa5a3 | 4319 | /* enable itr by default in dynamic mode */ |
f7554a2b NS |
4320 | adapter->rx_itr_setting = 1; |
4321 | adapter->rx_eitr_param = 20000; | |
4322 | adapter->tx_itr_setting = 1; | |
4323 | adapter->tx_eitr_param = 10000; | |
30efa5a3 JB |
4324 | |
4325 | /* set defaults for eitr in MegaBytes */ | |
4326 | adapter->eitr_low = 10; | |
4327 | adapter->eitr_high = 20; | |
4328 | ||
4329 | /* set default ring sizes */ | |
4330 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
4331 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
4332 | ||
9a799d71 | 4333 | /* initialize eeprom parameters */ |
c44ade9e | 4334 | if (ixgbe_init_eeprom_params_generic(hw)) { |
9a799d71 AK |
4335 | dev_err(&pdev->dev, "EEPROM initialization failed\n"); |
4336 | return -EIO; | |
4337 | } | |
4338 | ||
021230d4 | 4339 | /* enable rx csum by default */ |
9a799d71 AK |
4340 | adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED; |
4341 | ||
1a6c14a2 JB |
4342 | /* get assigned NUMA node */ |
4343 | adapter->node = dev_to_node(&pdev->dev); | |
4344 | ||
9a799d71 AK |
4345 | set_bit(__IXGBE_DOWN, &adapter->state); |
4346 | ||
4347 | return 0; | |
4348 | } | |
4349 | ||
4350 | /** | |
4351 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
4352 | * @adapter: board private structure | |
3a581073 | 4353 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
4354 | * |
4355 | * Return 0 on success, negative on failure | |
4356 | **/ | |
4357 | int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter, | |
e01c31a5 | 4358 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
4359 | { |
4360 | struct pci_dev *pdev = adapter->pdev; | |
4361 | int size; | |
4362 | ||
3a581073 | 4363 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
4a0b9ca0 | 4364 | tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node); |
1a6c14a2 JB |
4365 | if (!tx_ring->tx_buffer_info) |
4366 | tx_ring->tx_buffer_info = vmalloc(size); | |
e01c31a5 JB |
4367 | if (!tx_ring->tx_buffer_info) |
4368 | goto err; | |
3a581073 | 4369 | memset(tx_ring->tx_buffer_info, 0, size); |
9a799d71 AK |
4370 | |
4371 | /* round up to nearest 4K */ | |
12207e49 | 4372 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 4373 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 4374 | |
3a581073 JB |
4375 | tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, |
4376 | &tx_ring->dma); | |
e01c31a5 JB |
4377 | if (!tx_ring->desc) |
4378 | goto err; | |
9a799d71 | 4379 | |
3a581073 JB |
4380 | tx_ring->next_to_use = 0; |
4381 | tx_ring->next_to_clean = 0; | |
4382 | tx_ring->work_limit = tx_ring->count; | |
9a799d71 | 4383 | return 0; |
e01c31a5 JB |
4384 | |
4385 | err: | |
4386 | vfree(tx_ring->tx_buffer_info); | |
4387 | tx_ring->tx_buffer_info = NULL; | |
4388 | DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit " | |
4389 | "descriptor ring\n"); | |
4390 | return -ENOMEM; | |
9a799d71 AK |
4391 | } |
4392 | ||
69888674 AD |
4393 | /** |
4394 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
4395 | * @adapter: board private structure | |
4396 | * | |
4397 | * If this function returns with an error, then it's possible one or | |
4398 | * more of the rings is populated (while the rest are not). It is the | |
4399 | * callers duty to clean those orphaned rings. | |
4400 | * | |
4401 | * Return 0 on success, negative on failure | |
4402 | **/ | |
4403 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
4404 | { | |
4405 | int i, err = 0; | |
4406 | ||
4407 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 4408 | err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]); |
69888674 AD |
4409 | if (!err) |
4410 | continue; | |
4411 | DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i); | |
4412 | break; | |
4413 | } | |
4414 | ||
4415 | return err; | |
4416 | } | |
4417 | ||
9a799d71 AK |
4418 | /** |
4419 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
4420 | * @adapter: board private structure | |
3a581073 | 4421 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
4422 | * |
4423 | * Returns 0 on success, negative on failure | |
4424 | **/ | |
4425 | int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, | |
b4617240 | 4426 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
4427 | { |
4428 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 4429 | int size; |
9a799d71 | 4430 | |
3a581073 | 4431 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
1a6c14a2 JB |
4432 | rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node); |
4433 | if (!rx_ring->rx_buffer_info) | |
4434 | rx_ring->rx_buffer_info = vmalloc(size); | |
3a581073 | 4435 | if (!rx_ring->rx_buffer_info) { |
9a799d71 | 4436 | DPRINTK(PROBE, ERR, |
b4617240 | 4437 | "vmalloc allocation failed for the rx desc ring\n"); |
177db6ff | 4438 | goto alloc_failed; |
9a799d71 | 4439 | } |
3a581073 | 4440 | memset(rx_ring->rx_buffer_info, 0, size); |
9a799d71 | 4441 | |
9a799d71 | 4442 | /* Round up to nearest 4K */ |
3a581073 JB |
4443 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
4444 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 4445 | |
3a581073 | 4446 | rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma); |
9a799d71 | 4447 | |
3a581073 | 4448 | if (!rx_ring->desc) { |
9a799d71 | 4449 | DPRINTK(PROBE, ERR, |
b4617240 | 4450 | "Memory allocation failed for the rx desc ring\n"); |
3a581073 | 4451 | vfree(rx_ring->rx_buffer_info); |
177db6ff | 4452 | goto alloc_failed; |
9a799d71 AK |
4453 | } |
4454 | ||
3a581073 JB |
4455 | rx_ring->next_to_clean = 0; |
4456 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
4457 | |
4458 | return 0; | |
177db6ff MC |
4459 | |
4460 | alloc_failed: | |
177db6ff | 4461 | return -ENOMEM; |
9a799d71 AK |
4462 | } |
4463 | ||
69888674 AD |
4464 | /** |
4465 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
4466 | * @adapter: board private structure | |
4467 | * | |
4468 | * If this function returns with an error, then it's possible one or | |
4469 | * more of the rings is populated (while the rest are not). It is the | |
4470 | * callers duty to clean those orphaned rings. | |
4471 | * | |
4472 | * Return 0 on success, negative on failure | |
4473 | **/ | |
4474 | ||
4475 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) | |
4476 | { | |
4477 | int i, err = 0; | |
4478 | ||
4479 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
4a0b9ca0 | 4480 | err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]); |
69888674 AD |
4481 | if (!err) |
4482 | continue; | |
4483 | DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i); | |
4484 | break; | |
4485 | } | |
4486 | ||
4487 | return err; | |
4488 | } | |
4489 | ||
9a799d71 AK |
4490 | /** |
4491 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
4492 | * @adapter: board private structure | |
4493 | * @tx_ring: Tx descriptor ring for a specific queue | |
4494 | * | |
4495 | * Free all transmit software resources | |
4496 | **/ | |
c431f97e JB |
4497 | void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter, |
4498 | struct ixgbe_ring *tx_ring) | |
9a799d71 AK |
4499 | { |
4500 | struct pci_dev *pdev = adapter->pdev; | |
4501 | ||
4502 | ixgbe_clean_tx_ring(adapter, tx_ring); | |
4503 | ||
4504 | vfree(tx_ring->tx_buffer_info); | |
4505 | tx_ring->tx_buffer_info = NULL; | |
4506 | ||
4507 | pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma); | |
4508 | ||
4509 | tx_ring->desc = NULL; | |
4510 | } | |
4511 | ||
4512 | /** | |
4513 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
4514 | * @adapter: board private structure | |
4515 | * | |
4516 | * Free all transmit software resources | |
4517 | **/ | |
4518 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
4519 | { | |
4520 | int i; | |
4521 | ||
4522 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 PW |
4523 | if (adapter->tx_ring[i]->desc) |
4524 | ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]); | |
9a799d71 AK |
4525 | } |
4526 | ||
4527 | /** | |
b4617240 | 4528 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
4529 | * @adapter: board private structure |
4530 | * @rx_ring: ring to clean the resources from | |
4531 | * | |
4532 | * Free all receive software resources | |
4533 | **/ | |
c431f97e JB |
4534 | void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter, |
4535 | struct ixgbe_ring *rx_ring) | |
9a799d71 AK |
4536 | { |
4537 | struct pci_dev *pdev = adapter->pdev; | |
4538 | ||
4539 | ixgbe_clean_rx_ring(adapter, rx_ring); | |
4540 | ||
4541 | vfree(rx_ring->rx_buffer_info); | |
4542 | rx_ring->rx_buffer_info = NULL; | |
4543 | ||
4544 | pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); | |
4545 | ||
4546 | rx_ring->desc = NULL; | |
4547 | } | |
4548 | ||
4549 | /** | |
4550 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
4551 | * @adapter: board private structure | |
4552 | * | |
4553 | * Free all receive software resources | |
4554 | **/ | |
4555 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
4556 | { | |
4557 | int i; | |
4558 | ||
4559 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 PW |
4560 | if (adapter->rx_ring[i]->desc) |
4561 | ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]); | |
9a799d71 AK |
4562 | } |
4563 | ||
9a799d71 AK |
4564 | /** |
4565 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
4566 | * @netdev: network interface device structure | |
4567 | * @new_mtu: new value for maximum frame size | |
4568 | * | |
4569 | * Returns 0 on success, negative on failure | |
4570 | **/ | |
4571 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
4572 | { | |
4573 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4574 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
4575 | ||
42c783c5 JB |
4576 | /* MTU < 68 is an error and causes problems on some kernels */ |
4577 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) | |
9a799d71 AK |
4578 | return -EINVAL; |
4579 | ||
021230d4 | 4580 | DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n", |
b4617240 | 4581 | netdev->mtu, new_mtu); |
021230d4 | 4582 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
4583 | netdev->mtu = new_mtu; |
4584 | ||
d4f80882 AV |
4585 | if (netif_running(netdev)) |
4586 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
4587 | |
4588 | return 0; | |
4589 | } | |
4590 | ||
4591 | /** | |
4592 | * ixgbe_open - Called when a network interface is made active | |
4593 | * @netdev: network interface device structure | |
4594 | * | |
4595 | * Returns 0 on success, negative value on failure | |
4596 | * | |
4597 | * The open entry point is called when a network interface is made | |
4598 | * active by the system (IFF_UP). At this point all resources needed | |
4599 | * for transmit and receive operations are allocated, the interrupt | |
4600 | * handler is registered with the OS, the watchdog timer is started, | |
4601 | * and the stack is notified that the interface is ready. | |
4602 | **/ | |
4603 | static int ixgbe_open(struct net_device *netdev) | |
4604 | { | |
4605 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4606 | int err; | |
4bebfaa5 AK |
4607 | |
4608 | /* disallow open during test */ | |
4609 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
4610 | return -EBUSY; | |
9a799d71 | 4611 | |
54386467 JB |
4612 | netif_carrier_off(netdev); |
4613 | ||
9a799d71 AK |
4614 | /* allocate transmit descriptors */ |
4615 | err = ixgbe_setup_all_tx_resources(adapter); | |
4616 | if (err) | |
4617 | goto err_setup_tx; | |
4618 | ||
9a799d71 AK |
4619 | /* allocate receive descriptors */ |
4620 | err = ixgbe_setup_all_rx_resources(adapter); | |
4621 | if (err) | |
4622 | goto err_setup_rx; | |
4623 | ||
4624 | ixgbe_configure(adapter); | |
4625 | ||
021230d4 | 4626 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
4627 | if (err) |
4628 | goto err_req_irq; | |
4629 | ||
9a799d71 AK |
4630 | err = ixgbe_up_complete(adapter); |
4631 | if (err) | |
4632 | goto err_up; | |
4633 | ||
d55b53ff JK |
4634 | netif_tx_start_all_queues(netdev); |
4635 | ||
9a799d71 AK |
4636 | return 0; |
4637 | ||
4638 | err_up: | |
5eba3699 | 4639 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
4640 | ixgbe_free_irq(adapter); |
4641 | err_req_irq: | |
9a799d71 | 4642 | err_setup_rx: |
a20a1199 | 4643 | ixgbe_free_all_rx_resources(adapter); |
9a799d71 | 4644 | err_setup_tx: |
a20a1199 | 4645 | ixgbe_free_all_tx_resources(adapter); |
9a799d71 AK |
4646 | ixgbe_reset(adapter); |
4647 | ||
4648 | return err; | |
4649 | } | |
4650 | ||
4651 | /** | |
4652 | * ixgbe_close - Disables a network interface | |
4653 | * @netdev: network interface device structure | |
4654 | * | |
4655 | * Returns 0, this is not allowed to fail | |
4656 | * | |
4657 | * The close entry point is called when an interface is de-activated | |
4658 | * by the OS. The hardware is still under the drivers control, but | |
4659 | * needs to be disabled. A global MAC reset is issued to stop the | |
4660 | * hardware, and all transmit and receive resources are freed. | |
4661 | **/ | |
4662 | static int ixgbe_close(struct net_device *netdev) | |
4663 | { | |
4664 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 AK |
4665 | |
4666 | ixgbe_down(adapter); | |
4667 | ixgbe_free_irq(adapter); | |
4668 | ||
4669 | ixgbe_free_all_tx_resources(adapter); | |
4670 | ixgbe_free_all_rx_resources(adapter); | |
4671 | ||
5eba3699 | 4672 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
4673 | |
4674 | return 0; | |
4675 | } | |
4676 | ||
b3c8b4ba AD |
4677 | #ifdef CONFIG_PM |
4678 | static int ixgbe_resume(struct pci_dev *pdev) | |
4679 | { | |
4680 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4681 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4682 | u32 err; | |
4683 | ||
4684 | pci_set_power_state(pdev, PCI_D0); | |
4685 | pci_restore_state(pdev); | |
656ab817 DS |
4686 | /* |
4687 | * pci_restore_state clears dev->state_saved so call | |
4688 | * pci_save_state to restore it. | |
4689 | */ | |
4690 | pci_save_state(pdev); | |
9ce77666 | 4691 | |
4692 | err = pci_enable_device_mem(pdev); | |
b3c8b4ba | 4693 | if (err) { |
69888674 | 4694 | printk(KERN_ERR "ixgbe: Cannot enable PCI device from " |
b3c8b4ba AD |
4695 | "suspend\n"); |
4696 | return err; | |
4697 | } | |
4698 | pci_set_master(pdev); | |
4699 | ||
dd4d8ca6 | 4700 | pci_wake_from_d3(pdev, false); |
b3c8b4ba AD |
4701 | |
4702 | err = ixgbe_init_interrupt_scheme(adapter); | |
4703 | if (err) { | |
4704 | printk(KERN_ERR "ixgbe: Cannot initialize interrupts for " | |
4705 | "device\n"); | |
4706 | return err; | |
4707 | } | |
4708 | ||
b3c8b4ba AD |
4709 | ixgbe_reset(adapter); |
4710 | ||
495dce12 WJP |
4711 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
4712 | ||
b3c8b4ba AD |
4713 | if (netif_running(netdev)) { |
4714 | err = ixgbe_open(adapter->netdev); | |
4715 | if (err) | |
4716 | return err; | |
4717 | } | |
4718 | ||
4719 | netif_device_attach(netdev); | |
4720 | ||
4721 | return 0; | |
4722 | } | |
b3c8b4ba | 4723 | #endif /* CONFIG_PM */ |
9d8d05ae RW |
4724 | |
4725 | static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) | |
b3c8b4ba AD |
4726 | { |
4727 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4728 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
e8e26350 PW |
4729 | struct ixgbe_hw *hw = &adapter->hw; |
4730 | u32 ctrl, fctrl; | |
4731 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
4732 | #ifdef CONFIG_PM |
4733 | int retval = 0; | |
4734 | #endif | |
4735 | ||
4736 | netif_device_detach(netdev); | |
4737 | ||
4738 | if (netif_running(netdev)) { | |
4739 | ixgbe_down(adapter); | |
4740 | ixgbe_free_irq(adapter); | |
4741 | ixgbe_free_all_tx_resources(adapter); | |
4742 | ixgbe_free_all_rx_resources(adapter); | |
4743 | } | |
7a921c93 | 4744 | ixgbe_clear_interrupt_scheme(adapter); |
b3c8b4ba AD |
4745 | |
4746 | #ifdef CONFIG_PM | |
4747 | retval = pci_save_state(pdev); | |
4748 | if (retval) | |
4749 | return retval; | |
4df10466 | 4750 | |
b3c8b4ba | 4751 | #endif |
e8e26350 PW |
4752 | if (wufc) { |
4753 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 4754 | |
e8e26350 PW |
4755 | /* turn on all-multi mode if wake on multicast is enabled */ |
4756 | if (wufc & IXGBE_WUFC_MC) { | |
4757 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
4758 | fctrl |= IXGBE_FCTRL_MPE; | |
4759 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
4760 | } | |
4761 | ||
4762 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
4763 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
4764 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
4765 | ||
4766 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
4767 | } else { | |
4768 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
4769 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
4770 | } | |
4771 | ||
dd4d8ca6 DS |
4772 | if (wufc && hw->mac.type == ixgbe_mac_82599EB) |
4773 | pci_wake_from_d3(pdev, true); | |
4774 | else | |
4775 | pci_wake_from_d3(pdev, false); | |
b3c8b4ba | 4776 | |
9d8d05ae RW |
4777 | *enable_wake = !!wufc; |
4778 | ||
b3c8b4ba AD |
4779 | ixgbe_release_hw_control(adapter); |
4780 | ||
4781 | pci_disable_device(pdev); | |
4782 | ||
9d8d05ae RW |
4783 | return 0; |
4784 | } | |
4785 | ||
4786 | #ifdef CONFIG_PM | |
4787 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
4788 | { | |
4789 | int retval; | |
4790 | bool wake; | |
4791 | ||
4792 | retval = __ixgbe_shutdown(pdev, &wake); | |
4793 | if (retval) | |
4794 | return retval; | |
4795 | ||
4796 | if (wake) { | |
4797 | pci_prepare_to_sleep(pdev); | |
4798 | } else { | |
4799 | pci_wake_from_d3(pdev, false); | |
4800 | pci_set_power_state(pdev, PCI_D3hot); | |
4801 | } | |
b3c8b4ba AD |
4802 | |
4803 | return 0; | |
4804 | } | |
9d8d05ae | 4805 | #endif /* CONFIG_PM */ |
b3c8b4ba AD |
4806 | |
4807 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
4808 | { | |
9d8d05ae RW |
4809 | bool wake; |
4810 | ||
4811 | __ixgbe_shutdown(pdev, &wake); | |
4812 | ||
4813 | if (system_state == SYSTEM_POWER_OFF) { | |
4814 | pci_wake_from_d3(pdev, wake); | |
4815 | pci_set_power_state(pdev, PCI_D3hot); | |
4816 | } | |
b3c8b4ba AD |
4817 | } |
4818 | ||
9a799d71 AK |
4819 | /** |
4820 | * ixgbe_update_stats - Update the board statistics counters. | |
4821 | * @adapter: board private structure | |
4822 | **/ | |
4823 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
4824 | { | |
2d86f139 | 4825 | struct net_device *netdev = adapter->netdev; |
9a799d71 | 4826 | struct ixgbe_hw *hw = &adapter->hw; |
6f11eef7 AV |
4827 | u64 total_mpc = 0; |
4828 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
eb985f09 | 4829 | u64 non_eop_descs = 0, restart_queue = 0; |
9a799d71 | 4830 | |
94b982b2 | 4831 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { |
f8212f97 | 4832 | u64 rsc_count = 0; |
94b982b2 | 4833 | u64 rsc_flush = 0; |
d51019a4 PW |
4834 | for (i = 0; i < 16; i++) |
4835 | adapter->hw_rx_no_dma_resources += | |
4836 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
94b982b2 | 4837 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 PW |
4838 | rsc_count += adapter->rx_ring[i]->rsc_count; |
4839 | rsc_flush += adapter->rx_ring[i]->rsc_flush; | |
94b982b2 MC |
4840 | } |
4841 | adapter->rsc_total_count = rsc_count; | |
4842 | adapter->rsc_total_flush = rsc_flush; | |
d51019a4 PW |
4843 | } |
4844 | ||
7ca3bc58 JB |
4845 | /* gather some stats to the adapter struct that are per queue */ |
4846 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 4847 | restart_queue += adapter->tx_ring[i]->restart_queue; |
eb985f09 | 4848 | adapter->restart_queue = restart_queue; |
7ca3bc58 JB |
4849 | |
4850 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 | 4851 | non_eop_descs += adapter->rx_ring[i]->non_eop_descs; |
eb985f09 | 4852 | adapter->non_eop_descs = non_eop_descs; |
7ca3bc58 | 4853 | |
9a799d71 | 4854 | adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
6f11eef7 AV |
4855 | for (i = 0; i < 8; i++) { |
4856 | /* for packet buffers not used, the register should read 0 */ | |
4857 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
4858 | missed_rx += mpc; | |
4859 | adapter->stats.mpc[i] += mpc; | |
4860 | total_mpc += adapter->stats.mpc[i]; | |
e8e26350 PW |
4861 | if (hw->mac.type == ixgbe_mac_82598EB) |
4862 | adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); | |
2f90b865 AD |
4863 | adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); |
4864 | adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
4865 | adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
4866 | adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
e8e26350 PW |
4867 | if (hw->mac.type == ixgbe_mac_82599EB) { |
4868 | adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, | |
4869 | IXGBE_PXONRXCNT(i)); | |
4870 | adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, | |
4871 | IXGBE_PXOFFRXCNT(i)); | |
4872 | adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
e8e26350 PW |
4873 | } else { |
4874 | adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, | |
4875 | IXGBE_PXONRXC(i)); | |
4876 | adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, | |
4877 | IXGBE_PXOFFRXC(i)); | |
4878 | } | |
2f90b865 AD |
4879 | adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw, |
4880 | IXGBE_PXONTXC(i)); | |
2f90b865 | 4881 | adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw, |
e8e26350 | 4882 | IXGBE_PXOFFTXC(i)); |
6f11eef7 AV |
4883 | } |
4884 | adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); | |
4885 | /* work around hardware counting issue */ | |
4886 | adapter->stats.gprc -= missed_rx; | |
4887 | ||
4888 | /* 82598 hardware only has a 32 bit counter in the high register */ | |
e8e26350 | 4889 | if (hw->mac.type == ixgbe_mac_82599EB) { |
aad71918 | 4890 | u64 tmp; |
e8e26350 | 4891 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); |
aad71918 BG |
4892 | tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */ |
4893 | adapter->stats.gorc += (tmp << 32); | |
e8e26350 | 4894 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); |
aad71918 BG |
4895 | tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */ |
4896 | adapter->stats.gotc += (tmp << 32); | |
e8e26350 PW |
4897 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL); |
4898 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ | |
4899 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); | |
4900 | adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); | |
c4cf55e5 PWJ |
4901 | adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); |
4902 | adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); | |
6d45522c YZ |
4903 | #ifdef IXGBE_FCOE |
4904 | adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); | |
4905 | adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); | |
4906 | adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); | |
4907 | adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); | |
4908 | adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); | |
4909 | adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); | |
4910 | #endif /* IXGBE_FCOE */ | |
e8e26350 PW |
4911 | } else { |
4912 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
4913 | adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
4914 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); | |
4915 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
4916 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
4917 | } | |
9a799d71 AK |
4918 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
4919 | adapter->stats.bprc += bprc; | |
4920 | adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 PW |
4921 | if (hw->mac.type == ixgbe_mac_82598EB) |
4922 | adapter->stats.mprc -= bprc; | |
9a799d71 AK |
4923 | adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC); |
4924 | adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
4925 | adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
4926 | adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
4927 | adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
4928 | adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
4929 | adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
9a799d71 | 4930 | adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); |
6f11eef7 AV |
4931 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
4932 | adapter->stats.lxontxc += lxon; | |
4933 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); | |
4934 | adapter->stats.lxofftxc += lxoff; | |
9a799d71 AK |
4935 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
4936 | adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); | |
6f11eef7 AV |
4937 | adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); |
4938 | /* | |
4939 | * 82598 errata - tx of flow control packets is included in tx counters | |
4940 | */ | |
4941 | xon_off_tot = lxon + lxoff; | |
4942 | adapter->stats.gptc -= xon_off_tot; | |
4943 | adapter->stats.mptc -= xon_off_tot; | |
4944 | adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
9a799d71 AK |
4945 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
4946 | adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
4947 | adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
9a799d71 AK |
4948 | adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR); |
4949 | adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
6f11eef7 | 4950 | adapter->stats.ptc64 -= xon_off_tot; |
9a799d71 AK |
4951 | adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); |
4952 | adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
4953 | adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
4954 | adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
4955 | adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
9a799d71 AK |
4956 | adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); |
4957 | ||
4958 | /* Fill out the OS statistics structure */ | |
2d86f139 | 4959 | netdev->stats.multicast = adapter->stats.mprc; |
9a799d71 AK |
4960 | |
4961 | /* Rx Errors */ | |
2d86f139 | 4962 | netdev->stats.rx_errors = adapter->stats.crcerrs + |
b4617240 | 4963 | adapter->stats.rlec; |
2d86f139 AK |
4964 | netdev->stats.rx_dropped = 0; |
4965 | netdev->stats.rx_length_errors = adapter->stats.rlec; | |
4966 | netdev->stats.rx_crc_errors = adapter->stats.crcerrs; | |
4967 | netdev->stats.rx_missed_errors = total_mpc; | |
9a799d71 AK |
4968 | } |
4969 | ||
4970 | /** | |
4971 | * ixgbe_watchdog - Timer Call-back | |
4972 | * @data: pointer to adapter cast into an unsigned long | |
4973 | **/ | |
4974 | static void ixgbe_watchdog(unsigned long data) | |
4975 | { | |
4976 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
cf8280ee | 4977 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
4978 | u64 eics = 0; |
4979 | int i; | |
cf8280ee | 4980 | |
fe49f04a AD |
4981 | /* |
4982 | * Do the watchdog outside of interrupt context due to the lovely | |
4983 | * delays that some of the newer hardware requires | |
4984 | */ | |
22d5a71b | 4985 | |
fe49f04a AD |
4986 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
4987 | goto watchdog_short_circuit; | |
22d5a71b | 4988 | |
fe49f04a AD |
4989 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
4990 | /* | |
4991 | * for legacy and MSI interrupts don't set any bits | |
4992 | * that are enabled for EIAM, because this operation | |
4993 | * would set *both* EIMS and EICS for any bit in EIAM | |
4994 | */ | |
4995 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
4996 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
4997 | goto watchdog_reschedule; | |
4998 | } | |
4999 | ||
5000 | /* get one bit for every active tx/rx interrupt vector */ | |
5001 | for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) { | |
5002 | struct ixgbe_q_vector *qv = adapter->q_vector[i]; | |
5003 | if (qv->rxr_count || qv->txr_count) | |
5004 | eics |= ((u64)1 << i); | |
cf8280ee | 5005 | } |
9a799d71 | 5006 | |
fe49f04a AD |
5007 | /* Cause software interrupt to ensure rx rings are cleaned */ |
5008 | ixgbe_irq_rearm_queues(adapter, eics); | |
5009 | ||
5010 | watchdog_reschedule: | |
5011 | /* Reset the timer */ | |
5012 | mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ)); | |
5013 | ||
5014 | watchdog_short_circuit: | |
cf8280ee JB |
5015 | schedule_work(&adapter->watchdog_task); |
5016 | } | |
5017 | ||
e8e26350 PW |
5018 | /** |
5019 | * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber | |
5020 | * @work: pointer to work_struct containing our data | |
5021 | **/ | |
5022 | static void ixgbe_multispeed_fiber_task(struct work_struct *work) | |
5023 | { | |
5024 | struct ixgbe_adapter *adapter = container_of(work, | |
5025 | struct ixgbe_adapter, | |
5026 | multispeed_fiber_task); | |
5027 | struct ixgbe_hw *hw = &adapter->hw; | |
5028 | u32 autoneg; | |
8620a103 | 5029 | bool negotiation; |
e8e26350 PW |
5030 | |
5031 | adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK; | |
a1f25324 MC |
5032 | autoneg = hw->phy.autoneg_advertised; |
5033 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
8620a103 | 5034 | hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation); |
1097cd17 | 5035 | hw->mac.autotry_restart = false; |
8620a103 MC |
5036 | if (hw->mac.ops.setup_link) |
5037 | hw->mac.ops.setup_link(hw, autoneg, negotiation, true); | |
e8e26350 PW |
5038 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
5039 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK; | |
5040 | } | |
5041 | ||
5042 | /** | |
5043 | * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module | |
5044 | * @work: pointer to work_struct containing our data | |
5045 | **/ | |
5046 | static void ixgbe_sfp_config_module_task(struct work_struct *work) | |
5047 | { | |
5048 | struct ixgbe_adapter *adapter = container_of(work, | |
5049 | struct ixgbe_adapter, | |
5050 | sfp_config_module_task); | |
5051 | struct ixgbe_hw *hw = &adapter->hw; | |
5052 | u32 err; | |
5053 | ||
5054 | adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK; | |
63d6e1d8 DS |
5055 | |
5056 | /* Time for electrical oscillations to settle down */ | |
5057 | msleep(100); | |
e8e26350 | 5058 | err = hw->phy.ops.identify_sfp(hw); |
63d6e1d8 | 5059 | |
e8e26350 | 5060 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { |
88d2b81f DS |
5061 | dev_err(&adapter->pdev->dev, "failed to initialize because " |
5062 | "an unsupported SFP+ module type was detected.\n" | |
5063 | "Reload the driver after installing a supported " | |
5064 | "module.\n"); | |
63d6e1d8 | 5065 | unregister_netdev(adapter->netdev); |
e8e26350 PW |
5066 | return; |
5067 | } | |
5068 | hw->mac.ops.setup_sfp(hw); | |
5069 | ||
8d1c3c07 | 5070 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) |
e8e26350 PW |
5071 | /* This will also work for DA Twinax connections */ |
5072 | schedule_work(&adapter->multispeed_fiber_task); | |
5073 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK; | |
5074 | } | |
5075 | ||
c4cf55e5 PWJ |
5076 | /** |
5077 | * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table | |
5078 | * @work: pointer to work_struct containing our data | |
5079 | **/ | |
5080 | static void ixgbe_fdir_reinit_task(struct work_struct *work) | |
5081 | { | |
5082 | struct ixgbe_adapter *adapter = container_of(work, | |
5083 | struct ixgbe_adapter, | |
5084 | fdir_reinit_task); | |
5085 | struct ixgbe_hw *hw = &adapter->hw; | |
5086 | int i; | |
5087 | ||
5088 | if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { | |
5089 | for (i = 0; i < adapter->num_tx_queues; i++) | |
5090 | set_bit(__IXGBE_FDIR_INIT_DONE, | |
4a0b9ca0 | 5091 | &(adapter->tx_ring[i]->reinit_state)); |
c4cf55e5 PWJ |
5092 | } else { |
5093 | DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, " | |
5094 | "ignored adding FDIR ATR filters \n"); | |
5095 | } | |
5096 | /* Done FDIR Re-initialization, enable transmits */ | |
5097 | netif_tx_start_all_queues(adapter->netdev); | |
5098 | } | |
5099 | ||
10eec955 JF |
5100 | static DEFINE_MUTEX(ixgbe_watchdog_lock); |
5101 | ||
cf8280ee | 5102 | /** |
69888674 AD |
5103 | * ixgbe_watchdog_task - worker thread to bring link up |
5104 | * @work: pointer to work_struct containing our data | |
cf8280ee JB |
5105 | **/ |
5106 | static void ixgbe_watchdog_task(struct work_struct *work) | |
5107 | { | |
5108 | struct ixgbe_adapter *adapter = container_of(work, | |
5109 | struct ixgbe_adapter, | |
5110 | watchdog_task); | |
5111 | struct net_device *netdev = adapter->netdev; | |
5112 | struct ixgbe_hw *hw = &adapter->hw; | |
10eec955 JF |
5113 | u32 link_speed; |
5114 | bool link_up; | |
bc59fcda NS |
5115 | int i; |
5116 | struct ixgbe_ring *tx_ring; | |
5117 | int some_tx_pending = 0; | |
cf8280ee | 5118 | |
10eec955 JF |
5119 | mutex_lock(&ixgbe_watchdog_lock); |
5120 | ||
5121 | link_up = adapter->link_up; | |
5122 | link_speed = adapter->link_speed; | |
cf8280ee JB |
5123 | |
5124 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { | |
5125 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
264857b8 PWJ |
5126 | if (link_up) { |
5127 | #ifdef CONFIG_DCB | |
5128 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
5129 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) | |
620fa036 | 5130 | hw->mac.ops.fc_enable(hw, i); |
264857b8 | 5131 | } else { |
620fa036 | 5132 | hw->mac.ops.fc_enable(hw, 0); |
264857b8 PWJ |
5133 | } |
5134 | #else | |
620fa036 | 5135 | hw->mac.ops.fc_enable(hw, 0); |
264857b8 PWJ |
5136 | #endif |
5137 | } | |
5138 | ||
cf8280ee JB |
5139 | if (link_up || |
5140 | time_after(jiffies, (adapter->link_check_timeout + | |
5141 | IXGBE_TRY_LINK_TIMEOUT))) { | |
cf8280ee | 5142 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; |
264857b8 | 5143 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); |
cf8280ee JB |
5144 | } |
5145 | adapter->link_up = link_up; | |
5146 | adapter->link_speed = link_speed; | |
5147 | } | |
9a799d71 AK |
5148 | |
5149 | if (link_up) { | |
5150 | if (!netif_carrier_ok(netdev)) { | |
e8e26350 PW |
5151 | bool flow_rx, flow_tx; |
5152 | ||
5153 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
5154 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
5155 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
078788b6 PWJ |
5156 | flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); |
5157 | flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
e8e26350 PW |
5158 | } else { |
5159 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
5160 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
078788b6 PWJ |
5161 | flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); |
5162 | flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); | |
e8e26350 PW |
5163 | } |
5164 | ||
a46e534b JK |
5165 | printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, " |
5166 | "Flow Control: %s\n", | |
5167 | netdev->name, | |
5168 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? | |
5169 | "10 Gbps" : | |
5170 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
5171 | "1 Gbps" : "unknown speed")), | |
e8e26350 PW |
5172 | ((flow_rx && flow_tx) ? "RX/TX" : |
5173 | (flow_rx ? "RX" : | |
5174 | (flow_tx ? "TX" : "None")))); | |
9a799d71 AK |
5175 | |
5176 | netif_carrier_on(netdev); | |
9a799d71 AK |
5177 | } else { |
5178 | /* Force detection of hung controller */ | |
5179 | adapter->detect_tx_hung = true; | |
5180 | } | |
5181 | } else { | |
cf8280ee JB |
5182 | adapter->link_up = false; |
5183 | adapter->link_speed = 0; | |
9a799d71 | 5184 | if (netif_carrier_ok(netdev)) { |
a46e534b JK |
5185 | printk(KERN_INFO "ixgbe: %s NIC Link is Down\n", |
5186 | netdev->name); | |
9a799d71 | 5187 | netif_carrier_off(netdev); |
9a799d71 AK |
5188 | } |
5189 | } | |
5190 | ||
bc59fcda NS |
5191 | if (!netif_carrier_ok(netdev)) { |
5192 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 5193 | tx_ring = adapter->tx_ring[i]; |
bc59fcda NS |
5194 | if (tx_ring->next_to_use != tx_ring->next_to_clean) { |
5195 | some_tx_pending = 1; | |
5196 | break; | |
5197 | } | |
5198 | } | |
5199 | ||
5200 | if (some_tx_pending) { | |
5201 | /* We've lost link, so the controller stops DMA, | |
5202 | * but we've got queued Tx work that's never going | |
5203 | * to get done, so reset controller to flush Tx. | |
5204 | * (Do the reset outside of interrupt context). | |
5205 | */ | |
5206 | schedule_work(&adapter->reset_task); | |
5207 | } | |
5208 | } | |
5209 | ||
9a799d71 | 5210 | ixgbe_update_stats(adapter); |
10eec955 | 5211 | mutex_unlock(&ixgbe_watchdog_lock); |
9a799d71 AK |
5212 | } |
5213 | ||
9a799d71 | 5214 | static int ixgbe_tso(struct ixgbe_adapter *adapter, |
b4617240 PW |
5215 | struct ixgbe_ring *tx_ring, struct sk_buff *skb, |
5216 | u32 tx_flags, u8 *hdr_len) | |
9a799d71 AK |
5217 | { |
5218 | struct ixgbe_adv_tx_context_desc *context_desc; | |
5219 | unsigned int i; | |
5220 | int err; | |
5221 | struct ixgbe_tx_buffer *tx_buffer_info; | |
9f8cdf4f JB |
5222 | u32 vlan_macip_lens = 0, type_tucmd_mlhl; |
5223 | u32 mss_l4len_idx, l4len; | |
9a799d71 AK |
5224 | |
5225 | if (skb_is_gso(skb)) { | |
5226 | if (skb_header_cloned(skb)) { | |
5227 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
5228 | if (err) | |
5229 | return err; | |
5230 | } | |
5231 | l4len = tcp_hdrlen(skb); | |
5232 | *hdr_len += l4len; | |
5233 | ||
8327d000 | 5234 | if (skb->protocol == htons(ETH_P_IP)) { |
9a799d71 AK |
5235 | struct iphdr *iph = ip_hdr(skb); |
5236 | iph->tot_len = 0; | |
5237 | iph->check = 0; | |
5238 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
b4617240 PW |
5239 | iph->daddr, 0, |
5240 | IPPROTO_TCP, | |
5241 | 0); | |
8e1e8a47 | 5242 | } else if (skb_is_gso_v6(skb)) { |
9a799d71 AK |
5243 | ipv6_hdr(skb)->payload_len = 0; |
5244 | tcp_hdr(skb)->check = | |
5245 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
b4617240 PW |
5246 | &ipv6_hdr(skb)->daddr, |
5247 | 0, IPPROTO_TCP, 0); | |
9a799d71 AK |
5248 | } |
5249 | ||
5250 | i = tx_ring->next_to_use; | |
5251 | ||
5252 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
5253 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
5254 | ||
5255 | /* VLAN MACLEN IPLEN */ | |
5256 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
5257 | vlan_macip_lens |= | |
5258 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
5259 | vlan_macip_lens |= ((skb_network_offset(skb)) << | |
b4617240 | 5260 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
5261 | *hdr_len += skb_network_offset(skb); |
5262 | vlan_macip_lens |= | |
5263 | (skb_transport_header(skb) - skb_network_header(skb)); | |
5264 | *hdr_len += | |
5265 | (skb_transport_header(skb) - skb_network_header(skb)); | |
5266 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
5267 | context_desc->seqnum_seed = 0; | |
5268 | ||
5269 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ | |
9f8cdf4f | 5270 | type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT | |
b4617240 | 5271 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 | 5272 | |
8327d000 | 5273 | if (skb->protocol == htons(ETH_P_IP)) |
9a799d71 AK |
5274 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
5275 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
5276 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
5277 | ||
5278 | /* MSS L4LEN IDX */ | |
9f8cdf4f | 5279 | mss_l4len_idx = |
9a799d71 AK |
5280 | (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT); |
5281 | mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT); | |
4eeae6fd PW |
5282 | /* use index 1 for TSO */ |
5283 | mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
5284 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); |
5285 | ||
5286 | tx_buffer_info->time_stamp = jiffies; | |
5287 | tx_buffer_info->next_to_watch = i; | |
5288 | ||
5289 | i++; | |
5290 | if (i == tx_ring->count) | |
5291 | i = 0; | |
5292 | tx_ring->next_to_use = i; | |
5293 | ||
5294 | return true; | |
5295 | } | |
5296 | return false; | |
5297 | } | |
5298 | ||
5299 | static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter, | |
b4617240 PW |
5300 | struct ixgbe_ring *tx_ring, |
5301 | struct sk_buff *skb, u32 tx_flags) | |
9a799d71 AK |
5302 | { |
5303 | struct ixgbe_adv_tx_context_desc *context_desc; | |
5304 | unsigned int i; | |
5305 | struct ixgbe_tx_buffer *tx_buffer_info; | |
5306 | u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0; | |
5307 | ||
5308 | if (skb->ip_summed == CHECKSUM_PARTIAL || | |
5309 | (tx_flags & IXGBE_TX_FLAGS_VLAN)) { | |
5310 | i = tx_ring->next_to_use; | |
5311 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
5312 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
5313 | ||
5314 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
5315 | vlan_macip_lens |= | |
5316 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
5317 | vlan_macip_lens |= (skb_network_offset(skb) << | |
b4617240 | 5318 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
5319 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
5320 | vlan_macip_lens |= (skb_transport_header(skb) - | |
b4617240 | 5321 | skb_network_header(skb)); |
9a799d71 AK |
5322 | |
5323 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
5324 | context_desc->seqnum_seed = 0; | |
5325 | ||
5326 | type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT | | |
b4617240 | 5327 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 AK |
5328 | |
5329 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
ca553980 GS |
5330 | __be16 protocol; |
5331 | ||
5332 | if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) { | |
5333 | const struct vlan_ethhdr *vhdr = | |
5334 | (const struct vlan_ethhdr *)skb->data; | |
5335 | ||
5336 | protocol = vhdr->h_vlan_encapsulated_proto; | |
5337 | } else { | |
5338 | protocol = skb->protocol; | |
5339 | } | |
5340 | ||
5341 | switch (protocol) { | |
09640e63 | 5342 | case cpu_to_be16(ETH_P_IP): |
9a799d71 | 5343 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
41825d71 AK |
5344 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) |
5345 | type_tucmd_mlhl |= | |
b4617240 | 5346 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
45a5ead0 JB |
5347 | else if (ip_hdr(skb)->protocol == IPPROTO_SCTP) |
5348 | type_tucmd_mlhl |= | |
5349 | IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
41825d71 | 5350 | break; |
09640e63 | 5351 | case cpu_to_be16(ETH_P_IPV6): |
41825d71 AK |
5352 | /* XXX what about other V6 headers?? */ |
5353 | if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) | |
5354 | type_tucmd_mlhl |= | |
b4617240 | 5355 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
45a5ead0 JB |
5356 | else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP) |
5357 | type_tucmd_mlhl |= | |
5358 | IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
41825d71 | 5359 | break; |
41825d71 AK |
5360 | default: |
5361 | if (unlikely(net_ratelimit())) { | |
5362 | DPRINTK(PROBE, WARNING, | |
5363 | "partial checksum but proto=%x!\n", | |
5364 | skb->protocol); | |
5365 | } | |
5366 | break; | |
5367 | } | |
9a799d71 AK |
5368 | } |
5369 | ||
5370 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
4eeae6fd | 5371 | /* use index zero for tx checksum offload */ |
9a799d71 AK |
5372 | context_desc->mss_l4len_idx = 0; |
5373 | ||
5374 | tx_buffer_info->time_stamp = jiffies; | |
5375 | tx_buffer_info->next_to_watch = i; | |
9f8cdf4f | 5376 | |
9a799d71 AK |
5377 | i++; |
5378 | if (i == tx_ring->count) | |
5379 | i = 0; | |
5380 | tx_ring->next_to_use = i; | |
5381 | ||
5382 | return true; | |
5383 | } | |
9f8cdf4f | 5384 | |
9a799d71 AK |
5385 | return false; |
5386 | } | |
5387 | ||
5388 | static int ixgbe_tx_map(struct ixgbe_adapter *adapter, | |
b4617240 | 5389 | struct ixgbe_ring *tx_ring, |
eacd73f7 YZ |
5390 | struct sk_buff *skb, u32 tx_flags, |
5391 | unsigned int first) | |
9a799d71 | 5392 | { |
e5a43549 | 5393 | struct pci_dev *pdev = adapter->pdev; |
9a799d71 | 5394 | struct ixgbe_tx_buffer *tx_buffer_info; |
eacd73f7 YZ |
5395 | unsigned int len; |
5396 | unsigned int total = skb->len; | |
9a799d71 AK |
5397 | unsigned int offset = 0, size, count = 0, i; |
5398 | unsigned int nr_frags = skb_shinfo(skb)->nr_frags; | |
5399 | unsigned int f; | |
9a799d71 AK |
5400 | |
5401 | i = tx_ring->next_to_use; | |
5402 | ||
eacd73f7 YZ |
5403 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) |
5404 | /* excluding fcoe_crc_eof for FCoE */ | |
5405 | total -= sizeof(struct fcoe_crc_eof); | |
5406 | ||
5407 | len = min(skb_headlen(skb), total); | |
9a799d71 AK |
5408 | while (len) { |
5409 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
5410 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
5411 | ||
5412 | tx_buffer_info->length = size; | |
e5a43549 AD |
5413 | tx_buffer_info->mapped_as_page = false; |
5414 | tx_buffer_info->dma = pci_map_single(pdev, | |
5415 | skb->data + offset, | |
5416 | size, PCI_DMA_TODEVICE); | |
5417 | if (pci_dma_mapping_error(pdev, tx_buffer_info->dma)) | |
5418 | goto dma_error; | |
9a799d71 AK |
5419 | tx_buffer_info->time_stamp = jiffies; |
5420 | tx_buffer_info->next_to_watch = i; | |
5421 | ||
5422 | len -= size; | |
eacd73f7 | 5423 | total -= size; |
9a799d71 AK |
5424 | offset += size; |
5425 | count++; | |
44df32c5 AD |
5426 | |
5427 | if (len) { | |
5428 | i++; | |
5429 | if (i == tx_ring->count) | |
5430 | i = 0; | |
5431 | } | |
9a799d71 AK |
5432 | } |
5433 | ||
5434 | for (f = 0; f < nr_frags; f++) { | |
5435 | struct skb_frag_struct *frag; | |
5436 | ||
5437 | frag = &skb_shinfo(skb)->frags[f]; | |
eacd73f7 | 5438 | len = min((unsigned int)frag->size, total); |
e5a43549 | 5439 | offset = frag->page_offset; |
9a799d71 AK |
5440 | |
5441 | while (len) { | |
44df32c5 AD |
5442 | i++; |
5443 | if (i == tx_ring->count) | |
5444 | i = 0; | |
5445 | ||
9a799d71 AK |
5446 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
5447 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
5448 | ||
5449 | tx_buffer_info->length = size; | |
e5a43549 AD |
5450 | tx_buffer_info->dma = pci_map_page(adapter->pdev, |
5451 | frag->page, | |
5452 | offset, size, | |
5453 | PCI_DMA_TODEVICE); | |
5454 | tx_buffer_info->mapped_as_page = true; | |
5455 | if (pci_dma_mapping_error(pdev, tx_buffer_info->dma)) | |
5456 | goto dma_error; | |
9a799d71 AK |
5457 | tx_buffer_info->time_stamp = jiffies; |
5458 | tx_buffer_info->next_to_watch = i; | |
5459 | ||
5460 | len -= size; | |
eacd73f7 | 5461 | total -= size; |
9a799d71 AK |
5462 | offset += size; |
5463 | count++; | |
9a799d71 | 5464 | } |
eacd73f7 YZ |
5465 | if (total == 0) |
5466 | break; | |
9a799d71 | 5467 | } |
44df32c5 | 5468 | |
9a799d71 AK |
5469 | tx_ring->tx_buffer_info[i].skb = skb; |
5470 | tx_ring->tx_buffer_info[first].next_to_watch = i; | |
5471 | ||
e5a43549 AD |
5472 | return count; |
5473 | ||
5474 | dma_error: | |
5475 | dev_err(&pdev->dev, "TX DMA map failed\n"); | |
5476 | ||
5477 | /* clear timestamp and dma mappings for failed tx_buffer_info map */ | |
5478 | tx_buffer_info->dma = 0; | |
5479 | tx_buffer_info->time_stamp = 0; | |
5480 | tx_buffer_info->next_to_watch = 0; | |
c1fa347f RK |
5481 | if (count) |
5482 | count--; | |
e5a43549 AD |
5483 | |
5484 | /* clear timestamp and dma mappings for remaining portion of packet */ | |
c1fa347f RK |
5485 | while (count--) { |
5486 | if (i==0) | |
e5a43549 | 5487 | i += tx_ring->count; |
c1fa347f | 5488 | i--; |
e5a43549 AD |
5489 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
5490 | ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info); | |
5491 | } | |
5492 | ||
e44d38e1 | 5493 | return 0; |
9a799d71 AK |
5494 | } |
5495 | ||
5496 | static void ixgbe_tx_queue(struct ixgbe_adapter *adapter, | |
b4617240 PW |
5497 | struct ixgbe_ring *tx_ring, |
5498 | int tx_flags, int count, u32 paylen, u8 hdr_len) | |
9a799d71 AK |
5499 | { |
5500 | union ixgbe_adv_tx_desc *tx_desc = NULL; | |
5501 | struct ixgbe_tx_buffer *tx_buffer_info; | |
5502 | u32 olinfo_status = 0, cmd_type_len = 0; | |
5503 | unsigned int i; | |
5504 | u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS; | |
5505 | ||
5506 | cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA; | |
5507 | ||
5508 | cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT; | |
5509 | ||
5510 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
5511 | cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE; | |
5512 | ||
5513 | if (tx_flags & IXGBE_TX_FLAGS_TSO) { | |
5514 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
5515 | ||
5516 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 5517 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 5518 | |
4eeae6fd PW |
5519 | /* use index 1 context for tso */ |
5520 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
5521 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) |
5522 | olinfo_status |= IXGBE_TXD_POPTS_IXSM << | |
b4617240 | 5523 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 AK |
5524 | |
5525 | } else if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
5526 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 5527 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 5528 | |
eacd73f7 YZ |
5529 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { |
5530 | olinfo_status |= IXGBE_ADVTXD_CC; | |
5531 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
5532 | if (tx_flags & IXGBE_TX_FLAGS_FSO) | |
5533 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
5534 | } | |
5535 | ||
9a799d71 AK |
5536 | olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT); |
5537 | ||
5538 | i = tx_ring->next_to_use; | |
5539 | while (count--) { | |
5540 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
5541 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); | |
5542 | tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma); | |
5543 | tx_desc->read.cmd_type_len = | |
b4617240 | 5544 | cpu_to_le32(cmd_type_len | tx_buffer_info->length); |
9a799d71 | 5545 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
9a799d71 AK |
5546 | i++; |
5547 | if (i == tx_ring->count) | |
5548 | i = 0; | |
5549 | } | |
5550 | ||
5551 | tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd); | |
5552 | ||
5553 | /* | |
5554 | * Force memory writes to complete before letting h/w | |
5555 | * know there are new descriptors to fetch. (Only | |
5556 | * applicable for weak-ordered memory model archs, | |
5557 | * such as IA-64). | |
5558 | */ | |
5559 | wmb(); | |
5560 | ||
5561 | tx_ring->next_to_use = i; | |
5562 | writel(i, adapter->hw.hw_addr + tx_ring->tail); | |
5563 | } | |
5564 | ||
c4cf55e5 PWJ |
5565 | static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb, |
5566 | int queue, u32 tx_flags) | |
5567 | { | |
5568 | /* Right now, we support IPv4 only */ | |
5569 | struct ixgbe_atr_input atr_input; | |
5570 | struct tcphdr *th; | |
c4cf55e5 PWJ |
5571 | struct iphdr *iph = ip_hdr(skb); |
5572 | struct ethhdr *eth = (struct ethhdr *)skb->data; | |
5573 | u16 vlan_id, src_port, dst_port, flex_bytes; | |
5574 | u32 src_ipv4_addr, dst_ipv4_addr; | |
5575 | u8 l4type = 0; | |
5576 | ||
5577 | /* check if we're UDP or TCP */ | |
5578 | if (iph->protocol == IPPROTO_TCP) { | |
5579 | th = tcp_hdr(skb); | |
5580 | src_port = th->source; | |
5581 | dst_port = th->dest; | |
5582 | l4type |= IXGBE_ATR_L4TYPE_TCP; | |
5583 | /* l4type IPv4 type is 0, no need to assign */ | |
c4cf55e5 PWJ |
5584 | } else { |
5585 | /* Unsupported L4 header, just bail here */ | |
5586 | return; | |
5587 | } | |
5588 | ||
5589 | memset(&atr_input, 0, sizeof(struct ixgbe_atr_input)); | |
5590 | ||
5591 | vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >> | |
5592 | IXGBE_TX_FLAGS_VLAN_SHIFT; | |
5593 | src_ipv4_addr = iph->saddr; | |
5594 | dst_ipv4_addr = iph->daddr; | |
5595 | flex_bytes = eth->h_proto; | |
5596 | ||
5597 | ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id); | |
5598 | ixgbe_atr_set_src_port_82599(&atr_input, dst_port); | |
5599 | ixgbe_atr_set_dst_port_82599(&atr_input, src_port); | |
5600 | ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes); | |
5601 | ixgbe_atr_set_l4type_82599(&atr_input, l4type); | |
5602 | /* src and dst are inverted, think how the receiver sees them */ | |
5603 | ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr); | |
5604 | ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr); | |
5605 | ||
5606 | /* This assumes the Rx queue and Tx queue are bound to the same CPU */ | |
5607 | ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue); | |
5608 | } | |
5609 | ||
e092be60 | 5610 | static int __ixgbe_maybe_stop_tx(struct net_device *netdev, |
b4617240 | 5611 | struct ixgbe_ring *tx_ring, int size) |
e092be60 | 5612 | { |
30eba97a | 5613 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
e092be60 AV |
5614 | /* Herbert's original patch had: |
5615 | * smp_mb__after_netif_stop_queue(); | |
5616 | * but since that doesn't exist yet, just open code it. */ | |
5617 | smp_mb(); | |
5618 | ||
5619 | /* We need to check again in a case another CPU has just | |
5620 | * made room available. */ | |
5621 | if (likely(IXGBE_DESC_UNUSED(tx_ring) < size)) | |
5622 | return -EBUSY; | |
5623 | ||
5624 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
af72166f | 5625 | netif_start_subqueue(netdev, tx_ring->queue_index); |
7ca3bc58 | 5626 | ++tx_ring->restart_queue; |
e092be60 AV |
5627 | return 0; |
5628 | } | |
5629 | ||
5630 | static int ixgbe_maybe_stop_tx(struct net_device *netdev, | |
b4617240 | 5631 | struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
5632 | { |
5633 | if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size)) | |
5634 | return 0; | |
5635 | return __ixgbe_maybe_stop_tx(netdev, tx_ring, size); | |
5636 | } | |
5637 | ||
09a3b1f8 SH |
5638 | static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb) |
5639 | { | |
5640 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
5f715823 | 5641 | int txq = smp_processor_id(); |
09a3b1f8 | 5642 | |
fdd3d631 KK |
5643 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
5644 | while (unlikely(txq >= dev->real_num_tx_queues)) | |
5645 | txq -= dev->real_num_tx_queues; | |
5f715823 | 5646 | return txq; |
fdd3d631 | 5647 | } |
c4cf55e5 | 5648 | |
5f715823 YZ |
5649 | #ifdef IXGBE_FCOE |
5650 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
5651 | (skb->protocol == htons(ETH_P_FCOE))) { | |
5652 | txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1); | |
5653 | txq += adapter->ring_feature[RING_F_FCOE].mask; | |
5654 | return txq; | |
5655 | } | |
5656 | #endif | |
2ea186ae JF |
5657 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
5658 | if (skb->priority == TC_PRIO_CONTROL) | |
5659 | txq = adapter->ring_feature[RING_F_DCB].indices-1; | |
5660 | else | |
5661 | txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) | |
5662 | >> 13; | |
5663 | return txq; | |
5664 | } | |
09a3b1f8 SH |
5665 | |
5666 | return skb_tx_hash(dev, skb); | |
5667 | } | |
5668 | ||
3b29a56d SH |
5669 | static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, |
5670 | struct net_device *netdev) | |
9a799d71 AK |
5671 | { |
5672 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5673 | struct ixgbe_ring *tx_ring; | |
60d51134 | 5674 | struct netdev_queue *txq; |
9a799d71 AK |
5675 | unsigned int first; |
5676 | unsigned int tx_flags = 0; | |
30eba97a | 5677 | u8 hdr_len = 0; |
5f715823 | 5678 | int tso; |
9a799d71 AK |
5679 | int count = 0; |
5680 | unsigned int f; | |
9f8cdf4f | 5681 | |
9f8cdf4f JB |
5682 | if (adapter->vlgrp && vlan_tx_tag_present(skb)) { |
5683 | tx_flags |= vlan_tx_tag_get(skb); | |
2f90b865 AD |
5684 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
5685 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; | |
5f715823 | 5686 | tx_flags |= ((skb->queue_mapping & 0x7) << 13); |
2f90b865 AD |
5687 | } |
5688 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; | |
5689 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
5690 | } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
2ea186ae JF |
5691 | tx_flags |= ((skb->queue_mapping & 0x7) << 13); |
5692 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; | |
5693 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
9a799d71 | 5694 | } |
eacd73f7 | 5695 | |
4a0b9ca0 | 5696 | tx_ring = adapter->tx_ring[skb->queue_mapping]; |
60127865 | 5697 | |
eacd73f7 | 5698 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && |
09ad1cc0 | 5699 | (skb->protocol == htons(ETH_P_FCOE))) { |
eacd73f7 | 5700 | tx_flags |= IXGBE_TX_FLAGS_FCOE; |
09ad1cc0 | 5701 | #ifdef IXGBE_FCOE |
61a0f421 YZ |
5702 | #ifdef CONFIG_IXGBE_DCB |
5703 | tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK | |
5704 | << IXGBE_TX_FLAGS_VLAN_SHIFT); | |
5705 | tx_flags |= ((adapter->fcoe.up << 13) | |
5706 | << IXGBE_TX_FLAGS_VLAN_SHIFT); | |
5707 | #endif | |
09ad1cc0 YZ |
5708 | #endif |
5709 | } | |
eacd73f7 | 5710 | /* four things can cause us to need a context descriptor */ |
9f8cdf4f JB |
5711 | if (skb_is_gso(skb) || |
5712 | (skb->ip_summed == CHECKSUM_PARTIAL) || | |
eacd73f7 YZ |
5713 | (tx_flags & IXGBE_TX_FLAGS_VLAN) || |
5714 | (tx_flags & IXGBE_TX_FLAGS_FCOE)) | |
9a799d71 AK |
5715 | count++; |
5716 | ||
9f8cdf4f JB |
5717 | count += TXD_USE_COUNT(skb_headlen(skb)); |
5718 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
9a799d71 AK |
5719 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); |
5720 | ||
e092be60 | 5721 | if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) { |
9a799d71 | 5722 | adapter->tx_busy++; |
9a799d71 AK |
5723 | return NETDEV_TX_BUSY; |
5724 | } | |
9a799d71 | 5725 | |
9a799d71 | 5726 | first = tx_ring->next_to_use; |
eacd73f7 YZ |
5727 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { |
5728 | #ifdef IXGBE_FCOE | |
5729 | /* setup tx offload for FCoE */ | |
5730 | tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
5731 | if (tso < 0) { | |
5732 | dev_kfree_skb_any(skb); | |
5733 | return NETDEV_TX_OK; | |
5734 | } | |
5735 | if (tso) | |
5736 | tx_flags |= IXGBE_TX_FLAGS_FSO; | |
5737 | #endif /* IXGBE_FCOE */ | |
5738 | } else { | |
5739 | if (skb->protocol == htons(ETH_P_IP)) | |
5740 | tx_flags |= IXGBE_TX_FLAGS_IPV4; | |
5741 | tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
5742 | if (tso < 0) { | |
5743 | dev_kfree_skb_any(skb); | |
5744 | return NETDEV_TX_OK; | |
5745 | } | |
9a799d71 | 5746 | |
eacd73f7 YZ |
5747 | if (tso) |
5748 | tx_flags |= IXGBE_TX_FLAGS_TSO; | |
5749 | else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) && | |
5750 | (skb->ip_summed == CHECKSUM_PARTIAL)) | |
5751 | tx_flags |= IXGBE_TX_FLAGS_CSUM; | |
5752 | } | |
9a799d71 | 5753 | |
eacd73f7 | 5754 | count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first); |
44df32c5 | 5755 | if (count) { |
c4cf55e5 PWJ |
5756 | /* add the ATR filter if ATR is on */ |
5757 | if (tx_ring->atr_sample_rate) { | |
5758 | ++tx_ring->atr_count; | |
5759 | if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) && | |
5760 | test_bit(__IXGBE_FDIR_INIT_DONE, | |
5761 | &tx_ring->reinit_state)) { | |
5762 | ixgbe_atr(adapter, skb, tx_ring->queue_index, | |
5763 | tx_flags); | |
5764 | tx_ring->atr_count = 0; | |
5765 | } | |
5766 | } | |
60d51134 ED |
5767 | txq = netdev_get_tx_queue(netdev, tx_ring->queue_index); |
5768 | txq->tx_bytes += skb->len; | |
5769 | txq->tx_packets++; | |
44df32c5 AD |
5770 | ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len, |
5771 | hdr_len); | |
44df32c5 | 5772 | ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED); |
9a799d71 | 5773 | |
44df32c5 AD |
5774 | } else { |
5775 | dev_kfree_skb_any(skb); | |
5776 | tx_ring->tx_buffer_info[first].time_stamp = 0; | |
5777 | tx_ring->next_to_use = first; | |
5778 | } | |
9a799d71 AK |
5779 | |
5780 | return NETDEV_TX_OK; | |
5781 | } | |
5782 | ||
9a799d71 AK |
5783 | /** |
5784 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
5785 | * @netdev: network interface device structure | |
5786 | * @p: pointer to an address structure | |
5787 | * | |
5788 | * Returns 0 on success, negative on failure | |
5789 | **/ | |
5790 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
5791 | { | |
5792 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 5793 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
5794 | struct sockaddr *addr = p; |
5795 | ||
5796 | if (!is_valid_ether_addr(addr->sa_data)) | |
5797 | return -EADDRNOTAVAIL; | |
5798 | ||
5799 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 5800 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 5801 | |
1cdd1ec8 GR |
5802 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
5803 | IXGBE_RAH_AV); | |
9a799d71 AK |
5804 | |
5805 | return 0; | |
5806 | } | |
5807 | ||
6b73e10d BH |
5808 | static int |
5809 | ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) | |
5810 | { | |
5811 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5812 | struct ixgbe_hw *hw = &adapter->hw; | |
5813 | u16 value; | |
5814 | int rc; | |
5815 | ||
5816 | if (prtad != hw->phy.mdio.prtad) | |
5817 | return -EINVAL; | |
5818 | rc = hw->phy.ops.read_reg(hw, addr, devad, &value); | |
5819 | if (!rc) | |
5820 | rc = value; | |
5821 | return rc; | |
5822 | } | |
5823 | ||
5824 | static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, | |
5825 | u16 addr, u16 value) | |
5826 | { | |
5827 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5828 | struct ixgbe_hw *hw = &adapter->hw; | |
5829 | ||
5830 | if (prtad != hw->phy.mdio.prtad) | |
5831 | return -EINVAL; | |
5832 | return hw->phy.ops.write_reg(hw, addr, devad, value); | |
5833 | } | |
5834 | ||
5835 | static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | |
5836 | { | |
5837 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5838 | ||
5839 | return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); | |
5840 | } | |
5841 | ||
0365e6e4 PW |
5842 | /** |
5843 | * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding | |
31278e71 | 5844 | * netdev->dev_addrs |
0365e6e4 PW |
5845 | * @netdev: network interface device structure |
5846 | * | |
5847 | * Returns non-zero on failure | |
5848 | **/ | |
5849 | static int ixgbe_add_sanmac_netdev(struct net_device *dev) | |
5850 | { | |
5851 | int err = 0; | |
5852 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
5853 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
5854 | ||
5855 | if (is_valid_ether_addr(mac->san_addr)) { | |
5856 | rtnl_lock(); | |
5857 | err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
5858 | rtnl_unlock(); | |
5859 | } | |
5860 | return err; | |
5861 | } | |
5862 | ||
5863 | /** | |
5864 | * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding | |
31278e71 | 5865 | * netdev->dev_addrs |
0365e6e4 PW |
5866 | * @netdev: network interface device structure |
5867 | * | |
5868 | * Returns non-zero on failure | |
5869 | **/ | |
5870 | static int ixgbe_del_sanmac_netdev(struct net_device *dev) | |
5871 | { | |
5872 | int err = 0; | |
5873 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
5874 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
5875 | ||
5876 | if (is_valid_ether_addr(mac->san_addr)) { | |
5877 | rtnl_lock(); | |
5878 | err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
5879 | rtnl_unlock(); | |
5880 | } | |
5881 | return err; | |
5882 | } | |
5883 | ||
9a799d71 AK |
5884 | #ifdef CONFIG_NET_POLL_CONTROLLER |
5885 | /* | |
5886 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
5887 | * without having to re-enable interrupts. It's not called while | |
5888 | * the interrupt routine is executing. | |
5889 | */ | |
5890 | static void ixgbe_netpoll(struct net_device *netdev) | |
5891 | { | |
5892 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8f9a7167 | 5893 | int i; |
9a799d71 | 5894 | |
1a647bd2 AD |
5895 | /* if interface is down do nothing */ |
5896 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
5897 | return; | |
5898 | ||
9a799d71 | 5899 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; |
8f9a7167 PWJ |
5900 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
5901 | int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
5902 | for (i = 0; i < num_q_vectors; i++) { | |
5903 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; | |
5904 | ixgbe_msix_clean_many(0, q_vector); | |
5905 | } | |
5906 | } else { | |
5907 | ixgbe_intr(adapter->pdev->irq, netdev); | |
5908 | } | |
9a799d71 | 5909 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; |
9a799d71 AK |
5910 | } |
5911 | #endif | |
5912 | ||
0edc3527 SH |
5913 | static const struct net_device_ops ixgbe_netdev_ops = { |
5914 | .ndo_open = ixgbe_open, | |
5915 | .ndo_stop = ixgbe_close, | |
00829823 | 5916 | .ndo_start_xmit = ixgbe_xmit_frame, |
09a3b1f8 | 5917 | .ndo_select_queue = ixgbe_select_queue, |
e90d400c | 5918 | .ndo_set_rx_mode = ixgbe_set_rx_mode, |
0edc3527 SH |
5919 | .ndo_set_multicast_list = ixgbe_set_rx_mode, |
5920 | .ndo_validate_addr = eth_validate_addr, | |
5921 | .ndo_set_mac_address = ixgbe_set_mac, | |
5922 | .ndo_change_mtu = ixgbe_change_mtu, | |
5923 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
5924 | .ndo_vlan_rx_register = ixgbe_vlan_rx_register, | |
5925 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, | |
5926 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
6b73e10d | 5927 | .ndo_do_ioctl = ixgbe_ioctl, |
0edc3527 SH |
5928 | #ifdef CONFIG_NET_POLL_CONTROLLER |
5929 | .ndo_poll_controller = ixgbe_netpoll, | |
5930 | #endif | |
332d4a7d YZ |
5931 | #ifdef IXGBE_FCOE |
5932 | .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, | |
5933 | .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, | |
8450ff8c YZ |
5934 | .ndo_fcoe_enable = ixgbe_fcoe_enable, |
5935 | .ndo_fcoe_disable = ixgbe_fcoe_disable, | |
61a1fa10 | 5936 | .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, |
332d4a7d | 5937 | #endif /* IXGBE_FCOE */ |
0edc3527 SH |
5938 | }; |
5939 | ||
1cdd1ec8 GR |
5940 | static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter, |
5941 | const struct ixgbe_info *ii) | |
5942 | { | |
5943 | #ifdef CONFIG_PCI_IOV | |
5944 | struct ixgbe_hw *hw = &adapter->hw; | |
5945 | int err; | |
5946 | ||
5947 | if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs) | |
5948 | return; | |
5949 | ||
5950 | /* The 82599 supports up to 64 VFs per physical function | |
5951 | * but this implementation limits allocation to 63 so that | |
5952 | * basic networking resources are still available to the | |
5953 | * physical function | |
5954 | */ | |
5955 | adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs; | |
5956 | adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED; | |
5957 | err = pci_enable_sriov(adapter->pdev, adapter->num_vfs); | |
5958 | if (err) { | |
5959 | DPRINTK(PROBE, ERR, | |
5960 | "Failed to enable PCI sriov: %d\n", err); | |
5961 | goto err_novfs; | |
5962 | } | |
5963 | /* If call to enable VFs succeeded then allocate memory | |
5964 | * for per VF control structures. | |
5965 | */ | |
5966 | adapter->vfinfo = | |
5967 | kcalloc(adapter->num_vfs, | |
5968 | sizeof(struct vf_data_storage), GFP_KERNEL); | |
5969 | if (adapter->vfinfo) { | |
5970 | /* Now that we're sure SR-IOV is enabled | |
5971 | * and memory allocated set up the mailbox parameters | |
5972 | */ | |
5973 | ixgbe_init_mbx_params_pf(hw); | |
5974 | memcpy(&hw->mbx.ops, ii->mbx_ops, | |
5975 | sizeof(hw->mbx.ops)); | |
5976 | ||
5977 | /* Disable RSC when in SR-IOV mode */ | |
5978 | adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE | | |
5979 | IXGBE_FLAG2_RSC_ENABLED); | |
5980 | return; | |
5981 | } | |
5982 | ||
5983 | /* Oh oh */ | |
5984 | DPRINTK(PROBE, ERR, | |
5985 | "Unable to allocate memory for VF " | |
5986 | "Data Storage - SRIOV disabled\n"); | |
5987 | pci_disable_sriov(adapter->pdev); | |
5988 | ||
5989 | err_novfs: | |
5990 | adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED; | |
5991 | adapter->num_vfs = 0; | |
5992 | #endif /* CONFIG_PCI_IOV */ | |
5993 | } | |
5994 | ||
9a799d71 AK |
5995 | /** |
5996 | * ixgbe_probe - Device Initialization Routine | |
5997 | * @pdev: PCI device information struct | |
5998 | * @ent: entry in ixgbe_pci_tbl | |
5999 | * | |
6000 | * Returns 0 on success, negative on failure | |
6001 | * | |
6002 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
6003 | * The OS initialization, configuring of the adapter private structure, | |
6004 | * and a hardware reset occur. | |
6005 | **/ | |
6006 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
b4617240 | 6007 | const struct pci_device_id *ent) |
9a799d71 AK |
6008 | { |
6009 | struct net_device *netdev; | |
6010 | struct ixgbe_adapter *adapter = NULL; | |
6011 | struct ixgbe_hw *hw; | |
6012 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
6013 | static int cards_found; |
6014 | int i, err, pci_using_dac; | |
c85a2618 | 6015 | unsigned int indices = num_possible_cpus(); |
eacd73f7 YZ |
6016 | #ifdef IXGBE_FCOE |
6017 | u16 device_caps; | |
6018 | #endif | |
c44ade9e | 6019 | u32 part_num, eec; |
9a799d71 | 6020 | |
9ce77666 | 6021 | err = pci_enable_device_mem(pdev); |
9a799d71 AK |
6022 | if (err) |
6023 | return err; | |
6024 | ||
6a35528a YH |
6025 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && |
6026 | !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { | |
9a799d71 AK |
6027 | pci_using_dac = 1; |
6028 | } else { | |
284901a9 | 6029 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
9a799d71 | 6030 | if (err) { |
284901a9 | 6031 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
9a799d71 | 6032 | if (err) { |
b4617240 PW |
6033 | dev_err(&pdev->dev, "No usable DMA " |
6034 | "configuration, aborting\n"); | |
9a799d71 AK |
6035 | goto err_dma; |
6036 | } | |
6037 | } | |
6038 | pci_using_dac = 0; | |
6039 | } | |
6040 | ||
9ce77666 | 6041 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
6042 | IORESOURCE_MEM), ixgbe_driver_name); | |
9a799d71 | 6043 | if (err) { |
9ce77666 | 6044 | dev_err(&pdev->dev, |
6045 | "pci_request_selected_regions failed 0x%x\n", err); | |
9a799d71 AK |
6046 | goto err_pci_reg; |
6047 | } | |
6048 | ||
19d5afd4 | 6049 | pci_enable_pcie_error_reporting(pdev); |
6fabd715 | 6050 | |
9a799d71 | 6051 | pci_set_master(pdev); |
fb3b27bc | 6052 | pci_save_state(pdev); |
9a799d71 | 6053 | |
c85a2618 JF |
6054 | if (ii->mac == ixgbe_mac_82598EB) |
6055 | indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES); | |
6056 | else | |
6057 | indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES); | |
6058 | ||
6059 | indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES); | |
6060 | #ifdef IXGBE_FCOE | |
6061 | indices += min_t(unsigned int, num_possible_cpus(), | |
6062 | IXGBE_MAX_FCOE_INDICES); | |
6063 | #endif | |
c85a2618 | 6064 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); |
9a799d71 AK |
6065 | if (!netdev) { |
6066 | err = -ENOMEM; | |
6067 | goto err_alloc_etherdev; | |
6068 | } | |
6069 | ||
9a799d71 AK |
6070 | SET_NETDEV_DEV(netdev, &pdev->dev); |
6071 | ||
6072 | pci_set_drvdata(pdev, netdev); | |
6073 | adapter = netdev_priv(netdev); | |
6074 | ||
6075 | adapter->netdev = netdev; | |
6076 | adapter->pdev = pdev; | |
6077 | hw = &adapter->hw; | |
6078 | hw->back = adapter; | |
6079 | adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1; | |
6080 | ||
05857980 JK |
6081 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
6082 | pci_resource_len(pdev, 0)); | |
9a799d71 AK |
6083 | if (!hw->hw_addr) { |
6084 | err = -EIO; | |
6085 | goto err_ioremap; | |
6086 | } | |
6087 | ||
6088 | for (i = 1; i <= 5; i++) { | |
6089 | if (pci_resource_len(pdev, i) == 0) | |
6090 | continue; | |
6091 | } | |
6092 | ||
0edc3527 | 6093 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 6094 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 6095 | netdev->watchdog_timeo = 5 * HZ; |
9a799d71 AK |
6096 | strcpy(netdev->name, pci_name(pdev)); |
6097 | ||
9a799d71 AK |
6098 | adapter->bd_number = cards_found; |
6099 | ||
9a799d71 AK |
6100 | /* Setup hw api */ |
6101 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 6102 | hw->mac.type = ii->mac; |
9a799d71 | 6103 | |
c44ade9e JB |
6104 | /* EEPROM */ |
6105 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
6106 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
6107 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
6108 | if (!(eec & (1 << 8))) | |
6109 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
6110 | ||
6111 | /* PHY */ | |
6112 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 | 6113 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
6b73e10d BH |
6114 | /* ixgbe_identify_phy_generic will set prtad and mmds properly */ |
6115 | hw->phy.mdio.prtad = MDIO_PRTAD_NONE; | |
6116 | hw->phy.mdio.mmds = 0; | |
6117 | hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
6118 | hw->phy.mdio.dev = netdev; | |
6119 | hw->phy.mdio.mdio_read = ixgbe_mdio_read; | |
6120 | hw->phy.mdio.mdio_write = ixgbe_mdio_write; | |
c4900be0 DS |
6121 | |
6122 | /* set up this timer and work struct before calling get_invariants | |
6123 | * which might start the timer | |
6124 | */ | |
6125 | init_timer(&adapter->sfp_timer); | |
6126 | adapter->sfp_timer.function = &ixgbe_sfp_timer; | |
6127 | adapter->sfp_timer.data = (unsigned long) adapter; | |
6128 | ||
6129 | INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task); | |
c44ade9e | 6130 | |
e8e26350 PW |
6131 | /* multispeed fiber has its own tasklet, called from GPI SDP1 context */ |
6132 | INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task); | |
6133 | ||
6134 | /* a new SFP+ module arrival, called from GPI SDP2 context */ | |
6135 | INIT_WORK(&adapter->sfp_config_module_task, | |
6136 | ixgbe_sfp_config_module_task); | |
6137 | ||
8ca783ab | 6138 | ii->get_invariants(hw); |
9a799d71 AK |
6139 | |
6140 | /* setup the private structure */ | |
6141 | err = ixgbe_sw_init(adapter); | |
6142 | if (err) | |
6143 | goto err_sw_init; | |
6144 | ||
e86bff0e DS |
6145 | /* Make it possible the adapter to be woken up via WOL */ |
6146 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) | |
6147 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); | |
6148 | ||
bf069c97 DS |
6149 | /* |
6150 | * If there is a fan on this device and it has failed log the | |
6151 | * failure. | |
6152 | */ | |
6153 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
6154 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
6155 | if (esdp & IXGBE_ESDP_SDP1) | |
6156 | DPRINTK(PROBE, CRIT, | |
6157 | "Fan has stopped, replace the adapter\n"); | |
6158 | } | |
6159 | ||
c44ade9e JB |
6160 | /* reset_hw fills in the perm_addr as well */ |
6161 | err = hw->mac.ops.reset_hw(hw); | |
8ca783ab DS |
6162 | if (err == IXGBE_ERR_SFP_NOT_PRESENT && |
6163 | hw->mac.type == ixgbe_mac_82598EB) { | |
6164 | /* | |
6165 | * Start a kernel thread to watch for a module to arrive. | |
6166 | * Only do this for 82598, since 82599 will generate | |
6167 | * interrupts on module arrival. | |
6168 | */ | |
6169 | set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
6170 | mod_timer(&adapter->sfp_timer, | |
6171 | round_jiffies(jiffies + (2 * HZ))); | |
6172 | err = 0; | |
6173 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
88d2b81f DS |
6174 | dev_err(&adapter->pdev->dev, "failed to initialize because " |
6175 | "an unsupported SFP+ module type was detected.\n" | |
6176 | "Reload the driver after installing a supported " | |
6177 | "module.\n"); | |
04f165ef PW |
6178 | goto err_sw_init; |
6179 | } else if (err) { | |
c44ade9e JB |
6180 | dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err); |
6181 | goto err_sw_init; | |
6182 | } | |
6183 | ||
1cdd1ec8 GR |
6184 | ixgbe_probe_vf(adapter, ii); |
6185 | ||
9a799d71 | 6186 | netdev->features = NETIF_F_SG | |
b4617240 PW |
6187 | NETIF_F_IP_CSUM | |
6188 | NETIF_F_HW_VLAN_TX | | |
6189 | NETIF_F_HW_VLAN_RX | | |
6190 | NETIF_F_HW_VLAN_FILTER; | |
9a799d71 | 6191 | |
e9990a9c | 6192 | netdev->features |= NETIF_F_IPV6_CSUM; |
9a799d71 | 6193 | netdev->features |= NETIF_F_TSO; |
9a799d71 | 6194 | netdev->features |= NETIF_F_TSO6; |
78b6f4ce | 6195 | netdev->features |= NETIF_F_GRO; |
ad31c402 | 6196 | |
45a5ead0 JB |
6197 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) |
6198 | netdev->features |= NETIF_F_SCTP_CSUM; | |
6199 | ||
ad31c402 JK |
6200 | netdev->vlan_features |= NETIF_F_TSO; |
6201 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 6202 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
cd1da503 | 6203 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; |
ad31c402 JK |
6204 | netdev->vlan_features |= NETIF_F_SG; |
6205 | ||
1cdd1ec8 GR |
6206 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
6207 | adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED | | |
6208 | IXGBE_FLAG_DCB_ENABLED); | |
2f90b865 AD |
6209 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) |
6210 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
6211 | ||
7a6b6f51 | 6212 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
6213 | netdev->dcbnl_ops = &dcbnl_ops; |
6214 | #endif | |
6215 | ||
eacd73f7 | 6216 | #ifdef IXGBE_FCOE |
0d551589 | 6217 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
eacd73f7 YZ |
6218 | if (hw->mac.ops.get_device_caps) { |
6219 | hw->mac.ops.get_device_caps(hw, &device_caps); | |
0d551589 YZ |
6220 | if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) |
6221 | adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; | |
eacd73f7 YZ |
6222 | } |
6223 | } | |
6224 | #endif /* IXGBE_FCOE */ | |
9a799d71 AK |
6225 | if (pci_using_dac) |
6226 | netdev->features |= NETIF_F_HIGHDMA; | |
6227 | ||
0c19d6af | 6228 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
f8212f97 AD |
6229 | netdev->features |= NETIF_F_LRO; |
6230 | ||
9a799d71 | 6231 | /* make sure the EEPROM is good */ |
c44ade9e | 6232 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
9a799d71 AK |
6233 | dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n"); |
6234 | err = -EIO; | |
6235 | goto err_eeprom; | |
6236 | } | |
6237 | ||
6238 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
6239 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
6240 | ||
c44ade9e JB |
6241 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
6242 | dev_err(&pdev->dev, "invalid MAC address\n"); | |
9a799d71 AK |
6243 | err = -EIO; |
6244 | goto err_eeprom; | |
6245 | } | |
6246 | ||
6247 | init_timer(&adapter->watchdog_timer); | |
6248 | adapter->watchdog_timer.function = &ixgbe_watchdog; | |
6249 | adapter->watchdog_timer.data = (unsigned long)adapter; | |
6250 | ||
6251 | INIT_WORK(&adapter->reset_task, ixgbe_reset_task); | |
cf8280ee | 6252 | INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task); |
9a799d71 | 6253 | |
021230d4 AV |
6254 | err = ixgbe_init_interrupt_scheme(adapter); |
6255 | if (err) | |
6256 | goto err_sw_init; | |
9a799d71 | 6257 | |
e8e26350 PW |
6258 | switch (pdev->device) { |
6259 | case IXGBE_DEV_ID_82599_KX4: | |
495dce12 WJP |
6260 | adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX | |
6261 | IXGBE_WUFC_MC | IXGBE_WUFC_BC); | |
e8e26350 PW |
6262 | break; |
6263 | default: | |
6264 | adapter->wol = 0; | |
6265 | break; | |
6266 | } | |
e8e26350 PW |
6267 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
6268 | ||
04f165ef PW |
6269 | /* pick up the PCI bus settings for reporting later */ |
6270 | hw->mac.ops.get_bus_info(hw); | |
6271 | ||
9a799d71 | 6272 | /* print bus type/speed/width info */ |
7c510e4b | 6273 | dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n", |
e8e26350 PW |
6274 | ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s": |
6275 | (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"), | |
6276 | ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" : | |
6277 | (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" : | |
6278 | (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" : | |
b4617240 | 6279 | "Unknown"), |
7c510e4b | 6280 | netdev->dev_addr); |
c44ade9e | 6281 | ixgbe_read_pba_num_generic(hw, &part_num); |
e8e26350 PW |
6282 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
6283 | dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n", | |
6284 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, | |
6285 | (part_num >> 8), (part_num & 0xff)); | |
6286 | else | |
6287 | dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n", | |
6288 | hw->mac.type, hw->phy.type, | |
6289 | (part_num >> 8), (part_num & 0xff)); | |
9a799d71 | 6290 | |
e8e26350 | 6291 | if (hw->bus.width <= ixgbe_bus_width_pcie_x4) { |
0c254d86 | 6292 | dev_warn(&pdev->dev, "PCI-Express bandwidth available for " |
b4617240 PW |
6293 | "this card is not sufficient for optimal " |
6294 | "performance.\n"); | |
0c254d86 | 6295 | dev_warn(&pdev->dev, "For optimal performance a x8 " |
b4617240 | 6296 | "PCI-Express slot is required.\n"); |
0c254d86 AK |
6297 | } |
6298 | ||
34b0368c PWJ |
6299 | /* save off EEPROM version number */ |
6300 | hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version); | |
6301 | ||
9a799d71 | 6302 | /* reset the hardware with the new settings */ |
794caeb2 | 6303 | err = hw->mac.ops.start_hw(hw); |
c44ade9e | 6304 | |
794caeb2 PWJ |
6305 | if (err == IXGBE_ERR_EEPROM_VERSION) { |
6306 | /* We are running on a pre-production device, log a warning */ | |
6307 | dev_warn(&pdev->dev, "This device is a pre-production " | |
6308 | "adapter/LOM. Please be aware there may be issues " | |
6309 | "associated with your hardware. If you are " | |
6310 | "experiencing problems please contact your Intel or " | |
6311 | "hardware representative who provided you with this " | |
6312 | "hardware.\n"); | |
6313 | } | |
9a799d71 AK |
6314 | strcpy(netdev->name, "eth%d"); |
6315 | err = register_netdev(netdev); | |
6316 | if (err) | |
6317 | goto err_register; | |
6318 | ||
54386467 JB |
6319 | /* carrier off reporting is important to ethtool even BEFORE open */ |
6320 | netif_carrier_off(netdev); | |
6321 | ||
c4cf55e5 PWJ |
6322 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
6323 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
6324 | INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task); | |
6325 | ||
5dd2d332 | 6326 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 6327 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd | 6328 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
6329 | ixgbe_setup_dca(adapter); |
6330 | } | |
6331 | #endif | |
1cdd1ec8 GR |
6332 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
6333 | DPRINTK(PROBE, INFO, "IOV is enabled with %d VFs\n", | |
6334 | adapter->num_vfs); | |
6335 | for (i = 0; i < adapter->num_vfs; i++) | |
6336 | ixgbe_vf_configuration(pdev, (i | 0x10000000)); | |
6337 | } | |
6338 | ||
0365e6e4 PW |
6339 | /* add san mac addr to netdev */ |
6340 | ixgbe_add_sanmac_netdev(netdev); | |
9a799d71 AK |
6341 | |
6342 | dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n"); | |
6343 | cards_found++; | |
6344 | return 0; | |
6345 | ||
6346 | err_register: | |
5eba3699 | 6347 | ixgbe_release_hw_control(adapter); |
7a921c93 | 6348 | ixgbe_clear_interrupt_scheme(adapter); |
9a799d71 AK |
6349 | err_sw_init: |
6350 | err_eeprom: | |
1cdd1ec8 GR |
6351 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
6352 | ixgbe_disable_sriov(adapter); | |
c4900be0 DS |
6353 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); |
6354 | del_timer_sync(&adapter->sfp_timer); | |
6355 | cancel_work_sync(&adapter->sfp_task); | |
e8e26350 PW |
6356 | cancel_work_sync(&adapter->multispeed_fiber_task); |
6357 | cancel_work_sync(&adapter->sfp_config_module_task); | |
9a799d71 AK |
6358 | iounmap(hw->hw_addr); |
6359 | err_ioremap: | |
6360 | free_netdev(netdev); | |
6361 | err_alloc_etherdev: | |
9ce77666 | 6362 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
6363 | IORESOURCE_MEM)); | |
9a799d71 AK |
6364 | err_pci_reg: |
6365 | err_dma: | |
6366 | pci_disable_device(pdev); | |
6367 | return err; | |
6368 | } | |
6369 | ||
6370 | /** | |
6371 | * ixgbe_remove - Device Removal Routine | |
6372 | * @pdev: PCI device information struct | |
6373 | * | |
6374 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
6375 | * that it should release a PCI device. The could be caused by a | |
6376 | * Hot-Plug event, or because the driver is going to be removed from | |
6377 | * memory. | |
6378 | **/ | |
6379 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
6380 | { | |
6381 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6382 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6383 | ||
6384 | set_bit(__IXGBE_DOWN, &adapter->state); | |
c4900be0 DS |
6385 | /* clear the module not found bit to make sure the worker won't |
6386 | * reschedule | |
6387 | */ | |
6388 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
9a799d71 AK |
6389 | del_timer_sync(&adapter->watchdog_timer); |
6390 | ||
c4900be0 DS |
6391 | del_timer_sync(&adapter->sfp_timer); |
6392 | cancel_work_sync(&adapter->watchdog_task); | |
6393 | cancel_work_sync(&adapter->sfp_task); | |
1097cd17 MC |
6394 | if (adapter->hw.phy.multispeed_fiber) { |
6395 | struct ixgbe_hw *hw = &adapter->hw; | |
6396 | /* | |
6397 | * Restart clause 37 autoneg, disable and re-enable | |
6398 | * the tx laser, to clear & alert the link partner | |
6399 | * that it needs to restart autotry | |
6400 | */ | |
6401 | hw->mac.autotry_restart = true; | |
6402 | hw->mac.ops.flap_tx_laser(hw); | |
6403 | } | |
e8e26350 PW |
6404 | cancel_work_sync(&adapter->multispeed_fiber_task); |
6405 | cancel_work_sync(&adapter->sfp_config_module_task); | |
c4cf55e5 PWJ |
6406 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
6407 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
6408 | cancel_work_sync(&adapter->fdir_reinit_task); | |
9a799d71 AK |
6409 | flush_scheduled_work(); |
6410 | ||
5dd2d332 | 6411 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
6412 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
6413 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
6414 | dca_remove_requester(&pdev->dev); | |
6415 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
6416 | } | |
6417 | ||
6418 | #endif | |
332d4a7d YZ |
6419 | #ifdef IXGBE_FCOE |
6420 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
6421 | ixgbe_cleanup_fcoe(adapter); | |
6422 | ||
6423 | #endif /* IXGBE_FCOE */ | |
0365e6e4 PW |
6424 | |
6425 | /* remove the added san mac */ | |
6426 | ixgbe_del_sanmac_netdev(netdev); | |
6427 | ||
c4900be0 DS |
6428 | if (netdev->reg_state == NETREG_REGISTERED) |
6429 | unregister_netdev(netdev); | |
9a799d71 | 6430 | |
1cdd1ec8 GR |
6431 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
6432 | ixgbe_disable_sriov(adapter); | |
6433 | ||
7a921c93 | 6434 | ixgbe_clear_interrupt_scheme(adapter); |
5eba3699 | 6435 | |
021230d4 | 6436 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
6437 | |
6438 | iounmap(adapter->hw.hw_addr); | |
9ce77666 | 6439 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
6440 | IORESOURCE_MEM)); | |
9a799d71 | 6441 | |
021230d4 | 6442 | DPRINTK(PROBE, INFO, "complete\n"); |
021230d4 | 6443 | |
9a799d71 AK |
6444 | free_netdev(netdev); |
6445 | ||
19d5afd4 | 6446 | pci_disable_pcie_error_reporting(pdev); |
6fabd715 | 6447 | |
9a799d71 AK |
6448 | pci_disable_device(pdev); |
6449 | } | |
6450 | ||
6451 | /** | |
6452 | * ixgbe_io_error_detected - called when PCI error is detected | |
6453 | * @pdev: Pointer to PCI device | |
6454 | * @state: The current pci connection state | |
6455 | * | |
6456 | * This function is called after a PCI bus error affecting | |
6457 | * this device has been detected. | |
6458 | */ | |
6459 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
b4617240 | 6460 | pci_channel_state_t state) |
9a799d71 AK |
6461 | { |
6462 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 6463 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
6464 | |
6465 | netif_device_detach(netdev); | |
6466 | ||
3044b8d1 BL |
6467 | if (state == pci_channel_io_perm_failure) |
6468 | return PCI_ERS_RESULT_DISCONNECT; | |
6469 | ||
9a799d71 AK |
6470 | if (netif_running(netdev)) |
6471 | ixgbe_down(adapter); | |
6472 | pci_disable_device(pdev); | |
6473 | ||
b4617240 | 6474 | /* Request a slot reset. */ |
9a799d71 AK |
6475 | return PCI_ERS_RESULT_NEED_RESET; |
6476 | } | |
6477 | ||
6478 | /** | |
6479 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
6480 | * @pdev: Pointer to PCI device | |
6481 | * | |
6482 | * Restart the card from scratch, as if from a cold-boot. | |
6483 | */ | |
6484 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
6485 | { | |
6486 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 6487 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
6fabd715 PWJ |
6488 | pci_ers_result_t result; |
6489 | int err; | |
9a799d71 | 6490 | |
9ce77666 | 6491 | if (pci_enable_device_mem(pdev)) { |
9a799d71 | 6492 | DPRINTK(PROBE, ERR, |
b4617240 | 6493 | "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
6494 | result = PCI_ERS_RESULT_DISCONNECT; |
6495 | } else { | |
6496 | pci_set_master(pdev); | |
6497 | pci_restore_state(pdev); | |
c0e1f68b | 6498 | pci_save_state(pdev); |
9a799d71 | 6499 | |
dd4d8ca6 | 6500 | pci_wake_from_d3(pdev, false); |
9a799d71 | 6501 | |
6fabd715 | 6502 | ixgbe_reset(adapter); |
88512539 | 6503 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6fabd715 PWJ |
6504 | result = PCI_ERS_RESULT_RECOVERED; |
6505 | } | |
6506 | ||
6507 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
6508 | if (err) { | |
6509 | dev_err(&pdev->dev, | |
6510 | "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err); | |
6511 | /* non-fatal, continue */ | |
6512 | } | |
9a799d71 | 6513 | |
6fabd715 | 6514 | return result; |
9a799d71 AK |
6515 | } |
6516 | ||
6517 | /** | |
6518 | * ixgbe_io_resume - called when traffic can start flowing again. | |
6519 | * @pdev: Pointer to PCI device | |
6520 | * | |
6521 | * This callback is called when the error recovery driver tells us that | |
6522 | * its OK to resume normal operation. | |
6523 | */ | |
6524 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
6525 | { | |
6526 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 6527 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
6528 | |
6529 | if (netif_running(netdev)) { | |
6530 | if (ixgbe_up(adapter)) { | |
6531 | DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n"); | |
6532 | return; | |
6533 | } | |
6534 | } | |
6535 | ||
6536 | netif_device_attach(netdev); | |
9a799d71 AK |
6537 | } |
6538 | ||
6539 | static struct pci_error_handlers ixgbe_err_handler = { | |
6540 | .error_detected = ixgbe_io_error_detected, | |
6541 | .slot_reset = ixgbe_io_slot_reset, | |
6542 | .resume = ixgbe_io_resume, | |
6543 | }; | |
6544 | ||
6545 | static struct pci_driver ixgbe_driver = { | |
6546 | .name = ixgbe_driver_name, | |
6547 | .id_table = ixgbe_pci_tbl, | |
6548 | .probe = ixgbe_probe, | |
6549 | .remove = __devexit_p(ixgbe_remove), | |
6550 | #ifdef CONFIG_PM | |
6551 | .suspend = ixgbe_suspend, | |
6552 | .resume = ixgbe_resume, | |
6553 | #endif | |
6554 | .shutdown = ixgbe_shutdown, | |
6555 | .err_handler = &ixgbe_err_handler | |
6556 | }; | |
6557 | ||
6558 | /** | |
6559 | * ixgbe_init_module - Driver Registration Routine | |
6560 | * | |
6561 | * ixgbe_init_module is the first routine called when the driver is | |
6562 | * loaded. All it does is register with the PCI subsystem. | |
6563 | **/ | |
6564 | static int __init ixgbe_init_module(void) | |
6565 | { | |
6566 | int ret; | |
6567 | printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name, | |
6568 | ixgbe_driver_string, ixgbe_driver_version); | |
6569 | ||
6570 | printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright); | |
6571 | ||
5dd2d332 | 6572 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 6573 | dca_register_notify(&dca_notifier); |
bd0362dd | 6574 | #endif |
5dd2d332 | 6575 | |
9a799d71 AK |
6576 | ret = pci_register_driver(&ixgbe_driver); |
6577 | return ret; | |
6578 | } | |
b4617240 | 6579 | |
9a799d71 AK |
6580 | module_init(ixgbe_init_module); |
6581 | ||
6582 | /** | |
6583 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
6584 | * | |
6585 | * ixgbe_exit_module is called just before the driver is removed | |
6586 | * from memory. | |
6587 | **/ | |
6588 | static void __exit ixgbe_exit_module(void) | |
6589 | { | |
5dd2d332 | 6590 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
6591 | dca_unregister_notify(&dca_notifier); |
6592 | #endif | |
9a799d71 AK |
6593 | pci_unregister_driver(&ixgbe_driver); |
6594 | } | |
bd0362dd | 6595 | |
5dd2d332 | 6596 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 6597 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
b4617240 | 6598 | void *p) |
bd0362dd JC |
6599 | { |
6600 | int ret_val; | |
6601 | ||
6602 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
b4617240 | 6603 | __ixgbe_notify_dca); |
bd0362dd JC |
6604 | |
6605 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
6606 | } | |
b453368d | 6607 | |
5dd2d332 | 6608 | #endif /* CONFIG_IXGBE_DCA */ |
b453368d AD |
6609 | #ifdef DEBUG |
6610 | /** | |
6611 | * ixgbe_get_hw_dev_name - return device name string | |
6612 | * used by hardware layer to print debugging information | |
6613 | **/ | |
6614 | char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw) | |
6615 | { | |
6616 | struct ixgbe_adapter *adapter = hw->back; | |
6617 | return adapter->netdev->name; | |
6618 | } | |
bd0362dd | 6619 | |
b453368d | 6620 | #endif |
9a799d71 AK |
6621 | module_exit(ixgbe_exit_module); |
6622 | ||
6623 | /* ixgbe_main.c */ |