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ixgbe: Pass rx_ring directly in ixgbe_configure_srrctl()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71
AK		 38#include <linux/ipv6.h>
39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
41#include <linux/ethtool.h>
42#include <linux/if_vlan.h>
eacd73f7 43#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 44
45#include "ixgbe.h"
46#include "ixgbe_common.h"
47
48char ixgbe_driver_name[] = "ixgbe";
9c8eb720 49static const char ixgbe_driver_string[] =
b4617240 50 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 51
a1c1db39 52#define DRV_VERSION "2.0.34-k2"
9c8eb720 53const char ixgbe_driver_version[] = DRV_VERSION;
3efac5a0 54static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
9a799d71
AK		 55
56static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 57 [board_82598] = &ixgbe_82598_info,
e8e26350 58 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 59};
60
61/* ixgbe_pci_tbl - PCI Device ID Table
62 *
63 * Wildcard entries (PCI_ANY_ID) should come last
64 * Last entry must be all 0s
65 *
66 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
67 * Class, Class Mask, private data (not used) }
68 */
69static struct pci_device_id ixgbe_pci_tbl[] = {
1e336d0f
DS		 70 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
71 board_82598 },
9a799d71 72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 73 board_82598 },
9a799d71 74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 75 board_82598 },
0befdb3e
JB		 76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
77 board_82598 },
9a799d71 78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 79 board_82598 },
8d792cd9
JB		 80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
81 board_82598 },
c4900be0
DS		 82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
83 board_82598 },
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
85 board_82598 },
b95f5fcb
JB		 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
87 board_82598 },
c4900be0
DS		 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
89 board_82598 },
2f21bdd3
DS		 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
91 board_82598 },
e8e26350
PW		 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
93 board_82599 },
1fcf03e6
PWJ		 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
95 board_82599 },
e8e26350
PW		 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
97 board_82599 },
9a799d71
AK		 98
99 /* required last entry */
100 {0, }
101};
102MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
103
5dd2d332 104#ifdef CONFIG_IXGBE_DCA
bd0362dd 105static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 106 void *p);
bd0362dd
JC		 107static struct notifier_block dca_notifier = {
108 .notifier_call = ixgbe_notify_dca,
109 .next = NULL,
110 .priority = 0
111};
112#endif
113
9a799d71
AK		 114MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
115MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
116MODULE_LICENSE("GPL");
117MODULE_VERSION(DRV_VERSION);
118
119#define DEFAULT_DEBUG_LEVEL_SHIFT 3
120
5eba3699
AV		 121static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
122{
123 u32 ctrl_ext;
124
125 /* Let firmware take over control of h/w */
126 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
127 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 128 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 129}
130
131static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
132{
133 u32 ctrl_ext;
134
135 /* Let firmware know the driver has taken over */
136 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
137 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 138 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 139}
9a799d71 140
e8e26350
PW		 141/*
142 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
143 * @adapter: pointer to adapter struct
144 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
145 * @queue: queue to map the corresponding interrupt to
146 * @msix_vector: the vector to map to the corresponding queue
147 *
148 */
149static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
150 u8 queue, u8 msix_vector)
9a799d71
AK		 151{
152 u32 ivar, index;
e8e26350
PW		 153 struct ixgbe_hw *hw = &adapter->hw;
154 switch (hw->mac.type) {
155 case ixgbe_mac_82598EB:
156 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
157 if (direction == -1)
158 direction = 0;
159 index = (((direction * 64) + queue) >> 2) & 0x1F;
160 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
161 ivar &= ~(0xFF << (8 * (queue & 0x3)));
162 ivar |= (msix_vector << (8 * (queue & 0x3)));
163 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
164 break;
165 case ixgbe_mac_82599EB:
166 if (direction == -1) {
167 /* other causes */
168 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
169 index = ((queue & 1) * 8);
170 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
171 ivar &= ~(0xFF << index);
172 ivar |= (msix_vector << index);
173 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
174 break;
175 } else {
176 /* tx or rx causes */
177 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
178 index = ((16 * (queue & 1)) + (8 * direction));
179 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
180 ivar &= ~(0xFF << index);
181 ivar |= (msix_vector << index);
182 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
183 break;
184 }
185 default:
186 break;
187 }
9a799d71
AK		 188}
189
fe49f04a
AD		 190static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
191 u64 qmask)
192{
193 u32 mask;
194
195 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
196 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
197 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
198 } else {
199 mask = (qmask & 0xFFFFFFFF);
200 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
201 mask = (qmask >> 32);
202 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
203 }
204}
205
9a799d71 206static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 207 struct ixgbe_tx_buffer
208 *tx_buffer_info)
9a799d71 209{
44df32c5 210 tx_buffer_info->dma = 0;
9a799d71 211 if (tx_buffer_info->skb) {
44df32c5
AD		 212 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
213 DMA_TO_DEVICE);
9a799d71
AK		 214 dev_kfree_skb_any(tx_buffer_info->skb);
215 tx_buffer_info->skb = NULL;
216 }
44df32c5 217 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 218 /* tx_buffer_info must be completely set up in the transmit path */
219}
220
221static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 222 struct ixgbe_ring *tx_ring,
223 unsigned int eop)
9a799d71 224{
e01c31a5 225 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 226
9a799d71 227 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 228 * check with the clearing of time_stamp and movement of eop */
9a799d71 229 adapter->detect_tx_hung = false;
44df32c5 230 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 231 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
232 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
233 /* detected Tx unit hang */
e01c31a5
JB		 234 union ixgbe_adv_tx_desc *tx_desc;
235 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 236 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 237 " Tx Queue <%d>\n"
238 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 239 " next_to_use <%x>\n"
240 " next_to_clean <%x>\n"
241 "tx_buffer_info[next_to_clean]\n"
242 " time_stamp <%lx>\n"
e01c31a5
JB		 243 " jiffies <%lx>\n",
244 tx_ring->queue_index,
44df32c5
AD		 245 IXGBE_READ_REG(hw, tx_ring->head),
246 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 247 tx_ring->next_to_use, eop,
248 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 249 return true;
250 }
251
252 return false;
253}
254
b4617240
PW		 255#define IXGBE_MAX_TXD_PWR 14
256#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 257
258/* Tx Descriptors needed, worst case */
259#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
260 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
261#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 262 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 263
e01c31a5
JB		 264static void ixgbe_tx_timeout(struct net_device *netdev);
265
9a799d71
AK		 266/**
267 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 268 * @q_vector: structure containing interrupt and ring information
e01c31a5 269 * @tx_ring: tx ring to clean
9a799d71 270 **/
fe49f04a 271static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e01c31a5 272 struct ixgbe_ring *tx_ring)
9a799d71 273{
fe49f04a 274 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 275 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 276 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
277 struct ixgbe_tx_buffer *tx_buffer_info;
278 unsigned int i, eop, count = 0;
e01c31a5 279 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 280
281 i = tx_ring->next_to_clean;
12207e49
PWJ		 282 eop = tx_ring->tx_buffer_info[i].next_to_watch;
283 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
284
285 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 286 (count < tx_ring->work_limit)) {
12207e49
PWJ		 287 bool cleaned = false;
288 for ( ; !cleaned; count++) {
289 struct sk_buff *skb;
9a799d71
AK		 290 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
291 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 292 cleaned = (i == eop);
e01c31a5 293 skb = tx_buffer_info->skb;
9a799d71 294
12207e49 295 if (cleaned && skb) {
e092be60 296 unsigned int segs, bytecount;
3d8fd385 297 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 298
299 /* gso_segs is currently only valid for tcp */
e092be60 300 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 301#ifdef IXGBE_FCOE
302 /* adjust for FCoE Sequence Offload */
303 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
304 && (skb->protocol == htons(ETH_P_FCOE)) &&
305 skb_is_gso(skb)) {
306 hlen = skb_transport_offset(skb) +
307 sizeof(struct fc_frame_header) +
308 sizeof(struct fcoe_crc_eof);
309 segs = DIV_ROUND_UP(skb->len - hlen,
310 skb_shinfo(skb)->gso_size);
311 }
312#endif /* IXGBE_FCOE */
e092be60 313 /* multiply data chunks by size of headers */
3d8fd385 314 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 315 total_packets += segs;
316 total_bytes += bytecount;
e092be60 317 }
e01c31a5 318
9a799d71 319 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 320 tx_buffer_info);
9a799d71 321
12207e49
PWJ		 322 tx_desc->wb.status = 0;
323
9a799d71
AK		 324 i++;
325 if (i == tx_ring->count)
326 i = 0;
e01c31a5 327 }
12207e49
PWJ		 328
329 eop = tx_ring->tx_buffer_info[i].next_to_watch;
330 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
331 }
332
9a799d71
AK		 333 tx_ring->next_to_clean = i;
334
e092be60 335#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 336 if (unlikely(count && netif_carrier_ok(netdev) &&
337 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 338 /* Make sure that anybody stopping the queue after this
339 * sees the new next_to_clean.
340 */
341 smp_mb();
30eba97a
AV		 342 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
343 !test_bit(__IXGBE_DOWN, &adapter->state)) {
344 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 345 ++adapter->restart_queue;
30eba97a 346 }
e092be60 347 }
9a799d71 348
e01c31a5
JB		 349 if (adapter->detect_tx_hung) {
350 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
351 /* schedule immediate reset if we believe we hung */
352 DPRINTK(PROBE, INFO,
353 "tx hang %d detected, resetting adapter\n",
354 adapter->tx_timeout_count + 1);
355 ixgbe_tx_timeout(adapter->netdev);
356 }
357 }
9a799d71 358
e01c31a5 359 /* re-arm the interrupt */
fe49f04a
AD		 360 if (count >= tx_ring->work_limit)
361 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 362
e01c31a5
JB		 363 tx_ring->total_bytes += total_bytes;
364 tx_ring->total_packets += total_packets;
e01c31a5 365 tx_ring->stats.packets += total_packets;
12207e49 366 tx_ring->stats.bytes += total_bytes;
e01c31a5
JB		 367 adapter->net_stats.tx_bytes += total_bytes;
368 adapter->net_stats.tx_packets += total_packets;
9a1a69ad 369 return (count < tx_ring->work_limit);
9a799d71
AK		 370}
371
5dd2d332 372#ifdef CONFIG_IXGBE_DCA
bd0362dd 373static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 374 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 375{
376 u32 rxctrl;
377 int cpu = get_cpu();
3a581073 378 int q = rx_ring - adapter->rx_ring;
bd0362dd 379
3a581073 380 if (rx_ring->cpu != cpu) {
bd0362dd 381 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 382 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
383 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
384 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
385 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
386 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
387 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
388 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
389 }
bd0362dd
JC		 390 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
391 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 392 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
393 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 394 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 395 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 396 rx_ring->cpu = cpu;
bd0362dd
JC		 397 }
398 put_cpu();
399}
400
401static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 402 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 403{
404 u32 txctrl;
405 int cpu = get_cpu();
3a581073 406 int q = tx_ring - adapter->tx_ring;
bd0362dd 407
3a581073 408 if (tx_ring->cpu != cpu) {
bd0362dd 409 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 410 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
411 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
412 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
413 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
414 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
415 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
416 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
417 }
bd0362dd
JC		 418 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
419 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 420 tx_ring->cpu = cpu;
bd0362dd
JC		 421 }
422 put_cpu();
423}
424
425static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
426{
427 int i;
428
429 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
430 return;
431
e35ec126
AD		 432 /* always use CB2 mode, difference is masked in the CB driver */
433 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
434
bd0362dd
JC		 435 for (i = 0; i < adapter->num_tx_queues; i++) {
436 adapter->tx_ring[i].cpu = -1;
437 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
438 }
439 for (i = 0; i < adapter->num_rx_queues; i++) {
440 adapter->rx_ring[i].cpu = -1;
441 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
442 }
443}
444
445static int __ixgbe_notify_dca(struct device *dev, void *data)
446{
447 struct net_device *netdev = dev_get_drvdata(dev);
448 struct ixgbe_adapter *adapter = netdev_priv(netdev);
449 unsigned long event = *(unsigned long *)data;
450
451 switch (event) {
452 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 453 /* if we're already enabled, don't do it again */
454 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
455 break;
652f093f 456 if (dca_add_requester(dev) == 0) {
96b0e0f6 457 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 458 ixgbe_setup_dca(adapter);
459 break;
460 }
461 /* Fall Through since DCA is disabled. */
462 case DCA_PROVIDER_REMOVE:
463 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
464 dca_remove_requester(dev);
465 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
466 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
467 }
468 break;
469 }
470
652f093f 471 return 0;
bd0362dd
JC		 472}
473
5dd2d332 474#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 475/**
476 * ixgbe_receive_skb - Send a completed packet up the stack
477 * @adapter: board private structure
478 * @skb: packet to send up
177db6ff
MC		 479 * @status: hardware indication of status of receive
480 * @rx_ring: rx descriptor ring (for a specific queue) to setup
481 * @rx_desc: rx descriptor
9a799d71 482 **/
78b6f4ce 483static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 484 struct sk_buff *skb, u8 status,
fdaff1ce 485 struct ixgbe_ring *ring,
177db6ff 486 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 487{
78b6f4ce
HX		 488 struct ixgbe_adapter *adapter = q_vector->adapter;
489 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 490 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
491 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 492
fdaff1ce 493 skb_record_rx_queue(skb, ring->queue_index);
182ff8df 494 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
2f90b865 495 if (adapter->vlgrp && is_vlan && (tag != 0))
78b6f4ce 496 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 497 else
78b6f4ce 498 napi_gro_receive(napi, skb);
177db6ff 499 } else {
182ff8df
AD		 500 if (adapter->vlgrp && is_vlan && (tag != 0))
501 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
502 else
503 netif_rx(skb);
9a799d71
AK		 504 }
505}
506
e59bd25d
AV		 507/**
508 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
509 * @adapter: address of board private structure
510 * @status_err: hardware indication of status of receive
511 * @skb: skb currently being received and modified
512 **/
9a799d71 513static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 514 union ixgbe_adv_rx_desc *rx_desc,
515 struct sk_buff *skb)
9a799d71 516{
8bae1b2b
DS		 517 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
518
9a799d71
AK		 519 skb->ip_summed = CHECKSUM_NONE;
520
712744be
JB		 521 /* Rx csum disabled */
522 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 523 return;
e59bd25d
AV		 524
525 /* if IP and error */
526 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
527 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 528 adapter->hw_csum_rx_error++;
529 return;
530 }
e59bd25d
AV		 531
532 if (!(status_err & IXGBE_RXD_STAT_L4CS))
533 return;
534
535 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 536 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
537
538 /*
539 * 82599 errata, UDP frames with a 0 checksum can be marked as
540 * checksum errors.
541 */
542 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
543 (adapter->hw.mac.type == ixgbe_mac_82599EB))
544 return;
545
e59bd25d
AV		 546 adapter->hw_csum_rx_error++;
547 return;
548 }
549
9a799d71 550 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 551 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 552 adapter->hw_csum_rx_good++;
553}
554
e8e26350
PW		 555static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
556 struct ixgbe_ring *rx_ring, u32 val)
557{
558 /*
559 * Force memory writes to complete before letting h/w
560 * know there are new descriptors to fetch. (Only
561 * applicable for weak-ordered memory model archs,
562 * such as IA-64).
563 */
564 wmb();
565 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
566}
567
9a799d71
AK		 568/**
569 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
570 * @adapter: address of board private structure
571 **/
572static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 573 struct ixgbe_ring *rx_ring,
574 int cleaned_count)
9a799d71 575{
9a799d71
AK		 576 struct pci_dev *pdev = adapter->pdev;
577 union ixgbe_adv_rx_desc *rx_desc;
3a581073 578 struct ixgbe_rx_buffer *bi;
9a799d71 579 unsigned int i;
9a799d71
AK		 580
581 i = rx_ring->next_to_use;
3a581073 582 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 583
584 while (cleaned_count--) {
585 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
586
762f4c57 587 if (!bi->page_dma &&
3a581073 588 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
3a581073 589 if (!bi->page) {
762f4c57
JB		 590 bi->page = alloc_page(GFP_ATOMIC);
591 if (!bi->page) {
592 adapter->alloc_rx_page_failed++;
593 goto no_buffers;
594 }
595 bi->page_offset = 0;
596 } else {
597 /* use a half page if we're re-using */
598 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 599 }
762f4c57
JB		 600
601 bi->page_dma = pci_map_page(pdev, bi->page,
602 bi->page_offset,
603 (PAGE_SIZE / 2),
604 PCI_DMA_FROMDEVICE);
9a799d71
AK		 605 }
606
3a581073 607 if (!bi->skb) {
5ecc3614 608 struct sk_buff *skb;
4f57ca6e
JB		 609 skb = netdev_alloc_skb(adapter->netdev,
610 (rx_ring->rx_buf_len +
611 NET_IP_ALIGN));
9a799d71
AK		 612
613 if (!skb) {
614 adapter->alloc_rx_buff_failed++;
615 goto no_buffers;
616 }
617
618 /*
619 * Make buffer alignment 2 beyond a 16 byte boundary
620 * this will result in a 16 byte aligned IP header after
621 * the 14 byte MAC header is removed
622 */
623 skb_reserve(skb, NET_IP_ALIGN);
624
3a581073 625 bi->skb = skb;
4f57ca6e
JB		 626 bi->dma = pci_map_single(pdev, skb->data,
627 rx_ring->rx_buf_len,
3a581073 628 PCI_DMA_FROMDEVICE);
9a799d71
AK		 629 }
630 /* Refresh the desc even if buffer_addrs didn't change because
631 * each write-back erases this info. */
632 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3a581073
JB		 633 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
634 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 635 } else {
3a581073 636 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 637 }
638
639 i++;
640 if (i == rx_ring->count)
641 i = 0;
3a581073 642 bi = &rx_ring->rx_buffer_info[i];
9a799d71 643 }
7c6e0a43 644
9a799d71
AK		 645no_buffers:
646 if (rx_ring->next_to_use != i) {
647 rx_ring->next_to_use = i;
648 if (i-- == 0)
649 i = (rx_ring->count - 1);
650
e8e26350 651 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 652 }
653}
654
7c6e0a43
JB		 655static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
656{
657 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
658}
659
660static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
661{
662 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
663}
664
f8212f97
AD		 665static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
666{
667 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
668 IXGBE_RXDADV_RSCCNT_MASK) >>
669 IXGBE_RXDADV_RSCCNT_SHIFT;
670}
671
672/**
673 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
674 * @skb: pointer to the last skb in the rsc queue
675 *
676 * This function changes a queue full of hw rsc buffers into a completed
677 * packet. It uses the ->prev pointers to find the first packet and then
678 * turns it into the frag list owner.
679 **/
680static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
681{
682 unsigned int frag_list_size = 0;
683
684 while (skb->prev) {
685 struct sk_buff *prev = skb->prev;
686 frag_list_size += skb->len;
687 skb->prev = NULL;
688 skb = prev;
689 }
690
691 skb_shinfo(skb)->frag_list = skb->next;
692 skb->next = NULL;
693 skb->len += frag_list_size;
694 skb->data_len += frag_list_size;
695 skb->truesize += frag_list_size;
696 return skb;
697}
698
78b6f4ce 699static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 700 struct ixgbe_ring *rx_ring,
701 int *work_done, int work_to_do)
9a799d71 702{
78b6f4ce 703 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 704 struct pci_dev *pdev = adapter->pdev;
705 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
706 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
707 struct sk_buff *skb;
f8212f97 708 unsigned int i, rsc_count = 0;
7c6e0a43 709 u32 len, staterr;
177db6ff
MC		 710 u16 hdr_info;
711 bool cleaned = false;
9a799d71 712 int cleaned_count = 0;
d2f4fbe2 713 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 714#ifdef IXGBE_FCOE
715 int ddp_bytes = 0;
716#endif /* IXGBE_FCOE */
9a799d71
AK		 717
718 i = rx_ring->next_to_clean;
9a799d71
AK		 719 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
720 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
721 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 722
723 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 724 u32 upper_len = 0;
9a799d71
AK		 725 if (*work_done >= work_to_do)
726 break;
727 (*work_done)++;
728
729 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43
JB		 730 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
731 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 732 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 733 if (hdr_info & IXGBE_RXDADV_SPH)
734 adapter->rx_hdr_split++;
735 if (len > IXGBE_RX_HDR_SIZE)
736 len = IXGBE_RX_HDR_SIZE;
737 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 738 } else {
9a799d71 739 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 740 }
9a799d71
AK		 741
742 cleaned = true;
743 skb = rx_buffer_info->skb;
744 prefetch(skb->data - NET_IP_ALIGN);
745 rx_buffer_info->skb = NULL;
746
21fa4e66 747 if (rx_buffer_info->dma) {
9a799d71 748 pci_unmap_single(pdev, rx_buffer_info->dma,
5ecc3614 749 rx_ring->rx_buf_len,
b4617240 750 PCI_DMA_FROMDEVICE);
4f57ca6e 751 rx_buffer_info->dma = 0;
9a799d71
AK		 752 skb_put(skb, len);
753 }
754
755 if (upper_len) {
756 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 757 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 758 rx_buffer_info->page_dma = 0;
759 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 760 rx_buffer_info->page,
761 rx_buffer_info->page_offset,
762 upper_len);
763
764 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
765 (page_count(rx_buffer_info->page) != 1))
766 rx_buffer_info->page = NULL;
767 else
768 get_page(rx_buffer_info->page);
9a799d71
AK		 769
770 skb->len += upper_len;
771 skb->data_len += upper_len;
772 skb->truesize += upper_len;
773 }
774
775 i++;
776 if (i == rx_ring->count)
777 i = 0;
9a799d71
AK		 778
779 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
780 prefetch(next_rxd);
9a799d71 781 cleaned_count++;
f8212f97 782
0c19d6af 783 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 784 rsc_count = ixgbe_get_rsc_count(rx_desc);
785
786 if (rsc_count) {
787 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
788 IXGBE_RXDADV_NEXTP_SHIFT;
789 next_buffer = &rx_ring->rx_buffer_info[nextp];
790 rx_ring->rsc_count += (rsc_count - 1);
791 } else {
792 next_buffer = &rx_ring->rx_buffer_info[i];
793 }
794
9a799d71 795 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97
AD		 796 if (skb->prev)
797 skb = ixgbe_transform_rsc_queue(skb);
9a799d71
AK		 798 rx_ring->stats.packets++;
799 rx_ring->stats.bytes += skb->len;
800 } else {
f8212f97
AD		 801 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
802 rx_buffer_info->skb = next_buffer->skb;
803 rx_buffer_info->dma = next_buffer->dma;
804 next_buffer->skb = skb;
805 next_buffer->dma = 0;
806 } else {
807 skb->next = next_buffer->skb;
808 skb->next->prev = skb;
809 }
9a799d71
AK		 810 adapter->non_eop_descs++;
811 goto next_desc;
812 }
813
814 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
815 dev_kfree_skb_irq(skb);
816 goto next_desc;
817 }
818
8bae1b2b 819 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 820
821 /* probably a little skewed due to removing CRC */
822 total_rx_bytes += skb->len;
823 total_rx_packets++;
824
74ce8dd2 825 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 826#ifdef IXGBE_FCOE
827 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 828 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
829 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
830 if (!ddp_bytes)
332d4a7d 831 goto next_desc;
3d8fd385 832 }
332d4a7d 833#endif /* IXGBE_FCOE */
fdaff1ce 834 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 835
836next_desc:
837 rx_desc->wb.upper.status_error = 0;
838
839 /* return some buffers to hardware, one at a time is too slow */
840 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
841 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
842 cleaned_count = 0;
843 }
844
845 /* use prefetched values */
846 rx_desc = next_rxd;
f8212f97 847 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 848
849 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 850 }
851
9a799d71
AK		 852 rx_ring->next_to_clean = i;
853 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
854
855 if (cleaned_count)
856 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
857
3d8fd385
YZ		 858#ifdef IXGBE_FCOE
859 /* include DDPed FCoE data */
860 if (ddp_bytes > 0) {
861 unsigned int mss;
862
863 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
864 sizeof(struct fc_frame_header) -
865 sizeof(struct fcoe_crc_eof);
866 if (mss > 512)
867 mss &= ~511;
868 total_rx_bytes += ddp_bytes;
869 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
870 }
871#endif /* IXGBE_FCOE */
872
f494e8fa
AV		 873 rx_ring->total_packets += total_rx_packets;
874 rx_ring->total_bytes += total_rx_bytes;
875 adapter->net_stats.rx_bytes += total_rx_bytes;
876 adapter->net_stats.rx_packets += total_rx_packets;
877
9a799d71
AK		 878 return cleaned;
879}
880
021230d4 881static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 882/**
883 * ixgbe_configure_msix - Configure MSI-X hardware
884 * @adapter: board private structure
885 *
886 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
887 * interrupts.
888 **/
889static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
890{
021230d4
AV		 891 struct ixgbe_q_vector *q_vector;
892 int i, j, q_vectors, v_idx, r_idx;
893 u32 mask;
9a799d71 894
021230d4 895 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 896
4df10466
JB		 897 /*
898 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 899 * corresponding register.
900 */
901 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 902 q_vector = adapter->q_vector[v_idx];
021230d4
AV		 903 /* XXX for_each_bit(...) */
904 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 905 adapter->num_rx_queues);
021230d4
AV		 906
907 for (i = 0; i < q_vector->rxr_count; i++) {
908 j = adapter->rx_ring[r_idx].reg_idx;
e8e26350 909 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 910 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 911 adapter->num_rx_queues,
912 r_idx + 1);
021230d4
AV		 913 }
914 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 915 adapter->num_tx_queues);
021230d4
AV		 916
917 for (i = 0; i < q_vector->txr_count; i++) {
918 j = adapter->tx_ring[r_idx].reg_idx;
e8e26350 919 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 920 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 921 adapter->num_tx_queues,
922 r_idx + 1);
021230d4
AV		 923 }
924
30efa5a3 925 /* if this is a tx only vector halve the interrupt rate */
021230d4 926 if (q_vector->txr_count && !q_vector->rxr_count)
30efa5a3 927 q_vector->eitr = (adapter->eitr_param >> 1);
509ee935 928 else if (q_vector->rxr_count)
30efa5a3
JB		 929 /* rx only */
930 q_vector->eitr = adapter->eitr_param;
021230d4 931
fe49f04a 932 ixgbe_write_eitr(q_vector);
9a799d71
AK		 933 }
934
e8e26350
PW		 935 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
936 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
937 v_idx);
938 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
939 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 940 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
941
41fb9248 942 /* set up to autoclear timer, and the vectors */
021230d4 943 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 944 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 945 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 946}
947
f494e8fa
AV		 948enum latency_range {
949 lowest_latency = 0,
950 low_latency = 1,
951 bulk_latency = 2,
952 latency_invalid = 255
953};
954
955/**
956 * ixgbe_update_itr - update the dynamic ITR value based on statistics
957 * @adapter: pointer to adapter
958 * @eitr: eitr setting (ints per sec) to give last timeslice
959 * @itr_setting: current throttle rate in ints/second
960 * @packets: the number of packets during this measurement interval
961 * @bytes: the number of bytes during this measurement interval
962 *
963 * Stores a new ITR value based on packets and byte
964 * counts during the last interrupt. The advantage of per interrupt
965 * computation is faster updates and more accurate ITR for the current
966 * traffic pattern. Constants in this function were computed
967 * based on theoretical maximum wire speed and thresholds were set based
968 * on testing data as well as attempting to minimize response time
969 * while increasing bulk throughput.
970 * this functionality is controlled by the InterruptThrottleRate module
971 * parameter (see ixgbe_param.c)
972 **/
973static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 974 u32 eitr, u8 itr_setting,
975 int packets, int bytes)
f494e8fa
AV		 976{
977 unsigned int retval = itr_setting;
978 u32 timepassed_us;
979 u64 bytes_perint;
980
981 if (packets == 0)
982 goto update_itr_done;
983
984
985 /* simple throttlerate management
986 * 0-20MB/s lowest (100000 ints/s)
987 * 20-100MB/s low (20000 ints/s)
988 * 100-1249MB/s bulk (8000 ints/s)
989 */
990 /* what was last interrupt timeslice? */
991 timepassed_us = 1000000/eitr;
992 bytes_perint = bytes / timepassed_us; /* bytes/usec */
993
994 switch (itr_setting) {
995 case lowest_latency:
996 if (bytes_perint > adapter->eitr_low)
997 retval = low_latency;
998 break;
999 case low_latency:
1000 if (bytes_perint > adapter->eitr_high)
1001 retval = bulk_latency;
1002 else if (bytes_perint <= adapter->eitr_low)
1003 retval = lowest_latency;
1004 break;
1005 case bulk_latency:
1006 if (bytes_perint <= adapter->eitr_high)
1007 retval = low_latency;
1008 break;
1009 }
1010
1011update_itr_done:
1012 return retval;
1013}
1014
509ee935
JB		 1015/**
1016 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1017 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1018 *
1019 * This function is made to be called by ethtool and by the driver
1020 * when it needs to update EITR registers at runtime. Hardware
1021 * specific quirks/differences are taken care of here.
1022 */
fe49f04a 1023void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1024{
fe49f04a 1025 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1026 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1027 int v_idx = q_vector->v_idx;
1028 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1029
509ee935
JB		 1030 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1031 /* must write high and low 16 bits to reset counter */
1032 itr_reg |= (itr_reg << 16);
1033 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1034 /*
1035 * set the WDIS bit to not clear the timer bits and cause an
1036 * immediate assertion of the interrupt
1037 */
1038 itr_reg |= IXGBE_EITR_CNT_WDIS;
1039 }
1040 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1041}
1042
f494e8fa
AV		 1043static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1044{
1045 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1046 u32 new_itr;
1047 u8 current_itr, ret_itr;
fe49f04a 1048 int i, r_idx;
f494e8fa
AV		 1049 struct ixgbe_ring *rx_ring, *tx_ring;
1050
1051 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1052 for (i = 0; i < q_vector->txr_count; i++) {
1053 tx_ring = &(adapter->tx_ring[r_idx]);
1054 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1055 q_vector->tx_itr,
1056 tx_ring->total_packets,
1057 tx_ring->total_bytes);
f494e8fa
AV		 1058 /* if the result for this queue would decrease interrupt
1059 * rate for this vector then use that result */
30efa5a3 1060 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1061 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1062 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1063 r_idx + 1);
f494e8fa
AV		 1064 }
1065
1066 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1067 for (i = 0; i < q_vector->rxr_count; i++) {
1068 rx_ring = &(adapter->rx_ring[r_idx]);
1069 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1070 q_vector->rx_itr,
1071 rx_ring->total_packets,
1072 rx_ring->total_bytes);
f494e8fa
AV		 1073 /* if the result for this queue would decrease interrupt
1074 * rate for this vector then use that result */
30efa5a3 1075 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1076 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1077 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1078 r_idx + 1);
f494e8fa
AV		 1079 }
1080
30efa5a3 1081 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1082
1083 switch (current_itr) {
1084 /* counts and packets in update_itr are dependent on these numbers */
1085 case lowest_latency:
1086 new_itr = 100000;
1087 break;
1088 case low_latency:
1089 new_itr = 20000; /* aka hwitr = ~200 */
1090 break;
1091 case bulk_latency:
1092 default:
1093 new_itr = 8000;
1094 break;
1095 }
1096
1097 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1098 /* do an exponential smoothing */
1099 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1100
1101 /* save the algorithm value here, not the smoothed one */
1102 q_vector->eitr = new_itr;
fe49f04a
AD		 1103
1104 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1105 }
1106
1107 return;
1108}
1109
0befdb3e
JB		 1110static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1111{
1112 struct ixgbe_hw *hw = &adapter->hw;
1113
1114 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1115 (eicr & IXGBE_EICR_GPI_SDP1)) {
1116 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1117 /* write to clear the interrupt */
1118 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1119 }
1120}
cf8280ee 1121
e8e26350
PW		 1122static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1123{
1124 struct ixgbe_hw *hw = &adapter->hw;
1125
1126 if (eicr & IXGBE_EICR_GPI_SDP1) {
1127 /* Clear the interrupt */
1128 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1129 schedule_work(&adapter->multispeed_fiber_task);
1130 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1131 /* Clear the interrupt */
1132 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1133 schedule_work(&adapter->sfp_config_module_task);
1134 } else {
1135 /* Interrupt isn't for us... */
1136 return;
1137 }
1138}
1139
cf8280ee
JB		 1140static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1141{
1142 struct ixgbe_hw *hw = &adapter->hw;
1143
1144 adapter->lsc_int++;
1145 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1146 adapter->link_check_timeout = jiffies;
1147 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1148 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1149 schedule_work(&adapter->watchdog_task);
1150 }
1151}
1152
9a799d71
AK		 1153static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1154{
1155 struct net_device *netdev = data;
1156 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1157 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1158 u32 eicr;
1159
1160 /*
1161 * Workaround for Silicon errata. Use clear-by-write instead
1162 * of clear-by-read. Reading with EICS will return the
1163 * interrupt causes without clearing, which later be done
1164 * with the write to EICR.
1165 */
1166 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1167 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1168
cf8280ee
JB		 1169 if (eicr & IXGBE_EICR_LSC)
1170 ixgbe_check_lsc(adapter);
d4f80882 1171
e8e26350
PW		 1172 if (hw->mac.type == ixgbe_mac_82598EB)
1173 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1174
c4cf55e5 1175 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1176 ixgbe_check_sfp_event(adapter, eicr);
c4cf55e5
PWJ		 1177
1178 /* Handle Flow Director Full threshold interrupt */
1179 if (eicr & IXGBE_EICR_FLOW_DIR) {
1180 int i;
1181 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1182 /* Disable transmits before FDIR Re-initialization */
1183 netif_tx_stop_all_queues(netdev);
1184 for (i = 0; i < adapter->num_tx_queues; i++) {
1185 struct ixgbe_ring *tx_ring =
1186 &adapter->tx_ring[i];
1187 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1188 &tx_ring->reinit_state))
1189 schedule_work(&adapter->fdir_reinit_task);
1190 }
1191 }
1192 }
d4f80882
AV		 1193 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1194 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1195
1196 return IRQ_HANDLED;
1197}
1198
fe49f04a
AD		 1199static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1200 u64 qmask)
1201{
1202 u32 mask;
1203
1204 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1205 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1206 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1207 } else {
1208 mask = (qmask & 0xFFFFFFFF);
1209 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1210 mask = (qmask >> 32);
1211 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1212 }
1213 /* skip the flush */
1214}
1215
1216static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1217 u64 qmask)
1218{
1219 u32 mask;
1220
1221 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1222 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1223 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1224 } else {
1225 mask = (qmask & 0xFFFFFFFF);
1226 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1227 mask = (qmask >> 32);
1228 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1229 }
1230 /* skip the flush */
1231}
1232
9a799d71
AK		 1233static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1234{
021230d4
AV		 1235 struct ixgbe_q_vector *q_vector = data;
1236 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1237 struct ixgbe_ring *tx_ring;
021230d4
AV		 1238 int i, r_idx;
1239
1240 if (!q_vector->txr_count)
1241 return IRQ_HANDLED;
1242
1243 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1244 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 1245 tx_ring = &(adapter->tx_ring[r_idx]);
3a581073
JB		 1246 tx_ring->total_bytes = 0;
1247 tx_ring->total_packets = 0;
021230d4 1248 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1249 r_idx + 1);
021230d4 1250 }
9a799d71 1251
91281fd3
AD		 1252 /* disable interrupts on this vector only */
1253 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1254 napi_schedule(&q_vector->napi);
1255
9a799d71
AK		 1256 return IRQ_HANDLED;
1257}
1258
021230d4
AV		 1259/**
1260 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1261 * @irq: unused
1262 * @data: pointer to our q_vector struct for this interrupt vector
1263 **/
9a799d71
AK		 1264static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1265{
021230d4
AV		 1266 struct ixgbe_q_vector *q_vector = data;
1267 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1268 struct ixgbe_ring *rx_ring;
021230d4 1269 int r_idx;
30efa5a3 1270 int i;
021230d4
AV		 1271
1272 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 1273 for (i = 0; i < q_vector->rxr_count; i++) {
1274 rx_ring = &(adapter->rx_ring[r_idx]);
1275 rx_ring->total_bytes = 0;
1276 rx_ring->total_packets = 0;
1277 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1278 r_idx + 1);
1279 }
1280
021230d4
AV		 1281 if (!q_vector->rxr_count)
1282 return IRQ_HANDLED;
1283
30efa5a3 1284 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1285 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 1286 /* disable interrupts on this vector only */
fe49f04a 1287 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
288379f0 1288 napi_schedule(&q_vector->napi);
021230d4
AV		 1289
1290 return IRQ_HANDLED;
1291}
1292
1293static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1294{
91281fd3
AD		 1295 struct ixgbe_q_vector *q_vector = data;
1296 struct ixgbe_adapter *adapter = q_vector->adapter;
1297 struct ixgbe_ring *ring;
1298 int r_idx;
1299 int i;
1300
1301 if (!q_vector->txr_count && !q_vector->rxr_count)
1302 return IRQ_HANDLED;
1303
1304 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1305 for (i = 0; i < q_vector->txr_count; i++) {
1306 ring = &(adapter->tx_ring[r_idx]);
1307 ring->total_bytes = 0;
1308 ring->total_packets = 0;
1309 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1310 r_idx + 1);
1311 }
1312
1313 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1314 for (i = 0; i < q_vector->rxr_count; i++) {
1315 ring = &(adapter->rx_ring[r_idx]);
1316 ring->total_bytes = 0;
1317 ring->total_packets = 0;
1318 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1319 r_idx + 1);
1320 }
1321
1322 /* disable interrupts on this vector only */
1323 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1324 napi_schedule(&q_vector->napi);
9a799d71 1325
9a799d71
AK		 1326 return IRQ_HANDLED;
1327}
1328
021230d4
AV		 1329/**
1330 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1331 * @napi: napi struct with our devices info in it
1332 * @budget: amount of work driver is allowed to do this pass, in packets
1333 *
f0848276
JB		 1334 * This function is optimized for cleaning one queue only on a single
1335 * q_vector!!!
021230d4 1336 **/
9a799d71
AK		 1337static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1338{
021230d4 1339 struct ixgbe_q_vector *q_vector =
b4617240 1340 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1341 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1342 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1343 int work_done = 0;
021230d4 1344 long r_idx;
9a799d71 1345
021230d4 1346 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1347 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1348#ifdef CONFIG_IXGBE_DCA
bd0362dd 1349 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1350 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1351#endif
9a799d71 1352
78b6f4ce 1353 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1354
021230d4
AV		 1355 /* If all Rx work done, exit the polling mode */
1356 if (work_done < budget) {
288379f0 1357 napi_complete(napi);
509ee935 1358 if (adapter->itr_setting & 1)
f494e8fa 1359 ixgbe_set_itr_msix(q_vector);
9a799d71 1360 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1361 ixgbe_irq_enable_queues(adapter,
1362 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1363 }
1364
1365 return work_done;
1366}
1367
f0848276 1368/**
91281fd3 1369 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1370 * @napi: napi struct with our devices info in it
1371 * @budget: amount of work driver is allowed to do this pass, in packets
1372 *
1373 * This function will clean more than one rx queue associated with a
1374 * q_vector.
1375 **/
91281fd3 1376static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1377{
1378 struct ixgbe_q_vector *q_vector =
1379 container_of(napi, struct ixgbe_q_vector, napi);
1380 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1381 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1382 int work_done = 0, i;
1383 long r_idx;
91281fd3
AD		 1384 bool tx_clean_complete = true;
1385
1386 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1387 for (i = 0; i < q_vector->txr_count; i++) {
1388 ring = &(adapter->tx_ring[r_idx]);
1389#ifdef CONFIG_IXGBE_DCA
1390 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1391 ixgbe_update_tx_dca(adapter, ring);
1392#endif
1393 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1394 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1395 r_idx + 1);
1396 }
f0848276
JB		 1397
1398 /* attempt to distribute budget to each queue fairly, but don't allow
1399 * the budget to go below 1 because we'll exit polling */
1400 budget /= (q_vector->rxr_count ?: 1);
1401 budget = max(budget, 1);
1402 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1403 for (i = 0; i < q_vector->rxr_count; i++) {
91281fd3 1404 ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1405#ifdef CONFIG_IXGBE_DCA
f0848276 1406 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1407 ixgbe_update_rx_dca(adapter, ring);
f0848276 1408#endif
91281fd3 1409 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276
JB		 1410 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1411 r_idx + 1);
1412 }
1413
1414 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
91281fd3 1415 ring = &(adapter->rx_ring[r_idx]);
f0848276 1416 /* If all Rx work done, exit the polling mode */
7f821875 1417 if (work_done < budget) {
288379f0 1418 napi_complete(napi);
509ee935 1419 if (adapter->itr_setting & 1)
f0848276
JB		 1420 ixgbe_set_itr_msix(q_vector);
1421 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1422 ixgbe_irq_enable_queues(adapter,
1423 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1424 return 0;
1425 }
1426
1427 return work_done;
1428}
91281fd3
AD		 1429
1430/**
1431 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1432 * @napi: napi struct with our devices info in it
1433 * @budget: amount of work driver is allowed to do this pass, in packets
1434 *
1435 * This function is optimized for cleaning one queue only on a single
1436 * q_vector!!!
1437 **/
1438static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1439{
1440 struct ixgbe_q_vector *q_vector =
1441 container_of(napi, struct ixgbe_q_vector, napi);
1442 struct ixgbe_adapter *adapter = q_vector->adapter;
1443 struct ixgbe_ring *tx_ring = NULL;
1444 int work_done = 0;
1445 long r_idx;
1446
1447 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1448 tx_ring = &(adapter->tx_ring[r_idx]);
1449#ifdef CONFIG_IXGBE_DCA
1450 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1451 ixgbe_update_tx_dca(adapter, tx_ring);
1452#endif
1453
1454 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1455 work_done = budget;
1456
1457 /* If all Rx work done, exit the polling mode */
1458 if (work_done < budget) {
1459 napi_complete(napi);
1460 if (adapter->itr_setting & 1)
1461 ixgbe_set_itr_msix(q_vector);
1462 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1463 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1464 }
1465
1466 return work_done;
1467}
1468
021230d4 1469static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1470 int r_idx)
021230d4 1471{
7a921c93
AD		 1472 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1473
1474 set_bit(r_idx, q_vector->rxr_idx);
1475 q_vector->rxr_count++;
021230d4
AV		 1476}
1477
1478static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 1479 int t_idx)
021230d4 1480{
7a921c93
AD		 1481 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1482
1483 set_bit(t_idx, q_vector->txr_idx);
1484 q_vector->txr_count++;
021230d4
AV		 1485}
1486
9a799d71 1487/**
021230d4
AV		 1488 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1489 * @adapter: board private structure to initialize
1490 * @vectors: allotted vector count for descriptor rings
9a799d71 1491 *
021230d4
AV		 1492 * This function maps descriptor rings to the queue-specific vectors
1493 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1494 * one vector per ring/queue, but on a constrained vector budget, we
1495 * group the rings as "efficiently" as possible. You would add new
1496 * mapping configurations in here.
9a799d71 1497 **/
021230d4 1498static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1499 int vectors)
021230d4
AV		 1500{
1501 int v_start = 0;
1502 int rxr_idx = 0, txr_idx = 0;
1503 int rxr_remaining = adapter->num_rx_queues;
1504 int txr_remaining = adapter->num_tx_queues;
1505 int i, j;
1506 int rqpv, tqpv;
1507 int err = 0;
1508
1509 /* No mapping required if MSI-X is disabled. */
1510 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1511 goto out;
9a799d71 1512
021230d4
AV		 1513 /*
1514 * The ideal configuration...
1515 * We have enough vectors to map one per queue.
1516 */
1517 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1518 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1519 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1520
021230d4
AV		 1521 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1522 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1523
9a799d71 1524 goto out;
021230d4 1525 }
9a799d71 1526
021230d4
AV		 1527 /*
1528 * If we don't have enough vectors for a 1-to-1
1529 * mapping, we'll have to group them so there are
1530 * multiple queues per vector.
1531 */
1532 /* Re-adjusting *qpv takes care of the remainder. */
1533 for (i = v_start; i < vectors; i++) {
1534 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1535 for (j = 0; j < rqpv; j++) {
1536 map_vector_to_rxq(adapter, i, rxr_idx);
1537 rxr_idx++;
1538 rxr_remaining--;
1539 }
1540 }
1541 for (i = v_start; i < vectors; i++) {
1542 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1543 for (j = 0; j < tqpv; j++) {
1544 map_vector_to_txq(adapter, i, txr_idx);
1545 txr_idx++;
1546 txr_remaining--;
9a799d71 1547 }
9a799d71
AK		 1548 }
1549
021230d4
AV		 1550out:
1551 return err;
1552}
1553
1554/**
1555 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1556 * @adapter: board private structure
1557 *
1558 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1559 * interrupts from the kernel.
1560 **/
1561static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1562{
1563 struct net_device *netdev = adapter->netdev;
1564 irqreturn_t (*handler)(int, void *);
1565 int i, vector, q_vectors, err;
cb13fc20 1566 int ri=0, ti=0;
021230d4
AV		 1567
1568 /* Decrement for Other and TCP Timer vectors */
1569 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1570
1571 /* Map the Tx/Rx rings to the vectors we were allotted. */
1572 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1573 if (err)
1574 goto out;
1575
1576#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1577 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1578 &ixgbe_msix_clean_many)
021230d4 1579 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 1580 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 1581
1582 if(handler == &ixgbe_msix_clean_rx) {
1583 sprintf(adapter->name[vector], "%s-%s-%d",
1584 netdev->name, "rx", ri++);
1585 }
1586 else if(handler == &ixgbe_msix_clean_tx) {
1587 sprintf(adapter->name[vector], "%s-%s-%d",
1588 netdev->name, "tx", ti++);
1589 }
1590 else
1591 sprintf(adapter->name[vector], "%s-%s-%d",
1592 netdev->name, "TxRx", vector);
1593
021230d4 1594 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1595 handler, 0, adapter->name[vector],
7a921c93 1596 adapter->q_vector[vector]);
9a799d71
AK		 1597 if (err) {
1598 DPRINTK(PROBE, ERR,
b4617240
PW		 1599 "request_irq failed for MSIX interrupt "
1600 "Error: %d\n", err);
021230d4 1601 goto free_queue_irqs;
9a799d71 1602 }
9a799d71
AK		 1603 }
1604
021230d4
AV		 1605 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1606 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1607 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1608 if (err) {
1609 DPRINTK(PROBE, ERR,
1610 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1611 goto free_queue_irqs;
9a799d71
AK		 1612 }
1613
9a799d71
AK		 1614 return 0;
1615
021230d4
AV		 1616free_queue_irqs:
1617 for (i = vector - 1; i >= 0; i--)
1618 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 1619 adapter->q_vector[i]);
021230d4
AV		 1620 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1621 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1622 kfree(adapter->msix_entries);
1623 adapter->msix_entries = NULL;
021230d4 1624out:
9a799d71
AK		 1625 return err;
1626}
1627
f494e8fa
AV		 1628static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1629{
7a921c93 1630 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 1631 u8 current_itr;
1632 u32 new_itr = q_vector->eitr;
1633 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1634 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1635
30efa5a3 1636 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1637 q_vector->tx_itr,
1638 tx_ring->total_packets,
1639 tx_ring->total_bytes);
30efa5a3 1640 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1641 q_vector->rx_itr,
1642 rx_ring->total_packets,
1643 rx_ring->total_bytes);
f494e8fa 1644
30efa5a3 1645 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1646
1647 switch (current_itr) {
1648 /* counts and packets in update_itr are dependent on these numbers */
1649 case lowest_latency:
1650 new_itr = 100000;
1651 break;
1652 case low_latency:
1653 new_itr = 20000; /* aka hwitr = ~200 */
1654 break;
1655 case bulk_latency:
1656 new_itr = 8000;
1657 break;
1658 default:
1659 break;
1660 }
1661
1662 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1663 /* do an exponential smoothing */
1664 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1665
1666 /* save the algorithm value here, not the smoothed one */
1667 q_vector->eitr = new_itr;
fe49f04a
AD		 1668
1669 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1670 }
1671
1672 return;
1673}
1674
79aefa45
AD		 1675/**
1676 * ixgbe_irq_enable - Enable default interrupt generation settings
1677 * @adapter: board private structure
1678 **/
1679static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1680{
1681 u32 mask;
835462fc
NS		 1682
1683 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 1684 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1685 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1686 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1687 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1688 mask |= IXGBE_EIMS_GPI_SDP1;
1689 mask |= IXGBE_EIMS_GPI_SDP2;
1690 }
c4cf55e5
PWJ		 1691 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1692 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1693 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 1694
79aefa45 1695 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 1696 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45
AD		 1697 IXGBE_WRITE_FLUSH(&adapter->hw);
1698}
021230d4 1699
9a799d71 1700/**
021230d4 1701 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1702 * @irq: interrupt number
1703 * @data: pointer to a network interface device structure
9a799d71
AK		 1704 **/
1705static irqreturn_t ixgbe_intr(int irq, void *data)
1706{
1707 struct net_device *netdev = data;
1708 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1709 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 1710 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 1711 u32 eicr;
1712
54037505
DS		 1713 /*
1714 * Workaround for silicon errata. Mask the interrupts
1715 * before the read of EICR.
1716 */
1717 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1718
021230d4
AV		 1719 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1720 * therefore no explict interrupt disable is necessary */
1721 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1722 if (!eicr) {
1723 /* shared interrupt alert!
1724 * make sure interrupts are enabled because the read will
1725 * have disabled interrupts due to EIAM */
1726 ixgbe_irq_enable(adapter);
9a799d71 1727 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1728 }
9a799d71 1729
cf8280ee
JB		 1730 if (eicr & IXGBE_EICR_LSC)
1731 ixgbe_check_lsc(adapter);
021230d4 1732
e8e26350
PW		 1733 if (hw->mac.type == ixgbe_mac_82599EB)
1734 ixgbe_check_sfp_event(adapter, eicr);
1735
0befdb3e
JB		 1736 ixgbe_check_fan_failure(adapter, eicr);
1737
7a921c93 1738 if (napi_schedule_prep(&(q_vector->napi))) {
f494e8fa
AV		 1739 adapter->tx_ring[0].total_packets = 0;
1740 adapter->tx_ring[0].total_bytes = 0;
1741 adapter->rx_ring[0].total_packets = 0;
1742 adapter->rx_ring[0].total_bytes = 0;
021230d4 1743 /* would disable interrupts here but EIAM disabled it */
7a921c93 1744 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 1745 }
1746
1747 return IRQ_HANDLED;
1748}
1749
021230d4
AV		 1750static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1751{
1752 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1753
1754 for (i = 0; i < q_vectors; i++) {
7a921c93 1755 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 1756 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1757 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1758 q_vector->rxr_count = 0;
1759 q_vector->txr_count = 0;
1760 }
1761}
1762
9a799d71
AK		 1763/**
1764 * ixgbe_request_irq - initialize interrupts
1765 * @adapter: board private structure
1766 *
1767 * Attempts to configure interrupts using the best available
1768 * capabilities of the hardware and kernel.
1769 **/
021230d4 1770static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1771{
1772 struct net_device *netdev = adapter->netdev;
021230d4 1773 int err;
9a799d71 1774
021230d4
AV		 1775 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1776 err = ixgbe_request_msix_irqs(adapter);
1777 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1778 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
b4617240 1779 netdev->name, netdev);
021230d4
AV		 1780 } else {
1781 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
b4617240 1782 netdev->name, netdev);
9a799d71
AK		 1783 }
1784
9a799d71
AK		 1785 if (err)
1786 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1787
9a799d71
AK		 1788 return err;
1789}
1790
1791static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1792{
1793 struct net_device *netdev = adapter->netdev;
1794
1795 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1796 int i, q_vectors;
9a799d71 1797
021230d4
AV		 1798 q_vectors = adapter->num_msix_vectors;
1799
1800 i = q_vectors - 1;
9a799d71 1801 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1802
021230d4
AV		 1803 i--;
1804 for (; i >= 0; i--) {
1805 free_irq(adapter->msix_entries[i].vector,
7a921c93 1806 adapter->q_vector[i]);
021230d4
AV		 1807 }
1808
1809 ixgbe_reset_q_vectors(adapter);
1810 } else {
1811 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1812 }
1813}
1814
22d5a71b
JB		 1815/**
1816 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1817 * @adapter: board private structure
1818 **/
1819static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1820{
835462fc
NS		 1821 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1822 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1823 } else {
1824 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1825 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 1826 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
22d5a71b
JB		 1827 }
1828 IXGBE_WRITE_FLUSH(&adapter->hw);
1829 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1830 int i;
1831 for (i = 0; i < adapter->num_msix_vectors; i++)
1832 synchronize_irq(adapter->msix_entries[i].vector);
1833 } else {
1834 synchronize_irq(adapter->pdev->irq);
1835 }
1836}
1837
9a799d71
AK		 1838/**
1839 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1840 *
1841 **/
1842static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1843{
9a799d71
AK		 1844 struct ixgbe_hw *hw = &adapter->hw;
1845
021230d4 1846 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
30efa5a3 1847 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
9a799d71 1848
e8e26350
PW		 1849 ixgbe_set_ivar(adapter, 0, 0, 0);
1850 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 1851
1852 map_vector_to_rxq(adapter, 0, 0);
1853 map_vector_to_txq(adapter, 0, 0);
1854
1855 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1856}
1857
1858/**
3a581073 1859 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1860 * @adapter: board private structure
1861 *
1862 * Configure the Tx unit of the MAC after a reset.
1863 **/
1864static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1865{
12207e49 1866 u64 tdba;
9a799d71 1867 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1868 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1869
1870 /* Setup the HW Tx Head and Tail descriptor pointers */
1871 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1872 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1873 j = ring->reg_idx;
1874 tdba = ring->dma;
1875 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1876 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 1877 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 1878 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1879 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1880 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1881 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1882 adapter->tx_ring[i].head = IXGBE_TDH(j);
1883 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1884 /* Disable Tx Head Writeback RO bit, since this hoses
1885 * bookkeeping if things aren't delivered in order.
1886 */
e01c31a5 1887 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1888 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1889 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1890 }
e8e26350
PW		 1891 if (hw->mac.type == ixgbe_mac_82599EB) {
1892 /* We enable 8 traffic classes, DCB only */
1893 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1894 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1895 IXGBE_MTQC_8TC_8TQ));
1896 }
9a799d71
AK		 1897}
1898
e8e26350 1899#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 1900
a6616b42
YZ		 1901static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
1902 struct ixgbe_ring *rx_ring)
cc41ac7c 1903{
cc41ac7c 1904 u32 srrctl;
a6616b42 1905 int index;
0cefafad 1906 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 1907
a6616b42
YZ		 1908 index = rx_ring->reg_idx;
1909 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1910 unsigned long mask;
0cefafad 1911 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 1912 index = index & mask;
cc41ac7c 1913 }
cc41ac7c
JB		 1914 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1915
1916 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1917 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1918
afafd5b0
AD		 1919 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1920 IXGBE_SRRCTL_BSIZEHDR_MASK;
1921
cc41ac7c 1922 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
afafd5b0
AD		 1923#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1924 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1925#else
1926 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1927#endif
cc41ac7c 1928 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 1929 } else {
afafd5b0
AD		 1930 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1931 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 1932 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 1933 }
e8e26350 1934
cc41ac7c
JB		 1935 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1936}
9a799d71 1937
0cefafad
JB		 1938static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1939{
1940 u32 mrqc = 0;
1941 int mask;
1942
1943 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1944 return mrqc;
1945
1946 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1947#ifdef CONFIG_IXGBE_DCB
1948 | IXGBE_FLAG_DCB_ENABLED
1949#endif
1950 );
1951
1952 switch (mask) {
1953 case (IXGBE_FLAG_RSS_ENABLED):
1954 mrqc = IXGBE_MRQC_RSSEN;
1955 break;
1956#ifdef CONFIG_IXGBE_DCB
1957 case (IXGBE_FLAG_DCB_ENABLED):
1958 mrqc = IXGBE_MRQC_RT8TCEN;
1959 break;
1960#endif /* CONFIG_IXGBE_DCB */
1961 default:
1962 break;
1963 }
1964
1965 return mrqc;
1966}
1967
9a799d71 1968/**
3a581073 1969 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1970 * @adapter: board private structure
1971 *
1972 * Configure the Rx unit of the MAC after a reset.
1973 **/
1974static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1975{
1976 u64 rdba;
1977 struct ixgbe_hw *hw = &adapter->hw;
a6616b42 1978 struct ixgbe_ring *rx_ring;
9a799d71
AK		 1979 struct net_device *netdev = adapter->netdev;
1980 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1981 int i, j;
9a799d71 1982 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1983 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1984 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1985 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1986 u32 fctrl, hlreg0;
509ee935 1987 u32 reta = 0, mrqc = 0;
cc41ac7c 1988 u32 rdrxctl;
f8212f97 1989 u32 rscctrl;
7c6e0a43 1990 int rx_buf_len;
9a799d71
AK		 1991
1992 /* Decide whether to use packet split mode or not */
762f4c57 1993 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71 1994
eacd73f7
YZ		 1995#ifdef IXGBE_FCOE
1996 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
1997 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
1998#endif /* IXGBE_FCOE */
1999
9a799d71
AK		 2000 /* Set the RX buffer length according to the mode */
2001 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2002 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 2003 if (hw->mac.type == ixgbe_mac_82599EB) {
2004 /* PSRTYPE must be initialized in 82599 */
2005 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2006 IXGBE_PSRTYPE_UDPHDR |
2007 IXGBE_PSRTYPE_IPV4HDR |
dfa12f05
YZ		 2008 IXGBE_PSRTYPE_IPV6HDR |
2009 IXGBE_PSRTYPE_L2HDR;
e8e26350
PW		 2010 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2011 }
9a799d71 2012 } else {
0c19d6af 2013 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2014 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2015 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2016 else
7c6e0a43 2017 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 2018 }
2019
2020 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2021 fctrl |= IXGBE_FCTRL_BAM;
021230d4 2022 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 2023 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 2024 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2025
2026 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2027 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2028 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2029 else
2030 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
63f39bd1
YZ		 2031#ifdef IXGBE_FCOE
2032 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2033 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2034#endif
9a799d71
AK		 2035 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2036
9a799d71
AK		 2037 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2038 /* disable receives while setting up the descriptors */
2039 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2040 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2041
0cefafad
JB		 2042 /*
2043 * Setup the HW Rx Head and Tail Descriptor Pointers and
2044 * the Base and Length of the Rx Descriptor Ring
2045 */
9a799d71 2046 for (i = 0; i < adapter->num_rx_queues; i++) {
a6616b42
YZ		 2047 rx_ring = &adapter->rx_ring[i];
2048 rdba = rx_ring->dma;
2049 j = rx_ring->reg_idx;
284901a9 2050 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 2051 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2052 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2053 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2054 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
a6616b42
YZ		 2055 rx_ring->head = IXGBE_RDH(j);
2056 rx_ring->tail = IXGBE_RDT(j);
2057 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2058
63f39bd1
YZ		 2059#ifdef IXGBE_FCOE
2060 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
2061 struct ixgbe_ring_feature *f;
2062 f = &adapter->ring_feature[RING_F_FCOE];
2063 if ((rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
2064 (i >= f->mask) && (i < f->mask + f->indices))
a6616b42 2065 rx_ring->rx_buf_len =
63f39bd1
YZ		 2066 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2067 }
2068
2069#endif /* IXGBE_FCOE */
a6616b42 2070 ixgbe_configure_srrctl(adapter, rx_ring);
9a799d71
AK		 2071 }
2072
e8e26350
PW		 2073 if (hw->mac.type == ixgbe_mac_82598EB) {
2074 /*
2075 * For VMDq support of different descriptor types or
2076 * buffer sizes through the use of multiple SRRCTL
2077 * registers, RDRXCTL.MVMEN must be set to 1
2078 *
2079 * also, the manual doesn't mention it clearly but DCA hints
2080 * will only use queue 0's tags unless this bit is set. Side
2081 * effects of setting this bit are only that SRRCTL must be
2082 * fully programmed [0..15]
2083 */
2a41ff81
JB		 2084 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2085 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2086 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 2087 }
177db6ff 2088
e8e26350 2089 /* Program MRQC for the distribution of queues */
0cefafad 2090 mrqc = ixgbe_setup_mrqc(adapter);
e8e26350 2091
021230d4 2092 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 2093 /* Fill out redirection table */
021230d4
AV		 2094 for (i = 0, j = 0; i < 128; i++, j++) {
2095 if (j == adapter->ring_feature[RING_F_RSS].indices)
2096 j = 0;
2097 /* reta = 4-byte sliding window of
2098 * 0x00..(indices-1)(indices-1)00..etc. */
2099 reta = (reta << 8) | (j * 0x11);
2100 if ((i & 3) == 3)
2101 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 2102 }
2103
2104 /* Fill out hash function seeds */
2105 for (i = 0; i < 10; i++)
7c6e0a43 2106 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 2107
2a41ff81
JB		 2108 if (hw->mac.type == ixgbe_mac_82598EB)
2109 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 2110 /* Perform hash on these packet types */
2a41ff81
JB		 2111 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2112 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2113 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2114 | IXGBE_MRQC_RSS_FIELD_IPV6
2115 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2116 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 2117 }
2a41ff81 2118 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 2119
021230d4
AV		 2120 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2121
2122 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2123 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2124 /* Disable indicating checksum in descriptor, enables
2125 * RSS hash */
9a799d71 2126 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 2127 }
021230d4
AV		 2128 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2129 /* Enable IPv4 payload checksum for UDP fragments
2130 * if PCSD is not set */
2131 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2132 }
2133
2134 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 2135
2136 if (hw->mac.type == ixgbe_mac_82599EB) {
2137 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2138 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 2139 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 2140 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2141 }
f8212f97 2142
0c19d6af 2143 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97
AD		 2144 /* Enable 82599 HW-RSC */
2145 for (i = 0; i < adapter->num_rx_queues; i++) {
2146 j = adapter->rx_ring[i].reg_idx;
2147 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2148 rscctrl |= IXGBE_RSCCTL_RSCEN;
2149 /*
e76678dd
AD		 2150 * we must limit the number of descriptors so that the
2151 * total size of max desc * buf_len is not greater
2152 * than 65535
f8212f97 2153 */
e76678dd
AD		 2154 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2155#if (MAX_SKB_FRAGS > 16)
2156 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2157#elif (MAX_SKB_FRAGS > 8)
f8212f97 2158 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
e76678dd
AD		 2159#elif (MAX_SKB_FRAGS > 4)
2160 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
f8212f97 2161#else
e76678dd 2162 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
f8212f97 2163#endif
e76678dd
AD		 2164 } else {
2165 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2166 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2167 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2168 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2169 else
2170 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2171 }
f8212f97
AD		 2172 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2173 }
2174 /* Disable RSC for ACK packets */
2175 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2176 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2177 }
9a799d71
AK		 2178}
2179
068c89b0
DS		 2180static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2181{
2182 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2183 struct ixgbe_hw *hw = &adapter->hw;
2184
2185 /* add VID to filter table */
2186 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2187}
2188
2189static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2190{
2191 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2192 struct ixgbe_hw *hw = &adapter->hw;
2193
2194 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2195 ixgbe_irq_disable(adapter);
2196
2197 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2198
2199 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2200 ixgbe_irq_enable(adapter);
2201
2202 /* remove VID from filter table */
2203 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2204}
2205
9a799d71 2206static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2207 struct vlan_group *grp)
9a799d71
AK		 2208{
2209 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2210 u32 ctrl;
e8e26350 2211 int i, j;
9a799d71 2212
d4f80882
AV		 2213 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2214 ixgbe_irq_disable(adapter);
9a799d71
AK		 2215 adapter->vlgrp = grp;
2216
2f90b865
AD		 2217 /*
2218 * For a DCB driver, always enable VLAN tag stripping so we can
2219 * still receive traffic from a DCB-enabled host even if we're
2220 * not in DCB mode.
2221 */
2222 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
e8e26350
PW		 2223 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2224 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2225 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2226 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2227 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2228 ctrl |= IXGBE_VLNCTRL_VFE;
9a799d71
AK		 2229 /* enable VLAN tag insert/strip */
2230 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
9a799d71
AK		 2231 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2232 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
e8e26350
PW		 2233 for (i = 0; i < adapter->num_rx_queues; i++) {
2234 j = adapter->rx_ring[i].reg_idx;
2235 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2236 ctrl |= IXGBE_RXDCTL_VME;
2237 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2238 }
9a799d71 2239 }
e8e26350 2240 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2241
d4f80882
AV		 2242 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2243 ixgbe_irq_enable(adapter);
9a799d71
AK		 2244}
2245
9a799d71
AK		 2246static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2247{
2248 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2249
2250 if (adapter->vlgrp) {
2251 u16 vid;
2252 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2253 if (!vlan_group_get_device(adapter->vlgrp, vid))
2254 continue;
2255 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2256 }
2257 }
2258}
2259
2c5645cf
CL		 2260static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2261{
2262 struct dev_mc_list *mc_ptr;
2263 u8 *addr = *mc_addr_ptr;
2264 *vmdq = 0;
2265
2266 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2267 if (mc_ptr->next)
2268 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2269 else
2270 *mc_addr_ptr = NULL;
2271
2272 return addr;
2273}
2274
9a799d71 2275/**
2c5645cf 2276 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2277 * @netdev: network interface device structure
2278 *
2c5645cf
CL		 2279 * The set_rx_method entry point is called whenever the unicast/multicast
2280 * address list or the network interface flags are updated. This routine is
2281 * responsible for configuring the hardware for proper unicast, multicast and
2282 * promiscuous mode.
9a799d71 2283 **/
2c5645cf 2284static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2285{
2286 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2287 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 2288 u32 fctrl, vlnctrl;
2c5645cf
CL		 2289 u8 *addr_list = NULL;
2290 int addr_count = 0;
9a799d71
AK		 2291
2292 /* Check for Promiscuous and All Multicast modes */
2293
2294 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 2295 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 2296
2297 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2298 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2299 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 2300 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 2301 } else {
746b9f02
PM		 2302 if (netdev->flags & IFF_ALLMULTI) {
2303 fctrl |= IXGBE_FCTRL_MPE;
2304 fctrl &= ~IXGBE_FCTRL_UPE;
2305 } else {
2306 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2307 }
3d01625a 2308 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 2309 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2310 }
2311
2312 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 2313 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 2314
2c5645cf 2315 /* reprogram secondary unicast list */
31278e71 2316 hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
9a799d71 2317
2c5645cf
CL		 2318 /* reprogram multicast list */
2319 addr_count = netdev->mc_count;
2320 if (addr_count)
2321 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 2322 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2323 ixgbe_addr_list_itr);
9a799d71
AK		 2324}
2325
021230d4
AV		 2326static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2327{
2328 int q_idx;
2329 struct ixgbe_q_vector *q_vector;
2330 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2331
2332 /* legacy and MSI only use one vector */
2333 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2334 q_vectors = 1;
2335
2336 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2337 struct napi_struct *napi;
7a921c93 2338 q_vector = adapter->q_vector[q_idx];
f0848276 2339 napi = &q_vector->napi;
91281fd3
AD		 2340 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2341 if (!q_vector->rxr_count || !q_vector->txr_count) {
2342 if (q_vector->txr_count == 1)
2343 napi->poll = &ixgbe_clean_txonly;
2344 else if (q_vector->rxr_count == 1)
2345 napi->poll = &ixgbe_clean_rxonly;
2346 }
2347 }
f0848276
JB		 2348
2349 napi_enable(napi);
021230d4
AV		 2350 }
2351}
2352
2353static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2354{
2355 int q_idx;
2356 struct ixgbe_q_vector *q_vector;
2357 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2358
2359 /* legacy and MSI only use one vector */
2360 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2361 q_vectors = 1;
2362
2363 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 2364 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2365 napi_disable(&q_vector->napi);
2366 }
2367}
2368
7a6b6f51 2369#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2370/*
2371 * ixgbe_configure_dcb - Configure DCB hardware
2372 * @adapter: ixgbe adapter struct
2373 *
2374 * This is called by the driver on open to configure the DCB hardware.
2375 * This is also called by the gennetlink interface when reconfiguring
2376 * the DCB state.
2377 */
2378static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2379{
2380 struct ixgbe_hw *hw = &adapter->hw;
2381 u32 txdctl, vlnctrl;
2382 int i, j;
2383
2384 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2385 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2386 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2387
2388 /* reconfigure the hardware */
2389 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2390
2391 for (i = 0; i < adapter->num_tx_queues; i++) {
2392 j = adapter->tx_ring[i].reg_idx;
2393 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2394 /* PThresh workaround for Tx hang with DFP enabled. */
2395 txdctl |= 32;
2396 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2397 }
2398 /* Enable VLAN tag insert/strip */
2399 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
e8e26350
PW		 2400 if (hw->mac.type == ixgbe_mac_82598EB) {
2401 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2402 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2403 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2404 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2405 vlnctrl |= IXGBE_VLNCTRL_VFE;
2406 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2407 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2408 for (i = 0; i < adapter->num_rx_queues; i++) {
2409 j = adapter->rx_ring[i].reg_idx;
2410 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2411 vlnctrl |= IXGBE_RXDCTL_VME;
2412 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2413 }
2414 }
2f90b865
AD		 2415 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2416}
2417
2418#endif
9a799d71
AK		 2419static void ixgbe_configure(struct ixgbe_adapter *adapter)
2420{
2421 struct net_device *netdev = adapter->netdev;
c4cf55e5 2422 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 2423 int i;
2424
2c5645cf 2425 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2426
2427 ixgbe_restore_vlan(adapter);
7a6b6f51 2428#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2429 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2430 netif_set_gso_max_size(netdev, 32768);
2431 ixgbe_configure_dcb(adapter);
2432 } else {
2433 netif_set_gso_max_size(netdev, 65536);
2434 }
2435#else
2436 netif_set_gso_max_size(netdev, 65536);
2437#endif
9a799d71 2438
eacd73f7
YZ		 2439#ifdef IXGBE_FCOE
2440 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2441 ixgbe_configure_fcoe(adapter);
2442
2443#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 2444 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2445 for (i = 0; i < adapter->num_tx_queues; i++)
2446 adapter->tx_ring[i].atr_sample_rate =
2447 adapter->atr_sample_rate;
2448 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2449 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2450 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2451 }
2452
9a799d71
AK		 2453 ixgbe_configure_tx(adapter);
2454 ixgbe_configure_rx(adapter);
2455 for (i = 0; i < adapter->num_rx_queues; i++)
2456 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 2457 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 2458}
2459
e8e26350
PW		 2460static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2461{
2462 switch (hw->phy.type) {
2463 case ixgbe_phy_sfp_avago:
2464 case ixgbe_phy_sfp_ftl:
2465 case ixgbe_phy_sfp_intel:
2466 case ixgbe_phy_sfp_unknown:
2467 case ixgbe_phy_tw_tyco:
2468 case ixgbe_phy_tw_unknown:
2469 return true;
2470 default:
2471 return false;
2472 }
2473}
2474
0ecc061d 2475/**
e8e26350
PW		 2476 * ixgbe_sfp_link_config - set up SFP+ link
2477 * @adapter: pointer to private adapter struct
2478 **/
2479static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2480{
2481 struct ixgbe_hw *hw = &adapter->hw;
2482
2483 if (hw->phy.multispeed_fiber) {
2484 /*
2485 * In multispeed fiber setups, the device may not have
2486 * had a physical connection when the driver loaded.
2487 * If that's the case, the initial link configuration
2488 * couldn't get the MAC into 10G or 1G mode, so we'll
2489 * never have a link status change interrupt fire.
2490 * We need to try and force an autonegotiation
2491 * session, then bring up link.
2492 */
2493 hw->mac.ops.setup_sfp(hw);
2494 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2495 schedule_work(&adapter->multispeed_fiber_task);
2496 } else {
2497 /*
2498 * Direct Attach Cu and non-multispeed fiber modules
2499 * still need to be configured properly prior to
2500 * attempting link.
2501 */
2502 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2503 schedule_work(&adapter->sfp_config_module_task);
2504 }
2505}
2506
2507/**
2508 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2509 * @hw: pointer to private hardware struct
2510 *
2511 * Returns 0 on success, negative on failure
2512 **/
e8e26350 2513static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2514{
2515 u32 autoneg;
2516 bool link_up = false;
2517 u32 ret = IXGBE_ERR_LINK_SETUP;
2518
2519 if (hw->mac.ops.check_link)
2520 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2521
2522 if (ret)
2523 goto link_cfg_out;
2524
2525 if (hw->mac.ops.get_link_capabilities)
2526 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2527 &hw->mac.autoneg);
2528 if (ret)
2529 goto link_cfg_out;
2530
2531 if (hw->mac.ops.setup_link_speed)
2532 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
0ecc061d
PWJ		 2533link_cfg_out:
2534 return ret;
2535}
2536
e8e26350
PW		 2537#define IXGBE_MAX_RX_DESC_POLL 10
2538static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2539 int rxr)
2540{
2541 int j = adapter->rx_ring[rxr].reg_idx;
2542 int k;
2543
2544 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2545 if (IXGBE_READ_REG(&adapter->hw,
2546 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2547 break;
2548 else
2549 msleep(1);
2550 }
2551 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2552 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2553 "not set within the polling period\n", rxr);
2554 }
2555 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2556 (adapter->rx_ring[rxr].count - 1));
2557}
2558
9a799d71
AK		 2559static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2560{
2561 struct net_device *netdev = adapter->netdev;
9a799d71 2562 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2563 int i, j = 0;
e8e26350 2564 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2565 int err;
9a799d71 2566 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2567 u32 txdctl, rxdctl, mhadd;
e8e26350 2568 u32 dmatxctl;
021230d4 2569 u32 gpie;
9a799d71 2570
5eba3699
AV		 2571 ixgbe_get_hw_control(adapter);
2572
021230d4
AV		 2573 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2574 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2575 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2576 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2577 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2578 } else {
2579 /* MSI only */
021230d4 2580 gpie = 0;
9a799d71 2581 }
021230d4
AV		 2582 /* XXX: to interrupt immediately for EICS writes, enable this */
2583 /* gpie |= IXGBE_GPIE_EIMEN; */
2584 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2585 }
2586
021230d4
AV		 2587 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2588 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2589 * specifically only auto mask tx and rx interrupts */
2590 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2591 }
9a799d71 2592
0befdb3e
JB		 2593 /* Enable fan failure interrupt if media type is copper */
2594 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2595 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2596 gpie |= IXGBE_SDP1_GPIEN;
2597 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2598 }
2599
e8e26350
PW		 2600 if (hw->mac.type == ixgbe_mac_82599EB) {
2601 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2602 gpie |= IXGBE_SDP1_GPIEN;
2603 gpie |= IXGBE_SDP2_GPIEN;
2604 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2605 }
2606
63f39bd1
YZ		 2607#ifdef IXGBE_FCOE
2608 /* adjust max frame to be able to do baby jumbo for FCoE */
2609 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2610 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2611 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2612
2613#endif /* IXGBE_FCOE */
021230d4 2614 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2615 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2616 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2617 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2618
2619 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2620 }
2621
2622 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 2623 j = adapter->tx_ring[i].reg_idx;
2624 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2625 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2626 txdctl |= (8 << 16);
e8e26350
PW		 2627 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2628 }
2629
2630 if (hw->mac.type == ixgbe_mac_82599EB) {
2631 /* DMATXCTL.EN must be set after all Tx queue config is done */
2632 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2633 dmatxctl |= IXGBE_DMATXCTL_TE;
2634 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2635 }
2636 for (i = 0; i < adapter->num_tx_queues; i++) {
2637 j = adapter->tx_ring[i].reg_idx;
2638 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2639 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2640 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 2641 }
2642
e8e26350 2643 for (i = 0; i < num_rx_rings; i++) {
021230d4
AV		 2644 j = adapter->rx_ring[i].reg_idx;
2645 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2646 /* enable PTHRESH=32 descriptors (half the internal cache)
2647 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2648 * this also removes a pesky rx_no_buffer_count increment */
2649 rxdctl |= 0x0020;
9a799d71 2650 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2651 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2652 if (hw->mac.type == ixgbe_mac_82599EB)
2653 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2654 }
2655 /* enable all receives */
2656 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2657 if (hw->mac.type == ixgbe_mac_82598EB)
2658 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2659 else
2660 rxdctl |= IXGBE_RXCTRL_RXEN;
2661 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2662
2663 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2664 ixgbe_configure_msix(adapter);
2665 else
2666 ixgbe_configure_msi_and_legacy(adapter);
2667
2668 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2669 ixgbe_napi_enable_all(adapter);
2670
2671 /* clear any pending interrupts, may auto mask */
2672 IXGBE_READ_REG(hw, IXGBE_EICR);
2673
9a799d71
AK		 2674 ixgbe_irq_enable(adapter);
2675
bf069c97
DS		 2676 /*
2677 * If this adapter has a fan, check to see if we had a failure
2678 * before we enabled the interrupt.
2679 */
2680 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2681 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2682 if (esdp & IXGBE_ESDP_SDP1)
2683 DPRINTK(DRV, CRIT,
2684 "Fan has stopped, replace the adapter\n");
2685 }
2686
e8e26350
PW		 2687 /*
2688 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 2689 * arrived before interrupts were enabled but after probe. Such
2690 * devices wouldn't have their type identified yet. We need to
2691 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 2692 * If we're not hot-pluggable SFP+, we just need to configure link
2693 * and bring it up.
2694 */
19343de2
DS		 2695 if (hw->phy.type == ixgbe_phy_unknown) {
2696 err = hw->phy.ops.identify(hw);
2697 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 2698 /*
2699 * Take the device down and schedule the sfp tasklet
2700 * which will unregister_netdev and log it.
2701 */
19343de2 2702 ixgbe_down(adapter);
5da43c1a 2703 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 2704 return err;
2705 }
e8e26350
PW		 2706 }
2707
2708 if (ixgbe_is_sfp(hw)) {
2709 ixgbe_sfp_link_config(adapter);
2710 } else {
2711 err = ixgbe_non_sfp_link_config(hw);
2712 if (err)
2713 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2714 }
0ecc061d 2715
c4cf55e5
PWJ		 2716 for (i = 0; i < adapter->num_tx_queues; i++)
2717 set_bit(__IXGBE_FDIR_INIT_DONE,
2718 &(adapter->tx_ring[i].reinit_state));
2719
1da100bb
PWJ		 2720 /* enable transmits */
2721 netif_tx_start_all_queues(netdev);
2722
9a799d71
AK		 2723 /* bring the link up in the watchdog, this could race with our first
2724 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 2725 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2726 adapter->link_check_timeout = jiffies;
9a799d71
AK		 2727 mod_timer(&adapter->watchdog_timer, jiffies);
2728 return 0;
2729}
2730
d4f80882
AV		 2731void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2732{
2733 WARN_ON(in_interrupt());
2734 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2735 msleep(1);
2736 ixgbe_down(adapter);
2737 ixgbe_up(adapter);
2738 clear_bit(__IXGBE_RESETTING, &adapter->state);
2739}
2740
9a799d71
AK		 2741int ixgbe_up(struct ixgbe_adapter *adapter)
2742{
2743 /* hardware has been reset, we need to reload some things */
2744 ixgbe_configure(adapter);
2745
2746 return ixgbe_up_complete(adapter);
2747}
2748
2749void ixgbe_reset(struct ixgbe_adapter *adapter)
2750{
c44ade9e 2751 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 2752 int err;
2753
2754 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 2755 switch (err) {
2756 case 0:
2757 case IXGBE_ERR_SFP_NOT_PRESENT:
2758 break;
2759 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2760 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2761 break;
794caeb2
PWJ		 2762 case IXGBE_ERR_EEPROM_VERSION:
2763 /* We are running on a pre-production device, log a warning */
2764 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2765 "adapter/LOM. Please be aware there may be issues "
2766 "associated with your hardware. If you are "
2767 "experiencing problems please contact your Intel or "
2768 "hardware representative who provided you with this "
2769 "hardware.\n");
2770 break;
da4dd0f7
PWJ		 2771 default:
2772 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2773 }
9a799d71
AK		 2774
2775 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2776 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2777}
2778
9a799d71
AK		 2779/**
2780 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2781 * @adapter: board private structure
2782 * @rx_ring: ring to free buffers from
2783 **/
2784static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2785 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2786{
2787 struct pci_dev *pdev = adapter->pdev;
2788 unsigned long size;
2789 unsigned int i;
2790
2791 /* Free all the Rx ring sk_buffs */
2792
2793 for (i = 0; i < rx_ring->count; i++) {
2794 struct ixgbe_rx_buffer *rx_buffer_info;
2795
2796 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2797 if (rx_buffer_info->dma) {
2798 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2799 rx_ring->rx_buf_len,
2800 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2801 rx_buffer_info->dma = 0;
2802 }
2803 if (rx_buffer_info->skb) {
f8212f97 2804 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 2805 rx_buffer_info->skb = NULL;
f8212f97
AD		 2806 do {
2807 struct sk_buff *this = skb;
2808 skb = skb->prev;
2809 dev_kfree_skb(this);
2810 } while (skb);
9a799d71
AK		 2811 }
2812 if (!rx_buffer_info->page)
2813 continue;
4f57ca6e
JB		 2814 if (rx_buffer_info->page_dma) {
2815 pci_unmap_page(pdev, rx_buffer_info->page_dma,
2816 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2817 rx_buffer_info->page_dma = 0;
2818 }
9a799d71
AK		 2819 put_page(rx_buffer_info->page);
2820 rx_buffer_info->page = NULL;
762f4c57 2821 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2822 }
2823
2824 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2825 memset(rx_ring->rx_buffer_info, 0, size);
2826
2827 /* Zero out the descriptor ring */
2828 memset(rx_ring->desc, 0, rx_ring->size);
2829
2830 rx_ring->next_to_clean = 0;
2831 rx_ring->next_to_use = 0;
2832
9891ca7c
JB		 2833 if (rx_ring->head)
2834 writel(0, adapter->hw.hw_addr + rx_ring->head);
2835 if (rx_ring->tail)
2836 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 2837}
2838
2839/**
2840 * ixgbe_clean_tx_ring - Free Tx Buffers
2841 * @adapter: board private structure
2842 * @tx_ring: ring to be cleaned
2843 **/
2844static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2845 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2846{
2847 struct ixgbe_tx_buffer *tx_buffer_info;
2848 unsigned long size;
2849 unsigned int i;
2850
2851 /* Free all the Tx ring sk_buffs */
2852
2853 for (i = 0; i < tx_ring->count; i++) {
2854 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2855 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2856 }
2857
2858 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2859 memset(tx_ring->tx_buffer_info, 0, size);
2860
2861 /* Zero out the descriptor ring */
2862 memset(tx_ring->desc, 0, tx_ring->size);
2863
2864 tx_ring->next_to_use = 0;
2865 tx_ring->next_to_clean = 0;
2866
9891ca7c
JB		 2867 if (tx_ring->head)
2868 writel(0, adapter->hw.hw_addr + tx_ring->head);
2869 if (tx_ring->tail)
2870 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 2871}
2872
2873/**
021230d4 2874 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2875 * @adapter: board private structure
2876 **/
021230d4 2877static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2878{
2879 int i;
2880
021230d4
AV		 2881 for (i = 0; i < adapter->num_rx_queues; i++)
2882 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2883}
2884
2885/**
021230d4 2886 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2887 * @adapter: board private structure
2888 **/
021230d4 2889static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2890{
2891 int i;
2892
021230d4
AV		 2893 for (i = 0; i < adapter->num_tx_queues; i++)
2894 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2895}
2896
2897void ixgbe_down(struct ixgbe_adapter *adapter)
2898{
2899 struct net_device *netdev = adapter->netdev;
7f821875 2900 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2901 u32 rxctrl;
7f821875
JB		 2902 u32 txdctl;
2903 int i, j;
9a799d71
AK		 2904
2905 /* signal that we are down to the interrupt handler */
2906 set_bit(__IXGBE_DOWN, &adapter->state);
2907
2908 /* disable receives */
7f821875
JB		 2909 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2910 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 2911
2912 netif_tx_disable(netdev);
2913
7f821875 2914 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 2915 msleep(10);
2916
7f821875
JB		 2917 netif_tx_stop_all_queues(netdev);
2918
9a799d71
AK		 2919 ixgbe_irq_disable(adapter);
2920
021230d4 2921 ixgbe_napi_disable_all(adapter);
7f821875 2922
9a799d71 2923 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 2924 cancel_work_sync(&adapter->watchdog_task);
9a799d71 2925
c4cf55e5
PWJ		 2926 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2927 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2928 cancel_work_sync(&adapter->fdir_reinit_task);
2929
7f821875
JB		 2930 /* disable transmits in the hardware now that interrupts are off */
2931 for (i = 0; i < adapter->num_tx_queues; i++) {
2932 j = adapter->tx_ring[i].reg_idx;
2933 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2934 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2935 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2936 }
88512539
PW		 2937 /* Disable the Tx DMA engine on 82599 */
2938 if (hw->mac.type == ixgbe_mac_82599EB)
2939 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2940 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2941 ~IXGBE_DMATXCTL_TE));
7f821875 2942
9a799d71 2943 netif_carrier_off(netdev);
9a799d71 2944
6f4a0e45
PL		 2945 if (!pci_channel_offline(adapter->pdev))
2946 ixgbe_reset(adapter);
9a799d71
AK		 2947 ixgbe_clean_all_tx_rings(adapter);
2948 ixgbe_clean_all_rx_rings(adapter);
2949
5dd2d332 2950#ifdef CONFIG_IXGBE_DCA
96b0e0f6 2951 /* since we reset the hardware DCA settings were cleared */
e35ec126 2952 ixgbe_setup_dca(adapter);
96b0e0f6 2953#endif
9a799d71
AK		 2954}
2955
9a799d71 2956/**
021230d4
AV		 2957 * ixgbe_poll - NAPI Rx polling callback
2958 * @napi: structure for representing this polling device
2959 * @budget: how many packets driver is allowed to clean
2960 *
2961 * This function is used for legacy and MSI, NAPI mode
9a799d71 2962 **/
021230d4 2963static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2964{
9a1a69ad
JB		 2965 struct ixgbe_q_vector *q_vector =
2966 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2967 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 2968 int tx_clean_complete, work_done = 0;
9a799d71 2969
5dd2d332 2970#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 2971 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2972 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2973 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2974 }
2975#endif
2976
fe49f04a 2977 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
78b6f4ce 2978 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
9a799d71 2979
9a1a69ad 2980 if (!tx_clean_complete)
d2c7ddd6
DM		 2981 work_done = budget;
2982
53e52c72
DM		 2983 /* If budget not fully consumed, exit the polling mode */
2984 if (work_done < budget) {
288379f0 2985 napi_complete(napi);
509ee935 2986 if (adapter->itr_setting & 1)
f494e8fa 2987 ixgbe_set_itr(adapter);
d4f80882 2988 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 2989 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 2990 }
9a799d71
AK		 2991 return work_done;
2992}
2993
2994/**
2995 * ixgbe_tx_timeout - Respond to a Tx Hang
2996 * @netdev: network interface device structure
2997 **/
2998static void ixgbe_tx_timeout(struct net_device *netdev)
2999{
3000 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3001
3002 /* Do the reset outside of interrupt context */
3003 schedule_work(&adapter->reset_task);
3004}
3005
3006static void ixgbe_reset_task(struct work_struct *work)
3007{
3008 struct ixgbe_adapter *adapter;
3009 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3010
2f90b865
AD		 3011 /* If we're already down or resetting, just bail */
3012 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3013 test_bit(__IXGBE_RESETTING, &adapter->state))
3014 return;
3015
9a799d71
AK		 3016 adapter->tx_timeout_count++;
3017
d4f80882 3018 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3019}
3020
bc97114d
PWJ		 3021#ifdef CONFIG_IXGBE_DCB
3022static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3023{
bc97114d 3024 bool ret = false;
0cefafad 3025 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3026
0cefafad
JB		 3027 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3028 return ret;
3029
3030 f->mask = 0x7 << 3;
3031 adapter->num_rx_queues = f->indices;
3032 adapter->num_tx_queues = f->indices;
3033 ret = true;
2f90b865 3034
bc97114d
PWJ		 3035 return ret;
3036}
3037#endif
3038
4df10466
JB		 3039/**
3040 * ixgbe_set_rss_queues: Allocate queues for RSS
3041 * @adapter: board private structure to initialize
3042 *
3043 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3044 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3045 *
3046 **/
bc97114d
PWJ		 3047static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3048{
3049 bool ret = false;
0cefafad 3050 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3051
3052 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3053 f->mask = 0xF;
3054 adapter->num_rx_queues = f->indices;
3055 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3056 ret = true;
3057 } else {
bc97114d 3058 ret = false;
b9804972
JB		 3059 }
3060
bc97114d
PWJ		 3061 return ret;
3062}
3063
c4cf55e5
PWJ		 3064/**
3065 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3066 * @adapter: board private structure to initialize
3067 *
3068 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3069 * to the original CPU that initiated the Tx session. This runs in addition
3070 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3071 * Rx load across CPUs using RSS.
3072 *
3073 **/
3074static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3075{
3076 bool ret = false;
3077 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3078
3079 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3080 f_fdir->mask = 0;
3081
3082 /* Flow Director must have RSS enabled */
3083 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3084 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3085 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3086 adapter->num_tx_queues = f_fdir->indices;
3087 adapter->num_rx_queues = f_fdir->indices;
3088 ret = true;
3089 } else {
3090 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3091 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3092 }
3093 return ret;
3094}
3095
0331a832
YZ		 3096#ifdef IXGBE_FCOE
3097/**
3098 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3099 * @adapter: board private structure to initialize
3100 *
3101 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3102 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3103 * rx queues out of the max number of rx queues, instead, it is used as the
3104 * index of the first rx queue used by FCoE.
3105 *
3106 **/
3107static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3108{
3109 bool ret = false;
3110 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3111
3112 f->indices = min((int)num_online_cpus(), f->indices);
3113 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3114#ifdef CONFIG_IXGBE_DCB
3115 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3116 DPRINTK(PROBE, INFO, "FCOE enabled with DCB \n");
3117 ixgbe_set_dcb_queues(adapter);
3118 }
3119#endif
3120 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3121 DPRINTK(PROBE, INFO, "FCOE enabled with RSS \n");
8faa2a78
YZ		 3122 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3123 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3124 ixgbe_set_fdir_queues(adapter);
3125 else
3126 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 3127 }
3128 /* adding FCoE rx rings to the end */
3129 f->mask = adapter->num_rx_queues;
3130 adapter->num_rx_queues += f->indices;
3131 if (adapter->num_tx_queues == 0)
3132 adapter->num_tx_queues = f->indices;
3133
3134 ret = true;
3135 }
3136
3137 return ret;
3138}
3139
3140#endif /* IXGBE_FCOE */
4df10466
JB		 3141/*
3142 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3143 * @adapter: board private structure to initialize
3144 *
3145 * This is the top level queue allocation routine. The order here is very
3146 * important, starting with the "most" number of features turned on at once,
3147 * and ending with the smallest set of features. This way large combinations
3148 * can be allocated if they're turned on, and smaller combinations are the
3149 * fallthrough conditions.
3150 *
3151 **/
bc97114d
PWJ		 3152static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3153{
0331a832
YZ		 3154#ifdef IXGBE_FCOE
3155 if (ixgbe_set_fcoe_queues(adapter))
3156 goto done;
3157
3158#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3159#ifdef CONFIG_IXGBE_DCB
3160 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 3161 goto done;
bc97114d
PWJ		 3162
3163#endif
c4cf55e5
PWJ		 3164 if (ixgbe_set_fdir_queues(adapter))
3165 goto done;
3166
bc97114d 3167 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 3168 goto done;
3169
3170 /* fallback to base case */
3171 adapter->num_rx_queues = 1;
3172 adapter->num_tx_queues = 1;
3173
3174done:
3175 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3176 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 3177}
3178
021230d4 3179static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 3180 int vectors)
021230d4
AV		 3181{
3182 int err, vector_threshold;
3183
3184 /* We'll want at least 3 (vector_threshold):
3185 * 1) TxQ[0] Cleanup
3186 * 2) RxQ[0] Cleanup
3187 * 3) Other (Link Status Change, etc.)
3188 * 4) TCP Timer (optional)
3189 */
3190 vector_threshold = MIN_MSIX_COUNT;
3191
3192 /* The more we get, the more we will assign to Tx/Rx Cleanup
3193 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3194 * Right now, we simply care about how many we'll get; we'll
3195 * set them up later while requesting irq's.
3196 */
3197 while (vectors >= vector_threshold) {
3198 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 3199 vectors);
021230d4
AV		 3200 if (!err) /* Success in acquiring all requested vectors. */
3201 break;
3202 else if (err < 0)
3203 vectors = 0; /* Nasty failure, quit now */
3204 else /* err == number of vectors we should try again with */
3205 vectors = err;
3206 }
3207
3208 if (vectors < vector_threshold) {
3209 /* Can't allocate enough MSI-X interrupts? Oh well.
3210 * This just means we'll go with either a single MSI
3211 * vector or fall back to legacy interrupts.
3212 */
3213 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3214 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3215 kfree(adapter->msix_entries);
3216 adapter->msix_entries = NULL;
021230d4
AV		 3217 } else {
3218 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 3219 /*
3220 * Adjust for only the vectors we'll use, which is minimum
3221 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3222 * vectors we were allocated.
3223 */
3224 adapter->num_msix_vectors = min(vectors,
3225 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 3226 }
3227}
3228
021230d4 3229/**
bc97114d 3230 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 3231 * @adapter: board private structure to initialize
3232 *
bc97114d
PWJ		 3233 * Cache the descriptor ring offsets for RSS to the assigned rings.
3234 *
021230d4 3235 **/
bc97114d 3236static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 3237{
bc97114d
PWJ		 3238 int i;
3239 bool ret = false;
3240
3241 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3242 for (i = 0; i < adapter->num_rx_queues; i++)
3243 adapter->rx_ring[i].reg_idx = i;
3244 for (i = 0; i < adapter->num_tx_queues; i++)
3245 adapter->tx_ring[i].reg_idx = i;
3246 ret = true;
3247 } else {
3248 ret = false;
3249 }
3250
3251 return ret;
3252}
3253
3254#ifdef CONFIG_IXGBE_DCB
3255/**
3256 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3257 * @adapter: board private structure to initialize
3258 *
3259 * Cache the descriptor ring offsets for DCB to the assigned rings.
3260 *
3261 **/
3262static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3263{
3264 int i;
3265 bool ret = false;
3266 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3267
3268 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3269 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 3270 /* the number of queues is assumed to be symmetric */
3271 for (i = 0; i < dcb_i; i++) {
3272 adapter->rx_ring[i].reg_idx = i << 3;
3273 adapter->tx_ring[i].reg_idx = i << 2;
3274 }
bc97114d 3275 ret = true;
e8e26350 3276 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 3277 if (dcb_i == 8) {
3278 /*
3279 * Tx TC0 starts at: descriptor queue 0
3280 * Tx TC1 starts at: descriptor queue 32
3281 * Tx TC2 starts at: descriptor queue 64
3282 * Tx TC3 starts at: descriptor queue 80
3283 * Tx TC4 starts at: descriptor queue 96
3284 * Tx TC5 starts at: descriptor queue 104
3285 * Tx TC6 starts at: descriptor queue 112
3286 * Tx TC7 starts at: descriptor queue 120
3287 *
3288 * Rx TC0-TC7 are offset by 16 queues each
3289 */
3290 for (i = 0; i < 3; i++) {
3291 adapter->tx_ring[i].reg_idx = i << 5;
3292 adapter->rx_ring[i].reg_idx = i << 4;
3293 }
3294 for ( ; i < 5; i++) {
3295 adapter->tx_ring[i].reg_idx =
3296 ((i + 2) << 4);
3297 adapter->rx_ring[i].reg_idx = i << 4;
3298 }
3299 for ( ; i < dcb_i; i++) {
3300 adapter->tx_ring[i].reg_idx =
3301 ((i + 8) << 3);
3302 adapter->rx_ring[i].reg_idx = i << 4;
3303 }
3304
3305 ret = true;
3306 } else if (dcb_i == 4) {
3307 /*
3308 * Tx TC0 starts at: descriptor queue 0
3309 * Tx TC1 starts at: descriptor queue 64
3310 * Tx TC2 starts at: descriptor queue 96
3311 * Tx TC3 starts at: descriptor queue 112
3312 *
3313 * Rx TC0-TC3 are offset by 32 queues each
3314 */
3315 adapter->tx_ring[0].reg_idx = 0;
3316 adapter->tx_ring[1].reg_idx = 64;
3317 adapter->tx_ring[2].reg_idx = 96;
3318 adapter->tx_ring[3].reg_idx = 112;
3319 for (i = 0 ; i < dcb_i; i++)
3320 adapter->rx_ring[i].reg_idx = i << 5;
3321
3322 ret = true;
3323 } else {
3324 ret = false;
e8e26350 3325 }
bc97114d
PWJ		 3326 } else {
3327 ret = false;
021230d4 3328 }
bc97114d
PWJ		 3329 } else {
3330 ret = false;
021230d4 3331 }
bc97114d
PWJ		 3332
3333 return ret;
3334}
3335#endif
3336
c4cf55e5
PWJ		 3337/**
3338 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3339 * @adapter: board private structure to initialize
3340 *
3341 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3342 *
3343 **/
3344static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3345{
3346 int i;
3347 bool ret = false;
3348
3349 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3350 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3351 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3352 for (i = 0; i < adapter->num_rx_queues; i++)
3353 adapter->rx_ring[i].reg_idx = i;
3354 for (i = 0; i < adapter->num_tx_queues; i++)
3355 adapter->tx_ring[i].reg_idx = i;
3356 ret = true;
3357 }
3358
3359 return ret;
3360}
3361
0331a832
YZ		 3362#ifdef IXGBE_FCOE
3363/**
3364 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3365 * @adapter: board private structure to initialize
3366 *
3367 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3368 *
3369 */
3370static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3371{
3372 int i, fcoe_i = 0;
3373 bool ret = false;
3374 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3375
3376 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3377#ifdef CONFIG_IXGBE_DCB
3378 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3379 ixgbe_cache_ring_dcb(adapter);
3380 fcoe_i = adapter->rx_ring[0].reg_idx + 1;
3381 }
3382#endif /* CONFIG_IXGBE_DCB */
3383 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 3384 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3385 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3386 ixgbe_cache_ring_fdir(adapter);
3387 else
3388 ixgbe_cache_ring_rss(adapter);
3389
0331a832
YZ		 3390 fcoe_i = f->mask;
3391 }
3392 for (i = 0; i < f->indices; i++, fcoe_i++)
3393 adapter->rx_ring[f->mask + i].reg_idx = fcoe_i;
3394 ret = true;
3395 }
3396 return ret;
3397}
3398
3399#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3400/**
3401 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3402 * @adapter: board private structure to initialize
3403 *
3404 * Once we know the feature-set enabled for the device, we'll cache
3405 * the register offset the descriptor ring is assigned to.
3406 *
3407 * Note, the order the various feature calls is important. It must start with
3408 * the "most" features enabled at the same time, then trickle down to the
3409 * least amount of features turned on at once.
3410 **/
3411static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3412{
3413 /* start with default case */
3414 adapter->rx_ring[0].reg_idx = 0;
3415 adapter->tx_ring[0].reg_idx = 0;
3416
0331a832
YZ		 3417#ifdef IXGBE_FCOE
3418 if (ixgbe_cache_ring_fcoe(adapter))
3419 return;
3420
3421#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3422#ifdef CONFIG_IXGBE_DCB
3423 if (ixgbe_cache_ring_dcb(adapter))
3424 return;
3425
3426#endif
c4cf55e5
PWJ		 3427 if (ixgbe_cache_ring_fdir(adapter))
3428 return;
3429
bc97114d
PWJ		 3430 if (ixgbe_cache_ring_rss(adapter))
3431 return;
021230d4
AV		 3432}
3433
9a799d71
AK		 3434/**
3435 * ixgbe_alloc_queues - Allocate memory for all rings
3436 * @adapter: board private structure to initialize
3437 *
3438 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 3439 * number of queues at compile-time. The polling_netdev array is
3440 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 3441 **/
2f90b865 3442static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 3443{
3444 int i;
3445
3446 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 3447 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 3448 if (!adapter->tx_ring)
021230d4 3449 goto err_tx_ring_allocation;
9a799d71
AK		 3450
3451 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 3452 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 3453 if (!adapter->rx_ring)
3454 goto err_rx_ring_allocation;
9a799d71 3455
021230d4 3456 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 3457 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 3458 adapter->tx_ring[i].queue_index = i;
3459 }
b9804972 3460
9a799d71 3461 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 3462 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 3463 adapter->rx_ring[i].queue_index = i;
3464 }
3465
3466 ixgbe_cache_ring_register(adapter);
3467
3468 return 0;
3469
3470err_rx_ring_allocation:
3471 kfree(adapter->tx_ring);
3472err_tx_ring_allocation:
3473 return -ENOMEM;
3474}
3475
3476/**
3477 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3478 * @adapter: board private structure to initialize
3479 *
3480 * Attempt to configure the interrupts using the best available
3481 * capabilities of the hardware and the kernel.
3482 **/
feea6a57 3483static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 3484{
8be0e467 3485 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 3486 int err = 0;
3487 int vector, v_budget;
3488
3489 /*
3490 * It's easy to be greedy for MSI-X vectors, but it really
3491 * doesn't do us much good if we have a lot more vectors
3492 * than CPU's. So let's be conservative and only ask for
3493 * (roughly) twice the number of vectors as there are CPU's.
3494 */
3495 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
b4617240 3496 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
021230d4
AV		 3497
3498 /*
3499 * At the same time, hardware can only support a maximum of
8be0e467
PW		 3500 * hw.mac->max_msix_vectors vectors. With features
3501 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3502 * descriptor queues supported by our device. Thus, we cap it off in
3503 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3504 */
8be0e467 3505 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3506
3507 /* A failure in MSI-X entry allocation isn't fatal, but it does
3508 * mean we disable MSI-X capabilities of the adapter. */
3509 adapter->msix_entries = kcalloc(v_budget,
b4617240 3510 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 3511 if (adapter->msix_entries) {
3512 for (vector = 0; vector < v_budget; vector++)
3513 adapter->msix_entries[vector].entry = vector;
021230d4 3514
7a921c93 3515 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 3516
7a921c93
AD		 3517 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3518 goto out;
3519 }
021230d4 3520
7a921c93
AD		 3521 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3522 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 3523 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3524 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3525 adapter->atr_sample_rate = 0;
7a921c93 3526 ixgbe_set_num_queues(adapter);
021230d4 3527
021230d4
AV		 3528 err = pci_enable_msi(adapter->pdev);
3529 if (!err) {
3530 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3531 } else {
3532 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 3533 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 3534 /* reset err */
3535 err = 0;
3536 }
3537
3538out:
021230d4
AV		 3539 return err;
3540}
3541
7a921c93
AD		 3542/**
3543 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3544 * @adapter: board private structure to initialize
3545 *
3546 * We allocate one q_vector per queue interrupt. If allocation fails we
3547 * return -ENOMEM.
3548 **/
3549static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3550{
3551 int q_idx, num_q_vectors;
3552 struct ixgbe_q_vector *q_vector;
3553 int napi_vectors;
3554 int (*poll)(struct napi_struct *, int);
3555
3556 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3557 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3558 napi_vectors = adapter->num_rx_queues;
91281fd3 3559 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 3560 } else {
3561 num_q_vectors = 1;
3562 napi_vectors = 1;
3563 poll = &ixgbe_poll;
3564 }
3565
3566 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3567 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3568 if (!q_vector)
3569 goto err_out;
3570 q_vector->adapter = adapter;
7a921c93 3571 q_vector->eitr = adapter->eitr_param;
fe49f04a 3572 q_vector->v_idx = q_idx;
91281fd3 3573 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 3574 adapter->q_vector[q_idx] = q_vector;
3575 }
3576
3577 return 0;
3578
3579err_out:
3580 while (q_idx) {
3581 q_idx--;
3582 q_vector = adapter->q_vector[q_idx];
3583 netif_napi_del(&q_vector->napi);
3584 kfree(q_vector);
3585 adapter->q_vector[q_idx] = NULL;
3586 }
3587 return -ENOMEM;
3588}
3589
3590/**
3591 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3592 * @adapter: board private structure to initialize
3593 *
3594 * This function frees the memory allocated to the q_vectors. In addition if
3595 * NAPI is enabled it will delete any references to the NAPI struct prior
3596 * to freeing the q_vector.
3597 **/
3598static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3599{
3600 int q_idx, num_q_vectors;
7a921c93 3601
91281fd3 3602 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 3603 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 3604 else
7a921c93 3605 num_q_vectors = 1;
7a921c93
AD		 3606
3607 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3608 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 3609 adapter->q_vector[q_idx] = NULL;
91281fd3 3610 netif_napi_del(&q_vector->napi);
7a921c93
AD		 3611 kfree(q_vector);
3612 }
3613}
3614
2f90b865 3615void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 3616{
3617 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3618 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3619 pci_disable_msix(adapter->pdev);
3620 kfree(adapter->msix_entries);
3621 adapter->msix_entries = NULL;
3622 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3623 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3624 pci_disable_msi(adapter->pdev);
3625 }
3626 return;
3627}
3628
3629/**
3630 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3631 * @adapter: board private structure to initialize
3632 *
3633 * We determine which interrupt scheme to use based on...
3634 * - Kernel support (MSI, MSI-X)
3635 * - which can be user-defined (via MODULE_PARAM)
3636 * - Hardware queue count (num_*_queues)
3637 * - defined by miscellaneous hardware support/features (RSS, etc.)
3638 **/
2f90b865 3639int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 3640{
3641 int err;
3642
3643 /* Number of supported queues */
3644 ixgbe_set_num_queues(adapter);
3645
021230d4
AV		 3646 err = ixgbe_set_interrupt_capability(adapter);
3647 if (err) {
3648 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3649 goto err_set_interrupt;
9a799d71
AK		 3650 }
3651
7a921c93
AD		 3652 err = ixgbe_alloc_q_vectors(adapter);
3653 if (err) {
3654 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3655 "vectors\n");
3656 goto err_alloc_q_vectors;
3657 }
3658
3659 err = ixgbe_alloc_queues(adapter);
3660 if (err) {
3661 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3662 goto err_alloc_queues;
3663 }
3664
021230d4 3665 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 3666 "Tx Queue count = %u\n",
3667 (adapter->num_rx_queues > 1) ? "Enabled" :
3668 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 3669
3670 set_bit(__IXGBE_DOWN, &adapter->state);
3671
9a799d71 3672 return 0;
021230d4 3673
7a921c93
AD		 3674err_alloc_queues:
3675 ixgbe_free_q_vectors(adapter);
3676err_alloc_q_vectors:
3677 ixgbe_reset_interrupt_capability(adapter);
021230d4 3678err_set_interrupt:
7a921c93
AD		 3679 return err;
3680}
3681
3682/**
3683 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3684 * @adapter: board private structure to clear interrupt scheme on
3685 *
3686 * We go through and clear interrupt specific resources and reset the structure
3687 * to pre-load conditions
3688 **/
3689void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3690{
021230d4
AV		 3691 kfree(adapter->tx_ring);
3692 kfree(adapter->rx_ring);
7a921c93
AD		 3693 adapter->tx_ring = NULL;
3694 adapter->rx_ring = NULL;
3695
3696 ixgbe_free_q_vectors(adapter);
3697 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 3698}
3699
c4900be0
DS		 3700/**
3701 * ixgbe_sfp_timer - worker thread to find a missing module
3702 * @data: pointer to our adapter struct
3703 **/
3704static void ixgbe_sfp_timer(unsigned long data)
3705{
3706 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3707
4df10466
JB		 3708 /*
3709 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 3710 * delays that sfp+ detection requires
3711 */
3712 schedule_work(&adapter->sfp_task);
3713}
3714
3715/**
3716 * ixgbe_sfp_task - worker thread to find a missing module
3717 * @work: pointer to work_struct containing our data
3718 **/
3719static void ixgbe_sfp_task(struct work_struct *work)
3720{
3721 struct ixgbe_adapter *adapter = container_of(work,
3722 struct ixgbe_adapter,
3723 sfp_task);
3724 struct ixgbe_hw *hw = &adapter->hw;
3725
3726 if ((hw->phy.type == ixgbe_phy_nl) &&
3727 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3728 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 3729 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 3730 goto reschedule;
3731 ret = hw->phy.ops.reset(hw);
3732 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 3733 dev_err(&adapter->pdev->dev, "failed to initialize "
3734 "because an unsupported SFP+ module type "
3735 "was detected.\n"
3736 "Reload the driver after installing a "
3737 "supported module.\n");
c4900be0
DS		 3738 unregister_netdev(adapter->netdev);
3739 } else {
3740 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3741 hw->phy.sfp_type);
3742 }
3743 /* don't need this routine any more */
3744 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3745 }
3746 return;
3747reschedule:
3748 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3749 mod_timer(&adapter->sfp_timer,
3750 round_jiffies(jiffies + (2 * HZ)));
3751}
3752
9a799d71
AK		 3753/**
3754 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3755 * @adapter: board private structure to initialize
3756 *
3757 * ixgbe_sw_init initializes the Adapter private data structure.
3758 * Fields are initialized based on PCI device information and
3759 * OS network device settings (MTU size).
3760 **/
3761static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3762{
3763 struct ixgbe_hw *hw = &adapter->hw;
3764 struct pci_dev *pdev = adapter->pdev;
021230d4 3765 unsigned int rss;
7a6b6f51 3766#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3767 int j;
3768 struct tc_configuration *tc;
3769#endif
021230d4 3770
c44ade9e
JB		 3771 /* PCI config space info */
3772
3773 hw->vendor_id = pdev->vendor;
3774 hw->device_id = pdev->device;
3775 hw->revision_id = pdev->revision;
3776 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3777 hw->subsystem_device_id = pdev->subsystem_device;
3778
021230d4
AV		 3779 /* Set capability flags */
3780 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3781 adapter->ring_feature[RING_F_RSS].indices = rss;
3782 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 3783 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 3784 if (hw->mac.type == ixgbe_mac_82598EB) {
3785 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3786 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 3787 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 3788 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 3789 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 3790 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3791 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
c4cf55e5
PWJ		 3792 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3793 adapter->ring_feature[RING_F_FDIR].indices =
3794 IXGBE_MAX_FDIR_INDICES;
3795 adapter->atr_sample_rate = 20;
3796 adapter->fdir_pballoc = 0;
eacd73f7 3797#ifdef IXGBE_FCOE
0d551589
YZ		 3798 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3799 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3800 adapter->ring_feature[RING_F_FCOE].indices = 0;
eacd73f7 3801#endif /* IXGBE_FCOE */
f8212f97 3802 }
2f90b865 3803
7a6b6f51 3804#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3805 /* Configure DCB traffic classes */
3806 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3807 tc = &adapter->dcb_cfg.tc_config[j];
3808 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3809 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3810 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3811 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3812 tc->dcb_pfc = pfc_disabled;
3813 }
3814 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3815 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3816 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 3817 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 3818 adapter->dcb_cfg.round_robin_enable = false;
3819 adapter->dcb_set_bitmap = 0x00;
3820 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3821 adapter->ring_feature[RING_F_DCB].indices);
3822
3823#endif
9a799d71
AK		 3824
3825 /* default flow control settings */
cd7664f6 3826 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 3827 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 3828#ifdef CONFIG_DCB
3829 adapter->last_lfc_mode = hw->fc.current_mode;
3830#endif
2b9ade93
JB		 3831 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3832 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3833 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3834 hw->fc.send_xon = true;
71fd570b 3835 hw->fc.disable_fc_autoneg = false;
9a799d71 3836
30efa5a3
JB		 3837 /* enable itr by default in dynamic mode */
3838 adapter->itr_setting = 1;
3839 adapter->eitr_param = 20000;
3840
3841 /* set defaults for eitr in MegaBytes */
3842 adapter->eitr_low = 10;
3843 adapter->eitr_high = 20;
3844
3845 /* set default ring sizes */
3846 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3847 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3848
9a799d71 3849 /* initialize eeprom parameters */
c44ade9e 3850 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 3851 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3852 return -EIO;
3853 }
3854
021230d4 3855 /* enable rx csum by default */
9a799d71
AK		 3856 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3857
9a799d71
AK		 3858 set_bit(__IXGBE_DOWN, &adapter->state);
3859
3860 return 0;
3861}
3862
3863/**
3864 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3865 * @adapter: board private structure
3a581073 3866 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3867 *
3868 * Return 0 on success, negative on failure
3869 **/
3870int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 3871 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3872{
3873 struct pci_dev *pdev = adapter->pdev;
3874 int size;
3875
3a581073
JB		 3876 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3877 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 3878 if (!tx_ring->tx_buffer_info)
3879 goto err;
3a581073 3880 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 3881
3882 /* round up to nearest 4K */
12207e49 3883 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 3884 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 3885
3a581073
JB		 3886 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3887 &tx_ring->dma);
e01c31a5
JB		 3888 if (!tx_ring->desc)
3889 goto err;
9a799d71 3890
3a581073
JB		 3891 tx_ring->next_to_use = 0;
3892 tx_ring->next_to_clean = 0;
3893 tx_ring->work_limit = tx_ring->count;
9a799d71 3894 return 0;
e01c31a5
JB		 3895
3896err:
3897 vfree(tx_ring->tx_buffer_info);
3898 tx_ring->tx_buffer_info = NULL;
3899 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3900 "descriptor ring\n");
3901 return -ENOMEM;
9a799d71
AK		 3902}
3903
69888674
AD		 3904/**
3905 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3906 * @adapter: board private structure
3907 *
3908 * If this function returns with an error, then it's possible one or
3909 * more of the rings is populated (while the rest are not). It is the
3910 * callers duty to clean those orphaned rings.
3911 *
3912 * Return 0 on success, negative on failure
3913 **/
3914static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3915{
3916 int i, err = 0;
3917
3918 for (i = 0; i < adapter->num_tx_queues; i++) {
3919 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3920 if (!err)
3921 continue;
3922 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3923 break;
3924 }
3925
3926 return err;
3927}
3928
9a799d71
AK		 3929/**
3930 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3931 * @adapter: board private structure
3a581073 3932 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3933 *
3934 * Returns 0 on success, negative on failure
3935 **/
3936int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 3937 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3938{
3939 struct pci_dev *pdev = adapter->pdev;
021230d4 3940 int size;
9a799d71 3941
3a581073
JB		 3942 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3943 rx_ring->rx_buffer_info = vmalloc(size);
3944 if (!rx_ring->rx_buffer_info) {
9a799d71 3945 DPRINTK(PROBE, ERR,
b4617240 3946 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 3947 goto alloc_failed;
9a799d71 3948 }
3a581073 3949 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 3950
9a799d71 3951 /* Round up to nearest 4K */
3a581073
JB		 3952 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3953 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 3954
3a581073 3955 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 3956
3a581073 3957 if (!rx_ring->desc) {
9a799d71 3958 DPRINTK(PROBE, ERR,
b4617240 3959 "Memory allocation failed for the rx desc ring\n");
3a581073 3960 vfree(rx_ring->rx_buffer_info);
177db6ff 3961 goto alloc_failed;
9a799d71
AK		 3962 }
3963
3a581073
JB		 3964 rx_ring->next_to_clean = 0;
3965 rx_ring->next_to_use = 0;
9a799d71
AK		 3966
3967 return 0;
177db6ff
MC		 3968
3969alloc_failed:
177db6ff 3970 return -ENOMEM;
9a799d71
AK		 3971}
3972
69888674
AD		 3973/**
3974 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3975 * @adapter: board private structure
3976 *
3977 * If this function returns with an error, then it's possible one or
3978 * more of the rings is populated (while the rest are not). It is the
3979 * callers duty to clean those orphaned rings.
3980 *
3981 * Return 0 on success, negative on failure
3982 **/
3983
3984static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3985{
3986 int i, err = 0;
3987
3988 for (i = 0; i < adapter->num_rx_queues; i++) {
3989 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3990 if (!err)
3991 continue;
3992 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3993 break;
3994 }
3995
3996 return err;
3997}
3998
9a799d71
AK		 3999/**
4000 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4001 * @adapter: board private structure
4002 * @tx_ring: Tx descriptor ring for a specific queue
4003 *
4004 * Free all transmit software resources
4005 **/
c431f97e
JB		 4006void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4007 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4008{
4009 struct pci_dev *pdev = adapter->pdev;
4010
4011 ixgbe_clean_tx_ring(adapter, tx_ring);
4012
4013 vfree(tx_ring->tx_buffer_info);
4014 tx_ring->tx_buffer_info = NULL;
4015
4016 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4017
4018 tx_ring->desc = NULL;
4019}
4020
4021/**
4022 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4023 * @adapter: board private structure
4024 *
4025 * Free all transmit software resources
4026 **/
4027static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4028{
4029 int i;
4030
4031 for (i = 0; i < adapter->num_tx_queues; i++)
9891ca7c
JB		 4032 if (adapter->tx_ring[i].desc)
4033 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 4034}
4035
4036/**
b4617240 4037 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4038 * @adapter: board private structure
4039 * @rx_ring: ring to clean the resources from
4040 *
4041 * Free all receive software resources
4042 **/
c431f97e
JB		 4043void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4044 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4045{
4046 struct pci_dev *pdev = adapter->pdev;
4047
4048 ixgbe_clean_rx_ring(adapter, rx_ring);
4049
4050 vfree(rx_ring->rx_buffer_info);
4051 rx_ring->rx_buffer_info = NULL;
4052
4053 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4054
4055 rx_ring->desc = NULL;
4056}
4057
4058/**
4059 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4060 * @adapter: board private structure
4061 *
4062 * Free all receive software resources
4063 **/
4064static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4065{
4066 int i;
4067
4068 for (i = 0; i < adapter->num_rx_queues; i++)
9891ca7c
JB		 4069 if (adapter->rx_ring[i].desc)
4070 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 4071}
4072
9a799d71
AK		 4073/**
4074 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4075 * @netdev: network interface device structure
4076 * @new_mtu: new value for maximum frame size
4077 *
4078 * Returns 0 on success, negative on failure
4079 **/
4080static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4081{
4082 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4083 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4084
42c783c5
JB		 4085 /* MTU < 68 is an error and causes problems on some kernels */
4086 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 4087 return -EINVAL;
4088
021230d4 4089 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 4090 netdev->mtu, new_mtu);
021230d4 4091 /* must set new MTU before calling down or up */
9a799d71
AK		 4092 netdev->mtu = new_mtu;
4093
d4f80882
AV		 4094 if (netif_running(netdev))
4095 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4096
4097 return 0;
4098}
4099
4100/**
4101 * ixgbe_open - Called when a network interface is made active
4102 * @netdev: network interface device structure
4103 *
4104 * Returns 0 on success, negative value on failure
4105 *
4106 * The open entry point is called when a network interface is made
4107 * active by the system (IFF_UP). At this point all resources needed
4108 * for transmit and receive operations are allocated, the interrupt
4109 * handler is registered with the OS, the watchdog timer is started,
4110 * and the stack is notified that the interface is ready.
4111 **/
4112static int ixgbe_open(struct net_device *netdev)
4113{
4114 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4115 int err;
4bebfaa5
AK		 4116
4117 /* disallow open during test */
4118 if (test_bit(__IXGBE_TESTING, &adapter->state))
4119 return -EBUSY;
9a799d71 4120
54386467
JB		 4121 netif_carrier_off(netdev);
4122
9a799d71
AK		 4123 /* allocate transmit descriptors */
4124 err = ixgbe_setup_all_tx_resources(adapter);
4125 if (err)
4126 goto err_setup_tx;
4127
9a799d71
AK		 4128 /* allocate receive descriptors */
4129 err = ixgbe_setup_all_rx_resources(adapter);
4130 if (err)
4131 goto err_setup_rx;
4132
4133 ixgbe_configure(adapter);
4134
021230d4 4135 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4136 if (err)
4137 goto err_req_irq;
4138
9a799d71
AK		 4139 err = ixgbe_up_complete(adapter);
4140 if (err)
4141 goto err_up;
4142
d55b53ff
JK		 4143 netif_tx_start_all_queues(netdev);
4144
9a799d71
AK		 4145 return 0;
4146
4147err_up:
5eba3699 4148 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4149 ixgbe_free_irq(adapter);
4150err_req_irq:
9a799d71 4151err_setup_rx:
a20a1199 4152 ixgbe_free_all_rx_resources(adapter);
9a799d71 4153err_setup_tx:
a20a1199 4154 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 4155 ixgbe_reset(adapter);
4156
4157 return err;
4158}
4159
4160/**
4161 * ixgbe_close - Disables a network interface
4162 * @netdev: network interface device structure
4163 *
4164 * Returns 0, this is not allowed to fail
4165 *
4166 * The close entry point is called when an interface is de-activated
4167 * by the OS. The hardware is still under the drivers control, but
4168 * needs to be disabled. A global MAC reset is issued to stop the
4169 * hardware, and all transmit and receive resources are freed.
4170 **/
4171static int ixgbe_close(struct net_device *netdev)
4172{
4173 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4174
4175 ixgbe_down(adapter);
4176 ixgbe_free_irq(adapter);
4177
4178 ixgbe_free_all_tx_resources(adapter);
4179 ixgbe_free_all_rx_resources(adapter);
4180
5eba3699 4181 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4182
4183 return 0;
4184}
4185
b3c8b4ba
AD		 4186#ifdef CONFIG_PM
4187static int ixgbe_resume(struct pci_dev *pdev)
4188{
4189 struct net_device *netdev = pci_get_drvdata(pdev);
4190 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4191 u32 err;
4192
4193 pci_set_power_state(pdev, PCI_D0);
4194 pci_restore_state(pdev);
9ce77666 4195
4196 err = pci_enable_device_mem(pdev);
b3c8b4ba 4197 if (err) {
69888674 4198 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 4199 "suspend\n");
4200 return err;
4201 }
4202 pci_set_master(pdev);
4203
dd4d8ca6 4204 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 4205
4206 err = ixgbe_init_interrupt_scheme(adapter);
4207 if (err) {
4208 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4209 "device\n");
4210 return err;
4211 }
4212
b3c8b4ba
AD		 4213 ixgbe_reset(adapter);
4214
495dce12
WJP		 4215 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4216
b3c8b4ba
AD		 4217 if (netif_running(netdev)) {
4218 err = ixgbe_open(adapter->netdev);
4219 if (err)
4220 return err;
4221 }
4222
4223 netif_device_attach(netdev);
4224
4225 return 0;
4226}
b3c8b4ba 4227#endif /* CONFIG_PM */
9d8d05ae
RW		 4228
4229static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 4230{
4231 struct net_device *netdev = pci_get_drvdata(pdev);
4232 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 4233 struct ixgbe_hw *hw = &adapter->hw;
4234 u32 ctrl, fctrl;
4235 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4236#ifdef CONFIG_PM
4237 int retval = 0;
4238#endif
4239
4240 netif_device_detach(netdev);
4241
4242 if (netif_running(netdev)) {
4243 ixgbe_down(adapter);
4244 ixgbe_free_irq(adapter);
4245 ixgbe_free_all_tx_resources(adapter);
4246 ixgbe_free_all_rx_resources(adapter);
4247 }
7a921c93 4248 ixgbe_clear_interrupt_scheme(adapter);
b3c8b4ba
AD		 4249
4250#ifdef CONFIG_PM
4251 retval = pci_save_state(pdev);
4252 if (retval)
4253 return retval;
4df10466 4254
b3c8b4ba 4255#endif
e8e26350
PW		 4256 if (wufc) {
4257 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4258
e8e26350
PW		 4259 /* turn on all-multi mode if wake on multicast is enabled */
4260 if (wufc & IXGBE_WUFC_MC) {
4261 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4262 fctrl |= IXGBE_FCTRL_MPE;
4263 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4264 }
4265
4266 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4267 ctrl |= IXGBE_CTRL_GIO_DIS;
4268 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4269
4270 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4271 } else {
4272 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4273 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4274 }
4275
dd4d8ca6
DS		 4276 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4277 pci_wake_from_d3(pdev, true);
4278 else
4279 pci_wake_from_d3(pdev, false);
b3c8b4ba 4280
9d8d05ae
RW		 4281 *enable_wake = !!wufc;
4282
b3c8b4ba
AD		 4283 ixgbe_release_hw_control(adapter);
4284
4285 pci_disable_device(pdev);
4286
9d8d05ae
RW		 4287 return 0;
4288}
4289
4290#ifdef CONFIG_PM
4291static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4292{
4293 int retval;
4294 bool wake;
4295
4296 retval = __ixgbe_shutdown(pdev, &wake);
4297 if (retval)
4298 return retval;
4299
4300 if (wake) {
4301 pci_prepare_to_sleep(pdev);
4302 } else {
4303 pci_wake_from_d3(pdev, false);
4304 pci_set_power_state(pdev, PCI_D3hot);
4305 }
b3c8b4ba
AD		 4306
4307 return 0;
4308}
9d8d05ae 4309#endif /* CONFIG_PM */
b3c8b4ba
AD		 4310
4311static void ixgbe_shutdown(struct pci_dev *pdev)
4312{
9d8d05ae
RW		 4313 bool wake;
4314
4315 __ixgbe_shutdown(pdev, &wake);
4316
4317 if (system_state == SYSTEM_POWER_OFF) {
4318 pci_wake_from_d3(pdev, wake);
4319 pci_set_power_state(pdev, PCI_D3hot);
4320 }
b3c8b4ba
AD		 4321}
4322
9a799d71
AK		 4323/**
4324 * ixgbe_update_stats - Update the board statistics counters.
4325 * @adapter: board private structure
4326 **/
4327void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4328{
4329 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 4330 u64 total_mpc = 0;
4331 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71 4332
d51019a4 4333 if (hw->mac.type == ixgbe_mac_82599EB) {
f8212f97 4334 u64 rsc_count = 0;
d51019a4
PW		 4335 for (i = 0; i < 16; i++)
4336 adapter->hw_rx_no_dma_resources +=
4337 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
f8212f97
AD		 4338 for (i = 0; i < adapter->num_rx_queues; i++)
4339 rsc_count += adapter->rx_ring[i].rsc_count;
4340 adapter->rsc_count = rsc_count;
d51019a4
PW		 4341 }
4342
9a799d71 4343 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 4344 for (i = 0; i < 8; i++) {
4345 /* for packet buffers not used, the register should read 0 */
4346 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4347 missed_rx += mpc;
4348 adapter->stats.mpc[i] += mpc;
4349 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 4350 if (hw->mac.type == ixgbe_mac_82598EB)
4351 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 4352 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4353 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4354 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4355 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 4356 if (hw->mac.type == ixgbe_mac_82599EB) {
4357 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4358 IXGBE_PXONRXCNT(i));
4359 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4360 IXGBE_PXOFFRXCNT(i));
4361 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 4362 } else {
4363 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4364 IXGBE_PXONRXC(i));
4365 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4366 IXGBE_PXOFFRXC(i));
4367 }
2f90b865
AD		 4368 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4369 IXGBE_PXONTXC(i));
2f90b865 4370 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 4371 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 4372 }
4373 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4374 /* work around hardware counting issue */
4375 adapter->stats.gprc -= missed_rx;
4376
4377 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350
PW		 4378 if (hw->mac.type == ixgbe_mac_82599EB) {
4379 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4380 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
4381 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4382 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
4383 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4384 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4385 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4386 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
c4cf55e5
PWJ		 4387 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4388 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c
YZ		 4389#ifdef IXGBE_FCOE
4390 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4391 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4392 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4393 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4394 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4395 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4396#endif /* IXGBE_FCOE */
e8e26350
PW		 4397 } else {
4398 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4399 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4400 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4401 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4402 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4403 }
9a799d71
AK		 4404 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4405 adapter->stats.bprc += bprc;
4406 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 4407 if (hw->mac.type == ixgbe_mac_82598EB)
4408 adapter->stats.mprc -= bprc;
9a799d71
AK		 4409 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4410 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4411 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4412 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4413 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4414 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4415 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 4416 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 4417 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4418 adapter->stats.lxontxc += lxon;
4419 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4420 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 4421 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4422 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 4423 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4424 /*
4425 * 82598 errata - tx of flow control packets is included in tx counters
4426 */
4427 xon_off_tot = lxon + lxoff;
4428 adapter->stats.gptc -= xon_off_tot;
4429 adapter->stats.mptc -= xon_off_tot;
4430 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 4431 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4432 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4433 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 4434 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4435 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 4436 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 4437 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4438 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4439 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4440 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4441 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 4442 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4443
4444 /* Fill out the OS statistics structure */
9a799d71
AK		 4445 adapter->net_stats.multicast = adapter->stats.mprc;
4446
4447 /* Rx Errors */
4448 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
b4617240 4449 adapter->stats.rlec;
9a799d71
AK		 4450 adapter->net_stats.rx_dropped = 0;
4451 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4452 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 4453 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 4454}
4455
4456/**
4457 * ixgbe_watchdog - Timer Call-back
4458 * @data: pointer to adapter cast into an unsigned long
4459 **/
4460static void ixgbe_watchdog(unsigned long data)
4461{
4462 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 4463 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 4464 u64 eics = 0;
4465 int i;
cf8280ee 4466
fe49f04a
AD		 4467 /*
4468 * Do the watchdog outside of interrupt context due to the lovely
4469 * delays that some of the newer hardware requires
4470 */
22d5a71b 4471
fe49f04a
AD		 4472 if (test_bit(__IXGBE_DOWN, &adapter->state))
4473 goto watchdog_short_circuit;
22d5a71b 4474
fe49f04a
AD		 4475 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4476 /*
4477 * for legacy and MSI interrupts don't set any bits
4478 * that are enabled for EIAM, because this operation
4479 * would set *both* EIMS and EICS for any bit in EIAM
4480 */
4481 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4482 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4483 goto watchdog_reschedule;
4484 }
4485
4486 /* get one bit for every active tx/rx interrupt vector */
4487 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4488 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4489 if (qv->rxr_count || qv->txr_count)
4490 eics |= ((u64)1 << i);
cf8280ee 4491 }
9a799d71 4492
fe49f04a
AD		 4493 /* Cause software interrupt to ensure rx rings are cleaned */
4494 ixgbe_irq_rearm_queues(adapter, eics);
4495
4496watchdog_reschedule:
4497 /* Reset the timer */
4498 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4499
4500watchdog_short_circuit:
cf8280ee
JB		 4501 schedule_work(&adapter->watchdog_task);
4502}
4503
e8e26350
PW		 4504/**
4505 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4506 * @work: pointer to work_struct containing our data
4507 **/
4508static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4509{
4510 struct ixgbe_adapter *adapter = container_of(work,
4511 struct ixgbe_adapter,
4512 multispeed_fiber_task);
4513 struct ixgbe_hw *hw = &adapter->hw;
4514 u32 autoneg;
4515
4516 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 4517 autoneg = hw->phy.autoneg_advertised;
4518 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e26350
PW		 4519 hw->mac.ops.get_link_capabilities(hw, &autoneg,
4520 &hw->mac.autoneg);
4521 if (hw->mac.ops.setup_link_speed)
4522 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
4523 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4524 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4525}
4526
4527/**
4528 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4529 * @work: pointer to work_struct containing our data
4530 **/
4531static void ixgbe_sfp_config_module_task(struct work_struct *work)
4532{
4533 struct ixgbe_adapter *adapter = container_of(work,
4534 struct ixgbe_adapter,
4535 sfp_config_module_task);
4536 struct ixgbe_hw *hw = &adapter->hw;
4537 u32 err;
4538
4539 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 4540
4541 /* Time for electrical oscillations to settle down */
4542 msleep(100);
e8e26350 4543 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4544
e8e26350 4545 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 4546 dev_err(&adapter->pdev->dev, "failed to initialize because "
4547 "an unsupported SFP+ module type was detected.\n"
4548 "Reload the driver after installing a supported "
4549 "module.\n");
63d6e1d8 4550 unregister_netdev(adapter->netdev);
e8e26350
PW		 4551 return;
4552 }
4553 hw->mac.ops.setup_sfp(hw);
4554
8d1c3c07 4555 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 4556 /* This will also work for DA Twinax connections */
4557 schedule_work(&adapter->multispeed_fiber_task);
4558 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4559}
4560
c4cf55e5
PWJ		 4561/**
4562 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4563 * @work: pointer to work_struct containing our data
4564 **/
4565static void ixgbe_fdir_reinit_task(struct work_struct *work)
4566{
4567 struct ixgbe_adapter *adapter = container_of(work,
4568 struct ixgbe_adapter,
4569 fdir_reinit_task);
4570 struct ixgbe_hw *hw = &adapter->hw;
4571 int i;
4572
4573 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4574 for (i = 0; i < adapter->num_tx_queues; i++)
4575 set_bit(__IXGBE_FDIR_INIT_DONE,
4576 &(adapter->tx_ring[i].reinit_state));
4577 } else {
4578 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4579 "ignored adding FDIR ATR filters \n");
4580 }
4581 /* Done FDIR Re-initialization, enable transmits */
4582 netif_tx_start_all_queues(adapter->netdev);
4583}
4584
cf8280ee 4585/**
69888674
AD		 4586 * ixgbe_watchdog_task - worker thread to bring link up
4587 * @work: pointer to work_struct containing our data
cf8280ee
JB		 4588 **/
4589static void ixgbe_watchdog_task(struct work_struct *work)
4590{
4591 struct ixgbe_adapter *adapter = container_of(work,
4592 struct ixgbe_adapter,
4593 watchdog_task);
4594 struct net_device *netdev = adapter->netdev;
4595 struct ixgbe_hw *hw = &adapter->hw;
4596 u32 link_speed = adapter->link_speed;
4597 bool link_up = adapter->link_up;
bc59fcda
NS		 4598 int i;
4599 struct ixgbe_ring *tx_ring;
4600 int some_tx_pending = 0;
cf8280ee
JB		 4601
4602 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4603
4604 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4605 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 4606 if (link_up) {
4607#ifdef CONFIG_DCB
4608 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4609 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 4610 hw->mac.ops.fc_enable(hw, i);
264857b8 4611 } else {
620fa036 4612 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 4613 }
4614#else
620fa036 4615 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 4616#endif
4617 }
4618
cf8280ee
JB		 4619 if (link_up ||
4620 time_after(jiffies, (adapter->link_check_timeout +
4621 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 4622 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 4623 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 4624 }
4625 adapter->link_up = link_up;
4626 adapter->link_speed = link_speed;
4627 }
9a799d71
AK		 4628
4629 if (link_up) {
4630 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 4631 bool flow_rx, flow_tx;
4632
4633 if (hw->mac.type == ixgbe_mac_82599EB) {
4634 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4635 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4636 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
4637 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
4638 } else {
4639 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4640 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4641 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
4642 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
4643 }
4644
a46e534b
JK		 4645 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4646 "Flow Control: %s\n",
4647 netdev->name,
4648 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4649 "10 Gbps" :
4650 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4651 "1 Gbps" : "unknown speed")),
e8e26350
PW		 4652 ((flow_rx && flow_tx) ? "RX/TX" :
4653 (flow_rx ? "RX" :
4654 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 4655
4656 netif_carrier_on(netdev);
9a799d71
AK		 4657 } else {
4658 /* Force detection of hung controller */
4659 adapter->detect_tx_hung = true;
4660 }
4661 } else {
cf8280ee
JB		 4662 adapter->link_up = false;
4663 adapter->link_speed = 0;
9a799d71 4664 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 4665 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4666 netdev->name);
9a799d71 4667 netif_carrier_off(netdev);
9a799d71
AK		 4668 }
4669 }
4670
bc59fcda
NS		 4671 if (!netif_carrier_ok(netdev)) {
4672 for (i = 0; i < adapter->num_tx_queues; i++) {
4673 tx_ring = &adapter->tx_ring[i];
4674 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4675 some_tx_pending = 1;
4676 break;
4677 }
4678 }
4679
4680 if (some_tx_pending) {
4681 /* We've lost link, so the controller stops DMA,
4682 * but we've got queued Tx work that's never going
4683 * to get done, so reset controller to flush Tx.
4684 * (Do the reset outside of interrupt context).
4685 */
4686 schedule_work(&adapter->reset_task);
4687 }
4688 }
4689
9a799d71 4690 ixgbe_update_stats(adapter);
cf8280ee 4691 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 4692}
4693
9a799d71 4694static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 4695 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4696 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 4697{
4698 struct ixgbe_adv_tx_context_desc *context_desc;
4699 unsigned int i;
4700 int err;
4701 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 4702 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4703 u32 mss_l4len_idx, l4len;
9a799d71
AK		 4704
4705 if (skb_is_gso(skb)) {
4706 if (skb_header_cloned(skb)) {
4707 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4708 if (err)
4709 return err;
4710 }
4711 l4len = tcp_hdrlen(skb);
4712 *hdr_len += l4len;
4713
8327d000 4714 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 4715 struct iphdr *iph = ip_hdr(skb);
4716 iph->tot_len = 0;
4717 iph->check = 0;
4718 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 4719 iph->daddr, 0,
4720 IPPROTO_TCP,
4721 0);
9a799d71
AK		 4722 adapter->hw_tso_ctxt++;
4723 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4724 ipv6_hdr(skb)->payload_len = 0;
4725 tcp_hdr(skb)->check =
4726 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 4727 &ipv6_hdr(skb)->daddr,
4728 0, IPPROTO_TCP, 0);
9a799d71
AK		 4729 adapter->hw_tso6_ctxt++;
4730 }
4731
4732 i = tx_ring->next_to_use;
4733
4734 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4735 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4736
4737 /* VLAN MACLEN IPLEN */
4738 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4739 vlan_macip_lens |=
4740 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4741 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 4742 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4743 *hdr_len += skb_network_offset(skb);
4744 vlan_macip_lens |=
4745 (skb_transport_header(skb) - skb_network_header(skb));
4746 *hdr_len +=
4747 (skb_transport_header(skb) - skb_network_header(skb));
4748 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4749 context_desc->seqnum_seed = 0;
4750
4751 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 4752 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 4753 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 4754
8327d000 4755 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4756 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4757 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4758 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4759
4760 /* MSS L4LEN IDX */
9f8cdf4f 4761 mss_l4len_idx =
9a799d71
AK		 4762 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4763 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 4764 /* use index 1 for TSO */
4765 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4766 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4767
4768 tx_buffer_info->time_stamp = jiffies;
4769 tx_buffer_info->next_to_watch = i;
4770
4771 i++;
4772 if (i == tx_ring->count)
4773 i = 0;
4774 tx_ring->next_to_use = i;
4775
4776 return true;
4777 }
4778 return false;
4779}
4780
4781static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 4782 struct ixgbe_ring *tx_ring,
4783 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 4784{
4785 struct ixgbe_adv_tx_context_desc *context_desc;
4786 unsigned int i;
4787 struct ixgbe_tx_buffer *tx_buffer_info;
4788 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4789
4790 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4791 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4792 i = tx_ring->next_to_use;
4793 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4794 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4795
4796 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4797 vlan_macip_lens |=
4798 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4799 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 4800 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4801 if (skb->ip_summed == CHECKSUM_PARTIAL)
4802 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 4803 skb_network_header(skb));
9a799d71
AK		 4804
4805 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4806 context_desc->seqnum_seed = 0;
4807
4808 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 4809 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 4810
4811 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71 4812 switch (skb->protocol) {
09640e63 4813 case cpu_to_be16(ETH_P_IP):
9a799d71 4814 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 4815 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4816 type_tucmd_mlhl |=
b4617240 4817 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4818 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4819 type_tucmd_mlhl |=
4820 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4821 break;
09640e63 4822 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 4823 /* XXX what about other V6 headers?? */
4824 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4825 type_tucmd_mlhl |=
b4617240 4826 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4827 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4828 type_tucmd_mlhl |=
4829 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4830 break;
41825d71
AK		 4831 default:
4832 if (unlikely(net_ratelimit())) {
4833 DPRINTK(PROBE, WARNING,
4834 "partial checksum but proto=%x!\n",
4835 skb->protocol);
4836 }
4837 break;
4838 }
9a799d71
AK		 4839 }
4840
4841 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 4842 /* use index zero for tx checksum offload */
9a799d71
AK		 4843 context_desc->mss_l4len_idx = 0;
4844
4845 tx_buffer_info->time_stamp = jiffies;
4846 tx_buffer_info->next_to_watch = i;
9f8cdf4f 4847
9a799d71
AK		 4848 adapter->hw_csum_tx_good++;
4849 i++;
4850 if (i == tx_ring->count)
4851 i = 0;
4852 tx_ring->next_to_use = i;
4853
4854 return true;
4855 }
9f8cdf4f 4856
9a799d71
AK		 4857 return false;
4858}
4859
4860static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 4861 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 4862 struct sk_buff *skb, u32 tx_flags,
4863 unsigned int first)
9a799d71
AK		 4864{
4865 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 4866 unsigned int len;
4867 unsigned int total = skb->len;
9a799d71
AK		 4868 unsigned int offset = 0, size, count = 0, i;
4869 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4870 unsigned int f;
44df32c5 4871 dma_addr_t *map;
9a799d71
AK		 4872
4873 i = tx_ring->next_to_use;
4874
44df32c5
AD		 4875 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4876 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4877 return 0;
4878 }
4879
4880 map = skb_shinfo(skb)->dma_maps;
4881
eacd73f7
YZ		 4882 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4883 /* excluding fcoe_crc_eof for FCoE */
4884 total -= sizeof(struct fcoe_crc_eof);
4885
4886 len = min(skb_headlen(skb), total);
9a799d71
AK		 4887 while (len) {
4888 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4889 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4890
4891 tx_buffer_info->length = size;
042a53a9 4892 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
9a799d71
AK		 4893 tx_buffer_info->time_stamp = jiffies;
4894 tx_buffer_info->next_to_watch = i;
4895
4896 len -= size;
eacd73f7 4897 total -= size;
9a799d71
AK		 4898 offset += size;
4899 count++;
44df32c5
AD		 4900
4901 if (len) {
4902 i++;
4903 if (i == tx_ring->count)
4904 i = 0;
4905 }
9a799d71
AK		 4906 }
4907
4908 for (f = 0; f < nr_frags; f++) {
4909 struct skb_frag_struct *frag;
4910
4911 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 4912 len = min((unsigned int)frag->size, total);
44df32c5 4913 offset = 0;
9a799d71
AK		 4914
4915 while (len) {
44df32c5
AD		 4916 i++;
4917 if (i == tx_ring->count)
4918 i = 0;
4919
9a799d71
AK		 4920 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4921 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4922
4923 tx_buffer_info->length = size;
042a53a9 4924 tx_buffer_info->dma = map[f] + offset;
9a799d71
AK		 4925 tx_buffer_info->time_stamp = jiffies;
4926 tx_buffer_info->next_to_watch = i;
4927
4928 len -= size;
eacd73f7 4929 total -= size;
9a799d71
AK		 4930 offset += size;
4931 count++;
9a799d71 4932 }
eacd73f7
YZ		 4933 if (total == 0)
4934 break;
9a799d71 4935 }
44df32c5 4936
9a799d71
AK		 4937 tx_ring->tx_buffer_info[i].skb = skb;
4938 tx_ring->tx_buffer_info[first].next_to_watch = i;
4939
4940 return count;
4941}
4942
4943static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 4944 struct ixgbe_ring *tx_ring,
4945 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 4946{
4947 union ixgbe_adv_tx_desc *tx_desc = NULL;
4948 struct ixgbe_tx_buffer *tx_buffer_info;
4949 u32 olinfo_status = 0, cmd_type_len = 0;
4950 unsigned int i;
4951 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4952
4953 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4954
4955 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4956
4957 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4958 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4959
4960 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4961 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4962
4963 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4964 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 4965
4eeae6fd
PW		 4966 /* use index 1 context for tso */
4967 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4968 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4969 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 4970 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 4971
4972 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4973 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4974 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 4975
eacd73f7
YZ		 4976 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
4977 olinfo_status |= IXGBE_ADVTXD_CC;
4978 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4979 if (tx_flags & IXGBE_TX_FLAGS_FSO)
4980 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4981 }
4982
9a799d71
AK		 4983 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4984
4985 i = tx_ring->next_to_use;
4986 while (count--) {
4987 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4988 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4989 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4990 tx_desc->read.cmd_type_len =
b4617240 4991 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 4992 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 4993 i++;
4994 if (i == tx_ring->count)
4995 i = 0;
4996 }
4997
4998 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
4999
5000 /*
5001 * Force memory writes to complete before letting h/w
5002 * know there are new descriptors to fetch. (Only
5003 * applicable for weak-ordered memory model archs,
5004 * such as IA-64).
5005 */
5006 wmb();
5007
5008 tx_ring->next_to_use = i;
5009 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5010}
5011
c4cf55e5
PWJ		 5012static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5013 int queue, u32 tx_flags)
5014{
5015 /* Right now, we support IPv4 only */
5016 struct ixgbe_atr_input atr_input;
5017 struct tcphdr *th;
5018 struct udphdr *uh;
5019 struct iphdr *iph = ip_hdr(skb);
5020 struct ethhdr *eth = (struct ethhdr *)skb->data;
5021 u16 vlan_id, src_port, dst_port, flex_bytes;
5022 u32 src_ipv4_addr, dst_ipv4_addr;
5023 u8 l4type = 0;
5024
5025 /* check if we're UDP or TCP */
5026 if (iph->protocol == IPPROTO_TCP) {
5027 th = tcp_hdr(skb);
5028 src_port = th->source;
5029 dst_port = th->dest;
5030 l4type |= IXGBE_ATR_L4TYPE_TCP;
5031 /* l4type IPv4 type is 0, no need to assign */
5032 } else if(iph->protocol == IPPROTO_UDP) {
5033 uh = udp_hdr(skb);
5034 src_port = uh->source;
5035 dst_port = uh->dest;
5036 l4type |= IXGBE_ATR_L4TYPE_UDP;
5037 /* l4type IPv4 type is 0, no need to assign */
5038 } else {
5039 /* Unsupported L4 header, just bail here */
5040 return;
5041 }
5042
5043 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5044
5045 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5046 IXGBE_TX_FLAGS_VLAN_SHIFT;
5047 src_ipv4_addr = iph->saddr;
5048 dst_ipv4_addr = iph->daddr;
5049 flex_bytes = eth->h_proto;
5050
5051 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5052 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5053 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5054 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5055 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5056 /* src and dst are inverted, think how the receiver sees them */
5057 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5058 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5059
5060 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5061 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5062}
5063
e092be60 5064static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5065 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 5066{
5067 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5068
30eba97a 5069 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5070 /* Herbert's original patch had:
5071 * smp_mb__after_netif_stop_queue();
5072 * but since that doesn't exist yet, just open code it. */
5073 smp_mb();
5074
5075 /* We need to check again in a case another CPU has just
5076 * made room available. */
5077 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5078 return -EBUSY;
5079
5080 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 5081 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5082 ++adapter->restart_queue;
5083 return 0;
5084}
5085
5086static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5087 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 5088{
5089 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5090 return 0;
5091 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5092}
5093
09a3b1f8
SH		 5094static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5095{
5096 struct ixgbe_adapter *adapter = netdev_priv(dev);
5097
c4cf55e5
PWJ		 5098 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5099 return smp_processor_id();
5100
09a3b1f8
SH		 5101 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5102 return 0; /* All traffic should default to class 0 */
5103
5104 return skb_tx_hash(dev, skb);
5105}
5106
9a799d71
AK		 5107static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
5108{
5109 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5110 struct ixgbe_ring *tx_ring;
9a799d71
AK		 5111 unsigned int first;
5112 unsigned int tx_flags = 0;
30eba97a
AV		 5113 u8 hdr_len = 0;
5114 int r_idx = 0, tso;
9a799d71
AK		 5115 int count = 0;
5116 unsigned int f;
9f8cdf4f 5117
9f8cdf4f
JB		 5118 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5119 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 5120 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5121 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5122 tx_flags |= (skb->queue_mapping << 13);
5123 }
5124 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5125 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5126 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
60127865
LL		 5127 if (skb->priority != TC_PRIO_CONTROL) {
5128 tx_flags |= (skb->queue_mapping << 13);
5129 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5130 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5131 } else {
5132 skb->queue_mapping =
5133 adapter->ring_feature[RING_F_DCB].indices-1;
5134 }
9a799d71 5135 }
eacd73f7 5136
60127865
LL		 5137 r_idx = skb->queue_mapping;
5138 tx_ring = &adapter->tx_ring[r_idx];
5139
eacd73f7
YZ		 5140 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5141 (skb->protocol == htons(ETH_P_FCOE)))
5142 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5143
5144 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 5145 if (skb_is_gso(skb) ||
5146 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 5147 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5148 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 5149 count++;
5150
9f8cdf4f
JB		 5151 count += TXD_USE_COUNT(skb_headlen(skb));
5152 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 5153 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5154
e092be60 5155 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 5156 adapter->tx_busy++;
9a799d71
AK		 5157 return NETDEV_TX_BUSY;
5158 }
9a799d71 5159
9a799d71 5160 first = tx_ring->next_to_use;
eacd73f7
YZ		 5161 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5162#ifdef IXGBE_FCOE
5163 /* setup tx offload for FCoE */
5164 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5165 if (tso < 0) {
5166 dev_kfree_skb_any(skb);
5167 return NETDEV_TX_OK;
5168 }
5169 if (tso)
5170 tx_flags |= IXGBE_TX_FLAGS_FSO;
5171#endif /* IXGBE_FCOE */
5172 } else {
5173 if (skb->protocol == htons(ETH_P_IP))
5174 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5175 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5176 if (tso < 0) {
5177 dev_kfree_skb_any(skb);
5178 return NETDEV_TX_OK;
5179 }
9a799d71 5180
eacd73f7
YZ		 5181 if (tso)
5182 tx_flags |= IXGBE_TX_FLAGS_TSO;
5183 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5184 (skb->ip_summed == CHECKSUM_PARTIAL))
5185 tx_flags |= IXGBE_TX_FLAGS_CSUM;
5186 }
9a799d71 5187
eacd73f7 5188 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 5189 if (count) {
c4cf55e5
PWJ		 5190 /* add the ATR filter if ATR is on */
5191 if (tx_ring->atr_sample_rate) {
5192 ++tx_ring->atr_count;
5193 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5194 test_bit(__IXGBE_FDIR_INIT_DONE,
5195 &tx_ring->reinit_state)) {
5196 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5197 tx_flags);
5198 tx_ring->atr_count = 0;
5199 }
5200 }
44df32c5
AD		 5201 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5202 hdr_len);
44df32c5 5203 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 5204
44df32c5
AD		 5205 } else {
5206 dev_kfree_skb_any(skb);
5207 tx_ring->tx_buffer_info[first].time_stamp = 0;
5208 tx_ring->next_to_use = first;
5209 }
9a799d71
AK		 5210
5211 return NETDEV_TX_OK;
5212}
5213
5214/**
5215 * ixgbe_get_stats - Get System Network Statistics
5216 * @netdev: network interface device structure
5217 *
5218 * Returns the address of the device statistics structure.
5219 * The statistics are actually updated from the timer callback.
5220 **/
5221static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5222{
5223 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5224
5225 /* only return the current stats */
5226 return &adapter->net_stats;
5227}
5228
5229/**
5230 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5231 * @netdev: network interface device structure
5232 * @p: pointer to an address structure
5233 *
5234 * Returns 0 on success, negative on failure
5235 **/
5236static int ixgbe_set_mac(struct net_device *netdev, void *p)
5237{
5238 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 5239 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5240 struct sockaddr *addr = p;
5241
5242 if (!is_valid_ether_addr(addr->sa_data))
5243 return -EADDRNOTAVAIL;
5244
5245 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 5246 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 5247
b4617240 5248 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 5249
5250 return 0;
5251}
5252
6b73e10d
BH		 5253static int
5254ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5255{
5256 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5257 struct ixgbe_hw *hw = &adapter->hw;
5258 u16 value;
5259 int rc;
5260
5261 if (prtad != hw->phy.mdio.prtad)
5262 return -EINVAL;
5263 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5264 if (!rc)
5265 rc = value;
5266 return rc;
5267}
5268
5269static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5270 u16 addr, u16 value)
5271{
5272 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5273 struct ixgbe_hw *hw = &adapter->hw;
5274
5275 if (prtad != hw->phy.mdio.prtad)
5276 return -EINVAL;
5277 return hw->phy.ops.write_reg(hw, addr, devad, value);
5278}
5279
5280static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5281{
5282 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5283
5284 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5285}
5286
0365e6e4
PW		 5287/**
5288 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 5289 * netdev->dev_addrs
0365e6e4
PW		 5290 * @netdev: network interface device structure
5291 *
5292 * Returns non-zero on failure
5293 **/
5294static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5295{
5296 int err = 0;
5297 struct ixgbe_adapter *adapter = netdev_priv(dev);
5298 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5299
5300 if (is_valid_ether_addr(mac->san_addr)) {
5301 rtnl_lock();
5302 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5303 rtnl_unlock();
5304 }
5305 return err;
5306}
5307
5308/**
5309 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 5310 * netdev->dev_addrs
0365e6e4
PW		 5311 * @netdev: network interface device structure
5312 *
5313 * Returns non-zero on failure
5314 **/
5315static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5316{
5317 int err = 0;
5318 struct ixgbe_adapter *adapter = netdev_priv(dev);
5319 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5320
5321 if (is_valid_ether_addr(mac->san_addr)) {
5322 rtnl_lock();
5323 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5324 rtnl_unlock();
5325 }
5326 return err;
5327}
5328
9a799d71
AK		 5329#ifdef CONFIG_NET_POLL_CONTROLLER
5330/*
5331 * Polling 'interrupt' - used by things like netconsole to send skbs
5332 * without having to re-enable interrupts. It's not called while
5333 * the interrupt routine is executing.
5334 */
5335static void ixgbe_netpoll(struct net_device *netdev)
5336{
5337 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 5338 int i;
9a799d71 5339
9a799d71 5340 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 5341 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5342 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5343 for (i = 0; i < num_q_vectors; i++) {
5344 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5345 ixgbe_msix_clean_many(0, q_vector);
5346 }
5347 } else {
5348 ixgbe_intr(adapter->pdev->irq, netdev);
5349 }
9a799d71 5350 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 5351}
5352#endif
5353
0edc3527
SH		 5354static const struct net_device_ops ixgbe_netdev_ops = {
5355 .ndo_open = ixgbe_open,
5356 .ndo_stop = ixgbe_close,
00829823 5357 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 5358 .ndo_select_queue = ixgbe_select_queue,
0edc3527 5359 .ndo_get_stats = ixgbe_get_stats,
e90d400c 5360 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 5361 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5362 .ndo_validate_addr = eth_validate_addr,
5363 .ndo_set_mac_address = ixgbe_set_mac,
5364 .ndo_change_mtu = ixgbe_change_mtu,
5365 .ndo_tx_timeout = ixgbe_tx_timeout,
5366 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5367 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5368 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 5369 .ndo_do_ioctl = ixgbe_ioctl,
0edc3527
SH		 5370#ifdef CONFIG_NET_POLL_CONTROLLER
5371 .ndo_poll_controller = ixgbe_netpoll,
5372#endif
332d4a7d
YZ		 5373#ifdef IXGBE_FCOE
5374 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5375 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5376#endif /* IXGBE_FCOE */
0edc3527
SH		 5377};
5378
9a799d71
AK		 5379/**
5380 * ixgbe_probe - Device Initialization Routine
5381 * @pdev: PCI device information struct
5382 * @ent: entry in ixgbe_pci_tbl
5383 *
5384 * Returns 0 on success, negative on failure
5385 *
5386 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5387 * The OS initialization, configuring of the adapter private structure,
5388 * and a hardware reset occur.
5389 **/
5390static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 5391 const struct pci_device_id *ent)
9a799d71
AK		 5392{
5393 struct net_device *netdev;
5394 struct ixgbe_adapter *adapter = NULL;
5395 struct ixgbe_hw *hw;
5396 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 5397 static int cards_found;
5398 int i, err, pci_using_dac;
eacd73f7
YZ		 5399#ifdef IXGBE_FCOE
5400 u16 device_caps;
5401#endif
c44ade9e 5402 u32 part_num, eec;
9a799d71 5403
9ce77666 5404 err = pci_enable_device_mem(pdev);
9a799d71
AK		 5405 if (err)
5406 return err;
5407
6a35528a
YH		 5408 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5409 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
9a799d71
AK		 5410 pci_using_dac = 1;
5411 } else {
284901a9 5412 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5413 if (err) {
284901a9 5414 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5415 if (err) {
b4617240
PW		 5416 dev_err(&pdev->dev, "No usable DMA "
5417 "configuration, aborting\n");
9a799d71
AK		 5418 goto err_dma;
5419 }
5420 }
5421 pci_using_dac = 0;
5422 }
5423
9ce77666 5424 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5425 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 5426 if (err) {
9ce77666 5427 dev_err(&pdev->dev,
5428 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 5429 goto err_pci_reg;
5430 }
5431
6fabd715
PWJ		 5432 err = pci_enable_pcie_error_reporting(pdev);
5433 if (err) {
5434 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
5435 "0x%x\n", err);
5436 /* non-fatal, continue */
5437 }
5438
9a799d71 5439 pci_set_master(pdev);
fb3b27bc 5440 pci_save_state(pdev);
9a799d71 5441
30eba97a 5442 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 5443 if (!netdev) {
5444 err = -ENOMEM;
5445 goto err_alloc_etherdev;
5446 }
5447
9a799d71
AK		 5448 SET_NETDEV_DEV(netdev, &pdev->dev);
5449
5450 pci_set_drvdata(pdev, netdev);
5451 adapter = netdev_priv(netdev);
5452
5453 adapter->netdev = netdev;
5454 adapter->pdev = pdev;
5455 hw = &adapter->hw;
5456 hw->back = adapter;
5457 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5458
05857980
JK		 5459 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5460 pci_resource_len(pdev, 0));
9a799d71
AK		 5461 if (!hw->hw_addr) {
5462 err = -EIO;
5463 goto err_ioremap;
5464 }
5465
5466 for (i = 1; i <= 5; i++) {
5467 if (pci_resource_len(pdev, i) == 0)
5468 continue;
5469 }
5470
0edc3527 5471 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 5472 ixgbe_set_ethtool_ops(netdev);
9a799d71 5473 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 5474 strcpy(netdev->name, pci_name(pdev));
5475
9a799d71
AK		 5476 adapter->bd_number = cards_found;
5477
9a799d71
AK		 5478 /* Setup hw api */
5479 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 5480 hw->mac.type = ii->mac;
9a799d71 5481
c44ade9e
JB		 5482 /* EEPROM */
5483 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5484 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5485 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5486 if (!(eec & (1 << 8)))
5487 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5488
5489 /* PHY */
5490 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 5491 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 5492 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5493 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5494 hw->phy.mdio.mmds = 0;
5495 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5496 hw->phy.mdio.dev = netdev;
5497 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5498 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 5499
5500 /* set up this timer and work struct before calling get_invariants
5501 * which might start the timer
5502 */
5503 init_timer(&adapter->sfp_timer);
5504 adapter->sfp_timer.function = &ixgbe_sfp_timer;
5505 adapter->sfp_timer.data = (unsigned long) adapter;
5506
5507 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 5508
e8e26350
PW		 5509 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5510 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5511
5512 /* a new SFP+ module arrival, called from GPI SDP2 context */
5513 INIT_WORK(&adapter->sfp_config_module_task,
5514 ixgbe_sfp_config_module_task);
5515
8ca783ab 5516 ii->get_invariants(hw);
9a799d71
AK		 5517
5518 /* setup the private structure */
5519 err = ixgbe_sw_init(adapter);
5520 if (err)
5521 goto err_sw_init;
5522
bf069c97
DS		 5523 /*
5524 * If there is a fan on this device and it has failed log the
5525 * failure.
5526 */
5527 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5528 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5529 if (esdp & IXGBE_ESDP_SDP1)
5530 DPRINTK(PROBE, CRIT,
5531 "Fan has stopped, replace the adapter\n");
5532 }
5533
c44ade9e
JB		 5534 /* reset_hw fills in the perm_addr as well */
5535 err = hw->mac.ops.reset_hw(hw);
8ca783ab
DS		 5536 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5537 hw->mac.type == ixgbe_mac_82598EB) {
5538 /*
5539 * Start a kernel thread to watch for a module to arrive.
5540 * Only do this for 82598, since 82599 will generate
5541 * interrupts on module arrival.
5542 */
5543 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5544 mod_timer(&adapter->sfp_timer,
5545 round_jiffies(jiffies + (2 * HZ)));
5546 err = 0;
5547 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 5548 dev_err(&adapter->pdev->dev, "failed to initialize because "
5549 "an unsupported SFP+ module type was detected.\n"
5550 "Reload the driver after installing a supported "
5551 "module.\n");
04f165ef
PW		 5552 goto err_sw_init;
5553 } else if (err) {
c44ade9e
JB		 5554 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5555 goto err_sw_init;
5556 }
5557
9a799d71 5558 netdev->features = NETIF_F_SG |
b4617240
PW		 5559 NETIF_F_IP_CSUM |
5560 NETIF_F_HW_VLAN_TX |
5561 NETIF_F_HW_VLAN_RX |
5562 NETIF_F_HW_VLAN_FILTER;
9a799d71 5563
e9990a9c 5564 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 5565 netdev->features |= NETIF_F_TSO;
9a799d71 5566 netdev->features |= NETIF_F_TSO6;
78b6f4ce 5567 netdev->features |= NETIF_F_GRO;
ad31c402 5568
45a5ead0
JB		 5569 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5570 netdev->features |= NETIF_F_SCTP_CSUM;
5571
ad31c402
JK		 5572 netdev->vlan_features |= NETIF_F_TSO;
5573 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 5574 netdev->vlan_features |= NETIF_F_IP_CSUM;
ad31c402
JK		 5575 netdev->vlan_features |= NETIF_F_SG;
5576
2f90b865
AD		 5577 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5578 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5579
7a6b6f51 5580#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5581 netdev->dcbnl_ops = &dcbnl_ops;
5582#endif
5583
eacd73f7 5584#ifdef IXGBE_FCOE
0d551589 5585 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 5586 if (hw->mac.ops.get_device_caps) {
5587 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 5588 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5589 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 5590 }
5591 }
5592#endif /* IXGBE_FCOE */
9a799d71
AK		 5593 if (pci_using_dac)
5594 netdev->features |= NETIF_F_HIGHDMA;
5595
0c19d6af 5596 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 5597 netdev->features |= NETIF_F_LRO;
5598
9a799d71 5599 /* make sure the EEPROM is good */
c44ade9e 5600 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 5601 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5602 err = -EIO;
5603 goto err_eeprom;
5604 }
5605
5606 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5607 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5608
c44ade9e
JB		 5609 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5610 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 5611 err = -EIO;
5612 goto err_eeprom;
5613 }
5614
5615 init_timer(&adapter->watchdog_timer);
5616 adapter->watchdog_timer.function = &ixgbe_watchdog;
5617 adapter->watchdog_timer.data = (unsigned long)adapter;
5618
5619 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 5620 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 5621
021230d4
AV		 5622 err = ixgbe_init_interrupt_scheme(adapter);
5623 if (err)
5624 goto err_sw_init;
9a799d71 5625
e8e26350
PW		 5626 switch (pdev->device) {
5627 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 5628 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5629 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
bdf0a550
PWJ		 5630 /* Enable ACPI wakeup in GRC */
5631 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5632 (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
e8e26350
PW		 5633 break;
5634 default:
5635 adapter->wol = 0;
5636 break;
5637 }
e8e26350
PW		 5638 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5639
04f165ef
PW		 5640 /* pick up the PCI bus settings for reporting later */
5641 hw->mac.ops.get_bus_info(hw);
5642
9a799d71 5643 /* print bus type/speed/width info */
7c510e4b 5644 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 5645 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5646 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5647 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5648 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5649 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 5650 "Unknown"),
7c510e4b 5651 netdev->dev_addr);
c44ade9e 5652 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 5653 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5654 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5655 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5656 (part_num >> 8), (part_num & 0xff));
5657 else
5658 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5659 hw->mac.type, hw->phy.type,
5660 (part_num >> 8), (part_num & 0xff));
9a799d71 5661
e8e26350 5662 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 5663 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 5664 "this card is not sufficient for optimal "
5665 "performance.\n");
0c254d86 5666 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 5667 "PCI-Express slot is required.\n");
0c254d86
AK		 5668 }
5669
34b0368c
PWJ		 5670 /* save off EEPROM version number */
5671 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5672
9a799d71 5673 /* reset the hardware with the new settings */
794caeb2 5674 err = hw->mac.ops.start_hw(hw);
c44ade9e 5675
794caeb2
PWJ		 5676 if (err == IXGBE_ERR_EEPROM_VERSION) {
5677 /* We are running on a pre-production device, log a warning */
5678 dev_warn(&pdev->dev, "This device is a pre-production "
5679 "adapter/LOM. Please be aware there may be issues "
5680 "associated with your hardware. If you are "
5681 "experiencing problems please contact your Intel or "
5682 "hardware representative who provided you with this "
5683 "hardware.\n");
5684 }
9a799d71
AK		 5685 strcpy(netdev->name, "eth%d");
5686 err = register_netdev(netdev);
5687 if (err)
5688 goto err_register;
5689
54386467
JB		 5690 /* carrier off reporting is important to ethtool even BEFORE open */
5691 netif_carrier_off(netdev);
5692
c4cf55e5
PWJ		 5693 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5694 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5695 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5696
5dd2d332 5697#ifdef CONFIG_IXGBE_DCA
652f093f 5698 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 5699 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 5700 ixgbe_setup_dca(adapter);
5701 }
5702#endif
0365e6e4
PW		 5703 /* add san mac addr to netdev */
5704 ixgbe_add_sanmac_netdev(netdev);
9a799d71
AK		 5705
5706 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5707 cards_found++;
5708 return 0;
5709
5710err_register:
5eba3699 5711 ixgbe_release_hw_control(adapter);
7a921c93 5712 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 5713err_sw_init:
5714err_eeprom:
c4900be0
DS		 5715 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5716 del_timer_sync(&adapter->sfp_timer);
5717 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5718 cancel_work_sync(&adapter->multispeed_fiber_task);
5719 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 5720 iounmap(hw->hw_addr);
5721err_ioremap:
5722 free_netdev(netdev);
5723err_alloc_etherdev:
9ce77666 5724 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5725 IORESOURCE_MEM));
9a799d71
AK		 5726err_pci_reg:
5727err_dma:
5728 pci_disable_device(pdev);
5729 return err;
5730}
5731
5732/**
5733 * ixgbe_remove - Device Removal Routine
5734 * @pdev: PCI device information struct
5735 *
5736 * ixgbe_remove is called by the PCI subsystem to alert the driver
5737 * that it should release a PCI device. The could be caused by a
5738 * Hot-Plug event, or because the driver is going to be removed from
5739 * memory.
5740 **/
5741static void __devexit ixgbe_remove(struct pci_dev *pdev)
5742{
5743 struct net_device *netdev = pci_get_drvdata(pdev);
5744 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715 5745 int err;
9a799d71
AK		 5746
5747 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 5748 /* clear the module not found bit to make sure the worker won't
5749 * reschedule
5750 */
5751 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 5752 del_timer_sync(&adapter->watchdog_timer);
5753
c4900be0
DS		 5754 del_timer_sync(&adapter->sfp_timer);
5755 cancel_work_sync(&adapter->watchdog_task);
5756 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5757 cancel_work_sync(&adapter->multispeed_fiber_task);
5758 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 5759 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5760 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5761 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 5762 flush_scheduled_work();
5763
5dd2d332 5764#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5765 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5766 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5767 dca_remove_requester(&pdev->dev);
5768 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5769 }
5770
5771#endif
332d4a7d
YZ		 5772#ifdef IXGBE_FCOE
5773 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5774 ixgbe_cleanup_fcoe(adapter);
5775
5776#endif /* IXGBE_FCOE */
0365e6e4
PW		 5777
5778 /* remove the added san mac */
5779 ixgbe_del_sanmac_netdev(netdev);
5780
c4900be0
DS		 5781 if (netdev->reg_state == NETREG_REGISTERED)
5782 unregister_netdev(netdev);
9a799d71 5783
7a921c93 5784 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 5785
021230d4 5786 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5787
5788 iounmap(adapter->hw.hw_addr);
9ce77666 5789 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5790 IORESOURCE_MEM));
9a799d71 5791
021230d4 5792 DPRINTK(PROBE, INFO, "complete\n");
021230d4 5793
9a799d71
AK		 5794 free_netdev(netdev);
5795
6fabd715
PWJ		 5796 err = pci_disable_pcie_error_reporting(pdev);
5797 if (err)
5798 dev_err(&pdev->dev,
5799 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5800
9a799d71
AK		 5801 pci_disable_device(pdev);
5802}
5803
5804/**
5805 * ixgbe_io_error_detected - called when PCI error is detected
5806 * @pdev: Pointer to PCI device
5807 * @state: The current pci connection state
5808 *
5809 * This function is called after a PCI bus error affecting
5810 * this device has been detected.
5811 */
5812static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 5813 pci_channel_state_t state)
9a799d71
AK		 5814{
5815 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5816 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5817
5818 netif_device_detach(netdev);
5819
3044b8d1
BL		 5820 if (state == pci_channel_io_perm_failure)
5821 return PCI_ERS_RESULT_DISCONNECT;
5822
9a799d71
AK		 5823 if (netif_running(netdev))
5824 ixgbe_down(adapter);
5825 pci_disable_device(pdev);
5826
b4617240 5827 /* Request a slot reset. */
9a799d71
AK		 5828 return PCI_ERS_RESULT_NEED_RESET;
5829}
5830
5831/**
5832 * ixgbe_io_slot_reset - called after the pci bus has been reset.
5833 * @pdev: Pointer to PCI device
5834 *
5835 * Restart the card from scratch, as if from a cold-boot.
5836 */
5837static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5838{
5839 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5840 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 5841 pci_ers_result_t result;
5842 int err;
9a799d71 5843
9ce77666 5844 if (pci_enable_device_mem(pdev)) {
9a799d71 5845 DPRINTK(PROBE, ERR,
b4617240 5846 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 5847 result = PCI_ERS_RESULT_DISCONNECT;
5848 } else {
5849 pci_set_master(pdev);
5850 pci_restore_state(pdev);
9a799d71 5851
dd4d8ca6 5852 pci_wake_from_d3(pdev, false);
9a799d71 5853
6fabd715 5854 ixgbe_reset(adapter);
88512539 5855 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 5856 result = PCI_ERS_RESULT_RECOVERED;
5857 }
5858
5859 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5860 if (err) {
5861 dev_err(&pdev->dev,
5862 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5863 /* non-fatal, continue */
5864 }
9a799d71 5865
6fabd715 5866 return result;
9a799d71
AK		 5867}
5868
5869/**
5870 * ixgbe_io_resume - called when traffic can start flowing again.
5871 * @pdev: Pointer to PCI device
5872 *
5873 * This callback is called when the error recovery driver tells us that
5874 * its OK to resume normal operation.
5875 */
5876static void ixgbe_io_resume(struct pci_dev *pdev)
5877{
5878 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5879 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5880
5881 if (netif_running(netdev)) {
5882 if (ixgbe_up(adapter)) {
5883 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5884 return;
5885 }
5886 }
5887
5888 netif_device_attach(netdev);
9a799d71
AK		 5889}
5890
5891static struct pci_error_handlers ixgbe_err_handler = {
5892 .error_detected = ixgbe_io_error_detected,
5893 .slot_reset = ixgbe_io_slot_reset,
5894 .resume = ixgbe_io_resume,
5895};
5896
5897static struct pci_driver ixgbe_driver = {
5898 .name = ixgbe_driver_name,
5899 .id_table = ixgbe_pci_tbl,
5900 .probe = ixgbe_probe,
5901 .remove = __devexit_p(ixgbe_remove),
5902#ifdef CONFIG_PM
5903 .suspend = ixgbe_suspend,
5904 .resume = ixgbe_resume,
5905#endif
5906 .shutdown = ixgbe_shutdown,
5907 .err_handler = &ixgbe_err_handler
5908};
5909
5910/**
5911 * ixgbe_init_module - Driver Registration Routine
5912 *
5913 * ixgbe_init_module is the first routine called when the driver is
5914 * loaded. All it does is register with the PCI subsystem.
5915 **/
5916static int __init ixgbe_init_module(void)
5917{
5918 int ret;
5919 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5920 ixgbe_driver_string, ixgbe_driver_version);
5921
5922 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5923
5dd2d332 5924#ifdef CONFIG_IXGBE_DCA
bd0362dd 5925 dca_register_notify(&dca_notifier);
bd0362dd 5926#endif
5dd2d332 5927
9a799d71
AK		 5928 ret = pci_register_driver(&ixgbe_driver);
5929 return ret;
5930}
b4617240 5931
9a799d71
AK		 5932module_init(ixgbe_init_module);
5933
5934/**
5935 * ixgbe_exit_module - Driver Exit Cleanup Routine
5936 *
5937 * ixgbe_exit_module is called just before the driver is removed
5938 * from memory.
5939 **/
5940static void __exit ixgbe_exit_module(void)
5941{
5dd2d332 5942#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5943 dca_unregister_notify(&dca_notifier);
5944#endif
9a799d71
AK		 5945 pci_unregister_driver(&ixgbe_driver);
5946}
bd0362dd 5947
5dd2d332 5948#ifdef CONFIG_IXGBE_DCA
bd0362dd 5949static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 5950 void *p)
bd0362dd
JC		 5951{
5952 int ret_val;
5953
5954 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 5955 __ixgbe_notify_dca);
bd0362dd
JC		 5956
5957 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5958}
b453368d 5959
5dd2d332 5960#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 5961#ifdef DEBUG
5962/**
5963 * ixgbe_get_hw_dev_name - return device name string
5964 * used by hardware layer to print debugging information
5965 **/
5966char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5967{
5968 struct ixgbe_adapter *adapter = hw->back;
5969 return adapter->netdev->name;
5970}
bd0362dd 5971
b453368d 5972#endif
9a799d71
AK		 5973module_exit(ixgbe_exit_module);
5974
5975/* ixgbe_main.c */
kernel source for telekom puls (alcatel/mediatek)