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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
8c47eaa7 | 4 | Copyright(c) 1999 - 2010 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
35 | #include <linux/ip.h> | |
36 | #include <linux/tcp.h> | |
60127865 | 37 | #include <linux/pkt_sched.h> |
9a799d71 | 38 | #include <linux/ipv6.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
9a799d71 AK |
40 | #include <net/checksum.h> |
41 | #include <net/ip6_checksum.h> | |
42 | #include <linux/ethtool.h> | |
43 | #include <linux/if_vlan.h> | |
eacd73f7 | 44 | #include <scsi/fc/fc_fcoe.h> |
9a799d71 AK |
45 | |
46 | #include "ixgbe.h" | |
47 | #include "ixgbe_common.h" | |
ee5f784a | 48 | #include "ixgbe_dcb_82599.h" |
1cdd1ec8 | 49 | #include "ixgbe_sriov.h" |
9a799d71 AK |
50 | |
51 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 52 | static const char ixgbe_driver_string[] = |
b4617240 | 53 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
9a799d71 | 54 | |
92eb879f | 55 | #define DRV_VERSION "2.0.62-k2" |
9c8eb720 | 56 | const char ixgbe_driver_version[] = DRV_VERSION; |
8c47eaa7 | 57 | static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation."; |
9a799d71 AK |
58 | |
59 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 60 | [board_82598] = &ixgbe_82598_info, |
e8e26350 | 61 | [board_82599] = &ixgbe_82599_info, |
9a799d71 AK |
62 | }; |
63 | ||
64 | /* ixgbe_pci_tbl - PCI Device ID Table | |
65 | * | |
66 | * Wildcard entries (PCI_ANY_ID) should come last | |
67 | * Last entry must be all 0s | |
68 | * | |
69 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
70 | * Class, Class Mask, private data (not used) } | |
71 | */ | |
a3aa1884 | 72 | static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = { |
1e336d0f DS |
73 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), |
74 | board_82598 }, | |
9a799d71 | 75 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), |
3957d63d | 76 | board_82598 }, |
9a799d71 | 77 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), |
3957d63d | 78 | board_82598 }, |
0befdb3e JB |
79 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), |
80 | board_82598 }, | |
3845bec0 PWJ |
81 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), |
82 | board_82598 }, | |
9a799d71 | 83 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), |
3957d63d | 84 | board_82598 }, |
8d792cd9 JB |
85 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), |
86 | board_82598 }, | |
c4900be0 DS |
87 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), |
88 | board_82598 }, | |
89 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), | |
90 | board_82598 }, | |
b95f5fcb JB |
91 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), |
92 | board_82598 }, | |
c4900be0 DS |
93 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), |
94 | board_82598 }, | |
2f21bdd3 DS |
95 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), |
96 | board_82598 }, | |
e8e26350 PW |
97 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), |
98 | board_82599 }, | |
1fcf03e6 PWJ |
99 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), |
100 | board_82599 }, | |
74757d49 DS |
101 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), |
102 | board_82599 }, | |
e8e26350 PW |
103 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), |
104 | board_82599 }, | |
38ad1c8e DS |
105 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), |
106 | board_82599 }, | |
dbfec662 DS |
107 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), |
108 | board_82599 }, | |
8911184f PWJ |
109 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), |
110 | board_82599 }, | |
312eb931 DS |
111 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), |
112 | board_82599 }, | |
9a799d71 AK |
113 | |
114 | /* required last entry */ | |
115 | {0, } | |
116 | }; | |
117 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
118 | ||
5dd2d332 | 119 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 120 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
b4617240 | 121 | void *p); |
bd0362dd JC |
122 | static struct notifier_block dca_notifier = { |
123 | .notifier_call = ixgbe_notify_dca, | |
124 | .next = NULL, | |
125 | .priority = 0 | |
126 | }; | |
127 | #endif | |
128 | ||
1cdd1ec8 GR |
129 | #ifdef CONFIG_PCI_IOV |
130 | static unsigned int max_vfs; | |
131 | module_param(max_vfs, uint, 0); | |
132 | MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate " | |
133 | "per physical function"); | |
134 | #endif /* CONFIG_PCI_IOV */ | |
135 | ||
9a799d71 AK |
136 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
137 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
138 | MODULE_LICENSE("GPL"); | |
139 | MODULE_VERSION(DRV_VERSION); | |
140 | ||
141 | #define DEFAULT_DEBUG_LEVEL_SHIFT 3 | |
142 | ||
1cdd1ec8 GR |
143 | static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter) |
144 | { | |
145 | struct ixgbe_hw *hw = &adapter->hw; | |
146 | u32 gcr; | |
147 | u32 gpie; | |
148 | u32 vmdctl; | |
149 | ||
150 | #ifdef CONFIG_PCI_IOV | |
151 | /* disable iov and allow time for transactions to clear */ | |
152 | pci_disable_sriov(adapter->pdev); | |
153 | #endif | |
154 | ||
155 | /* turn off device IOV mode */ | |
156 | gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); | |
157 | gcr &= ~(IXGBE_GCR_EXT_SRIOV); | |
158 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr); | |
159 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
160 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
161 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
162 | ||
163 | /* set default pool back to 0 */ | |
164 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
165 | vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; | |
166 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); | |
167 | ||
168 | /* take a breather then clean up driver data */ | |
169 | msleep(100); | |
170 | if (adapter->vfinfo) | |
171 | kfree(adapter->vfinfo); | |
172 | adapter->vfinfo = NULL; | |
173 | ||
174 | adapter->num_vfs = 0; | |
175 | adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED; | |
176 | } | |
177 | ||
5eba3699 AV |
178 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
179 | { | |
180 | u32 ctrl_ext; | |
181 | ||
182 | /* Let firmware take over control of h/w */ | |
183 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
184 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 185 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
186 | } |
187 | ||
188 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
189 | { | |
190 | u32 ctrl_ext; | |
191 | ||
192 | /* Let firmware know the driver has taken over */ | |
193 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
194 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 195 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 196 | } |
9a799d71 | 197 | |
e8e26350 PW |
198 | /* |
199 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors | |
200 | * @adapter: pointer to adapter struct | |
201 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
202 | * @queue: queue to map the corresponding interrupt to | |
203 | * @msix_vector: the vector to map to the corresponding queue | |
204 | * | |
205 | */ | |
206 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
207 | u8 queue, u8 msix_vector) | |
9a799d71 AK |
208 | { |
209 | u32 ivar, index; | |
e8e26350 PW |
210 | struct ixgbe_hw *hw = &adapter->hw; |
211 | switch (hw->mac.type) { | |
212 | case ixgbe_mac_82598EB: | |
213 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
214 | if (direction == -1) | |
215 | direction = 0; | |
216 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
217 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
218 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
219 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
220 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
221 | break; | |
222 | case ixgbe_mac_82599EB: | |
223 | if (direction == -1) { | |
224 | /* other causes */ | |
225 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
226 | index = ((queue & 1) * 8); | |
227 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
228 | ivar &= ~(0xFF << index); | |
229 | ivar |= (msix_vector << index); | |
230 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
231 | break; | |
232 | } else { | |
233 | /* tx or rx causes */ | |
234 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
235 | index = ((16 * (queue & 1)) + (8 * direction)); | |
236 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
237 | ivar &= ~(0xFF << index); | |
238 | ivar |= (msix_vector << index); | |
239 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
240 | break; | |
241 | } | |
242 | default: | |
243 | break; | |
244 | } | |
9a799d71 AK |
245 | } |
246 | ||
fe49f04a AD |
247 | static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, |
248 | u64 qmask) | |
249 | { | |
250 | u32 mask; | |
251 | ||
252 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
253 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); | |
254 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); | |
255 | } else { | |
256 | mask = (qmask & 0xFFFFFFFF); | |
257 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); | |
258 | mask = (qmask >> 32); | |
259 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); | |
260 | } | |
261 | } | |
262 | ||
9a799d71 | 263 | static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter, |
b4617240 PW |
264 | struct ixgbe_tx_buffer |
265 | *tx_buffer_info) | |
9a799d71 | 266 | { |
e5a43549 AD |
267 | if (tx_buffer_info->dma) { |
268 | if (tx_buffer_info->mapped_as_page) | |
269 | pci_unmap_page(adapter->pdev, | |
270 | tx_buffer_info->dma, | |
271 | tx_buffer_info->length, | |
272 | PCI_DMA_TODEVICE); | |
273 | else | |
274 | pci_unmap_single(adapter->pdev, | |
275 | tx_buffer_info->dma, | |
276 | tx_buffer_info->length, | |
277 | PCI_DMA_TODEVICE); | |
278 | tx_buffer_info->dma = 0; | |
279 | } | |
9a799d71 AK |
280 | if (tx_buffer_info->skb) { |
281 | dev_kfree_skb_any(tx_buffer_info->skb); | |
282 | tx_buffer_info->skb = NULL; | |
283 | } | |
44df32c5 | 284 | tx_buffer_info->time_stamp = 0; |
9a799d71 AK |
285 | /* tx_buffer_info must be completely set up in the transmit path */ |
286 | } | |
287 | ||
26f23d82 YZ |
288 | /** |
289 | * ixgbe_tx_is_paused - check if the tx ring is paused | |
290 | * @adapter: the ixgbe adapter | |
291 | * @tx_ring: the corresponding tx_ring | |
292 | * | |
293 | * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the | |
294 | * corresponding TC of this tx_ring when checking TFCS. | |
295 | * | |
296 | * Returns : true if paused | |
297 | */ | |
298 | static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter, | |
299 | struct ixgbe_ring *tx_ring) | |
300 | { | |
26f23d82 YZ |
301 | u32 txoff = IXGBE_TFCS_TXOFF; |
302 | ||
303 | #ifdef CONFIG_IXGBE_DCB | |
304 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
30b76832 | 305 | int tc; |
26f23d82 YZ |
306 | int reg_idx = tx_ring->reg_idx; |
307 | int dcb_i = adapter->ring_feature[RING_F_DCB].indices; | |
308 | ||
6837e895 PW |
309 | switch (adapter->hw.mac.type) { |
310 | case ixgbe_mac_82598EB: | |
26f23d82 YZ |
311 | tc = reg_idx >> 2; |
312 | txoff = IXGBE_TFCS_TXOFF0; | |
6837e895 PW |
313 | break; |
314 | case ixgbe_mac_82599EB: | |
26f23d82 YZ |
315 | tc = 0; |
316 | txoff = IXGBE_TFCS_TXOFF; | |
317 | if (dcb_i == 8) { | |
318 | /* TC0, TC1 */ | |
319 | tc = reg_idx >> 5; | |
320 | if (tc == 2) /* TC2, TC3 */ | |
321 | tc += (reg_idx - 64) >> 4; | |
322 | else if (tc == 3) /* TC4, TC5, TC6, TC7 */ | |
323 | tc += 1 + ((reg_idx - 96) >> 3); | |
324 | } else if (dcb_i == 4) { | |
325 | /* TC0, TC1 */ | |
326 | tc = reg_idx >> 6; | |
327 | if (tc == 1) { | |
328 | tc += (reg_idx - 64) >> 5; | |
329 | if (tc == 2) /* TC2, TC3 */ | |
330 | tc += (reg_idx - 96) >> 4; | |
331 | } | |
332 | } | |
6837e895 PW |
333 | break; |
334 | default: | |
335 | tc = 0; | |
26f23d82 YZ |
336 | } |
337 | txoff <<= tc; | |
338 | } | |
339 | #endif | |
340 | return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff; | |
341 | } | |
342 | ||
9a799d71 | 343 | static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter, |
b4617240 PW |
344 | struct ixgbe_ring *tx_ring, |
345 | unsigned int eop) | |
9a799d71 | 346 | { |
e01c31a5 | 347 | struct ixgbe_hw *hw = &adapter->hw; |
e01c31a5 | 348 | |
9a799d71 | 349 | /* Detect a transmit hang in hardware, this serializes the |
e01c31a5 | 350 | * check with the clearing of time_stamp and movement of eop */ |
9a799d71 | 351 | adapter->detect_tx_hung = false; |
44df32c5 | 352 | if (tx_ring->tx_buffer_info[eop].time_stamp && |
9a799d71 | 353 | time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) && |
26f23d82 | 354 | !ixgbe_tx_is_paused(adapter, tx_ring)) { |
9a799d71 | 355 | /* detected Tx unit hang */ |
e01c31a5 JB |
356 | union ixgbe_adv_tx_desc *tx_desc; |
357 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
9a799d71 | 358 | DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n" |
e01c31a5 JB |
359 | " Tx Queue <%d>\n" |
360 | " TDH, TDT <%x>, <%x>\n" | |
9a799d71 AK |
361 | " next_to_use <%x>\n" |
362 | " next_to_clean <%x>\n" | |
363 | "tx_buffer_info[next_to_clean]\n" | |
364 | " time_stamp <%lx>\n" | |
e01c31a5 JB |
365 | " jiffies <%lx>\n", |
366 | tx_ring->queue_index, | |
44df32c5 AD |
367 | IXGBE_READ_REG(hw, tx_ring->head), |
368 | IXGBE_READ_REG(hw, tx_ring->tail), | |
e01c31a5 JB |
369 | tx_ring->next_to_use, eop, |
370 | tx_ring->tx_buffer_info[eop].time_stamp, jiffies); | |
9a799d71 AK |
371 | return true; |
372 | } | |
373 | ||
374 | return false; | |
375 | } | |
376 | ||
b4617240 PW |
377 | #define IXGBE_MAX_TXD_PWR 14 |
378 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
e092be60 AV |
379 | |
380 | /* Tx Descriptors needed, worst case */ | |
381 | #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \ | |
382 | (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0)) | |
383 | #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \ | |
b4617240 | 384 | MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */ |
e092be60 | 385 | |
e01c31a5 JB |
386 | static void ixgbe_tx_timeout(struct net_device *netdev); |
387 | ||
9a799d71 AK |
388 | /** |
389 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
fe49f04a | 390 | * @q_vector: structure containing interrupt and ring information |
e01c31a5 | 391 | * @tx_ring: tx ring to clean |
9a799d71 | 392 | **/ |
fe49f04a | 393 | static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, |
e01c31a5 | 394 | struct ixgbe_ring *tx_ring) |
9a799d71 | 395 | { |
fe49f04a | 396 | struct ixgbe_adapter *adapter = q_vector->adapter; |
e01c31a5 | 397 | struct net_device *netdev = adapter->netdev; |
12207e49 PWJ |
398 | union ixgbe_adv_tx_desc *tx_desc, *eop_desc; |
399 | struct ixgbe_tx_buffer *tx_buffer_info; | |
400 | unsigned int i, eop, count = 0; | |
e01c31a5 | 401 | unsigned int total_bytes = 0, total_packets = 0; |
9a799d71 AK |
402 | |
403 | i = tx_ring->next_to_clean; | |
12207e49 PWJ |
404 | eop = tx_ring->tx_buffer_info[i].next_to_watch; |
405 | eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
406 | ||
407 | while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) && | |
9a1a69ad | 408 | (count < tx_ring->work_limit)) { |
12207e49 PWJ |
409 | bool cleaned = false; |
410 | for ( ; !cleaned; count++) { | |
411 | struct sk_buff *skb; | |
9a799d71 AK |
412 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); |
413 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
12207e49 | 414 | cleaned = (i == eop); |
e01c31a5 | 415 | skb = tx_buffer_info->skb; |
9a799d71 | 416 | |
12207e49 | 417 | if (cleaned && skb) { |
e092be60 | 418 | unsigned int segs, bytecount; |
3d8fd385 | 419 | unsigned int hlen = skb_headlen(skb); |
e01c31a5 JB |
420 | |
421 | /* gso_segs is currently only valid for tcp */ | |
e092be60 | 422 | segs = skb_shinfo(skb)->gso_segs ?: 1; |
3d8fd385 YZ |
423 | #ifdef IXGBE_FCOE |
424 | /* adjust for FCoE Sequence Offload */ | |
425 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
426 | && (skb->protocol == htons(ETH_P_FCOE)) && | |
427 | skb_is_gso(skb)) { | |
428 | hlen = skb_transport_offset(skb) + | |
429 | sizeof(struct fc_frame_header) + | |
430 | sizeof(struct fcoe_crc_eof); | |
431 | segs = DIV_ROUND_UP(skb->len - hlen, | |
432 | skb_shinfo(skb)->gso_size); | |
433 | } | |
434 | #endif /* IXGBE_FCOE */ | |
e092be60 | 435 | /* multiply data chunks by size of headers */ |
3d8fd385 | 436 | bytecount = ((segs - 1) * hlen) + skb->len; |
e01c31a5 JB |
437 | total_packets += segs; |
438 | total_bytes += bytecount; | |
e092be60 | 439 | } |
e01c31a5 | 440 | |
9a799d71 | 441 | ixgbe_unmap_and_free_tx_resource(adapter, |
e01c31a5 | 442 | tx_buffer_info); |
9a799d71 | 443 | |
12207e49 PWJ |
444 | tx_desc->wb.status = 0; |
445 | ||
9a799d71 AK |
446 | i++; |
447 | if (i == tx_ring->count) | |
448 | i = 0; | |
e01c31a5 | 449 | } |
12207e49 PWJ |
450 | |
451 | eop = tx_ring->tx_buffer_info[i].next_to_watch; | |
452 | eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
453 | } | |
454 | ||
9a799d71 AK |
455 | tx_ring->next_to_clean = i; |
456 | ||
e092be60 | 457 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
e01c31a5 JB |
458 | if (unlikely(count && netif_carrier_ok(netdev) && |
459 | (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { | |
e092be60 AV |
460 | /* Make sure that anybody stopping the queue after this |
461 | * sees the new next_to_clean. | |
462 | */ | |
463 | smp_mb(); | |
30eba97a AV |
464 | if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && |
465 | !test_bit(__IXGBE_DOWN, &adapter->state)) { | |
466 | netif_wake_subqueue(netdev, tx_ring->queue_index); | |
7ca3bc58 | 467 | ++tx_ring->restart_queue; |
30eba97a | 468 | } |
e092be60 | 469 | } |
9a799d71 | 470 | |
e01c31a5 JB |
471 | if (adapter->detect_tx_hung) { |
472 | if (ixgbe_check_tx_hang(adapter, tx_ring, i)) { | |
473 | /* schedule immediate reset if we believe we hung */ | |
474 | DPRINTK(PROBE, INFO, | |
475 | "tx hang %d detected, resetting adapter\n", | |
476 | adapter->tx_timeout_count + 1); | |
477 | ixgbe_tx_timeout(adapter->netdev); | |
478 | } | |
479 | } | |
9a799d71 | 480 | |
e01c31a5 | 481 | /* re-arm the interrupt */ |
fe49f04a AD |
482 | if (count >= tx_ring->work_limit) |
483 | ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
9a799d71 | 484 | |
e01c31a5 JB |
485 | tx_ring->total_bytes += total_bytes; |
486 | tx_ring->total_packets += total_packets; | |
e01c31a5 | 487 | tx_ring->stats.packets += total_packets; |
12207e49 | 488 | tx_ring->stats.bytes += total_bytes; |
9a1a69ad | 489 | return (count < tx_ring->work_limit); |
9a799d71 AK |
490 | } |
491 | ||
5dd2d332 | 492 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 493 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
b4617240 | 494 | struct ixgbe_ring *rx_ring) |
bd0362dd JC |
495 | { |
496 | u32 rxctrl; | |
497 | int cpu = get_cpu(); | |
4a0b9ca0 | 498 | int q = rx_ring->reg_idx; |
bd0362dd | 499 | |
3a581073 | 500 | if (rx_ring->cpu != cpu) { |
bd0362dd | 501 | rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q)); |
e8e26350 PW |
502 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
503 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK; | |
504 | rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
505 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
506 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599; | |
507 | rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
508 | IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599); | |
509 | } | |
bd0362dd JC |
510 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN; |
511 | rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN; | |
15005a32 DS |
512 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN); |
513 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN | | |
e8e26350 | 514 | IXGBE_DCA_RXCTRL_DESC_HSRO_EN); |
bd0362dd | 515 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl); |
3a581073 | 516 | rx_ring->cpu = cpu; |
bd0362dd JC |
517 | } |
518 | put_cpu(); | |
519 | } | |
520 | ||
521 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, | |
b4617240 | 522 | struct ixgbe_ring *tx_ring) |
bd0362dd JC |
523 | { |
524 | u32 txctrl; | |
525 | int cpu = get_cpu(); | |
4a0b9ca0 | 526 | int q = tx_ring->reg_idx; |
ee5f784a | 527 | struct ixgbe_hw *hw = &adapter->hw; |
bd0362dd | 528 | |
3a581073 | 529 | if (tx_ring->cpu != cpu) { |
e8e26350 | 530 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
ee5f784a | 531 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q)); |
e8e26350 PW |
532 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK; |
533 | txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
ee5f784a DS |
534 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; |
535 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl); | |
e8e26350 | 536 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
ee5f784a | 537 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q)); |
e8e26350 PW |
538 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599; |
539 | txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
ee5f784a DS |
540 | IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599); |
541 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; | |
542 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl); | |
e8e26350 | 543 | } |
3a581073 | 544 | tx_ring->cpu = cpu; |
bd0362dd JC |
545 | } |
546 | put_cpu(); | |
547 | } | |
548 | ||
549 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
550 | { | |
551 | int i; | |
552 | ||
553 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
554 | return; | |
555 | ||
e35ec126 AD |
556 | /* always use CB2 mode, difference is masked in the CB driver */ |
557 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
558 | ||
bd0362dd | 559 | for (i = 0; i < adapter->num_tx_queues; i++) { |
4a0b9ca0 PW |
560 | adapter->tx_ring[i]->cpu = -1; |
561 | ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]); | |
bd0362dd JC |
562 | } |
563 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
4a0b9ca0 PW |
564 | adapter->rx_ring[i]->cpu = -1; |
565 | ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]); | |
bd0362dd JC |
566 | } |
567 | } | |
568 | ||
569 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
570 | { | |
571 | struct net_device *netdev = dev_get_drvdata(dev); | |
572 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
573 | unsigned long event = *(unsigned long *)data; | |
574 | ||
575 | switch (event) { | |
576 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
577 | /* if we're already enabled, don't do it again */ |
578 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
579 | break; | |
652f093f | 580 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 581 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
582 | ixgbe_setup_dca(adapter); |
583 | break; | |
584 | } | |
585 | /* Fall Through since DCA is disabled. */ | |
586 | case DCA_PROVIDER_REMOVE: | |
587 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
588 | dca_remove_requester(dev); | |
589 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
590 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
591 | } | |
592 | break; | |
593 | } | |
594 | ||
652f093f | 595 | return 0; |
bd0362dd JC |
596 | } |
597 | ||
5dd2d332 | 598 | #endif /* CONFIG_IXGBE_DCA */ |
9a799d71 AK |
599 | /** |
600 | * ixgbe_receive_skb - Send a completed packet up the stack | |
601 | * @adapter: board private structure | |
602 | * @skb: packet to send up | |
177db6ff MC |
603 | * @status: hardware indication of status of receive |
604 | * @rx_ring: rx descriptor ring (for a specific queue) to setup | |
605 | * @rx_desc: rx descriptor | |
9a799d71 | 606 | **/ |
78b6f4ce | 607 | static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector, |
b4617240 | 608 | struct sk_buff *skb, u8 status, |
fdaff1ce | 609 | struct ixgbe_ring *ring, |
177db6ff | 610 | union ixgbe_adv_rx_desc *rx_desc) |
9a799d71 | 611 | { |
78b6f4ce HX |
612 | struct ixgbe_adapter *adapter = q_vector->adapter; |
613 | struct napi_struct *napi = &q_vector->napi; | |
177db6ff MC |
614 | bool is_vlan = (status & IXGBE_RXD_STAT_VP); |
615 | u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan); | |
9a799d71 | 616 | |
fdaff1ce | 617 | skb_record_rx_queue(skb, ring->queue_index); |
182ff8df | 618 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) { |
8a62babf | 619 | if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK)) |
78b6f4ce | 620 | vlan_gro_receive(napi, adapter->vlgrp, tag, skb); |
9a799d71 | 621 | else |
78b6f4ce | 622 | napi_gro_receive(napi, skb); |
177db6ff | 623 | } else { |
8a62babf | 624 | if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK)) |
182ff8df AD |
625 | vlan_hwaccel_rx(skb, adapter->vlgrp, tag); |
626 | else | |
627 | netif_rx(skb); | |
9a799d71 AK |
628 | } |
629 | } | |
630 | ||
e59bd25d AV |
631 | /** |
632 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
633 | * @adapter: address of board private structure | |
634 | * @status_err: hardware indication of status of receive | |
635 | * @skb: skb currently being received and modified | |
636 | **/ | |
9a799d71 | 637 | static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter, |
8bae1b2b DS |
638 | union ixgbe_adv_rx_desc *rx_desc, |
639 | struct sk_buff *skb) | |
9a799d71 | 640 | { |
8bae1b2b DS |
641 | u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error); |
642 | ||
9a799d71 AK |
643 | skb->ip_summed = CHECKSUM_NONE; |
644 | ||
712744be JB |
645 | /* Rx csum disabled */ |
646 | if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED)) | |
9a799d71 | 647 | return; |
e59bd25d AV |
648 | |
649 | /* if IP and error */ | |
650 | if ((status_err & IXGBE_RXD_STAT_IPCS) && | |
651 | (status_err & IXGBE_RXDADV_ERR_IPE)) { | |
9a799d71 AK |
652 | adapter->hw_csum_rx_error++; |
653 | return; | |
654 | } | |
e59bd25d AV |
655 | |
656 | if (!(status_err & IXGBE_RXD_STAT_L4CS)) | |
657 | return; | |
658 | ||
659 | if (status_err & IXGBE_RXDADV_ERR_TCPE) { | |
8bae1b2b DS |
660 | u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; |
661 | ||
662 | /* | |
663 | * 82599 errata, UDP frames with a 0 checksum can be marked as | |
664 | * checksum errors. | |
665 | */ | |
666 | if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) && | |
667 | (adapter->hw.mac.type == ixgbe_mac_82599EB)) | |
668 | return; | |
669 | ||
e59bd25d AV |
670 | adapter->hw_csum_rx_error++; |
671 | return; | |
672 | } | |
673 | ||
9a799d71 | 674 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 675 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
676 | } |
677 | ||
e8e26350 PW |
678 | static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw, |
679 | struct ixgbe_ring *rx_ring, u32 val) | |
680 | { | |
681 | /* | |
682 | * Force memory writes to complete before letting h/w | |
683 | * know there are new descriptors to fetch. (Only | |
684 | * applicable for weak-ordered memory model archs, | |
685 | * such as IA-64). | |
686 | */ | |
687 | wmb(); | |
688 | IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val); | |
689 | } | |
690 | ||
9a799d71 AK |
691 | /** |
692 | * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split | |
693 | * @adapter: address of board private structure | |
694 | **/ | |
695 | static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter, | |
7c6e0a43 JB |
696 | struct ixgbe_ring *rx_ring, |
697 | int cleaned_count) | |
9a799d71 | 698 | { |
9a799d71 AK |
699 | struct pci_dev *pdev = adapter->pdev; |
700 | union ixgbe_adv_rx_desc *rx_desc; | |
3a581073 | 701 | struct ixgbe_rx_buffer *bi; |
9a799d71 | 702 | unsigned int i; |
9a799d71 AK |
703 | |
704 | i = rx_ring->next_to_use; | |
3a581073 | 705 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 AK |
706 | |
707 | while (cleaned_count--) { | |
708 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
709 | ||
762f4c57 | 710 | if (!bi->page_dma && |
6e455b89 | 711 | (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) { |
3a581073 | 712 | if (!bi->page) { |
762f4c57 JB |
713 | bi->page = alloc_page(GFP_ATOMIC); |
714 | if (!bi->page) { | |
715 | adapter->alloc_rx_page_failed++; | |
716 | goto no_buffers; | |
717 | } | |
718 | bi->page_offset = 0; | |
719 | } else { | |
720 | /* use a half page if we're re-using */ | |
721 | bi->page_offset ^= (PAGE_SIZE / 2); | |
9a799d71 | 722 | } |
762f4c57 JB |
723 | |
724 | bi->page_dma = pci_map_page(pdev, bi->page, | |
725 | bi->page_offset, | |
726 | (PAGE_SIZE / 2), | |
727 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
728 | } |
729 | ||
3a581073 | 730 | if (!bi->skb) { |
5ecc3614 | 731 | struct sk_buff *skb; |
7ca3bc58 JB |
732 | /* netdev_alloc_skb reserves 32 bytes up front!! */ |
733 | uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES; | |
734 | skb = netdev_alloc_skb(adapter->netdev, bufsz); | |
9a799d71 AK |
735 | |
736 | if (!skb) { | |
737 | adapter->alloc_rx_buff_failed++; | |
738 | goto no_buffers; | |
739 | } | |
740 | ||
7ca3bc58 JB |
741 | /* advance the data pointer to the next cache line */ |
742 | skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES) | |
743 | - skb->data)); | |
744 | ||
3a581073 | 745 | bi->skb = skb; |
4f57ca6e JB |
746 | bi->dma = pci_map_single(pdev, skb->data, |
747 | rx_ring->rx_buf_len, | |
3a581073 | 748 | PCI_DMA_FROMDEVICE); |
9a799d71 AK |
749 | } |
750 | /* Refresh the desc even if buffer_addrs didn't change because | |
751 | * each write-back erases this info. */ | |
6e455b89 | 752 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) { |
3a581073 JB |
753 | rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma); |
754 | rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); | |
9a799d71 | 755 | } else { |
3a581073 | 756 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma); |
9a799d71 AK |
757 | } |
758 | ||
759 | i++; | |
760 | if (i == rx_ring->count) | |
761 | i = 0; | |
3a581073 | 762 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 | 763 | } |
7c6e0a43 | 764 | |
9a799d71 AK |
765 | no_buffers: |
766 | if (rx_ring->next_to_use != i) { | |
767 | rx_ring->next_to_use = i; | |
768 | if (i-- == 0) | |
769 | i = (rx_ring->count - 1); | |
770 | ||
e8e26350 | 771 | ixgbe_release_rx_desc(&adapter->hw, rx_ring, i); |
9a799d71 AK |
772 | } |
773 | } | |
774 | ||
7c6e0a43 JB |
775 | static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc) |
776 | { | |
777 | return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info; | |
778 | } | |
779 | ||
780 | static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc) | |
781 | { | |
782 | return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
783 | } | |
784 | ||
f8212f97 AD |
785 | static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc) |
786 | { | |
787 | return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) & | |
788 | IXGBE_RXDADV_RSCCNT_MASK) >> | |
789 | IXGBE_RXDADV_RSCCNT_SHIFT; | |
790 | } | |
791 | ||
792 | /** | |
793 | * ixgbe_transform_rsc_queue - change rsc queue into a full packet | |
794 | * @skb: pointer to the last skb in the rsc queue | |
94b982b2 | 795 | * @count: pointer to number of packets coalesced in this context |
f8212f97 AD |
796 | * |
797 | * This function changes a queue full of hw rsc buffers into a completed | |
798 | * packet. It uses the ->prev pointers to find the first packet and then | |
799 | * turns it into the frag list owner. | |
800 | **/ | |
94b982b2 MC |
801 | static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb, |
802 | u64 *count) | |
f8212f97 AD |
803 | { |
804 | unsigned int frag_list_size = 0; | |
805 | ||
806 | while (skb->prev) { | |
807 | struct sk_buff *prev = skb->prev; | |
808 | frag_list_size += skb->len; | |
809 | skb->prev = NULL; | |
810 | skb = prev; | |
94b982b2 | 811 | *count += 1; |
f8212f97 AD |
812 | } |
813 | ||
814 | skb_shinfo(skb)->frag_list = skb->next; | |
815 | skb->next = NULL; | |
816 | skb->len += frag_list_size; | |
817 | skb->data_len += frag_list_size; | |
818 | skb->truesize += frag_list_size; | |
819 | return skb; | |
820 | } | |
821 | ||
43634e82 MC |
822 | struct ixgbe_rsc_cb { |
823 | dma_addr_t dma; | |
824 | }; | |
825 | ||
826 | #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb) | |
827 | ||
78b6f4ce | 828 | static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
b4617240 PW |
829 | struct ixgbe_ring *rx_ring, |
830 | int *work_done, int work_to_do) | |
9a799d71 | 831 | { |
78b6f4ce | 832 | struct ixgbe_adapter *adapter = q_vector->adapter; |
2d86f139 | 833 | struct net_device *netdev = adapter->netdev; |
9a799d71 AK |
834 | struct pci_dev *pdev = adapter->pdev; |
835 | union ixgbe_adv_rx_desc *rx_desc, *next_rxd; | |
836 | struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer; | |
837 | struct sk_buff *skb; | |
f8212f97 | 838 | unsigned int i, rsc_count = 0; |
7c6e0a43 | 839 | u32 len, staterr; |
177db6ff MC |
840 | u16 hdr_info; |
841 | bool cleaned = false; | |
9a799d71 | 842 | int cleaned_count = 0; |
d2f4fbe2 | 843 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
3d8fd385 YZ |
844 | #ifdef IXGBE_FCOE |
845 | int ddp_bytes = 0; | |
846 | #endif /* IXGBE_FCOE */ | |
9a799d71 AK |
847 | |
848 | i = rx_ring->next_to_clean; | |
9a799d71 AK |
849 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); |
850 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
851 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
9a799d71 AK |
852 | |
853 | while (staterr & IXGBE_RXD_STAT_DD) { | |
7c6e0a43 | 854 | u32 upper_len = 0; |
9a799d71 AK |
855 | if (*work_done >= work_to_do) |
856 | break; | |
857 | (*work_done)++; | |
858 | ||
3c945e5b | 859 | rmb(); /* read descriptor and rx_buffer_info after status DD */ |
6e455b89 | 860 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) { |
7c6e0a43 JB |
861 | hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc)); |
862 | len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >> | |
762f4c57 | 863 | IXGBE_RXDADV_HDRBUFLEN_SHIFT; |
9a799d71 AK |
864 | if (len > IXGBE_RX_HDR_SIZE) |
865 | len = IXGBE_RX_HDR_SIZE; | |
866 | upper_len = le16_to_cpu(rx_desc->wb.upper.length); | |
7c6e0a43 | 867 | } else { |
9a799d71 | 868 | len = le16_to_cpu(rx_desc->wb.upper.length); |
7c6e0a43 | 869 | } |
9a799d71 AK |
870 | |
871 | cleaned = true; | |
872 | skb = rx_buffer_info->skb; | |
7ca3bc58 | 873 | prefetch(skb->data); |
9a799d71 AK |
874 | rx_buffer_info->skb = NULL; |
875 | ||
21fa4e66 | 876 | if (rx_buffer_info->dma) { |
43634e82 MC |
877 | if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) && |
878 | (!(staterr & IXGBE_RXD_STAT_EOP)) && | |
879 | (!(skb->prev))) | |
880 | /* | |
881 | * When HWRSC is enabled, delay unmapping | |
882 | * of the first packet. It carries the | |
883 | * header information, HW may still | |
884 | * access the header after the writeback. | |
885 | * Only unmap it when EOP is reached | |
886 | */ | |
887 | IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma; | |
888 | else | |
889 | pci_unmap_single(pdev, rx_buffer_info->dma, | |
890 | rx_ring->rx_buf_len, | |
891 | PCI_DMA_FROMDEVICE); | |
4f57ca6e | 892 | rx_buffer_info->dma = 0; |
9a799d71 AK |
893 | skb_put(skb, len); |
894 | } | |
895 | ||
896 | if (upper_len) { | |
897 | pci_unmap_page(pdev, rx_buffer_info->page_dma, | |
762f4c57 | 898 | PAGE_SIZE / 2, PCI_DMA_FROMDEVICE); |
9a799d71 AK |
899 | rx_buffer_info->page_dma = 0; |
900 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
762f4c57 JB |
901 | rx_buffer_info->page, |
902 | rx_buffer_info->page_offset, | |
903 | upper_len); | |
904 | ||
905 | if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) || | |
906 | (page_count(rx_buffer_info->page) != 1)) | |
907 | rx_buffer_info->page = NULL; | |
908 | else | |
909 | get_page(rx_buffer_info->page); | |
9a799d71 AK |
910 | |
911 | skb->len += upper_len; | |
912 | skb->data_len += upper_len; | |
913 | skb->truesize += upper_len; | |
914 | } | |
915 | ||
916 | i++; | |
917 | if (i == rx_ring->count) | |
918 | i = 0; | |
9a799d71 AK |
919 | |
920 | next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
921 | prefetch(next_rxd); | |
9a799d71 | 922 | cleaned_count++; |
f8212f97 | 923 | |
0c19d6af | 924 | if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) |
f8212f97 AD |
925 | rsc_count = ixgbe_get_rsc_count(rx_desc); |
926 | ||
927 | if (rsc_count) { | |
928 | u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >> | |
929 | IXGBE_RXDADV_NEXTP_SHIFT; | |
930 | next_buffer = &rx_ring->rx_buffer_info[nextp]; | |
f8212f97 AD |
931 | } else { |
932 | next_buffer = &rx_ring->rx_buffer_info[i]; | |
933 | } | |
934 | ||
9a799d71 | 935 | if (staterr & IXGBE_RXD_STAT_EOP) { |
f8212f97 | 936 | if (skb->prev) |
94b982b2 MC |
937 | skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count)); |
938 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { | |
fd3686a8 | 939 | if (IXGBE_RSC_CB(skb)->dma) { |
43634e82 MC |
940 | pci_unmap_single(pdev, IXGBE_RSC_CB(skb)->dma, |
941 | rx_ring->rx_buf_len, | |
942 | PCI_DMA_FROMDEVICE); | |
fd3686a8 MC |
943 | IXGBE_RSC_CB(skb)->dma = 0; |
944 | } | |
94b982b2 MC |
945 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) |
946 | rx_ring->rsc_count += skb_shinfo(skb)->nr_frags; | |
947 | else | |
948 | rx_ring->rsc_count++; | |
949 | rx_ring->rsc_flush++; | |
950 | } | |
9a799d71 AK |
951 | rx_ring->stats.packets++; |
952 | rx_ring->stats.bytes += skb->len; | |
953 | } else { | |
6e455b89 | 954 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) { |
f8212f97 AD |
955 | rx_buffer_info->skb = next_buffer->skb; |
956 | rx_buffer_info->dma = next_buffer->dma; | |
957 | next_buffer->skb = skb; | |
958 | next_buffer->dma = 0; | |
959 | } else { | |
960 | skb->next = next_buffer->skb; | |
961 | skb->next->prev = skb; | |
962 | } | |
7ca3bc58 | 963 | rx_ring->non_eop_descs++; |
9a799d71 AK |
964 | goto next_desc; |
965 | } | |
966 | ||
967 | if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) { | |
968 | dev_kfree_skb_irq(skb); | |
969 | goto next_desc; | |
970 | } | |
971 | ||
8bae1b2b | 972 | ixgbe_rx_checksum(adapter, rx_desc, skb); |
d2f4fbe2 AV |
973 | |
974 | /* probably a little skewed due to removing CRC */ | |
975 | total_rx_bytes += skb->len; | |
976 | total_rx_packets++; | |
977 | ||
74ce8dd2 | 978 | skb->protocol = eth_type_trans(skb, adapter->netdev); |
332d4a7d YZ |
979 | #ifdef IXGBE_FCOE |
980 | /* if ddp, not passing to ULD unless for FCP_RSP or error */ | |
3d8fd385 YZ |
981 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { |
982 | ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); | |
983 | if (!ddp_bytes) | |
332d4a7d | 984 | goto next_desc; |
3d8fd385 | 985 | } |
332d4a7d | 986 | #endif /* IXGBE_FCOE */ |
fdaff1ce | 987 | ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc); |
9a799d71 AK |
988 | |
989 | next_desc: | |
990 | rx_desc->wb.upper.status_error = 0; | |
991 | ||
992 | /* return some buffers to hardware, one at a time is too slow */ | |
993 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
994 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
995 | cleaned_count = 0; | |
996 | } | |
997 | ||
998 | /* use prefetched values */ | |
999 | rx_desc = next_rxd; | |
f8212f97 | 1000 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; |
9a799d71 AK |
1001 | |
1002 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
177db6ff MC |
1003 | } |
1004 | ||
9a799d71 AK |
1005 | rx_ring->next_to_clean = i; |
1006 | cleaned_count = IXGBE_DESC_UNUSED(rx_ring); | |
1007 | ||
1008 | if (cleaned_count) | |
1009 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
1010 | ||
3d8fd385 YZ |
1011 | #ifdef IXGBE_FCOE |
1012 | /* include DDPed FCoE data */ | |
1013 | if (ddp_bytes > 0) { | |
1014 | unsigned int mss; | |
1015 | ||
1016 | mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) - | |
1017 | sizeof(struct fc_frame_header) - | |
1018 | sizeof(struct fcoe_crc_eof); | |
1019 | if (mss > 512) | |
1020 | mss &= ~511; | |
1021 | total_rx_bytes += ddp_bytes; | |
1022 | total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss); | |
1023 | } | |
1024 | #endif /* IXGBE_FCOE */ | |
1025 | ||
f494e8fa AV |
1026 | rx_ring->total_packets += total_rx_packets; |
1027 | rx_ring->total_bytes += total_rx_bytes; | |
2d86f139 AK |
1028 | netdev->stats.rx_bytes += total_rx_bytes; |
1029 | netdev->stats.rx_packets += total_rx_packets; | |
f494e8fa | 1030 | |
9a799d71 AK |
1031 | return cleaned; |
1032 | } | |
1033 | ||
021230d4 | 1034 | static int ixgbe_clean_rxonly(struct napi_struct *, int); |
9a799d71 AK |
1035 | /** |
1036 | * ixgbe_configure_msix - Configure MSI-X hardware | |
1037 | * @adapter: board private structure | |
1038 | * | |
1039 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
1040 | * interrupts. | |
1041 | **/ | |
1042 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
1043 | { | |
021230d4 AV |
1044 | struct ixgbe_q_vector *q_vector; |
1045 | int i, j, q_vectors, v_idx, r_idx; | |
1046 | u32 mask; | |
9a799d71 | 1047 | |
021230d4 | 1048 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 | 1049 | |
4df10466 JB |
1050 | /* |
1051 | * Populate the IVAR table and set the ITR values to the | |
021230d4 AV |
1052 | * corresponding register. |
1053 | */ | |
1054 | for (v_idx = 0; v_idx < q_vectors; v_idx++) { | |
7a921c93 | 1055 | q_vector = adapter->q_vector[v_idx]; |
984b3f57 | 1056 | /* XXX for_each_set_bit(...) */ |
021230d4 | 1057 | r_idx = find_first_bit(q_vector->rxr_idx, |
b4617240 | 1058 | adapter->num_rx_queues); |
021230d4 AV |
1059 | |
1060 | for (i = 0; i < q_vector->rxr_count; i++) { | |
4a0b9ca0 | 1061 | j = adapter->rx_ring[r_idx]->reg_idx; |
e8e26350 | 1062 | ixgbe_set_ivar(adapter, 0, j, v_idx); |
021230d4 | 1063 | r_idx = find_next_bit(q_vector->rxr_idx, |
b4617240 PW |
1064 | adapter->num_rx_queues, |
1065 | r_idx + 1); | |
021230d4 AV |
1066 | } |
1067 | r_idx = find_first_bit(q_vector->txr_idx, | |
b4617240 | 1068 | adapter->num_tx_queues); |
021230d4 AV |
1069 | |
1070 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 1071 | j = adapter->tx_ring[r_idx]->reg_idx; |
e8e26350 | 1072 | ixgbe_set_ivar(adapter, 1, j, v_idx); |
021230d4 | 1073 | r_idx = find_next_bit(q_vector->txr_idx, |
b4617240 PW |
1074 | adapter->num_tx_queues, |
1075 | r_idx + 1); | |
021230d4 AV |
1076 | } |
1077 | ||
021230d4 | 1078 | if (q_vector->txr_count && !q_vector->rxr_count) |
f7554a2b NS |
1079 | /* tx only */ |
1080 | q_vector->eitr = adapter->tx_eitr_param; | |
509ee935 | 1081 | else if (q_vector->rxr_count) |
f7554a2b NS |
1082 | /* rx or mixed */ |
1083 | q_vector->eitr = adapter->rx_eitr_param; | |
021230d4 | 1084 | |
fe49f04a | 1085 | ixgbe_write_eitr(q_vector); |
9a799d71 AK |
1086 | } |
1087 | ||
e8e26350 PW |
1088 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) |
1089 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, | |
1090 | v_idx); | |
1091 | else if (adapter->hw.mac.type == ixgbe_mac_82599EB) | |
1092 | ixgbe_set_ivar(adapter, -1, 1, v_idx); | |
021230d4 AV |
1093 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
1094 | ||
41fb9248 | 1095 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 1096 | mask = IXGBE_EIMS_ENABLE_MASK; |
1cdd1ec8 GR |
1097 | if (adapter->num_vfs) |
1098 | mask &= ~(IXGBE_EIMS_OTHER | | |
1099 | IXGBE_EIMS_MAILBOX | | |
1100 | IXGBE_EIMS_LSC); | |
1101 | else | |
1102 | mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC); | |
021230d4 | 1103 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
1104 | } |
1105 | ||
f494e8fa AV |
1106 | enum latency_range { |
1107 | lowest_latency = 0, | |
1108 | low_latency = 1, | |
1109 | bulk_latency = 2, | |
1110 | latency_invalid = 255 | |
1111 | }; | |
1112 | ||
1113 | /** | |
1114 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
1115 | * @adapter: pointer to adapter | |
1116 | * @eitr: eitr setting (ints per sec) to give last timeslice | |
1117 | * @itr_setting: current throttle rate in ints/second | |
1118 | * @packets: the number of packets during this measurement interval | |
1119 | * @bytes: the number of bytes during this measurement interval | |
1120 | * | |
1121 | * Stores a new ITR value based on packets and byte | |
1122 | * counts during the last interrupt. The advantage of per interrupt | |
1123 | * computation is faster updates and more accurate ITR for the current | |
1124 | * traffic pattern. Constants in this function were computed | |
1125 | * based on theoretical maximum wire speed and thresholds were set based | |
1126 | * on testing data as well as attempting to minimize response time | |
1127 | * while increasing bulk throughput. | |
1128 | * this functionality is controlled by the InterruptThrottleRate module | |
1129 | * parameter (see ixgbe_param.c) | |
1130 | **/ | |
1131 | static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter, | |
b4617240 PW |
1132 | u32 eitr, u8 itr_setting, |
1133 | int packets, int bytes) | |
f494e8fa AV |
1134 | { |
1135 | unsigned int retval = itr_setting; | |
1136 | u32 timepassed_us; | |
1137 | u64 bytes_perint; | |
1138 | ||
1139 | if (packets == 0) | |
1140 | goto update_itr_done; | |
1141 | ||
1142 | ||
1143 | /* simple throttlerate management | |
1144 | * 0-20MB/s lowest (100000 ints/s) | |
1145 | * 20-100MB/s low (20000 ints/s) | |
1146 | * 100-1249MB/s bulk (8000 ints/s) | |
1147 | */ | |
1148 | /* what was last interrupt timeslice? */ | |
1149 | timepassed_us = 1000000/eitr; | |
1150 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ | |
1151 | ||
1152 | switch (itr_setting) { | |
1153 | case lowest_latency: | |
1154 | if (bytes_perint > adapter->eitr_low) | |
1155 | retval = low_latency; | |
1156 | break; | |
1157 | case low_latency: | |
1158 | if (bytes_perint > adapter->eitr_high) | |
1159 | retval = bulk_latency; | |
1160 | else if (bytes_perint <= adapter->eitr_low) | |
1161 | retval = lowest_latency; | |
1162 | break; | |
1163 | case bulk_latency: | |
1164 | if (bytes_perint <= adapter->eitr_high) | |
1165 | retval = low_latency; | |
1166 | break; | |
1167 | } | |
1168 | ||
1169 | update_itr_done: | |
1170 | return retval; | |
1171 | } | |
1172 | ||
509ee935 JB |
1173 | /** |
1174 | * ixgbe_write_eitr - write EITR register in hardware specific way | |
fe49f04a | 1175 | * @q_vector: structure containing interrupt and ring information |
509ee935 JB |
1176 | * |
1177 | * This function is made to be called by ethtool and by the driver | |
1178 | * when it needs to update EITR registers at runtime. Hardware | |
1179 | * specific quirks/differences are taken care of here. | |
1180 | */ | |
fe49f04a | 1181 | void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) |
509ee935 | 1182 | { |
fe49f04a | 1183 | struct ixgbe_adapter *adapter = q_vector->adapter; |
509ee935 | 1184 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
1185 | int v_idx = q_vector->v_idx; |
1186 | u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr); | |
1187 | ||
509ee935 JB |
1188 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
1189 | /* must write high and low 16 bits to reset counter */ | |
1190 | itr_reg |= (itr_reg << 16); | |
1191 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
1192 | /* | |
1193 | * set the WDIS bit to not clear the timer bits and cause an | |
1194 | * immediate assertion of the interrupt | |
1195 | */ | |
1196 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
1197 | } | |
1198 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); | |
1199 | } | |
1200 | ||
f494e8fa AV |
1201 | static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector) |
1202 | { | |
1203 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
f494e8fa AV |
1204 | u32 new_itr; |
1205 | u8 current_itr, ret_itr; | |
fe49f04a | 1206 | int i, r_idx; |
f494e8fa AV |
1207 | struct ixgbe_ring *rx_ring, *tx_ring; |
1208 | ||
1209 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1210 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 1211 | tx_ring = adapter->tx_ring[r_idx]; |
f494e8fa | 1212 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, |
b4617240 PW |
1213 | q_vector->tx_itr, |
1214 | tx_ring->total_packets, | |
1215 | tx_ring->total_bytes); | |
f494e8fa AV |
1216 | /* if the result for this queue would decrease interrupt |
1217 | * rate for this vector then use that result */ | |
30efa5a3 | 1218 | q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ? |
b4617240 | 1219 | q_vector->tx_itr - 1 : ret_itr); |
f494e8fa | 1220 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 1221 | r_idx + 1); |
f494e8fa AV |
1222 | } |
1223 | ||
1224 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1225 | for (i = 0; i < q_vector->rxr_count; i++) { | |
4a0b9ca0 | 1226 | rx_ring = adapter->rx_ring[r_idx]; |
f494e8fa | 1227 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, |
b4617240 PW |
1228 | q_vector->rx_itr, |
1229 | rx_ring->total_packets, | |
1230 | rx_ring->total_bytes); | |
f494e8fa AV |
1231 | /* if the result for this queue would decrease interrupt |
1232 | * rate for this vector then use that result */ | |
30efa5a3 | 1233 | q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ? |
b4617240 | 1234 | q_vector->rx_itr - 1 : ret_itr); |
f494e8fa | 1235 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
b4617240 | 1236 | r_idx + 1); |
f494e8fa AV |
1237 | } |
1238 | ||
30efa5a3 | 1239 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1240 | |
1241 | switch (current_itr) { | |
1242 | /* counts and packets in update_itr are dependent on these numbers */ | |
1243 | case lowest_latency: | |
1244 | new_itr = 100000; | |
1245 | break; | |
1246 | case low_latency: | |
1247 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1248 | break; | |
1249 | case bulk_latency: | |
1250 | default: | |
1251 | new_itr = 8000; | |
1252 | break; | |
1253 | } | |
1254 | ||
1255 | if (new_itr != q_vector->eitr) { | |
fe49f04a AD |
1256 | /* do an exponential smoothing */ |
1257 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
509ee935 JB |
1258 | |
1259 | /* save the algorithm value here, not the smoothed one */ | |
1260 | q_vector->eitr = new_itr; | |
fe49f04a AD |
1261 | |
1262 | ixgbe_write_eitr(q_vector); | |
f494e8fa AV |
1263 | } |
1264 | ||
1265 | return; | |
1266 | } | |
1267 | ||
0befdb3e JB |
1268 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
1269 | { | |
1270 | struct ixgbe_hw *hw = &adapter->hw; | |
1271 | ||
1272 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
1273 | (eicr & IXGBE_EICR_GPI_SDP1)) { | |
1274 | DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n"); | |
1275 | /* write to clear the interrupt */ | |
1276 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
1277 | } | |
1278 | } | |
cf8280ee | 1279 | |
e8e26350 PW |
1280 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
1281 | { | |
1282 | struct ixgbe_hw *hw = &adapter->hw; | |
1283 | ||
1284 | if (eicr & IXGBE_EICR_GPI_SDP1) { | |
1285 | /* Clear the interrupt */ | |
1286 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
1287 | schedule_work(&adapter->multispeed_fiber_task); | |
1288 | } else if (eicr & IXGBE_EICR_GPI_SDP2) { | |
1289 | /* Clear the interrupt */ | |
1290 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); | |
1291 | schedule_work(&adapter->sfp_config_module_task); | |
1292 | } else { | |
1293 | /* Interrupt isn't for us... */ | |
1294 | return; | |
1295 | } | |
1296 | } | |
1297 | ||
cf8280ee JB |
1298 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
1299 | { | |
1300 | struct ixgbe_hw *hw = &adapter->hw; | |
1301 | ||
1302 | adapter->lsc_int++; | |
1303 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
1304 | adapter->link_check_timeout = jiffies; | |
1305 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
1306 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
8a0717f3 | 1307 | IXGBE_WRITE_FLUSH(hw); |
cf8280ee JB |
1308 | schedule_work(&adapter->watchdog_task); |
1309 | } | |
1310 | } | |
1311 | ||
9a799d71 AK |
1312 | static irqreturn_t ixgbe_msix_lsc(int irq, void *data) |
1313 | { | |
1314 | struct net_device *netdev = data; | |
1315 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1316 | struct ixgbe_hw *hw = &adapter->hw; | |
54037505 DS |
1317 | u32 eicr; |
1318 | ||
1319 | /* | |
1320 | * Workaround for Silicon errata. Use clear-by-write instead | |
1321 | * of clear-by-read. Reading with EICS will return the | |
1322 | * interrupt causes without clearing, which later be done | |
1323 | * with the write to EICR. | |
1324 | */ | |
1325 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
1326 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); | |
9a799d71 | 1327 | |
cf8280ee JB |
1328 | if (eicr & IXGBE_EICR_LSC) |
1329 | ixgbe_check_lsc(adapter); | |
d4f80882 | 1330 | |
1cdd1ec8 GR |
1331 | if (eicr & IXGBE_EICR_MAILBOX) |
1332 | ixgbe_msg_task(adapter); | |
1333 | ||
e8e26350 PW |
1334 | if (hw->mac.type == ixgbe_mac_82598EB) |
1335 | ixgbe_check_fan_failure(adapter, eicr); | |
0befdb3e | 1336 | |
c4cf55e5 | 1337 | if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 | 1338 | ixgbe_check_sfp_event(adapter, eicr); |
c4cf55e5 PWJ |
1339 | |
1340 | /* Handle Flow Director Full threshold interrupt */ | |
1341 | if (eicr & IXGBE_EICR_FLOW_DIR) { | |
1342 | int i; | |
1343 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR); | |
1344 | /* Disable transmits before FDIR Re-initialization */ | |
1345 | netif_tx_stop_all_queues(netdev); | |
1346 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
1347 | struct ixgbe_ring *tx_ring = | |
4a0b9ca0 | 1348 | adapter->tx_ring[i]; |
c4cf55e5 PWJ |
1349 | if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE, |
1350 | &tx_ring->reinit_state)) | |
1351 | schedule_work(&adapter->fdir_reinit_task); | |
1352 | } | |
1353 | } | |
1354 | } | |
d4f80882 AV |
1355 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
1356 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER); | |
9a799d71 AK |
1357 | |
1358 | return IRQ_HANDLED; | |
1359 | } | |
1360 | ||
fe49f04a AD |
1361 | static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, |
1362 | u64 qmask) | |
1363 | { | |
1364 | u32 mask; | |
1365 | ||
1366 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
1367 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); | |
1368 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); | |
1369 | } else { | |
1370 | mask = (qmask & 0xFFFFFFFF); | |
1371 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask); | |
1372 | mask = (qmask >> 32); | |
1373 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask); | |
1374 | } | |
1375 | /* skip the flush */ | |
1376 | } | |
1377 | ||
1378 | static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, | |
1379 | u64 qmask) | |
1380 | { | |
1381 | u32 mask; | |
1382 | ||
1383 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
1384 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); | |
1385 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask); | |
1386 | } else { | |
1387 | mask = (qmask & 0xFFFFFFFF); | |
1388 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask); | |
1389 | mask = (qmask >> 32); | |
1390 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask); | |
1391 | } | |
1392 | /* skip the flush */ | |
1393 | } | |
1394 | ||
9a799d71 AK |
1395 | static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data) |
1396 | { | |
021230d4 AV |
1397 | struct ixgbe_q_vector *q_vector = data; |
1398 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 1399 | struct ixgbe_ring *tx_ring; |
021230d4 AV |
1400 | int i, r_idx; |
1401 | ||
1402 | if (!q_vector->txr_count) | |
1403 | return IRQ_HANDLED; | |
1404 | ||
1405 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1406 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 1407 | tx_ring = adapter->tx_ring[r_idx]; |
3a581073 JB |
1408 | tx_ring->total_bytes = 0; |
1409 | tx_ring->total_packets = 0; | |
021230d4 | 1410 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 1411 | r_idx + 1); |
021230d4 | 1412 | } |
9a799d71 | 1413 | |
9b471446 | 1414 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 AD |
1415 | napi_schedule(&q_vector->napi); |
1416 | ||
9a799d71 AK |
1417 | return IRQ_HANDLED; |
1418 | } | |
1419 | ||
021230d4 AV |
1420 | /** |
1421 | * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues) | |
1422 | * @irq: unused | |
1423 | * @data: pointer to our q_vector struct for this interrupt vector | |
1424 | **/ | |
9a799d71 AK |
1425 | static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data) |
1426 | { | |
021230d4 AV |
1427 | struct ixgbe_q_vector *q_vector = data; |
1428 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 1429 | struct ixgbe_ring *rx_ring; |
021230d4 | 1430 | int r_idx; |
30efa5a3 | 1431 | int i; |
021230d4 AV |
1432 | |
1433 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
30efa5a3 | 1434 | for (i = 0; i < q_vector->rxr_count; i++) { |
4a0b9ca0 | 1435 | rx_ring = adapter->rx_ring[r_idx]; |
30efa5a3 JB |
1436 | rx_ring->total_bytes = 0; |
1437 | rx_ring->total_packets = 0; | |
1438 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1439 | r_idx + 1); | |
1440 | } | |
1441 | ||
021230d4 AV |
1442 | if (!q_vector->rxr_count) |
1443 | return IRQ_HANDLED; | |
1444 | ||
021230d4 | 1445 | /* disable interrupts on this vector only */ |
9b471446 | 1446 | /* EIAM disabled interrupts (on this vector) for us */ |
288379f0 | 1447 | napi_schedule(&q_vector->napi); |
021230d4 AV |
1448 | |
1449 | return IRQ_HANDLED; | |
1450 | } | |
1451 | ||
1452 | static irqreturn_t ixgbe_msix_clean_many(int irq, void *data) | |
1453 | { | |
91281fd3 AD |
1454 | struct ixgbe_q_vector *q_vector = data; |
1455 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
1456 | struct ixgbe_ring *ring; | |
1457 | int r_idx; | |
1458 | int i; | |
1459 | ||
1460 | if (!q_vector->txr_count && !q_vector->rxr_count) | |
1461 | return IRQ_HANDLED; | |
1462 | ||
1463 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1464 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 1465 | ring = adapter->tx_ring[r_idx]; |
91281fd3 AD |
1466 | ring->total_bytes = 0; |
1467 | ring->total_packets = 0; | |
1468 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, | |
1469 | r_idx + 1); | |
1470 | } | |
1471 | ||
1472 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1473 | for (i = 0; i < q_vector->rxr_count; i++) { | |
4a0b9ca0 | 1474 | ring = adapter->rx_ring[r_idx]; |
91281fd3 AD |
1475 | ring->total_bytes = 0; |
1476 | ring->total_packets = 0; | |
1477 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1478 | r_idx + 1); | |
1479 | } | |
1480 | ||
9b471446 | 1481 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 | 1482 | napi_schedule(&q_vector->napi); |
9a799d71 | 1483 | |
9a799d71 AK |
1484 | return IRQ_HANDLED; |
1485 | } | |
1486 | ||
021230d4 AV |
1487 | /** |
1488 | * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine | |
1489 | * @napi: napi struct with our devices info in it | |
1490 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1491 | * | |
f0848276 JB |
1492 | * This function is optimized for cleaning one queue only on a single |
1493 | * q_vector!!! | |
021230d4 | 1494 | **/ |
9a799d71 AK |
1495 | static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget) |
1496 | { | |
021230d4 | 1497 | struct ixgbe_q_vector *q_vector = |
b4617240 | 1498 | container_of(napi, struct ixgbe_q_vector, napi); |
021230d4 | 1499 | struct ixgbe_adapter *adapter = q_vector->adapter; |
f0848276 | 1500 | struct ixgbe_ring *rx_ring = NULL; |
9a799d71 | 1501 | int work_done = 0; |
021230d4 | 1502 | long r_idx; |
9a799d71 | 1503 | |
021230d4 | 1504 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
4a0b9ca0 | 1505 | rx_ring = adapter->rx_ring[r_idx]; |
5dd2d332 | 1506 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 1507 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
3a581073 | 1508 | ixgbe_update_rx_dca(adapter, rx_ring); |
bd0362dd | 1509 | #endif |
9a799d71 | 1510 | |
78b6f4ce | 1511 | ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget); |
9a799d71 | 1512 | |
021230d4 AV |
1513 | /* If all Rx work done, exit the polling mode */ |
1514 | if (work_done < budget) { | |
288379f0 | 1515 | napi_complete(napi); |
f7554a2b | 1516 | if (adapter->rx_itr_setting & 1) |
f494e8fa | 1517 | ixgbe_set_itr_msix(q_vector); |
9a799d71 | 1518 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
fe49f04a AD |
1519 | ixgbe_irq_enable_queues(adapter, |
1520 | ((u64)1 << q_vector->v_idx)); | |
9a799d71 AK |
1521 | } |
1522 | ||
1523 | return work_done; | |
1524 | } | |
1525 | ||
f0848276 | 1526 | /** |
91281fd3 | 1527 | * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine |
f0848276 JB |
1528 | * @napi: napi struct with our devices info in it |
1529 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1530 | * | |
1531 | * This function will clean more than one rx queue associated with a | |
1532 | * q_vector. | |
1533 | **/ | |
91281fd3 | 1534 | static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget) |
f0848276 JB |
1535 | { |
1536 | struct ixgbe_q_vector *q_vector = | |
1537 | container_of(napi, struct ixgbe_q_vector, napi); | |
1538 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
91281fd3 | 1539 | struct ixgbe_ring *ring = NULL; |
f0848276 JB |
1540 | int work_done = 0, i; |
1541 | long r_idx; | |
91281fd3 AD |
1542 | bool tx_clean_complete = true; |
1543 | ||
1544 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1545 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 1546 | ring = adapter->tx_ring[r_idx]; |
91281fd3 AD |
1547 | #ifdef CONFIG_IXGBE_DCA |
1548 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
1549 | ixgbe_update_tx_dca(adapter, ring); | |
1550 | #endif | |
1551 | tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring); | |
1552 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, | |
1553 | r_idx + 1); | |
1554 | } | |
f0848276 JB |
1555 | |
1556 | /* attempt to distribute budget to each queue fairly, but don't allow | |
1557 | * the budget to go below 1 because we'll exit polling */ | |
1558 | budget /= (q_vector->rxr_count ?: 1); | |
1559 | budget = max(budget, 1); | |
1560 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1561 | for (i = 0; i < q_vector->rxr_count; i++) { | |
4a0b9ca0 | 1562 | ring = adapter->rx_ring[r_idx]; |
5dd2d332 | 1563 | #ifdef CONFIG_IXGBE_DCA |
f0848276 | 1564 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
91281fd3 | 1565 | ixgbe_update_rx_dca(adapter, ring); |
f0848276 | 1566 | #endif |
91281fd3 | 1567 | ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget); |
f0848276 JB |
1568 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
1569 | r_idx + 1); | |
1570 | } | |
1571 | ||
1572 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
4a0b9ca0 | 1573 | ring = adapter->rx_ring[r_idx]; |
f0848276 | 1574 | /* If all Rx work done, exit the polling mode */ |
7f821875 | 1575 | if (work_done < budget) { |
288379f0 | 1576 | napi_complete(napi); |
f7554a2b | 1577 | if (adapter->rx_itr_setting & 1) |
f0848276 JB |
1578 | ixgbe_set_itr_msix(q_vector); |
1579 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
fe49f04a AD |
1580 | ixgbe_irq_enable_queues(adapter, |
1581 | ((u64)1 << q_vector->v_idx)); | |
f0848276 JB |
1582 | return 0; |
1583 | } | |
1584 | ||
1585 | return work_done; | |
1586 | } | |
91281fd3 AD |
1587 | |
1588 | /** | |
1589 | * ixgbe_clean_txonly - msix (aka one shot) tx clean routine | |
1590 | * @napi: napi struct with our devices info in it | |
1591 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1592 | * | |
1593 | * This function is optimized for cleaning one queue only on a single | |
1594 | * q_vector!!! | |
1595 | **/ | |
1596 | static int ixgbe_clean_txonly(struct napi_struct *napi, int budget) | |
1597 | { | |
1598 | struct ixgbe_q_vector *q_vector = | |
1599 | container_of(napi, struct ixgbe_q_vector, napi); | |
1600 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
1601 | struct ixgbe_ring *tx_ring = NULL; | |
1602 | int work_done = 0; | |
1603 | long r_idx; | |
1604 | ||
1605 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
4a0b9ca0 | 1606 | tx_ring = adapter->tx_ring[r_idx]; |
91281fd3 AD |
1607 | #ifdef CONFIG_IXGBE_DCA |
1608 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
1609 | ixgbe_update_tx_dca(adapter, tx_ring); | |
1610 | #endif | |
1611 | ||
1612 | if (!ixgbe_clean_tx_irq(q_vector, tx_ring)) | |
1613 | work_done = budget; | |
1614 | ||
f7554a2b | 1615 | /* If all Tx work done, exit the polling mode */ |
91281fd3 AD |
1616 | if (work_done < budget) { |
1617 | napi_complete(napi); | |
f7554a2b | 1618 | if (adapter->tx_itr_setting & 1) |
91281fd3 AD |
1619 | ixgbe_set_itr_msix(q_vector); |
1620 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
1621 | ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
1622 | } | |
1623 | ||
1624 | return work_done; | |
1625 | } | |
1626 | ||
021230d4 | 1627 | static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx, |
b4617240 | 1628 | int r_idx) |
021230d4 | 1629 | { |
7a921c93 AD |
1630 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
1631 | ||
1632 | set_bit(r_idx, q_vector->rxr_idx); | |
1633 | q_vector->rxr_count++; | |
021230d4 AV |
1634 | } |
1635 | ||
1636 | static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx, | |
7a921c93 | 1637 | int t_idx) |
021230d4 | 1638 | { |
7a921c93 AD |
1639 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
1640 | ||
1641 | set_bit(t_idx, q_vector->txr_idx); | |
1642 | q_vector->txr_count++; | |
021230d4 AV |
1643 | } |
1644 | ||
9a799d71 | 1645 | /** |
021230d4 AV |
1646 | * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors |
1647 | * @adapter: board private structure to initialize | |
1648 | * @vectors: allotted vector count for descriptor rings | |
9a799d71 | 1649 | * |
021230d4 AV |
1650 | * This function maps descriptor rings to the queue-specific vectors |
1651 | * we were allotted through the MSI-X enabling code. Ideally, we'd have | |
1652 | * one vector per ring/queue, but on a constrained vector budget, we | |
1653 | * group the rings as "efficiently" as possible. You would add new | |
1654 | * mapping configurations in here. | |
9a799d71 | 1655 | **/ |
021230d4 | 1656 | static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 1657 | int vectors) |
021230d4 AV |
1658 | { |
1659 | int v_start = 0; | |
1660 | int rxr_idx = 0, txr_idx = 0; | |
1661 | int rxr_remaining = adapter->num_rx_queues; | |
1662 | int txr_remaining = adapter->num_tx_queues; | |
1663 | int i, j; | |
1664 | int rqpv, tqpv; | |
1665 | int err = 0; | |
1666 | ||
1667 | /* No mapping required if MSI-X is disabled. */ | |
1668 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
1669 | goto out; | |
9a799d71 | 1670 | |
021230d4 AV |
1671 | /* |
1672 | * The ideal configuration... | |
1673 | * We have enough vectors to map one per queue. | |
1674 | */ | |
1675 | if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) { | |
1676 | for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++) | |
1677 | map_vector_to_rxq(adapter, v_start, rxr_idx); | |
9a799d71 | 1678 | |
021230d4 AV |
1679 | for (; txr_idx < txr_remaining; v_start++, txr_idx++) |
1680 | map_vector_to_txq(adapter, v_start, txr_idx); | |
9a799d71 | 1681 | |
9a799d71 | 1682 | goto out; |
021230d4 | 1683 | } |
9a799d71 | 1684 | |
021230d4 AV |
1685 | /* |
1686 | * If we don't have enough vectors for a 1-to-1 | |
1687 | * mapping, we'll have to group them so there are | |
1688 | * multiple queues per vector. | |
1689 | */ | |
1690 | /* Re-adjusting *qpv takes care of the remainder. */ | |
1691 | for (i = v_start; i < vectors; i++) { | |
1692 | rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i); | |
1693 | for (j = 0; j < rqpv; j++) { | |
1694 | map_vector_to_rxq(adapter, i, rxr_idx); | |
1695 | rxr_idx++; | |
1696 | rxr_remaining--; | |
1697 | } | |
1698 | } | |
1699 | for (i = v_start; i < vectors; i++) { | |
1700 | tqpv = DIV_ROUND_UP(txr_remaining, vectors - i); | |
1701 | for (j = 0; j < tqpv; j++) { | |
1702 | map_vector_to_txq(adapter, i, txr_idx); | |
1703 | txr_idx++; | |
1704 | txr_remaining--; | |
9a799d71 | 1705 | } |
9a799d71 AK |
1706 | } |
1707 | ||
021230d4 AV |
1708 | out: |
1709 | return err; | |
1710 | } | |
1711 | ||
1712 | /** | |
1713 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
1714 | * @adapter: board private structure | |
1715 | * | |
1716 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
1717 | * interrupts from the kernel. | |
1718 | **/ | |
1719 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
1720 | { | |
1721 | struct net_device *netdev = adapter->netdev; | |
1722 | irqreturn_t (*handler)(int, void *); | |
1723 | int i, vector, q_vectors, err; | |
cb13fc20 | 1724 | int ri=0, ti=0; |
021230d4 AV |
1725 | |
1726 | /* Decrement for Other and TCP Timer vectors */ | |
1727 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1728 | ||
1729 | /* Map the Tx/Rx rings to the vectors we were allotted. */ | |
1730 | err = ixgbe_map_rings_to_vectors(adapter, q_vectors); | |
1731 | if (err) | |
1732 | goto out; | |
1733 | ||
1734 | #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \ | |
b4617240 PW |
1735 | (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \ |
1736 | &ixgbe_msix_clean_many) | |
021230d4 | 1737 | for (vector = 0; vector < q_vectors; vector++) { |
7a921c93 | 1738 | handler = SET_HANDLER(adapter->q_vector[vector]); |
cb13fc20 RO |
1739 | |
1740 | if(handler == &ixgbe_msix_clean_rx) { | |
1741 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1742 | netdev->name, "rx", ri++); | |
1743 | } | |
1744 | else if(handler == &ixgbe_msix_clean_tx) { | |
1745 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1746 | netdev->name, "tx", ti++); | |
1747 | } | |
1748 | else | |
1749 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1750 | netdev->name, "TxRx", vector); | |
1751 | ||
021230d4 | 1752 | err = request_irq(adapter->msix_entries[vector].vector, |
b4617240 | 1753 | handler, 0, adapter->name[vector], |
7a921c93 | 1754 | adapter->q_vector[vector]); |
9a799d71 AK |
1755 | if (err) { |
1756 | DPRINTK(PROBE, ERR, | |
b4617240 PW |
1757 | "request_irq failed for MSIX interrupt " |
1758 | "Error: %d\n", err); | |
021230d4 | 1759 | goto free_queue_irqs; |
9a799d71 | 1760 | } |
9a799d71 AK |
1761 | } |
1762 | ||
021230d4 AV |
1763 | sprintf(adapter->name[vector], "%s:lsc", netdev->name); |
1764 | err = request_irq(adapter->msix_entries[vector].vector, | |
a0607fd3 | 1765 | ixgbe_msix_lsc, 0, adapter->name[vector], netdev); |
9a799d71 AK |
1766 | if (err) { |
1767 | DPRINTK(PROBE, ERR, | |
1768 | "request_irq for msix_lsc failed: %d\n", err); | |
021230d4 | 1769 | goto free_queue_irqs; |
9a799d71 AK |
1770 | } |
1771 | ||
9a799d71 AK |
1772 | return 0; |
1773 | ||
021230d4 AV |
1774 | free_queue_irqs: |
1775 | for (i = vector - 1; i >= 0; i--) | |
1776 | free_irq(adapter->msix_entries[--vector].vector, | |
7a921c93 | 1777 | adapter->q_vector[i]); |
021230d4 AV |
1778 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
1779 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
1780 | kfree(adapter->msix_entries); |
1781 | adapter->msix_entries = NULL; | |
021230d4 | 1782 | out: |
9a799d71 AK |
1783 | return err; |
1784 | } | |
1785 | ||
f494e8fa AV |
1786 | static void ixgbe_set_itr(struct ixgbe_adapter *adapter) |
1787 | { | |
7a921c93 | 1788 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
f494e8fa AV |
1789 | u8 current_itr; |
1790 | u32 new_itr = q_vector->eitr; | |
4a0b9ca0 PW |
1791 | struct ixgbe_ring *rx_ring = adapter->rx_ring[0]; |
1792 | struct ixgbe_ring *tx_ring = adapter->tx_ring[0]; | |
f494e8fa | 1793 | |
30efa5a3 | 1794 | q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
1795 | q_vector->tx_itr, |
1796 | tx_ring->total_packets, | |
1797 | tx_ring->total_bytes); | |
30efa5a3 | 1798 | q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
1799 | q_vector->rx_itr, |
1800 | rx_ring->total_packets, | |
1801 | rx_ring->total_bytes); | |
f494e8fa | 1802 | |
30efa5a3 | 1803 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1804 | |
1805 | switch (current_itr) { | |
1806 | /* counts and packets in update_itr are dependent on these numbers */ | |
1807 | case lowest_latency: | |
1808 | new_itr = 100000; | |
1809 | break; | |
1810 | case low_latency: | |
1811 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1812 | break; | |
1813 | case bulk_latency: | |
1814 | new_itr = 8000; | |
1815 | break; | |
1816 | default: | |
1817 | break; | |
1818 | } | |
1819 | ||
1820 | if (new_itr != q_vector->eitr) { | |
fe49f04a AD |
1821 | /* do an exponential smoothing */ |
1822 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
509ee935 JB |
1823 | |
1824 | /* save the algorithm value here, not the smoothed one */ | |
1825 | q_vector->eitr = new_itr; | |
fe49f04a AD |
1826 | |
1827 | ixgbe_write_eitr(q_vector); | |
f494e8fa AV |
1828 | } |
1829 | ||
1830 | return; | |
1831 | } | |
1832 | ||
79aefa45 AD |
1833 | /** |
1834 | * ixgbe_irq_enable - Enable default interrupt generation settings | |
1835 | * @adapter: board private structure | |
1836 | **/ | |
1837 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter) | |
1838 | { | |
1839 | u32 mask; | |
835462fc NS |
1840 | |
1841 | mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); | |
6ab33d51 DM |
1842 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
1843 | mask |= IXGBE_EIMS_GPI_SDP1; | |
e8e26350 | 1844 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
2a41ff81 | 1845 | mask |= IXGBE_EIMS_ECC; |
e8e26350 PW |
1846 | mask |= IXGBE_EIMS_GPI_SDP1; |
1847 | mask |= IXGBE_EIMS_GPI_SDP2; | |
1cdd1ec8 GR |
1848 | if (adapter->num_vfs) |
1849 | mask |= IXGBE_EIMS_MAILBOX; | |
e8e26350 | 1850 | } |
c4cf55e5 PWJ |
1851 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
1852 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
1853 | mask |= IXGBE_EIMS_FLOW_DIR; | |
e8e26350 | 1854 | |
79aefa45 | 1855 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
835462fc | 1856 | ixgbe_irq_enable_queues(adapter, ~0); |
79aefa45 | 1857 | IXGBE_WRITE_FLUSH(&adapter->hw); |
1cdd1ec8 GR |
1858 | |
1859 | if (adapter->num_vfs > 32) { | |
1860 | u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1; | |
1861 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); | |
1862 | } | |
79aefa45 | 1863 | } |
021230d4 | 1864 | |
9a799d71 | 1865 | /** |
021230d4 | 1866 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
1867 | * @irq: interrupt number |
1868 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
1869 | **/ |
1870 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
1871 | { | |
1872 | struct net_device *netdev = data; | |
1873 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1874 | struct ixgbe_hw *hw = &adapter->hw; | |
7a921c93 | 1875 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 AK |
1876 | u32 eicr; |
1877 | ||
54037505 DS |
1878 | /* |
1879 | * Workaround for silicon errata. Mask the interrupts | |
1880 | * before the read of EICR. | |
1881 | */ | |
1882 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
1883 | ||
021230d4 AV |
1884 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
1885 | * therefore no explict interrupt disable is necessary */ | |
1886 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); | |
f47cf66e JB |
1887 | if (!eicr) { |
1888 | /* shared interrupt alert! | |
1889 | * make sure interrupts are enabled because the read will | |
1890 | * have disabled interrupts due to EIAM */ | |
1891 | ixgbe_irq_enable(adapter); | |
9a799d71 | 1892 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 1893 | } |
9a799d71 | 1894 | |
cf8280ee JB |
1895 | if (eicr & IXGBE_EICR_LSC) |
1896 | ixgbe_check_lsc(adapter); | |
021230d4 | 1897 | |
e8e26350 PW |
1898 | if (hw->mac.type == ixgbe_mac_82599EB) |
1899 | ixgbe_check_sfp_event(adapter, eicr); | |
1900 | ||
0befdb3e JB |
1901 | ixgbe_check_fan_failure(adapter, eicr); |
1902 | ||
7a921c93 | 1903 | if (napi_schedule_prep(&(q_vector->napi))) { |
4a0b9ca0 PW |
1904 | adapter->tx_ring[0]->total_packets = 0; |
1905 | adapter->tx_ring[0]->total_bytes = 0; | |
1906 | adapter->rx_ring[0]->total_packets = 0; | |
1907 | adapter->rx_ring[0]->total_bytes = 0; | |
021230d4 | 1908 | /* would disable interrupts here but EIAM disabled it */ |
7a921c93 | 1909 | __napi_schedule(&(q_vector->napi)); |
9a799d71 AK |
1910 | } |
1911 | ||
1912 | return IRQ_HANDLED; | |
1913 | } | |
1914 | ||
021230d4 AV |
1915 | static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter) |
1916 | { | |
1917 | int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1918 | ||
1919 | for (i = 0; i < q_vectors; i++) { | |
7a921c93 | 1920 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; |
021230d4 AV |
1921 | bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES); |
1922 | bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES); | |
1923 | q_vector->rxr_count = 0; | |
1924 | q_vector->txr_count = 0; | |
1925 | } | |
1926 | } | |
1927 | ||
9a799d71 AK |
1928 | /** |
1929 | * ixgbe_request_irq - initialize interrupts | |
1930 | * @adapter: board private structure | |
1931 | * | |
1932 | * Attempts to configure interrupts using the best available | |
1933 | * capabilities of the hardware and kernel. | |
1934 | **/ | |
021230d4 | 1935 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
1936 | { |
1937 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 1938 | int err; |
9a799d71 | 1939 | |
021230d4 AV |
1940 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
1941 | err = ixgbe_request_msix_irqs(adapter); | |
1942 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
a0607fd3 | 1943 | err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, |
b4617240 | 1944 | netdev->name, netdev); |
021230d4 | 1945 | } else { |
a0607fd3 | 1946 | err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, |
b4617240 | 1947 | netdev->name, netdev); |
9a799d71 AK |
1948 | } |
1949 | ||
9a799d71 AK |
1950 | if (err) |
1951 | DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err); | |
1952 | ||
9a799d71 AK |
1953 | return err; |
1954 | } | |
1955 | ||
1956 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
1957 | { | |
1958 | struct net_device *netdev = adapter->netdev; | |
1959 | ||
1960 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
021230d4 | 1961 | int i, q_vectors; |
9a799d71 | 1962 | |
021230d4 AV |
1963 | q_vectors = adapter->num_msix_vectors; |
1964 | ||
1965 | i = q_vectors - 1; | |
9a799d71 | 1966 | free_irq(adapter->msix_entries[i].vector, netdev); |
9a799d71 | 1967 | |
021230d4 AV |
1968 | i--; |
1969 | for (; i >= 0; i--) { | |
1970 | free_irq(adapter->msix_entries[i].vector, | |
7a921c93 | 1971 | adapter->q_vector[i]); |
021230d4 AV |
1972 | } |
1973 | ||
1974 | ixgbe_reset_q_vectors(adapter); | |
1975 | } else { | |
1976 | free_irq(adapter->pdev->irq, netdev); | |
9a799d71 AK |
1977 | } |
1978 | } | |
1979 | ||
22d5a71b JB |
1980 | /** |
1981 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
1982 | * @adapter: board private structure | |
1983 | **/ | |
1984 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
1985 | { | |
835462fc NS |
1986 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
1987 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); | |
1988 | } else { | |
1989 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); | |
1990 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); | |
22d5a71b | 1991 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); |
1cdd1ec8 GR |
1992 | if (adapter->num_vfs > 32) |
1993 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); | |
22d5a71b JB |
1994 | } |
1995 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
1996 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
1997 | int i; | |
1998 | for (i = 0; i < adapter->num_msix_vectors; i++) | |
1999 | synchronize_irq(adapter->msix_entries[i].vector); | |
2000 | } else { | |
2001 | synchronize_irq(adapter->pdev->irq); | |
2002 | } | |
2003 | } | |
2004 | ||
9a799d71 AK |
2005 | /** |
2006 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
2007 | * | |
2008 | **/ | |
2009 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
2010 | { | |
9a799d71 AK |
2011 | struct ixgbe_hw *hw = &adapter->hw; |
2012 | ||
021230d4 | 2013 | IXGBE_WRITE_REG(hw, IXGBE_EITR(0), |
f7554a2b | 2014 | EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param)); |
9a799d71 | 2015 | |
e8e26350 PW |
2016 | ixgbe_set_ivar(adapter, 0, 0, 0); |
2017 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 AV |
2018 | |
2019 | map_vector_to_rxq(adapter, 0, 0); | |
2020 | map_vector_to_txq(adapter, 0, 0); | |
2021 | ||
2022 | DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n"); | |
9a799d71 AK |
2023 | } |
2024 | ||
2025 | /** | |
3a581073 | 2026 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
2027 | * @adapter: board private structure |
2028 | * | |
2029 | * Configure the Tx unit of the MAC after a reset. | |
2030 | **/ | |
2031 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
2032 | { | |
12207e49 | 2033 | u64 tdba; |
9a799d71 | 2034 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 2035 | u32 i, j, tdlen, txctrl; |
9a799d71 AK |
2036 | |
2037 | /* Setup the HW Tx Head and Tail descriptor pointers */ | |
2038 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 2039 | struct ixgbe_ring *ring = adapter->tx_ring[i]; |
e01c31a5 JB |
2040 | j = ring->reg_idx; |
2041 | tdba = ring->dma; | |
2042 | tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc); | |
021230d4 | 2043 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j), |
284901a9 | 2044 | (tdba & DMA_BIT_MASK(32))); |
021230d4 AV |
2045 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32)); |
2046 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen); | |
2047 | IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0); | |
2048 | IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0); | |
4a0b9ca0 PW |
2049 | adapter->tx_ring[i]->head = IXGBE_TDH(j); |
2050 | adapter->tx_ring[i]->tail = IXGBE_TDT(j); | |
84f62d4b PWJ |
2051 | /* |
2052 | * Disable Tx Head Writeback RO bit, since this hoses | |
021230d4 AV |
2053 | * bookkeeping if things aren't delivered in order. |
2054 | */ | |
84f62d4b PWJ |
2055 | switch (hw->mac.type) { |
2056 | case ixgbe_mac_82598EB: | |
2057 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j)); | |
2058 | break; | |
2059 | case ixgbe_mac_82599EB: | |
2060 | default: | |
2061 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j)); | |
2062 | break; | |
2063 | } | |
021230d4 | 2064 | txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; |
84f62d4b PWJ |
2065 | switch (hw->mac.type) { |
2066 | case ixgbe_mac_82598EB: | |
2067 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl); | |
2068 | break; | |
2069 | case ixgbe_mac_82599EB: | |
2070 | default: | |
2071 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl); | |
2072 | break; | |
2073 | } | |
9a799d71 | 2074 | } |
ee5f784a | 2075 | |
e8e26350 | 2076 | if (hw->mac.type == ixgbe_mac_82599EB) { |
ee5f784a | 2077 | u32 rttdcs; |
1cdd1ec8 | 2078 | u32 mask; |
ee5f784a DS |
2079 | |
2080 | /* disable the arbiter while setting MTQC */ | |
2081 | rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); | |
2082 | rttdcs |= IXGBE_RTTDCS_ARBDIS; | |
2083 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2084 | ||
1cdd1ec8 GR |
2085 | /* set transmit pool layout */ |
2086 | mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED); | |
2087 | switch (adapter->flags & mask) { | |
2088 | ||
2089 | case (IXGBE_FLAG_SRIOV_ENABLED): | |
2090 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, | |
2091 | (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF)); | |
2092 | break; | |
2093 | ||
2094 | case (IXGBE_FLAG_DCB_ENABLED): | |
2095 | /* We enable 8 traffic classes, DCB only */ | |
2096 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, | |
2097 | (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ)); | |
2098 | break; | |
2099 | ||
2100 | default: | |
ee5f784a | 2101 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB); |
1cdd1ec8 GR |
2102 | break; |
2103 | } | |
ee5f784a DS |
2104 | |
2105 | /* re-eable the arbiter */ | |
2106 | rttdcs &= ~IXGBE_RTTDCS_ARBDIS; | |
2107 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
e8e26350 | 2108 | } |
9a799d71 AK |
2109 | } |
2110 | ||
e8e26350 | 2111 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c | 2112 | |
a6616b42 YZ |
2113 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, |
2114 | struct ixgbe_ring *rx_ring) | |
cc41ac7c | 2115 | { |
cc41ac7c | 2116 | u32 srrctl; |
a6616b42 | 2117 | int index; |
0cefafad | 2118 | struct ixgbe_ring_feature *feature = adapter->ring_feature; |
3be1adfb | 2119 | |
a6616b42 YZ |
2120 | index = rx_ring->reg_idx; |
2121 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
2122 | unsigned long mask; | |
0cefafad | 2123 | mask = (unsigned long) feature[RING_F_RSS].mask; |
3be1adfb | 2124 | index = index & mask; |
cc41ac7c | 2125 | } |
cc41ac7c JB |
2126 | srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index)); |
2127 | ||
2128 | srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; | |
2129 | srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; | |
2130 | ||
afafd5b0 AD |
2131 | srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & |
2132 | IXGBE_SRRCTL_BSIZEHDR_MASK; | |
2133 | ||
6e455b89 | 2134 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) { |
afafd5b0 AD |
2135 | #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER |
2136 | srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
2137 | #else | |
2138 | srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
2139 | #endif | |
cc41ac7c | 2140 | srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; |
cc41ac7c | 2141 | } else { |
afafd5b0 AD |
2142 | srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >> |
2143 | IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
cc41ac7c | 2144 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
cc41ac7c | 2145 | } |
e8e26350 | 2146 | |
cc41ac7c JB |
2147 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl); |
2148 | } | |
9a799d71 | 2149 | |
0cefafad JB |
2150 | static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) |
2151 | { | |
2152 | u32 mrqc = 0; | |
2153 | int mask; | |
2154 | ||
2155 | if (!(adapter->hw.mac.type == ixgbe_mac_82599EB)) | |
2156 | return mrqc; | |
2157 | ||
2158 | mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED | |
2159 | #ifdef CONFIG_IXGBE_DCB | |
2160 | | IXGBE_FLAG_DCB_ENABLED | |
2161 | #endif | |
1cdd1ec8 | 2162 | | IXGBE_FLAG_SRIOV_ENABLED |
0cefafad JB |
2163 | ); |
2164 | ||
2165 | switch (mask) { | |
2166 | case (IXGBE_FLAG_RSS_ENABLED): | |
2167 | mrqc = IXGBE_MRQC_RSSEN; | |
2168 | break; | |
1cdd1ec8 GR |
2169 | case (IXGBE_FLAG_SRIOV_ENABLED): |
2170 | mrqc = IXGBE_MRQC_VMDQEN; | |
2171 | break; | |
0cefafad JB |
2172 | #ifdef CONFIG_IXGBE_DCB |
2173 | case (IXGBE_FLAG_DCB_ENABLED): | |
2174 | mrqc = IXGBE_MRQC_RT8TCEN; | |
2175 | break; | |
2176 | #endif /* CONFIG_IXGBE_DCB */ | |
2177 | default: | |
2178 | break; | |
2179 | } | |
2180 | ||
2181 | return mrqc; | |
2182 | } | |
2183 | ||
bb5a9ad2 NS |
2184 | /** |
2185 | * ixgbe_configure_rscctl - enable RSC for the indicated ring | |
2186 | * @adapter: address of board private structure | |
2187 | * @index: index of ring to set | |
bb5a9ad2 | 2188 | **/ |
edd2ea55 | 2189 | static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index) |
bb5a9ad2 NS |
2190 | { |
2191 | struct ixgbe_ring *rx_ring; | |
2192 | struct ixgbe_hw *hw = &adapter->hw; | |
2193 | int j; | |
2194 | u32 rscctrl; | |
edd2ea55 | 2195 | int rx_buf_len; |
bb5a9ad2 | 2196 | |
4a0b9ca0 | 2197 | rx_ring = adapter->rx_ring[index]; |
bb5a9ad2 | 2198 | j = rx_ring->reg_idx; |
edd2ea55 | 2199 | rx_buf_len = rx_ring->rx_buf_len; |
bb5a9ad2 NS |
2200 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j)); |
2201 | rscctrl |= IXGBE_RSCCTL_RSCEN; | |
2202 | /* | |
2203 | * we must limit the number of descriptors so that the | |
2204 | * total size of max desc * buf_len is not greater | |
2205 | * than 65535 | |
2206 | */ | |
2207 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) { | |
2208 | #if (MAX_SKB_FRAGS > 16) | |
2209 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2210 | #elif (MAX_SKB_FRAGS > 8) | |
2211 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
2212 | #elif (MAX_SKB_FRAGS > 4) | |
2213 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
2214 | #else | |
2215 | rscctrl |= IXGBE_RSCCTL_MAXDESC_1; | |
2216 | #endif | |
2217 | } else { | |
2218 | if (rx_buf_len < IXGBE_RXBUFFER_4096) | |
2219 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2220 | else if (rx_buf_len < IXGBE_RXBUFFER_8192) | |
2221 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
2222 | else | |
2223 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
2224 | } | |
2225 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl); | |
2226 | } | |
2227 | ||
9a799d71 | 2228 | /** |
3a581073 | 2229 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset |
9a799d71 AK |
2230 | * @adapter: board private structure |
2231 | * | |
2232 | * Configure the Rx unit of the MAC after a reset. | |
2233 | **/ | |
2234 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
2235 | { | |
2236 | u64 rdba; | |
2237 | struct ixgbe_hw *hw = &adapter->hw; | |
a6616b42 | 2238 | struct ixgbe_ring *rx_ring; |
9a799d71 AK |
2239 | struct net_device *netdev = adapter->netdev; |
2240 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
021230d4 | 2241 | int i, j; |
9a799d71 | 2242 | u32 rdlen, rxctrl, rxcsum; |
7c6e0a43 JB |
2243 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, |
2244 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, | |
2245 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
9a799d71 | 2246 | u32 fctrl, hlreg0; |
509ee935 | 2247 | u32 reta = 0, mrqc = 0; |
cc41ac7c | 2248 | u32 rdrxctl; |
7c6e0a43 | 2249 | int rx_buf_len; |
9a799d71 AK |
2250 | |
2251 | /* Decide whether to use packet split mode or not */ | |
1cdd1ec8 GR |
2252 | /* Do not use packet split if we're in SR-IOV Mode */ |
2253 | if (!adapter->num_vfs) | |
2254 | adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED; | |
9a799d71 AK |
2255 | |
2256 | /* Set the RX buffer length according to the mode */ | |
2257 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 | 2258 | rx_buf_len = IXGBE_RX_HDR_SIZE; |
e8e26350 PW |
2259 | if (hw->mac.type == ixgbe_mac_82599EB) { |
2260 | /* PSRTYPE must be initialized in 82599 */ | |
2261 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
2262 | IXGBE_PSRTYPE_UDPHDR | | |
2263 | IXGBE_PSRTYPE_IPV4HDR | | |
dfa12f05 YZ |
2264 | IXGBE_PSRTYPE_IPV6HDR | |
2265 | IXGBE_PSRTYPE_L2HDR; | |
1cdd1ec8 GR |
2266 | IXGBE_WRITE_REG(hw, |
2267 | IXGBE_PSRTYPE(adapter->num_vfs), | |
2268 | psrtype); | |
e8e26350 | 2269 | } |
9a799d71 | 2270 | } else { |
0c19d6af | 2271 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) && |
f8212f97 | 2272 | (netdev->mtu <= ETH_DATA_LEN)) |
7c6e0a43 | 2273 | rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
9a799d71 | 2274 | else |
7c6e0a43 | 2275 | rx_buf_len = ALIGN(max_frame, 1024); |
9a799d71 AK |
2276 | } |
2277 | ||
2278 | fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL); | |
2279 | fctrl |= IXGBE_FCTRL_BAM; | |
021230d4 | 2280 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ |
e8e26350 | 2281 | fctrl |= IXGBE_FCTRL_PMCF; |
9a799d71 AK |
2282 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl); |
2283 | ||
2284 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |
2285 | if (adapter->netdev->mtu <= ETH_DATA_LEN) | |
2286 | hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; | |
2287 | else | |
2288 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
63f39bd1 | 2289 | #ifdef IXGBE_FCOE |
f34c5c82 | 2290 | if (netdev->features & NETIF_F_FCOE_MTU) |
63f39bd1 YZ |
2291 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; |
2292 | #endif | |
9a799d71 AK |
2293 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); |
2294 | ||
4a0b9ca0 | 2295 | rdlen = adapter->rx_ring[0]->count * sizeof(union ixgbe_adv_rx_desc); |
9a799d71 AK |
2296 | /* disable receives while setting up the descriptors */ |
2297 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
2298 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
2299 | ||
0cefafad JB |
2300 | /* |
2301 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
2302 | * the Base and Length of the Rx Descriptor Ring | |
2303 | */ | |
9a799d71 | 2304 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 | 2305 | rx_ring = adapter->rx_ring[i]; |
a6616b42 YZ |
2306 | rdba = rx_ring->dma; |
2307 | j = rx_ring->reg_idx; | |
284901a9 | 2308 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32))); |
7c6e0a43 JB |
2309 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32)); |
2310 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen); | |
2311 | IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0); | |
2312 | IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0); | |
a6616b42 YZ |
2313 | rx_ring->head = IXGBE_RDH(j); |
2314 | rx_ring->tail = IXGBE_RDT(j); | |
2315 | rx_ring->rx_buf_len = rx_buf_len; | |
cc41ac7c | 2316 | |
6e455b89 YZ |
2317 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) |
2318 | rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED; | |
1b3ff02e PWJ |
2319 | else |
2320 | rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED; | |
cc41ac7c | 2321 | |
63f39bd1 | 2322 | #ifdef IXGBE_FCOE |
f34c5c82 | 2323 | if (netdev->features & NETIF_F_FCOE_MTU) { |
63f39bd1 YZ |
2324 | struct ixgbe_ring_feature *f; |
2325 | f = &adapter->ring_feature[RING_F_FCOE]; | |
6e455b89 YZ |
2326 | if ((i >= f->mask) && (i < f->mask + f->indices)) { |
2327 | rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED; | |
2328 | if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) | |
2329 | rx_ring->rx_buf_len = | |
2330 | IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
2331 | } | |
63f39bd1 YZ |
2332 | } |
2333 | ||
2334 | #endif /* IXGBE_FCOE */ | |
a6616b42 | 2335 | ixgbe_configure_srrctl(adapter, rx_ring); |
9a799d71 AK |
2336 | } |
2337 | ||
e8e26350 PW |
2338 | if (hw->mac.type == ixgbe_mac_82598EB) { |
2339 | /* | |
2340 | * For VMDq support of different descriptor types or | |
2341 | * buffer sizes through the use of multiple SRRCTL | |
2342 | * registers, RDRXCTL.MVMEN must be set to 1 | |
2343 | * | |
2344 | * also, the manual doesn't mention it clearly but DCA hints | |
2345 | * will only use queue 0's tags unless this bit is set. Side | |
2346 | * effects of setting this bit are only that SRRCTL must be | |
2347 | * fully programmed [0..15] | |
2348 | */ | |
2a41ff81 JB |
2349 | rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); |
2350 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
2351 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
2f90b865 | 2352 | } |
177db6ff | 2353 | |
1cdd1ec8 GR |
2354 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
2355 | u32 vt_reg_bits; | |
2356 | u32 reg_offset, vf_shift; | |
2357 | u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
2358 | vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | |
2359 | | IXGBE_VT_CTL_REPLEN; | |
2360 | vt_reg_bits |= (adapter->num_vfs << | |
2361 | IXGBE_VT_CTL_POOL_SHIFT); | |
2362 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits); | |
2363 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0); | |
2364 | ||
2365 | vf_shift = adapter->num_vfs % 32; | |
2366 | reg_offset = adapter->num_vfs / 32; | |
2367 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0); | |
2368 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0); | |
2369 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0); | |
2370 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0); | |
2371 | /* Enable only the PF's pool for Tx/Rx */ | |
2372 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift)); | |
2373 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift)); | |
2374 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); | |
2375 | ixgbe_set_vmolr(hw, adapter->num_vfs); | |
2376 | } | |
2377 | ||
e8e26350 | 2378 | /* Program MRQC for the distribution of queues */ |
0cefafad | 2379 | mrqc = ixgbe_setup_mrqc(adapter); |
e8e26350 | 2380 | |
021230d4 | 2381 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { |
9a799d71 | 2382 | /* Fill out redirection table */ |
021230d4 AV |
2383 | for (i = 0, j = 0; i < 128; i++, j++) { |
2384 | if (j == adapter->ring_feature[RING_F_RSS].indices) | |
2385 | j = 0; | |
2386 | /* reta = 4-byte sliding window of | |
2387 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
2388 | reta = (reta << 8) | (j * 0x11); | |
2389 | if ((i & 3) == 3) | |
2390 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
9a799d71 AK |
2391 | } |
2392 | ||
2393 | /* Fill out hash function seeds */ | |
2394 | for (i = 0; i < 10; i++) | |
7c6e0a43 | 2395 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); |
9a799d71 | 2396 | |
2a41ff81 JB |
2397 | if (hw->mac.type == ixgbe_mac_82598EB) |
2398 | mrqc |= IXGBE_MRQC_RSSEN; | |
9a799d71 | 2399 | /* Perform hash on these packet types */ |
2a41ff81 JB |
2400 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
2401 | | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | |
2402 | | IXGBE_MRQC_RSS_FIELD_IPV4_UDP | |
2403 | | IXGBE_MRQC_RSS_FIELD_IPV6 | |
2404 | | IXGBE_MRQC_RSS_FIELD_IPV6_TCP | |
2405 | | IXGBE_MRQC_RSS_FIELD_IPV6_UDP; | |
021230d4 | 2406 | } |
2a41ff81 | 2407 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); |
9a799d71 | 2408 | |
1cdd1ec8 GR |
2409 | if (adapter->num_vfs) { |
2410 | u32 reg; | |
2411 | ||
2412 | /* Map PF MAC address in RAR Entry 0 to first pool | |
2413 | * following VFs */ | |
2414 | hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs); | |
2415 | ||
2416 | /* Set up VF register offsets for selected VT Mode, i.e. | |
2417 | * 64 VFs for SR-IOV */ | |
2418 | reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); | |
2419 | reg |= IXGBE_GCR_EXT_SRIOV; | |
2420 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg); | |
2421 | } | |
2422 | ||
021230d4 AV |
2423 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); |
2424 | ||
2425 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED || | |
2426 | adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) { | |
2427 | /* Disable indicating checksum in descriptor, enables | |
2428 | * RSS hash */ | |
9a799d71 | 2429 | rxcsum |= IXGBE_RXCSUM_PCSD; |
9a799d71 | 2430 | } |
021230d4 AV |
2431 | if (!(rxcsum & IXGBE_RXCSUM_PCSD)) { |
2432 | /* Enable IPv4 payload checksum for UDP fragments | |
2433 | * if PCSD is not set */ | |
2434 | rxcsum |= IXGBE_RXCSUM_IPPCSE; | |
2435 | } | |
2436 | ||
2437 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
e8e26350 PW |
2438 | |
2439 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
2440 | rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
2441 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
f8212f97 | 2442 | rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; |
e8e26350 PW |
2443 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); |
2444 | } | |
f8212f97 | 2445 | |
0c19d6af | 2446 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { |
f8212f97 | 2447 | /* Enable 82599 HW-RSC */ |
bb5a9ad2 | 2448 | for (i = 0; i < adapter->num_rx_queues; i++) |
edd2ea55 | 2449 | ixgbe_configure_rscctl(adapter, i); |
bb5a9ad2 | 2450 | |
f8212f97 AD |
2451 | /* Disable RSC for ACK packets */ |
2452 | IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, | |
2453 | (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); | |
2454 | } | |
9a799d71 AK |
2455 | } |
2456 | ||
068c89b0 DS |
2457 | static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
2458 | { | |
2459 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2460 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 2461 | int pool_ndx = adapter->num_vfs; |
068c89b0 DS |
2462 | |
2463 | /* add VID to filter table */ | |
1ada1b1b | 2464 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true); |
068c89b0 DS |
2465 | } |
2466 | ||
2467 | static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |
2468 | { | |
2469 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2470 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 2471 | int pool_ndx = adapter->num_vfs; |
068c89b0 DS |
2472 | |
2473 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2474 | ixgbe_irq_disable(adapter); | |
2475 | ||
2476 | vlan_group_set_device(adapter->vlgrp, vid, NULL); | |
2477 | ||
2478 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2479 | ixgbe_irq_enable(adapter); | |
2480 | ||
2481 | /* remove VID from filter table */ | |
1ada1b1b | 2482 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false); |
068c89b0 DS |
2483 | } |
2484 | ||
9a799d71 | 2485 | static void ixgbe_vlan_rx_register(struct net_device *netdev, |
b4617240 | 2486 | struct vlan_group *grp) |
9a799d71 AK |
2487 | { |
2488 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2489 | u32 ctrl; | |
e8e26350 | 2490 | int i, j; |
9a799d71 | 2491 | |
d4f80882 AV |
2492 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2493 | ixgbe_irq_disable(adapter); | |
9a799d71 AK |
2494 | adapter->vlgrp = grp; |
2495 | ||
2f90b865 AD |
2496 | /* |
2497 | * For a DCB driver, always enable VLAN tag stripping so we can | |
2498 | * still receive traffic from a DCB-enabled host even if we're | |
2499 | * not in DCB mode. | |
2500 | */ | |
2501 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL); | |
dc63d377 AD |
2502 | |
2503 | /* Disable CFI check */ | |
2504 | ctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2505 | ||
2506 | /* enable VLAN tag stripping */ | |
e8e26350 | 2507 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
dc63d377 | 2508 | ctrl |= IXGBE_VLNCTRL_VME; |
e8e26350 | 2509 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
e8e26350 | 2510 | for (i = 0; i < adapter->num_rx_queues; i++) { |
dc63d377 | 2511 | u32 ctrl; |
4a0b9ca0 | 2512 | j = adapter->rx_ring[i]->reg_idx; |
e8e26350 PW |
2513 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j)); |
2514 | ctrl |= IXGBE_RXDCTL_VME; | |
2515 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl); | |
2516 | } | |
9a799d71 | 2517 | } |
dc63d377 AD |
2518 | |
2519 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl); | |
2520 | ||
e8e26350 | 2521 | ixgbe_vlan_rx_add_vid(netdev, 0); |
9a799d71 | 2522 | |
d4f80882 AV |
2523 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2524 | ixgbe_irq_enable(adapter); | |
9a799d71 AK |
2525 | } |
2526 | ||
9a799d71 AK |
2527 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
2528 | { | |
2529 | ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp); | |
2530 | ||
2531 | if (adapter->vlgrp) { | |
2532 | u16 vid; | |
2533 | for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) { | |
2534 | if (!vlan_group_get_device(adapter->vlgrp, vid)) | |
2535 | continue; | |
2536 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
2537 | } | |
2538 | } | |
2539 | } | |
2540 | ||
2c5645cf CL |
2541 | static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq) |
2542 | { | |
2543 | struct dev_mc_list *mc_ptr; | |
2544 | u8 *addr = *mc_addr_ptr; | |
2545 | *vmdq = 0; | |
2546 | ||
2547 | mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]); | |
2548 | if (mc_ptr->next) | |
2549 | *mc_addr_ptr = mc_ptr->next->dmi_addr; | |
2550 | else | |
2551 | *mc_addr_ptr = NULL; | |
2552 | ||
2553 | return addr; | |
2554 | } | |
2555 | ||
9a799d71 | 2556 | /** |
2c5645cf | 2557 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
2558 | * @netdev: network interface device structure |
2559 | * | |
2c5645cf CL |
2560 | * The set_rx_method entry point is called whenever the unicast/multicast |
2561 | * address list or the network interface flags are updated. This routine is | |
2562 | * responsible for configuring the hardware for proper unicast, multicast and | |
2563 | * promiscuous mode. | |
9a799d71 | 2564 | **/ |
7f870475 | 2565 | void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
2566 | { |
2567 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2568 | struct ixgbe_hw *hw = &adapter->hw; | |
3d01625a | 2569 | u32 fctrl, vlnctrl; |
2c5645cf CL |
2570 | u8 *addr_list = NULL; |
2571 | int addr_count = 0; | |
9a799d71 AK |
2572 | |
2573 | /* Check for Promiscuous and All Multicast modes */ | |
2574 | ||
2575 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3d01625a | 2576 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
9a799d71 AK |
2577 | |
2578 | if (netdev->flags & IFF_PROMISC) { | |
2c5645cf | 2579 | hw->addr_ctrl.user_set_promisc = 1; |
9a799d71 | 2580 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
3d01625a | 2581 | vlnctrl &= ~IXGBE_VLNCTRL_VFE; |
9a799d71 | 2582 | } else { |
746b9f02 PM |
2583 | if (netdev->flags & IFF_ALLMULTI) { |
2584 | fctrl |= IXGBE_FCTRL_MPE; | |
2585 | fctrl &= ~IXGBE_FCTRL_UPE; | |
2586 | } else { | |
2587 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
2588 | } | |
3d01625a | 2589 | vlnctrl |= IXGBE_VLNCTRL_VFE; |
2c5645cf | 2590 | hw->addr_ctrl.user_set_promisc = 0; |
9a799d71 AK |
2591 | } |
2592 | ||
2593 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
3d01625a | 2594 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
9a799d71 | 2595 | |
2c5645cf | 2596 | /* reprogram secondary unicast list */ |
32e7bfc4 | 2597 | hw->mac.ops.update_uc_addr_list(hw, netdev); |
9a799d71 | 2598 | |
2c5645cf | 2599 | /* reprogram multicast list */ |
4cd24eaf | 2600 | addr_count = netdev_mc_count(netdev); |
2c5645cf CL |
2601 | if (addr_count) |
2602 | addr_list = netdev->mc_list->dmi_addr; | |
c44ade9e JB |
2603 | hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count, |
2604 | ixgbe_addr_list_itr); | |
1cdd1ec8 GR |
2605 | if (adapter->num_vfs) |
2606 | ixgbe_restore_vf_multicasts(adapter); | |
9a799d71 AK |
2607 | } |
2608 | ||
021230d4 AV |
2609 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
2610 | { | |
2611 | int q_idx; | |
2612 | struct ixgbe_q_vector *q_vector; | |
2613 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2614 | ||
2615 | /* legacy and MSI only use one vector */ | |
2616 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2617 | q_vectors = 1; | |
2618 | ||
2619 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
f0848276 | 2620 | struct napi_struct *napi; |
7a921c93 | 2621 | q_vector = adapter->q_vector[q_idx]; |
f0848276 | 2622 | napi = &q_vector->napi; |
91281fd3 AD |
2623 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
2624 | if (!q_vector->rxr_count || !q_vector->txr_count) { | |
2625 | if (q_vector->txr_count == 1) | |
2626 | napi->poll = &ixgbe_clean_txonly; | |
2627 | else if (q_vector->rxr_count == 1) | |
2628 | napi->poll = &ixgbe_clean_rxonly; | |
2629 | } | |
2630 | } | |
f0848276 JB |
2631 | |
2632 | napi_enable(napi); | |
021230d4 AV |
2633 | } |
2634 | } | |
2635 | ||
2636 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
2637 | { | |
2638 | int q_idx; | |
2639 | struct ixgbe_q_vector *q_vector; | |
2640 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2641 | ||
2642 | /* legacy and MSI only use one vector */ | |
2643 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2644 | q_vectors = 1; | |
2645 | ||
2646 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
7a921c93 | 2647 | q_vector = adapter->q_vector[q_idx]; |
021230d4 AV |
2648 | napi_disable(&q_vector->napi); |
2649 | } | |
2650 | } | |
2651 | ||
7a6b6f51 | 2652 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
2653 | /* |
2654 | * ixgbe_configure_dcb - Configure DCB hardware | |
2655 | * @adapter: ixgbe adapter struct | |
2656 | * | |
2657 | * This is called by the driver on open to configure the DCB hardware. | |
2658 | * This is also called by the gennetlink interface when reconfiguring | |
2659 | * the DCB state. | |
2660 | */ | |
2661 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
2662 | { | |
2663 | struct ixgbe_hw *hw = &adapter->hw; | |
2664 | u32 txdctl, vlnctrl; | |
2665 | int i, j; | |
2666 | ||
2667 | ixgbe_dcb_check_config(&adapter->dcb_cfg); | |
2668 | ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG); | |
2669 | ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG); | |
2670 | ||
2671 | /* reconfigure the hardware */ | |
2672 | ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg); | |
2673 | ||
2674 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 2675 | j = adapter->tx_ring[i]->reg_idx; |
2f90b865 AD |
2676 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); |
2677 | /* PThresh workaround for Tx hang with DFP enabled. */ | |
2678 | txdctl |= 32; | |
2679 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); | |
2680 | } | |
2681 | /* Enable VLAN tag insert/strip */ | |
2682 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
e8e26350 PW |
2683 | if (hw->mac.type == ixgbe_mac_82598EB) { |
2684 | vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE; | |
2685 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2686 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
2687 | } else if (hw->mac.type == ixgbe_mac_82599EB) { | |
2688 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
2689 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2690 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
2691 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
4a0b9ca0 | 2692 | j = adapter->rx_ring[i]->reg_idx; |
e8e26350 PW |
2693 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); |
2694 | vlnctrl |= IXGBE_RXDCTL_VME; | |
2695 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
2696 | } | |
2697 | } | |
2f90b865 AD |
2698 | hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); |
2699 | } | |
2700 | ||
2701 | #endif | |
9a799d71 AK |
2702 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
2703 | { | |
2704 | struct net_device *netdev = adapter->netdev; | |
c4cf55e5 | 2705 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
2706 | int i; |
2707 | ||
2c5645cf | 2708 | ixgbe_set_rx_mode(netdev); |
9a799d71 AK |
2709 | |
2710 | ixgbe_restore_vlan(adapter); | |
7a6b6f51 | 2711 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 | 2712 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
b352e40d YZ |
2713 | if (hw->mac.type == ixgbe_mac_82598EB) |
2714 | netif_set_gso_max_size(netdev, 32768); | |
2715 | else | |
2716 | netif_set_gso_max_size(netdev, 65536); | |
2f90b865 AD |
2717 | ixgbe_configure_dcb(adapter); |
2718 | } else { | |
2719 | netif_set_gso_max_size(netdev, 65536); | |
2720 | } | |
2721 | #else | |
2722 | netif_set_gso_max_size(netdev, 65536); | |
2723 | #endif | |
9a799d71 | 2724 | |
eacd73f7 YZ |
2725 | #ifdef IXGBE_FCOE |
2726 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
2727 | ixgbe_configure_fcoe(adapter); | |
2728 | ||
2729 | #endif /* IXGBE_FCOE */ | |
c4cf55e5 PWJ |
2730 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
2731 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 2732 | adapter->tx_ring[i]->atr_sample_rate = |
c4cf55e5 PWJ |
2733 | adapter->atr_sample_rate; |
2734 | ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc); | |
2735 | } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { | |
2736 | ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc); | |
2737 | } | |
2738 | ||
9a799d71 AK |
2739 | ixgbe_configure_tx(adapter); |
2740 | ixgbe_configure_rx(adapter); | |
2741 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 PW |
2742 | ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i], |
2743 | (adapter->rx_ring[i]->count - 1)); | |
9a799d71 AK |
2744 | } |
2745 | ||
e8e26350 PW |
2746 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
2747 | { | |
2748 | switch (hw->phy.type) { | |
2749 | case ixgbe_phy_sfp_avago: | |
2750 | case ixgbe_phy_sfp_ftl: | |
2751 | case ixgbe_phy_sfp_intel: | |
2752 | case ixgbe_phy_sfp_unknown: | |
2753 | case ixgbe_phy_tw_tyco: | |
2754 | case ixgbe_phy_tw_unknown: | |
2755 | return true; | |
2756 | default: | |
2757 | return false; | |
2758 | } | |
2759 | } | |
2760 | ||
0ecc061d | 2761 | /** |
e8e26350 PW |
2762 | * ixgbe_sfp_link_config - set up SFP+ link |
2763 | * @adapter: pointer to private adapter struct | |
2764 | **/ | |
2765 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
2766 | { | |
2767 | struct ixgbe_hw *hw = &adapter->hw; | |
2768 | ||
2769 | if (hw->phy.multispeed_fiber) { | |
2770 | /* | |
2771 | * In multispeed fiber setups, the device may not have | |
2772 | * had a physical connection when the driver loaded. | |
2773 | * If that's the case, the initial link configuration | |
2774 | * couldn't get the MAC into 10G or 1G mode, so we'll | |
2775 | * never have a link status change interrupt fire. | |
2776 | * We need to try and force an autonegotiation | |
2777 | * session, then bring up link. | |
2778 | */ | |
2779 | hw->mac.ops.setup_sfp(hw); | |
2780 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) | |
2781 | schedule_work(&adapter->multispeed_fiber_task); | |
2782 | } else { | |
2783 | /* | |
2784 | * Direct Attach Cu and non-multispeed fiber modules | |
2785 | * still need to be configured properly prior to | |
2786 | * attempting link. | |
2787 | */ | |
2788 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK)) | |
2789 | schedule_work(&adapter->sfp_config_module_task); | |
2790 | } | |
2791 | } | |
2792 | ||
2793 | /** | |
2794 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
2795 | * @hw: pointer to private hardware struct |
2796 | * | |
2797 | * Returns 0 on success, negative on failure | |
2798 | **/ | |
e8e26350 | 2799 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d PWJ |
2800 | { |
2801 | u32 autoneg; | |
8620a103 | 2802 | bool negotiation, link_up = false; |
0ecc061d PWJ |
2803 | u32 ret = IXGBE_ERR_LINK_SETUP; |
2804 | ||
2805 | if (hw->mac.ops.check_link) | |
2806 | ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
2807 | ||
2808 | if (ret) | |
2809 | goto link_cfg_out; | |
2810 | ||
2811 | if (hw->mac.ops.get_link_capabilities) | |
8620a103 | 2812 | ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation); |
0ecc061d PWJ |
2813 | if (ret) |
2814 | goto link_cfg_out; | |
2815 | ||
8620a103 MC |
2816 | if (hw->mac.ops.setup_link) |
2817 | ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up); | |
0ecc061d PWJ |
2818 | link_cfg_out: |
2819 | return ret; | |
2820 | } | |
2821 | ||
e8e26350 PW |
2822 | #define IXGBE_MAX_RX_DESC_POLL 10 |
2823 | static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
2824 | int rxr) | |
2825 | { | |
4a0b9ca0 | 2826 | int j = adapter->rx_ring[rxr]->reg_idx; |
e8e26350 PW |
2827 | int k; |
2828 | ||
2829 | for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) { | |
2830 | if (IXGBE_READ_REG(&adapter->hw, | |
2831 | IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE) | |
2832 | break; | |
2833 | else | |
2834 | msleep(1); | |
2835 | } | |
2836 | if (k >= IXGBE_MAX_RX_DESC_POLL) { | |
2837 | DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d " | |
2838 | "not set within the polling period\n", rxr); | |
2839 | } | |
4a0b9ca0 PW |
2840 | ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr], |
2841 | (adapter->rx_ring[rxr]->count - 1)); | |
e8e26350 PW |
2842 | } |
2843 | ||
9a799d71 AK |
2844 | static int ixgbe_up_complete(struct ixgbe_adapter *adapter) |
2845 | { | |
2846 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 2847 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 2848 | int i, j = 0; |
e8e26350 | 2849 | int num_rx_rings = adapter->num_rx_queues; |
0ecc061d | 2850 | int err; |
9a799d71 | 2851 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
021230d4 | 2852 | u32 txdctl, rxdctl, mhadd; |
e8e26350 | 2853 | u32 dmatxctl; |
021230d4 | 2854 | u32 gpie; |
c9205697 | 2855 | u32 ctrl_ext; |
9a799d71 | 2856 | |
5eba3699 AV |
2857 | ixgbe_get_hw_control(adapter); |
2858 | ||
021230d4 AV |
2859 | if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) || |
2860 | (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) { | |
9a799d71 AK |
2861 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
2862 | gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME | | |
b4617240 | 2863 | IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD); |
9a799d71 AK |
2864 | } else { |
2865 | /* MSI only */ | |
021230d4 | 2866 | gpie = 0; |
9a799d71 | 2867 | } |
1cdd1ec8 GR |
2868 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
2869 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
2870 | gpie |= IXGBE_GPIE_VTMODE_64; | |
2871 | } | |
021230d4 AV |
2872 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
2873 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
2874 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
9a799d71 AK |
2875 | } |
2876 | ||
9b471446 JB |
2877 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
2878 | /* | |
2879 | * use EIAM to auto-mask when MSI-X interrupt is asserted | |
2880 | * this saves a register write for every interrupt | |
2881 | */ | |
2882 | switch (hw->mac.type) { | |
2883 | case ixgbe_mac_82598EB: | |
2884 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
2885 | break; | |
2886 | default: | |
2887 | case ixgbe_mac_82599EB: | |
2888 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); | |
2889 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); | |
2890 | break; | |
2891 | } | |
2892 | } else { | |
021230d4 AV |
2893 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, |
2894 | * specifically only auto mask tx and rx interrupts */ | |
2895 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
2896 | } | |
9a799d71 | 2897 | |
0befdb3e JB |
2898 | /* Enable fan failure interrupt if media type is copper */ |
2899 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
2900 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
2901 | gpie |= IXGBE_SDP1_GPIEN; | |
2902 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
2903 | } | |
2904 | ||
e8e26350 PW |
2905 | if (hw->mac.type == ixgbe_mac_82599EB) { |
2906 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
2907 | gpie |= IXGBE_SDP1_GPIEN; | |
2908 | gpie |= IXGBE_SDP2_GPIEN; | |
2909 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
2910 | } | |
2911 | ||
63f39bd1 YZ |
2912 | #ifdef IXGBE_FCOE |
2913 | /* adjust max frame to be able to do baby jumbo for FCoE */ | |
f34c5c82 | 2914 | if ((netdev->features & NETIF_F_FCOE_MTU) && |
63f39bd1 YZ |
2915 | (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) |
2916 | max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
2917 | ||
2918 | #endif /* IXGBE_FCOE */ | |
021230d4 | 2919 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); |
9a799d71 AK |
2920 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { |
2921 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
2922 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
2923 | ||
2924 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
2925 | } | |
2926 | ||
2927 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 2928 | j = adapter->tx_ring[i]->reg_idx; |
021230d4 | 2929 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); |
e01c31a5 JB |
2930 | /* enable WTHRESH=8 descriptors, to encourage burst writeback */ |
2931 | txdctl |= (8 << 16); | |
e8e26350 PW |
2932 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); |
2933 | } | |
2934 | ||
2935 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
2936 | /* DMATXCTL.EN must be set after all Tx queue config is done */ | |
2937 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
2938 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
2939 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
2940 | } | |
2941 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 2942 | j = adapter->tx_ring[i]->reg_idx; |
e8e26350 | 2943 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); |
9a799d71 | 2944 | txdctl |= IXGBE_TXDCTL_ENABLE; |
021230d4 | 2945 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); |
1cdd1ec8 GR |
2946 | if (hw->mac.type == ixgbe_mac_82599EB) { |
2947 | int wait_loop = 10; | |
2948 | /* poll for Tx Enable ready */ | |
2949 | do { | |
2950 | msleep(1); | |
2951 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
2952 | } while (--wait_loop && | |
2953 | !(txdctl & IXGBE_TXDCTL_ENABLE)); | |
2954 | if (!wait_loop) | |
2955 | DPRINTK(DRV, ERR, "Could not enable " | |
2956 | "Tx Queue %d\n", j); | |
2957 | } | |
9a799d71 AK |
2958 | } |
2959 | ||
e8e26350 | 2960 | for (i = 0; i < num_rx_rings; i++) { |
4a0b9ca0 | 2961 | j = adapter->rx_ring[i]->reg_idx; |
021230d4 AV |
2962 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); |
2963 | /* enable PTHRESH=32 descriptors (half the internal cache) | |
2964 | * and HTHRESH=0 descriptors (to minimize latency on fetch), | |
2965 | * this also removes a pesky rx_no_buffer_count increment */ | |
2966 | rxdctl |= 0x0020; | |
9a799d71 | 2967 | rxdctl |= IXGBE_RXDCTL_ENABLE; |
021230d4 | 2968 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl); |
e8e26350 PW |
2969 | if (hw->mac.type == ixgbe_mac_82599EB) |
2970 | ixgbe_rx_desc_queue_enable(adapter, i); | |
9a799d71 AK |
2971 | } |
2972 | /* enable all receives */ | |
2973 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
e8e26350 PW |
2974 | if (hw->mac.type == ixgbe_mac_82598EB) |
2975 | rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN); | |
2976 | else | |
2977 | rxdctl |= IXGBE_RXCTRL_RXEN; | |
2978 | hw->mac.ops.enable_rx_dma(hw, rxdctl); | |
9a799d71 AK |
2979 | |
2980 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) | |
2981 | ixgbe_configure_msix(adapter); | |
2982 | else | |
2983 | ixgbe_configure_msi_and_legacy(adapter); | |
2984 | ||
2985 | clear_bit(__IXGBE_DOWN, &adapter->state); | |
021230d4 AV |
2986 | ixgbe_napi_enable_all(adapter); |
2987 | ||
2988 | /* clear any pending interrupts, may auto mask */ | |
2989 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
2990 | ||
9a799d71 AK |
2991 | ixgbe_irq_enable(adapter); |
2992 | ||
bf069c97 DS |
2993 | /* |
2994 | * If this adapter has a fan, check to see if we had a failure | |
2995 | * before we enabled the interrupt. | |
2996 | */ | |
2997 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
2998 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
2999 | if (esdp & IXGBE_ESDP_SDP1) | |
3000 | DPRINTK(DRV, CRIT, | |
3001 | "Fan has stopped, replace the adapter\n"); | |
3002 | } | |
3003 | ||
e8e26350 PW |
3004 | /* |
3005 | * For hot-pluggable SFP+ devices, a new SFP+ module may have | |
19343de2 DS |
3006 | * arrived before interrupts were enabled but after probe. Such |
3007 | * devices wouldn't have their type identified yet. We need to | |
3008 | * kick off the SFP+ module setup first, then try to bring up link. | |
e8e26350 PW |
3009 | * If we're not hot-pluggable SFP+, we just need to configure link |
3010 | * and bring it up. | |
3011 | */ | |
19343de2 DS |
3012 | if (hw->phy.type == ixgbe_phy_unknown) { |
3013 | err = hw->phy.ops.identify(hw); | |
3014 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
5da43c1a DS |
3015 | /* |
3016 | * Take the device down and schedule the sfp tasklet | |
3017 | * which will unregister_netdev and log it. | |
3018 | */ | |
19343de2 | 3019 | ixgbe_down(adapter); |
5da43c1a | 3020 | schedule_work(&adapter->sfp_config_module_task); |
19343de2 DS |
3021 | return err; |
3022 | } | |
e8e26350 PW |
3023 | } |
3024 | ||
3025 | if (ixgbe_is_sfp(hw)) { | |
3026 | ixgbe_sfp_link_config(adapter); | |
3027 | } else { | |
3028 | err = ixgbe_non_sfp_link_config(hw); | |
3029 | if (err) | |
3030 | DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err); | |
3031 | } | |
0ecc061d | 3032 | |
c4cf55e5 PWJ |
3033 | for (i = 0; i < adapter->num_tx_queues; i++) |
3034 | set_bit(__IXGBE_FDIR_INIT_DONE, | |
4a0b9ca0 | 3035 | &(adapter->tx_ring[i]->reinit_state)); |
c4cf55e5 | 3036 | |
1da100bb PWJ |
3037 | /* enable transmits */ |
3038 | netif_tx_start_all_queues(netdev); | |
3039 | ||
9a799d71 AK |
3040 | /* bring the link up in the watchdog, this could race with our first |
3041 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
3042 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
3043 | adapter->link_check_timeout = jiffies; | |
9a799d71 | 3044 | mod_timer(&adapter->watchdog_timer, jiffies); |
c9205697 GR |
3045 | |
3046 | /* Set PF Reset Done bit so PF/VF Mail Ops can work */ | |
3047 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
3048 | ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; | |
3049 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); | |
3050 | ||
9a799d71 AK |
3051 | return 0; |
3052 | } | |
3053 | ||
d4f80882 AV |
3054 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
3055 | { | |
3056 | WARN_ON(in_interrupt()); | |
3057 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) | |
3058 | msleep(1); | |
3059 | ixgbe_down(adapter); | |
5809a1ae GR |
3060 | /* |
3061 | * If SR-IOV enabled then wait a bit before bringing the adapter | |
3062 | * back up to give the VFs time to respond to the reset. The | |
3063 | * two second wait is based upon the watchdog timer cycle in | |
3064 | * the VF driver. | |
3065 | */ | |
3066 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
3067 | msleep(2000); | |
d4f80882 AV |
3068 | ixgbe_up(adapter); |
3069 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
3070 | } | |
3071 | ||
9a799d71 AK |
3072 | int ixgbe_up(struct ixgbe_adapter *adapter) |
3073 | { | |
3074 | /* hardware has been reset, we need to reload some things */ | |
3075 | ixgbe_configure(adapter); | |
3076 | ||
3077 | return ixgbe_up_complete(adapter); | |
3078 | } | |
3079 | ||
3080 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
3081 | { | |
c44ade9e | 3082 | struct ixgbe_hw *hw = &adapter->hw; |
8ca783ab DS |
3083 | int err; |
3084 | ||
3085 | err = hw->mac.ops.init_hw(hw); | |
da4dd0f7 PWJ |
3086 | switch (err) { |
3087 | case 0: | |
3088 | case IXGBE_ERR_SFP_NOT_PRESENT: | |
3089 | break; | |
3090 | case IXGBE_ERR_MASTER_REQUESTS_PENDING: | |
3091 | dev_err(&adapter->pdev->dev, "master disable timed out\n"); | |
3092 | break; | |
794caeb2 PWJ |
3093 | case IXGBE_ERR_EEPROM_VERSION: |
3094 | /* We are running on a pre-production device, log a warning */ | |
3095 | dev_warn(&adapter->pdev->dev, "This device is a pre-production " | |
3096 | "adapter/LOM. Please be aware there may be issues " | |
3097 | "associated with your hardware. If you are " | |
3098 | "experiencing problems please contact your Intel or " | |
3099 | "hardware representative who provided you with this " | |
3100 | "hardware.\n"); | |
3101 | break; | |
da4dd0f7 PWJ |
3102 | default: |
3103 | dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err); | |
3104 | } | |
9a799d71 AK |
3105 | |
3106 | /* reprogram the RAR[0] in case user changed it. */ | |
1cdd1ec8 GR |
3107 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
3108 | IXGBE_RAH_AV); | |
9a799d71 AK |
3109 | } |
3110 | ||
9a799d71 AK |
3111 | /** |
3112 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
3113 | * @adapter: board private structure | |
3114 | * @rx_ring: ring to free buffers from | |
3115 | **/ | |
3116 | static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 3117 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
3118 | { |
3119 | struct pci_dev *pdev = adapter->pdev; | |
3120 | unsigned long size; | |
3121 | unsigned int i; | |
3122 | ||
3123 | /* Free all the Rx ring sk_buffs */ | |
3124 | ||
3125 | for (i = 0; i < rx_ring->count; i++) { | |
3126 | struct ixgbe_rx_buffer *rx_buffer_info; | |
3127 | ||
3128 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
3129 | if (rx_buffer_info->dma) { | |
3130 | pci_unmap_single(pdev, rx_buffer_info->dma, | |
b4617240 PW |
3131 | rx_ring->rx_buf_len, |
3132 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
3133 | rx_buffer_info->dma = 0; |
3134 | } | |
3135 | if (rx_buffer_info->skb) { | |
f8212f97 | 3136 | struct sk_buff *skb = rx_buffer_info->skb; |
9a799d71 | 3137 | rx_buffer_info->skb = NULL; |
f8212f97 AD |
3138 | do { |
3139 | struct sk_buff *this = skb; | |
fd3686a8 | 3140 | if (IXGBE_RSC_CB(this)->dma) { |
43634e82 MC |
3141 | pci_unmap_single(pdev, IXGBE_RSC_CB(this)->dma, |
3142 | rx_ring->rx_buf_len, | |
3143 | PCI_DMA_FROMDEVICE); | |
fd3686a8 MC |
3144 | IXGBE_RSC_CB(this)->dma = 0; |
3145 | } | |
f8212f97 AD |
3146 | skb = skb->prev; |
3147 | dev_kfree_skb(this); | |
3148 | } while (skb); | |
9a799d71 AK |
3149 | } |
3150 | if (!rx_buffer_info->page) | |
3151 | continue; | |
4f57ca6e JB |
3152 | if (rx_buffer_info->page_dma) { |
3153 | pci_unmap_page(pdev, rx_buffer_info->page_dma, | |
3154 | PAGE_SIZE / 2, PCI_DMA_FROMDEVICE); | |
3155 | rx_buffer_info->page_dma = 0; | |
3156 | } | |
9a799d71 AK |
3157 | put_page(rx_buffer_info->page); |
3158 | rx_buffer_info->page = NULL; | |
762f4c57 | 3159 | rx_buffer_info->page_offset = 0; |
9a799d71 AK |
3160 | } |
3161 | ||
3162 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
3163 | memset(rx_ring->rx_buffer_info, 0, size); | |
3164 | ||
3165 | /* Zero out the descriptor ring */ | |
3166 | memset(rx_ring->desc, 0, rx_ring->size); | |
3167 | ||
3168 | rx_ring->next_to_clean = 0; | |
3169 | rx_ring->next_to_use = 0; | |
3170 | ||
9891ca7c JB |
3171 | if (rx_ring->head) |
3172 | writel(0, adapter->hw.hw_addr + rx_ring->head); | |
3173 | if (rx_ring->tail) | |
3174 | writel(0, adapter->hw.hw_addr + rx_ring->tail); | |
9a799d71 AK |
3175 | } |
3176 | ||
3177 | /** | |
3178 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
3179 | * @adapter: board private structure | |
3180 | * @tx_ring: ring to be cleaned | |
3181 | **/ | |
3182 | static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 3183 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
3184 | { |
3185 | struct ixgbe_tx_buffer *tx_buffer_info; | |
3186 | unsigned long size; | |
3187 | unsigned int i; | |
3188 | ||
3189 | /* Free all the Tx ring sk_buffs */ | |
3190 | ||
3191 | for (i = 0; i < tx_ring->count; i++) { | |
3192 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
3193 | ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info); | |
3194 | } | |
3195 | ||
3196 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; | |
3197 | memset(tx_ring->tx_buffer_info, 0, size); | |
3198 | ||
3199 | /* Zero out the descriptor ring */ | |
3200 | memset(tx_ring->desc, 0, tx_ring->size); | |
3201 | ||
3202 | tx_ring->next_to_use = 0; | |
3203 | tx_ring->next_to_clean = 0; | |
3204 | ||
9891ca7c JB |
3205 | if (tx_ring->head) |
3206 | writel(0, adapter->hw.hw_addr + tx_ring->head); | |
3207 | if (tx_ring->tail) | |
3208 | writel(0, adapter->hw.hw_addr + tx_ring->tail); | |
9a799d71 AK |
3209 | } |
3210 | ||
3211 | /** | |
021230d4 | 3212 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
3213 | * @adapter: board private structure |
3214 | **/ | |
021230d4 | 3215 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
3216 | { |
3217 | int i; | |
3218 | ||
021230d4 | 3219 | for (i = 0; i < adapter->num_rx_queues; i++) |
4a0b9ca0 | 3220 | ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]); |
9a799d71 AK |
3221 | } |
3222 | ||
3223 | /** | |
021230d4 | 3224 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
3225 | * @adapter: board private structure |
3226 | **/ | |
021230d4 | 3227 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
3228 | { |
3229 | int i; | |
3230 | ||
021230d4 | 3231 | for (i = 0; i < adapter->num_tx_queues; i++) |
4a0b9ca0 | 3232 | ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]); |
9a799d71 AK |
3233 | } |
3234 | ||
3235 | void ixgbe_down(struct ixgbe_adapter *adapter) | |
3236 | { | |
3237 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 3238 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 3239 | u32 rxctrl; |
7f821875 JB |
3240 | u32 txdctl; |
3241 | int i, j; | |
9a799d71 AK |
3242 | |
3243 | /* signal that we are down to the interrupt handler */ | |
3244 | set_bit(__IXGBE_DOWN, &adapter->state); | |
3245 | ||
767081ad GR |
3246 | /* disable receive for all VFs and wait one second */ |
3247 | if (adapter->num_vfs) { | |
767081ad GR |
3248 | /* ping all the active vfs to let them know we are going down */ |
3249 | ixgbe_ping_all_vfs(adapter); | |
581d1aa7 | 3250 | |
767081ad GR |
3251 | /* Disable all VFTE/VFRE TX/RX */ |
3252 | ixgbe_disable_tx_rx(adapter); | |
581d1aa7 GR |
3253 | |
3254 | /* Mark all the VFs as inactive */ | |
3255 | for (i = 0 ; i < adapter->num_vfs; i++) | |
3256 | adapter->vfinfo[i].clear_to_send = 0; | |
767081ad GR |
3257 | } |
3258 | ||
9a799d71 | 3259 | /* disable receives */ |
7f821875 JB |
3260 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
3261 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 AK |
3262 | |
3263 | netif_tx_disable(netdev); | |
3264 | ||
7f821875 | 3265 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
3266 | msleep(10); |
3267 | ||
7f821875 JB |
3268 | netif_tx_stop_all_queues(netdev); |
3269 | ||
9a799d71 AK |
3270 | ixgbe_irq_disable(adapter); |
3271 | ||
021230d4 | 3272 | ixgbe_napi_disable_all(adapter); |
7f821875 | 3273 | |
0a1f87cb DS |
3274 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); |
3275 | del_timer_sync(&adapter->sfp_timer); | |
9a799d71 | 3276 | del_timer_sync(&adapter->watchdog_timer); |
cf8280ee | 3277 | cancel_work_sync(&adapter->watchdog_task); |
9a799d71 | 3278 | |
c4cf55e5 PWJ |
3279 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
3280 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
3281 | cancel_work_sync(&adapter->fdir_reinit_task); | |
3282 | ||
7f821875 JB |
3283 | /* disable transmits in the hardware now that interrupts are off */ |
3284 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 3285 | j = adapter->tx_ring[i]->reg_idx; |
7f821875 JB |
3286 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); |
3287 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), | |
3288 | (txdctl & ~IXGBE_TXDCTL_ENABLE)); | |
3289 | } | |
88512539 PW |
3290 | /* Disable the Tx DMA engine on 82599 */ |
3291 | if (hw->mac.type == ixgbe_mac_82599EB) | |
3292 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, | |
3293 | (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & | |
3294 | ~IXGBE_DMATXCTL_TE)); | |
7f821875 | 3295 | |
9a799d71 | 3296 | netif_carrier_off(netdev); |
9a799d71 | 3297 | |
9a713e7c PW |
3298 | /* clear n-tuple filters that are cached */ |
3299 | ethtool_ntuple_flush(netdev); | |
3300 | ||
6f4a0e45 PL |
3301 | if (!pci_channel_offline(adapter->pdev)) |
3302 | ixgbe_reset(adapter); | |
9a799d71 AK |
3303 | ixgbe_clean_all_tx_rings(adapter); |
3304 | ixgbe_clean_all_rx_rings(adapter); | |
3305 | ||
5dd2d332 | 3306 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 | 3307 | /* since we reset the hardware DCA settings were cleared */ |
e35ec126 | 3308 | ixgbe_setup_dca(adapter); |
96b0e0f6 | 3309 | #endif |
9a799d71 AK |
3310 | } |
3311 | ||
9a799d71 | 3312 | /** |
021230d4 AV |
3313 | * ixgbe_poll - NAPI Rx polling callback |
3314 | * @napi: structure for representing this polling device | |
3315 | * @budget: how many packets driver is allowed to clean | |
3316 | * | |
3317 | * This function is used for legacy and MSI, NAPI mode | |
9a799d71 | 3318 | **/ |
021230d4 | 3319 | static int ixgbe_poll(struct napi_struct *napi, int budget) |
9a799d71 | 3320 | { |
9a1a69ad JB |
3321 | struct ixgbe_q_vector *q_vector = |
3322 | container_of(napi, struct ixgbe_q_vector, napi); | |
021230d4 | 3323 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a1a69ad | 3324 | int tx_clean_complete, work_done = 0; |
9a799d71 | 3325 | |
5dd2d332 | 3326 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 3327 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
4a0b9ca0 PW |
3328 | ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]); |
3329 | ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]); | |
bd0362dd JC |
3330 | } |
3331 | #endif | |
3332 | ||
4a0b9ca0 PW |
3333 | tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]); |
3334 | ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget); | |
9a799d71 | 3335 | |
9a1a69ad | 3336 | if (!tx_clean_complete) |
d2c7ddd6 DM |
3337 | work_done = budget; |
3338 | ||
53e52c72 DM |
3339 | /* If budget not fully consumed, exit the polling mode */ |
3340 | if (work_done < budget) { | |
288379f0 | 3341 | napi_complete(napi); |
f7554a2b | 3342 | if (adapter->rx_itr_setting & 1) |
f494e8fa | 3343 | ixgbe_set_itr(adapter); |
d4f80882 | 3344 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
835462fc | 3345 | ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE); |
9a799d71 | 3346 | } |
9a799d71 AK |
3347 | return work_done; |
3348 | } | |
3349 | ||
3350 | /** | |
3351 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
3352 | * @netdev: network interface device structure | |
3353 | **/ | |
3354 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
3355 | { | |
3356 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3357 | ||
3358 | /* Do the reset outside of interrupt context */ | |
3359 | schedule_work(&adapter->reset_task); | |
3360 | } | |
3361 | ||
3362 | static void ixgbe_reset_task(struct work_struct *work) | |
3363 | { | |
3364 | struct ixgbe_adapter *adapter; | |
3365 | adapter = container_of(work, struct ixgbe_adapter, reset_task); | |
3366 | ||
2f90b865 AD |
3367 | /* If we're already down or resetting, just bail */ |
3368 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
3369 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
3370 | return; | |
3371 | ||
9a799d71 AK |
3372 | adapter->tx_timeout_count++; |
3373 | ||
d4f80882 | 3374 | ixgbe_reinit_locked(adapter); |
9a799d71 AK |
3375 | } |
3376 | ||
bc97114d PWJ |
3377 | #ifdef CONFIG_IXGBE_DCB |
3378 | static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter) | |
b9804972 | 3379 | { |
bc97114d | 3380 | bool ret = false; |
0cefafad | 3381 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB]; |
b9804972 | 3382 | |
0cefafad JB |
3383 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) |
3384 | return ret; | |
3385 | ||
3386 | f->mask = 0x7 << 3; | |
3387 | adapter->num_rx_queues = f->indices; | |
3388 | adapter->num_tx_queues = f->indices; | |
3389 | ret = true; | |
2f90b865 | 3390 | |
bc97114d PWJ |
3391 | return ret; |
3392 | } | |
3393 | #endif | |
3394 | ||
4df10466 JB |
3395 | /** |
3396 | * ixgbe_set_rss_queues: Allocate queues for RSS | |
3397 | * @adapter: board private structure to initialize | |
3398 | * | |
3399 | * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try | |
3400 | * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. | |
3401 | * | |
3402 | **/ | |
bc97114d PWJ |
3403 | static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter) |
3404 | { | |
3405 | bool ret = false; | |
0cefafad | 3406 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS]; |
bc97114d PWJ |
3407 | |
3408 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
0cefafad JB |
3409 | f->mask = 0xF; |
3410 | adapter->num_rx_queues = f->indices; | |
3411 | adapter->num_tx_queues = f->indices; | |
bc97114d PWJ |
3412 | ret = true; |
3413 | } else { | |
bc97114d | 3414 | ret = false; |
b9804972 JB |
3415 | } |
3416 | ||
bc97114d PWJ |
3417 | return ret; |
3418 | } | |
3419 | ||
c4cf55e5 PWJ |
3420 | /** |
3421 | * ixgbe_set_fdir_queues: Allocate queues for Flow Director | |
3422 | * @adapter: board private structure to initialize | |
3423 | * | |
3424 | * Flow Director is an advanced Rx filter, attempting to get Rx flows back | |
3425 | * to the original CPU that initiated the Tx session. This runs in addition | |
3426 | * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the | |
3427 | * Rx load across CPUs using RSS. | |
3428 | * | |
3429 | **/ | |
3430 | static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter) | |
3431 | { | |
3432 | bool ret = false; | |
3433 | struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR]; | |
3434 | ||
3435 | f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices); | |
3436 | f_fdir->mask = 0; | |
3437 | ||
3438 | /* Flow Director must have RSS enabled */ | |
3439 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED && | |
3440 | ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || | |
3441 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) { | |
3442 | adapter->num_tx_queues = f_fdir->indices; | |
3443 | adapter->num_rx_queues = f_fdir->indices; | |
3444 | ret = true; | |
3445 | } else { | |
3446 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
3447 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
3448 | } | |
3449 | return ret; | |
3450 | } | |
3451 | ||
0331a832 YZ |
3452 | #ifdef IXGBE_FCOE |
3453 | /** | |
3454 | * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE) | |
3455 | * @adapter: board private structure to initialize | |
3456 | * | |
3457 | * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges. | |
3458 | * The ring feature mask is not used as a mask for FCoE, as it can take any 8 | |
3459 | * rx queues out of the max number of rx queues, instead, it is used as the | |
3460 | * index of the first rx queue used by FCoE. | |
3461 | * | |
3462 | **/ | |
3463 | static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter) | |
3464 | { | |
3465 | bool ret = false; | |
3466 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; | |
3467 | ||
3468 | f->indices = min((int)num_online_cpus(), f->indices); | |
3469 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
8de8b2e6 YZ |
3470 | adapter->num_rx_queues = 1; |
3471 | adapter->num_tx_queues = 1; | |
0331a832 YZ |
3472 | #ifdef CONFIG_IXGBE_DCB |
3473 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
8de8b2e6 | 3474 | DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n"); |
0331a832 YZ |
3475 | ixgbe_set_dcb_queues(adapter); |
3476 | } | |
3477 | #endif | |
3478 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
8de8b2e6 | 3479 | DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n"); |
8faa2a78 YZ |
3480 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || |
3481 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) | |
3482 | ixgbe_set_fdir_queues(adapter); | |
3483 | else | |
3484 | ixgbe_set_rss_queues(adapter); | |
0331a832 YZ |
3485 | } |
3486 | /* adding FCoE rx rings to the end */ | |
3487 | f->mask = adapter->num_rx_queues; | |
3488 | adapter->num_rx_queues += f->indices; | |
8de8b2e6 | 3489 | adapter->num_tx_queues += f->indices; |
0331a832 YZ |
3490 | |
3491 | ret = true; | |
3492 | } | |
3493 | ||
3494 | return ret; | |
3495 | } | |
3496 | ||
3497 | #endif /* IXGBE_FCOE */ | |
1cdd1ec8 GR |
3498 | /** |
3499 | * ixgbe_set_sriov_queues: Allocate queues for IOV use | |
3500 | * @adapter: board private structure to initialize | |
3501 | * | |
3502 | * IOV doesn't actually use anything, so just NAK the | |
3503 | * request for now and let the other queue routines | |
3504 | * figure out what to do. | |
3505 | */ | |
3506 | static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter) | |
3507 | { | |
3508 | return false; | |
3509 | } | |
3510 | ||
4df10466 JB |
3511 | /* |
3512 | * ixgbe_set_num_queues: Allocate queues for device, feature dependant | |
3513 | * @adapter: board private structure to initialize | |
3514 | * | |
3515 | * This is the top level queue allocation routine. The order here is very | |
3516 | * important, starting with the "most" number of features turned on at once, | |
3517 | * and ending with the smallest set of features. This way large combinations | |
3518 | * can be allocated if they're turned on, and smaller combinations are the | |
3519 | * fallthrough conditions. | |
3520 | * | |
3521 | **/ | |
bc97114d PWJ |
3522 | static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter) |
3523 | { | |
1cdd1ec8 GR |
3524 | /* Start with base case */ |
3525 | adapter->num_rx_queues = 1; | |
3526 | adapter->num_tx_queues = 1; | |
3527 | adapter->num_rx_pools = adapter->num_rx_queues; | |
3528 | adapter->num_rx_queues_per_pool = 1; | |
3529 | ||
3530 | if (ixgbe_set_sriov_queues(adapter)) | |
3531 | return; | |
3532 | ||
0331a832 YZ |
3533 | #ifdef IXGBE_FCOE |
3534 | if (ixgbe_set_fcoe_queues(adapter)) | |
3535 | goto done; | |
3536 | ||
3537 | #endif /* IXGBE_FCOE */ | |
bc97114d PWJ |
3538 | #ifdef CONFIG_IXGBE_DCB |
3539 | if (ixgbe_set_dcb_queues(adapter)) | |
af22ab1b | 3540 | goto done; |
bc97114d PWJ |
3541 | |
3542 | #endif | |
c4cf55e5 PWJ |
3543 | if (ixgbe_set_fdir_queues(adapter)) |
3544 | goto done; | |
3545 | ||
bc97114d | 3546 | if (ixgbe_set_rss_queues(adapter)) |
af22ab1b WF |
3547 | goto done; |
3548 | ||
3549 | /* fallback to base case */ | |
3550 | adapter->num_rx_queues = 1; | |
3551 | adapter->num_tx_queues = 1; | |
3552 | ||
3553 | done: | |
3554 | /* Notify the stack of the (possibly) reduced Tx Queue count. */ | |
3555 | adapter->netdev->real_num_tx_queues = adapter->num_tx_queues; | |
b9804972 JB |
3556 | } |
3557 | ||
021230d4 | 3558 | static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 3559 | int vectors) |
021230d4 AV |
3560 | { |
3561 | int err, vector_threshold; | |
3562 | ||
3563 | /* We'll want at least 3 (vector_threshold): | |
3564 | * 1) TxQ[0] Cleanup | |
3565 | * 2) RxQ[0] Cleanup | |
3566 | * 3) Other (Link Status Change, etc.) | |
3567 | * 4) TCP Timer (optional) | |
3568 | */ | |
3569 | vector_threshold = MIN_MSIX_COUNT; | |
3570 | ||
3571 | /* The more we get, the more we will assign to Tx/Rx Cleanup | |
3572 | * for the separate queues...where Rx Cleanup >= Tx Cleanup. | |
3573 | * Right now, we simply care about how many we'll get; we'll | |
3574 | * set them up later while requesting irq's. | |
3575 | */ | |
3576 | while (vectors >= vector_threshold) { | |
3577 | err = pci_enable_msix(adapter->pdev, adapter->msix_entries, | |
b4617240 | 3578 | vectors); |
021230d4 AV |
3579 | if (!err) /* Success in acquiring all requested vectors. */ |
3580 | break; | |
3581 | else if (err < 0) | |
3582 | vectors = 0; /* Nasty failure, quit now */ | |
3583 | else /* err == number of vectors we should try again with */ | |
3584 | vectors = err; | |
3585 | } | |
3586 | ||
3587 | if (vectors < vector_threshold) { | |
3588 | /* Can't allocate enough MSI-X interrupts? Oh well. | |
3589 | * This just means we'll go with either a single MSI | |
3590 | * vector or fall back to legacy interrupts. | |
3591 | */ | |
3592 | DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n"); | |
3593 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
3594 | kfree(adapter->msix_entries); | |
3595 | adapter->msix_entries = NULL; | |
021230d4 AV |
3596 | } else { |
3597 | adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */ | |
eb7f139c PWJ |
3598 | /* |
3599 | * Adjust for only the vectors we'll use, which is minimum | |
3600 | * of max_msix_q_vectors + NON_Q_VECTORS, or the number of | |
3601 | * vectors we were allocated. | |
3602 | */ | |
3603 | adapter->num_msix_vectors = min(vectors, | |
3604 | adapter->max_msix_q_vectors + NON_Q_VECTORS); | |
021230d4 AV |
3605 | } |
3606 | } | |
3607 | ||
021230d4 | 3608 | /** |
bc97114d | 3609 | * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS |
021230d4 AV |
3610 | * @adapter: board private structure to initialize |
3611 | * | |
bc97114d PWJ |
3612 | * Cache the descriptor ring offsets for RSS to the assigned rings. |
3613 | * | |
021230d4 | 3614 | **/ |
bc97114d | 3615 | static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter) |
021230d4 | 3616 | { |
bc97114d PWJ |
3617 | int i; |
3618 | bool ret = false; | |
3619 | ||
3620 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
3621 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 | 3622 | adapter->rx_ring[i]->reg_idx = i; |
bc97114d | 3623 | for (i = 0; i < adapter->num_tx_queues; i++) |
4a0b9ca0 | 3624 | adapter->tx_ring[i]->reg_idx = i; |
bc97114d PWJ |
3625 | ret = true; |
3626 | } else { | |
3627 | ret = false; | |
3628 | } | |
3629 | ||
3630 | return ret; | |
3631 | } | |
3632 | ||
3633 | #ifdef CONFIG_IXGBE_DCB | |
3634 | /** | |
3635 | * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB | |
3636 | * @adapter: board private structure to initialize | |
3637 | * | |
3638 | * Cache the descriptor ring offsets for DCB to the assigned rings. | |
3639 | * | |
3640 | **/ | |
3641 | static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) | |
3642 | { | |
3643 | int i; | |
3644 | bool ret = false; | |
3645 | int dcb_i = adapter->ring_feature[RING_F_DCB].indices; | |
3646 | ||
3647 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
3648 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
2f90b865 AD |
3649 | /* the number of queues is assumed to be symmetric */ |
3650 | for (i = 0; i < dcb_i; i++) { | |
4a0b9ca0 PW |
3651 | adapter->rx_ring[i]->reg_idx = i << 3; |
3652 | adapter->tx_ring[i]->reg_idx = i << 2; | |
2f90b865 | 3653 | } |
bc97114d | 3654 | ret = true; |
e8e26350 | 3655 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
f92ef202 PW |
3656 | if (dcb_i == 8) { |
3657 | /* | |
3658 | * Tx TC0 starts at: descriptor queue 0 | |
3659 | * Tx TC1 starts at: descriptor queue 32 | |
3660 | * Tx TC2 starts at: descriptor queue 64 | |
3661 | * Tx TC3 starts at: descriptor queue 80 | |
3662 | * Tx TC4 starts at: descriptor queue 96 | |
3663 | * Tx TC5 starts at: descriptor queue 104 | |
3664 | * Tx TC6 starts at: descriptor queue 112 | |
3665 | * Tx TC7 starts at: descriptor queue 120 | |
3666 | * | |
3667 | * Rx TC0-TC7 are offset by 16 queues each | |
3668 | */ | |
3669 | for (i = 0; i < 3; i++) { | |
4a0b9ca0 PW |
3670 | adapter->tx_ring[i]->reg_idx = i << 5; |
3671 | adapter->rx_ring[i]->reg_idx = i << 4; | |
f92ef202 PW |
3672 | } |
3673 | for ( ; i < 5; i++) { | |
4a0b9ca0 | 3674 | adapter->tx_ring[i]->reg_idx = |
f92ef202 | 3675 | ((i + 2) << 4); |
4a0b9ca0 | 3676 | adapter->rx_ring[i]->reg_idx = i << 4; |
f92ef202 PW |
3677 | } |
3678 | for ( ; i < dcb_i; i++) { | |
4a0b9ca0 | 3679 | adapter->tx_ring[i]->reg_idx = |
f92ef202 | 3680 | ((i + 8) << 3); |
4a0b9ca0 | 3681 | adapter->rx_ring[i]->reg_idx = i << 4; |
f92ef202 PW |
3682 | } |
3683 | ||
3684 | ret = true; | |
3685 | } else if (dcb_i == 4) { | |
3686 | /* | |
3687 | * Tx TC0 starts at: descriptor queue 0 | |
3688 | * Tx TC1 starts at: descriptor queue 64 | |
3689 | * Tx TC2 starts at: descriptor queue 96 | |
3690 | * Tx TC3 starts at: descriptor queue 112 | |
3691 | * | |
3692 | * Rx TC0-TC3 are offset by 32 queues each | |
3693 | */ | |
4a0b9ca0 PW |
3694 | adapter->tx_ring[0]->reg_idx = 0; |
3695 | adapter->tx_ring[1]->reg_idx = 64; | |
3696 | adapter->tx_ring[2]->reg_idx = 96; | |
3697 | adapter->tx_ring[3]->reg_idx = 112; | |
f92ef202 | 3698 | for (i = 0 ; i < dcb_i; i++) |
4a0b9ca0 | 3699 | adapter->rx_ring[i]->reg_idx = i << 5; |
f92ef202 PW |
3700 | |
3701 | ret = true; | |
3702 | } else { | |
3703 | ret = false; | |
e8e26350 | 3704 | } |
bc97114d PWJ |
3705 | } else { |
3706 | ret = false; | |
021230d4 | 3707 | } |
bc97114d PWJ |
3708 | } else { |
3709 | ret = false; | |
021230d4 | 3710 | } |
bc97114d PWJ |
3711 | |
3712 | return ret; | |
3713 | } | |
3714 | #endif | |
3715 | ||
c4cf55e5 PWJ |
3716 | /** |
3717 | * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director | |
3718 | * @adapter: board private structure to initialize | |
3719 | * | |
3720 | * Cache the descriptor ring offsets for Flow Director to the assigned rings. | |
3721 | * | |
3722 | **/ | |
3723 | static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter) | |
3724 | { | |
3725 | int i; | |
3726 | bool ret = false; | |
3727 | ||
3728 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED && | |
3729 | ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || | |
3730 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) { | |
3731 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 | 3732 | adapter->rx_ring[i]->reg_idx = i; |
c4cf55e5 | 3733 | for (i = 0; i < adapter->num_tx_queues; i++) |
4a0b9ca0 | 3734 | adapter->tx_ring[i]->reg_idx = i; |
c4cf55e5 PWJ |
3735 | ret = true; |
3736 | } | |
3737 | ||
3738 | return ret; | |
3739 | } | |
3740 | ||
0331a832 YZ |
3741 | #ifdef IXGBE_FCOE |
3742 | /** | |
3743 | * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE | |
3744 | * @adapter: board private structure to initialize | |
3745 | * | |
3746 | * Cache the descriptor ring offsets for FCoE mode to the assigned rings. | |
3747 | * | |
3748 | */ | |
3749 | static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter) | |
3750 | { | |
8de8b2e6 | 3751 | int i, fcoe_rx_i = 0, fcoe_tx_i = 0; |
0331a832 YZ |
3752 | bool ret = false; |
3753 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; | |
3754 | ||
3755 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
3756 | #ifdef CONFIG_IXGBE_DCB | |
3757 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
8de8b2e6 YZ |
3758 | struct ixgbe_fcoe *fcoe = &adapter->fcoe; |
3759 | ||
0331a832 | 3760 | ixgbe_cache_ring_dcb(adapter); |
8de8b2e6 | 3761 | /* find out queues in TC for FCoE */ |
4a0b9ca0 PW |
3762 | fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1; |
3763 | fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1; | |
8de8b2e6 YZ |
3764 | /* |
3765 | * In 82599, the number of Tx queues for each traffic | |
3766 | * class for both 8-TC and 4-TC modes are: | |
3767 | * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 | |
3768 | * 8 TCs: 32 32 16 16 8 8 8 8 | |
3769 | * 4 TCs: 64 64 32 32 | |
3770 | * We have max 8 queues for FCoE, where 8 the is | |
3771 | * FCoE redirection table size. If TC for FCoE is | |
3772 | * less than or equal to TC3, we have enough queues | |
3773 | * to add max of 8 queues for FCoE, so we start FCoE | |
3774 | * tx descriptor from the next one, i.e., reg_idx + 1. | |
3775 | * If TC for FCoE is above TC3, implying 8 TC mode, | |
3776 | * and we need 8 for FCoE, we have to take all queues | |
3777 | * in that traffic class for FCoE. | |
3778 | */ | |
3779 | if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3)) | |
3780 | fcoe_tx_i--; | |
0331a832 YZ |
3781 | } |
3782 | #endif /* CONFIG_IXGBE_DCB */ | |
3783 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
8faa2a78 YZ |
3784 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || |
3785 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) | |
3786 | ixgbe_cache_ring_fdir(adapter); | |
3787 | else | |
3788 | ixgbe_cache_ring_rss(adapter); | |
3789 | ||
8de8b2e6 YZ |
3790 | fcoe_rx_i = f->mask; |
3791 | fcoe_tx_i = f->mask; | |
3792 | } | |
3793 | for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) { | |
4a0b9ca0 PW |
3794 | adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i; |
3795 | adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i; | |
0331a832 | 3796 | } |
0331a832 YZ |
3797 | ret = true; |
3798 | } | |
3799 | return ret; | |
3800 | } | |
3801 | ||
3802 | #endif /* IXGBE_FCOE */ | |
1cdd1ec8 GR |
3803 | /** |
3804 | * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov | |
3805 | * @adapter: board private structure to initialize | |
3806 | * | |
3807 | * SR-IOV doesn't use any descriptor rings but changes the default if | |
3808 | * no other mapping is used. | |
3809 | * | |
3810 | */ | |
3811 | static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter) | |
3812 | { | |
4a0b9ca0 PW |
3813 | adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2; |
3814 | adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2; | |
1cdd1ec8 GR |
3815 | if (adapter->num_vfs) |
3816 | return true; | |
3817 | else | |
3818 | return false; | |
3819 | } | |
3820 | ||
bc97114d PWJ |
3821 | /** |
3822 | * ixgbe_cache_ring_register - Descriptor ring to register mapping | |
3823 | * @adapter: board private structure to initialize | |
3824 | * | |
3825 | * Once we know the feature-set enabled for the device, we'll cache | |
3826 | * the register offset the descriptor ring is assigned to. | |
3827 | * | |
3828 | * Note, the order the various feature calls is important. It must start with | |
3829 | * the "most" features enabled at the same time, then trickle down to the | |
3830 | * least amount of features turned on at once. | |
3831 | **/ | |
3832 | static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) | |
3833 | { | |
3834 | /* start with default case */ | |
4a0b9ca0 PW |
3835 | adapter->rx_ring[0]->reg_idx = 0; |
3836 | adapter->tx_ring[0]->reg_idx = 0; | |
bc97114d | 3837 | |
1cdd1ec8 GR |
3838 | if (ixgbe_cache_ring_sriov(adapter)) |
3839 | return; | |
3840 | ||
0331a832 YZ |
3841 | #ifdef IXGBE_FCOE |
3842 | if (ixgbe_cache_ring_fcoe(adapter)) | |
3843 | return; | |
3844 | ||
3845 | #endif /* IXGBE_FCOE */ | |
bc97114d PWJ |
3846 | #ifdef CONFIG_IXGBE_DCB |
3847 | if (ixgbe_cache_ring_dcb(adapter)) | |
3848 | return; | |
3849 | ||
3850 | #endif | |
c4cf55e5 PWJ |
3851 | if (ixgbe_cache_ring_fdir(adapter)) |
3852 | return; | |
3853 | ||
bc97114d PWJ |
3854 | if (ixgbe_cache_ring_rss(adapter)) |
3855 | return; | |
021230d4 AV |
3856 | } |
3857 | ||
9a799d71 AK |
3858 | /** |
3859 | * ixgbe_alloc_queues - Allocate memory for all rings | |
3860 | * @adapter: board private structure to initialize | |
3861 | * | |
3862 | * We allocate one ring per queue at run-time since we don't know the | |
4df10466 JB |
3863 | * number of queues at compile-time. The polling_netdev array is |
3864 | * intended for Multiqueue, but should work fine with a single queue. | |
9a799d71 | 3865 | **/ |
2f90b865 | 3866 | static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter) |
9a799d71 AK |
3867 | { |
3868 | int i; | |
4a0b9ca0 | 3869 | int orig_node = adapter->node; |
9a799d71 | 3870 | |
021230d4 | 3871 | for (i = 0; i < adapter->num_tx_queues; i++) { |
4a0b9ca0 PW |
3872 | struct ixgbe_ring *ring = adapter->tx_ring[i]; |
3873 | if (orig_node == -1) { | |
3874 | int cur_node = next_online_node(adapter->node); | |
3875 | if (cur_node == MAX_NUMNODES) | |
3876 | cur_node = first_online_node; | |
3877 | adapter->node = cur_node; | |
3878 | } | |
3879 | ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL, | |
3880 | adapter->node); | |
3881 | if (!ring) | |
3882 | ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL); | |
3883 | if (!ring) | |
3884 | goto err_tx_ring_allocation; | |
3885 | ring->count = adapter->tx_ring_count; | |
3886 | ring->queue_index = i; | |
3887 | ring->numa_node = adapter->node; | |
3888 | ||
3889 | adapter->tx_ring[i] = ring; | |
021230d4 | 3890 | } |
b9804972 | 3891 | |
4a0b9ca0 PW |
3892 | /* Restore the adapter's original node */ |
3893 | adapter->node = orig_node; | |
3894 | ||
9a799d71 | 3895 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 PW |
3896 | struct ixgbe_ring *ring = adapter->rx_ring[i]; |
3897 | if (orig_node == -1) { | |
3898 | int cur_node = next_online_node(adapter->node); | |
3899 | if (cur_node == MAX_NUMNODES) | |
3900 | cur_node = first_online_node; | |
3901 | adapter->node = cur_node; | |
3902 | } | |
3903 | ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL, | |
3904 | adapter->node); | |
3905 | if (!ring) | |
3906 | ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL); | |
3907 | if (!ring) | |
3908 | goto err_rx_ring_allocation; | |
3909 | ring->count = adapter->rx_ring_count; | |
3910 | ring->queue_index = i; | |
3911 | ring->numa_node = adapter->node; | |
3912 | ||
3913 | adapter->rx_ring[i] = ring; | |
021230d4 AV |
3914 | } |
3915 | ||
4a0b9ca0 PW |
3916 | /* Restore the adapter's original node */ |
3917 | adapter->node = orig_node; | |
3918 | ||
021230d4 AV |
3919 | ixgbe_cache_ring_register(adapter); |
3920 | ||
3921 | return 0; | |
3922 | ||
3923 | err_rx_ring_allocation: | |
4a0b9ca0 PW |
3924 | for (i = 0; i < adapter->num_tx_queues; i++) |
3925 | kfree(adapter->tx_ring[i]); | |
021230d4 AV |
3926 | err_tx_ring_allocation: |
3927 | return -ENOMEM; | |
3928 | } | |
3929 | ||
3930 | /** | |
3931 | * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported | |
3932 | * @adapter: board private structure to initialize | |
3933 | * | |
3934 | * Attempt to configure the interrupts using the best available | |
3935 | * capabilities of the hardware and the kernel. | |
3936 | **/ | |
feea6a57 | 3937 | static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 | 3938 | { |
8be0e467 | 3939 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 AV |
3940 | int err = 0; |
3941 | int vector, v_budget; | |
3942 | ||
3943 | /* | |
3944 | * It's easy to be greedy for MSI-X vectors, but it really | |
3945 | * doesn't do us much good if we have a lot more vectors | |
3946 | * than CPU's. So let's be conservative and only ask for | |
342bde1b | 3947 | * (roughly) the same number of vectors as there are CPU's. |
021230d4 AV |
3948 | */ |
3949 | v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues, | |
342bde1b | 3950 | (int)num_online_cpus()) + NON_Q_VECTORS; |
021230d4 AV |
3951 | |
3952 | /* | |
3953 | * At the same time, hardware can only support a maximum of | |
8be0e467 PW |
3954 | * hw.mac->max_msix_vectors vectors. With features |
3955 | * such as RSS and VMDq, we can easily surpass the number of Rx and Tx | |
3956 | * descriptor queues supported by our device. Thus, we cap it off in | |
3957 | * those rare cases where the cpu count also exceeds our vector limit. | |
021230d4 | 3958 | */ |
8be0e467 | 3959 | v_budget = min(v_budget, (int)hw->mac.max_msix_vectors); |
021230d4 AV |
3960 | |
3961 | /* A failure in MSI-X entry allocation isn't fatal, but it does | |
3962 | * mean we disable MSI-X capabilities of the adapter. */ | |
3963 | adapter->msix_entries = kcalloc(v_budget, | |
b4617240 | 3964 | sizeof(struct msix_entry), GFP_KERNEL); |
7a921c93 AD |
3965 | if (adapter->msix_entries) { |
3966 | for (vector = 0; vector < v_budget; vector++) | |
3967 | adapter->msix_entries[vector].entry = vector; | |
021230d4 | 3968 | |
7a921c93 | 3969 | ixgbe_acquire_msix_vectors(adapter, v_budget); |
021230d4 | 3970 | |
7a921c93 AD |
3971 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
3972 | goto out; | |
3973 | } | |
021230d4 | 3974 | |
7a921c93 AD |
3975 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; |
3976 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
c4cf55e5 PWJ |
3977 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; |
3978 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
3979 | adapter->atr_sample_rate = 0; | |
1cdd1ec8 GR |
3980 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
3981 | ixgbe_disable_sriov(adapter); | |
3982 | ||
7a921c93 | 3983 | ixgbe_set_num_queues(adapter); |
021230d4 | 3984 | |
021230d4 AV |
3985 | err = pci_enable_msi(adapter->pdev); |
3986 | if (!err) { | |
3987 | adapter->flags |= IXGBE_FLAG_MSI_ENABLED; | |
3988 | } else { | |
3989 | DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, " | |
b4617240 | 3990 | "falling back to legacy. Error: %d\n", err); |
021230d4 AV |
3991 | /* reset err */ |
3992 | err = 0; | |
3993 | } | |
3994 | ||
3995 | out: | |
021230d4 AV |
3996 | return err; |
3997 | } | |
3998 | ||
7a921c93 AD |
3999 | /** |
4000 | * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors | |
4001 | * @adapter: board private structure to initialize | |
4002 | * | |
4003 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
4004 | * return -ENOMEM. | |
4005 | **/ | |
4006 | static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter) | |
4007 | { | |
4008 | int q_idx, num_q_vectors; | |
4009 | struct ixgbe_q_vector *q_vector; | |
4010 | int napi_vectors; | |
4011 | int (*poll)(struct napi_struct *, int); | |
4012 | ||
4013 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
4014 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
4015 | napi_vectors = adapter->num_rx_queues; | |
91281fd3 | 4016 | poll = &ixgbe_clean_rxtx_many; |
7a921c93 AD |
4017 | } else { |
4018 | num_q_vectors = 1; | |
4019 | napi_vectors = 1; | |
4020 | poll = &ixgbe_poll; | |
4021 | } | |
4022 | ||
4023 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
1a6c14a2 JB |
4024 | q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector), |
4025 | GFP_KERNEL, adapter->node); | |
4026 | if (!q_vector) | |
4027 | q_vector = kzalloc(sizeof(struct ixgbe_q_vector), | |
4028 | GFP_KERNEL); | |
7a921c93 AD |
4029 | if (!q_vector) |
4030 | goto err_out; | |
4031 | q_vector->adapter = adapter; | |
f7554a2b NS |
4032 | if (q_vector->txr_count && !q_vector->rxr_count) |
4033 | q_vector->eitr = adapter->tx_eitr_param; | |
4034 | else | |
4035 | q_vector->eitr = adapter->rx_eitr_param; | |
fe49f04a | 4036 | q_vector->v_idx = q_idx; |
91281fd3 | 4037 | netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64); |
7a921c93 AD |
4038 | adapter->q_vector[q_idx] = q_vector; |
4039 | } | |
4040 | ||
4041 | return 0; | |
4042 | ||
4043 | err_out: | |
4044 | while (q_idx) { | |
4045 | q_idx--; | |
4046 | q_vector = adapter->q_vector[q_idx]; | |
4047 | netif_napi_del(&q_vector->napi); | |
4048 | kfree(q_vector); | |
4049 | adapter->q_vector[q_idx] = NULL; | |
4050 | } | |
4051 | return -ENOMEM; | |
4052 | } | |
4053 | ||
4054 | /** | |
4055 | * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors | |
4056 | * @adapter: board private structure to initialize | |
4057 | * | |
4058 | * This function frees the memory allocated to the q_vectors. In addition if | |
4059 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
4060 | * to freeing the q_vector. | |
4061 | **/ | |
4062 | static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter) | |
4063 | { | |
4064 | int q_idx, num_q_vectors; | |
7a921c93 | 4065 | |
91281fd3 | 4066 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
7a921c93 | 4067 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
91281fd3 | 4068 | else |
7a921c93 | 4069 | num_q_vectors = 1; |
7a921c93 AD |
4070 | |
4071 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
4072 | struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx]; | |
7a921c93 | 4073 | adapter->q_vector[q_idx] = NULL; |
91281fd3 | 4074 | netif_napi_del(&q_vector->napi); |
7a921c93 AD |
4075 | kfree(q_vector); |
4076 | } | |
4077 | } | |
4078 | ||
7b25cdba | 4079 | static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 AV |
4080 | { |
4081 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
4082 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
4083 | pci_disable_msix(adapter->pdev); | |
4084 | kfree(adapter->msix_entries); | |
4085 | adapter->msix_entries = NULL; | |
4086 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
4087 | adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; | |
4088 | pci_disable_msi(adapter->pdev); | |
4089 | } | |
4090 | return; | |
4091 | } | |
4092 | ||
4093 | /** | |
4094 | * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme | |
4095 | * @adapter: board private structure to initialize | |
4096 | * | |
4097 | * We determine which interrupt scheme to use based on... | |
4098 | * - Kernel support (MSI, MSI-X) | |
4099 | * - which can be user-defined (via MODULE_PARAM) | |
4100 | * - Hardware queue count (num_*_queues) | |
4101 | * - defined by miscellaneous hardware support/features (RSS, etc.) | |
4102 | **/ | |
2f90b865 | 4103 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) |
021230d4 AV |
4104 | { |
4105 | int err; | |
4106 | ||
4107 | /* Number of supported queues */ | |
4108 | ixgbe_set_num_queues(adapter); | |
4109 | ||
021230d4 AV |
4110 | err = ixgbe_set_interrupt_capability(adapter); |
4111 | if (err) { | |
4112 | DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n"); | |
4113 | goto err_set_interrupt; | |
9a799d71 AK |
4114 | } |
4115 | ||
7a921c93 AD |
4116 | err = ixgbe_alloc_q_vectors(adapter); |
4117 | if (err) { | |
4118 | DPRINTK(PROBE, ERR, "Unable to allocate memory for queue " | |
4119 | "vectors\n"); | |
4120 | goto err_alloc_q_vectors; | |
4121 | } | |
4122 | ||
4123 | err = ixgbe_alloc_queues(adapter); | |
4124 | if (err) { | |
4125 | DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n"); | |
4126 | goto err_alloc_queues; | |
4127 | } | |
4128 | ||
021230d4 | 4129 | DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, " |
b4617240 PW |
4130 | "Tx Queue count = %u\n", |
4131 | (adapter->num_rx_queues > 1) ? "Enabled" : | |
4132 | "Disabled", adapter->num_rx_queues, adapter->num_tx_queues); | |
021230d4 AV |
4133 | |
4134 | set_bit(__IXGBE_DOWN, &adapter->state); | |
4135 | ||
9a799d71 | 4136 | return 0; |
021230d4 | 4137 | |
7a921c93 AD |
4138 | err_alloc_queues: |
4139 | ixgbe_free_q_vectors(adapter); | |
4140 | err_alloc_q_vectors: | |
4141 | ixgbe_reset_interrupt_capability(adapter); | |
021230d4 | 4142 | err_set_interrupt: |
7a921c93 AD |
4143 | return err; |
4144 | } | |
4145 | ||
4146 | /** | |
4147 | * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings | |
4148 | * @adapter: board private structure to clear interrupt scheme on | |
4149 | * | |
4150 | * We go through and clear interrupt specific resources and reset the structure | |
4151 | * to pre-load conditions | |
4152 | **/ | |
4153 | void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter) | |
4154 | { | |
4a0b9ca0 PW |
4155 | int i; |
4156 | ||
4157 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4158 | kfree(adapter->tx_ring[i]); | |
4159 | adapter->tx_ring[i] = NULL; | |
4160 | } | |
4161 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
4162 | kfree(adapter->rx_ring[i]); | |
4163 | adapter->rx_ring[i] = NULL; | |
4164 | } | |
7a921c93 AD |
4165 | |
4166 | ixgbe_free_q_vectors(adapter); | |
4167 | ixgbe_reset_interrupt_capability(adapter); | |
9a799d71 AK |
4168 | } |
4169 | ||
c4900be0 DS |
4170 | /** |
4171 | * ixgbe_sfp_timer - worker thread to find a missing module | |
4172 | * @data: pointer to our adapter struct | |
4173 | **/ | |
4174 | static void ixgbe_sfp_timer(unsigned long data) | |
4175 | { | |
4176 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
4177 | ||
4df10466 JB |
4178 | /* |
4179 | * Do the sfp_timer outside of interrupt context due to the | |
c4900be0 DS |
4180 | * delays that sfp+ detection requires |
4181 | */ | |
4182 | schedule_work(&adapter->sfp_task); | |
4183 | } | |
4184 | ||
4185 | /** | |
4186 | * ixgbe_sfp_task - worker thread to find a missing module | |
4187 | * @work: pointer to work_struct containing our data | |
4188 | **/ | |
4189 | static void ixgbe_sfp_task(struct work_struct *work) | |
4190 | { | |
4191 | struct ixgbe_adapter *adapter = container_of(work, | |
4192 | struct ixgbe_adapter, | |
4193 | sfp_task); | |
4194 | struct ixgbe_hw *hw = &adapter->hw; | |
4195 | ||
4196 | if ((hw->phy.type == ixgbe_phy_nl) && | |
4197 | (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) { | |
4198 | s32 ret = hw->phy.ops.identify_sfp(hw); | |
63d6e1d8 | 4199 | if (ret == IXGBE_ERR_SFP_NOT_PRESENT) |
c4900be0 DS |
4200 | goto reschedule; |
4201 | ret = hw->phy.ops.reset(hw); | |
4202 | if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
88d2b81f DS |
4203 | dev_err(&adapter->pdev->dev, "failed to initialize " |
4204 | "because an unsupported SFP+ module type " | |
4205 | "was detected.\n" | |
4206 | "Reload the driver after installing a " | |
4207 | "supported module.\n"); | |
c4900be0 DS |
4208 | unregister_netdev(adapter->netdev); |
4209 | } else { | |
4210 | DPRINTK(PROBE, INFO, "detected SFP+: %d\n", | |
4211 | hw->phy.sfp_type); | |
4212 | } | |
4213 | /* don't need this routine any more */ | |
4214 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
4215 | } | |
4216 | return; | |
4217 | reschedule: | |
4218 | if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state)) | |
4219 | mod_timer(&adapter->sfp_timer, | |
4220 | round_jiffies(jiffies + (2 * HZ))); | |
4221 | } | |
4222 | ||
9a799d71 AK |
4223 | /** |
4224 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
4225 | * @adapter: board private structure to initialize | |
4226 | * | |
4227 | * ixgbe_sw_init initializes the Adapter private data structure. | |
4228 | * Fields are initialized based on PCI device information and | |
4229 | * OS network device settings (MTU size). | |
4230 | **/ | |
4231 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
4232 | { | |
4233 | struct ixgbe_hw *hw = &adapter->hw; | |
4234 | struct pci_dev *pdev = adapter->pdev; | |
9a713e7c | 4235 | struct net_device *dev = adapter->netdev; |
021230d4 | 4236 | unsigned int rss; |
7a6b6f51 | 4237 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
4238 | int j; |
4239 | struct tc_configuration *tc; | |
4240 | #endif | |
021230d4 | 4241 | |
c44ade9e JB |
4242 | /* PCI config space info */ |
4243 | ||
4244 | hw->vendor_id = pdev->vendor; | |
4245 | hw->device_id = pdev->device; | |
4246 | hw->revision_id = pdev->revision; | |
4247 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
4248 | hw->subsystem_device_id = pdev->subsystem_device; | |
4249 | ||
021230d4 AV |
4250 | /* Set capability flags */ |
4251 | rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus()); | |
4252 | adapter->ring_feature[RING_F_RSS].indices = rss; | |
4253 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; | |
2f90b865 | 4254 | adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES; |
bf069c97 DS |
4255 | if (hw->mac.type == ixgbe_mac_82598EB) { |
4256 | if (hw->device_id == IXGBE_DEV_ID_82598AT) | |
4257 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
e8e26350 | 4258 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598; |
bf069c97 | 4259 | } else if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 | 4260 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599; |
0c19d6af PWJ |
4261 | adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; |
4262 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
9a713e7c PW |
4263 | if (dev->features & NETIF_F_NTUPLE) { |
4264 | /* Flow Director perfect filter enabled */ | |
4265 | adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
4266 | adapter->atr_sample_rate = 0; | |
4267 | spin_lock_init(&adapter->fdir_perfect_lock); | |
4268 | } else { | |
4269 | /* Flow Director hash filters enabled */ | |
4270 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
4271 | adapter->atr_sample_rate = 20; | |
4272 | } | |
c4cf55e5 PWJ |
4273 | adapter->ring_feature[RING_F_FDIR].indices = |
4274 | IXGBE_MAX_FDIR_INDICES; | |
c4cf55e5 | 4275 | adapter->fdir_pballoc = 0; |
eacd73f7 | 4276 | #ifdef IXGBE_FCOE |
0d551589 YZ |
4277 | adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; |
4278 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
4279 | adapter->ring_feature[RING_F_FCOE].indices = 0; | |
61a0f421 | 4280 | #ifdef CONFIG_IXGBE_DCB |
6ee16520 YZ |
4281 | /* Default traffic class to use for FCoE */ |
4282 | adapter->fcoe.tc = IXGBE_FCOE_DEFTC; | |
61a0f421 | 4283 | #endif |
eacd73f7 | 4284 | #endif /* IXGBE_FCOE */ |
f8212f97 | 4285 | } |
2f90b865 | 4286 | |
7a6b6f51 | 4287 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
4288 | /* Configure DCB traffic classes */ |
4289 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
4290 | tc = &adapter->dcb_cfg.tc_config[j]; | |
4291 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
4292 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
4293 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
4294 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
4295 | tc->dcb_pfc = pfc_disabled; | |
4296 | } | |
4297 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; | |
4298 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
4299 | adapter->dcb_cfg.rx_pba_cfg = pba_equal; | |
264857b8 | 4300 | adapter->dcb_cfg.pfc_mode_enable = false; |
2f90b865 AD |
4301 | adapter->dcb_cfg.round_robin_enable = false; |
4302 | adapter->dcb_set_bitmap = 0x00; | |
4303 | ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, | |
4304 | adapter->ring_feature[RING_F_DCB].indices); | |
4305 | ||
4306 | #endif | |
9a799d71 AK |
4307 | |
4308 | /* default flow control settings */ | |
cd7664f6 | 4309 | hw->fc.requested_mode = ixgbe_fc_full; |
71fd570b | 4310 | hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ |
264857b8 PWJ |
4311 | #ifdef CONFIG_DCB |
4312 | adapter->last_lfc_mode = hw->fc.current_mode; | |
4313 | #endif | |
2b9ade93 JB |
4314 | hw->fc.high_water = IXGBE_DEFAULT_FCRTH; |
4315 | hw->fc.low_water = IXGBE_DEFAULT_FCRTL; | |
4316 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; | |
4317 | hw->fc.send_xon = true; | |
71fd570b | 4318 | hw->fc.disable_fc_autoneg = false; |
9a799d71 | 4319 | |
30efa5a3 | 4320 | /* enable itr by default in dynamic mode */ |
f7554a2b NS |
4321 | adapter->rx_itr_setting = 1; |
4322 | adapter->rx_eitr_param = 20000; | |
4323 | adapter->tx_itr_setting = 1; | |
4324 | adapter->tx_eitr_param = 10000; | |
30efa5a3 JB |
4325 | |
4326 | /* set defaults for eitr in MegaBytes */ | |
4327 | adapter->eitr_low = 10; | |
4328 | adapter->eitr_high = 20; | |
4329 | ||
4330 | /* set default ring sizes */ | |
4331 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
4332 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
4333 | ||
9a799d71 | 4334 | /* initialize eeprom parameters */ |
c44ade9e | 4335 | if (ixgbe_init_eeprom_params_generic(hw)) { |
9a799d71 AK |
4336 | dev_err(&pdev->dev, "EEPROM initialization failed\n"); |
4337 | return -EIO; | |
4338 | } | |
4339 | ||
021230d4 | 4340 | /* enable rx csum by default */ |
9a799d71 AK |
4341 | adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED; |
4342 | ||
1a6c14a2 JB |
4343 | /* get assigned NUMA node */ |
4344 | adapter->node = dev_to_node(&pdev->dev); | |
4345 | ||
9a799d71 AK |
4346 | set_bit(__IXGBE_DOWN, &adapter->state); |
4347 | ||
4348 | return 0; | |
4349 | } | |
4350 | ||
4351 | /** | |
4352 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
4353 | * @adapter: board private structure | |
3a581073 | 4354 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
4355 | * |
4356 | * Return 0 on success, negative on failure | |
4357 | **/ | |
4358 | int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter, | |
e01c31a5 | 4359 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
4360 | { |
4361 | struct pci_dev *pdev = adapter->pdev; | |
4362 | int size; | |
4363 | ||
3a581073 | 4364 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
4a0b9ca0 | 4365 | tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node); |
1a6c14a2 JB |
4366 | if (!tx_ring->tx_buffer_info) |
4367 | tx_ring->tx_buffer_info = vmalloc(size); | |
e01c31a5 JB |
4368 | if (!tx_ring->tx_buffer_info) |
4369 | goto err; | |
3a581073 | 4370 | memset(tx_ring->tx_buffer_info, 0, size); |
9a799d71 AK |
4371 | |
4372 | /* round up to nearest 4K */ | |
12207e49 | 4373 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 4374 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 4375 | |
3a581073 JB |
4376 | tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, |
4377 | &tx_ring->dma); | |
e01c31a5 JB |
4378 | if (!tx_ring->desc) |
4379 | goto err; | |
9a799d71 | 4380 | |
3a581073 JB |
4381 | tx_ring->next_to_use = 0; |
4382 | tx_ring->next_to_clean = 0; | |
4383 | tx_ring->work_limit = tx_ring->count; | |
9a799d71 | 4384 | return 0; |
e01c31a5 JB |
4385 | |
4386 | err: | |
4387 | vfree(tx_ring->tx_buffer_info); | |
4388 | tx_ring->tx_buffer_info = NULL; | |
4389 | DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit " | |
4390 | "descriptor ring\n"); | |
4391 | return -ENOMEM; | |
9a799d71 AK |
4392 | } |
4393 | ||
69888674 AD |
4394 | /** |
4395 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
4396 | * @adapter: board private structure | |
4397 | * | |
4398 | * If this function returns with an error, then it's possible one or | |
4399 | * more of the rings is populated (while the rest are not). It is the | |
4400 | * callers duty to clean those orphaned rings. | |
4401 | * | |
4402 | * Return 0 on success, negative on failure | |
4403 | **/ | |
4404 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
4405 | { | |
4406 | int i, err = 0; | |
4407 | ||
4408 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 4409 | err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]); |
69888674 AD |
4410 | if (!err) |
4411 | continue; | |
4412 | DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i); | |
4413 | break; | |
4414 | } | |
4415 | ||
4416 | return err; | |
4417 | } | |
4418 | ||
9a799d71 AK |
4419 | /** |
4420 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
4421 | * @adapter: board private structure | |
3a581073 | 4422 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
4423 | * |
4424 | * Returns 0 on success, negative on failure | |
4425 | **/ | |
4426 | int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, | |
b4617240 | 4427 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
4428 | { |
4429 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 4430 | int size; |
9a799d71 | 4431 | |
3a581073 | 4432 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
1a6c14a2 JB |
4433 | rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node); |
4434 | if (!rx_ring->rx_buffer_info) | |
4435 | rx_ring->rx_buffer_info = vmalloc(size); | |
3a581073 | 4436 | if (!rx_ring->rx_buffer_info) { |
9a799d71 | 4437 | DPRINTK(PROBE, ERR, |
b4617240 | 4438 | "vmalloc allocation failed for the rx desc ring\n"); |
177db6ff | 4439 | goto alloc_failed; |
9a799d71 | 4440 | } |
3a581073 | 4441 | memset(rx_ring->rx_buffer_info, 0, size); |
9a799d71 | 4442 | |
9a799d71 | 4443 | /* Round up to nearest 4K */ |
3a581073 JB |
4444 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
4445 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 4446 | |
3a581073 | 4447 | rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma); |
9a799d71 | 4448 | |
3a581073 | 4449 | if (!rx_ring->desc) { |
9a799d71 | 4450 | DPRINTK(PROBE, ERR, |
b4617240 | 4451 | "Memory allocation failed for the rx desc ring\n"); |
3a581073 | 4452 | vfree(rx_ring->rx_buffer_info); |
177db6ff | 4453 | goto alloc_failed; |
9a799d71 AK |
4454 | } |
4455 | ||
3a581073 JB |
4456 | rx_ring->next_to_clean = 0; |
4457 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
4458 | |
4459 | return 0; | |
177db6ff MC |
4460 | |
4461 | alloc_failed: | |
177db6ff | 4462 | return -ENOMEM; |
9a799d71 AK |
4463 | } |
4464 | ||
69888674 AD |
4465 | /** |
4466 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
4467 | * @adapter: board private structure | |
4468 | * | |
4469 | * If this function returns with an error, then it's possible one or | |
4470 | * more of the rings is populated (while the rest are not). It is the | |
4471 | * callers duty to clean those orphaned rings. | |
4472 | * | |
4473 | * Return 0 on success, negative on failure | |
4474 | **/ | |
4475 | ||
4476 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) | |
4477 | { | |
4478 | int i, err = 0; | |
4479 | ||
4480 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
4a0b9ca0 | 4481 | err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]); |
69888674 AD |
4482 | if (!err) |
4483 | continue; | |
4484 | DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i); | |
4485 | break; | |
4486 | } | |
4487 | ||
4488 | return err; | |
4489 | } | |
4490 | ||
9a799d71 AK |
4491 | /** |
4492 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
4493 | * @adapter: board private structure | |
4494 | * @tx_ring: Tx descriptor ring for a specific queue | |
4495 | * | |
4496 | * Free all transmit software resources | |
4497 | **/ | |
c431f97e JB |
4498 | void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter, |
4499 | struct ixgbe_ring *tx_ring) | |
9a799d71 AK |
4500 | { |
4501 | struct pci_dev *pdev = adapter->pdev; | |
4502 | ||
4503 | ixgbe_clean_tx_ring(adapter, tx_ring); | |
4504 | ||
4505 | vfree(tx_ring->tx_buffer_info); | |
4506 | tx_ring->tx_buffer_info = NULL; | |
4507 | ||
4508 | pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma); | |
4509 | ||
4510 | tx_ring->desc = NULL; | |
4511 | } | |
4512 | ||
4513 | /** | |
4514 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
4515 | * @adapter: board private structure | |
4516 | * | |
4517 | * Free all transmit software resources | |
4518 | **/ | |
4519 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
4520 | { | |
4521 | int i; | |
4522 | ||
4523 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 PW |
4524 | if (adapter->tx_ring[i]->desc) |
4525 | ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]); | |
9a799d71 AK |
4526 | } |
4527 | ||
4528 | /** | |
b4617240 | 4529 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
4530 | * @adapter: board private structure |
4531 | * @rx_ring: ring to clean the resources from | |
4532 | * | |
4533 | * Free all receive software resources | |
4534 | **/ | |
c431f97e JB |
4535 | void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter, |
4536 | struct ixgbe_ring *rx_ring) | |
9a799d71 AK |
4537 | { |
4538 | struct pci_dev *pdev = adapter->pdev; | |
4539 | ||
4540 | ixgbe_clean_rx_ring(adapter, rx_ring); | |
4541 | ||
4542 | vfree(rx_ring->rx_buffer_info); | |
4543 | rx_ring->rx_buffer_info = NULL; | |
4544 | ||
4545 | pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); | |
4546 | ||
4547 | rx_ring->desc = NULL; | |
4548 | } | |
4549 | ||
4550 | /** | |
4551 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
4552 | * @adapter: board private structure | |
4553 | * | |
4554 | * Free all receive software resources | |
4555 | **/ | |
4556 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
4557 | { | |
4558 | int i; | |
4559 | ||
4560 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 PW |
4561 | if (adapter->rx_ring[i]->desc) |
4562 | ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]); | |
9a799d71 AK |
4563 | } |
4564 | ||
9a799d71 AK |
4565 | /** |
4566 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
4567 | * @netdev: network interface device structure | |
4568 | * @new_mtu: new value for maximum frame size | |
4569 | * | |
4570 | * Returns 0 on success, negative on failure | |
4571 | **/ | |
4572 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
4573 | { | |
4574 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4575 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
4576 | ||
42c783c5 JB |
4577 | /* MTU < 68 is an error and causes problems on some kernels */ |
4578 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) | |
9a799d71 AK |
4579 | return -EINVAL; |
4580 | ||
021230d4 | 4581 | DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n", |
b4617240 | 4582 | netdev->mtu, new_mtu); |
021230d4 | 4583 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
4584 | netdev->mtu = new_mtu; |
4585 | ||
d4f80882 AV |
4586 | if (netif_running(netdev)) |
4587 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
4588 | |
4589 | return 0; | |
4590 | } | |
4591 | ||
4592 | /** | |
4593 | * ixgbe_open - Called when a network interface is made active | |
4594 | * @netdev: network interface device structure | |
4595 | * | |
4596 | * Returns 0 on success, negative value on failure | |
4597 | * | |
4598 | * The open entry point is called when a network interface is made | |
4599 | * active by the system (IFF_UP). At this point all resources needed | |
4600 | * for transmit and receive operations are allocated, the interrupt | |
4601 | * handler is registered with the OS, the watchdog timer is started, | |
4602 | * and the stack is notified that the interface is ready. | |
4603 | **/ | |
4604 | static int ixgbe_open(struct net_device *netdev) | |
4605 | { | |
4606 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4607 | int err; | |
4bebfaa5 AK |
4608 | |
4609 | /* disallow open during test */ | |
4610 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
4611 | return -EBUSY; | |
9a799d71 | 4612 | |
54386467 JB |
4613 | netif_carrier_off(netdev); |
4614 | ||
9a799d71 AK |
4615 | /* allocate transmit descriptors */ |
4616 | err = ixgbe_setup_all_tx_resources(adapter); | |
4617 | if (err) | |
4618 | goto err_setup_tx; | |
4619 | ||
9a799d71 AK |
4620 | /* allocate receive descriptors */ |
4621 | err = ixgbe_setup_all_rx_resources(adapter); | |
4622 | if (err) | |
4623 | goto err_setup_rx; | |
4624 | ||
4625 | ixgbe_configure(adapter); | |
4626 | ||
021230d4 | 4627 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
4628 | if (err) |
4629 | goto err_req_irq; | |
4630 | ||
9a799d71 AK |
4631 | err = ixgbe_up_complete(adapter); |
4632 | if (err) | |
4633 | goto err_up; | |
4634 | ||
d55b53ff JK |
4635 | netif_tx_start_all_queues(netdev); |
4636 | ||
9a799d71 AK |
4637 | return 0; |
4638 | ||
4639 | err_up: | |
5eba3699 | 4640 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
4641 | ixgbe_free_irq(adapter); |
4642 | err_req_irq: | |
9a799d71 | 4643 | err_setup_rx: |
a20a1199 | 4644 | ixgbe_free_all_rx_resources(adapter); |
9a799d71 | 4645 | err_setup_tx: |
a20a1199 | 4646 | ixgbe_free_all_tx_resources(adapter); |
9a799d71 AK |
4647 | ixgbe_reset(adapter); |
4648 | ||
4649 | return err; | |
4650 | } | |
4651 | ||
4652 | /** | |
4653 | * ixgbe_close - Disables a network interface | |
4654 | * @netdev: network interface device structure | |
4655 | * | |
4656 | * Returns 0, this is not allowed to fail | |
4657 | * | |
4658 | * The close entry point is called when an interface is de-activated | |
4659 | * by the OS. The hardware is still under the drivers control, but | |
4660 | * needs to be disabled. A global MAC reset is issued to stop the | |
4661 | * hardware, and all transmit and receive resources are freed. | |
4662 | **/ | |
4663 | static int ixgbe_close(struct net_device *netdev) | |
4664 | { | |
4665 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 AK |
4666 | |
4667 | ixgbe_down(adapter); | |
4668 | ixgbe_free_irq(adapter); | |
4669 | ||
4670 | ixgbe_free_all_tx_resources(adapter); | |
4671 | ixgbe_free_all_rx_resources(adapter); | |
4672 | ||
5eba3699 | 4673 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
4674 | |
4675 | return 0; | |
4676 | } | |
4677 | ||
b3c8b4ba AD |
4678 | #ifdef CONFIG_PM |
4679 | static int ixgbe_resume(struct pci_dev *pdev) | |
4680 | { | |
4681 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4682 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4683 | u32 err; | |
4684 | ||
4685 | pci_set_power_state(pdev, PCI_D0); | |
4686 | pci_restore_state(pdev); | |
656ab817 DS |
4687 | /* |
4688 | * pci_restore_state clears dev->state_saved so call | |
4689 | * pci_save_state to restore it. | |
4690 | */ | |
4691 | pci_save_state(pdev); | |
9ce77666 | 4692 | |
4693 | err = pci_enable_device_mem(pdev); | |
b3c8b4ba | 4694 | if (err) { |
69888674 | 4695 | printk(KERN_ERR "ixgbe: Cannot enable PCI device from " |
b3c8b4ba AD |
4696 | "suspend\n"); |
4697 | return err; | |
4698 | } | |
4699 | pci_set_master(pdev); | |
4700 | ||
dd4d8ca6 | 4701 | pci_wake_from_d3(pdev, false); |
b3c8b4ba AD |
4702 | |
4703 | err = ixgbe_init_interrupt_scheme(adapter); | |
4704 | if (err) { | |
4705 | printk(KERN_ERR "ixgbe: Cannot initialize interrupts for " | |
4706 | "device\n"); | |
4707 | return err; | |
4708 | } | |
4709 | ||
b3c8b4ba AD |
4710 | ixgbe_reset(adapter); |
4711 | ||
495dce12 WJP |
4712 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
4713 | ||
b3c8b4ba AD |
4714 | if (netif_running(netdev)) { |
4715 | err = ixgbe_open(adapter->netdev); | |
4716 | if (err) | |
4717 | return err; | |
4718 | } | |
4719 | ||
4720 | netif_device_attach(netdev); | |
4721 | ||
4722 | return 0; | |
4723 | } | |
b3c8b4ba | 4724 | #endif /* CONFIG_PM */ |
9d8d05ae RW |
4725 | |
4726 | static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) | |
b3c8b4ba AD |
4727 | { |
4728 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4729 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
e8e26350 PW |
4730 | struct ixgbe_hw *hw = &adapter->hw; |
4731 | u32 ctrl, fctrl; | |
4732 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
4733 | #ifdef CONFIG_PM |
4734 | int retval = 0; | |
4735 | #endif | |
4736 | ||
4737 | netif_device_detach(netdev); | |
4738 | ||
4739 | if (netif_running(netdev)) { | |
4740 | ixgbe_down(adapter); | |
4741 | ixgbe_free_irq(adapter); | |
4742 | ixgbe_free_all_tx_resources(adapter); | |
4743 | ixgbe_free_all_rx_resources(adapter); | |
4744 | } | |
7a921c93 | 4745 | ixgbe_clear_interrupt_scheme(adapter); |
b3c8b4ba AD |
4746 | |
4747 | #ifdef CONFIG_PM | |
4748 | retval = pci_save_state(pdev); | |
4749 | if (retval) | |
4750 | return retval; | |
4df10466 | 4751 | |
b3c8b4ba | 4752 | #endif |
e8e26350 PW |
4753 | if (wufc) { |
4754 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 4755 | |
e8e26350 PW |
4756 | /* turn on all-multi mode if wake on multicast is enabled */ |
4757 | if (wufc & IXGBE_WUFC_MC) { | |
4758 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
4759 | fctrl |= IXGBE_FCTRL_MPE; | |
4760 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
4761 | } | |
4762 | ||
4763 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
4764 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
4765 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
4766 | ||
4767 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
4768 | } else { | |
4769 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
4770 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
4771 | } | |
4772 | ||
dd4d8ca6 DS |
4773 | if (wufc && hw->mac.type == ixgbe_mac_82599EB) |
4774 | pci_wake_from_d3(pdev, true); | |
4775 | else | |
4776 | pci_wake_from_d3(pdev, false); | |
b3c8b4ba | 4777 | |
9d8d05ae RW |
4778 | *enable_wake = !!wufc; |
4779 | ||
b3c8b4ba AD |
4780 | ixgbe_release_hw_control(adapter); |
4781 | ||
4782 | pci_disable_device(pdev); | |
4783 | ||
9d8d05ae RW |
4784 | return 0; |
4785 | } | |
4786 | ||
4787 | #ifdef CONFIG_PM | |
4788 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
4789 | { | |
4790 | int retval; | |
4791 | bool wake; | |
4792 | ||
4793 | retval = __ixgbe_shutdown(pdev, &wake); | |
4794 | if (retval) | |
4795 | return retval; | |
4796 | ||
4797 | if (wake) { | |
4798 | pci_prepare_to_sleep(pdev); | |
4799 | } else { | |
4800 | pci_wake_from_d3(pdev, false); | |
4801 | pci_set_power_state(pdev, PCI_D3hot); | |
4802 | } | |
b3c8b4ba AD |
4803 | |
4804 | return 0; | |
4805 | } | |
9d8d05ae | 4806 | #endif /* CONFIG_PM */ |
b3c8b4ba AD |
4807 | |
4808 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
4809 | { | |
9d8d05ae RW |
4810 | bool wake; |
4811 | ||
4812 | __ixgbe_shutdown(pdev, &wake); | |
4813 | ||
4814 | if (system_state == SYSTEM_POWER_OFF) { | |
4815 | pci_wake_from_d3(pdev, wake); | |
4816 | pci_set_power_state(pdev, PCI_D3hot); | |
4817 | } | |
b3c8b4ba AD |
4818 | } |
4819 | ||
9a799d71 AK |
4820 | /** |
4821 | * ixgbe_update_stats - Update the board statistics counters. | |
4822 | * @adapter: board private structure | |
4823 | **/ | |
4824 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
4825 | { | |
2d86f139 | 4826 | struct net_device *netdev = adapter->netdev; |
9a799d71 | 4827 | struct ixgbe_hw *hw = &adapter->hw; |
6f11eef7 AV |
4828 | u64 total_mpc = 0; |
4829 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
eb985f09 | 4830 | u64 non_eop_descs = 0, restart_queue = 0; |
9a799d71 | 4831 | |
94b982b2 | 4832 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { |
f8212f97 | 4833 | u64 rsc_count = 0; |
94b982b2 | 4834 | u64 rsc_flush = 0; |
d51019a4 PW |
4835 | for (i = 0; i < 16; i++) |
4836 | adapter->hw_rx_no_dma_resources += | |
4837 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
94b982b2 | 4838 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 PW |
4839 | rsc_count += adapter->rx_ring[i]->rsc_count; |
4840 | rsc_flush += adapter->rx_ring[i]->rsc_flush; | |
94b982b2 MC |
4841 | } |
4842 | adapter->rsc_total_count = rsc_count; | |
4843 | adapter->rsc_total_flush = rsc_flush; | |
d51019a4 PW |
4844 | } |
4845 | ||
7ca3bc58 JB |
4846 | /* gather some stats to the adapter struct that are per queue */ |
4847 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 4848 | restart_queue += adapter->tx_ring[i]->restart_queue; |
eb985f09 | 4849 | adapter->restart_queue = restart_queue; |
7ca3bc58 JB |
4850 | |
4851 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 | 4852 | non_eop_descs += adapter->rx_ring[i]->non_eop_descs; |
eb985f09 | 4853 | adapter->non_eop_descs = non_eop_descs; |
7ca3bc58 | 4854 | |
9a799d71 | 4855 | adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
6f11eef7 AV |
4856 | for (i = 0; i < 8; i++) { |
4857 | /* for packet buffers not used, the register should read 0 */ | |
4858 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
4859 | missed_rx += mpc; | |
4860 | adapter->stats.mpc[i] += mpc; | |
4861 | total_mpc += adapter->stats.mpc[i]; | |
e8e26350 PW |
4862 | if (hw->mac.type == ixgbe_mac_82598EB) |
4863 | adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); | |
2f90b865 AD |
4864 | adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); |
4865 | adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
4866 | adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
4867 | adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
e8e26350 PW |
4868 | if (hw->mac.type == ixgbe_mac_82599EB) { |
4869 | adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, | |
4870 | IXGBE_PXONRXCNT(i)); | |
4871 | adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, | |
4872 | IXGBE_PXOFFRXCNT(i)); | |
4873 | adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
e8e26350 PW |
4874 | } else { |
4875 | adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, | |
4876 | IXGBE_PXONRXC(i)); | |
4877 | adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, | |
4878 | IXGBE_PXOFFRXC(i)); | |
4879 | } | |
2f90b865 AD |
4880 | adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw, |
4881 | IXGBE_PXONTXC(i)); | |
2f90b865 | 4882 | adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw, |
e8e26350 | 4883 | IXGBE_PXOFFTXC(i)); |
6f11eef7 AV |
4884 | } |
4885 | adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); | |
4886 | /* work around hardware counting issue */ | |
4887 | adapter->stats.gprc -= missed_rx; | |
4888 | ||
4889 | /* 82598 hardware only has a 32 bit counter in the high register */ | |
e8e26350 | 4890 | if (hw->mac.type == ixgbe_mac_82599EB) { |
aad71918 | 4891 | u64 tmp; |
e8e26350 | 4892 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); |
aad71918 BG |
4893 | tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */ |
4894 | adapter->stats.gorc += (tmp << 32); | |
e8e26350 | 4895 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); |
aad71918 BG |
4896 | tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */ |
4897 | adapter->stats.gotc += (tmp << 32); | |
e8e26350 PW |
4898 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL); |
4899 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ | |
4900 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); | |
4901 | adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); | |
c4cf55e5 PWJ |
4902 | adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); |
4903 | adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); | |
6d45522c YZ |
4904 | #ifdef IXGBE_FCOE |
4905 | adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); | |
4906 | adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); | |
4907 | adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); | |
4908 | adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); | |
4909 | adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); | |
4910 | adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); | |
4911 | #endif /* IXGBE_FCOE */ | |
e8e26350 PW |
4912 | } else { |
4913 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
4914 | adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
4915 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); | |
4916 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
4917 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
4918 | } | |
9a799d71 AK |
4919 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
4920 | adapter->stats.bprc += bprc; | |
4921 | adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 PW |
4922 | if (hw->mac.type == ixgbe_mac_82598EB) |
4923 | adapter->stats.mprc -= bprc; | |
9a799d71 AK |
4924 | adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC); |
4925 | adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
4926 | adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
4927 | adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
4928 | adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
4929 | adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
4930 | adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
9a799d71 | 4931 | adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); |
6f11eef7 AV |
4932 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
4933 | adapter->stats.lxontxc += lxon; | |
4934 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); | |
4935 | adapter->stats.lxofftxc += lxoff; | |
9a799d71 AK |
4936 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
4937 | adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); | |
6f11eef7 AV |
4938 | adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); |
4939 | /* | |
4940 | * 82598 errata - tx of flow control packets is included in tx counters | |
4941 | */ | |
4942 | xon_off_tot = lxon + lxoff; | |
4943 | adapter->stats.gptc -= xon_off_tot; | |
4944 | adapter->stats.mptc -= xon_off_tot; | |
4945 | adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
9a799d71 AK |
4946 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
4947 | adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
4948 | adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
9a799d71 AK |
4949 | adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR); |
4950 | adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
6f11eef7 | 4951 | adapter->stats.ptc64 -= xon_off_tot; |
9a799d71 AK |
4952 | adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); |
4953 | adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
4954 | adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
4955 | adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
4956 | adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
9a799d71 AK |
4957 | adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); |
4958 | ||
4959 | /* Fill out the OS statistics structure */ | |
2d86f139 | 4960 | netdev->stats.multicast = adapter->stats.mprc; |
9a799d71 AK |
4961 | |
4962 | /* Rx Errors */ | |
2d86f139 | 4963 | netdev->stats.rx_errors = adapter->stats.crcerrs + |
b4617240 | 4964 | adapter->stats.rlec; |
2d86f139 AK |
4965 | netdev->stats.rx_dropped = 0; |
4966 | netdev->stats.rx_length_errors = adapter->stats.rlec; | |
4967 | netdev->stats.rx_crc_errors = adapter->stats.crcerrs; | |
4968 | netdev->stats.rx_missed_errors = total_mpc; | |
9a799d71 AK |
4969 | } |
4970 | ||
4971 | /** | |
4972 | * ixgbe_watchdog - Timer Call-back | |
4973 | * @data: pointer to adapter cast into an unsigned long | |
4974 | **/ | |
4975 | static void ixgbe_watchdog(unsigned long data) | |
4976 | { | |
4977 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
cf8280ee | 4978 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
4979 | u64 eics = 0; |
4980 | int i; | |
cf8280ee | 4981 | |
fe49f04a AD |
4982 | /* |
4983 | * Do the watchdog outside of interrupt context due to the lovely | |
4984 | * delays that some of the newer hardware requires | |
4985 | */ | |
22d5a71b | 4986 | |
fe49f04a AD |
4987 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
4988 | goto watchdog_short_circuit; | |
22d5a71b | 4989 | |
fe49f04a AD |
4990 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
4991 | /* | |
4992 | * for legacy and MSI interrupts don't set any bits | |
4993 | * that are enabled for EIAM, because this operation | |
4994 | * would set *both* EIMS and EICS for any bit in EIAM | |
4995 | */ | |
4996 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
4997 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
4998 | goto watchdog_reschedule; | |
4999 | } | |
5000 | ||
5001 | /* get one bit for every active tx/rx interrupt vector */ | |
5002 | for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) { | |
5003 | struct ixgbe_q_vector *qv = adapter->q_vector[i]; | |
5004 | if (qv->rxr_count || qv->txr_count) | |
5005 | eics |= ((u64)1 << i); | |
cf8280ee | 5006 | } |
9a799d71 | 5007 | |
fe49f04a AD |
5008 | /* Cause software interrupt to ensure rx rings are cleaned */ |
5009 | ixgbe_irq_rearm_queues(adapter, eics); | |
5010 | ||
5011 | watchdog_reschedule: | |
5012 | /* Reset the timer */ | |
5013 | mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ)); | |
5014 | ||
5015 | watchdog_short_circuit: | |
cf8280ee JB |
5016 | schedule_work(&adapter->watchdog_task); |
5017 | } | |
5018 | ||
e8e26350 PW |
5019 | /** |
5020 | * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber | |
5021 | * @work: pointer to work_struct containing our data | |
5022 | **/ | |
5023 | static void ixgbe_multispeed_fiber_task(struct work_struct *work) | |
5024 | { | |
5025 | struct ixgbe_adapter *adapter = container_of(work, | |
5026 | struct ixgbe_adapter, | |
5027 | multispeed_fiber_task); | |
5028 | struct ixgbe_hw *hw = &adapter->hw; | |
5029 | u32 autoneg; | |
8620a103 | 5030 | bool negotiation; |
e8e26350 PW |
5031 | |
5032 | adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK; | |
a1f25324 MC |
5033 | autoneg = hw->phy.autoneg_advertised; |
5034 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
8620a103 | 5035 | hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation); |
1097cd17 | 5036 | hw->mac.autotry_restart = false; |
8620a103 MC |
5037 | if (hw->mac.ops.setup_link) |
5038 | hw->mac.ops.setup_link(hw, autoneg, negotiation, true); | |
e8e26350 PW |
5039 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
5040 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK; | |
5041 | } | |
5042 | ||
5043 | /** | |
5044 | * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module | |
5045 | * @work: pointer to work_struct containing our data | |
5046 | **/ | |
5047 | static void ixgbe_sfp_config_module_task(struct work_struct *work) | |
5048 | { | |
5049 | struct ixgbe_adapter *adapter = container_of(work, | |
5050 | struct ixgbe_adapter, | |
5051 | sfp_config_module_task); | |
5052 | struct ixgbe_hw *hw = &adapter->hw; | |
5053 | u32 err; | |
5054 | ||
5055 | adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK; | |
63d6e1d8 DS |
5056 | |
5057 | /* Time for electrical oscillations to settle down */ | |
5058 | msleep(100); | |
e8e26350 | 5059 | err = hw->phy.ops.identify_sfp(hw); |
63d6e1d8 | 5060 | |
e8e26350 | 5061 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { |
88d2b81f DS |
5062 | dev_err(&adapter->pdev->dev, "failed to initialize because " |
5063 | "an unsupported SFP+ module type was detected.\n" | |
5064 | "Reload the driver after installing a supported " | |
5065 | "module.\n"); | |
63d6e1d8 | 5066 | unregister_netdev(adapter->netdev); |
e8e26350 PW |
5067 | return; |
5068 | } | |
5069 | hw->mac.ops.setup_sfp(hw); | |
5070 | ||
8d1c3c07 | 5071 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) |
e8e26350 PW |
5072 | /* This will also work for DA Twinax connections */ |
5073 | schedule_work(&adapter->multispeed_fiber_task); | |
5074 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK; | |
5075 | } | |
5076 | ||
c4cf55e5 PWJ |
5077 | /** |
5078 | * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table | |
5079 | * @work: pointer to work_struct containing our data | |
5080 | **/ | |
5081 | static void ixgbe_fdir_reinit_task(struct work_struct *work) | |
5082 | { | |
5083 | struct ixgbe_adapter *adapter = container_of(work, | |
5084 | struct ixgbe_adapter, | |
5085 | fdir_reinit_task); | |
5086 | struct ixgbe_hw *hw = &adapter->hw; | |
5087 | int i; | |
5088 | ||
5089 | if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { | |
5090 | for (i = 0; i < adapter->num_tx_queues; i++) | |
5091 | set_bit(__IXGBE_FDIR_INIT_DONE, | |
4a0b9ca0 | 5092 | &(adapter->tx_ring[i]->reinit_state)); |
c4cf55e5 PWJ |
5093 | } else { |
5094 | DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, " | |
5095 | "ignored adding FDIR ATR filters \n"); | |
5096 | } | |
5097 | /* Done FDIR Re-initialization, enable transmits */ | |
5098 | netif_tx_start_all_queues(adapter->netdev); | |
5099 | } | |
5100 | ||
10eec955 JF |
5101 | static DEFINE_MUTEX(ixgbe_watchdog_lock); |
5102 | ||
cf8280ee | 5103 | /** |
69888674 AD |
5104 | * ixgbe_watchdog_task - worker thread to bring link up |
5105 | * @work: pointer to work_struct containing our data | |
cf8280ee JB |
5106 | **/ |
5107 | static void ixgbe_watchdog_task(struct work_struct *work) | |
5108 | { | |
5109 | struct ixgbe_adapter *adapter = container_of(work, | |
5110 | struct ixgbe_adapter, | |
5111 | watchdog_task); | |
5112 | struct net_device *netdev = adapter->netdev; | |
5113 | struct ixgbe_hw *hw = &adapter->hw; | |
10eec955 JF |
5114 | u32 link_speed; |
5115 | bool link_up; | |
bc59fcda NS |
5116 | int i; |
5117 | struct ixgbe_ring *tx_ring; | |
5118 | int some_tx_pending = 0; | |
cf8280ee | 5119 | |
10eec955 JF |
5120 | mutex_lock(&ixgbe_watchdog_lock); |
5121 | ||
5122 | link_up = adapter->link_up; | |
5123 | link_speed = adapter->link_speed; | |
cf8280ee JB |
5124 | |
5125 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { | |
5126 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
264857b8 PWJ |
5127 | if (link_up) { |
5128 | #ifdef CONFIG_DCB | |
5129 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
5130 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) | |
620fa036 | 5131 | hw->mac.ops.fc_enable(hw, i); |
264857b8 | 5132 | } else { |
620fa036 | 5133 | hw->mac.ops.fc_enable(hw, 0); |
264857b8 PWJ |
5134 | } |
5135 | #else | |
620fa036 | 5136 | hw->mac.ops.fc_enable(hw, 0); |
264857b8 PWJ |
5137 | #endif |
5138 | } | |
5139 | ||
cf8280ee JB |
5140 | if (link_up || |
5141 | time_after(jiffies, (adapter->link_check_timeout + | |
5142 | IXGBE_TRY_LINK_TIMEOUT))) { | |
cf8280ee | 5143 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; |
264857b8 | 5144 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); |
cf8280ee JB |
5145 | } |
5146 | adapter->link_up = link_up; | |
5147 | adapter->link_speed = link_speed; | |
5148 | } | |
9a799d71 AK |
5149 | |
5150 | if (link_up) { | |
5151 | if (!netif_carrier_ok(netdev)) { | |
e8e26350 PW |
5152 | bool flow_rx, flow_tx; |
5153 | ||
5154 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
5155 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
5156 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
078788b6 PWJ |
5157 | flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); |
5158 | flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
e8e26350 PW |
5159 | } else { |
5160 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
5161 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
078788b6 PWJ |
5162 | flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); |
5163 | flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); | |
e8e26350 PW |
5164 | } |
5165 | ||
a46e534b JK |
5166 | printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, " |
5167 | "Flow Control: %s\n", | |
5168 | netdev->name, | |
5169 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? | |
5170 | "10 Gbps" : | |
5171 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
5172 | "1 Gbps" : "unknown speed")), | |
e8e26350 PW |
5173 | ((flow_rx && flow_tx) ? "RX/TX" : |
5174 | (flow_rx ? "RX" : | |
5175 | (flow_tx ? "TX" : "None")))); | |
9a799d71 AK |
5176 | |
5177 | netif_carrier_on(netdev); | |
9a799d71 AK |
5178 | } else { |
5179 | /* Force detection of hung controller */ | |
5180 | adapter->detect_tx_hung = true; | |
5181 | } | |
5182 | } else { | |
cf8280ee JB |
5183 | adapter->link_up = false; |
5184 | adapter->link_speed = 0; | |
9a799d71 | 5185 | if (netif_carrier_ok(netdev)) { |
a46e534b JK |
5186 | printk(KERN_INFO "ixgbe: %s NIC Link is Down\n", |
5187 | netdev->name); | |
9a799d71 | 5188 | netif_carrier_off(netdev); |
9a799d71 AK |
5189 | } |
5190 | } | |
5191 | ||
bc59fcda NS |
5192 | if (!netif_carrier_ok(netdev)) { |
5193 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 5194 | tx_ring = adapter->tx_ring[i]; |
bc59fcda NS |
5195 | if (tx_ring->next_to_use != tx_ring->next_to_clean) { |
5196 | some_tx_pending = 1; | |
5197 | break; | |
5198 | } | |
5199 | } | |
5200 | ||
5201 | if (some_tx_pending) { | |
5202 | /* We've lost link, so the controller stops DMA, | |
5203 | * but we've got queued Tx work that's never going | |
5204 | * to get done, so reset controller to flush Tx. | |
5205 | * (Do the reset outside of interrupt context). | |
5206 | */ | |
5207 | schedule_work(&adapter->reset_task); | |
5208 | } | |
5209 | } | |
5210 | ||
9a799d71 | 5211 | ixgbe_update_stats(adapter); |
10eec955 | 5212 | mutex_unlock(&ixgbe_watchdog_lock); |
9a799d71 AK |
5213 | } |
5214 | ||
9a799d71 | 5215 | static int ixgbe_tso(struct ixgbe_adapter *adapter, |
b4617240 PW |
5216 | struct ixgbe_ring *tx_ring, struct sk_buff *skb, |
5217 | u32 tx_flags, u8 *hdr_len) | |
9a799d71 AK |
5218 | { |
5219 | struct ixgbe_adv_tx_context_desc *context_desc; | |
5220 | unsigned int i; | |
5221 | int err; | |
5222 | struct ixgbe_tx_buffer *tx_buffer_info; | |
9f8cdf4f JB |
5223 | u32 vlan_macip_lens = 0, type_tucmd_mlhl; |
5224 | u32 mss_l4len_idx, l4len; | |
9a799d71 AK |
5225 | |
5226 | if (skb_is_gso(skb)) { | |
5227 | if (skb_header_cloned(skb)) { | |
5228 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
5229 | if (err) | |
5230 | return err; | |
5231 | } | |
5232 | l4len = tcp_hdrlen(skb); | |
5233 | *hdr_len += l4len; | |
5234 | ||
8327d000 | 5235 | if (skb->protocol == htons(ETH_P_IP)) { |
9a799d71 AK |
5236 | struct iphdr *iph = ip_hdr(skb); |
5237 | iph->tot_len = 0; | |
5238 | iph->check = 0; | |
5239 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
b4617240 PW |
5240 | iph->daddr, 0, |
5241 | IPPROTO_TCP, | |
5242 | 0); | |
8e1e8a47 | 5243 | } else if (skb_is_gso_v6(skb)) { |
9a799d71 AK |
5244 | ipv6_hdr(skb)->payload_len = 0; |
5245 | tcp_hdr(skb)->check = | |
5246 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
b4617240 PW |
5247 | &ipv6_hdr(skb)->daddr, |
5248 | 0, IPPROTO_TCP, 0); | |
9a799d71 AK |
5249 | } |
5250 | ||
5251 | i = tx_ring->next_to_use; | |
5252 | ||
5253 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
5254 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
5255 | ||
5256 | /* VLAN MACLEN IPLEN */ | |
5257 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
5258 | vlan_macip_lens |= | |
5259 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
5260 | vlan_macip_lens |= ((skb_network_offset(skb)) << | |
b4617240 | 5261 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
5262 | *hdr_len += skb_network_offset(skb); |
5263 | vlan_macip_lens |= | |
5264 | (skb_transport_header(skb) - skb_network_header(skb)); | |
5265 | *hdr_len += | |
5266 | (skb_transport_header(skb) - skb_network_header(skb)); | |
5267 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
5268 | context_desc->seqnum_seed = 0; | |
5269 | ||
5270 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ | |
9f8cdf4f | 5271 | type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT | |
b4617240 | 5272 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 | 5273 | |
8327d000 | 5274 | if (skb->protocol == htons(ETH_P_IP)) |
9a799d71 AK |
5275 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
5276 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
5277 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
5278 | ||
5279 | /* MSS L4LEN IDX */ | |
9f8cdf4f | 5280 | mss_l4len_idx = |
9a799d71 AK |
5281 | (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT); |
5282 | mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT); | |
4eeae6fd PW |
5283 | /* use index 1 for TSO */ |
5284 | mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
5285 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); |
5286 | ||
5287 | tx_buffer_info->time_stamp = jiffies; | |
5288 | tx_buffer_info->next_to_watch = i; | |
5289 | ||
5290 | i++; | |
5291 | if (i == tx_ring->count) | |
5292 | i = 0; | |
5293 | tx_ring->next_to_use = i; | |
5294 | ||
5295 | return true; | |
5296 | } | |
5297 | return false; | |
5298 | } | |
5299 | ||
5300 | static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter, | |
b4617240 PW |
5301 | struct ixgbe_ring *tx_ring, |
5302 | struct sk_buff *skb, u32 tx_flags) | |
9a799d71 AK |
5303 | { |
5304 | struct ixgbe_adv_tx_context_desc *context_desc; | |
5305 | unsigned int i; | |
5306 | struct ixgbe_tx_buffer *tx_buffer_info; | |
5307 | u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0; | |
5308 | ||
5309 | if (skb->ip_summed == CHECKSUM_PARTIAL || | |
5310 | (tx_flags & IXGBE_TX_FLAGS_VLAN)) { | |
5311 | i = tx_ring->next_to_use; | |
5312 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
5313 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
5314 | ||
5315 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
5316 | vlan_macip_lens |= | |
5317 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
5318 | vlan_macip_lens |= (skb_network_offset(skb) << | |
b4617240 | 5319 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
5320 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
5321 | vlan_macip_lens |= (skb_transport_header(skb) - | |
b4617240 | 5322 | skb_network_header(skb)); |
9a799d71 AK |
5323 | |
5324 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
5325 | context_desc->seqnum_seed = 0; | |
5326 | ||
5327 | type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT | | |
b4617240 | 5328 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 AK |
5329 | |
5330 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
ca553980 GS |
5331 | __be16 protocol; |
5332 | ||
5333 | if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) { | |
5334 | const struct vlan_ethhdr *vhdr = | |
5335 | (const struct vlan_ethhdr *)skb->data; | |
5336 | ||
5337 | protocol = vhdr->h_vlan_encapsulated_proto; | |
5338 | } else { | |
5339 | protocol = skb->protocol; | |
5340 | } | |
5341 | ||
5342 | switch (protocol) { | |
09640e63 | 5343 | case cpu_to_be16(ETH_P_IP): |
9a799d71 | 5344 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
41825d71 AK |
5345 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) |
5346 | type_tucmd_mlhl |= | |
b4617240 | 5347 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
45a5ead0 JB |
5348 | else if (ip_hdr(skb)->protocol == IPPROTO_SCTP) |
5349 | type_tucmd_mlhl |= | |
5350 | IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
41825d71 | 5351 | break; |
09640e63 | 5352 | case cpu_to_be16(ETH_P_IPV6): |
41825d71 AK |
5353 | /* XXX what about other V6 headers?? */ |
5354 | if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) | |
5355 | type_tucmd_mlhl |= | |
b4617240 | 5356 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
45a5ead0 JB |
5357 | else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP) |
5358 | type_tucmd_mlhl |= | |
5359 | IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
41825d71 | 5360 | break; |
41825d71 AK |
5361 | default: |
5362 | if (unlikely(net_ratelimit())) { | |
5363 | DPRINTK(PROBE, WARNING, | |
5364 | "partial checksum but proto=%x!\n", | |
5365 | skb->protocol); | |
5366 | } | |
5367 | break; | |
5368 | } | |
9a799d71 AK |
5369 | } |
5370 | ||
5371 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
4eeae6fd | 5372 | /* use index zero for tx checksum offload */ |
9a799d71 AK |
5373 | context_desc->mss_l4len_idx = 0; |
5374 | ||
5375 | tx_buffer_info->time_stamp = jiffies; | |
5376 | tx_buffer_info->next_to_watch = i; | |
9f8cdf4f | 5377 | |
9a799d71 AK |
5378 | i++; |
5379 | if (i == tx_ring->count) | |
5380 | i = 0; | |
5381 | tx_ring->next_to_use = i; | |
5382 | ||
5383 | return true; | |
5384 | } | |
9f8cdf4f | 5385 | |
9a799d71 AK |
5386 | return false; |
5387 | } | |
5388 | ||
5389 | static int ixgbe_tx_map(struct ixgbe_adapter *adapter, | |
b4617240 | 5390 | struct ixgbe_ring *tx_ring, |
eacd73f7 YZ |
5391 | struct sk_buff *skb, u32 tx_flags, |
5392 | unsigned int first) | |
9a799d71 | 5393 | { |
e5a43549 | 5394 | struct pci_dev *pdev = adapter->pdev; |
9a799d71 | 5395 | struct ixgbe_tx_buffer *tx_buffer_info; |
eacd73f7 YZ |
5396 | unsigned int len; |
5397 | unsigned int total = skb->len; | |
9a799d71 AK |
5398 | unsigned int offset = 0, size, count = 0, i; |
5399 | unsigned int nr_frags = skb_shinfo(skb)->nr_frags; | |
5400 | unsigned int f; | |
9a799d71 AK |
5401 | |
5402 | i = tx_ring->next_to_use; | |
5403 | ||
eacd73f7 YZ |
5404 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) |
5405 | /* excluding fcoe_crc_eof for FCoE */ | |
5406 | total -= sizeof(struct fcoe_crc_eof); | |
5407 | ||
5408 | len = min(skb_headlen(skb), total); | |
9a799d71 AK |
5409 | while (len) { |
5410 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
5411 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
5412 | ||
5413 | tx_buffer_info->length = size; | |
e5a43549 AD |
5414 | tx_buffer_info->mapped_as_page = false; |
5415 | tx_buffer_info->dma = pci_map_single(pdev, | |
5416 | skb->data + offset, | |
5417 | size, PCI_DMA_TODEVICE); | |
5418 | if (pci_dma_mapping_error(pdev, tx_buffer_info->dma)) | |
5419 | goto dma_error; | |
9a799d71 AK |
5420 | tx_buffer_info->time_stamp = jiffies; |
5421 | tx_buffer_info->next_to_watch = i; | |
5422 | ||
5423 | len -= size; | |
eacd73f7 | 5424 | total -= size; |
9a799d71 AK |
5425 | offset += size; |
5426 | count++; | |
44df32c5 AD |
5427 | |
5428 | if (len) { | |
5429 | i++; | |
5430 | if (i == tx_ring->count) | |
5431 | i = 0; | |
5432 | } | |
9a799d71 AK |
5433 | } |
5434 | ||
5435 | for (f = 0; f < nr_frags; f++) { | |
5436 | struct skb_frag_struct *frag; | |
5437 | ||
5438 | frag = &skb_shinfo(skb)->frags[f]; | |
eacd73f7 | 5439 | len = min((unsigned int)frag->size, total); |
e5a43549 | 5440 | offset = frag->page_offset; |
9a799d71 AK |
5441 | |
5442 | while (len) { | |
44df32c5 AD |
5443 | i++; |
5444 | if (i == tx_ring->count) | |
5445 | i = 0; | |
5446 | ||
9a799d71 AK |
5447 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
5448 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
5449 | ||
5450 | tx_buffer_info->length = size; | |
e5a43549 AD |
5451 | tx_buffer_info->dma = pci_map_page(adapter->pdev, |
5452 | frag->page, | |
5453 | offset, size, | |
5454 | PCI_DMA_TODEVICE); | |
5455 | tx_buffer_info->mapped_as_page = true; | |
5456 | if (pci_dma_mapping_error(pdev, tx_buffer_info->dma)) | |
5457 | goto dma_error; | |
9a799d71 AK |
5458 | tx_buffer_info->time_stamp = jiffies; |
5459 | tx_buffer_info->next_to_watch = i; | |
5460 | ||
5461 | len -= size; | |
eacd73f7 | 5462 | total -= size; |
9a799d71 AK |
5463 | offset += size; |
5464 | count++; | |
9a799d71 | 5465 | } |
eacd73f7 YZ |
5466 | if (total == 0) |
5467 | break; | |
9a799d71 | 5468 | } |
44df32c5 | 5469 | |
9a799d71 AK |
5470 | tx_ring->tx_buffer_info[i].skb = skb; |
5471 | tx_ring->tx_buffer_info[first].next_to_watch = i; | |
5472 | ||
e5a43549 AD |
5473 | return count; |
5474 | ||
5475 | dma_error: | |
5476 | dev_err(&pdev->dev, "TX DMA map failed\n"); | |
5477 | ||
5478 | /* clear timestamp and dma mappings for failed tx_buffer_info map */ | |
5479 | tx_buffer_info->dma = 0; | |
5480 | tx_buffer_info->time_stamp = 0; | |
5481 | tx_buffer_info->next_to_watch = 0; | |
c1fa347f RK |
5482 | if (count) |
5483 | count--; | |
e5a43549 AD |
5484 | |
5485 | /* clear timestamp and dma mappings for remaining portion of packet */ | |
c1fa347f RK |
5486 | while (count--) { |
5487 | if (i==0) | |
e5a43549 | 5488 | i += tx_ring->count; |
c1fa347f | 5489 | i--; |
e5a43549 AD |
5490 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
5491 | ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info); | |
5492 | } | |
5493 | ||
e44d38e1 | 5494 | return 0; |
9a799d71 AK |
5495 | } |
5496 | ||
5497 | static void ixgbe_tx_queue(struct ixgbe_adapter *adapter, | |
b4617240 PW |
5498 | struct ixgbe_ring *tx_ring, |
5499 | int tx_flags, int count, u32 paylen, u8 hdr_len) | |
9a799d71 AK |
5500 | { |
5501 | union ixgbe_adv_tx_desc *tx_desc = NULL; | |
5502 | struct ixgbe_tx_buffer *tx_buffer_info; | |
5503 | u32 olinfo_status = 0, cmd_type_len = 0; | |
5504 | unsigned int i; | |
5505 | u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS; | |
5506 | ||
5507 | cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA; | |
5508 | ||
5509 | cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT; | |
5510 | ||
5511 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
5512 | cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE; | |
5513 | ||
5514 | if (tx_flags & IXGBE_TX_FLAGS_TSO) { | |
5515 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
5516 | ||
5517 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 5518 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 5519 | |
4eeae6fd PW |
5520 | /* use index 1 context for tso */ |
5521 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
5522 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) |
5523 | olinfo_status |= IXGBE_TXD_POPTS_IXSM << | |
b4617240 | 5524 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 AK |
5525 | |
5526 | } else if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
5527 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 5528 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 5529 | |
eacd73f7 YZ |
5530 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { |
5531 | olinfo_status |= IXGBE_ADVTXD_CC; | |
5532 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
5533 | if (tx_flags & IXGBE_TX_FLAGS_FSO) | |
5534 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
5535 | } | |
5536 | ||
9a799d71 AK |
5537 | olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT); |
5538 | ||
5539 | i = tx_ring->next_to_use; | |
5540 | while (count--) { | |
5541 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
5542 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); | |
5543 | tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma); | |
5544 | tx_desc->read.cmd_type_len = | |
b4617240 | 5545 | cpu_to_le32(cmd_type_len | tx_buffer_info->length); |
9a799d71 | 5546 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
9a799d71 AK |
5547 | i++; |
5548 | if (i == tx_ring->count) | |
5549 | i = 0; | |
5550 | } | |
5551 | ||
5552 | tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd); | |
5553 | ||
5554 | /* | |
5555 | * Force memory writes to complete before letting h/w | |
5556 | * know there are new descriptors to fetch. (Only | |
5557 | * applicable for weak-ordered memory model archs, | |
5558 | * such as IA-64). | |
5559 | */ | |
5560 | wmb(); | |
5561 | ||
5562 | tx_ring->next_to_use = i; | |
5563 | writel(i, adapter->hw.hw_addr + tx_ring->tail); | |
5564 | } | |
5565 | ||
c4cf55e5 PWJ |
5566 | static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb, |
5567 | int queue, u32 tx_flags) | |
5568 | { | |
5569 | /* Right now, we support IPv4 only */ | |
5570 | struct ixgbe_atr_input atr_input; | |
5571 | struct tcphdr *th; | |
c4cf55e5 PWJ |
5572 | struct iphdr *iph = ip_hdr(skb); |
5573 | struct ethhdr *eth = (struct ethhdr *)skb->data; | |
5574 | u16 vlan_id, src_port, dst_port, flex_bytes; | |
5575 | u32 src_ipv4_addr, dst_ipv4_addr; | |
5576 | u8 l4type = 0; | |
5577 | ||
5578 | /* check if we're UDP or TCP */ | |
5579 | if (iph->protocol == IPPROTO_TCP) { | |
5580 | th = tcp_hdr(skb); | |
5581 | src_port = th->source; | |
5582 | dst_port = th->dest; | |
5583 | l4type |= IXGBE_ATR_L4TYPE_TCP; | |
5584 | /* l4type IPv4 type is 0, no need to assign */ | |
c4cf55e5 PWJ |
5585 | } else { |
5586 | /* Unsupported L4 header, just bail here */ | |
5587 | return; | |
5588 | } | |
5589 | ||
5590 | memset(&atr_input, 0, sizeof(struct ixgbe_atr_input)); | |
5591 | ||
5592 | vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >> | |
5593 | IXGBE_TX_FLAGS_VLAN_SHIFT; | |
5594 | src_ipv4_addr = iph->saddr; | |
5595 | dst_ipv4_addr = iph->daddr; | |
5596 | flex_bytes = eth->h_proto; | |
5597 | ||
5598 | ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id); | |
5599 | ixgbe_atr_set_src_port_82599(&atr_input, dst_port); | |
5600 | ixgbe_atr_set_dst_port_82599(&atr_input, src_port); | |
5601 | ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes); | |
5602 | ixgbe_atr_set_l4type_82599(&atr_input, l4type); | |
5603 | /* src and dst are inverted, think how the receiver sees them */ | |
5604 | ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr); | |
5605 | ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr); | |
5606 | ||
5607 | /* This assumes the Rx queue and Tx queue are bound to the same CPU */ | |
5608 | ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue); | |
5609 | } | |
5610 | ||
e092be60 | 5611 | static int __ixgbe_maybe_stop_tx(struct net_device *netdev, |
b4617240 | 5612 | struct ixgbe_ring *tx_ring, int size) |
e092be60 | 5613 | { |
30eba97a | 5614 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
e092be60 AV |
5615 | /* Herbert's original patch had: |
5616 | * smp_mb__after_netif_stop_queue(); | |
5617 | * but since that doesn't exist yet, just open code it. */ | |
5618 | smp_mb(); | |
5619 | ||
5620 | /* We need to check again in a case another CPU has just | |
5621 | * made room available. */ | |
5622 | if (likely(IXGBE_DESC_UNUSED(tx_ring) < size)) | |
5623 | return -EBUSY; | |
5624 | ||
5625 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
af72166f | 5626 | netif_start_subqueue(netdev, tx_ring->queue_index); |
7ca3bc58 | 5627 | ++tx_ring->restart_queue; |
e092be60 AV |
5628 | return 0; |
5629 | } | |
5630 | ||
5631 | static int ixgbe_maybe_stop_tx(struct net_device *netdev, | |
b4617240 | 5632 | struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
5633 | { |
5634 | if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size)) | |
5635 | return 0; | |
5636 | return __ixgbe_maybe_stop_tx(netdev, tx_ring, size); | |
5637 | } | |
5638 | ||
09a3b1f8 SH |
5639 | static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb) |
5640 | { | |
5641 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
5f715823 | 5642 | int txq = smp_processor_id(); |
09a3b1f8 | 5643 | |
fdd3d631 KK |
5644 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
5645 | while (unlikely(txq >= dev->real_num_tx_queues)) | |
5646 | txq -= dev->real_num_tx_queues; | |
5f715823 | 5647 | return txq; |
fdd3d631 | 5648 | } |
c4cf55e5 | 5649 | |
5f715823 YZ |
5650 | #ifdef IXGBE_FCOE |
5651 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
ca77cd59 RL |
5652 | ((skb->protocol == htons(ETH_P_FCOE)) || |
5653 | (skb->protocol == htons(ETH_P_FIP)))) { | |
5f715823 YZ |
5654 | txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1); |
5655 | txq += adapter->ring_feature[RING_F_FCOE].mask; | |
5656 | return txq; | |
5657 | } | |
5658 | #endif | |
2ea186ae JF |
5659 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
5660 | if (skb->priority == TC_PRIO_CONTROL) | |
5661 | txq = adapter->ring_feature[RING_F_DCB].indices-1; | |
5662 | else | |
5663 | txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) | |
5664 | >> 13; | |
5665 | return txq; | |
5666 | } | |
09a3b1f8 SH |
5667 | |
5668 | return skb_tx_hash(dev, skb); | |
5669 | } | |
5670 | ||
3b29a56d SH |
5671 | static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, |
5672 | struct net_device *netdev) | |
9a799d71 AK |
5673 | { |
5674 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5675 | struct ixgbe_ring *tx_ring; | |
60d51134 | 5676 | struct netdev_queue *txq; |
9a799d71 AK |
5677 | unsigned int first; |
5678 | unsigned int tx_flags = 0; | |
30eba97a | 5679 | u8 hdr_len = 0; |
5f715823 | 5680 | int tso; |
9a799d71 AK |
5681 | int count = 0; |
5682 | unsigned int f; | |
9f8cdf4f | 5683 | |
9f8cdf4f JB |
5684 | if (adapter->vlgrp && vlan_tx_tag_present(skb)) { |
5685 | tx_flags |= vlan_tx_tag_get(skb); | |
2f90b865 AD |
5686 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
5687 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; | |
5f715823 | 5688 | tx_flags |= ((skb->queue_mapping & 0x7) << 13); |
2f90b865 AD |
5689 | } |
5690 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; | |
5691 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
5692 | } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
2ea186ae JF |
5693 | tx_flags |= ((skb->queue_mapping & 0x7) << 13); |
5694 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; | |
5695 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
9a799d71 | 5696 | } |
eacd73f7 | 5697 | |
4a0b9ca0 | 5698 | tx_ring = adapter->tx_ring[skb->queue_mapping]; |
60127865 | 5699 | |
09ad1cc0 | 5700 | #ifdef IXGBE_FCOE |
ca77cd59 | 5701 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { |
61a0f421 | 5702 | #ifdef CONFIG_IXGBE_DCB |
ca77cd59 RL |
5703 | /* for FCoE with DCB, we force the priority to what |
5704 | * was specified by the switch */ | |
5705 | if ((skb->protocol == htons(ETH_P_FCOE)) || | |
5706 | (skb->protocol == htons(ETH_P_FIP))) { | |
5707 | tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK | |
5708 | << IXGBE_TX_FLAGS_VLAN_SHIFT); | |
5709 | tx_flags |= ((adapter->fcoe.up << 13) | |
5710 | << IXGBE_TX_FLAGS_VLAN_SHIFT); | |
5711 | } | |
09ad1cc0 | 5712 | #endif |
ca77cd59 RL |
5713 | /* flag for FCoE offloads */ |
5714 | if (skb->protocol == htons(ETH_P_FCOE)) | |
5715 | tx_flags |= IXGBE_TX_FLAGS_FCOE; | |
09ad1cc0 | 5716 | } |
ca77cd59 RL |
5717 | #endif |
5718 | ||
eacd73f7 | 5719 | /* four things can cause us to need a context descriptor */ |
9f8cdf4f JB |
5720 | if (skb_is_gso(skb) || |
5721 | (skb->ip_summed == CHECKSUM_PARTIAL) || | |
eacd73f7 YZ |
5722 | (tx_flags & IXGBE_TX_FLAGS_VLAN) || |
5723 | (tx_flags & IXGBE_TX_FLAGS_FCOE)) | |
9a799d71 AK |
5724 | count++; |
5725 | ||
9f8cdf4f JB |
5726 | count += TXD_USE_COUNT(skb_headlen(skb)); |
5727 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
9a799d71 AK |
5728 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); |
5729 | ||
e092be60 | 5730 | if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) { |
9a799d71 | 5731 | adapter->tx_busy++; |
9a799d71 AK |
5732 | return NETDEV_TX_BUSY; |
5733 | } | |
9a799d71 | 5734 | |
9a799d71 | 5735 | first = tx_ring->next_to_use; |
eacd73f7 YZ |
5736 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { |
5737 | #ifdef IXGBE_FCOE | |
5738 | /* setup tx offload for FCoE */ | |
5739 | tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
5740 | if (tso < 0) { | |
5741 | dev_kfree_skb_any(skb); | |
5742 | return NETDEV_TX_OK; | |
5743 | } | |
5744 | if (tso) | |
5745 | tx_flags |= IXGBE_TX_FLAGS_FSO; | |
5746 | #endif /* IXGBE_FCOE */ | |
5747 | } else { | |
5748 | if (skb->protocol == htons(ETH_P_IP)) | |
5749 | tx_flags |= IXGBE_TX_FLAGS_IPV4; | |
5750 | tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
5751 | if (tso < 0) { | |
5752 | dev_kfree_skb_any(skb); | |
5753 | return NETDEV_TX_OK; | |
5754 | } | |
9a799d71 | 5755 | |
eacd73f7 YZ |
5756 | if (tso) |
5757 | tx_flags |= IXGBE_TX_FLAGS_TSO; | |
5758 | else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) && | |
5759 | (skb->ip_summed == CHECKSUM_PARTIAL)) | |
5760 | tx_flags |= IXGBE_TX_FLAGS_CSUM; | |
5761 | } | |
9a799d71 | 5762 | |
eacd73f7 | 5763 | count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first); |
44df32c5 | 5764 | if (count) { |
c4cf55e5 PWJ |
5765 | /* add the ATR filter if ATR is on */ |
5766 | if (tx_ring->atr_sample_rate) { | |
5767 | ++tx_ring->atr_count; | |
5768 | if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) && | |
5769 | test_bit(__IXGBE_FDIR_INIT_DONE, | |
5770 | &tx_ring->reinit_state)) { | |
5771 | ixgbe_atr(adapter, skb, tx_ring->queue_index, | |
5772 | tx_flags); | |
5773 | tx_ring->atr_count = 0; | |
5774 | } | |
5775 | } | |
60d51134 ED |
5776 | txq = netdev_get_tx_queue(netdev, tx_ring->queue_index); |
5777 | txq->tx_bytes += skb->len; | |
5778 | txq->tx_packets++; | |
44df32c5 AD |
5779 | ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len, |
5780 | hdr_len); | |
44df32c5 | 5781 | ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED); |
9a799d71 | 5782 | |
44df32c5 AD |
5783 | } else { |
5784 | dev_kfree_skb_any(skb); | |
5785 | tx_ring->tx_buffer_info[first].time_stamp = 0; | |
5786 | tx_ring->next_to_use = first; | |
5787 | } | |
9a799d71 AK |
5788 | |
5789 | return NETDEV_TX_OK; | |
5790 | } | |
5791 | ||
9a799d71 AK |
5792 | /** |
5793 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
5794 | * @netdev: network interface device structure | |
5795 | * @p: pointer to an address structure | |
5796 | * | |
5797 | * Returns 0 on success, negative on failure | |
5798 | **/ | |
5799 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
5800 | { | |
5801 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 5802 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
5803 | struct sockaddr *addr = p; |
5804 | ||
5805 | if (!is_valid_ether_addr(addr->sa_data)) | |
5806 | return -EADDRNOTAVAIL; | |
5807 | ||
5808 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 5809 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 5810 | |
1cdd1ec8 GR |
5811 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
5812 | IXGBE_RAH_AV); | |
9a799d71 AK |
5813 | |
5814 | return 0; | |
5815 | } | |
5816 | ||
6b73e10d BH |
5817 | static int |
5818 | ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) | |
5819 | { | |
5820 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5821 | struct ixgbe_hw *hw = &adapter->hw; | |
5822 | u16 value; | |
5823 | int rc; | |
5824 | ||
5825 | if (prtad != hw->phy.mdio.prtad) | |
5826 | return -EINVAL; | |
5827 | rc = hw->phy.ops.read_reg(hw, addr, devad, &value); | |
5828 | if (!rc) | |
5829 | rc = value; | |
5830 | return rc; | |
5831 | } | |
5832 | ||
5833 | static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, | |
5834 | u16 addr, u16 value) | |
5835 | { | |
5836 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5837 | struct ixgbe_hw *hw = &adapter->hw; | |
5838 | ||
5839 | if (prtad != hw->phy.mdio.prtad) | |
5840 | return -EINVAL; | |
5841 | return hw->phy.ops.write_reg(hw, addr, devad, value); | |
5842 | } | |
5843 | ||
5844 | static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | |
5845 | { | |
5846 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5847 | ||
5848 | return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); | |
5849 | } | |
5850 | ||
0365e6e4 PW |
5851 | /** |
5852 | * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding | |
31278e71 | 5853 | * netdev->dev_addrs |
0365e6e4 PW |
5854 | * @netdev: network interface device structure |
5855 | * | |
5856 | * Returns non-zero on failure | |
5857 | **/ | |
5858 | static int ixgbe_add_sanmac_netdev(struct net_device *dev) | |
5859 | { | |
5860 | int err = 0; | |
5861 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
5862 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
5863 | ||
5864 | if (is_valid_ether_addr(mac->san_addr)) { | |
5865 | rtnl_lock(); | |
5866 | err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
5867 | rtnl_unlock(); | |
5868 | } | |
5869 | return err; | |
5870 | } | |
5871 | ||
5872 | /** | |
5873 | * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding | |
31278e71 | 5874 | * netdev->dev_addrs |
0365e6e4 PW |
5875 | * @netdev: network interface device structure |
5876 | * | |
5877 | * Returns non-zero on failure | |
5878 | **/ | |
5879 | static int ixgbe_del_sanmac_netdev(struct net_device *dev) | |
5880 | { | |
5881 | int err = 0; | |
5882 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
5883 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
5884 | ||
5885 | if (is_valid_ether_addr(mac->san_addr)) { | |
5886 | rtnl_lock(); | |
5887 | err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
5888 | rtnl_unlock(); | |
5889 | } | |
5890 | return err; | |
5891 | } | |
5892 | ||
9a799d71 AK |
5893 | #ifdef CONFIG_NET_POLL_CONTROLLER |
5894 | /* | |
5895 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
5896 | * without having to re-enable interrupts. It's not called while | |
5897 | * the interrupt routine is executing. | |
5898 | */ | |
5899 | static void ixgbe_netpoll(struct net_device *netdev) | |
5900 | { | |
5901 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8f9a7167 | 5902 | int i; |
9a799d71 | 5903 | |
1a647bd2 AD |
5904 | /* if interface is down do nothing */ |
5905 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
5906 | return; | |
5907 | ||
9a799d71 | 5908 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; |
8f9a7167 PWJ |
5909 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
5910 | int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
5911 | for (i = 0; i < num_q_vectors; i++) { | |
5912 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; | |
5913 | ixgbe_msix_clean_many(0, q_vector); | |
5914 | } | |
5915 | } else { | |
5916 | ixgbe_intr(adapter->pdev->irq, netdev); | |
5917 | } | |
9a799d71 | 5918 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; |
9a799d71 AK |
5919 | } |
5920 | #endif | |
5921 | ||
0edc3527 SH |
5922 | static const struct net_device_ops ixgbe_netdev_ops = { |
5923 | .ndo_open = ixgbe_open, | |
5924 | .ndo_stop = ixgbe_close, | |
00829823 | 5925 | .ndo_start_xmit = ixgbe_xmit_frame, |
09a3b1f8 | 5926 | .ndo_select_queue = ixgbe_select_queue, |
e90d400c | 5927 | .ndo_set_rx_mode = ixgbe_set_rx_mode, |
0edc3527 SH |
5928 | .ndo_set_multicast_list = ixgbe_set_rx_mode, |
5929 | .ndo_validate_addr = eth_validate_addr, | |
5930 | .ndo_set_mac_address = ixgbe_set_mac, | |
5931 | .ndo_change_mtu = ixgbe_change_mtu, | |
5932 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
5933 | .ndo_vlan_rx_register = ixgbe_vlan_rx_register, | |
5934 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, | |
5935 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
6b73e10d | 5936 | .ndo_do_ioctl = ixgbe_ioctl, |
0edc3527 SH |
5937 | #ifdef CONFIG_NET_POLL_CONTROLLER |
5938 | .ndo_poll_controller = ixgbe_netpoll, | |
5939 | #endif | |
332d4a7d YZ |
5940 | #ifdef IXGBE_FCOE |
5941 | .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, | |
5942 | .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, | |
8450ff8c YZ |
5943 | .ndo_fcoe_enable = ixgbe_fcoe_enable, |
5944 | .ndo_fcoe_disable = ixgbe_fcoe_disable, | |
61a1fa10 | 5945 | .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, |
332d4a7d | 5946 | #endif /* IXGBE_FCOE */ |
0edc3527 SH |
5947 | }; |
5948 | ||
1cdd1ec8 GR |
5949 | static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter, |
5950 | const struct ixgbe_info *ii) | |
5951 | { | |
5952 | #ifdef CONFIG_PCI_IOV | |
5953 | struct ixgbe_hw *hw = &adapter->hw; | |
5954 | int err; | |
5955 | ||
5956 | if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs) | |
5957 | return; | |
5958 | ||
5959 | /* The 82599 supports up to 64 VFs per physical function | |
5960 | * but this implementation limits allocation to 63 so that | |
5961 | * basic networking resources are still available to the | |
5962 | * physical function | |
5963 | */ | |
5964 | adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs; | |
5965 | adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED; | |
5966 | err = pci_enable_sriov(adapter->pdev, adapter->num_vfs); | |
5967 | if (err) { | |
5968 | DPRINTK(PROBE, ERR, | |
5969 | "Failed to enable PCI sriov: %d\n", err); | |
5970 | goto err_novfs; | |
5971 | } | |
5972 | /* If call to enable VFs succeeded then allocate memory | |
5973 | * for per VF control structures. | |
5974 | */ | |
5975 | adapter->vfinfo = | |
5976 | kcalloc(adapter->num_vfs, | |
5977 | sizeof(struct vf_data_storage), GFP_KERNEL); | |
5978 | if (adapter->vfinfo) { | |
5979 | /* Now that we're sure SR-IOV is enabled | |
5980 | * and memory allocated set up the mailbox parameters | |
5981 | */ | |
5982 | ixgbe_init_mbx_params_pf(hw); | |
5983 | memcpy(&hw->mbx.ops, ii->mbx_ops, | |
5984 | sizeof(hw->mbx.ops)); | |
5985 | ||
5986 | /* Disable RSC when in SR-IOV mode */ | |
5987 | adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE | | |
5988 | IXGBE_FLAG2_RSC_ENABLED); | |
5989 | return; | |
5990 | } | |
5991 | ||
5992 | /* Oh oh */ | |
5993 | DPRINTK(PROBE, ERR, | |
5994 | "Unable to allocate memory for VF " | |
5995 | "Data Storage - SRIOV disabled\n"); | |
5996 | pci_disable_sriov(adapter->pdev); | |
5997 | ||
5998 | err_novfs: | |
5999 | adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED; | |
6000 | adapter->num_vfs = 0; | |
6001 | #endif /* CONFIG_PCI_IOV */ | |
6002 | } | |
6003 | ||
9a799d71 AK |
6004 | /** |
6005 | * ixgbe_probe - Device Initialization Routine | |
6006 | * @pdev: PCI device information struct | |
6007 | * @ent: entry in ixgbe_pci_tbl | |
6008 | * | |
6009 | * Returns 0 on success, negative on failure | |
6010 | * | |
6011 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
6012 | * The OS initialization, configuring of the adapter private structure, | |
6013 | * and a hardware reset occur. | |
6014 | **/ | |
6015 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
b4617240 | 6016 | const struct pci_device_id *ent) |
9a799d71 AK |
6017 | { |
6018 | struct net_device *netdev; | |
6019 | struct ixgbe_adapter *adapter = NULL; | |
6020 | struct ixgbe_hw *hw; | |
6021 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
6022 | static int cards_found; |
6023 | int i, err, pci_using_dac; | |
c85a2618 | 6024 | unsigned int indices = num_possible_cpus(); |
eacd73f7 YZ |
6025 | #ifdef IXGBE_FCOE |
6026 | u16 device_caps; | |
6027 | #endif | |
c44ade9e | 6028 | u32 part_num, eec; |
9a799d71 | 6029 | |
9ce77666 | 6030 | err = pci_enable_device_mem(pdev); |
9a799d71 AK |
6031 | if (err) |
6032 | return err; | |
6033 | ||
6a35528a YH |
6034 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && |
6035 | !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { | |
9a799d71 AK |
6036 | pci_using_dac = 1; |
6037 | } else { | |
284901a9 | 6038 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
9a799d71 | 6039 | if (err) { |
284901a9 | 6040 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
9a799d71 | 6041 | if (err) { |
b4617240 PW |
6042 | dev_err(&pdev->dev, "No usable DMA " |
6043 | "configuration, aborting\n"); | |
9a799d71 AK |
6044 | goto err_dma; |
6045 | } | |
6046 | } | |
6047 | pci_using_dac = 0; | |
6048 | } | |
6049 | ||
9ce77666 | 6050 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
6051 | IORESOURCE_MEM), ixgbe_driver_name); | |
9a799d71 | 6052 | if (err) { |
9ce77666 | 6053 | dev_err(&pdev->dev, |
6054 | "pci_request_selected_regions failed 0x%x\n", err); | |
9a799d71 AK |
6055 | goto err_pci_reg; |
6056 | } | |
6057 | ||
19d5afd4 | 6058 | pci_enable_pcie_error_reporting(pdev); |
6fabd715 | 6059 | |
9a799d71 | 6060 | pci_set_master(pdev); |
fb3b27bc | 6061 | pci_save_state(pdev); |
9a799d71 | 6062 | |
c85a2618 JF |
6063 | if (ii->mac == ixgbe_mac_82598EB) |
6064 | indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES); | |
6065 | else | |
6066 | indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES); | |
6067 | ||
6068 | indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES); | |
6069 | #ifdef IXGBE_FCOE | |
6070 | indices += min_t(unsigned int, num_possible_cpus(), | |
6071 | IXGBE_MAX_FCOE_INDICES); | |
6072 | #endif | |
c85a2618 | 6073 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); |
9a799d71 AK |
6074 | if (!netdev) { |
6075 | err = -ENOMEM; | |
6076 | goto err_alloc_etherdev; | |
6077 | } | |
6078 | ||
9a799d71 AK |
6079 | SET_NETDEV_DEV(netdev, &pdev->dev); |
6080 | ||
6081 | pci_set_drvdata(pdev, netdev); | |
6082 | adapter = netdev_priv(netdev); | |
6083 | ||
6084 | adapter->netdev = netdev; | |
6085 | adapter->pdev = pdev; | |
6086 | hw = &adapter->hw; | |
6087 | hw->back = adapter; | |
6088 | adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1; | |
6089 | ||
05857980 JK |
6090 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
6091 | pci_resource_len(pdev, 0)); | |
9a799d71 AK |
6092 | if (!hw->hw_addr) { |
6093 | err = -EIO; | |
6094 | goto err_ioremap; | |
6095 | } | |
6096 | ||
6097 | for (i = 1; i <= 5; i++) { | |
6098 | if (pci_resource_len(pdev, i) == 0) | |
6099 | continue; | |
6100 | } | |
6101 | ||
0edc3527 | 6102 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 6103 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 6104 | netdev->watchdog_timeo = 5 * HZ; |
9a799d71 AK |
6105 | strcpy(netdev->name, pci_name(pdev)); |
6106 | ||
9a799d71 AK |
6107 | adapter->bd_number = cards_found; |
6108 | ||
9a799d71 AK |
6109 | /* Setup hw api */ |
6110 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 6111 | hw->mac.type = ii->mac; |
9a799d71 | 6112 | |
c44ade9e JB |
6113 | /* EEPROM */ |
6114 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
6115 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
6116 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
6117 | if (!(eec & (1 << 8))) | |
6118 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
6119 | ||
6120 | /* PHY */ | |
6121 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 | 6122 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
6b73e10d BH |
6123 | /* ixgbe_identify_phy_generic will set prtad and mmds properly */ |
6124 | hw->phy.mdio.prtad = MDIO_PRTAD_NONE; | |
6125 | hw->phy.mdio.mmds = 0; | |
6126 | hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
6127 | hw->phy.mdio.dev = netdev; | |
6128 | hw->phy.mdio.mdio_read = ixgbe_mdio_read; | |
6129 | hw->phy.mdio.mdio_write = ixgbe_mdio_write; | |
c4900be0 DS |
6130 | |
6131 | /* set up this timer and work struct before calling get_invariants | |
6132 | * which might start the timer | |
6133 | */ | |
6134 | init_timer(&adapter->sfp_timer); | |
6135 | adapter->sfp_timer.function = &ixgbe_sfp_timer; | |
6136 | adapter->sfp_timer.data = (unsigned long) adapter; | |
6137 | ||
6138 | INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task); | |
c44ade9e | 6139 | |
e8e26350 PW |
6140 | /* multispeed fiber has its own tasklet, called from GPI SDP1 context */ |
6141 | INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task); | |
6142 | ||
6143 | /* a new SFP+ module arrival, called from GPI SDP2 context */ | |
6144 | INIT_WORK(&adapter->sfp_config_module_task, | |
6145 | ixgbe_sfp_config_module_task); | |
6146 | ||
8ca783ab | 6147 | ii->get_invariants(hw); |
9a799d71 AK |
6148 | |
6149 | /* setup the private structure */ | |
6150 | err = ixgbe_sw_init(adapter); | |
6151 | if (err) | |
6152 | goto err_sw_init; | |
6153 | ||
e86bff0e DS |
6154 | /* Make it possible the adapter to be woken up via WOL */ |
6155 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) | |
6156 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); | |
6157 | ||
bf069c97 DS |
6158 | /* |
6159 | * If there is a fan on this device and it has failed log the | |
6160 | * failure. | |
6161 | */ | |
6162 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
6163 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
6164 | if (esdp & IXGBE_ESDP_SDP1) | |
6165 | DPRINTK(PROBE, CRIT, | |
6166 | "Fan has stopped, replace the adapter\n"); | |
6167 | } | |
6168 | ||
c44ade9e JB |
6169 | /* reset_hw fills in the perm_addr as well */ |
6170 | err = hw->mac.ops.reset_hw(hw); | |
8ca783ab DS |
6171 | if (err == IXGBE_ERR_SFP_NOT_PRESENT && |
6172 | hw->mac.type == ixgbe_mac_82598EB) { | |
6173 | /* | |
6174 | * Start a kernel thread to watch for a module to arrive. | |
6175 | * Only do this for 82598, since 82599 will generate | |
6176 | * interrupts on module arrival. | |
6177 | */ | |
6178 | set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
6179 | mod_timer(&adapter->sfp_timer, | |
6180 | round_jiffies(jiffies + (2 * HZ))); | |
6181 | err = 0; | |
6182 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
88d2b81f DS |
6183 | dev_err(&adapter->pdev->dev, "failed to initialize because " |
6184 | "an unsupported SFP+ module type was detected.\n" | |
6185 | "Reload the driver after installing a supported " | |
6186 | "module.\n"); | |
04f165ef PW |
6187 | goto err_sw_init; |
6188 | } else if (err) { | |
c44ade9e JB |
6189 | dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err); |
6190 | goto err_sw_init; | |
6191 | } | |
6192 | ||
1cdd1ec8 GR |
6193 | ixgbe_probe_vf(adapter, ii); |
6194 | ||
9a799d71 | 6195 | netdev->features = NETIF_F_SG | |
b4617240 PW |
6196 | NETIF_F_IP_CSUM | |
6197 | NETIF_F_HW_VLAN_TX | | |
6198 | NETIF_F_HW_VLAN_RX | | |
6199 | NETIF_F_HW_VLAN_FILTER; | |
9a799d71 | 6200 | |
e9990a9c | 6201 | netdev->features |= NETIF_F_IPV6_CSUM; |
9a799d71 | 6202 | netdev->features |= NETIF_F_TSO; |
9a799d71 | 6203 | netdev->features |= NETIF_F_TSO6; |
78b6f4ce | 6204 | netdev->features |= NETIF_F_GRO; |
ad31c402 | 6205 | |
45a5ead0 JB |
6206 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) |
6207 | netdev->features |= NETIF_F_SCTP_CSUM; | |
6208 | ||
ad31c402 JK |
6209 | netdev->vlan_features |= NETIF_F_TSO; |
6210 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 6211 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
cd1da503 | 6212 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; |
ad31c402 JK |
6213 | netdev->vlan_features |= NETIF_F_SG; |
6214 | ||
1cdd1ec8 GR |
6215 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
6216 | adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED | | |
6217 | IXGBE_FLAG_DCB_ENABLED); | |
2f90b865 AD |
6218 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) |
6219 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
6220 | ||
7a6b6f51 | 6221 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
6222 | netdev->dcbnl_ops = &dcbnl_ops; |
6223 | #endif | |
6224 | ||
eacd73f7 | 6225 | #ifdef IXGBE_FCOE |
0d551589 | 6226 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
eacd73f7 YZ |
6227 | if (hw->mac.ops.get_device_caps) { |
6228 | hw->mac.ops.get_device_caps(hw, &device_caps); | |
0d551589 YZ |
6229 | if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) |
6230 | adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; | |
eacd73f7 YZ |
6231 | } |
6232 | } | |
6233 | #endif /* IXGBE_FCOE */ | |
9a799d71 AK |
6234 | if (pci_using_dac) |
6235 | netdev->features |= NETIF_F_HIGHDMA; | |
6236 | ||
0c19d6af | 6237 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
f8212f97 AD |
6238 | netdev->features |= NETIF_F_LRO; |
6239 | ||
9a799d71 | 6240 | /* make sure the EEPROM is good */ |
c44ade9e | 6241 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
9a799d71 AK |
6242 | dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n"); |
6243 | err = -EIO; | |
6244 | goto err_eeprom; | |
6245 | } | |
6246 | ||
6247 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
6248 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
6249 | ||
c44ade9e JB |
6250 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
6251 | dev_err(&pdev->dev, "invalid MAC address\n"); | |
9a799d71 AK |
6252 | err = -EIO; |
6253 | goto err_eeprom; | |
6254 | } | |
6255 | ||
6256 | init_timer(&adapter->watchdog_timer); | |
6257 | adapter->watchdog_timer.function = &ixgbe_watchdog; | |
6258 | adapter->watchdog_timer.data = (unsigned long)adapter; | |
6259 | ||
6260 | INIT_WORK(&adapter->reset_task, ixgbe_reset_task); | |
cf8280ee | 6261 | INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task); |
9a799d71 | 6262 | |
021230d4 AV |
6263 | err = ixgbe_init_interrupt_scheme(adapter); |
6264 | if (err) | |
6265 | goto err_sw_init; | |
9a799d71 | 6266 | |
e8e26350 PW |
6267 | switch (pdev->device) { |
6268 | case IXGBE_DEV_ID_82599_KX4: | |
495dce12 WJP |
6269 | adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX | |
6270 | IXGBE_WUFC_MC | IXGBE_WUFC_BC); | |
e8e26350 PW |
6271 | break; |
6272 | default: | |
6273 | adapter->wol = 0; | |
6274 | break; | |
6275 | } | |
e8e26350 PW |
6276 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
6277 | ||
04f165ef PW |
6278 | /* pick up the PCI bus settings for reporting later */ |
6279 | hw->mac.ops.get_bus_info(hw); | |
6280 | ||
9a799d71 | 6281 | /* print bus type/speed/width info */ |
7c510e4b | 6282 | dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n", |
e8e26350 PW |
6283 | ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s": |
6284 | (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"), | |
6285 | ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" : | |
6286 | (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" : | |
6287 | (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" : | |
b4617240 | 6288 | "Unknown"), |
7c510e4b | 6289 | netdev->dev_addr); |
c44ade9e | 6290 | ixgbe_read_pba_num_generic(hw, &part_num); |
e8e26350 PW |
6291 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
6292 | dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n", | |
6293 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, | |
6294 | (part_num >> 8), (part_num & 0xff)); | |
6295 | else | |
6296 | dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n", | |
6297 | hw->mac.type, hw->phy.type, | |
6298 | (part_num >> 8), (part_num & 0xff)); | |
9a799d71 | 6299 | |
e8e26350 | 6300 | if (hw->bus.width <= ixgbe_bus_width_pcie_x4) { |
0c254d86 | 6301 | dev_warn(&pdev->dev, "PCI-Express bandwidth available for " |
b4617240 PW |
6302 | "this card is not sufficient for optimal " |
6303 | "performance.\n"); | |
0c254d86 | 6304 | dev_warn(&pdev->dev, "For optimal performance a x8 " |
b4617240 | 6305 | "PCI-Express slot is required.\n"); |
0c254d86 AK |
6306 | } |
6307 | ||
34b0368c PWJ |
6308 | /* save off EEPROM version number */ |
6309 | hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version); | |
6310 | ||
9a799d71 | 6311 | /* reset the hardware with the new settings */ |
794caeb2 | 6312 | err = hw->mac.ops.start_hw(hw); |
c44ade9e | 6313 | |
794caeb2 PWJ |
6314 | if (err == IXGBE_ERR_EEPROM_VERSION) { |
6315 | /* We are running on a pre-production device, log a warning */ | |
6316 | dev_warn(&pdev->dev, "This device is a pre-production " | |
6317 | "adapter/LOM. Please be aware there may be issues " | |
6318 | "associated with your hardware. If you are " | |
6319 | "experiencing problems please contact your Intel or " | |
6320 | "hardware representative who provided you with this " | |
6321 | "hardware.\n"); | |
6322 | } | |
9a799d71 AK |
6323 | strcpy(netdev->name, "eth%d"); |
6324 | err = register_netdev(netdev); | |
6325 | if (err) | |
6326 | goto err_register; | |
6327 | ||
54386467 JB |
6328 | /* carrier off reporting is important to ethtool even BEFORE open */ |
6329 | netif_carrier_off(netdev); | |
6330 | ||
c4cf55e5 PWJ |
6331 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
6332 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
6333 | INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task); | |
6334 | ||
5dd2d332 | 6335 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 6336 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd | 6337 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
6338 | ixgbe_setup_dca(adapter); |
6339 | } | |
6340 | #endif | |
1cdd1ec8 GR |
6341 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
6342 | DPRINTK(PROBE, INFO, "IOV is enabled with %d VFs\n", | |
6343 | adapter->num_vfs); | |
6344 | for (i = 0; i < adapter->num_vfs; i++) | |
6345 | ixgbe_vf_configuration(pdev, (i | 0x10000000)); | |
6346 | } | |
6347 | ||
0365e6e4 PW |
6348 | /* add san mac addr to netdev */ |
6349 | ixgbe_add_sanmac_netdev(netdev); | |
9a799d71 AK |
6350 | |
6351 | dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n"); | |
6352 | cards_found++; | |
6353 | return 0; | |
6354 | ||
6355 | err_register: | |
5eba3699 | 6356 | ixgbe_release_hw_control(adapter); |
7a921c93 | 6357 | ixgbe_clear_interrupt_scheme(adapter); |
9a799d71 AK |
6358 | err_sw_init: |
6359 | err_eeprom: | |
1cdd1ec8 GR |
6360 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
6361 | ixgbe_disable_sriov(adapter); | |
c4900be0 DS |
6362 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); |
6363 | del_timer_sync(&adapter->sfp_timer); | |
6364 | cancel_work_sync(&adapter->sfp_task); | |
e8e26350 PW |
6365 | cancel_work_sync(&adapter->multispeed_fiber_task); |
6366 | cancel_work_sync(&adapter->sfp_config_module_task); | |
9a799d71 AK |
6367 | iounmap(hw->hw_addr); |
6368 | err_ioremap: | |
6369 | free_netdev(netdev); | |
6370 | err_alloc_etherdev: | |
9ce77666 | 6371 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
6372 | IORESOURCE_MEM)); | |
9a799d71 AK |
6373 | err_pci_reg: |
6374 | err_dma: | |
6375 | pci_disable_device(pdev); | |
6376 | return err; | |
6377 | } | |
6378 | ||
6379 | /** | |
6380 | * ixgbe_remove - Device Removal Routine | |
6381 | * @pdev: PCI device information struct | |
6382 | * | |
6383 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
6384 | * that it should release a PCI device. The could be caused by a | |
6385 | * Hot-Plug event, or because the driver is going to be removed from | |
6386 | * memory. | |
6387 | **/ | |
6388 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
6389 | { | |
6390 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6391 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6392 | ||
6393 | set_bit(__IXGBE_DOWN, &adapter->state); | |
c4900be0 DS |
6394 | /* clear the module not found bit to make sure the worker won't |
6395 | * reschedule | |
6396 | */ | |
6397 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
9a799d71 AK |
6398 | del_timer_sync(&adapter->watchdog_timer); |
6399 | ||
c4900be0 DS |
6400 | del_timer_sync(&adapter->sfp_timer); |
6401 | cancel_work_sync(&adapter->watchdog_task); | |
6402 | cancel_work_sync(&adapter->sfp_task); | |
1097cd17 MC |
6403 | if (adapter->hw.phy.multispeed_fiber) { |
6404 | struct ixgbe_hw *hw = &adapter->hw; | |
6405 | /* | |
6406 | * Restart clause 37 autoneg, disable and re-enable | |
6407 | * the tx laser, to clear & alert the link partner | |
6408 | * that it needs to restart autotry | |
6409 | */ | |
6410 | hw->mac.autotry_restart = true; | |
6411 | hw->mac.ops.flap_tx_laser(hw); | |
6412 | } | |
e8e26350 PW |
6413 | cancel_work_sync(&adapter->multispeed_fiber_task); |
6414 | cancel_work_sync(&adapter->sfp_config_module_task); | |
c4cf55e5 PWJ |
6415 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
6416 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
6417 | cancel_work_sync(&adapter->fdir_reinit_task); | |
9a799d71 AK |
6418 | flush_scheduled_work(); |
6419 | ||
5dd2d332 | 6420 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
6421 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
6422 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
6423 | dca_remove_requester(&pdev->dev); | |
6424 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
6425 | } | |
6426 | ||
6427 | #endif | |
332d4a7d YZ |
6428 | #ifdef IXGBE_FCOE |
6429 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
6430 | ixgbe_cleanup_fcoe(adapter); | |
6431 | ||
6432 | #endif /* IXGBE_FCOE */ | |
0365e6e4 PW |
6433 | |
6434 | /* remove the added san mac */ | |
6435 | ixgbe_del_sanmac_netdev(netdev); | |
6436 | ||
c4900be0 DS |
6437 | if (netdev->reg_state == NETREG_REGISTERED) |
6438 | unregister_netdev(netdev); | |
9a799d71 | 6439 | |
1cdd1ec8 GR |
6440 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
6441 | ixgbe_disable_sriov(adapter); | |
6442 | ||
7a921c93 | 6443 | ixgbe_clear_interrupt_scheme(adapter); |
5eba3699 | 6444 | |
021230d4 | 6445 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
6446 | |
6447 | iounmap(adapter->hw.hw_addr); | |
9ce77666 | 6448 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
6449 | IORESOURCE_MEM)); | |
9a799d71 | 6450 | |
021230d4 | 6451 | DPRINTK(PROBE, INFO, "complete\n"); |
021230d4 | 6452 | |
9a799d71 AK |
6453 | free_netdev(netdev); |
6454 | ||
19d5afd4 | 6455 | pci_disable_pcie_error_reporting(pdev); |
6fabd715 | 6456 | |
9a799d71 AK |
6457 | pci_disable_device(pdev); |
6458 | } | |
6459 | ||
6460 | /** | |
6461 | * ixgbe_io_error_detected - called when PCI error is detected | |
6462 | * @pdev: Pointer to PCI device | |
6463 | * @state: The current pci connection state | |
6464 | * | |
6465 | * This function is called after a PCI bus error affecting | |
6466 | * this device has been detected. | |
6467 | */ | |
6468 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
b4617240 | 6469 | pci_channel_state_t state) |
9a799d71 AK |
6470 | { |
6471 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 6472 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
6473 | |
6474 | netif_device_detach(netdev); | |
6475 | ||
3044b8d1 BL |
6476 | if (state == pci_channel_io_perm_failure) |
6477 | return PCI_ERS_RESULT_DISCONNECT; | |
6478 | ||
9a799d71 AK |
6479 | if (netif_running(netdev)) |
6480 | ixgbe_down(adapter); | |
6481 | pci_disable_device(pdev); | |
6482 | ||
b4617240 | 6483 | /* Request a slot reset. */ |
9a799d71 AK |
6484 | return PCI_ERS_RESULT_NEED_RESET; |
6485 | } | |
6486 | ||
6487 | /** | |
6488 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
6489 | * @pdev: Pointer to PCI device | |
6490 | * | |
6491 | * Restart the card from scratch, as if from a cold-boot. | |
6492 | */ | |
6493 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
6494 | { | |
6495 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 6496 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
6fabd715 PWJ |
6497 | pci_ers_result_t result; |
6498 | int err; | |
9a799d71 | 6499 | |
9ce77666 | 6500 | if (pci_enable_device_mem(pdev)) { |
9a799d71 | 6501 | DPRINTK(PROBE, ERR, |
b4617240 | 6502 | "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
6503 | result = PCI_ERS_RESULT_DISCONNECT; |
6504 | } else { | |
6505 | pci_set_master(pdev); | |
6506 | pci_restore_state(pdev); | |
c0e1f68b | 6507 | pci_save_state(pdev); |
9a799d71 | 6508 | |
dd4d8ca6 | 6509 | pci_wake_from_d3(pdev, false); |
9a799d71 | 6510 | |
6fabd715 | 6511 | ixgbe_reset(adapter); |
88512539 | 6512 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6fabd715 PWJ |
6513 | result = PCI_ERS_RESULT_RECOVERED; |
6514 | } | |
6515 | ||
6516 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
6517 | if (err) { | |
6518 | dev_err(&pdev->dev, | |
6519 | "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err); | |
6520 | /* non-fatal, continue */ | |
6521 | } | |
9a799d71 | 6522 | |
6fabd715 | 6523 | return result; |
9a799d71 AK |
6524 | } |
6525 | ||
6526 | /** | |
6527 | * ixgbe_io_resume - called when traffic can start flowing again. | |
6528 | * @pdev: Pointer to PCI device | |
6529 | * | |
6530 | * This callback is called when the error recovery driver tells us that | |
6531 | * its OK to resume normal operation. | |
6532 | */ | |
6533 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
6534 | { | |
6535 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 6536 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
6537 | |
6538 | if (netif_running(netdev)) { | |
6539 | if (ixgbe_up(adapter)) { | |
6540 | DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n"); | |
6541 | return; | |
6542 | } | |
6543 | } | |
6544 | ||
6545 | netif_device_attach(netdev); | |
9a799d71 AK |
6546 | } |
6547 | ||
6548 | static struct pci_error_handlers ixgbe_err_handler = { | |
6549 | .error_detected = ixgbe_io_error_detected, | |
6550 | .slot_reset = ixgbe_io_slot_reset, | |
6551 | .resume = ixgbe_io_resume, | |
6552 | }; | |
6553 | ||
6554 | static struct pci_driver ixgbe_driver = { | |
6555 | .name = ixgbe_driver_name, | |
6556 | .id_table = ixgbe_pci_tbl, | |
6557 | .probe = ixgbe_probe, | |
6558 | .remove = __devexit_p(ixgbe_remove), | |
6559 | #ifdef CONFIG_PM | |
6560 | .suspend = ixgbe_suspend, | |
6561 | .resume = ixgbe_resume, | |
6562 | #endif | |
6563 | .shutdown = ixgbe_shutdown, | |
6564 | .err_handler = &ixgbe_err_handler | |
6565 | }; | |
6566 | ||
6567 | /** | |
6568 | * ixgbe_init_module - Driver Registration Routine | |
6569 | * | |
6570 | * ixgbe_init_module is the first routine called when the driver is | |
6571 | * loaded. All it does is register with the PCI subsystem. | |
6572 | **/ | |
6573 | static int __init ixgbe_init_module(void) | |
6574 | { | |
6575 | int ret; | |
6576 | printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name, | |
6577 | ixgbe_driver_string, ixgbe_driver_version); | |
6578 | ||
6579 | printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright); | |
6580 | ||
5dd2d332 | 6581 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 6582 | dca_register_notify(&dca_notifier); |
bd0362dd | 6583 | #endif |
5dd2d332 | 6584 | |
9a799d71 AK |
6585 | ret = pci_register_driver(&ixgbe_driver); |
6586 | return ret; | |
6587 | } | |
b4617240 | 6588 | |
9a799d71 AK |
6589 | module_init(ixgbe_init_module); |
6590 | ||
6591 | /** | |
6592 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
6593 | * | |
6594 | * ixgbe_exit_module is called just before the driver is removed | |
6595 | * from memory. | |
6596 | **/ | |
6597 | static void __exit ixgbe_exit_module(void) | |
6598 | { | |
5dd2d332 | 6599 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
6600 | dca_unregister_notify(&dca_notifier); |
6601 | #endif | |
9a799d71 AK |
6602 | pci_unregister_driver(&ixgbe_driver); |
6603 | } | |
bd0362dd | 6604 | |
5dd2d332 | 6605 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 6606 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
b4617240 | 6607 | void *p) |
bd0362dd JC |
6608 | { |
6609 | int ret_val; | |
6610 | ||
6611 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
b4617240 | 6612 | __ixgbe_notify_dca); |
bd0362dd JC |
6613 | |
6614 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
6615 | } | |
b453368d | 6616 | |
5dd2d332 | 6617 | #endif /* CONFIG_IXGBE_DCA */ |
b453368d AD |
6618 | #ifdef DEBUG |
6619 | /** | |
6620 | * ixgbe_get_hw_dev_name - return device name string | |
6621 | * used by hardware layer to print debugging information | |
6622 | **/ | |
6623 | char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw) | |
6624 | { | |
6625 | struct ixgbe_adapter *adapter = hw->back; | |
6626 | return adapter->netdev->name; | |
6627 | } | |
bd0362dd | 6628 | |
b453368d | 6629 | #endif |
9a799d71 AK |
6630 | module_exit(ixgbe_exit_module); |
6631 | ||
6632 | /* ixgbe_main.c */ |