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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
b4617240 | 4 | Copyright(c) 1999 - 2008 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
35 | #include <linux/ip.h> | |
36 | #include <linux/tcp.h> | |
37 | #include <linux/ipv6.h> | |
38 | #include <net/checksum.h> | |
39 | #include <net/ip6_checksum.h> | |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/if_vlan.h> | |
42 | ||
43 | #include "ixgbe.h" | |
44 | #include "ixgbe_common.h" | |
45 | ||
46 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 47 | static const char ixgbe_driver_string[] = |
b4617240 | 48 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
9a799d71 | 49 | |
51ac6445 | 50 | #define DRV_VERSION "1.3.30-k2" |
9c8eb720 | 51 | const char ixgbe_driver_version[] = DRV_VERSION; |
b4617240 | 52 | static char ixgbe_copyright[] = "Copyright (c) 1999-2007 Intel Corporation."; |
9a799d71 AK |
53 | |
54 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 55 | [board_82598] = &ixgbe_82598_info, |
9a799d71 AK |
56 | }; |
57 | ||
58 | /* ixgbe_pci_tbl - PCI Device ID Table | |
59 | * | |
60 | * Wildcard entries (PCI_ANY_ID) should come last | |
61 | * Last entry must be all 0s | |
62 | * | |
63 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
64 | * Class, Class Mask, private data (not used) } | |
65 | */ | |
66 | static struct pci_device_id ixgbe_pci_tbl[] = { | |
67 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), | |
3957d63d | 68 | board_82598 }, |
9a799d71 | 69 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), |
3957d63d | 70 | board_82598 }, |
0befdb3e JB |
71 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), |
72 | board_82598 }, | |
9a799d71 | 73 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), |
3957d63d | 74 | board_82598 }, |
8d792cd9 JB |
75 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), |
76 | board_82598 }, | |
c4900be0 DS |
77 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), |
78 | board_82598 }, | |
79 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), | |
80 | board_82598 }, | |
b95f5fcb JB |
81 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), |
82 | board_82598 }, | |
c4900be0 DS |
83 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), |
84 | board_82598 }, | |
9a799d71 AK |
85 | |
86 | /* required last entry */ | |
87 | {0, } | |
88 | }; | |
89 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
90 | ||
5dd2d332 | 91 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 92 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
b4617240 | 93 | void *p); |
bd0362dd JC |
94 | static struct notifier_block dca_notifier = { |
95 | .notifier_call = ixgbe_notify_dca, | |
96 | .next = NULL, | |
97 | .priority = 0 | |
98 | }; | |
99 | #endif | |
100 | ||
9a799d71 AK |
101 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
102 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
103 | MODULE_LICENSE("GPL"); | |
104 | MODULE_VERSION(DRV_VERSION); | |
105 | ||
106 | #define DEFAULT_DEBUG_LEVEL_SHIFT 3 | |
107 | ||
5eba3699 AV |
108 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
109 | { | |
110 | u32 ctrl_ext; | |
111 | ||
112 | /* Let firmware take over control of h/w */ | |
113 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
114 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 115 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
116 | } |
117 | ||
118 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
119 | { | |
120 | u32 ctrl_ext; | |
121 | ||
122 | /* Let firmware know the driver has taken over */ | |
123 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
124 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 125 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 126 | } |
9a799d71 | 127 | |
9a799d71 | 128 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, u16 int_alloc_entry, |
b4617240 | 129 | u8 msix_vector) |
9a799d71 AK |
130 | { |
131 | u32 ivar, index; | |
132 | ||
133 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
134 | index = (int_alloc_entry >> 2) & 0x1F; | |
135 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR(index)); | |
136 | ivar &= ~(0xFF << (8 * (int_alloc_entry & 0x3))); | |
137 | ivar |= (msix_vector << (8 * (int_alloc_entry & 0x3))); | |
138 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR(index), ivar); | |
139 | } | |
140 | ||
141 | static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter, | |
b4617240 PW |
142 | struct ixgbe_tx_buffer |
143 | *tx_buffer_info) | |
9a799d71 AK |
144 | { |
145 | if (tx_buffer_info->dma) { | |
e01c31a5 | 146 | pci_unmap_page(adapter->pdev, tx_buffer_info->dma, |
b4617240 | 147 | tx_buffer_info->length, PCI_DMA_TODEVICE); |
9a799d71 AK |
148 | tx_buffer_info->dma = 0; |
149 | } | |
150 | if (tx_buffer_info->skb) { | |
151 | dev_kfree_skb_any(tx_buffer_info->skb); | |
152 | tx_buffer_info->skb = NULL; | |
153 | } | |
154 | /* tx_buffer_info must be completely set up in the transmit path */ | |
155 | } | |
156 | ||
157 | static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter, | |
b4617240 PW |
158 | struct ixgbe_ring *tx_ring, |
159 | unsigned int eop) | |
9a799d71 | 160 | { |
e01c31a5 JB |
161 | struct ixgbe_hw *hw = &adapter->hw; |
162 | u32 head, tail; | |
163 | ||
9a799d71 | 164 | /* Detect a transmit hang in hardware, this serializes the |
e01c31a5 JB |
165 | * check with the clearing of time_stamp and movement of eop */ |
166 | head = IXGBE_READ_REG(hw, tx_ring->head); | |
167 | tail = IXGBE_READ_REG(hw, tx_ring->tail); | |
9a799d71 | 168 | adapter->detect_tx_hung = false; |
e01c31a5 JB |
169 | if ((head != tail) && |
170 | tx_ring->tx_buffer_info[eop].time_stamp && | |
9a799d71 AK |
171 | time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) && |
172 | !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) { | |
173 | /* detected Tx unit hang */ | |
e01c31a5 JB |
174 | union ixgbe_adv_tx_desc *tx_desc; |
175 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
9a799d71 | 176 | DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n" |
e01c31a5 JB |
177 | " Tx Queue <%d>\n" |
178 | " TDH, TDT <%x>, <%x>\n" | |
9a799d71 AK |
179 | " next_to_use <%x>\n" |
180 | " next_to_clean <%x>\n" | |
181 | "tx_buffer_info[next_to_clean]\n" | |
182 | " time_stamp <%lx>\n" | |
e01c31a5 JB |
183 | " jiffies <%lx>\n", |
184 | tx_ring->queue_index, | |
185 | head, tail, | |
186 | tx_ring->next_to_use, eop, | |
187 | tx_ring->tx_buffer_info[eop].time_stamp, jiffies); | |
9a799d71 AK |
188 | return true; |
189 | } | |
190 | ||
191 | return false; | |
192 | } | |
193 | ||
b4617240 PW |
194 | #define IXGBE_MAX_TXD_PWR 14 |
195 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
e092be60 AV |
196 | |
197 | /* Tx Descriptors needed, worst case */ | |
198 | #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \ | |
199 | (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0)) | |
200 | #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \ | |
b4617240 | 201 | MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */ |
e092be60 | 202 | |
e01c31a5 JB |
203 | #define GET_TX_HEAD_FROM_RING(ring) (\ |
204 | *(volatile u32 *) \ | |
205 | ((union ixgbe_adv_tx_desc *)(ring)->desc + (ring)->count)) | |
206 | static void ixgbe_tx_timeout(struct net_device *netdev); | |
207 | ||
9a799d71 AK |
208 | /** |
209 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
210 | * @adapter: board private structure | |
e01c31a5 | 211 | * @tx_ring: tx ring to clean |
9a799d71 AK |
212 | **/ |
213 | static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter, | |
e01c31a5 | 214 | struct ixgbe_ring *tx_ring) |
9a799d71 | 215 | { |
e01c31a5 | 216 | union ixgbe_adv_tx_desc *tx_desc; |
9a799d71 | 217 | struct ixgbe_tx_buffer *tx_buffer_info; |
e01c31a5 JB |
218 | struct net_device *netdev = adapter->netdev; |
219 | struct sk_buff *skb; | |
220 | unsigned int i; | |
221 | u32 head, oldhead; | |
222 | unsigned int count = 0; | |
223 | unsigned int total_bytes = 0, total_packets = 0; | |
9a799d71 | 224 | |
e01c31a5 JB |
225 | rmb(); |
226 | head = GET_TX_HEAD_FROM_RING(tx_ring); | |
227 | head = le32_to_cpu(head); | |
9a799d71 | 228 | i = tx_ring->next_to_clean; |
e01c31a5 JB |
229 | while (1) { |
230 | while (i != head) { | |
9a799d71 AK |
231 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); |
232 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
e01c31a5 | 233 | skb = tx_buffer_info->skb; |
9a799d71 | 234 | |
e01c31a5 | 235 | if (skb) { |
e092be60 | 236 | unsigned int segs, bytecount; |
e01c31a5 JB |
237 | |
238 | /* gso_segs is currently only valid for tcp */ | |
e092be60 AV |
239 | segs = skb_shinfo(skb)->gso_segs ?: 1; |
240 | /* multiply data chunks by size of headers */ | |
241 | bytecount = ((segs - 1) * skb_headlen(skb)) + | |
e01c31a5 JB |
242 | skb->len; |
243 | total_packets += segs; | |
244 | total_bytes += bytecount; | |
e092be60 | 245 | } |
e01c31a5 | 246 | |
9a799d71 | 247 | ixgbe_unmap_and_free_tx_resource(adapter, |
e01c31a5 | 248 | tx_buffer_info); |
9a799d71 AK |
249 | |
250 | i++; | |
251 | if (i == tx_ring->count) | |
252 | i = 0; | |
9a799d71 | 253 | |
e01c31a5 JB |
254 | count++; |
255 | if (count == tx_ring->count) | |
256 | goto done_cleaning; | |
257 | } | |
258 | oldhead = head; | |
259 | rmb(); | |
260 | head = GET_TX_HEAD_FROM_RING(tx_ring); | |
261 | head = le32_to_cpu(head); | |
262 | if (head == oldhead) | |
263 | goto done_cleaning; | |
264 | } /* while (1) */ | |
265 | ||
266 | done_cleaning: | |
9a799d71 AK |
267 | tx_ring->next_to_clean = i; |
268 | ||
e092be60 | 269 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
e01c31a5 JB |
270 | if (unlikely(count && netif_carrier_ok(netdev) && |
271 | (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { | |
e092be60 AV |
272 | /* Make sure that anybody stopping the queue after this |
273 | * sees the new next_to_clean. | |
274 | */ | |
275 | smp_mb(); | |
30eba97a AV |
276 | if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && |
277 | !test_bit(__IXGBE_DOWN, &adapter->state)) { | |
278 | netif_wake_subqueue(netdev, tx_ring->queue_index); | |
e01c31a5 | 279 | ++adapter->restart_queue; |
30eba97a | 280 | } |
e092be60 | 281 | } |
9a799d71 | 282 | |
e01c31a5 JB |
283 | if (adapter->detect_tx_hung) { |
284 | if (ixgbe_check_tx_hang(adapter, tx_ring, i)) { | |
285 | /* schedule immediate reset if we believe we hung */ | |
286 | DPRINTK(PROBE, INFO, | |
287 | "tx hang %d detected, resetting adapter\n", | |
288 | adapter->tx_timeout_count + 1); | |
289 | ixgbe_tx_timeout(adapter->netdev); | |
290 | } | |
291 | } | |
9a799d71 | 292 | |
e01c31a5 JB |
293 | /* re-arm the interrupt */ |
294 | if ((total_packets >= tx_ring->work_limit) || | |
295 | (count == tx_ring->count)) | |
296 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx); | |
9a799d71 | 297 | |
e01c31a5 JB |
298 | tx_ring->total_bytes += total_bytes; |
299 | tx_ring->total_packets += total_packets; | |
300 | tx_ring->stats.bytes += total_bytes; | |
301 | tx_ring->stats.packets += total_packets; | |
302 | adapter->net_stats.tx_bytes += total_bytes; | |
303 | adapter->net_stats.tx_packets += total_packets; | |
304 | return (total_packets ? true : false); | |
9a799d71 AK |
305 | } |
306 | ||
5dd2d332 | 307 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 308 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
b4617240 | 309 | struct ixgbe_ring *rx_ring) |
bd0362dd JC |
310 | { |
311 | u32 rxctrl; | |
312 | int cpu = get_cpu(); | |
3a581073 | 313 | int q = rx_ring - adapter->rx_ring; |
bd0362dd | 314 | |
3a581073 | 315 | if (rx_ring->cpu != cpu) { |
bd0362dd JC |
316 | rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q)); |
317 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK; | |
96b0e0f6 | 318 | rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); |
bd0362dd JC |
319 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN; |
320 | rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN; | |
321 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl); | |
3a581073 | 322 | rx_ring->cpu = cpu; |
bd0362dd JC |
323 | } |
324 | put_cpu(); | |
325 | } | |
326 | ||
327 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, | |
b4617240 | 328 | struct ixgbe_ring *tx_ring) |
bd0362dd JC |
329 | { |
330 | u32 txctrl; | |
331 | int cpu = get_cpu(); | |
3a581073 | 332 | int q = tx_ring - adapter->tx_ring; |
bd0362dd | 333 | |
3a581073 | 334 | if (tx_ring->cpu != cpu) { |
bd0362dd JC |
335 | txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q)); |
336 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK; | |
96b0e0f6 | 337 | txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); |
bd0362dd JC |
338 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; |
339 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl); | |
3a581073 | 340 | tx_ring->cpu = cpu; |
bd0362dd JC |
341 | } |
342 | put_cpu(); | |
343 | } | |
344 | ||
345 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
346 | { | |
347 | int i; | |
348 | ||
349 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
350 | return; | |
351 | ||
352 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
353 | adapter->tx_ring[i].cpu = -1; | |
354 | ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]); | |
355 | } | |
356 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
357 | adapter->rx_ring[i].cpu = -1; | |
358 | ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]); | |
359 | } | |
360 | } | |
361 | ||
362 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
363 | { | |
364 | struct net_device *netdev = dev_get_drvdata(dev); | |
365 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
366 | unsigned long event = *(unsigned long *)data; | |
367 | ||
368 | switch (event) { | |
369 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
370 | /* if we're already enabled, don't do it again */ |
371 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
372 | break; | |
bd0362dd JC |
373 | /* Always use CB2 mode, difference is masked |
374 | * in the CB driver. */ | |
375 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
652f093f | 376 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 377 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
378 | ixgbe_setup_dca(adapter); |
379 | break; | |
380 | } | |
381 | /* Fall Through since DCA is disabled. */ | |
382 | case DCA_PROVIDER_REMOVE: | |
383 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
384 | dca_remove_requester(dev); | |
385 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
386 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
387 | } | |
388 | break; | |
389 | } | |
390 | ||
652f093f | 391 | return 0; |
bd0362dd JC |
392 | } |
393 | ||
5dd2d332 | 394 | #endif /* CONFIG_IXGBE_DCA */ |
9a799d71 AK |
395 | /** |
396 | * ixgbe_receive_skb - Send a completed packet up the stack | |
397 | * @adapter: board private structure | |
398 | * @skb: packet to send up | |
177db6ff MC |
399 | * @status: hardware indication of status of receive |
400 | * @rx_ring: rx descriptor ring (for a specific queue) to setup | |
401 | * @rx_desc: rx descriptor | |
9a799d71 AK |
402 | **/ |
403 | static void ixgbe_receive_skb(struct ixgbe_adapter *adapter, | |
b4617240 PW |
404 | struct sk_buff *skb, u8 status, |
405 | struct ixgbe_ring *ring, | |
177db6ff | 406 | union ixgbe_adv_rx_desc *rx_desc) |
9a799d71 | 407 | { |
177db6ff MC |
408 | bool is_vlan = (status & IXGBE_RXD_STAT_VP); |
409 | u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan); | |
9a799d71 | 410 | |
177db6ff MC |
411 | if (adapter->netdev->features & NETIF_F_LRO && |
412 | skb->ip_summed == CHECKSUM_UNNECESSARY) { | |
2f90b865 | 413 | if (adapter->vlgrp && is_vlan && (tag != 0)) |
177db6ff MC |
414 | lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb, |
415 | adapter->vlgrp, tag, | |
416 | rx_desc); | |
9a799d71 | 417 | else |
177db6ff MC |
418 | lro_receive_skb(&ring->lro_mgr, skb, rx_desc); |
419 | ring->lro_used = true; | |
420 | } else { | |
421 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) { | |
2f90b865 | 422 | if (adapter->vlgrp && is_vlan && (tag != 0)) |
177db6ff MC |
423 | vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag); |
424 | else | |
425 | netif_receive_skb(skb); | |
426 | } else { | |
2f90b865 | 427 | if (adapter->vlgrp && is_vlan && (tag != 0)) |
177db6ff MC |
428 | vlan_hwaccel_rx(skb, adapter->vlgrp, tag); |
429 | else | |
430 | netif_rx(skb); | |
431 | } | |
9a799d71 AK |
432 | } |
433 | } | |
434 | ||
e59bd25d AV |
435 | /** |
436 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
437 | * @adapter: address of board private structure | |
438 | * @status_err: hardware indication of status of receive | |
439 | * @skb: skb currently being received and modified | |
440 | **/ | |
9a799d71 | 441 | static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter, |
712744be | 442 | u32 status_err, struct sk_buff *skb) |
9a799d71 AK |
443 | { |
444 | skb->ip_summed = CHECKSUM_NONE; | |
445 | ||
712744be JB |
446 | /* Rx csum disabled */ |
447 | if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED)) | |
9a799d71 | 448 | return; |
e59bd25d AV |
449 | |
450 | /* if IP and error */ | |
451 | if ((status_err & IXGBE_RXD_STAT_IPCS) && | |
452 | (status_err & IXGBE_RXDADV_ERR_IPE)) { | |
9a799d71 AK |
453 | adapter->hw_csum_rx_error++; |
454 | return; | |
455 | } | |
e59bd25d AV |
456 | |
457 | if (!(status_err & IXGBE_RXD_STAT_L4CS)) | |
458 | return; | |
459 | ||
460 | if (status_err & IXGBE_RXDADV_ERR_TCPE) { | |
461 | adapter->hw_csum_rx_error++; | |
462 | return; | |
463 | } | |
464 | ||
9a799d71 | 465 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 466 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
467 | adapter->hw_csum_rx_good++; |
468 | } | |
469 | ||
470 | /** | |
471 | * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split | |
472 | * @adapter: address of board private structure | |
473 | **/ | |
474 | static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter, | |
7c6e0a43 JB |
475 | struct ixgbe_ring *rx_ring, |
476 | int cleaned_count) | |
9a799d71 | 477 | { |
9a799d71 AK |
478 | struct pci_dev *pdev = adapter->pdev; |
479 | union ixgbe_adv_rx_desc *rx_desc; | |
3a581073 | 480 | struct ixgbe_rx_buffer *bi; |
9a799d71 | 481 | unsigned int i; |
7c6e0a43 | 482 | unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN; |
9a799d71 AK |
483 | |
484 | i = rx_ring->next_to_use; | |
3a581073 | 485 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 AK |
486 | |
487 | while (cleaned_count--) { | |
488 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
489 | ||
762f4c57 | 490 | if (!bi->page_dma && |
3a581073 | 491 | (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) { |
3a581073 | 492 | if (!bi->page) { |
762f4c57 JB |
493 | bi->page = alloc_page(GFP_ATOMIC); |
494 | if (!bi->page) { | |
495 | adapter->alloc_rx_page_failed++; | |
496 | goto no_buffers; | |
497 | } | |
498 | bi->page_offset = 0; | |
499 | } else { | |
500 | /* use a half page if we're re-using */ | |
501 | bi->page_offset ^= (PAGE_SIZE / 2); | |
9a799d71 | 502 | } |
762f4c57 JB |
503 | |
504 | bi->page_dma = pci_map_page(pdev, bi->page, | |
505 | bi->page_offset, | |
506 | (PAGE_SIZE / 2), | |
507 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
508 | } |
509 | ||
3a581073 | 510 | if (!bi->skb) { |
74ce8dd2 JB |
511 | struct sk_buff *skb = netdev_alloc_skb(adapter->netdev, |
512 | bufsz); | |
9a799d71 AK |
513 | |
514 | if (!skb) { | |
515 | adapter->alloc_rx_buff_failed++; | |
516 | goto no_buffers; | |
517 | } | |
518 | ||
519 | /* | |
520 | * Make buffer alignment 2 beyond a 16 byte boundary | |
521 | * this will result in a 16 byte aligned IP header after | |
522 | * the 14 byte MAC header is removed | |
523 | */ | |
524 | skb_reserve(skb, NET_IP_ALIGN); | |
525 | ||
3a581073 JB |
526 | bi->skb = skb; |
527 | bi->dma = pci_map_single(pdev, skb->data, bufsz, | |
528 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
529 | } |
530 | /* Refresh the desc even if buffer_addrs didn't change because | |
531 | * each write-back erases this info. */ | |
532 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
3a581073 JB |
533 | rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma); |
534 | rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); | |
9a799d71 | 535 | } else { |
3a581073 | 536 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma); |
9a799d71 AK |
537 | } |
538 | ||
539 | i++; | |
540 | if (i == rx_ring->count) | |
541 | i = 0; | |
3a581073 | 542 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 | 543 | } |
7c6e0a43 | 544 | |
9a799d71 AK |
545 | no_buffers: |
546 | if (rx_ring->next_to_use != i) { | |
547 | rx_ring->next_to_use = i; | |
548 | if (i-- == 0) | |
549 | i = (rx_ring->count - 1); | |
550 | ||
551 | /* | |
552 | * Force memory writes to complete before letting h/w | |
553 | * know there are new descriptors to fetch. (Only | |
554 | * applicable for weak-ordered memory model archs, | |
555 | * such as IA-64). | |
556 | */ | |
557 | wmb(); | |
558 | writel(i, adapter->hw.hw_addr + rx_ring->tail); | |
559 | } | |
560 | } | |
561 | ||
7c6e0a43 JB |
562 | static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc) |
563 | { | |
564 | return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info; | |
565 | } | |
566 | ||
567 | static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc) | |
568 | { | |
569 | return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
570 | } | |
571 | ||
9a799d71 | 572 | static bool ixgbe_clean_rx_irq(struct ixgbe_adapter *adapter, |
b4617240 PW |
573 | struct ixgbe_ring *rx_ring, |
574 | int *work_done, int work_to_do) | |
9a799d71 | 575 | { |
9a799d71 AK |
576 | struct pci_dev *pdev = adapter->pdev; |
577 | union ixgbe_adv_rx_desc *rx_desc, *next_rxd; | |
578 | struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer; | |
579 | struct sk_buff *skb; | |
580 | unsigned int i; | |
7c6e0a43 | 581 | u32 len, staterr; |
177db6ff MC |
582 | u16 hdr_info; |
583 | bool cleaned = false; | |
9a799d71 | 584 | int cleaned_count = 0; |
d2f4fbe2 | 585 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
9a799d71 AK |
586 | |
587 | i = rx_ring->next_to_clean; | |
9a799d71 AK |
588 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); |
589 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
590 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
9a799d71 AK |
591 | |
592 | while (staterr & IXGBE_RXD_STAT_DD) { | |
7c6e0a43 | 593 | u32 upper_len = 0; |
9a799d71 AK |
594 | if (*work_done >= work_to_do) |
595 | break; | |
596 | (*work_done)++; | |
597 | ||
598 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 JB |
599 | hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc)); |
600 | len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >> | |
762f4c57 | 601 | IXGBE_RXDADV_HDRBUFLEN_SHIFT; |
9a799d71 AK |
602 | if (hdr_info & IXGBE_RXDADV_SPH) |
603 | adapter->rx_hdr_split++; | |
604 | if (len > IXGBE_RX_HDR_SIZE) | |
605 | len = IXGBE_RX_HDR_SIZE; | |
606 | upper_len = le16_to_cpu(rx_desc->wb.upper.length); | |
7c6e0a43 | 607 | } else { |
9a799d71 | 608 | len = le16_to_cpu(rx_desc->wb.upper.length); |
7c6e0a43 | 609 | } |
9a799d71 AK |
610 | |
611 | cleaned = true; | |
612 | skb = rx_buffer_info->skb; | |
613 | prefetch(skb->data - NET_IP_ALIGN); | |
614 | rx_buffer_info->skb = NULL; | |
615 | ||
616 | if (len && !skb_shinfo(skb)->nr_frags) { | |
617 | pci_unmap_single(pdev, rx_buffer_info->dma, | |
b4617240 PW |
618 | rx_ring->rx_buf_len + NET_IP_ALIGN, |
619 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
620 | skb_put(skb, len); |
621 | } | |
622 | ||
623 | if (upper_len) { | |
624 | pci_unmap_page(pdev, rx_buffer_info->page_dma, | |
762f4c57 | 625 | PAGE_SIZE / 2, PCI_DMA_FROMDEVICE); |
9a799d71 AK |
626 | rx_buffer_info->page_dma = 0; |
627 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
762f4c57 JB |
628 | rx_buffer_info->page, |
629 | rx_buffer_info->page_offset, | |
630 | upper_len); | |
631 | ||
632 | if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) || | |
633 | (page_count(rx_buffer_info->page) != 1)) | |
634 | rx_buffer_info->page = NULL; | |
635 | else | |
636 | get_page(rx_buffer_info->page); | |
9a799d71 AK |
637 | |
638 | skb->len += upper_len; | |
639 | skb->data_len += upper_len; | |
640 | skb->truesize += upper_len; | |
641 | } | |
642 | ||
643 | i++; | |
644 | if (i == rx_ring->count) | |
645 | i = 0; | |
646 | next_buffer = &rx_ring->rx_buffer_info[i]; | |
647 | ||
648 | next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
649 | prefetch(next_rxd); | |
650 | ||
651 | cleaned_count++; | |
652 | if (staterr & IXGBE_RXD_STAT_EOP) { | |
653 | rx_ring->stats.packets++; | |
654 | rx_ring->stats.bytes += skb->len; | |
655 | } else { | |
656 | rx_buffer_info->skb = next_buffer->skb; | |
657 | rx_buffer_info->dma = next_buffer->dma; | |
658 | next_buffer->skb = skb; | |
762f4c57 | 659 | next_buffer->dma = 0; |
9a799d71 AK |
660 | adapter->non_eop_descs++; |
661 | goto next_desc; | |
662 | } | |
663 | ||
664 | if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) { | |
665 | dev_kfree_skb_irq(skb); | |
666 | goto next_desc; | |
667 | } | |
668 | ||
669 | ixgbe_rx_checksum(adapter, staterr, skb); | |
d2f4fbe2 AV |
670 | |
671 | /* probably a little skewed due to removing CRC */ | |
672 | total_rx_bytes += skb->len; | |
673 | total_rx_packets++; | |
674 | ||
74ce8dd2 | 675 | skb->protocol = eth_type_trans(skb, adapter->netdev); |
177db6ff | 676 | ixgbe_receive_skb(adapter, skb, staterr, rx_ring, rx_desc); |
9a799d71 AK |
677 | |
678 | next_desc: | |
679 | rx_desc->wb.upper.status_error = 0; | |
680 | ||
681 | /* return some buffers to hardware, one at a time is too slow */ | |
682 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
683 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
684 | cleaned_count = 0; | |
685 | } | |
686 | ||
687 | /* use prefetched values */ | |
688 | rx_desc = next_rxd; | |
689 | rx_buffer_info = next_buffer; | |
690 | ||
691 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
177db6ff MC |
692 | } |
693 | ||
694 | if (rx_ring->lro_used) { | |
695 | lro_flush_all(&rx_ring->lro_mgr); | |
696 | rx_ring->lro_used = false; | |
9a799d71 AK |
697 | } |
698 | ||
699 | rx_ring->next_to_clean = i; | |
700 | cleaned_count = IXGBE_DESC_UNUSED(rx_ring); | |
701 | ||
702 | if (cleaned_count) | |
703 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
704 | ||
f494e8fa AV |
705 | rx_ring->total_packets += total_rx_packets; |
706 | rx_ring->total_bytes += total_rx_bytes; | |
707 | adapter->net_stats.rx_bytes += total_rx_bytes; | |
708 | adapter->net_stats.rx_packets += total_rx_packets; | |
709 | ||
9a799d71 AK |
710 | return cleaned; |
711 | } | |
712 | ||
021230d4 | 713 | static int ixgbe_clean_rxonly(struct napi_struct *, int); |
9a799d71 AK |
714 | /** |
715 | * ixgbe_configure_msix - Configure MSI-X hardware | |
716 | * @adapter: board private structure | |
717 | * | |
718 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
719 | * interrupts. | |
720 | **/ | |
721 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
722 | { | |
021230d4 AV |
723 | struct ixgbe_q_vector *q_vector; |
724 | int i, j, q_vectors, v_idx, r_idx; | |
725 | u32 mask; | |
9a799d71 | 726 | |
021230d4 | 727 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 | 728 | |
021230d4 AV |
729 | /* Populate the IVAR table and set the ITR values to the |
730 | * corresponding register. | |
731 | */ | |
732 | for (v_idx = 0; v_idx < q_vectors; v_idx++) { | |
733 | q_vector = &adapter->q_vector[v_idx]; | |
734 | /* XXX for_each_bit(...) */ | |
735 | r_idx = find_first_bit(q_vector->rxr_idx, | |
b4617240 | 736 | adapter->num_rx_queues); |
021230d4 AV |
737 | |
738 | for (i = 0; i < q_vector->rxr_count; i++) { | |
739 | j = adapter->rx_ring[r_idx].reg_idx; | |
740 | ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(j), v_idx); | |
741 | r_idx = find_next_bit(q_vector->rxr_idx, | |
b4617240 PW |
742 | adapter->num_rx_queues, |
743 | r_idx + 1); | |
021230d4 AV |
744 | } |
745 | r_idx = find_first_bit(q_vector->txr_idx, | |
b4617240 | 746 | adapter->num_tx_queues); |
021230d4 AV |
747 | |
748 | for (i = 0; i < q_vector->txr_count; i++) { | |
749 | j = adapter->tx_ring[r_idx].reg_idx; | |
750 | ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(j), v_idx); | |
751 | r_idx = find_next_bit(q_vector->txr_idx, | |
b4617240 PW |
752 | adapter->num_tx_queues, |
753 | r_idx + 1); | |
021230d4 AV |
754 | } |
755 | ||
30efa5a3 | 756 | /* if this is a tx only vector halve the interrupt rate */ |
021230d4 | 757 | if (q_vector->txr_count && !q_vector->rxr_count) |
30efa5a3 | 758 | q_vector->eitr = (adapter->eitr_param >> 1); |
021230d4 | 759 | else |
30efa5a3 JB |
760 | /* rx only */ |
761 | q_vector->eitr = adapter->eitr_param; | |
021230d4 AV |
762 | |
763 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), | |
b4617240 | 764 | EITR_INTS_PER_SEC_TO_REG(q_vector->eitr)); |
9a799d71 AK |
765 | } |
766 | ||
021230d4 AV |
767 | ixgbe_set_ivar(adapter, IXGBE_IVAR_OTHER_CAUSES_INDEX, v_idx); |
768 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); | |
769 | ||
41fb9248 | 770 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 771 | mask = IXGBE_EIMS_ENABLE_MASK; |
41fb9248 | 772 | mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC); |
021230d4 | 773 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
774 | } |
775 | ||
f494e8fa AV |
776 | enum latency_range { |
777 | lowest_latency = 0, | |
778 | low_latency = 1, | |
779 | bulk_latency = 2, | |
780 | latency_invalid = 255 | |
781 | }; | |
782 | ||
783 | /** | |
784 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
785 | * @adapter: pointer to adapter | |
786 | * @eitr: eitr setting (ints per sec) to give last timeslice | |
787 | * @itr_setting: current throttle rate in ints/second | |
788 | * @packets: the number of packets during this measurement interval | |
789 | * @bytes: the number of bytes during this measurement interval | |
790 | * | |
791 | * Stores a new ITR value based on packets and byte | |
792 | * counts during the last interrupt. The advantage of per interrupt | |
793 | * computation is faster updates and more accurate ITR for the current | |
794 | * traffic pattern. Constants in this function were computed | |
795 | * based on theoretical maximum wire speed and thresholds were set based | |
796 | * on testing data as well as attempting to minimize response time | |
797 | * while increasing bulk throughput. | |
798 | * this functionality is controlled by the InterruptThrottleRate module | |
799 | * parameter (see ixgbe_param.c) | |
800 | **/ | |
801 | static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter, | |
b4617240 PW |
802 | u32 eitr, u8 itr_setting, |
803 | int packets, int bytes) | |
f494e8fa AV |
804 | { |
805 | unsigned int retval = itr_setting; | |
806 | u32 timepassed_us; | |
807 | u64 bytes_perint; | |
808 | ||
809 | if (packets == 0) | |
810 | goto update_itr_done; | |
811 | ||
812 | ||
813 | /* simple throttlerate management | |
814 | * 0-20MB/s lowest (100000 ints/s) | |
815 | * 20-100MB/s low (20000 ints/s) | |
816 | * 100-1249MB/s bulk (8000 ints/s) | |
817 | */ | |
818 | /* what was last interrupt timeslice? */ | |
819 | timepassed_us = 1000000/eitr; | |
820 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ | |
821 | ||
822 | switch (itr_setting) { | |
823 | case lowest_latency: | |
824 | if (bytes_perint > adapter->eitr_low) | |
825 | retval = low_latency; | |
826 | break; | |
827 | case low_latency: | |
828 | if (bytes_perint > adapter->eitr_high) | |
829 | retval = bulk_latency; | |
830 | else if (bytes_perint <= adapter->eitr_low) | |
831 | retval = lowest_latency; | |
832 | break; | |
833 | case bulk_latency: | |
834 | if (bytes_perint <= adapter->eitr_high) | |
835 | retval = low_latency; | |
836 | break; | |
837 | } | |
838 | ||
839 | update_itr_done: | |
840 | return retval; | |
841 | } | |
842 | ||
843 | static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector) | |
844 | { | |
845 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
846 | struct ixgbe_hw *hw = &adapter->hw; | |
847 | u32 new_itr; | |
848 | u8 current_itr, ret_itr; | |
849 | int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) / | |
b4617240 | 850 | sizeof(struct ixgbe_q_vector); |
f494e8fa AV |
851 | struct ixgbe_ring *rx_ring, *tx_ring; |
852 | ||
853 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
854 | for (i = 0; i < q_vector->txr_count; i++) { | |
855 | tx_ring = &(adapter->tx_ring[r_idx]); | |
856 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, | |
b4617240 PW |
857 | q_vector->tx_itr, |
858 | tx_ring->total_packets, | |
859 | tx_ring->total_bytes); | |
f494e8fa AV |
860 | /* if the result for this queue would decrease interrupt |
861 | * rate for this vector then use that result */ | |
30efa5a3 | 862 | q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ? |
b4617240 | 863 | q_vector->tx_itr - 1 : ret_itr); |
f494e8fa | 864 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 865 | r_idx + 1); |
f494e8fa AV |
866 | } |
867 | ||
868 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
869 | for (i = 0; i < q_vector->rxr_count; i++) { | |
870 | rx_ring = &(adapter->rx_ring[r_idx]); | |
871 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, | |
b4617240 PW |
872 | q_vector->rx_itr, |
873 | rx_ring->total_packets, | |
874 | rx_ring->total_bytes); | |
f494e8fa AV |
875 | /* if the result for this queue would decrease interrupt |
876 | * rate for this vector then use that result */ | |
30efa5a3 | 877 | q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ? |
b4617240 | 878 | q_vector->rx_itr - 1 : ret_itr); |
f494e8fa | 879 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
b4617240 | 880 | r_idx + 1); |
f494e8fa AV |
881 | } |
882 | ||
30efa5a3 | 883 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
884 | |
885 | switch (current_itr) { | |
886 | /* counts and packets in update_itr are dependent on these numbers */ | |
887 | case lowest_latency: | |
888 | new_itr = 100000; | |
889 | break; | |
890 | case low_latency: | |
891 | new_itr = 20000; /* aka hwitr = ~200 */ | |
892 | break; | |
893 | case bulk_latency: | |
894 | default: | |
895 | new_itr = 8000; | |
896 | break; | |
897 | } | |
898 | ||
899 | if (new_itr != q_vector->eitr) { | |
900 | u32 itr_reg; | |
901 | /* do an exponential smoothing */ | |
902 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
903 | q_vector->eitr = new_itr; | |
904 | itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr); | |
905 | /* must write high and low 16 bits to reset counter */ | |
906 | DPRINTK(TX_ERR, DEBUG, "writing eitr(%d): %08X\n", v_idx, | |
b4617240 | 907 | itr_reg); |
f494e8fa AV |
908 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg | (itr_reg)<<16); |
909 | } | |
910 | ||
911 | return; | |
912 | } | |
913 | ||
0befdb3e JB |
914 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
915 | { | |
916 | struct ixgbe_hw *hw = &adapter->hw; | |
917 | ||
918 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
919 | (eicr & IXGBE_EICR_GPI_SDP1)) { | |
920 | DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n"); | |
921 | /* write to clear the interrupt */ | |
922 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
923 | } | |
924 | } | |
cf8280ee JB |
925 | |
926 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) | |
927 | { | |
928 | struct ixgbe_hw *hw = &adapter->hw; | |
929 | ||
930 | adapter->lsc_int++; | |
931 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
932 | adapter->link_check_timeout = jiffies; | |
933 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
934 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
935 | schedule_work(&adapter->watchdog_task); | |
936 | } | |
937 | } | |
938 | ||
9a799d71 AK |
939 | static irqreturn_t ixgbe_msix_lsc(int irq, void *data) |
940 | { | |
941 | struct net_device *netdev = data; | |
942 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
943 | struct ixgbe_hw *hw = &adapter->hw; | |
944 | u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); | |
945 | ||
cf8280ee JB |
946 | if (eicr & IXGBE_EICR_LSC) |
947 | ixgbe_check_lsc(adapter); | |
d4f80882 | 948 | |
0befdb3e JB |
949 | ixgbe_check_fan_failure(adapter, eicr); |
950 | ||
d4f80882 AV |
951 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
952 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER); | |
9a799d71 AK |
953 | |
954 | return IRQ_HANDLED; | |
955 | } | |
956 | ||
957 | static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data) | |
958 | { | |
021230d4 AV |
959 | struct ixgbe_q_vector *q_vector = data; |
960 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 961 | struct ixgbe_ring *tx_ring; |
021230d4 AV |
962 | int i, r_idx; |
963 | ||
964 | if (!q_vector->txr_count) | |
965 | return IRQ_HANDLED; | |
966 | ||
967 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
968 | for (i = 0; i < q_vector->txr_count; i++) { | |
3a581073 | 969 | tx_ring = &(adapter->tx_ring[r_idx]); |
5dd2d332 | 970 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 971 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
3a581073 | 972 | ixgbe_update_tx_dca(adapter, tx_ring); |
bd0362dd | 973 | #endif |
3a581073 JB |
974 | tx_ring->total_bytes = 0; |
975 | tx_ring->total_packets = 0; | |
976 | ixgbe_clean_tx_irq(adapter, tx_ring); | |
021230d4 | 977 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 978 | r_idx + 1); |
021230d4 | 979 | } |
9a799d71 | 980 | |
9a799d71 AK |
981 | return IRQ_HANDLED; |
982 | } | |
983 | ||
021230d4 AV |
984 | /** |
985 | * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues) | |
986 | * @irq: unused | |
987 | * @data: pointer to our q_vector struct for this interrupt vector | |
988 | **/ | |
9a799d71 AK |
989 | static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data) |
990 | { | |
021230d4 AV |
991 | struct ixgbe_q_vector *q_vector = data; |
992 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 993 | struct ixgbe_ring *rx_ring; |
021230d4 | 994 | int r_idx; |
30efa5a3 | 995 | int i; |
021230d4 AV |
996 | |
997 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
30efa5a3 JB |
998 | for (i = 0; i < q_vector->rxr_count; i++) { |
999 | rx_ring = &(adapter->rx_ring[r_idx]); | |
1000 | rx_ring->total_bytes = 0; | |
1001 | rx_ring->total_packets = 0; | |
1002 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1003 | r_idx + 1); | |
1004 | } | |
1005 | ||
021230d4 AV |
1006 | if (!q_vector->rxr_count) |
1007 | return IRQ_HANDLED; | |
1008 | ||
30efa5a3 | 1009 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
3a581073 | 1010 | rx_ring = &(adapter->rx_ring[r_idx]); |
021230d4 | 1011 | /* disable interrupts on this vector only */ |
3a581073 | 1012 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx); |
021230d4 AV |
1013 | netif_rx_schedule(adapter->netdev, &q_vector->napi); |
1014 | ||
1015 | return IRQ_HANDLED; | |
1016 | } | |
1017 | ||
1018 | static irqreturn_t ixgbe_msix_clean_many(int irq, void *data) | |
1019 | { | |
1020 | ixgbe_msix_clean_rx(irq, data); | |
1021 | ixgbe_msix_clean_tx(irq, data); | |
9a799d71 | 1022 | |
9a799d71 AK |
1023 | return IRQ_HANDLED; |
1024 | } | |
1025 | ||
021230d4 AV |
1026 | /** |
1027 | * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine | |
1028 | * @napi: napi struct with our devices info in it | |
1029 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1030 | * | |
f0848276 JB |
1031 | * This function is optimized for cleaning one queue only on a single |
1032 | * q_vector!!! | |
021230d4 | 1033 | **/ |
9a799d71 AK |
1034 | static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget) |
1035 | { | |
021230d4 | 1036 | struct ixgbe_q_vector *q_vector = |
b4617240 | 1037 | container_of(napi, struct ixgbe_q_vector, napi); |
021230d4 | 1038 | struct ixgbe_adapter *adapter = q_vector->adapter; |
f0848276 | 1039 | struct ixgbe_ring *rx_ring = NULL; |
9a799d71 | 1040 | int work_done = 0; |
021230d4 | 1041 | long r_idx; |
9a799d71 | 1042 | |
021230d4 | 1043 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
3a581073 | 1044 | rx_ring = &(adapter->rx_ring[r_idx]); |
5dd2d332 | 1045 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 1046 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
3a581073 | 1047 | ixgbe_update_rx_dca(adapter, rx_ring); |
bd0362dd | 1048 | #endif |
9a799d71 | 1049 | |
3a581073 | 1050 | ixgbe_clean_rx_irq(adapter, rx_ring, &work_done, budget); |
9a799d71 | 1051 | |
021230d4 AV |
1052 | /* If all Rx work done, exit the polling mode */ |
1053 | if (work_done < budget) { | |
1054 | netif_rx_complete(adapter->netdev, napi); | |
30efa5a3 | 1055 | if (adapter->itr_setting & 3) |
f494e8fa | 1056 | ixgbe_set_itr_msix(q_vector); |
9a799d71 | 1057 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
3a581073 | 1058 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx); |
9a799d71 AK |
1059 | } |
1060 | ||
1061 | return work_done; | |
1062 | } | |
1063 | ||
f0848276 JB |
1064 | /** |
1065 | * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine | |
1066 | * @napi: napi struct with our devices info in it | |
1067 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1068 | * | |
1069 | * This function will clean more than one rx queue associated with a | |
1070 | * q_vector. | |
1071 | **/ | |
1072 | static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget) | |
1073 | { | |
1074 | struct ixgbe_q_vector *q_vector = | |
1075 | container_of(napi, struct ixgbe_q_vector, napi); | |
1076 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
f0848276 JB |
1077 | struct ixgbe_ring *rx_ring = NULL; |
1078 | int work_done = 0, i; | |
1079 | long r_idx; | |
1080 | u16 enable_mask = 0; | |
1081 | ||
1082 | /* attempt to distribute budget to each queue fairly, but don't allow | |
1083 | * the budget to go below 1 because we'll exit polling */ | |
1084 | budget /= (q_vector->rxr_count ?: 1); | |
1085 | budget = max(budget, 1); | |
1086 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1087 | for (i = 0; i < q_vector->rxr_count; i++) { | |
1088 | rx_ring = &(adapter->rx_ring[r_idx]); | |
5dd2d332 | 1089 | #ifdef CONFIG_IXGBE_DCA |
f0848276 JB |
1090 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
1091 | ixgbe_update_rx_dca(adapter, rx_ring); | |
1092 | #endif | |
1093 | ixgbe_clean_rx_irq(adapter, rx_ring, &work_done, budget); | |
1094 | enable_mask |= rx_ring->v_idx; | |
1095 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1096 | r_idx + 1); | |
1097 | } | |
1098 | ||
1099 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1100 | rx_ring = &(adapter->rx_ring[r_idx]); | |
1101 | /* If all Rx work done, exit the polling mode */ | |
7f821875 | 1102 | if (work_done < budget) { |
74ce8dd2 | 1103 | netif_rx_complete(adapter->netdev, napi); |
f0848276 JB |
1104 | if (adapter->itr_setting & 3) |
1105 | ixgbe_set_itr_msix(q_vector); | |
1106 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
1107 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask); | |
1108 | return 0; | |
1109 | } | |
1110 | ||
1111 | return work_done; | |
1112 | } | |
021230d4 | 1113 | static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx, |
b4617240 | 1114 | int r_idx) |
021230d4 AV |
1115 | { |
1116 | a->q_vector[v_idx].adapter = a; | |
1117 | set_bit(r_idx, a->q_vector[v_idx].rxr_idx); | |
1118 | a->q_vector[v_idx].rxr_count++; | |
1119 | a->rx_ring[r_idx].v_idx = 1 << v_idx; | |
1120 | } | |
1121 | ||
1122 | static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx, | |
b4617240 | 1123 | int r_idx) |
021230d4 AV |
1124 | { |
1125 | a->q_vector[v_idx].adapter = a; | |
1126 | set_bit(r_idx, a->q_vector[v_idx].txr_idx); | |
1127 | a->q_vector[v_idx].txr_count++; | |
1128 | a->tx_ring[r_idx].v_idx = 1 << v_idx; | |
1129 | } | |
1130 | ||
9a799d71 | 1131 | /** |
021230d4 AV |
1132 | * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors |
1133 | * @adapter: board private structure to initialize | |
1134 | * @vectors: allotted vector count for descriptor rings | |
9a799d71 | 1135 | * |
021230d4 AV |
1136 | * This function maps descriptor rings to the queue-specific vectors |
1137 | * we were allotted through the MSI-X enabling code. Ideally, we'd have | |
1138 | * one vector per ring/queue, but on a constrained vector budget, we | |
1139 | * group the rings as "efficiently" as possible. You would add new | |
1140 | * mapping configurations in here. | |
9a799d71 | 1141 | **/ |
021230d4 | 1142 | static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 1143 | int vectors) |
021230d4 AV |
1144 | { |
1145 | int v_start = 0; | |
1146 | int rxr_idx = 0, txr_idx = 0; | |
1147 | int rxr_remaining = adapter->num_rx_queues; | |
1148 | int txr_remaining = adapter->num_tx_queues; | |
1149 | int i, j; | |
1150 | int rqpv, tqpv; | |
1151 | int err = 0; | |
1152 | ||
1153 | /* No mapping required if MSI-X is disabled. */ | |
1154 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
1155 | goto out; | |
9a799d71 | 1156 | |
021230d4 AV |
1157 | /* |
1158 | * The ideal configuration... | |
1159 | * We have enough vectors to map one per queue. | |
1160 | */ | |
1161 | if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) { | |
1162 | for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++) | |
1163 | map_vector_to_rxq(adapter, v_start, rxr_idx); | |
9a799d71 | 1164 | |
021230d4 AV |
1165 | for (; txr_idx < txr_remaining; v_start++, txr_idx++) |
1166 | map_vector_to_txq(adapter, v_start, txr_idx); | |
9a799d71 | 1167 | |
9a799d71 | 1168 | goto out; |
021230d4 | 1169 | } |
9a799d71 | 1170 | |
021230d4 AV |
1171 | /* |
1172 | * If we don't have enough vectors for a 1-to-1 | |
1173 | * mapping, we'll have to group them so there are | |
1174 | * multiple queues per vector. | |
1175 | */ | |
1176 | /* Re-adjusting *qpv takes care of the remainder. */ | |
1177 | for (i = v_start; i < vectors; i++) { | |
1178 | rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i); | |
1179 | for (j = 0; j < rqpv; j++) { | |
1180 | map_vector_to_rxq(adapter, i, rxr_idx); | |
1181 | rxr_idx++; | |
1182 | rxr_remaining--; | |
1183 | } | |
1184 | } | |
1185 | for (i = v_start; i < vectors; i++) { | |
1186 | tqpv = DIV_ROUND_UP(txr_remaining, vectors - i); | |
1187 | for (j = 0; j < tqpv; j++) { | |
1188 | map_vector_to_txq(adapter, i, txr_idx); | |
1189 | txr_idx++; | |
1190 | txr_remaining--; | |
9a799d71 | 1191 | } |
9a799d71 AK |
1192 | } |
1193 | ||
021230d4 AV |
1194 | out: |
1195 | return err; | |
1196 | } | |
1197 | ||
1198 | /** | |
1199 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
1200 | * @adapter: board private structure | |
1201 | * | |
1202 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
1203 | * interrupts from the kernel. | |
1204 | **/ | |
1205 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
1206 | { | |
1207 | struct net_device *netdev = adapter->netdev; | |
1208 | irqreturn_t (*handler)(int, void *); | |
1209 | int i, vector, q_vectors, err; | |
1210 | ||
1211 | /* Decrement for Other and TCP Timer vectors */ | |
1212 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1213 | ||
1214 | /* Map the Tx/Rx rings to the vectors we were allotted. */ | |
1215 | err = ixgbe_map_rings_to_vectors(adapter, q_vectors); | |
1216 | if (err) | |
1217 | goto out; | |
1218 | ||
1219 | #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \ | |
b4617240 PW |
1220 | (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \ |
1221 | &ixgbe_msix_clean_many) | |
021230d4 AV |
1222 | for (vector = 0; vector < q_vectors; vector++) { |
1223 | handler = SET_HANDLER(&adapter->q_vector[vector]); | |
1224 | sprintf(adapter->name[vector], "%s:v%d-%s", | |
b4617240 PW |
1225 | netdev->name, vector, |
1226 | (handler == &ixgbe_msix_clean_rx) ? "Rx" : | |
1227 | ((handler == &ixgbe_msix_clean_tx) ? "Tx" : "TxRx")); | |
021230d4 | 1228 | err = request_irq(adapter->msix_entries[vector].vector, |
b4617240 PW |
1229 | handler, 0, adapter->name[vector], |
1230 | &(adapter->q_vector[vector])); | |
9a799d71 AK |
1231 | if (err) { |
1232 | DPRINTK(PROBE, ERR, | |
b4617240 PW |
1233 | "request_irq failed for MSIX interrupt " |
1234 | "Error: %d\n", err); | |
021230d4 | 1235 | goto free_queue_irqs; |
9a799d71 | 1236 | } |
9a799d71 AK |
1237 | } |
1238 | ||
021230d4 AV |
1239 | sprintf(adapter->name[vector], "%s:lsc", netdev->name); |
1240 | err = request_irq(adapter->msix_entries[vector].vector, | |
b4617240 | 1241 | &ixgbe_msix_lsc, 0, adapter->name[vector], netdev); |
9a799d71 AK |
1242 | if (err) { |
1243 | DPRINTK(PROBE, ERR, | |
1244 | "request_irq for msix_lsc failed: %d\n", err); | |
021230d4 | 1245 | goto free_queue_irqs; |
9a799d71 AK |
1246 | } |
1247 | ||
9a799d71 AK |
1248 | return 0; |
1249 | ||
021230d4 AV |
1250 | free_queue_irqs: |
1251 | for (i = vector - 1; i >= 0; i--) | |
1252 | free_irq(adapter->msix_entries[--vector].vector, | |
b4617240 | 1253 | &(adapter->q_vector[i])); |
021230d4 AV |
1254 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
1255 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
1256 | kfree(adapter->msix_entries); |
1257 | adapter->msix_entries = NULL; | |
021230d4 | 1258 | out: |
9a799d71 AK |
1259 | return err; |
1260 | } | |
1261 | ||
f494e8fa AV |
1262 | static void ixgbe_set_itr(struct ixgbe_adapter *adapter) |
1263 | { | |
1264 | struct ixgbe_hw *hw = &adapter->hw; | |
1265 | struct ixgbe_q_vector *q_vector = adapter->q_vector; | |
1266 | u8 current_itr; | |
1267 | u32 new_itr = q_vector->eitr; | |
1268 | struct ixgbe_ring *rx_ring = &adapter->rx_ring[0]; | |
1269 | struct ixgbe_ring *tx_ring = &adapter->tx_ring[0]; | |
1270 | ||
30efa5a3 | 1271 | q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
1272 | q_vector->tx_itr, |
1273 | tx_ring->total_packets, | |
1274 | tx_ring->total_bytes); | |
30efa5a3 | 1275 | q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
1276 | q_vector->rx_itr, |
1277 | rx_ring->total_packets, | |
1278 | rx_ring->total_bytes); | |
f494e8fa | 1279 | |
30efa5a3 | 1280 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1281 | |
1282 | switch (current_itr) { | |
1283 | /* counts and packets in update_itr are dependent on these numbers */ | |
1284 | case lowest_latency: | |
1285 | new_itr = 100000; | |
1286 | break; | |
1287 | case low_latency: | |
1288 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1289 | break; | |
1290 | case bulk_latency: | |
1291 | new_itr = 8000; | |
1292 | break; | |
1293 | default: | |
1294 | break; | |
1295 | } | |
1296 | ||
1297 | if (new_itr != q_vector->eitr) { | |
1298 | u32 itr_reg; | |
1299 | /* do an exponential smoothing */ | |
1300 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
1301 | q_vector->eitr = new_itr; | |
1302 | itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr); | |
1303 | /* must write high and low 16 bits to reset counter */ | |
1304 | IXGBE_WRITE_REG(hw, IXGBE_EITR(0), itr_reg | (itr_reg)<<16); | |
1305 | } | |
1306 | ||
1307 | return; | |
1308 | } | |
1309 | ||
79aefa45 AD |
1310 | /** |
1311 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
1312 | * @adapter: board private structure | |
1313 | **/ | |
1314 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
1315 | { | |
1316 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); | |
1317 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
1318 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
1319 | int i; | |
1320 | for (i = 0; i < adapter->num_msix_vectors; i++) | |
1321 | synchronize_irq(adapter->msix_entries[i].vector); | |
1322 | } else { | |
1323 | synchronize_irq(adapter->pdev->irq); | |
1324 | } | |
1325 | } | |
1326 | ||
1327 | /** | |
1328 | * ixgbe_irq_enable - Enable default interrupt generation settings | |
1329 | * @adapter: board private structure | |
1330 | **/ | |
1331 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter) | |
1332 | { | |
1333 | u32 mask; | |
1334 | mask = IXGBE_EIMS_ENABLE_MASK; | |
6ab33d51 DM |
1335 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
1336 | mask |= IXGBE_EIMS_GPI_SDP1; | |
79aefa45 AD |
1337 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
1338 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
1339 | } | |
021230d4 | 1340 | |
9a799d71 | 1341 | /** |
021230d4 | 1342 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
1343 | * @irq: interrupt number |
1344 | * @data: pointer to a network interface device structure | |
1345 | * @pt_regs: CPU registers structure | |
1346 | **/ | |
1347 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
1348 | { | |
1349 | struct net_device *netdev = data; | |
1350 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1351 | struct ixgbe_hw *hw = &adapter->hw; | |
1352 | u32 eicr; | |
1353 | ||
021230d4 AV |
1354 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
1355 | * therefore no explict interrupt disable is necessary */ | |
1356 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); | |
f47cf66e JB |
1357 | if (!eicr) { |
1358 | /* shared interrupt alert! | |
1359 | * make sure interrupts are enabled because the read will | |
1360 | * have disabled interrupts due to EIAM */ | |
1361 | ixgbe_irq_enable(adapter); | |
9a799d71 | 1362 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 1363 | } |
9a799d71 | 1364 | |
cf8280ee JB |
1365 | if (eicr & IXGBE_EICR_LSC) |
1366 | ixgbe_check_lsc(adapter); | |
021230d4 | 1367 | |
0befdb3e JB |
1368 | ixgbe_check_fan_failure(adapter, eicr); |
1369 | ||
021230d4 | 1370 | if (netif_rx_schedule_prep(netdev, &adapter->q_vector[0].napi)) { |
f494e8fa AV |
1371 | adapter->tx_ring[0].total_packets = 0; |
1372 | adapter->tx_ring[0].total_bytes = 0; | |
1373 | adapter->rx_ring[0].total_packets = 0; | |
1374 | adapter->rx_ring[0].total_bytes = 0; | |
021230d4 AV |
1375 | /* would disable interrupts here but EIAM disabled it */ |
1376 | __netif_rx_schedule(netdev, &adapter->q_vector[0].napi); | |
9a799d71 AK |
1377 | } |
1378 | ||
1379 | return IRQ_HANDLED; | |
1380 | } | |
1381 | ||
021230d4 AV |
1382 | static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter) |
1383 | { | |
1384 | int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1385 | ||
1386 | for (i = 0; i < q_vectors; i++) { | |
1387 | struct ixgbe_q_vector *q_vector = &adapter->q_vector[i]; | |
1388 | bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES); | |
1389 | bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES); | |
1390 | q_vector->rxr_count = 0; | |
1391 | q_vector->txr_count = 0; | |
1392 | } | |
1393 | } | |
1394 | ||
9a799d71 AK |
1395 | /** |
1396 | * ixgbe_request_irq - initialize interrupts | |
1397 | * @adapter: board private structure | |
1398 | * | |
1399 | * Attempts to configure interrupts using the best available | |
1400 | * capabilities of the hardware and kernel. | |
1401 | **/ | |
021230d4 | 1402 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
1403 | { |
1404 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 1405 | int err; |
9a799d71 | 1406 | |
021230d4 AV |
1407 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
1408 | err = ixgbe_request_msix_irqs(adapter); | |
1409 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
1410 | err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0, | |
b4617240 | 1411 | netdev->name, netdev); |
021230d4 AV |
1412 | } else { |
1413 | err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED, | |
b4617240 | 1414 | netdev->name, netdev); |
9a799d71 AK |
1415 | } |
1416 | ||
9a799d71 AK |
1417 | if (err) |
1418 | DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err); | |
1419 | ||
9a799d71 AK |
1420 | return err; |
1421 | } | |
1422 | ||
1423 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
1424 | { | |
1425 | struct net_device *netdev = adapter->netdev; | |
1426 | ||
1427 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
021230d4 | 1428 | int i, q_vectors; |
9a799d71 | 1429 | |
021230d4 AV |
1430 | q_vectors = adapter->num_msix_vectors; |
1431 | ||
1432 | i = q_vectors - 1; | |
9a799d71 | 1433 | free_irq(adapter->msix_entries[i].vector, netdev); |
9a799d71 | 1434 | |
021230d4 AV |
1435 | i--; |
1436 | for (; i >= 0; i--) { | |
1437 | free_irq(adapter->msix_entries[i].vector, | |
b4617240 | 1438 | &(adapter->q_vector[i])); |
021230d4 AV |
1439 | } |
1440 | ||
1441 | ixgbe_reset_q_vectors(adapter); | |
1442 | } else { | |
1443 | free_irq(adapter->pdev->irq, netdev); | |
9a799d71 AK |
1444 | } |
1445 | } | |
1446 | ||
9a799d71 AK |
1447 | /** |
1448 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
1449 | * | |
1450 | **/ | |
1451 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
1452 | { | |
9a799d71 AK |
1453 | struct ixgbe_hw *hw = &adapter->hw; |
1454 | ||
021230d4 | 1455 | IXGBE_WRITE_REG(hw, IXGBE_EITR(0), |
30efa5a3 | 1456 | EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param)); |
9a799d71 AK |
1457 | |
1458 | ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(0), 0); | |
021230d4 AV |
1459 | ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(0), 0); |
1460 | ||
1461 | map_vector_to_rxq(adapter, 0, 0); | |
1462 | map_vector_to_txq(adapter, 0, 0); | |
1463 | ||
1464 | DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n"); | |
9a799d71 AK |
1465 | } |
1466 | ||
1467 | /** | |
3a581073 | 1468 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
1469 | * @adapter: board private structure |
1470 | * | |
1471 | * Configure the Tx unit of the MAC after a reset. | |
1472 | **/ | |
1473 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
1474 | { | |
e01c31a5 | 1475 | u64 tdba, tdwba; |
9a799d71 | 1476 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 1477 | u32 i, j, tdlen, txctrl; |
9a799d71 AK |
1478 | |
1479 | /* Setup the HW Tx Head and Tail descriptor pointers */ | |
1480 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
e01c31a5 JB |
1481 | struct ixgbe_ring *ring = &adapter->tx_ring[i]; |
1482 | j = ring->reg_idx; | |
1483 | tdba = ring->dma; | |
1484 | tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc); | |
021230d4 | 1485 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j), |
e01c31a5 | 1486 | (tdba & DMA_32BIT_MASK)); |
021230d4 | 1487 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32)); |
e01c31a5 JB |
1488 | tdwba = ring->dma + |
1489 | (ring->count * sizeof(union ixgbe_adv_tx_desc)); | |
1490 | tdwba |= IXGBE_TDWBAL_HEAD_WB_ENABLE; | |
1491 | IXGBE_WRITE_REG(hw, IXGBE_TDWBAL(j), tdwba & DMA_32BIT_MASK); | |
1492 | IXGBE_WRITE_REG(hw, IXGBE_TDWBAH(j), (tdwba >> 32)); | |
021230d4 AV |
1493 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen); |
1494 | IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0); | |
1495 | IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0); | |
1496 | adapter->tx_ring[i].head = IXGBE_TDH(j); | |
1497 | adapter->tx_ring[i].tail = IXGBE_TDT(j); | |
1498 | /* Disable Tx Head Writeback RO bit, since this hoses | |
1499 | * bookkeeping if things aren't delivered in order. | |
1500 | */ | |
e01c31a5 | 1501 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j)); |
021230d4 | 1502 | txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; |
e01c31a5 | 1503 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl); |
9a799d71 | 1504 | } |
9a799d71 AK |
1505 | } |
1506 | ||
cc41ac7c JB |
1507 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
1508 | ||
1509 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index) | |
1510 | { | |
1511 | struct ixgbe_ring *rx_ring; | |
1512 | u32 srrctl; | |
1513 | int queue0; | |
3be1adfb AD |
1514 | unsigned long mask; |
1515 | ||
1516 | /* program one srrctl register per VMDq index */ | |
1517 | if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) { | |
1518 | long shift, len; | |
1519 | mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask; | |
1520 | len = sizeof(adapter->ring_feature[RING_F_VMDQ].mask) * 8; | |
1521 | shift = find_first_bit(&mask, len); | |
1522 | queue0 = index & mask; | |
1523 | index = (index & mask) >> shift; | |
1524 | /* program one srrctl per RSS queue since RDRXCTL.MVMEN is enabled */ | |
cc41ac7c | 1525 | } else { |
3be1adfb AD |
1526 | mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask; |
1527 | queue0 = index & mask; | |
1528 | index = index & mask; | |
cc41ac7c | 1529 | } |
3be1adfb | 1530 | |
cc41ac7c JB |
1531 | rx_ring = &adapter->rx_ring[queue0]; |
1532 | ||
1533 | srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index)); | |
1534 | ||
1535 | srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; | |
1536 | srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; | |
1537 | ||
1538 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
1539 | srrctl |= IXGBE_RXBUFFER_2048 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
1540 | srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; | |
1541 | srrctl |= ((IXGBE_RX_HDR_SIZE << | |
b4617240 PW |
1542 | IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & |
1543 | IXGBE_SRRCTL_BSIZEHDR_MASK); | |
cc41ac7c JB |
1544 | } else { |
1545 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; | |
1546 | ||
1547 | if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE) | |
1548 | srrctl |= IXGBE_RXBUFFER_2048 >> | |
1549 | IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
1550 | else | |
1551 | srrctl |= rx_ring->rx_buf_len >> | |
1552 | IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
1553 | } | |
1554 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl); | |
1555 | } | |
9a799d71 | 1556 | |
177db6ff MC |
1557 | /** |
1558 | * ixgbe_get_skb_hdr - helper function for LRO header processing | |
1559 | * @skb: pointer to sk_buff to be added to LRO packet | |
b4617240 | 1560 | * @iphdr: pointer to ip header structure |
177db6ff MC |
1561 | * @tcph: pointer to tcp header structure |
1562 | * @hdr_flags: pointer to header flags | |
1563 | * @priv: private data | |
1564 | **/ | |
1565 | static int ixgbe_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph, | |
1566 | u64 *hdr_flags, void *priv) | |
1567 | { | |
1568 | union ixgbe_adv_rx_desc *rx_desc = priv; | |
1569 | ||
1570 | /* Verify that this is a valid IPv4 TCP packet */ | |
e9990a9c JB |
1571 | if (!((ixgbe_get_pkt_info(rx_desc) & IXGBE_RXDADV_PKTTYPE_IPV4) && |
1572 | (ixgbe_get_pkt_info(rx_desc) & IXGBE_RXDADV_PKTTYPE_TCP))) | |
177db6ff MC |
1573 | return -1; |
1574 | ||
1575 | /* Set network headers */ | |
1576 | skb_reset_network_header(skb); | |
1577 | skb_set_transport_header(skb, ip_hdrlen(skb)); | |
1578 | *iphdr = ip_hdr(skb); | |
1579 | *tcph = tcp_hdr(skb); | |
1580 | *hdr_flags = LRO_IPV4 | LRO_TCP; | |
1581 | return 0; | |
1582 | } | |
1583 | ||
cc41ac7c | 1584 | #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \ |
b4617240 | 1585 | (((S) & (PAGE_SIZE - 1)) ? 1 : 0)) |
cc41ac7c | 1586 | |
9a799d71 | 1587 | /** |
3a581073 | 1588 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset |
9a799d71 AK |
1589 | * @adapter: board private structure |
1590 | * | |
1591 | * Configure the Rx unit of the MAC after a reset. | |
1592 | **/ | |
1593 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
1594 | { | |
1595 | u64 rdba; | |
1596 | struct ixgbe_hw *hw = &adapter->hw; | |
1597 | struct net_device *netdev = adapter->netdev; | |
1598 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
021230d4 | 1599 | int i, j; |
9a799d71 | 1600 | u32 rdlen, rxctrl, rxcsum; |
7c6e0a43 JB |
1601 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, |
1602 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, | |
1603 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
9a799d71 | 1604 | u32 fctrl, hlreg0; |
9a799d71 | 1605 | u32 pages; |
cc41ac7c JB |
1606 | u32 reta = 0, mrqc; |
1607 | u32 rdrxctl; | |
7c6e0a43 | 1608 | int rx_buf_len; |
9a799d71 AK |
1609 | |
1610 | /* Decide whether to use packet split mode or not */ | |
762f4c57 | 1611 | adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED; |
9a799d71 AK |
1612 | |
1613 | /* Set the RX buffer length according to the mode */ | |
1614 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 | 1615 | rx_buf_len = IXGBE_RX_HDR_SIZE; |
9a799d71 AK |
1616 | } else { |
1617 | if (netdev->mtu <= ETH_DATA_LEN) | |
7c6e0a43 | 1618 | rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
9a799d71 | 1619 | else |
7c6e0a43 | 1620 | rx_buf_len = ALIGN(max_frame, 1024); |
9a799d71 AK |
1621 | } |
1622 | ||
1623 | fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL); | |
1624 | fctrl |= IXGBE_FCTRL_BAM; | |
021230d4 | 1625 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ |
9a799d71 AK |
1626 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl); |
1627 | ||
1628 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |
1629 | if (adapter->netdev->mtu <= ETH_DATA_LEN) | |
1630 | hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; | |
1631 | else | |
1632 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
1633 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); | |
1634 | ||
1635 | pages = PAGE_USE_COUNT(adapter->netdev->mtu); | |
1636 | ||
9a799d71 AK |
1637 | rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc); |
1638 | /* disable receives while setting up the descriptors */ | |
1639 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
1640 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
1641 | ||
1642 | /* Setup the HW Rx Head and Tail Descriptor Pointers and | |
1643 | * the Base and Length of the Rx Descriptor Ring */ | |
1644 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1645 | rdba = adapter->rx_ring[i].dma; | |
7c6e0a43 JB |
1646 | j = adapter->rx_ring[i].reg_idx; |
1647 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK)); | |
1648 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32)); | |
1649 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen); | |
1650 | IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0); | |
1651 | IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0); | |
1652 | adapter->rx_ring[i].head = IXGBE_RDH(j); | |
1653 | adapter->rx_ring[i].tail = IXGBE_RDT(j); | |
1654 | adapter->rx_ring[i].rx_buf_len = rx_buf_len; | |
e9990a9c JB |
1655 | /* Intitial LRO Settings */ |
1656 | adapter->rx_ring[i].lro_mgr.max_aggr = IXGBE_MAX_LRO_AGGREGATE; | |
1657 | adapter->rx_ring[i].lro_mgr.max_desc = IXGBE_MAX_LRO_DESCRIPTORS; | |
1658 | adapter->rx_ring[i].lro_mgr.get_skb_header = ixgbe_get_skb_hdr; | |
1659 | adapter->rx_ring[i].lro_mgr.features = LRO_F_EXTRACT_VLAN_ID; | |
1660 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) | |
1661 | adapter->rx_ring[i].lro_mgr.features |= LRO_F_NAPI; | |
1662 | adapter->rx_ring[i].lro_mgr.dev = adapter->netdev; | |
1663 | adapter->rx_ring[i].lro_mgr.ip_summed = CHECKSUM_UNNECESSARY; | |
1664 | adapter->rx_ring[i].lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY; | |
cc41ac7c JB |
1665 | |
1666 | ixgbe_configure_srrctl(adapter, j); | |
9a799d71 AK |
1667 | } |
1668 | ||
cc41ac7c JB |
1669 | /* |
1670 | * For VMDq support of different descriptor types or | |
1671 | * buffer sizes through the use of multiple SRRCTL | |
1672 | * registers, RDRXCTL.MVMEN must be set to 1 | |
1673 | * | |
1674 | * also, the manual doesn't mention it clearly but DCA hints | |
1675 | * will only use queue 0's tags unless this bit is set. Side | |
1676 | * effects of setting this bit are only that SRRCTL must be | |
1677 | * fully programmed [0..15] | |
1678 | */ | |
2f90b865 AD |
1679 | if (adapter->flags & |
1680 | (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_VMDQ_ENABLED)) { | |
1681 | rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
1682 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
1683 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
1684 | } | |
177db6ff | 1685 | |
021230d4 | 1686 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { |
9a799d71 | 1687 | /* Fill out redirection table */ |
021230d4 AV |
1688 | for (i = 0, j = 0; i < 128; i++, j++) { |
1689 | if (j == adapter->ring_feature[RING_F_RSS].indices) | |
1690 | j = 0; | |
1691 | /* reta = 4-byte sliding window of | |
1692 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
1693 | reta = (reta << 8) | (j * 0x11); | |
1694 | if ((i & 3) == 3) | |
1695 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
9a799d71 AK |
1696 | } |
1697 | ||
1698 | /* Fill out hash function seeds */ | |
1699 | for (i = 0; i < 10; i++) | |
7c6e0a43 | 1700 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); |
9a799d71 AK |
1701 | |
1702 | mrqc = IXGBE_MRQC_RSSEN | |
1703 | /* Perform hash on these packet types */ | |
7c6e0a43 JB |
1704 | | IXGBE_MRQC_RSS_FIELD_IPV4 |
1705 | | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | |
1706 | | IXGBE_MRQC_RSS_FIELD_IPV4_UDP | |
1707 | | IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP | |
1708 | | IXGBE_MRQC_RSS_FIELD_IPV6_EX | |
1709 | | IXGBE_MRQC_RSS_FIELD_IPV6 | |
1710 | | IXGBE_MRQC_RSS_FIELD_IPV6_TCP | |
1711 | | IXGBE_MRQC_RSS_FIELD_IPV6_UDP | |
1712 | | IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP; | |
9a799d71 | 1713 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); |
021230d4 | 1714 | } |
9a799d71 | 1715 | |
021230d4 AV |
1716 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); |
1717 | ||
1718 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED || | |
1719 | adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) { | |
1720 | /* Disable indicating checksum in descriptor, enables | |
1721 | * RSS hash */ | |
9a799d71 | 1722 | rxcsum |= IXGBE_RXCSUM_PCSD; |
9a799d71 | 1723 | } |
021230d4 AV |
1724 | if (!(rxcsum & IXGBE_RXCSUM_PCSD)) { |
1725 | /* Enable IPv4 payload checksum for UDP fragments | |
1726 | * if PCSD is not set */ | |
1727 | rxcsum |= IXGBE_RXCSUM_IPPCSE; | |
1728 | } | |
1729 | ||
1730 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
9a799d71 AK |
1731 | } |
1732 | ||
1733 | static void ixgbe_vlan_rx_register(struct net_device *netdev, | |
b4617240 | 1734 | struct vlan_group *grp) |
9a799d71 AK |
1735 | { |
1736 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1737 | u32 ctrl; | |
1738 | ||
d4f80882 AV |
1739 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
1740 | ixgbe_irq_disable(adapter); | |
9a799d71 AK |
1741 | adapter->vlgrp = grp; |
1742 | ||
2f90b865 AD |
1743 | /* |
1744 | * For a DCB driver, always enable VLAN tag stripping so we can | |
1745 | * still receive traffic from a DCB-enabled host even if we're | |
1746 | * not in DCB mode. | |
1747 | */ | |
1748 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL); | |
1749 | ctrl |= IXGBE_VLNCTRL_VME; | |
1750 | ctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
1751 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl); | |
1752 | ||
9a799d71 AK |
1753 | if (grp) { |
1754 | /* enable VLAN tag insert/strip */ | |
1755 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL); | |
746b9f02 | 1756 | ctrl |= IXGBE_VLNCTRL_VME; |
9a799d71 AK |
1757 | ctrl &= ~IXGBE_VLNCTRL_CFIEN; |
1758 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl); | |
1759 | } | |
1760 | ||
d4f80882 AV |
1761 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
1762 | ixgbe_irq_enable(adapter); | |
9a799d71 AK |
1763 | } |
1764 | ||
1765 | static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) | |
1766 | { | |
1767 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
c44ade9e | 1768 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
1769 | |
1770 | /* add VID to filter table */ | |
c44ade9e | 1771 | hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true); |
9a799d71 AK |
1772 | } |
1773 | ||
1774 | static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |
1775 | { | |
1776 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
c44ade9e | 1777 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 1778 | |
d4f80882 AV |
1779 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
1780 | ixgbe_irq_disable(adapter); | |
1781 | ||
9a799d71 | 1782 | vlan_group_set_device(adapter->vlgrp, vid, NULL); |
d4f80882 AV |
1783 | |
1784 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
1785 | ixgbe_irq_enable(adapter); | |
9a799d71 AK |
1786 | |
1787 | /* remove VID from filter table */ | |
c44ade9e | 1788 | hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false); |
9a799d71 AK |
1789 | } |
1790 | ||
1791 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) | |
1792 | { | |
1793 | ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp); | |
1794 | ||
1795 | if (adapter->vlgrp) { | |
1796 | u16 vid; | |
1797 | for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) { | |
1798 | if (!vlan_group_get_device(adapter->vlgrp, vid)) | |
1799 | continue; | |
1800 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
1801 | } | |
1802 | } | |
1803 | } | |
1804 | ||
2c5645cf CL |
1805 | static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq) |
1806 | { | |
1807 | struct dev_mc_list *mc_ptr; | |
1808 | u8 *addr = *mc_addr_ptr; | |
1809 | *vmdq = 0; | |
1810 | ||
1811 | mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]); | |
1812 | if (mc_ptr->next) | |
1813 | *mc_addr_ptr = mc_ptr->next->dmi_addr; | |
1814 | else | |
1815 | *mc_addr_ptr = NULL; | |
1816 | ||
1817 | return addr; | |
1818 | } | |
1819 | ||
9a799d71 | 1820 | /** |
2c5645cf | 1821 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
1822 | * @netdev: network interface device structure |
1823 | * | |
2c5645cf CL |
1824 | * The set_rx_method entry point is called whenever the unicast/multicast |
1825 | * address list or the network interface flags are updated. This routine is | |
1826 | * responsible for configuring the hardware for proper unicast, multicast and | |
1827 | * promiscuous mode. | |
9a799d71 | 1828 | **/ |
2c5645cf | 1829 | static void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
1830 | { |
1831 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1832 | struct ixgbe_hw *hw = &adapter->hw; | |
3d01625a | 1833 | u32 fctrl, vlnctrl; |
2c5645cf CL |
1834 | u8 *addr_list = NULL; |
1835 | int addr_count = 0; | |
9a799d71 AK |
1836 | |
1837 | /* Check for Promiscuous and All Multicast modes */ | |
1838 | ||
1839 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3d01625a | 1840 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
9a799d71 AK |
1841 | |
1842 | if (netdev->flags & IFF_PROMISC) { | |
2c5645cf | 1843 | hw->addr_ctrl.user_set_promisc = 1; |
9a799d71 | 1844 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
3d01625a | 1845 | vlnctrl &= ~IXGBE_VLNCTRL_VFE; |
9a799d71 | 1846 | } else { |
746b9f02 PM |
1847 | if (netdev->flags & IFF_ALLMULTI) { |
1848 | fctrl |= IXGBE_FCTRL_MPE; | |
1849 | fctrl &= ~IXGBE_FCTRL_UPE; | |
1850 | } else { | |
1851 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
1852 | } | |
3d01625a | 1853 | vlnctrl |= IXGBE_VLNCTRL_VFE; |
2c5645cf | 1854 | hw->addr_ctrl.user_set_promisc = 0; |
9a799d71 AK |
1855 | } |
1856 | ||
1857 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
3d01625a | 1858 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
9a799d71 | 1859 | |
2c5645cf CL |
1860 | /* reprogram secondary unicast list */ |
1861 | addr_count = netdev->uc_count; | |
1862 | if (addr_count) | |
1863 | addr_list = netdev->uc_list->dmi_addr; | |
c44ade9e JB |
1864 | hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count, |
1865 | ixgbe_addr_list_itr); | |
9a799d71 | 1866 | |
2c5645cf CL |
1867 | /* reprogram multicast list */ |
1868 | addr_count = netdev->mc_count; | |
1869 | if (addr_count) | |
1870 | addr_list = netdev->mc_list->dmi_addr; | |
c44ade9e JB |
1871 | hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count, |
1872 | ixgbe_addr_list_itr); | |
9a799d71 AK |
1873 | } |
1874 | ||
021230d4 AV |
1875 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
1876 | { | |
1877 | int q_idx; | |
1878 | struct ixgbe_q_vector *q_vector; | |
1879 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1880 | ||
1881 | /* legacy and MSI only use one vector */ | |
1882 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
1883 | q_vectors = 1; | |
1884 | ||
1885 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
f0848276 | 1886 | struct napi_struct *napi; |
021230d4 AV |
1887 | q_vector = &adapter->q_vector[q_idx]; |
1888 | if (!q_vector->rxr_count) | |
1889 | continue; | |
f0848276 JB |
1890 | napi = &q_vector->napi; |
1891 | if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) && | |
1892 | (q_vector->rxr_count > 1)) | |
1893 | napi->poll = &ixgbe_clean_rxonly_many; | |
1894 | ||
1895 | napi_enable(napi); | |
021230d4 AV |
1896 | } |
1897 | } | |
1898 | ||
1899 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
1900 | { | |
1901 | int q_idx; | |
1902 | struct ixgbe_q_vector *q_vector; | |
1903 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1904 | ||
1905 | /* legacy and MSI only use one vector */ | |
1906 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
1907 | q_vectors = 1; | |
1908 | ||
1909 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
1910 | q_vector = &adapter->q_vector[q_idx]; | |
1911 | if (!q_vector->rxr_count) | |
1912 | continue; | |
1913 | napi_disable(&q_vector->napi); | |
1914 | } | |
1915 | } | |
1916 | ||
7a6b6f51 | 1917 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
1918 | /* |
1919 | * ixgbe_configure_dcb - Configure DCB hardware | |
1920 | * @adapter: ixgbe adapter struct | |
1921 | * | |
1922 | * This is called by the driver on open to configure the DCB hardware. | |
1923 | * This is also called by the gennetlink interface when reconfiguring | |
1924 | * the DCB state. | |
1925 | */ | |
1926 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
1927 | { | |
1928 | struct ixgbe_hw *hw = &adapter->hw; | |
1929 | u32 txdctl, vlnctrl; | |
1930 | int i, j; | |
1931 | ||
1932 | ixgbe_dcb_check_config(&adapter->dcb_cfg); | |
1933 | ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG); | |
1934 | ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG); | |
1935 | ||
1936 | /* reconfigure the hardware */ | |
1937 | ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg); | |
1938 | ||
1939 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
1940 | j = adapter->tx_ring[i].reg_idx; | |
1941 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
1942 | /* PThresh workaround for Tx hang with DFP enabled. */ | |
1943 | txdctl |= 32; | |
1944 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); | |
1945 | } | |
1946 | /* Enable VLAN tag insert/strip */ | |
1947 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
1948 | vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE; | |
1949 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
1950 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
1951 | hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); | |
1952 | } | |
1953 | ||
1954 | #endif | |
9a799d71 AK |
1955 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
1956 | { | |
1957 | struct net_device *netdev = adapter->netdev; | |
1958 | int i; | |
1959 | ||
2c5645cf | 1960 | ixgbe_set_rx_mode(netdev); |
9a799d71 AK |
1961 | |
1962 | ixgbe_restore_vlan(adapter); | |
7a6b6f51 | 1963 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
1964 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
1965 | netif_set_gso_max_size(netdev, 32768); | |
1966 | ixgbe_configure_dcb(adapter); | |
1967 | } else { | |
1968 | netif_set_gso_max_size(netdev, 65536); | |
1969 | } | |
1970 | #else | |
1971 | netif_set_gso_max_size(netdev, 65536); | |
1972 | #endif | |
9a799d71 AK |
1973 | |
1974 | ixgbe_configure_tx(adapter); | |
1975 | ixgbe_configure_rx(adapter); | |
1976 | for (i = 0; i < adapter->num_rx_queues; i++) | |
1977 | ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i], | |
b4617240 | 1978 | (adapter->rx_ring[i].count - 1)); |
9a799d71 AK |
1979 | } |
1980 | ||
1981 | static int ixgbe_up_complete(struct ixgbe_adapter *adapter) | |
1982 | { | |
1983 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 1984 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 1985 | int i, j = 0; |
9a799d71 | 1986 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
021230d4 AV |
1987 | u32 txdctl, rxdctl, mhadd; |
1988 | u32 gpie; | |
9a799d71 | 1989 | |
5eba3699 AV |
1990 | ixgbe_get_hw_control(adapter); |
1991 | ||
021230d4 AV |
1992 | if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) || |
1993 | (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) { | |
9a799d71 AK |
1994 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
1995 | gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME | | |
b4617240 | 1996 | IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD); |
9a799d71 AK |
1997 | } else { |
1998 | /* MSI only */ | |
021230d4 | 1999 | gpie = 0; |
9a799d71 | 2000 | } |
021230d4 AV |
2001 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
2002 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
2003 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
9a799d71 AK |
2004 | } |
2005 | ||
021230d4 AV |
2006 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
2007 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, | |
2008 | * specifically only auto mask tx and rx interrupts */ | |
2009 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
2010 | } | |
9a799d71 | 2011 | |
0befdb3e JB |
2012 | /* Enable fan failure interrupt if media type is copper */ |
2013 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
2014 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
2015 | gpie |= IXGBE_SDP1_GPIEN; | |
2016 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
2017 | } | |
2018 | ||
021230d4 | 2019 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); |
9a799d71 AK |
2020 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { |
2021 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
2022 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
2023 | ||
2024 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
2025 | } | |
2026 | ||
2027 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
021230d4 AV |
2028 | j = adapter->tx_ring[i].reg_idx; |
2029 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
e01c31a5 JB |
2030 | /* enable WTHRESH=8 descriptors, to encourage burst writeback */ |
2031 | txdctl |= (8 << 16); | |
9a799d71 | 2032 | txdctl |= IXGBE_TXDCTL_ENABLE; |
021230d4 | 2033 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); |
9a799d71 AK |
2034 | } |
2035 | ||
2036 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
021230d4 AV |
2037 | j = adapter->rx_ring[i].reg_idx; |
2038 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
2039 | /* enable PTHRESH=32 descriptors (half the internal cache) | |
2040 | * and HTHRESH=0 descriptors (to minimize latency on fetch), | |
2041 | * this also removes a pesky rx_no_buffer_count increment */ | |
2042 | rxdctl |= 0x0020; | |
9a799d71 | 2043 | rxdctl |= IXGBE_RXDCTL_ENABLE; |
021230d4 | 2044 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl); |
9a799d71 AK |
2045 | } |
2046 | /* enable all receives */ | |
2047 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
2048 | rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN); | |
2049 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxdctl); | |
2050 | ||
2051 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) | |
2052 | ixgbe_configure_msix(adapter); | |
2053 | else | |
2054 | ixgbe_configure_msi_and_legacy(adapter); | |
2055 | ||
2056 | clear_bit(__IXGBE_DOWN, &adapter->state); | |
021230d4 AV |
2057 | ixgbe_napi_enable_all(adapter); |
2058 | ||
2059 | /* clear any pending interrupts, may auto mask */ | |
2060 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
2061 | ||
9a799d71 AK |
2062 | ixgbe_irq_enable(adapter); |
2063 | ||
2064 | /* bring the link up in the watchdog, this could race with our first | |
2065 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
2066 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
2067 | adapter->link_check_timeout = jiffies; | |
9a799d71 AK |
2068 | mod_timer(&adapter->watchdog_timer, jiffies); |
2069 | return 0; | |
2070 | } | |
2071 | ||
d4f80882 AV |
2072 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
2073 | { | |
2074 | WARN_ON(in_interrupt()); | |
2075 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) | |
2076 | msleep(1); | |
2077 | ixgbe_down(adapter); | |
2078 | ixgbe_up(adapter); | |
2079 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
2080 | } | |
2081 | ||
9a799d71 AK |
2082 | int ixgbe_up(struct ixgbe_adapter *adapter) |
2083 | { | |
2084 | /* hardware has been reset, we need to reload some things */ | |
2085 | ixgbe_configure(adapter); | |
2086 | ||
2087 | return ixgbe_up_complete(adapter); | |
2088 | } | |
2089 | ||
2090 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
2091 | { | |
c44ade9e JB |
2092 | struct ixgbe_hw *hw = &adapter->hw; |
2093 | if (hw->mac.ops.init_hw(hw)) | |
2094 | dev_err(&adapter->pdev->dev, "Hardware Error\n"); | |
9a799d71 AK |
2095 | |
2096 | /* reprogram the RAR[0] in case user changed it. */ | |
c44ade9e | 2097 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
9a799d71 AK |
2098 | |
2099 | } | |
2100 | ||
9a799d71 AK |
2101 | /** |
2102 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
2103 | * @adapter: board private structure | |
2104 | * @rx_ring: ring to free buffers from | |
2105 | **/ | |
2106 | static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 2107 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
2108 | { |
2109 | struct pci_dev *pdev = adapter->pdev; | |
2110 | unsigned long size; | |
2111 | unsigned int i; | |
2112 | ||
2113 | /* Free all the Rx ring sk_buffs */ | |
2114 | ||
2115 | for (i = 0; i < rx_ring->count; i++) { | |
2116 | struct ixgbe_rx_buffer *rx_buffer_info; | |
2117 | ||
2118 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
2119 | if (rx_buffer_info->dma) { | |
2120 | pci_unmap_single(pdev, rx_buffer_info->dma, | |
b4617240 PW |
2121 | rx_ring->rx_buf_len, |
2122 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
2123 | rx_buffer_info->dma = 0; |
2124 | } | |
2125 | if (rx_buffer_info->skb) { | |
2126 | dev_kfree_skb(rx_buffer_info->skb); | |
2127 | rx_buffer_info->skb = NULL; | |
2128 | } | |
2129 | if (!rx_buffer_info->page) | |
2130 | continue; | |
762f4c57 JB |
2131 | pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2, |
2132 | PCI_DMA_FROMDEVICE); | |
9a799d71 | 2133 | rx_buffer_info->page_dma = 0; |
9a799d71 AK |
2134 | put_page(rx_buffer_info->page); |
2135 | rx_buffer_info->page = NULL; | |
762f4c57 | 2136 | rx_buffer_info->page_offset = 0; |
9a799d71 AK |
2137 | } |
2138 | ||
2139 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
2140 | memset(rx_ring->rx_buffer_info, 0, size); | |
2141 | ||
2142 | /* Zero out the descriptor ring */ | |
2143 | memset(rx_ring->desc, 0, rx_ring->size); | |
2144 | ||
2145 | rx_ring->next_to_clean = 0; | |
2146 | rx_ring->next_to_use = 0; | |
2147 | ||
2148 | writel(0, adapter->hw.hw_addr + rx_ring->head); | |
2149 | writel(0, adapter->hw.hw_addr + rx_ring->tail); | |
2150 | } | |
2151 | ||
2152 | /** | |
2153 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
2154 | * @adapter: board private structure | |
2155 | * @tx_ring: ring to be cleaned | |
2156 | **/ | |
2157 | static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 2158 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
2159 | { |
2160 | struct ixgbe_tx_buffer *tx_buffer_info; | |
2161 | unsigned long size; | |
2162 | unsigned int i; | |
2163 | ||
2164 | /* Free all the Tx ring sk_buffs */ | |
2165 | ||
2166 | for (i = 0; i < tx_ring->count; i++) { | |
2167 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
2168 | ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info); | |
2169 | } | |
2170 | ||
2171 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; | |
2172 | memset(tx_ring->tx_buffer_info, 0, size); | |
2173 | ||
2174 | /* Zero out the descriptor ring */ | |
2175 | memset(tx_ring->desc, 0, tx_ring->size); | |
2176 | ||
2177 | tx_ring->next_to_use = 0; | |
2178 | tx_ring->next_to_clean = 0; | |
2179 | ||
2180 | writel(0, adapter->hw.hw_addr + tx_ring->head); | |
2181 | writel(0, adapter->hw.hw_addr + tx_ring->tail); | |
2182 | } | |
2183 | ||
2184 | /** | |
021230d4 | 2185 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
2186 | * @adapter: board private structure |
2187 | **/ | |
021230d4 | 2188 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2189 | { |
2190 | int i; | |
2191 | ||
021230d4 AV |
2192 | for (i = 0; i < adapter->num_rx_queues; i++) |
2193 | ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]); | |
9a799d71 AK |
2194 | } |
2195 | ||
2196 | /** | |
021230d4 | 2197 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
2198 | * @adapter: board private structure |
2199 | **/ | |
021230d4 | 2200 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2201 | { |
2202 | int i; | |
2203 | ||
021230d4 AV |
2204 | for (i = 0; i < adapter->num_tx_queues; i++) |
2205 | ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]); | |
9a799d71 AK |
2206 | } |
2207 | ||
2208 | void ixgbe_down(struct ixgbe_adapter *adapter) | |
2209 | { | |
2210 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 2211 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 2212 | u32 rxctrl; |
7f821875 JB |
2213 | u32 txdctl; |
2214 | int i, j; | |
9a799d71 AK |
2215 | |
2216 | /* signal that we are down to the interrupt handler */ | |
2217 | set_bit(__IXGBE_DOWN, &adapter->state); | |
2218 | ||
2219 | /* disable receives */ | |
7f821875 JB |
2220 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
2221 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 AK |
2222 | |
2223 | netif_tx_disable(netdev); | |
2224 | ||
7f821875 | 2225 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
2226 | msleep(10); |
2227 | ||
7f821875 JB |
2228 | netif_tx_stop_all_queues(netdev); |
2229 | ||
9a799d71 AK |
2230 | ixgbe_irq_disable(adapter); |
2231 | ||
021230d4 | 2232 | ixgbe_napi_disable_all(adapter); |
7f821875 | 2233 | |
9a799d71 | 2234 | del_timer_sync(&adapter->watchdog_timer); |
cf8280ee | 2235 | cancel_work_sync(&adapter->watchdog_task); |
9a799d71 | 2236 | |
7f821875 JB |
2237 | /* disable transmits in the hardware now that interrupts are off */ |
2238 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2239 | j = adapter->tx_ring[i].reg_idx; | |
2240 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
2241 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), | |
2242 | (txdctl & ~IXGBE_TXDCTL_ENABLE)); | |
2243 | } | |
2244 | ||
9a799d71 | 2245 | netif_carrier_off(netdev); |
9a799d71 | 2246 | |
5dd2d332 | 2247 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 JB |
2248 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
2249 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
2250 | dca_remove_requester(&adapter->pdev->dev); | |
2251 | } | |
2252 | ||
2253 | #endif | |
6f4a0e45 PL |
2254 | if (!pci_channel_offline(adapter->pdev)) |
2255 | ixgbe_reset(adapter); | |
9a799d71 AK |
2256 | ixgbe_clean_all_tx_rings(adapter); |
2257 | ixgbe_clean_all_rx_rings(adapter); | |
2258 | ||
5dd2d332 | 2259 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 JB |
2260 | /* since we reset the hardware DCA settings were cleared */ |
2261 | if (dca_add_requester(&adapter->pdev->dev) == 0) { | |
2262 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; | |
2263 | /* always use CB2 mode, difference is masked | |
2264 | * in the CB driver */ | |
b4617240 | 2265 | IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2); |
96b0e0f6 JB |
2266 | ixgbe_setup_dca(adapter); |
2267 | } | |
2268 | #endif | |
9a799d71 AK |
2269 | } |
2270 | ||
9a799d71 | 2271 | /** |
021230d4 AV |
2272 | * ixgbe_poll - NAPI Rx polling callback |
2273 | * @napi: structure for representing this polling device | |
2274 | * @budget: how many packets driver is allowed to clean | |
2275 | * | |
2276 | * This function is used for legacy and MSI, NAPI mode | |
9a799d71 | 2277 | **/ |
021230d4 | 2278 | static int ixgbe_poll(struct napi_struct *napi, int budget) |
9a799d71 | 2279 | { |
021230d4 | 2280 | struct ixgbe_q_vector *q_vector = container_of(napi, |
b4617240 | 2281 | struct ixgbe_q_vector, napi); |
021230d4 | 2282 | struct ixgbe_adapter *adapter = q_vector->adapter; |
74ce8dd2 | 2283 | int tx_cleaned, work_done = 0; |
9a799d71 | 2284 | |
5dd2d332 | 2285 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
2286 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
2287 | ixgbe_update_tx_dca(adapter, adapter->tx_ring); | |
2288 | ixgbe_update_rx_dca(adapter, adapter->rx_ring); | |
2289 | } | |
2290 | #endif | |
2291 | ||
d2c7ddd6 | 2292 | tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring); |
021230d4 | 2293 | ixgbe_clean_rx_irq(adapter, adapter->rx_ring, &work_done, budget); |
9a799d71 | 2294 | |
d2c7ddd6 DM |
2295 | if (tx_cleaned) |
2296 | work_done = budget; | |
2297 | ||
53e52c72 DM |
2298 | /* If budget not fully consumed, exit the polling mode */ |
2299 | if (work_done < budget) { | |
021230d4 | 2300 | netif_rx_complete(adapter->netdev, napi); |
30efa5a3 | 2301 | if (adapter->itr_setting & 3) |
f494e8fa | 2302 | ixgbe_set_itr(adapter); |
d4f80882 AV |
2303 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2304 | ixgbe_irq_enable(adapter); | |
9a799d71 | 2305 | } |
9a799d71 AK |
2306 | return work_done; |
2307 | } | |
2308 | ||
2309 | /** | |
2310 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
2311 | * @netdev: network interface device structure | |
2312 | **/ | |
2313 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
2314 | { | |
2315 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2316 | ||
2317 | /* Do the reset outside of interrupt context */ | |
2318 | schedule_work(&adapter->reset_task); | |
2319 | } | |
2320 | ||
2321 | static void ixgbe_reset_task(struct work_struct *work) | |
2322 | { | |
2323 | struct ixgbe_adapter *adapter; | |
2324 | adapter = container_of(work, struct ixgbe_adapter, reset_task); | |
2325 | ||
2f90b865 AD |
2326 | /* If we're already down or resetting, just bail */ |
2327 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
2328 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
2329 | return; | |
2330 | ||
9a799d71 AK |
2331 | adapter->tx_timeout_count++; |
2332 | ||
d4f80882 | 2333 | ixgbe_reinit_locked(adapter); |
9a799d71 AK |
2334 | } |
2335 | ||
b9804972 JB |
2336 | static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter) |
2337 | { | |
2338 | int nrq = 1, ntq = 1; | |
2339 | int feature_mask = 0, rss_i, rss_m; | |
2f90b865 | 2340 | int dcb_i, dcb_m; |
b9804972 JB |
2341 | |
2342 | /* Number of supported queues */ | |
2343 | switch (adapter->hw.mac.type) { | |
2344 | case ixgbe_mac_82598EB: | |
2f90b865 AD |
2345 | dcb_i = adapter->ring_feature[RING_F_DCB].indices; |
2346 | dcb_m = 0; | |
b9804972 JB |
2347 | rss_i = adapter->ring_feature[RING_F_RSS].indices; |
2348 | rss_m = 0; | |
2349 | feature_mask |= IXGBE_FLAG_RSS_ENABLED; | |
2f90b865 | 2350 | feature_mask |= IXGBE_FLAG_DCB_ENABLED; |
b9804972 JB |
2351 | |
2352 | switch (adapter->flags & feature_mask) { | |
2f90b865 AD |
2353 | case (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_DCB_ENABLED): |
2354 | dcb_m = 0x7 << 3; | |
2355 | rss_i = min(8, rss_i); | |
2356 | rss_m = 0x7; | |
2357 | nrq = dcb_i * rss_i; | |
2358 | ntq = min(MAX_TX_QUEUES, dcb_i * rss_i); | |
2359 | break; | |
2360 | case (IXGBE_FLAG_DCB_ENABLED): | |
2361 | dcb_m = 0x7 << 3; | |
2362 | nrq = dcb_i; | |
2363 | ntq = dcb_i; | |
2364 | break; | |
b9804972 JB |
2365 | case (IXGBE_FLAG_RSS_ENABLED): |
2366 | rss_m = 0xF; | |
2367 | nrq = rss_i; | |
2368 | ntq = rss_i; | |
2369 | break; | |
2370 | case 0: | |
2371 | default: | |
2f90b865 AD |
2372 | dcb_i = 0; |
2373 | dcb_m = 0; | |
b9804972 JB |
2374 | rss_i = 0; |
2375 | rss_m = 0; | |
2376 | nrq = 1; | |
2377 | ntq = 1; | |
2378 | break; | |
2379 | } | |
2380 | ||
2f90b865 AD |
2381 | /* Sanity check, we should never have zero queues */ |
2382 | nrq = (nrq ?:1); | |
2383 | ntq = (ntq ?:1); | |
2384 | ||
2385 | adapter->ring_feature[RING_F_DCB].indices = dcb_i; | |
2386 | adapter->ring_feature[RING_F_DCB].mask = dcb_m; | |
b9804972 JB |
2387 | adapter->ring_feature[RING_F_RSS].indices = rss_i; |
2388 | adapter->ring_feature[RING_F_RSS].mask = rss_m; | |
2389 | break; | |
2390 | default: | |
2391 | nrq = 1; | |
2392 | ntq = 1; | |
2393 | break; | |
2394 | } | |
2395 | ||
2396 | adapter->num_rx_queues = nrq; | |
2397 | adapter->num_tx_queues = ntq; | |
2398 | } | |
2399 | ||
021230d4 | 2400 | static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 2401 | int vectors) |
021230d4 AV |
2402 | { |
2403 | int err, vector_threshold; | |
2404 | ||
2405 | /* We'll want at least 3 (vector_threshold): | |
2406 | * 1) TxQ[0] Cleanup | |
2407 | * 2) RxQ[0] Cleanup | |
2408 | * 3) Other (Link Status Change, etc.) | |
2409 | * 4) TCP Timer (optional) | |
2410 | */ | |
2411 | vector_threshold = MIN_MSIX_COUNT; | |
2412 | ||
2413 | /* The more we get, the more we will assign to Tx/Rx Cleanup | |
2414 | * for the separate queues...where Rx Cleanup >= Tx Cleanup. | |
2415 | * Right now, we simply care about how many we'll get; we'll | |
2416 | * set them up later while requesting irq's. | |
2417 | */ | |
2418 | while (vectors >= vector_threshold) { | |
2419 | err = pci_enable_msix(adapter->pdev, adapter->msix_entries, | |
b4617240 | 2420 | vectors); |
021230d4 AV |
2421 | if (!err) /* Success in acquiring all requested vectors. */ |
2422 | break; | |
2423 | else if (err < 0) | |
2424 | vectors = 0; /* Nasty failure, quit now */ | |
2425 | else /* err == number of vectors we should try again with */ | |
2426 | vectors = err; | |
2427 | } | |
2428 | ||
2429 | if (vectors < vector_threshold) { | |
2430 | /* Can't allocate enough MSI-X interrupts? Oh well. | |
2431 | * This just means we'll go with either a single MSI | |
2432 | * vector or fall back to legacy interrupts. | |
2433 | */ | |
2434 | DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n"); | |
2435 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
2436 | kfree(adapter->msix_entries); | |
2437 | adapter->msix_entries = NULL; | |
2f90b865 | 2438 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; |
021230d4 | 2439 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; |
b9804972 | 2440 | ixgbe_set_num_queues(adapter); |
021230d4 AV |
2441 | } else { |
2442 | adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */ | |
2443 | adapter->num_msix_vectors = vectors; | |
2444 | } | |
2445 | } | |
2446 | ||
021230d4 AV |
2447 | /** |
2448 | * ixgbe_cache_ring_register - Descriptor ring to register mapping | |
2449 | * @adapter: board private structure to initialize | |
2450 | * | |
2451 | * Once we know the feature-set enabled for the device, we'll cache | |
2452 | * the register offset the descriptor ring is assigned to. | |
2453 | **/ | |
2454 | static void __devinit ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) | |
2455 | { | |
021230d4 AV |
2456 | int feature_mask = 0, rss_i; |
2457 | int i, txr_idx, rxr_idx; | |
2f90b865 | 2458 | int dcb_i; |
021230d4 AV |
2459 | |
2460 | /* Number of supported queues */ | |
2461 | switch (adapter->hw.mac.type) { | |
2462 | case ixgbe_mac_82598EB: | |
2f90b865 | 2463 | dcb_i = adapter->ring_feature[RING_F_DCB].indices; |
021230d4 AV |
2464 | rss_i = adapter->ring_feature[RING_F_RSS].indices; |
2465 | txr_idx = 0; | |
2466 | rxr_idx = 0; | |
2f90b865 | 2467 | feature_mask |= IXGBE_FLAG_DCB_ENABLED; |
021230d4 AV |
2468 | feature_mask |= IXGBE_FLAG_RSS_ENABLED; |
2469 | switch (adapter->flags & feature_mask) { | |
2f90b865 AD |
2470 | case (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_DCB_ENABLED): |
2471 | for (i = 0; i < dcb_i; i++) { | |
2472 | int j; | |
2473 | /* Rx first */ | |
2474 | for (j = 0; j < adapter->num_rx_queues; j++) { | |
2475 | adapter->rx_ring[rxr_idx].reg_idx = | |
2476 | i << 3 | j; | |
2477 | rxr_idx++; | |
2478 | } | |
2479 | /* Tx now */ | |
2480 | for (j = 0; j < adapter->num_tx_queues; j++) { | |
2481 | adapter->tx_ring[txr_idx].reg_idx = | |
2482 | i << 2 | (j >> 1); | |
2483 | if (j & 1) | |
2484 | txr_idx++; | |
2485 | } | |
2486 | } | |
2487 | case (IXGBE_FLAG_DCB_ENABLED): | |
2488 | /* the number of queues is assumed to be symmetric */ | |
2489 | for (i = 0; i < dcb_i; i++) { | |
2490 | adapter->rx_ring[i].reg_idx = i << 3; | |
2491 | adapter->tx_ring[i].reg_idx = i << 2; | |
2492 | } | |
2493 | break; | |
021230d4 AV |
2494 | case (IXGBE_FLAG_RSS_ENABLED): |
2495 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2496 | adapter->rx_ring[i].reg_idx = i; | |
2497 | for (i = 0; i < adapter->num_tx_queues; i++) | |
2498 | adapter->tx_ring[i].reg_idx = i; | |
2499 | break; | |
2500 | case 0: | |
2501 | default: | |
2502 | break; | |
2503 | } | |
2504 | break; | |
2505 | default: | |
2506 | break; | |
2507 | } | |
2508 | } | |
2509 | ||
9a799d71 AK |
2510 | /** |
2511 | * ixgbe_alloc_queues - Allocate memory for all rings | |
2512 | * @adapter: board private structure to initialize | |
2513 | * | |
2514 | * We allocate one ring per queue at run-time since we don't know the | |
2515 | * number of queues at compile-time. The polling_netdev array is | |
2516 | * intended for Multiqueue, but should work fine with a single queue. | |
2517 | **/ | |
2f90b865 | 2518 | static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2519 | { |
2520 | int i; | |
2521 | ||
2522 | adapter->tx_ring = kcalloc(adapter->num_tx_queues, | |
b4617240 | 2523 | sizeof(struct ixgbe_ring), GFP_KERNEL); |
9a799d71 | 2524 | if (!adapter->tx_ring) |
021230d4 | 2525 | goto err_tx_ring_allocation; |
9a799d71 AK |
2526 | |
2527 | adapter->rx_ring = kcalloc(adapter->num_rx_queues, | |
b4617240 | 2528 | sizeof(struct ixgbe_ring), GFP_KERNEL); |
021230d4 AV |
2529 | if (!adapter->rx_ring) |
2530 | goto err_rx_ring_allocation; | |
9a799d71 | 2531 | |
021230d4 | 2532 | for (i = 0; i < adapter->num_tx_queues; i++) { |
b9804972 | 2533 | adapter->tx_ring[i].count = adapter->tx_ring_count; |
021230d4 AV |
2534 | adapter->tx_ring[i].queue_index = i; |
2535 | } | |
b9804972 | 2536 | |
9a799d71 | 2537 | for (i = 0; i < adapter->num_rx_queues; i++) { |
b9804972 | 2538 | adapter->rx_ring[i].count = adapter->rx_ring_count; |
021230d4 AV |
2539 | adapter->rx_ring[i].queue_index = i; |
2540 | } | |
2541 | ||
2542 | ixgbe_cache_ring_register(adapter); | |
2543 | ||
2544 | return 0; | |
2545 | ||
2546 | err_rx_ring_allocation: | |
2547 | kfree(adapter->tx_ring); | |
2548 | err_tx_ring_allocation: | |
2549 | return -ENOMEM; | |
2550 | } | |
2551 | ||
2552 | /** | |
2553 | * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported | |
2554 | * @adapter: board private structure to initialize | |
2555 | * | |
2556 | * Attempt to configure the interrupts using the best available | |
2557 | * capabilities of the hardware and the kernel. | |
2558 | **/ | |
2559 | static int __devinit ixgbe_set_interrupt_capability(struct ixgbe_adapter | |
b4617240 | 2560 | *adapter) |
021230d4 AV |
2561 | { |
2562 | int err = 0; | |
2563 | int vector, v_budget; | |
2564 | ||
2565 | /* | |
2566 | * It's easy to be greedy for MSI-X vectors, but it really | |
2567 | * doesn't do us much good if we have a lot more vectors | |
2568 | * than CPU's. So let's be conservative and only ask for | |
2569 | * (roughly) twice the number of vectors as there are CPU's. | |
2570 | */ | |
2571 | v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues, | |
b4617240 | 2572 | (int)(num_online_cpus() * 2)) + NON_Q_VECTORS; |
021230d4 AV |
2573 | |
2574 | /* | |
2575 | * At the same time, hardware can only support a maximum of | |
2576 | * MAX_MSIX_COUNT vectors. With features such as RSS and VMDq, | |
2577 | * we can easily reach upwards of 64 Rx descriptor queues and | |
2578 | * 32 Tx queues. Thus, we cap it off in those rare cases where | |
2579 | * the cpu count also exceeds our vector limit. | |
2580 | */ | |
2581 | v_budget = min(v_budget, MAX_MSIX_COUNT); | |
2582 | ||
2583 | /* A failure in MSI-X entry allocation isn't fatal, but it does | |
2584 | * mean we disable MSI-X capabilities of the adapter. */ | |
2585 | adapter->msix_entries = kcalloc(v_budget, | |
b4617240 | 2586 | sizeof(struct msix_entry), GFP_KERNEL); |
021230d4 | 2587 | if (!adapter->msix_entries) { |
2f90b865 | 2588 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; |
021230d4 AV |
2589 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; |
2590 | ixgbe_set_num_queues(adapter); | |
2591 | kfree(adapter->tx_ring); | |
2592 | kfree(adapter->rx_ring); | |
2593 | err = ixgbe_alloc_queues(adapter); | |
2594 | if (err) { | |
2595 | DPRINTK(PROBE, ERR, "Unable to allocate memory " | |
b4617240 | 2596 | "for queues\n"); |
021230d4 AV |
2597 | goto out; |
2598 | } | |
2599 | ||
2600 | goto try_msi; | |
2601 | } | |
2602 | ||
2603 | for (vector = 0; vector < v_budget; vector++) | |
2604 | adapter->msix_entries[vector].entry = vector; | |
2605 | ||
2606 | ixgbe_acquire_msix_vectors(adapter, v_budget); | |
2607 | ||
2608 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) | |
2609 | goto out; | |
2610 | ||
2611 | try_msi: | |
2612 | err = pci_enable_msi(adapter->pdev); | |
2613 | if (!err) { | |
2614 | adapter->flags |= IXGBE_FLAG_MSI_ENABLED; | |
2615 | } else { | |
2616 | DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, " | |
b4617240 | 2617 | "falling back to legacy. Error: %d\n", err); |
021230d4 AV |
2618 | /* reset err */ |
2619 | err = 0; | |
2620 | } | |
2621 | ||
2622 | out: | |
30eba97a | 2623 | /* Notify the stack of the (possibly) reduced Tx Queue count. */ |
fd2ea0a7 | 2624 | adapter->netdev->real_num_tx_queues = adapter->num_tx_queues; |
021230d4 AV |
2625 | |
2626 | return err; | |
2627 | } | |
2628 | ||
2f90b865 | 2629 | void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 AV |
2630 | { |
2631 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
2632 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
2633 | pci_disable_msix(adapter->pdev); | |
2634 | kfree(adapter->msix_entries); | |
2635 | adapter->msix_entries = NULL; | |
2636 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
2637 | adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; | |
2638 | pci_disable_msi(adapter->pdev); | |
2639 | } | |
2640 | return; | |
2641 | } | |
2642 | ||
2643 | /** | |
2644 | * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme | |
2645 | * @adapter: board private structure to initialize | |
2646 | * | |
2647 | * We determine which interrupt scheme to use based on... | |
2648 | * - Kernel support (MSI, MSI-X) | |
2649 | * - which can be user-defined (via MODULE_PARAM) | |
2650 | * - Hardware queue count (num_*_queues) | |
2651 | * - defined by miscellaneous hardware support/features (RSS, etc.) | |
2652 | **/ | |
2f90b865 | 2653 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) |
021230d4 AV |
2654 | { |
2655 | int err; | |
2656 | ||
2657 | /* Number of supported queues */ | |
2658 | ixgbe_set_num_queues(adapter); | |
2659 | ||
2660 | err = ixgbe_alloc_queues(adapter); | |
2661 | if (err) { | |
2662 | DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n"); | |
2663 | goto err_alloc_queues; | |
2664 | } | |
2665 | ||
2666 | err = ixgbe_set_interrupt_capability(adapter); | |
2667 | if (err) { | |
2668 | DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n"); | |
2669 | goto err_set_interrupt; | |
9a799d71 AK |
2670 | } |
2671 | ||
021230d4 | 2672 | DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, " |
b4617240 PW |
2673 | "Tx Queue count = %u\n", |
2674 | (adapter->num_rx_queues > 1) ? "Enabled" : | |
2675 | "Disabled", adapter->num_rx_queues, adapter->num_tx_queues); | |
021230d4 AV |
2676 | |
2677 | set_bit(__IXGBE_DOWN, &adapter->state); | |
2678 | ||
9a799d71 | 2679 | return 0; |
021230d4 AV |
2680 | |
2681 | err_set_interrupt: | |
2682 | kfree(adapter->tx_ring); | |
2683 | kfree(adapter->rx_ring); | |
2684 | err_alloc_queues: | |
2685 | return err; | |
9a799d71 AK |
2686 | } |
2687 | ||
c4900be0 DS |
2688 | /** |
2689 | * ixgbe_sfp_timer - worker thread to find a missing module | |
2690 | * @data: pointer to our adapter struct | |
2691 | **/ | |
2692 | static void ixgbe_sfp_timer(unsigned long data) | |
2693 | { | |
2694 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
2695 | ||
2696 | /* Do the sfp_timer outside of interrupt context due to the | |
2697 | * delays that sfp+ detection requires | |
2698 | */ | |
2699 | schedule_work(&adapter->sfp_task); | |
2700 | } | |
2701 | ||
2702 | /** | |
2703 | * ixgbe_sfp_task - worker thread to find a missing module | |
2704 | * @work: pointer to work_struct containing our data | |
2705 | **/ | |
2706 | static void ixgbe_sfp_task(struct work_struct *work) | |
2707 | { | |
2708 | struct ixgbe_adapter *adapter = container_of(work, | |
2709 | struct ixgbe_adapter, | |
2710 | sfp_task); | |
2711 | struct ixgbe_hw *hw = &adapter->hw; | |
2712 | ||
2713 | if ((hw->phy.type == ixgbe_phy_nl) && | |
2714 | (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) { | |
2715 | s32 ret = hw->phy.ops.identify_sfp(hw); | |
2716 | if (ret) | |
2717 | goto reschedule; | |
2718 | ret = hw->phy.ops.reset(hw); | |
2719 | if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
2720 | DPRINTK(PROBE, ERR, "failed to initialize because an " | |
2721 | "unsupported SFP+ module type was detected.\n" | |
2722 | "Reload the driver after installing a " | |
2723 | "supported module.\n"); | |
2724 | unregister_netdev(adapter->netdev); | |
2725 | } else { | |
2726 | DPRINTK(PROBE, INFO, "detected SFP+: %d\n", | |
2727 | hw->phy.sfp_type); | |
2728 | } | |
2729 | /* don't need this routine any more */ | |
2730 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
2731 | } | |
2732 | return; | |
2733 | reschedule: | |
2734 | if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state)) | |
2735 | mod_timer(&adapter->sfp_timer, | |
2736 | round_jiffies(jiffies + (2 * HZ))); | |
2737 | } | |
2738 | ||
9a799d71 AK |
2739 | /** |
2740 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
2741 | * @adapter: board private structure to initialize | |
2742 | * | |
2743 | * ixgbe_sw_init initializes the Adapter private data structure. | |
2744 | * Fields are initialized based on PCI device information and | |
2745 | * OS network device settings (MTU size). | |
2746 | **/ | |
2747 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
2748 | { | |
2749 | struct ixgbe_hw *hw = &adapter->hw; | |
2750 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 2751 | unsigned int rss; |
7a6b6f51 | 2752 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
2753 | int j; |
2754 | struct tc_configuration *tc; | |
2755 | #endif | |
021230d4 | 2756 | |
c44ade9e JB |
2757 | /* PCI config space info */ |
2758 | ||
2759 | hw->vendor_id = pdev->vendor; | |
2760 | hw->device_id = pdev->device; | |
2761 | hw->revision_id = pdev->revision; | |
2762 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
2763 | hw->subsystem_device_id = pdev->subsystem_device; | |
2764 | ||
021230d4 AV |
2765 | /* Set capability flags */ |
2766 | rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus()); | |
2767 | adapter->ring_feature[RING_F_RSS].indices = rss; | |
2768 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; | |
2f90b865 AD |
2769 | adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES; |
2770 | ||
7a6b6f51 | 2771 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
2772 | /* Configure DCB traffic classes */ |
2773 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
2774 | tc = &adapter->dcb_cfg.tc_config[j]; | |
2775 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
2776 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
2777 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
2778 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
2779 | tc->dcb_pfc = pfc_disabled; | |
2780 | } | |
2781 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; | |
2782 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
2783 | adapter->dcb_cfg.rx_pba_cfg = pba_equal; | |
2784 | adapter->dcb_cfg.round_robin_enable = false; | |
2785 | adapter->dcb_set_bitmap = 0x00; | |
2786 | ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, | |
2787 | adapter->ring_feature[RING_F_DCB].indices); | |
2788 | ||
2789 | #endif | |
0befdb3e JB |
2790 | if (hw->mac.ops.get_media_type && |
2791 | (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) | |
2792 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
9a799d71 AK |
2793 | |
2794 | /* default flow control settings */ | |
2b9ade93 JB |
2795 | hw->fc.original_type = ixgbe_fc_none; |
2796 | hw->fc.type = ixgbe_fc_none; | |
2797 | hw->fc.high_water = IXGBE_DEFAULT_FCRTH; | |
2798 | hw->fc.low_water = IXGBE_DEFAULT_FCRTL; | |
2799 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; | |
2800 | hw->fc.send_xon = true; | |
9a799d71 | 2801 | |
021230d4 | 2802 | /* select 10G link by default */ |
9a799d71 | 2803 | hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN; |
9a799d71 | 2804 | |
30efa5a3 JB |
2805 | /* enable itr by default in dynamic mode */ |
2806 | adapter->itr_setting = 1; | |
2807 | adapter->eitr_param = 20000; | |
2808 | ||
2809 | /* set defaults for eitr in MegaBytes */ | |
2810 | adapter->eitr_low = 10; | |
2811 | adapter->eitr_high = 20; | |
2812 | ||
2813 | /* set default ring sizes */ | |
2814 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
2815 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
2816 | ||
9a799d71 | 2817 | /* initialize eeprom parameters */ |
c44ade9e | 2818 | if (ixgbe_init_eeprom_params_generic(hw)) { |
9a799d71 AK |
2819 | dev_err(&pdev->dev, "EEPROM initialization failed\n"); |
2820 | return -EIO; | |
2821 | } | |
2822 | ||
021230d4 | 2823 | /* enable rx csum by default */ |
9a799d71 AK |
2824 | adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED; |
2825 | ||
9a799d71 AK |
2826 | set_bit(__IXGBE_DOWN, &adapter->state); |
2827 | ||
2828 | return 0; | |
2829 | } | |
2830 | ||
2831 | /** | |
2832 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
2833 | * @adapter: board private structure | |
3a581073 | 2834 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
2835 | * |
2836 | * Return 0 on success, negative on failure | |
2837 | **/ | |
2838 | int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter, | |
e01c31a5 | 2839 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
2840 | { |
2841 | struct pci_dev *pdev = adapter->pdev; | |
2842 | int size; | |
2843 | ||
3a581073 JB |
2844 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
2845 | tx_ring->tx_buffer_info = vmalloc(size); | |
e01c31a5 JB |
2846 | if (!tx_ring->tx_buffer_info) |
2847 | goto err; | |
3a581073 | 2848 | memset(tx_ring->tx_buffer_info, 0, size); |
9a799d71 AK |
2849 | |
2850 | /* round up to nearest 4K */ | |
e01c31a5 JB |
2851 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc) + |
2852 | sizeof(u32); | |
3a581073 | 2853 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 2854 | |
3a581073 JB |
2855 | tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, |
2856 | &tx_ring->dma); | |
e01c31a5 JB |
2857 | if (!tx_ring->desc) |
2858 | goto err; | |
9a799d71 | 2859 | |
3a581073 JB |
2860 | tx_ring->next_to_use = 0; |
2861 | tx_ring->next_to_clean = 0; | |
2862 | tx_ring->work_limit = tx_ring->count; | |
9a799d71 | 2863 | return 0; |
e01c31a5 JB |
2864 | |
2865 | err: | |
2866 | vfree(tx_ring->tx_buffer_info); | |
2867 | tx_ring->tx_buffer_info = NULL; | |
2868 | DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit " | |
2869 | "descriptor ring\n"); | |
2870 | return -ENOMEM; | |
9a799d71 AK |
2871 | } |
2872 | ||
69888674 AD |
2873 | /** |
2874 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
2875 | * @adapter: board private structure | |
2876 | * | |
2877 | * If this function returns with an error, then it's possible one or | |
2878 | * more of the rings is populated (while the rest are not). It is the | |
2879 | * callers duty to clean those orphaned rings. | |
2880 | * | |
2881 | * Return 0 on success, negative on failure | |
2882 | **/ | |
2883 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
2884 | { | |
2885 | int i, err = 0; | |
2886 | ||
2887 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2888 | err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]); | |
2889 | if (!err) | |
2890 | continue; | |
2891 | DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i); | |
2892 | break; | |
2893 | } | |
2894 | ||
2895 | return err; | |
2896 | } | |
2897 | ||
9a799d71 AK |
2898 | /** |
2899 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
2900 | * @adapter: board private structure | |
3a581073 | 2901 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
2902 | * |
2903 | * Returns 0 on success, negative on failure | |
2904 | **/ | |
2905 | int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, | |
b4617240 | 2906 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
2907 | { |
2908 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 2909 | int size; |
9a799d71 | 2910 | |
177db6ff | 2911 | size = sizeof(struct net_lro_desc) * IXGBE_MAX_LRO_DESCRIPTORS; |
3a581073 JB |
2912 | rx_ring->lro_mgr.lro_arr = vmalloc(size); |
2913 | if (!rx_ring->lro_mgr.lro_arr) | |
177db6ff | 2914 | return -ENOMEM; |
3a581073 | 2915 | memset(rx_ring->lro_mgr.lro_arr, 0, size); |
177db6ff | 2916 | |
3a581073 JB |
2917 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
2918 | rx_ring->rx_buffer_info = vmalloc(size); | |
2919 | if (!rx_ring->rx_buffer_info) { | |
9a799d71 | 2920 | DPRINTK(PROBE, ERR, |
b4617240 | 2921 | "vmalloc allocation failed for the rx desc ring\n"); |
177db6ff | 2922 | goto alloc_failed; |
9a799d71 | 2923 | } |
3a581073 | 2924 | memset(rx_ring->rx_buffer_info, 0, size); |
9a799d71 | 2925 | |
9a799d71 | 2926 | /* Round up to nearest 4K */ |
3a581073 JB |
2927 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
2928 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 2929 | |
3a581073 | 2930 | rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma); |
9a799d71 | 2931 | |
3a581073 | 2932 | if (!rx_ring->desc) { |
9a799d71 | 2933 | DPRINTK(PROBE, ERR, |
b4617240 | 2934 | "Memory allocation failed for the rx desc ring\n"); |
3a581073 | 2935 | vfree(rx_ring->rx_buffer_info); |
177db6ff | 2936 | goto alloc_failed; |
9a799d71 AK |
2937 | } |
2938 | ||
3a581073 JB |
2939 | rx_ring->next_to_clean = 0; |
2940 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
2941 | |
2942 | return 0; | |
177db6ff MC |
2943 | |
2944 | alloc_failed: | |
3a581073 JB |
2945 | vfree(rx_ring->lro_mgr.lro_arr); |
2946 | rx_ring->lro_mgr.lro_arr = NULL; | |
177db6ff | 2947 | return -ENOMEM; |
9a799d71 AK |
2948 | } |
2949 | ||
69888674 AD |
2950 | /** |
2951 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
2952 | * @adapter: board private structure | |
2953 | * | |
2954 | * If this function returns with an error, then it's possible one or | |
2955 | * more of the rings is populated (while the rest are not). It is the | |
2956 | * callers duty to clean those orphaned rings. | |
2957 | * | |
2958 | * Return 0 on success, negative on failure | |
2959 | **/ | |
2960 | ||
2961 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) | |
2962 | { | |
2963 | int i, err = 0; | |
2964 | ||
2965 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
2966 | err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]); | |
2967 | if (!err) | |
2968 | continue; | |
2969 | DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i); | |
2970 | break; | |
2971 | } | |
2972 | ||
2973 | return err; | |
2974 | } | |
2975 | ||
9a799d71 AK |
2976 | /** |
2977 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
2978 | * @adapter: board private structure | |
2979 | * @tx_ring: Tx descriptor ring for a specific queue | |
2980 | * | |
2981 | * Free all transmit software resources | |
2982 | **/ | |
c431f97e JB |
2983 | void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter, |
2984 | struct ixgbe_ring *tx_ring) | |
9a799d71 AK |
2985 | { |
2986 | struct pci_dev *pdev = adapter->pdev; | |
2987 | ||
2988 | ixgbe_clean_tx_ring(adapter, tx_ring); | |
2989 | ||
2990 | vfree(tx_ring->tx_buffer_info); | |
2991 | tx_ring->tx_buffer_info = NULL; | |
2992 | ||
2993 | pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma); | |
2994 | ||
2995 | tx_ring->desc = NULL; | |
2996 | } | |
2997 | ||
2998 | /** | |
2999 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
3000 | * @adapter: board private structure | |
3001 | * | |
3002 | * Free all transmit software resources | |
3003 | **/ | |
3004 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
3005 | { | |
3006 | int i; | |
3007 | ||
3008 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3009 | ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]); | |
3010 | } | |
3011 | ||
3012 | /** | |
b4617240 | 3013 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
3014 | * @adapter: board private structure |
3015 | * @rx_ring: ring to clean the resources from | |
3016 | * | |
3017 | * Free all receive software resources | |
3018 | **/ | |
c431f97e JB |
3019 | void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter, |
3020 | struct ixgbe_ring *rx_ring) | |
9a799d71 AK |
3021 | { |
3022 | struct pci_dev *pdev = adapter->pdev; | |
3023 | ||
177db6ff MC |
3024 | vfree(rx_ring->lro_mgr.lro_arr); |
3025 | rx_ring->lro_mgr.lro_arr = NULL; | |
3026 | ||
9a799d71 AK |
3027 | ixgbe_clean_rx_ring(adapter, rx_ring); |
3028 | ||
3029 | vfree(rx_ring->rx_buffer_info); | |
3030 | rx_ring->rx_buffer_info = NULL; | |
3031 | ||
3032 | pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); | |
3033 | ||
3034 | rx_ring->desc = NULL; | |
3035 | } | |
3036 | ||
3037 | /** | |
3038 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
3039 | * @adapter: board private structure | |
3040 | * | |
3041 | * Free all receive software resources | |
3042 | **/ | |
3043 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
3044 | { | |
3045 | int i; | |
3046 | ||
3047 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3048 | ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]); | |
3049 | } | |
3050 | ||
9a799d71 AK |
3051 | /** |
3052 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
3053 | * @netdev: network interface device structure | |
3054 | * @new_mtu: new value for maximum frame size | |
3055 | * | |
3056 | * Returns 0 on success, negative on failure | |
3057 | **/ | |
3058 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
3059 | { | |
3060 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3061 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
3062 | ||
42c783c5 JB |
3063 | /* MTU < 68 is an error and causes problems on some kernels */ |
3064 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) | |
9a799d71 AK |
3065 | return -EINVAL; |
3066 | ||
021230d4 | 3067 | DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n", |
b4617240 | 3068 | netdev->mtu, new_mtu); |
021230d4 | 3069 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
3070 | netdev->mtu = new_mtu; |
3071 | ||
d4f80882 AV |
3072 | if (netif_running(netdev)) |
3073 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
3074 | |
3075 | return 0; | |
3076 | } | |
3077 | ||
3078 | /** | |
3079 | * ixgbe_open - Called when a network interface is made active | |
3080 | * @netdev: network interface device structure | |
3081 | * | |
3082 | * Returns 0 on success, negative value on failure | |
3083 | * | |
3084 | * The open entry point is called when a network interface is made | |
3085 | * active by the system (IFF_UP). At this point all resources needed | |
3086 | * for transmit and receive operations are allocated, the interrupt | |
3087 | * handler is registered with the OS, the watchdog timer is started, | |
3088 | * and the stack is notified that the interface is ready. | |
3089 | **/ | |
3090 | static int ixgbe_open(struct net_device *netdev) | |
3091 | { | |
3092 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3093 | int err; | |
4bebfaa5 AK |
3094 | |
3095 | /* disallow open during test */ | |
3096 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
3097 | return -EBUSY; | |
9a799d71 | 3098 | |
9a799d71 AK |
3099 | /* allocate transmit descriptors */ |
3100 | err = ixgbe_setup_all_tx_resources(adapter); | |
3101 | if (err) | |
3102 | goto err_setup_tx; | |
3103 | ||
9a799d71 AK |
3104 | /* allocate receive descriptors */ |
3105 | err = ixgbe_setup_all_rx_resources(adapter); | |
3106 | if (err) | |
3107 | goto err_setup_rx; | |
3108 | ||
3109 | ixgbe_configure(adapter); | |
3110 | ||
021230d4 | 3111 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
3112 | if (err) |
3113 | goto err_req_irq; | |
3114 | ||
9a799d71 AK |
3115 | err = ixgbe_up_complete(adapter); |
3116 | if (err) | |
3117 | goto err_up; | |
3118 | ||
d55b53ff JK |
3119 | netif_tx_start_all_queues(netdev); |
3120 | ||
9a799d71 AK |
3121 | return 0; |
3122 | ||
3123 | err_up: | |
5eba3699 | 3124 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
3125 | ixgbe_free_irq(adapter); |
3126 | err_req_irq: | |
3127 | ixgbe_free_all_rx_resources(adapter); | |
3128 | err_setup_rx: | |
3129 | ixgbe_free_all_tx_resources(adapter); | |
3130 | err_setup_tx: | |
3131 | ixgbe_reset(adapter); | |
3132 | ||
3133 | return err; | |
3134 | } | |
3135 | ||
3136 | /** | |
3137 | * ixgbe_close - Disables a network interface | |
3138 | * @netdev: network interface device structure | |
3139 | * | |
3140 | * Returns 0, this is not allowed to fail | |
3141 | * | |
3142 | * The close entry point is called when an interface is de-activated | |
3143 | * by the OS. The hardware is still under the drivers control, but | |
3144 | * needs to be disabled. A global MAC reset is issued to stop the | |
3145 | * hardware, and all transmit and receive resources are freed. | |
3146 | **/ | |
3147 | static int ixgbe_close(struct net_device *netdev) | |
3148 | { | |
3149 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 AK |
3150 | |
3151 | ixgbe_down(adapter); | |
3152 | ixgbe_free_irq(adapter); | |
3153 | ||
3154 | ixgbe_free_all_tx_resources(adapter); | |
3155 | ixgbe_free_all_rx_resources(adapter); | |
3156 | ||
5eba3699 | 3157 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
3158 | |
3159 | return 0; | |
3160 | } | |
3161 | ||
b3c8b4ba AD |
3162 | /** |
3163 | * ixgbe_napi_add_all - prep napi structs for use | |
3164 | * @adapter: private struct | |
3165 | * helper function to napi_add each possible q_vector->napi | |
3166 | */ | |
2f90b865 | 3167 | void ixgbe_napi_add_all(struct ixgbe_adapter *adapter) |
b3c8b4ba AD |
3168 | { |
3169 | int q_idx, q_vectors; | |
3170 | int (*poll)(struct napi_struct *, int); | |
3171 | ||
3172 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
3173 | poll = &ixgbe_clean_rxonly; | |
3174 | /* Only enable as many vectors as we have rx queues. */ | |
3175 | q_vectors = adapter->num_rx_queues; | |
3176 | } else { | |
3177 | poll = &ixgbe_poll; | |
3178 | /* only one q_vector for legacy modes */ | |
3179 | q_vectors = 1; | |
3180 | } | |
3181 | ||
3182 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
3183 | struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx]; | |
3184 | netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64); | |
3185 | } | |
3186 | } | |
3187 | ||
2f90b865 | 3188 | void ixgbe_napi_del_all(struct ixgbe_adapter *adapter) |
b3c8b4ba AD |
3189 | { |
3190 | int q_idx; | |
3191 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3192 | ||
3193 | /* legacy and MSI only use one vector */ | |
3194 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
3195 | q_vectors = 1; | |
3196 | ||
3197 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
3198 | struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx]; | |
3199 | if (!q_vector->rxr_count) | |
3200 | continue; | |
3201 | netif_napi_del(&q_vector->napi); | |
3202 | } | |
3203 | } | |
3204 | ||
3205 | #ifdef CONFIG_PM | |
3206 | static int ixgbe_resume(struct pci_dev *pdev) | |
3207 | { | |
3208 | struct net_device *netdev = pci_get_drvdata(pdev); | |
3209 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3210 | u32 err; | |
3211 | ||
3212 | pci_set_power_state(pdev, PCI_D0); | |
3213 | pci_restore_state(pdev); | |
3214 | err = pci_enable_device(pdev); | |
3215 | if (err) { | |
69888674 | 3216 | printk(KERN_ERR "ixgbe: Cannot enable PCI device from " |
b3c8b4ba AD |
3217 | "suspend\n"); |
3218 | return err; | |
3219 | } | |
3220 | pci_set_master(pdev); | |
3221 | ||
3222 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
3223 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
3224 | ||
3225 | err = ixgbe_init_interrupt_scheme(adapter); | |
3226 | if (err) { | |
3227 | printk(KERN_ERR "ixgbe: Cannot initialize interrupts for " | |
3228 | "device\n"); | |
3229 | return err; | |
3230 | } | |
3231 | ||
3232 | ixgbe_napi_add_all(adapter); | |
3233 | ixgbe_reset(adapter); | |
3234 | ||
3235 | if (netif_running(netdev)) { | |
3236 | err = ixgbe_open(adapter->netdev); | |
3237 | if (err) | |
3238 | return err; | |
3239 | } | |
3240 | ||
3241 | netif_device_attach(netdev); | |
3242 | ||
3243 | return 0; | |
3244 | } | |
3245 | ||
3246 | #endif /* CONFIG_PM */ | |
3247 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
3248 | { | |
3249 | struct net_device *netdev = pci_get_drvdata(pdev); | |
3250 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3251 | #ifdef CONFIG_PM | |
3252 | int retval = 0; | |
3253 | #endif | |
3254 | ||
3255 | netif_device_detach(netdev); | |
3256 | ||
3257 | if (netif_running(netdev)) { | |
3258 | ixgbe_down(adapter); | |
3259 | ixgbe_free_irq(adapter); | |
3260 | ixgbe_free_all_tx_resources(adapter); | |
3261 | ixgbe_free_all_rx_resources(adapter); | |
3262 | } | |
3263 | ixgbe_reset_interrupt_capability(adapter); | |
3264 | ixgbe_napi_del_all(adapter); | |
3265 | kfree(adapter->tx_ring); | |
3266 | kfree(adapter->rx_ring); | |
3267 | ||
3268 | #ifdef CONFIG_PM | |
3269 | retval = pci_save_state(pdev); | |
3270 | if (retval) | |
3271 | return retval; | |
3272 | #endif | |
3273 | ||
3274 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
3275 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
3276 | ||
3277 | ixgbe_release_hw_control(adapter); | |
3278 | ||
3279 | pci_disable_device(pdev); | |
3280 | ||
3281 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
3282 | ||
3283 | return 0; | |
3284 | } | |
3285 | ||
3286 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
3287 | { | |
3288 | ixgbe_suspend(pdev, PMSG_SUSPEND); | |
3289 | } | |
3290 | ||
9a799d71 AK |
3291 | /** |
3292 | * ixgbe_update_stats - Update the board statistics counters. | |
3293 | * @adapter: board private structure | |
3294 | **/ | |
3295 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
3296 | { | |
3297 | struct ixgbe_hw *hw = &adapter->hw; | |
6f11eef7 AV |
3298 | u64 total_mpc = 0; |
3299 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
9a799d71 AK |
3300 | |
3301 | adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); | |
6f11eef7 AV |
3302 | for (i = 0; i < 8; i++) { |
3303 | /* for packet buffers not used, the register should read 0 */ | |
3304 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
3305 | missed_rx += mpc; | |
3306 | adapter->stats.mpc[i] += mpc; | |
3307 | total_mpc += adapter->stats.mpc[i]; | |
3308 | adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); | |
2f90b865 AD |
3309 | adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); |
3310 | adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
3311 | adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
3312 | adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
3313 | adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, | |
3314 | IXGBE_PXONRXC(i)); | |
3315 | adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw, | |
3316 | IXGBE_PXONTXC(i)); | |
3317 | adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, | |
3318 | IXGBE_PXOFFRXC(i)); | |
3319 | adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw, | |
3320 | IXGBE_PXOFFTXC(i)); | |
6f11eef7 AV |
3321 | } |
3322 | adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); | |
3323 | /* work around hardware counting issue */ | |
3324 | adapter->stats.gprc -= missed_rx; | |
3325 | ||
3326 | /* 82598 hardware only has a 32 bit counter in the high register */ | |
9a799d71 | 3327 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); |
6f11eef7 AV |
3328 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); |
3329 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
9a799d71 AK |
3330 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
3331 | adapter->stats.bprc += bprc; | |
3332 | adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
3333 | adapter->stats.mprc -= bprc; | |
3334 | adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC); | |
3335 | adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
3336 | adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
3337 | adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
3338 | adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
3339 | adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
3340 | adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
9a799d71 AK |
3341 | adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); |
3342 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
9a799d71 | 3343 | adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); |
6f11eef7 AV |
3344 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
3345 | adapter->stats.lxontxc += lxon; | |
3346 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); | |
3347 | adapter->stats.lxofftxc += lxoff; | |
9a799d71 AK |
3348 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
3349 | adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); | |
6f11eef7 AV |
3350 | adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); |
3351 | /* | |
3352 | * 82598 errata - tx of flow control packets is included in tx counters | |
3353 | */ | |
3354 | xon_off_tot = lxon + lxoff; | |
3355 | adapter->stats.gptc -= xon_off_tot; | |
3356 | adapter->stats.mptc -= xon_off_tot; | |
3357 | adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
9a799d71 AK |
3358 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
3359 | adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
3360 | adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
9a799d71 AK |
3361 | adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR); |
3362 | adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
6f11eef7 | 3363 | adapter->stats.ptc64 -= xon_off_tot; |
9a799d71 AK |
3364 | adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); |
3365 | adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
3366 | adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
3367 | adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
3368 | adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
9a799d71 AK |
3369 | adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); |
3370 | ||
3371 | /* Fill out the OS statistics structure */ | |
9a799d71 AK |
3372 | adapter->net_stats.multicast = adapter->stats.mprc; |
3373 | ||
3374 | /* Rx Errors */ | |
3375 | adapter->net_stats.rx_errors = adapter->stats.crcerrs + | |
b4617240 | 3376 | adapter->stats.rlec; |
9a799d71 AK |
3377 | adapter->net_stats.rx_dropped = 0; |
3378 | adapter->net_stats.rx_length_errors = adapter->stats.rlec; | |
3379 | adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs; | |
6f11eef7 | 3380 | adapter->net_stats.rx_missed_errors = total_mpc; |
9a799d71 AK |
3381 | } |
3382 | ||
3383 | /** | |
3384 | * ixgbe_watchdog - Timer Call-back | |
3385 | * @data: pointer to adapter cast into an unsigned long | |
3386 | **/ | |
3387 | static void ixgbe_watchdog(unsigned long data) | |
3388 | { | |
3389 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
cf8280ee JB |
3390 | struct ixgbe_hw *hw = &adapter->hw; |
3391 | ||
3392 | /* Do the watchdog outside of interrupt context due to the lovely | |
3393 | * delays that some of the newer hardware requires */ | |
3394 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
3395 | /* Cause software interrupt to ensure rx rings are cleaned */ | |
3396 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
3397 | u32 eics = | |
3398 | (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1; | |
3399 | IXGBE_WRITE_REG(hw, IXGBE_EICS, eics); | |
3400 | } else { | |
3401 | /* For legacy and MSI interrupts don't set any bits that | |
3402 | * are enabled for EIAM, because this operation would | |
3403 | * set *both* EIMS and EICS for any bit in EIAM */ | |
3404 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
3405 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
3406 | } | |
3407 | /* Reset the timer */ | |
3408 | mod_timer(&adapter->watchdog_timer, | |
3409 | round_jiffies(jiffies + 2 * HZ)); | |
3410 | } | |
9a799d71 | 3411 | |
cf8280ee JB |
3412 | schedule_work(&adapter->watchdog_task); |
3413 | } | |
3414 | ||
3415 | /** | |
69888674 AD |
3416 | * ixgbe_watchdog_task - worker thread to bring link up |
3417 | * @work: pointer to work_struct containing our data | |
cf8280ee JB |
3418 | **/ |
3419 | static void ixgbe_watchdog_task(struct work_struct *work) | |
3420 | { | |
3421 | struct ixgbe_adapter *adapter = container_of(work, | |
3422 | struct ixgbe_adapter, | |
3423 | watchdog_task); | |
3424 | struct net_device *netdev = adapter->netdev; | |
3425 | struct ixgbe_hw *hw = &adapter->hw; | |
3426 | u32 link_speed = adapter->link_speed; | |
3427 | bool link_up = adapter->link_up; | |
3428 | ||
3429 | adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK; | |
3430 | ||
3431 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { | |
3432 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
3433 | if (link_up || | |
3434 | time_after(jiffies, (adapter->link_check_timeout + | |
3435 | IXGBE_TRY_LINK_TIMEOUT))) { | |
3436 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); | |
3437 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; | |
3438 | } | |
3439 | adapter->link_up = link_up; | |
3440 | adapter->link_speed = link_speed; | |
3441 | } | |
9a799d71 AK |
3442 | |
3443 | if (link_up) { | |
3444 | if (!netif_carrier_ok(netdev)) { | |
cf8280ee JB |
3445 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); |
3446 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
9a799d71 AK |
3447 | #define FLOW_RX (frctl & IXGBE_FCTRL_RFCE) |
3448 | #define FLOW_TX (rmcs & IXGBE_RMCS_TFCE_802_3X) | |
3449 | DPRINTK(LINK, INFO, "NIC Link is Up %s, " | |
cf8280ee JB |
3450 | "Flow Control: %s\n", |
3451 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? | |
3452 | "10 Gbps" : | |
3453 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
3454 | "1 Gbps" : "unknown speed")), | |
3455 | ((FLOW_RX && FLOW_TX) ? "RX/TX" : | |
3456 | (FLOW_RX ? "RX" : | |
3457 | (FLOW_TX ? "TX" : "None")))); | |
9a799d71 AK |
3458 | |
3459 | netif_carrier_on(netdev); | |
2f90b865 | 3460 | netif_tx_wake_all_queues(netdev); |
9a799d71 AK |
3461 | } else { |
3462 | /* Force detection of hung controller */ | |
3463 | adapter->detect_tx_hung = true; | |
3464 | } | |
3465 | } else { | |
cf8280ee JB |
3466 | adapter->link_up = false; |
3467 | adapter->link_speed = 0; | |
9a799d71 AK |
3468 | if (netif_carrier_ok(netdev)) { |
3469 | DPRINTK(LINK, INFO, "NIC Link is Down\n"); | |
3470 | netif_carrier_off(netdev); | |
2f90b865 | 3471 | netif_tx_stop_all_queues(netdev); |
9a799d71 AK |
3472 | } |
3473 | } | |
3474 | ||
3475 | ixgbe_update_stats(adapter); | |
cf8280ee | 3476 | adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK; |
9a799d71 AK |
3477 | } |
3478 | ||
9a799d71 | 3479 | static int ixgbe_tso(struct ixgbe_adapter *adapter, |
b4617240 PW |
3480 | struct ixgbe_ring *tx_ring, struct sk_buff *skb, |
3481 | u32 tx_flags, u8 *hdr_len) | |
9a799d71 AK |
3482 | { |
3483 | struct ixgbe_adv_tx_context_desc *context_desc; | |
3484 | unsigned int i; | |
3485 | int err; | |
3486 | struct ixgbe_tx_buffer *tx_buffer_info; | |
9f8cdf4f JB |
3487 | u32 vlan_macip_lens = 0, type_tucmd_mlhl; |
3488 | u32 mss_l4len_idx, l4len; | |
9a799d71 AK |
3489 | |
3490 | if (skb_is_gso(skb)) { | |
3491 | if (skb_header_cloned(skb)) { | |
3492 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
3493 | if (err) | |
3494 | return err; | |
3495 | } | |
3496 | l4len = tcp_hdrlen(skb); | |
3497 | *hdr_len += l4len; | |
3498 | ||
8327d000 | 3499 | if (skb->protocol == htons(ETH_P_IP)) { |
9a799d71 AK |
3500 | struct iphdr *iph = ip_hdr(skb); |
3501 | iph->tot_len = 0; | |
3502 | iph->check = 0; | |
3503 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
b4617240 PW |
3504 | iph->daddr, 0, |
3505 | IPPROTO_TCP, | |
3506 | 0); | |
9a799d71 AK |
3507 | adapter->hw_tso_ctxt++; |
3508 | } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) { | |
3509 | ipv6_hdr(skb)->payload_len = 0; | |
3510 | tcp_hdr(skb)->check = | |
3511 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
b4617240 PW |
3512 | &ipv6_hdr(skb)->daddr, |
3513 | 0, IPPROTO_TCP, 0); | |
9a799d71 AK |
3514 | adapter->hw_tso6_ctxt++; |
3515 | } | |
3516 | ||
3517 | i = tx_ring->next_to_use; | |
3518 | ||
3519 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
3520 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
3521 | ||
3522 | /* VLAN MACLEN IPLEN */ | |
3523 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
3524 | vlan_macip_lens |= | |
3525 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
3526 | vlan_macip_lens |= ((skb_network_offset(skb)) << | |
b4617240 | 3527 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
3528 | *hdr_len += skb_network_offset(skb); |
3529 | vlan_macip_lens |= | |
3530 | (skb_transport_header(skb) - skb_network_header(skb)); | |
3531 | *hdr_len += | |
3532 | (skb_transport_header(skb) - skb_network_header(skb)); | |
3533 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
3534 | context_desc->seqnum_seed = 0; | |
3535 | ||
3536 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ | |
9f8cdf4f | 3537 | type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT | |
b4617240 | 3538 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 | 3539 | |
8327d000 | 3540 | if (skb->protocol == htons(ETH_P_IP)) |
9a799d71 AK |
3541 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
3542 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
3543 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
3544 | ||
3545 | /* MSS L4LEN IDX */ | |
9f8cdf4f | 3546 | mss_l4len_idx = |
9a799d71 AK |
3547 | (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT); |
3548 | mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT); | |
4eeae6fd PW |
3549 | /* use index 1 for TSO */ |
3550 | mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
3551 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); |
3552 | ||
3553 | tx_buffer_info->time_stamp = jiffies; | |
3554 | tx_buffer_info->next_to_watch = i; | |
3555 | ||
3556 | i++; | |
3557 | if (i == tx_ring->count) | |
3558 | i = 0; | |
3559 | tx_ring->next_to_use = i; | |
3560 | ||
3561 | return true; | |
3562 | } | |
3563 | return false; | |
3564 | } | |
3565 | ||
3566 | static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter, | |
b4617240 PW |
3567 | struct ixgbe_ring *tx_ring, |
3568 | struct sk_buff *skb, u32 tx_flags) | |
9a799d71 AK |
3569 | { |
3570 | struct ixgbe_adv_tx_context_desc *context_desc; | |
3571 | unsigned int i; | |
3572 | struct ixgbe_tx_buffer *tx_buffer_info; | |
3573 | u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0; | |
3574 | ||
3575 | if (skb->ip_summed == CHECKSUM_PARTIAL || | |
3576 | (tx_flags & IXGBE_TX_FLAGS_VLAN)) { | |
3577 | i = tx_ring->next_to_use; | |
3578 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
3579 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
3580 | ||
3581 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
3582 | vlan_macip_lens |= | |
3583 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
3584 | vlan_macip_lens |= (skb_network_offset(skb) << | |
b4617240 | 3585 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
3586 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
3587 | vlan_macip_lens |= (skb_transport_header(skb) - | |
b4617240 | 3588 | skb_network_header(skb)); |
9a799d71 AK |
3589 | |
3590 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
3591 | context_desc->seqnum_seed = 0; | |
3592 | ||
3593 | type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT | | |
b4617240 | 3594 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 AK |
3595 | |
3596 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
41825d71 AK |
3597 | switch (skb->protocol) { |
3598 | case __constant_htons(ETH_P_IP): | |
9a799d71 | 3599 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
41825d71 AK |
3600 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) |
3601 | type_tucmd_mlhl |= | |
b4617240 | 3602 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
41825d71 | 3603 | break; |
41825d71 AK |
3604 | case __constant_htons(ETH_P_IPV6): |
3605 | /* XXX what about other V6 headers?? */ | |
3606 | if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) | |
3607 | type_tucmd_mlhl |= | |
b4617240 | 3608 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
41825d71 | 3609 | break; |
41825d71 AK |
3610 | default: |
3611 | if (unlikely(net_ratelimit())) { | |
3612 | DPRINTK(PROBE, WARNING, | |
3613 | "partial checksum but proto=%x!\n", | |
3614 | skb->protocol); | |
3615 | } | |
3616 | break; | |
3617 | } | |
9a799d71 AK |
3618 | } |
3619 | ||
3620 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
4eeae6fd | 3621 | /* use index zero for tx checksum offload */ |
9a799d71 AK |
3622 | context_desc->mss_l4len_idx = 0; |
3623 | ||
3624 | tx_buffer_info->time_stamp = jiffies; | |
3625 | tx_buffer_info->next_to_watch = i; | |
9f8cdf4f | 3626 | |
9a799d71 AK |
3627 | adapter->hw_csum_tx_good++; |
3628 | i++; | |
3629 | if (i == tx_ring->count) | |
3630 | i = 0; | |
3631 | tx_ring->next_to_use = i; | |
3632 | ||
3633 | return true; | |
3634 | } | |
9f8cdf4f | 3635 | |
9a799d71 AK |
3636 | return false; |
3637 | } | |
3638 | ||
3639 | static int ixgbe_tx_map(struct ixgbe_adapter *adapter, | |
b4617240 PW |
3640 | struct ixgbe_ring *tx_ring, |
3641 | struct sk_buff *skb, unsigned int first) | |
9a799d71 AK |
3642 | { |
3643 | struct ixgbe_tx_buffer *tx_buffer_info; | |
3644 | unsigned int len = skb->len; | |
3645 | unsigned int offset = 0, size, count = 0, i; | |
3646 | unsigned int nr_frags = skb_shinfo(skb)->nr_frags; | |
3647 | unsigned int f; | |
3648 | ||
3649 | len -= skb->data_len; | |
3650 | ||
3651 | i = tx_ring->next_to_use; | |
3652 | ||
3653 | while (len) { | |
3654 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
3655 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
3656 | ||
3657 | tx_buffer_info->length = size; | |
3658 | tx_buffer_info->dma = pci_map_single(adapter->pdev, | |
b4617240 PW |
3659 | skb->data + offset, |
3660 | size, PCI_DMA_TODEVICE); | |
9a799d71 AK |
3661 | tx_buffer_info->time_stamp = jiffies; |
3662 | tx_buffer_info->next_to_watch = i; | |
3663 | ||
3664 | len -= size; | |
3665 | offset += size; | |
3666 | count++; | |
3667 | i++; | |
3668 | if (i == tx_ring->count) | |
3669 | i = 0; | |
3670 | } | |
3671 | ||
3672 | for (f = 0; f < nr_frags; f++) { | |
3673 | struct skb_frag_struct *frag; | |
3674 | ||
3675 | frag = &skb_shinfo(skb)->frags[f]; | |
3676 | len = frag->size; | |
3677 | offset = frag->page_offset; | |
3678 | ||
3679 | while (len) { | |
3680 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
3681 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
3682 | ||
3683 | tx_buffer_info->length = size; | |
3684 | tx_buffer_info->dma = pci_map_page(adapter->pdev, | |
b4617240 PW |
3685 | frag->page, |
3686 | offset, | |
3687 | size, | |
3688 | PCI_DMA_TODEVICE); | |
9a799d71 AK |
3689 | tx_buffer_info->time_stamp = jiffies; |
3690 | tx_buffer_info->next_to_watch = i; | |
3691 | ||
3692 | len -= size; | |
3693 | offset += size; | |
3694 | count++; | |
3695 | i++; | |
3696 | if (i == tx_ring->count) | |
3697 | i = 0; | |
3698 | } | |
3699 | } | |
3700 | if (i == 0) | |
3701 | i = tx_ring->count - 1; | |
3702 | else | |
3703 | i = i - 1; | |
3704 | tx_ring->tx_buffer_info[i].skb = skb; | |
3705 | tx_ring->tx_buffer_info[first].next_to_watch = i; | |
3706 | ||
3707 | return count; | |
3708 | } | |
3709 | ||
3710 | static void ixgbe_tx_queue(struct ixgbe_adapter *adapter, | |
b4617240 PW |
3711 | struct ixgbe_ring *tx_ring, |
3712 | int tx_flags, int count, u32 paylen, u8 hdr_len) | |
9a799d71 AK |
3713 | { |
3714 | union ixgbe_adv_tx_desc *tx_desc = NULL; | |
3715 | struct ixgbe_tx_buffer *tx_buffer_info; | |
3716 | u32 olinfo_status = 0, cmd_type_len = 0; | |
3717 | unsigned int i; | |
3718 | u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS; | |
3719 | ||
3720 | cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA; | |
3721 | ||
3722 | cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT; | |
3723 | ||
3724 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
3725 | cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE; | |
3726 | ||
3727 | if (tx_flags & IXGBE_TX_FLAGS_TSO) { | |
3728 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
3729 | ||
3730 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 3731 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 3732 | |
4eeae6fd PW |
3733 | /* use index 1 context for tso */ |
3734 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
3735 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) |
3736 | olinfo_status |= IXGBE_TXD_POPTS_IXSM << | |
b4617240 | 3737 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 AK |
3738 | |
3739 | } else if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
3740 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 3741 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 AK |
3742 | |
3743 | olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT); | |
3744 | ||
3745 | i = tx_ring->next_to_use; | |
3746 | while (count--) { | |
3747 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
3748 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); | |
3749 | tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma); | |
3750 | tx_desc->read.cmd_type_len = | |
b4617240 | 3751 | cpu_to_le32(cmd_type_len | tx_buffer_info->length); |
9a799d71 | 3752 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
9a799d71 AK |
3753 | i++; |
3754 | if (i == tx_ring->count) | |
3755 | i = 0; | |
3756 | } | |
3757 | ||
3758 | tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd); | |
3759 | ||
3760 | /* | |
3761 | * Force memory writes to complete before letting h/w | |
3762 | * know there are new descriptors to fetch. (Only | |
3763 | * applicable for weak-ordered memory model archs, | |
3764 | * such as IA-64). | |
3765 | */ | |
3766 | wmb(); | |
3767 | ||
3768 | tx_ring->next_to_use = i; | |
3769 | writel(i, adapter->hw.hw_addr + tx_ring->tail); | |
3770 | } | |
3771 | ||
e092be60 | 3772 | static int __ixgbe_maybe_stop_tx(struct net_device *netdev, |
b4617240 | 3773 | struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
3774 | { |
3775 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3776 | ||
30eba97a | 3777 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
e092be60 AV |
3778 | /* Herbert's original patch had: |
3779 | * smp_mb__after_netif_stop_queue(); | |
3780 | * but since that doesn't exist yet, just open code it. */ | |
3781 | smp_mb(); | |
3782 | ||
3783 | /* We need to check again in a case another CPU has just | |
3784 | * made room available. */ | |
3785 | if (likely(IXGBE_DESC_UNUSED(tx_ring) < size)) | |
3786 | return -EBUSY; | |
3787 | ||
3788 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
af72166f | 3789 | netif_start_subqueue(netdev, tx_ring->queue_index); |
e092be60 AV |
3790 | ++adapter->restart_queue; |
3791 | return 0; | |
3792 | } | |
3793 | ||
3794 | static int ixgbe_maybe_stop_tx(struct net_device *netdev, | |
b4617240 | 3795 | struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
3796 | { |
3797 | if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size)) | |
3798 | return 0; | |
3799 | return __ixgbe_maybe_stop_tx(netdev, tx_ring, size); | |
3800 | } | |
3801 | ||
9a799d71 AK |
3802 | static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev) |
3803 | { | |
3804 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3805 | struct ixgbe_ring *tx_ring; | |
9a799d71 AK |
3806 | unsigned int first; |
3807 | unsigned int tx_flags = 0; | |
30eba97a AV |
3808 | u8 hdr_len = 0; |
3809 | int r_idx = 0, tso; | |
9a799d71 AK |
3810 | int count = 0; |
3811 | unsigned int f; | |
9f8cdf4f | 3812 | |
30eba97a | 3813 | r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping; |
30eba97a | 3814 | tx_ring = &adapter->tx_ring[r_idx]; |
9a799d71 | 3815 | |
9f8cdf4f JB |
3816 | if (adapter->vlgrp && vlan_tx_tag_present(skb)) { |
3817 | tx_flags |= vlan_tx_tag_get(skb); | |
2f90b865 AD |
3818 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
3819 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; | |
3820 | tx_flags |= (skb->queue_mapping << 13); | |
3821 | } | |
3822 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; | |
3823 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
3824 | } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
3825 | tx_flags |= (skb->queue_mapping << 13); | |
9f8cdf4f JB |
3826 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; |
3827 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
9a799d71 | 3828 | } |
9f8cdf4f JB |
3829 | /* three things can cause us to need a context descriptor */ |
3830 | if (skb_is_gso(skb) || | |
3831 | (skb->ip_summed == CHECKSUM_PARTIAL) || | |
3832 | (tx_flags & IXGBE_TX_FLAGS_VLAN)) | |
9a799d71 AK |
3833 | count++; |
3834 | ||
9f8cdf4f JB |
3835 | count += TXD_USE_COUNT(skb_headlen(skb)); |
3836 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
9a799d71 AK |
3837 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); |
3838 | ||
e092be60 | 3839 | if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) { |
9a799d71 | 3840 | adapter->tx_busy++; |
9a799d71 AK |
3841 | return NETDEV_TX_BUSY; |
3842 | } | |
9a799d71 | 3843 | |
8327d000 | 3844 | if (skb->protocol == htons(ETH_P_IP)) |
9a799d71 AK |
3845 | tx_flags |= IXGBE_TX_FLAGS_IPV4; |
3846 | first = tx_ring->next_to_use; | |
3847 | tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
3848 | if (tso < 0) { | |
3849 | dev_kfree_skb_any(skb); | |
3850 | return NETDEV_TX_OK; | |
3851 | } | |
3852 | ||
3853 | if (tso) | |
3854 | tx_flags |= IXGBE_TX_FLAGS_TSO; | |
3855 | else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) && | |
b4617240 | 3856 | (skb->ip_summed == CHECKSUM_PARTIAL)) |
9a799d71 AK |
3857 | tx_flags |= IXGBE_TX_FLAGS_CSUM; |
3858 | ||
3859 | ixgbe_tx_queue(adapter, tx_ring, tx_flags, | |
b4617240 PW |
3860 | ixgbe_tx_map(adapter, tx_ring, skb, first), |
3861 | skb->len, hdr_len); | |
9a799d71 AK |
3862 | |
3863 | netdev->trans_start = jiffies; | |
3864 | ||
e092be60 | 3865 | ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED); |
9a799d71 AK |
3866 | |
3867 | return NETDEV_TX_OK; | |
3868 | } | |
3869 | ||
3870 | /** | |
3871 | * ixgbe_get_stats - Get System Network Statistics | |
3872 | * @netdev: network interface device structure | |
3873 | * | |
3874 | * Returns the address of the device statistics structure. | |
3875 | * The statistics are actually updated from the timer callback. | |
3876 | **/ | |
3877 | static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev) | |
3878 | { | |
3879 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3880 | ||
3881 | /* only return the current stats */ | |
3882 | return &adapter->net_stats; | |
3883 | } | |
3884 | ||
3885 | /** | |
3886 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
3887 | * @netdev: network interface device structure | |
3888 | * @p: pointer to an address structure | |
3889 | * | |
3890 | * Returns 0 on success, negative on failure | |
3891 | **/ | |
3892 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
3893 | { | |
3894 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 3895 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
3896 | struct sockaddr *addr = p; |
3897 | ||
3898 | if (!is_valid_ether_addr(addr->sa_data)) | |
3899 | return -EADDRNOTAVAIL; | |
3900 | ||
3901 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 3902 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 3903 | |
b4617240 | 3904 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
9a799d71 AK |
3905 | |
3906 | return 0; | |
3907 | } | |
3908 | ||
3909 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3910 | /* | |
3911 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
3912 | * without having to re-enable interrupts. It's not called while | |
3913 | * the interrupt routine is executing. | |
3914 | */ | |
3915 | static void ixgbe_netpoll(struct net_device *netdev) | |
3916 | { | |
3917 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3918 | ||
3919 | disable_irq(adapter->pdev->irq); | |
3920 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; | |
3921 | ixgbe_intr(adapter->pdev->irq, netdev); | |
3922 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; | |
3923 | enable_irq(adapter->pdev->irq); | |
3924 | } | |
3925 | #endif | |
3926 | ||
c44ade9e JB |
3927 | /** |
3928 | * ixgbe_link_config - set up initial link with default speed and duplex | |
3929 | * @hw: pointer to private hardware struct | |
3930 | * | |
3931 | * Returns 0 on success, negative on failure | |
3932 | **/ | |
3933 | static int ixgbe_link_config(struct ixgbe_hw *hw) | |
3934 | { | |
3935 | u32 autoneg = IXGBE_LINK_SPEED_10GB_FULL; | |
3936 | ||
3937 | /* must always autoneg for both 1G and 10G link */ | |
3938 | hw->mac.autoneg = true; | |
3939 | ||
0befdb3e JB |
3940 | if ((hw->mac.type == ixgbe_mac_82598EB) && |
3941 | (hw->phy.media_type == ixgbe_media_type_copper)) | |
3942 | autoneg = IXGBE_LINK_SPEED_82598_AUTONEG; | |
3943 | ||
c44ade9e JB |
3944 | return hw->mac.ops.setup_link_speed(hw, autoneg, true, true); |
3945 | } | |
3946 | ||
0edc3527 SH |
3947 | static const struct net_device_ops ixgbe_netdev_ops = { |
3948 | .ndo_open = ixgbe_open, | |
3949 | .ndo_stop = ixgbe_close, | |
00829823 | 3950 | .ndo_start_xmit = ixgbe_xmit_frame, |
0edc3527 SH |
3951 | .ndo_get_stats = ixgbe_get_stats, |
3952 | .ndo_set_multicast_list = ixgbe_set_rx_mode, | |
3953 | .ndo_validate_addr = eth_validate_addr, | |
3954 | .ndo_set_mac_address = ixgbe_set_mac, | |
3955 | .ndo_change_mtu = ixgbe_change_mtu, | |
3956 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
3957 | .ndo_vlan_rx_register = ixgbe_vlan_rx_register, | |
3958 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, | |
3959 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
3960 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3961 | .ndo_poll_controller = ixgbe_netpoll, | |
3962 | #endif | |
3963 | }; | |
3964 | ||
9a799d71 AK |
3965 | /** |
3966 | * ixgbe_probe - Device Initialization Routine | |
3967 | * @pdev: PCI device information struct | |
3968 | * @ent: entry in ixgbe_pci_tbl | |
3969 | * | |
3970 | * Returns 0 on success, negative on failure | |
3971 | * | |
3972 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
3973 | * The OS initialization, configuring of the adapter private structure, | |
3974 | * and a hardware reset occur. | |
3975 | **/ | |
3976 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
b4617240 | 3977 | const struct pci_device_id *ent) |
9a799d71 AK |
3978 | { |
3979 | struct net_device *netdev; | |
3980 | struct ixgbe_adapter *adapter = NULL; | |
3981 | struct ixgbe_hw *hw; | |
3982 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
3983 | static int cards_found; |
3984 | int i, err, pci_using_dac; | |
3985 | u16 link_status, link_speed, link_width; | |
c44ade9e | 3986 | u32 part_num, eec; |
9a799d71 AK |
3987 | |
3988 | err = pci_enable_device(pdev); | |
3989 | if (err) | |
3990 | return err; | |
3991 | ||
3992 | if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) && | |
3993 | !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) { | |
3994 | pci_using_dac = 1; | |
3995 | } else { | |
3996 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
3997 | if (err) { | |
3998 | err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
3999 | if (err) { | |
b4617240 PW |
4000 | dev_err(&pdev->dev, "No usable DMA " |
4001 | "configuration, aborting\n"); | |
9a799d71 AK |
4002 | goto err_dma; |
4003 | } | |
4004 | } | |
4005 | pci_using_dac = 0; | |
4006 | } | |
4007 | ||
4008 | err = pci_request_regions(pdev, ixgbe_driver_name); | |
4009 | if (err) { | |
4010 | dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err); | |
4011 | goto err_pci_reg; | |
4012 | } | |
4013 | ||
4014 | pci_set_master(pdev); | |
fb3b27bc | 4015 | pci_save_state(pdev); |
9a799d71 | 4016 | |
30eba97a | 4017 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES); |
9a799d71 AK |
4018 | if (!netdev) { |
4019 | err = -ENOMEM; | |
4020 | goto err_alloc_etherdev; | |
4021 | } | |
4022 | ||
9a799d71 AK |
4023 | SET_NETDEV_DEV(netdev, &pdev->dev); |
4024 | ||
4025 | pci_set_drvdata(pdev, netdev); | |
4026 | adapter = netdev_priv(netdev); | |
4027 | ||
4028 | adapter->netdev = netdev; | |
4029 | adapter->pdev = pdev; | |
4030 | hw = &adapter->hw; | |
4031 | hw->back = adapter; | |
4032 | adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1; | |
4033 | ||
05857980 JK |
4034 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
4035 | pci_resource_len(pdev, 0)); | |
9a799d71 AK |
4036 | if (!hw->hw_addr) { |
4037 | err = -EIO; | |
4038 | goto err_ioremap; | |
4039 | } | |
4040 | ||
4041 | for (i = 1; i <= 5; i++) { | |
4042 | if (pci_resource_len(pdev, i) == 0) | |
4043 | continue; | |
4044 | } | |
4045 | ||
0edc3527 | 4046 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 4047 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 4048 | netdev->watchdog_timeo = 5 * HZ; |
9a799d71 AK |
4049 | strcpy(netdev->name, pci_name(pdev)); |
4050 | ||
9a799d71 AK |
4051 | adapter->bd_number = cards_found; |
4052 | ||
9a799d71 AK |
4053 | /* Setup hw api */ |
4054 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 4055 | hw->mac.type = ii->mac; |
9a799d71 | 4056 | |
c44ade9e JB |
4057 | /* EEPROM */ |
4058 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
4059 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
4060 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
4061 | if (!(eec & (1 << 8))) | |
4062 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
4063 | ||
4064 | /* PHY */ | |
4065 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 DS |
4066 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
4067 | ||
4068 | /* set up this timer and work struct before calling get_invariants | |
4069 | * which might start the timer | |
4070 | */ | |
4071 | init_timer(&adapter->sfp_timer); | |
4072 | adapter->sfp_timer.function = &ixgbe_sfp_timer; | |
4073 | adapter->sfp_timer.data = (unsigned long) adapter; | |
4074 | ||
4075 | INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task); | |
c44ade9e | 4076 | |
9a799d71 | 4077 | err = ii->get_invariants(hw); |
c4900be0 DS |
4078 | if (err == IXGBE_ERR_SFP_NOT_PRESENT) { |
4079 | /* start a kernel thread to watch for a module to arrive */ | |
4080 | set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
4081 | mod_timer(&adapter->sfp_timer, | |
4082 | round_jiffies(jiffies + (2 * HZ))); | |
4083 | err = 0; | |
4084 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
4085 | DPRINTK(PROBE, ERR, "failed to load because an " | |
4086 | "unsupported SFP+ module type was detected.\n"); | |
9a799d71 | 4087 | goto err_hw_init; |
c4900be0 DS |
4088 | } else if (err) { |
4089 | goto err_hw_init; | |
4090 | } | |
9a799d71 AK |
4091 | |
4092 | /* setup the private structure */ | |
4093 | err = ixgbe_sw_init(adapter); | |
4094 | if (err) | |
4095 | goto err_sw_init; | |
4096 | ||
c44ade9e JB |
4097 | /* reset_hw fills in the perm_addr as well */ |
4098 | err = hw->mac.ops.reset_hw(hw); | |
4099 | if (err) { | |
4100 | dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err); | |
4101 | goto err_sw_init; | |
4102 | } | |
4103 | ||
9a799d71 | 4104 | netdev->features = NETIF_F_SG | |
b4617240 PW |
4105 | NETIF_F_IP_CSUM | |
4106 | NETIF_F_HW_VLAN_TX | | |
4107 | NETIF_F_HW_VLAN_RX | | |
4108 | NETIF_F_HW_VLAN_FILTER; | |
9a799d71 | 4109 | |
e9990a9c | 4110 | netdev->features |= NETIF_F_IPV6_CSUM; |
9a799d71 | 4111 | netdev->features |= NETIF_F_TSO; |
9a799d71 | 4112 | netdev->features |= NETIF_F_TSO6; |
e9990a9c | 4113 | netdev->features |= NETIF_F_LRO; |
ad31c402 JK |
4114 | |
4115 | netdev->vlan_features |= NETIF_F_TSO; | |
4116 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 4117 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
ad31c402 JK |
4118 | netdev->vlan_features |= NETIF_F_SG; |
4119 | ||
2f90b865 AD |
4120 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) |
4121 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
4122 | ||
7a6b6f51 | 4123 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
4124 | netdev->dcbnl_ops = &dcbnl_ops; |
4125 | #endif | |
4126 | ||
9a799d71 AK |
4127 | if (pci_using_dac) |
4128 | netdev->features |= NETIF_F_HIGHDMA; | |
4129 | ||
9a799d71 | 4130 | /* make sure the EEPROM is good */ |
c44ade9e | 4131 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
9a799d71 AK |
4132 | dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n"); |
4133 | err = -EIO; | |
4134 | goto err_eeprom; | |
4135 | } | |
4136 | ||
4137 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
4138 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
4139 | ||
c44ade9e JB |
4140 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
4141 | dev_err(&pdev->dev, "invalid MAC address\n"); | |
9a799d71 AK |
4142 | err = -EIO; |
4143 | goto err_eeprom; | |
4144 | } | |
4145 | ||
4146 | init_timer(&adapter->watchdog_timer); | |
4147 | adapter->watchdog_timer.function = &ixgbe_watchdog; | |
4148 | adapter->watchdog_timer.data = (unsigned long)adapter; | |
4149 | ||
4150 | INIT_WORK(&adapter->reset_task, ixgbe_reset_task); | |
cf8280ee | 4151 | INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task); |
9a799d71 | 4152 | |
021230d4 AV |
4153 | err = ixgbe_init_interrupt_scheme(adapter); |
4154 | if (err) | |
4155 | goto err_sw_init; | |
9a799d71 AK |
4156 | |
4157 | /* print bus type/speed/width info */ | |
4158 | pci_read_config_word(pdev, IXGBE_PCI_LINK_STATUS, &link_status); | |
4159 | link_speed = link_status & IXGBE_PCI_LINK_SPEED; | |
4160 | link_width = link_status & IXGBE_PCI_LINK_WIDTH; | |
7c510e4b | 4161 | dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n", |
b4617240 PW |
4162 | ((link_speed == IXGBE_PCI_LINK_SPEED_5000) ? "5.0Gb/s" : |
4163 | (link_speed == IXGBE_PCI_LINK_SPEED_2500) ? "2.5Gb/s" : | |
4164 | "Unknown"), | |
4165 | ((link_width == IXGBE_PCI_LINK_WIDTH_8) ? "Width x8" : | |
4166 | (link_width == IXGBE_PCI_LINK_WIDTH_4) ? "Width x4" : | |
4167 | (link_width == IXGBE_PCI_LINK_WIDTH_2) ? "Width x2" : | |
4168 | (link_width == IXGBE_PCI_LINK_WIDTH_1) ? "Width x1" : | |
4169 | "Unknown"), | |
7c510e4b | 4170 | netdev->dev_addr); |
c44ade9e | 4171 | ixgbe_read_pba_num_generic(hw, &part_num); |
9a799d71 | 4172 | dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n", |
b4617240 PW |
4173 | hw->mac.type, hw->phy.type, |
4174 | (part_num >> 8), (part_num & 0xff)); | |
9a799d71 | 4175 | |
0c254d86 AK |
4176 | if (link_width <= IXGBE_PCI_LINK_WIDTH_4) { |
4177 | dev_warn(&pdev->dev, "PCI-Express bandwidth available for " | |
b4617240 PW |
4178 | "this card is not sufficient for optimal " |
4179 | "performance.\n"); | |
0c254d86 | 4180 | dev_warn(&pdev->dev, "For optimal performance a x8 " |
b4617240 | 4181 | "PCI-Express slot is required.\n"); |
0c254d86 AK |
4182 | } |
4183 | ||
9a799d71 | 4184 | /* reset the hardware with the new settings */ |
c44ade9e JB |
4185 | hw->mac.ops.start_hw(hw); |
4186 | ||
4187 | /* link_config depends on start_hw being called at least once */ | |
4188 | err = ixgbe_link_config(hw); | |
4189 | if (err) { | |
4190 | dev_err(&pdev->dev, "setup_link_speed FAILED %d\n", err); | |
4191 | goto err_register; | |
4192 | } | |
9a799d71 AK |
4193 | |
4194 | netif_carrier_off(netdev); | |
2f90b865 | 4195 | netif_tx_stop_all_queues(netdev); |
9a799d71 | 4196 | |
021230d4 AV |
4197 | ixgbe_napi_add_all(adapter); |
4198 | ||
9a799d71 AK |
4199 | strcpy(netdev->name, "eth%d"); |
4200 | err = register_netdev(netdev); | |
4201 | if (err) | |
4202 | goto err_register; | |
4203 | ||
5dd2d332 | 4204 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 4205 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd JC |
4206 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
4207 | /* always use CB2 mode, difference is masked | |
4208 | * in the CB driver */ | |
4209 | IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2); | |
4210 | ixgbe_setup_dca(adapter); | |
4211 | } | |
4212 | #endif | |
9a799d71 AK |
4213 | |
4214 | dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n"); | |
4215 | cards_found++; | |
4216 | return 0; | |
4217 | ||
4218 | err_register: | |
5eba3699 | 4219 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
4220 | err_hw_init: |
4221 | err_sw_init: | |
021230d4 | 4222 | ixgbe_reset_interrupt_capability(adapter); |
9a799d71 | 4223 | err_eeprom: |
c4900be0 DS |
4224 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); |
4225 | del_timer_sync(&adapter->sfp_timer); | |
4226 | cancel_work_sync(&adapter->sfp_task); | |
9a799d71 AK |
4227 | iounmap(hw->hw_addr); |
4228 | err_ioremap: | |
4229 | free_netdev(netdev); | |
4230 | err_alloc_etherdev: | |
4231 | pci_release_regions(pdev); | |
4232 | err_pci_reg: | |
4233 | err_dma: | |
4234 | pci_disable_device(pdev); | |
4235 | return err; | |
4236 | } | |
4237 | ||
4238 | /** | |
4239 | * ixgbe_remove - Device Removal Routine | |
4240 | * @pdev: PCI device information struct | |
4241 | * | |
4242 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
4243 | * that it should release a PCI device. The could be caused by a | |
4244 | * Hot-Plug event, or because the driver is going to be removed from | |
4245 | * memory. | |
4246 | **/ | |
4247 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
4248 | { | |
4249 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4250 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4251 | ||
4252 | set_bit(__IXGBE_DOWN, &adapter->state); | |
c4900be0 DS |
4253 | /* clear the module not found bit to make sure the worker won't |
4254 | * reschedule | |
4255 | */ | |
4256 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
9a799d71 AK |
4257 | del_timer_sync(&adapter->watchdog_timer); |
4258 | ||
c4900be0 DS |
4259 | del_timer_sync(&adapter->sfp_timer); |
4260 | cancel_work_sync(&adapter->watchdog_task); | |
4261 | cancel_work_sync(&adapter->sfp_task); | |
9a799d71 AK |
4262 | flush_scheduled_work(); |
4263 | ||
5dd2d332 | 4264 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
4265 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
4266 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
4267 | dca_remove_requester(&pdev->dev); | |
4268 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
4269 | } | |
4270 | ||
4271 | #endif | |
c4900be0 DS |
4272 | if (netdev->reg_state == NETREG_REGISTERED) |
4273 | unregister_netdev(netdev); | |
9a799d71 | 4274 | |
021230d4 | 4275 | ixgbe_reset_interrupt_capability(adapter); |
5eba3699 | 4276 | |
021230d4 | 4277 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
4278 | |
4279 | iounmap(adapter->hw.hw_addr); | |
4280 | pci_release_regions(pdev); | |
4281 | ||
021230d4 | 4282 | DPRINTK(PROBE, INFO, "complete\n"); |
b3c8b4ba | 4283 | ixgbe_napi_del_all(adapter); |
021230d4 AV |
4284 | kfree(adapter->tx_ring); |
4285 | kfree(adapter->rx_ring); | |
4286 | ||
9a799d71 AK |
4287 | free_netdev(netdev); |
4288 | ||
4289 | pci_disable_device(pdev); | |
4290 | } | |
4291 | ||
4292 | /** | |
4293 | * ixgbe_io_error_detected - called when PCI error is detected | |
4294 | * @pdev: Pointer to PCI device | |
4295 | * @state: The current pci connection state | |
4296 | * | |
4297 | * This function is called after a PCI bus error affecting | |
4298 | * this device has been detected. | |
4299 | */ | |
4300 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
b4617240 | 4301 | pci_channel_state_t state) |
9a799d71 AK |
4302 | { |
4303 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 4304 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
4305 | |
4306 | netif_device_detach(netdev); | |
4307 | ||
4308 | if (netif_running(netdev)) | |
4309 | ixgbe_down(adapter); | |
4310 | pci_disable_device(pdev); | |
4311 | ||
b4617240 | 4312 | /* Request a slot reset. */ |
9a799d71 AK |
4313 | return PCI_ERS_RESULT_NEED_RESET; |
4314 | } | |
4315 | ||
4316 | /** | |
4317 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
4318 | * @pdev: Pointer to PCI device | |
4319 | * | |
4320 | * Restart the card from scratch, as if from a cold-boot. | |
4321 | */ | |
4322 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
4323 | { | |
4324 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 4325 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
4326 | |
4327 | if (pci_enable_device(pdev)) { | |
4328 | DPRINTK(PROBE, ERR, | |
b4617240 | 4329 | "Cannot re-enable PCI device after reset.\n"); |
9a799d71 AK |
4330 | return PCI_ERS_RESULT_DISCONNECT; |
4331 | } | |
4332 | pci_set_master(pdev); | |
fb3b27bc | 4333 | pci_restore_state(pdev); |
9a799d71 AK |
4334 | |
4335 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
4336 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
4337 | ||
4338 | ixgbe_reset(adapter); | |
4339 | ||
4340 | return PCI_ERS_RESULT_RECOVERED; | |
4341 | } | |
4342 | ||
4343 | /** | |
4344 | * ixgbe_io_resume - called when traffic can start flowing again. | |
4345 | * @pdev: Pointer to PCI device | |
4346 | * | |
4347 | * This callback is called when the error recovery driver tells us that | |
4348 | * its OK to resume normal operation. | |
4349 | */ | |
4350 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
4351 | { | |
4352 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 4353 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
4354 | |
4355 | if (netif_running(netdev)) { | |
4356 | if (ixgbe_up(adapter)) { | |
4357 | DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n"); | |
4358 | return; | |
4359 | } | |
4360 | } | |
4361 | ||
4362 | netif_device_attach(netdev); | |
9a799d71 AK |
4363 | } |
4364 | ||
4365 | static struct pci_error_handlers ixgbe_err_handler = { | |
4366 | .error_detected = ixgbe_io_error_detected, | |
4367 | .slot_reset = ixgbe_io_slot_reset, | |
4368 | .resume = ixgbe_io_resume, | |
4369 | }; | |
4370 | ||
4371 | static struct pci_driver ixgbe_driver = { | |
4372 | .name = ixgbe_driver_name, | |
4373 | .id_table = ixgbe_pci_tbl, | |
4374 | .probe = ixgbe_probe, | |
4375 | .remove = __devexit_p(ixgbe_remove), | |
4376 | #ifdef CONFIG_PM | |
4377 | .suspend = ixgbe_suspend, | |
4378 | .resume = ixgbe_resume, | |
4379 | #endif | |
4380 | .shutdown = ixgbe_shutdown, | |
4381 | .err_handler = &ixgbe_err_handler | |
4382 | }; | |
4383 | ||
4384 | /** | |
4385 | * ixgbe_init_module - Driver Registration Routine | |
4386 | * | |
4387 | * ixgbe_init_module is the first routine called when the driver is | |
4388 | * loaded. All it does is register with the PCI subsystem. | |
4389 | **/ | |
4390 | static int __init ixgbe_init_module(void) | |
4391 | { | |
4392 | int ret; | |
4393 | printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name, | |
4394 | ixgbe_driver_string, ixgbe_driver_version); | |
4395 | ||
4396 | printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright); | |
4397 | ||
5dd2d332 | 4398 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 4399 | dca_register_notify(&dca_notifier); |
bd0362dd | 4400 | #endif |
5dd2d332 | 4401 | |
9a799d71 AK |
4402 | ret = pci_register_driver(&ixgbe_driver); |
4403 | return ret; | |
4404 | } | |
b4617240 | 4405 | |
9a799d71 AK |
4406 | module_init(ixgbe_init_module); |
4407 | ||
4408 | /** | |
4409 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
4410 | * | |
4411 | * ixgbe_exit_module is called just before the driver is removed | |
4412 | * from memory. | |
4413 | **/ | |
4414 | static void __exit ixgbe_exit_module(void) | |
4415 | { | |
5dd2d332 | 4416 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
4417 | dca_unregister_notify(&dca_notifier); |
4418 | #endif | |
9a799d71 AK |
4419 | pci_unregister_driver(&ixgbe_driver); |
4420 | } | |
bd0362dd | 4421 | |
5dd2d332 | 4422 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 4423 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
b4617240 | 4424 | void *p) |
bd0362dd JC |
4425 | { |
4426 | int ret_val; | |
4427 | ||
4428 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
b4617240 | 4429 | __ixgbe_notify_dca); |
bd0362dd JC |
4430 | |
4431 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
4432 | } | |
5dd2d332 | 4433 | #endif /* CONFIG_IXGBE_DCA */ |
bd0362dd | 4434 | |
9a799d71 AK |
4435 | module_exit(ixgbe_exit_module); |
4436 | ||
4437 | /* ixgbe_main.c */ |