projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ixgbe: In SR-IOV mode insert delay before bring the adapter up
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71
AK		 38#include <linux/ipv6.h>
39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
41#include <linux/ethtool.h>
42#include <linux/if_vlan.h>
eacd73f7 43#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 44
45#include "ixgbe.h"
46#include "ixgbe_common.h"
ee5f784a 47#include "ixgbe_dcb_82599.h"
1cdd1ec8 48#include "ixgbe_sriov.h"
9a799d71
AK		 49
50char ixgbe_driver_name[] = "ixgbe";
9c8eb720 51static const char ixgbe_driver_string[] =
b4617240 52 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 53
92eb879f 54#define DRV_VERSION "2.0.62-k2"
9c8eb720 55const char ixgbe_driver_version[] = DRV_VERSION;
8c47eaa7 56static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
9a799d71
AK		 57
58static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 59 [board_82598] = &ixgbe_82598_info,
e8e26350 60 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 61};
62
63/* ixgbe_pci_tbl - PCI Device ID Table
64 *
65 * Wildcard entries (PCI_ANY_ID) should come last
66 * Last entry must be all 0s
67 *
68 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
69 * Class, Class Mask, private data (not used) }
70 */
a3aa1884 71static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
73 board_82598 },
9a799d71 74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 75 board_82598 },
9a799d71 76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 77 board_82598 },
0befdb3e
JB		 78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
79 board_82598 },
3845bec0
PWJ		 80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
81 board_82598 },
9a799d71 82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 83 board_82598 },
8d792cd9
JB		 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
85 board_82598 },
c4900be0
DS		 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
87 board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
89 board_82598 },
b95f5fcb
JB		 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
91 board_82598 },
c4900be0
DS		 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
93 board_82598 },
2f21bdd3
DS		 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
95 board_82598 },
e8e26350
PW		 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
97 board_82599 },
1fcf03e6
PWJ		 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
99 board_82599 },
74757d49
DS		 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
101 board_82599 },
e8e26350
PW		 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
103 board_82599 },
38ad1c8e
DS		 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
105 board_82599 },
dbfec662
DS		 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
107 board_82599 },
8911184f
PWJ		 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
109 board_82599 },
312eb931
DS		 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
111 board_82599 },
9a799d71
AK		 112
113 /* required last entry */
114 {0, }
115};
116MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
117
5dd2d332 118#ifdef CONFIG_IXGBE_DCA
bd0362dd 119static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 120 void *p);
bd0362dd
JC		 121static struct notifier_block dca_notifier = {
122 .notifier_call = ixgbe_notify_dca,
123 .next = NULL,
124 .priority = 0
125};
126#endif
127
1cdd1ec8
GR		 128#ifdef CONFIG_PCI_IOV
129static unsigned int max_vfs;
130module_param(max_vfs, uint, 0);
131MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
132 "per physical function");
133#endif /* CONFIG_PCI_IOV */
134
9a799d71
AK		 135MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
136MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
137MODULE_LICENSE("GPL");
138MODULE_VERSION(DRV_VERSION);
139
140#define DEFAULT_DEBUG_LEVEL_SHIFT 3
141
1cdd1ec8
GR		 142static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
143{
144 struct ixgbe_hw *hw = &adapter->hw;
145 u32 gcr;
146 u32 gpie;
147 u32 vmdctl;
148
149#ifdef CONFIG_PCI_IOV
150 /* disable iov and allow time for transactions to clear */
151 pci_disable_sriov(adapter->pdev);
152#endif
153
154 /* turn off device IOV mode */
155 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
156 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
157 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
158 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
159 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
160 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
161
162 /* set default pool back to 0 */
163 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
164 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
165 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
166
167 /* take a breather then clean up driver data */
168 msleep(100);
169 if (adapter->vfinfo)
170 kfree(adapter->vfinfo);
171 adapter->vfinfo = NULL;
172
173 adapter->num_vfs = 0;
174 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
175}
176
5eba3699
AV		 177static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
178{
179 u32 ctrl_ext;
180
181 /* Let firmware take over control of h/w */
182 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
183 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 184 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 185}
186
187static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
188{
189 u32 ctrl_ext;
190
191 /* Let firmware know the driver has taken over */
192 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
193 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 194 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 195}
9a799d71 196
e8e26350
PW		 197/*
198 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
199 * @adapter: pointer to adapter struct
200 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
201 * @queue: queue to map the corresponding interrupt to
202 * @msix_vector: the vector to map to the corresponding queue
203 *
204 */
205static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
206 u8 queue, u8 msix_vector)
9a799d71
AK		 207{
208 u32 ivar, index;
e8e26350
PW		 209 struct ixgbe_hw *hw = &adapter->hw;
210 switch (hw->mac.type) {
211 case ixgbe_mac_82598EB:
212 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
213 if (direction == -1)
214 direction = 0;
215 index = (((direction * 64) + queue) >> 2) & 0x1F;
216 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
217 ivar &= ~(0xFF << (8 * (queue & 0x3)));
218 ivar |= (msix_vector << (8 * (queue & 0x3)));
219 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
220 break;
221 case ixgbe_mac_82599EB:
222 if (direction == -1) {
223 /* other causes */
224 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
225 index = ((queue & 1) * 8);
226 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
227 ivar &= ~(0xFF << index);
228 ivar |= (msix_vector << index);
229 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
230 break;
231 } else {
232 /* tx or rx causes */
233 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
234 index = ((16 * (queue & 1)) + (8 * direction));
235 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
236 ivar &= ~(0xFF << index);
237 ivar |= (msix_vector << index);
238 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
239 break;
240 }
241 default:
242 break;
243 }
9a799d71
AK		 244}
245
fe49f04a
AD		 246static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
247 u64 qmask)
248{
249 u32 mask;
250
251 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
252 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
253 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
254 } else {
255 mask = (qmask & 0xFFFFFFFF);
256 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
257 mask = (qmask >> 32);
258 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
259 }
260}
261
9a799d71 262static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 263 struct ixgbe_tx_buffer
264 *tx_buffer_info)
9a799d71 265{
e5a43549
AD		 266 if (tx_buffer_info->dma) {
267 if (tx_buffer_info->mapped_as_page)
268 pci_unmap_page(adapter->pdev,
269 tx_buffer_info->dma,
270 tx_buffer_info->length,
271 PCI_DMA_TODEVICE);
272 else
273 pci_unmap_single(adapter->pdev,
274 tx_buffer_info->dma,
275 tx_buffer_info->length,
276 PCI_DMA_TODEVICE);
277 tx_buffer_info->dma = 0;
278 }
9a799d71
AK		 279 if (tx_buffer_info->skb) {
280 dev_kfree_skb_any(tx_buffer_info->skb);
281 tx_buffer_info->skb = NULL;
282 }
44df32c5 283 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 284 /* tx_buffer_info must be completely set up in the transmit path */
285}
286
26f23d82
YZ		 287/**
288 * ixgbe_tx_is_paused - check if the tx ring is paused
289 * @adapter: the ixgbe adapter
290 * @tx_ring: the corresponding tx_ring
291 *
292 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
293 * corresponding TC of this tx_ring when checking TFCS.
294 *
295 * Returns : true if paused
296 */
297static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
298 struct ixgbe_ring *tx_ring)
299{
26f23d82
YZ		 300 u32 txoff = IXGBE_TFCS_TXOFF;
301
302#ifdef CONFIG_IXGBE_DCB
303 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
30b76832 304 int tc;
26f23d82
YZ		 305 int reg_idx = tx_ring->reg_idx;
306 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
307
6837e895
PW		 308 switch (adapter->hw.mac.type) {
309 case ixgbe_mac_82598EB:
26f23d82
YZ		 310 tc = reg_idx >> 2;
311 txoff = IXGBE_TFCS_TXOFF0;
6837e895
PW		 312 break;
313 case ixgbe_mac_82599EB:
26f23d82
YZ		 314 tc = 0;
315 txoff = IXGBE_TFCS_TXOFF;
316 if (dcb_i == 8) {
317 /* TC0, TC1 */
318 tc = reg_idx >> 5;
319 if (tc == 2) /* TC2, TC3 */
320 tc += (reg_idx - 64) >> 4;
321 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
322 tc += 1 + ((reg_idx - 96) >> 3);
323 } else if (dcb_i == 4) {
324 /* TC0, TC1 */
325 tc = reg_idx >> 6;
326 if (tc == 1) {
327 tc += (reg_idx - 64) >> 5;
328 if (tc == 2) /* TC2, TC3 */
329 tc += (reg_idx - 96) >> 4;
330 }
331 }
6837e895
PW		 332 break;
333 default:
334 tc = 0;
26f23d82
YZ		 335 }
336 txoff <<= tc;
337 }
338#endif
339 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
340}
341
9a799d71 342static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 343 struct ixgbe_ring *tx_ring,
344 unsigned int eop)
9a799d71 345{
e01c31a5 346 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 347
9a799d71 348 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 349 * check with the clearing of time_stamp and movement of eop */
9a799d71 350 adapter->detect_tx_hung = false;
44df32c5 351 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71 352 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
26f23d82 353 !ixgbe_tx_is_paused(adapter, tx_ring)) {
9a799d71 354 /* detected Tx unit hang */
e01c31a5
JB		 355 union ixgbe_adv_tx_desc *tx_desc;
356 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 357 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 358 " Tx Queue <%d>\n"
359 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 360 " next_to_use <%x>\n"
361 " next_to_clean <%x>\n"
362 "tx_buffer_info[next_to_clean]\n"
363 " time_stamp <%lx>\n"
e01c31a5
JB		 364 " jiffies <%lx>\n",
365 tx_ring->queue_index,
44df32c5
AD		 366 IXGBE_READ_REG(hw, tx_ring->head),
367 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 368 tx_ring->next_to_use, eop,
369 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 370 return true;
371 }
372
373 return false;
374}
375
b4617240
PW		 376#define IXGBE_MAX_TXD_PWR 14
377#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 378
379/* Tx Descriptors needed, worst case */
380#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
381 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
382#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 383 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 384
e01c31a5
JB		 385static void ixgbe_tx_timeout(struct net_device *netdev);
386
9a799d71
AK		 387/**
388 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 389 * @q_vector: structure containing interrupt and ring information
e01c31a5 390 * @tx_ring: tx ring to clean
9a799d71 391 **/
fe49f04a 392static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e01c31a5 393 struct ixgbe_ring *tx_ring)
9a799d71 394{
fe49f04a 395 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 396 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 397 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
398 struct ixgbe_tx_buffer *tx_buffer_info;
399 unsigned int i, eop, count = 0;
e01c31a5 400 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 401
402 i = tx_ring->next_to_clean;
12207e49
PWJ		 403 eop = tx_ring->tx_buffer_info[i].next_to_watch;
404 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
405
406 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 407 (count < tx_ring->work_limit)) {
12207e49
PWJ		 408 bool cleaned = false;
409 for ( ; !cleaned; count++) {
410 struct sk_buff *skb;
9a799d71
AK		 411 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
412 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 413 cleaned = (i == eop);
e01c31a5 414 skb = tx_buffer_info->skb;
9a799d71 415
12207e49 416 if (cleaned && skb) {
e092be60 417 unsigned int segs, bytecount;
3d8fd385 418 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 419
420 /* gso_segs is currently only valid for tcp */
e092be60 421 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 422#ifdef IXGBE_FCOE
423 /* adjust for FCoE Sequence Offload */
424 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
425 && (skb->protocol == htons(ETH_P_FCOE)) &&
426 skb_is_gso(skb)) {
427 hlen = skb_transport_offset(skb) +
428 sizeof(struct fc_frame_header) +
429 sizeof(struct fcoe_crc_eof);
430 segs = DIV_ROUND_UP(skb->len - hlen,
431 skb_shinfo(skb)->gso_size);
432 }
433#endif /* IXGBE_FCOE */
e092be60 434 /* multiply data chunks by size of headers */
3d8fd385 435 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 436 total_packets += segs;
437 total_bytes += bytecount;
e092be60 438 }
e01c31a5 439
9a799d71 440 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 441 tx_buffer_info);
9a799d71 442
12207e49
PWJ		 443 tx_desc->wb.status = 0;
444
9a799d71
AK		 445 i++;
446 if (i == tx_ring->count)
447 i = 0;
e01c31a5 448 }
12207e49
PWJ		 449
450 eop = tx_ring->tx_buffer_info[i].next_to_watch;
451 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
452 }
453
9a799d71
AK		 454 tx_ring->next_to_clean = i;
455
e092be60 456#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 457 if (unlikely(count && netif_carrier_ok(netdev) &&
458 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 459 /* Make sure that anybody stopping the queue after this
460 * sees the new next_to_clean.
461 */
462 smp_mb();
30eba97a
AV		 463 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
464 !test_bit(__IXGBE_DOWN, &adapter->state)) {
465 netif_wake_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 466 ++tx_ring->restart_queue;
30eba97a 467 }
e092be60 468 }
9a799d71 469
e01c31a5
JB		 470 if (adapter->detect_tx_hung) {
471 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
472 /* schedule immediate reset if we believe we hung */
473 DPRINTK(PROBE, INFO,
474 "tx hang %d detected, resetting adapter\n",
475 adapter->tx_timeout_count + 1);
476 ixgbe_tx_timeout(adapter->netdev);
477 }
478 }
9a799d71 479
e01c31a5 480 /* re-arm the interrupt */
fe49f04a
AD		 481 if (count >= tx_ring->work_limit)
482 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 483
e01c31a5
JB		 484 tx_ring->total_bytes += total_bytes;
485 tx_ring->total_packets += total_packets;
e01c31a5 486 tx_ring->stats.packets += total_packets;
12207e49 487 tx_ring->stats.bytes += total_bytes;
9a1a69ad 488 return (count < tx_ring->work_limit);
9a799d71
AK		 489}
490
5dd2d332 491#ifdef CONFIG_IXGBE_DCA
bd0362dd 492static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 493 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 494{
495 u32 rxctrl;
496 int cpu = get_cpu();
4a0b9ca0 497 int q = rx_ring->reg_idx;
bd0362dd 498
3a581073 499 if (rx_ring->cpu != cpu) {
bd0362dd 500 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 501 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
502 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
503 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
504 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
505 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
506 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
507 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
508 }
bd0362dd
JC		 509 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
510 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 511 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
512 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 513 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 514 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 515 rx_ring->cpu = cpu;
bd0362dd
JC		 516 }
517 put_cpu();
518}
519
520static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 521 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 522{
523 u32 txctrl;
524 int cpu = get_cpu();
4a0b9ca0 525 int q = tx_ring->reg_idx;
ee5f784a 526 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 527
3a581073 528 if (tx_ring->cpu != cpu) {
e8e26350 529 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
ee5f784a 530 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 531 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
532 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
ee5f784a
DS		 533 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
534 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
e8e26350 535 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
ee5f784a 536 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
e8e26350
PW		 537 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
538 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
ee5f784a
DS		 539 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
540 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
541 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
e8e26350 542 }
3a581073 543 tx_ring->cpu = cpu;
bd0362dd
JC		 544 }
545 put_cpu();
546}
547
548static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
549{
550 int i;
551
552 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
553 return;
554
e35ec126
AD		 555 /* always use CB2 mode, difference is masked in the CB driver */
556 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
557
bd0362dd 558 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 559 adapter->tx_ring[i]->cpu = -1;
560 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
bd0362dd
JC		 561 }
562 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 563 adapter->rx_ring[i]->cpu = -1;
564 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
bd0362dd
JC		 565 }
566}
567
568static int __ixgbe_notify_dca(struct device *dev, void *data)
569{
570 struct net_device *netdev = dev_get_drvdata(dev);
571 struct ixgbe_adapter *adapter = netdev_priv(netdev);
572 unsigned long event = *(unsigned long *)data;
573
574 switch (event) {
575 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 576 /* if we're already enabled, don't do it again */
577 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
578 break;
652f093f 579 if (dca_add_requester(dev) == 0) {
96b0e0f6 580 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 581 ixgbe_setup_dca(adapter);
582 break;
583 }
584 /* Fall Through since DCA is disabled. */
585 case DCA_PROVIDER_REMOVE:
586 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
587 dca_remove_requester(dev);
588 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
589 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
590 }
591 break;
592 }
593
652f093f 594 return 0;
bd0362dd
JC		 595}
596
5dd2d332 597#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 598/**
599 * ixgbe_receive_skb - Send a completed packet up the stack
600 * @adapter: board private structure
601 * @skb: packet to send up
177db6ff
MC		 602 * @status: hardware indication of status of receive
603 * @rx_ring: rx descriptor ring (for a specific queue) to setup
604 * @rx_desc: rx descriptor
9a799d71 605 **/
78b6f4ce 606static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 607 struct sk_buff *skb, u8 status,
fdaff1ce 608 struct ixgbe_ring *ring,
177db6ff 609 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 610{
78b6f4ce
HX		 611 struct ixgbe_adapter *adapter = q_vector->adapter;
612 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 613 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
614 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 615
fdaff1ce 616 skb_record_rx_queue(skb, ring->queue_index);
182ff8df 617 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
8a62babf 618 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
78b6f4ce 619 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 620 else
78b6f4ce 621 napi_gro_receive(napi, skb);
177db6ff 622 } else {
8a62babf 623 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
182ff8df
AD		 624 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
625 else
626 netif_rx(skb);
9a799d71
AK		 627 }
628}
629
e59bd25d
AV		 630/**
631 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
632 * @adapter: address of board private structure
633 * @status_err: hardware indication of status of receive
634 * @skb: skb currently being received and modified
635 **/
9a799d71 636static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 637 union ixgbe_adv_rx_desc *rx_desc,
638 struct sk_buff *skb)
9a799d71 639{
8bae1b2b
DS		 640 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
641
9a799d71
AK		 642 skb->ip_summed = CHECKSUM_NONE;
643
712744be
JB		 644 /* Rx csum disabled */
645 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 646 return;
e59bd25d
AV		 647
648 /* if IP and error */
649 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
650 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 651 adapter->hw_csum_rx_error++;
652 return;
653 }
e59bd25d
AV		 654
655 if (!(status_err & IXGBE_RXD_STAT_L4CS))
656 return;
657
658 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 659 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
660
661 /*
662 * 82599 errata, UDP frames with a 0 checksum can be marked as
663 * checksum errors.
664 */
665 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
666 (adapter->hw.mac.type == ixgbe_mac_82599EB))
667 return;
668
e59bd25d
AV		 669 adapter->hw_csum_rx_error++;
670 return;
671 }
672
9a799d71 673 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 674 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 675}
676
e8e26350
PW		 677static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
678 struct ixgbe_ring *rx_ring, u32 val)
679{
680 /*
681 * Force memory writes to complete before letting h/w
682 * know there are new descriptors to fetch. (Only
683 * applicable for weak-ordered memory model archs,
684 * such as IA-64).
685 */
686 wmb();
687 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
688}
689
9a799d71
AK		 690/**
691 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
692 * @adapter: address of board private structure
693 **/
694static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 695 struct ixgbe_ring *rx_ring,
696 int cleaned_count)
9a799d71 697{
9a799d71
AK		 698 struct pci_dev *pdev = adapter->pdev;
699 union ixgbe_adv_rx_desc *rx_desc;
3a581073 700 struct ixgbe_rx_buffer *bi;
9a799d71 701 unsigned int i;
9a799d71
AK		 702
703 i = rx_ring->next_to_use;
3a581073 704 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 705
706 while (cleaned_count--) {
707 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
708
762f4c57 709 if (!bi->page_dma &&
6e455b89 710 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 711 if (!bi->page) {
762f4c57
JB		 712 bi->page = alloc_page(GFP_ATOMIC);
713 if (!bi->page) {
714 adapter->alloc_rx_page_failed++;
715 goto no_buffers;
716 }
717 bi->page_offset = 0;
718 } else {
719 /* use a half page if we're re-using */
720 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 721 }
762f4c57
JB		 722
723 bi->page_dma = pci_map_page(pdev, bi->page,
724 bi->page_offset,
725 (PAGE_SIZE / 2),
726 PCI_DMA_FROMDEVICE);
9a799d71
AK		 727 }
728
3a581073 729 if (!bi->skb) {
5ecc3614 730 struct sk_buff *skb;
7ca3bc58
JB		 731 /* netdev_alloc_skb reserves 32 bytes up front!! */
732 uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES;
733 skb = netdev_alloc_skb(adapter->netdev, bufsz);
9a799d71
AK		 734
735 if (!skb) {
736 adapter->alloc_rx_buff_failed++;
737 goto no_buffers;
738 }
739
7ca3bc58
JB		 740 /* advance the data pointer to the next cache line */
741 skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES)
742 - skb->data));
743
3a581073 744 bi->skb = skb;
4f57ca6e
JB		 745 bi->dma = pci_map_single(pdev, skb->data,
746 rx_ring->rx_buf_len,
3a581073 747 PCI_DMA_FROMDEVICE);
9a799d71
AK		 748 }
749 /* Refresh the desc even if buffer_addrs didn't change because
750 * each write-back erases this info. */
6e455b89 751 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 752 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
753 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 754 } else {
3a581073 755 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 756 }
757
758 i++;
759 if (i == rx_ring->count)
760 i = 0;
3a581073 761 bi = &rx_ring->rx_buffer_info[i];
9a799d71 762 }
7c6e0a43 763
9a799d71
AK		 764no_buffers:
765 if (rx_ring->next_to_use != i) {
766 rx_ring->next_to_use = i;
767 if (i-- == 0)
768 i = (rx_ring->count - 1);
769
e8e26350 770 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 771 }
772}
773
7c6e0a43
JB		 774static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
775{
776 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
777}
778
779static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
780{
781 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
782}
783
f8212f97
AD		 784static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
785{
786 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
787 IXGBE_RXDADV_RSCCNT_MASK) >>
788 IXGBE_RXDADV_RSCCNT_SHIFT;
789}
790
791/**
792 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
793 * @skb: pointer to the last skb in the rsc queue
94b982b2 794 * @count: pointer to number of packets coalesced in this context
f8212f97
AD		 795 *
796 * This function changes a queue full of hw rsc buffers into a completed
797 * packet. It uses the ->prev pointers to find the first packet and then
798 * turns it into the frag list owner.
799 **/
94b982b2
MC		 800static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
801 u64 *count)
f8212f97
AD		 802{
803 unsigned int frag_list_size = 0;
804
805 while (skb->prev) {
806 struct sk_buff *prev = skb->prev;
807 frag_list_size += skb->len;
808 skb->prev = NULL;
809 skb = prev;
94b982b2 810 *count += 1;
f8212f97
AD		 811 }
812
813 skb_shinfo(skb)->frag_list = skb->next;
814 skb->next = NULL;
815 skb->len += frag_list_size;
816 skb->data_len += frag_list_size;
817 skb->truesize += frag_list_size;
818 return skb;
819}
820
43634e82
MC		 821struct ixgbe_rsc_cb {
822 dma_addr_t dma;
823};
824
825#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
826
78b6f4ce 827static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 828 struct ixgbe_ring *rx_ring,
829 int *work_done, int work_to_do)
9a799d71 830{
78b6f4ce 831 struct ixgbe_adapter *adapter = q_vector->adapter;
2d86f139 832 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 833 struct pci_dev *pdev = adapter->pdev;
834 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
835 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
836 struct sk_buff *skb;
f8212f97 837 unsigned int i, rsc_count = 0;
7c6e0a43 838 u32 len, staterr;
177db6ff
MC		 839 u16 hdr_info;
840 bool cleaned = false;
9a799d71 841 int cleaned_count = 0;
d2f4fbe2 842 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 843#ifdef IXGBE_FCOE
844 int ddp_bytes = 0;
845#endif /* IXGBE_FCOE */
9a799d71
AK		 846
847 i = rx_ring->next_to_clean;
9a799d71
AK		 848 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
849 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
850 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 851
852 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 853 u32 upper_len = 0;
9a799d71
AK		 854 if (*work_done >= work_to_do)
855 break;
856 (*work_done)++;
857
3c945e5b 858 rmb(); /* read descriptor and rx_buffer_info after status DD */
6e455b89 859 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 860 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
861 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 862 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 863 if (len > IXGBE_RX_HDR_SIZE)
864 len = IXGBE_RX_HDR_SIZE;
865 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 866 } else {
9a799d71 867 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 868 }
9a799d71
AK		 869
870 cleaned = true;
871 skb = rx_buffer_info->skb;
7ca3bc58 872 prefetch(skb->data);
9a799d71
AK		 873 rx_buffer_info->skb = NULL;
874
21fa4e66 875 if (rx_buffer_info->dma) {
43634e82
MC		 876 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
877 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
878 (!(skb->prev)))
879 /*
880 * When HWRSC is enabled, delay unmapping
881 * of the first packet. It carries the
882 * header information, HW may still
883 * access the header after the writeback.
884 * Only unmap it when EOP is reached
885 */
886 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
887 else
888 pci_unmap_single(pdev, rx_buffer_info->dma,
889 rx_ring->rx_buf_len,
890 PCI_DMA_FROMDEVICE);
4f57ca6e 891 rx_buffer_info->dma = 0;
9a799d71
AK		 892 skb_put(skb, len);
893 }
894
895 if (upper_len) {
896 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 897 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 898 rx_buffer_info->page_dma = 0;
899 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 900 rx_buffer_info->page,
901 rx_buffer_info->page_offset,
902 upper_len);
903
904 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
905 (page_count(rx_buffer_info->page) != 1))
906 rx_buffer_info->page = NULL;
907 else
908 get_page(rx_buffer_info->page);
9a799d71
AK		 909
910 skb->len += upper_len;
911 skb->data_len += upper_len;
912 skb->truesize += upper_len;
913 }
914
915 i++;
916 if (i == rx_ring->count)
917 i = 0;
9a799d71
AK		 918
919 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
920 prefetch(next_rxd);
9a799d71 921 cleaned_count++;
f8212f97 922
0c19d6af 923 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 924 rsc_count = ixgbe_get_rsc_count(rx_desc);
925
926 if (rsc_count) {
927 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
928 IXGBE_RXDADV_NEXTP_SHIFT;
929 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 930 } else {
931 next_buffer = &rx_ring->rx_buffer_info[i];
932 }
933
9a799d71 934 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97 935 if (skb->prev)
94b982b2
MC		 936 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
937 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
fd3686a8 938 if (IXGBE_RSC_CB(skb)->dma) {
43634e82
MC		 939 pci_unmap_single(pdev, IXGBE_RSC_CB(skb)->dma,
940 rx_ring->rx_buf_len,
941 PCI_DMA_FROMDEVICE);
fd3686a8
MC		 942 IXGBE_RSC_CB(skb)->dma = 0;
943 }
94b982b2
MC		 944 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
945 rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
946 else
947 rx_ring->rsc_count++;
948 rx_ring->rsc_flush++;
949 }
9a799d71
AK		 950 rx_ring->stats.packets++;
951 rx_ring->stats.bytes += skb->len;
952 } else {
6e455b89 953 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 954 rx_buffer_info->skb = next_buffer->skb;
955 rx_buffer_info->dma = next_buffer->dma;
956 next_buffer->skb = skb;
957 next_buffer->dma = 0;
958 } else {
959 skb->next = next_buffer->skb;
960 skb->next->prev = skb;
961 }
7ca3bc58 962 rx_ring->non_eop_descs++;
9a799d71
AK		 963 goto next_desc;
964 }
965
966 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
967 dev_kfree_skb_irq(skb);
968 goto next_desc;
969 }
970
8bae1b2b 971 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 972
973 /* probably a little skewed due to removing CRC */
974 total_rx_bytes += skb->len;
975 total_rx_packets++;
976
74ce8dd2 977 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 978#ifdef IXGBE_FCOE
979 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 980 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
981 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
982 if (!ddp_bytes)
332d4a7d 983 goto next_desc;
3d8fd385 984 }
332d4a7d 985#endif /* IXGBE_FCOE */
fdaff1ce 986 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 987
988next_desc:
989 rx_desc->wb.upper.status_error = 0;
990
991 /* return some buffers to hardware, one at a time is too slow */
992 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
993 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
994 cleaned_count = 0;
995 }
996
997 /* use prefetched values */
998 rx_desc = next_rxd;
f8212f97 999 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1000
1001 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1002 }
1003
9a799d71
AK		 1004 rx_ring->next_to_clean = i;
1005 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1006
1007 if (cleaned_count)
1008 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1009
3d8fd385
YZ		 1010#ifdef IXGBE_FCOE
1011 /* include DDPed FCoE data */
1012 if (ddp_bytes > 0) {
1013 unsigned int mss;
1014
1015 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1016 sizeof(struct fc_frame_header) -
1017 sizeof(struct fcoe_crc_eof);
1018 if (mss > 512)
1019 mss &= ~511;
1020 total_rx_bytes += ddp_bytes;
1021 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1022 }
1023#endif /* IXGBE_FCOE */
1024
f494e8fa
AV		 1025 rx_ring->total_packets += total_rx_packets;
1026 rx_ring->total_bytes += total_rx_bytes;
2d86f139
AK		 1027 netdev->stats.rx_bytes += total_rx_bytes;
1028 netdev->stats.rx_packets += total_rx_packets;
f494e8fa 1029
9a799d71
AK		 1030 return cleaned;
1031}
1032
021230d4 1033static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1034/**
1035 * ixgbe_configure_msix - Configure MSI-X hardware
1036 * @adapter: board private structure
1037 *
1038 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1039 * interrupts.
1040 **/
1041static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1042{
021230d4
AV		 1043 struct ixgbe_q_vector *q_vector;
1044 int i, j, q_vectors, v_idx, r_idx;
1045 u32 mask;
9a799d71 1046
021230d4 1047 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1048
4df10466
JB		 1049 /*
1050 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1051 * corresponding register.
1052 */
1053 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1054 q_vector = adapter->q_vector[v_idx];
984b3f57 1055 /* XXX for_each_set_bit(...) */
021230d4 1056 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 1057 adapter->num_rx_queues);
021230d4
AV		 1058
1059 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1060 j = adapter->rx_ring[r_idx]->reg_idx;
e8e26350 1061 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 1062 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 1063 adapter->num_rx_queues,
1064 r_idx + 1);
021230d4
AV		 1065 }
1066 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 1067 adapter->num_tx_queues);
021230d4
AV		 1068
1069 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1070 j = adapter->tx_ring[r_idx]->reg_idx;
e8e26350 1071 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 1072 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 1073 adapter->num_tx_queues,
1074 r_idx + 1);
021230d4
AV		 1075 }
1076
021230d4 1077 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1078 /* tx only */
1079 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1080 else if (q_vector->rxr_count)
f7554a2b
NS		 1081 /* rx or mixed */
1082 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1083
fe49f04a 1084 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1085 }
1086
e8e26350
PW		 1087 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1088 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1089 v_idx);
1090 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1091 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 1092 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1093
41fb9248 1094 /* set up to autoclear timer, and the vectors */
021230d4 1095 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1096 if (adapter->num_vfs)
1097 mask &= ~(IXGBE_EIMS_OTHER |
1098 IXGBE_EIMS_MAILBOX |
1099 IXGBE_EIMS_LSC);
1100 else
1101 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1102 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1103}
1104
f494e8fa
AV		 1105enum latency_range {
1106 lowest_latency = 0,
1107 low_latency = 1,
1108 bulk_latency = 2,
1109 latency_invalid = 255
1110};
1111
1112/**
1113 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1114 * @adapter: pointer to adapter
1115 * @eitr: eitr setting (ints per sec) to give last timeslice
1116 * @itr_setting: current throttle rate in ints/second
1117 * @packets: the number of packets during this measurement interval
1118 * @bytes: the number of bytes during this measurement interval
1119 *
1120 * Stores a new ITR value based on packets and byte
1121 * counts during the last interrupt. The advantage of per interrupt
1122 * computation is faster updates and more accurate ITR for the current
1123 * traffic pattern. Constants in this function were computed
1124 * based on theoretical maximum wire speed and thresholds were set based
1125 * on testing data as well as attempting to minimize response time
1126 * while increasing bulk throughput.
1127 * this functionality is controlled by the InterruptThrottleRate module
1128 * parameter (see ixgbe_param.c)
1129 **/
1130static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 1131 u32 eitr, u8 itr_setting,
1132 int packets, int bytes)
f494e8fa
AV		 1133{
1134 unsigned int retval = itr_setting;
1135 u32 timepassed_us;
1136 u64 bytes_perint;
1137
1138 if (packets == 0)
1139 goto update_itr_done;
1140
1141
1142 /* simple throttlerate management
1143 * 0-20MB/s lowest (100000 ints/s)
1144 * 20-100MB/s low (20000 ints/s)
1145 * 100-1249MB/s bulk (8000 ints/s)
1146 */
1147 /* what was last interrupt timeslice? */
1148 timepassed_us = 1000000/eitr;
1149 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1150
1151 switch (itr_setting) {
1152 case lowest_latency:
1153 if (bytes_perint > adapter->eitr_low)
1154 retval = low_latency;
1155 break;
1156 case low_latency:
1157 if (bytes_perint > adapter->eitr_high)
1158 retval = bulk_latency;
1159 else if (bytes_perint <= adapter->eitr_low)
1160 retval = lowest_latency;
1161 break;
1162 case bulk_latency:
1163 if (bytes_perint <= adapter->eitr_high)
1164 retval = low_latency;
1165 break;
1166 }
1167
1168update_itr_done:
1169 return retval;
1170}
1171
509ee935
JB		 1172/**
1173 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1174 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1175 *
1176 * This function is made to be called by ethtool and by the driver
1177 * when it needs to update EITR registers at runtime. Hardware
1178 * specific quirks/differences are taken care of here.
1179 */
fe49f04a 1180void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1181{
fe49f04a 1182 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1183 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1184 int v_idx = q_vector->v_idx;
1185 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1186
509ee935
JB		 1187 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1188 /* must write high and low 16 bits to reset counter */
1189 itr_reg |= (itr_reg << 16);
1190 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1191 /*
1192 * set the WDIS bit to not clear the timer bits and cause an
1193 * immediate assertion of the interrupt
1194 */
1195 itr_reg |= IXGBE_EITR_CNT_WDIS;
1196 }
1197 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1198}
1199
f494e8fa
AV		 1200static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1201{
1202 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1203 u32 new_itr;
1204 u8 current_itr, ret_itr;
fe49f04a 1205 int i, r_idx;
f494e8fa
AV		 1206 struct ixgbe_ring *rx_ring, *tx_ring;
1207
1208 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1209 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1210 tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1211 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1212 q_vector->tx_itr,
1213 tx_ring->total_packets,
1214 tx_ring->total_bytes);
f494e8fa
AV		 1215 /* if the result for this queue would decrease interrupt
1216 * rate for this vector then use that result */
30efa5a3 1217 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1218 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1219 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1220 r_idx + 1);
f494e8fa
AV		 1221 }
1222
1223 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1224 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1225 rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1226 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1227 q_vector->rx_itr,
1228 rx_ring->total_packets,
1229 rx_ring->total_bytes);
f494e8fa
AV		 1230 /* if the result for this queue would decrease interrupt
1231 * rate for this vector then use that result */
30efa5a3 1232 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1233 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1234 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1235 r_idx + 1);
f494e8fa
AV		 1236 }
1237
30efa5a3 1238 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1239
1240 switch (current_itr) {
1241 /* counts and packets in update_itr are dependent on these numbers */
1242 case lowest_latency:
1243 new_itr = 100000;
1244 break;
1245 case low_latency:
1246 new_itr = 20000; /* aka hwitr = ~200 */
1247 break;
1248 case bulk_latency:
1249 default:
1250 new_itr = 8000;
1251 break;
1252 }
1253
1254 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1255 /* do an exponential smoothing */
1256 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1257
1258 /* save the algorithm value here, not the smoothed one */
1259 q_vector->eitr = new_itr;
fe49f04a
AD		 1260
1261 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1262 }
1263
1264 return;
1265}
1266
0befdb3e
JB		 1267static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1268{
1269 struct ixgbe_hw *hw = &adapter->hw;
1270
1271 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1272 (eicr & IXGBE_EICR_GPI_SDP1)) {
1273 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1274 /* write to clear the interrupt */
1275 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1276 }
1277}
cf8280ee 1278
e8e26350
PW		 1279static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1280{
1281 struct ixgbe_hw *hw = &adapter->hw;
1282
1283 if (eicr & IXGBE_EICR_GPI_SDP1) {
1284 /* Clear the interrupt */
1285 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1286 schedule_work(&adapter->multispeed_fiber_task);
1287 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1288 /* Clear the interrupt */
1289 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1290 schedule_work(&adapter->sfp_config_module_task);
1291 } else {
1292 /* Interrupt isn't for us... */
1293 return;
1294 }
1295}
1296
cf8280ee
JB		 1297static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1298{
1299 struct ixgbe_hw *hw = &adapter->hw;
1300
1301 adapter->lsc_int++;
1302 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1303 adapter->link_check_timeout = jiffies;
1304 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1305 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1306 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1307 schedule_work(&adapter->watchdog_task);
1308 }
1309}
1310
9a799d71
AK		 1311static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1312{
1313 struct net_device *netdev = data;
1314 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1315 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1316 u32 eicr;
1317
1318 /*
1319 * Workaround for Silicon errata. Use clear-by-write instead
1320 * of clear-by-read. Reading with EICS will return the
1321 * interrupt causes without clearing, which later be done
1322 * with the write to EICR.
1323 */
1324 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1325 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1326
cf8280ee
JB		 1327 if (eicr & IXGBE_EICR_LSC)
1328 ixgbe_check_lsc(adapter);
d4f80882 1329
1cdd1ec8
GR		 1330 if (eicr & IXGBE_EICR_MAILBOX)
1331 ixgbe_msg_task(adapter);
1332
e8e26350
PW		 1333 if (hw->mac.type == ixgbe_mac_82598EB)
1334 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1335
c4cf55e5 1336 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1337 ixgbe_check_sfp_event(adapter, eicr);
c4cf55e5
PWJ		 1338
1339 /* Handle Flow Director Full threshold interrupt */
1340 if (eicr & IXGBE_EICR_FLOW_DIR) {
1341 int i;
1342 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1343 /* Disable transmits before FDIR Re-initialization */
1344 netif_tx_stop_all_queues(netdev);
1345 for (i = 0; i < adapter->num_tx_queues; i++) {
1346 struct ixgbe_ring *tx_ring =
4a0b9ca0 1347 adapter->tx_ring[i];
c4cf55e5
PWJ		 1348 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1349 &tx_ring->reinit_state))
1350 schedule_work(&adapter->fdir_reinit_task);
1351 }
1352 }
1353 }
d4f80882
AV		 1354 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1355 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1356
1357 return IRQ_HANDLED;
1358}
1359
fe49f04a
AD		 1360static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1361 u64 qmask)
1362{
1363 u32 mask;
1364
1365 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1366 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1367 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1368 } else {
1369 mask = (qmask & 0xFFFFFFFF);
1370 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1371 mask = (qmask >> 32);
1372 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1373 }
1374 /* skip the flush */
1375}
1376
1377static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1378 u64 qmask)
1379{
1380 u32 mask;
1381
1382 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1383 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1384 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1385 } else {
1386 mask = (qmask & 0xFFFFFFFF);
1387 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1388 mask = (qmask >> 32);
1389 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1390 }
1391 /* skip the flush */
1392}
1393
9a799d71
AK		 1394static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1395{
021230d4
AV		 1396 struct ixgbe_q_vector *q_vector = data;
1397 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1398 struct ixgbe_ring *tx_ring;
021230d4
AV		 1399 int i, r_idx;
1400
1401 if (!q_vector->txr_count)
1402 return IRQ_HANDLED;
1403
1404 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1405 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1406 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 1407 tx_ring->total_bytes = 0;
1408 tx_ring->total_packets = 0;
021230d4 1409 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1410 r_idx + 1);
021230d4 1411 }
9a799d71 1412
9b471446 1413 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 1414 napi_schedule(&q_vector->napi);
1415
9a799d71
AK		 1416 return IRQ_HANDLED;
1417}
1418
021230d4
AV		 1419/**
1420 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1421 * @irq: unused
1422 * @data: pointer to our q_vector struct for this interrupt vector
1423 **/
9a799d71
AK		 1424static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1425{
021230d4
AV		 1426 struct ixgbe_q_vector *q_vector = data;
1427 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1428 struct ixgbe_ring *rx_ring;
021230d4 1429 int r_idx;
30efa5a3 1430 int i;
021230d4
AV		 1431
1432 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3 1433 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1434 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 1435 rx_ring->total_bytes = 0;
1436 rx_ring->total_packets = 0;
1437 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1438 r_idx + 1);
1439 }
1440
021230d4
AV		 1441 if (!q_vector->rxr_count)
1442 return IRQ_HANDLED;
1443
021230d4 1444 /* disable interrupts on this vector only */
9b471446 1445 /* EIAM disabled interrupts (on this vector) for us */
288379f0 1446 napi_schedule(&q_vector->napi);
021230d4
AV		 1447
1448 return IRQ_HANDLED;
1449}
1450
1451static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1452{
91281fd3
AD		 1453 struct ixgbe_q_vector *q_vector = data;
1454 struct ixgbe_adapter *adapter = q_vector->adapter;
1455 struct ixgbe_ring *ring;
1456 int r_idx;
1457 int i;
1458
1459 if (!q_vector->txr_count && !q_vector->rxr_count)
1460 return IRQ_HANDLED;
1461
1462 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1463 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1464 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1465 ring->total_bytes = 0;
1466 ring->total_packets = 0;
1467 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1468 r_idx + 1);
1469 }
1470
1471 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1472 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1473 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 1474 ring->total_bytes = 0;
1475 ring->total_packets = 0;
1476 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1477 r_idx + 1);
1478 }
1479
9b471446 1480 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1481 napi_schedule(&q_vector->napi);
9a799d71 1482
9a799d71
AK		 1483 return IRQ_HANDLED;
1484}
1485
021230d4
AV		 1486/**
1487 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1488 * @napi: napi struct with our devices info in it
1489 * @budget: amount of work driver is allowed to do this pass, in packets
1490 *
f0848276
JB		 1491 * This function is optimized for cleaning one queue only on a single
1492 * q_vector!!!
021230d4 1493 **/
9a799d71
AK		 1494static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1495{
021230d4 1496 struct ixgbe_q_vector *q_vector =
b4617240 1497 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1498 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1499 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1500 int work_done = 0;
021230d4 1501 long r_idx;
9a799d71 1502
021230d4 1503 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1504 rx_ring = adapter->rx_ring[r_idx];
5dd2d332 1505#ifdef CONFIG_IXGBE_DCA
bd0362dd 1506 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1507 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1508#endif
9a799d71 1509
78b6f4ce 1510 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1511
021230d4
AV		 1512 /* If all Rx work done, exit the polling mode */
1513 if (work_done < budget) {
288379f0 1514 napi_complete(napi);
f7554a2b 1515 if (adapter->rx_itr_setting & 1)
f494e8fa 1516 ixgbe_set_itr_msix(q_vector);
9a799d71 1517 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1518 ixgbe_irq_enable_queues(adapter,
1519 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1520 }
1521
1522 return work_done;
1523}
1524
f0848276 1525/**
91281fd3 1526 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1527 * @napi: napi struct with our devices info in it
1528 * @budget: amount of work driver is allowed to do this pass, in packets
1529 *
1530 * This function will clean more than one rx queue associated with a
1531 * q_vector.
1532 **/
91281fd3 1533static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1534{
1535 struct ixgbe_q_vector *q_vector =
1536 container_of(napi, struct ixgbe_q_vector, napi);
1537 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1538 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1539 int work_done = 0, i;
1540 long r_idx;
91281fd3
AD		 1541 bool tx_clean_complete = true;
1542
1543 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1544 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1545 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1546#ifdef CONFIG_IXGBE_DCA
1547 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1548 ixgbe_update_tx_dca(adapter, ring);
1549#endif
1550 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1551 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1552 r_idx + 1);
1553 }
f0848276
JB		 1554
1555 /* attempt to distribute budget to each queue fairly, but don't allow
1556 * the budget to go below 1 because we'll exit polling */
1557 budget /= (q_vector->rxr_count ?: 1);
1558 budget = max(budget, 1);
1559 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1560 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1561 ring = adapter->rx_ring[r_idx];
5dd2d332 1562#ifdef CONFIG_IXGBE_DCA
f0848276 1563 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1564 ixgbe_update_rx_dca(adapter, ring);
f0848276 1565#endif
91281fd3 1566 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276
JB		 1567 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1568 r_idx + 1);
1569 }
1570
1571 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1572 ring = adapter->rx_ring[r_idx];
f0848276 1573 /* If all Rx work done, exit the polling mode */
7f821875 1574 if (work_done < budget) {
288379f0 1575 napi_complete(napi);
f7554a2b 1576 if (adapter->rx_itr_setting & 1)
f0848276
JB		 1577 ixgbe_set_itr_msix(q_vector);
1578 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1579 ixgbe_irq_enable_queues(adapter,
1580 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1581 return 0;
1582 }
1583
1584 return work_done;
1585}
91281fd3
AD		 1586
1587/**
1588 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1589 * @napi: napi struct with our devices info in it
1590 * @budget: amount of work driver is allowed to do this pass, in packets
1591 *
1592 * This function is optimized for cleaning one queue only on a single
1593 * q_vector!!!
1594 **/
1595static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1596{
1597 struct ixgbe_q_vector *q_vector =
1598 container_of(napi, struct ixgbe_q_vector, napi);
1599 struct ixgbe_adapter *adapter = q_vector->adapter;
1600 struct ixgbe_ring *tx_ring = NULL;
1601 int work_done = 0;
1602 long r_idx;
1603
1604 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
4a0b9ca0 1605 tx_ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1606#ifdef CONFIG_IXGBE_DCA
1607 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1608 ixgbe_update_tx_dca(adapter, tx_ring);
1609#endif
1610
1611 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1612 work_done = budget;
1613
f7554a2b 1614 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 1615 if (work_done < budget) {
1616 napi_complete(napi);
f7554a2b 1617 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 1618 ixgbe_set_itr_msix(q_vector);
1619 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1620 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1621 }
1622
1623 return work_done;
1624}
1625
021230d4 1626static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1627 int r_idx)
021230d4 1628{
7a921c93
AD		 1629 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1630
1631 set_bit(r_idx, q_vector->rxr_idx);
1632 q_vector->rxr_count++;
021230d4
AV		 1633}
1634
1635static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 1636 int t_idx)
021230d4 1637{
7a921c93
AD		 1638 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1639
1640 set_bit(t_idx, q_vector->txr_idx);
1641 q_vector->txr_count++;
021230d4
AV		 1642}
1643
9a799d71 1644/**
021230d4
AV		 1645 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1646 * @adapter: board private structure to initialize
1647 * @vectors: allotted vector count for descriptor rings
9a799d71 1648 *
021230d4
AV		 1649 * This function maps descriptor rings to the queue-specific vectors
1650 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1651 * one vector per ring/queue, but on a constrained vector budget, we
1652 * group the rings as "efficiently" as possible. You would add new
1653 * mapping configurations in here.
9a799d71 1654 **/
021230d4 1655static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1656 int vectors)
021230d4
AV		 1657{
1658 int v_start = 0;
1659 int rxr_idx = 0, txr_idx = 0;
1660 int rxr_remaining = adapter->num_rx_queues;
1661 int txr_remaining = adapter->num_tx_queues;
1662 int i, j;
1663 int rqpv, tqpv;
1664 int err = 0;
1665
1666 /* No mapping required if MSI-X is disabled. */
1667 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1668 goto out;
9a799d71 1669
021230d4
AV		 1670 /*
1671 * The ideal configuration...
1672 * We have enough vectors to map one per queue.
1673 */
1674 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1675 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1676 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1677
021230d4
AV		 1678 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1679 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1680
9a799d71 1681 goto out;
021230d4 1682 }
9a799d71 1683
021230d4
AV		 1684 /*
1685 * If we don't have enough vectors for a 1-to-1
1686 * mapping, we'll have to group them so there are
1687 * multiple queues per vector.
1688 */
1689 /* Re-adjusting *qpv takes care of the remainder. */
1690 for (i = v_start; i < vectors; i++) {
1691 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1692 for (j = 0; j < rqpv; j++) {
1693 map_vector_to_rxq(adapter, i, rxr_idx);
1694 rxr_idx++;
1695 rxr_remaining--;
1696 }
1697 }
1698 for (i = v_start; i < vectors; i++) {
1699 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1700 for (j = 0; j < tqpv; j++) {
1701 map_vector_to_txq(adapter, i, txr_idx);
1702 txr_idx++;
1703 txr_remaining--;
9a799d71 1704 }
9a799d71
AK		 1705 }
1706
021230d4
AV		 1707out:
1708 return err;
1709}
1710
1711/**
1712 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1713 * @adapter: board private structure
1714 *
1715 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1716 * interrupts from the kernel.
1717 **/
1718static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1719{
1720 struct net_device *netdev = adapter->netdev;
1721 irqreturn_t (*handler)(int, void *);
1722 int i, vector, q_vectors, err;
cb13fc20 1723 int ri=0, ti=0;
021230d4
AV		 1724
1725 /* Decrement for Other and TCP Timer vectors */
1726 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1727
1728 /* Map the Tx/Rx rings to the vectors we were allotted. */
1729 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1730 if (err)
1731 goto out;
1732
1733#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1734 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1735 &ixgbe_msix_clean_many)
021230d4 1736 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 1737 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 1738
1739 if(handler == &ixgbe_msix_clean_rx) {
1740 sprintf(adapter->name[vector], "%s-%s-%d",
1741 netdev->name, "rx", ri++);
1742 }
1743 else if(handler == &ixgbe_msix_clean_tx) {
1744 sprintf(adapter->name[vector], "%s-%s-%d",
1745 netdev->name, "tx", ti++);
1746 }
1747 else
1748 sprintf(adapter->name[vector], "%s-%s-%d",
1749 netdev->name, "TxRx", vector);
1750
021230d4 1751 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1752 handler, 0, adapter->name[vector],
7a921c93 1753 adapter->q_vector[vector]);
9a799d71
AK		 1754 if (err) {
1755 DPRINTK(PROBE, ERR,
b4617240
PW		 1756 "request_irq failed for MSIX interrupt "
1757 "Error: %d\n", err);
021230d4 1758 goto free_queue_irqs;
9a799d71 1759 }
9a799d71
AK		 1760 }
1761
021230d4
AV		 1762 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1763 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1764 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1765 if (err) {
1766 DPRINTK(PROBE, ERR,
1767 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1768 goto free_queue_irqs;
9a799d71
AK		 1769 }
1770
9a799d71
AK		 1771 return 0;
1772
021230d4
AV		 1773free_queue_irqs:
1774 for (i = vector - 1; i >= 0; i--)
1775 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 1776 adapter->q_vector[i]);
021230d4
AV		 1777 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1778 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1779 kfree(adapter->msix_entries);
1780 adapter->msix_entries = NULL;
021230d4 1781out:
9a799d71
AK		 1782 return err;
1783}
1784
f494e8fa
AV		 1785static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1786{
7a921c93 1787 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 1788 u8 current_itr;
1789 u32 new_itr = q_vector->eitr;
4a0b9ca0
PW		 1790 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
1791 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
f494e8fa 1792
30efa5a3 1793 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1794 q_vector->tx_itr,
1795 tx_ring->total_packets,
1796 tx_ring->total_bytes);
30efa5a3 1797 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1798 q_vector->rx_itr,
1799 rx_ring->total_packets,
1800 rx_ring->total_bytes);
f494e8fa 1801
30efa5a3 1802 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1803
1804 switch (current_itr) {
1805 /* counts and packets in update_itr are dependent on these numbers */
1806 case lowest_latency:
1807 new_itr = 100000;
1808 break;
1809 case low_latency:
1810 new_itr = 20000; /* aka hwitr = ~200 */
1811 break;
1812 case bulk_latency:
1813 new_itr = 8000;
1814 break;
1815 default:
1816 break;
1817 }
1818
1819 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1820 /* do an exponential smoothing */
1821 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1822
1823 /* save the algorithm value here, not the smoothed one */
1824 q_vector->eitr = new_itr;
fe49f04a
AD		 1825
1826 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1827 }
1828
1829 return;
1830}
1831
79aefa45
AD		 1832/**
1833 * ixgbe_irq_enable - Enable default interrupt generation settings
1834 * @adapter: board private structure
1835 **/
1836static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1837{
1838 u32 mask;
835462fc
NS		 1839
1840 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 1841 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1842 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1843 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1844 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1845 mask |= IXGBE_EIMS_GPI_SDP1;
1846 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 1847 if (adapter->num_vfs)
1848 mask |= IXGBE_EIMS_MAILBOX;
e8e26350 1849 }
c4cf55e5
PWJ		 1850 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1851 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1852 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 1853
79aefa45 1854 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 1855 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45 1856 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 1857
1858 if (adapter->num_vfs > 32) {
1859 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1860 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1861 }
79aefa45 1862}
021230d4 1863
9a799d71 1864/**
021230d4 1865 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1866 * @irq: interrupt number
1867 * @data: pointer to a network interface device structure
9a799d71
AK		 1868 **/
1869static irqreturn_t ixgbe_intr(int irq, void *data)
1870{
1871 struct net_device *netdev = data;
1872 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1873 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 1874 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 1875 u32 eicr;
1876
54037505
DS		 1877 /*
1878 * Workaround for silicon errata. Mask the interrupts
1879 * before the read of EICR.
1880 */
1881 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1882
021230d4
AV		 1883 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1884 * therefore no explict interrupt disable is necessary */
1885 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1886 if (!eicr) {
1887 /* shared interrupt alert!
1888 * make sure interrupts are enabled because the read will
1889 * have disabled interrupts due to EIAM */
1890 ixgbe_irq_enable(adapter);
9a799d71 1891 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1892 }
9a799d71 1893
cf8280ee
JB		 1894 if (eicr & IXGBE_EICR_LSC)
1895 ixgbe_check_lsc(adapter);
021230d4 1896
e8e26350
PW		 1897 if (hw->mac.type == ixgbe_mac_82599EB)
1898 ixgbe_check_sfp_event(adapter, eicr);
1899
0befdb3e
JB		 1900 ixgbe_check_fan_failure(adapter, eicr);
1901
7a921c93 1902 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 1903 adapter->tx_ring[0]->total_packets = 0;
1904 adapter->tx_ring[0]->total_bytes = 0;
1905 adapter->rx_ring[0]->total_packets = 0;
1906 adapter->rx_ring[0]->total_bytes = 0;
021230d4 1907 /* would disable interrupts here but EIAM disabled it */
7a921c93 1908 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 1909 }
1910
1911 return IRQ_HANDLED;
1912}
1913
021230d4
AV		 1914static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1915{
1916 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1917
1918 for (i = 0; i < q_vectors; i++) {
7a921c93 1919 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 1920 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1921 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1922 q_vector->rxr_count = 0;
1923 q_vector->txr_count = 0;
1924 }
1925}
1926
9a799d71
AK		 1927/**
1928 * ixgbe_request_irq - initialize interrupts
1929 * @adapter: board private structure
1930 *
1931 * Attempts to configure interrupts using the best available
1932 * capabilities of the hardware and kernel.
1933 **/
021230d4 1934static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1935{
1936 struct net_device *netdev = adapter->netdev;
021230d4 1937 int err;
9a799d71 1938
021230d4
AV		 1939 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1940 err = ixgbe_request_msix_irqs(adapter);
1941 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 1942 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
b4617240 1943 netdev->name, netdev);
021230d4 1944 } else {
a0607fd3 1945 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
b4617240 1946 netdev->name, netdev);
9a799d71
AK		 1947 }
1948
9a799d71
AK		 1949 if (err)
1950 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1951
9a799d71
AK		 1952 return err;
1953}
1954
1955static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1956{
1957 struct net_device *netdev = adapter->netdev;
1958
1959 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1960 int i, q_vectors;
9a799d71 1961
021230d4
AV		 1962 q_vectors = adapter->num_msix_vectors;
1963
1964 i = q_vectors - 1;
9a799d71 1965 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1966
021230d4
AV		 1967 i--;
1968 for (; i >= 0; i--) {
1969 free_irq(adapter->msix_entries[i].vector,
7a921c93 1970 adapter->q_vector[i]);
021230d4
AV		 1971 }
1972
1973 ixgbe_reset_q_vectors(adapter);
1974 } else {
1975 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1976 }
1977}
1978
22d5a71b
JB		 1979/**
1980 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1981 * @adapter: board private structure
1982 **/
1983static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1984{
835462fc
NS		 1985 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1986 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1987 } else {
1988 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1989 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 1990 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 1991 if (adapter->num_vfs > 32)
1992 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
22d5a71b
JB		 1993 }
1994 IXGBE_WRITE_FLUSH(&adapter->hw);
1995 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1996 int i;
1997 for (i = 0; i < adapter->num_msix_vectors; i++)
1998 synchronize_irq(adapter->msix_entries[i].vector);
1999 } else {
2000 synchronize_irq(adapter->pdev->irq);
2001 }
2002}
2003
9a799d71
AK		 2004/**
2005 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2006 *
2007 **/
2008static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2009{
9a799d71
AK		 2010 struct ixgbe_hw *hw = &adapter->hw;
2011
021230d4 2012 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
f7554a2b 2013 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2014
e8e26350
PW		 2015 ixgbe_set_ivar(adapter, 0, 0, 0);
2016 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2017
2018 map_vector_to_rxq(adapter, 0, 0);
2019 map_vector_to_txq(adapter, 0, 0);
2020
2021 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2022}
2023
2024/**
3a581073 2025 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2026 * @adapter: board private structure
2027 *
2028 * Configure the Tx unit of the MAC after a reset.
2029 **/
2030static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2031{
12207e49 2032 u64 tdba;
9a799d71 2033 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2034 u32 i, j, tdlen, txctrl;
9a799d71
AK		 2035
2036 /* Setup the HW Tx Head and Tail descriptor pointers */
2037 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2038 struct ixgbe_ring *ring = adapter->tx_ring[i];
e01c31a5
JB		 2039 j = ring->reg_idx;
2040 tdba = ring->dma;
2041 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 2042 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 2043 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 2044 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
2045 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
2046 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
2047 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
4a0b9ca0
PW		 2048 adapter->tx_ring[i]->head = IXGBE_TDH(j);
2049 adapter->tx_ring[i]->tail = IXGBE_TDT(j);
84f62d4b
PWJ		 2050 /*
2051 * Disable Tx Head Writeback RO bit, since this hoses
021230d4
AV		 2052 * bookkeeping if things aren't delivered in order.
2053 */
84f62d4b
PWJ		 2054 switch (hw->mac.type) {
2055 case ixgbe_mac_82598EB:
2056 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
2057 break;
2058 case ixgbe_mac_82599EB:
2059 default:
2060 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
2061 break;
2062 }
021230d4 2063 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
84f62d4b
PWJ		 2064 switch (hw->mac.type) {
2065 case ixgbe_mac_82598EB:
2066 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
2067 break;
2068 case ixgbe_mac_82599EB:
2069 default:
2070 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
2071 break;
2072 }
9a799d71 2073 }
ee5f784a 2074
e8e26350 2075 if (hw->mac.type == ixgbe_mac_82599EB) {
ee5f784a 2076 u32 rttdcs;
1cdd1ec8 2077 u32 mask;
ee5f784a
DS		 2078
2079 /* disable the arbiter while setting MTQC */
2080 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2081 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2082 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2083
1cdd1ec8
GR		 2084 /* set transmit pool layout */
2085 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2086 switch (adapter->flags & mask) {
2087
2088 case (IXGBE_FLAG_SRIOV_ENABLED):
2089 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2090 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2091 break;
2092
2093 case (IXGBE_FLAG_DCB_ENABLED):
2094 /* We enable 8 traffic classes, DCB only */
2095 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2096 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2097 break;
2098
2099 default:
ee5f784a 2100 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
1cdd1ec8
GR		 2101 break;
2102 }
ee5f784a
DS		 2103
2104 /* re-eable the arbiter */
2105 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2106 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
e8e26350 2107 }
9a799d71
AK		 2108}
2109
e8e26350 2110#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2111
a6616b42
YZ		 2112static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2113 struct ixgbe_ring *rx_ring)
cc41ac7c 2114{
cc41ac7c 2115 u32 srrctl;
a6616b42 2116 int index;
0cefafad 2117 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 2118
a6616b42
YZ		 2119 index = rx_ring->reg_idx;
2120 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2121 unsigned long mask;
0cefafad 2122 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 2123 index = index & mask;
cc41ac7c 2124 }
cc41ac7c
JB		 2125 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2126
2127 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2128 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2129
afafd5b0
AD		 2130 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2131 IXGBE_SRRCTL_BSIZEHDR_MASK;
2132
6e455b89 2133 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 2134#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2135 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2136#else
2137 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2138#endif
cc41ac7c 2139 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2140 } else {
afafd5b0
AD		 2141 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2142 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2143 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2144 }
e8e26350 2145
cc41ac7c
JB		 2146 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2147}
9a799d71 2148
0cefafad
JB		 2149static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2150{
2151 u32 mrqc = 0;
2152 int mask;
2153
2154 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2155 return mrqc;
2156
2157 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2158#ifdef CONFIG_IXGBE_DCB
2159 | IXGBE_FLAG_DCB_ENABLED
2160#endif
1cdd1ec8 2161 | IXGBE_FLAG_SRIOV_ENABLED
0cefafad
JB		 2162 );
2163
2164 switch (mask) {
2165 case (IXGBE_FLAG_RSS_ENABLED):
2166 mrqc = IXGBE_MRQC_RSSEN;
2167 break;
1cdd1ec8
GR		 2168 case (IXGBE_FLAG_SRIOV_ENABLED):
2169 mrqc = IXGBE_MRQC_VMDQEN;
2170 break;
0cefafad
JB		 2171#ifdef CONFIG_IXGBE_DCB
2172 case (IXGBE_FLAG_DCB_ENABLED):
2173 mrqc = IXGBE_MRQC_RT8TCEN;
2174 break;
2175#endif /* CONFIG_IXGBE_DCB */
2176 default:
2177 break;
2178 }
2179
2180 return mrqc;
2181}
2182
bb5a9ad2
NS		 2183/**
2184 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2185 * @adapter: address of board private structure
2186 * @index: index of ring to set
bb5a9ad2 2187 **/
edd2ea55 2188static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
bb5a9ad2
NS		 2189{
2190 struct ixgbe_ring *rx_ring;
2191 struct ixgbe_hw *hw = &adapter->hw;
2192 int j;
2193 u32 rscctrl;
edd2ea55 2194 int rx_buf_len;
bb5a9ad2 2195
4a0b9ca0 2196 rx_ring = adapter->rx_ring[index];
bb5a9ad2 2197 j = rx_ring->reg_idx;
edd2ea55 2198 rx_buf_len = rx_ring->rx_buf_len;
bb5a9ad2
NS		 2199 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2200 rscctrl |= IXGBE_RSCCTL_RSCEN;
2201 /*
2202 * we must limit the number of descriptors so that the
2203 * total size of max desc * buf_len is not greater
2204 * than 65535
2205 */
2206 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2207#if (MAX_SKB_FRAGS > 16)
2208 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2209#elif (MAX_SKB_FRAGS > 8)
2210 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2211#elif (MAX_SKB_FRAGS > 4)
2212 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2213#else
2214 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2215#endif
2216 } else {
2217 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2218 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2219 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2220 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2221 else
2222 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2223 }
2224 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2225}
2226
9a799d71 2227/**
3a581073 2228 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 2229 * @adapter: board private structure
2230 *
2231 * Configure the Rx unit of the MAC after a reset.
2232 **/
2233static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2234{
2235 u64 rdba;
2236 struct ixgbe_hw *hw = &adapter->hw;
a6616b42 2237 struct ixgbe_ring *rx_ring;
9a799d71
AK		 2238 struct net_device *netdev = adapter->netdev;
2239 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2240 int i, j;
9a799d71 2241 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 2242 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2243 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2244 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 2245 u32 fctrl, hlreg0;
509ee935 2246 u32 reta = 0, mrqc = 0;
cc41ac7c 2247 u32 rdrxctl;
7c6e0a43 2248 int rx_buf_len;
9a799d71
AK		 2249
2250 /* Decide whether to use packet split mode or not */
1cdd1ec8
GR		 2251 /* Do not use packet split if we're in SR-IOV Mode */
2252 if (!adapter->num_vfs)
2253 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 2254
2255 /* Set the RX buffer length according to the mode */
2256 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2257 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 2258 if (hw->mac.type == ixgbe_mac_82599EB) {
2259 /* PSRTYPE must be initialized in 82599 */
2260 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2261 IXGBE_PSRTYPE_UDPHDR |
2262 IXGBE_PSRTYPE_IPV4HDR |
dfa12f05
YZ		 2263 IXGBE_PSRTYPE_IPV6HDR |
2264 IXGBE_PSRTYPE_L2HDR;
1cdd1ec8
GR		 2265 IXGBE_WRITE_REG(hw,
2266 IXGBE_PSRTYPE(adapter->num_vfs),
2267 psrtype);
e8e26350 2268 }
9a799d71 2269 } else {
0c19d6af 2270 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2271 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2272 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2273 else
7c6e0a43 2274 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 2275 }
2276
2277 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2278 fctrl |= IXGBE_FCTRL_BAM;
021230d4 2279 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 2280 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 2281 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2282
2283 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2284 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2285 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2286 else
2287 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
63f39bd1 2288#ifdef IXGBE_FCOE
f34c5c82 2289 if (netdev->features & NETIF_F_FCOE_MTU)
63f39bd1
YZ		 2290 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2291#endif
9a799d71
AK		 2292 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2293
4a0b9ca0 2294 rdlen = adapter->rx_ring[0]->count * sizeof(union ixgbe_adv_rx_desc);
9a799d71
AK		 2295 /* disable receives while setting up the descriptors */
2296 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2297 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2298
0cefafad
JB		 2299 /*
2300 * Setup the HW Rx Head and Tail Descriptor Pointers and
2301 * the Base and Length of the Rx Descriptor Ring
2302 */
9a799d71 2303 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2304 rx_ring = adapter->rx_ring[i];
a6616b42
YZ		 2305 rdba = rx_ring->dma;
2306 j = rx_ring->reg_idx;
284901a9 2307 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 2308 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2309 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2310 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2311 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
a6616b42
YZ		 2312 rx_ring->head = IXGBE_RDH(j);
2313 rx_ring->tail = IXGBE_RDT(j);
2314 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2315
6e455b89
YZ		 2316 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2317 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
1b3ff02e
PWJ		 2318 else
2319 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2320
63f39bd1 2321#ifdef IXGBE_FCOE
f34c5c82 2322 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2323 struct ixgbe_ring_feature *f;
2324 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2325 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2326 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2327 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2328 rx_ring->rx_buf_len =
2329 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2330 }
63f39bd1
YZ		 2331 }
2332
2333#endif /* IXGBE_FCOE */
a6616b42 2334 ixgbe_configure_srrctl(adapter, rx_ring);
9a799d71
AK		 2335 }
2336
e8e26350
PW		 2337 if (hw->mac.type == ixgbe_mac_82598EB) {
2338 /*
2339 * For VMDq support of different descriptor types or
2340 * buffer sizes through the use of multiple SRRCTL
2341 * registers, RDRXCTL.MVMEN must be set to 1
2342 *
2343 * also, the manual doesn't mention it clearly but DCA hints
2344 * will only use queue 0's tags unless this bit is set. Side
2345 * effects of setting this bit are only that SRRCTL must be
2346 * fully programmed [0..15]
2347 */
2a41ff81
JB		 2348 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2349 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2350 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 2351 }
177db6ff 2352
1cdd1ec8
GR		 2353 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2354 u32 vt_reg_bits;
2355 u32 reg_offset, vf_shift;
2356 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2357 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2358 | IXGBE_VT_CTL_REPLEN;
2359 vt_reg_bits |= (adapter->num_vfs <<
2360 IXGBE_VT_CTL_POOL_SHIFT);
2361 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2362 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2363
2364 vf_shift = adapter->num_vfs % 32;
2365 reg_offset = adapter->num_vfs / 32;
2366 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2367 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2368 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2369 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2370 /* Enable only the PF's pool for Tx/Rx */
2371 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2372 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2373 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2374 ixgbe_set_vmolr(hw, adapter->num_vfs);
2375 }
2376
e8e26350 2377 /* Program MRQC for the distribution of queues */
0cefafad 2378 mrqc = ixgbe_setup_mrqc(adapter);
e8e26350 2379
021230d4 2380 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 2381 /* Fill out redirection table */
021230d4
AV		 2382 for (i = 0, j = 0; i < 128; i++, j++) {
2383 if (j == adapter->ring_feature[RING_F_RSS].indices)
2384 j = 0;
2385 /* reta = 4-byte sliding window of
2386 * 0x00..(indices-1)(indices-1)00..etc. */
2387 reta = (reta << 8) | (j * 0x11);
2388 if ((i & 3) == 3)
2389 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 2390 }
2391
2392 /* Fill out hash function seeds */
2393 for (i = 0; i < 10; i++)
7c6e0a43 2394 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 2395
2a41ff81
JB		 2396 if (hw->mac.type == ixgbe_mac_82598EB)
2397 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 2398 /* Perform hash on these packet types */
2a41ff81
JB		 2399 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2400 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2401 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2402 | IXGBE_MRQC_RSS_FIELD_IPV6
2403 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2404 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 2405 }
2a41ff81 2406 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 2407
1cdd1ec8
GR		 2408 if (adapter->num_vfs) {
2409 u32 reg;
2410
2411 /* Map PF MAC address in RAR Entry 0 to first pool
2412 * following VFs */
2413 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2414
2415 /* Set up VF register offsets for selected VT Mode, i.e.
2416 * 64 VFs for SR-IOV */
2417 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2418 reg |= IXGBE_GCR_EXT_SRIOV;
2419 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2420 }
2421
021230d4
AV		 2422 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2423
2424 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2425 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2426 /* Disable indicating checksum in descriptor, enables
2427 * RSS hash */
9a799d71 2428 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 2429 }
021230d4
AV		 2430 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2431 /* Enable IPv4 payload checksum for UDP fragments
2432 * if PCSD is not set */
2433 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2434 }
2435
2436 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 2437
2438 if (hw->mac.type == ixgbe_mac_82599EB) {
2439 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2440 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 2441 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 2442 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2443 }
f8212f97 2444
0c19d6af 2445 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 2446 /* Enable 82599 HW-RSC */
bb5a9ad2 2447 for (i = 0; i < adapter->num_rx_queues; i++)
edd2ea55 2448 ixgbe_configure_rscctl(adapter, i);
bb5a9ad2 2449
f8212f97
AD		 2450 /* Disable RSC for ACK packets */
2451 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2452 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2453 }
9a799d71
AK		 2454}
2455
068c89b0
DS		 2456static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2457{
2458 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2459 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2460 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2461
2462 /* add VID to filter table */
1ada1b1b 2463 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
068c89b0
DS		 2464}
2465
2466static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2467{
2468 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2469 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2470 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2471
2472 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2473 ixgbe_irq_disable(adapter);
2474
2475 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2476
2477 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2478 ixgbe_irq_enable(adapter);
2479
2480 /* remove VID from filter table */
1ada1b1b 2481 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
068c89b0
DS		 2482}
2483
9a799d71 2484static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2485 struct vlan_group *grp)
9a799d71
AK		 2486{
2487 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2488 u32 ctrl;
e8e26350 2489 int i, j;
9a799d71 2490
d4f80882
AV		 2491 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2492 ixgbe_irq_disable(adapter);
9a799d71
AK		 2493 adapter->vlgrp = grp;
2494
2f90b865
AD		 2495 /*
2496 * For a DCB driver, always enable VLAN tag stripping so we can
2497 * still receive traffic from a DCB-enabled host even if we're
2498 * not in DCB mode.
2499 */
2500 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
dc63d377
AD		 2501
2502 /* Disable CFI check */
2503 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2504
2505 /* enable VLAN tag stripping */
e8e26350 2506 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
dc63d377 2507 ctrl |= IXGBE_VLNCTRL_VME;
e8e26350 2508 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
e8e26350 2509 for (i = 0; i < adapter->num_rx_queues; i++) {
dc63d377 2510 u32 ctrl;
4a0b9ca0 2511 j = adapter->rx_ring[i]->reg_idx;
e8e26350
PW		 2512 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2513 ctrl |= IXGBE_RXDCTL_VME;
2514 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2515 }
9a799d71 2516 }
dc63d377
AD		 2517
2518 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2519
e8e26350 2520 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2521
d4f80882
AV		 2522 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2523 ixgbe_irq_enable(adapter);
9a799d71
AK		 2524}
2525
9a799d71
AK		 2526static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2527{
2528 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2529
2530 if (adapter->vlgrp) {
2531 u16 vid;
2532 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2533 if (!vlan_group_get_device(adapter->vlgrp, vid))
2534 continue;
2535 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2536 }
2537 }
2538}
2539
2c5645cf
CL		 2540static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2541{
2542 struct dev_mc_list *mc_ptr;
2543 u8 *addr = *mc_addr_ptr;
2544 *vmdq = 0;
2545
2546 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2547 if (mc_ptr->next)
2548 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2549 else
2550 *mc_addr_ptr = NULL;
2551
2552 return addr;
2553}
2554
9a799d71 2555/**
2c5645cf 2556 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2557 * @netdev: network interface device structure
2558 *
2c5645cf
CL		 2559 * The set_rx_method entry point is called whenever the unicast/multicast
2560 * address list or the network interface flags are updated. This routine is
2561 * responsible for configuring the hardware for proper unicast, multicast and
2562 * promiscuous mode.
9a799d71 2563 **/
7f870475 2564void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2565{
2566 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2567 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 2568 u32 fctrl, vlnctrl;
2c5645cf
CL		 2569 u8 *addr_list = NULL;
2570 int addr_count = 0;
9a799d71
AK		 2571
2572 /* Check for Promiscuous and All Multicast modes */
2573
2574 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 2575 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 2576
2577 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2578 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2579 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 2580 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 2581 } else {
746b9f02
PM		 2582 if (netdev->flags & IFF_ALLMULTI) {
2583 fctrl |= IXGBE_FCTRL_MPE;
2584 fctrl &= ~IXGBE_FCTRL_UPE;
2585 } else {
2586 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2587 }
3d01625a 2588 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 2589 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2590 }
2591
2592 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 2593 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 2594
2c5645cf 2595 /* reprogram secondary unicast list */
32e7bfc4 2596 hw->mac.ops.update_uc_addr_list(hw, netdev);
9a799d71 2597
2c5645cf 2598 /* reprogram multicast list */
4cd24eaf 2599 addr_count = netdev_mc_count(netdev);
2c5645cf
CL		 2600 if (addr_count)
2601 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 2602 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2603 ixgbe_addr_list_itr);
1cdd1ec8
GR		 2604 if (adapter->num_vfs)
2605 ixgbe_restore_vf_multicasts(adapter);
9a799d71
AK		 2606}
2607
021230d4
AV		 2608static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2609{
2610 int q_idx;
2611 struct ixgbe_q_vector *q_vector;
2612 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2613
2614 /* legacy and MSI only use one vector */
2615 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2616 q_vectors = 1;
2617
2618 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2619 struct napi_struct *napi;
7a921c93 2620 q_vector = adapter->q_vector[q_idx];
f0848276 2621 napi = &q_vector->napi;
91281fd3
AD		 2622 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2623 if (!q_vector->rxr_count || !q_vector->txr_count) {
2624 if (q_vector->txr_count == 1)
2625 napi->poll = &ixgbe_clean_txonly;
2626 else if (q_vector->rxr_count == 1)
2627 napi->poll = &ixgbe_clean_rxonly;
2628 }
2629 }
f0848276
JB		 2630
2631 napi_enable(napi);
021230d4
AV		 2632 }
2633}
2634
2635static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2636{
2637 int q_idx;
2638 struct ixgbe_q_vector *q_vector;
2639 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2640
2641 /* legacy and MSI only use one vector */
2642 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2643 q_vectors = 1;
2644
2645 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 2646 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2647 napi_disable(&q_vector->napi);
2648 }
2649}
2650
7a6b6f51 2651#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2652/*
2653 * ixgbe_configure_dcb - Configure DCB hardware
2654 * @adapter: ixgbe adapter struct
2655 *
2656 * This is called by the driver on open to configure the DCB hardware.
2657 * This is also called by the gennetlink interface when reconfiguring
2658 * the DCB state.
2659 */
2660static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2661{
2662 struct ixgbe_hw *hw = &adapter->hw;
2663 u32 txdctl, vlnctrl;
2664 int i, j;
2665
2666 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2667 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2668 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2669
2670 /* reconfigure the hardware */
2671 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2672
2673 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2674 j = adapter->tx_ring[i]->reg_idx;
2f90b865
AD		 2675 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2676 /* PThresh workaround for Tx hang with DFP enabled. */
2677 txdctl |= 32;
2678 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2679 }
2680 /* Enable VLAN tag insert/strip */
2681 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
e8e26350
PW		 2682 if (hw->mac.type == ixgbe_mac_82598EB) {
2683 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2684 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2685 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2686 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2687 vlnctrl |= IXGBE_VLNCTRL_VFE;
2688 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2689 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2690 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2691 j = adapter->rx_ring[i]->reg_idx;
e8e26350
PW		 2692 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2693 vlnctrl |= IXGBE_RXDCTL_VME;
2694 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2695 }
2696 }
2f90b865
AD		 2697 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2698}
2699
2700#endif
9a799d71
AK		 2701static void ixgbe_configure(struct ixgbe_adapter *adapter)
2702{
2703 struct net_device *netdev = adapter->netdev;
c4cf55e5 2704 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 2705 int i;
2706
2c5645cf 2707 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2708
2709 ixgbe_restore_vlan(adapter);
7a6b6f51 2710#ifdef CONFIG_IXGBE_DCB
2f90b865 2711 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
b352e40d
YZ		 2712 if (hw->mac.type == ixgbe_mac_82598EB)
2713 netif_set_gso_max_size(netdev, 32768);
2714 else
2715 netif_set_gso_max_size(netdev, 65536);
2f90b865
AD		 2716 ixgbe_configure_dcb(adapter);
2717 } else {
2718 netif_set_gso_max_size(netdev, 65536);
2719 }
2720#else
2721 netif_set_gso_max_size(netdev, 65536);
2722#endif
9a799d71 2723
eacd73f7
YZ		 2724#ifdef IXGBE_FCOE
2725 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2726 ixgbe_configure_fcoe(adapter);
2727
2728#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 2729 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2730 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 2731 adapter->tx_ring[i]->atr_sample_rate =
c4cf55e5
PWJ		 2732 adapter->atr_sample_rate;
2733 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2734 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2735 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2736 }
2737
9a799d71
AK		 2738 ixgbe_configure_tx(adapter);
2739 ixgbe_configure_rx(adapter);
2740 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 2741 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
2742 (adapter->rx_ring[i]->count - 1));
9a799d71
AK		 2743}
2744
e8e26350
PW		 2745static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2746{
2747 switch (hw->phy.type) {
2748 case ixgbe_phy_sfp_avago:
2749 case ixgbe_phy_sfp_ftl:
2750 case ixgbe_phy_sfp_intel:
2751 case ixgbe_phy_sfp_unknown:
2752 case ixgbe_phy_tw_tyco:
2753 case ixgbe_phy_tw_unknown:
2754 return true;
2755 default:
2756 return false;
2757 }
2758}
2759
0ecc061d 2760/**
e8e26350
PW		 2761 * ixgbe_sfp_link_config - set up SFP+ link
2762 * @adapter: pointer to private adapter struct
2763 **/
2764static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2765{
2766 struct ixgbe_hw *hw = &adapter->hw;
2767
2768 if (hw->phy.multispeed_fiber) {
2769 /*
2770 * In multispeed fiber setups, the device may not have
2771 * had a physical connection when the driver loaded.
2772 * If that's the case, the initial link configuration
2773 * couldn't get the MAC into 10G or 1G mode, so we'll
2774 * never have a link status change interrupt fire.
2775 * We need to try and force an autonegotiation
2776 * session, then bring up link.
2777 */
2778 hw->mac.ops.setup_sfp(hw);
2779 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2780 schedule_work(&adapter->multispeed_fiber_task);
2781 } else {
2782 /*
2783 * Direct Attach Cu and non-multispeed fiber modules
2784 * still need to be configured properly prior to
2785 * attempting link.
2786 */
2787 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2788 schedule_work(&adapter->sfp_config_module_task);
2789 }
2790}
2791
2792/**
2793 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2794 * @hw: pointer to private hardware struct
2795 *
2796 * Returns 0 on success, negative on failure
2797 **/
e8e26350 2798static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2799{
2800 u32 autoneg;
8620a103 2801 bool negotiation, link_up = false;
0ecc061d
PWJ		 2802 u32 ret = IXGBE_ERR_LINK_SETUP;
2803
2804 if (hw->mac.ops.check_link)
2805 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2806
2807 if (ret)
2808 goto link_cfg_out;
2809
2810 if (hw->mac.ops.get_link_capabilities)
8620a103 2811 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
0ecc061d
PWJ		 2812 if (ret)
2813 goto link_cfg_out;
2814
8620a103
MC		 2815 if (hw->mac.ops.setup_link)
2816 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 2817link_cfg_out:
2818 return ret;
2819}
2820
e8e26350
PW		 2821#define IXGBE_MAX_RX_DESC_POLL 10
2822static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2823 int rxr)
2824{
4a0b9ca0 2825 int j = adapter->rx_ring[rxr]->reg_idx;
e8e26350
PW		 2826 int k;
2827
2828 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2829 if (IXGBE_READ_REG(&adapter->hw,
2830 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2831 break;
2832 else
2833 msleep(1);
2834 }
2835 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2836 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2837 "not set within the polling period\n", rxr);
2838 }
4a0b9ca0
PW		 2839 ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
2840 (adapter->rx_ring[rxr]->count - 1));
e8e26350
PW		 2841}
2842
9a799d71
AK		 2843static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2844{
2845 struct net_device *netdev = adapter->netdev;
9a799d71 2846 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2847 int i, j = 0;
e8e26350 2848 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2849 int err;
9a799d71 2850 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2851 u32 txdctl, rxdctl, mhadd;
e8e26350 2852 u32 dmatxctl;
021230d4 2853 u32 gpie;
c9205697 2854 u32 ctrl_ext;
9a799d71 2855
5eba3699
AV		 2856 ixgbe_get_hw_control(adapter);
2857
021230d4
AV		 2858 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2859 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2860 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2861 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2862 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2863 } else {
2864 /* MSI only */
021230d4 2865 gpie = 0;
9a799d71 2866 }
1cdd1ec8
GR		 2867 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2868 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
2869 gpie |= IXGBE_GPIE_VTMODE_64;
2870 }
021230d4
AV		 2871 /* XXX: to interrupt immediately for EICS writes, enable this */
2872 /* gpie |= IXGBE_GPIE_EIMEN; */
2873 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2874 }
2875
9b471446
JB		 2876 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2877 /*
2878 * use EIAM to auto-mask when MSI-X interrupt is asserted
2879 * this saves a register write for every interrupt
2880 */
2881 switch (hw->mac.type) {
2882 case ixgbe_mac_82598EB:
2883 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2884 break;
2885 default:
2886 case ixgbe_mac_82599EB:
2887 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
2888 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
2889 break;
2890 }
2891 } else {
021230d4
AV		 2892 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2893 * specifically only auto mask tx and rx interrupts */
2894 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2895 }
9a799d71 2896
0befdb3e
JB		 2897 /* Enable fan failure interrupt if media type is copper */
2898 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2899 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2900 gpie |= IXGBE_SDP1_GPIEN;
2901 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2902 }
2903
e8e26350
PW		 2904 if (hw->mac.type == ixgbe_mac_82599EB) {
2905 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2906 gpie |= IXGBE_SDP1_GPIEN;
2907 gpie |= IXGBE_SDP2_GPIEN;
2908 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2909 }
2910
63f39bd1
YZ		 2911#ifdef IXGBE_FCOE
2912 /* adjust max frame to be able to do baby jumbo for FCoE */
f34c5c82 2913 if ((netdev->features & NETIF_F_FCOE_MTU) &&
63f39bd1
YZ		 2914 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2915 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2916
2917#endif /* IXGBE_FCOE */
021230d4 2918 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2919 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2920 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2921 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2922
2923 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2924 }
2925
2926 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2927 j = adapter->tx_ring[i]->reg_idx;
021230d4 2928 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2929 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2930 txdctl |= (8 << 16);
e8e26350
PW		 2931 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2932 }
2933
2934 if (hw->mac.type == ixgbe_mac_82599EB) {
2935 /* DMATXCTL.EN must be set after all Tx queue config is done */
2936 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2937 dmatxctl |= IXGBE_DMATXCTL_TE;
2938 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2939 }
2940 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2941 j = adapter->tx_ring[i]->reg_idx;
e8e26350 2942 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2943 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2944 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
1cdd1ec8
GR		 2945 if (hw->mac.type == ixgbe_mac_82599EB) {
2946 int wait_loop = 10;
2947 /* poll for Tx Enable ready */
2948 do {
2949 msleep(1);
2950 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2951 } while (--wait_loop &&
2952 !(txdctl & IXGBE_TXDCTL_ENABLE));
2953 if (!wait_loop)
2954 DPRINTK(DRV, ERR, "Could not enable "
2955 "Tx Queue %d\n", j);
2956 }
9a799d71
AK		 2957 }
2958
e8e26350 2959 for (i = 0; i < num_rx_rings; i++) {
4a0b9ca0 2960 j = adapter->rx_ring[i]->reg_idx;
021230d4
AV		 2961 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2962 /* enable PTHRESH=32 descriptors (half the internal cache)
2963 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2964 * this also removes a pesky rx_no_buffer_count increment */
2965 rxdctl |= 0x0020;
9a799d71 2966 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2967 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2968 if (hw->mac.type == ixgbe_mac_82599EB)
2969 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2970 }
2971 /* enable all receives */
2972 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2973 if (hw->mac.type == ixgbe_mac_82598EB)
2974 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2975 else
2976 rxdctl |= IXGBE_RXCTRL_RXEN;
2977 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2978
2979 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2980 ixgbe_configure_msix(adapter);
2981 else
2982 ixgbe_configure_msi_and_legacy(adapter);
2983
2984 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2985 ixgbe_napi_enable_all(adapter);
2986
2987 /* clear any pending interrupts, may auto mask */
2988 IXGBE_READ_REG(hw, IXGBE_EICR);
2989
9a799d71
AK		 2990 ixgbe_irq_enable(adapter);
2991
bf069c97
DS		 2992 /*
2993 * If this adapter has a fan, check to see if we had a failure
2994 * before we enabled the interrupt.
2995 */
2996 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2997 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2998 if (esdp & IXGBE_ESDP_SDP1)
2999 DPRINTK(DRV, CRIT,
3000 "Fan has stopped, replace the adapter\n");
3001 }
3002
e8e26350
PW		 3003 /*
3004 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 3005 * arrived before interrupts were enabled but after probe. Such
3006 * devices wouldn't have their type identified yet. We need to
3007 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 3008 * If we're not hot-pluggable SFP+, we just need to configure link
3009 * and bring it up.
3010 */
19343de2
DS		 3011 if (hw->phy.type == ixgbe_phy_unknown) {
3012 err = hw->phy.ops.identify(hw);
3013 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 3014 /*
3015 * Take the device down and schedule the sfp tasklet
3016 * which will unregister_netdev and log it.
3017 */
19343de2 3018 ixgbe_down(adapter);
5da43c1a 3019 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 3020 return err;
3021 }
e8e26350
PW		 3022 }
3023
3024 if (ixgbe_is_sfp(hw)) {
3025 ixgbe_sfp_link_config(adapter);
3026 } else {
3027 err = ixgbe_non_sfp_link_config(hw);
3028 if (err)
3029 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
3030 }
0ecc061d 3031
c4cf55e5
PWJ		 3032 for (i = 0; i < adapter->num_tx_queues; i++)
3033 set_bit(__IXGBE_FDIR_INIT_DONE,
4a0b9ca0 3034 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5 3035
1da100bb
PWJ		 3036 /* enable transmits */
3037 netif_tx_start_all_queues(netdev);
3038
9a799d71
AK		 3039 /* bring the link up in the watchdog, this could race with our first
3040 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3041 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3042 adapter->link_check_timeout = jiffies;
9a799d71 3043 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3044
3045 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3046 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3047 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3048 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3049
9a799d71
AK		 3050 return 0;
3051}
3052
d4f80882
AV		 3053void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3054{
3055 WARN_ON(in_interrupt());
3056 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3057 msleep(1);
3058 ixgbe_down(adapter);
5809a1ae
GR		 3059 /*
3060 * If SR-IOV enabled then wait a bit before bringing the adapter
3061 * back up to give the VFs time to respond to the reset. The
3062 * two second wait is based upon the watchdog timer cycle in
3063 * the VF driver.
3064 */
3065 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3066 msleep(2000);
d4f80882
AV		 3067 ixgbe_up(adapter);
3068 clear_bit(__IXGBE_RESETTING, &adapter->state);
3069}
3070
9a799d71
AK		 3071int ixgbe_up(struct ixgbe_adapter *adapter)
3072{
3073 /* hardware has been reset, we need to reload some things */
3074 ixgbe_configure(adapter);
3075
3076 return ixgbe_up_complete(adapter);
3077}
3078
3079void ixgbe_reset(struct ixgbe_adapter *adapter)
3080{
c44ade9e 3081 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3082 int err;
3083
3084 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3085 switch (err) {
3086 case 0:
3087 case IXGBE_ERR_SFP_NOT_PRESENT:
3088 break;
3089 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3090 dev_err(&adapter->pdev->dev, "master disable timed out\n");
3091 break;
794caeb2
PWJ		 3092 case IXGBE_ERR_EEPROM_VERSION:
3093 /* We are running on a pre-production device, log a warning */
3094 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
3095 "adapter/LOM. Please be aware there may be issues "
3096 "associated with your hardware. If you are "
3097 "experiencing problems please contact your Intel or "
3098 "hardware representative who provided you with this "
3099 "hardware.\n");
3100 break;
da4dd0f7
PWJ		 3101 default:
3102 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
3103 }
9a799d71
AK		 3104
3105 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3106 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3107 IXGBE_RAH_AV);
9a799d71
AK		 3108}
3109
9a799d71
AK		 3110/**
3111 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3112 * @adapter: board private structure
3113 * @rx_ring: ring to free buffers from
3114 **/
3115static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 3116 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3117{
3118 struct pci_dev *pdev = adapter->pdev;
3119 unsigned long size;
3120 unsigned int i;
3121
3122 /* Free all the Rx ring sk_buffs */
3123
3124 for (i = 0; i < rx_ring->count; i++) {
3125 struct ixgbe_rx_buffer *rx_buffer_info;
3126
3127 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3128 if (rx_buffer_info->dma) {
3129 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 3130 rx_ring->rx_buf_len,
3131 PCI_DMA_FROMDEVICE);
9a799d71
AK		 3132 rx_buffer_info->dma = 0;
3133 }
3134 if (rx_buffer_info->skb) {
f8212f97 3135 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3136 rx_buffer_info->skb = NULL;
f8212f97
AD		 3137 do {
3138 struct sk_buff *this = skb;
fd3686a8 3139 if (IXGBE_RSC_CB(this)->dma) {
43634e82
MC		 3140 pci_unmap_single(pdev, IXGBE_RSC_CB(this)->dma,
3141 rx_ring->rx_buf_len,
3142 PCI_DMA_FROMDEVICE);
fd3686a8
MC		 3143 IXGBE_RSC_CB(this)->dma = 0;
3144 }
f8212f97
AD		 3145 skb = skb->prev;
3146 dev_kfree_skb(this);
3147 } while (skb);
9a799d71
AK		 3148 }
3149 if (!rx_buffer_info->page)
3150 continue;
4f57ca6e
JB		 3151 if (rx_buffer_info->page_dma) {
3152 pci_unmap_page(pdev, rx_buffer_info->page_dma,
3153 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
3154 rx_buffer_info->page_dma = 0;
3155 }
9a799d71
AK		 3156 put_page(rx_buffer_info->page);
3157 rx_buffer_info->page = NULL;
762f4c57 3158 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3159 }
3160
3161 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3162 memset(rx_ring->rx_buffer_info, 0, size);
3163
3164 /* Zero out the descriptor ring */
3165 memset(rx_ring->desc, 0, rx_ring->size);
3166
3167 rx_ring->next_to_clean = 0;
3168 rx_ring->next_to_use = 0;
3169
9891ca7c
JB		 3170 if (rx_ring->head)
3171 writel(0, adapter->hw.hw_addr + rx_ring->head);
3172 if (rx_ring->tail)
3173 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 3174}
3175
3176/**
3177 * ixgbe_clean_tx_ring - Free Tx Buffers
3178 * @adapter: board private structure
3179 * @tx_ring: ring to be cleaned
3180 **/
3181static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 3182 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3183{
3184 struct ixgbe_tx_buffer *tx_buffer_info;
3185 unsigned long size;
3186 unsigned int i;
3187
3188 /* Free all the Tx ring sk_buffs */
3189
3190 for (i = 0; i < tx_ring->count; i++) {
3191 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3192 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3193 }
3194
3195 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3196 memset(tx_ring->tx_buffer_info, 0, size);
3197
3198 /* Zero out the descriptor ring */
3199 memset(tx_ring->desc, 0, tx_ring->size);
3200
3201 tx_ring->next_to_use = 0;
3202 tx_ring->next_to_clean = 0;
3203
9891ca7c
JB		 3204 if (tx_ring->head)
3205 writel(0, adapter->hw.hw_addr + tx_ring->head);
3206 if (tx_ring->tail)
3207 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 3208}
3209
3210/**
021230d4 3211 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3212 * @adapter: board private structure
3213 **/
021230d4 3214static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3215{
3216 int i;
3217
021230d4 3218 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3219 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
9a799d71
AK		 3220}
3221
3222/**
021230d4 3223 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3224 * @adapter: board private structure
3225 **/
021230d4 3226static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3227{
3228 int i;
3229
021230d4 3230 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3231 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3232}
3233
3234void ixgbe_down(struct ixgbe_adapter *adapter)
3235{
3236 struct net_device *netdev = adapter->netdev;
7f821875 3237 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3238 u32 rxctrl;
7f821875
JB		 3239 u32 txdctl;
3240 int i, j;
9a799d71
AK		 3241
3242 /* signal that we are down to the interrupt handler */
3243 set_bit(__IXGBE_DOWN, &adapter->state);
3244
767081ad
GR		 3245 /* disable receive for all VFs and wait one second */
3246 if (adapter->num_vfs) {
3247 for (i = 0 ; i < adapter->num_vfs; i++)
3248 adapter->vfinfo[i].clear_to_send = 0;
3249
3250 /* ping all the active vfs to let them know we are going down */
3251 ixgbe_ping_all_vfs(adapter);
3252 /* Disable all VFTE/VFRE TX/RX */
3253 ixgbe_disable_tx_rx(adapter);
3254 }
3255
9a799d71 3256 /* disable receives */
7f821875
JB		 3257 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3258 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 3259
3260 netif_tx_disable(netdev);
3261
7f821875 3262 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 3263 msleep(10);
3264
7f821875
JB		 3265 netif_tx_stop_all_queues(netdev);
3266
9a799d71
AK		 3267 ixgbe_irq_disable(adapter);
3268
021230d4 3269 ixgbe_napi_disable_all(adapter);
7f821875 3270
0a1f87cb
DS		 3271 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3272 del_timer_sync(&adapter->sfp_timer);
9a799d71 3273 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 3274 cancel_work_sync(&adapter->watchdog_task);
9a799d71 3275
c4cf55e5
PWJ		 3276 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3277 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3278 cancel_work_sync(&adapter->fdir_reinit_task);
3279
7f821875
JB		 3280 /* disable transmits in the hardware now that interrupts are off */
3281 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3282 j = adapter->tx_ring[i]->reg_idx;
7f821875
JB		 3283 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3284 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3285 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3286 }
88512539
PW		 3287 /* Disable the Tx DMA engine on 82599 */
3288 if (hw->mac.type == ixgbe_mac_82599EB)
3289 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3290 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3291 ~IXGBE_DMATXCTL_TE));
7f821875 3292
9a799d71 3293 netif_carrier_off(netdev);
9a799d71 3294
9a713e7c
PW		 3295 /* clear n-tuple filters that are cached */
3296 ethtool_ntuple_flush(netdev);
3297
6f4a0e45
PL		 3298 if (!pci_channel_offline(adapter->pdev))
3299 ixgbe_reset(adapter);
9a799d71
AK		 3300 ixgbe_clean_all_tx_rings(adapter);
3301 ixgbe_clean_all_rx_rings(adapter);
3302
5dd2d332 3303#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3304 /* since we reset the hardware DCA settings were cleared */
e35ec126 3305 ixgbe_setup_dca(adapter);
96b0e0f6 3306#endif
9a799d71
AK		 3307}
3308
9a799d71 3309/**
021230d4
AV		 3310 * ixgbe_poll - NAPI Rx polling callback
3311 * @napi: structure for representing this polling device
3312 * @budget: how many packets driver is allowed to clean
3313 *
3314 * This function is used for legacy and MSI, NAPI mode
9a799d71 3315 **/
021230d4 3316static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3317{
9a1a69ad
JB		 3318 struct ixgbe_q_vector *q_vector =
3319 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3320 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 3321 int tx_clean_complete, work_done = 0;
9a799d71 3322
5dd2d332 3323#ifdef CONFIG_IXGBE_DCA
bd0362dd 3324 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4a0b9ca0
PW		 3325 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3326 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
bd0362dd
JC		 3327 }
3328#endif
3329
4a0b9ca0
PW		 3330 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3331 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 3332
9a1a69ad 3333 if (!tx_clean_complete)
d2c7ddd6
DM		 3334 work_done = budget;
3335
53e52c72
DM		 3336 /* If budget not fully consumed, exit the polling mode */
3337 if (work_done < budget) {
288379f0 3338 napi_complete(napi);
f7554a2b 3339 if (adapter->rx_itr_setting & 1)
f494e8fa 3340 ixgbe_set_itr(adapter);
d4f80882 3341 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 3342 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 3343 }
9a799d71
AK		 3344 return work_done;
3345}
3346
3347/**
3348 * ixgbe_tx_timeout - Respond to a Tx Hang
3349 * @netdev: network interface device structure
3350 **/
3351static void ixgbe_tx_timeout(struct net_device *netdev)
3352{
3353 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3354
3355 /* Do the reset outside of interrupt context */
3356 schedule_work(&adapter->reset_task);
3357}
3358
3359static void ixgbe_reset_task(struct work_struct *work)
3360{
3361 struct ixgbe_adapter *adapter;
3362 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3363
2f90b865
AD		 3364 /* If we're already down or resetting, just bail */
3365 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3366 test_bit(__IXGBE_RESETTING, &adapter->state))
3367 return;
3368
9a799d71
AK		 3369 adapter->tx_timeout_count++;
3370
d4f80882 3371 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3372}
3373
bc97114d
PWJ		 3374#ifdef CONFIG_IXGBE_DCB
3375static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3376{
bc97114d 3377 bool ret = false;
0cefafad 3378 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3379
0cefafad
JB		 3380 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3381 return ret;
3382
3383 f->mask = 0x7 << 3;
3384 adapter->num_rx_queues = f->indices;
3385 adapter->num_tx_queues = f->indices;
3386 ret = true;
2f90b865 3387
bc97114d
PWJ		 3388 return ret;
3389}
3390#endif
3391
4df10466
JB		 3392/**
3393 * ixgbe_set_rss_queues: Allocate queues for RSS
3394 * @adapter: board private structure to initialize
3395 *
3396 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3397 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3398 *
3399 **/
bc97114d
PWJ		 3400static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3401{
3402 bool ret = false;
0cefafad 3403 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3404
3405 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3406 f->mask = 0xF;
3407 adapter->num_rx_queues = f->indices;
3408 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3409 ret = true;
3410 } else {
bc97114d 3411 ret = false;
b9804972
JB		 3412 }
3413
bc97114d
PWJ		 3414 return ret;
3415}
3416
c4cf55e5
PWJ		 3417/**
3418 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3419 * @adapter: board private structure to initialize
3420 *
3421 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3422 * to the original CPU that initiated the Tx session. This runs in addition
3423 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3424 * Rx load across CPUs using RSS.
3425 *
3426 **/
3427static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3428{
3429 bool ret = false;
3430 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3431
3432 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3433 f_fdir->mask = 0;
3434
3435 /* Flow Director must have RSS enabled */
3436 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3437 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3438 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3439 adapter->num_tx_queues = f_fdir->indices;
3440 adapter->num_rx_queues = f_fdir->indices;
3441 ret = true;
3442 } else {
3443 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3444 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3445 }
3446 return ret;
3447}
3448
0331a832
YZ		 3449#ifdef IXGBE_FCOE
3450/**
3451 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3452 * @adapter: board private structure to initialize
3453 *
3454 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3455 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3456 * rx queues out of the max number of rx queues, instead, it is used as the
3457 * index of the first rx queue used by FCoE.
3458 *
3459 **/
3460static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3461{
3462 bool ret = false;
3463 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3464
3465 f->indices = min((int)num_online_cpus(), f->indices);
3466 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 3467 adapter->num_rx_queues = 1;
3468 adapter->num_tx_queues = 1;
0331a832
YZ		 3469#ifdef CONFIG_IXGBE_DCB
3470 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6 3471 DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
0331a832
YZ		 3472 ixgbe_set_dcb_queues(adapter);
3473 }
3474#endif
3475 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8de8b2e6 3476 DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
8faa2a78
YZ		 3477 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3478 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3479 ixgbe_set_fdir_queues(adapter);
3480 else
3481 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 3482 }
3483 /* adding FCoE rx rings to the end */
3484 f->mask = adapter->num_rx_queues;
3485 adapter->num_rx_queues += f->indices;
8de8b2e6 3486 adapter->num_tx_queues += f->indices;
0331a832
YZ		 3487
3488 ret = true;
3489 }
3490
3491 return ret;
3492}
3493
3494#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 3495/**
3496 * ixgbe_set_sriov_queues: Allocate queues for IOV use
3497 * @adapter: board private structure to initialize
3498 *
3499 * IOV doesn't actually use anything, so just NAK the
3500 * request for now and let the other queue routines
3501 * figure out what to do.
3502 */
3503static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
3504{
3505 return false;
3506}
3507
4df10466
JB		 3508/*
3509 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3510 * @adapter: board private structure to initialize
3511 *
3512 * This is the top level queue allocation routine. The order here is very
3513 * important, starting with the "most" number of features turned on at once,
3514 * and ending with the smallest set of features. This way large combinations
3515 * can be allocated if they're turned on, and smaller combinations are the
3516 * fallthrough conditions.
3517 *
3518 **/
bc97114d
PWJ		 3519static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3520{
1cdd1ec8
GR		 3521 /* Start with base case */
3522 adapter->num_rx_queues = 1;
3523 adapter->num_tx_queues = 1;
3524 adapter->num_rx_pools = adapter->num_rx_queues;
3525 adapter->num_rx_queues_per_pool = 1;
3526
3527 if (ixgbe_set_sriov_queues(adapter))
3528 return;
3529
0331a832
YZ		 3530#ifdef IXGBE_FCOE
3531 if (ixgbe_set_fcoe_queues(adapter))
3532 goto done;
3533
3534#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3535#ifdef CONFIG_IXGBE_DCB
3536 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 3537 goto done;
bc97114d
PWJ		 3538
3539#endif
c4cf55e5
PWJ		 3540 if (ixgbe_set_fdir_queues(adapter))
3541 goto done;
3542
bc97114d 3543 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 3544 goto done;
3545
3546 /* fallback to base case */
3547 adapter->num_rx_queues = 1;
3548 adapter->num_tx_queues = 1;
3549
3550done:
3551 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3552 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 3553}
3554
021230d4 3555static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 3556 int vectors)
021230d4
AV		 3557{
3558 int err, vector_threshold;
3559
3560 /* We'll want at least 3 (vector_threshold):
3561 * 1) TxQ[0] Cleanup
3562 * 2) RxQ[0] Cleanup
3563 * 3) Other (Link Status Change, etc.)
3564 * 4) TCP Timer (optional)
3565 */
3566 vector_threshold = MIN_MSIX_COUNT;
3567
3568 /* The more we get, the more we will assign to Tx/Rx Cleanup
3569 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3570 * Right now, we simply care about how many we'll get; we'll
3571 * set them up later while requesting irq's.
3572 */
3573 while (vectors >= vector_threshold) {
3574 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 3575 vectors);
021230d4
AV		 3576 if (!err) /* Success in acquiring all requested vectors. */
3577 break;
3578 else if (err < 0)
3579 vectors = 0; /* Nasty failure, quit now */
3580 else /* err == number of vectors we should try again with */
3581 vectors = err;
3582 }
3583
3584 if (vectors < vector_threshold) {
3585 /* Can't allocate enough MSI-X interrupts? Oh well.
3586 * This just means we'll go with either a single MSI
3587 * vector or fall back to legacy interrupts.
3588 */
3589 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3590 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3591 kfree(adapter->msix_entries);
3592 adapter->msix_entries = NULL;
021230d4
AV		 3593 } else {
3594 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 3595 /*
3596 * Adjust for only the vectors we'll use, which is minimum
3597 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3598 * vectors we were allocated.
3599 */
3600 adapter->num_msix_vectors = min(vectors,
3601 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 3602 }
3603}
3604
021230d4 3605/**
bc97114d 3606 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 3607 * @adapter: board private structure to initialize
3608 *
bc97114d
PWJ		 3609 * Cache the descriptor ring offsets for RSS to the assigned rings.
3610 *
021230d4 3611 **/
bc97114d 3612static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 3613{
bc97114d
PWJ		 3614 int i;
3615 bool ret = false;
3616
3617 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3618 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3619 adapter->rx_ring[i]->reg_idx = i;
bc97114d 3620 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3621 adapter->tx_ring[i]->reg_idx = i;
bc97114d
PWJ		 3622 ret = true;
3623 } else {
3624 ret = false;
3625 }
3626
3627 return ret;
3628}
3629
3630#ifdef CONFIG_IXGBE_DCB
3631/**
3632 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3633 * @adapter: board private structure to initialize
3634 *
3635 * Cache the descriptor ring offsets for DCB to the assigned rings.
3636 *
3637 **/
3638static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3639{
3640 int i;
3641 bool ret = false;
3642 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3643
3644 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3645 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 3646 /* the number of queues is assumed to be symmetric */
3647 for (i = 0; i < dcb_i; i++) {
4a0b9ca0
PW		 3648 adapter->rx_ring[i]->reg_idx = i << 3;
3649 adapter->tx_ring[i]->reg_idx = i << 2;
2f90b865 3650 }
bc97114d 3651 ret = true;
e8e26350 3652 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 3653 if (dcb_i == 8) {
3654 /*
3655 * Tx TC0 starts at: descriptor queue 0
3656 * Tx TC1 starts at: descriptor queue 32
3657 * Tx TC2 starts at: descriptor queue 64
3658 * Tx TC3 starts at: descriptor queue 80
3659 * Tx TC4 starts at: descriptor queue 96
3660 * Tx TC5 starts at: descriptor queue 104
3661 * Tx TC6 starts at: descriptor queue 112
3662 * Tx TC7 starts at: descriptor queue 120
3663 *
3664 * Rx TC0-TC7 are offset by 16 queues each
3665 */
3666 for (i = 0; i < 3; i++) {
4a0b9ca0
PW		 3667 adapter->tx_ring[i]->reg_idx = i << 5;
3668 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 3669 }
3670 for ( ; i < 5; i++) {
4a0b9ca0 3671 adapter->tx_ring[i]->reg_idx =
f92ef202 3672 ((i + 2) << 4);
4a0b9ca0 3673 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 3674 }
3675 for ( ; i < dcb_i; i++) {
4a0b9ca0 3676 adapter->tx_ring[i]->reg_idx =
f92ef202 3677 ((i + 8) << 3);
4a0b9ca0 3678 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 3679 }
3680
3681 ret = true;
3682 } else if (dcb_i == 4) {
3683 /*
3684 * Tx TC0 starts at: descriptor queue 0
3685 * Tx TC1 starts at: descriptor queue 64
3686 * Tx TC2 starts at: descriptor queue 96
3687 * Tx TC3 starts at: descriptor queue 112
3688 *
3689 * Rx TC0-TC3 are offset by 32 queues each
3690 */
4a0b9ca0
PW		 3691 adapter->tx_ring[0]->reg_idx = 0;
3692 adapter->tx_ring[1]->reg_idx = 64;
3693 adapter->tx_ring[2]->reg_idx = 96;
3694 adapter->tx_ring[3]->reg_idx = 112;
f92ef202 3695 for (i = 0 ; i < dcb_i; i++)
4a0b9ca0 3696 adapter->rx_ring[i]->reg_idx = i << 5;
f92ef202
PW		 3697
3698 ret = true;
3699 } else {
3700 ret = false;
e8e26350 3701 }
bc97114d
PWJ		 3702 } else {
3703 ret = false;
021230d4 3704 }
bc97114d
PWJ		 3705 } else {
3706 ret = false;
021230d4 3707 }
bc97114d
PWJ		 3708
3709 return ret;
3710}
3711#endif
3712
c4cf55e5
PWJ		 3713/**
3714 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3715 * @adapter: board private structure to initialize
3716 *
3717 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3718 *
3719 **/
3720static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3721{
3722 int i;
3723 bool ret = false;
3724
3725 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3726 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3727 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3728 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3729 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 3730 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3731 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 3732 ret = true;
3733 }
3734
3735 return ret;
3736}
3737
0331a832
YZ		 3738#ifdef IXGBE_FCOE
3739/**
3740 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3741 * @adapter: board private structure to initialize
3742 *
3743 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3744 *
3745 */
3746static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3747{
8de8b2e6 3748 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 3749 bool ret = false;
3750 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3751
3752 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3753#ifdef CONFIG_IXGBE_DCB
3754 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 3755 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3756
0331a832 3757 ixgbe_cache_ring_dcb(adapter);
8de8b2e6 3758 /* find out queues in TC for FCoE */
4a0b9ca0
PW		 3759 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
3760 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
8de8b2e6
YZ		 3761 /*
3762 * In 82599, the number of Tx queues for each traffic
3763 * class for both 8-TC and 4-TC modes are:
3764 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3765 * 8 TCs: 32 32 16 16 8 8 8 8
3766 * 4 TCs: 64 64 32 32
3767 * We have max 8 queues for FCoE, where 8 the is
3768 * FCoE redirection table size. If TC for FCoE is
3769 * less than or equal to TC3, we have enough queues
3770 * to add max of 8 queues for FCoE, so we start FCoE
3771 * tx descriptor from the next one, i.e., reg_idx + 1.
3772 * If TC for FCoE is above TC3, implying 8 TC mode,
3773 * and we need 8 for FCoE, we have to take all queues
3774 * in that traffic class for FCoE.
3775 */
3776 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3777 fcoe_tx_i--;
0331a832
YZ		 3778 }
3779#endif /* CONFIG_IXGBE_DCB */
3780 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 3781 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3782 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3783 ixgbe_cache_ring_fdir(adapter);
3784 else
3785 ixgbe_cache_ring_rss(adapter);
3786
8de8b2e6
YZ		 3787 fcoe_rx_i = f->mask;
3788 fcoe_tx_i = f->mask;
3789 }
3790 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4a0b9ca0
PW		 3791 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
3792 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
0331a832 3793 }
0331a832
YZ		 3794 ret = true;
3795 }
3796 return ret;
3797}
3798
3799#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 3800/**
3801 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
3802 * @adapter: board private structure to initialize
3803 *
3804 * SR-IOV doesn't use any descriptor rings but changes the default if
3805 * no other mapping is used.
3806 *
3807 */
3808static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
3809{
4a0b9ca0
PW		 3810 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
3811 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 3812 if (adapter->num_vfs)
3813 return true;
3814 else
3815 return false;
3816}
3817
bc97114d
PWJ		 3818/**
3819 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3820 * @adapter: board private structure to initialize
3821 *
3822 * Once we know the feature-set enabled for the device, we'll cache
3823 * the register offset the descriptor ring is assigned to.
3824 *
3825 * Note, the order the various feature calls is important. It must start with
3826 * the "most" features enabled at the same time, then trickle down to the
3827 * least amount of features turned on at once.
3828 **/
3829static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3830{
3831 /* start with default case */
4a0b9ca0
PW		 3832 adapter->rx_ring[0]->reg_idx = 0;
3833 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 3834
1cdd1ec8
GR		 3835 if (ixgbe_cache_ring_sriov(adapter))
3836 return;
3837
0331a832
YZ		 3838#ifdef IXGBE_FCOE
3839 if (ixgbe_cache_ring_fcoe(adapter))
3840 return;
3841
3842#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3843#ifdef CONFIG_IXGBE_DCB
3844 if (ixgbe_cache_ring_dcb(adapter))
3845 return;
3846
3847#endif
c4cf55e5
PWJ		 3848 if (ixgbe_cache_ring_fdir(adapter))
3849 return;
3850
bc97114d
PWJ		 3851 if (ixgbe_cache_ring_rss(adapter))
3852 return;
021230d4
AV		 3853}
3854
9a799d71
AK		 3855/**
3856 * ixgbe_alloc_queues - Allocate memory for all rings
3857 * @adapter: board private structure to initialize
3858 *
3859 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 3860 * number of queues at compile-time. The polling_netdev array is
3861 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 3862 **/
2f90b865 3863static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 3864{
3865 int i;
4a0b9ca0 3866 int orig_node = adapter->node;
9a799d71 3867
021230d4 3868 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 3869 struct ixgbe_ring *ring = adapter->tx_ring[i];
3870 if (orig_node == -1) {
3871 int cur_node = next_online_node(adapter->node);
3872 if (cur_node == MAX_NUMNODES)
3873 cur_node = first_online_node;
3874 adapter->node = cur_node;
3875 }
3876 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
3877 adapter->node);
3878 if (!ring)
3879 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
3880 if (!ring)
3881 goto err_tx_ring_allocation;
3882 ring->count = adapter->tx_ring_count;
3883 ring->queue_index = i;
3884 ring->numa_node = adapter->node;
3885
3886 adapter->tx_ring[i] = ring;
021230d4 3887 }
b9804972 3888
4a0b9ca0
PW		 3889 /* Restore the adapter's original node */
3890 adapter->node = orig_node;
3891
9a799d71 3892 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 3893 struct ixgbe_ring *ring = adapter->rx_ring[i];
3894 if (orig_node == -1) {
3895 int cur_node = next_online_node(adapter->node);
3896 if (cur_node == MAX_NUMNODES)
3897 cur_node = first_online_node;
3898 adapter->node = cur_node;
3899 }
3900 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
3901 adapter->node);
3902 if (!ring)
3903 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
3904 if (!ring)
3905 goto err_rx_ring_allocation;
3906 ring->count = adapter->rx_ring_count;
3907 ring->queue_index = i;
3908 ring->numa_node = adapter->node;
3909
3910 adapter->rx_ring[i] = ring;
021230d4
AV		 3911 }
3912
4a0b9ca0
PW		 3913 /* Restore the adapter's original node */
3914 adapter->node = orig_node;
3915
021230d4
AV		 3916 ixgbe_cache_ring_register(adapter);
3917
3918 return 0;
3919
3920err_rx_ring_allocation:
4a0b9ca0
PW		 3921 for (i = 0; i < adapter->num_tx_queues; i++)
3922 kfree(adapter->tx_ring[i]);
021230d4
AV		 3923err_tx_ring_allocation:
3924 return -ENOMEM;
3925}
3926
3927/**
3928 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3929 * @adapter: board private structure to initialize
3930 *
3931 * Attempt to configure the interrupts using the best available
3932 * capabilities of the hardware and the kernel.
3933 **/
feea6a57 3934static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 3935{
8be0e467 3936 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 3937 int err = 0;
3938 int vector, v_budget;
3939
3940 /*
3941 * It's easy to be greedy for MSI-X vectors, but it really
3942 * doesn't do us much good if we have a lot more vectors
3943 * than CPU's. So let's be conservative and only ask for
342bde1b 3944 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 3945 */
3946 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
342bde1b 3947 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 3948
3949 /*
3950 * At the same time, hardware can only support a maximum of
8be0e467
PW		 3951 * hw.mac->max_msix_vectors vectors. With features
3952 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3953 * descriptor queues supported by our device. Thus, we cap it off in
3954 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3955 */
8be0e467 3956 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3957
3958 /* A failure in MSI-X entry allocation isn't fatal, but it does
3959 * mean we disable MSI-X capabilities of the adapter. */
3960 adapter->msix_entries = kcalloc(v_budget,
b4617240 3961 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 3962 if (adapter->msix_entries) {
3963 for (vector = 0; vector < v_budget; vector++)
3964 adapter->msix_entries[vector].entry = vector;
021230d4 3965
7a921c93 3966 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 3967
7a921c93
AD		 3968 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3969 goto out;
3970 }
021230d4 3971
7a921c93
AD		 3972 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3973 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 3974 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3975 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3976 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 3977 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3978 ixgbe_disable_sriov(adapter);
3979
7a921c93 3980 ixgbe_set_num_queues(adapter);
021230d4 3981
021230d4
AV		 3982 err = pci_enable_msi(adapter->pdev);
3983 if (!err) {
3984 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3985 } else {
3986 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 3987 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 3988 /* reset err */
3989 err = 0;
3990 }
3991
3992out:
021230d4
AV		 3993 return err;
3994}
3995
7a921c93
AD		 3996/**
3997 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3998 * @adapter: board private structure to initialize
3999 *
4000 * We allocate one q_vector per queue interrupt. If allocation fails we
4001 * return -ENOMEM.
4002 **/
4003static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4004{
4005 int q_idx, num_q_vectors;
4006 struct ixgbe_q_vector *q_vector;
4007 int napi_vectors;
4008 int (*poll)(struct napi_struct *, int);
4009
4010 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4011 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4012 napi_vectors = adapter->num_rx_queues;
91281fd3 4013 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4014 } else {
4015 num_q_vectors = 1;
4016 napi_vectors = 1;
4017 poll = &ixgbe_poll;
4018 }
4019
4020 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2
JB		 4021 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4022 GFP_KERNEL, adapter->node);
4023 if (!q_vector)
4024 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4025 GFP_KERNEL);
7a921c93
AD		 4026 if (!q_vector)
4027 goto err_out;
4028 q_vector->adapter = adapter;
f7554a2b
NS		 4029 if (q_vector->txr_count && !q_vector->rxr_count)
4030 q_vector->eitr = adapter->tx_eitr_param;
4031 else
4032 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4033 q_vector->v_idx = q_idx;
91281fd3 4034 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4035 adapter->q_vector[q_idx] = q_vector;
4036 }
4037
4038 return 0;
4039
4040err_out:
4041 while (q_idx) {
4042 q_idx--;
4043 q_vector = adapter->q_vector[q_idx];
4044 netif_napi_del(&q_vector->napi);
4045 kfree(q_vector);
4046 adapter->q_vector[q_idx] = NULL;
4047 }
4048 return -ENOMEM;
4049}
4050
4051/**
4052 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4053 * @adapter: board private structure to initialize
4054 *
4055 * This function frees the memory allocated to the q_vectors. In addition if
4056 * NAPI is enabled it will delete any references to the NAPI struct prior
4057 * to freeing the q_vector.
4058 **/
4059static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4060{
4061 int q_idx, num_q_vectors;
7a921c93 4062
91281fd3 4063 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4064 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4065 else
7a921c93 4066 num_q_vectors = 1;
7a921c93
AD		 4067
4068 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4069 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4070 adapter->q_vector[q_idx] = NULL;
91281fd3 4071 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4072 kfree(q_vector);
4073 }
4074}
4075
7b25cdba 4076static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4077{
4078 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4079 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4080 pci_disable_msix(adapter->pdev);
4081 kfree(adapter->msix_entries);
4082 adapter->msix_entries = NULL;
4083 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4084 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4085 pci_disable_msi(adapter->pdev);
4086 }
4087 return;
4088}
4089
4090/**
4091 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4092 * @adapter: board private structure to initialize
4093 *
4094 * We determine which interrupt scheme to use based on...
4095 * - Kernel support (MSI, MSI-X)
4096 * - which can be user-defined (via MODULE_PARAM)
4097 * - Hardware queue count (num_*_queues)
4098 * - defined by miscellaneous hardware support/features (RSS, etc.)
4099 **/
2f90b865 4100int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4101{
4102 int err;
4103
4104 /* Number of supported queues */
4105 ixgbe_set_num_queues(adapter);
4106
021230d4
AV		 4107 err = ixgbe_set_interrupt_capability(adapter);
4108 if (err) {
4109 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
4110 goto err_set_interrupt;
9a799d71
AK		 4111 }
4112
7a921c93
AD		 4113 err = ixgbe_alloc_q_vectors(adapter);
4114 if (err) {
4115 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
4116 "vectors\n");
4117 goto err_alloc_q_vectors;
4118 }
4119
4120 err = ixgbe_alloc_queues(adapter);
4121 if (err) {
4122 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
4123 goto err_alloc_queues;
4124 }
4125
021230d4 4126 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 4127 "Tx Queue count = %u\n",
4128 (adapter->num_rx_queues > 1) ? "Enabled" :
4129 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4130
4131 set_bit(__IXGBE_DOWN, &adapter->state);
4132
9a799d71 4133 return 0;
021230d4 4134
7a921c93
AD		 4135err_alloc_queues:
4136 ixgbe_free_q_vectors(adapter);
4137err_alloc_q_vectors:
4138 ixgbe_reset_interrupt_capability(adapter);
021230d4 4139err_set_interrupt:
7a921c93
AD		 4140 return err;
4141}
4142
4143/**
4144 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4145 * @adapter: board private structure to clear interrupt scheme on
4146 *
4147 * We go through and clear interrupt specific resources and reset the structure
4148 * to pre-load conditions
4149 **/
4150void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4151{
4a0b9ca0
PW		 4152 int i;
4153
4154 for (i = 0; i < adapter->num_tx_queues; i++) {
4155 kfree(adapter->tx_ring[i]);
4156 adapter->tx_ring[i] = NULL;
4157 }
4158 for (i = 0; i < adapter->num_rx_queues; i++) {
4159 kfree(adapter->rx_ring[i]);
4160 adapter->rx_ring[i] = NULL;
4161 }
7a921c93
AD		 4162
4163 ixgbe_free_q_vectors(adapter);
4164 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4165}
4166
c4900be0
DS		 4167/**
4168 * ixgbe_sfp_timer - worker thread to find a missing module
4169 * @data: pointer to our adapter struct
4170 **/
4171static void ixgbe_sfp_timer(unsigned long data)
4172{
4173 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4174
4df10466
JB		 4175 /*
4176 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 4177 * delays that sfp+ detection requires
4178 */
4179 schedule_work(&adapter->sfp_task);
4180}
4181
4182/**
4183 * ixgbe_sfp_task - worker thread to find a missing module
4184 * @work: pointer to work_struct containing our data
4185 **/
4186static void ixgbe_sfp_task(struct work_struct *work)
4187{
4188 struct ixgbe_adapter *adapter = container_of(work,
4189 struct ixgbe_adapter,
4190 sfp_task);
4191 struct ixgbe_hw *hw = &adapter->hw;
4192
4193 if ((hw->phy.type == ixgbe_phy_nl) &&
4194 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4195 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4196 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 4197 goto reschedule;
4198 ret = hw->phy.ops.reset(hw);
4199 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 4200 dev_err(&adapter->pdev->dev, "failed to initialize "
4201 "because an unsupported SFP+ module type "
4202 "was detected.\n"
4203 "Reload the driver after installing a "
4204 "supported module.\n");
c4900be0
DS		 4205 unregister_netdev(adapter->netdev);
4206 } else {
4207 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
4208 hw->phy.sfp_type);
4209 }
4210 /* don't need this routine any more */
4211 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4212 }
4213 return;
4214reschedule:
4215 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4216 mod_timer(&adapter->sfp_timer,
4217 round_jiffies(jiffies + (2 * HZ)));
4218}
4219
9a799d71
AK		 4220/**
4221 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4222 * @adapter: board private structure to initialize
4223 *
4224 * ixgbe_sw_init initializes the Adapter private data structure.
4225 * Fields are initialized based on PCI device information and
4226 * OS network device settings (MTU size).
4227 **/
4228static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4229{
4230 struct ixgbe_hw *hw = &adapter->hw;
4231 struct pci_dev *pdev = adapter->pdev;
9a713e7c 4232 struct net_device *dev = adapter->netdev;
021230d4 4233 unsigned int rss;
7a6b6f51 4234#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4235 int j;
4236 struct tc_configuration *tc;
4237#endif
021230d4 4238
c44ade9e
JB		 4239 /* PCI config space info */
4240
4241 hw->vendor_id = pdev->vendor;
4242 hw->device_id = pdev->device;
4243 hw->revision_id = pdev->revision;
4244 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4245 hw->subsystem_device_id = pdev->subsystem_device;
4246
021230d4
AV		 4247 /* Set capability flags */
4248 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4249 adapter->ring_feature[RING_F_RSS].indices = rss;
4250 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 4251 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 4252 if (hw->mac.type == ixgbe_mac_82598EB) {
4253 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4254 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4255 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 4256 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 4257 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4258 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4259 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
9a713e7c
PW		 4260 if (dev->features & NETIF_F_NTUPLE) {
4261 /* Flow Director perfect filter enabled */
4262 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4263 adapter->atr_sample_rate = 0;
4264 spin_lock_init(&adapter->fdir_perfect_lock);
4265 } else {
4266 /* Flow Director hash filters enabled */
4267 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4268 adapter->atr_sample_rate = 20;
4269 }
c4cf55e5
PWJ		 4270 adapter->ring_feature[RING_F_FDIR].indices =
4271 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 4272 adapter->fdir_pballoc = 0;
eacd73f7 4273#ifdef IXGBE_FCOE
0d551589
YZ		 4274 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4275 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4276 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4277#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 4278 /* Default traffic class to use for FCoE */
4279 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
61a0f421 4280#endif
eacd73f7 4281#endif /* IXGBE_FCOE */
f8212f97 4282 }
2f90b865 4283
7a6b6f51 4284#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4285 /* Configure DCB traffic classes */
4286 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4287 tc = &adapter->dcb_cfg.tc_config[j];
4288 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4289 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4290 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4291 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4292 tc->dcb_pfc = pfc_disabled;
4293 }
4294 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4295 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4296 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 4297 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 4298 adapter->dcb_cfg.round_robin_enable = false;
4299 adapter->dcb_set_bitmap = 0x00;
4300 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4301 adapter->ring_feature[RING_F_DCB].indices);
4302
4303#endif
9a799d71
AK		 4304
4305 /* default flow control settings */
cd7664f6 4306 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4307 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 4308#ifdef CONFIG_DCB
4309 adapter->last_lfc_mode = hw->fc.current_mode;
4310#endif
2b9ade93
JB		 4311 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4312 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4313 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4314 hw->fc.send_xon = true;
71fd570b 4315 hw->fc.disable_fc_autoneg = false;
9a799d71 4316
30efa5a3 4317 /* enable itr by default in dynamic mode */
f7554a2b
NS		 4318 adapter->rx_itr_setting = 1;
4319 adapter->rx_eitr_param = 20000;
4320 adapter->tx_itr_setting = 1;
4321 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 4322
4323 /* set defaults for eitr in MegaBytes */
4324 adapter->eitr_low = 10;
4325 adapter->eitr_high = 20;
4326
4327 /* set default ring sizes */
4328 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4329 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4330
9a799d71 4331 /* initialize eeprom parameters */
c44ade9e 4332 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 4333 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4334 return -EIO;
4335 }
4336
021230d4 4337 /* enable rx csum by default */
9a799d71
AK		 4338 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4339
1a6c14a2
JB		 4340 /* get assigned NUMA node */
4341 adapter->node = dev_to_node(&pdev->dev);
4342
9a799d71
AK		 4343 set_bit(__IXGBE_DOWN, &adapter->state);
4344
4345 return 0;
4346}
4347
4348/**
4349 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4350 * @adapter: board private structure
3a581073 4351 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4352 *
4353 * Return 0 on success, negative on failure
4354 **/
4355int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 4356 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4357{
4358 struct pci_dev *pdev = adapter->pdev;
4359 int size;
4360
3a581073 4361 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4a0b9ca0 4362 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
1a6c14a2
JB		 4363 if (!tx_ring->tx_buffer_info)
4364 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 4365 if (!tx_ring->tx_buffer_info)
4366 goto err;
3a581073 4367 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 4368
4369 /* round up to nearest 4K */
12207e49 4370 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4371 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4372
3a581073
JB		 4373 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
4374 &tx_ring->dma);
e01c31a5
JB		 4375 if (!tx_ring->desc)
4376 goto err;
9a799d71 4377
3a581073
JB		 4378 tx_ring->next_to_use = 0;
4379 tx_ring->next_to_clean = 0;
4380 tx_ring->work_limit = tx_ring->count;
9a799d71 4381 return 0;
e01c31a5
JB		 4382
4383err:
4384 vfree(tx_ring->tx_buffer_info);
4385 tx_ring->tx_buffer_info = NULL;
4386 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4387 "descriptor ring\n");
4388 return -ENOMEM;
9a799d71
AK		 4389}
4390
69888674
AD		 4391/**
4392 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4393 * @adapter: board private structure
4394 *
4395 * If this function returns with an error, then it's possible one or
4396 * more of the rings is populated (while the rest are not). It is the
4397 * callers duty to clean those orphaned rings.
4398 *
4399 * Return 0 on success, negative on failure
4400 **/
4401static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4402{
4403 int i, err = 0;
4404
4405 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 4406 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
69888674
AD		 4407 if (!err)
4408 continue;
4409 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4410 break;
4411 }
4412
4413 return err;
4414}
4415
9a799d71
AK		 4416/**
4417 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4418 * @adapter: board private structure
3a581073 4419 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4420 *
4421 * Returns 0 on success, negative on failure
4422 **/
4423int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 4424 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4425{
4426 struct pci_dev *pdev = adapter->pdev;
021230d4 4427 int size;
9a799d71 4428
3a581073 4429 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
1a6c14a2
JB		 4430 rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4431 if (!rx_ring->rx_buffer_info)
4432 rx_ring->rx_buffer_info = vmalloc(size);
3a581073 4433 if (!rx_ring->rx_buffer_info) {
9a799d71 4434 DPRINTK(PROBE, ERR,
b4617240 4435 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 4436 goto alloc_failed;
9a799d71 4437 }
3a581073 4438 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 4439
9a799d71 4440 /* Round up to nearest 4K */
3a581073
JB		 4441 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4442 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4443
3a581073 4444 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 4445
3a581073 4446 if (!rx_ring->desc) {
9a799d71 4447 DPRINTK(PROBE, ERR,
b4617240 4448 "Memory allocation failed for the rx desc ring\n");
3a581073 4449 vfree(rx_ring->rx_buffer_info);
177db6ff 4450 goto alloc_failed;
9a799d71
AK		 4451 }
4452
3a581073
JB		 4453 rx_ring->next_to_clean = 0;
4454 rx_ring->next_to_use = 0;
9a799d71
AK		 4455
4456 return 0;
177db6ff
MC		 4457
4458alloc_failed:
177db6ff 4459 return -ENOMEM;
9a799d71
AK		 4460}
4461
69888674
AD		 4462/**
4463 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4464 * @adapter: board private structure
4465 *
4466 * If this function returns with an error, then it's possible one or
4467 * more of the rings is populated (while the rest are not). It is the
4468 * callers duty to clean those orphaned rings.
4469 *
4470 * Return 0 on success, negative on failure
4471 **/
4472
4473static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4474{
4475 int i, err = 0;
4476
4477 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 4478 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
69888674
AD		 4479 if (!err)
4480 continue;
4481 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4482 break;
4483 }
4484
4485 return err;
4486}
4487
9a799d71
AK		 4488/**
4489 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4490 * @adapter: board private structure
4491 * @tx_ring: Tx descriptor ring for a specific queue
4492 *
4493 * Free all transmit software resources
4494 **/
c431f97e
JB		 4495void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4496 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4497{
4498 struct pci_dev *pdev = adapter->pdev;
4499
4500 ixgbe_clean_tx_ring(adapter, tx_ring);
4501
4502 vfree(tx_ring->tx_buffer_info);
4503 tx_ring->tx_buffer_info = NULL;
4504
4505 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4506
4507 tx_ring->desc = NULL;
4508}
4509
4510/**
4511 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4512 * @adapter: board private structure
4513 *
4514 * Free all transmit software resources
4515 **/
4516static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4517{
4518 int i;
4519
4520 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0
PW		 4521 if (adapter->tx_ring[i]->desc)
4522 ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
9a799d71
AK		 4523}
4524
4525/**
b4617240 4526 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4527 * @adapter: board private structure
4528 * @rx_ring: ring to clean the resources from
4529 *
4530 * Free all receive software resources
4531 **/
c431f97e
JB		 4532void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4533 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4534{
4535 struct pci_dev *pdev = adapter->pdev;
4536
4537 ixgbe_clean_rx_ring(adapter, rx_ring);
4538
4539 vfree(rx_ring->rx_buffer_info);
4540 rx_ring->rx_buffer_info = NULL;
4541
4542 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4543
4544 rx_ring->desc = NULL;
4545}
4546
4547/**
4548 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4549 * @adapter: board private structure
4550 *
4551 * Free all receive software resources
4552 **/
4553static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4554{
4555 int i;
4556
4557 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 4558 if (adapter->rx_ring[i]->desc)
4559 ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
9a799d71
AK		 4560}
4561
9a799d71
AK		 4562/**
4563 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4564 * @netdev: network interface device structure
4565 * @new_mtu: new value for maximum frame size
4566 *
4567 * Returns 0 on success, negative on failure
4568 **/
4569static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4570{
4571 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4572 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4573
42c783c5
JB		 4574 /* MTU < 68 is an error and causes problems on some kernels */
4575 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 4576 return -EINVAL;
4577
021230d4 4578 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 4579 netdev->mtu, new_mtu);
021230d4 4580 /* must set new MTU before calling down or up */
9a799d71
AK		 4581 netdev->mtu = new_mtu;
4582
d4f80882
AV		 4583 if (netif_running(netdev))
4584 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4585
4586 return 0;
4587}
4588
4589/**
4590 * ixgbe_open - Called when a network interface is made active
4591 * @netdev: network interface device structure
4592 *
4593 * Returns 0 on success, negative value on failure
4594 *
4595 * The open entry point is called when a network interface is made
4596 * active by the system (IFF_UP). At this point all resources needed
4597 * for transmit and receive operations are allocated, the interrupt
4598 * handler is registered with the OS, the watchdog timer is started,
4599 * and the stack is notified that the interface is ready.
4600 **/
4601static int ixgbe_open(struct net_device *netdev)
4602{
4603 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4604 int err;
4bebfaa5
AK		 4605
4606 /* disallow open during test */
4607 if (test_bit(__IXGBE_TESTING, &adapter->state))
4608 return -EBUSY;
9a799d71 4609
54386467
JB		 4610 netif_carrier_off(netdev);
4611
9a799d71
AK		 4612 /* allocate transmit descriptors */
4613 err = ixgbe_setup_all_tx_resources(adapter);
4614 if (err)
4615 goto err_setup_tx;
4616
9a799d71
AK		 4617 /* allocate receive descriptors */
4618 err = ixgbe_setup_all_rx_resources(adapter);
4619 if (err)
4620 goto err_setup_rx;
4621
4622 ixgbe_configure(adapter);
4623
021230d4 4624 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4625 if (err)
4626 goto err_req_irq;
4627
9a799d71
AK		 4628 err = ixgbe_up_complete(adapter);
4629 if (err)
4630 goto err_up;
4631
d55b53ff
JK		 4632 netif_tx_start_all_queues(netdev);
4633
9a799d71
AK		 4634 return 0;
4635
4636err_up:
5eba3699 4637 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4638 ixgbe_free_irq(adapter);
4639err_req_irq:
9a799d71 4640err_setup_rx:
a20a1199 4641 ixgbe_free_all_rx_resources(adapter);
9a799d71 4642err_setup_tx:
a20a1199 4643 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 4644 ixgbe_reset(adapter);
4645
4646 return err;
4647}
4648
4649/**
4650 * ixgbe_close - Disables a network interface
4651 * @netdev: network interface device structure
4652 *
4653 * Returns 0, this is not allowed to fail
4654 *
4655 * The close entry point is called when an interface is de-activated
4656 * by the OS. The hardware is still under the drivers control, but
4657 * needs to be disabled. A global MAC reset is issued to stop the
4658 * hardware, and all transmit and receive resources are freed.
4659 **/
4660static int ixgbe_close(struct net_device *netdev)
4661{
4662 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4663
4664 ixgbe_down(adapter);
4665 ixgbe_free_irq(adapter);
4666
4667 ixgbe_free_all_tx_resources(adapter);
4668 ixgbe_free_all_rx_resources(adapter);
4669
5eba3699 4670 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4671
4672 return 0;
4673}
4674
b3c8b4ba
AD		 4675#ifdef CONFIG_PM
4676static int ixgbe_resume(struct pci_dev *pdev)
4677{
4678 struct net_device *netdev = pci_get_drvdata(pdev);
4679 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4680 u32 err;
4681
4682 pci_set_power_state(pdev, PCI_D0);
4683 pci_restore_state(pdev);
656ab817
DS		 4684 /*
4685 * pci_restore_state clears dev->state_saved so call
4686 * pci_save_state to restore it.
4687 */
4688 pci_save_state(pdev);
9ce77666 4689
4690 err = pci_enable_device_mem(pdev);
b3c8b4ba 4691 if (err) {
69888674 4692 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 4693 "suspend\n");
4694 return err;
4695 }
4696 pci_set_master(pdev);
4697
dd4d8ca6 4698 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 4699
4700 err = ixgbe_init_interrupt_scheme(adapter);
4701 if (err) {
4702 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4703 "device\n");
4704 return err;
4705 }
4706
b3c8b4ba
AD		 4707 ixgbe_reset(adapter);
4708
495dce12
WJP		 4709 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4710
b3c8b4ba
AD		 4711 if (netif_running(netdev)) {
4712 err = ixgbe_open(adapter->netdev);
4713 if (err)
4714 return err;
4715 }
4716
4717 netif_device_attach(netdev);
4718
4719 return 0;
4720}
b3c8b4ba 4721#endif /* CONFIG_PM */
9d8d05ae
RW		 4722
4723static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 4724{
4725 struct net_device *netdev = pci_get_drvdata(pdev);
4726 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 4727 struct ixgbe_hw *hw = &adapter->hw;
4728 u32 ctrl, fctrl;
4729 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4730#ifdef CONFIG_PM
4731 int retval = 0;
4732#endif
4733
4734 netif_device_detach(netdev);
4735
4736 if (netif_running(netdev)) {
4737 ixgbe_down(adapter);
4738 ixgbe_free_irq(adapter);
4739 ixgbe_free_all_tx_resources(adapter);
4740 ixgbe_free_all_rx_resources(adapter);
4741 }
7a921c93 4742 ixgbe_clear_interrupt_scheme(adapter);
b3c8b4ba
AD		 4743
4744#ifdef CONFIG_PM
4745 retval = pci_save_state(pdev);
4746 if (retval)
4747 return retval;
4df10466 4748
b3c8b4ba 4749#endif
e8e26350
PW		 4750 if (wufc) {
4751 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4752
e8e26350
PW		 4753 /* turn on all-multi mode if wake on multicast is enabled */
4754 if (wufc & IXGBE_WUFC_MC) {
4755 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4756 fctrl |= IXGBE_FCTRL_MPE;
4757 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4758 }
4759
4760 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4761 ctrl |= IXGBE_CTRL_GIO_DIS;
4762 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4763
4764 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4765 } else {
4766 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4767 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4768 }
4769
dd4d8ca6
DS		 4770 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4771 pci_wake_from_d3(pdev, true);
4772 else
4773 pci_wake_from_d3(pdev, false);
b3c8b4ba 4774
9d8d05ae
RW		 4775 *enable_wake = !!wufc;
4776
b3c8b4ba
AD		 4777 ixgbe_release_hw_control(adapter);
4778
4779 pci_disable_device(pdev);
4780
9d8d05ae
RW		 4781 return 0;
4782}
4783
4784#ifdef CONFIG_PM
4785static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4786{
4787 int retval;
4788 bool wake;
4789
4790 retval = __ixgbe_shutdown(pdev, &wake);
4791 if (retval)
4792 return retval;
4793
4794 if (wake) {
4795 pci_prepare_to_sleep(pdev);
4796 } else {
4797 pci_wake_from_d3(pdev, false);
4798 pci_set_power_state(pdev, PCI_D3hot);
4799 }
b3c8b4ba
AD		 4800
4801 return 0;
4802}
9d8d05ae 4803#endif /* CONFIG_PM */
b3c8b4ba
AD		 4804
4805static void ixgbe_shutdown(struct pci_dev *pdev)
4806{
9d8d05ae
RW		 4807 bool wake;
4808
4809 __ixgbe_shutdown(pdev, &wake);
4810
4811 if (system_state == SYSTEM_POWER_OFF) {
4812 pci_wake_from_d3(pdev, wake);
4813 pci_set_power_state(pdev, PCI_D3hot);
4814 }
b3c8b4ba
AD		 4815}
4816
9a799d71
AK		 4817/**
4818 * ixgbe_update_stats - Update the board statistics counters.
4819 * @adapter: board private structure
4820 **/
4821void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4822{
2d86f139 4823 struct net_device *netdev = adapter->netdev;
9a799d71 4824 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 4825 u64 total_mpc = 0;
4826 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
eb985f09 4827 u64 non_eop_descs = 0, restart_queue = 0;
9a799d71 4828
94b982b2 4829 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 4830 u64 rsc_count = 0;
94b982b2 4831 u64 rsc_flush = 0;
d51019a4
PW		 4832 for (i = 0; i < 16; i++)
4833 adapter->hw_rx_no_dma_resources +=
4834 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 4835 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 4836 rsc_count += adapter->rx_ring[i]->rsc_count;
4837 rsc_flush += adapter->rx_ring[i]->rsc_flush;
94b982b2
MC		 4838 }
4839 adapter->rsc_total_count = rsc_count;
4840 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 4841 }
4842
7ca3bc58
JB		 4843 /* gather some stats to the adapter struct that are per queue */
4844 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4845 restart_queue += adapter->tx_ring[i]->restart_queue;
eb985f09 4846 adapter->restart_queue = restart_queue;
7ca3bc58
JB		 4847
4848 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4849 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
eb985f09 4850 adapter->non_eop_descs = non_eop_descs;
7ca3bc58 4851
9a799d71 4852 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 4853 for (i = 0; i < 8; i++) {
4854 /* for packet buffers not used, the register should read 0 */
4855 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4856 missed_rx += mpc;
4857 adapter->stats.mpc[i] += mpc;
4858 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 4859 if (hw->mac.type == ixgbe_mac_82598EB)
4860 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 4861 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4862 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4863 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4864 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 4865 if (hw->mac.type == ixgbe_mac_82599EB) {
4866 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4867 IXGBE_PXONRXCNT(i));
4868 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4869 IXGBE_PXOFFRXCNT(i));
4870 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 4871 } else {
4872 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4873 IXGBE_PXONRXC(i));
4874 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4875 IXGBE_PXOFFRXC(i));
4876 }
2f90b865
AD		 4877 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4878 IXGBE_PXONTXC(i));
2f90b865 4879 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 4880 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 4881 }
4882 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4883 /* work around hardware counting issue */
4884 adapter->stats.gprc -= missed_rx;
4885
4886 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350 4887 if (hw->mac.type == ixgbe_mac_82599EB) {
aad71918 4888 u64 tmp;
e8e26350 4889 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
aad71918
BG		 4890 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4891 adapter->stats.gorc += (tmp << 32);
e8e26350 4892 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
aad71918
BG		 4893 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4894 adapter->stats.gotc += (tmp << 32);
e8e26350
PW		 4895 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4896 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4897 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4898 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
c4cf55e5
PWJ		 4899 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4900 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c
YZ		 4901#ifdef IXGBE_FCOE
4902 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4903 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4904 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4905 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4906 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4907 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4908#endif /* IXGBE_FCOE */
e8e26350
PW		 4909 } else {
4910 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4911 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4912 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4913 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4914 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4915 }
9a799d71
AK		 4916 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4917 adapter->stats.bprc += bprc;
4918 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 4919 if (hw->mac.type == ixgbe_mac_82598EB)
4920 adapter->stats.mprc -= bprc;
9a799d71
AK		 4921 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4922 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4923 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4924 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4925 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4926 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4927 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 4928 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 4929 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4930 adapter->stats.lxontxc += lxon;
4931 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4932 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 4933 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4934 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 4935 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4936 /*
4937 * 82598 errata - tx of flow control packets is included in tx counters
4938 */
4939 xon_off_tot = lxon + lxoff;
4940 adapter->stats.gptc -= xon_off_tot;
4941 adapter->stats.mptc -= xon_off_tot;
4942 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 4943 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4944 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4945 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 4946 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4947 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 4948 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 4949 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4950 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4951 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4952 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4953 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 4954 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4955
4956 /* Fill out the OS statistics structure */
2d86f139 4957 netdev->stats.multicast = adapter->stats.mprc;
9a799d71
AK		 4958
4959 /* Rx Errors */
2d86f139 4960 netdev->stats.rx_errors = adapter->stats.crcerrs +
b4617240 4961 adapter->stats.rlec;
2d86f139
AK		 4962 netdev->stats.rx_dropped = 0;
4963 netdev->stats.rx_length_errors = adapter->stats.rlec;
4964 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4965 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 4966}
4967
4968/**
4969 * ixgbe_watchdog - Timer Call-back
4970 * @data: pointer to adapter cast into an unsigned long
4971 **/
4972static void ixgbe_watchdog(unsigned long data)
4973{
4974 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 4975 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 4976 u64 eics = 0;
4977 int i;
cf8280ee 4978
fe49f04a
AD		 4979 /*
4980 * Do the watchdog outside of interrupt context due to the lovely
4981 * delays that some of the newer hardware requires
4982 */
22d5a71b 4983
fe49f04a
AD		 4984 if (test_bit(__IXGBE_DOWN, &adapter->state))
4985 goto watchdog_short_circuit;
22d5a71b 4986
fe49f04a
AD		 4987 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4988 /*
4989 * for legacy and MSI interrupts don't set any bits
4990 * that are enabled for EIAM, because this operation
4991 * would set *both* EIMS and EICS for any bit in EIAM
4992 */
4993 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4994 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4995 goto watchdog_reschedule;
4996 }
4997
4998 /* get one bit for every active tx/rx interrupt vector */
4999 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5000 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5001 if (qv->rxr_count || qv->txr_count)
5002 eics |= ((u64)1 << i);
cf8280ee 5003 }
9a799d71 5004
fe49f04a
AD		 5005 /* Cause software interrupt to ensure rx rings are cleaned */
5006 ixgbe_irq_rearm_queues(adapter, eics);
5007
5008watchdog_reschedule:
5009 /* Reset the timer */
5010 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5011
5012watchdog_short_circuit:
cf8280ee
JB		 5013 schedule_work(&adapter->watchdog_task);
5014}
5015
e8e26350
PW		 5016/**
5017 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5018 * @work: pointer to work_struct containing our data
5019 **/
5020static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5021{
5022 struct ixgbe_adapter *adapter = container_of(work,
5023 struct ixgbe_adapter,
5024 multispeed_fiber_task);
5025 struct ixgbe_hw *hw = &adapter->hw;
5026 u32 autoneg;
8620a103 5027 bool negotiation;
e8e26350
PW		 5028
5029 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 5030 autoneg = hw->phy.autoneg_advertised;
5031 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103 5032 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
1097cd17 5033 hw->mac.autotry_restart = false;
8620a103
MC		 5034 if (hw->mac.ops.setup_link)
5035 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 5036 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5037 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5038}
5039
5040/**
5041 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5042 * @work: pointer to work_struct containing our data
5043 **/
5044static void ixgbe_sfp_config_module_task(struct work_struct *work)
5045{
5046 struct ixgbe_adapter *adapter = container_of(work,
5047 struct ixgbe_adapter,
5048 sfp_config_module_task);
5049 struct ixgbe_hw *hw = &adapter->hw;
5050 u32 err;
5051
5052 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 5053
5054 /* Time for electrical oscillations to settle down */
5055 msleep(100);
e8e26350 5056 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5057
e8e26350 5058 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 5059 dev_err(&adapter->pdev->dev, "failed to initialize because "
5060 "an unsupported SFP+ module type was detected.\n"
5061 "Reload the driver after installing a supported "
5062 "module.\n");
63d6e1d8 5063 unregister_netdev(adapter->netdev);
e8e26350
PW		 5064 return;
5065 }
5066 hw->mac.ops.setup_sfp(hw);
5067
8d1c3c07 5068 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 5069 /* This will also work for DA Twinax connections */
5070 schedule_work(&adapter->multispeed_fiber_task);
5071 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5072}
5073
c4cf55e5
PWJ		 5074/**
5075 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5076 * @work: pointer to work_struct containing our data
5077 **/
5078static void ixgbe_fdir_reinit_task(struct work_struct *work)
5079{
5080 struct ixgbe_adapter *adapter = container_of(work,
5081 struct ixgbe_adapter,
5082 fdir_reinit_task);
5083 struct ixgbe_hw *hw = &adapter->hw;
5084 int i;
5085
5086 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5087 for (i = 0; i < adapter->num_tx_queues; i++)
5088 set_bit(__IXGBE_FDIR_INIT_DONE,
4a0b9ca0 5089 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5
PWJ		 5090 } else {
5091 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
5092 "ignored adding FDIR ATR filters \n");
5093 }
5094 /* Done FDIR Re-initialization, enable transmits */
5095 netif_tx_start_all_queues(adapter->netdev);
5096}
5097
10eec955
JF		 5098static DEFINE_MUTEX(ixgbe_watchdog_lock);
5099
cf8280ee 5100/**
69888674
AD		 5101 * ixgbe_watchdog_task - worker thread to bring link up
5102 * @work: pointer to work_struct containing our data
cf8280ee
JB		 5103 **/
5104static void ixgbe_watchdog_task(struct work_struct *work)
5105{
5106 struct ixgbe_adapter *adapter = container_of(work,
5107 struct ixgbe_adapter,
5108 watchdog_task);
5109 struct net_device *netdev = adapter->netdev;
5110 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 5111 u32 link_speed;
5112 bool link_up;
bc59fcda
NS		 5113 int i;
5114 struct ixgbe_ring *tx_ring;
5115 int some_tx_pending = 0;
cf8280ee 5116
10eec955
JF		 5117 mutex_lock(&ixgbe_watchdog_lock);
5118
5119 link_up = adapter->link_up;
5120 link_speed = adapter->link_speed;
cf8280ee
JB		 5121
5122 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5123 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 5124 if (link_up) {
5125#ifdef CONFIG_DCB
5126 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5127 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 5128 hw->mac.ops.fc_enable(hw, i);
264857b8 5129 } else {
620fa036 5130 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5131 }
5132#else
620fa036 5133 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5134#endif
5135 }
5136
cf8280ee
JB		 5137 if (link_up ||
5138 time_after(jiffies, (adapter->link_check_timeout +
5139 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 5140 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 5141 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 5142 }
5143 adapter->link_up = link_up;
5144 adapter->link_speed = link_speed;
5145 }
9a799d71
AK		 5146
5147 if (link_up) {
5148 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 5149 bool flow_rx, flow_tx;
5150
5151 if (hw->mac.type == ixgbe_mac_82599EB) {
5152 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5153 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 5154 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5155 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 5156 } else {
5157 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5158 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 5159 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5160 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 5161 }
5162
a46e534b
JK		 5163 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
5164 "Flow Control: %s\n",
5165 netdev->name,
5166 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5167 "10 Gbps" :
5168 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5169 "1 Gbps" : "unknown speed")),
e8e26350
PW		 5170 ((flow_rx && flow_tx) ? "RX/TX" :
5171 (flow_rx ? "RX" :
5172 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 5173
5174 netif_carrier_on(netdev);
9a799d71
AK		 5175 } else {
5176 /* Force detection of hung controller */
5177 adapter->detect_tx_hung = true;
5178 }
5179 } else {
cf8280ee
JB		 5180 adapter->link_up = false;
5181 adapter->link_speed = 0;
9a799d71 5182 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 5183 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
5184 netdev->name);
9a799d71 5185 netif_carrier_off(netdev);
9a799d71
AK		 5186 }
5187 }
5188
bc59fcda
NS		 5189 if (!netif_carrier_ok(netdev)) {
5190 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 5191 tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5192 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5193 some_tx_pending = 1;
5194 break;
5195 }
5196 }
5197
5198 if (some_tx_pending) {
5199 /* We've lost link, so the controller stops DMA,
5200 * but we've got queued Tx work that's never going
5201 * to get done, so reset controller to flush Tx.
5202 * (Do the reset outside of interrupt context).
5203 */
5204 schedule_work(&adapter->reset_task);
5205 }
5206 }
5207
9a799d71 5208 ixgbe_update_stats(adapter);
10eec955 5209 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 5210}
5211
9a799d71 5212static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 5213 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5214 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 5215{
5216 struct ixgbe_adv_tx_context_desc *context_desc;
5217 unsigned int i;
5218 int err;
5219 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 5220 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5221 u32 mss_l4len_idx, l4len;
9a799d71
AK		 5222
5223 if (skb_is_gso(skb)) {
5224 if (skb_header_cloned(skb)) {
5225 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5226 if (err)
5227 return err;
5228 }
5229 l4len = tcp_hdrlen(skb);
5230 *hdr_len += l4len;
5231
8327d000 5232 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 5233 struct iphdr *iph = ip_hdr(skb);
5234 iph->tot_len = 0;
5235 iph->check = 0;
5236 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 5237 iph->daddr, 0,
5238 IPPROTO_TCP,
5239 0);
8e1e8a47 5240 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 5241 ipv6_hdr(skb)->payload_len = 0;
5242 tcp_hdr(skb)->check =
5243 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 5244 &ipv6_hdr(skb)->daddr,
5245 0, IPPROTO_TCP, 0);
9a799d71
AK		 5246 }
5247
5248 i = tx_ring->next_to_use;
5249
5250 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5251 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5252
5253 /* VLAN MACLEN IPLEN */
5254 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5255 vlan_macip_lens |=
5256 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5257 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 5258 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5259 *hdr_len += skb_network_offset(skb);
5260 vlan_macip_lens |=
5261 (skb_transport_header(skb) - skb_network_header(skb));
5262 *hdr_len +=
5263 (skb_transport_header(skb) - skb_network_header(skb));
5264 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5265 context_desc->seqnum_seed = 0;
5266
5267 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 5268 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 5269 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 5270
8327d000 5271 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 5272 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5273 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5274 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5275
5276 /* MSS L4LEN IDX */
9f8cdf4f 5277 mss_l4len_idx =
9a799d71
AK		 5278 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5279 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 5280 /* use index 1 for TSO */
5281 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5282 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5283
5284 tx_buffer_info->time_stamp = jiffies;
5285 tx_buffer_info->next_to_watch = i;
5286
5287 i++;
5288 if (i == tx_ring->count)
5289 i = 0;
5290 tx_ring->next_to_use = i;
5291
5292 return true;
5293 }
5294 return false;
5295}
5296
5297static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 5298 struct ixgbe_ring *tx_ring,
5299 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 5300{
5301 struct ixgbe_adv_tx_context_desc *context_desc;
5302 unsigned int i;
5303 struct ixgbe_tx_buffer *tx_buffer_info;
5304 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5305
5306 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5307 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5308 i = tx_ring->next_to_use;
5309 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5310 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5311
5312 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5313 vlan_macip_lens |=
5314 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5315 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 5316 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5317 if (skb->ip_summed == CHECKSUM_PARTIAL)
5318 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 5319 skb_network_header(skb));
9a799d71
AK		 5320
5321 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5322 context_desc->seqnum_seed = 0;
5323
5324 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 5325 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 5326
5327 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ca553980
GS		 5328 __be16 protocol;
5329
5330 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5331 const struct vlan_ethhdr *vhdr =
5332 (const struct vlan_ethhdr *)skb->data;
5333
5334 protocol = vhdr->h_vlan_encapsulated_proto;
5335 } else {
5336 protocol = skb->protocol;
5337 }
5338
5339 switch (protocol) {
09640e63 5340 case cpu_to_be16(ETH_P_IP):
9a799d71 5341 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 5342 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5343 type_tucmd_mlhl |=
b4617240 5344 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5345 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5346 type_tucmd_mlhl |=
5347 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5348 break;
09640e63 5349 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 5350 /* XXX what about other V6 headers?? */
5351 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5352 type_tucmd_mlhl |=
b4617240 5353 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5354 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5355 type_tucmd_mlhl |=
5356 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5357 break;
41825d71
AK		 5358 default:
5359 if (unlikely(net_ratelimit())) {
5360 DPRINTK(PROBE, WARNING,
5361 "partial checksum but proto=%x!\n",
5362 skb->protocol);
5363 }
5364 break;
5365 }
9a799d71
AK		 5366 }
5367
5368 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 5369 /* use index zero for tx checksum offload */
9a799d71
AK		 5370 context_desc->mss_l4len_idx = 0;
5371
5372 tx_buffer_info->time_stamp = jiffies;
5373 tx_buffer_info->next_to_watch = i;
9f8cdf4f 5374
9a799d71
AK		 5375 i++;
5376 if (i == tx_ring->count)
5377 i = 0;
5378 tx_ring->next_to_use = i;
5379
5380 return true;
5381 }
9f8cdf4f 5382
9a799d71
AK		 5383 return false;
5384}
5385
5386static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 5387 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 5388 struct sk_buff *skb, u32 tx_flags,
5389 unsigned int first)
9a799d71 5390{
e5a43549 5391 struct pci_dev *pdev = adapter->pdev;
9a799d71 5392 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 5393 unsigned int len;
5394 unsigned int total = skb->len;
9a799d71
AK		 5395 unsigned int offset = 0, size, count = 0, i;
5396 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5397 unsigned int f;
9a799d71
AK		 5398
5399 i = tx_ring->next_to_use;
5400
eacd73f7
YZ		 5401 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5402 /* excluding fcoe_crc_eof for FCoE */
5403 total -= sizeof(struct fcoe_crc_eof);
5404
5405 len = min(skb_headlen(skb), total);
9a799d71
AK		 5406 while (len) {
5407 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5408 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5409
5410 tx_buffer_info->length = size;
e5a43549
AD		 5411 tx_buffer_info->mapped_as_page = false;
5412 tx_buffer_info->dma = pci_map_single(pdev,
5413 skb->data + offset,
5414 size, PCI_DMA_TODEVICE);
5415 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5416 goto dma_error;
9a799d71
AK		 5417 tx_buffer_info->time_stamp = jiffies;
5418 tx_buffer_info->next_to_watch = i;
5419
5420 len -= size;
eacd73f7 5421 total -= size;
9a799d71
AK		 5422 offset += size;
5423 count++;
44df32c5
AD		 5424
5425 if (len) {
5426 i++;
5427 if (i == tx_ring->count)
5428 i = 0;
5429 }
9a799d71
AK		 5430 }
5431
5432 for (f = 0; f < nr_frags; f++) {
5433 struct skb_frag_struct *frag;
5434
5435 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 5436 len = min((unsigned int)frag->size, total);
e5a43549 5437 offset = frag->page_offset;
9a799d71
AK		 5438
5439 while (len) {
44df32c5
AD		 5440 i++;
5441 if (i == tx_ring->count)
5442 i = 0;
5443
9a799d71
AK		 5444 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5445 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5446
5447 tx_buffer_info->length = size;
e5a43549
AD		 5448 tx_buffer_info->dma = pci_map_page(adapter->pdev,
5449 frag->page,
5450 offset, size,
5451 PCI_DMA_TODEVICE);
5452 tx_buffer_info->mapped_as_page = true;
5453 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5454 goto dma_error;
9a799d71
AK		 5455 tx_buffer_info->time_stamp = jiffies;
5456 tx_buffer_info->next_to_watch = i;
5457
5458 len -= size;
eacd73f7 5459 total -= size;
9a799d71
AK		 5460 offset += size;
5461 count++;
9a799d71 5462 }
eacd73f7
YZ		 5463 if (total == 0)
5464 break;
9a799d71 5465 }
44df32c5 5466
9a799d71
AK		 5467 tx_ring->tx_buffer_info[i].skb = skb;
5468 tx_ring->tx_buffer_info[first].next_to_watch = i;
5469
e5a43549
AD		 5470 return count;
5471
5472dma_error:
5473 dev_err(&pdev->dev, "TX DMA map failed\n");
5474
5475 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5476 tx_buffer_info->dma = 0;
5477 tx_buffer_info->time_stamp = 0;
5478 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 5479 if (count)
5480 count--;
e5a43549
AD		 5481
5482 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f
RK		 5483 while (count--) {
5484 if (i==0)
e5a43549 5485 i += tx_ring->count;
c1fa347f 5486 i--;
e5a43549
AD		 5487 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5488 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5489 }
5490
e44d38e1 5491 return 0;
9a799d71
AK		 5492}
5493
5494static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 5495 struct ixgbe_ring *tx_ring,
5496 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 5497{
5498 union ixgbe_adv_tx_desc *tx_desc = NULL;
5499 struct ixgbe_tx_buffer *tx_buffer_info;
5500 u32 olinfo_status = 0, cmd_type_len = 0;
5501 unsigned int i;
5502 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5503
5504 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5505
5506 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5507
5508 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5509 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5510
5511 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5512 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5513
5514 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5515 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5516
4eeae6fd
PW		 5517 /* use index 1 context for tso */
5518 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5519 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5520 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 5521 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 5522
5523 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5524 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5525 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5526
eacd73f7
YZ		 5527 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5528 olinfo_status |= IXGBE_ADVTXD_CC;
5529 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5530 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5531 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5532 }
5533
9a799d71
AK		 5534 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5535
5536 i = tx_ring->next_to_use;
5537 while (count--) {
5538 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5539 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5540 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5541 tx_desc->read.cmd_type_len =
b4617240 5542 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 5543 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 5544 i++;
5545 if (i == tx_ring->count)
5546 i = 0;
5547 }
5548
5549 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5550
5551 /*
5552 * Force memory writes to complete before letting h/w
5553 * know there are new descriptors to fetch. (Only
5554 * applicable for weak-ordered memory model archs,
5555 * such as IA-64).
5556 */
5557 wmb();
5558
5559 tx_ring->next_to_use = i;
5560 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5561}
5562
c4cf55e5
PWJ		 5563static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5564 int queue, u32 tx_flags)
5565{
5566 /* Right now, we support IPv4 only */
5567 struct ixgbe_atr_input atr_input;
5568 struct tcphdr *th;
c4cf55e5
PWJ		 5569 struct iphdr *iph = ip_hdr(skb);
5570 struct ethhdr *eth = (struct ethhdr *)skb->data;
5571 u16 vlan_id, src_port, dst_port, flex_bytes;
5572 u32 src_ipv4_addr, dst_ipv4_addr;
5573 u8 l4type = 0;
5574
5575 /* check if we're UDP or TCP */
5576 if (iph->protocol == IPPROTO_TCP) {
5577 th = tcp_hdr(skb);
5578 src_port = th->source;
5579 dst_port = th->dest;
5580 l4type |= IXGBE_ATR_L4TYPE_TCP;
5581 /* l4type IPv4 type is 0, no need to assign */
c4cf55e5
PWJ		 5582 } else {
5583 /* Unsupported L4 header, just bail here */
5584 return;
5585 }
5586
5587 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5588
5589 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5590 IXGBE_TX_FLAGS_VLAN_SHIFT;
5591 src_ipv4_addr = iph->saddr;
5592 dst_ipv4_addr = iph->daddr;
5593 flex_bytes = eth->h_proto;
5594
5595 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5596 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5597 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5598 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5599 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5600 /* src and dst are inverted, think how the receiver sees them */
5601 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5602 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5603
5604 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5605 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5606}
5607
e092be60 5608static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5609 struct ixgbe_ring *tx_ring, int size)
e092be60 5610{
30eba97a 5611 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5612 /* Herbert's original patch had:
5613 * smp_mb__after_netif_stop_queue();
5614 * but since that doesn't exist yet, just open code it. */
5615 smp_mb();
5616
5617 /* We need to check again in a case another CPU has just
5618 * made room available. */
5619 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5620 return -EBUSY;
5621
5622 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 5623 netif_start_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 5624 ++tx_ring->restart_queue;
e092be60
AV		 5625 return 0;
5626}
5627
5628static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5629 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 5630{
5631 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5632 return 0;
5633 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5634}
5635
09a3b1f8
SH		 5636static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5637{
5638 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 5639 int txq = smp_processor_id();
09a3b1f8 5640
fdd3d631
KK		 5641 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
5642 while (unlikely(txq >= dev->real_num_tx_queues))
5643 txq -= dev->real_num_tx_queues;
5f715823 5644 return txq;
fdd3d631 5645 }
c4cf55e5 5646
5f715823
YZ		 5647#ifdef IXGBE_FCOE
5648 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5649 (skb->protocol == htons(ETH_P_FCOE))) {
5650 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5651 txq += adapter->ring_feature[RING_F_FCOE].mask;
5652 return txq;
5653 }
5654#endif
2ea186ae
JF		 5655 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5656 if (skb->priority == TC_PRIO_CONTROL)
5657 txq = adapter->ring_feature[RING_F_DCB].indices-1;
5658 else
5659 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
5660 >> 13;
5661 return txq;
5662 }
09a3b1f8
SH		 5663
5664 return skb_tx_hash(dev, skb);
5665}
5666
3b29a56d
SH		 5667static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5668 struct net_device *netdev)
9a799d71
AK		 5669{
5670 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5671 struct ixgbe_ring *tx_ring;
60d51134 5672 struct netdev_queue *txq;
9a799d71
AK		 5673 unsigned int first;
5674 unsigned int tx_flags = 0;
30eba97a 5675 u8 hdr_len = 0;
5f715823 5676 int tso;
9a799d71
AK		 5677 int count = 0;
5678 unsigned int f;
9f8cdf4f 5679
9f8cdf4f
JB		 5680 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5681 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 5682 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5683 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5f715823 5684 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
2f90b865
AD		 5685 }
5686 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5687 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5688 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2ea186ae
JF		 5689 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
5690 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5691 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 5692 }
eacd73f7 5693
4a0b9ca0 5694 tx_ring = adapter->tx_ring[skb->queue_mapping];
60127865 5695
eacd73f7 5696 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
09ad1cc0 5697 (skb->protocol == htons(ETH_P_FCOE))) {
eacd73f7 5698 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0 5699#ifdef IXGBE_FCOE
61a0f421
YZ		 5700#ifdef CONFIG_IXGBE_DCB
5701 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
5702 << IXGBE_TX_FLAGS_VLAN_SHIFT);
5703 tx_flags |= ((adapter->fcoe.up << 13)
5704 << IXGBE_TX_FLAGS_VLAN_SHIFT);
5705#endif
09ad1cc0
YZ		 5706#endif
5707 }
eacd73f7 5708 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 5709 if (skb_is_gso(skb) ||
5710 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 5711 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5712 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 5713 count++;
5714
9f8cdf4f
JB		 5715 count += TXD_USE_COUNT(skb_headlen(skb));
5716 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 5717 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5718
e092be60 5719 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 5720 adapter->tx_busy++;
9a799d71
AK		 5721 return NETDEV_TX_BUSY;
5722 }
9a799d71 5723
9a799d71 5724 first = tx_ring->next_to_use;
eacd73f7
YZ		 5725 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5726#ifdef IXGBE_FCOE
5727 /* setup tx offload for FCoE */
5728 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5729 if (tso < 0) {
5730 dev_kfree_skb_any(skb);
5731 return NETDEV_TX_OK;
5732 }
5733 if (tso)
5734 tx_flags |= IXGBE_TX_FLAGS_FSO;
5735#endif /* IXGBE_FCOE */
5736 } else {
5737 if (skb->protocol == htons(ETH_P_IP))
5738 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5739 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5740 if (tso < 0) {
5741 dev_kfree_skb_any(skb);
5742 return NETDEV_TX_OK;
5743 }
9a799d71 5744
eacd73f7
YZ		 5745 if (tso)
5746 tx_flags |= IXGBE_TX_FLAGS_TSO;
5747 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5748 (skb->ip_summed == CHECKSUM_PARTIAL))
5749 tx_flags |= IXGBE_TX_FLAGS_CSUM;
5750 }
9a799d71 5751
eacd73f7 5752 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 5753 if (count) {
c4cf55e5
PWJ		 5754 /* add the ATR filter if ATR is on */
5755 if (tx_ring->atr_sample_rate) {
5756 ++tx_ring->atr_count;
5757 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5758 test_bit(__IXGBE_FDIR_INIT_DONE,
5759 &tx_ring->reinit_state)) {
5760 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5761 tx_flags);
5762 tx_ring->atr_count = 0;
5763 }
5764 }
60d51134
ED		 5765 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
5766 txq->tx_bytes += skb->len;
5767 txq->tx_packets++;
44df32c5
AD		 5768 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5769 hdr_len);
44df32c5 5770 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 5771
44df32c5
AD		 5772 } else {
5773 dev_kfree_skb_any(skb);
5774 tx_ring->tx_buffer_info[first].time_stamp = 0;
5775 tx_ring->next_to_use = first;
5776 }
9a799d71
AK		 5777
5778 return NETDEV_TX_OK;
5779}
5780
9a799d71
AK		 5781/**
5782 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5783 * @netdev: network interface device structure
5784 * @p: pointer to an address structure
5785 *
5786 * Returns 0 on success, negative on failure
5787 **/
5788static int ixgbe_set_mac(struct net_device *netdev, void *p)
5789{
5790 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 5791 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5792 struct sockaddr *addr = p;
5793
5794 if (!is_valid_ether_addr(addr->sa_data))
5795 return -EADDRNOTAVAIL;
5796
5797 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 5798 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 5799
1cdd1ec8
GR		 5800 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
5801 IXGBE_RAH_AV);
9a799d71
AK		 5802
5803 return 0;
5804}
5805
6b73e10d
BH		 5806static int
5807ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5808{
5809 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5810 struct ixgbe_hw *hw = &adapter->hw;
5811 u16 value;
5812 int rc;
5813
5814 if (prtad != hw->phy.mdio.prtad)
5815 return -EINVAL;
5816 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5817 if (!rc)
5818 rc = value;
5819 return rc;
5820}
5821
5822static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5823 u16 addr, u16 value)
5824{
5825 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5826 struct ixgbe_hw *hw = &adapter->hw;
5827
5828 if (prtad != hw->phy.mdio.prtad)
5829 return -EINVAL;
5830 return hw->phy.ops.write_reg(hw, addr, devad, value);
5831}
5832
5833static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5834{
5835 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5836
5837 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5838}
5839
0365e6e4
PW		 5840/**
5841 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 5842 * netdev->dev_addrs
0365e6e4
PW		 5843 * @netdev: network interface device structure
5844 *
5845 * Returns non-zero on failure
5846 **/
5847static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5848{
5849 int err = 0;
5850 struct ixgbe_adapter *adapter = netdev_priv(dev);
5851 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5852
5853 if (is_valid_ether_addr(mac->san_addr)) {
5854 rtnl_lock();
5855 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5856 rtnl_unlock();
5857 }
5858 return err;
5859}
5860
5861/**
5862 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 5863 * netdev->dev_addrs
0365e6e4
PW		 5864 * @netdev: network interface device structure
5865 *
5866 * Returns non-zero on failure
5867 **/
5868static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5869{
5870 int err = 0;
5871 struct ixgbe_adapter *adapter = netdev_priv(dev);
5872 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5873
5874 if (is_valid_ether_addr(mac->san_addr)) {
5875 rtnl_lock();
5876 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5877 rtnl_unlock();
5878 }
5879 return err;
5880}
5881
9a799d71
AK		 5882#ifdef CONFIG_NET_POLL_CONTROLLER
5883/*
5884 * Polling 'interrupt' - used by things like netconsole to send skbs
5885 * without having to re-enable interrupts. It's not called while
5886 * the interrupt routine is executing.
5887 */
5888static void ixgbe_netpoll(struct net_device *netdev)
5889{
5890 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 5891 int i;
9a799d71 5892
1a647bd2
AD		 5893 /* if interface is down do nothing */
5894 if (test_bit(__IXGBE_DOWN, &adapter->state))
5895 return;
5896
9a799d71 5897 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 5898 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5899 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5900 for (i = 0; i < num_q_vectors; i++) {
5901 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5902 ixgbe_msix_clean_many(0, q_vector);
5903 }
5904 } else {
5905 ixgbe_intr(adapter->pdev->irq, netdev);
5906 }
9a799d71 5907 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 5908}
5909#endif
5910
0edc3527
SH		 5911static const struct net_device_ops ixgbe_netdev_ops = {
5912 .ndo_open = ixgbe_open,
5913 .ndo_stop = ixgbe_close,
00829823 5914 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 5915 .ndo_select_queue = ixgbe_select_queue,
e90d400c 5916 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 5917 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5918 .ndo_validate_addr = eth_validate_addr,
5919 .ndo_set_mac_address = ixgbe_set_mac,
5920 .ndo_change_mtu = ixgbe_change_mtu,
5921 .ndo_tx_timeout = ixgbe_tx_timeout,
5922 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5923 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5924 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 5925 .ndo_do_ioctl = ixgbe_ioctl,
0edc3527
SH		 5926#ifdef CONFIG_NET_POLL_CONTROLLER
5927 .ndo_poll_controller = ixgbe_netpoll,
5928#endif
332d4a7d
YZ		 5929#ifdef IXGBE_FCOE
5930 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5931 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 5932 .ndo_fcoe_enable = ixgbe_fcoe_enable,
5933 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 5934 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 5935#endif /* IXGBE_FCOE */
0edc3527
SH		 5936};
5937
1cdd1ec8
GR		 5938static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
5939 const struct ixgbe_info *ii)
5940{
5941#ifdef CONFIG_PCI_IOV
5942 struct ixgbe_hw *hw = &adapter->hw;
5943 int err;
5944
5945 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
5946 return;
5947
5948 /* The 82599 supports up to 64 VFs per physical function
5949 * but this implementation limits allocation to 63 so that
5950 * basic networking resources are still available to the
5951 * physical function
5952 */
5953 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
5954 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
5955 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
5956 if (err) {
5957 DPRINTK(PROBE, ERR,
5958 "Failed to enable PCI sriov: %d\n", err);
5959 goto err_novfs;
5960 }
5961 /* If call to enable VFs succeeded then allocate memory
5962 * for per VF control structures.
5963 */
5964 adapter->vfinfo =
5965 kcalloc(adapter->num_vfs,
5966 sizeof(struct vf_data_storage), GFP_KERNEL);
5967 if (adapter->vfinfo) {
5968 /* Now that we're sure SR-IOV is enabled
5969 * and memory allocated set up the mailbox parameters
5970 */
5971 ixgbe_init_mbx_params_pf(hw);
5972 memcpy(&hw->mbx.ops, ii->mbx_ops,
5973 sizeof(hw->mbx.ops));
5974
5975 /* Disable RSC when in SR-IOV mode */
5976 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
5977 IXGBE_FLAG2_RSC_ENABLED);
5978 return;
5979 }
5980
5981 /* Oh oh */
5982 DPRINTK(PROBE, ERR,
5983 "Unable to allocate memory for VF "
5984 "Data Storage - SRIOV disabled\n");
5985 pci_disable_sriov(adapter->pdev);
5986
5987err_novfs:
5988 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
5989 adapter->num_vfs = 0;
5990#endif /* CONFIG_PCI_IOV */
5991}
5992
9a799d71
AK		 5993/**
5994 * ixgbe_probe - Device Initialization Routine
5995 * @pdev: PCI device information struct
5996 * @ent: entry in ixgbe_pci_tbl
5997 *
5998 * Returns 0 on success, negative on failure
5999 *
6000 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6001 * The OS initialization, configuring of the adapter private structure,
6002 * and a hardware reset occur.
6003 **/
6004static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 6005 const struct pci_device_id *ent)
9a799d71
AK		 6006{
6007 struct net_device *netdev;
6008 struct ixgbe_adapter *adapter = NULL;
6009 struct ixgbe_hw *hw;
6010 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 6011 static int cards_found;
6012 int i, err, pci_using_dac;
c85a2618 6013 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 6014#ifdef IXGBE_FCOE
6015 u16 device_caps;
6016#endif
c44ade9e 6017 u32 part_num, eec;
9a799d71 6018
9ce77666 6019 err = pci_enable_device_mem(pdev);
9a799d71
AK		 6020 if (err)
6021 return err;
6022
6a35528a
YH		 6023 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
6024 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
9a799d71
AK		 6025 pci_using_dac = 1;
6026 } else {
284901a9 6027 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 6028 if (err) {
284901a9 6029 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 6030 if (err) {
b4617240
PW		 6031 dev_err(&pdev->dev, "No usable DMA "
6032 "configuration, aborting\n");
9a799d71
AK		 6033 goto err_dma;
6034 }
6035 }
6036 pci_using_dac = 0;
6037 }
6038
9ce77666 6039 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6040 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 6041 if (err) {
9ce77666 6042 dev_err(&pdev->dev,
6043 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 6044 goto err_pci_reg;
6045 }
6046
19d5afd4 6047 pci_enable_pcie_error_reporting(pdev);
6fabd715 6048
9a799d71 6049 pci_set_master(pdev);
fb3b27bc 6050 pci_save_state(pdev);
9a799d71 6051
c85a2618
JF		 6052 if (ii->mac == ixgbe_mac_82598EB)
6053 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6054 else
6055 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6056
6057 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6058#ifdef IXGBE_FCOE
6059 indices += min_t(unsigned int, num_possible_cpus(),
6060 IXGBE_MAX_FCOE_INDICES);
6061#endif
6062 indices = min_t(unsigned int, indices, MAX_TX_QUEUES);
6063 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 6064 if (!netdev) {
6065 err = -ENOMEM;
6066 goto err_alloc_etherdev;
6067 }
6068
9a799d71
AK		 6069 SET_NETDEV_DEV(netdev, &pdev->dev);
6070
6071 pci_set_drvdata(pdev, netdev);
6072 adapter = netdev_priv(netdev);
6073
6074 adapter->netdev = netdev;
6075 adapter->pdev = pdev;
6076 hw = &adapter->hw;
6077 hw->back = adapter;
6078 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6079
05857980
JK		 6080 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6081 pci_resource_len(pdev, 0));
9a799d71
AK		 6082 if (!hw->hw_addr) {
6083 err = -EIO;
6084 goto err_ioremap;
6085 }
6086
6087 for (i = 1; i <= 5; i++) {
6088 if (pci_resource_len(pdev, i) == 0)
6089 continue;
6090 }
6091
0edc3527 6092 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 6093 ixgbe_set_ethtool_ops(netdev);
9a799d71 6094 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 6095 strcpy(netdev->name, pci_name(pdev));
6096
9a799d71
AK		 6097 adapter->bd_number = cards_found;
6098
9a799d71
AK		 6099 /* Setup hw api */
6100 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 6101 hw->mac.type = ii->mac;
9a799d71 6102
c44ade9e
JB		 6103 /* EEPROM */
6104 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6105 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6106 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6107 if (!(eec & (1 << 8)))
6108 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6109
6110 /* PHY */
6111 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 6112 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 6113 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6114 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6115 hw->phy.mdio.mmds = 0;
6116 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6117 hw->phy.mdio.dev = netdev;
6118 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6119 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 6120
6121 /* set up this timer and work struct before calling get_invariants
6122 * which might start the timer
6123 */
6124 init_timer(&adapter->sfp_timer);
6125 adapter->sfp_timer.function = &ixgbe_sfp_timer;
6126 adapter->sfp_timer.data = (unsigned long) adapter;
6127
6128 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 6129
e8e26350
PW		 6130 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6131 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6132
6133 /* a new SFP+ module arrival, called from GPI SDP2 context */
6134 INIT_WORK(&adapter->sfp_config_module_task,
6135 ixgbe_sfp_config_module_task);
6136
8ca783ab 6137 ii->get_invariants(hw);
9a799d71
AK		 6138
6139 /* setup the private structure */
6140 err = ixgbe_sw_init(adapter);
6141 if (err)
6142 goto err_sw_init;
6143
e86bff0e
DS		 6144 /* Make it possible the adapter to be woken up via WOL */
6145 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6146 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6147
bf069c97
DS		 6148 /*
6149 * If there is a fan on this device and it has failed log the
6150 * failure.
6151 */
6152 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6153 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6154 if (esdp & IXGBE_ESDP_SDP1)
6155 DPRINTK(PROBE, CRIT,
6156 "Fan has stopped, replace the adapter\n");
6157 }
6158
c44ade9e
JB		 6159 /* reset_hw fills in the perm_addr as well */
6160 err = hw->mac.ops.reset_hw(hw);
8ca783ab
DS		 6161 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6162 hw->mac.type == ixgbe_mac_82598EB) {
6163 /*
6164 * Start a kernel thread to watch for a module to arrive.
6165 * Only do this for 82598, since 82599 will generate
6166 * interrupts on module arrival.
6167 */
6168 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6169 mod_timer(&adapter->sfp_timer,
6170 round_jiffies(jiffies + (2 * HZ)));
6171 err = 0;
6172 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 6173 dev_err(&adapter->pdev->dev, "failed to initialize because "
6174 "an unsupported SFP+ module type was detected.\n"
6175 "Reload the driver after installing a supported "
6176 "module.\n");
04f165ef
PW		 6177 goto err_sw_init;
6178 } else if (err) {
c44ade9e
JB		 6179 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
6180 goto err_sw_init;
6181 }
6182
1cdd1ec8
GR		 6183 ixgbe_probe_vf(adapter, ii);
6184
9a799d71 6185 netdev->features = NETIF_F_SG |
b4617240
PW		 6186 NETIF_F_IP_CSUM |
6187 NETIF_F_HW_VLAN_TX |
6188 NETIF_F_HW_VLAN_RX |
6189 NETIF_F_HW_VLAN_FILTER;
9a799d71 6190
e9990a9c 6191 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 6192 netdev->features |= NETIF_F_TSO;
9a799d71 6193 netdev->features |= NETIF_F_TSO6;
78b6f4ce 6194 netdev->features |= NETIF_F_GRO;
ad31c402 6195
45a5ead0
JB		 6196 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6197 netdev->features |= NETIF_F_SCTP_CSUM;
6198
ad31c402
JK		 6199 netdev->vlan_features |= NETIF_F_TSO;
6200 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 6201 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 6202 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 6203 netdev->vlan_features |= NETIF_F_SG;
6204
1cdd1ec8
GR		 6205 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6206 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6207 IXGBE_FLAG_DCB_ENABLED);
2f90b865
AD		 6208 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6209 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6210
7a6b6f51 6211#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 6212 netdev->dcbnl_ops = &dcbnl_ops;
6213#endif
6214
eacd73f7 6215#ifdef IXGBE_FCOE
0d551589 6216 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 6217 if (hw->mac.ops.get_device_caps) {
6218 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 6219 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6220 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 6221 }
6222 }
6223#endif /* IXGBE_FCOE */
9a799d71
AK		 6224 if (pci_using_dac)
6225 netdev->features |= NETIF_F_HIGHDMA;
6226
0c19d6af 6227 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 6228 netdev->features |= NETIF_F_LRO;
6229
9a799d71 6230 /* make sure the EEPROM is good */
c44ade9e 6231 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 6232 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
6233 err = -EIO;
6234 goto err_eeprom;
6235 }
6236
6237 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6238 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6239
c44ade9e
JB		 6240 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6241 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 6242 err = -EIO;
6243 goto err_eeprom;
6244 }
6245
6246 init_timer(&adapter->watchdog_timer);
6247 adapter->watchdog_timer.function = &ixgbe_watchdog;
6248 adapter->watchdog_timer.data = (unsigned long)adapter;
6249
6250 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 6251 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 6252
021230d4
AV		 6253 err = ixgbe_init_interrupt_scheme(adapter);
6254 if (err)
6255 goto err_sw_init;
9a799d71 6256
e8e26350
PW		 6257 switch (pdev->device) {
6258 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 6259 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6260 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 6261 break;
6262 default:
6263 adapter->wol = 0;
6264 break;
6265 }
e8e26350
PW		 6266 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6267
04f165ef
PW		 6268 /* pick up the PCI bus settings for reporting later */
6269 hw->mac.ops.get_bus_info(hw);
6270
9a799d71 6271 /* print bus type/speed/width info */
7c510e4b 6272 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 6273 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6274 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6275 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6276 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6277 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 6278 "Unknown"),
7c510e4b 6279 netdev->dev_addr);
c44ade9e 6280 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 6281 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6282 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
6283 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6284 (part_num >> 8), (part_num & 0xff));
6285 else
6286 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6287 hw->mac.type, hw->phy.type,
6288 (part_num >> 8), (part_num & 0xff));
9a799d71 6289
e8e26350 6290 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 6291 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 6292 "this card is not sufficient for optimal "
6293 "performance.\n");
0c254d86 6294 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 6295 "PCI-Express slot is required.\n");
0c254d86
AK		 6296 }
6297
34b0368c
PWJ		 6298 /* save off EEPROM version number */
6299 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6300
9a799d71 6301 /* reset the hardware with the new settings */
794caeb2 6302 err = hw->mac.ops.start_hw(hw);
c44ade9e 6303
794caeb2
PWJ		 6304 if (err == IXGBE_ERR_EEPROM_VERSION) {
6305 /* We are running on a pre-production device, log a warning */
6306 dev_warn(&pdev->dev, "This device is a pre-production "
6307 "adapter/LOM. Please be aware there may be issues "
6308 "associated with your hardware. If you are "
6309 "experiencing problems please contact your Intel or "
6310 "hardware representative who provided you with this "
6311 "hardware.\n");
6312 }
9a799d71
AK		 6313 strcpy(netdev->name, "eth%d");
6314 err = register_netdev(netdev);
6315 if (err)
6316 goto err_register;
6317
54386467
JB		 6318 /* carrier off reporting is important to ethtool even BEFORE open */
6319 netif_carrier_off(netdev);
6320
c4cf55e5
PWJ		 6321 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6322 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6323 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6324
5dd2d332 6325#ifdef CONFIG_IXGBE_DCA
652f093f 6326 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 6327 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 6328 ixgbe_setup_dca(adapter);
6329 }
6330#endif
1cdd1ec8
GR		 6331 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6332 DPRINTK(PROBE, INFO, "IOV is enabled with %d VFs\n",
6333 adapter->num_vfs);
6334 for (i = 0; i < adapter->num_vfs; i++)
6335 ixgbe_vf_configuration(pdev, (i | 0x10000000));
6336 }
6337
0365e6e4
PW		 6338 /* add san mac addr to netdev */
6339 ixgbe_add_sanmac_netdev(netdev);
9a799d71
AK		 6340
6341 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
6342 cards_found++;
6343 return 0;
6344
6345err_register:
5eba3699 6346 ixgbe_release_hw_control(adapter);
7a921c93 6347 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 6348err_sw_init:
6349err_eeprom:
1cdd1ec8
GR		 6350 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6351 ixgbe_disable_sriov(adapter);
c4900be0
DS		 6352 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6353 del_timer_sync(&adapter->sfp_timer);
6354 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6355 cancel_work_sync(&adapter->multispeed_fiber_task);
6356 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 6357 iounmap(hw->hw_addr);
6358err_ioremap:
6359 free_netdev(netdev);
6360err_alloc_etherdev:
9ce77666 6361 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6362 IORESOURCE_MEM));
9a799d71
AK		 6363err_pci_reg:
6364err_dma:
6365 pci_disable_device(pdev);
6366 return err;
6367}
6368
6369/**
6370 * ixgbe_remove - Device Removal Routine
6371 * @pdev: PCI device information struct
6372 *
6373 * ixgbe_remove is called by the PCI subsystem to alert the driver
6374 * that it should release a PCI device. The could be caused by a
6375 * Hot-Plug event, or because the driver is going to be removed from
6376 * memory.
6377 **/
6378static void __devexit ixgbe_remove(struct pci_dev *pdev)
6379{
6380 struct net_device *netdev = pci_get_drvdata(pdev);
6381 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6382
6383 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 6384 /* clear the module not found bit to make sure the worker won't
6385 * reschedule
6386 */
6387 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 6388 del_timer_sync(&adapter->watchdog_timer);
6389
c4900be0
DS		 6390 del_timer_sync(&adapter->sfp_timer);
6391 cancel_work_sync(&adapter->watchdog_task);
6392 cancel_work_sync(&adapter->sfp_task);
1097cd17
MC		 6393 if (adapter->hw.phy.multispeed_fiber) {
6394 struct ixgbe_hw *hw = &adapter->hw;
6395 /*
6396 * Restart clause 37 autoneg, disable and re-enable
6397 * the tx laser, to clear & alert the link partner
6398 * that it needs to restart autotry
6399 */
6400 hw->mac.autotry_restart = true;
6401 hw->mac.ops.flap_tx_laser(hw);
6402 }
e8e26350
PW		 6403 cancel_work_sync(&adapter->multispeed_fiber_task);
6404 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 6405 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6406 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6407 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 6408 flush_scheduled_work();
6409
5dd2d332 6410#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6411 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6412 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6413 dca_remove_requester(&pdev->dev);
6414 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6415 }
6416
6417#endif
332d4a7d
YZ		 6418#ifdef IXGBE_FCOE
6419 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6420 ixgbe_cleanup_fcoe(adapter);
6421
6422#endif /* IXGBE_FCOE */
0365e6e4
PW		 6423
6424 /* remove the added san mac */
6425 ixgbe_del_sanmac_netdev(netdev);
6426
c4900be0
DS		 6427 if (netdev->reg_state == NETREG_REGISTERED)
6428 unregister_netdev(netdev);
9a799d71 6429
1cdd1ec8
GR		 6430 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6431 ixgbe_disable_sriov(adapter);
6432
7a921c93 6433 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 6434
021230d4 6435 ixgbe_release_hw_control(adapter);
9a799d71
AK		 6436
6437 iounmap(adapter->hw.hw_addr);
9ce77666 6438 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6439 IORESOURCE_MEM));
9a799d71 6440
021230d4 6441 DPRINTK(PROBE, INFO, "complete\n");
021230d4 6442
9a799d71
AK		 6443 free_netdev(netdev);
6444
19d5afd4 6445 pci_disable_pcie_error_reporting(pdev);
6fabd715 6446
9a799d71
AK		 6447 pci_disable_device(pdev);
6448}
6449
6450/**
6451 * ixgbe_io_error_detected - called when PCI error is detected
6452 * @pdev: Pointer to PCI device
6453 * @state: The current pci connection state
6454 *
6455 * This function is called after a PCI bus error affecting
6456 * this device has been detected.
6457 */
6458static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 6459 pci_channel_state_t state)
9a799d71
AK		 6460{
6461 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6462 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6463
6464 netif_device_detach(netdev);
6465
3044b8d1
BL		 6466 if (state == pci_channel_io_perm_failure)
6467 return PCI_ERS_RESULT_DISCONNECT;
6468
9a799d71
AK		 6469 if (netif_running(netdev))
6470 ixgbe_down(adapter);
6471 pci_disable_device(pdev);
6472
b4617240 6473 /* Request a slot reset. */
9a799d71
AK		 6474 return PCI_ERS_RESULT_NEED_RESET;
6475}
6476
6477/**
6478 * ixgbe_io_slot_reset - called after the pci bus has been reset.
6479 * @pdev: Pointer to PCI device
6480 *
6481 * Restart the card from scratch, as if from a cold-boot.
6482 */
6483static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
6484{
6485 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6486 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 6487 pci_ers_result_t result;
6488 int err;
9a799d71 6489
9ce77666 6490 if (pci_enable_device_mem(pdev)) {
9a799d71 6491 DPRINTK(PROBE, ERR,
b4617240 6492 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 6493 result = PCI_ERS_RESULT_DISCONNECT;
6494 } else {
6495 pci_set_master(pdev);
6496 pci_restore_state(pdev);
c0e1f68b 6497 pci_save_state(pdev);
9a799d71 6498
dd4d8ca6 6499 pci_wake_from_d3(pdev, false);
9a799d71 6500
6fabd715 6501 ixgbe_reset(adapter);
88512539 6502 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 6503 result = PCI_ERS_RESULT_RECOVERED;
6504 }
6505
6506 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6507 if (err) {
6508 dev_err(&pdev->dev,
6509 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6510 /* non-fatal, continue */
6511 }
9a799d71 6512
6fabd715 6513 return result;
9a799d71
AK		 6514}
6515
6516/**
6517 * ixgbe_io_resume - called when traffic can start flowing again.
6518 * @pdev: Pointer to PCI device
6519 *
6520 * This callback is called when the error recovery driver tells us that
6521 * its OK to resume normal operation.
6522 */
6523static void ixgbe_io_resume(struct pci_dev *pdev)
6524{
6525 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6526 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6527
6528 if (netif_running(netdev)) {
6529 if (ixgbe_up(adapter)) {
6530 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6531 return;
6532 }
6533 }
6534
6535 netif_device_attach(netdev);
9a799d71
AK		 6536}
6537
6538static struct pci_error_handlers ixgbe_err_handler = {
6539 .error_detected = ixgbe_io_error_detected,
6540 .slot_reset = ixgbe_io_slot_reset,
6541 .resume = ixgbe_io_resume,
6542};
6543
6544static struct pci_driver ixgbe_driver = {
6545 .name = ixgbe_driver_name,
6546 .id_table = ixgbe_pci_tbl,
6547 .probe = ixgbe_probe,
6548 .remove = __devexit_p(ixgbe_remove),
6549#ifdef CONFIG_PM
6550 .suspend = ixgbe_suspend,
6551 .resume = ixgbe_resume,
6552#endif
6553 .shutdown = ixgbe_shutdown,
6554 .err_handler = &ixgbe_err_handler
6555};
6556
6557/**
6558 * ixgbe_init_module - Driver Registration Routine
6559 *
6560 * ixgbe_init_module is the first routine called when the driver is
6561 * loaded. All it does is register with the PCI subsystem.
6562 **/
6563static int __init ixgbe_init_module(void)
6564{
6565 int ret;
6566 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6567 ixgbe_driver_string, ixgbe_driver_version);
6568
6569 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6570
5dd2d332 6571#ifdef CONFIG_IXGBE_DCA
bd0362dd 6572 dca_register_notify(&dca_notifier);
bd0362dd 6573#endif
5dd2d332 6574
9a799d71
AK		 6575 ret = pci_register_driver(&ixgbe_driver);
6576 return ret;
6577}
b4617240 6578
9a799d71
AK		 6579module_init(ixgbe_init_module);
6580
6581/**
6582 * ixgbe_exit_module - Driver Exit Cleanup Routine
6583 *
6584 * ixgbe_exit_module is called just before the driver is removed
6585 * from memory.
6586 **/
6587static void __exit ixgbe_exit_module(void)
6588{
5dd2d332 6589#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6590 dca_unregister_notify(&dca_notifier);
6591#endif
9a799d71
AK		 6592 pci_unregister_driver(&ixgbe_driver);
6593}
bd0362dd 6594
5dd2d332 6595#ifdef CONFIG_IXGBE_DCA
bd0362dd 6596static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 6597 void *p)
bd0362dd
JC		 6598{
6599 int ret_val;
6600
6601 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 6602 __ixgbe_notify_dca);
bd0362dd
JC		 6603
6604 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6605}
b453368d 6606
5dd2d332 6607#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 6608#ifdef DEBUG
6609/**
6610 * ixgbe_get_hw_dev_name - return device name string
6611 * used by hardware layer to print debugging information
6612 **/
6613char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6614{
6615 struct ixgbe_adapter *adapter = hw->back;
6616 return adapter->netdev->name;
6617}
bd0362dd 6618
b453368d 6619#endif
9a799d71
AK		 6620module_exit(ixgbe_exit_module);
6621
6622/* ixgbe_main.c */
kernel source for telekom puls (alcatel/mediatek)