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ixgbe: dcb, do not tag tc_prio_control frames
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71 38#include <linux/ipv6.h>
5a0e3ad6 39#include <linux/slab.h>
9a799d71
AK		 40#include <net/checksum.h>
41#include <net/ip6_checksum.h>
42#include <linux/ethtool.h>
43#include <linux/if_vlan.h>
eacd73f7 44#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 45
46#include "ixgbe.h"
47#include "ixgbe_common.h"
ee5f784a 48#include "ixgbe_dcb_82599.h"
1cdd1ec8 49#include "ixgbe_sriov.h"
9a799d71
AK		 50
51char ixgbe_driver_name[] = "ixgbe";
9c8eb720 52static const char ixgbe_driver_string[] =
b4617240 53 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 54
92eb879f 55#define DRV_VERSION "2.0.62-k2"
9c8eb720 56const char ixgbe_driver_version[] = DRV_VERSION;
8c47eaa7 57static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
9a799d71
AK		 58
59static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 60 [board_82598] = &ixgbe_82598_info,
e8e26350 61 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 62};
63
64/* ixgbe_pci_tbl - PCI Device ID Table
65 *
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
a3aa1884 72static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
74 board_82598 },
9a799d71 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 76 board_82598 },
9a799d71 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 78 board_82598 },
0befdb3e
JB		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
80 board_82598 },
3845bec0
PWJ		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
82 board_82598 },
9a799d71 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 84 board_82598 },
8d792cd9
JB		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
86 board_82598 },
c4900be0
DS		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
90 board_82598 },
b95f5fcb
JB		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
92 board_82598 },
c4900be0
DS		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
94 board_82598 },
2f21bdd3
DS		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
96 board_82598 },
e8e26350
PW		 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
98 board_82599 },
1fcf03e6
PWJ		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
100 board_82599 },
74757d49
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
102 board_82599 },
e8e26350
PW		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
104 board_82599 },
38ad1c8e
DS		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
106 board_82599 },
dbfec662
DS		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
108 board_82599 },
8911184f
PWJ		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
110 board_82599 },
312eb931
DS		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
112 board_82599 },
9a799d71
AK		 113
114 /* required last entry */
115 {0, }
116};
117MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
118
5dd2d332 119#ifdef CONFIG_IXGBE_DCA
bd0362dd 120static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 121 void *p);
bd0362dd
JC		 122static struct notifier_block dca_notifier = {
123 .notifier_call = ixgbe_notify_dca,
124 .next = NULL,
125 .priority = 0
126};
127#endif
128
1cdd1ec8
GR		 129#ifdef CONFIG_PCI_IOV
130static unsigned int max_vfs;
131module_param(max_vfs, uint, 0);
132MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
133 "per physical function");
134#endif /* CONFIG_PCI_IOV */
135
9a799d71
AK		 136MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
137MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
138MODULE_LICENSE("GPL");
139MODULE_VERSION(DRV_VERSION);
140
141#define DEFAULT_DEBUG_LEVEL_SHIFT 3
142
1cdd1ec8
GR		 143static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
144{
145 struct ixgbe_hw *hw = &adapter->hw;
146 u32 gcr;
147 u32 gpie;
148 u32 vmdctl;
149
150#ifdef CONFIG_PCI_IOV
151 /* disable iov and allow time for transactions to clear */
152 pci_disable_sriov(adapter->pdev);
153#endif
154
155 /* turn off device IOV mode */
156 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
157 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
158 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
159 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
160 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
161 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
162
163 /* set default pool back to 0 */
164 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
165 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
166 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
167
168 /* take a breather then clean up driver data */
169 msleep(100);
170 if (adapter->vfinfo)
171 kfree(adapter->vfinfo);
172 adapter->vfinfo = NULL;
173
174 adapter->num_vfs = 0;
175 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
176}
177
dcd79aeb
TI		 178struct ixgbe_reg_info {
179 u32 ofs;
180 char *name;
181};
182
183static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
184
185 /* General Registers */
186 {IXGBE_CTRL, "CTRL"},
187 {IXGBE_STATUS, "STATUS"},
188 {IXGBE_CTRL_EXT, "CTRL_EXT"},
189
190 /* Interrupt Registers */
191 {IXGBE_EICR, "EICR"},
192
193 /* RX Registers */
194 {IXGBE_SRRCTL(0), "SRRCTL"},
195 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
196 {IXGBE_RDLEN(0), "RDLEN"},
197 {IXGBE_RDH(0), "RDH"},
198 {IXGBE_RDT(0), "RDT"},
199 {IXGBE_RXDCTL(0), "RXDCTL"},
200 {IXGBE_RDBAL(0), "RDBAL"},
201 {IXGBE_RDBAH(0), "RDBAH"},
202
203 /* TX Registers */
204 {IXGBE_TDBAL(0), "TDBAL"},
205 {IXGBE_TDBAH(0), "TDBAH"},
206 {IXGBE_TDLEN(0), "TDLEN"},
207 {IXGBE_TDH(0), "TDH"},
208 {IXGBE_TDT(0), "TDT"},
209 {IXGBE_TXDCTL(0), "TXDCTL"},
210
211 /* List Terminator */
212 {}
213};
214
215
216/*
217 * ixgbe_regdump - register printout routine
218 */
219static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
220{
221 int i = 0, j = 0;
222 char rname[16];
223 u32 regs[64];
224
225 switch (reginfo->ofs) {
226 case IXGBE_SRRCTL(0):
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
229 break;
230 case IXGBE_DCA_RXCTRL(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
233 break;
234 case IXGBE_RDLEN(0):
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
237 break;
238 case IXGBE_RDH(0):
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
241 break;
242 case IXGBE_RDT(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
245 break;
246 case IXGBE_RXDCTL(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
249 break;
250 case IXGBE_RDBAL(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
253 break;
254 case IXGBE_RDBAH(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
257 break;
258 case IXGBE_TDBAL(0):
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
261 break;
262 case IXGBE_TDBAH(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
265 break;
266 case IXGBE_TDLEN(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
269 break;
270 case IXGBE_TDH(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
273 break;
274 case IXGBE_TDT(0):
275 for (i = 0; i < 64; i++)
276 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
277 break;
278 case IXGBE_TXDCTL(0):
279 for (i = 0; i < 64; i++)
280 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
281 break;
282 default:
283 printk(KERN_INFO "%-15s %08x\n", reginfo->name,
284 IXGBE_READ_REG(hw, reginfo->ofs));
285 return;
286 }
287
288 for (i = 0; i < 8; i++) {
289 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
290 printk(KERN_ERR "%-15s ", rname);
291 for (j = 0; j < 8; j++)
292 printk(KERN_CONT "%08x ", regs[i*8+j]);
293 printk(KERN_CONT "\n");
294 }
295
296}
297
298/*
299 * ixgbe_dump - Print registers, tx-rings and rx-rings
300 */
301static void ixgbe_dump(struct ixgbe_adapter *adapter)
302{
303 struct net_device *netdev = adapter->netdev;
304 struct ixgbe_hw *hw = &adapter->hw;
305 struct ixgbe_reg_info *reginfo;
306 int n = 0;
307 struct ixgbe_ring *tx_ring;
308 struct ixgbe_tx_buffer *tx_buffer_info;
309 union ixgbe_adv_tx_desc *tx_desc;
310 struct my_u0 { u64 a; u64 b; } *u0;
311 struct ixgbe_ring *rx_ring;
312 union ixgbe_adv_rx_desc *rx_desc;
313 struct ixgbe_rx_buffer *rx_buffer_info;
314 u32 staterr;
315 int i = 0;
316
317 if (!netif_msg_hw(adapter))
318 return;
319
320 /* Print netdevice Info */
321 if (netdev) {
322 dev_info(&adapter->pdev->dev, "Net device Info\n");
323 printk(KERN_INFO "Device Name state "
324 "trans_start last_rx\n");
325 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
326 netdev->name,
327 netdev->state,
328 netdev->trans_start,
329 netdev->last_rx);
330 }
331
332 /* Print Registers */
333 dev_info(&adapter->pdev->dev, "Register Dump\n");
334 printk(KERN_INFO " Register Name Value\n");
335 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
336 reginfo->name; reginfo++) {
337 ixgbe_regdump(hw, reginfo);
338 }
339
340 /* Print TX Ring Summary */
341 if (!netdev || !netif_running(netdev))
342 goto exit;
343
344 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
345 printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma ] "
346 "leng ntw timestamp\n");
347 for (n = 0; n < adapter->num_tx_queues; n++) {
348 tx_ring = adapter->tx_ring[n];
349 tx_buffer_info =
350 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
351 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
352 n, tx_ring->next_to_use, tx_ring->next_to_clean,
353 (u64)tx_buffer_info->dma,
354 tx_buffer_info->length,
355 tx_buffer_info->next_to_watch,
356 (u64)tx_buffer_info->time_stamp);
357 }
358
359 /* Print TX Rings */
360 if (!netif_msg_tx_done(adapter))
361 goto rx_ring_summary;
362
363 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
364
365 /* Transmit Descriptor Formats
366 *
367 * Advanced Transmit Descriptor
368 * +--------------------------------------------------------------+
369 * 0 | Buffer Address [63:0] |
370 * +--------------------------------------------------------------+
371 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
372 * +--------------------------------------------------------------+
373 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
374 */
375
376 for (n = 0; n < adapter->num_tx_queues; n++) {
377 tx_ring = adapter->tx_ring[n];
378 printk(KERN_INFO "------------------------------------\n");
379 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
380 printk(KERN_INFO "------------------------------------\n");
381 printk(KERN_INFO "T [desc] [address 63:0 ] "
382 "[PlPOIdStDDt Ln] [bi->dma ] "
383 "leng ntw timestamp bi->skb\n");
384
385 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
386 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
387 tx_buffer_info = &tx_ring->tx_buffer_info[i];
388 u0 = (struct my_u0 *)tx_desc;
389 printk(KERN_INFO "T [0x%03X] %016llX %016llX %016llX"
390 " %04X %3X %016llX %p", i,
391 le64_to_cpu(u0->a),
392 le64_to_cpu(u0->b),
393 (u64)tx_buffer_info->dma,
394 tx_buffer_info->length,
395 tx_buffer_info->next_to_watch,
396 (u64)tx_buffer_info->time_stamp,
397 tx_buffer_info->skb);
398 if (i == tx_ring->next_to_use &&
399 i == tx_ring->next_to_clean)
400 printk(KERN_CONT " NTC/U\n");
401 else if (i == tx_ring->next_to_use)
402 printk(KERN_CONT " NTU\n");
403 else if (i == tx_ring->next_to_clean)
404 printk(KERN_CONT " NTC\n");
405 else
406 printk(KERN_CONT "\n");
407
408 if (netif_msg_pktdata(adapter) &&
409 tx_buffer_info->dma != 0)
410 print_hex_dump(KERN_INFO, "",
411 DUMP_PREFIX_ADDRESS, 16, 1,
412 phys_to_virt(tx_buffer_info->dma),
413 tx_buffer_info->length, true);
414 }
415 }
416
417 /* Print RX Rings Summary */
418rx_ring_summary:
419 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
420 printk(KERN_INFO "Queue [NTU] [NTC]\n");
421 for (n = 0; n < adapter->num_rx_queues; n++) {
422 rx_ring = adapter->rx_ring[n];
423 printk(KERN_INFO "%5d %5X %5X\n", n,
424 rx_ring->next_to_use, rx_ring->next_to_clean);
425 }
426
427 /* Print RX Rings */
428 if (!netif_msg_rx_status(adapter))
429 goto exit;
430
431 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
432
433 /* Advanced Receive Descriptor (Read) Format
434 * 63 1 0
435 * +-----------------------------------------------------+
436 * 0 | Packet Buffer Address [63:1] |A0/NSE|
437 * +----------------------------------------------+------+
438 * 8 | Header Buffer Address [63:1] | DD |
439 * +-----------------------------------------------------+
440 *
441 *
442 * Advanced Receive Descriptor (Write-Back) Format
443 *
444 * 63 48 47 32 31 30 21 20 16 15 4 3 0
445 * +------------------------------------------------------+
446 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
447 * | Checksum Ident | | | | Type | Type |
448 * +------------------------------------------------------+
449 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
450 * +------------------------------------------------------+
451 * 63 48 47 32 31 20 19 0
452 */
453 for (n = 0; n < adapter->num_rx_queues; n++) {
454 rx_ring = adapter->rx_ring[n];
455 printk(KERN_INFO "------------------------------------\n");
456 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
457 printk(KERN_INFO "------------------------------------\n");
458 printk(KERN_INFO "R [desc] [ PktBuf A0] "
459 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
460 "<-- Adv Rx Read format\n");
461 printk(KERN_INFO "RWB[desc] [PcsmIpSHl PtRs] "
462 "[vl er S cks ln] ---------------- [bi->skb] "
463 "<-- Adv Rx Write-Back format\n");
464
465 for (i = 0; i < rx_ring->count; i++) {
466 rx_buffer_info = &rx_ring->rx_buffer_info[i];
467 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
468 u0 = (struct my_u0 *)rx_desc;
469 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
470 if (staterr & IXGBE_RXD_STAT_DD) {
471 /* Descriptor Done */
472 printk(KERN_INFO "RWB[0x%03X] %016llX "
473 "%016llX ---------------- %p", i,
474 le64_to_cpu(u0->a),
475 le64_to_cpu(u0->b),
476 rx_buffer_info->skb);
477 } else {
478 printk(KERN_INFO "R [0x%03X] %016llX "
479 "%016llX %016llX %p", i,
480 le64_to_cpu(u0->a),
481 le64_to_cpu(u0->b),
482 (u64)rx_buffer_info->dma,
483 rx_buffer_info->skb);
484
485 if (netif_msg_pktdata(adapter)) {
486 print_hex_dump(KERN_INFO, "",
487 DUMP_PREFIX_ADDRESS, 16, 1,
488 phys_to_virt(rx_buffer_info->dma),
489 rx_ring->rx_buf_len, true);
490
491 if (rx_ring->rx_buf_len
492 < IXGBE_RXBUFFER_2048)
493 print_hex_dump(KERN_INFO, "",
494 DUMP_PREFIX_ADDRESS, 16, 1,
495 phys_to_virt(
496 rx_buffer_info->page_dma +
497 rx_buffer_info->page_offset
498 ),
499 PAGE_SIZE/2, true);
500 }
501 }
502
503 if (i == rx_ring->next_to_use)
504 printk(KERN_CONT " NTU\n");
505 else if (i == rx_ring->next_to_clean)
506 printk(KERN_CONT " NTC\n");
507 else
508 printk(KERN_CONT "\n");
509
510 }
511 }
512
513exit:
514 return;
515}
516
5eba3699
AV		 517static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
518{
519 u32 ctrl_ext;
520
521 /* Let firmware take over control of h/w */
522 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
523 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 524 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 525}
526
527static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
528{
529 u32 ctrl_ext;
530
531 /* Let firmware know the driver has taken over */
532 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
533 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 534 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 535}
9a799d71 536
e8e26350
PW		 537/*
538 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
539 * @adapter: pointer to adapter struct
540 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
541 * @queue: queue to map the corresponding interrupt to
542 * @msix_vector: the vector to map to the corresponding queue
543 *
544 */
545static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
546 u8 queue, u8 msix_vector)
9a799d71
AK		 547{
548 u32 ivar, index;
e8e26350
PW		 549 struct ixgbe_hw *hw = &adapter->hw;
550 switch (hw->mac.type) {
551 case ixgbe_mac_82598EB:
552 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
553 if (direction == -1)
554 direction = 0;
555 index = (((direction * 64) + queue) >> 2) & 0x1F;
556 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
557 ivar &= ~(0xFF << (8 * (queue & 0x3)));
558 ivar |= (msix_vector << (8 * (queue & 0x3)));
559 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
560 break;
561 case ixgbe_mac_82599EB:
562 if (direction == -1) {
563 /* other causes */
564 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
565 index = ((queue & 1) * 8);
566 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
567 ivar &= ~(0xFF << index);
568 ivar |= (msix_vector << index);
569 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
570 break;
571 } else {
572 /* tx or rx causes */
573 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
574 index = ((16 * (queue & 1)) + (8 * direction));
575 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
576 ivar &= ~(0xFF << index);
577 ivar |= (msix_vector << index);
578 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
579 break;
580 }
581 default:
582 break;
583 }
9a799d71
AK		 584}
585
fe49f04a
AD		 586static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
587 u64 qmask)
588{
589 u32 mask;
590
591 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
592 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
593 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
594 } else {
595 mask = (qmask & 0xFFFFFFFF);
596 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
597 mask = (qmask >> 32);
598 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
599 }
600}
601
9a799d71 602static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 603 struct ixgbe_tx_buffer
604 *tx_buffer_info)
9a799d71 605{
e5a43549
AD		 606 if (tx_buffer_info->dma) {
607 if (tx_buffer_info->mapped_as_page)
1b507730 608 dma_unmap_page(&adapter->pdev->dev,
e5a43549
AD		 609 tx_buffer_info->dma,
610 tx_buffer_info->length,
1b507730 611 DMA_TO_DEVICE);
e5a43549 612 else
1b507730 613 dma_unmap_single(&adapter->pdev->dev,
e5a43549
AD		 614 tx_buffer_info->dma,
615 tx_buffer_info->length,
1b507730 616 DMA_TO_DEVICE);
e5a43549
AD		 617 tx_buffer_info->dma = 0;
618 }
9a799d71
AK		 619 if (tx_buffer_info->skb) {
620 dev_kfree_skb_any(tx_buffer_info->skb);
621 tx_buffer_info->skb = NULL;
622 }
44df32c5 623 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 624 /* tx_buffer_info must be completely set up in the transmit path */
625}
626
26f23d82 627/**
7483d9dd 628 * ixgbe_tx_xon_state - check the tx ring xon state
26f23d82
YZ		 629 * @adapter: the ixgbe adapter
630 * @tx_ring: the corresponding tx_ring
631 *
632 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
633 * corresponding TC of this tx_ring when checking TFCS.
634 *
7483d9dd 635 * Returns : true if in xon state (currently not paused)
26f23d82 636 */
7483d9dd 637static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
26f23d82
YZ		 638 struct ixgbe_ring *tx_ring)
639{
26f23d82
YZ		 640 u32 txoff = IXGBE_TFCS_TXOFF;
641
642#ifdef CONFIG_IXGBE_DCB
643 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
30b76832 644 int tc;
26f23d82
YZ		 645 int reg_idx = tx_ring->reg_idx;
646 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
647
6837e895
PW		 648 switch (adapter->hw.mac.type) {
649 case ixgbe_mac_82598EB:
26f23d82
YZ		 650 tc = reg_idx >> 2;
651 txoff = IXGBE_TFCS_TXOFF0;
6837e895
PW		 652 break;
653 case ixgbe_mac_82599EB:
26f23d82
YZ		 654 tc = 0;
655 txoff = IXGBE_TFCS_TXOFF;
656 if (dcb_i == 8) {
657 /* TC0, TC1 */
658 tc = reg_idx >> 5;
659 if (tc == 2) /* TC2, TC3 */
660 tc += (reg_idx - 64) >> 4;
661 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
662 tc += 1 + ((reg_idx - 96) >> 3);
663 } else if (dcb_i == 4) {
664 /* TC0, TC1 */
665 tc = reg_idx >> 6;
666 if (tc == 1) {
667 tc += (reg_idx - 64) >> 5;
668 if (tc == 2) /* TC2, TC3 */
669 tc += (reg_idx - 96) >> 4;
670 }
671 }
6837e895
PW		 672 break;
673 default:
674 tc = 0;
26f23d82
YZ		 675 }
676 txoff <<= tc;
677 }
678#endif
679 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
680}
681
9a799d71 682static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 683 struct ixgbe_ring *tx_ring,
684 unsigned int eop)
9a799d71 685{
e01c31a5 686 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 687
9a799d71 688 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 689 * check with the clearing of time_stamp and movement of eop */
9a799d71 690 adapter->detect_tx_hung = false;
44df32c5 691 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71 692 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
7483d9dd 693 ixgbe_tx_xon_state(adapter, tx_ring)) {
9a799d71 694 /* detected Tx unit hang */
e01c31a5
JB		 695 union ixgbe_adv_tx_desc *tx_desc;
696 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 697 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 698 " Tx Queue <%d>\n"
699 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 700 " next_to_use <%x>\n"
701 " next_to_clean <%x>\n"
702 "tx_buffer_info[next_to_clean]\n"
703 " time_stamp <%lx>\n"
e01c31a5
JB		 704 " jiffies <%lx>\n",
705 tx_ring->queue_index,
44df32c5
AD		 706 IXGBE_READ_REG(hw, tx_ring->head),
707 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 708 tx_ring->next_to_use, eop,
709 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 710 return true;
711 }
712
713 return false;
714}
715
b4617240
PW		 716#define IXGBE_MAX_TXD_PWR 14
717#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 718
719/* Tx Descriptors needed, worst case */
720#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
721 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
722#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 723 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 724
e01c31a5
JB		 725static void ixgbe_tx_timeout(struct net_device *netdev);
726
9a799d71
AK		 727/**
728 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 729 * @q_vector: structure containing interrupt and ring information
e01c31a5 730 * @tx_ring: tx ring to clean
9a799d71 731 **/
fe49f04a 732static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e01c31a5 733 struct ixgbe_ring *tx_ring)
9a799d71 734{
fe49f04a 735 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 736 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 737 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
738 struct ixgbe_tx_buffer *tx_buffer_info;
739 unsigned int i, eop, count = 0;
e01c31a5 740 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 741
742 i = tx_ring->next_to_clean;
12207e49
PWJ		 743 eop = tx_ring->tx_buffer_info[i].next_to_watch;
744 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
745
746 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 747 (count < tx_ring->work_limit)) {
12207e49
PWJ		 748 bool cleaned = false;
749 for ( ; !cleaned; count++) {
750 struct sk_buff *skb;
9a799d71
AK		 751 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
752 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 753 cleaned = (i == eop);
e01c31a5 754 skb = tx_buffer_info->skb;
9a799d71 755
12207e49 756 if (cleaned && skb) {
e092be60 757 unsigned int segs, bytecount;
3d8fd385 758 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 759
760 /* gso_segs is currently only valid for tcp */
e092be60 761 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 762#ifdef IXGBE_FCOE
763 /* adjust for FCoE Sequence Offload */
764 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
765 && (skb->protocol == htons(ETH_P_FCOE)) &&
766 skb_is_gso(skb)) {
767 hlen = skb_transport_offset(skb) +
768 sizeof(struct fc_frame_header) +
769 sizeof(struct fcoe_crc_eof);
770 segs = DIV_ROUND_UP(skb->len - hlen,
771 skb_shinfo(skb)->gso_size);
772 }
773#endif /* IXGBE_FCOE */
e092be60 774 /* multiply data chunks by size of headers */
3d8fd385 775 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 776 total_packets += segs;
777 total_bytes += bytecount;
e092be60 778 }
e01c31a5 779
9a799d71 780 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 781 tx_buffer_info);
9a799d71 782
12207e49
PWJ		 783 tx_desc->wb.status = 0;
784
9a799d71
AK		 785 i++;
786 if (i == tx_ring->count)
787 i = 0;
e01c31a5 788 }
12207e49
PWJ		 789
790 eop = tx_ring->tx_buffer_info[i].next_to_watch;
791 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
792 }
793
9a799d71
AK		 794 tx_ring->next_to_clean = i;
795
e092be60 796#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 797 if (unlikely(count && netif_carrier_ok(netdev) &&
798 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 799 /* Make sure that anybody stopping the queue after this
800 * sees the new next_to_clean.
801 */
802 smp_mb();
30eba97a
AV		 803 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
804 !test_bit(__IXGBE_DOWN, &adapter->state)) {
805 netif_wake_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 806 ++tx_ring->restart_queue;
30eba97a 807 }
e092be60 808 }
9a799d71 809
e01c31a5
JB		 810 if (adapter->detect_tx_hung) {
811 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
812 /* schedule immediate reset if we believe we hung */
813 DPRINTK(PROBE, INFO,
814 "tx hang %d detected, resetting adapter\n",
815 adapter->tx_timeout_count + 1);
816 ixgbe_tx_timeout(adapter->netdev);
817 }
818 }
9a799d71 819
e01c31a5 820 /* re-arm the interrupt */
fe49f04a
AD		 821 if (count >= tx_ring->work_limit)
822 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 823
e01c31a5
JB		 824 tx_ring->total_bytes += total_bytes;
825 tx_ring->total_packets += total_packets;
e01c31a5 826 tx_ring->stats.packets += total_packets;
12207e49 827 tx_ring->stats.bytes += total_bytes;
9a1a69ad 828 return (count < tx_ring->work_limit);
9a799d71
AK		 829}
830
5dd2d332 831#ifdef CONFIG_IXGBE_DCA
bd0362dd 832static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 833 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 834{
835 u32 rxctrl;
836 int cpu = get_cpu();
4a0b9ca0 837 int q = rx_ring->reg_idx;
bd0362dd 838
3a581073 839 if (rx_ring->cpu != cpu) {
bd0362dd 840 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 841 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
842 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
843 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
844 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
845 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
846 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
847 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
848 }
bd0362dd
JC		 849 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
850 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 851 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
852 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 853 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 854 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 855 rx_ring->cpu = cpu;
bd0362dd
JC		 856 }
857 put_cpu();
858}
859
860static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 861 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 862{
863 u32 txctrl;
864 int cpu = get_cpu();
4a0b9ca0 865 int q = tx_ring->reg_idx;
ee5f784a 866 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 867
3a581073 868 if (tx_ring->cpu != cpu) {
e8e26350 869 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
ee5f784a 870 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 871 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
872 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
ee5f784a
DS		 873 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
874 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
e8e26350 875 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
ee5f784a 876 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
e8e26350
PW		 877 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
878 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
ee5f784a
DS		 879 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
880 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
881 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
e8e26350 882 }
3a581073 883 tx_ring->cpu = cpu;
bd0362dd
JC		 884 }
885 put_cpu();
886}
887
888static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
889{
890 int i;
891
892 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
893 return;
894
e35ec126
AD		 895 /* always use CB2 mode, difference is masked in the CB driver */
896 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
897
bd0362dd 898 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 899 adapter->tx_ring[i]->cpu = -1;
900 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
bd0362dd
JC		 901 }
902 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 903 adapter->rx_ring[i]->cpu = -1;
904 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
bd0362dd
JC		 905 }
906}
907
908static int __ixgbe_notify_dca(struct device *dev, void *data)
909{
910 struct net_device *netdev = dev_get_drvdata(dev);
911 struct ixgbe_adapter *adapter = netdev_priv(netdev);
912 unsigned long event = *(unsigned long *)data;
913
914 switch (event) {
915 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 916 /* if we're already enabled, don't do it again */
917 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
918 break;
652f093f 919 if (dca_add_requester(dev) == 0) {
96b0e0f6 920 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 921 ixgbe_setup_dca(adapter);
922 break;
923 }
924 /* Fall Through since DCA is disabled. */
925 case DCA_PROVIDER_REMOVE:
926 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
927 dca_remove_requester(dev);
928 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
929 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
930 }
931 break;
932 }
933
652f093f 934 return 0;
bd0362dd
JC		 935}
936
5dd2d332 937#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 938/**
939 * ixgbe_receive_skb - Send a completed packet up the stack
940 * @adapter: board private structure
941 * @skb: packet to send up
177db6ff
MC		 942 * @status: hardware indication of status of receive
943 * @rx_ring: rx descriptor ring (for a specific queue) to setup
944 * @rx_desc: rx descriptor
9a799d71 945 **/
78b6f4ce 946static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 947 struct sk_buff *skb, u8 status,
fdaff1ce 948 struct ixgbe_ring *ring,
177db6ff 949 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 950{
78b6f4ce
HX		 951 struct ixgbe_adapter *adapter = q_vector->adapter;
952 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 953 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
954 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 955
fdaff1ce 956 skb_record_rx_queue(skb, ring->queue_index);
182ff8df 957 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
8a62babf 958 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
78b6f4ce 959 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 960 else
78b6f4ce 961 napi_gro_receive(napi, skb);
177db6ff 962 } else {
8a62babf 963 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
182ff8df
AD		 964 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
965 else
966 netif_rx(skb);
9a799d71
AK		 967 }
968}
969
e59bd25d
AV		 970/**
971 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
972 * @adapter: address of board private structure
973 * @status_err: hardware indication of status of receive
974 * @skb: skb currently being received and modified
975 **/
9a799d71 976static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 977 union ixgbe_adv_rx_desc *rx_desc,
978 struct sk_buff *skb)
9a799d71 979{
8bae1b2b
DS		 980 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
981
9a799d71
AK		 982 skb->ip_summed = CHECKSUM_NONE;
983
712744be
JB		 984 /* Rx csum disabled */
985 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 986 return;
e59bd25d
AV		 987
988 /* if IP and error */
989 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
990 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 991 adapter->hw_csum_rx_error++;
992 return;
993 }
e59bd25d
AV		 994
995 if (!(status_err & IXGBE_RXD_STAT_L4CS))
996 return;
997
998 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 999 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1000
1001 /*
1002 * 82599 errata, UDP frames with a 0 checksum can be marked as
1003 * checksum errors.
1004 */
1005 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1006 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1007 return;
1008
e59bd25d
AV		 1009 adapter->hw_csum_rx_error++;
1010 return;
1011 }
1012
9a799d71 1013 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1014 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1015}
1016
e8e26350
PW		 1017static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
1018 struct ixgbe_ring *rx_ring, u32 val)
1019{
1020 /*
1021 * Force memory writes to complete before letting h/w
1022 * know there are new descriptors to fetch. (Only
1023 * applicable for weak-ordered memory model archs,
1024 * such as IA-64).
1025 */
1026 wmb();
1027 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1028}
1029
9a799d71
AK		 1030/**
1031 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1032 * @adapter: address of board private structure
1033 **/
1034static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 1035 struct ixgbe_ring *rx_ring,
1036 int cleaned_count)
9a799d71 1037{
9a799d71
AK		 1038 struct pci_dev *pdev = adapter->pdev;
1039 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1040 struct ixgbe_rx_buffer *bi;
9a799d71 1041 unsigned int i;
9a799d71
AK		 1042
1043 i = rx_ring->next_to_use;
3a581073 1044 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1045
1046 while (cleaned_count--) {
1047 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1048
762f4c57 1049 if (!bi->page_dma &&
6e455b89 1050 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 1051 if (!bi->page) {
762f4c57
JB		 1052 bi->page = alloc_page(GFP_ATOMIC);
1053 if (!bi->page) {
1054 adapter->alloc_rx_page_failed++;
1055 goto no_buffers;
1056 }
1057 bi->page_offset = 0;
1058 } else {
1059 /* use a half page if we're re-using */
1060 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 1061 }
762f4c57 1062
1b507730 1063 bi->page_dma = dma_map_page(&pdev->dev, bi->page,
762f4c57
JB		 1064 bi->page_offset,
1065 (PAGE_SIZE / 2),
1b507730 1066 DMA_FROM_DEVICE);
9a799d71
AK		 1067 }
1068
3a581073 1069 if (!bi->skb) {
5ecc3614 1070 struct sk_buff *skb;
7ca3bc58
JB		 1071 /* netdev_alloc_skb reserves 32 bytes up front!! */
1072 uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES;
1073 skb = netdev_alloc_skb(adapter->netdev, bufsz);
9a799d71
AK		 1074
1075 if (!skb) {
1076 adapter->alloc_rx_buff_failed++;
1077 goto no_buffers;
1078 }
1079
7ca3bc58
JB		 1080 /* advance the data pointer to the next cache line */
1081 skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES)
1082 - skb->data));
1083
3a581073 1084 bi->skb = skb;
1b507730 1085 bi->dma = dma_map_single(&pdev->dev, skb->data,
4f57ca6e 1086 rx_ring->rx_buf_len,
1b507730 1087 DMA_FROM_DEVICE);
9a799d71
AK		 1088 }
1089 /* Refresh the desc even if buffer_addrs didn't change because
1090 * each write-back erases this info. */
6e455b89 1091 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 1092 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1093 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1094 } else {
3a581073 1095 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 1096 }
1097
1098 i++;
1099 if (i == rx_ring->count)
1100 i = 0;
3a581073 1101 bi = &rx_ring->rx_buffer_info[i];
9a799d71 1102 }
7c6e0a43 1103
9a799d71
AK		 1104no_buffers:
1105 if (rx_ring->next_to_use != i) {
1106 rx_ring->next_to_use = i;
1107 if (i-- == 0)
1108 i = (rx_ring->count - 1);
1109
e8e26350 1110 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 1111 }
1112}
1113
7c6e0a43
JB		 1114static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1115{
1116 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1117}
1118
1119static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1120{
1121 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1122}
1123
f8212f97
AD		 1124static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1125{
1126 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1127 IXGBE_RXDADV_RSCCNT_MASK) >>
1128 IXGBE_RXDADV_RSCCNT_SHIFT;
1129}
1130
1131/**
1132 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1133 * @skb: pointer to the last skb in the rsc queue
94b982b2 1134 * @count: pointer to number of packets coalesced in this context
f8212f97
AD		 1135 *
1136 * This function changes a queue full of hw rsc buffers into a completed
1137 * packet. It uses the ->prev pointers to find the first packet and then
1138 * turns it into the frag list owner.
1139 **/
94b982b2
MC		 1140static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1141 u64 *count)
f8212f97
AD		 1142{
1143 unsigned int frag_list_size = 0;
1144
1145 while (skb->prev) {
1146 struct sk_buff *prev = skb->prev;
1147 frag_list_size += skb->len;
1148 skb->prev = NULL;
1149 skb = prev;
94b982b2 1150 *count += 1;
f8212f97
AD		 1151 }
1152
1153 skb_shinfo(skb)->frag_list = skb->next;
1154 skb->next = NULL;
1155 skb->len += frag_list_size;
1156 skb->data_len += frag_list_size;
1157 skb->truesize += frag_list_size;
1158 return skb;
1159}
1160
43634e82
MC		 1161struct ixgbe_rsc_cb {
1162 dma_addr_t dma;
e8171aaa 1163 bool delay_unmap;
43634e82
MC		 1164};
1165
1166#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1167
78b6f4ce 1168static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 1169 struct ixgbe_ring *rx_ring,
1170 int *work_done, int work_to_do)
9a799d71 1171{
78b6f4ce 1172 struct ixgbe_adapter *adapter = q_vector->adapter;
2d86f139 1173 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 1174 struct pci_dev *pdev = adapter->pdev;
1175 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1176 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1177 struct sk_buff *skb;
f8212f97 1178 unsigned int i, rsc_count = 0;
7c6e0a43 1179 u32 len, staterr;
177db6ff
MC		 1180 u16 hdr_info;
1181 bool cleaned = false;
9a799d71 1182 int cleaned_count = 0;
d2f4fbe2 1183 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 1184#ifdef IXGBE_FCOE
1185 int ddp_bytes = 0;
1186#endif /* IXGBE_FCOE */
9a799d71
AK		 1187
1188 i = rx_ring->next_to_clean;
9a799d71
AK		 1189 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1190 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1191 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1192
1193 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1194 u32 upper_len = 0;
9a799d71
AK		 1195 if (*work_done >= work_to_do)
1196 break;
1197 (*work_done)++;
1198
3c945e5b 1199 rmb(); /* read descriptor and rx_buffer_info after status DD */
6e455b89 1200 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 1201 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1202 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 1203 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71 1204 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
0b746e08
SN		 1205 if ((len > IXGBE_RX_HDR_SIZE) ||
1206 (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1207 len = IXGBE_RX_HDR_SIZE;
7c6e0a43 1208 } else {
9a799d71 1209 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 1210 }
9a799d71
AK		 1211
1212 cleaned = true;
1213 skb = rx_buffer_info->skb;
7ca3bc58 1214 prefetch(skb->data);
9a799d71
AK		 1215 rx_buffer_info->skb = NULL;
1216
21fa4e66 1217 if (rx_buffer_info->dma) {
43634e82
MC		 1218 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1219 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
e8171aaa 1220 (!(skb->prev))) {
43634e82
MC		 1221 /*
1222 * When HWRSC is enabled, delay unmapping
1223 * of the first packet. It carries the
1224 * header information, HW may still
1225 * access the header after the writeback.
1226 * Only unmap it when EOP is reached
1227 */
e8171aaa 1228 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1229 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1230 } else {
1b507730 1231 dma_unmap_single(&pdev->dev,
e8171aaa 1232 rx_buffer_info->dma,
43634e82 1233 rx_ring->rx_buf_len,
e8171aaa
MC		 1234 DMA_FROM_DEVICE);
1235 }
4f57ca6e 1236 rx_buffer_info->dma = 0;
9a799d71
AK		 1237 skb_put(skb, len);
1238 }
1239
1240 if (upper_len) {
1b507730
NN		 1241 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1242 PAGE_SIZE / 2, DMA_FROM_DEVICE);
9a799d71
AK		 1243 rx_buffer_info->page_dma = 0;
1244 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 1245 rx_buffer_info->page,
1246 rx_buffer_info->page_offset,
1247 upper_len);
1248
1249 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1250 (page_count(rx_buffer_info->page) != 1))
1251 rx_buffer_info->page = NULL;
1252 else
1253 get_page(rx_buffer_info->page);
9a799d71
AK		 1254
1255 skb->len += upper_len;
1256 skb->data_len += upper_len;
1257 skb->truesize += upper_len;
1258 }
1259
1260 i++;
1261 if (i == rx_ring->count)
1262 i = 0;
9a799d71
AK		 1263
1264 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
1265 prefetch(next_rxd);
9a799d71 1266 cleaned_count++;
f8212f97 1267
0c19d6af 1268 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 1269 rsc_count = ixgbe_get_rsc_count(rx_desc);
1270
1271 if (rsc_count) {
1272 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1273 IXGBE_RXDADV_NEXTP_SHIFT;
1274 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1275 } else {
1276 next_buffer = &rx_ring->rx_buffer_info[i];
1277 }
1278
9a799d71 1279 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97 1280 if (skb->prev)
94b982b2
MC		 1281 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
1282 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
e8171aaa 1283 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1b507730
NN		 1284 dma_unmap_single(&pdev->dev,
1285 IXGBE_RSC_CB(skb)->dma,
43634e82 1286 rx_ring->rx_buf_len,
1b507730 1287 DMA_FROM_DEVICE);
fd3686a8 1288 IXGBE_RSC_CB(skb)->dma = 0;
e8171aaa 1289 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 1290 }
94b982b2
MC		 1291 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
1292 rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
1293 else
1294 rx_ring->rsc_count++;
1295 rx_ring->rsc_flush++;
1296 }
9a799d71
AK		 1297 rx_ring->stats.packets++;
1298 rx_ring->stats.bytes += skb->len;
1299 } else {
6e455b89 1300 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 1301 rx_buffer_info->skb = next_buffer->skb;
1302 rx_buffer_info->dma = next_buffer->dma;
1303 next_buffer->skb = skb;
1304 next_buffer->dma = 0;
1305 } else {
1306 skb->next = next_buffer->skb;
1307 skb->next->prev = skb;
1308 }
7ca3bc58 1309 rx_ring->non_eop_descs++;
9a799d71
AK		 1310 goto next_desc;
1311 }
1312
1313 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1314 dev_kfree_skb_irq(skb);
1315 goto next_desc;
1316 }
1317
8bae1b2b 1318 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 1319
1320 /* probably a little skewed due to removing CRC */
1321 total_rx_bytes += skb->len;
1322 total_rx_packets++;
1323
74ce8dd2 1324 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 1325#ifdef IXGBE_FCOE
1326 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 1327 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1328 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1329 if (!ddp_bytes)
332d4a7d 1330 goto next_desc;
3d8fd385 1331 }
332d4a7d 1332#endif /* IXGBE_FCOE */
fdaff1ce 1333 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1334
1335next_desc:
1336 rx_desc->wb.upper.status_error = 0;
1337
1338 /* return some buffers to hardware, one at a time is too slow */
1339 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1340 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1341 cleaned_count = 0;
1342 }
1343
1344 /* use prefetched values */
1345 rx_desc = next_rxd;
f8212f97 1346 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1347
1348 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1349 }
1350
9a799d71
AK		 1351 rx_ring->next_to_clean = i;
1352 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1353
1354 if (cleaned_count)
1355 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1356
3d8fd385
YZ		 1357#ifdef IXGBE_FCOE
1358 /* include DDPed FCoE data */
1359 if (ddp_bytes > 0) {
1360 unsigned int mss;
1361
1362 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1363 sizeof(struct fc_frame_header) -
1364 sizeof(struct fcoe_crc_eof);
1365 if (mss > 512)
1366 mss &= ~511;
1367 total_rx_bytes += ddp_bytes;
1368 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1369 }
1370#endif /* IXGBE_FCOE */
1371
f494e8fa
AV		 1372 rx_ring->total_packets += total_rx_packets;
1373 rx_ring->total_bytes += total_rx_bytes;
2d86f139
AK		 1374 netdev->stats.rx_bytes += total_rx_bytes;
1375 netdev->stats.rx_packets += total_rx_packets;
f494e8fa 1376
9a799d71
AK		 1377 return cleaned;
1378}
1379
021230d4 1380static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1381/**
1382 * ixgbe_configure_msix - Configure MSI-X hardware
1383 * @adapter: board private structure
1384 *
1385 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1386 * interrupts.
1387 **/
1388static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1389{
021230d4
AV		 1390 struct ixgbe_q_vector *q_vector;
1391 int i, j, q_vectors, v_idx, r_idx;
1392 u32 mask;
9a799d71 1393
021230d4 1394 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1395
4df10466
JB		 1396 /*
1397 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1398 * corresponding register.
1399 */
1400 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1401 q_vector = adapter->q_vector[v_idx];
984b3f57 1402 /* XXX for_each_set_bit(...) */
021230d4 1403 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 1404 adapter->num_rx_queues);
021230d4
AV		 1405
1406 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1407 j = adapter->rx_ring[r_idx]->reg_idx;
e8e26350 1408 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 1409 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 1410 adapter->num_rx_queues,
1411 r_idx + 1);
021230d4
AV		 1412 }
1413 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 1414 adapter->num_tx_queues);
021230d4
AV		 1415
1416 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1417 j = adapter->tx_ring[r_idx]->reg_idx;
e8e26350 1418 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 1419 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 1420 adapter->num_tx_queues,
1421 r_idx + 1);
021230d4
AV		 1422 }
1423
021230d4 1424 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1425 /* tx only */
1426 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1427 else if (q_vector->rxr_count)
f7554a2b
NS		 1428 /* rx or mixed */
1429 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1430
fe49f04a 1431 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1432 }
1433
e8e26350
PW		 1434 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1435 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1436 v_idx);
1437 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1438 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 1439 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1440
41fb9248 1441 /* set up to autoclear timer, and the vectors */
021230d4 1442 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1443 if (adapter->num_vfs)
1444 mask &= ~(IXGBE_EIMS_OTHER |
1445 IXGBE_EIMS_MAILBOX |
1446 IXGBE_EIMS_LSC);
1447 else
1448 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1449 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1450}
1451
f494e8fa
AV		 1452enum latency_range {
1453 lowest_latency = 0,
1454 low_latency = 1,
1455 bulk_latency = 2,
1456 latency_invalid = 255
1457};
1458
1459/**
1460 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1461 * @adapter: pointer to adapter
1462 * @eitr: eitr setting (ints per sec) to give last timeslice
1463 * @itr_setting: current throttle rate in ints/second
1464 * @packets: the number of packets during this measurement interval
1465 * @bytes: the number of bytes during this measurement interval
1466 *
1467 * Stores a new ITR value based on packets and byte
1468 * counts during the last interrupt. The advantage of per interrupt
1469 * computation is faster updates and more accurate ITR for the current
1470 * traffic pattern. Constants in this function were computed
1471 * based on theoretical maximum wire speed and thresholds were set based
1472 * on testing data as well as attempting to minimize response time
1473 * while increasing bulk throughput.
1474 * this functionality is controlled by the InterruptThrottleRate module
1475 * parameter (see ixgbe_param.c)
1476 **/
1477static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 1478 u32 eitr, u8 itr_setting,
1479 int packets, int bytes)
f494e8fa
AV		 1480{
1481 unsigned int retval = itr_setting;
1482 u32 timepassed_us;
1483 u64 bytes_perint;
1484
1485 if (packets == 0)
1486 goto update_itr_done;
1487
1488
1489 /* simple throttlerate management
1490 * 0-20MB/s lowest (100000 ints/s)
1491 * 20-100MB/s low (20000 ints/s)
1492 * 100-1249MB/s bulk (8000 ints/s)
1493 */
1494 /* what was last interrupt timeslice? */
1495 timepassed_us = 1000000/eitr;
1496 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1497
1498 switch (itr_setting) {
1499 case lowest_latency:
1500 if (bytes_perint > adapter->eitr_low)
1501 retval = low_latency;
1502 break;
1503 case low_latency:
1504 if (bytes_perint > adapter->eitr_high)
1505 retval = bulk_latency;
1506 else if (bytes_perint <= adapter->eitr_low)
1507 retval = lowest_latency;
1508 break;
1509 case bulk_latency:
1510 if (bytes_perint <= adapter->eitr_high)
1511 retval = low_latency;
1512 break;
1513 }
1514
1515update_itr_done:
1516 return retval;
1517}
1518
509ee935
JB		 1519/**
1520 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1521 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1522 *
1523 * This function is made to be called by ethtool and by the driver
1524 * when it needs to update EITR registers at runtime. Hardware
1525 * specific quirks/differences are taken care of here.
1526 */
fe49f04a 1527void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1528{
fe49f04a 1529 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1530 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1531 int v_idx = q_vector->v_idx;
1532 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1533
509ee935
JB		 1534 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1535 /* must write high and low 16 bits to reset counter */
1536 itr_reg |= (itr_reg << 16);
1537 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f8d1dcaf
JB		 1538 /*
1539 * 82599 can support a value of zero, so allow it for
1540 * max interrupt rate, but there is an errata where it can
1541 * not be zero with RSC
1542 */
1543 if (itr_reg == 8 &&
1544 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1545 itr_reg = 0;
1546
509ee935
JB		 1547 /*
1548 * set the WDIS bit to not clear the timer bits and cause an
1549 * immediate assertion of the interrupt
1550 */
1551 itr_reg |= IXGBE_EITR_CNT_WDIS;
1552 }
1553 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1554}
1555
f494e8fa
AV		 1556static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1557{
1558 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1559 u32 new_itr;
1560 u8 current_itr, ret_itr;
fe49f04a 1561 int i, r_idx;
f494e8fa
AV		 1562 struct ixgbe_ring *rx_ring, *tx_ring;
1563
1564 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1565 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1566 tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1567 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1568 q_vector->tx_itr,
1569 tx_ring->total_packets,
1570 tx_ring->total_bytes);
f494e8fa
AV		 1571 /* if the result for this queue would decrease interrupt
1572 * rate for this vector then use that result */
30efa5a3 1573 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1574 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1575 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1576 r_idx + 1);
f494e8fa
AV		 1577 }
1578
1579 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1580 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1581 rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1582 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1583 q_vector->rx_itr,
1584 rx_ring->total_packets,
1585 rx_ring->total_bytes);
f494e8fa
AV		 1586 /* if the result for this queue would decrease interrupt
1587 * rate for this vector then use that result */
30efa5a3 1588 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1589 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1590 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1591 r_idx + 1);
f494e8fa
AV		 1592 }
1593
30efa5a3 1594 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1595
1596 switch (current_itr) {
1597 /* counts and packets in update_itr are dependent on these numbers */
1598 case lowest_latency:
1599 new_itr = 100000;
1600 break;
1601 case low_latency:
1602 new_itr = 20000; /* aka hwitr = ~200 */
1603 break;
1604 case bulk_latency:
1605 default:
1606 new_itr = 8000;
1607 break;
1608 }
1609
1610 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1611 /* do an exponential smoothing */
1612 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1613
1614 /* save the algorithm value here, not the smoothed one */
1615 q_vector->eitr = new_itr;
fe49f04a
AD		 1616
1617 ixgbe_write_eitr(q_vector);
f494e8fa 1618 }
f494e8fa
AV		 1619}
1620
0befdb3e
JB		 1621static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1622{
1623 struct ixgbe_hw *hw = &adapter->hw;
1624
1625 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1626 (eicr & IXGBE_EICR_GPI_SDP1)) {
1627 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1628 /* write to clear the interrupt */
1629 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1630 }
1631}
cf8280ee 1632
e8e26350
PW		 1633static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1634{
1635 struct ixgbe_hw *hw = &adapter->hw;
1636
1637 if (eicr & IXGBE_EICR_GPI_SDP1) {
1638 /* Clear the interrupt */
1639 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1640 schedule_work(&adapter->multispeed_fiber_task);
1641 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1642 /* Clear the interrupt */
1643 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1644 schedule_work(&adapter->sfp_config_module_task);
1645 } else {
1646 /* Interrupt isn't for us... */
1647 return;
1648 }
1649}
1650
cf8280ee
JB		 1651static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1652{
1653 struct ixgbe_hw *hw = &adapter->hw;
1654
1655 adapter->lsc_int++;
1656 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1657 adapter->link_check_timeout = jiffies;
1658 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1659 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1660 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1661 schedule_work(&adapter->watchdog_task);
1662 }
1663}
1664
9a799d71
AK		 1665static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1666{
1667 struct net_device *netdev = data;
1668 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1669 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1670 u32 eicr;
1671
1672 /*
1673 * Workaround for Silicon errata. Use clear-by-write instead
1674 * of clear-by-read. Reading with EICS will return the
1675 * interrupt causes without clearing, which later be done
1676 * with the write to EICR.
1677 */
1678 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1679 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1680
cf8280ee
JB		 1681 if (eicr & IXGBE_EICR_LSC)
1682 ixgbe_check_lsc(adapter);
d4f80882 1683
1cdd1ec8
GR		 1684 if (eicr & IXGBE_EICR_MAILBOX)
1685 ixgbe_msg_task(adapter);
1686
e8e26350
PW		 1687 if (hw->mac.type == ixgbe_mac_82598EB)
1688 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1689
c4cf55e5 1690 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1691 ixgbe_check_sfp_event(adapter, eicr);
c4cf55e5
PWJ		 1692
1693 /* Handle Flow Director Full threshold interrupt */
1694 if (eicr & IXGBE_EICR_FLOW_DIR) {
1695 int i;
1696 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1697 /* Disable transmits before FDIR Re-initialization */
1698 netif_tx_stop_all_queues(netdev);
1699 for (i = 0; i < adapter->num_tx_queues; i++) {
1700 struct ixgbe_ring *tx_ring =
4a0b9ca0 1701 adapter->tx_ring[i];
c4cf55e5
PWJ		 1702 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1703 &tx_ring->reinit_state))
1704 schedule_work(&adapter->fdir_reinit_task);
1705 }
1706 }
1707 }
d4f80882
AV		 1708 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1709 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1710
1711 return IRQ_HANDLED;
1712}
1713
fe49f04a
AD		 1714static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1715 u64 qmask)
1716{
1717 u32 mask;
1718
1719 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1720 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1721 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1722 } else {
1723 mask = (qmask & 0xFFFFFFFF);
1724 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1725 mask = (qmask >> 32);
1726 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1727 }
1728 /* skip the flush */
1729}
1730
1731static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1732 u64 qmask)
1733{
1734 u32 mask;
1735
1736 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1737 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1738 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1739 } else {
1740 mask = (qmask & 0xFFFFFFFF);
1741 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1742 mask = (qmask >> 32);
1743 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1744 }
1745 /* skip the flush */
1746}
1747
9a799d71
AK		 1748static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1749{
021230d4
AV		 1750 struct ixgbe_q_vector *q_vector = data;
1751 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1752 struct ixgbe_ring *tx_ring;
021230d4
AV		 1753 int i, r_idx;
1754
1755 if (!q_vector->txr_count)
1756 return IRQ_HANDLED;
1757
1758 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1759 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1760 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 1761 tx_ring->total_bytes = 0;
1762 tx_ring->total_packets = 0;
021230d4 1763 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1764 r_idx + 1);
021230d4 1765 }
9a799d71 1766
9b471446 1767 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 1768 napi_schedule(&q_vector->napi);
1769
9a799d71
AK		 1770 return IRQ_HANDLED;
1771}
1772
021230d4
AV		 1773/**
1774 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1775 * @irq: unused
1776 * @data: pointer to our q_vector struct for this interrupt vector
1777 **/
9a799d71
AK		 1778static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1779{
021230d4
AV		 1780 struct ixgbe_q_vector *q_vector = data;
1781 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1782 struct ixgbe_ring *rx_ring;
021230d4 1783 int r_idx;
30efa5a3 1784 int i;
021230d4
AV		 1785
1786 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3 1787 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1788 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 1789 rx_ring->total_bytes = 0;
1790 rx_ring->total_packets = 0;
1791 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1792 r_idx + 1);
1793 }
1794
021230d4
AV		 1795 if (!q_vector->rxr_count)
1796 return IRQ_HANDLED;
1797
021230d4 1798 /* disable interrupts on this vector only */
9b471446 1799 /* EIAM disabled interrupts (on this vector) for us */
288379f0 1800 napi_schedule(&q_vector->napi);
021230d4
AV		 1801
1802 return IRQ_HANDLED;
1803}
1804
1805static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1806{
91281fd3
AD		 1807 struct ixgbe_q_vector *q_vector = data;
1808 struct ixgbe_adapter *adapter = q_vector->adapter;
1809 struct ixgbe_ring *ring;
1810 int r_idx;
1811 int i;
1812
1813 if (!q_vector->txr_count && !q_vector->rxr_count)
1814 return IRQ_HANDLED;
1815
1816 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1817 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1818 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1819 ring->total_bytes = 0;
1820 ring->total_packets = 0;
1821 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1822 r_idx + 1);
1823 }
1824
1825 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1826 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1827 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 1828 ring->total_bytes = 0;
1829 ring->total_packets = 0;
1830 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1831 r_idx + 1);
1832 }
1833
9b471446 1834 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1835 napi_schedule(&q_vector->napi);
9a799d71 1836
9a799d71
AK		 1837 return IRQ_HANDLED;
1838}
1839
021230d4
AV		 1840/**
1841 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1842 * @napi: napi struct with our devices info in it
1843 * @budget: amount of work driver is allowed to do this pass, in packets
1844 *
f0848276
JB		 1845 * This function is optimized for cleaning one queue only on a single
1846 * q_vector!!!
021230d4 1847 **/
9a799d71
AK		 1848static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1849{
021230d4 1850 struct ixgbe_q_vector *q_vector =
b4617240 1851 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1852 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1853 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1854 int work_done = 0;
021230d4 1855 long r_idx;
9a799d71 1856
021230d4 1857 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1858 rx_ring = adapter->rx_ring[r_idx];
5dd2d332 1859#ifdef CONFIG_IXGBE_DCA
bd0362dd 1860 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1861 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1862#endif
9a799d71 1863
78b6f4ce 1864 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1865
021230d4
AV		 1866 /* If all Rx work done, exit the polling mode */
1867 if (work_done < budget) {
288379f0 1868 napi_complete(napi);
f7554a2b 1869 if (adapter->rx_itr_setting & 1)
f494e8fa 1870 ixgbe_set_itr_msix(q_vector);
9a799d71 1871 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1872 ixgbe_irq_enable_queues(adapter,
1873 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1874 }
1875
1876 return work_done;
1877}
1878
f0848276 1879/**
91281fd3 1880 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1881 * @napi: napi struct with our devices info in it
1882 * @budget: amount of work driver is allowed to do this pass, in packets
1883 *
1884 * This function will clean more than one rx queue associated with a
1885 * q_vector.
1886 **/
91281fd3 1887static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1888{
1889 struct ixgbe_q_vector *q_vector =
1890 container_of(napi, struct ixgbe_q_vector, napi);
1891 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1892 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1893 int work_done = 0, i;
1894 long r_idx;
91281fd3
AD		 1895 bool tx_clean_complete = true;
1896
1897 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1898 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1899 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1900#ifdef CONFIG_IXGBE_DCA
1901 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1902 ixgbe_update_tx_dca(adapter, ring);
1903#endif
1904 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1905 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1906 r_idx + 1);
1907 }
f0848276
JB		 1908
1909 /* attempt to distribute budget to each queue fairly, but don't allow
1910 * the budget to go below 1 because we'll exit polling */
1911 budget /= (q_vector->rxr_count ?: 1);
1912 budget = max(budget, 1);
1913 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1914 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1915 ring = adapter->rx_ring[r_idx];
5dd2d332 1916#ifdef CONFIG_IXGBE_DCA
f0848276 1917 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1918 ixgbe_update_rx_dca(adapter, ring);
f0848276 1919#endif
91281fd3 1920 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276
JB		 1921 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1922 r_idx + 1);
1923 }
1924
1925 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1926 ring = adapter->rx_ring[r_idx];
f0848276 1927 /* If all Rx work done, exit the polling mode */
7f821875 1928 if (work_done < budget) {
288379f0 1929 napi_complete(napi);
f7554a2b 1930 if (adapter->rx_itr_setting & 1)
f0848276
JB		 1931 ixgbe_set_itr_msix(q_vector);
1932 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1933 ixgbe_irq_enable_queues(adapter,
1934 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1935 return 0;
1936 }
1937
1938 return work_done;
1939}
91281fd3
AD		 1940
1941/**
1942 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1943 * @napi: napi struct with our devices info in it
1944 * @budget: amount of work driver is allowed to do this pass, in packets
1945 *
1946 * This function is optimized for cleaning one queue only on a single
1947 * q_vector!!!
1948 **/
1949static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1950{
1951 struct ixgbe_q_vector *q_vector =
1952 container_of(napi, struct ixgbe_q_vector, napi);
1953 struct ixgbe_adapter *adapter = q_vector->adapter;
1954 struct ixgbe_ring *tx_ring = NULL;
1955 int work_done = 0;
1956 long r_idx;
1957
1958 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
4a0b9ca0 1959 tx_ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1960#ifdef CONFIG_IXGBE_DCA
1961 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1962 ixgbe_update_tx_dca(adapter, tx_ring);
1963#endif
1964
1965 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1966 work_done = budget;
1967
f7554a2b 1968 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 1969 if (work_done < budget) {
1970 napi_complete(napi);
f7554a2b 1971 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 1972 ixgbe_set_itr_msix(q_vector);
1973 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1974 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1975 }
1976
1977 return work_done;
1978}
1979
021230d4 1980static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1981 int r_idx)
021230d4 1982{
7a921c93
AD		 1983 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1984
1985 set_bit(r_idx, q_vector->rxr_idx);
1986 q_vector->rxr_count++;
021230d4
AV		 1987}
1988
1989static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 1990 int t_idx)
021230d4 1991{
7a921c93
AD		 1992 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1993
1994 set_bit(t_idx, q_vector->txr_idx);
1995 q_vector->txr_count++;
021230d4
AV		 1996}
1997
9a799d71 1998/**
021230d4
AV		 1999 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2000 * @adapter: board private structure to initialize
2001 * @vectors: allotted vector count for descriptor rings
9a799d71 2002 *
021230d4
AV		 2003 * This function maps descriptor rings to the queue-specific vectors
2004 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2005 * one vector per ring/queue, but on a constrained vector budget, we
2006 * group the rings as "efficiently" as possible. You would add new
2007 * mapping configurations in here.
9a799d71 2008 **/
021230d4 2009static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 2010 int vectors)
021230d4
AV		 2011{
2012 int v_start = 0;
2013 int rxr_idx = 0, txr_idx = 0;
2014 int rxr_remaining = adapter->num_rx_queues;
2015 int txr_remaining = adapter->num_tx_queues;
2016 int i, j;
2017 int rqpv, tqpv;
2018 int err = 0;
2019
2020 /* No mapping required if MSI-X is disabled. */
2021 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2022 goto out;
9a799d71 2023
021230d4
AV		 2024 /*
2025 * The ideal configuration...
2026 * We have enough vectors to map one per queue.
2027 */
2028 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2029 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2030 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2031
021230d4
AV		 2032 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2033 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2034
9a799d71 2035 goto out;
021230d4 2036 }
9a799d71 2037
021230d4
AV		 2038 /*
2039 * If we don't have enough vectors for a 1-to-1
2040 * mapping, we'll have to group them so there are
2041 * multiple queues per vector.
2042 */
2043 /* Re-adjusting *qpv takes care of the remainder. */
2044 for (i = v_start; i < vectors; i++) {
2045 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2046 for (j = 0; j < rqpv; j++) {
2047 map_vector_to_rxq(adapter, i, rxr_idx);
2048 rxr_idx++;
2049 rxr_remaining--;
2050 }
2051 }
2052 for (i = v_start; i < vectors; i++) {
2053 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2054 for (j = 0; j < tqpv; j++) {
2055 map_vector_to_txq(adapter, i, txr_idx);
2056 txr_idx++;
2057 txr_remaining--;
9a799d71 2058 }
9a799d71
AK		 2059 }
2060
021230d4
AV		 2061out:
2062 return err;
2063}
2064
2065/**
2066 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2067 * @adapter: board private structure
2068 *
2069 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2070 * interrupts from the kernel.
2071 **/
2072static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2073{
2074 struct net_device *netdev = adapter->netdev;
2075 irqreturn_t (*handler)(int, void *);
2076 int i, vector, q_vectors, err;
cb13fc20 2077 int ri=0, ti=0;
021230d4
AV		 2078
2079 /* Decrement for Other and TCP Timer vectors */
2080 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2081
2082 /* Map the Tx/Rx rings to the vectors we were allotted. */
2083 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2084 if (err)
2085 goto out;
2086
2087#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 2088 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2089 &ixgbe_msix_clean_many)
021230d4 2090 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 2091 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 2092
2093 if(handler == &ixgbe_msix_clean_rx) {
2094 sprintf(adapter->name[vector], "%s-%s-%d",
2095 netdev->name, "rx", ri++);
2096 }
2097 else if(handler == &ixgbe_msix_clean_tx) {
2098 sprintf(adapter->name[vector], "%s-%s-%d",
2099 netdev->name, "tx", ti++);
2100 }
2101 else
2102 sprintf(adapter->name[vector], "%s-%s-%d",
2103 netdev->name, "TxRx", vector);
2104
021230d4 2105 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 2106 handler, 0, adapter->name[vector],
7a921c93 2107 adapter->q_vector[vector]);
9a799d71
AK		 2108 if (err) {
2109 DPRINTK(PROBE, ERR,
b4617240
PW		 2110 "request_irq failed for MSIX interrupt "
2111 "Error: %d\n", err);
021230d4 2112 goto free_queue_irqs;
9a799d71 2113 }
9a799d71
AK		 2114 }
2115
021230d4
AV		 2116 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2117 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2118 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 2119 if (err) {
2120 DPRINTK(PROBE, ERR,
2121 "request_irq for msix_lsc failed: %d\n", err);
021230d4 2122 goto free_queue_irqs;
9a799d71
AK		 2123 }
2124
9a799d71
AK		 2125 return 0;
2126
021230d4
AV		 2127free_queue_irqs:
2128 for (i = vector - 1; i >= 0; i--)
2129 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 2130 adapter->q_vector[i]);
021230d4
AV		 2131 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2132 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2133 kfree(adapter->msix_entries);
2134 adapter->msix_entries = NULL;
021230d4 2135out:
9a799d71
AK		 2136 return err;
2137}
2138
f494e8fa
AV		 2139static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2140{
7a921c93 2141 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 2142 u8 current_itr;
2143 u32 new_itr = q_vector->eitr;
4a0b9ca0
PW		 2144 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2145 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
f494e8fa 2146
30efa5a3 2147 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 2148 q_vector->tx_itr,
2149 tx_ring->total_packets,
2150 tx_ring->total_bytes);
30efa5a3 2151 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 2152 q_vector->rx_itr,
2153 rx_ring->total_packets,
2154 rx_ring->total_bytes);
f494e8fa 2155
30efa5a3 2156 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 2157
2158 switch (current_itr) {
2159 /* counts and packets in update_itr are dependent on these numbers */
2160 case lowest_latency:
2161 new_itr = 100000;
2162 break;
2163 case low_latency:
2164 new_itr = 20000; /* aka hwitr = ~200 */
2165 break;
2166 case bulk_latency:
2167 new_itr = 8000;
2168 break;
2169 default:
2170 break;
2171 }
2172
2173 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 2174 /* do an exponential smoothing */
2175 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 2176
2177 /* save the algorithm value here, not the smoothed one */
2178 q_vector->eitr = new_itr;
fe49f04a
AD		 2179
2180 ixgbe_write_eitr(q_vector);
f494e8fa 2181 }
f494e8fa
AV		 2182}
2183
79aefa45
AD		 2184/**
2185 * ixgbe_irq_enable - Enable default interrupt generation settings
2186 * @adapter: board private structure
2187 **/
2188static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
2189{
2190 u32 mask;
835462fc
NS		 2191
2192 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 2193 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2194 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 2195 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 2196 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2197 mask |= IXGBE_EIMS_GPI_SDP1;
2198 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2199 if (adapter->num_vfs)
2200 mask |= IXGBE_EIMS_MAILBOX;
e8e26350 2201 }
c4cf55e5
PWJ		 2202 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2203 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2204 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2205
79aefa45 2206 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 2207 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45 2208 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2209
2210 if (adapter->num_vfs > 32) {
2211 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2212 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2213 }
79aefa45 2214}
021230d4 2215
9a799d71 2216/**
021230d4 2217 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2218 * @irq: interrupt number
2219 * @data: pointer to a network interface device structure
9a799d71
AK		 2220 **/
2221static irqreturn_t ixgbe_intr(int irq, void *data)
2222{
2223 struct net_device *netdev = data;
2224 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2225 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2226 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2227 u32 eicr;
2228
54037505
DS		 2229 /*
2230 * Workaround for silicon errata. Mask the interrupts
2231 * before the read of EICR.
2232 */
2233 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2234
021230d4
AV		 2235 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2236 * therefore no explict interrupt disable is necessary */
2237 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 2238 if (!eicr) {
2239 /* shared interrupt alert!
2240 * make sure interrupts are enabled because the read will
2241 * have disabled interrupts due to EIAM */
2242 ixgbe_irq_enable(adapter);
9a799d71 2243 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2244 }
9a799d71 2245
cf8280ee
JB		 2246 if (eicr & IXGBE_EICR_LSC)
2247 ixgbe_check_lsc(adapter);
021230d4 2248
e8e26350
PW		 2249 if (hw->mac.type == ixgbe_mac_82599EB)
2250 ixgbe_check_sfp_event(adapter, eicr);
2251
0befdb3e
JB		 2252 ixgbe_check_fan_failure(adapter, eicr);
2253
7a921c93 2254 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 2255 adapter->tx_ring[0]->total_packets = 0;
2256 adapter->tx_ring[0]->total_bytes = 0;
2257 adapter->rx_ring[0]->total_packets = 0;
2258 adapter->rx_ring[0]->total_bytes = 0;
021230d4 2259 /* would disable interrupts here but EIAM disabled it */
7a921c93 2260 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2261 }
2262
2263 return IRQ_HANDLED;
2264}
2265
021230d4
AV		 2266static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2267{
2268 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2269
2270 for (i = 0; i < q_vectors; i++) {
7a921c93 2271 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 2272 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2273 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2274 q_vector->rxr_count = 0;
2275 q_vector->txr_count = 0;
2276 }
2277}
2278
9a799d71
AK		 2279/**
2280 * ixgbe_request_irq - initialize interrupts
2281 * @adapter: board private structure
2282 *
2283 * Attempts to configure interrupts using the best available
2284 * capabilities of the hardware and kernel.
2285 **/
021230d4 2286static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2287{
2288 struct net_device *netdev = adapter->netdev;
021230d4 2289 int err;
9a799d71 2290
021230d4
AV		 2291 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2292 err = ixgbe_request_msix_irqs(adapter);
2293 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2294 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
b4617240 2295 netdev->name, netdev);
021230d4 2296 } else {
a0607fd3 2297 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
b4617240 2298 netdev->name, netdev);
9a799d71
AK		 2299 }
2300
9a799d71
AK		 2301 if (err)
2302 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
2303
9a799d71
AK		 2304 return err;
2305}
2306
2307static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2308{
2309 struct net_device *netdev = adapter->netdev;
2310
2311 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2312 int i, q_vectors;
9a799d71 2313
021230d4
AV		 2314 q_vectors = adapter->num_msix_vectors;
2315
2316 i = q_vectors - 1;
9a799d71 2317 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 2318
021230d4
AV		 2319 i--;
2320 for (; i >= 0; i--) {
2321 free_irq(adapter->msix_entries[i].vector,
7a921c93 2322 adapter->q_vector[i]);
021230d4
AV		 2323 }
2324
2325 ixgbe_reset_q_vectors(adapter);
2326 } else {
2327 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 2328 }
2329}
2330
22d5a71b
JB		 2331/**
2332 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2333 * @adapter: board private structure
2334 **/
2335static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2336{
835462fc
NS		 2337 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2338 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2339 } else {
2340 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2341 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2342 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2343 if (adapter->num_vfs > 32)
2344 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
22d5a71b
JB		 2345 }
2346 IXGBE_WRITE_FLUSH(&adapter->hw);
2347 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2348 int i;
2349 for (i = 0; i < adapter->num_msix_vectors; i++)
2350 synchronize_irq(adapter->msix_entries[i].vector);
2351 } else {
2352 synchronize_irq(adapter->pdev->irq);
2353 }
2354}
2355
9a799d71
AK		 2356/**
2357 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2358 *
2359 **/
2360static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2361{
9a799d71
AK		 2362 struct ixgbe_hw *hw = &adapter->hw;
2363
021230d4 2364 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
f7554a2b 2365 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2366
e8e26350
PW		 2367 ixgbe_set_ivar(adapter, 0, 0, 0);
2368 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2369
2370 map_vector_to_rxq(adapter, 0, 0);
2371 map_vector_to_txq(adapter, 0, 0);
2372
2373 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2374}
2375
2376/**
3a581073 2377 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2378 * @adapter: board private structure
2379 *
2380 * Configure the Tx unit of the MAC after a reset.
2381 **/
2382static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2383{
12207e49 2384 u64 tdba;
9a799d71 2385 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2386 u32 i, j, tdlen, txctrl;
9a799d71
AK		 2387
2388 /* Setup the HW Tx Head and Tail descriptor pointers */
2389 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2390 struct ixgbe_ring *ring = adapter->tx_ring[i];
e01c31a5
JB		 2391 j = ring->reg_idx;
2392 tdba = ring->dma;
2393 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 2394 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 2395 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 2396 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
2397 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
2398 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
2399 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
4a0b9ca0
PW		 2400 adapter->tx_ring[i]->head = IXGBE_TDH(j);
2401 adapter->tx_ring[i]->tail = IXGBE_TDT(j);
84f62d4b
PWJ		 2402 /*
2403 * Disable Tx Head Writeback RO bit, since this hoses
021230d4
AV		 2404 * bookkeeping if things aren't delivered in order.
2405 */
84f62d4b
PWJ		 2406 switch (hw->mac.type) {
2407 case ixgbe_mac_82598EB:
2408 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
2409 break;
2410 case ixgbe_mac_82599EB:
2411 default:
2412 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
2413 break;
2414 }
021230d4 2415 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
84f62d4b
PWJ		 2416 switch (hw->mac.type) {
2417 case ixgbe_mac_82598EB:
2418 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
2419 break;
2420 case ixgbe_mac_82599EB:
2421 default:
2422 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
2423 break;
2424 }
9a799d71 2425 }
ee5f784a 2426
e8e26350 2427 if (hw->mac.type == ixgbe_mac_82599EB) {
ee5f784a 2428 u32 rttdcs;
1cdd1ec8 2429 u32 mask;
ee5f784a
DS		 2430
2431 /* disable the arbiter while setting MTQC */
2432 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2433 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2434 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2435
1cdd1ec8
GR		 2436 /* set transmit pool layout */
2437 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2438 switch (adapter->flags & mask) {
2439
2440 case (IXGBE_FLAG_SRIOV_ENABLED):
2441 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2442 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2443 break;
2444
2445 case (IXGBE_FLAG_DCB_ENABLED):
2446 /* We enable 8 traffic classes, DCB only */
2447 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2448 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2449 break;
2450
2451 default:
ee5f784a 2452 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
1cdd1ec8
GR		 2453 break;
2454 }
ee5f784a
DS		 2455
2456 /* re-eable the arbiter */
2457 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2458 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
e8e26350 2459 }
9a799d71
AK		 2460}
2461
e8e26350 2462#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2463
a6616b42
YZ		 2464static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2465 struct ixgbe_ring *rx_ring)
cc41ac7c 2466{
cc41ac7c 2467 u32 srrctl;
a6616b42 2468 int index;
0cefafad 2469 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 2470
a6616b42
YZ		 2471 index = rx_ring->reg_idx;
2472 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2473 unsigned long mask;
0cefafad 2474 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 2475 index = index & mask;
cc41ac7c 2476 }
cc41ac7c
JB		 2477 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2478
2479 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2480 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2481
afafd5b0
AD		 2482 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2483 IXGBE_SRRCTL_BSIZEHDR_MASK;
2484
6e455b89 2485 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 2486#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2487 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2488#else
2489 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2490#endif
cc41ac7c 2491 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2492 } else {
afafd5b0
AD		 2493 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2494 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2495 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2496 }
e8e26350 2497
cc41ac7c
JB		 2498 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2499}
9a799d71 2500
0cefafad
JB		 2501static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2502{
2503 u32 mrqc = 0;
2504 int mask;
2505
2506 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2507 return mrqc;
2508
2509 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2510#ifdef CONFIG_IXGBE_DCB
2511 | IXGBE_FLAG_DCB_ENABLED
2512#endif
1cdd1ec8 2513 | IXGBE_FLAG_SRIOV_ENABLED
0cefafad
JB		 2514 );
2515
2516 switch (mask) {
2517 case (IXGBE_FLAG_RSS_ENABLED):
2518 mrqc = IXGBE_MRQC_RSSEN;
2519 break;
1cdd1ec8
GR		 2520 case (IXGBE_FLAG_SRIOV_ENABLED):
2521 mrqc = IXGBE_MRQC_VMDQEN;
2522 break;
0cefafad
JB		 2523#ifdef CONFIG_IXGBE_DCB
2524 case (IXGBE_FLAG_DCB_ENABLED):
2525 mrqc = IXGBE_MRQC_RT8TCEN;
2526 break;
2527#endif /* CONFIG_IXGBE_DCB */
2528 default:
2529 break;
2530 }
2531
2532 return mrqc;
2533}
2534
bb5a9ad2
NS		 2535/**
2536 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2537 * @adapter: address of board private structure
2538 * @index: index of ring to set
bb5a9ad2 2539 **/
edd2ea55 2540static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
bb5a9ad2
NS		 2541{
2542 struct ixgbe_ring *rx_ring;
2543 struct ixgbe_hw *hw = &adapter->hw;
2544 int j;
2545 u32 rscctrl;
edd2ea55 2546 int rx_buf_len;
bb5a9ad2 2547
4a0b9ca0 2548 rx_ring = adapter->rx_ring[index];
bb5a9ad2 2549 j = rx_ring->reg_idx;
edd2ea55 2550 rx_buf_len = rx_ring->rx_buf_len;
bb5a9ad2
NS		 2551 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2552 rscctrl |= IXGBE_RSCCTL_RSCEN;
2553 /*
2554 * we must limit the number of descriptors so that the
2555 * total size of max desc * buf_len is not greater
2556 * than 65535
2557 */
2558 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2559#if (MAX_SKB_FRAGS > 16)
2560 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2561#elif (MAX_SKB_FRAGS > 8)
2562 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2563#elif (MAX_SKB_FRAGS > 4)
2564 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2565#else
2566 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2567#endif
2568 } else {
2569 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2570 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2571 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2572 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2573 else
2574 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2575 }
2576 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2577}
2578
9a799d71 2579/**
3a581073 2580 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 2581 * @adapter: board private structure
2582 *
2583 * Configure the Rx unit of the MAC after a reset.
2584 **/
2585static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2586{
2587 u64 rdba;
2588 struct ixgbe_hw *hw = &adapter->hw;
a6616b42 2589 struct ixgbe_ring *rx_ring;
9a799d71
AK		 2590 struct net_device *netdev = adapter->netdev;
2591 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2592 int i, j;
9a799d71 2593 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 2594 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2595 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2596 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 2597 u32 fctrl, hlreg0;
509ee935 2598 u32 reta = 0, mrqc = 0;
cc41ac7c 2599 u32 rdrxctl;
7c6e0a43 2600 int rx_buf_len;
9a799d71
AK		 2601
2602 /* Decide whether to use packet split mode or not */
1cdd1ec8
GR		 2603 /* Do not use packet split if we're in SR-IOV Mode */
2604 if (!adapter->num_vfs)
2605 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 2606
2607 /* Set the RX buffer length according to the mode */
2608 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2609 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 2610 if (hw->mac.type == ixgbe_mac_82599EB) {
2611 /* PSRTYPE must be initialized in 82599 */
2612 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2613 IXGBE_PSRTYPE_UDPHDR |
2614 IXGBE_PSRTYPE_IPV4HDR |
dfa12f05
YZ		 2615 IXGBE_PSRTYPE_IPV6HDR |
2616 IXGBE_PSRTYPE_L2HDR;
1cdd1ec8
GR		 2617 IXGBE_WRITE_REG(hw,
2618 IXGBE_PSRTYPE(adapter->num_vfs),
2619 psrtype);
e8e26350 2620 }
9a799d71 2621 } else {
0c19d6af 2622 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2623 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2624 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2625 else
7c6e0a43 2626 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 2627 }
2628
2629 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2630 fctrl |= IXGBE_FCTRL_BAM;
021230d4 2631 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 2632 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 2633 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2634
2635 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2636 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2637 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2638 else
2639 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
63f39bd1 2640#ifdef IXGBE_FCOE
f34c5c82 2641 if (netdev->features & NETIF_F_FCOE_MTU)
63f39bd1
YZ		 2642 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2643#endif
9a799d71
AK		 2644 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2645
4a0b9ca0 2646 rdlen = adapter->rx_ring[0]->count * sizeof(union ixgbe_adv_rx_desc);
9a799d71
AK		 2647 /* disable receives while setting up the descriptors */
2648 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2649 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2650
0cefafad
JB		 2651 /*
2652 * Setup the HW Rx Head and Tail Descriptor Pointers and
2653 * the Base and Length of the Rx Descriptor Ring
2654 */
9a799d71 2655 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2656 rx_ring = adapter->rx_ring[i];
a6616b42
YZ		 2657 rdba = rx_ring->dma;
2658 j = rx_ring->reg_idx;
284901a9 2659 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 2660 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2661 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2662 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2663 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
a6616b42
YZ		 2664 rx_ring->head = IXGBE_RDH(j);
2665 rx_ring->tail = IXGBE_RDT(j);
2666 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2667
6e455b89
YZ		 2668 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2669 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
1b3ff02e
PWJ		 2670 else
2671 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2672
63f39bd1 2673#ifdef IXGBE_FCOE
f34c5c82 2674 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2675 struct ixgbe_ring_feature *f;
2676 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2677 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2678 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2679 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2680 rx_ring->rx_buf_len =
2681 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2682 }
63f39bd1
YZ		 2683 }
2684
2685#endif /* IXGBE_FCOE */
a6616b42 2686 ixgbe_configure_srrctl(adapter, rx_ring);
9a799d71
AK		 2687 }
2688
e8e26350
PW		 2689 if (hw->mac.type == ixgbe_mac_82598EB) {
2690 /*
2691 * For VMDq support of different descriptor types or
2692 * buffer sizes through the use of multiple SRRCTL
2693 * registers, RDRXCTL.MVMEN must be set to 1
2694 *
2695 * also, the manual doesn't mention it clearly but DCA hints
2696 * will only use queue 0's tags unless this bit is set. Side
2697 * effects of setting this bit are only that SRRCTL must be
2698 * fully programmed [0..15]
2699 */
2a41ff81
JB		 2700 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2701 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2702 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 2703 }
177db6ff 2704
1cdd1ec8
GR		 2705 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2706 u32 vt_reg_bits;
2707 u32 reg_offset, vf_shift;
2708 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2709 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2710 | IXGBE_VT_CTL_REPLEN;
2711 vt_reg_bits |= (adapter->num_vfs <<
2712 IXGBE_VT_CTL_POOL_SHIFT);
2713 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2714 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2715
2716 vf_shift = adapter->num_vfs % 32;
2717 reg_offset = adapter->num_vfs / 32;
2718 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2719 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2720 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2721 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2722 /* Enable only the PF's pool for Tx/Rx */
2723 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2724 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2725 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f0412776 2726 ixgbe_set_vmolr(hw, adapter->num_vfs, true);
1cdd1ec8
GR		 2727 }
2728
e8e26350 2729 /* Program MRQC for the distribution of queues */
0cefafad 2730 mrqc = ixgbe_setup_mrqc(adapter);
e8e26350 2731
021230d4 2732 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 2733 /* Fill out redirection table */
021230d4
AV		 2734 for (i = 0, j = 0; i < 128; i++, j++) {
2735 if (j == adapter->ring_feature[RING_F_RSS].indices)
2736 j = 0;
2737 /* reta = 4-byte sliding window of
2738 * 0x00..(indices-1)(indices-1)00..etc. */
2739 reta = (reta << 8) | (j * 0x11);
2740 if ((i & 3) == 3)
2741 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 2742 }
2743
2744 /* Fill out hash function seeds */
2745 for (i = 0; i < 10; i++)
7c6e0a43 2746 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 2747
2a41ff81
JB		 2748 if (hw->mac.type == ixgbe_mac_82598EB)
2749 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 2750 /* Perform hash on these packet types */
2a41ff81
JB		 2751 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2752 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2753 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2754 | IXGBE_MRQC_RSS_FIELD_IPV6
2755 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2756 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 2757 }
2a41ff81 2758 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 2759
1cdd1ec8
GR		 2760 if (adapter->num_vfs) {
2761 u32 reg;
2762
2763 /* Map PF MAC address in RAR Entry 0 to first pool
2764 * following VFs */
2765 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2766
2767 /* Set up VF register offsets for selected VT Mode, i.e.
2768 * 64 VFs for SR-IOV */
2769 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2770 reg |= IXGBE_GCR_EXT_SRIOV;
2771 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2772 }
2773
021230d4
AV		 2774 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2775
2776 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2777 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2778 /* Disable indicating checksum in descriptor, enables
2779 * RSS hash */
9a799d71 2780 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 2781 }
021230d4
AV		 2782 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2783 /* Enable IPv4 payload checksum for UDP fragments
2784 * if PCSD is not set */
2785 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2786 }
2787
2788 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 2789
2790 if (hw->mac.type == ixgbe_mac_82599EB) {
2791 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2792 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 2793 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 2794 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2795 }
f8212f97 2796
0c19d6af 2797 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 2798 /* Enable 82599 HW-RSC */
bb5a9ad2 2799 for (i = 0; i < adapter->num_rx_queues; i++)
edd2ea55 2800 ixgbe_configure_rscctl(adapter, i);
bb5a9ad2 2801
f8212f97
AD		 2802 /* Disable RSC for ACK packets */
2803 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2804 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2805 }
9a799d71
AK		 2806}
2807
068c89b0
DS		 2808static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2809{
2810 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2811 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2812 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2813
2814 /* add VID to filter table */
1ada1b1b 2815 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
068c89b0
DS		 2816}
2817
2818static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2819{
2820 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2821 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2822 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2823
2824 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2825 ixgbe_irq_disable(adapter);
2826
2827 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2828
2829 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2830 ixgbe_irq_enable(adapter);
2831
2832 /* remove VID from filter table */
1ada1b1b 2833 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
068c89b0
DS		 2834}
2835
5f6c0181
JB		 2836/**
2837 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
2838 * @adapter: driver data
2839 */
2840static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
2841{
2842 struct ixgbe_hw *hw = &adapter->hw;
2843 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2844 int i, j;
2845
2846 switch (hw->mac.type) {
2847 case ixgbe_mac_82598EB:
38e0bd98
YZ		 2848 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2849#ifdef CONFIG_IXGBE_DCB
2850 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
2851 vlnctrl &= ~IXGBE_VLNCTRL_VME;
2852#endif
5f6c0181
JB		 2853 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2854 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2855 break;
2856 case ixgbe_mac_82599EB:
2857 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2858 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2859 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
38e0bd98
YZ		 2860#ifdef CONFIG_IXGBE_DCB
2861 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
2862 break;
2863#endif
5f6c0181
JB		 2864 for (i = 0; i < adapter->num_rx_queues; i++) {
2865 j = adapter->rx_ring[i]->reg_idx;
2866 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2867 vlnctrl &= ~IXGBE_RXDCTL_VME;
2868 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2869 }
2870 break;
2871 default:
2872 break;
2873 }
2874}
2875
2876/**
2877 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
2878 * @adapter: driver data
2879 */
2880static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
2881{
2882 struct ixgbe_hw *hw = &adapter->hw;
2883 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2884 int i, j;
2885
2886 switch (hw->mac.type) {
2887 case ixgbe_mac_82598EB:
2888 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2889 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2890 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2891 break;
2892 case ixgbe_mac_82599EB:
2893 vlnctrl |= IXGBE_VLNCTRL_VFE;
2894 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2895 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2896 for (i = 0; i < adapter->num_rx_queues; i++) {
2897 j = adapter->rx_ring[i]->reg_idx;
2898 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2899 vlnctrl |= IXGBE_RXDCTL_VME;
2900 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2901 }
2902 break;
2903 default:
2904 break;
2905 }
2906}
2907
9a799d71 2908static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2909 struct vlan_group *grp)
9a799d71
AK		 2910{
2911 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 2912
d4f80882
AV		 2913 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2914 ixgbe_irq_disable(adapter);
9a799d71
AK		 2915 adapter->vlgrp = grp;
2916
2f90b865
AD		 2917 /*
2918 * For a DCB driver, always enable VLAN tag stripping so we can
2919 * still receive traffic from a DCB-enabled host even if we're
2920 * not in DCB mode.
2921 */
5f6c0181 2922 ixgbe_vlan_filter_enable(adapter);
dc63d377 2923
e8e26350 2924 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2925
d4f80882
AV		 2926 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2927 ixgbe_irq_enable(adapter);
9a799d71
AK		 2928}
2929
9a799d71
AK		 2930static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2931{
2932 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2933
2934 if (adapter->vlgrp) {
2935 u16 vid;
2936 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2937 if (!vlan_group_get_device(adapter->vlgrp, vid))
2938 continue;
2939 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2940 }
2941 }
2942}
2943
2944/**
2c5645cf 2945 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2946 * @netdev: network interface device structure
2947 *
2c5645cf
CL		 2948 * The set_rx_method entry point is called whenever the unicast/multicast
2949 * address list or the network interface flags are updated. This routine is
2950 * responsible for configuring the hardware for proper unicast, multicast and
2951 * promiscuous mode.
9a799d71 2952 **/
7f870475 2953void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2954{
2955 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2956 struct ixgbe_hw *hw = &adapter->hw;
5f6c0181 2957 u32 fctrl;
9a799d71
AK		 2958
2959 /* Check for Promiscuous and All Multicast modes */
2960
2961 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2962
2963 if (netdev->flags & IFF_PROMISC) {
e433ea1f 2964 hw->addr_ctrl.user_set_promisc = true;
9a799d71 2965 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
5f6c0181
JB		 2966 /* don't hardware filter vlans in promisc mode */
2967 ixgbe_vlan_filter_disable(adapter);
9a799d71 2968 } else {
746b9f02
PM		 2969 if (netdev->flags & IFF_ALLMULTI) {
2970 fctrl |= IXGBE_FCTRL_MPE;
2971 fctrl &= ~IXGBE_FCTRL_UPE;
e433ea1f 2972 } else if (!hw->addr_ctrl.uc_set_promisc) {
746b9f02
PM		 2973 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2974 }
5f6c0181 2975 ixgbe_vlan_filter_enable(adapter);
e433ea1f 2976 hw->addr_ctrl.user_set_promisc = false;
9a799d71
AK		 2977 }
2978
2979 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2980
2c5645cf 2981 /* reprogram secondary unicast list */
32e7bfc4 2982 hw->mac.ops.update_uc_addr_list(hw, netdev);
9a799d71 2983
2c5645cf 2984 /* reprogram multicast list */
2853eb89
JP		 2985 hw->mac.ops.update_mc_addr_list(hw, netdev);
2986
1cdd1ec8
GR		 2987 if (adapter->num_vfs)
2988 ixgbe_restore_vf_multicasts(adapter);
9a799d71
AK		 2989}
2990
021230d4
AV		 2991static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2992{
2993 int q_idx;
2994 struct ixgbe_q_vector *q_vector;
2995 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2996
2997 /* legacy and MSI only use one vector */
2998 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2999 q_vectors = 1;
3000
3001 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 3002 struct napi_struct *napi;
7a921c93 3003 q_vector = adapter->q_vector[q_idx];
f0848276 3004 napi = &q_vector->napi;
91281fd3
AD		 3005 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3006 if (!q_vector->rxr_count || !q_vector->txr_count) {
3007 if (q_vector->txr_count == 1)
3008 napi->poll = &ixgbe_clean_txonly;
3009 else if (q_vector->rxr_count == 1)
3010 napi->poll = &ixgbe_clean_rxonly;
3011 }
3012 }
f0848276
JB		 3013
3014 napi_enable(napi);
021230d4
AV		 3015 }
3016}
3017
3018static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3019{
3020 int q_idx;
3021 struct ixgbe_q_vector *q_vector;
3022 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3023
3024 /* legacy and MSI only use one vector */
3025 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3026 q_vectors = 1;
3027
3028 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3029 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3030 napi_disable(&q_vector->napi);
3031 }
3032}
3033
7a6b6f51 3034#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3035/*
3036 * ixgbe_configure_dcb - Configure DCB hardware
3037 * @adapter: ixgbe adapter struct
3038 *
3039 * This is called by the driver on open to configure the DCB hardware.
3040 * This is also called by the gennetlink interface when reconfiguring
3041 * the DCB state.
3042 */
3043static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3044{
3045 struct ixgbe_hw *hw = &adapter->hw;
5f6c0181 3046 u32 txdctl;
2f90b865
AD		 3047 int i, j;
3048
3049 ixgbe_dcb_check_config(&adapter->dcb_cfg);
3050 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
3051 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
3052
3053 /* reconfigure the hardware */
3054 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3055
3056 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3057 j = adapter->tx_ring[i]->reg_idx;
2f90b865
AD		 3058 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3059 /* PThresh workaround for Tx hang with DFP enabled. */
3060 txdctl |= 32;
3061 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3062 }
3063 /* Enable VLAN tag insert/strip */
5f6c0181
JB		 3064 ixgbe_vlan_filter_enable(adapter);
3065
2f90b865
AD		 3066 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3067}
3068
3069#endif
9a799d71
AK		 3070static void ixgbe_configure(struct ixgbe_adapter *adapter)
3071{
3072 struct net_device *netdev = adapter->netdev;
c4cf55e5 3073 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3074 int i;
3075
2c5645cf 3076 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 3077
3078 ixgbe_restore_vlan(adapter);
7a6b6f51 3079#ifdef CONFIG_IXGBE_DCB
2f90b865 3080 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
b352e40d
YZ		 3081 if (hw->mac.type == ixgbe_mac_82598EB)
3082 netif_set_gso_max_size(netdev, 32768);
3083 else
3084 netif_set_gso_max_size(netdev, 65536);
2f90b865
AD		 3085 ixgbe_configure_dcb(adapter);
3086 } else {
3087 netif_set_gso_max_size(netdev, 65536);
3088 }
3089#else
3090 netif_set_gso_max_size(netdev, 65536);
3091#endif
9a799d71 3092
eacd73f7
YZ		 3093#ifdef IXGBE_FCOE
3094 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3095 ixgbe_configure_fcoe(adapter);
3096
3097#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3098 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3099 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3100 adapter->tx_ring[i]->atr_sample_rate =
c4cf55e5
PWJ		 3101 adapter->atr_sample_rate;
3102 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3103 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3104 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3105 }
3106
9a799d71
AK		 3107 ixgbe_configure_tx(adapter);
3108 ixgbe_configure_rx(adapter);
3109 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 3110 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
3111 (adapter->rx_ring[i]->count - 1));
9a799d71
AK		 3112}
3113
e8e26350
PW		 3114static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3115{
3116 switch (hw->phy.type) {
3117 case ixgbe_phy_sfp_avago:
3118 case ixgbe_phy_sfp_ftl:
3119 case ixgbe_phy_sfp_intel:
3120 case ixgbe_phy_sfp_unknown:
3121 case ixgbe_phy_tw_tyco:
3122 case ixgbe_phy_tw_unknown:
3123 return true;
3124 default:
3125 return false;
3126 }
3127}
3128
0ecc061d 3129/**
e8e26350
PW		 3130 * ixgbe_sfp_link_config - set up SFP+ link
3131 * @adapter: pointer to private adapter struct
3132 **/
3133static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3134{
3135 struct ixgbe_hw *hw = &adapter->hw;
3136
3137 if (hw->phy.multispeed_fiber) {
3138 /*
3139 * In multispeed fiber setups, the device may not have
3140 * had a physical connection when the driver loaded.
3141 * If that's the case, the initial link configuration
3142 * couldn't get the MAC into 10G or 1G mode, so we'll
3143 * never have a link status change interrupt fire.
3144 * We need to try and force an autonegotiation
3145 * session, then bring up link.
3146 */
3147 hw->mac.ops.setup_sfp(hw);
3148 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3149 schedule_work(&adapter->multispeed_fiber_task);
3150 } else {
3151 /*
3152 * Direct Attach Cu and non-multispeed fiber modules
3153 * still need to be configured properly prior to
3154 * attempting link.
3155 */
3156 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3157 schedule_work(&adapter->sfp_config_module_task);
3158 }
3159}
3160
3161/**
3162 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3163 * @hw: pointer to private hardware struct
3164 *
3165 * Returns 0 on success, negative on failure
3166 **/
e8e26350 3167static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3168{
3169 u32 autoneg;
8620a103 3170 bool negotiation, link_up = false;
0ecc061d
PWJ		 3171 u32 ret = IXGBE_ERR_LINK_SETUP;
3172
3173 if (hw->mac.ops.check_link)
3174 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3175
3176 if (ret)
3177 goto link_cfg_out;
3178
3179 if (hw->mac.ops.get_link_capabilities)
8620a103 3180 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
0ecc061d
PWJ		 3181 if (ret)
3182 goto link_cfg_out;
3183
8620a103
MC		 3184 if (hw->mac.ops.setup_link)
3185 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3186link_cfg_out:
3187 return ret;
3188}
3189
e8e26350
PW		 3190#define IXGBE_MAX_RX_DESC_POLL 10
3191static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3192 int rxr)
3193{
4a0b9ca0 3194 int j = adapter->rx_ring[rxr]->reg_idx;
e8e26350
PW		 3195 int k;
3196
3197 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
3198 if (IXGBE_READ_REG(&adapter->hw,
3199 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
3200 break;
3201 else
3202 msleep(1);
3203 }
3204 if (k >= IXGBE_MAX_RX_DESC_POLL) {
3205 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
3206 "not set within the polling period\n", rxr);
3207 }
4a0b9ca0
PW		 3208 ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
3209 (adapter->rx_ring[rxr]->count - 1));
e8e26350
PW		 3210}
3211
9a799d71
AK		 3212static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3213{
3214 struct net_device *netdev = adapter->netdev;
9a799d71 3215 struct ixgbe_hw *hw = &adapter->hw;
021230d4 3216 int i, j = 0;
e8e26350 3217 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 3218 int err;
9a799d71 3219 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 3220 u32 txdctl, rxdctl, mhadd;
e8e26350 3221 u32 dmatxctl;
021230d4 3222 u32 gpie;
c9205697 3223 u32 ctrl_ext;
9a799d71 3224
5eba3699
AV		 3225 ixgbe_get_hw_control(adapter);
3226
021230d4
AV		 3227 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
3228 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 3229 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3230 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 3231 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 3232 } else {
3233 /* MSI only */
021230d4 3234 gpie = 0;
9a799d71 3235 }
1cdd1ec8
GR		 3236 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3237 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3238 gpie |= IXGBE_GPIE_VTMODE_64;
3239 }
021230d4
AV		 3240 /* XXX: to interrupt immediately for EICS writes, enable this */
3241 /* gpie |= IXGBE_GPIE_EIMEN; */
3242 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 3243 }
3244
9b471446
JB		 3245 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3246 /*
3247 * use EIAM to auto-mask when MSI-X interrupt is asserted
3248 * this saves a register write for every interrupt
3249 */
3250 switch (hw->mac.type) {
3251 case ixgbe_mac_82598EB:
3252 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3253 break;
3254 default:
3255 case ixgbe_mac_82599EB:
3256 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3257 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3258 break;
3259 }
3260 } else {
021230d4
AV		 3261 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3262 * specifically only auto mask tx and rx interrupts */
3263 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3264 }
9a799d71 3265
0befdb3e
JB		 3266 /* Enable fan failure interrupt if media type is copper */
3267 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3268 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3269 gpie |= IXGBE_SDP1_GPIEN;
3270 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3271 }
3272
e8e26350
PW		 3273 if (hw->mac.type == ixgbe_mac_82599EB) {
3274 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3275 gpie |= IXGBE_SDP1_GPIEN;
3276 gpie |= IXGBE_SDP2_GPIEN;
3277 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3278 }
3279
63f39bd1
YZ		 3280#ifdef IXGBE_FCOE
3281 /* adjust max frame to be able to do baby jumbo for FCoE */
f34c5c82 3282 if ((netdev->features & NETIF_F_FCOE_MTU) &&
63f39bd1
YZ		 3283 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3284 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3285
3286#endif /* IXGBE_FCOE */
021230d4 3287 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 3288 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3289 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3290 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3291
3292 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3293 }
3294
3295 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3296 j = adapter->tx_ring[i]->reg_idx;
021230d4 3297 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
ef021194
JB		 3298 if (adapter->rx_itr_setting == 0) {
3299 /* cannot set wthresh when itr==0 */
3300 txdctl &= ~0x007F0000;
3301 } else {
3302 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
3303 txdctl |= (8 << 16);
3304 }
e8e26350
PW		 3305 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3306 }
3307
3308 if (hw->mac.type == ixgbe_mac_82599EB) {
3309 /* DMATXCTL.EN must be set after all Tx queue config is done */
3310 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3311 dmatxctl |= IXGBE_DMATXCTL_TE;
3312 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3313 }
3314 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3315 j = adapter->tx_ring[i]->reg_idx;
e8e26350 3316 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 3317 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 3318 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
1cdd1ec8
GR		 3319 if (hw->mac.type == ixgbe_mac_82599EB) {
3320 int wait_loop = 10;
3321 /* poll for Tx Enable ready */
3322 do {
3323 msleep(1);
3324 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3325 } while (--wait_loop &&
3326 !(txdctl & IXGBE_TXDCTL_ENABLE));
3327 if (!wait_loop)
3328 DPRINTK(DRV, ERR, "Could not enable "
3329 "Tx Queue %d\n", j);
3330 }
9a799d71
AK		 3331 }
3332
e8e26350 3333 for (i = 0; i < num_rx_rings; i++) {
4a0b9ca0 3334 j = adapter->rx_ring[i]->reg_idx;
021230d4
AV		 3335 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3336 /* enable PTHRESH=32 descriptors (half the internal cache)
3337 * and HTHRESH=0 descriptors (to minimize latency on fetch),
3338 * this also removes a pesky rx_no_buffer_count increment */
3339 rxdctl |= 0x0020;
9a799d71 3340 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 3341 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 3342 if (hw->mac.type == ixgbe_mac_82599EB)
3343 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 3344 }
3345 /* enable all receives */
3346 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 3347 if (hw->mac.type == ixgbe_mac_82598EB)
3348 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
3349 else
3350 rxdctl |= IXGBE_RXCTRL_RXEN;
3351 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 3352
3353 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3354 ixgbe_configure_msix(adapter);
3355 else
3356 ixgbe_configure_msi_and_legacy(adapter);
3357
61fac744
PW		 3358 /* enable the optics */
3359 if (hw->phy.multispeed_fiber)
3360 hw->mac.ops.enable_tx_laser(hw);
3361
9a799d71 3362 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3363 ixgbe_napi_enable_all(adapter);
3364
3365 /* clear any pending interrupts, may auto mask */
3366 IXGBE_READ_REG(hw, IXGBE_EICR);
3367
9a799d71
AK		 3368 ixgbe_irq_enable(adapter);
3369
bf069c97
DS		 3370 /*
3371 * If this adapter has a fan, check to see if we had a failure
3372 * before we enabled the interrupt.
3373 */
3374 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3375 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3376 if (esdp & IXGBE_ESDP_SDP1)
3377 DPRINTK(DRV, CRIT,
3378 "Fan has stopped, replace the adapter\n");
3379 }
3380
e8e26350
PW		 3381 /*
3382 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 3383 * arrived before interrupts were enabled but after probe. Such
3384 * devices wouldn't have their type identified yet. We need to
3385 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 3386 * If we're not hot-pluggable SFP+, we just need to configure link
3387 * and bring it up.
3388 */
19343de2
DS		 3389 if (hw->phy.type == ixgbe_phy_unknown) {
3390 err = hw->phy.ops.identify(hw);
3391 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 3392 /*
3393 * Take the device down and schedule the sfp tasklet
3394 * which will unregister_netdev and log it.
3395 */
19343de2 3396 ixgbe_down(adapter);
5da43c1a 3397 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 3398 return err;
3399 }
e8e26350
PW		 3400 }
3401
3402 if (ixgbe_is_sfp(hw)) {
3403 ixgbe_sfp_link_config(adapter);
3404 } else {
3405 err = ixgbe_non_sfp_link_config(hw);
3406 if (err)
3407 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
3408 }
0ecc061d 3409
c4cf55e5
PWJ		 3410 for (i = 0; i < adapter->num_tx_queues; i++)
3411 set_bit(__IXGBE_FDIR_INIT_DONE,
4a0b9ca0 3412 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5 3413
1da100bb
PWJ		 3414 /* enable transmits */
3415 netif_tx_start_all_queues(netdev);
3416
9a799d71
AK		 3417 /* bring the link up in the watchdog, this could race with our first
3418 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3419 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3420 adapter->link_check_timeout = jiffies;
9a799d71 3421 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3422
3423 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3424 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3425 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3426 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3427
9a799d71
AK		 3428 return 0;
3429}
3430
d4f80882
AV		 3431void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3432{
3433 WARN_ON(in_interrupt());
3434 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3435 msleep(1);
3436 ixgbe_down(adapter);
5809a1ae
GR		 3437 /*
3438 * If SR-IOV enabled then wait a bit before bringing the adapter
3439 * back up to give the VFs time to respond to the reset. The
3440 * two second wait is based upon the watchdog timer cycle in
3441 * the VF driver.
3442 */
3443 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3444 msleep(2000);
d4f80882
AV		 3445 ixgbe_up(adapter);
3446 clear_bit(__IXGBE_RESETTING, &adapter->state);
3447}
3448
9a799d71
AK		 3449int ixgbe_up(struct ixgbe_adapter *adapter)
3450{
3451 /* hardware has been reset, we need to reload some things */
3452 ixgbe_configure(adapter);
3453
3454 return ixgbe_up_complete(adapter);
3455}
3456
3457void ixgbe_reset(struct ixgbe_adapter *adapter)
3458{
c44ade9e 3459 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3460 int err;
3461
3462 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3463 switch (err) {
3464 case 0:
3465 case IXGBE_ERR_SFP_NOT_PRESENT:
3466 break;
3467 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3468 dev_err(&adapter->pdev->dev, "master disable timed out\n");
3469 break;
794caeb2
PWJ		 3470 case IXGBE_ERR_EEPROM_VERSION:
3471 /* We are running on a pre-production device, log a warning */
3472 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
3473 "adapter/LOM. Please be aware there may be issues "
3474 "associated with your hardware. If you are "
3475 "experiencing problems please contact your Intel or "
3476 "hardware representative who provided you with this "
3477 "hardware.\n");
3478 break;
da4dd0f7
PWJ		 3479 default:
3480 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
3481 }
9a799d71
AK		 3482
3483 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3484 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3485 IXGBE_RAH_AV);
9a799d71
AK		 3486}
3487
9a799d71
AK		 3488/**
3489 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3490 * @adapter: board private structure
3491 * @rx_ring: ring to free buffers from
3492 **/
3493static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 3494 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3495{
3496 struct pci_dev *pdev = adapter->pdev;
3497 unsigned long size;
3498 unsigned int i;
3499
3500 /* Free all the Rx ring sk_buffs */
3501
3502 for (i = 0; i < rx_ring->count; i++) {
3503 struct ixgbe_rx_buffer *rx_buffer_info;
3504
3505 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3506 if (rx_buffer_info->dma) {
1b507730 3507 dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
b4617240 3508 rx_ring->rx_buf_len,
1b507730 3509 DMA_FROM_DEVICE);
9a799d71
AK		 3510 rx_buffer_info->dma = 0;
3511 }
3512 if (rx_buffer_info->skb) {
f8212f97 3513 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3514 rx_buffer_info->skb = NULL;
f8212f97
AD		 3515 do {
3516 struct sk_buff *this = skb;
e8171aaa 3517 if (IXGBE_RSC_CB(this)->delay_unmap) {
1b507730
NN		 3518 dma_unmap_single(&pdev->dev,
3519 IXGBE_RSC_CB(this)->dma,
43634e82 3520 rx_ring->rx_buf_len,
1b507730 3521 DMA_FROM_DEVICE);
fd3686a8 3522 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 3523 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 3524 }
f8212f97
AD		 3525 skb = skb->prev;
3526 dev_kfree_skb(this);
3527 } while (skb);
9a799d71
AK		 3528 }
3529 if (!rx_buffer_info->page)
3530 continue;
4f57ca6e 3531 if (rx_buffer_info->page_dma) {
1b507730
NN		 3532 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3533 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 3534 rx_buffer_info->page_dma = 0;
3535 }
9a799d71
AK		 3536 put_page(rx_buffer_info->page);
3537 rx_buffer_info->page = NULL;
762f4c57 3538 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3539 }
3540
3541 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3542 memset(rx_ring->rx_buffer_info, 0, size);
3543
3544 /* Zero out the descriptor ring */
3545 memset(rx_ring->desc, 0, rx_ring->size);
3546
3547 rx_ring->next_to_clean = 0;
3548 rx_ring->next_to_use = 0;
3549
9891ca7c
JB		 3550 if (rx_ring->head)
3551 writel(0, adapter->hw.hw_addr + rx_ring->head);
3552 if (rx_ring->tail)
3553 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 3554}
3555
3556/**
3557 * ixgbe_clean_tx_ring - Free Tx Buffers
3558 * @adapter: board private structure
3559 * @tx_ring: ring to be cleaned
3560 **/
3561static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 3562 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3563{
3564 struct ixgbe_tx_buffer *tx_buffer_info;
3565 unsigned long size;
3566 unsigned int i;
3567
3568 /* Free all the Tx ring sk_buffs */
3569
3570 for (i = 0; i < tx_ring->count; i++) {
3571 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3572 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3573 }
3574
3575 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3576 memset(tx_ring->tx_buffer_info, 0, size);
3577
3578 /* Zero out the descriptor ring */
3579 memset(tx_ring->desc, 0, tx_ring->size);
3580
3581 tx_ring->next_to_use = 0;
3582 tx_ring->next_to_clean = 0;
3583
9891ca7c
JB		 3584 if (tx_ring->head)
3585 writel(0, adapter->hw.hw_addr + tx_ring->head);
3586 if (tx_ring->tail)
3587 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 3588}
3589
3590/**
021230d4 3591 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3592 * @adapter: board private structure
3593 **/
021230d4 3594static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3595{
3596 int i;
3597
021230d4 3598 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3599 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
9a799d71
AK		 3600}
3601
3602/**
021230d4 3603 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3604 * @adapter: board private structure
3605 **/
021230d4 3606static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3607{
3608 int i;
3609
021230d4 3610 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3611 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3612}
3613
3614void ixgbe_down(struct ixgbe_adapter *adapter)
3615{
3616 struct net_device *netdev = adapter->netdev;
7f821875 3617 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3618 u32 rxctrl;
7f821875
JB		 3619 u32 txdctl;
3620 int i, j;
9a799d71
AK		 3621
3622 /* signal that we are down to the interrupt handler */
3623 set_bit(__IXGBE_DOWN, &adapter->state);
3624
61fac744
PW		 3625 /* power down the optics */
3626 if (hw->phy.multispeed_fiber)
3627 hw->mac.ops.disable_tx_laser(hw);
3628
767081ad
GR		 3629 /* disable receive for all VFs and wait one second */
3630 if (adapter->num_vfs) {
767081ad
GR		 3631 /* ping all the active vfs to let them know we are going down */
3632 ixgbe_ping_all_vfs(adapter);
581d1aa7 3633
767081ad
GR		 3634 /* Disable all VFTE/VFRE TX/RX */
3635 ixgbe_disable_tx_rx(adapter);
581d1aa7
GR		 3636
3637 /* Mark all the VFs as inactive */
3638 for (i = 0 ; i < adapter->num_vfs; i++)
3639 adapter->vfinfo[i].clear_to_send = 0;
767081ad
GR		 3640 }
3641
9a799d71 3642 /* disable receives */
7f821875
JB		 3643 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3644 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 3645
7f821875 3646 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 3647 msleep(10);
3648
7f821875
JB		 3649 netif_tx_stop_all_queues(netdev);
3650
0a1f87cb
DS		 3651 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3652 del_timer_sync(&adapter->sfp_timer);
9a799d71 3653 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 3654 cancel_work_sync(&adapter->watchdog_task);
9a799d71 3655
c0dfb90e
JF		 3656 netif_carrier_off(netdev);
3657 netif_tx_disable(netdev);
3658
3659 ixgbe_irq_disable(adapter);
3660
3661 ixgbe_napi_disable_all(adapter);
3662
c4cf55e5
PWJ		 3663 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3664 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3665 cancel_work_sync(&adapter->fdir_reinit_task);
3666
7f821875
JB		 3667 /* disable transmits in the hardware now that interrupts are off */
3668 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3669 j = adapter->tx_ring[i]->reg_idx;
7f821875
JB		 3670 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3671 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3672 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3673 }
88512539
PW		 3674 /* Disable the Tx DMA engine on 82599 */
3675 if (hw->mac.type == ixgbe_mac_82599EB)
3676 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3677 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3678 ~IXGBE_DMATXCTL_TE));
7f821875 3679
9a713e7c
PW		 3680 /* clear n-tuple filters that are cached */
3681 ethtool_ntuple_flush(netdev);
3682
6f4a0e45
PL		 3683 if (!pci_channel_offline(adapter->pdev))
3684 ixgbe_reset(adapter);
9a799d71
AK		 3685 ixgbe_clean_all_tx_rings(adapter);
3686 ixgbe_clean_all_rx_rings(adapter);
3687
5dd2d332 3688#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3689 /* since we reset the hardware DCA settings were cleared */
e35ec126 3690 ixgbe_setup_dca(adapter);
96b0e0f6 3691#endif
9a799d71
AK		 3692}
3693
9a799d71 3694/**
021230d4
AV		 3695 * ixgbe_poll - NAPI Rx polling callback
3696 * @napi: structure for representing this polling device
3697 * @budget: how many packets driver is allowed to clean
3698 *
3699 * This function is used for legacy and MSI, NAPI mode
9a799d71 3700 **/
021230d4 3701static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3702{
9a1a69ad
JB		 3703 struct ixgbe_q_vector *q_vector =
3704 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3705 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 3706 int tx_clean_complete, work_done = 0;
9a799d71 3707
5dd2d332 3708#ifdef CONFIG_IXGBE_DCA
bd0362dd 3709 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4a0b9ca0
PW		 3710 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3711 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
bd0362dd
JC		 3712 }
3713#endif
3714
4a0b9ca0
PW		 3715 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3716 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 3717
9a1a69ad 3718 if (!tx_clean_complete)
d2c7ddd6
DM		 3719 work_done = budget;
3720
53e52c72
DM		 3721 /* If budget not fully consumed, exit the polling mode */
3722 if (work_done < budget) {
288379f0 3723 napi_complete(napi);
f7554a2b 3724 if (adapter->rx_itr_setting & 1)
f494e8fa 3725 ixgbe_set_itr(adapter);
d4f80882 3726 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 3727 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 3728 }
9a799d71
AK		 3729 return work_done;
3730}
3731
3732/**
3733 * ixgbe_tx_timeout - Respond to a Tx Hang
3734 * @netdev: network interface device structure
3735 **/
3736static void ixgbe_tx_timeout(struct net_device *netdev)
3737{
3738 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3739
3740 /* Do the reset outside of interrupt context */
3741 schedule_work(&adapter->reset_task);
3742}
3743
3744static void ixgbe_reset_task(struct work_struct *work)
3745{
3746 struct ixgbe_adapter *adapter;
3747 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3748
2f90b865
AD		 3749 /* If we're already down or resetting, just bail */
3750 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3751 test_bit(__IXGBE_RESETTING, &adapter->state))
3752 return;
3753
9a799d71
AK		 3754 adapter->tx_timeout_count++;
3755
dcd79aeb
TI		 3756 ixgbe_dump(adapter);
3757 netdev_err(adapter->netdev, "Reset adapter\n");
d4f80882 3758 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3759}
3760
bc97114d
PWJ		 3761#ifdef CONFIG_IXGBE_DCB
3762static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3763{
bc97114d 3764 bool ret = false;
0cefafad 3765 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3766
0cefafad
JB		 3767 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3768 return ret;
3769
3770 f->mask = 0x7 << 3;
3771 adapter->num_rx_queues = f->indices;
3772 adapter->num_tx_queues = f->indices;
3773 ret = true;
2f90b865 3774
bc97114d
PWJ		 3775 return ret;
3776}
3777#endif
3778
4df10466
JB		 3779/**
3780 * ixgbe_set_rss_queues: Allocate queues for RSS
3781 * @adapter: board private structure to initialize
3782 *
3783 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3784 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3785 *
3786 **/
bc97114d
PWJ		 3787static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3788{
3789 bool ret = false;
0cefafad 3790 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3791
3792 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3793 f->mask = 0xF;
3794 adapter->num_rx_queues = f->indices;
3795 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3796 ret = true;
3797 } else {
bc97114d 3798 ret = false;
b9804972
JB		 3799 }
3800
bc97114d
PWJ		 3801 return ret;
3802}
3803
c4cf55e5
PWJ		 3804/**
3805 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3806 * @adapter: board private structure to initialize
3807 *
3808 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3809 * to the original CPU that initiated the Tx session. This runs in addition
3810 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3811 * Rx load across CPUs using RSS.
3812 *
3813 **/
3814static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3815{
3816 bool ret = false;
3817 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3818
3819 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3820 f_fdir->mask = 0;
3821
3822 /* Flow Director must have RSS enabled */
3823 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3824 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3825 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3826 adapter->num_tx_queues = f_fdir->indices;
3827 adapter->num_rx_queues = f_fdir->indices;
3828 ret = true;
3829 } else {
3830 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3831 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3832 }
3833 return ret;
3834}
3835
0331a832
YZ		 3836#ifdef IXGBE_FCOE
3837/**
3838 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3839 * @adapter: board private structure to initialize
3840 *
3841 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3842 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3843 * rx queues out of the max number of rx queues, instead, it is used as the
3844 * index of the first rx queue used by FCoE.
3845 *
3846 **/
3847static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3848{
3849 bool ret = false;
3850 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3851
3852 f->indices = min((int)num_online_cpus(), f->indices);
3853 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 3854 adapter->num_rx_queues = 1;
3855 adapter->num_tx_queues = 1;
0331a832
YZ		 3856#ifdef CONFIG_IXGBE_DCB
3857 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
d6dbee86 3858 DPRINTK(PROBE, INFO, "FCoE enabled with DCB\n");
0331a832
YZ		 3859 ixgbe_set_dcb_queues(adapter);
3860 }
3861#endif
3862 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
d6dbee86 3863 DPRINTK(PROBE, INFO, "FCoE enabled with RSS\n");
8faa2a78
YZ		 3864 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3865 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3866 ixgbe_set_fdir_queues(adapter);
3867 else
3868 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 3869 }
3870 /* adding FCoE rx rings to the end */
3871 f->mask = adapter->num_rx_queues;
3872 adapter->num_rx_queues += f->indices;
8de8b2e6 3873 adapter->num_tx_queues += f->indices;
0331a832
YZ		 3874
3875 ret = true;
3876 }
3877
3878 return ret;
3879}
3880
3881#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 3882/**
3883 * ixgbe_set_sriov_queues: Allocate queues for IOV use
3884 * @adapter: board private structure to initialize
3885 *
3886 * IOV doesn't actually use anything, so just NAK the
3887 * request for now and let the other queue routines
3888 * figure out what to do.
3889 */
3890static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
3891{
3892 return false;
3893}
3894
4df10466
JB		 3895/*
3896 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3897 * @adapter: board private structure to initialize
3898 *
3899 * This is the top level queue allocation routine. The order here is very
3900 * important, starting with the "most" number of features turned on at once,
3901 * and ending with the smallest set of features. This way large combinations
3902 * can be allocated if they're turned on, and smaller combinations are the
3903 * fallthrough conditions.
3904 *
3905 **/
bc97114d
PWJ		 3906static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3907{
1cdd1ec8
GR		 3908 /* Start with base case */
3909 adapter->num_rx_queues = 1;
3910 adapter->num_tx_queues = 1;
3911 adapter->num_rx_pools = adapter->num_rx_queues;
3912 adapter->num_rx_queues_per_pool = 1;
3913
3914 if (ixgbe_set_sriov_queues(adapter))
3915 return;
3916
0331a832
YZ		 3917#ifdef IXGBE_FCOE
3918 if (ixgbe_set_fcoe_queues(adapter))
3919 goto done;
3920
3921#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3922#ifdef CONFIG_IXGBE_DCB
3923 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 3924 goto done;
bc97114d
PWJ		 3925
3926#endif
c4cf55e5
PWJ		 3927 if (ixgbe_set_fdir_queues(adapter))
3928 goto done;
3929
bc97114d 3930 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 3931 goto done;
3932
3933 /* fallback to base case */
3934 adapter->num_rx_queues = 1;
3935 adapter->num_tx_queues = 1;
3936
3937done:
3938 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3939 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 3940}
3941
021230d4 3942static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 3943 int vectors)
021230d4
AV		 3944{
3945 int err, vector_threshold;
3946
3947 /* We'll want at least 3 (vector_threshold):
3948 * 1) TxQ[0] Cleanup
3949 * 2) RxQ[0] Cleanup
3950 * 3) Other (Link Status Change, etc.)
3951 * 4) TCP Timer (optional)
3952 */
3953 vector_threshold = MIN_MSIX_COUNT;
3954
3955 /* The more we get, the more we will assign to Tx/Rx Cleanup
3956 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3957 * Right now, we simply care about how many we'll get; we'll
3958 * set them up later while requesting irq's.
3959 */
3960 while (vectors >= vector_threshold) {
3961 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 3962 vectors);
021230d4
AV		 3963 if (!err) /* Success in acquiring all requested vectors. */
3964 break;
3965 else if (err < 0)
3966 vectors = 0; /* Nasty failure, quit now */
3967 else /* err == number of vectors we should try again with */
3968 vectors = err;
3969 }
3970
3971 if (vectors < vector_threshold) {
3972 /* Can't allocate enough MSI-X interrupts? Oh well.
3973 * This just means we'll go with either a single MSI
3974 * vector or fall back to legacy interrupts.
3975 */
3976 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3977 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3978 kfree(adapter->msix_entries);
3979 adapter->msix_entries = NULL;
021230d4
AV		 3980 } else {
3981 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 3982 /*
3983 * Adjust for only the vectors we'll use, which is minimum
3984 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3985 * vectors we were allocated.
3986 */
3987 adapter->num_msix_vectors = min(vectors,
3988 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 3989 }
3990}
3991
021230d4 3992/**
bc97114d 3993 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 3994 * @adapter: board private structure to initialize
3995 *
bc97114d
PWJ		 3996 * Cache the descriptor ring offsets for RSS to the assigned rings.
3997 *
021230d4 3998 **/
bc97114d 3999static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4000{
bc97114d
PWJ		 4001 int i;
4002 bool ret = false;
4003
4004 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4005 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4006 adapter->rx_ring[i]->reg_idx = i;
bc97114d 4007 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4008 adapter->tx_ring[i]->reg_idx = i;
bc97114d
PWJ		 4009 ret = true;
4010 } else {
4011 ret = false;
4012 }
4013
4014 return ret;
4015}
4016
4017#ifdef CONFIG_IXGBE_DCB
4018/**
4019 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4020 * @adapter: board private structure to initialize
4021 *
4022 * Cache the descriptor ring offsets for DCB to the assigned rings.
4023 *
4024 **/
4025static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4026{
4027 int i;
4028 bool ret = false;
4029 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4030
4031 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4032 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 4033 /* the number of queues is assumed to be symmetric */
4034 for (i = 0; i < dcb_i; i++) {
4a0b9ca0
PW		 4035 adapter->rx_ring[i]->reg_idx = i << 3;
4036 adapter->tx_ring[i]->reg_idx = i << 2;
2f90b865 4037 }
bc97114d 4038 ret = true;
e8e26350 4039 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 4040 if (dcb_i == 8) {
4041 /*
4042 * Tx TC0 starts at: descriptor queue 0
4043 * Tx TC1 starts at: descriptor queue 32
4044 * Tx TC2 starts at: descriptor queue 64
4045 * Tx TC3 starts at: descriptor queue 80
4046 * Tx TC4 starts at: descriptor queue 96
4047 * Tx TC5 starts at: descriptor queue 104
4048 * Tx TC6 starts at: descriptor queue 112
4049 * Tx TC7 starts at: descriptor queue 120
4050 *
4051 * Rx TC0-TC7 are offset by 16 queues each
4052 */
4053 for (i = 0; i < 3; i++) {
4a0b9ca0
PW		 4054 adapter->tx_ring[i]->reg_idx = i << 5;
4055 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4056 }
4057 for ( ; i < 5; i++) {
4a0b9ca0 4058 adapter->tx_ring[i]->reg_idx =
f92ef202 4059 ((i + 2) << 4);
4a0b9ca0 4060 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4061 }
4062 for ( ; i < dcb_i; i++) {
4a0b9ca0 4063 adapter->tx_ring[i]->reg_idx =
f92ef202 4064 ((i + 8) << 3);
4a0b9ca0 4065 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4066 }
4067
4068 ret = true;
4069 } else if (dcb_i == 4) {
4070 /*
4071 * Tx TC0 starts at: descriptor queue 0
4072 * Tx TC1 starts at: descriptor queue 64
4073 * Tx TC2 starts at: descriptor queue 96
4074 * Tx TC3 starts at: descriptor queue 112
4075 *
4076 * Rx TC0-TC3 are offset by 32 queues each
4077 */
4a0b9ca0
PW		 4078 adapter->tx_ring[0]->reg_idx = 0;
4079 adapter->tx_ring[1]->reg_idx = 64;
4080 adapter->tx_ring[2]->reg_idx = 96;
4081 adapter->tx_ring[3]->reg_idx = 112;
f92ef202 4082 for (i = 0 ; i < dcb_i; i++)
4a0b9ca0 4083 adapter->rx_ring[i]->reg_idx = i << 5;
f92ef202
PW		 4084
4085 ret = true;
4086 } else {
4087 ret = false;
e8e26350 4088 }
bc97114d
PWJ		 4089 } else {
4090 ret = false;
021230d4 4091 }
bc97114d
PWJ		 4092 } else {
4093 ret = false;
021230d4 4094 }
bc97114d
PWJ		 4095
4096 return ret;
4097}
4098#endif
4099
c4cf55e5
PWJ		 4100/**
4101 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4102 * @adapter: board private structure to initialize
4103 *
4104 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4105 *
4106 **/
4107static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4108{
4109 int i;
4110 bool ret = false;
4111
4112 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4113 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4114 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4115 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4116 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4117 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4118 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4119 ret = true;
4120 }
4121
4122 return ret;
4123}
4124
0331a832
YZ		 4125#ifdef IXGBE_FCOE
4126/**
4127 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4128 * @adapter: board private structure to initialize
4129 *
4130 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4131 *
4132 */
4133static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4134{
8de8b2e6 4135 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 4136 bool ret = false;
4137 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4138
4139 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4140#ifdef CONFIG_IXGBE_DCB
4141 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 4142 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4143
0331a832 4144 ixgbe_cache_ring_dcb(adapter);
8de8b2e6 4145 /* find out queues in TC for FCoE */
4a0b9ca0
PW		 4146 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4147 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
8de8b2e6
YZ		 4148 /*
4149 * In 82599, the number of Tx queues for each traffic
4150 * class for both 8-TC and 4-TC modes are:
4151 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4152 * 8 TCs: 32 32 16 16 8 8 8 8
4153 * 4 TCs: 64 64 32 32
4154 * We have max 8 queues for FCoE, where 8 the is
4155 * FCoE redirection table size. If TC for FCoE is
4156 * less than or equal to TC3, we have enough queues
4157 * to add max of 8 queues for FCoE, so we start FCoE
4158 * tx descriptor from the next one, i.e., reg_idx + 1.
4159 * If TC for FCoE is above TC3, implying 8 TC mode,
4160 * and we need 8 for FCoE, we have to take all queues
4161 * in that traffic class for FCoE.
4162 */
4163 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4164 fcoe_tx_i--;
0331a832
YZ		 4165 }
4166#endif /* CONFIG_IXGBE_DCB */
4167 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 4168 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4169 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4170 ixgbe_cache_ring_fdir(adapter);
4171 else
4172 ixgbe_cache_ring_rss(adapter);
4173
8de8b2e6
YZ		 4174 fcoe_rx_i = f->mask;
4175 fcoe_tx_i = f->mask;
4176 }
4177 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4a0b9ca0
PW		 4178 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4179 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
0331a832 4180 }
0331a832
YZ		 4181 ret = true;
4182 }
4183 return ret;
4184}
4185
4186#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4187/**
4188 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4189 * @adapter: board private structure to initialize
4190 *
4191 * SR-IOV doesn't use any descriptor rings but changes the default if
4192 * no other mapping is used.
4193 *
4194 */
4195static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4196{
4a0b9ca0
PW		 4197 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4198 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4199 if (adapter->num_vfs)
4200 return true;
4201 else
4202 return false;
4203}
4204
bc97114d
PWJ		 4205/**
4206 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4207 * @adapter: board private structure to initialize
4208 *
4209 * Once we know the feature-set enabled for the device, we'll cache
4210 * the register offset the descriptor ring is assigned to.
4211 *
4212 * Note, the order the various feature calls is important. It must start with
4213 * the "most" features enabled at the same time, then trickle down to the
4214 * least amount of features turned on at once.
4215 **/
4216static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4217{
4218 /* start with default case */
4a0b9ca0
PW		 4219 adapter->rx_ring[0]->reg_idx = 0;
4220 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4221
1cdd1ec8
GR		 4222 if (ixgbe_cache_ring_sriov(adapter))
4223 return;
4224
0331a832
YZ		 4225#ifdef IXGBE_FCOE
4226 if (ixgbe_cache_ring_fcoe(adapter))
4227 return;
4228
4229#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4230#ifdef CONFIG_IXGBE_DCB
4231 if (ixgbe_cache_ring_dcb(adapter))
4232 return;
4233
4234#endif
c4cf55e5
PWJ		 4235 if (ixgbe_cache_ring_fdir(adapter))
4236 return;
4237
bc97114d
PWJ		 4238 if (ixgbe_cache_ring_rss(adapter))
4239 return;
021230d4
AV		 4240}
4241
9a799d71
AK		 4242/**
4243 * ixgbe_alloc_queues - Allocate memory for all rings
4244 * @adapter: board private structure to initialize
4245 *
4246 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4247 * number of queues at compile-time. The polling_netdev array is
4248 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4249 **/
2f90b865 4250static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 4251{
4252 int i;
4a0b9ca0 4253 int orig_node = adapter->node;
9a799d71 4254
021230d4 4255 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 4256 struct ixgbe_ring *ring = adapter->tx_ring[i];
4257 if (orig_node == -1) {
4258 int cur_node = next_online_node(adapter->node);
4259 if (cur_node == MAX_NUMNODES)
4260 cur_node = first_online_node;
4261 adapter->node = cur_node;
4262 }
4263 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4264 adapter->node);
4265 if (!ring)
4266 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4267 if (!ring)
4268 goto err_tx_ring_allocation;
4269 ring->count = adapter->tx_ring_count;
4270 ring->queue_index = i;
4271 ring->numa_node = adapter->node;
4272
4273 adapter->tx_ring[i] = ring;
021230d4 4274 }
b9804972 4275
4a0b9ca0
PW		 4276 /* Restore the adapter's original node */
4277 adapter->node = orig_node;
4278
9a799d71 4279 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 4280 struct ixgbe_ring *ring = adapter->rx_ring[i];
4281 if (orig_node == -1) {
4282 int cur_node = next_online_node(adapter->node);
4283 if (cur_node == MAX_NUMNODES)
4284 cur_node = first_online_node;
4285 adapter->node = cur_node;
4286 }
4287 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4288 adapter->node);
4289 if (!ring)
4290 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4291 if (!ring)
4292 goto err_rx_ring_allocation;
4293 ring->count = adapter->rx_ring_count;
4294 ring->queue_index = i;
4295 ring->numa_node = adapter->node;
4296
4297 adapter->rx_ring[i] = ring;
021230d4
AV		 4298 }
4299
4a0b9ca0
PW		 4300 /* Restore the adapter's original node */
4301 adapter->node = orig_node;
4302
021230d4
AV		 4303 ixgbe_cache_ring_register(adapter);
4304
4305 return 0;
4306
4307err_rx_ring_allocation:
4a0b9ca0
PW		 4308 for (i = 0; i < adapter->num_tx_queues; i++)
4309 kfree(adapter->tx_ring[i]);
021230d4
AV		 4310err_tx_ring_allocation:
4311 return -ENOMEM;
4312}
4313
4314/**
4315 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4316 * @adapter: board private structure to initialize
4317 *
4318 * Attempt to configure the interrupts using the best available
4319 * capabilities of the hardware and the kernel.
4320 **/
feea6a57 4321static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4322{
8be0e467 4323 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4324 int err = 0;
4325 int vector, v_budget;
4326
4327 /*
4328 * It's easy to be greedy for MSI-X vectors, but it really
4329 * doesn't do us much good if we have a lot more vectors
4330 * than CPU's. So let's be conservative and only ask for
342bde1b 4331 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4332 */
4333 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
342bde1b 4334 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4335
4336 /*
4337 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4338 * hw.mac->max_msix_vectors vectors. With features
4339 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4340 * descriptor queues supported by our device. Thus, we cap it off in
4341 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4342 */
8be0e467 4343 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4344
4345 /* A failure in MSI-X entry allocation isn't fatal, but it does
4346 * mean we disable MSI-X capabilities of the adapter. */
4347 adapter->msix_entries = kcalloc(v_budget,
b4617240 4348 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4349 if (adapter->msix_entries) {
4350 for (vector = 0; vector < v_budget; vector++)
4351 adapter->msix_entries[vector].entry = vector;
021230d4 4352
7a921c93 4353 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4354
7a921c93
AD		 4355 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4356 goto out;
4357 }
26d27844 4358
7a921c93
AD		 4359 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4360 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 4361 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4362 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4363 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4364 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4365 ixgbe_disable_sriov(adapter);
4366
7a921c93 4367 ixgbe_set_num_queues(adapter);
021230d4 4368
021230d4
AV		 4369 err = pci_enable_msi(adapter->pdev);
4370 if (!err) {
4371 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4372 } else {
4373 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 4374 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4375 /* reset err */
4376 err = 0;
4377 }
4378
4379out:
021230d4
AV		 4380 return err;
4381}
4382
7a921c93
AD		 4383/**
4384 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4385 * @adapter: board private structure to initialize
4386 *
4387 * We allocate one q_vector per queue interrupt. If allocation fails we
4388 * return -ENOMEM.
4389 **/
4390static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4391{
4392 int q_idx, num_q_vectors;
4393 struct ixgbe_q_vector *q_vector;
4394 int napi_vectors;
4395 int (*poll)(struct napi_struct *, int);
4396
4397 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4398 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4399 napi_vectors = adapter->num_rx_queues;
91281fd3 4400 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4401 } else {
4402 num_q_vectors = 1;
4403 napi_vectors = 1;
4404 poll = &ixgbe_poll;
4405 }
4406
4407 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2
JB		 4408 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4409 GFP_KERNEL, adapter->node);
4410 if (!q_vector)
4411 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4412 GFP_KERNEL);
7a921c93
AD		 4413 if (!q_vector)
4414 goto err_out;
4415 q_vector->adapter = adapter;
f7554a2b
NS		 4416 if (q_vector->txr_count && !q_vector->rxr_count)
4417 q_vector->eitr = adapter->tx_eitr_param;
4418 else
4419 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4420 q_vector->v_idx = q_idx;
91281fd3 4421 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4422 adapter->q_vector[q_idx] = q_vector;
4423 }
4424
4425 return 0;
4426
4427err_out:
4428 while (q_idx) {
4429 q_idx--;
4430 q_vector = adapter->q_vector[q_idx];
4431 netif_napi_del(&q_vector->napi);
4432 kfree(q_vector);
4433 adapter->q_vector[q_idx] = NULL;
4434 }
4435 return -ENOMEM;
4436}
4437
4438/**
4439 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4440 * @adapter: board private structure to initialize
4441 *
4442 * This function frees the memory allocated to the q_vectors. In addition if
4443 * NAPI is enabled it will delete any references to the NAPI struct prior
4444 * to freeing the q_vector.
4445 **/
4446static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4447{
4448 int q_idx, num_q_vectors;
7a921c93 4449
91281fd3 4450 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4451 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4452 else
7a921c93 4453 num_q_vectors = 1;
7a921c93
AD		 4454
4455 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4456 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4457 adapter->q_vector[q_idx] = NULL;
91281fd3 4458 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4459 kfree(q_vector);
4460 }
4461}
4462
7b25cdba 4463static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4464{
4465 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4466 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4467 pci_disable_msix(adapter->pdev);
4468 kfree(adapter->msix_entries);
4469 adapter->msix_entries = NULL;
4470 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4471 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4472 pci_disable_msi(adapter->pdev);
4473 }
021230d4
AV		 4474}
4475
4476/**
4477 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4478 * @adapter: board private structure to initialize
4479 *
4480 * We determine which interrupt scheme to use based on...
4481 * - Kernel support (MSI, MSI-X)
4482 * - which can be user-defined (via MODULE_PARAM)
4483 * - Hardware queue count (num_*_queues)
4484 * - defined by miscellaneous hardware support/features (RSS, etc.)
4485 **/
2f90b865 4486int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4487{
4488 int err;
4489
4490 /* Number of supported queues */
4491 ixgbe_set_num_queues(adapter);
4492
021230d4
AV		 4493 err = ixgbe_set_interrupt_capability(adapter);
4494 if (err) {
4495 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
4496 goto err_set_interrupt;
9a799d71
AK		 4497 }
4498
7a921c93
AD		 4499 err = ixgbe_alloc_q_vectors(adapter);
4500 if (err) {
4501 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
4502 "vectors\n");
4503 goto err_alloc_q_vectors;
4504 }
4505
4506 err = ixgbe_alloc_queues(adapter);
4507 if (err) {
4508 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
4509 goto err_alloc_queues;
4510 }
4511
021230d4 4512 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 4513 "Tx Queue count = %u\n",
4514 (adapter->num_rx_queues > 1) ? "Enabled" :
4515 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4516
4517 set_bit(__IXGBE_DOWN, &adapter->state);
4518
9a799d71 4519 return 0;
021230d4 4520
7a921c93
AD		 4521err_alloc_queues:
4522 ixgbe_free_q_vectors(adapter);
4523err_alloc_q_vectors:
4524 ixgbe_reset_interrupt_capability(adapter);
021230d4 4525err_set_interrupt:
7a921c93
AD		 4526 return err;
4527}
4528
4529/**
4530 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4531 * @adapter: board private structure to clear interrupt scheme on
4532 *
4533 * We go through and clear interrupt specific resources and reset the structure
4534 * to pre-load conditions
4535 **/
4536void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4537{
4a0b9ca0
PW		 4538 int i;
4539
4540 for (i = 0; i < adapter->num_tx_queues; i++) {
4541 kfree(adapter->tx_ring[i]);
4542 adapter->tx_ring[i] = NULL;
4543 }
4544 for (i = 0; i < adapter->num_rx_queues; i++) {
4545 kfree(adapter->rx_ring[i]);
4546 adapter->rx_ring[i] = NULL;
4547 }
7a921c93
AD		 4548
4549 ixgbe_free_q_vectors(adapter);
4550 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4551}
4552
c4900be0
DS		 4553/**
4554 * ixgbe_sfp_timer - worker thread to find a missing module
4555 * @data: pointer to our adapter struct
4556 **/
4557static void ixgbe_sfp_timer(unsigned long data)
4558{
4559 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4560
4df10466
JB		 4561 /*
4562 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 4563 * delays that sfp+ detection requires
4564 */
4565 schedule_work(&adapter->sfp_task);
4566}
4567
4568/**
4569 * ixgbe_sfp_task - worker thread to find a missing module
4570 * @work: pointer to work_struct containing our data
4571 **/
4572static void ixgbe_sfp_task(struct work_struct *work)
4573{
4574 struct ixgbe_adapter *adapter = container_of(work,
4575 struct ixgbe_adapter,
4576 sfp_task);
4577 struct ixgbe_hw *hw = &adapter->hw;
4578
4579 if ((hw->phy.type == ixgbe_phy_nl) &&
4580 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4581 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4582 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 4583 goto reschedule;
4584 ret = hw->phy.ops.reset(hw);
4585 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 4586 dev_err(&adapter->pdev->dev, "failed to initialize "
4587 "because an unsupported SFP+ module type "
4588 "was detected.\n"
4589 "Reload the driver after installing a "
4590 "supported module.\n");
c4900be0
DS		 4591 unregister_netdev(adapter->netdev);
4592 } else {
4593 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
4594 hw->phy.sfp_type);
4595 }
4596 /* don't need this routine any more */
4597 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4598 }
4599 return;
4600reschedule:
4601 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4602 mod_timer(&adapter->sfp_timer,
4603 round_jiffies(jiffies + (2 * HZ)));
4604}
4605
9a799d71
AK		 4606/**
4607 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4608 * @adapter: board private structure to initialize
4609 *
4610 * ixgbe_sw_init initializes the Adapter private data structure.
4611 * Fields are initialized based on PCI device information and
4612 * OS network device settings (MTU size).
4613 **/
4614static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4615{
4616 struct ixgbe_hw *hw = &adapter->hw;
4617 struct pci_dev *pdev = adapter->pdev;
9a713e7c 4618 struct net_device *dev = adapter->netdev;
021230d4 4619 unsigned int rss;
7a6b6f51 4620#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4621 int j;
4622 struct tc_configuration *tc;
4623#endif
021230d4 4624
c44ade9e
JB		 4625 /* PCI config space info */
4626
4627 hw->vendor_id = pdev->vendor;
4628 hw->device_id = pdev->device;
4629 hw->revision_id = pdev->revision;
4630 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4631 hw->subsystem_device_id = pdev->subsystem_device;
4632
021230d4
AV		 4633 /* Set capability flags */
4634 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4635 adapter->ring_feature[RING_F_RSS].indices = rss;
4636 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 4637 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 4638 if (hw->mac.type == ixgbe_mac_82598EB) {
4639 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4640 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4641 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 4642 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 4643 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4644 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4645 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
9a713e7c
PW		 4646 if (dev->features & NETIF_F_NTUPLE) {
4647 /* Flow Director perfect filter enabled */
4648 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4649 adapter->atr_sample_rate = 0;
4650 spin_lock_init(&adapter->fdir_perfect_lock);
4651 } else {
4652 /* Flow Director hash filters enabled */
4653 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4654 adapter->atr_sample_rate = 20;
4655 }
c4cf55e5
PWJ		 4656 adapter->ring_feature[RING_F_FDIR].indices =
4657 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 4658 adapter->fdir_pballoc = 0;
eacd73f7 4659#ifdef IXGBE_FCOE
0d551589
YZ		 4660 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4661 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4662 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4663#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 4664 /* Default traffic class to use for FCoE */
4665 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
61a0f421 4666#endif
eacd73f7 4667#endif /* IXGBE_FCOE */
f8212f97 4668 }
2f90b865 4669
7a6b6f51 4670#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4671 /* Configure DCB traffic classes */
4672 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4673 tc = &adapter->dcb_cfg.tc_config[j];
4674 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4675 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4676 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4677 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4678 tc->dcb_pfc = pfc_disabled;
4679 }
4680 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4681 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4682 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 4683 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 4684 adapter->dcb_cfg.round_robin_enable = false;
4685 adapter->dcb_set_bitmap = 0x00;
4686 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4687 adapter->ring_feature[RING_F_DCB].indices);
4688
4689#endif
9a799d71
AK		 4690
4691 /* default flow control settings */
cd7664f6 4692 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4693 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 4694#ifdef CONFIG_DCB
4695 adapter->last_lfc_mode = hw->fc.current_mode;
4696#endif
2b9ade93
JB		 4697 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4698 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4699 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4700 hw->fc.send_xon = true;
71fd570b 4701 hw->fc.disable_fc_autoneg = false;
9a799d71 4702
30efa5a3 4703 /* enable itr by default in dynamic mode */
f7554a2b
NS		 4704 adapter->rx_itr_setting = 1;
4705 adapter->rx_eitr_param = 20000;
4706 adapter->tx_itr_setting = 1;
4707 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 4708
4709 /* set defaults for eitr in MegaBytes */
4710 adapter->eitr_low = 10;
4711 adapter->eitr_high = 20;
4712
4713 /* set default ring sizes */
4714 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4715 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4716
9a799d71 4717 /* initialize eeprom parameters */
c44ade9e 4718 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 4719 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4720 return -EIO;
4721 }
4722
021230d4 4723 /* enable rx csum by default */
9a799d71
AK		 4724 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4725
1a6c14a2
JB		 4726 /* get assigned NUMA node */
4727 adapter->node = dev_to_node(&pdev->dev);
4728
9a799d71
AK		 4729 set_bit(__IXGBE_DOWN, &adapter->state);
4730
4731 return 0;
4732}
4733
4734/**
4735 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4736 * @adapter: board private structure
3a581073 4737 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4738 *
4739 * Return 0 on success, negative on failure
4740 **/
4741int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 4742 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4743{
4744 struct pci_dev *pdev = adapter->pdev;
4745 int size;
4746
3a581073 4747 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4a0b9ca0 4748 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
1a6c14a2
JB		 4749 if (!tx_ring->tx_buffer_info)
4750 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 4751 if (!tx_ring->tx_buffer_info)
4752 goto err;
3a581073 4753 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 4754
4755 /* round up to nearest 4K */
12207e49 4756 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4757 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4758
1b507730
NN		 4759 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4760 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4761 if (!tx_ring->desc)
4762 goto err;
9a799d71 4763
3a581073
JB		 4764 tx_ring->next_to_use = 0;
4765 tx_ring->next_to_clean = 0;
4766 tx_ring->work_limit = tx_ring->count;
9a799d71 4767 return 0;
e01c31a5
JB		 4768
4769err:
4770 vfree(tx_ring->tx_buffer_info);
4771 tx_ring->tx_buffer_info = NULL;
4772 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4773 "descriptor ring\n");
4774 return -ENOMEM;
9a799d71
AK		 4775}
4776
69888674
AD		 4777/**
4778 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4779 * @adapter: board private structure
4780 *
4781 * If this function returns with an error, then it's possible one or
4782 * more of the rings is populated (while the rest are not). It is the
4783 * callers duty to clean those orphaned rings.
4784 *
4785 * Return 0 on success, negative on failure
4786 **/
4787static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4788{
4789 int i, err = 0;
4790
4791 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 4792 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
69888674
AD		 4793 if (!err)
4794 continue;
4795 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4796 break;
4797 }
4798
4799 return err;
4800}
4801
9a799d71
AK		 4802/**
4803 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4804 * @adapter: board private structure
3a581073 4805 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4806 *
4807 * Returns 0 on success, negative on failure
4808 **/
4809int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 4810 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4811{
4812 struct pci_dev *pdev = adapter->pdev;
021230d4 4813 int size;
9a799d71 4814
3a581073 4815 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
1a6c14a2
JB		 4816 rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4817 if (!rx_ring->rx_buffer_info)
4818 rx_ring->rx_buffer_info = vmalloc(size);
3a581073 4819 if (!rx_ring->rx_buffer_info) {
9a799d71 4820 DPRINTK(PROBE, ERR,
b4617240 4821 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 4822 goto alloc_failed;
9a799d71 4823 }
3a581073 4824 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 4825
9a799d71 4826 /* Round up to nearest 4K */
3a581073
JB		 4827 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4828 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4829
1b507730
NN		 4830 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
4831 &rx_ring->dma, GFP_KERNEL);
9a799d71 4832
3a581073 4833 if (!rx_ring->desc) {
9a799d71 4834 DPRINTK(PROBE, ERR,
b4617240 4835 "Memory allocation failed for the rx desc ring\n");
3a581073 4836 vfree(rx_ring->rx_buffer_info);
177db6ff 4837 goto alloc_failed;
9a799d71
AK		 4838 }
4839
3a581073
JB		 4840 rx_ring->next_to_clean = 0;
4841 rx_ring->next_to_use = 0;
9a799d71
AK		 4842
4843 return 0;
177db6ff
MC		 4844
4845alloc_failed:
177db6ff 4846 return -ENOMEM;
9a799d71
AK		 4847}
4848
69888674
AD		 4849/**
4850 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4851 * @adapter: board private structure
4852 *
4853 * If this function returns with an error, then it's possible one or
4854 * more of the rings is populated (while the rest are not). It is the
4855 * callers duty to clean those orphaned rings.
4856 *
4857 * Return 0 on success, negative on failure
4858 **/
4859
4860static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4861{
4862 int i, err = 0;
4863
4864 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 4865 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
69888674
AD		 4866 if (!err)
4867 continue;
4868 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4869 break;
4870 }
4871
4872 return err;
4873}
4874
9a799d71
AK		 4875/**
4876 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4877 * @adapter: board private structure
4878 * @tx_ring: Tx descriptor ring for a specific queue
4879 *
4880 * Free all transmit software resources
4881 **/
c431f97e
JB		 4882void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4883 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4884{
4885 struct pci_dev *pdev = adapter->pdev;
4886
4887 ixgbe_clean_tx_ring(adapter, tx_ring);
4888
4889 vfree(tx_ring->tx_buffer_info);
4890 tx_ring->tx_buffer_info = NULL;
4891
1b507730
NN		 4892 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
4893 tx_ring->dma);
9a799d71
AK		 4894
4895 tx_ring->desc = NULL;
4896}
4897
4898/**
4899 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4900 * @adapter: board private structure
4901 *
4902 * Free all transmit software resources
4903 **/
4904static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4905{
4906 int i;
4907
4908 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0
PW		 4909 if (adapter->tx_ring[i]->desc)
4910 ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
9a799d71
AK		 4911}
4912
4913/**
b4617240 4914 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4915 * @adapter: board private structure
4916 * @rx_ring: ring to clean the resources from
4917 *
4918 * Free all receive software resources
4919 **/
c431f97e
JB		 4920void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4921 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4922{
4923 struct pci_dev *pdev = adapter->pdev;
4924
4925 ixgbe_clean_rx_ring(adapter, rx_ring);
4926
4927 vfree(rx_ring->rx_buffer_info);
4928 rx_ring->rx_buffer_info = NULL;
4929
1b507730
NN		 4930 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
4931 rx_ring->dma);
9a799d71
AK		 4932
4933 rx_ring->desc = NULL;
4934}
4935
4936/**
4937 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4938 * @adapter: board private structure
4939 *
4940 * Free all receive software resources
4941 **/
4942static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4943{
4944 int i;
4945
4946 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 4947 if (adapter->rx_ring[i]->desc)
4948 ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
9a799d71
AK		 4949}
4950
9a799d71
AK		 4951/**
4952 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4953 * @netdev: network interface device structure
4954 * @new_mtu: new value for maximum frame size
4955 *
4956 * Returns 0 on success, negative on failure
4957 **/
4958static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4959{
4960 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4961 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4962
42c783c5
JB		 4963 /* MTU < 68 is an error and causes problems on some kernels */
4964 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 4965 return -EINVAL;
4966
021230d4 4967 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 4968 netdev->mtu, new_mtu);
021230d4 4969 /* must set new MTU before calling down or up */
9a799d71
AK		 4970 netdev->mtu = new_mtu;
4971
d4f80882
AV		 4972 if (netif_running(netdev))
4973 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4974
4975 return 0;
4976}
4977
4978/**
4979 * ixgbe_open - Called when a network interface is made active
4980 * @netdev: network interface device structure
4981 *
4982 * Returns 0 on success, negative value on failure
4983 *
4984 * The open entry point is called when a network interface is made
4985 * active by the system (IFF_UP). At this point all resources needed
4986 * for transmit and receive operations are allocated, the interrupt
4987 * handler is registered with the OS, the watchdog timer is started,
4988 * and the stack is notified that the interface is ready.
4989 **/
4990static int ixgbe_open(struct net_device *netdev)
4991{
4992 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4993 int err;
4bebfaa5
AK		 4994
4995 /* disallow open during test */
4996 if (test_bit(__IXGBE_TESTING, &adapter->state))
4997 return -EBUSY;
9a799d71 4998
54386467
JB		 4999 netif_carrier_off(netdev);
5000
9a799d71
AK		 5001 /* allocate transmit descriptors */
5002 err = ixgbe_setup_all_tx_resources(adapter);
5003 if (err)
5004 goto err_setup_tx;
5005
9a799d71
AK		 5006 /* allocate receive descriptors */
5007 err = ixgbe_setup_all_rx_resources(adapter);
5008 if (err)
5009 goto err_setup_rx;
5010
5011 ixgbe_configure(adapter);
5012
021230d4 5013 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5014 if (err)
5015 goto err_req_irq;
5016
9a799d71
AK		 5017 err = ixgbe_up_complete(adapter);
5018 if (err)
5019 goto err_up;
5020
d55b53ff
JK		 5021 netif_tx_start_all_queues(netdev);
5022
9a799d71
AK		 5023 return 0;
5024
5025err_up:
5eba3699 5026 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5027 ixgbe_free_irq(adapter);
5028err_req_irq:
9a799d71 5029err_setup_rx:
a20a1199 5030 ixgbe_free_all_rx_resources(adapter);
9a799d71 5031err_setup_tx:
a20a1199 5032 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5033 ixgbe_reset(adapter);
5034
5035 return err;
5036}
5037
5038/**
5039 * ixgbe_close - Disables a network interface
5040 * @netdev: network interface device structure
5041 *
5042 * Returns 0, this is not allowed to fail
5043 *
5044 * The close entry point is called when an interface is de-activated
5045 * by the OS. The hardware is still under the drivers control, but
5046 * needs to be disabled. A global MAC reset is issued to stop the
5047 * hardware, and all transmit and receive resources are freed.
5048 **/
5049static int ixgbe_close(struct net_device *netdev)
5050{
5051 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5052
5053 ixgbe_down(adapter);
5054 ixgbe_free_irq(adapter);
5055
5056 ixgbe_free_all_tx_resources(adapter);
5057 ixgbe_free_all_rx_resources(adapter);
5058
5eba3699 5059 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5060
5061 return 0;
5062}
5063
b3c8b4ba
AD		 5064#ifdef CONFIG_PM
5065static int ixgbe_resume(struct pci_dev *pdev)
5066{
5067 struct net_device *netdev = pci_get_drvdata(pdev);
5068 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5069 u32 err;
5070
5071 pci_set_power_state(pdev, PCI_D0);
5072 pci_restore_state(pdev);
656ab817
DS		 5073 /*
5074 * pci_restore_state clears dev->state_saved so call
5075 * pci_save_state to restore it.
5076 */
5077 pci_save_state(pdev);
9ce77666 5078
5079 err = pci_enable_device_mem(pdev);
b3c8b4ba 5080 if (err) {
69888674 5081 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 5082 "suspend\n");
5083 return err;
5084 }
5085 pci_set_master(pdev);
5086
dd4d8ca6 5087 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5088
5089 err = ixgbe_init_interrupt_scheme(adapter);
5090 if (err) {
5091 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
5092 "device\n");
5093 return err;
5094 }
5095
b3c8b4ba
AD		 5096 ixgbe_reset(adapter);
5097
495dce12
WJP		 5098 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5099
b3c8b4ba
AD		 5100 if (netif_running(netdev)) {
5101 err = ixgbe_open(adapter->netdev);
5102 if (err)
5103 return err;
5104 }
5105
5106 netif_device_attach(netdev);
5107
5108 return 0;
5109}
b3c8b4ba 5110#endif /* CONFIG_PM */
9d8d05ae
RW		 5111
5112static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 5113{
5114 struct net_device *netdev = pci_get_drvdata(pdev);
5115 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 5116 struct ixgbe_hw *hw = &adapter->hw;
5117 u32 ctrl, fctrl;
5118 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5119#ifdef CONFIG_PM
5120 int retval = 0;
5121#endif
5122
5123 netif_device_detach(netdev);
5124
5125 if (netif_running(netdev)) {
5126 ixgbe_down(adapter);
5127 ixgbe_free_irq(adapter);
5128 ixgbe_free_all_tx_resources(adapter);
5129 ixgbe_free_all_rx_resources(adapter);
5130 }
7a921c93 5131 ixgbe_clear_interrupt_scheme(adapter);
b3c8b4ba
AD		 5132
5133#ifdef CONFIG_PM
5134 retval = pci_save_state(pdev);
5135 if (retval)
5136 return retval;
4df10466 5137
b3c8b4ba 5138#endif
e8e26350
PW		 5139 if (wufc) {
5140 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5141
e8e26350
PW		 5142 /* turn on all-multi mode if wake on multicast is enabled */
5143 if (wufc & IXGBE_WUFC_MC) {
5144 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5145 fctrl |= IXGBE_FCTRL_MPE;
5146 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5147 }
5148
5149 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5150 ctrl |= IXGBE_CTRL_GIO_DIS;
5151 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5152
5153 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5154 } else {
5155 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5156 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5157 }
5158
dd4d8ca6
DS		 5159 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5160 pci_wake_from_d3(pdev, true);
5161 else
5162 pci_wake_from_d3(pdev, false);
b3c8b4ba 5163
9d8d05ae
RW		 5164 *enable_wake = !!wufc;
5165
b3c8b4ba
AD		 5166 ixgbe_release_hw_control(adapter);
5167
5168 pci_disable_device(pdev);
5169
9d8d05ae
RW		 5170 return 0;
5171}
5172
5173#ifdef CONFIG_PM
5174static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5175{
5176 int retval;
5177 bool wake;
5178
5179 retval = __ixgbe_shutdown(pdev, &wake);
5180 if (retval)
5181 return retval;
5182
5183 if (wake) {
5184 pci_prepare_to_sleep(pdev);
5185 } else {
5186 pci_wake_from_d3(pdev, false);
5187 pci_set_power_state(pdev, PCI_D3hot);
5188 }
b3c8b4ba
AD		 5189
5190 return 0;
5191}
9d8d05ae 5192#endif /* CONFIG_PM */
b3c8b4ba
AD		 5193
5194static void ixgbe_shutdown(struct pci_dev *pdev)
5195{
9d8d05ae
RW		 5196 bool wake;
5197
5198 __ixgbe_shutdown(pdev, &wake);
5199
5200 if (system_state == SYSTEM_POWER_OFF) {
5201 pci_wake_from_d3(pdev, wake);
5202 pci_set_power_state(pdev, PCI_D3hot);
5203 }
b3c8b4ba
AD		 5204}
5205
9a799d71
AK		 5206/**
5207 * ixgbe_update_stats - Update the board statistics counters.
5208 * @adapter: board private structure
5209 **/
5210void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5211{
2d86f139 5212 struct net_device *netdev = adapter->netdev;
9a799d71 5213 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 5214 u64 total_mpc = 0;
5215 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
eb985f09 5216 u64 non_eop_descs = 0, restart_queue = 0;
9a799d71 5217
94b982b2 5218 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5219 u64 rsc_count = 0;
94b982b2 5220 u64 rsc_flush = 0;
d51019a4
PW		 5221 for (i = 0; i < 16; i++)
5222 adapter->hw_rx_no_dma_resources +=
5223 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5224 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 5225 rsc_count += adapter->rx_ring[i]->rsc_count;
5226 rsc_flush += adapter->rx_ring[i]->rsc_flush;
94b982b2
MC		 5227 }
5228 adapter->rsc_total_count = rsc_count;
5229 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5230 }
5231
7ca3bc58
JB		 5232 /* gather some stats to the adapter struct that are per queue */
5233 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5234 restart_queue += adapter->tx_ring[i]->restart_queue;
eb985f09 5235 adapter->restart_queue = restart_queue;
7ca3bc58
JB		 5236
5237 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5238 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
eb985f09 5239 adapter->non_eop_descs = non_eop_descs;
7ca3bc58 5240
9a799d71 5241 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5242 for (i = 0; i < 8; i++) {
5243 /* for packet buffers not used, the register should read 0 */
5244 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5245 missed_rx += mpc;
5246 adapter->stats.mpc[i] += mpc;
5247 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 5248 if (hw->mac.type == ixgbe_mac_82598EB)
5249 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 5250 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5251 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5252 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5253 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 5254 if (hw->mac.type == ixgbe_mac_82599EB) {
5255 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5256 IXGBE_PXONRXCNT(i));
5257 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5258 IXGBE_PXOFFRXCNT(i));
5259 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 5260 } else {
5261 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5262 IXGBE_PXONRXC(i));
5263 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5264 IXGBE_PXOFFRXC(i));
5265 }
2f90b865
AD		 5266 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
5267 IXGBE_PXONTXC(i));
2f90b865 5268 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 5269 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 5270 }
5271 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5272 /* work around hardware counting issue */
5273 adapter->stats.gprc -= missed_rx;
5274
5275 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350 5276 if (hw->mac.type == ixgbe_mac_82599EB) {
aad71918 5277 u64 tmp;
e8e26350 5278 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
aad71918
BG		 5279 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
5280 adapter->stats.gorc += (tmp << 32);
e8e26350 5281 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
aad71918
BG		 5282 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
5283 adapter->stats.gotc += (tmp << 32);
e8e26350
PW		 5284 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5285 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5286 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5287 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
c4cf55e5
PWJ		 5288 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5289 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c
YZ		 5290#ifdef IXGBE_FCOE
5291 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5292 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5293 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5294 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5295 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5296 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5297#endif /* IXGBE_FCOE */
e8e26350
PW		 5298 } else {
5299 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5300 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5301 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5302 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5303 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5304 }
9a799d71
AK		 5305 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5306 adapter->stats.bprc += bprc;
5307 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 5308 if (hw->mac.type == ixgbe_mac_82598EB)
5309 adapter->stats.mprc -= bprc;
9a799d71
AK		 5310 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5311 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5312 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5313 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5314 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5315 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5316 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 5317 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 5318 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5319 adapter->stats.lxontxc += lxon;
5320 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5321 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 5322 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5323 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 5324 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5325 /*
5326 * 82598 errata - tx of flow control packets is included in tx counters
5327 */
5328 xon_off_tot = lxon + lxoff;
5329 adapter->stats.gptc -= xon_off_tot;
5330 adapter->stats.mptc -= xon_off_tot;
5331 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 5332 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5333 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5334 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 5335 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5336 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 5337 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 5338 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5339 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5340 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5341 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5342 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 5343 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5344
5345 /* Fill out the OS statistics structure */
2d86f139 5346 netdev->stats.multicast = adapter->stats.mprc;
9a799d71
AK		 5347
5348 /* Rx Errors */
2d86f139 5349 netdev->stats.rx_errors = adapter->stats.crcerrs +
b4617240 5350 adapter->stats.rlec;
2d86f139
AK		 5351 netdev->stats.rx_dropped = 0;
5352 netdev->stats.rx_length_errors = adapter->stats.rlec;
5353 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5354 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5355}
5356
5357/**
5358 * ixgbe_watchdog - Timer Call-back
5359 * @data: pointer to adapter cast into an unsigned long
5360 **/
5361static void ixgbe_watchdog(unsigned long data)
5362{
5363 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 5364 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5365 u64 eics = 0;
5366 int i;
cf8280ee 5367
fe49f04a
AD		 5368 /*
5369 * Do the watchdog outside of interrupt context due to the lovely
5370 * delays that some of the newer hardware requires
5371 */
22d5a71b 5372
fe49f04a
AD		 5373 if (test_bit(__IXGBE_DOWN, &adapter->state))
5374 goto watchdog_short_circuit;
22d5a71b 5375
fe49f04a
AD		 5376 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5377 /*
5378 * for legacy and MSI interrupts don't set any bits
5379 * that are enabled for EIAM, because this operation
5380 * would set *both* EIMS and EICS for any bit in EIAM
5381 */
5382 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5383 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5384 goto watchdog_reschedule;
5385 }
5386
5387 /* get one bit for every active tx/rx interrupt vector */
5388 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5389 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5390 if (qv->rxr_count || qv->txr_count)
5391 eics |= ((u64)1 << i);
cf8280ee 5392 }
9a799d71 5393
fe49f04a
AD		 5394 /* Cause software interrupt to ensure rx rings are cleaned */
5395 ixgbe_irq_rearm_queues(adapter, eics);
5396
5397watchdog_reschedule:
5398 /* Reset the timer */
5399 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5400
5401watchdog_short_circuit:
cf8280ee
JB		 5402 schedule_work(&adapter->watchdog_task);
5403}
5404
e8e26350
PW		 5405/**
5406 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5407 * @work: pointer to work_struct containing our data
5408 **/
5409static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5410{
5411 struct ixgbe_adapter *adapter = container_of(work,
5412 struct ixgbe_adapter,
5413 multispeed_fiber_task);
5414 struct ixgbe_hw *hw = &adapter->hw;
5415 u32 autoneg;
8620a103 5416 bool negotiation;
e8e26350
PW		 5417
5418 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 5419 autoneg = hw->phy.autoneg_advertised;
5420 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103 5421 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
1097cd17 5422 hw->mac.autotry_restart = false;
8620a103
MC		 5423 if (hw->mac.ops.setup_link)
5424 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 5425 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5426 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5427}
5428
5429/**
5430 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5431 * @work: pointer to work_struct containing our data
5432 **/
5433static void ixgbe_sfp_config_module_task(struct work_struct *work)
5434{
5435 struct ixgbe_adapter *adapter = container_of(work,
5436 struct ixgbe_adapter,
5437 sfp_config_module_task);
5438 struct ixgbe_hw *hw = &adapter->hw;
5439 u32 err;
5440
5441 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 5442
5443 /* Time for electrical oscillations to settle down */
5444 msleep(100);
e8e26350 5445 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5446
e8e26350 5447 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 5448 dev_err(&adapter->pdev->dev, "failed to initialize because "
5449 "an unsupported SFP+ module type was detected.\n"
5450 "Reload the driver after installing a supported "
5451 "module.\n");
63d6e1d8 5452 unregister_netdev(adapter->netdev);
e8e26350
PW		 5453 return;
5454 }
5455 hw->mac.ops.setup_sfp(hw);
5456
8d1c3c07 5457 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 5458 /* This will also work for DA Twinax connections */
5459 schedule_work(&adapter->multispeed_fiber_task);
5460 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5461}
5462
c4cf55e5
PWJ		 5463/**
5464 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5465 * @work: pointer to work_struct containing our data
5466 **/
5467static void ixgbe_fdir_reinit_task(struct work_struct *work)
5468{
5469 struct ixgbe_adapter *adapter = container_of(work,
5470 struct ixgbe_adapter,
5471 fdir_reinit_task);
5472 struct ixgbe_hw *hw = &adapter->hw;
5473 int i;
5474
5475 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5476 for (i = 0; i < adapter->num_tx_queues; i++)
5477 set_bit(__IXGBE_FDIR_INIT_DONE,
4a0b9ca0 5478 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5
PWJ		 5479 } else {
5480 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
d6dbee86 5481 "ignored adding FDIR ATR filters\n");
c4cf55e5
PWJ		 5482 }
5483 /* Done FDIR Re-initialization, enable transmits */
5484 netif_tx_start_all_queues(adapter->netdev);
5485}
5486
10eec955
JF		 5487static DEFINE_MUTEX(ixgbe_watchdog_lock);
5488
cf8280ee 5489/**
69888674
AD		 5490 * ixgbe_watchdog_task - worker thread to bring link up
5491 * @work: pointer to work_struct containing our data
cf8280ee
JB		 5492 **/
5493static void ixgbe_watchdog_task(struct work_struct *work)
5494{
5495 struct ixgbe_adapter *adapter = container_of(work,
5496 struct ixgbe_adapter,
5497 watchdog_task);
5498 struct net_device *netdev = adapter->netdev;
5499 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 5500 u32 link_speed;
5501 bool link_up;
bc59fcda
NS		 5502 int i;
5503 struct ixgbe_ring *tx_ring;
5504 int some_tx_pending = 0;
cf8280ee 5505
10eec955
JF		 5506 mutex_lock(&ixgbe_watchdog_lock);
5507
5508 link_up = adapter->link_up;
5509 link_speed = adapter->link_speed;
cf8280ee
JB		 5510
5511 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5512 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 5513 if (link_up) {
5514#ifdef CONFIG_DCB
5515 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5516 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 5517 hw->mac.ops.fc_enable(hw, i);
264857b8 5518 } else {
620fa036 5519 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5520 }
5521#else
620fa036 5522 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5523#endif
5524 }
5525
cf8280ee
JB		 5526 if (link_up ||
5527 time_after(jiffies, (adapter->link_check_timeout +
5528 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 5529 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 5530 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 5531 }
5532 adapter->link_up = link_up;
5533 adapter->link_speed = link_speed;
5534 }
9a799d71
AK		 5535
5536 if (link_up) {
5537 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 5538 bool flow_rx, flow_tx;
5539
5540 if (hw->mac.type == ixgbe_mac_82599EB) {
5541 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5542 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 5543 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5544 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 5545 } else {
5546 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5547 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 5548 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5549 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 5550 }
5551
a46e534b
JK		 5552 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
5553 "Flow Control: %s\n",
5554 netdev->name,
5555 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5556 "10 Gbps" :
5557 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5558 "1 Gbps" : "unknown speed")),
e8e26350
PW		 5559 ((flow_rx && flow_tx) ? "RX/TX" :
5560 (flow_rx ? "RX" :
5561 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 5562
5563 netif_carrier_on(netdev);
9a799d71
AK		 5564 } else {
5565 /* Force detection of hung controller */
5566 adapter->detect_tx_hung = true;
5567 }
5568 } else {
cf8280ee
JB		 5569 adapter->link_up = false;
5570 adapter->link_speed = 0;
9a799d71 5571 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 5572 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
5573 netdev->name);
9a799d71 5574 netif_carrier_off(netdev);
9a799d71
AK		 5575 }
5576 }
5577
bc59fcda
NS		 5578 if (!netif_carrier_ok(netdev)) {
5579 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 5580 tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5581 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5582 some_tx_pending = 1;
5583 break;
5584 }
5585 }
5586
5587 if (some_tx_pending) {
5588 /* We've lost link, so the controller stops DMA,
5589 * but we've got queued Tx work that's never going
5590 * to get done, so reset controller to flush Tx.
5591 * (Do the reset outside of interrupt context).
5592 */
5593 schedule_work(&adapter->reset_task);
5594 }
5595 }
5596
9a799d71 5597 ixgbe_update_stats(adapter);
10eec955 5598 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 5599}
5600
9a799d71 5601static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 5602 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5603 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 5604{
5605 struct ixgbe_adv_tx_context_desc *context_desc;
5606 unsigned int i;
5607 int err;
5608 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 5609 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5610 u32 mss_l4len_idx, l4len;
9a799d71
AK		 5611
5612 if (skb_is_gso(skb)) {
5613 if (skb_header_cloned(skb)) {
5614 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5615 if (err)
5616 return err;
5617 }
5618 l4len = tcp_hdrlen(skb);
5619 *hdr_len += l4len;
5620
8327d000 5621 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 5622 struct iphdr *iph = ip_hdr(skb);
5623 iph->tot_len = 0;
5624 iph->check = 0;
5625 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 5626 iph->daddr, 0,
5627 IPPROTO_TCP,
5628 0);
8e1e8a47 5629 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 5630 ipv6_hdr(skb)->payload_len = 0;
5631 tcp_hdr(skb)->check =
5632 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 5633 &ipv6_hdr(skb)->daddr,
5634 0, IPPROTO_TCP, 0);
9a799d71
AK		 5635 }
5636
5637 i = tx_ring->next_to_use;
5638
5639 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5640 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5641
5642 /* VLAN MACLEN IPLEN */
5643 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5644 vlan_macip_lens |=
5645 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5646 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 5647 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5648 *hdr_len += skb_network_offset(skb);
5649 vlan_macip_lens |=
5650 (skb_transport_header(skb) - skb_network_header(skb));
5651 *hdr_len +=
5652 (skb_transport_header(skb) - skb_network_header(skb));
5653 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5654 context_desc->seqnum_seed = 0;
5655
5656 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 5657 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 5658 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 5659
8327d000 5660 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 5661 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5662 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5663 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5664
5665 /* MSS L4LEN IDX */
9f8cdf4f 5666 mss_l4len_idx =
9a799d71
AK		 5667 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5668 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 5669 /* use index 1 for TSO */
5670 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5671 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5672
5673 tx_buffer_info->time_stamp = jiffies;
5674 tx_buffer_info->next_to_watch = i;
5675
5676 i++;
5677 if (i == tx_ring->count)
5678 i = 0;
5679 tx_ring->next_to_use = i;
5680
5681 return true;
5682 }
5683 return false;
5684}
5685
5686static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 5687 struct ixgbe_ring *tx_ring,
5688 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 5689{
5690 struct ixgbe_adv_tx_context_desc *context_desc;
5691 unsigned int i;
5692 struct ixgbe_tx_buffer *tx_buffer_info;
5693 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5694
5695 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5696 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5697 i = tx_ring->next_to_use;
5698 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5699 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5700
5701 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5702 vlan_macip_lens |=
5703 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5704 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 5705 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5706 if (skb->ip_summed == CHECKSUM_PARTIAL)
5707 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 5708 skb_network_header(skb));
9a799d71
AK		 5709
5710 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5711 context_desc->seqnum_seed = 0;
5712
5713 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 5714 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 5715
5716 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ca553980
GS		 5717 __be16 protocol;
5718
5719 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5720 const struct vlan_ethhdr *vhdr =
5721 (const struct vlan_ethhdr *)skb->data;
5722
5723 protocol = vhdr->h_vlan_encapsulated_proto;
5724 } else {
5725 protocol = skb->protocol;
5726 }
5727
5728 switch (protocol) {
09640e63 5729 case cpu_to_be16(ETH_P_IP):
9a799d71 5730 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 5731 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5732 type_tucmd_mlhl |=
b4617240 5733 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5734 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5735 type_tucmd_mlhl |=
5736 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5737 break;
09640e63 5738 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 5739 /* XXX what about other V6 headers?? */
5740 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5741 type_tucmd_mlhl |=
b4617240 5742 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5743 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5744 type_tucmd_mlhl |=
5745 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5746 break;
41825d71
AK		 5747 default:
5748 if (unlikely(net_ratelimit())) {
5749 DPRINTK(PROBE, WARNING,
5750 "partial checksum but proto=%x!\n",
5751 skb->protocol);
5752 }
5753 break;
5754 }
9a799d71
AK		 5755 }
5756
5757 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 5758 /* use index zero for tx checksum offload */
9a799d71
AK		 5759 context_desc->mss_l4len_idx = 0;
5760
5761 tx_buffer_info->time_stamp = jiffies;
5762 tx_buffer_info->next_to_watch = i;
9f8cdf4f 5763
9a799d71
AK		 5764 i++;
5765 if (i == tx_ring->count)
5766 i = 0;
5767 tx_ring->next_to_use = i;
5768
5769 return true;
5770 }
9f8cdf4f 5771
9a799d71
AK		 5772 return false;
5773}
5774
5775static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 5776 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 5777 struct sk_buff *skb, u32 tx_flags,
5778 unsigned int first)
9a799d71 5779{
e5a43549 5780 struct pci_dev *pdev = adapter->pdev;
9a799d71 5781 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 5782 unsigned int len;
5783 unsigned int total = skb->len;
9a799d71
AK		 5784 unsigned int offset = 0, size, count = 0, i;
5785 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5786 unsigned int f;
9a799d71
AK		 5787
5788 i = tx_ring->next_to_use;
5789
eacd73f7
YZ		 5790 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5791 /* excluding fcoe_crc_eof for FCoE */
5792 total -= sizeof(struct fcoe_crc_eof);
5793
5794 len = min(skb_headlen(skb), total);
9a799d71
AK		 5795 while (len) {
5796 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5797 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5798
5799 tx_buffer_info->length = size;
e5a43549 5800 tx_buffer_info->mapped_as_page = false;
1b507730 5801 tx_buffer_info->dma = dma_map_single(&pdev->dev,
e5a43549 5802 skb->data + offset,
1b507730
NN		 5803 size, DMA_TO_DEVICE);
5804 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
e5a43549 5805 goto dma_error;
9a799d71
AK		 5806 tx_buffer_info->time_stamp = jiffies;
5807 tx_buffer_info->next_to_watch = i;
5808
5809 len -= size;
eacd73f7 5810 total -= size;
9a799d71
AK		 5811 offset += size;
5812 count++;
44df32c5
AD		 5813
5814 if (len) {
5815 i++;
5816 if (i == tx_ring->count)
5817 i = 0;
5818 }
9a799d71
AK		 5819 }
5820
5821 for (f = 0; f < nr_frags; f++) {
5822 struct skb_frag_struct *frag;
5823
5824 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 5825 len = min((unsigned int)frag->size, total);
e5a43549 5826 offset = frag->page_offset;
9a799d71
AK		 5827
5828 while (len) {
44df32c5
AD		 5829 i++;
5830 if (i == tx_ring->count)
5831 i = 0;
5832
9a799d71
AK		 5833 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5834 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5835
5836 tx_buffer_info->length = size;
1b507730 5837 tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
e5a43549
AD		 5838 frag->page,
5839 offset, size,
1b507730 5840 DMA_TO_DEVICE);
e5a43549 5841 tx_buffer_info->mapped_as_page = true;
1b507730 5842 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
e5a43549 5843 goto dma_error;
9a799d71
AK		 5844 tx_buffer_info->time_stamp = jiffies;
5845 tx_buffer_info->next_to_watch = i;
5846
5847 len -= size;
eacd73f7 5848 total -= size;
9a799d71
AK		 5849 offset += size;
5850 count++;
9a799d71 5851 }
eacd73f7
YZ		 5852 if (total == 0)
5853 break;
9a799d71 5854 }
44df32c5 5855
9a799d71
AK		 5856 tx_ring->tx_buffer_info[i].skb = skb;
5857 tx_ring->tx_buffer_info[first].next_to_watch = i;
5858
e5a43549
AD		 5859 return count;
5860
5861dma_error:
5862 dev_err(&pdev->dev, "TX DMA map failed\n");
5863
5864 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5865 tx_buffer_info->dma = 0;
5866 tx_buffer_info->time_stamp = 0;
5867 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 5868 if (count)
5869 count--;
e5a43549
AD		 5870
5871 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f
RK		 5872 while (count--) {
5873 if (i==0)
e5a43549 5874 i += tx_ring->count;
c1fa347f 5875 i--;
e5a43549
AD		 5876 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5877 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5878 }
5879
e44d38e1 5880 return 0;
9a799d71
AK		 5881}
5882
5883static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 5884 struct ixgbe_ring *tx_ring,
5885 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 5886{
5887 union ixgbe_adv_tx_desc *tx_desc = NULL;
5888 struct ixgbe_tx_buffer *tx_buffer_info;
5889 u32 olinfo_status = 0, cmd_type_len = 0;
5890 unsigned int i;
5891 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5892
5893 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5894
5895 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5896
5897 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5898 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5899
5900 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5901 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5902
5903 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5904 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5905
4eeae6fd
PW		 5906 /* use index 1 context for tso */
5907 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5908 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5909 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 5910 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 5911
5912 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5913 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5914 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5915
eacd73f7
YZ		 5916 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5917 olinfo_status |= IXGBE_ADVTXD_CC;
5918 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5919 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5920 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5921 }
5922
9a799d71
AK		 5923 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5924
5925 i = tx_ring->next_to_use;
5926 while (count--) {
5927 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5928 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5929 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5930 tx_desc->read.cmd_type_len =
b4617240 5931 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 5932 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 5933 i++;
5934 if (i == tx_ring->count)
5935 i = 0;
5936 }
5937
5938 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5939
5940 /*
5941 * Force memory writes to complete before letting h/w
5942 * know there are new descriptors to fetch. (Only
5943 * applicable for weak-ordered memory model archs,
5944 * such as IA-64).
5945 */
5946 wmb();
5947
5948 tx_ring->next_to_use = i;
5949 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5950}
5951
c4cf55e5
PWJ		 5952static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5953 int queue, u32 tx_flags)
5954{
5955 /* Right now, we support IPv4 only */
5956 struct ixgbe_atr_input atr_input;
5957 struct tcphdr *th;
c4cf55e5
PWJ		 5958 struct iphdr *iph = ip_hdr(skb);
5959 struct ethhdr *eth = (struct ethhdr *)skb->data;
5960 u16 vlan_id, src_port, dst_port, flex_bytes;
5961 u32 src_ipv4_addr, dst_ipv4_addr;
5962 u8 l4type = 0;
5963
5964 /* check if we're UDP or TCP */
5965 if (iph->protocol == IPPROTO_TCP) {
5966 th = tcp_hdr(skb);
5967 src_port = th->source;
5968 dst_port = th->dest;
5969 l4type |= IXGBE_ATR_L4TYPE_TCP;
5970 /* l4type IPv4 type is 0, no need to assign */
c4cf55e5
PWJ		 5971 } else {
5972 /* Unsupported L4 header, just bail here */
5973 return;
5974 }
5975
5976 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5977
5978 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5979 IXGBE_TX_FLAGS_VLAN_SHIFT;
5980 src_ipv4_addr = iph->saddr;
5981 dst_ipv4_addr = iph->daddr;
5982 flex_bytes = eth->h_proto;
5983
5984 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5985 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5986 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5987 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5988 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5989 /* src and dst are inverted, think how the receiver sees them */
5990 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5991 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5992
5993 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5994 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5995}
5996
e092be60 5997static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5998 struct ixgbe_ring *tx_ring, int size)
e092be60 5999{
30eba97a 6000 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 6001 /* Herbert's original patch had:
6002 * smp_mb__after_netif_stop_queue();
6003 * but since that doesn't exist yet, just open code it. */
6004 smp_mb();
6005
6006 /* We need to check again in a case another CPU has just
6007 * made room available. */
6008 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6009 return -EBUSY;
6010
6011 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 6012 netif_start_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 6013 ++tx_ring->restart_queue;
e092be60
AV		 6014 return 0;
6015}
6016
6017static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 6018 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 6019{
6020 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6021 return 0;
6022 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6023}
6024
09a3b1f8
SH		 6025static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6026{
6027 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 6028 int txq = smp_processor_id();
09a3b1f8 6029
fdd3d631
KK		 6030 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6031 while (unlikely(txq >= dev->real_num_tx_queues))
6032 txq -= dev->real_num_tx_queues;
5f715823 6033 return txq;
fdd3d631 6034 }
c4cf55e5 6035
5f715823
YZ		 6036#ifdef IXGBE_FCOE
6037 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
ca77cd59
RL		 6038 ((skb->protocol == htons(ETH_P_FCOE)) ||
6039 (skb->protocol == htons(ETH_P_FIP)))) {
5f715823
YZ		 6040 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6041 txq += adapter->ring_feature[RING_F_FCOE].mask;
6042 return txq;
6043 }
6044#endif
2ea186ae
JF		 6045 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6046 if (skb->priority == TC_PRIO_CONTROL)
6047 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6048 else
6049 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6050 >> 13;
6051 return txq;
6052 }
09a3b1f8
SH		 6053
6054 return skb_tx_hash(dev, skb);
6055}
6056
3b29a56d
SH		 6057static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6058 struct net_device *netdev)
9a799d71
AK		 6059{
6060 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6061 struct ixgbe_ring *tx_ring;
60d51134 6062 struct netdev_queue *txq;
9a799d71
AK		 6063 unsigned int first;
6064 unsigned int tx_flags = 0;
30eba97a 6065 u8 hdr_len = 0;
5f715823 6066 int tso;
9a799d71
AK		 6067 int count = 0;
6068 unsigned int f;
9f8cdf4f 6069
9f8cdf4f
JB		 6070 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
6071 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 6072 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6073 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5f715823 6074 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
2f90b865
AD		 6075 }
6076 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6077 tx_flags |= IXGBE_TX_FLAGS_VLAN;
33c66bd1
JF		 6078 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6079 skb->priority != TC_PRIO_CONTROL) {
2ea186ae
JF		 6080 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6081 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6082 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 6083 }
eacd73f7 6084
4a0b9ca0 6085 tx_ring = adapter->tx_ring[skb->queue_mapping];
60127865 6086
09ad1cc0 6087#ifdef IXGBE_FCOE
ca77cd59 6088 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
61a0f421 6089#ifdef CONFIG_IXGBE_DCB
ca77cd59
RL		 6090 /* for FCoE with DCB, we force the priority to what
6091 * was specified by the switch */
6092 if ((skb->protocol == htons(ETH_P_FCOE)) ||
6093 (skb->protocol == htons(ETH_P_FIP))) {
6094 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6095 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6096 tx_flags |= ((adapter->fcoe.up << 13)
6097 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6098 }
09ad1cc0 6099#endif
ca77cd59
RL		 6100 /* flag for FCoE offloads */
6101 if (skb->protocol == htons(ETH_P_FCOE))
6102 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0 6103 }
ca77cd59
RL		 6104#endif
6105
eacd73f7 6106 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 6107 if (skb_is_gso(skb) ||
6108 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 6109 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6110 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 6111 count++;
6112
9f8cdf4f
JB		 6113 count += TXD_USE_COUNT(skb_headlen(skb));
6114 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 6115 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6116
e092be60 6117 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 6118 adapter->tx_busy++;
9a799d71
AK		 6119 return NETDEV_TX_BUSY;
6120 }
9a799d71 6121
9a799d71 6122 first = tx_ring->next_to_use;
eacd73f7
YZ		 6123 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6124#ifdef IXGBE_FCOE
6125 /* setup tx offload for FCoE */
6126 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6127 if (tso < 0) {
6128 dev_kfree_skb_any(skb);
6129 return NETDEV_TX_OK;
6130 }
6131 if (tso)
6132 tx_flags |= IXGBE_TX_FLAGS_FSO;
6133#endif /* IXGBE_FCOE */
6134 } else {
6135 if (skb->protocol == htons(ETH_P_IP))
6136 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6137 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6138 if (tso < 0) {
6139 dev_kfree_skb_any(skb);
6140 return NETDEV_TX_OK;
6141 }
9a799d71 6142
eacd73f7
YZ		 6143 if (tso)
6144 tx_flags |= IXGBE_TX_FLAGS_TSO;
6145 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
6146 (skb->ip_summed == CHECKSUM_PARTIAL))
6147 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6148 }
9a799d71 6149
eacd73f7 6150 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 6151 if (count) {
c4cf55e5
PWJ		 6152 /* add the ATR filter if ATR is on */
6153 if (tx_ring->atr_sample_rate) {
6154 ++tx_ring->atr_count;
6155 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6156 test_bit(__IXGBE_FDIR_INIT_DONE,
6157 &tx_ring->reinit_state)) {
6158 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6159 tx_flags);
6160 tx_ring->atr_count = 0;
6161 }
6162 }
60d51134
ED		 6163 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6164 txq->tx_bytes += skb->len;
6165 txq->tx_packets++;
44df32c5
AD		 6166 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
6167 hdr_len);
44df32c5 6168 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 6169
44df32c5
AD		 6170 } else {
6171 dev_kfree_skb_any(skb);
6172 tx_ring->tx_buffer_info[first].time_stamp = 0;
6173 tx_ring->next_to_use = first;
6174 }
9a799d71
AK		 6175
6176 return NETDEV_TX_OK;
6177}
6178
9a799d71
AK		 6179/**
6180 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6181 * @netdev: network interface device structure
6182 * @p: pointer to an address structure
6183 *
6184 * Returns 0 on success, negative on failure
6185 **/
6186static int ixgbe_set_mac(struct net_device *netdev, void *p)
6187{
6188 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6189 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6190 struct sockaddr *addr = p;
6191
6192 if (!is_valid_ether_addr(addr->sa_data))
6193 return -EADDRNOTAVAIL;
6194
6195 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6196 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6197
1cdd1ec8
GR		 6198 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6199 IXGBE_RAH_AV);
9a799d71
AK		 6200
6201 return 0;
6202}
6203
6b73e10d
BH		 6204static int
6205ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6206{
6207 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6208 struct ixgbe_hw *hw = &adapter->hw;
6209 u16 value;
6210 int rc;
6211
6212 if (prtad != hw->phy.mdio.prtad)
6213 return -EINVAL;
6214 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6215 if (!rc)
6216 rc = value;
6217 return rc;
6218}
6219
6220static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6221 u16 addr, u16 value)
6222{
6223 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6224 struct ixgbe_hw *hw = &adapter->hw;
6225
6226 if (prtad != hw->phy.mdio.prtad)
6227 return -EINVAL;
6228 return hw->phy.ops.write_reg(hw, addr, devad, value);
6229}
6230
6231static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6232{
6233 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6234
6235 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6236}
6237
0365e6e4
PW		 6238/**
6239 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6240 * netdev->dev_addrs
0365e6e4
PW		 6241 * @netdev: network interface device structure
6242 *
6243 * Returns non-zero on failure
6244 **/
6245static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6246{
6247 int err = 0;
6248 struct ixgbe_adapter *adapter = netdev_priv(dev);
6249 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6250
6251 if (is_valid_ether_addr(mac->san_addr)) {
6252 rtnl_lock();
6253 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6254 rtnl_unlock();
6255 }
6256 return err;
6257}
6258
6259/**
6260 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6261 * netdev->dev_addrs
0365e6e4
PW		 6262 * @netdev: network interface device structure
6263 *
6264 * Returns non-zero on failure
6265 **/
6266static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6267{
6268 int err = 0;
6269 struct ixgbe_adapter *adapter = netdev_priv(dev);
6270 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6271
6272 if (is_valid_ether_addr(mac->san_addr)) {
6273 rtnl_lock();
6274 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6275 rtnl_unlock();
6276 }
6277 return err;
6278}
6279
9a799d71
AK		 6280#ifdef CONFIG_NET_POLL_CONTROLLER
6281/*
6282 * Polling 'interrupt' - used by things like netconsole to send skbs
6283 * without having to re-enable interrupts. It's not called while
6284 * the interrupt routine is executing.
6285 */
6286static void ixgbe_netpoll(struct net_device *netdev)
6287{
6288 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6289 int i;
9a799d71 6290
1a647bd2
AD		 6291 /* if interface is down do nothing */
6292 if (test_bit(__IXGBE_DOWN, &adapter->state))
6293 return;
6294
9a799d71 6295 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 6296 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6297 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6298 for (i = 0; i < num_q_vectors; i++) {
6299 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6300 ixgbe_msix_clean_many(0, q_vector);
6301 }
6302 } else {
6303 ixgbe_intr(adapter->pdev->irq, netdev);
6304 }
9a799d71 6305 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 6306}
6307#endif
6308
0edc3527
SH		 6309static const struct net_device_ops ixgbe_netdev_ops = {
6310 .ndo_open = ixgbe_open,
6311 .ndo_stop = ixgbe_close,
00829823 6312 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 6313 .ndo_select_queue = ixgbe_select_queue,
e90d400c 6314 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 6315 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6316 .ndo_validate_addr = eth_validate_addr,
6317 .ndo_set_mac_address = ixgbe_set_mac,
6318 .ndo_change_mtu = ixgbe_change_mtu,
6319 .ndo_tx_timeout = ixgbe_tx_timeout,
6320 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
6321 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6322 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 6323 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 6324 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6325 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6326 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6327 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
0edc3527
SH		 6328#ifdef CONFIG_NET_POLL_CONTROLLER
6329 .ndo_poll_controller = ixgbe_netpoll,
6330#endif
332d4a7d
YZ		 6331#ifdef IXGBE_FCOE
6332 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6333 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 6334 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6335 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 6336 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 6337#endif /* IXGBE_FCOE */
0edc3527
SH		 6338};
6339
1cdd1ec8
GR		 6340static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6341 const struct ixgbe_info *ii)
6342{
6343#ifdef CONFIG_PCI_IOV
6344 struct ixgbe_hw *hw = &adapter->hw;
6345 int err;
6346
6347 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6348 return;
6349
6350 /* The 82599 supports up to 64 VFs per physical function
6351 * but this implementation limits allocation to 63 so that
6352 * basic networking resources are still available to the
6353 * physical function
6354 */
6355 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6356 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6357 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6358 if (err) {
6359 DPRINTK(PROBE, ERR,
6360 "Failed to enable PCI sriov: %d\n", err);
6361 goto err_novfs;
6362 }
6363 /* If call to enable VFs succeeded then allocate memory
6364 * for per VF control structures.
6365 */
6366 adapter->vfinfo =
6367 kcalloc(adapter->num_vfs,
6368 sizeof(struct vf_data_storage), GFP_KERNEL);
6369 if (adapter->vfinfo) {
6370 /* Now that we're sure SR-IOV is enabled
6371 * and memory allocated set up the mailbox parameters
6372 */
6373 ixgbe_init_mbx_params_pf(hw);
6374 memcpy(&hw->mbx.ops, ii->mbx_ops,
6375 sizeof(hw->mbx.ops));
6376
6377 /* Disable RSC when in SR-IOV mode */
6378 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6379 IXGBE_FLAG2_RSC_ENABLED);
6380 return;
6381 }
6382
6383 /* Oh oh */
6384 DPRINTK(PROBE, ERR,
6385 "Unable to allocate memory for VF "
6386 "Data Storage - SRIOV disabled\n");
6387 pci_disable_sriov(adapter->pdev);
6388
6389err_novfs:
6390 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6391 adapter->num_vfs = 0;
6392#endif /* CONFIG_PCI_IOV */
6393}
6394
9a799d71
AK		 6395/**
6396 * ixgbe_probe - Device Initialization Routine
6397 * @pdev: PCI device information struct
6398 * @ent: entry in ixgbe_pci_tbl
6399 *
6400 * Returns 0 on success, negative on failure
6401 *
6402 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6403 * The OS initialization, configuring of the adapter private structure,
6404 * and a hardware reset occur.
6405 **/
6406static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 6407 const struct pci_device_id *ent)
9a799d71
AK		 6408{
6409 struct net_device *netdev;
6410 struct ixgbe_adapter *adapter = NULL;
6411 struct ixgbe_hw *hw;
6412 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 6413 static int cards_found;
6414 int i, err, pci_using_dac;
c85a2618 6415 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 6416#ifdef IXGBE_FCOE
6417 u16 device_caps;
6418#endif
c44ade9e 6419 u32 part_num, eec;
9a799d71 6420
9ce77666 6421 err = pci_enable_device_mem(pdev);
9a799d71
AK		 6422 if (err)
6423 return err;
6424
1b507730
NN		 6425 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6426 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 6427 pci_using_dac = 1;
6428 } else {
1b507730 6429 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 6430 if (err) {
1b507730
NN		 6431 err = dma_set_coherent_mask(&pdev->dev,
6432 DMA_BIT_MASK(32));
9a799d71 6433 if (err) {
b4617240
PW		 6434 dev_err(&pdev->dev, "No usable DMA "
6435 "configuration, aborting\n");
9a799d71
AK		 6436 goto err_dma;
6437 }
6438 }
6439 pci_using_dac = 0;
6440 }
6441
9ce77666 6442 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6443 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 6444 if (err) {
9ce77666 6445 dev_err(&pdev->dev,
6446 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 6447 goto err_pci_reg;
6448 }
6449
19d5afd4 6450 pci_enable_pcie_error_reporting(pdev);
6fabd715 6451
9a799d71 6452 pci_set_master(pdev);
fb3b27bc 6453 pci_save_state(pdev);
9a799d71 6454
c85a2618
JF		 6455 if (ii->mac == ixgbe_mac_82598EB)
6456 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6457 else
6458 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6459
6460 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6461#ifdef IXGBE_FCOE
6462 indices += min_t(unsigned int, num_possible_cpus(),
6463 IXGBE_MAX_FCOE_INDICES);
6464#endif
c85a2618 6465 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 6466 if (!netdev) {
6467 err = -ENOMEM;
6468 goto err_alloc_etherdev;
6469 }
6470
9a799d71
AK		 6471 SET_NETDEV_DEV(netdev, &pdev->dev);
6472
6473 pci_set_drvdata(pdev, netdev);
6474 adapter = netdev_priv(netdev);
6475
6476 adapter->netdev = netdev;
6477 adapter->pdev = pdev;
6478 hw = &adapter->hw;
6479 hw->back = adapter;
6480 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6481
05857980
JK		 6482 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6483 pci_resource_len(pdev, 0));
9a799d71
AK		 6484 if (!hw->hw_addr) {
6485 err = -EIO;
6486 goto err_ioremap;
6487 }
6488
6489 for (i = 1; i <= 5; i++) {
6490 if (pci_resource_len(pdev, i) == 0)
6491 continue;
6492 }
6493
0edc3527 6494 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 6495 ixgbe_set_ethtool_ops(netdev);
9a799d71 6496 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 6497 strcpy(netdev->name, pci_name(pdev));
6498
9a799d71
AK		 6499 adapter->bd_number = cards_found;
6500
9a799d71
AK		 6501 /* Setup hw api */
6502 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 6503 hw->mac.type = ii->mac;
9a799d71 6504
c44ade9e
JB		 6505 /* EEPROM */
6506 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6507 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6508 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6509 if (!(eec & (1 << 8)))
6510 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6511
6512 /* PHY */
6513 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 6514 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 6515 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6516 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6517 hw->phy.mdio.mmds = 0;
6518 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6519 hw->phy.mdio.dev = netdev;
6520 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6521 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 6522
6523 /* set up this timer and work struct before calling get_invariants
6524 * which might start the timer
6525 */
6526 init_timer(&adapter->sfp_timer);
6527 adapter->sfp_timer.function = &ixgbe_sfp_timer;
6528 adapter->sfp_timer.data = (unsigned long) adapter;
6529
6530 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 6531
e8e26350
PW		 6532 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6533 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6534
6535 /* a new SFP+ module arrival, called from GPI SDP2 context */
6536 INIT_WORK(&adapter->sfp_config_module_task,
6537 ixgbe_sfp_config_module_task);
6538
8ca783ab 6539 ii->get_invariants(hw);
9a799d71
AK		 6540
6541 /* setup the private structure */
6542 err = ixgbe_sw_init(adapter);
6543 if (err)
6544 goto err_sw_init;
6545
e86bff0e
DS		 6546 /* Make it possible the adapter to be woken up via WOL */
6547 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6548 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6549
bf069c97
DS		 6550 /*
6551 * If there is a fan on this device and it has failed log the
6552 * failure.
6553 */
6554 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6555 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6556 if (esdp & IXGBE_ESDP_SDP1)
6557 DPRINTK(PROBE, CRIT,
6558 "Fan has stopped, replace the adapter\n");
6559 }
6560
c44ade9e
JB		 6561 /* reset_hw fills in the perm_addr as well */
6562 err = hw->mac.ops.reset_hw(hw);
8ca783ab
DS		 6563 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6564 hw->mac.type == ixgbe_mac_82598EB) {
6565 /*
6566 * Start a kernel thread to watch for a module to arrive.
6567 * Only do this for 82598, since 82599 will generate
6568 * interrupts on module arrival.
6569 */
6570 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6571 mod_timer(&adapter->sfp_timer,
6572 round_jiffies(jiffies + (2 * HZ)));
6573 err = 0;
6574 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 6575 dev_err(&adapter->pdev->dev, "failed to initialize because "
6576 "an unsupported SFP+ module type was detected.\n"
6577 "Reload the driver after installing a supported "
6578 "module.\n");
04f165ef
PW		 6579 goto err_sw_init;
6580 } else if (err) {
c44ade9e
JB		 6581 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
6582 goto err_sw_init;
6583 }
6584
1cdd1ec8
GR		 6585 ixgbe_probe_vf(adapter, ii);
6586
9a799d71 6587 netdev->features = NETIF_F_SG |
b4617240
PW		 6588 NETIF_F_IP_CSUM |
6589 NETIF_F_HW_VLAN_TX |
6590 NETIF_F_HW_VLAN_RX |
6591 NETIF_F_HW_VLAN_FILTER;
9a799d71 6592
e9990a9c 6593 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 6594 netdev->features |= NETIF_F_TSO;
9a799d71 6595 netdev->features |= NETIF_F_TSO6;
78b6f4ce 6596 netdev->features |= NETIF_F_GRO;
ad31c402 6597
45a5ead0
JB		 6598 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6599 netdev->features |= NETIF_F_SCTP_CSUM;
6600
ad31c402
JK		 6601 netdev->vlan_features |= NETIF_F_TSO;
6602 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 6603 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 6604 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 6605 netdev->vlan_features |= NETIF_F_SG;
6606
1cdd1ec8
GR		 6607 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6608 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6609 IXGBE_FLAG_DCB_ENABLED);
2f90b865
AD		 6610 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6611 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6612
7a6b6f51 6613#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 6614 netdev->dcbnl_ops = &dcbnl_ops;
6615#endif
6616
eacd73f7 6617#ifdef IXGBE_FCOE
0d551589 6618 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 6619 if (hw->mac.ops.get_device_caps) {
6620 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 6621 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6622 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 6623 }
6624 }
6625#endif /* IXGBE_FCOE */
9a799d71
AK		 6626 if (pci_using_dac)
6627 netdev->features |= NETIF_F_HIGHDMA;
6628
0c19d6af 6629 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 6630 netdev->features |= NETIF_F_LRO;
6631
9a799d71 6632 /* make sure the EEPROM is good */
c44ade9e 6633 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 6634 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
6635 err = -EIO;
6636 goto err_eeprom;
6637 }
6638
6639 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6640 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6641
c44ade9e
JB		 6642 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6643 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 6644 err = -EIO;
6645 goto err_eeprom;
6646 }
6647
61fac744
PW		 6648 /* power down the optics */
6649 if (hw->phy.multispeed_fiber)
6650 hw->mac.ops.disable_tx_laser(hw);
6651
9a799d71
AK		 6652 init_timer(&adapter->watchdog_timer);
6653 adapter->watchdog_timer.function = &ixgbe_watchdog;
6654 adapter->watchdog_timer.data = (unsigned long)adapter;
6655
6656 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 6657 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 6658
021230d4
AV		 6659 err = ixgbe_init_interrupt_scheme(adapter);
6660 if (err)
6661 goto err_sw_init;
9a799d71 6662
e8e26350
PW		 6663 switch (pdev->device) {
6664 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 6665 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6666 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 6667 break;
6668 default:
6669 adapter->wol = 0;
6670 break;
6671 }
e8e26350
PW		 6672 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6673
04f165ef
PW		 6674 /* pick up the PCI bus settings for reporting later */
6675 hw->mac.ops.get_bus_info(hw);
6676
9a799d71 6677 /* print bus type/speed/width info */
7c510e4b 6678 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 6679 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6680 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6681 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6682 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6683 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 6684 "Unknown"),
7c510e4b 6685 netdev->dev_addr);
c44ade9e 6686 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 6687 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6688 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
6689 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6690 (part_num >> 8), (part_num & 0xff));
6691 else
6692 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6693 hw->mac.type, hw->phy.type,
6694 (part_num >> 8), (part_num & 0xff));
9a799d71 6695
e8e26350 6696 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 6697 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 6698 "this card is not sufficient for optimal "
6699 "performance.\n");
0c254d86 6700 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 6701 "PCI-Express slot is required.\n");
0c254d86
AK		 6702 }
6703
34b0368c
PWJ		 6704 /* save off EEPROM version number */
6705 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6706
9a799d71 6707 /* reset the hardware with the new settings */
794caeb2 6708 err = hw->mac.ops.start_hw(hw);
c44ade9e 6709
794caeb2
PWJ		 6710 if (err == IXGBE_ERR_EEPROM_VERSION) {
6711 /* We are running on a pre-production device, log a warning */
6712 dev_warn(&pdev->dev, "This device is a pre-production "
6713 "adapter/LOM. Please be aware there may be issues "
6714 "associated with your hardware. If you are "
6715 "experiencing problems please contact your Intel or "
6716 "hardware representative who provided you with this "
6717 "hardware.\n");
6718 }
9a799d71
AK		 6719 strcpy(netdev->name, "eth%d");
6720 err = register_netdev(netdev);
6721 if (err)
6722 goto err_register;
6723
54386467
JB		 6724 /* carrier off reporting is important to ethtool even BEFORE open */
6725 netif_carrier_off(netdev);
6726
c4cf55e5
PWJ		 6727 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6728 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6729 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6730
5dd2d332 6731#ifdef CONFIG_IXGBE_DCA
652f093f 6732 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 6733 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 6734 ixgbe_setup_dca(adapter);
6735 }
6736#endif
1cdd1ec8
GR		 6737 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6738 DPRINTK(PROBE, INFO, "IOV is enabled with %d VFs\n",
6739 adapter->num_vfs);
6740 for (i = 0; i < adapter->num_vfs; i++)
6741 ixgbe_vf_configuration(pdev, (i | 0x10000000));
6742 }
6743
0365e6e4
PW		 6744 /* add san mac addr to netdev */
6745 ixgbe_add_sanmac_netdev(netdev);
9a799d71
AK		 6746
6747 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
6748 cards_found++;
6749 return 0;
6750
6751err_register:
5eba3699 6752 ixgbe_release_hw_control(adapter);
7a921c93 6753 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 6754err_sw_init:
6755err_eeprom:
1cdd1ec8
GR		 6756 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6757 ixgbe_disable_sriov(adapter);
c4900be0
DS		 6758 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6759 del_timer_sync(&adapter->sfp_timer);
6760 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6761 cancel_work_sync(&adapter->multispeed_fiber_task);
6762 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 6763 iounmap(hw->hw_addr);
6764err_ioremap:
6765 free_netdev(netdev);
6766err_alloc_etherdev:
9ce77666 6767 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6768 IORESOURCE_MEM));
9a799d71
AK		 6769err_pci_reg:
6770err_dma:
6771 pci_disable_device(pdev);
6772 return err;
6773}
6774
6775/**
6776 * ixgbe_remove - Device Removal Routine
6777 * @pdev: PCI device information struct
6778 *
6779 * ixgbe_remove is called by the PCI subsystem to alert the driver
6780 * that it should release a PCI device. The could be caused by a
6781 * Hot-Plug event, or because the driver is going to be removed from
6782 * memory.
6783 **/
6784static void __devexit ixgbe_remove(struct pci_dev *pdev)
6785{
6786 struct net_device *netdev = pci_get_drvdata(pdev);
6787 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6788
6789 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 6790 /* clear the module not found bit to make sure the worker won't
6791 * reschedule
6792 */
6793 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 6794 del_timer_sync(&adapter->watchdog_timer);
6795
c4900be0
DS		 6796 del_timer_sync(&adapter->sfp_timer);
6797 cancel_work_sync(&adapter->watchdog_task);
6798 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6799 cancel_work_sync(&adapter->multispeed_fiber_task);
6800 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 6801 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6802 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6803 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 6804 flush_scheduled_work();
6805
5dd2d332 6806#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6807 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6808 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6809 dca_remove_requester(&pdev->dev);
6810 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6811 }
6812
6813#endif
332d4a7d
YZ		 6814#ifdef IXGBE_FCOE
6815 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6816 ixgbe_cleanup_fcoe(adapter);
6817
6818#endif /* IXGBE_FCOE */
0365e6e4
PW		 6819
6820 /* remove the added san mac */
6821 ixgbe_del_sanmac_netdev(netdev);
6822
c4900be0
DS		 6823 if (netdev->reg_state == NETREG_REGISTERED)
6824 unregister_netdev(netdev);
9a799d71 6825
1cdd1ec8
GR		 6826 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6827 ixgbe_disable_sriov(adapter);
6828
7a921c93 6829 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 6830
021230d4 6831 ixgbe_release_hw_control(adapter);
9a799d71
AK		 6832
6833 iounmap(adapter->hw.hw_addr);
9ce77666 6834 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6835 IORESOURCE_MEM));
9a799d71 6836
021230d4 6837 DPRINTK(PROBE, INFO, "complete\n");
021230d4 6838
9a799d71
AK		 6839 free_netdev(netdev);
6840
19d5afd4 6841 pci_disable_pcie_error_reporting(pdev);
6fabd715 6842
9a799d71
AK		 6843 pci_disable_device(pdev);
6844}
6845
6846/**
6847 * ixgbe_io_error_detected - called when PCI error is detected
6848 * @pdev: Pointer to PCI device
6849 * @state: The current pci connection state
6850 *
6851 * This function is called after a PCI bus error affecting
6852 * this device has been detected.
6853 */
6854static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 6855 pci_channel_state_t state)
9a799d71
AK		 6856{
6857 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6858 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6859
6860 netif_device_detach(netdev);
6861
3044b8d1
BL		 6862 if (state == pci_channel_io_perm_failure)
6863 return PCI_ERS_RESULT_DISCONNECT;
6864
9a799d71
AK		 6865 if (netif_running(netdev))
6866 ixgbe_down(adapter);
6867 pci_disable_device(pdev);
6868
b4617240 6869 /* Request a slot reset. */
9a799d71
AK		 6870 return PCI_ERS_RESULT_NEED_RESET;
6871}
6872
6873/**
6874 * ixgbe_io_slot_reset - called after the pci bus has been reset.
6875 * @pdev: Pointer to PCI device
6876 *
6877 * Restart the card from scratch, as if from a cold-boot.
6878 */
6879static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
6880{
6881 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6882 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 6883 pci_ers_result_t result;
6884 int err;
9a799d71 6885
9ce77666 6886 if (pci_enable_device_mem(pdev)) {
9a799d71 6887 DPRINTK(PROBE, ERR,
b4617240 6888 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 6889 result = PCI_ERS_RESULT_DISCONNECT;
6890 } else {
6891 pci_set_master(pdev);
6892 pci_restore_state(pdev);
c0e1f68b 6893 pci_save_state(pdev);
9a799d71 6894
dd4d8ca6 6895 pci_wake_from_d3(pdev, false);
9a799d71 6896
6fabd715 6897 ixgbe_reset(adapter);
88512539 6898 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 6899 result = PCI_ERS_RESULT_RECOVERED;
6900 }
6901
6902 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6903 if (err) {
6904 dev_err(&pdev->dev,
6905 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6906 /* non-fatal, continue */
6907 }
9a799d71 6908
6fabd715 6909 return result;
9a799d71
AK		 6910}
6911
6912/**
6913 * ixgbe_io_resume - called when traffic can start flowing again.
6914 * @pdev: Pointer to PCI device
6915 *
6916 * This callback is called when the error recovery driver tells us that
6917 * its OK to resume normal operation.
6918 */
6919static void ixgbe_io_resume(struct pci_dev *pdev)
6920{
6921 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6922 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6923
6924 if (netif_running(netdev)) {
6925 if (ixgbe_up(adapter)) {
6926 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6927 return;
6928 }
6929 }
6930
6931 netif_device_attach(netdev);
9a799d71
AK		 6932}
6933
6934static struct pci_error_handlers ixgbe_err_handler = {
6935 .error_detected = ixgbe_io_error_detected,
6936 .slot_reset = ixgbe_io_slot_reset,
6937 .resume = ixgbe_io_resume,
6938};
6939
6940static struct pci_driver ixgbe_driver = {
6941 .name = ixgbe_driver_name,
6942 .id_table = ixgbe_pci_tbl,
6943 .probe = ixgbe_probe,
6944 .remove = __devexit_p(ixgbe_remove),
6945#ifdef CONFIG_PM
6946 .suspend = ixgbe_suspend,
6947 .resume = ixgbe_resume,
6948#endif
6949 .shutdown = ixgbe_shutdown,
6950 .err_handler = &ixgbe_err_handler
6951};
6952
6953/**
6954 * ixgbe_init_module - Driver Registration Routine
6955 *
6956 * ixgbe_init_module is the first routine called when the driver is
6957 * loaded. All it does is register with the PCI subsystem.
6958 **/
6959static int __init ixgbe_init_module(void)
6960{
6961 int ret;
6962 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6963 ixgbe_driver_string, ixgbe_driver_version);
6964
6965 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6966
5dd2d332 6967#ifdef CONFIG_IXGBE_DCA
bd0362dd 6968 dca_register_notify(&dca_notifier);
bd0362dd 6969#endif
5dd2d332 6970
9a799d71
AK		 6971 ret = pci_register_driver(&ixgbe_driver);
6972 return ret;
6973}
b4617240 6974
9a799d71
AK		 6975module_init(ixgbe_init_module);
6976
6977/**
6978 * ixgbe_exit_module - Driver Exit Cleanup Routine
6979 *
6980 * ixgbe_exit_module is called just before the driver is removed
6981 * from memory.
6982 **/
6983static void __exit ixgbe_exit_module(void)
6984{
5dd2d332 6985#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6986 dca_unregister_notify(&dca_notifier);
6987#endif
9a799d71
AK		 6988 pci_unregister_driver(&ixgbe_driver);
6989}
bd0362dd 6990
5dd2d332 6991#ifdef CONFIG_IXGBE_DCA
bd0362dd 6992static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 6993 void *p)
bd0362dd
JC		 6994{
6995 int ret_val;
6996
6997 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 6998 __ixgbe_notify_dca);
bd0362dd
JC		 6999
7000 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7001}
b453368d 7002
5dd2d332 7003#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 7004#ifdef DEBUG
7005/**
7006 * ixgbe_get_hw_dev_name - return device name string
7007 * used by hardware layer to print debugging information
7008 **/
7009char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
7010{
7011 struct ixgbe_adapter *adapter = hw->back;
7012 return adapter->netdev->name;
7013}
bd0362dd 7014
b453368d 7015#endif
9a799d71
AK		 7016module_exit(ixgbe_exit_module);
7017
7018/* ixgbe_main.c */
kernel source for telekom puls (alcatel/mediatek)