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ixgbe: Properly disable packet split per-ring when globally disabled
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71
AK		 38#include <linux/ipv6.h>
39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
41#include <linux/ethtool.h>
42#include <linux/if_vlan.h>
eacd73f7 43#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 44
45#include "ixgbe.h"
46#include "ixgbe_common.h"
47
48char ixgbe_driver_name[] = "ixgbe";
9c8eb720 49static const char ixgbe_driver_string[] =
b4617240 50 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 51
bbf50e4d 52#define DRV_VERSION "2.0.37-k2"
9c8eb720 53const char ixgbe_driver_version[] = DRV_VERSION;
3efac5a0 54static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
9a799d71
AK		 55
56static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 57 [board_82598] = &ixgbe_82598_info,
e8e26350 58 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 59};
60
61/* ixgbe_pci_tbl - PCI Device ID Table
62 *
63 * Wildcard entries (PCI_ANY_ID) should come last
64 * Last entry must be all 0s
65 *
66 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
67 * Class, Class Mask, private data (not used) }
68 */
69static struct pci_device_id ixgbe_pci_tbl[] = {
1e336d0f
DS		 70 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
71 board_82598 },
9a799d71 72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 73 board_82598 },
9a799d71 74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 75 board_82598 },
0befdb3e
JB		 76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
77 board_82598 },
3845bec0
PWJ		 78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
79 board_82598 },
9a799d71 80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 81 board_82598 },
8d792cd9
JB		 82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
83 board_82598 },
c4900be0
DS		 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
85 board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
87 board_82598 },
b95f5fcb
JB		 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
89 board_82598 },
c4900be0
DS		 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
91 board_82598 },
2f21bdd3
DS		 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
93 board_82598 },
e8e26350
PW		 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
95 board_82599 },
1fcf03e6
PWJ		 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
97 board_82599 },
e8e26350
PW		 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
99 board_82599 },
9a799d71
AK		 100
101 /* required last entry */
102 {0, }
103};
104MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
105
5dd2d332 106#ifdef CONFIG_IXGBE_DCA
bd0362dd 107static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 108 void *p);
bd0362dd
JC		 109static struct notifier_block dca_notifier = {
110 .notifier_call = ixgbe_notify_dca,
111 .next = NULL,
112 .priority = 0
113};
114#endif
115
9a799d71
AK		 116MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
117MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
118MODULE_LICENSE("GPL");
119MODULE_VERSION(DRV_VERSION);
120
121#define DEFAULT_DEBUG_LEVEL_SHIFT 3
122
5eba3699
AV		 123static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
124{
125 u32 ctrl_ext;
126
127 /* Let firmware take over control of h/w */
128 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
129 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 130 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 131}
132
133static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
134{
135 u32 ctrl_ext;
136
137 /* Let firmware know the driver has taken over */
138 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
139 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 140 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 141}
9a799d71 142
e8e26350
PW		 143/*
144 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
145 * @adapter: pointer to adapter struct
146 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
147 * @queue: queue to map the corresponding interrupt to
148 * @msix_vector: the vector to map to the corresponding queue
149 *
150 */
151static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
152 u8 queue, u8 msix_vector)
9a799d71
AK		 153{
154 u32 ivar, index;
e8e26350
PW		 155 struct ixgbe_hw *hw = &adapter->hw;
156 switch (hw->mac.type) {
157 case ixgbe_mac_82598EB:
158 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
159 if (direction == -1)
160 direction = 0;
161 index = (((direction * 64) + queue) >> 2) & 0x1F;
162 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
163 ivar &= ~(0xFF << (8 * (queue & 0x3)));
164 ivar |= (msix_vector << (8 * (queue & 0x3)));
165 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
166 break;
167 case ixgbe_mac_82599EB:
168 if (direction == -1) {
169 /* other causes */
170 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
171 index = ((queue & 1) * 8);
172 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
173 ivar &= ~(0xFF << index);
174 ivar |= (msix_vector << index);
175 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
176 break;
177 } else {
178 /* tx or rx causes */
179 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
180 index = ((16 * (queue & 1)) + (8 * direction));
181 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
182 ivar &= ~(0xFF << index);
183 ivar |= (msix_vector << index);
184 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
185 break;
186 }
187 default:
188 break;
189 }
9a799d71
AK		 190}
191
fe49f04a
AD		 192static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
193 u64 qmask)
194{
195 u32 mask;
196
197 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
198 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
199 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
200 } else {
201 mask = (qmask & 0xFFFFFFFF);
202 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
203 mask = (qmask >> 32);
204 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
205 }
206}
207
9a799d71 208static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 209 struct ixgbe_tx_buffer
210 *tx_buffer_info)
9a799d71 211{
44df32c5 212 tx_buffer_info->dma = 0;
9a799d71 213 if (tx_buffer_info->skb) {
44df32c5
AD		 214 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
215 DMA_TO_DEVICE);
9a799d71
AK		 216 dev_kfree_skb_any(tx_buffer_info->skb);
217 tx_buffer_info->skb = NULL;
218 }
44df32c5 219 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 220 /* tx_buffer_info must be completely set up in the transmit path */
221}
222
223static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 224 struct ixgbe_ring *tx_ring,
225 unsigned int eop)
9a799d71 226{
e01c31a5 227 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 228
9a799d71 229 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 230 * check with the clearing of time_stamp and movement of eop */
9a799d71 231 adapter->detect_tx_hung = false;
44df32c5 232 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 233 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
234 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
235 /* detected Tx unit hang */
e01c31a5
JB		 236 union ixgbe_adv_tx_desc *tx_desc;
237 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 238 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 239 " Tx Queue <%d>\n"
240 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 241 " next_to_use <%x>\n"
242 " next_to_clean <%x>\n"
243 "tx_buffer_info[next_to_clean]\n"
244 " time_stamp <%lx>\n"
e01c31a5
JB		 245 " jiffies <%lx>\n",
246 tx_ring->queue_index,
44df32c5
AD		 247 IXGBE_READ_REG(hw, tx_ring->head),
248 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 249 tx_ring->next_to_use, eop,
250 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 251 return true;
252 }
253
254 return false;
255}
256
b4617240
PW		 257#define IXGBE_MAX_TXD_PWR 14
258#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 259
260/* Tx Descriptors needed, worst case */
261#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
262 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
263#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 264 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 265
e01c31a5
JB		 266static void ixgbe_tx_timeout(struct net_device *netdev);
267
9a799d71
AK		 268/**
269 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 270 * @q_vector: structure containing interrupt and ring information
e01c31a5 271 * @tx_ring: tx ring to clean
9a799d71 272 **/
fe49f04a 273static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e01c31a5 274 struct ixgbe_ring *tx_ring)
9a799d71 275{
fe49f04a 276 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 277 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 278 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
279 struct ixgbe_tx_buffer *tx_buffer_info;
280 unsigned int i, eop, count = 0;
e01c31a5 281 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 282
283 i = tx_ring->next_to_clean;
12207e49
PWJ		 284 eop = tx_ring->tx_buffer_info[i].next_to_watch;
285 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
286
287 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 288 (count < tx_ring->work_limit)) {
12207e49
PWJ		 289 bool cleaned = false;
290 for ( ; !cleaned; count++) {
291 struct sk_buff *skb;
9a799d71
AK		 292 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
293 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 294 cleaned = (i == eop);
e01c31a5 295 skb = tx_buffer_info->skb;
9a799d71 296
12207e49 297 if (cleaned && skb) {
e092be60 298 unsigned int segs, bytecount;
3d8fd385 299 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 300
301 /* gso_segs is currently only valid for tcp */
e092be60 302 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 303#ifdef IXGBE_FCOE
304 /* adjust for FCoE Sequence Offload */
305 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
306 && (skb->protocol == htons(ETH_P_FCOE)) &&
307 skb_is_gso(skb)) {
308 hlen = skb_transport_offset(skb) +
309 sizeof(struct fc_frame_header) +
310 sizeof(struct fcoe_crc_eof);
311 segs = DIV_ROUND_UP(skb->len - hlen,
312 skb_shinfo(skb)->gso_size);
313 }
314#endif /* IXGBE_FCOE */
e092be60 315 /* multiply data chunks by size of headers */
3d8fd385 316 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 317 total_packets += segs;
318 total_bytes += bytecount;
e092be60 319 }
e01c31a5 320
9a799d71 321 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 322 tx_buffer_info);
9a799d71 323
12207e49
PWJ		 324 tx_desc->wb.status = 0;
325
9a799d71
AK		 326 i++;
327 if (i == tx_ring->count)
328 i = 0;
e01c31a5 329 }
12207e49
PWJ		 330
331 eop = tx_ring->tx_buffer_info[i].next_to_watch;
332 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
333 }
334
9a799d71
AK		 335 tx_ring->next_to_clean = i;
336
e092be60 337#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 338 if (unlikely(count && netif_carrier_ok(netdev) &&
339 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 340 /* Make sure that anybody stopping the queue after this
341 * sees the new next_to_clean.
342 */
343 smp_mb();
30eba97a
AV		 344 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
345 !test_bit(__IXGBE_DOWN, &adapter->state)) {
346 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 347 ++adapter->restart_queue;
30eba97a 348 }
e092be60 349 }
9a799d71 350
e01c31a5
JB		 351 if (adapter->detect_tx_hung) {
352 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
353 /* schedule immediate reset if we believe we hung */
354 DPRINTK(PROBE, INFO,
355 "tx hang %d detected, resetting adapter\n",
356 adapter->tx_timeout_count + 1);
357 ixgbe_tx_timeout(adapter->netdev);
358 }
359 }
9a799d71 360
e01c31a5 361 /* re-arm the interrupt */
fe49f04a
AD		 362 if (count >= tx_ring->work_limit)
363 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 364
e01c31a5
JB		 365 tx_ring->total_bytes += total_bytes;
366 tx_ring->total_packets += total_packets;
e01c31a5 367 tx_ring->stats.packets += total_packets;
12207e49 368 tx_ring->stats.bytes += total_bytes;
e01c31a5
JB		 369 adapter->net_stats.tx_bytes += total_bytes;
370 adapter->net_stats.tx_packets += total_packets;
9a1a69ad 371 return (count < tx_ring->work_limit);
9a799d71
AK		 372}
373
5dd2d332 374#ifdef CONFIG_IXGBE_DCA
bd0362dd 375static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 376 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 377{
378 u32 rxctrl;
379 int cpu = get_cpu();
3a581073 380 int q = rx_ring - adapter->rx_ring;
bd0362dd 381
3a581073 382 if (rx_ring->cpu != cpu) {
bd0362dd 383 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 384 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
385 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
386 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
387 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
388 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
389 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
390 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
391 }
bd0362dd
JC		 392 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
393 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 394 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
395 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 396 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 397 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 398 rx_ring->cpu = cpu;
bd0362dd
JC		 399 }
400 put_cpu();
401}
402
403static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 404 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 405{
406 u32 txctrl;
407 int cpu = get_cpu();
3a581073 408 int q = tx_ring - adapter->tx_ring;
bd0362dd 409
3a581073 410 if (tx_ring->cpu != cpu) {
bd0362dd 411 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 412 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
413 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
414 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
415 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
416 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
417 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
418 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
419 }
bd0362dd
JC		 420 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
421 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 422 tx_ring->cpu = cpu;
bd0362dd
JC		 423 }
424 put_cpu();
425}
426
427static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
428{
429 int i;
430
431 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
432 return;
433
e35ec126
AD		 434 /* always use CB2 mode, difference is masked in the CB driver */
435 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
436
bd0362dd
JC		 437 for (i = 0; i < adapter->num_tx_queues; i++) {
438 adapter->tx_ring[i].cpu = -1;
439 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
440 }
441 for (i = 0; i < adapter->num_rx_queues; i++) {
442 adapter->rx_ring[i].cpu = -1;
443 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
444 }
445}
446
447static int __ixgbe_notify_dca(struct device *dev, void *data)
448{
449 struct net_device *netdev = dev_get_drvdata(dev);
450 struct ixgbe_adapter *adapter = netdev_priv(netdev);
451 unsigned long event = *(unsigned long *)data;
452
453 switch (event) {
454 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 455 /* if we're already enabled, don't do it again */
456 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
457 break;
652f093f 458 if (dca_add_requester(dev) == 0) {
96b0e0f6 459 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 460 ixgbe_setup_dca(adapter);
461 break;
462 }
463 /* Fall Through since DCA is disabled. */
464 case DCA_PROVIDER_REMOVE:
465 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
466 dca_remove_requester(dev);
467 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
468 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
469 }
470 break;
471 }
472
652f093f 473 return 0;
bd0362dd
JC		 474}
475
5dd2d332 476#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 477/**
478 * ixgbe_receive_skb - Send a completed packet up the stack
479 * @adapter: board private structure
480 * @skb: packet to send up
177db6ff
MC		 481 * @status: hardware indication of status of receive
482 * @rx_ring: rx descriptor ring (for a specific queue) to setup
483 * @rx_desc: rx descriptor
9a799d71 484 **/
78b6f4ce 485static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 486 struct sk_buff *skb, u8 status,
fdaff1ce 487 struct ixgbe_ring *ring,
177db6ff 488 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 489{
78b6f4ce
HX		 490 struct ixgbe_adapter *adapter = q_vector->adapter;
491 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 492 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
493 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 494
fdaff1ce 495 skb_record_rx_queue(skb, ring->queue_index);
182ff8df 496 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
8a62babf 497 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
78b6f4ce 498 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 499 else
78b6f4ce 500 napi_gro_receive(napi, skb);
177db6ff 501 } else {
8a62babf 502 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
182ff8df
AD		 503 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
504 else
505 netif_rx(skb);
9a799d71
AK		 506 }
507}
508
e59bd25d
AV		 509/**
510 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
511 * @adapter: address of board private structure
512 * @status_err: hardware indication of status of receive
513 * @skb: skb currently being received and modified
514 **/
9a799d71 515static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 516 union ixgbe_adv_rx_desc *rx_desc,
517 struct sk_buff *skb)
9a799d71 518{
8bae1b2b
DS		 519 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
520
9a799d71
AK		 521 skb->ip_summed = CHECKSUM_NONE;
522
712744be
JB		 523 /* Rx csum disabled */
524 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 525 return;
e59bd25d
AV		 526
527 /* if IP and error */
528 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
529 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 530 adapter->hw_csum_rx_error++;
531 return;
532 }
e59bd25d
AV		 533
534 if (!(status_err & IXGBE_RXD_STAT_L4CS))
535 return;
536
537 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 538 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
539
540 /*
541 * 82599 errata, UDP frames with a 0 checksum can be marked as
542 * checksum errors.
543 */
544 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
545 (adapter->hw.mac.type == ixgbe_mac_82599EB))
546 return;
547
e59bd25d
AV		 548 adapter->hw_csum_rx_error++;
549 return;
550 }
551
9a799d71 552 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 553 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 554 adapter->hw_csum_rx_good++;
555}
556
e8e26350
PW		 557static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
558 struct ixgbe_ring *rx_ring, u32 val)
559{
560 /*
561 * Force memory writes to complete before letting h/w
562 * know there are new descriptors to fetch. (Only
563 * applicable for weak-ordered memory model archs,
564 * such as IA-64).
565 */
566 wmb();
567 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
568}
569
9a799d71
AK		 570/**
571 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
572 * @adapter: address of board private structure
573 **/
574static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 575 struct ixgbe_ring *rx_ring,
576 int cleaned_count)
9a799d71 577{
9a799d71
AK		 578 struct pci_dev *pdev = adapter->pdev;
579 union ixgbe_adv_rx_desc *rx_desc;
3a581073 580 struct ixgbe_rx_buffer *bi;
9a799d71 581 unsigned int i;
9a799d71
AK		 582
583 i = rx_ring->next_to_use;
3a581073 584 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 585
586 while (cleaned_count--) {
587 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
588
762f4c57 589 if (!bi->page_dma &&
6e455b89 590 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 591 if (!bi->page) {
762f4c57
JB		 592 bi->page = alloc_page(GFP_ATOMIC);
593 if (!bi->page) {
594 adapter->alloc_rx_page_failed++;
595 goto no_buffers;
596 }
597 bi->page_offset = 0;
598 } else {
599 /* use a half page if we're re-using */
600 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 601 }
762f4c57
JB		 602
603 bi->page_dma = pci_map_page(pdev, bi->page,
604 bi->page_offset,
605 (PAGE_SIZE / 2),
606 PCI_DMA_FROMDEVICE);
9a799d71
AK		 607 }
608
3a581073 609 if (!bi->skb) {
5ecc3614 610 struct sk_buff *skb;
4f57ca6e
JB		 611 skb = netdev_alloc_skb(adapter->netdev,
612 (rx_ring->rx_buf_len +
613 NET_IP_ALIGN));
9a799d71
AK		 614
615 if (!skb) {
616 adapter->alloc_rx_buff_failed++;
617 goto no_buffers;
618 }
619
620 /*
621 * Make buffer alignment 2 beyond a 16 byte boundary
622 * this will result in a 16 byte aligned IP header after
623 * the 14 byte MAC header is removed
624 */
625 skb_reserve(skb, NET_IP_ALIGN);
626
3a581073 627 bi->skb = skb;
4f57ca6e
JB		 628 bi->dma = pci_map_single(pdev, skb->data,
629 rx_ring->rx_buf_len,
3a581073 630 PCI_DMA_FROMDEVICE);
9a799d71
AK		 631 }
632 /* Refresh the desc even if buffer_addrs didn't change because
633 * each write-back erases this info. */
6e455b89 634 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 635 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
636 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 637 } else {
3a581073 638 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 639 }
640
641 i++;
642 if (i == rx_ring->count)
643 i = 0;
3a581073 644 bi = &rx_ring->rx_buffer_info[i];
9a799d71 645 }
7c6e0a43 646
9a799d71
AK		 647no_buffers:
648 if (rx_ring->next_to_use != i) {
649 rx_ring->next_to_use = i;
650 if (i-- == 0)
651 i = (rx_ring->count - 1);
652
e8e26350 653 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 654 }
655}
656
7c6e0a43
JB		 657static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
658{
659 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
660}
661
662static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
663{
664 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
665}
666
f8212f97
AD		 667static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
668{
669 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
670 IXGBE_RXDADV_RSCCNT_MASK) >>
671 IXGBE_RXDADV_RSCCNT_SHIFT;
672}
673
674/**
675 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
676 * @skb: pointer to the last skb in the rsc queue
677 *
678 * This function changes a queue full of hw rsc buffers into a completed
679 * packet. It uses the ->prev pointers to find the first packet and then
680 * turns it into the frag list owner.
681 **/
682static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
683{
684 unsigned int frag_list_size = 0;
685
686 while (skb->prev) {
687 struct sk_buff *prev = skb->prev;
688 frag_list_size += skb->len;
689 skb->prev = NULL;
690 skb = prev;
691 }
692
693 skb_shinfo(skb)->frag_list = skb->next;
694 skb->next = NULL;
695 skb->len += frag_list_size;
696 skb->data_len += frag_list_size;
697 skb->truesize += frag_list_size;
698 return skb;
699}
700
78b6f4ce 701static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 702 struct ixgbe_ring *rx_ring,
703 int *work_done, int work_to_do)
9a799d71 704{
78b6f4ce 705 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 706 struct pci_dev *pdev = adapter->pdev;
707 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
708 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
709 struct sk_buff *skb;
f8212f97 710 unsigned int i, rsc_count = 0;
7c6e0a43 711 u32 len, staterr;
177db6ff
MC		 712 u16 hdr_info;
713 bool cleaned = false;
9a799d71 714 int cleaned_count = 0;
d2f4fbe2 715 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 716#ifdef IXGBE_FCOE
717 int ddp_bytes = 0;
718#endif /* IXGBE_FCOE */
9a799d71
AK		 719
720 i = rx_ring->next_to_clean;
9a799d71
AK		 721 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
722 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
723 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 724
725 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 726 u32 upper_len = 0;
9a799d71
AK		 727 if (*work_done >= work_to_do)
728 break;
729 (*work_done)++;
730
6e455b89 731 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 732 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
733 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 734 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 735 if (hdr_info & IXGBE_RXDADV_SPH)
736 adapter->rx_hdr_split++;
737 if (len > IXGBE_RX_HDR_SIZE)
738 len = IXGBE_RX_HDR_SIZE;
739 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 740 } else {
9a799d71 741 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 742 }
9a799d71
AK		 743
744 cleaned = true;
745 skb = rx_buffer_info->skb;
746 prefetch(skb->data - NET_IP_ALIGN);
747 rx_buffer_info->skb = NULL;
748
21fa4e66 749 if (rx_buffer_info->dma) {
9a799d71 750 pci_unmap_single(pdev, rx_buffer_info->dma,
5ecc3614 751 rx_ring->rx_buf_len,
b4617240 752 PCI_DMA_FROMDEVICE);
4f57ca6e 753 rx_buffer_info->dma = 0;
9a799d71
AK		 754 skb_put(skb, len);
755 }
756
757 if (upper_len) {
758 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 759 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 760 rx_buffer_info->page_dma = 0;
761 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 762 rx_buffer_info->page,
763 rx_buffer_info->page_offset,
764 upper_len);
765
766 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
767 (page_count(rx_buffer_info->page) != 1))
768 rx_buffer_info->page = NULL;
769 else
770 get_page(rx_buffer_info->page);
9a799d71
AK		 771
772 skb->len += upper_len;
773 skb->data_len += upper_len;
774 skb->truesize += upper_len;
775 }
776
777 i++;
778 if (i == rx_ring->count)
779 i = 0;
9a799d71
AK		 780
781 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
782 prefetch(next_rxd);
9a799d71 783 cleaned_count++;
f8212f97 784
0c19d6af 785 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 786 rsc_count = ixgbe_get_rsc_count(rx_desc);
787
788 if (rsc_count) {
789 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
790 IXGBE_RXDADV_NEXTP_SHIFT;
791 next_buffer = &rx_ring->rx_buffer_info[nextp];
792 rx_ring->rsc_count += (rsc_count - 1);
793 } else {
794 next_buffer = &rx_ring->rx_buffer_info[i];
795 }
796
9a799d71 797 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97
AD		 798 if (skb->prev)
799 skb = ixgbe_transform_rsc_queue(skb);
9a799d71
AK		 800 rx_ring->stats.packets++;
801 rx_ring->stats.bytes += skb->len;
802 } else {
6e455b89 803 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 804 rx_buffer_info->skb = next_buffer->skb;
805 rx_buffer_info->dma = next_buffer->dma;
806 next_buffer->skb = skb;
807 next_buffer->dma = 0;
808 } else {
809 skb->next = next_buffer->skb;
810 skb->next->prev = skb;
811 }
9a799d71
AK		 812 adapter->non_eop_descs++;
813 goto next_desc;
814 }
815
816 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
817 dev_kfree_skb_irq(skb);
818 goto next_desc;
819 }
820
8bae1b2b 821 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 822
823 /* probably a little skewed due to removing CRC */
824 total_rx_bytes += skb->len;
825 total_rx_packets++;
826
74ce8dd2 827 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 828#ifdef IXGBE_FCOE
829 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 830 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
831 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
832 if (!ddp_bytes)
332d4a7d 833 goto next_desc;
3d8fd385 834 }
332d4a7d 835#endif /* IXGBE_FCOE */
fdaff1ce 836 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 837
838next_desc:
839 rx_desc->wb.upper.status_error = 0;
840
841 /* return some buffers to hardware, one at a time is too slow */
842 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
843 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
844 cleaned_count = 0;
845 }
846
847 /* use prefetched values */
848 rx_desc = next_rxd;
f8212f97 849 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 850
851 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 852 }
853
9a799d71
AK		 854 rx_ring->next_to_clean = i;
855 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
856
857 if (cleaned_count)
858 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
859
3d8fd385
YZ		 860#ifdef IXGBE_FCOE
861 /* include DDPed FCoE data */
862 if (ddp_bytes > 0) {
863 unsigned int mss;
864
865 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
866 sizeof(struct fc_frame_header) -
867 sizeof(struct fcoe_crc_eof);
868 if (mss > 512)
869 mss &= ~511;
870 total_rx_bytes += ddp_bytes;
871 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
872 }
873#endif /* IXGBE_FCOE */
874
f494e8fa
AV		 875 rx_ring->total_packets += total_rx_packets;
876 rx_ring->total_bytes += total_rx_bytes;
877 adapter->net_stats.rx_bytes += total_rx_bytes;
878 adapter->net_stats.rx_packets += total_rx_packets;
879
9a799d71
AK		 880 return cleaned;
881}
882
021230d4 883static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 884/**
885 * ixgbe_configure_msix - Configure MSI-X hardware
886 * @adapter: board private structure
887 *
888 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
889 * interrupts.
890 **/
891static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
892{
021230d4
AV		 893 struct ixgbe_q_vector *q_vector;
894 int i, j, q_vectors, v_idx, r_idx;
895 u32 mask;
9a799d71 896
021230d4 897 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 898
4df10466
JB		 899 /*
900 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 901 * corresponding register.
902 */
903 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 904 q_vector = adapter->q_vector[v_idx];
021230d4
AV		 905 /* XXX for_each_bit(...) */
906 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 907 adapter->num_rx_queues);
021230d4
AV		 908
909 for (i = 0; i < q_vector->rxr_count; i++) {
910 j = adapter->rx_ring[r_idx].reg_idx;
e8e26350 911 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 912 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 913 adapter->num_rx_queues,
914 r_idx + 1);
021230d4
AV		 915 }
916 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 917 adapter->num_tx_queues);
021230d4
AV		 918
919 for (i = 0; i < q_vector->txr_count; i++) {
920 j = adapter->tx_ring[r_idx].reg_idx;
e8e26350 921 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 922 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 923 adapter->num_tx_queues,
924 r_idx + 1);
021230d4
AV		 925 }
926
30efa5a3 927 /* if this is a tx only vector halve the interrupt rate */
021230d4 928 if (q_vector->txr_count && !q_vector->rxr_count)
30efa5a3 929 q_vector->eitr = (adapter->eitr_param >> 1);
509ee935 930 else if (q_vector->rxr_count)
30efa5a3
JB		 931 /* rx only */
932 q_vector->eitr = adapter->eitr_param;
021230d4 933
fe49f04a 934 ixgbe_write_eitr(q_vector);
9a799d71
AK		 935 }
936
e8e26350
PW		 937 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
938 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
939 v_idx);
940 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
941 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 942 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
943
41fb9248 944 /* set up to autoclear timer, and the vectors */
021230d4 945 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 946 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 947 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 948}
949
f494e8fa
AV		 950enum latency_range {
951 lowest_latency = 0,
952 low_latency = 1,
953 bulk_latency = 2,
954 latency_invalid = 255
955};
956
957/**
958 * ixgbe_update_itr - update the dynamic ITR value based on statistics
959 * @adapter: pointer to adapter
960 * @eitr: eitr setting (ints per sec) to give last timeslice
961 * @itr_setting: current throttle rate in ints/second
962 * @packets: the number of packets during this measurement interval
963 * @bytes: the number of bytes during this measurement interval
964 *
965 * Stores a new ITR value based on packets and byte
966 * counts during the last interrupt. The advantage of per interrupt
967 * computation is faster updates and more accurate ITR for the current
968 * traffic pattern. Constants in this function were computed
969 * based on theoretical maximum wire speed and thresholds were set based
970 * on testing data as well as attempting to minimize response time
971 * while increasing bulk throughput.
972 * this functionality is controlled by the InterruptThrottleRate module
973 * parameter (see ixgbe_param.c)
974 **/
975static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 976 u32 eitr, u8 itr_setting,
977 int packets, int bytes)
f494e8fa
AV		 978{
979 unsigned int retval = itr_setting;
980 u32 timepassed_us;
981 u64 bytes_perint;
982
983 if (packets == 0)
984 goto update_itr_done;
985
986
987 /* simple throttlerate management
988 * 0-20MB/s lowest (100000 ints/s)
989 * 20-100MB/s low (20000 ints/s)
990 * 100-1249MB/s bulk (8000 ints/s)
991 */
992 /* what was last interrupt timeslice? */
993 timepassed_us = 1000000/eitr;
994 bytes_perint = bytes / timepassed_us; /* bytes/usec */
995
996 switch (itr_setting) {
997 case lowest_latency:
998 if (bytes_perint > adapter->eitr_low)
999 retval = low_latency;
1000 break;
1001 case low_latency:
1002 if (bytes_perint > adapter->eitr_high)
1003 retval = bulk_latency;
1004 else if (bytes_perint <= adapter->eitr_low)
1005 retval = lowest_latency;
1006 break;
1007 case bulk_latency:
1008 if (bytes_perint <= adapter->eitr_high)
1009 retval = low_latency;
1010 break;
1011 }
1012
1013update_itr_done:
1014 return retval;
1015}
1016
509ee935
JB		 1017/**
1018 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1019 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1020 *
1021 * This function is made to be called by ethtool and by the driver
1022 * when it needs to update EITR registers at runtime. Hardware
1023 * specific quirks/differences are taken care of here.
1024 */
fe49f04a 1025void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1026{
fe49f04a 1027 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1028 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1029 int v_idx = q_vector->v_idx;
1030 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1031
509ee935
JB		 1032 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1033 /* must write high and low 16 bits to reset counter */
1034 itr_reg |= (itr_reg << 16);
1035 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1036 /*
1037 * set the WDIS bit to not clear the timer bits and cause an
1038 * immediate assertion of the interrupt
1039 */
1040 itr_reg |= IXGBE_EITR_CNT_WDIS;
1041 }
1042 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1043}
1044
f494e8fa
AV		 1045static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1046{
1047 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1048 u32 new_itr;
1049 u8 current_itr, ret_itr;
fe49f04a 1050 int i, r_idx;
f494e8fa
AV		 1051 struct ixgbe_ring *rx_ring, *tx_ring;
1052
1053 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1054 for (i = 0; i < q_vector->txr_count; i++) {
1055 tx_ring = &(adapter->tx_ring[r_idx]);
1056 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1057 q_vector->tx_itr,
1058 tx_ring->total_packets,
1059 tx_ring->total_bytes);
f494e8fa
AV		 1060 /* if the result for this queue would decrease interrupt
1061 * rate for this vector then use that result */
30efa5a3 1062 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1063 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1064 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1065 r_idx + 1);
f494e8fa
AV		 1066 }
1067
1068 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1069 for (i = 0; i < q_vector->rxr_count; i++) {
1070 rx_ring = &(adapter->rx_ring[r_idx]);
1071 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1072 q_vector->rx_itr,
1073 rx_ring->total_packets,
1074 rx_ring->total_bytes);
f494e8fa
AV		 1075 /* if the result for this queue would decrease interrupt
1076 * rate for this vector then use that result */
30efa5a3 1077 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1078 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1079 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1080 r_idx + 1);
f494e8fa
AV		 1081 }
1082
30efa5a3 1083 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1084
1085 switch (current_itr) {
1086 /* counts and packets in update_itr are dependent on these numbers */
1087 case lowest_latency:
1088 new_itr = 100000;
1089 break;
1090 case low_latency:
1091 new_itr = 20000; /* aka hwitr = ~200 */
1092 break;
1093 case bulk_latency:
1094 default:
1095 new_itr = 8000;
1096 break;
1097 }
1098
1099 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1100 /* do an exponential smoothing */
1101 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1102
1103 /* save the algorithm value here, not the smoothed one */
1104 q_vector->eitr = new_itr;
fe49f04a
AD		 1105
1106 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1107 }
1108
1109 return;
1110}
1111
0befdb3e
JB		 1112static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1113{
1114 struct ixgbe_hw *hw = &adapter->hw;
1115
1116 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1117 (eicr & IXGBE_EICR_GPI_SDP1)) {
1118 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1119 /* write to clear the interrupt */
1120 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1121 }
1122}
cf8280ee 1123
e8e26350
PW		 1124static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1125{
1126 struct ixgbe_hw *hw = &adapter->hw;
1127
1128 if (eicr & IXGBE_EICR_GPI_SDP1) {
1129 /* Clear the interrupt */
1130 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1131 schedule_work(&adapter->multispeed_fiber_task);
1132 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1133 /* Clear the interrupt */
1134 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1135 schedule_work(&adapter->sfp_config_module_task);
1136 } else {
1137 /* Interrupt isn't for us... */
1138 return;
1139 }
1140}
1141
cf8280ee
JB		 1142static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1143{
1144 struct ixgbe_hw *hw = &adapter->hw;
1145
1146 adapter->lsc_int++;
1147 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1148 adapter->link_check_timeout = jiffies;
1149 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1150 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1151 schedule_work(&adapter->watchdog_task);
1152 }
1153}
1154
9a799d71
AK		 1155static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1156{
1157 struct net_device *netdev = data;
1158 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1159 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1160 u32 eicr;
1161
1162 /*
1163 * Workaround for Silicon errata. Use clear-by-write instead
1164 * of clear-by-read. Reading with EICS will return the
1165 * interrupt causes without clearing, which later be done
1166 * with the write to EICR.
1167 */
1168 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1169 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1170
cf8280ee
JB		 1171 if (eicr & IXGBE_EICR_LSC)
1172 ixgbe_check_lsc(adapter);
d4f80882 1173
e8e26350
PW		 1174 if (hw->mac.type == ixgbe_mac_82598EB)
1175 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1176
c4cf55e5 1177 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1178 ixgbe_check_sfp_event(adapter, eicr);
c4cf55e5
PWJ		 1179
1180 /* Handle Flow Director Full threshold interrupt */
1181 if (eicr & IXGBE_EICR_FLOW_DIR) {
1182 int i;
1183 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1184 /* Disable transmits before FDIR Re-initialization */
1185 netif_tx_stop_all_queues(netdev);
1186 for (i = 0; i < adapter->num_tx_queues; i++) {
1187 struct ixgbe_ring *tx_ring =
1188 &adapter->tx_ring[i];
1189 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1190 &tx_ring->reinit_state))
1191 schedule_work(&adapter->fdir_reinit_task);
1192 }
1193 }
1194 }
d4f80882
AV		 1195 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1196 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1197
1198 return IRQ_HANDLED;
1199}
1200
fe49f04a
AD		 1201static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1202 u64 qmask)
1203{
1204 u32 mask;
1205
1206 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1207 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1208 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1209 } else {
1210 mask = (qmask & 0xFFFFFFFF);
1211 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1212 mask = (qmask >> 32);
1213 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1214 }
1215 /* skip the flush */
1216}
1217
1218static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1219 u64 qmask)
1220{
1221 u32 mask;
1222
1223 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1224 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1225 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1226 } else {
1227 mask = (qmask & 0xFFFFFFFF);
1228 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1229 mask = (qmask >> 32);
1230 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1231 }
1232 /* skip the flush */
1233}
1234
9a799d71
AK		 1235static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1236{
021230d4
AV		 1237 struct ixgbe_q_vector *q_vector = data;
1238 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1239 struct ixgbe_ring *tx_ring;
021230d4
AV		 1240 int i, r_idx;
1241
1242 if (!q_vector->txr_count)
1243 return IRQ_HANDLED;
1244
1245 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1246 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 1247 tx_ring = &(adapter->tx_ring[r_idx]);
3a581073
JB		 1248 tx_ring->total_bytes = 0;
1249 tx_ring->total_packets = 0;
021230d4 1250 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1251 r_idx + 1);
021230d4 1252 }
9a799d71 1253
91281fd3
AD		 1254 /* disable interrupts on this vector only */
1255 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1256 napi_schedule(&q_vector->napi);
1257
9a799d71
AK		 1258 return IRQ_HANDLED;
1259}
1260
021230d4
AV		 1261/**
1262 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1263 * @irq: unused
1264 * @data: pointer to our q_vector struct for this interrupt vector
1265 **/
9a799d71
AK		 1266static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1267{
021230d4
AV		 1268 struct ixgbe_q_vector *q_vector = data;
1269 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1270 struct ixgbe_ring *rx_ring;
021230d4 1271 int r_idx;
30efa5a3 1272 int i;
021230d4
AV		 1273
1274 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 1275 for (i = 0; i < q_vector->rxr_count; i++) {
1276 rx_ring = &(adapter->rx_ring[r_idx]);
1277 rx_ring->total_bytes = 0;
1278 rx_ring->total_packets = 0;
1279 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1280 r_idx + 1);
1281 }
1282
021230d4
AV		 1283 if (!q_vector->rxr_count)
1284 return IRQ_HANDLED;
1285
30efa5a3 1286 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1287 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 1288 /* disable interrupts on this vector only */
fe49f04a 1289 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
288379f0 1290 napi_schedule(&q_vector->napi);
021230d4
AV		 1291
1292 return IRQ_HANDLED;
1293}
1294
1295static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1296{
91281fd3
AD		 1297 struct ixgbe_q_vector *q_vector = data;
1298 struct ixgbe_adapter *adapter = q_vector->adapter;
1299 struct ixgbe_ring *ring;
1300 int r_idx;
1301 int i;
1302
1303 if (!q_vector->txr_count && !q_vector->rxr_count)
1304 return IRQ_HANDLED;
1305
1306 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1307 for (i = 0; i < q_vector->txr_count; i++) {
1308 ring = &(adapter->tx_ring[r_idx]);
1309 ring->total_bytes = 0;
1310 ring->total_packets = 0;
1311 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1312 r_idx + 1);
1313 }
1314
1315 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1316 for (i = 0; i < q_vector->rxr_count; i++) {
1317 ring = &(adapter->rx_ring[r_idx]);
1318 ring->total_bytes = 0;
1319 ring->total_packets = 0;
1320 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1321 r_idx + 1);
1322 }
1323
1324 /* disable interrupts on this vector only */
1325 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1326 napi_schedule(&q_vector->napi);
9a799d71 1327
9a799d71
AK		 1328 return IRQ_HANDLED;
1329}
1330
021230d4
AV		 1331/**
1332 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1333 * @napi: napi struct with our devices info in it
1334 * @budget: amount of work driver is allowed to do this pass, in packets
1335 *
f0848276
JB		 1336 * This function is optimized for cleaning one queue only on a single
1337 * q_vector!!!
021230d4 1338 **/
9a799d71
AK		 1339static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1340{
021230d4 1341 struct ixgbe_q_vector *q_vector =
b4617240 1342 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1343 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1344 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1345 int work_done = 0;
021230d4 1346 long r_idx;
9a799d71 1347
021230d4 1348 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1349 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1350#ifdef CONFIG_IXGBE_DCA
bd0362dd 1351 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1352 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1353#endif
9a799d71 1354
78b6f4ce 1355 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1356
021230d4
AV		 1357 /* If all Rx work done, exit the polling mode */
1358 if (work_done < budget) {
288379f0 1359 napi_complete(napi);
509ee935 1360 if (adapter->itr_setting & 1)
f494e8fa 1361 ixgbe_set_itr_msix(q_vector);
9a799d71 1362 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1363 ixgbe_irq_enable_queues(adapter,
1364 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1365 }
1366
1367 return work_done;
1368}
1369
f0848276 1370/**
91281fd3 1371 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1372 * @napi: napi struct with our devices info in it
1373 * @budget: amount of work driver is allowed to do this pass, in packets
1374 *
1375 * This function will clean more than one rx queue associated with a
1376 * q_vector.
1377 **/
91281fd3 1378static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1379{
1380 struct ixgbe_q_vector *q_vector =
1381 container_of(napi, struct ixgbe_q_vector, napi);
1382 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1383 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1384 int work_done = 0, i;
1385 long r_idx;
91281fd3
AD		 1386 bool tx_clean_complete = true;
1387
1388 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1389 for (i = 0; i < q_vector->txr_count; i++) {
1390 ring = &(adapter->tx_ring[r_idx]);
1391#ifdef CONFIG_IXGBE_DCA
1392 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1393 ixgbe_update_tx_dca(adapter, ring);
1394#endif
1395 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1396 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1397 r_idx + 1);
1398 }
f0848276
JB		 1399
1400 /* attempt to distribute budget to each queue fairly, but don't allow
1401 * the budget to go below 1 because we'll exit polling */
1402 budget /= (q_vector->rxr_count ?: 1);
1403 budget = max(budget, 1);
1404 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1405 for (i = 0; i < q_vector->rxr_count; i++) {
91281fd3 1406 ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1407#ifdef CONFIG_IXGBE_DCA
f0848276 1408 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1409 ixgbe_update_rx_dca(adapter, ring);
f0848276 1410#endif
91281fd3 1411 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276
JB		 1412 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1413 r_idx + 1);
1414 }
1415
1416 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
91281fd3 1417 ring = &(adapter->rx_ring[r_idx]);
f0848276 1418 /* If all Rx work done, exit the polling mode */
7f821875 1419 if (work_done < budget) {
288379f0 1420 napi_complete(napi);
509ee935 1421 if (adapter->itr_setting & 1)
f0848276
JB		 1422 ixgbe_set_itr_msix(q_vector);
1423 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1424 ixgbe_irq_enable_queues(adapter,
1425 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1426 return 0;
1427 }
1428
1429 return work_done;
1430}
91281fd3
AD		 1431
1432/**
1433 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1434 * @napi: napi struct with our devices info in it
1435 * @budget: amount of work driver is allowed to do this pass, in packets
1436 *
1437 * This function is optimized for cleaning one queue only on a single
1438 * q_vector!!!
1439 **/
1440static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1441{
1442 struct ixgbe_q_vector *q_vector =
1443 container_of(napi, struct ixgbe_q_vector, napi);
1444 struct ixgbe_adapter *adapter = q_vector->adapter;
1445 struct ixgbe_ring *tx_ring = NULL;
1446 int work_done = 0;
1447 long r_idx;
1448
1449 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1450 tx_ring = &(adapter->tx_ring[r_idx]);
1451#ifdef CONFIG_IXGBE_DCA
1452 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1453 ixgbe_update_tx_dca(adapter, tx_ring);
1454#endif
1455
1456 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1457 work_done = budget;
1458
1459 /* If all Rx work done, exit the polling mode */
1460 if (work_done < budget) {
1461 napi_complete(napi);
1462 if (adapter->itr_setting & 1)
1463 ixgbe_set_itr_msix(q_vector);
1464 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1465 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1466 }
1467
1468 return work_done;
1469}
1470
021230d4 1471static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1472 int r_idx)
021230d4 1473{
7a921c93
AD		 1474 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1475
1476 set_bit(r_idx, q_vector->rxr_idx);
1477 q_vector->rxr_count++;
021230d4
AV		 1478}
1479
1480static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 1481 int t_idx)
021230d4 1482{
7a921c93
AD		 1483 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1484
1485 set_bit(t_idx, q_vector->txr_idx);
1486 q_vector->txr_count++;
021230d4
AV		 1487}
1488
9a799d71 1489/**
021230d4
AV		 1490 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1491 * @adapter: board private structure to initialize
1492 * @vectors: allotted vector count for descriptor rings
9a799d71 1493 *
021230d4
AV		 1494 * This function maps descriptor rings to the queue-specific vectors
1495 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1496 * one vector per ring/queue, but on a constrained vector budget, we
1497 * group the rings as "efficiently" as possible. You would add new
1498 * mapping configurations in here.
9a799d71 1499 **/
021230d4 1500static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1501 int vectors)
021230d4
AV		 1502{
1503 int v_start = 0;
1504 int rxr_idx = 0, txr_idx = 0;
1505 int rxr_remaining = adapter->num_rx_queues;
1506 int txr_remaining = adapter->num_tx_queues;
1507 int i, j;
1508 int rqpv, tqpv;
1509 int err = 0;
1510
1511 /* No mapping required if MSI-X is disabled. */
1512 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1513 goto out;
9a799d71 1514
021230d4
AV		 1515 /*
1516 * The ideal configuration...
1517 * We have enough vectors to map one per queue.
1518 */
1519 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1520 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1521 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1522
021230d4
AV		 1523 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1524 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1525
9a799d71 1526 goto out;
021230d4 1527 }
9a799d71 1528
021230d4
AV		 1529 /*
1530 * If we don't have enough vectors for a 1-to-1
1531 * mapping, we'll have to group them so there are
1532 * multiple queues per vector.
1533 */
1534 /* Re-adjusting *qpv takes care of the remainder. */
1535 for (i = v_start; i < vectors; i++) {
1536 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1537 for (j = 0; j < rqpv; j++) {
1538 map_vector_to_rxq(adapter, i, rxr_idx);
1539 rxr_idx++;
1540 rxr_remaining--;
1541 }
1542 }
1543 for (i = v_start; i < vectors; i++) {
1544 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1545 for (j = 0; j < tqpv; j++) {
1546 map_vector_to_txq(adapter, i, txr_idx);
1547 txr_idx++;
1548 txr_remaining--;
9a799d71 1549 }
9a799d71
AK		 1550 }
1551
021230d4
AV		 1552out:
1553 return err;
1554}
1555
1556/**
1557 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1558 * @adapter: board private structure
1559 *
1560 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1561 * interrupts from the kernel.
1562 **/
1563static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1564{
1565 struct net_device *netdev = adapter->netdev;
1566 irqreturn_t (*handler)(int, void *);
1567 int i, vector, q_vectors, err;
cb13fc20 1568 int ri=0, ti=0;
021230d4
AV		 1569
1570 /* Decrement for Other and TCP Timer vectors */
1571 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1572
1573 /* Map the Tx/Rx rings to the vectors we were allotted. */
1574 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1575 if (err)
1576 goto out;
1577
1578#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1579 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1580 &ixgbe_msix_clean_many)
021230d4 1581 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 1582 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 1583
1584 if(handler == &ixgbe_msix_clean_rx) {
1585 sprintf(adapter->name[vector], "%s-%s-%d",
1586 netdev->name, "rx", ri++);
1587 }
1588 else if(handler == &ixgbe_msix_clean_tx) {
1589 sprintf(adapter->name[vector], "%s-%s-%d",
1590 netdev->name, "tx", ti++);
1591 }
1592 else
1593 sprintf(adapter->name[vector], "%s-%s-%d",
1594 netdev->name, "TxRx", vector);
1595
021230d4 1596 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1597 handler, 0, adapter->name[vector],
7a921c93 1598 adapter->q_vector[vector]);
9a799d71
AK		 1599 if (err) {
1600 DPRINTK(PROBE, ERR,
b4617240
PW		 1601 "request_irq failed for MSIX interrupt "
1602 "Error: %d\n", err);
021230d4 1603 goto free_queue_irqs;
9a799d71 1604 }
9a799d71
AK		 1605 }
1606
021230d4
AV		 1607 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1608 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1609 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1610 if (err) {
1611 DPRINTK(PROBE, ERR,
1612 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1613 goto free_queue_irqs;
9a799d71
AK		 1614 }
1615
9a799d71
AK		 1616 return 0;
1617
021230d4
AV		 1618free_queue_irqs:
1619 for (i = vector - 1; i >= 0; i--)
1620 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 1621 adapter->q_vector[i]);
021230d4
AV		 1622 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1623 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1624 kfree(adapter->msix_entries);
1625 adapter->msix_entries = NULL;
021230d4 1626out:
9a799d71
AK		 1627 return err;
1628}
1629
f494e8fa
AV		 1630static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1631{
7a921c93 1632 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 1633 u8 current_itr;
1634 u32 new_itr = q_vector->eitr;
1635 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1636 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1637
30efa5a3 1638 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1639 q_vector->tx_itr,
1640 tx_ring->total_packets,
1641 tx_ring->total_bytes);
30efa5a3 1642 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1643 q_vector->rx_itr,
1644 rx_ring->total_packets,
1645 rx_ring->total_bytes);
f494e8fa 1646
30efa5a3 1647 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1648
1649 switch (current_itr) {
1650 /* counts and packets in update_itr are dependent on these numbers */
1651 case lowest_latency:
1652 new_itr = 100000;
1653 break;
1654 case low_latency:
1655 new_itr = 20000; /* aka hwitr = ~200 */
1656 break;
1657 case bulk_latency:
1658 new_itr = 8000;
1659 break;
1660 default:
1661 break;
1662 }
1663
1664 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1665 /* do an exponential smoothing */
1666 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1667
1668 /* save the algorithm value here, not the smoothed one */
1669 q_vector->eitr = new_itr;
fe49f04a
AD		 1670
1671 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1672 }
1673
1674 return;
1675}
1676
79aefa45
AD		 1677/**
1678 * ixgbe_irq_enable - Enable default interrupt generation settings
1679 * @adapter: board private structure
1680 **/
1681static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1682{
1683 u32 mask;
835462fc
NS		 1684
1685 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 1686 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1687 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1688 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1689 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1690 mask |= IXGBE_EIMS_GPI_SDP1;
1691 mask |= IXGBE_EIMS_GPI_SDP2;
1692 }
c4cf55e5
PWJ		 1693 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1694 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1695 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 1696
79aefa45 1697 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 1698 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45
AD		 1699 IXGBE_WRITE_FLUSH(&adapter->hw);
1700}
021230d4 1701
9a799d71 1702/**
021230d4 1703 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1704 * @irq: interrupt number
1705 * @data: pointer to a network interface device structure
9a799d71
AK		 1706 **/
1707static irqreturn_t ixgbe_intr(int irq, void *data)
1708{
1709 struct net_device *netdev = data;
1710 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1711 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 1712 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 1713 u32 eicr;
1714
54037505
DS		 1715 /*
1716 * Workaround for silicon errata. Mask the interrupts
1717 * before the read of EICR.
1718 */
1719 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1720
021230d4
AV		 1721 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1722 * therefore no explict interrupt disable is necessary */
1723 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1724 if (!eicr) {
1725 /* shared interrupt alert!
1726 * make sure interrupts are enabled because the read will
1727 * have disabled interrupts due to EIAM */
1728 ixgbe_irq_enable(adapter);
9a799d71 1729 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1730 }
9a799d71 1731
cf8280ee
JB		 1732 if (eicr & IXGBE_EICR_LSC)
1733 ixgbe_check_lsc(adapter);
021230d4 1734
e8e26350
PW		 1735 if (hw->mac.type == ixgbe_mac_82599EB)
1736 ixgbe_check_sfp_event(adapter, eicr);
1737
0befdb3e
JB		 1738 ixgbe_check_fan_failure(adapter, eicr);
1739
7a921c93 1740 if (napi_schedule_prep(&(q_vector->napi))) {
f494e8fa
AV		 1741 adapter->tx_ring[0].total_packets = 0;
1742 adapter->tx_ring[0].total_bytes = 0;
1743 adapter->rx_ring[0].total_packets = 0;
1744 adapter->rx_ring[0].total_bytes = 0;
021230d4 1745 /* would disable interrupts here but EIAM disabled it */
7a921c93 1746 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 1747 }
1748
1749 return IRQ_HANDLED;
1750}
1751
021230d4
AV		 1752static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1753{
1754 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1755
1756 for (i = 0; i < q_vectors; i++) {
7a921c93 1757 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 1758 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1759 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1760 q_vector->rxr_count = 0;
1761 q_vector->txr_count = 0;
1762 }
1763}
1764
9a799d71
AK		 1765/**
1766 * ixgbe_request_irq - initialize interrupts
1767 * @adapter: board private structure
1768 *
1769 * Attempts to configure interrupts using the best available
1770 * capabilities of the hardware and kernel.
1771 **/
021230d4 1772static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1773{
1774 struct net_device *netdev = adapter->netdev;
021230d4 1775 int err;
9a799d71 1776
021230d4
AV		 1777 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1778 err = ixgbe_request_msix_irqs(adapter);
1779 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1780 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
b4617240 1781 netdev->name, netdev);
021230d4
AV		 1782 } else {
1783 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
b4617240 1784 netdev->name, netdev);
9a799d71
AK		 1785 }
1786
9a799d71
AK		 1787 if (err)
1788 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1789
9a799d71
AK		 1790 return err;
1791}
1792
1793static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1794{
1795 struct net_device *netdev = adapter->netdev;
1796
1797 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1798 int i, q_vectors;
9a799d71 1799
021230d4
AV		 1800 q_vectors = adapter->num_msix_vectors;
1801
1802 i = q_vectors - 1;
9a799d71 1803 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1804
021230d4
AV		 1805 i--;
1806 for (; i >= 0; i--) {
1807 free_irq(adapter->msix_entries[i].vector,
7a921c93 1808 adapter->q_vector[i]);
021230d4
AV		 1809 }
1810
1811 ixgbe_reset_q_vectors(adapter);
1812 } else {
1813 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1814 }
1815}
1816
22d5a71b
JB		 1817/**
1818 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1819 * @adapter: board private structure
1820 **/
1821static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1822{
835462fc
NS		 1823 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1824 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1825 } else {
1826 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1827 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 1828 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
22d5a71b
JB		 1829 }
1830 IXGBE_WRITE_FLUSH(&adapter->hw);
1831 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1832 int i;
1833 for (i = 0; i < adapter->num_msix_vectors; i++)
1834 synchronize_irq(adapter->msix_entries[i].vector);
1835 } else {
1836 synchronize_irq(adapter->pdev->irq);
1837 }
1838}
1839
9a799d71
AK		 1840/**
1841 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1842 *
1843 **/
1844static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1845{
9a799d71
AK		 1846 struct ixgbe_hw *hw = &adapter->hw;
1847
021230d4 1848 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
30efa5a3 1849 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
9a799d71 1850
e8e26350
PW		 1851 ixgbe_set_ivar(adapter, 0, 0, 0);
1852 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 1853
1854 map_vector_to_rxq(adapter, 0, 0);
1855 map_vector_to_txq(adapter, 0, 0);
1856
1857 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1858}
1859
1860/**
3a581073 1861 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1862 * @adapter: board private structure
1863 *
1864 * Configure the Tx unit of the MAC after a reset.
1865 **/
1866static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1867{
12207e49 1868 u64 tdba;
9a799d71 1869 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1870 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1871
1872 /* Setup the HW Tx Head and Tail descriptor pointers */
1873 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1874 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1875 j = ring->reg_idx;
1876 tdba = ring->dma;
1877 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1878 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 1879 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 1880 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1881 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1882 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1883 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1884 adapter->tx_ring[i].head = IXGBE_TDH(j);
1885 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1886 /* Disable Tx Head Writeback RO bit, since this hoses
1887 * bookkeeping if things aren't delivered in order.
1888 */
e01c31a5 1889 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1890 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1891 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1892 }
e8e26350
PW		 1893 if (hw->mac.type == ixgbe_mac_82599EB) {
1894 /* We enable 8 traffic classes, DCB only */
1895 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1896 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1897 IXGBE_MTQC_8TC_8TQ));
1898 }
9a799d71
AK		 1899}
1900
e8e26350 1901#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 1902
a6616b42
YZ		 1903static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
1904 struct ixgbe_ring *rx_ring)
cc41ac7c 1905{
cc41ac7c 1906 u32 srrctl;
a6616b42 1907 int index;
0cefafad 1908 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 1909
a6616b42
YZ		 1910 index = rx_ring->reg_idx;
1911 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1912 unsigned long mask;
0cefafad 1913 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 1914 index = index & mask;
cc41ac7c 1915 }
cc41ac7c
JB		 1916 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1917
1918 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1919 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1920
afafd5b0
AD		 1921 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1922 IXGBE_SRRCTL_BSIZEHDR_MASK;
1923
6e455b89 1924 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 1925#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1926 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1927#else
1928 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1929#endif
cc41ac7c 1930 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 1931 } else {
afafd5b0
AD		 1932 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1933 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 1934 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 1935 }
e8e26350 1936
cc41ac7c
JB		 1937 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1938}
9a799d71 1939
0cefafad
JB		 1940static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1941{
1942 u32 mrqc = 0;
1943 int mask;
1944
1945 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1946 return mrqc;
1947
1948 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1949#ifdef CONFIG_IXGBE_DCB
1950 | IXGBE_FLAG_DCB_ENABLED
1951#endif
1952 );
1953
1954 switch (mask) {
1955 case (IXGBE_FLAG_RSS_ENABLED):
1956 mrqc = IXGBE_MRQC_RSSEN;
1957 break;
1958#ifdef CONFIG_IXGBE_DCB
1959 case (IXGBE_FLAG_DCB_ENABLED):
1960 mrqc = IXGBE_MRQC_RT8TCEN;
1961 break;
1962#endif /* CONFIG_IXGBE_DCB */
1963 default:
1964 break;
1965 }
1966
1967 return mrqc;
1968}
1969
9a799d71 1970/**
3a581073 1971 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1972 * @adapter: board private structure
1973 *
1974 * Configure the Rx unit of the MAC after a reset.
1975 **/
1976static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1977{
1978 u64 rdba;
1979 struct ixgbe_hw *hw = &adapter->hw;
a6616b42 1980 struct ixgbe_ring *rx_ring;
9a799d71
AK		 1981 struct net_device *netdev = adapter->netdev;
1982 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1983 int i, j;
9a799d71 1984 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1985 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1986 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1987 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1988 u32 fctrl, hlreg0;
509ee935 1989 u32 reta = 0, mrqc = 0;
cc41ac7c 1990 u32 rdrxctl;
f8212f97 1991 u32 rscctrl;
7c6e0a43 1992 int rx_buf_len;
9a799d71
AK		 1993
1994 /* Decide whether to use packet split mode or not */
762f4c57 1995 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 1996
1997 /* Set the RX buffer length according to the mode */
1998 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 1999 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 2000 if (hw->mac.type == ixgbe_mac_82599EB) {
2001 /* PSRTYPE must be initialized in 82599 */
2002 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2003 IXGBE_PSRTYPE_UDPHDR |
2004 IXGBE_PSRTYPE_IPV4HDR |
dfa12f05
YZ		 2005 IXGBE_PSRTYPE_IPV6HDR |
2006 IXGBE_PSRTYPE_L2HDR;
e8e26350
PW		 2007 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2008 }
9a799d71 2009 } else {
0c19d6af 2010 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2011 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2012 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2013 else
7c6e0a43 2014 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 2015 }
2016
2017 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2018 fctrl |= IXGBE_FCTRL_BAM;
021230d4 2019 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 2020 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 2021 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2022
2023 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2024 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2025 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2026 else
2027 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
63f39bd1 2028#ifdef IXGBE_FCOE
f34c5c82 2029 if (netdev->features & NETIF_F_FCOE_MTU)
63f39bd1
YZ		 2030 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2031#endif
9a799d71
AK		 2032 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2033
9a799d71
AK		 2034 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2035 /* disable receives while setting up the descriptors */
2036 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2037 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2038
0cefafad
JB		 2039 /*
2040 * Setup the HW Rx Head and Tail Descriptor Pointers and
2041 * the Base and Length of the Rx Descriptor Ring
2042 */
9a799d71 2043 for (i = 0; i < adapter->num_rx_queues; i++) {
a6616b42
YZ		 2044 rx_ring = &adapter->rx_ring[i];
2045 rdba = rx_ring->dma;
2046 j = rx_ring->reg_idx;
284901a9 2047 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 2048 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2049 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2050 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2051 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
a6616b42
YZ		 2052 rx_ring->head = IXGBE_RDH(j);
2053 rx_ring->tail = IXGBE_RDT(j);
2054 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2055
6e455b89
YZ		 2056 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2057 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
1b3ff02e
PWJ		 2058 else
2059 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2060
63f39bd1 2061#ifdef IXGBE_FCOE
f34c5c82 2062 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2063 struct ixgbe_ring_feature *f;
2064 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2065 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2066 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2067 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2068 rx_ring->rx_buf_len =
2069 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2070 }
63f39bd1
YZ		 2071 }
2072
2073#endif /* IXGBE_FCOE */
a6616b42 2074 ixgbe_configure_srrctl(adapter, rx_ring);
9a799d71
AK		 2075 }
2076
e8e26350
PW		 2077 if (hw->mac.type == ixgbe_mac_82598EB) {
2078 /*
2079 * For VMDq support of different descriptor types or
2080 * buffer sizes through the use of multiple SRRCTL
2081 * registers, RDRXCTL.MVMEN must be set to 1
2082 *
2083 * also, the manual doesn't mention it clearly but DCA hints
2084 * will only use queue 0's tags unless this bit is set. Side
2085 * effects of setting this bit are only that SRRCTL must be
2086 * fully programmed [0..15]
2087 */
2a41ff81
JB		 2088 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2089 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2090 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 2091 }
177db6ff 2092
e8e26350 2093 /* Program MRQC for the distribution of queues */
0cefafad 2094 mrqc = ixgbe_setup_mrqc(adapter);
e8e26350 2095
021230d4 2096 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 2097 /* Fill out redirection table */
021230d4
AV		 2098 for (i = 0, j = 0; i < 128; i++, j++) {
2099 if (j == adapter->ring_feature[RING_F_RSS].indices)
2100 j = 0;
2101 /* reta = 4-byte sliding window of
2102 * 0x00..(indices-1)(indices-1)00..etc. */
2103 reta = (reta << 8) | (j * 0x11);
2104 if ((i & 3) == 3)
2105 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 2106 }
2107
2108 /* Fill out hash function seeds */
2109 for (i = 0; i < 10; i++)
7c6e0a43 2110 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 2111
2a41ff81
JB		 2112 if (hw->mac.type == ixgbe_mac_82598EB)
2113 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 2114 /* Perform hash on these packet types */
2a41ff81
JB		 2115 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2116 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2117 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2118 | IXGBE_MRQC_RSS_FIELD_IPV6
2119 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2120 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 2121 }
2a41ff81 2122 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 2123
021230d4
AV		 2124 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2125
2126 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2127 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2128 /* Disable indicating checksum in descriptor, enables
2129 * RSS hash */
9a799d71 2130 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 2131 }
021230d4
AV		 2132 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2133 /* Enable IPv4 payload checksum for UDP fragments
2134 * if PCSD is not set */
2135 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2136 }
2137
2138 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 2139
2140 if (hw->mac.type == ixgbe_mac_82599EB) {
2141 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2142 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 2143 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 2144 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2145 }
f8212f97 2146
0c19d6af 2147 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97
AD		 2148 /* Enable 82599 HW-RSC */
2149 for (i = 0; i < adapter->num_rx_queues; i++) {
6e455b89
YZ		 2150 rx_ring = &adapter->rx_ring[i];
2151 j = rx_ring->reg_idx;
f8212f97
AD		 2152 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2153 rscctrl |= IXGBE_RSCCTL_RSCEN;
2154 /*
e76678dd
AD		 2155 * we must limit the number of descriptors so that the
2156 * total size of max desc * buf_len is not greater
2157 * than 65535
f8212f97 2158 */
6e455b89 2159 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
e76678dd
AD		 2160#if (MAX_SKB_FRAGS > 16)
2161 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2162#elif (MAX_SKB_FRAGS > 8)
f8212f97 2163 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
e76678dd
AD		 2164#elif (MAX_SKB_FRAGS > 4)
2165 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
f8212f97 2166#else
e76678dd 2167 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
f8212f97 2168#endif
e76678dd
AD		 2169 } else {
2170 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2171 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2172 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2173 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2174 else
2175 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2176 }
f8212f97
AD		 2177 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2178 }
2179 /* Disable RSC for ACK packets */
2180 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2181 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2182 }
9a799d71
AK		 2183}
2184
068c89b0
DS		 2185static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2186{
2187 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2188 struct ixgbe_hw *hw = &adapter->hw;
2189
2190 /* add VID to filter table */
2191 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2192}
2193
2194static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2195{
2196 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2197 struct ixgbe_hw *hw = &adapter->hw;
2198
2199 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2200 ixgbe_irq_disable(adapter);
2201
2202 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2203
2204 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2205 ixgbe_irq_enable(adapter);
2206
2207 /* remove VID from filter table */
2208 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2209}
2210
9a799d71 2211static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2212 struct vlan_group *grp)
9a799d71
AK		 2213{
2214 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2215 u32 ctrl;
e8e26350 2216 int i, j;
9a799d71 2217
d4f80882
AV		 2218 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2219 ixgbe_irq_disable(adapter);
9a799d71
AK		 2220 adapter->vlgrp = grp;
2221
2f90b865
AD		 2222 /*
2223 * For a DCB driver, always enable VLAN tag stripping so we can
2224 * still receive traffic from a DCB-enabled host even if we're
2225 * not in DCB mode.
2226 */
2227 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
e8e26350
PW		 2228 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2229 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2230 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2231 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2232 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2233 ctrl |= IXGBE_VLNCTRL_VFE;
9a799d71
AK		 2234 /* enable VLAN tag insert/strip */
2235 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
9a799d71
AK		 2236 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2237 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
e8e26350
PW		 2238 for (i = 0; i < adapter->num_rx_queues; i++) {
2239 j = adapter->rx_ring[i].reg_idx;
2240 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2241 ctrl |= IXGBE_RXDCTL_VME;
2242 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2243 }
9a799d71 2244 }
e8e26350 2245 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2246
d4f80882
AV		 2247 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2248 ixgbe_irq_enable(adapter);
9a799d71
AK		 2249}
2250
9a799d71
AK		 2251static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2252{
2253 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2254
2255 if (adapter->vlgrp) {
2256 u16 vid;
2257 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2258 if (!vlan_group_get_device(adapter->vlgrp, vid))
2259 continue;
2260 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2261 }
2262 }
2263}
2264
2c5645cf
CL		 2265static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2266{
2267 struct dev_mc_list *mc_ptr;
2268 u8 *addr = *mc_addr_ptr;
2269 *vmdq = 0;
2270
2271 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2272 if (mc_ptr->next)
2273 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2274 else
2275 *mc_addr_ptr = NULL;
2276
2277 return addr;
2278}
2279
9a799d71 2280/**
2c5645cf 2281 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2282 * @netdev: network interface device structure
2283 *
2c5645cf
CL		 2284 * The set_rx_method entry point is called whenever the unicast/multicast
2285 * address list or the network interface flags are updated. This routine is
2286 * responsible for configuring the hardware for proper unicast, multicast and
2287 * promiscuous mode.
9a799d71 2288 **/
2c5645cf 2289static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2290{
2291 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2292 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 2293 u32 fctrl, vlnctrl;
2c5645cf
CL		 2294 u8 *addr_list = NULL;
2295 int addr_count = 0;
9a799d71
AK		 2296
2297 /* Check for Promiscuous and All Multicast modes */
2298
2299 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 2300 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 2301
2302 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2303 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2304 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 2305 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 2306 } else {
746b9f02
PM		 2307 if (netdev->flags & IFF_ALLMULTI) {
2308 fctrl |= IXGBE_FCTRL_MPE;
2309 fctrl &= ~IXGBE_FCTRL_UPE;
2310 } else {
2311 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2312 }
3d01625a 2313 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 2314 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2315 }
2316
2317 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 2318 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 2319
2c5645cf 2320 /* reprogram secondary unicast list */
31278e71 2321 hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
9a799d71 2322
2c5645cf
CL		 2323 /* reprogram multicast list */
2324 addr_count = netdev->mc_count;
2325 if (addr_count)
2326 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 2327 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2328 ixgbe_addr_list_itr);
9a799d71
AK		 2329}
2330
021230d4
AV		 2331static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2332{
2333 int q_idx;
2334 struct ixgbe_q_vector *q_vector;
2335 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2336
2337 /* legacy and MSI only use one vector */
2338 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2339 q_vectors = 1;
2340
2341 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2342 struct napi_struct *napi;
7a921c93 2343 q_vector = adapter->q_vector[q_idx];
f0848276 2344 napi = &q_vector->napi;
91281fd3
AD		 2345 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2346 if (!q_vector->rxr_count || !q_vector->txr_count) {
2347 if (q_vector->txr_count == 1)
2348 napi->poll = &ixgbe_clean_txonly;
2349 else if (q_vector->rxr_count == 1)
2350 napi->poll = &ixgbe_clean_rxonly;
2351 }
2352 }
f0848276
JB		 2353
2354 napi_enable(napi);
021230d4
AV		 2355 }
2356}
2357
2358static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2359{
2360 int q_idx;
2361 struct ixgbe_q_vector *q_vector;
2362 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2363
2364 /* legacy and MSI only use one vector */
2365 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2366 q_vectors = 1;
2367
2368 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 2369 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2370 napi_disable(&q_vector->napi);
2371 }
2372}
2373
7a6b6f51 2374#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2375/*
2376 * ixgbe_configure_dcb - Configure DCB hardware
2377 * @adapter: ixgbe adapter struct
2378 *
2379 * This is called by the driver on open to configure the DCB hardware.
2380 * This is also called by the gennetlink interface when reconfiguring
2381 * the DCB state.
2382 */
2383static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2384{
2385 struct ixgbe_hw *hw = &adapter->hw;
2386 u32 txdctl, vlnctrl;
2387 int i, j;
2388
2389 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2390 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2391 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2392
2393 /* reconfigure the hardware */
2394 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2395
2396 for (i = 0; i < adapter->num_tx_queues; i++) {
2397 j = adapter->tx_ring[i].reg_idx;
2398 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2399 /* PThresh workaround for Tx hang with DFP enabled. */
2400 txdctl |= 32;
2401 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2402 }
2403 /* Enable VLAN tag insert/strip */
2404 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
e8e26350
PW		 2405 if (hw->mac.type == ixgbe_mac_82598EB) {
2406 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2407 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2408 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2409 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2410 vlnctrl |= IXGBE_VLNCTRL_VFE;
2411 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2412 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2413 for (i = 0; i < adapter->num_rx_queues; i++) {
2414 j = adapter->rx_ring[i].reg_idx;
2415 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2416 vlnctrl |= IXGBE_RXDCTL_VME;
2417 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2418 }
2419 }
2f90b865
AD		 2420 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2421}
2422
2423#endif
9a799d71
AK		 2424static void ixgbe_configure(struct ixgbe_adapter *adapter)
2425{
2426 struct net_device *netdev = adapter->netdev;
c4cf55e5 2427 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 2428 int i;
2429
2c5645cf 2430 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2431
2432 ixgbe_restore_vlan(adapter);
7a6b6f51 2433#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2434 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2435 netif_set_gso_max_size(netdev, 32768);
2436 ixgbe_configure_dcb(adapter);
2437 } else {
2438 netif_set_gso_max_size(netdev, 65536);
2439 }
2440#else
2441 netif_set_gso_max_size(netdev, 65536);
2442#endif
9a799d71 2443
eacd73f7
YZ		 2444#ifdef IXGBE_FCOE
2445 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2446 ixgbe_configure_fcoe(adapter);
2447
2448#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 2449 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2450 for (i = 0; i < adapter->num_tx_queues; i++)
2451 adapter->tx_ring[i].atr_sample_rate =
2452 adapter->atr_sample_rate;
2453 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2454 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2455 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2456 }
2457
9a799d71
AK		 2458 ixgbe_configure_tx(adapter);
2459 ixgbe_configure_rx(adapter);
2460 for (i = 0; i < adapter->num_rx_queues; i++)
2461 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 2462 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 2463}
2464
e8e26350
PW		 2465static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2466{
2467 switch (hw->phy.type) {
2468 case ixgbe_phy_sfp_avago:
2469 case ixgbe_phy_sfp_ftl:
2470 case ixgbe_phy_sfp_intel:
2471 case ixgbe_phy_sfp_unknown:
2472 case ixgbe_phy_tw_tyco:
2473 case ixgbe_phy_tw_unknown:
2474 return true;
2475 default:
2476 return false;
2477 }
2478}
2479
0ecc061d 2480/**
e8e26350
PW		 2481 * ixgbe_sfp_link_config - set up SFP+ link
2482 * @adapter: pointer to private adapter struct
2483 **/
2484static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2485{
2486 struct ixgbe_hw *hw = &adapter->hw;
2487
2488 if (hw->phy.multispeed_fiber) {
2489 /*
2490 * In multispeed fiber setups, the device may not have
2491 * had a physical connection when the driver loaded.
2492 * If that's the case, the initial link configuration
2493 * couldn't get the MAC into 10G or 1G mode, so we'll
2494 * never have a link status change interrupt fire.
2495 * We need to try and force an autonegotiation
2496 * session, then bring up link.
2497 */
2498 hw->mac.ops.setup_sfp(hw);
2499 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2500 schedule_work(&adapter->multispeed_fiber_task);
2501 } else {
2502 /*
2503 * Direct Attach Cu and non-multispeed fiber modules
2504 * still need to be configured properly prior to
2505 * attempting link.
2506 */
2507 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2508 schedule_work(&adapter->sfp_config_module_task);
2509 }
2510}
2511
2512/**
2513 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2514 * @hw: pointer to private hardware struct
2515 *
2516 * Returns 0 on success, negative on failure
2517 **/
e8e26350 2518static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2519{
2520 u32 autoneg;
8620a103 2521 bool negotiation, link_up = false;
0ecc061d
PWJ		 2522 u32 ret = IXGBE_ERR_LINK_SETUP;
2523
2524 if (hw->mac.ops.check_link)
2525 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2526
2527 if (ret)
2528 goto link_cfg_out;
2529
2530 if (hw->mac.ops.get_link_capabilities)
8620a103 2531 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
0ecc061d
PWJ		 2532 if (ret)
2533 goto link_cfg_out;
2534
8620a103
MC		 2535 if (hw->mac.ops.setup_link)
2536 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 2537link_cfg_out:
2538 return ret;
2539}
2540
e8e26350
PW		 2541#define IXGBE_MAX_RX_DESC_POLL 10
2542static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2543 int rxr)
2544{
2545 int j = adapter->rx_ring[rxr].reg_idx;
2546 int k;
2547
2548 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2549 if (IXGBE_READ_REG(&adapter->hw,
2550 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2551 break;
2552 else
2553 msleep(1);
2554 }
2555 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2556 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2557 "not set within the polling period\n", rxr);
2558 }
2559 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2560 (adapter->rx_ring[rxr].count - 1));
2561}
2562
9a799d71
AK		 2563static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2564{
2565 struct net_device *netdev = adapter->netdev;
9a799d71 2566 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2567 int i, j = 0;
e8e26350 2568 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2569 int err;
9a799d71 2570 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2571 u32 txdctl, rxdctl, mhadd;
e8e26350 2572 u32 dmatxctl;
021230d4 2573 u32 gpie;
9a799d71 2574
5eba3699
AV		 2575 ixgbe_get_hw_control(adapter);
2576
021230d4
AV		 2577 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2578 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2579 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2580 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2581 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2582 } else {
2583 /* MSI only */
021230d4 2584 gpie = 0;
9a799d71 2585 }
021230d4
AV		 2586 /* XXX: to interrupt immediately for EICS writes, enable this */
2587 /* gpie |= IXGBE_GPIE_EIMEN; */
2588 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2589 }
2590
021230d4
AV		 2591 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2592 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2593 * specifically only auto mask tx and rx interrupts */
2594 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2595 }
9a799d71 2596
0befdb3e
JB		 2597 /* Enable fan failure interrupt if media type is copper */
2598 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2599 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2600 gpie |= IXGBE_SDP1_GPIEN;
2601 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2602 }
2603
e8e26350
PW		 2604 if (hw->mac.type == ixgbe_mac_82599EB) {
2605 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2606 gpie |= IXGBE_SDP1_GPIEN;
2607 gpie |= IXGBE_SDP2_GPIEN;
2608 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2609 }
2610
63f39bd1
YZ		 2611#ifdef IXGBE_FCOE
2612 /* adjust max frame to be able to do baby jumbo for FCoE */
f34c5c82 2613 if ((netdev->features & NETIF_F_FCOE_MTU) &&
63f39bd1
YZ		 2614 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2615 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2616
2617#endif /* IXGBE_FCOE */
021230d4 2618 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2619 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2620 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2621 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2622
2623 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2624 }
2625
2626 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 2627 j = adapter->tx_ring[i].reg_idx;
2628 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2629 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2630 txdctl |= (8 << 16);
e8e26350
PW		 2631 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2632 }
2633
2634 if (hw->mac.type == ixgbe_mac_82599EB) {
2635 /* DMATXCTL.EN must be set after all Tx queue config is done */
2636 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2637 dmatxctl |= IXGBE_DMATXCTL_TE;
2638 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2639 }
2640 for (i = 0; i < adapter->num_tx_queues; i++) {
2641 j = adapter->tx_ring[i].reg_idx;
2642 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2643 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2644 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 2645 }
2646
e8e26350 2647 for (i = 0; i < num_rx_rings; i++) {
021230d4
AV		 2648 j = adapter->rx_ring[i].reg_idx;
2649 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2650 /* enable PTHRESH=32 descriptors (half the internal cache)
2651 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2652 * this also removes a pesky rx_no_buffer_count increment */
2653 rxdctl |= 0x0020;
9a799d71 2654 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2655 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2656 if (hw->mac.type == ixgbe_mac_82599EB)
2657 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2658 }
2659 /* enable all receives */
2660 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2661 if (hw->mac.type == ixgbe_mac_82598EB)
2662 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2663 else
2664 rxdctl |= IXGBE_RXCTRL_RXEN;
2665 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2666
2667 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2668 ixgbe_configure_msix(adapter);
2669 else
2670 ixgbe_configure_msi_and_legacy(adapter);
2671
2672 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2673 ixgbe_napi_enable_all(adapter);
2674
2675 /* clear any pending interrupts, may auto mask */
2676 IXGBE_READ_REG(hw, IXGBE_EICR);
2677
9a799d71
AK		 2678 ixgbe_irq_enable(adapter);
2679
bf069c97
DS		 2680 /*
2681 * If this adapter has a fan, check to see if we had a failure
2682 * before we enabled the interrupt.
2683 */
2684 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2685 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2686 if (esdp & IXGBE_ESDP_SDP1)
2687 DPRINTK(DRV, CRIT,
2688 "Fan has stopped, replace the adapter\n");
2689 }
2690
e8e26350
PW		 2691 /*
2692 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 2693 * arrived before interrupts were enabled but after probe. Such
2694 * devices wouldn't have their type identified yet. We need to
2695 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 2696 * If we're not hot-pluggable SFP+, we just need to configure link
2697 * and bring it up.
2698 */
19343de2
DS		 2699 if (hw->phy.type == ixgbe_phy_unknown) {
2700 err = hw->phy.ops.identify(hw);
2701 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 2702 /*
2703 * Take the device down and schedule the sfp tasklet
2704 * which will unregister_netdev and log it.
2705 */
19343de2 2706 ixgbe_down(adapter);
5da43c1a 2707 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 2708 return err;
2709 }
e8e26350
PW		 2710 }
2711
2712 if (ixgbe_is_sfp(hw)) {
2713 ixgbe_sfp_link_config(adapter);
2714 } else {
2715 err = ixgbe_non_sfp_link_config(hw);
2716 if (err)
2717 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2718 }
0ecc061d 2719
c4cf55e5
PWJ		 2720 for (i = 0; i < adapter->num_tx_queues; i++)
2721 set_bit(__IXGBE_FDIR_INIT_DONE,
2722 &(adapter->tx_ring[i].reinit_state));
2723
1da100bb
PWJ		 2724 /* enable transmits */
2725 netif_tx_start_all_queues(netdev);
2726
9a799d71
AK		 2727 /* bring the link up in the watchdog, this could race with our first
2728 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 2729 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2730 adapter->link_check_timeout = jiffies;
9a799d71
AK		 2731 mod_timer(&adapter->watchdog_timer, jiffies);
2732 return 0;
2733}
2734
d4f80882
AV		 2735void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2736{
2737 WARN_ON(in_interrupt());
2738 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2739 msleep(1);
2740 ixgbe_down(adapter);
2741 ixgbe_up(adapter);
2742 clear_bit(__IXGBE_RESETTING, &adapter->state);
2743}
2744
9a799d71
AK		 2745int ixgbe_up(struct ixgbe_adapter *adapter)
2746{
2747 /* hardware has been reset, we need to reload some things */
2748 ixgbe_configure(adapter);
2749
2750 return ixgbe_up_complete(adapter);
2751}
2752
2753void ixgbe_reset(struct ixgbe_adapter *adapter)
2754{
c44ade9e 2755 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 2756 int err;
2757
2758 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 2759 switch (err) {
2760 case 0:
2761 case IXGBE_ERR_SFP_NOT_PRESENT:
2762 break;
2763 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2764 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2765 break;
794caeb2
PWJ		 2766 case IXGBE_ERR_EEPROM_VERSION:
2767 /* We are running on a pre-production device, log a warning */
2768 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2769 "adapter/LOM. Please be aware there may be issues "
2770 "associated with your hardware. If you are "
2771 "experiencing problems please contact your Intel or "
2772 "hardware representative who provided you with this "
2773 "hardware.\n");
2774 break;
da4dd0f7
PWJ		 2775 default:
2776 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2777 }
9a799d71
AK		 2778
2779 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2780 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2781}
2782
9a799d71
AK		 2783/**
2784 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2785 * @adapter: board private structure
2786 * @rx_ring: ring to free buffers from
2787 **/
2788static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2789 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2790{
2791 struct pci_dev *pdev = adapter->pdev;
2792 unsigned long size;
2793 unsigned int i;
2794
2795 /* Free all the Rx ring sk_buffs */
2796
2797 for (i = 0; i < rx_ring->count; i++) {
2798 struct ixgbe_rx_buffer *rx_buffer_info;
2799
2800 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2801 if (rx_buffer_info->dma) {
2802 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2803 rx_ring->rx_buf_len,
2804 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2805 rx_buffer_info->dma = 0;
2806 }
2807 if (rx_buffer_info->skb) {
f8212f97 2808 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 2809 rx_buffer_info->skb = NULL;
f8212f97
AD		 2810 do {
2811 struct sk_buff *this = skb;
2812 skb = skb->prev;
2813 dev_kfree_skb(this);
2814 } while (skb);
9a799d71
AK		 2815 }
2816 if (!rx_buffer_info->page)
2817 continue;
4f57ca6e
JB		 2818 if (rx_buffer_info->page_dma) {
2819 pci_unmap_page(pdev, rx_buffer_info->page_dma,
2820 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2821 rx_buffer_info->page_dma = 0;
2822 }
9a799d71
AK		 2823 put_page(rx_buffer_info->page);
2824 rx_buffer_info->page = NULL;
762f4c57 2825 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2826 }
2827
2828 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2829 memset(rx_ring->rx_buffer_info, 0, size);
2830
2831 /* Zero out the descriptor ring */
2832 memset(rx_ring->desc, 0, rx_ring->size);
2833
2834 rx_ring->next_to_clean = 0;
2835 rx_ring->next_to_use = 0;
2836
9891ca7c
JB		 2837 if (rx_ring->head)
2838 writel(0, adapter->hw.hw_addr + rx_ring->head);
2839 if (rx_ring->tail)
2840 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 2841}
2842
2843/**
2844 * ixgbe_clean_tx_ring - Free Tx Buffers
2845 * @adapter: board private structure
2846 * @tx_ring: ring to be cleaned
2847 **/
2848static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2849 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2850{
2851 struct ixgbe_tx_buffer *tx_buffer_info;
2852 unsigned long size;
2853 unsigned int i;
2854
2855 /* Free all the Tx ring sk_buffs */
2856
2857 for (i = 0; i < tx_ring->count; i++) {
2858 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2859 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2860 }
2861
2862 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2863 memset(tx_ring->tx_buffer_info, 0, size);
2864
2865 /* Zero out the descriptor ring */
2866 memset(tx_ring->desc, 0, tx_ring->size);
2867
2868 tx_ring->next_to_use = 0;
2869 tx_ring->next_to_clean = 0;
2870
9891ca7c
JB		 2871 if (tx_ring->head)
2872 writel(0, adapter->hw.hw_addr + tx_ring->head);
2873 if (tx_ring->tail)
2874 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 2875}
2876
2877/**
021230d4 2878 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2879 * @adapter: board private structure
2880 **/
021230d4 2881static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2882{
2883 int i;
2884
021230d4
AV		 2885 for (i = 0; i < adapter->num_rx_queues; i++)
2886 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2887}
2888
2889/**
021230d4 2890 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2891 * @adapter: board private structure
2892 **/
021230d4 2893static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2894{
2895 int i;
2896
021230d4
AV		 2897 for (i = 0; i < adapter->num_tx_queues; i++)
2898 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2899}
2900
2901void ixgbe_down(struct ixgbe_adapter *adapter)
2902{
2903 struct net_device *netdev = adapter->netdev;
7f821875 2904 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2905 u32 rxctrl;
7f821875
JB		 2906 u32 txdctl;
2907 int i, j;
9a799d71
AK		 2908
2909 /* signal that we are down to the interrupt handler */
2910 set_bit(__IXGBE_DOWN, &adapter->state);
2911
2912 /* disable receives */
7f821875
JB		 2913 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2914 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 2915
2916 netif_tx_disable(netdev);
2917
7f821875 2918 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 2919 msleep(10);
2920
7f821875
JB		 2921 netif_tx_stop_all_queues(netdev);
2922
9a799d71
AK		 2923 ixgbe_irq_disable(adapter);
2924
021230d4 2925 ixgbe_napi_disable_all(adapter);
7f821875 2926
9a799d71 2927 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 2928 cancel_work_sync(&adapter->watchdog_task);
9a799d71 2929
c4cf55e5
PWJ		 2930 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2931 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2932 cancel_work_sync(&adapter->fdir_reinit_task);
2933
7f821875
JB		 2934 /* disable transmits in the hardware now that interrupts are off */
2935 for (i = 0; i < adapter->num_tx_queues; i++) {
2936 j = adapter->tx_ring[i].reg_idx;
2937 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2938 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2939 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2940 }
88512539
PW		 2941 /* Disable the Tx DMA engine on 82599 */
2942 if (hw->mac.type == ixgbe_mac_82599EB)
2943 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2944 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2945 ~IXGBE_DMATXCTL_TE));
7f821875 2946
9a799d71 2947 netif_carrier_off(netdev);
9a799d71 2948
6f4a0e45
PL		 2949 if (!pci_channel_offline(adapter->pdev))
2950 ixgbe_reset(adapter);
9a799d71
AK		 2951 ixgbe_clean_all_tx_rings(adapter);
2952 ixgbe_clean_all_rx_rings(adapter);
2953
5dd2d332 2954#ifdef CONFIG_IXGBE_DCA
96b0e0f6 2955 /* since we reset the hardware DCA settings were cleared */
e35ec126 2956 ixgbe_setup_dca(adapter);
96b0e0f6 2957#endif
9a799d71
AK		 2958}
2959
9a799d71 2960/**
021230d4
AV		 2961 * ixgbe_poll - NAPI Rx polling callback
2962 * @napi: structure for representing this polling device
2963 * @budget: how many packets driver is allowed to clean
2964 *
2965 * This function is used for legacy and MSI, NAPI mode
9a799d71 2966 **/
021230d4 2967static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2968{
9a1a69ad
JB		 2969 struct ixgbe_q_vector *q_vector =
2970 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2971 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 2972 int tx_clean_complete, work_done = 0;
9a799d71 2973
5dd2d332 2974#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 2975 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2976 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2977 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2978 }
2979#endif
2980
fe49f04a 2981 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
78b6f4ce 2982 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
9a799d71 2983
9a1a69ad 2984 if (!tx_clean_complete)
d2c7ddd6
DM		 2985 work_done = budget;
2986
53e52c72
DM		 2987 /* If budget not fully consumed, exit the polling mode */
2988 if (work_done < budget) {
288379f0 2989 napi_complete(napi);
509ee935 2990 if (adapter->itr_setting & 1)
f494e8fa 2991 ixgbe_set_itr(adapter);
d4f80882 2992 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 2993 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 2994 }
9a799d71
AK		 2995 return work_done;
2996}
2997
2998/**
2999 * ixgbe_tx_timeout - Respond to a Tx Hang
3000 * @netdev: network interface device structure
3001 **/
3002static void ixgbe_tx_timeout(struct net_device *netdev)
3003{
3004 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3005
3006 /* Do the reset outside of interrupt context */
3007 schedule_work(&adapter->reset_task);
3008}
3009
3010static void ixgbe_reset_task(struct work_struct *work)
3011{
3012 struct ixgbe_adapter *adapter;
3013 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3014
2f90b865
AD		 3015 /* If we're already down or resetting, just bail */
3016 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3017 test_bit(__IXGBE_RESETTING, &adapter->state))
3018 return;
3019
9a799d71
AK		 3020 adapter->tx_timeout_count++;
3021
d4f80882 3022 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3023}
3024
bc97114d
PWJ		 3025#ifdef CONFIG_IXGBE_DCB
3026static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3027{
bc97114d 3028 bool ret = false;
0cefafad 3029 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3030
0cefafad
JB		 3031 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3032 return ret;
3033
3034 f->mask = 0x7 << 3;
3035 adapter->num_rx_queues = f->indices;
3036 adapter->num_tx_queues = f->indices;
3037 ret = true;
2f90b865 3038
bc97114d
PWJ		 3039 return ret;
3040}
3041#endif
3042
4df10466
JB		 3043/**
3044 * ixgbe_set_rss_queues: Allocate queues for RSS
3045 * @adapter: board private structure to initialize
3046 *
3047 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3048 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3049 *
3050 **/
bc97114d
PWJ		 3051static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3052{
3053 bool ret = false;
0cefafad 3054 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3055
3056 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3057 f->mask = 0xF;
3058 adapter->num_rx_queues = f->indices;
3059 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3060 ret = true;
3061 } else {
bc97114d 3062 ret = false;
b9804972
JB		 3063 }
3064
bc97114d
PWJ		 3065 return ret;
3066}
3067
c4cf55e5
PWJ		 3068/**
3069 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3070 * @adapter: board private structure to initialize
3071 *
3072 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3073 * to the original CPU that initiated the Tx session. This runs in addition
3074 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3075 * Rx load across CPUs using RSS.
3076 *
3077 **/
3078static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3079{
3080 bool ret = false;
3081 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3082
3083 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3084 f_fdir->mask = 0;
3085
3086 /* Flow Director must have RSS enabled */
3087 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3088 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3089 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3090 adapter->num_tx_queues = f_fdir->indices;
3091 adapter->num_rx_queues = f_fdir->indices;
3092 ret = true;
3093 } else {
3094 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3095 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3096 }
3097 return ret;
3098}
3099
0331a832
YZ		 3100#ifdef IXGBE_FCOE
3101/**
3102 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3103 * @adapter: board private structure to initialize
3104 *
3105 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3106 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3107 * rx queues out of the max number of rx queues, instead, it is used as the
3108 * index of the first rx queue used by FCoE.
3109 *
3110 **/
3111static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3112{
3113 bool ret = false;
3114 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3115
3116 f->indices = min((int)num_online_cpus(), f->indices);
3117 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 3118 adapter->num_rx_queues = 1;
3119 adapter->num_tx_queues = 1;
0331a832
YZ		 3120#ifdef CONFIG_IXGBE_DCB
3121 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6 3122 DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
0331a832
YZ		 3123 ixgbe_set_dcb_queues(adapter);
3124 }
3125#endif
3126 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8de8b2e6 3127 DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
8faa2a78
YZ		 3128 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3129 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3130 ixgbe_set_fdir_queues(adapter);
3131 else
3132 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 3133 }
3134 /* adding FCoE rx rings to the end */
3135 f->mask = adapter->num_rx_queues;
3136 adapter->num_rx_queues += f->indices;
8de8b2e6 3137 adapter->num_tx_queues += f->indices;
0331a832
YZ		 3138
3139 ret = true;
3140 }
3141
3142 return ret;
3143}
3144
3145#endif /* IXGBE_FCOE */
4df10466
JB		 3146/*
3147 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3148 * @adapter: board private structure to initialize
3149 *
3150 * This is the top level queue allocation routine. The order here is very
3151 * important, starting with the "most" number of features turned on at once,
3152 * and ending with the smallest set of features. This way large combinations
3153 * can be allocated if they're turned on, and smaller combinations are the
3154 * fallthrough conditions.
3155 *
3156 **/
bc97114d
PWJ		 3157static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3158{
0331a832
YZ		 3159#ifdef IXGBE_FCOE
3160 if (ixgbe_set_fcoe_queues(adapter))
3161 goto done;
3162
3163#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3164#ifdef CONFIG_IXGBE_DCB
3165 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 3166 goto done;
bc97114d
PWJ		 3167
3168#endif
c4cf55e5
PWJ		 3169 if (ixgbe_set_fdir_queues(adapter))
3170 goto done;
3171
bc97114d 3172 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 3173 goto done;
3174
3175 /* fallback to base case */
3176 adapter->num_rx_queues = 1;
3177 adapter->num_tx_queues = 1;
3178
3179done:
3180 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3181 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 3182}
3183
021230d4 3184static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 3185 int vectors)
021230d4
AV		 3186{
3187 int err, vector_threshold;
3188
3189 /* We'll want at least 3 (vector_threshold):
3190 * 1) TxQ[0] Cleanup
3191 * 2) RxQ[0] Cleanup
3192 * 3) Other (Link Status Change, etc.)
3193 * 4) TCP Timer (optional)
3194 */
3195 vector_threshold = MIN_MSIX_COUNT;
3196
3197 /* The more we get, the more we will assign to Tx/Rx Cleanup
3198 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3199 * Right now, we simply care about how many we'll get; we'll
3200 * set them up later while requesting irq's.
3201 */
3202 while (vectors >= vector_threshold) {
3203 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 3204 vectors);
021230d4
AV		 3205 if (!err) /* Success in acquiring all requested vectors. */
3206 break;
3207 else if (err < 0)
3208 vectors = 0; /* Nasty failure, quit now */
3209 else /* err == number of vectors we should try again with */
3210 vectors = err;
3211 }
3212
3213 if (vectors < vector_threshold) {
3214 /* Can't allocate enough MSI-X interrupts? Oh well.
3215 * This just means we'll go with either a single MSI
3216 * vector or fall back to legacy interrupts.
3217 */
3218 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3219 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3220 kfree(adapter->msix_entries);
3221 adapter->msix_entries = NULL;
021230d4
AV		 3222 } else {
3223 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 3224 /*
3225 * Adjust for only the vectors we'll use, which is minimum
3226 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3227 * vectors we were allocated.
3228 */
3229 adapter->num_msix_vectors = min(vectors,
3230 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 3231 }
3232}
3233
021230d4 3234/**
bc97114d 3235 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 3236 * @adapter: board private structure to initialize
3237 *
bc97114d
PWJ		 3238 * Cache the descriptor ring offsets for RSS to the assigned rings.
3239 *
021230d4 3240 **/
bc97114d 3241static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 3242{
bc97114d
PWJ		 3243 int i;
3244 bool ret = false;
3245
3246 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3247 for (i = 0; i < adapter->num_rx_queues; i++)
3248 adapter->rx_ring[i].reg_idx = i;
3249 for (i = 0; i < adapter->num_tx_queues; i++)
3250 adapter->tx_ring[i].reg_idx = i;
3251 ret = true;
3252 } else {
3253 ret = false;
3254 }
3255
3256 return ret;
3257}
3258
3259#ifdef CONFIG_IXGBE_DCB
3260/**
3261 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3262 * @adapter: board private structure to initialize
3263 *
3264 * Cache the descriptor ring offsets for DCB to the assigned rings.
3265 *
3266 **/
3267static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3268{
3269 int i;
3270 bool ret = false;
3271 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3272
3273 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3274 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 3275 /* the number of queues is assumed to be symmetric */
3276 for (i = 0; i < dcb_i; i++) {
3277 adapter->rx_ring[i].reg_idx = i << 3;
3278 adapter->tx_ring[i].reg_idx = i << 2;
3279 }
bc97114d 3280 ret = true;
e8e26350 3281 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 3282 if (dcb_i == 8) {
3283 /*
3284 * Tx TC0 starts at: descriptor queue 0
3285 * Tx TC1 starts at: descriptor queue 32
3286 * Tx TC2 starts at: descriptor queue 64
3287 * Tx TC3 starts at: descriptor queue 80
3288 * Tx TC4 starts at: descriptor queue 96
3289 * Tx TC5 starts at: descriptor queue 104
3290 * Tx TC6 starts at: descriptor queue 112
3291 * Tx TC7 starts at: descriptor queue 120
3292 *
3293 * Rx TC0-TC7 are offset by 16 queues each
3294 */
3295 for (i = 0; i < 3; i++) {
3296 adapter->tx_ring[i].reg_idx = i << 5;
3297 adapter->rx_ring[i].reg_idx = i << 4;
3298 }
3299 for ( ; i < 5; i++) {
3300 adapter->tx_ring[i].reg_idx =
3301 ((i + 2) << 4);
3302 adapter->rx_ring[i].reg_idx = i << 4;
3303 }
3304 for ( ; i < dcb_i; i++) {
3305 adapter->tx_ring[i].reg_idx =
3306 ((i + 8) << 3);
3307 adapter->rx_ring[i].reg_idx = i << 4;
3308 }
3309
3310 ret = true;
3311 } else if (dcb_i == 4) {
3312 /*
3313 * Tx TC0 starts at: descriptor queue 0
3314 * Tx TC1 starts at: descriptor queue 64
3315 * Tx TC2 starts at: descriptor queue 96
3316 * Tx TC3 starts at: descriptor queue 112
3317 *
3318 * Rx TC0-TC3 are offset by 32 queues each
3319 */
3320 adapter->tx_ring[0].reg_idx = 0;
3321 adapter->tx_ring[1].reg_idx = 64;
3322 adapter->tx_ring[2].reg_idx = 96;
3323 adapter->tx_ring[3].reg_idx = 112;
3324 for (i = 0 ; i < dcb_i; i++)
3325 adapter->rx_ring[i].reg_idx = i << 5;
3326
3327 ret = true;
3328 } else {
3329 ret = false;
e8e26350 3330 }
bc97114d
PWJ		 3331 } else {
3332 ret = false;
021230d4 3333 }
bc97114d
PWJ		 3334 } else {
3335 ret = false;
021230d4 3336 }
bc97114d
PWJ		 3337
3338 return ret;
3339}
3340#endif
3341
c4cf55e5
PWJ		 3342/**
3343 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3344 * @adapter: board private structure to initialize
3345 *
3346 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3347 *
3348 **/
3349static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3350{
3351 int i;
3352 bool ret = false;
3353
3354 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3355 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3356 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3357 for (i = 0; i < adapter->num_rx_queues; i++)
3358 adapter->rx_ring[i].reg_idx = i;
3359 for (i = 0; i < adapter->num_tx_queues; i++)
3360 adapter->tx_ring[i].reg_idx = i;
3361 ret = true;
3362 }
3363
3364 return ret;
3365}
3366
0331a832
YZ		 3367#ifdef IXGBE_FCOE
3368/**
3369 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3370 * @adapter: board private structure to initialize
3371 *
3372 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3373 *
3374 */
3375static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3376{
8de8b2e6 3377 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 3378 bool ret = false;
3379 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3380
3381 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3382#ifdef CONFIG_IXGBE_DCB
3383 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 3384 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3385
0331a832 3386 ixgbe_cache_ring_dcb(adapter);
8de8b2e6
YZ		 3387 /* find out queues in TC for FCoE */
3388 fcoe_rx_i = adapter->rx_ring[fcoe->tc].reg_idx + 1;
3389 fcoe_tx_i = adapter->tx_ring[fcoe->tc].reg_idx + 1;
3390 /*
3391 * In 82599, the number of Tx queues for each traffic
3392 * class for both 8-TC and 4-TC modes are:
3393 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3394 * 8 TCs: 32 32 16 16 8 8 8 8
3395 * 4 TCs: 64 64 32 32
3396 * We have max 8 queues for FCoE, where 8 the is
3397 * FCoE redirection table size. If TC for FCoE is
3398 * less than or equal to TC3, we have enough queues
3399 * to add max of 8 queues for FCoE, so we start FCoE
3400 * tx descriptor from the next one, i.e., reg_idx + 1.
3401 * If TC for FCoE is above TC3, implying 8 TC mode,
3402 * and we need 8 for FCoE, we have to take all queues
3403 * in that traffic class for FCoE.
3404 */
3405 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3406 fcoe_tx_i--;
0331a832
YZ		 3407 }
3408#endif /* CONFIG_IXGBE_DCB */
3409 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 3410 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3411 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3412 ixgbe_cache_ring_fdir(adapter);
3413 else
3414 ixgbe_cache_ring_rss(adapter);
3415
8de8b2e6
YZ		 3416 fcoe_rx_i = f->mask;
3417 fcoe_tx_i = f->mask;
3418 }
3419 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3420 adapter->rx_ring[f->mask + i].reg_idx = fcoe_rx_i;
3421 adapter->tx_ring[f->mask + i].reg_idx = fcoe_tx_i;
0331a832 3422 }
0331a832
YZ		 3423 ret = true;
3424 }
3425 return ret;
3426}
3427
3428#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3429/**
3430 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3431 * @adapter: board private structure to initialize
3432 *
3433 * Once we know the feature-set enabled for the device, we'll cache
3434 * the register offset the descriptor ring is assigned to.
3435 *
3436 * Note, the order the various feature calls is important. It must start with
3437 * the "most" features enabled at the same time, then trickle down to the
3438 * least amount of features turned on at once.
3439 **/
3440static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3441{
3442 /* start with default case */
3443 adapter->rx_ring[0].reg_idx = 0;
3444 adapter->tx_ring[0].reg_idx = 0;
3445
0331a832
YZ		 3446#ifdef IXGBE_FCOE
3447 if (ixgbe_cache_ring_fcoe(adapter))
3448 return;
3449
3450#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3451#ifdef CONFIG_IXGBE_DCB
3452 if (ixgbe_cache_ring_dcb(adapter))
3453 return;
3454
3455#endif
c4cf55e5
PWJ		 3456 if (ixgbe_cache_ring_fdir(adapter))
3457 return;
3458
bc97114d
PWJ		 3459 if (ixgbe_cache_ring_rss(adapter))
3460 return;
021230d4
AV		 3461}
3462
9a799d71
AK		 3463/**
3464 * ixgbe_alloc_queues - Allocate memory for all rings
3465 * @adapter: board private structure to initialize
3466 *
3467 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 3468 * number of queues at compile-time. The polling_netdev array is
3469 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 3470 **/
2f90b865 3471static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 3472{
3473 int i;
3474
3475 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 3476 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 3477 if (!adapter->tx_ring)
021230d4 3478 goto err_tx_ring_allocation;
9a799d71
AK		 3479
3480 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 3481 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 3482 if (!adapter->rx_ring)
3483 goto err_rx_ring_allocation;
9a799d71 3484
021230d4 3485 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 3486 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 3487 adapter->tx_ring[i].queue_index = i;
3488 }
b9804972 3489
9a799d71 3490 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 3491 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 3492 adapter->rx_ring[i].queue_index = i;
3493 }
3494
3495 ixgbe_cache_ring_register(adapter);
3496
3497 return 0;
3498
3499err_rx_ring_allocation:
3500 kfree(adapter->tx_ring);
3501err_tx_ring_allocation:
3502 return -ENOMEM;
3503}
3504
3505/**
3506 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3507 * @adapter: board private structure to initialize
3508 *
3509 * Attempt to configure the interrupts using the best available
3510 * capabilities of the hardware and the kernel.
3511 **/
feea6a57 3512static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 3513{
8be0e467 3514 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 3515 int err = 0;
3516 int vector, v_budget;
3517
3518 /*
3519 * It's easy to be greedy for MSI-X vectors, but it really
3520 * doesn't do us much good if we have a lot more vectors
3521 * than CPU's. So let's be conservative and only ask for
3522 * (roughly) twice the number of vectors as there are CPU's.
3523 */
3524 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
b4617240 3525 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
021230d4
AV		 3526
3527 /*
3528 * At the same time, hardware can only support a maximum of
8be0e467
PW		 3529 * hw.mac->max_msix_vectors vectors. With features
3530 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3531 * descriptor queues supported by our device. Thus, we cap it off in
3532 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3533 */
8be0e467 3534 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3535
3536 /* A failure in MSI-X entry allocation isn't fatal, but it does
3537 * mean we disable MSI-X capabilities of the adapter. */
3538 adapter->msix_entries = kcalloc(v_budget,
b4617240 3539 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 3540 if (adapter->msix_entries) {
3541 for (vector = 0; vector < v_budget; vector++)
3542 adapter->msix_entries[vector].entry = vector;
021230d4 3543
7a921c93 3544 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 3545
7a921c93
AD		 3546 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3547 goto out;
3548 }
021230d4 3549
7a921c93
AD		 3550 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3551 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 3552 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3553 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3554 adapter->atr_sample_rate = 0;
7a921c93 3555 ixgbe_set_num_queues(adapter);
021230d4 3556
021230d4
AV		 3557 err = pci_enable_msi(adapter->pdev);
3558 if (!err) {
3559 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3560 } else {
3561 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 3562 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 3563 /* reset err */
3564 err = 0;
3565 }
3566
3567out:
021230d4
AV		 3568 return err;
3569}
3570
7a921c93
AD		 3571/**
3572 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3573 * @adapter: board private structure to initialize
3574 *
3575 * We allocate one q_vector per queue interrupt. If allocation fails we
3576 * return -ENOMEM.
3577 **/
3578static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3579{
3580 int q_idx, num_q_vectors;
3581 struct ixgbe_q_vector *q_vector;
3582 int napi_vectors;
3583 int (*poll)(struct napi_struct *, int);
3584
3585 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3586 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3587 napi_vectors = adapter->num_rx_queues;
91281fd3 3588 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 3589 } else {
3590 num_q_vectors = 1;
3591 napi_vectors = 1;
3592 poll = &ixgbe_poll;
3593 }
3594
3595 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3596 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3597 if (!q_vector)
3598 goto err_out;
3599 q_vector->adapter = adapter;
7a921c93 3600 q_vector->eitr = adapter->eitr_param;
fe49f04a 3601 q_vector->v_idx = q_idx;
91281fd3 3602 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 3603 adapter->q_vector[q_idx] = q_vector;
3604 }
3605
3606 return 0;
3607
3608err_out:
3609 while (q_idx) {
3610 q_idx--;
3611 q_vector = adapter->q_vector[q_idx];
3612 netif_napi_del(&q_vector->napi);
3613 kfree(q_vector);
3614 adapter->q_vector[q_idx] = NULL;
3615 }
3616 return -ENOMEM;
3617}
3618
3619/**
3620 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3621 * @adapter: board private structure to initialize
3622 *
3623 * This function frees the memory allocated to the q_vectors. In addition if
3624 * NAPI is enabled it will delete any references to the NAPI struct prior
3625 * to freeing the q_vector.
3626 **/
3627static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3628{
3629 int q_idx, num_q_vectors;
7a921c93 3630
91281fd3 3631 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 3632 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 3633 else
7a921c93 3634 num_q_vectors = 1;
7a921c93
AD		 3635
3636 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3637 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 3638 adapter->q_vector[q_idx] = NULL;
91281fd3 3639 netif_napi_del(&q_vector->napi);
7a921c93
AD		 3640 kfree(q_vector);
3641 }
3642}
3643
7b25cdba 3644static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 3645{
3646 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3647 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3648 pci_disable_msix(adapter->pdev);
3649 kfree(adapter->msix_entries);
3650 adapter->msix_entries = NULL;
3651 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3652 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3653 pci_disable_msi(adapter->pdev);
3654 }
3655 return;
3656}
3657
3658/**
3659 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3660 * @adapter: board private structure to initialize
3661 *
3662 * We determine which interrupt scheme to use based on...
3663 * - Kernel support (MSI, MSI-X)
3664 * - which can be user-defined (via MODULE_PARAM)
3665 * - Hardware queue count (num_*_queues)
3666 * - defined by miscellaneous hardware support/features (RSS, etc.)
3667 **/
2f90b865 3668int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 3669{
3670 int err;
3671
3672 /* Number of supported queues */
3673 ixgbe_set_num_queues(adapter);
3674
021230d4
AV		 3675 err = ixgbe_set_interrupt_capability(adapter);
3676 if (err) {
3677 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3678 goto err_set_interrupt;
9a799d71
AK		 3679 }
3680
7a921c93
AD		 3681 err = ixgbe_alloc_q_vectors(adapter);
3682 if (err) {
3683 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3684 "vectors\n");
3685 goto err_alloc_q_vectors;
3686 }
3687
3688 err = ixgbe_alloc_queues(adapter);
3689 if (err) {
3690 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3691 goto err_alloc_queues;
3692 }
3693
021230d4 3694 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 3695 "Tx Queue count = %u\n",
3696 (adapter->num_rx_queues > 1) ? "Enabled" :
3697 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 3698
3699 set_bit(__IXGBE_DOWN, &adapter->state);
3700
9a799d71 3701 return 0;
021230d4 3702
7a921c93
AD		 3703err_alloc_queues:
3704 ixgbe_free_q_vectors(adapter);
3705err_alloc_q_vectors:
3706 ixgbe_reset_interrupt_capability(adapter);
021230d4 3707err_set_interrupt:
7a921c93
AD		 3708 return err;
3709}
3710
3711/**
3712 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3713 * @adapter: board private structure to clear interrupt scheme on
3714 *
3715 * We go through and clear interrupt specific resources and reset the structure
3716 * to pre-load conditions
3717 **/
3718void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3719{
021230d4
AV		 3720 kfree(adapter->tx_ring);
3721 kfree(adapter->rx_ring);
7a921c93
AD		 3722 adapter->tx_ring = NULL;
3723 adapter->rx_ring = NULL;
3724
3725 ixgbe_free_q_vectors(adapter);
3726 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 3727}
3728
c4900be0
DS		 3729/**
3730 * ixgbe_sfp_timer - worker thread to find a missing module
3731 * @data: pointer to our adapter struct
3732 **/
3733static void ixgbe_sfp_timer(unsigned long data)
3734{
3735 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3736
4df10466
JB		 3737 /*
3738 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 3739 * delays that sfp+ detection requires
3740 */
3741 schedule_work(&adapter->sfp_task);
3742}
3743
3744/**
3745 * ixgbe_sfp_task - worker thread to find a missing module
3746 * @work: pointer to work_struct containing our data
3747 **/
3748static void ixgbe_sfp_task(struct work_struct *work)
3749{
3750 struct ixgbe_adapter *adapter = container_of(work,
3751 struct ixgbe_adapter,
3752 sfp_task);
3753 struct ixgbe_hw *hw = &adapter->hw;
3754
3755 if ((hw->phy.type == ixgbe_phy_nl) &&
3756 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3757 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 3758 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 3759 goto reschedule;
3760 ret = hw->phy.ops.reset(hw);
3761 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 3762 dev_err(&adapter->pdev->dev, "failed to initialize "
3763 "because an unsupported SFP+ module type "
3764 "was detected.\n"
3765 "Reload the driver after installing a "
3766 "supported module.\n");
c4900be0
DS		 3767 unregister_netdev(adapter->netdev);
3768 } else {
3769 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3770 hw->phy.sfp_type);
3771 }
3772 /* don't need this routine any more */
3773 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3774 }
3775 return;
3776reschedule:
3777 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3778 mod_timer(&adapter->sfp_timer,
3779 round_jiffies(jiffies + (2 * HZ)));
3780}
3781
9a799d71
AK		 3782/**
3783 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3784 * @adapter: board private structure to initialize
3785 *
3786 * ixgbe_sw_init initializes the Adapter private data structure.
3787 * Fields are initialized based on PCI device information and
3788 * OS network device settings (MTU size).
3789 **/
3790static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3791{
3792 struct ixgbe_hw *hw = &adapter->hw;
3793 struct pci_dev *pdev = adapter->pdev;
021230d4 3794 unsigned int rss;
7a6b6f51 3795#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3796 int j;
3797 struct tc_configuration *tc;
3798#endif
021230d4 3799
c44ade9e
JB		 3800 /* PCI config space info */
3801
3802 hw->vendor_id = pdev->vendor;
3803 hw->device_id = pdev->device;
3804 hw->revision_id = pdev->revision;
3805 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3806 hw->subsystem_device_id = pdev->subsystem_device;
3807
021230d4
AV		 3808 /* Set capability flags */
3809 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3810 adapter->ring_feature[RING_F_RSS].indices = rss;
3811 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 3812 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 3813 if (hw->mac.type == ixgbe_mac_82598EB) {
3814 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3815 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 3816 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 3817 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 3818 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 3819 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3820 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
c4cf55e5
PWJ		 3821 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3822 adapter->ring_feature[RING_F_FDIR].indices =
3823 IXGBE_MAX_FDIR_INDICES;
3824 adapter->atr_sample_rate = 20;
3825 adapter->fdir_pballoc = 0;
eacd73f7 3826#ifdef IXGBE_FCOE
0d551589
YZ		 3827 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3828 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3829 adapter->ring_feature[RING_F_FCOE].indices = 0;
6ee16520
YZ		 3830 /* Default traffic class to use for FCoE */
3831 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
eacd73f7 3832#endif /* IXGBE_FCOE */
f8212f97 3833 }
2f90b865 3834
7a6b6f51 3835#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3836 /* Configure DCB traffic classes */
3837 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3838 tc = &adapter->dcb_cfg.tc_config[j];
3839 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3840 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3841 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3842 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3843 tc->dcb_pfc = pfc_disabled;
3844 }
3845 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3846 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3847 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 3848 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 3849 adapter->dcb_cfg.round_robin_enable = false;
3850 adapter->dcb_set_bitmap = 0x00;
3851 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3852 adapter->ring_feature[RING_F_DCB].indices);
3853
3854#endif
9a799d71
AK		 3855
3856 /* default flow control settings */
cd7664f6 3857 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 3858 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 3859#ifdef CONFIG_DCB
3860 adapter->last_lfc_mode = hw->fc.current_mode;
3861#endif
2b9ade93
JB		 3862 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3863 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3864 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3865 hw->fc.send_xon = true;
71fd570b 3866 hw->fc.disable_fc_autoneg = false;
9a799d71 3867
30efa5a3
JB		 3868 /* enable itr by default in dynamic mode */
3869 adapter->itr_setting = 1;
3870 adapter->eitr_param = 20000;
3871
3872 /* set defaults for eitr in MegaBytes */
3873 adapter->eitr_low = 10;
3874 adapter->eitr_high = 20;
3875
3876 /* set default ring sizes */
3877 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3878 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3879
9a799d71 3880 /* initialize eeprom parameters */
c44ade9e 3881 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 3882 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3883 return -EIO;
3884 }
3885
021230d4 3886 /* enable rx csum by default */
9a799d71
AK		 3887 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3888
9a799d71
AK		 3889 set_bit(__IXGBE_DOWN, &adapter->state);
3890
3891 return 0;
3892}
3893
3894/**
3895 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3896 * @adapter: board private structure
3a581073 3897 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3898 *
3899 * Return 0 on success, negative on failure
3900 **/
3901int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 3902 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3903{
3904 struct pci_dev *pdev = adapter->pdev;
3905 int size;
3906
3a581073
JB		 3907 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3908 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 3909 if (!tx_ring->tx_buffer_info)
3910 goto err;
3a581073 3911 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 3912
3913 /* round up to nearest 4K */
12207e49 3914 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 3915 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 3916
3a581073
JB		 3917 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3918 &tx_ring->dma);
e01c31a5
JB		 3919 if (!tx_ring->desc)
3920 goto err;
9a799d71 3921
3a581073
JB		 3922 tx_ring->next_to_use = 0;
3923 tx_ring->next_to_clean = 0;
3924 tx_ring->work_limit = tx_ring->count;
9a799d71 3925 return 0;
e01c31a5
JB		 3926
3927err:
3928 vfree(tx_ring->tx_buffer_info);
3929 tx_ring->tx_buffer_info = NULL;
3930 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3931 "descriptor ring\n");
3932 return -ENOMEM;
9a799d71
AK		 3933}
3934
69888674
AD		 3935/**
3936 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3937 * @adapter: board private structure
3938 *
3939 * If this function returns with an error, then it's possible one or
3940 * more of the rings is populated (while the rest are not). It is the
3941 * callers duty to clean those orphaned rings.
3942 *
3943 * Return 0 on success, negative on failure
3944 **/
3945static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3946{
3947 int i, err = 0;
3948
3949 for (i = 0; i < adapter->num_tx_queues; i++) {
3950 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3951 if (!err)
3952 continue;
3953 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3954 break;
3955 }
3956
3957 return err;
3958}
3959
9a799d71
AK		 3960/**
3961 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3962 * @adapter: board private structure
3a581073 3963 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3964 *
3965 * Returns 0 on success, negative on failure
3966 **/
3967int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 3968 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3969{
3970 struct pci_dev *pdev = adapter->pdev;
021230d4 3971 int size;
9a799d71 3972
3a581073
JB		 3973 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3974 rx_ring->rx_buffer_info = vmalloc(size);
3975 if (!rx_ring->rx_buffer_info) {
9a799d71 3976 DPRINTK(PROBE, ERR,
b4617240 3977 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 3978 goto alloc_failed;
9a799d71 3979 }
3a581073 3980 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 3981
9a799d71 3982 /* Round up to nearest 4K */
3a581073
JB		 3983 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3984 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 3985
3a581073 3986 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 3987
3a581073 3988 if (!rx_ring->desc) {
9a799d71 3989 DPRINTK(PROBE, ERR,
b4617240 3990 "Memory allocation failed for the rx desc ring\n");
3a581073 3991 vfree(rx_ring->rx_buffer_info);
177db6ff 3992 goto alloc_failed;
9a799d71
AK		 3993 }
3994
3a581073
JB		 3995 rx_ring->next_to_clean = 0;
3996 rx_ring->next_to_use = 0;
9a799d71
AK		 3997
3998 return 0;
177db6ff
MC		 3999
4000alloc_failed:
177db6ff 4001 return -ENOMEM;
9a799d71
AK		 4002}
4003
69888674
AD		 4004/**
4005 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4006 * @adapter: board private structure
4007 *
4008 * If this function returns with an error, then it's possible one or
4009 * more of the rings is populated (while the rest are not). It is the
4010 * callers duty to clean those orphaned rings.
4011 *
4012 * Return 0 on success, negative on failure
4013 **/
4014
4015static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4016{
4017 int i, err = 0;
4018
4019 for (i = 0; i < adapter->num_rx_queues; i++) {
4020 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4021 if (!err)
4022 continue;
4023 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4024 break;
4025 }
4026
4027 return err;
4028}
4029
9a799d71
AK		 4030/**
4031 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4032 * @adapter: board private structure
4033 * @tx_ring: Tx descriptor ring for a specific queue
4034 *
4035 * Free all transmit software resources
4036 **/
c431f97e
JB		 4037void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4038 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4039{
4040 struct pci_dev *pdev = adapter->pdev;
4041
4042 ixgbe_clean_tx_ring(adapter, tx_ring);
4043
4044 vfree(tx_ring->tx_buffer_info);
4045 tx_ring->tx_buffer_info = NULL;
4046
4047 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4048
4049 tx_ring->desc = NULL;
4050}
4051
4052/**
4053 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4054 * @adapter: board private structure
4055 *
4056 * Free all transmit software resources
4057 **/
4058static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4059{
4060 int i;
4061
4062 for (i = 0; i < adapter->num_tx_queues; i++)
9891ca7c
JB		 4063 if (adapter->tx_ring[i].desc)
4064 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 4065}
4066
4067/**
b4617240 4068 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4069 * @adapter: board private structure
4070 * @rx_ring: ring to clean the resources from
4071 *
4072 * Free all receive software resources
4073 **/
c431f97e
JB		 4074void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4075 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4076{
4077 struct pci_dev *pdev = adapter->pdev;
4078
4079 ixgbe_clean_rx_ring(adapter, rx_ring);
4080
4081 vfree(rx_ring->rx_buffer_info);
4082 rx_ring->rx_buffer_info = NULL;
4083
4084 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4085
4086 rx_ring->desc = NULL;
4087}
4088
4089/**
4090 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4091 * @adapter: board private structure
4092 *
4093 * Free all receive software resources
4094 **/
4095static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4096{
4097 int i;
4098
4099 for (i = 0; i < adapter->num_rx_queues; i++)
9891ca7c
JB		 4100 if (adapter->rx_ring[i].desc)
4101 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 4102}
4103
9a799d71
AK		 4104/**
4105 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4106 * @netdev: network interface device structure
4107 * @new_mtu: new value for maximum frame size
4108 *
4109 * Returns 0 on success, negative on failure
4110 **/
4111static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4112{
4113 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4114 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4115
42c783c5
JB		 4116 /* MTU < 68 is an error and causes problems on some kernels */
4117 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 4118 return -EINVAL;
4119
021230d4 4120 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 4121 netdev->mtu, new_mtu);
021230d4 4122 /* must set new MTU before calling down or up */
9a799d71
AK		 4123 netdev->mtu = new_mtu;
4124
d4f80882
AV		 4125 if (netif_running(netdev))
4126 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4127
4128 return 0;
4129}
4130
4131/**
4132 * ixgbe_open - Called when a network interface is made active
4133 * @netdev: network interface device structure
4134 *
4135 * Returns 0 on success, negative value on failure
4136 *
4137 * The open entry point is called when a network interface is made
4138 * active by the system (IFF_UP). At this point all resources needed
4139 * for transmit and receive operations are allocated, the interrupt
4140 * handler is registered with the OS, the watchdog timer is started,
4141 * and the stack is notified that the interface is ready.
4142 **/
4143static int ixgbe_open(struct net_device *netdev)
4144{
4145 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4146 int err;
4bebfaa5
AK		 4147
4148 /* disallow open during test */
4149 if (test_bit(__IXGBE_TESTING, &adapter->state))
4150 return -EBUSY;
9a799d71 4151
54386467
JB		 4152 netif_carrier_off(netdev);
4153
9a799d71
AK		 4154 /* allocate transmit descriptors */
4155 err = ixgbe_setup_all_tx_resources(adapter);
4156 if (err)
4157 goto err_setup_tx;
4158
9a799d71
AK		 4159 /* allocate receive descriptors */
4160 err = ixgbe_setup_all_rx_resources(adapter);
4161 if (err)
4162 goto err_setup_rx;
4163
4164 ixgbe_configure(adapter);
4165
021230d4 4166 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4167 if (err)
4168 goto err_req_irq;
4169
9a799d71
AK		 4170 err = ixgbe_up_complete(adapter);
4171 if (err)
4172 goto err_up;
4173
d55b53ff
JK		 4174 netif_tx_start_all_queues(netdev);
4175
9a799d71
AK		 4176 return 0;
4177
4178err_up:
5eba3699 4179 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4180 ixgbe_free_irq(adapter);
4181err_req_irq:
9a799d71 4182err_setup_rx:
a20a1199 4183 ixgbe_free_all_rx_resources(adapter);
9a799d71 4184err_setup_tx:
a20a1199 4185 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 4186 ixgbe_reset(adapter);
4187
4188 return err;
4189}
4190
4191/**
4192 * ixgbe_close - Disables a network interface
4193 * @netdev: network interface device structure
4194 *
4195 * Returns 0, this is not allowed to fail
4196 *
4197 * The close entry point is called when an interface is de-activated
4198 * by the OS. The hardware is still under the drivers control, but
4199 * needs to be disabled. A global MAC reset is issued to stop the
4200 * hardware, and all transmit and receive resources are freed.
4201 **/
4202static int ixgbe_close(struct net_device *netdev)
4203{
4204 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4205
4206 ixgbe_down(adapter);
4207 ixgbe_free_irq(adapter);
4208
4209 ixgbe_free_all_tx_resources(adapter);
4210 ixgbe_free_all_rx_resources(adapter);
4211
5eba3699 4212 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4213
4214 return 0;
4215}
4216
b3c8b4ba
AD		 4217#ifdef CONFIG_PM
4218static int ixgbe_resume(struct pci_dev *pdev)
4219{
4220 struct net_device *netdev = pci_get_drvdata(pdev);
4221 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4222 u32 err;
4223
4224 pci_set_power_state(pdev, PCI_D0);
4225 pci_restore_state(pdev);
9ce77666 4226
4227 err = pci_enable_device_mem(pdev);
b3c8b4ba 4228 if (err) {
69888674 4229 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 4230 "suspend\n");
4231 return err;
4232 }
4233 pci_set_master(pdev);
4234
dd4d8ca6 4235 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 4236
4237 err = ixgbe_init_interrupt_scheme(adapter);
4238 if (err) {
4239 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4240 "device\n");
4241 return err;
4242 }
4243
b3c8b4ba
AD		 4244 ixgbe_reset(adapter);
4245
495dce12
WJP		 4246 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4247
b3c8b4ba
AD		 4248 if (netif_running(netdev)) {
4249 err = ixgbe_open(adapter->netdev);
4250 if (err)
4251 return err;
4252 }
4253
4254 netif_device_attach(netdev);
4255
4256 return 0;
4257}
b3c8b4ba 4258#endif /* CONFIG_PM */
9d8d05ae
RW		 4259
4260static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 4261{
4262 struct net_device *netdev = pci_get_drvdata(pdev);
4263 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 4264 struct ixgbe_hw *hw = &adapter->hw;
4265 u32 ctrl, fctrl;
4266 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4267#ifdef CONFIG_PM
4268 int retval = 0;
4269#endif
4270
4271 netif_device_detach(netdev);
4272
4273 if (netif_running(netdev)) {
4274 ixgbe_down(adapter);
4275 ixgbe_free_irq(adapter);
4276 ixgbe_free_all_tx_resources(adapter);
4277 ixgbe_free_all_rx_resources(adapter);
4278 }
7a921c93 4279 ixgbe_clear_interrupt_scheme(adapter);
b3c8b4ba
AD		 4280
4281#ifdef CONFIG_PM
4282 retval = pci_save_state(pdev);
4283 if (retval)
4284 return retval;
4df10466 4285
b3c8b4ba 4286#endif
e8e26350
PW		 4287 if (wufc) {
4288 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4289
e8e26350
PW		 4290 /* turn on all-multi mode if wake on multicast is enabled */
4291 if (wufc & IXGBE_WUFC_MC) {
4292 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4293 fctrl |= IXGBE_FCTRL_MPE;
4294 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4295 }
4296
4297 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4298 ctrl |= IXGBE_CTRL_GIO_DIS;
4299 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4300
4301 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4302 } else {
4303 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4304 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4305 }
4306
dd4d8ca6
DS		 4307 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4308 pci_wake_from_d3(pdev, true);
4309 else
4310 pci_wake_from_d3(pdev, false);
b3c8b4ba 4311
9d8d05ae
RW		 4312 *enable_wake = !!wufc;
4313
b3c8b4ba
AD		 4314 ixgbe_release_hw_control(adapter);
4315
4316 pci_disable_device(pdev);
4317
9d8d05ae
RW		 4318 return 0;
4319}
4320
4321#ifdef CONFIG_PM
4322static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4323{
4324 int retval;
4325 bool wake;
4326
4327 retval = __ixgbe_shutdown(pdev, &wake);
4328 if (retval)
4329 return retval;
4330
4331 if (wake) {
4332 pci_prepare_to_sleep(pdev);
4333 } else {
4334 pci_wake_from_d3(pdev, false);
4335 pci_set_power_state(pdev, PCI_D3hot);
4336 }
b3c8b4ba
AD		 4337
4338 return 0;
4339}
9d8d05ae 4340#endif /* CONFIG_PM */
b3c8b4ba
AD		 4341
4342static void ixgbe_shutdown(struct pci_dev *pdev)
4343{
9d8d05ae
RW		 4344 bool wake;
4345
4346 __ixgbe_shutdown(pdev, &wake);
4347
4348 if (system_state == SYSTEM_POWER_OFF) {
4349 pci_wake_from_d3(pdev, wake);
4350 pci_set_power_state(pdev, PCI_D3hot);
4351 }
b3c8b4ba
AD		 4352}
4353
9a799d71
AK		 4354/**
4355 * ixgbe_update_stats - Update the board statistics counters.
4356 * @adapter: board private structure
4357 **/
4358void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4359{
4360 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 4361 u64 total_mpc = 0;
4362 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71 4363
d51019a4 4364 if (hw->mac.type == ixgbe_mac_82599EB) {
f8212f97 4365 u64 rsc_count = 0;
d51019a4
PW		 4366 for (i = 0; i < 16; i++)
4367 adapter->hw_rx_no_dma_resources +=
4368 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
f8212f97
AD		 4369 for (i = 0; i < adapter->num_rx_queues; i++)
4370 rsc_count += adapter->rx_ring[i].rsc_count;
4371 adapter->rsc_count = rsc_count;
d51019a4
PW		 4372 }
4373
9a799d71 4374 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 4375 for (i = 0; i < 8; i++) {
4376 /* for packet buffers not used, the register should read 0 */
4377 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4378 missed_rx += mpc;
4379 adapter->stats.mpc[i] += mpc;
4380 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 4381 if (hw->mac.type == ixgbe_mac_82598EB)
4382 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 4383 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4384 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4385 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4386 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 4387 if (hw->mac.type == ixgbe_mac_82599EB) {
4388 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4389 IXGBE_PXONRXCNT(i));
4390 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4391 IXGBE_PXOFFRXCNT(i));
4392 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 4393 } else {
4394 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4395 IXGBE_PXONRXC(i));
4396 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4397 IXGBE_PXOFFRXC(i));
4398 }
2f90b865
AD		 4399 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4400 IXGBE_PXONTXC(i));
2f90b865 4401 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 4402 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 4403 }
4404 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4405 /* work around hardware counting issue */
4406 adapter->stats.gprc -= missed_rx;
4407
4408 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350
PW		 4409 if (hw->mac.type == ixgbe_mac_82599EB) {
4410 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4411 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
4412 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4413 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
4414 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4415 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4416 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4417 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
c4cf55e5
PWJ		 4418 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4419 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c
YZ		 4420#ifdef IXGBE_FCOE
4421 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4422 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4423 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4424 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4425 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4426 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4427#endif /* IXGBE_FCOE */
e8e26350
PW		 4428 } else {
4429 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4430 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4431 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4432 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4433 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4434 }
9a799d71
AK		 4435 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4436 adapter->stats.bprc += bprc;
4437 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 4438 if (hw->mac.type == ixgbe_mac_82598EB)
4439 adapter->stats.mprc -= bprc;
9a799d71
AK		 4440 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4441 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4442 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4443 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4444 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4445 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4446 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 4447 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 4448 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4449 adapter->stats.lxontxc += lxon;
4450 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4451 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 4452 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4453 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 4454 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4455 /*
4456 * 82598 errata - tx of flow control packets is included in tx counters
4457 */
4458 xon_off_tot = lxon + lxoff;
4459 adapter->stats.gptc -= xon_off_tot;
4460 adapter->stats.mptc -= xon_off_tot;
4461 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 4462 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4463 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4464 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 4465 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4466 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 4467 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 4468 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4469 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4470 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4471 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4472 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 4473 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4474
4475 /* Fill out the OS statistics structure */
9a799d71
AK		 4476 adapter->net_stats.multicast = adapter->stats.mprc;
4477
4478 /* Rx Errors */
4479 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
b4617240 4480 adapter->stats.rlec;
9a799d71
AK		 4481 adapter->net_stats.rx_dropped = 0;
4482 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4483 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 4484 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 4485}
4486
4487/**
4488 * ixgbe_watchdog - Timer Call-back
4489 * @data: pointer to adapter cast into an unsigned long
4490 **/
4491static void ixgbe_watchdog(unsigned long data)
4492{
4493 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 4494 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 4495 u64 eics = 0;
4496 int i;
cf8280ee 4497
fe49f04a
AD		 4498 /*
4499 * Do the watchdog outside of interrupt context due to the lovely
4500 * delays that some of the newer hardware requires
4501 */
22d5a71b 4502
fe49f04a
AD		 4503 if (test_bit(__IXGBE_DOWN, &adapter->state))
4504 goto watchdog_short_circuit;
22d5a71b 4505
fe49f04a
AD		 4506 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4507 /*
4508 * for legacy and MSI interrupts don't set any bits
4509 * that are enabled for EIAM, because this operation
4510 * would set *both* EIMS and EICS for any bit in EIAM
4511 */
4512 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4513 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4514 goto watchdog_reschedule;
4515 }
4516
4517 /* get one bit for every active tx/rx interrupt vector */
4518 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4519 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4520 if (qv->rxr_count || qv->txr_count)
4521 eics |= ((u64)1 << i);
cf8280ee 4522 }
9a799d71 4523
fe49f04a
AD		 4524 /* Cause software interrupt to ensure rx rings are cleaned */
4525 ixgbe_irq_rearm_queues(adapter, eics);
4526
4527watchdog_reschedule:
4528 /* Reset the timer */
4529 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4530
4531watchdog_short_circuit:
cf8280ee
JB		 4532 schedule_work(&adapter->watchdog_task);
4533}
4534
e8e26350
PW		 4535/**
4536 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4537 * @work: pointer to work_struct containing our data
4538 **/
4539static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4540{
4541 struct ixgbe_adapter *adapter = container_of(work,
4542 struct ixgbe_adapter,
4543 multispeed_fiber_task);
4544 struct ixgbe_hw *hw = &adapter->hw;
4545 u32 autoneg;
8620a103 4546 bool negotiation;
e8e26350
PW		 4547
4548 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 4549 autoneg = hw->phy.autoneg_advertised;
4550 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103
MC		 4551 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4552 if (hw->mac.ops.setup_link)
4553 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 4554 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4555 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4556}
4557
4558/**
4559 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4560 * @work: pointer to work_struct containing our data
4561 **/
4562static void ixgbe_sfp_config_module_task(struct work_struct *work)
4563{
4564 struct ixgbe_adapter *adapter = container_of(work,
4565 struct ixgbe_adapter,
4566 sfp_config_module_task);
4567 struct ixgbe_hw *hw = &adapter->hw;
4568 u32 err;
4569
4570 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 4571
4572 /* Time for electrical oscillations to settle down */
4573 msleep(100);
e8e26350 4574 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4575
e8e26350 4576 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 4577 dev_err(&adapter->pdev->dev, "failed to initialize because "
4578 "an unsupported SFP+ module type was detected.\n"
4579 "Reload the driver after installing a supported "
4580 "module.\n");
63d6e1d8 4581 unregister_netdev(adapter->netdev);
e8e26350
PW		 4582 return;
4583 }
4584 hw->mac.ops.setup_sfp(hw);
4585
8d1c3c07 4586 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 4587 /* This will also work for DA Twinax connections */
4588 schedule_work(&adapter->multispeed_fiber_task);
4589 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4590}
4591
c4cf55e5
PWJ		 4592/**
4593 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4594 * @work: pointer to work_struct containing our data
4595 **/
4596static void ixgbe_fdir_reinit_task(struct work_struct *work)
4597{
4598 struct ixgbe_adapter *adapter = container_of(work,
4599 struct ixgbe_adapter,
4600 fdir_reinit_task);
4601 struct ixgbe_hw *hw = &adapter->hw;
4602 int i;
4603
4604 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4605 for (i = 0; i < adapter->num_tx_queues; i++)
4606 set_bit(__IXGBE_FDIR_INIT_DONE,
4607 &(adapter->tx_ring[i].reinit_state));
4608 } else {
4609 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4610 "ignored adding FDIR ATR filters \n");
4611 }
4612 /* Done FDIR Re-initialization, enable transmits */
4613 netif_tx_start_all_queues(adapter->netdev);
4614}
4615
cf8280ee 4616/**
69888674
AD		 4617 * ixgbe_watchdog_task - worker thread to bring link up
4618 * @work: pointer to work_struct containing our data
cf8280ee
JB		 4619 **/
4620static void ixgbe_watchdog_task(struct work_struct *work)
4621{
4622 struct ixgbe_adapter *adapter = container_of(work,
4623 struct ixgbe_adapter,
4624 watchdog_task);
4625 struct net_device *netdev = adapter->netdev;
4626 struct ixgbe_hw *hw = &adapter->hw;
4627 u32 link_speed = adapter->link_speed;
4628 bool link_up = adapter->link_up;
bc59fcda
NS		 4629 int i;
4630 struct ixgbe_ring *tx_ring;
4631 int some_tx_pending = 0;
cf8280ee
JB		 4632
4633 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4634
4635 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4636 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 4637 if (link_up) {
4638#ifdef CONFIG_DCB
4639 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4640 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 4641 hw->mac.ops.fc_enable(hw, i);
264857b8 4642 } else {
620fa036 4643 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 4644 }
4645#else
620fa036 4646 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 4647#endif
4648 }
4649
cf8280ee
JB		 4650 if (link_up ||
4651 time_after(jiffies, (adapter->link_check_timeout +
4652 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 4653 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 4654 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 4655 }
4656 adapter->link_up = link_up;
4657 adapter->link_speed = link_speed;
4658 }
9a799d71
AK		 4659
4660 if (link_up) {
4661 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 4662 bool flow_rx, flow_tx;
4663
4664 if (hw->mac.type == ixgbe_mac_82599EB) {
4665 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4666 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 4667 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
4668 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 4669 } else {
4670 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4671 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 4672 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
4673 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 4674 }
4675
a46e534b
JK		 4676 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4677 "Flow Control: %s\n",
4678 netdev->name,
4679 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4680 "10 Gbps" :
4681 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4682 "1 Gbps" : "unknown speed")),
e8e26350
PW		 4683 ((flow_rx && flow_tx) ? "RX/TX" :
4684 (flow_rx ? "RX" :
4685 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 4686
4687 netif_carrier_on(netdev);
9a799d71
AK		 4688 } else {
4689 /* Force detection of hung controller */
4690 adapter->detect_tx_hung = true;
4691 }
4692 } else {
cf8280ee
JB		 4693 adapter->link_up = false;
4694 adapter->link_speed = 0;
9a799d71 4695 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 4696 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4697 netdev->name);
9a799d71 4698 netif_carrier_off(netdev);
9a799d71
AK		 4699 }
4700 }
4701
bc59fcda
NS		 4702 if (!netif_carrier_ok(netdev)) {
4703 for (i = 0; i < adapter->num_tx_queues; i++) {
4704 tx_ring = &adapter->tx_ring[i];
4705 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4706 some_tx_pending = 1;
4707 break;
4708 }
4709 }
4710
4711 if (some_tx_pending) {
4712 /* We've lost link, so the controller stops DMA,
4713 * but we've got queued Tx work that's never going
4714 * to get done, so reset controller to flush Tx.
4715 * (Do the reset outside of interrupt context).
4716 */
4717 schedule_work(&adapter->reset_task);
4718 }
4719 }
4720
9a799d71 4721 ixgbe_update_stats(adapter);
cf8280ee 4722 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 4723}
4724
9a799d71 4725static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 4726 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4727 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 4728{
4729 struct ixgbe_adv_tx_context_desc *context_desc;
4730 unsigned int i;
4731 int err;
4732 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 4733 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4734 u32 mss_l4len_idx, l4len;
9a799d71
AK		 4735
4736 if (skb_is_gso(skb)) {
4737 if (skb_header_cloned(skb)) {
4738 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4739 if (err)
4740 return err;
4741 }
4742 l4len = tcp_hdrlen(skb);
4743 *hdr_len += l4len;
4744
8327d000 4745 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 4746 struct iphdr *iph = ip_hdr(skb);
4747 iph->tot_len = 0;
4748 iph->check = 0;
4749 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 4750 iph->daddr, 0,
4751 IPPROTO_TCP,
4752 0);
9a799d71
AK		 4753 adapter->hw_tso_ctxt++;
4754 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4755 ipv6_hdr(skb)->payload_len = 0;
4756 tcp_hdr(skb)->check =
4757 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 4758 &ipv6_hdr(skb)->daddr,
4759 0, IPPROTO_TCP, 0);
9a799d71
AK		 4760 adapter->hw_tso6_ctxt++;
4761 }
4762
4763 i = tx_ring->next_to_use;
4764
4765 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4766 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4767
4768 /* VLAN MACLEN IPLEN */
4769 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4770 vlan_macip_lens |=
4771 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4772 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 4773 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4774 *hdr_len += skb_network_offset(skb);
4775 vlan_macip_lens |=
4776 (skb_transport_header(skb) - skb_network_header(skb));
4777 *hdr_len +=
4778 (skb_transport_header(skb) - skb_network_header(skb));
4779 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4780 context_desc->seqnum_seed = 0;
4781
4782 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 4783 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 4784 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 4785
8327d000 4786 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4787 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4788 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4789 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4790
4791 /* MSS L4LEN IDX */
9f8cdf4f 4792 mss_l4len_idx =
9a799d71
AK		 4793 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4794 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 4795 /* use index 1 for TSO */
4796 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4797 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4798
4799 tx_buffer_info->time_stamp = jiffies;
4800 tx_buffer_info->next_to_watch = i;
4801
4802 i++;
4803 if (i == tx_ring->count)
4804 i = 0;
4805 tx_ring->next_to_use = i;
4806
4807 return true;
4808 }
4809 return false;
4810}
4811
4812static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 4813 struct ixgbe_ring *tx_ring,
4814 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 4815{
4816 struct ixgbe_adv_tx_context_desc *context_desc;
4817 unsigned int i;
4818 struct ixgbe_tx_buffer *tx_buffer_info;
4819 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4820
4821 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4822 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4823 i = tx_ring->next_to_use;
4824 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4825 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4826
4827 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4828 vlan_macip_lens |=
4829 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4830 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 4831 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4832 if (skb->ip_summed == CHECKSUM_PARTIAL)
4833 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 4834 skb_network_header(skb));
9a799d71
AK		 4835
4836 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4837 context_desc->seqnum_seed = 0;
4838
4839 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 4840 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 4841
4842 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71 4843 switch (skb->protocol) {
09640e63 4844 case cpu_to_be16(ETH_P_IP):
9a799d71 4845 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 4846 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4847 type_tucmd_mlhl |=
b4617240 4848 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4849 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4850 type_tucmd_mlhl |=
4851 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4852 break;
09640e63 4853 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 4854 /* XXX what about other V6 headers?? */
4855 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4856 type_tucmd_mlhl |=
b4617240 4857 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4858 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4859 type_tucmd_mlhl |=
4860 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4861 break;
41825d71
AK		 4862 default:
4863 if (unlikely(net_ratelimit())) {
4864 DPRINTK(PROBE, WARNING,
4865 "partial checksum but proto=%x!\n",
4866 skb->protocol);
4867 }
4868 break;
4869 }
9a799d71
AK		 4870 }
4871
4872 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 4873 /* use index zero for tx checksum offload */
9a799d71
AK		 4874 context_desc->mss_l4len_idx = 0;
4875
4876 tx_buffer_info->time_stamp = jiffies;
4877 tx_buffer_info->next_to_watch = i;
9f8cdf4f 4878
9a799d71
AK		 4879 adapter->hw_csum_tx_good++;
4880 i++;
4881 if (i == tx_ring->count)
4882 i = 0;
4883 tx_ring->next_to_use = i;
4884
4885 return true;
4886 }
9f8cdf4f 4887
9a799d71
AK		 4888 return false;
4889}
4890
4891static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 4892 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 4893 struct sk_buff *skb, u32 tx_flags,
4894 unsigned int first)
9a799d71
AK		 4895{
4896 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 4897 unsigned int len;
4898 unsigned int total = skb->len;
9a799d71
AK		 4899 unsigned int offset = 0, size, count = 0, i;
4900 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4901 unsigned int f;
44df32c5 4902 dma_addr_t *map;
9a799d71
AK		 4903
4904 i = tx_ring->next_to_use;
4905
44df32c5
AD		 4906 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4907 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4908 return 0;
4909 }
4910
4911 map = skb_shinfo(skb)->dma_maps;
4912
eacd73f7
YZ		 4913 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4914 /* excluding fcoe_crc_eof for FCoE */
4915 total -= sizeof(struct fcoe_crc_eof);
4916
4917 len = min(skb_headlen(skb), total);
9a799d71
AK		 4918 while (len) {
4919 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4920 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4921
4922 tx_buffer_info->length = size;
042a53a9 4923 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
9a799d71
AK		 4924 tx_buffer_info->time_stamp = jiffies;
4925 tx_buffer_info->next_to_watch = i;
4926
4927 len -= size;
eacd73f7 4928 total -= size;
9a799d71
AK		 4929 offset += size;
4930 count++;
44df32c5
AD		 4931
4932 if (len) {
4933 i++;
4934 if (i == tx_ring->count)
4935 i = 0;
4936 }
9a799d71
AK		 4937 }
4938
4939 for (f = 0; f < nr_frags; f++) {
4940 struct skb_frag_struct *frag;
4941
4942 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 4943 len = min((unsigned int)frag->size, total);
44df32c5 4944 offset = 0;
9a799d71
AK		 4945
4946 while (len) {
44df32c5
AD		 4947 i++;
4948 if (i == tx_ring->count)
4949 i = 0;
4950
9a799d71
AK		 4951 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4952 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4953
4954 tx_buffer_info->length = size;
042a53a9 4955 tx_buffer_info->dma = map[f] + offset;
9a799d71
AK		 4956 tx_buffer_info->time_stamp = jiffies;
4957 tx_buffer_info->next_to_watch = i;
4958
4959 len -= size;
eacd73f7 4960 total -= size;
9a799d71
AK		 4961 offset += size;
4962 count++;
9a799d71 4963 }
eacd73f7
YZ		 4964 if (total == 0)
4965 break;
9a799d71 4966 }
44df32c5 4967
9a799d71
AK		 4968 tx_ring->tx_buffer_info[i].skb = skb;
4969 tx_ring->tx_buffer_info[first].next_to_watch = i;
4970
4971 return count;
4972}
4973
4974static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 4975 struct ixgbe_ring *tx_ring,
4976 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 4977{
4978 union ixgbe_adv_tx_desc *tx_desc = NULL;
4979 struct ixgbe_tx_buffer *tx_buffer_info;
4980 u32 olinfo_status = 0, cmd_type_len = 0;
4981 unsigned int i;
4982 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4983
4984 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4985
4986 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4987
4988 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4989 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4990
4991 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4992 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4993
4994 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4995 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 4996
4eeae6fd
PW		 4997 /* use index 1 context for tso */
4998 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4999 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5000 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 5001 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 5002
5003 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5004 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5005 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5006
eacd73f7
YZ		 5007 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5008 olinfo_status |= IXGBE_ADVTXD_CC;
5009 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5010 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5011 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5012 }
5013
9a799d71
AK		 5014 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5015
5016 i = tx_ring->next_to_use;
5017 while (count--) {
5018 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5019 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5020 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5021 tx_desc->read.cmd_type_len =
b4617240 5022 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 5023 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 5024 i++;
5025 if (i == tx_ring->count)
5026 i = 0;
5027 }
5028
5029 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5030
5031 /*
5032 * Force memory writes to complete before letting h/w
5033 * know there are new descriptors to fetch. (Only
5034 * applicable for weak-ordered memory model archs,
5035 * such as IA-64).
5036 */
5037 wmb();
5038
5039 tx_ring->next_to_use = i;
5040 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5041}
5042
c4cf55e5
PWJ		 5043static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5044 int queue, u32 tx_flags)
5045{
5046 /* Right now, we support IPv4 only */
5047 struct ixgbe_atr_input atr_input;
5048 struct tcphdr *th;
5049 struct udphdr *uh;
5050 struct iphdr *iph = ip_hdr(skb);
5051 struct ethhdr *eth = (struct ethhdr *)skb->data;
5052 u16 vlan_id, src_port, dst_port, flex_bytes;
5053 u32 src_ipv4_addr, dst_ipv4_addr;
5054 u8 l4type = 0;
5055
5056 /* check if we're UDP or TCP */
5057 if (iph->protocol == IPPROTO_TCP) {
5058 th = tcp_hdr(skb);
5059 src_port = th->source;
5060 dst_port = th->dest;
5061 l4type |= IXGBE_ATR_L4TYPE_TCP;
5062 /* l4type IPv4 type is 0, no need to assign */
5063 } else if(iph->protocol == IPPROTO_UDP) {
5064 uh = udp_hdr(skb);
5065 src_port = uh->source;
5066 dst_port = uh->dest;
5067 l4type |= IXGBE_ATR_L4TYPE_UDP;
5068 /* l4type IPv4 type is 0, no need to assign */
5069 } else {
5070 /* Unsupported L4 header, just bail here */
5071 return;
5072 }
5073
5074 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5075
5076 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5077 IXGBE_TX_FLAGS_VLAN_SHIFT;
5078 src_ipv4_addr = iph->saddr;
5079 dst_ipv4_addr = iph->daddr;
5080 flex_bytes = eth->h_proto;
5081
5082 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5083 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5084 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5085 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5086 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5087 /* src and dst are inverted, think how the receiver sees them */
5088 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5089 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5090
5091 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5092 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5093}
5094
e092be60 5095static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5096 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 5097{
5098 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5099
30eba97a 5100 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5101 /* Herbert's original patch had:
5102 * smp_mb__after_netif_stop_queue();
5103 * but since that doesn't exist yet, just open code it. */
5104 smp_mb();
5105
5106 /* We need to check again in a case another CPU has just
5107 * made room available. */
5108 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5109 return -EBUSY;
5110
5111 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 5112 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5113 ++adapter->restart_queue;
5114 return 0;
5115}
5116
5117static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5118 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 5119{
5120 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5121 return 0;
5122 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5123}
5124
09a3b1f8
SH		 5125static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5126{
5127 struct ixgbe_adapter *adapter = netdev_priv(dev);
5128
c4cf55e5
PWJ		 5129 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5130 return smp_processor_id();
5131
09a3b1f8 5132 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
36e89d73 5133 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
09a3b1f8
SH		 5134
5135 return skb_tx_hash(dev, skb);
5136}
5137
3b29a56d
SH		 5138static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5139 struct net_device *netdev)
9a799d71
AK		 5140{
5141 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5142 struct ixgbe_ring *tx_ring;
9a799d71
AK		 5143 unsigned int first;
5144 unsigned int tx_flags = 0;
30eba97a
AV		 5145 u8 hdr_len = 0;
5146 int r_idx = 0, tso;
9a799d71
AK		 5147 int count = 0;
5148 unsigned int f;
9f8cdf4f 5149
9f8cdf4f
JB		 5150 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5151 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 5152 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5153 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5154 tx_flags |= (skb->queue_mapping << 13);
5155 }
5156 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5157 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5158 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
60127865
LL		 5159 if (skb->priority != TC_PRIO_CONTROL) {
5160 tx_flags |= (skb->queue_mapping << 13);
5161 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5162 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5163 } else {
5164 skb->queue_mapping =
5165 adapter->ring_feature[RING_F_DCB].indices-1;
5166 }
9a799d71 5167 }
eacd73f7 5168
60127865
LL		 5169 r_idx = skb->queue_mapping;
5170 tx_ring = &adapter->tx_ring[r_idx];
5171
eacd73f7 5172 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
09ad1cc0 5173 (skb->protocol == htons(ETH_P_FCOE))) {
eacd73f7 5174 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0
YZ		 5175#ifdef IXGBE_FCOE
5176 r_idx = smp_processor_id();
5177 r_idx &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5178 r_idx += adapter->ring_feature[RING_F_FCOE].mask;
5179 tx_ring = &adapter->tx_ring[r_idx];
5180#endif
5181 }
eacd73f7 5182 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 5183 if (skb_is_gso(skb) ||
5184 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 5185 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5186 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 5187 count++;
5188
9f8cdf4f
JB		 5189 count += TXD_USE_COUNT(skb_headlen(skb));
5190 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 5191 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5192
e092be60 5193 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 5194 adapter->tx_busy++;
9a799d71
AK		 5195 return NETDEV_TX_BUSY;
5196 }
9a799d71 5197
9a799d71 5198 first = tx_ring->next_to_use;
eacd73f7
YZ		 5199 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5200#ifdef IXGBE_FCOE
5201 /* setup tx offload for FCoE */
5202 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5203 if (tso < 0) {
5204 dev_kfree_skb_any(skb);
5205 return NETDEV_TX_OK;
5206 }
5207 if (tso)
5208 tx_flags |= IXGBE_TX_FLAGS_FSO;
5209#endif /* IXGBE_FCOE */
5210 } else {
5211 if (skb->protocol == htons(ETH_P_IP))
5212 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5213 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5214 if (tso < 0) {
5215 dev_kfree_skb_any(skb);
5216 return NETDEV_TX_OK;
5217 }
9a799d71 5218
eacd73f7
YZ		 5219 if (tso)
5220 tx_flags |= IXGBE_TX_FLAGS_TSO;
5221 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5222 (skb->ip_summed == CHECKSUM_PARTIAL))
5223 tx_flags |= IXGBE_TX_FLAGS_CSUM;
5224 }
9a799d71 5225
eacd73f7 5226 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 5227 if (count) {
c4cf55e5
PWJ		 5228 /* add the ATR filter if ATR is on */
5229 if (tx_ring->atr_sample_rate) {
5230 ++tx_ring->atr_count;
5231 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5232 test_bit(__IXGBE_FDIR_INIT_DONE,
5233 &tx_ring->reinit_state)) {
5234 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5235 tx_flags);
5236 tx_ring->atr_count = 0;
5237 }
5238 }
44df32c5
AD		 5239 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5240 hdr_len);
44df32c5 5241 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 5242
44df32c5
AD		 5243 } else {
5244 dev_kfree_skb_any(skb);
5245 tx_ring->tx_buffer_info[first].time_stamp = 0;
5246 tx_ring->next_to_use = first;
5247 }
9a799d71
AK		 5248
5249 return NETDEV_TX_OK;
5250}
5251
5252/**
5253 * ixgbe_get_stats - Get System Network Statistics
5254 * @netdev: network interface device structure
5255 *
5256 * Returns the address of the device statistics structure.
5257 * The statistics are actually updated from the timer callback.
5258 **/
5259static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5260{
5261 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5262
5263 /* only return the current stats */
5264 return &adapter->net_stats;
5265}
5266
5267/**
5268 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5269 * @netdev: network interface device structure
5270 * @p: pointer to an address structure
5271 *
5272 * Returns 0 on success, negative on failure
5273 **/
5274static int ixgbe_set_mac(struct net_device *netdev, void *p)
5275{
5276 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 5277 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5278 struct sockaddr *addr = p;
5279
5280 if (!is_valid_ether_addr(addr->sa_data))
5281 return -EADDRNOTAVAIL;
5282
5283 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 5284 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 5285
b4617240 5286 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 5287
5288 return 0;
5289}
5290
6b73e10d
BH		 5291static int
5292ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5293{
5294 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5295 struct ixgbe_hw *hw = &adapter->hw;
5296 u16 value;
5297 int rc;
5298
5299 if (prtad != hw->phy.mdio.prtad)
5300 return -EINVAL;
5301 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5302 if (!rc)
5303 rc = value;
5304 return rc;
5305}
5306
5307static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5308 u16 addr, u16 value)
5309{
5310 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5311 struct ixgbe_hw *hw = &adapter->hw;
5312
5313 if (prtad != hw->phy.mdio.prtad)
5314 return -EINVAL;
5315 return hw->phy.ops.write_reg(hw, addr, devad, value);
5316}
5317
5318static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5319{
5320 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5321
5322 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5323}
5324
0365e6e4
PW		 5325/**
5326 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 5327 * netdev->dev_addrs
0365e6e4
PW		 5328 * @netdev: network interface device structure
5329 *
5330 * Returns non-zero on failure
5331 **/
5332static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5333{
5334 int err = 0;
5335 struct ixgbe_adapter *adapter = netdev_priv(dev);
5336 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5337
5338 if (is_valid_ether_addr(mac->san_addr)) {
5339 rtnl_lock();
5340 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5341 rtnl_unlock();
5342 }
5343 return err;
5344}
5345
5346/**
5347 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 5348 * netdev->dev_addrs
0365e6e4
PW		 5349 * @netdev: network interface device structure
5350 *
5351 * Returns non-zero on failure
5352 **/
5353static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5354{
5355 int err = 0;
5356 struct ixgbe_adapter *adapter = netdev_priv(dev);
5357 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5358
5359 if (is_valid_ether_addr(mac->san_addr)) {
5360 rtnl_lock();
5361 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5362 rtnl_unlock();
5363 }
5364 return err;
5365}
5366
9a799d71
AK		 5367#ifdef CONFIG_NET_POLL_CONTROLLER
5368/*
5369 * Polling 'interrupt' - used by things like netconsole to send skbs
5370 * without having to re-enable interrupts. It's not called while
5371 * the interrupt routine is executing.
5372 */
5373static void ixgbe_netpoll(struct net_device *netdev)
5374{
5375 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 5376 int i;
9a799d71 5377
9a799d71 5378 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 5379 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5380 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5381 for (i = 0; i < num_q_vectors; i++) {
5382 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5383 ixgbe_msix_clean_many(0, q_vector);
5384 }
5385 } else {
5386 ixgbe_intr(adapter->pdev->irq, netdev);
5387 }
9a799d71 5388 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 5389}
5390#endif
5391
0edc3527
SH		 5392static const struct net_device_ops ixgbe_netdev_ops = {
5393 .ndo_open = ixgbe_open,
5394 .ndo_stop = ixgbe_close,
00829823 5395 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 5396 .ndo_select_queue = ixgbe_select_queue,
0edc3527 5397 .ndo_get_stats = ixgbe_get_stats,
e90d400c 5398 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 5399 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5400 .ndo_validate_addr = eth_validate_addr,
5401 .ndo_set_mac_address = ixgbe_set_mac,
5402 .ndo_change_mtu = ixgbe_change_mtu,
5403 .ndo_tx_timeout = ixgbe_tx_timeout,
5404 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5405 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5406 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 5407 .ndo_do_ioctl = ixgbe_ioctl,
0edc3527
SH		 5408#ifdef CONFIG_NET_POLL_CONTROLLER
5409 .ndo_poll_controller = ixgbe_netpoll,
5410#endif
332d4a7d
YZ		 5411#ifdef IXGBE_FCOE
5412 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5413 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 5414 .ndo_fcoe_enable = ixgbe_fcoe_enable,
5415 .ndo_fcoe_disable = ixgbe_fcoe_disable,
332d4a7d 5416#endif /* IXGBE_FCOE */
0edc3527
SH		 5417};
5418
9a799d71
AK		 5419/**
5420 * ixgbe_probe - Device Initialization Routine
5421 * @pdev: PCI device information struct
5422 * @ent: entry in ixgbe_pci_tbl
5423 *
5424 * Returns 0 on success, negative on failure
5425 *
5426 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5427 * The OS initialization, configuring of the adapter private structure,
5428 * and a hardware reset occur.
5429 **/
5430static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 5431 const struct pci_device_id *ent)
9a799d71
AK		 5432{
5433 struct net_device *netdev;
5434 struct ixgbe_adapter *adapter = NULL;
5435 struct ixgbe_hw *hw;
5436 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 5437 static int cards_found;
5438 int i, err, pci_using_dac;
eacd73f7
YZ		 5439#ifdef IXGBE_FCOE
5440 u16 device_caps;
5441#endif
c44ade9e 5442 u32 part_num, eec;
9a799d71 5443
9ce77666 5444 err = pci_enable_device_mem(pdev);
9a799d71
AK		 5445 if (err)
5446 return err;
5447
6a35528a
YH		 5448 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5449 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
9a799d71
AK		 5450 pci_using_dac = 1;
5451 } else {
284901a9 5452 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5453 if (err) {
284901a9 5454 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5455 if (err) {
b4617240
PW		 5456 dev_err(&pdev->dev, "No usable DMA "
5457 "configuration, aborting\n");
9a799d71
AK		 5458 goto err_dma;
5459 }
5460 }
5461 pci_using_dac = 0;
5462 }
5463
9ce77666 5464 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5465 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 5466 if (err) {
9ce77666 5467 dev_err(&pdev->dev,
5468 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 5469 goto err_pci_reg;
5470 }
5471
6fabd715
PWJ		 5472 err = pci_enable_pcie_error_reporting(pdev);
5473 if (err) {
5474 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
5475 "0x%x\n", err);
5476 /* non-fatal, continue */
5477 }
5478
9a799d71 5479 pci_set_master(pdev);
fb3b27bc 5480 pci_save_state(pdev);
9a799d71 5481
30eba97a 5482 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 5483 if (!netdev) {
5484 err = -ENOMEM;
5485 goto err_alloc_etherdev;
5486 }
5487
9a799d71
AK		 5488 SET_NETDEV_DEV(netdev, &pdev->dev);
5489
5490 pci_set_drvdata(pdev, netdev);
5491 adapter = netdev_priv(netdev);
5492
5493 adapter->netdev = netdev;
5494 adapter->pdev = pdev;
5495 hw = &adapter->hw;
5496 hw->back = adapter;
5497 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5498
05857980
JK		 5499 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5500 pci_resource_len(pdev, 0));
9a799d71
AK		 5501 if (!hw->hw_addr) {
5502 err = -EIO;
5503 goto err_ioremap;
5504 }
5505
5506 for (i = 1; i <= 5; i++) {
5507 if (pci_resource_len(pdev, i) == 0)
5508 continue;
5509 }
5510
0edc3527 5511 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 5512 ixgbe_set_ethtool_ops(netdev);
9a799d71 5513 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 5514 strcpy(netdev->name, pci_name(pdev));
5515
9a799d71
AK		 5516 adapter->bd_number = cards_found;
5517
9a799d71
AK		 5518 /* Setup hw api */
5519 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 5520 hw->mac.type = ii->mac;
9a799d71 5521
c44ade9e
JB		 5522 /* EEPROM */
5523 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5524 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5525 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5526 if (!(eec & (1 << 8)))
5527 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5528
5529 /* PHY */
5530 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 5531 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 5532 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5533 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5534 hw->phy.mdio.mmds = 0;
5535 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5536 hw->phy.mdio.dev = netdev;
5537 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5538 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 5539
5540 /* set up this timer and work struct before calling get_invariants
5541 * which might start the timer
5542 */
5543 init_timer(&adapter->sfp_timer);
5544 adapter->sfp_timer.function = &ixgbe_sfp_timer;
5545 adapter->sfp_timer.data = (unsigned long) adapter;
5546
5547 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 5548
e8e26350
PW		 5549 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5550 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5551
5552 /* a new SFP+ module arrival, called from GPI SDP2 context */
5553 INIT_WORK(&adapter->sfp_config_module_task,
5554 ixgbe_sfp_config_module_task);
5555
8ca783ab 5556 ii->get_invariants(hw);
9a799d71
AK		 5557
5558 /* setup the private structure */
5559 err = ixgbe_sw_init(adapter);
5560 if (err)
5561 goto err_sw_init;
5562
bf069c97
DS		 5563 /*
5564 * If there is a fan on this device and it has failed log the
5565 * failure.
5566 */
5567 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5568 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5569 if (esdp & IXGBE_ESDP_SDP1)
5570 DPRINTK(PROBE, CRIT,
5571 "Fan has stopped, replace the adapter\n");
5572 }
5573
c44ade9e
JB		 5574 /* reset_hw fills in the perm_addr as well */
5575 err = hw->mac.ops.reset_hw(hw);
8ca783ab
DS		 5576 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5577 hw->mac.type == ixgbe_mac_82598EB) {
5578 /*
5579 * Start a kernel thread to watch for a module to arrive.
5580 * Only do this for 82598, since 82599 will generate
5581 * interrupts on module arrival.
5582 */
5583 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5584 mod_timer(&adapter->sfp_timer,
5585 round_jiffies(jiffies + (2 * HZ)));
5586 err = 0;
5587 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 5588 dev_err(&adapter->pdev->dev, "failed to initialize because "
5589 "an unsupported SFP+ module type was detected.\n"
5590 "Reload the driver after installing a supported "
5591 "module.\n");
04f165ef
PW		 5592 goto err_sw_init;
5593 } else if (err) {
c44ade9e
JB		 5594 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5595 goto err_sw_init;
5596 }
5597
9a799d71 5598 netdev->features = NETIF_F_SG |
b4617240
PW		 5599 NETIF_F_IP_CSUM |
5600 NETIF_F_HW_VLAN_TX |
5601 NETIF_F_HW_VLAN_RX |
5602 NETIF_F_HW_VLAN_FILTER;
9a799d71 5603
e9990a9c 5604 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 5605 netdev->features |= NETIF_F_TSO;
9a799d71 5606 netdev->features |= NETIF_F_TSO6;
78b6f4ce 5607 netdev->features |= NETIF_F_GRO;
ad31c402 5608
45a5ead0
JB		 5609 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5610 netdev->features |= NETIF_F_SCTP_CSUM;
5611
ad31c402
JK		 5612 netdev->vlan_features |= NETIF_F_TSO;
5613 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 5614 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 5615 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 5616 netdev->vlan_features |= NETIF_F_SG;
5617
2f90b865
AD		 5618 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5619 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5620
7a6b6f51 5621#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5622 netdev->dcbnl_ops = &dcbnl_ops;
5623#endif
5624
eacd73f7 5625#ifdef IXGBE_FCOE
0d551589 5626 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 5627 if (hw->mac.ops.get_device_caps) {
5628 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 5629 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5630 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 5631 }
5632 }
5633#endif /* IXGBE_FCOE */
9a799d71
AK		 5634 if (pci_using_dac)
5635 netdev->features |= NETIF_F_HIGHDMA;
5636
0c19d6af 5637 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 5638 netdev->features |= NETIF_F_LRO;
5639
9a799d71 5640 /* make sure the EEPROM is good */
c44ade9e 5641 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 5642 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5643 err = -EIO;
5644 goto err_eeprom;
5645 }
5646
5647 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5648 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5649
c44ade9e
JB		 5650 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5651 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 5652 err = -EIO;
5653 goto err_eeprom;
5654 }
5655
5656 init_timer(&adapter->watchdog_timer);
5657 adapter->watchdog_timer.function = &ixgbe_watchdog;
5658 adapter->watchdog_timer.data = (unsigned long)adapter;
5659
5660 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 5661 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 5662
021230d4
AV		 5663 err = ixgbe_init_interrupt_scheme(adapter);
5664 if (err)
5665 goto err_sw_init;
9a799d71 5666
e8e26350
PW		 5667 switch (pdev->device) {
5668 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 5669 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5670 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
bdf0a550
PWJ		 5671 /* Enable ACPI wakeup in GRC */
5672 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5673 (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
e8e26350
PW		 5674 break;
5675 default:
5676 adapter->wol = 0;
5677 break;
5678 }
e8e26350
PW		 5679 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5680
04f165ef
PW		 5681 /* pick up the PCI bus settings for reporting later */
5682 hw->mac.ops.get_bus_info(hw);
5683
9a799d71 5684 /* print bus type/speed/width info */
7c510e4b 5685 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 5686 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5687 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5688 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5689 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5690 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 5691 "Unknown"),
7c510e4b 5692 netdev->dev_addr);
c44ade9e 5693 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 5694 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5695 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5696 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5697 (part_num >> 8), (part_num & 0xff));
5698 else
5699 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5700 hw->mac.type, hw->phy.type,
5701 (part_num >> 8), (part_num & 0xff));
9a799d71 5702
e8e26350 5703 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 5704 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 5705 "this card is not sufficient for optimal "
5706 "performance.\n");
0c254d86 5707 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 5708 "PCI-Express slot is required.\n");
0c254d86
AK		 5709 }
5710
34b0368c
PWJ		 5711 /* save off EEPROM version number */
5712 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5713
9a799d71 5714 /* reset the hardware with the new settings */
794caeb2 5715 err = hw->mac.ops.start_hw(hw);
c44ade9e 5716
794caeb2
PWJ		 5717 if (err == IXGBE_ERR_EEPROM_VERSION) {
5718 /* We are running on a pre-production device, log a warning */
5719 dev_warn(&pdev->dev, "This device is a pre-production "
5720 "adapter/LOM. Please be aware there may be issues "
5721 "associated with your hardware. If you are "
5722 "experiencing problems please contact your Intel or "
5723 "hardware representative who provided you with this "
5724 "hardware.\n");
5725 }
9a799d71
AK		 5726 strcpy(netdev->name, "eth%d");
5727 err = register_netdev(netdev);
5728 if (err)
5729 goto err_register;
5730
54386467
JB		 5731 /* carrier off reporting is important to ethtool even BEFORE open */
5732 netif_carrier_off(netdev);
5733
c4cf55e5
PWJ		 5734 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5735 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5736 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5737
5dd2d332 5738#ifdef CONFIG_IXGBE_DCA
652f093f 5739 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 5740 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 5741 ixgbe_setup_dca(adapter);
5742 }
5743#endif
0365e6e4
PW		 5744 /* add san mac addr to netdev */
5745 ixgbe_add_sanmac_netdev(netdev);
9a799d71
AK		 5746
5747 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5748 cards_found++;
5749 return 0;
5750
5751err_register:
5eba3699 5752 ixgbe_release_hw_control(adapter);
7a921c93 5753 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 5754err_sw_init:
5755err_eeprom:
c4900be0
DS		 5756 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5757 del_timer_sync(&adapter->sfp_timer);
5758 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5759 cancel_work_sync(&adapter->multispeed_fiber_task);
5760 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 5761 iounmap(hw->hw_addr);
5762err_ioremap:
5763 free_netdev(netdev);
5764err_alloc_etherdev:
9ce77666 5765 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5766 IORESOURCE_MEM));
9a799d71
AK		 5767err_pci_reg:
5768err_dma:
5769 pci_disable_device(pdev);
5770 return err;
5771}
5772
5773/**
5774 * ixgbe_remove - Device Removal Routine
5775 * @pdev: PCI device information struct
5776 *
5777 * ixgbe_remove is called by the PCI subsystem to alert the driver
5778 * that it should release a PCI device. The could be caused by a
5779 * Hot-Plug event, or because the driver is going to be removed from
5780 * memory.
5781 **/
5782static void __devexit ixgbe_remove(struct pci_dev *pdev)
5783{
5784 struct net_device *netdev = pci_get_drvdata(pdev);
5785 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715 5786 int err;
9a799d71
AK		 5787
5788 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 5789 /* clear the module not found bit to make sure the worker won't
5790 * reschedule
5791 */
5792 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 5793 del_timer_sync(&adapter->watchdog_timer);
5794
c4900be0
DS		 5795 del_timer_sync(&adapter->sfp_timer);
5796 cancel_work_sync(&adapter->watchdog_task);
5797 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5798 cancel_work_sync(&adapter->multispeed_fiber_task);
5799 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 5800 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5801 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5802 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 5803 flush_scheduled_work();
5804
5dd2d332 5805#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5806 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5807 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5808 dca_remove_requester(&pdev->dev);
5809 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5810 }
5811
5812#endif
332d4a7d
YZ		 5813#ifdef IXGBE_FCOE
5814 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5815 ixgbe_cleanup_fcoe(adapter);
5816
5817#endif /* IXGBE_FCOE */
0365e6e4
PW		 5818
5819 /* remove the added san mac */
5820 ixgbe_del_sanmac_netdev(netdev);
5821
c4900be0
DS		 5822 if (netdev->reg_state == NETREG_REGISTERED)
5823 unregister_netdev(netdev);
9a799d71 5824
7a921c93 5825 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 5826
021230d4 5827 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5828
5829 iounmap(adapter->hw.hw_addr);
9ce77666 5830 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5831 IORESOURCE_MEM));
9a799d71 5832
021230d4 5833 DPRINTK(PROBE, INFO, "complete\n");
021230d4 5834
9a799d71
AK		 5835 free_netdev(netdev);
5836
6fabd715
PWJ		 5837 err = pci_disable_pcie_error_reporting(pdev);
5838 if (err)
5839 dev_err(&pdev->dev,
5840 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5841
9a799d71
AK		 5842 pci_disable_device(pdev);
5843}
5844
5845/**
5846 * ixgbe_io_error_detected - called when PCI error is detected
5847 * @pdev: Pointer to PCI device
5848 * @state: The current pci connection state
5849 *
5850 * This function is called after a PCI bus error affecting
5851 * this device has been detected.
5852 */
5853static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 5854 pci_channel_state_t state)
9a799d71
AK		 5855{
5856 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5857 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5858
5859 netif_device_detach(netdev);
5860
3044b8d1
BL		 5861 if (state == pci_channel_io_perm_failure)
5862 return PCI_ERS_RESULT_DISCONNECT;
5863
9a799d71
AK		 5864 if (netif_running(netdev))
5865 ixgbe_down(adapter);
5866 pci_disable_device(pdev);
5867
b4617240 5868 /* Request a slot reset. */
9a799d71
AK		 5869 return PCI_ERS_RESULT_NEED_RESET;
5870}
5871
5872/**
5873 * ixgbe_io_slot_reset - called after the pci bus has been reset.
5874 * @pdev: Pointer to PCI device
5875 *
5876 * Restart the card from scratch, as if from a cold-boot.
5877 */
5878static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5879{
5880 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5881 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 5882 pci_ers_result_t result;
5883 int err;
9a799d71 5884
9ce77666 5885 if (pci_enable_device_mem(pdev)) {
9a799d71 5886 DPRINTK(PROBE, ERR,
b4617240 5887 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 5888 result = PCI_ERS_RESULT_DISCONNECT;
5889 } else {
5890 pci_set_master(pdev);
5891 pci_restore_state(pdev);
9a799d71 5892
dd4d8ca6 5893 pci_wake_from_d3(pdev, false);
9a799d71 5894
6fabd715 5895 ixgbe_reset(adapter);
88512539 5896 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 5897 result = PCI_ERS_RESULT_RECOVERED;
5898 }
5899
5900 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5901 if (err) {
5902 dev_err(&pdev->dev,
5903 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5904 /* non-fatal, continue */
5905 }
9a799d71 5906
6fabd715 5907 return result;
9a799d71
AK		 5908}
5909
5910/**
5911 * ixgbe_io_resume - called when traffic can start flowing again.
5912 * @pdev: Pointer to PCI device
5913 *
5914 * This callback is called when the error recovery driver tells us that
5915 * its OK to resume normal operation.
5916 */
5917static void ixgbe_io_resume(struct pci_dev *pdev)
5918{
5919 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5920 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5921
5922 if (netif_running(netdev)) {
5923 if (ixgbe_up(adapter)) {
5924 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5925 return;
5926 }
5927 }
5928
5929 netif_device_attach(netdev);
9a799d71
AK		 5930}
5931
5932static struct pci_error_handlers ixgbe_err_handler = {
5933 .error_detected = ixgbe_io_error_detected,
5934 .slot_reset = ixgbe_io_slot_reset,
5935 .resume = ixgbe_io_resume,
5936};
5937
5938static struct pci_driver ixgbe_driver = {
5939 .name = ixgbe_driver_name,
5940 .id_table = ixgbe_pci_tbl,
5941 .probe = ixgbe_probe,
5942 .remove = __devexit_p(ixgbe_remove),
5943#ifdef CONFIG_PM
5944 .suspend = ixgbe_suspend,
5945 .resume = ixgbe_resume,
5946#endif
5947 .shutdown = ixgbe_shutdown,
5948 .err_handler = &ixgbe_err_handler
5949};
5950
5951/**
5952 * ixgbe_init_module - Driver Registration Routine
5953 *
5954 * ixgbe_init_module is the first routine called when the driver is
5955 * loaded. All it does is register with the PCI subsystem.
5956 **/
5957static int __init ixgbe_init_module(void)
5958{
5959 int ret;
5960 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5961 ixgbe_driver_string, ixgbe_driver_version);
5962
5963 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5964
5dd2d332 5965#ifdef CONFIG_IXGBE_DCA
bd0362dd 5966 dca_register_notify(&dca_notifier);
bd0362dd 5967#endif
5dd2d332 5968
9a799d71
AK		 5969 ret = pci_register_driver(&ixgbe_driver);
5970 return ret;
5971}
b4617240 5972
9a799d71
AK		 5973module_init(ixgbe_init_module);
5974
5975/**
5976 * ixgbe_exit_module - Driver Exit Cleanup Routine
5977 *
5978 * ixgbe_exit_module is called just before the driver is removed
5979 * from memory.
5980 **/
5981static void __exit ixgbe_exit_module(void)
5982{
5dd2d332 5983#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5984 dca_unregister_notify(&dca_notifier);
5985#endif
9a799d71
AK		 5986 pci_unregister_driver(&ixgbe_driver);
5987}
bd0362dd 5988
5dd2d332 5989#ifdef CONFIG_IXGBE_DCA
bd0362dd 5990static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 5991 void *p)
bd0362dd
JC		 5992{
5993 int ret_val;
5994
5995 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 5996 __ixgbe_notify_dca);
bd0362dd
JC		 5997
5998 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5999}
b453368d 6000
5dd2d332 6001#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 6002#ifdef DEBUG
6003/**
6004 * ixgbe_get_hw_dev_name - return device name string
6005 * used by hardware layer to print debugging information
6006 **/
6007char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6008{
6009 struct ixgbe_adapter *adapter = hw->back;
6010 return adapter->netdev->name;
6011}
bd0362dd 6012
b453368d 6013#endif
9a799d71
AK		 6014module_exit(ixgbe_exit_module);
6015
6016/* ixgbe_main.c */
kernel source for telekom puls (alcatel/mediatek)