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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
3efac5a0 | 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
35 | #include <linux/ip.h> | |
36 | #include <linux/tcp.h> | |
37 | #include <linux/ipv6.h> | |
38 | #include <net/checksum.h> | |
39 | #include <net/ip6_checksum.h> | |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/if_vlan.h> | |
eacd73f7 | 42 | #include <scsi/fc/fc_fcoe.h> |
9a799d71 AK |
43 | |
44 | #include "ixgbe.h" | |
45 | #include "ixgbe_common.h" | |
46 | ||
47 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 48 | static const char ixgbe_driver_string[] = |
b4617240 | 49 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
9a799d71 | 50 | |
a1c1db39 | 51 | #define DRV_VERSION "2.0.34-k2" |
9c8eb720 | 52 | const char ixgbe_driver_version[] = DRV_VERSION; |
3efac5a0 | 53 | static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation."; |
9a799d71 AK |
54 | |
55 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 56 | [board_82598] = &ixgbe_82598_info, |
e8e26350 | 57 | [board_82599] = &ixgbe_82599_info, |
9a799d71 AK |
58 | }; |
59 | ||
60 | /* ixgbe_pci_tbl - PCI Device ID Table | |
61 | * | |
62 | * Wildcard entries (PCI_ANY_ID) should come last | |
63 | * Last entry must be all 0s | |
64 | * | |
65 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
66 | * Class, Class Mask, private data (not used) } | |
67 | */ | |
68 | static struct pci_device_id ixgbe_pci_tbl[] = { | |
1e336d0f DS |
69 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), |
70 | board_82598 }, | |
9a799d71 | 71 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), |
3957d63d | 72 | board_82598 }, |
9a799d71 | 73 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), |
3957d63d | 74 | board_82598 }, |
0befdb3e JB |
75 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), |
76 | board_82598 }, | |
9a799d71 | 77 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), |
3957d63d | 78 | board_82598 }, |
8d792cd9 JB |
79 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), |
80 | board_82598 }, | |
c4900be0 DS |
81 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), |
82 | board_82598 }, | |
83 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), | |
84 | board_82598 }, | |
b95f5fcb JB |
85 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), |
86 | board_82598 }, | |
c4900be0 DS |
87 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), |
88 | board_82598 }, | |
2f21bdd3 DS |
89 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), |
90 | board_82598 }, | |
e8e26350 PW |
91 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), |
92 | board_82599 }, | |
1fcf03e6 PWJ |
93 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), |
94 | board_82599 }, | |
e8e26350 PW |
95 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), |
96 | board_82599 }, | |
9a799d71 AK |
97 | |
98 | /* required last entry */ | |
99 | {0, } | |
100 | }; | |
101 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
102 | ||
5dd2d332 | 103 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 104 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
b4617240 | 105 | void *p); |
bd0362dd JC |
106 | static struct notifier_block dca_notifier = { |
107 | .notifier_call = ixgbe_notify_dca, | |
108 | .next = NULL, | |
109 | .priority = 0 | |
110 | }; | |
111 | #endif | |
112 | ||
9a799d71 AK |
113 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
114 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
115 | MODULE_LICENSE("GPL"); | |
116 | MODULE_VERSION(DRV_VERSION); | |
117 | ||
118 | #define DEFAULT_DEBUG_LEVEL_SHIFT 3 | |
119 | ||
5eba3699 AV |
120 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
121 | { | |
122 | u32 ctrl_ext; | |
123 | ||
124 | /* Let firmware take over control of h/w */ | |
125 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
126 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 127 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
128 | } |
129 | ||
130 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
131 | { | |
132 | u32 ctrl_ext; | |
133 | ||
134 | /* Let firmware know the driver has taken over */ | |
135 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
136 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 137 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 138 | } |
9a799d71 | 139 | |
e8e26350 PW |
140 | /* |
141 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors | |
142 | * @adapter: pointer to adapter struct | |
143 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
144 | * @queue: queue to map the corresponding interrupt to | |
145 | * @msix_vector: the vector to map to the corresponding queue | |
146 | * | |
147 | */ | |
148 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
149 | u8 queue, u8 msix_vector) | |
9a799d71 AK |
150 | { |
151 | u32 ivar, index; | |
e8e26350 PW |
152 | struct ixgbe_hw *hw = &adapter->hw; |
153 | switch (hw->mac.type) { | |
154 | case ixgbe_mac_82598EB: | |
155 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
156 | if (direction == -1) | |
157 | direction = 0; | |
158 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
159 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
160 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
161 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
162 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
163 | break; | |
164 | case ixgbe_mac_82599EB: | |
165 | if (direction == -1) { | |
166 | /* other causes */ | |
167 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
168 | index = ((queue & 1) * 8); | |
169 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
170 | ivar &= ~(0xFF << index); | |
171 | ivar |= (msix_vector << index); | |
172 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
173 | break; | |
174 | } else { | |
175 | /* tx or rx causes */ | |
176 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
177 | index = ((16 * (queue & 1)) + (8 * direction)); | |
178 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
179 | ivar &= ~(0xFF << index); | |
180 | ivar |= (msix_vector << index); | |
181 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
182 | break; | |
183 | } | |
184 | default: | |
185 | break; | |
186 | } | |
9a799d71 AK |
187 | } |
188 | ||
fe49f04a AD |
189 | static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, |
190 | u64 qmask) | |
191 | { | |
192 | u32 mask; | |
193 | ||
194 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
195 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); | |
196 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); | |
197 | } else { | |
198 | mask = (qmask & 0xFFFFFFFF); | |
199 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); | |
200 | mask = (qmask >> 32); | |
201 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); | |
202 | } | |
203 | } | |
204 | ||
9a799d71 | 205 | static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter, |
b4617240 PW |
206 | struct ixgbe_tx_buffer |
207 | *tx_buffer_info) | |
9a799d71 | 208 | { |
44df32c5 | 209 | tx_buffer_info->dma = 0; |
9a799d71 | 210 | if (tx_buffer_info->skb) { |
44df32c5 AD |
211 | skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb, |
212 | DMA_TO_DEVICE); | |
9a799d71 AK |
213 | dev_kfree_skb_any(tx_buffer_info->skb); |
214 | tx_buffer_info->skb = NULL; | |
215 | } | |
44df32c5 | 216 | tx_buffer_info->time_stamp = 0; |
9a799d71 AK |
217 | /* tx_buffer_info must be completely set up in the transmit path */ |
218 | } | |
219 | ||
220 | static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter, | |
b4617240 PW |
221 | struct ixgbe_ring *tx_ring, |
222 | unsigned int eop) | |
9a799d71 | 223 | { |
e01c31a5 | 224 | struct ixgbe_hw *hw = &adapter->hw; |
e01c31a5 | 225 | |
9a799d71 | 226 | /* Detect a transmit hang in hardware, this serializes the |
e01c31a5 | 227 | * check with the clearing of time_stamp and movement of eop */ |
9a799d71 | 228 | adapter->detect_tx_hung = false; |
44df32c5 | 229 | if (tx_ring->tx_buffer_info[eop].time_stamp && |
9a799d71 AK |
230 | time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) && |
231 | !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) { | |
232 | /* detected Tx unit hang */ | |
e01c31a5 JB |
233 | union ixgbe_adv_tx_desc *tx_desc; |
234 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
9a799d71 | 235 | DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n" |
e01c31a5 JB |
236 | " Tx Queue <%d>\n" |
237 | " TDH, TDT <%x>, <%x>\n" | |
9a799d71 AK |
238 | " next_to_use <%x>\n" |
239 | " next_to_clean <%x>\n" | |
240 | "tx_buffer_info[next_to_clean]\n" | |
241 | " time_stamp <%lx>\n" | |
e01c31a5 JB |
242 | " jiffies <%lx>\n", |
243 | tx_ring->queue_index, | |
44df32c5 AD |
244 | IXGBE_READ_REG(hw, tx_ring->head), |
245 | IXGBE_READ_REG(hw, tx_ring->tail), | |
e01c31a5 JB |
246 | tx_ring->next_to_use, eop, |
247 | tx_ring->tx_buffer_info[eop].time_stamp, jiffies); | |
9a799d71 AK |
248 | return true; |
249 | } | |
250 | ||
251 | return false; | |
252 | } | |
253 | ||
b4617240 PW |
254 | #define IXGBE_MAX_TXD_PWR 14 |
255 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
e092be60 AV |
256 | |
257 | /* Tx Descriptors needed, worst case */ | |
258 | #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \ | |
259 | (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0)) | |
260 | #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \ | |
b4617240 | 261 | MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */ |
e092be60 | 262 | |
e01c31a5 JB |
263 | static void ixgbe_tx_timeout(struct net_device *netdev); |
264 | ||
9a799d71 AK |
265 | /** |
266 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
fe49f04a | 267 | * @q_vector: structure containing interrupt and ring information |
e01c31a5 | 268 | * @tx_ring: tx ring to clean |
9a799d71 | 269 | **/ |
fe49f04a | 270 | static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, |
e01c31a5 | 271 | struct ixgbe_ring *tx_ring) |
9a799d71 | 272 | { |
fe49f04a | 273 | struct ixgbe_adapter *adapter = q_vector->adapter; |
e01c31a5 | 274 | struct net_device *netdev = adapter->netdev; |
12207e49 PWJ |
275 | union ixgbe_adv_tx_desc *tx_desc, *eop_desc; |
276 | struct ixgbe_tx_buffer *tx_buffer_info; | |
277 | unsigned int i, eop, count = 0; | |
e01c31a5 | 278 | unsigned int total_bytes = 0, total_packets = 0; |
9a799d71 AK |
279 | |
280 | i = tx_ring->next_to_clean; | |
12207e49 PWJ |
281 | eop = tx_ring->tx_buffer_info[i].next_to_watch; |
282 | eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
283 | ||
284 | while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) && | |
9a1a69ad | 285 | (count < tx_ring->work_limit)) { |
12207e49 PWJ |
286 | bool cleaned = false; |
287 | for ( ; !cleaned; count++) { | |
288 | struct sk_buff *skb; | |
9a799d71 AK |
289 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); |
290 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
12207e49 | 291 | cleaned = (i == eop); |
e01c31a5 | 292 | skb = tx_buffer_info->skb; |
9a799d71 | 293 | |
12207e49 | 294 | if (cleaned && skb) { |
e092be60 | 295 | unsigned int segs, bytecount; |
e01c31a5 JB |
296 | |
297 | /* gso_segs is currently only valid for tcp */ | |
e092be60 AV |
298 | segs = skb_shinfo(skb)->gso_segs ?: 1; |
299 | /* multiply data chunks by size of headers */ | |
300 | bytecount = ((segs - 1) * skb_headlen(skb)) + | |
e01c31a5 JB |
301 | skb->len; |
302 | total_packets += segs; | |
303 | total_bytes += bytecount; | |
e092be60 | 304 | } |
e01c31a5 | 305 | |
9a799d71 | 306 | ixgbe_unmap_and_free_tx_resource(adapter, |
e01c31a5 | 307 | tx_buffer_info); |
9a799d71 | 308 | |
12207e49 PWJ |
309 | tx_desc->wb.status = 0; |
310 | ||
9a799d71 AK |
311 | i++; |
312 | if (i == tx_ring->count) | |
313 | i = 0; | |
e01c31a5 | 314 | } |
12207e49 PWJ |
315 | |
316 | eop = tx_ring->tx_buffer_info[i].next_to_watch; | |
317 | eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
318 | } | |
319 | ||
9a799d71 AK |
320 | tx_ring->next_to_clean = i; |
321 | ||
e092be60 | 322 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
e01c31a5 JB |
323 | if (unlikely(count && netif_carrier_ok(netdev) && |
324 | (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { | |
e092be60 AV |
325 | /* Make sure that anybody stopping the queue after this |
326 | * sees the new next_to_clean. | |
327 | */ | |
328 | smp_mb(); | |
30eba97a AV |
329 | if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && |
330 | !test_bit(__IXGBE_DOWN, &adapter->state)) { | |
331 | netif_wake_subqueue(netdev, tx_ring->queue_index); | |
e01c31a5 | 332 | ++adapter->restart_queue; |
30eba97a | 333 | } |
e092be60 | 334 | } |
9a799d71 | 335 | |
e01c31a5 JB |
336 | if (adapter->detect_tx_hung) { |
337 | if (ixgbe_check_tx_hang(adapter, tx_ring, i)) { | |
338 | /* schedule immediate reset if we believe we hung */ | |
339 | DPRINTK(PROBE, INFO, | |
340 | "tx hang %d detected, resetting adapter\n", | |
341 | adapter->tx_timeout_count + 1); | |
342 | ixgbe_tx_timeout(adapter->netdev); | |
343 | } | |
344 | } | |
9a799d71 | 345 | |
e01c31a5 | 346 | /* re-arm the interrupt */ |
fe49f04a AD |
347 | if (count >= tx_ring->work_limit) |
348 | ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
9a799d71 | 349 | |
e01c31a5 JB |
350 | tx_ring->total_bytes += total_bytes; |
351 | tx_ring->total_packets += total_packets; | |
e01c31a5 | 352 | tx_ring->stats.packets += total_packets; |
12207e49 | 353 | tx_ring->stats.bytes += total_bytes; |
e01c31a5 JB |
354 | adapter->net_stats.tx_bytes += total_bytes; |
355 | adapter->net_stats.tx_packets += total_packets; | |
9a1a69ad | 356 | return (count < tx_ring->work_limit); |
9a799d71 AK |
357 | } |
358 | ||
5dd2d332 | 359 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 360 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
b4617240 | 361 | struct ixgbe_ring *rx_ring) |
bd0362dd JC |
362 | { |
363 | u32 rxctrl; | |
364 | int cpu = get_cpu(); | |
3a581073 | 365 | int q = rx_ring - adapter->rx_ring; |
bd0362dd | 366 | |
3a581073 | 367 | if (rx_ring->cpu != cpu) { |
bd0362dd | 368 | rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q)); |
e8e26350 PW |
369 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
370 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK; | |
371 | rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
372 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
373 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599; | |
374 | rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
375 | IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599); | |
376 | } | |
bd0362dd JC |
377 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN; |
378 | rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN; | |
15005a32 DS |
379 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN); |
380 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN | | |
e8e26350 | 381 | IXGBE_DCA_RXCTRL_DESC_HSRO_EN); |
bd0362dd | 382 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl); |
3a581073 | 383 | rx_ring->cpu = cpu; |
bd0362dd JC |
384 | } |
385 | put_cpu(); | |
386 | } | |
387 | ||
388 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, | |
b4617240 | 389 | struct ixgbe_ring *tx_ring) |
bd0362dd JC |
390 | { |
391 | u32 txctrl; | |
392 | int cpu = get_cpu(); | |
3a581073 | 393 | int q = tx_ring - adapter->tx_ring; |
bd0362dd | 394 | |
3a581073 | 395 | if (tx_ring->cpu != cpu) { |
bd0362dd | 396 | txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q)); |
e8e26350 PW |
397 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
398 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK; | |
399 | txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
400 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
401 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599; | |
402 | txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
403 | IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599); | |
404 | } | |
bd0362dd JC |
405 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; |
406 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl); | |
3a581073 | 407 | tx_ring->cpu = cpu; |
bd0362dd JC |
408 | } |
409 | put_cpu(); | |
410 | } | |
411 | ||
412 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
413 | { | |
414 | int i; | |
415 | ||
416 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
417 | return; | |
418 | ||
e35ec126 AD |
419 | /* always use CB2 mode, difference is masked in the CB driver */ |
420 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
421 | ||
bd0362dd JC |
422 | for (i = 0; i < adapter->num_tx_queues; i++) { |
423 | adapter->tx_ring[i].cpu = -1; | |
424 | ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]); | |
425 | } | |
426 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
427 | adapter->rx_ring[i].cpu = -1; | |
428 | ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]); | |
429 | } | |
430 | } | |
431 | ||
432 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
433 | { | |
434 | struct net_device *netdev = dev_get_drvdata(dev); | |
435 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
436 | unsigned long event = *(unsigned long *)data; | |
437 | ||
438 | switch (event) { | |
439 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
440 | /* if we're already enabled, don't do it again */ |
441 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
442 | break; | |
652f093f | 443 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 444 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
445 | ixgbe_setup_dca(adapter); |
446 | break; | |
447 | } | |
448 | /* Fall Through since DCA is disabled. */ | |
449 | case DCA_PROVIDER_REMOVE: | |
450 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
451 | dca_remove_requester(dev); | |
452 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
453 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
454 | } | |
455 | break; | |
456 | } | |
457 | ||
652f093f | 458 | return 0; |
bd0362dd JC |
459 | } |
460 | ||
5dd2d332 | 461 | #endif /* CONFIG_IXGBE_DCA */ |
9a799d71 AK |
462 | /** |
463 | * ixgbe_receive_skb - Send a completed packet up the stack | |
464 | * @adapter: board private structure | |
465 | * @skb: packet to send up | |
177db6ff MC |
466 | * @status: hardware indication of status of receive |
467 | * @rx_ring: rx descriptor ring (for a specific queue) to setup | |
468 | * @rx_desc: rx descriptor | |
9a799d71 | 469 | **/ |
78b6f4ce | 470 | static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector, |
b4617240 | 471 | struct sk_buff *skb, u8 status, |
fdaff1ce | 472 | struct ixgbe_ring *ring, |
177db6ff | 473 | union ixgbe_adv_rx_desc *rx_desc) |
9a799d71 | 474 | { |
78b6f4ce HX |
475 | struct ixgbe_adapter *adapter = q_vector->adapter; |
476 | struct napi_struct *napi = &q_vector->napi; | |
177db6ff MC |
477 | bool is_vlan = (status & IXGBE_RXD_STAT_VP); |
478 | u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan); | |
9a799d71 | 479 | |
fdaff1ce | 480 | skb_record_rx_queue(skb, ring->queue_index); |
182ff8df | 481 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) { |
2f90b865 | 482 | if (adapter->vlgrp && is_vlan && (tag != 0)) |
78b6f4ce | 483 | vlan_gro_receive(napi, adapter->vlgrp, tag, skb); |
9a799d71 | 484 | else |
78b6f4ce | 485 | napi_gro_receive(napi, skb); |
177db6ff | 486 | } else { |
182ff8df AD |
487 | if (adapter->vlgrp && is_vlan && (tag != 0)) |
488 | vlan_hwaccel_rx(skb, adapter->vlgrp, tag); | |
489 | else | |
490 | netif_rx(skb); | |
9a799d71 AK |
491 | } |
492 | } | |
493 | ||
e59bd25d AV |
494 | /** |
495 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
496 | * @adapter: address of board private structure | |
497 | * @status_err: hardware indication of status of receive | |
498 | * @skb: skb currently being received and modified | |
499 | **/ | |
9a799d71 | 500 | static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter, |
712744be | 501 | u32 status_err, struct sk_buff *skb) |
9a799d71 AK |
502 | { |
503 | skb->ip_summed = CHECKSUM_NONE; | |
504 | ||
712744be JB |
505 | /* Rx csum disabled */ |
506 | if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED)) | |
9a799d71 | 507 | return; |
e59bd25d AV |
508 | |
509 | /* if IP and error */ | |
510 | if ((status_err & IXGBE_RXD_STAT_IPCS) && | |
511 | (status_err & IXGBE_RXDADV_ERR_IPE)) { | |
9a799d71 AK |
512 | adapter->hw_csum_rx_error++; |
513 | return; | |
514 | } | |
e59bd25d AV |
515 | |
516 | if (!(status_err & IXGBE_RXD_STAT_L4CS)) | |
517 | return; | |
518 | ||
519 | if (status_err & IXGBE_RXDADV_ERR_TCPE) { | |
520 | adapter->hw_csum_rx_error++; | |
521 | return; | |
522 | } | |
523 | ||
9a799d71 | 524 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 525 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
526 | adapter->hw_csum_rx_good++; |
527 | } | |
528 | ||
e8e26350 PW |
529 | static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw, |
530 | struct ixgbe_ring *rx_ring, u32 val) | |
531 | { | |
532 | /* | |
533 | * Force memory writes to complete before letting h/w | |
534 | * know there are new descriptors to fetch. (Only | |
535 | * applicable for weak-ordered memory model archs, | |
536 | * such as IA-64). | |
537 | */ | |
538 | wmb(); | |
539 | IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val); | |
540 | } | |
541 | ||
9a799d71 AK |
542 | /** |
543 | * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split | |
544 | * @adapter: address of board private structure | |
545 | **/ | |
546 | static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter, | |
7c6e0a43 JB |
547 | struct ixgbe_ring *rx_ring, |
548 | int cleaned_count) | |
9a799d71 | 549 | { |
9a799d71 AK |
550 | struct pci_dev *pdev = adapter->pdev; |
551 | union ixgbe_adv_rx_desc *rx_desc; | |
3a581073 | 552 | struct ixgbe_rx_buffer *bi; |
9a799d71 | 553 | unsigned int i; |
e8e26350 | 554 | unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN; |
9a799d71 AK |
555 | |
556 | i = rx_ring->next_to_use; | |
3a581073 | 557 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 AK |
558 | |
559 | while (cleaned_count--) { | |
560 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
561 | ||
762f4c57 | 562 | if (!bi->page_dma && |
3a581073 | 563 | (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) { |
3a581073 | 564 | if (!bi->page) { |
762f4c57 JB |
565 | bi->page = alloc_page(GFP_ATOMIC); |
566 | if (!bi->page) { | |
567 | adapter->alloc_rx_page_failed++; | |
568 | goto no_buffers; | |
569 | } | |
570 | bi->page_offset = 0; | |
571 | } else { | |
572 | /* use a half page if we're re-using */ | |
573 | bi->page_offset ^= (PAGE_SIZE / 2); | |
9a799d71 | 574 | } |
762f4c57 JB |
575 | |
576 | bi->page_dma = pci_map_page(pdev, bi->page, | |
577 | bi->page_offset, | |
578 | (PAGE_SIZE / 2), | |
579 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
580 | } |
581 | ||
3a581073 | 582 | if (!bi->skb) { |
5ecc3614 | 583 | struct sk_buff *skb; |
e8e26350 | 584 | skb = netdev_alloc_skb(adapter->netdev, bufsz); |
9a799d71 AK |
585 | |
586 | if (!skb) { | |
587 | adapter->alloc_rx_buff_failed++; | |
588 | goto no_buffers; | |
589 | } | |
590 | ||
591 | /* | |
592 | * Make buffer alignment 2 beyond a 16 byte boundary | |
593 | * this will result in a 16 byte aligned IP header after | |
594 | * the 14 byte MAC header is removed | |
595 | */ | |
596 | skb_reserve(skb, NET_IP_ALIGN); | |
597 | ||
3a581073 | 598 | bi->skb = skb; |
e8e26350 | 599 | bi->dma = pci_map_single(pdev, skb->data, bufsz, |
3a581073 | 600 | PCI_DMA_FROMDEVICE); |
9a799d71 AK |
601 | } |
602 | /* Refresh the desc even if buffer_addrs didn't change because | |
603 | * each write-back erases this info. */ | |
604 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
3a581073 JB |
605 | rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma); |
606 | rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); | |
9a799d71 | 607 | } else { |
3a581073 | 608 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma); |
9a799d71 AK |
609 | } |
610 | ||
611 | i++; | |
612 | if (i == rx_ring->count) | |
613 | i = 0; | |
3a581073 | 614 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 | 615 | } |
7c6e0a43 | 616 | |
9a799d71 AK |
617 | no_buffers: |
618 | if (rx_ring->next_to_use != i) { | |
619 | rx_ring->next_to_use = i; | |
620 | if (i-- == 0) | |
621 | i = (rx_ring->count - 1); | |
622 | ||
e8e26350 | 623 | ixgbe_release_rx_desc(&adapter->hw, rx_ring, i); |
9a799d71 AK |
624 | } |
625 | } | |
626 | ||
7c6e0a43 JB |
627 | static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc) |
628 | { | |
629 | return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info; | |
630 | } | |
631 | ||
632 | static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc) | |
633 | { | |
634 | return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
635 | } | |
636 | ||
f8212f97 AD |
637 | static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc) |
638 | { | |
639 | return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) & | |
640 | IXGBE_RXDADV_RSCCNT_MASK) >> | |
641 | IXGBE_RXDADV_RSCCNT_SHIFT; | |
642 | } | |
643 | ||
644 | /** | |
645 | * ixgbe_transform_rsc_queue - change rsc queue into a full packet | |
646 | * @skb: pointer to the last skb in the rsc queue | |
647 | * | |
648 | * This function changes a queue full of hw rsc buffers into a completed | |
649 | * packet. It uses the ->prev pointers to find the first packet and then | |
650 | * turns it into the frag list owner. | |
651 | **/ | |
652 | static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb) | |
653 | { | |
654 | unsigned int frag_list_size = 0; | |
655 | ||
656 | while (skb->prev) { | |
657 | struct sk_buff *prev = skb->prev; | |
658 | frag_list_size += skb->len; | |
659 | skb->prev = NULL; | |
660 | skb = prev; | |
661 | } | |
662 | ||
663 | skb_shinfo(skb)->frag_list = skb->next; | |
664 | skb->next = NULL; | |
665 | skb->len += frag_list_size; | |
666 | skb->data_len += frag_list_size; | |
667 | skb->truesize += frag_list_size; | |
668 | return skb; | |
669 | } | |
670 | ||
78b6f4ce | 671 | static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
b4617240 PW |
672 | struct ixgbe_ring *rx_ring, |
673 | int *work_done, int work_to_do) | |
9a799d71 | 674 | { |
78b6f4ce | 675 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a799d71 AK |
676 | struct pci_dev *pdev = adapter->pdev; |
677 | union ixgbe_adv_rx_desc *rx_desc, *next_rxd; | |
678 | struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer; | |
679 | struct sk_buff *skb; | |
f8212f97 | 680 | unsigned int i, rsc_count = 0; |
7c6e0a43 | 681 | u32 len, staterr; |
177db6ff MC |
682 | u16 hdr_info; |
683 | bool cleaned = false; | |
9a799d71 | 684 | int cleaned_count = 0; |
d2f4fbe2 | 685 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
9a799d71 AK |
686 | |
687 | i = rx_ring->next_to_clean; | |
9a799d71 AK |
688 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); |
689 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
690 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
9a799d71 AK |
691 | |
692 | while (staterr & IXGBE_RXD_STAT_DD) { | |
7c6e0a43 | 693 | u32 upper_len = 0; |
9a799d71 AK |
694 | if (*work_done >= work_to_do) |
695 | break; | |
696 | (*work_done)++; | |
697 | ||
698 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 JB |
699 | hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc)); |
700 | len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >> | |
762f4c57 | 701 | IXGBE_RXDADV_HDRBUFLEN_SHIFT; |
9a799d71 AK |
702 | if (hdr_info & IXGBE_RXDADV_SPH) |
703 | adapter->rx_hdr_split++; | |
704 | if (len > IXGBE_RX_HDR_SIZE) | |
705 | len = IXGBE_RX_HDR_SIZE; | |
706 | upper_len = le16_to_cpu(rx_desc->wb.upper.length); | |
7c6e0a43 | 707 | } else { |
9a799d71 | 708 | len = le16_to_cpu(rx_desc->wb.upper.length); |
7c6e0a43 | 709 | } |
9a799d71 AK |
710 | |
711 | cleaned = true; | |
712 | skb = rx_buffer_info->skb; | |
713 | prefetch(skb->data - NET_IP_ALIGN); | |
714 | rx_buffer_info->skb = NULL; | |
715 | ||
21fa4e66 | 716 | if (rx_buffer_info->dma) { |
9a799d71 | 717 | pci_unmap_single(pdev, rx_buffer_info->dma, |
5ecc3614 | 718 | rx_ring->rx_buf_len, |
b4617240 | 719 | PCI_DMA_FROMDEVICE); |
9a799d71 AK |
720 | skb_put(skb, len); |
721 | } | |
722 | ||
723 | if (upper_len) { | |
724 | pci_unmap_page(pdev, rx_buffer_info->page_dma, | |
762f4c57 | 725 | PAGE_SIZE / 2, PCI_DMA_FROMDEVICE); |
9a799d71 AK |
726 | rx_buffer_info->page_dma = 0; |
727 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
762f4c57 JB |
728 | rx_buffer_info->page, |
729 | rx_buffer_info->page_offset, | |
730 | upper_len); | |
731 | ||
732 | if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) || | |
733 | (page_count(rx_buffer_info->page) != 1)) | |
734 | rx_buffer_info->page = NULL; | |
735 | else | |
736 | get_page(rx_buffer_info->page); | |
9a799d71 AK |
737 | |
738 | skb->len += upper_len; | |
739 | skb->data_len += upper_len; | |
740 | skb->truesize += upper_len; | |
741 | } | |
742 | ||
743 | i++; | |
744 | if (i == rx_ring->count) | |
745 | i = 0; | |
9a799d71 AK |
746 | |
747 | next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
748 | prefetch(next_rxd); | |
9a799d71 | 749 | cleaned_count++; |
f8212f97 | 750 | |
df647b5c | 751 | if (adapter->flags & IXGBE_FLAG2_RSC_CAPABLE) |
f8212f97 AD |
752 | rsc_count = ixgbe_get_rsc_count(rx_desc); |
753 | ||
754 | if (rsc_count) { | |
755 | u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >> | |
756 | IXGBE_RXDADV_NEXTP_SHIFT; | |
757 | next_buffer = &rx_ring->rx_buffer_info[nextp]; | |
758 | rx_ring->rsc_count += (rsc_count - 1); | |
759 | } else { | |
760 | next_buffer = &rx_ring->rx_buffer_info[i]; | |
761 | } | |
762 | ||
9a799d71 | 763 | if (staterr & IXGBE_RXD_STAT_EOP) { |
f8212f97 AD |
764 | if (skb->prev) |
765 | skb = ixgbe_transform_rsc_queue(skb); | |
9a799d71 AK |
766 | rx_ring->stats.packets++; |
767 | rx_ring->stats.bytes += skb->len; | |
768 | } else { | |
f8212f97 AD |
769 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { |
770 | rx_buffer_info->skb = next_buffer->skb; | |
771 | rx_buffer_info->dma = next_buffer->dma; | |
772 | next_buffer->skb = skb; | |
773 | next_buffer->dma = 0; | |
774 | } else { | |
775 | skb->next = next_buffer->skb; | |
776 | skb->next->prev = skb; | |
777 | } | |
9a799d71 AK |
778 | adapter->non_eop_descs++; |
779 | goto next_desc; | |
780 | } | |
781 | ||
782 | if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) { | |
783 | dev_kfree_skb_irq(skb); | |
784 | goto next_desc; | |
785 | } | |
786 | ||
787 | ixgbe_rx_checksum(adapter, staterr, skb); | |
d2f4fbe2 AV |
788 | |
789 | /* probably a little skewed due to removing CRC */ | |
790 | total_rx_bytes += skb->len; | |
791 | total_rx_packets++; | |
792 | ||
74ce8dd2 | 793 | skb->protocol = eth_type_trans(skb, adapter->netdev); |
332d4a7d YZ |
794 | #ifdef IXGBE_FCOE |
795 | /* if ddp, not passing to ULD unless for FCP_RSP or error */ | |
796 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
797 | if (!ixgbe_fcoe_ddp(adapter, rx_desc, skb)) | |
798 | goto next_desc; | |
799 | #endif /* IXGBE_FCOE */ | |
fdaff1ce | 800 | ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc); |
9a799d71 AK |
801 | |
802 | next_desc: | |
803 | rx_desc->wb.upper.status_error = 0; | |
804 | ||
805 | /* return some buffers to hardware, one at a time is too slow */ | |
806 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
807 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
808 | cleaned_count = 0; | |
809 | } | |
810 | ||
811 | /* use prefetched values */ | |
812 | rx_desc = next_rxd; | |
f8212f97 | 813 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; |
9a799d71 AK |
814 | |
815 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
177db6ff MC |
816 | } |
817 | ||
9a799d71 AK |
818 | rx_ring->next_to_clean = i; |
819 | cleaned_count = IXGBE_DESC_UNUSED(rx_ring); | |
820 | ||
821 | if (cleaned_count) | |
822 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
823 | ||
f494e8fa AV |
824 | rx_ring->total_packets += total_rx_packets; |
825 | rx_ring->total_bytes += total_rx_bytes; | |
826 | adapter->net_stats.rx_bytes += total_rx_bytes; | |
827 | adapter->net_stats.rx_packets += total_rx_packets; | |
828 | ||
9a799d71 AK |
829 | return cleaned; |
830 | } | |
831 | ||
021230d4 | 832 | static int ixgbe_clean_rxonly(struct napi_struct *, int); |
9a799d71 AK |
833 | /** |
834 | * ixgbe_configure_msix - Configure MSI-X hardware | |
835 | * @adapter: board private structure | |
836 | * | |
837 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
838 | * interrupts. | |
839 | **/ | |
840 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
841 | { | |
021230d4 AV |
842 | struct ixgbe_q_vector *q_vector; |
843 | int i, j, q_vectors, v_idx, r_idx; | |
844 | u32 mask; | |
9a799d71 | 845 | |
021230d4 | 846 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 | 847 | |
4df10466 JB |
848 | /* |
849 | * Populate the IVAR table and set the ITR values to the | |
021230d4 AV |
850 | * corresponding register. |
851 | */ | |
852 | for (v_idx = 0; v_idx < q_vectors; v_idx++) { | |
7a921c93 | 853 | q_vector = adapter->q_vector[v_idx]; |
021230d4 AV |
854 | /* XXX for_each_bit(...) */ |
855 | r_idx = find_first_bit(q_vector->rxr_idx, | |
b4617240 | 856 | adapter->num_rx_queues); |
021230d4 AV |
857 | |
858 | for (i = 0; i < q_vector->rxr_count; i++) { | |
859 | j = adapter->rx_ring[r_idx].reg_idx; | |
e8e26350 | 860 | ixgbe_set_ivar(adapter, 0, j, v_idx); |
021230d4 | 861 | r_idx = find_next_bit(q_vector->rxr_idx, |
b4617240 PW |
862 | adapter->num_rx_queues, |
863 | r_idx + 1); | |
021230d4 AV |
864 | } |
865 | r_idx = find_first_bit(q_vector->txr_idx, | |
b4617240 | 866 | adapter->num_tx_queues); |
021230d4 AV |
867 | |
868 | for (i = 0; i < q_vector->txr_count; i++) { | |
869 | j = adapter->tx_ring[r_idx].reg_idx; | |
e8e26350 | 870 | ixgbe_set_ivar(adapter, 1, j, v_idx); |
021230d4 | 871 | r_idx = find_next_bit(q_vector->txr_idx, |
b4617240 PW |
872 | adapter->num_tx_queues, |
873 | r_idx + 1); | |
021230d4 AV |
874 | } |
875 | ||
30efa5a3 | 876 | /* if this is a tx only vector halve the interrupt rate */ |
021230d4 | 877 | if (q_vector->txr_count && !q_vector->rxr_count) |
30efa5a3 | 878 | q_vector->eitr = (adapter->eitr_param >> 1); |
509ee935 | 879 | else if (q_vector->rxr_count) |
30efa5a3 JB |
880 | /* rx only */ |
881 | q_vector->eitr = adapter->eitr_param; | |
021230d4 | 882 | |
fe49f04a | 883 | ixgbe_write_eitr(q_vector); |
9a799d71 AK |
884 | } |
885 | ||
e8e26350 PW |
886 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) |
887 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, | |
888 | v_idx); | |
889 | else if (adapter->hw.mac.type == ixgbe_mac_82599EB) | |
890 | ixgbe_set_ivar(adapter, -1, 1, v_idx); | |
021230d4 AV |
891 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
892 | ||
41fb9248 | 893 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 894 | mask = IXGBE_EIMS_ENABLE_MASK; |
41fb9248 | 895 | mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC); |
021230d4 | 896 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
897 | } |
898 | ||
f494e8fa AV |
899 | enum latency_range { |
900 | lowest_latency = 0, | |
901 | low_latency = 1, | |
902 | bulk_latency = 2, | |
903 | latency_invalid = 255 | |
904 | }; | |
905 | ||
906 | /** | |
907 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
908 | * @adapter: pointer to adapter | |
909 | * @eitr: eitr setting (ints per sec) to give last timeslice | |
910 | * @itr_setting: current throttle rate in ints/second | |
911 | * @packets: the number of packets during this measurement interval | |
912 | * @bytes: the number of bytes during this measurement interval | |
913 | * | |
914 | * Stores a new ITR value based on packets and byte | |
915 | * counts during the last interrupt. The advantage of per interrupt | |
916 | * computation is faster updates and more accurate ITR for the current | |
917 | * traffic pattern. Constants in this function were computed | |
918 | * based on theoretical maximum wire speed and thresholds were set based | |
919 | * on testing data as well as attempting to minimize response time | |
920 | * while increasing bulk throughput. | |
921 | * this functionality is controlled by the InterruptThrottleRate module | |
922 | * parameter (see ixgbe_param.c) | |
923 | **/ | |
924 | static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter, | |
b4617240 PW |
925 | u32 eitr, u8 itr_setting, |
926 | int packets, int bytes) | |
f494e8fa AV |
927 | { |
928 | unsigned int retval = itr_setting; | |
929 | u32 timepassed_us; | |
930 | u64 bytes_perint; | |
931 | ||
932 | if (packets == 0) | |
933 | goto update_itr_done; | |
934 | ||
935 | ||
936 | /* simple throttlerate management | |
937 | * 0-20MB/s lowest (100000 ints/s) | |
938 | * 20-100MB/s low (20000 ints/s) | |
939 | * 100-1249MB/s bulk (8000 ints/s) | |
940 | */ | |
941 | /* what was last interrupt timeslice? */ | |
942 | timepassed_us = 1000000/eitr; | |
943 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ | |
944 | ||
945 | switch (itr_setting) { | |
946 | case lowest_latency: | |
947 | if (bytes_perint > adapter->eitr_low) | |
948 | retval = low_latency; | |
949 | break; | |
950 | case low_latency: | |
951 | if (bytes_perint > adapter->eitr_high) | |
952 | retval = bulk_latency; | |
953 | else if (bytes_perint <= adapter->eitr_low) | |
954 | retval = lowest_latency; | |
955 | break; | |
956 | case bulk_latency: | |
957 | if (bytes_perint <= adapter->eitr_high) | |
958 | retval = low_latency; | |
959 | break; | |
960 | } | |
961 | ||
962 | update_itr_done: | |
963 | return retval; | |
964 | } | |
965 | ||
509ee935 JB |
966 | /** |
967 | * ixgbe_write_eitr - write EITR register in hardware specific way | |
fe49f04a | 968 | * @q_vector: structure containing interrupt and ring information |
509ee935 JB |
969 | * |
970 | * This function is made to be called by ethtool and by the driver | |
971 | * when it needs to update EITR registers at runtime. Hardware | |
972 | * specific quirks/differences are taken care of here. | |
973 | */ | |
fe49f04a | 974 | void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) |
509ee935 | 975 | { |
fe49f04a | 976 | struct ixgbe_adapter *adapter = q_vector->adapter; |
509ee935 | 977 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
978 | int v_idx = q_vector->v_idx; |
979 | u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr); | |
980 | ||
509ee935 JB |
981 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
982 | /* must write high and low 16 bits to reset counter */ | |
983 | itr_reg |= (itr_reg << 16); | |
984 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
985 | /* | |
986 | * set the WDIS bit to not clear the timer bits and cause an | |
987 | * immediate assertion of the interrupt | |
988 | */ | |
989 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
990 | } | |
991 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); | |
992 | } | |
993 | ||
f494e8fa AV |
994 | static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector) |
995 | { | |
996 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
f494e8fa AV |
997 | u32 new_itr; |
998 | u8 current_itr, ret_itr; | |
fe49f04a | 999 | int i, r_idx; |
f494e8fa AV |
1000 | struct ixgbe_ring *rx_ring, *tx_ring; |
1001 | ||
1002 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1003 | for (i = 0; i < q_vector->txr_count; i++) { | |
1004 | tx_ring = &(adapter->tx_ring[r_idx]); | |
1005 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, | |
b4617240 PW |
1006 | q_vector->tx_itr, |
1007 | tx_ring->total_packets, | |
1008 | tx_ring->total_bytes); | |
f494e8fa AV |
1009 | /* if the result for this queue would decrease interrupt |
1010 | * rate for this vector then use that result */ | |
30efa5a3 | 1011 | q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ? |
b4617240 | 1012 | q_vector->tx_itr - 1 : ret_itr); |
f494e8fa | 1013 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 1014 | r_idx + 1); |
f494e8fa AV |
1015 | } |
1016 | ||
1017 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1018 | for (i = 0; i < q_vector->rxr_count; i++) { | |
1019 | rx_ring = &(adapter->rx_ring[r_idx]); | |
1020 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, | |
b4617240 PW |
1021 | q_vector->rx_itr, |
1022 | rx_ring->total_packets, | |
1023 | rx_ring->total_bytes); | |
f494e8fa AV |
1024 | /* if the result for this queue would decrease interrupt |
1025 | * rate for this vector then use that result */ | |
30efa5a3 | 1026 | q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ? |
b4617240 | 1027 | q_vector->rx_itr - 1 : ret_itr); |
f494e8fa | 1028 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
b4617240 | 1029 | r_idx + 1); |
f494e8fa AV |
1030 | } |
1031 | ||
30efa5a3 | 1032 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1033 | |
1034 | switch (current_itr) { | |
1035 | /* counts and packets in update_itr are dependent on these numbers */ | |
1036 | case lowest_latency: | |
1037 | new_itr = 100000; | |
1038 | break; | |
1039 | case low_latency: | |
1040 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1041 | break; | |
1042 | case bulk_latency: | |
1043 | default: | |
1044 | new_itr = 8000; | |
1045 | break; | |
1046 | } | |
1047 | ||
1048 | if (new_itr != q_vector->eitr) { | |
fe49f04a AD |
1049 | /* do an exponential smoothing */ |
1050 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
509ee935 JB |
1051 | |
1052 | /* save the algorithm value here, not the smoothed one */ | |
1053 | q_vector->eitr = new_itr; | |
fe49f04a AD |
1054 | |
1055 | ixgbe_write_eitr(q_vector); | |
f494e8fa AV |
1056 | } |
1057 | ||
1058 | return; | |
1059 | } | |
1060 | ||
0befdb3e JB |
1061 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
1062 | { | |
1063 | struct ixgbe_hw *hw = &adapter->hw; | |
1064 | ||
1065 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
1066 | (eicr & IXGBE_EICR_GPI_SDP1)) { | |
1067 | DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n"); | |
1068 | /* write to clear the interrupt */ | |
1069 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
1070 | } | |
1071 | } | |
cf8280ee | 1072 | |
e8e26350 PW |
1073 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
1074 | { | |
1075 | struct ixgbe_hw *hw = &adapter->hw; | |
1076 | ||
1077 | if (eicr & IXGBE_EICR_GPI_SDP1) { | |
1078 | /* Clear the interrupt */ | |
1079 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
1080 | schedule_work(&adapter->multispeed_fiber_task); | |
1081 | } else if (eicr & IXGBE_EICR_GPI_SDP2) { | |
1082 | /* Clear the interrupt */ | |
1083 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); | |
1084 | schedule_work(&adapter->sfp_config_module_task); | |
1085 | } else { | |
1086 | /* Interrupt isn't for us... */ | |
1087 | return; | |
1088 | } | |
1089 | } | |
1090 | ||
cf8280ee JB |
1091 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
1092 | { | |
1093 | struct ixgbe_hw *hw = &adapter->hw; | |
1094 | ||
1095 | adapter->lsc_int++; | |
1096 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
1097 | adapter->link_check_timeout = jiffies; | |
1098 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
1099 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
1100 | schedule_work(&adapter->watchdog_task); | |
1101 | } | |
1102 | } | |
1103 | ||
9a799d71 AK |
1104 | static irqreturn_t ixgbe_msix_lsc(int irq, void *data) |
1105 | { | |
1106 | struct net_device *netdev = data; | |
1107 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1108 | struct ixgbe_hw *hw = &adapter->hw; | |
54037505 DS |
1109 | u32 eicr; |
1110 | ||
1111 | /* | |
1112 | * Workaround for Silicon errata. Use clear-by-write instead | |
1113 | * of clear-by-read. Reading with EICS will return the | |
1114 | * interrupt causes without clearing, which later be done | |
1115 | * with the write to EICR. | |
1116 | */ | |
1117 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
1118 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); | |
9a799d71 | 1119 | |
cf8280ee JB |
1120 | if (eicr & IXGBE_EICR_LSC) |
1121 | ixgbe_check_lsc(adapter); | |
d4f80882 | 1122 | |
e8e26350 PW |
1123 | if (hw->mac.type == ixgbe_mac_82598EB) |
1124 | ixgbe_check_fan_failure(adapter, eicr); | |
0befdb3e | 1125 | |
c4cf55e5 | 1126 | if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 | 1127 | ixgbe_check_sfp_event(adapter, eicr); |
c4cf55e5 PWJ |
1128 | |
1129 | /* Handle Flow Director Full threshold interrupt */ | |
1130 | if (eicr & IXGBE_EICR_FLOW_DIR) { | |
1131 | int i; | |
1132 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR); | |
1133 | /* Disable transmits before FDIR Re-initialization */ | |
1134 | netif_tx_stop_all_queues(netdev); | |
1135 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
1136 | struct ixgbe_ring *tx_ring = | |
1137 | &adapter->tx_ring[i]; | |
1138 | if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE, | |
1139 | &tx_ring->reinit_state)) | |
1140 | schedule_work(&adapter->fdir_reinit_task); | |
1141 | } | |
1142 | } | |
1143 | } | |
d4f80882 AV |
1144 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
1145 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER); | |
9a799d71 AK |
1146 | |
1147 | return IRQ_HANDLED; | |
1148 | } | |
1149 | ||
fe49f04a AD |
1150 | static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, |
1151 | u64 qmask) | |
1152 | { | |
1153 | u32 mask; | |
1154 | ||
1155 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
1156 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); | |
1157 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); | |
1158 | } else { | |
1159 | mask = (qmask & 0xFFFFFFFF); | |
1160 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask); | |
1161 | mask = (qmask >> 32); | |
1162 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask); | |
1163 | } | |
1164 | /* skip the flush */ | |
1165 | } | |
1166 | ||
1167 | static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, | |
1168 | u64 qmask) | |
1169 | { | |
1170 | u32 mask; | |
1171 | ||
1172 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
1173 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); | |
1174 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask); | |
1175 | } else { | |
1176 | mask = (qmask & 0xFFFFFFFF); | |
1177 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask); | |
1178 | mask = (qmask >> 32); | |
1179 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask); | |
1180 | } | |
1181 | /* skip the flush */ | |
1182 | } | |
1183 | ||
9a799d71 AK |
1184 | static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data) |
1185 | { | |
021230d4 AV |
1186 | struct ixgbe_q_vector *q_vector = data; |
1187 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 1188 | struct ixgbe_ring *tx_ring; |
021230d4 AV |
1189 | int i, r_idx; |
1190 | ||
1191 | if (!q_vector->txr_count) | |
1192 | return IRQ_HANDLED; | |
1193 | ||
1194 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1195 | for (i = 0; i < q_vector->txr_count; i++) { | |
3a581073 | 1196 | tx_ring = &(adapter->tx_ring[r_idx]); |
3a581073 JB |
1197 | tx_ring->total_bytes = 0; |
1198 | tx_ring->total_packets = 0; | |
021230d4 | 1199 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 1200 | r_idx + 1); |
021230d4 | 1201 | } |
9a799d71 | 1202 | |
91281fd3 AD |
1203 | /* disable interrupts on this vector only */ |
1204 | ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
1205 | napi_schedule(&q_vector->napi); | |
1206 | ||
9a799d71 AK |
1207 | return IRQ_HANDLED; |
1208 | } | |
1209 | ||
021230d4 AV |
1210 | /** |
1211 | * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues) | |
1212 | * @irq: unused | |
1213 | * @data: pointer to our q_vector struct for this interrupt vector | |
1214 | **/ | |
9a799d71 AK |
1215 | static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data) |
1216 | { | |
021230d4 AV |
1217 | struct ixgbe_q_vector *q_vector = data; |
1218 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 1219 | struct ixgbe_ring *rx_ring; |
021230d4 | 1220 | int r_idx; |
30efa5a3 | 1221 | int i; |
021230d4 AV |
1222 | |
1223 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
30efa5a3 JB |
1224 | for (i = 0; i < q_vector->rxr_count; i++) { |
1225 | rx_ring = &(adapter->rx_ring[r_idx]); | |
1226 | rx_ring->total_bytes = 0; | |
1227 | rx_ring->total_packets = 0; | |
1228 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1229 | r_idx + 1); | |
1230 | } | |
1231 | ||
021230d4 AV |
1232 | if (!q_vector->rxr_count) |
1233 | return IRQ_HANDLED; | |
1234 | ||
30efa5a3 | 1235 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
3a581073 | 1236 | rx_ring = &(adapter->rx_ring[r_idx]); |
021230d4 | 1237 | /* disable interrupts on this vector only */ |
fe49f04a | 1238 | ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx)); |
288379f0 | 1239 | napi_schedule(&q_vector->napi); |
021230d4 AV |
1240 | |
1241 | return IRQ_HANDLED; | |
1242 | } | |
1243 | ||
1244 | static irqreturn_t ixgbe_msix_clean_many(int irq, void *data) | |
1245 | { | |
91281fd3 AD |
1246 | struct ixgbe_q_vector *q_vector = data; |
1247 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
1248 | struct ixgbe_ring *ring; | |
1249 | int r_idx; | |
1250 | int i; | |
1251 | ||
1252 | if (!q_vector->txr_count && !q_vector->rxr_count) | |
1253 | return IRQ_HANDLED; | |
1254 | ||
1255 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1256 | for (i = 0; i < q_vector->txr_count; i++) { | |
1257 | ring = &(adapter->tx_ring[r_idx]); | |
1258 | ring->total_bytes = 0; | |
1259 | ring->total_packets = 0; | |
1260 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, | |
1261 | r_idx + 1); | |
1262 | } | |
1263 | ||
1264 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1265 | for (i = 0; i < q_vector->rxr_count; i++) { | |
1266 | ring = &(adapter->rx_ring[r_idx]); | |
1267 | ring->total_bytes = 0; | |
1268 | ring->total_packets = 0; | |
1269 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1270 | r_idx + 1); | |
1271 | } | |
1272 | ||
1273 | /* disable interrupts on this vector only */ | |
1274 | ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
1275 | napi_schedule(&q_vector->napi); | |
9a799d71 | 1276 | |
9a799d71 AK |
1277 | return IRQ_HANDLED; |
1278 | } | |
1279 | ||
021230d4 AV |
1280 | /** |
1281 | * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine | |
1282 | * @napi: napi struct with our devices info in it | |
1283 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1284 | * | |
f0848276 JB |
1285 | * This function is optimized for cleaning one queue only on a single |
1286 | * q_vector!!! | |
021230d4 | 1287 | **/ |
9a799d71 AK |
1288 | static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget) |
1289 | { | |
021230d4 | 1290 | struct ixgbe_q_vector *q_vector = |
b4617240 | 1291 | container_of(napi, struct ixgbe_q_vector, napi); |
021230d4 | 1292 | struct ixgbe_adapter *adapter = q_vector->adapter; |
f0848276 | 1293 | struct ixgbe_ring *rx_ring = NULL; |
9a799d71 | 1294 | int work_done = 0; |
021230d4 | 1295 | long r_idx; |
9a799d71 | 1296 | |
021230d4 | 1297 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
3a581073 | 1298 | rx_ring = &(adapter->rx_ring[r_idx]); |
5dd2d332 | 1299 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 1300 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
3a581073 | 1301 | ixgbe_update_rx_dca(adapter, rx_ring); |
bd0362dd | 1302 | #endif |
9a799d71 | 1303 | |
78b6f4ce | 1304 | ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget); |
9a799d71 | 1305 | |
021230d4 AV |
1306 | /* If all Rx work done, exit the polling mode */ |
1307 | if (work_done < budget) { | |
288379f0 | 1308 | napi_complete(napi); |
509ee935 | 1309 | if (adapter->itr_setting & 1) |
f494e8fa | 1310 | ixgbe_set_itr_msix(q_vector); |
9a799d71 | 1311 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
fe49f04a AD |
1312 | ixgbe_irq_enable_queues(adapter, |
1313 | ((u64)1 << q_vector->v_idx)); | |
9a799d71 AK |
1314 | } |
1315 | ||
1316 | return work_done; | |
1317 | } | |
1318 | ||
f0848276 | 1319 | /** |
91281fd3 | 1320 | * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine |
f0848276 JB |
1321 | * @napi: napi struct with our devices info in it |
1322 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1323 | * | |
1324 | * This function will clean more than one rx queue associated with a | |
1325 | * q_vector. | |
1326 | **/ | |
91281fd3 | 1327 | static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget) |
f0848276 JB |
1328 | { |
1329 | struct ixgbe_q_vector *q_vector = | |
1330 | container_of(napi, struct ixgbe_q_vector, napi); | |
1331 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
91281fd3 | 1332 | struct ixgbe_ring *ring = NULL; |
f0848276 JB |
1333 | int work_done = 0, i; |
1334 | long r_idx; | |
91281fd3 AD |
1335 | bool tx_clean_complete = true; |
1336 | ||
1337 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1338 | for (i = 0; i < q_vector->txr_count; i++) { | |
1339 | ring = &(adapter->tx_ring[r_idx]); | |
1340 | #ifdef CONFIG_IXGBE_DCA | |
1341 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
1342 | ixgbe_update_tx_dca(adapter, ring); | |
1343 | #endif | |
1344 | tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring); | |
1345 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, | |
1346 | r_idx + 1); | |
1347 | } | |
f0848276 JB |
1348 | |
1349 | /* attempt to distribute budget to each queue fairly, but don't allow | |
1350 | * the budget to go below 1 because we'll exit polling */ | |
1351 | budget /= (q_vector->rxr_count ?: 1); | |
1352 | budget = max(budget, 1); | |
1353 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1354 | for (i = 0; i < q_vector->rxr_count; i++) { | |
91281fd3 | 1355 | ring = &(adapter->rx_ring[r_idx]); |
5dd2d332 | 1356 | #ifdef CONFIG_IXGBE_DCA |
f0848276 | 1357 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
91281fd3 | 1358 | ixgbe_update_rx_dca(adapter, ring); |
f0848276 | 1359 | #endif |
91281fd3 | 1360 | ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget); |
f0848276 JB |
1361 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
1362 | r_idx + 1); | |
1363 | } | |
1364 | ||
1365 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
91281fd3 | 1366 | ring = &(adapter->rx_ring[r_idx]); |
f0848276 | 1367 | /* If all Rx work done, exit the polling mode */ |
7f821875 | 1368 | if (work_done < budget) { |
288379f0 | 1369 | napi_complete(napi); |
509ee935 | 1370 | if (adapter->itr_setting & 1) |
f0848276 JB |
1371 | ixgbe_set_itr_msix(q_vector); |
1372 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
fe49f04a AD |
1373 | ixgbe_irq_enable_queues(adapter, |
1374 | ((u64)1 << q_vector->v_idx)); | |
f0848276 JB |
1375 | return 0; |
1376 | } | |
1377 | ||
1378 | return work_done; | |
1379 | } | |
91281fd3 AD |
1380 | |
1381 | /** | |
1382 | * ixgbe_clean_txonly - msix (aka one shot) tx clean routine | |
1383 | * @napi: napi struct with our devices info in it | |
1384 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1385 | * | |
1386 | * This function is optimized for cleaning one queue only on a single | |
1387 | * q_vector!!! | |
1388 | **/ | |
1389 | static int ixgbe_clean_txonly(struct napi_struct *napi, int budget) | |
1390 | { | |
1391 | struct ixgbe_q_vector *q_vector = | |
1392 | container_of(napi, struct ixgbe_q_vector, napi); | |
1393 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
1394 | struct ixgbe_ring *tx_ring = NULL; | |
1395 | int work_done = 0; | |
1396 | long r_idx; | |
1397 | ||
1398 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1399 | tx_ring = &(adapter->tx_ring[r_idx]); | |
1400 | #ifdef CONFIG_IXGBE_DCA | |
1401 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
1402 | ixgbe_update_tx_dca(adapter, tx_ring); | |
1403 | #endif | |
1404 | ||
1405 | if (!ixgbe_clean_tx_irq(q_vector, tx_ring)) | |
1406 | work_done = budget; | |
1407 | ||
1408 | /* If all Rx work done, exit the polling mode */ | |
1409 | if (work_done < budget) { | |
1410 | napi_complete(napi); | |
1411 | if (adapter->itr_setting & 1) | |
1412 | ixgbe_set_itr_msix(q_vector); | |
1413 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
1414 | ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
1415 | } | |
1416 | ||
1417 | return work_done; | |
1418 | } | |
1419 | ||
021230d4 | 1420 | static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx, |
b4617240 | 1421 | int r_idx) |
021230d4 | 1422 | { |
7a921c93 AD |
1423 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
1424 | ||
1425 | set_bit(r_idx, q_vector->rxr_idx); | |
1426 | q_vector->rxr_count++; | |
021230d4 AV |
1427 | } |
1428 | ||
1429 | static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx, | |
7a921c93 | 1430 | int t_idx) |
021230d4 | 1431 | { |
7a921c93 AD |
1432 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
1433 | ||
1434 | set_bit(t_idx, q_vector->txr_idx); | |
1435 | q_vector->txr_count++; | |
021230d4 AV |
1436 | } |
1437 | ||
9a799d71 | 1438 | /** |
021230d4 AV |
1439 | * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors |
1440 | * @adapter: board private structure to initialize | |
1441 | * @vectors: allotted vector count for descriptor rings | |
9a799d71 | 1442 | * |
021230d4 AV |
1443 | * This function maps descriptor rings to the queue-specific vectors |
1444 | * we were allotted through the MSI-X enabling code. Ideally, we'd have | |
1445 | * one vector per ring/queue, but on a constrained vector budget, we | |
1446 | * group the rings as "efficiently" as possible. You would add new | |
1447 | * mapping configurations in here. | |
9a799d71 | 1448 | **/ |
021230d4 | 1449 | static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 1450 | int vectors) |
021230d4 AV |
1451 | { |
1452 | int v_start = 0; | |
1453 | int rxr_idx = 0, txr_idx = 0; | |
1454 | int rxr_remaining = adapter->num_rx_queues; | |
1455 | int txr_remaining = adapter->num_tx_queues; | |
1456 | int i, j; | |
1457 | int rqpv, tqpv; | |
1458 | int err = 0; | |
1459 | ||
1460 | /* No mapping required if MSI-X is disabled. */ | |
1461 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
1462 | goto out; | |
9a799d71 | 1463 | |
021230d4 AV |
1464 | /* |
1465 | * The ideal configuration... | |
1466 | * We have enough vectors to map one per queue. | |
1467 | */ | |
1468 | if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) { | |
1469 | for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++) | |
1470 | map_vector_to_rxq(adapter, v_start, rxr_idx); | |
9a799d71 | 1471 | |
021230d4 AV |
1472 | for (; txr_idx < txr_remaining; v_start++, txr_idx++) |
1473 | map_vector_to_txq(adapter, v_start, txr_idx); | |
9a799d71 | 1474 | |
9a799d71 | 1475 | goto out; |
021230d4 | 1476 | } |
9a799d71 | 1477 | |
021230d4 AV |
1478 | /* |
1479 | * If we don't have enough vectors for a 1-to-1 | |
1480 | * mapping, we'll have to group them so there are | |
1481 | * multiple queues per vector. | |
1482 | */ | |
1483 | /* Re-adjusting *qpv takes care of the remainder. */ | |
1484 | for (i = v_start; i < vectors; i++) { | |
1485 | rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i); | |
1486 | for (j = 0; j < rqpv; j++) { | |
1487 | map_vector_to_rxq(adapter, i, rxr_idx); | |
1488 | rxr_idx++; | |
1489 | rxr_remaining--; | |
1490 | } | |
1491 | } | |
1492 | for (i = v_start; i < vectors; i++) { | |
1493 | tqpv = DIV_ROUND_UP(txr_remaining, vectors - i); | |
1494 | for (j = 0; j < tqpv; j++) { | |
1495 | map_vector_to_txq(adapter, i, txr_idx); | |
1496 | txr_idx++; | |
1497 | txr_remaining--; | |
9a799d71 | 1498 | } |
9a799d71 AK |
1499 | } |
1500 | ||
021230d4 AV |
1501 | out: |
1502 | return err; | |
1503 | } | |
1504 | ||
1505 | /** | |
1506 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
1507 | * @adapter: board private structure | |
1508 | * | |
1509 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
1510 | * interrupts from the kernel. | |
1511 | **/ | |
1512 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
1513 | { | |
1514 | struct net_device *netdev = adapter->netdev; | |
1515 | irqreturn_t (*handler)(int, void *); | |
1516 | int i, vector, q_vectors, err; | |
cb13fc20 | 1517 | int ri=0, ti=0; |
021230d4 AV |
1518 | |
1519 | /* Decrement for Other and TCP Timer vectors */ | |
1520 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1521 | ||
1522 | /* Map the Tx/Rx rings to the vectors we were allotted. */ | |
1523 | err = ixgbe_map_rings_to_vectors(adapter, q_vectors); | |
1524 | if (err) | |
1525 | goto out; | |
1526 | ||
1527 | #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \ | |
b4617240 PW |
1528 | (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \ |
1529 | &ixgbe_msix_clean_many) | |
021230d4 | 1530 | for (vector = 0; vector < q_vectors; vector++) { |
7a921c93 | 1531 | handler = SET_HANDLER(adapter->q_vector[vector]); |
cb13fc20 RO |
1532 | |
1533 | if(handler == &ixgbe_msix_clean_rx) { | |
1534 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1535 | netdev->name, "rx", ri++); | |
1536 | } | |
1537 | else if(handler == &ixgbe_msix_clean_tx) { | |
1538 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1539 | netdev->name, "tx", ti++); | |
1540 | } | |
1541 | else | |
1542 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1543 | netdev->name, "TxRx", vector); | |
1544 | ||
021230d4 | 1545 | err = request_irq(adapter->msix_entries[vector].vector, |
b4617240 | 1546 | handler, 0, adapter->name[vector], |
7a921c93 | 1547 | adapter->q_vector[vector]); |
9a799d71 AK |
1548 | if (err) { |
1549 | DPRINTK(PROBE, ERR, | |
b4617240 PW |
1550 | "request_irq failed for MSIX interrupt " |
1551 | "Error: %d\n", err); | |
021230d4 | 1552 | goto free_queue_irqs; |
9a799d71 | 1553 | } |
9a799d71 AK |
1554 | } |
1555 | ||
021230d4 AV |
1556 | sprintf(adapter->name[vector], "%s:lsc", netdev->name); |
1557 | err = request_irq(adapter->msix_entries[vector].vector, | |
b4617240 | 1558 | &ixgbe_msix_lsc, 0, adapter->name[vector], netdev); |
9a799d71 AK |
1559 | if (err) { |
1560 | DPRINTK(PROBE, ERR, | |
1561 | "request_irq for msix_lsc failed: %d\n", err); | |
021230d4 | 1562 | goto free_queue_irqs; |
9a799d71 AK |
1563 | } |
1564 | ||
9a799d71 AK |
1565 | return 0; |
1566 | ||
021230d4 AV |
1567 | free_queue_irqs: |
1568 | for (i = vector - 1; i >= 0; i--) | |
1569 | free_irq(adapter->msix_entries[--vector].vector, | |
7a921c93 | 1570 | adapter->q_vector[i]); |
021230d4 AV |
1571 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
1572 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
1573 | kfree(adapter->msix_entries); |
1574 | adapter->msix_entries = NULL; | |
021230d4 | 1575 | out: |
9a799d71 AK |
1576 | return err; |
1577 | } | |
1578 | ||
f494e8fa AV |
1579 | static void ixgbe_set_itr(struct ixgbe_adapter *adapter) |
1580 | { | |
7a921c93 | 1581 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
f494e8fa AV |
1582 | u8 current_itr; |
1583 | u32 new_itr = q_vector->eitr; | |
1584 | struct ixgbe_ring *rx_ring = &adapter->rx_ring[0]; | |
1585 | struct ixgbe_ring *tx_ring = &adapter->tx_ring[0]; | |
1586 | ||
30efa5a3 | 1587 | q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
1588 | q_vector->tx_itr, |
1589 | tx_ring->total_packets, | |
1590 | tx_ring->total_bytes); | |
30efa5a3 | 1591 | q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
1592 | q_vector->rx_itr, |
1593 | rx_ring->total_packets, | |
1594 | rx_ring->total_bytes); | |
f494e8fa | 1595 | |
30efa5a3 | 1596 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1597 | |
1598 | switch (current_itr) { | |
1599 | /* counts and packets in update_itr are dependent on these numbers */ | |
1600 | case lowest_latency: | |
1601 | new_itr = 100000; | |
1602 | break; | |
1603 | case low_latency: | |
1604 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1605 | break; | |
1606 | case bulk_latency: | |
1607 | new_itr = 8000; | |
1608 | break; | |
1609 | default: | |
1610 | break; | |
1611 | } | |
1612 | ||
1613 | if (new_itr != q_vector->eitr) { | |
fe49f04a AD |
1614 | /* do an exponential smoothing */ |
1615 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
509ee935 JB |
1616 | |
1617 | /* save the algorithm value here, not the smoothed one */ | |
1618 | q_vector->eitr = new_itr; | |
fe49f04a AD |
1619 | |
1620 | ixgbe_write_eitr(q_vector); | |
f494e8fa AV |
1621 | } |
1622 | ||
1623 | return; | |
1624 | } | |
1625 | ||
79aefa45 AD |
1626 | /** |
1627 | * ixgbe_irq_enable - Enable default interrupt generation settings | |
1628 | * @adapter: board private structure | |
1629 | **/ | |
1630 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter) | |
1631 | { | |
1632 | u32 mask; | |
835462fc NS |
1633 | |
1634 | mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); | |
6ab33d51 DM |
1635 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
1636 | mask |= IXGBE_EIMS_GPI_SDP1; | |
e8e26350 | 1637 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
2a41ff81 | 1638 | mask |= IXGBE_EIMS_ECC; |
e8e26350 PW |
1639 | mask |= IXGBE_EIMS_GPI_SDP1; |
1640 | mask |= IXGBE_EIMS_GPI_SDP2; | |
1641 | } | |
c4cf55e5 PWJ |
1642 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
1643 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
1644 | mask |= IXGBE_EIMS_FLOW_DIR; | |
e8e26350 | 1645 | |
79aefa45 | 1646 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
835462fc | 1647 | ixgbe_irq_enable_queues(adapter, ~0); |
79aefa45 AD |
1648 | IXGBE_WRITE_FLUSH(&adapter->hw); |
1649 | } | |
021230d4 | 1650 | |
9a799d71 | 1651 | /** |
021230d4 | 1652 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
1653 | * @irq: interrupt number |
1654 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
1655 | **/ |
1656 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
1657 | { | |
1658 | struct net_device *netdev = data; | |
1659 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1660 | struct ixgbe_hw *hw = &adapter->hw; | |
7a921c93 | 1661 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 AK |
1662 | u32 eicr; |
1663 | ||
54037505 DS |
1664 | /* |
1665 | * Workaround for silicon errata. Mask the interrupts | |
1666 | * before the read of EICR. | |
1667 | */ | |
1668 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
1669 | ||
021230d4 AV |
1670 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
1671 | * therefore no explict interrupt disable is necessary */ | |
1672 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); | |
f47cf66e JB |
1673 | if (!eicr) { |
1674 | /* shared interrupt alert! | |
1675 | * make sure interrupts are enabled because the read will | |
1676 | * have disabled interrupts due to EIAM */ | |
1677 | ixgbe_irq_enable(adapter); | |
9a799d71 | 1678 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 1679 | } |
9a799d71 | 1680 | |
cf8280ee JB |
1681 | if (eicr & IXGBE_EICR_LSC) |
1682 | ixgbe_check_lsc(adapter); | |
021230d4 | 1683 | |
e8e26350 PW |
1684 | if (hw->mac.type == ixgbe_mac_82599EB) |
1685 | ixgbe_check_sfp_event(adapter, eicr); | |
1686 | ||
0befdb3e JB |
1687 | ixgbe_check_fan_failure(adapter, eicr); |
1688 | ||
7a921c93 | 1689 | if (napi_schedule_prep(&(q_vector->napi))) { |
f494e8fa AV |
1690 | adapter->tx_ring[0].total_packets = 0; |
1691 | adapter->tx_ring[0].total_bytes = 0; | |
1692 | adapter->rx_ring[0].total_packets = 0; | |
1693 | adapter->rx_ring[0].total_bytes = 0; | |
021230d4 | 1694 | /* would disable interrupts here but EIAM disabled it */ |
7a921c93 | 1695 | __napi_schedule(&(q_vector->napi)); |
9a799d71 AK |
1696 | } |
1697 | ||
1698 | return IRQ_HANDLED; | |
1699 | } | |
1700 | ||
021230d4 AV |
1701 | static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter) |
1702 | { | |
1703 | int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1704 | ||
1705 | for (i = 0; i < q_vectors; i++) { | |
7a921c93 | 1706 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; |
021230d4 AV |
1707 | bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES); |
1708 | bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES); | |
1709 | q_vector->rxr_count = 0; | |
1710 | q_vector->txr_count = 0; | |
1711 | } | |
1712 | } | |
1713 | ||
9a799d71 AK |
1714 | /** |
1715 | * ixgbe_request_irq - initialize interrupts | |
1716 | * @adapter: board private structure | |
1717 | * | |
1718 | * Attempts to configure interrupts using the best available | |
1719 | * capabilities of the hardware and kernel. | |
1720 | **/ | |
021230d4 | 1721 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
1722 | { |
1723 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 1724 | int err; |
9a799d71 | 1725 | |
021230d4 AV |
1726 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
1727 | err = ixgbe_request_msix_irqs(adapter); | |
1728 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
1729 | err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0, | |
b4617240 | 1730 | netdev->name, netdev); |
021230d4 AV |
1731 | } else { |
1732 | err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED, | |
b4617240 | 1733 | netdev->name, netdev); |
9a799d71 AK |
1734 | } |
1735 | ||
9a799d71 AK |
1736 | if (err) |
1737 | DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err); | |
1738 | ||
9a799d71 AK |
1739 | return err; |
1740 | } | |
1741 | ||
1742 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
1743 | { | |
1744 | struct net_device *netdev = adapter->netdev; | |
1745 | ||
1746 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
021230d4 | 1747 | int i, q_vectors; |
9a799d71 | 1748 | |
021230d4 AV |
1749 | q_vectors = adapter->num_msix_vectors; |
1750 | ||
1751 | i = q_vectors - 1; | |
9a799d71 | 1752 | free_irq(adapter->msix_entries[i].vector, netdev); |
9a799d71 | 1753 | |
021230d4 AV |
1754 | i--; |
1755 | for (; i >= 0; i--) { | |
1756 | free_irq(adapter->msix_entries[i].vector, | |
7a921c93 | 1757 | adapter->q_vector[i]); |
021230d4 AV |
1758 | } |
1759 | ||
1760 | ixgbe_reset_q_vectors(adapter); | |
1761 | } else { | |
1762 | free_irq(adapter->pdev->irq, netdev); | |
9a799d71 AK |
1763 | } |
1764 | } | |
1765 | ||
22d5a71b JB |
1766 | /** |
1767 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
1768 | * @adapter: board private structure | |
1769 | **/ | |
1770 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
1771 | { | |
835462fc NS |
1772 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
1773 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); | |
1774 | } else { | |
1775 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); | |
1776 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); | |
22d5a71b | 1777 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); |
22d5a71b JB |
1778 | } |
1779 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
1780 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
1781 | int i; | |
1782 | for (i = 0; i < adapter->num_msix_vectors; i++) | |
1783 | synchronize_irq(adapter->msix_entries[i].vector); | |
1784 | } else { | |
1785 | synchronize_irq(adapter->pdev->irq); | |
1786 | } | |
1787 | } | |
1788 | ||
9a799d71 AK |
1789 | /** |
1790 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
1791 | * | |
1792 | **/ | |
1793 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
1794 | { | |
9a799d71 AK |
1795 | struct ixgbe_hw *hw = &adapter->hw; |
1796 | ||
021230d4 | 1797 | IXGBE_WRITE_REG(hw, IXGBE_EITR(0), |
30efa5a3 | 1798 | EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param)); |
9a799d71 | 1799 | |
e8e26350 PW |
1800 | ixgbe_set_ivar(adapter, 0, 0, 0); |
1801 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 AV |
1802 | |
1803 | map_vector_to_rxq(adapter, 0, 0); | |
1804 | map_vector_to_txq(adapter, 0, 0); | |
1805 | ||
1806 | DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n"); | |
9a799d71 AK |
1807 | } |
1808 | ||
1809 | /** | |
3a581073 | 1810 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
1811 | * @adapter: board private structure |
1812 | * | |
1813 | * Configure the Tx unit of the MAC after a reset. | |
1814 | **/ | |
1815 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
1816 | { | |
12207e49 | 1817 | u64 tdba; |
9a799d71 | 1818 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 1819 | u32 i, j, tdlen, txctrl; |
9a799d71 AK |
1820 | |
1821 | /* Setup the HW Tx Head and Tail descriptor pointers */ | |
1822 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
e01c31a5 JB |
1823 | struct ixgbe_ring *ring = &adapter->tx_ring[i]; |
1824 | j = ring->reg_idx; | |
1825 | tdba = ring->dma; | |
1826 | tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc); | |
021230d4 | 1827 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j), |
284901a9 | 1828 | (tdba & DMA_BIT_MASK(32))); |
021230d4 AV |
1829 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32)); |
1830 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen); | |
1831 | IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0); | |
1832 | IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0); | |
1833 | adapter->tx_ring[i].head = IXGBE_TDH(j); | |
1834 | adapter->tx_ring[i].tail = IXGBE_TDT(j); | |
1835 | /* Disable Tx Head Writeback RO bit, since this hoses | |
1836 | * bookkeeping if things aren't delivered in order. | |
1837 | */ | |
e01c31a5 | 1838 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j)); |
021230d4 | 1839 | txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; |
e01c31a5 | 1840 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl); |
9a799d71 | 1841 | } |
e8e26350 PW |
1842 | if (hw->mac.type == ixgbe_mac_82599EB) { |
1843 | /* We enable 8 traffic classes, DCB only */ | |
1844 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) | |
1845 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA | | |
1846 | IXGBE_MTQC_8TC_8TQ)); | |
1847 | } | |
9a799d71 AK |
1848 | } |
1849 | ||
e8e26350 | 1850 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c JB |
1851 | |
1852 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index) | |
1853 | { | |
1854 | struct ixgbe_ring *rx_ring; | |
1855 | u32 srrctl; | |
e8e26350 | 1856 | int queue0 = 0; |
3be1adfb | 1857 | unsigned long mask; |
0cefafad | 1858 | struct ixgbe_ring_feature *feature = adapter->ring_feature; |
3be1adfb | 1859 | |
e8e26350 | 1860 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
163de42e | 1861 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
0cefafad | 1862 | int dcb_i = feature[RING_F_DCB].indices; |
163de42e AD |
1863 | if (dcb_i == 8) |
1864 | queue0 = index >> 4; | |
1865 | else if (dcb_i == 4) | |
1866 | queue0 = index >> 5; | |
1867 | else | |
1868 | dev_err(&adapter->pdev->dev, "Invalid DCB " | |
1869 | "configuration\n"); | |
0331a832 YZ |
1870 | #ifdef IXGBE_FCOE |
1871 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
1872 | struct ixgbe_ring_feature *f; | |
1873 | ||
1874 | rx_ring = &adapter->rx_ring[queue0]; | |
1875 | f = &adapter->ring_feature[RING_F_FCOE]; | |
1876 | if ((queue0 == 0) && (index > rx_ring->reg_idx)) | |
1877 | queue0 = f->mask + index - | |
1878 | rx_ring->reg_idx - 1; | |
1879 | } | |
1880 | #endif /* IXGBE_FCOE */ | |
163de42e AD |
1881 | } else { |
1882 | queue0 = index; | |
1883 | } | |
cc41ac7c | 1884 | } else { |
0cefafad | 1885 | mask = (unsigned long) feature[RING_F_RSS].mask; |
3be1adfb AD |
1886 | queue0 = index & mask; |
1887 | index = index & mask; | |
cc41ac7c | 1888 | } |
3be1adfb | 1889 | |
cc41ac7c JB |
1890 | rx_ring = &adapter->rx_ring[queue0]; |
1891 | ||
1892 | srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index)); | |
1893 | ||
1894 | srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; | |
1895 | srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; | |
1896 | ||
afafd5b0 AD |
1897 | srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & |
1898 | IXGBE_SRRCTL_BSIZEHDR_MASK; | |
1899 | ||
cc41ac7c | 1900 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { |
afafd5b0 AD |
1901 | #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER |
1902 | srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
1903 | #else | |
1904 | srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
1905 | #endif | |
cc41ac7c | 1906 | srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; |
cc41ac7c | 1907 | } else { |
afafd5b0 AD |
1908 | srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >> |
1909 | IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
cc41ac7c | 1910 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
cc41ac7c | 1911 | } |
e8e26350 | 1912 | |
cc41ac7c JB |
1913 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl); |
1914 | } | |
9a799d71 | 1915 | |
0cefafad JB |
1916 | static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) |
1917 | { | |
1918 | u32 mrqc = 0; | |
1919 | int mask; | |
1920 | ||
1921 | if (!(adapter->hw.mac.type == ixgbe_mac_82599EB)) | |
1922 | return mrqc; | |
1923 | ||
1924 | mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED | |
1925 | #ifdef CONFIG_IXGBE_DCB | |
1926 | | IXGBE_FLAG_DCB_ENABLED | |
1927 | #endif | |
1928 | ); | |
1929 | ||
1930 | switch (mask) { | |
1931 | case (IXGBE_FLAG_RSS_ENABLED): | |
1932 | mrqc = IXGBE_MRQC_RSSEN; | |
1933 | break; | |
1934 | #ifdef CONFIG_IXGBE_DCB | |
1935 | case (IXGBE_FLAG_DCB_ENABLED): | |
1936 | mrqc = IXGBE_MRQC_RT8TCEN; | |
1937 | break; | |
1938 | #endif /* CONFIG_IXGBE_DCB */ | |
1939 | default: | |
1940 | break; | |
1941 | } | |
1942 | ||
1943 | return mrqc; | |
1944 | } | |
1945 | ||
9a799d71 | 1946 | /** |
3a581073 | 1947 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset |
9a799d71 AK |
1948 | * @adapter: board private structure |
1949 | * | |
1950 | * Configure the Rx unit of the MAC after a reset. | |
1951 | **/ | |
1952 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
1953 | { | |
1954 | u64 rdba; | |
1955 | struct ixgbe_hw *hw = &adapter->hw; | |
1956 | struct net_device *netdev = adapter->netdev; | |
1957 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
021230d4 | 1958 | int i, j; |
9a799d71 | 1959 | u32 rdlen, rxctrl, rxcsum; |
7c6e0a43 JB |
1960 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, |
1961 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, | |
1962 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
9a799d71 | 1963 | u32 fctrl, hlreg0; |
509ee935 | 1964 | u32 reta = 0, mrqc = 0; |
cc41ac7c | 1965 | u32 rdrxctl; |
f8212f97 | 1966 | u32 rscctrl; |
7c6e0a43 | 1967 | int rx_buf_len; |
9a799d71 AK |
1968 | |
1969 | /* Decide whether to use packet split mode or not */ | |
762f4c57 | 1970 | adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED; |
9a799d71 | 1971 | |
eacd73f7 YZ |
1972 | #ifdef IXGBE_FCOE |
1973 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
1974 | adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED; | |
1975 | #endif /* IXGBE_FCOE */ | |
1976 | ||
9a799d71 AK |
1977 | /* Set the RX buffer length according to the mode */ |
1978 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 | 1979 | rx_buf_len = IXGBE_RX_HDR_SIZE; |
e8e26350 PW |
1980 | if (hw->mac.type == ixgbe_mac_82599EB) { |
1981 | /* PSRTYPE must be initialized in 82599 */ | |
1982 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
1983 | IXGBE_PSRTYPE_UDPHDR | | |
1984 | IXGBE_PSRTYPE_IPV4HDR | | |
dfa12f05 YZ |
1985 | IXGBE_PSRTYPE_IPV6HDR | |
1986 | IXGBE_PSRTYPE_L2HDR; | |
e8e26350 PW |
1987 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype); |
1988 | } | |
9a799d71 | 1989 | } else { |
df647b5c | 1990 | if (!(adapter->flags & IXGBE_FLAG2_RSC_ENABLED) && |
f8212f97 | 1991 | (netdev->mtu <= ETH_DATA_LEN)) |
7c6e0a43 | 1992 | rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
9a799d71 | 1993 | else |
7c6e0a43 | 1994 | rx_buf_len = ALIGN(max_frame, 1024); |
9a799d71 AK |
1995 | } |
1996 | ||
1997 | fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL); | |
1998 | fctrl |= IXGBE_FCTRL_BAM; | |
021230d4 | 1999 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ |
e8e26350 | 2000 | fctrl |= IXGBE_FCTRL_PMCF; |
9a799d71 AK |
2001 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl); |
2002 | ||
2003 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |
2004 | if (adapter->netdev->mtu <= ETH_DATA_LEN) | |
2005 | hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; | |
2006 | else | |
2007 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
63f39bd1 YZ |
2008 | #ifdef IXGBE_FCOE |
2009 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
2010 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
2011 | #endif | |
9a799d71 AK |
2012 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); |
2013 | ||
9a799d71 AK |
2014 | rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc); |
2015 | /* disable receives while setting up the descriptors */ | |
2016 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
2017 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
2018 | ||
0cefafad JB |
2019 | /* |
2020 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
2021 | * the Base and Length of the Rx Descriptor Ring | |
2022 | */ | |
9a799d71 AK |
2023 | for (i = 0; i < adapter->num_rx_queues; i++) { |
2024 | rdba = adapter->rx_ring[i].dma; | |
7c6e0a43 | 2025 | j = adapter->rx_ring[i].reg_idx; |
284901a9 | 2026 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32))); |
7c6e0a43 JB |
2027 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32)); |
2028 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen); | |
2029 | IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0); | |
2030 | IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0); | |
2031 | adapter->rx_ring[i].head = IXGBE_RDH(j); | |
2032 | adapter->rx_ring[i].tail = IXGBE_RDT(j); | |
2033 | adapter->rx_ring[i].rx_buf_len = rx_buf_len; | |
cc41ac7c | 2034 | |
63f39bd1 YZ |
2035 | #ifdef IXGBE_FCOE |
2036 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
2037 | struct ixgbe_ring_feature *f; | |
2038 | f = &adapter->ring_feature[RING_F_FCOE]; | |
2039 | if ((rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) && | |
2040 | (i >= f->mask) && (i < f->mask + f->indices)) | |
2041 | adapter->rx_ring[i].rx_buf_len = | |
2042 | IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
2043 | } | |
2044 | ||
2045 | #endif /* IXGBE_FCOE */ | |
cc41ac7c | 2046 | ixgbe_configure_srrctl(adapter, j); |
9a799d71 AK |
2047 | } |
2048 | ||
e8e26350 PW |
2049 | if (hw->mac.type == ixgbe_mac_82598EB) { |
2050 | /* | |
2051 | * For VMDq support of different descriptor types or | |
2052 | * buffer sizes through the use of multiple SRRCTL | |
2053 | * registers, RDRXCTL.MVMEN must be set to 1 | |
2054 | * | |
2055 | * also, the manual doesn't mention it clearly but DCA hints | |
2056 | * will only use queue 0's tags unless this bit is set. Side | |
2057 | * effects of setting this bit are only that SRRCTL must be | |
2058 | * fully programmed [0..15] | |
2059 | */ | |
2a41ff81 JB |
2060 | rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); |
2061 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
2062 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
2f90b865 | 2063 | } |
177db6ff | 2064 | |
e8e26350 | 2065 | /* Program MRQC for the distribution of queues */ |
0cefafad | 2066 | mrqc = ixgbe_setup_mrqc(adapter); |
e8e26350 | 2067 | |
021230d4 | 2068 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { |
9a799d71 | 2069 | /* Fill out redirection table */ |
021230d4 AV |
2070 | for (i = 0, j = 0; i < 128; i++, j++) { |
2071 | if (j == adapter->ring_feature[RING_F_RSS].indices) | |
2072 | j = 0; | |
2073 | /* reta = 4-byte sliding window of | |
2074 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
2075 | reta = (reta << 8) | (j * 0x11); | |
2076 | if ((i & 3) == 3) | |
2077 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
9a799d71 AK |
2078 | } |
2079 | ||
2080 | /* Fill out hash function seeds */ | |
2081 | for (i = 0; i < 10; i++) | |
7c6e0a43 | 2082 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); |
9a799d71 | 2083 | |
2a41ff81 JB |
2084 | if (hw->mac.type == ixgbe_mac_82598EB) |
2085 | mrqc |= IXGBE_MRQC_RSSEN; | |
9a799d71 | 2086 | /* Perform hash on these packet types */ |
2a41ff81 JB |
2087 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
2088 | | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | |
2089 | | IXGBE_MRQC_RSS_FIELD_IPV4_UDP | |
2090 | | IXGBE_MRQC_RSS_FIELD_IPV6 | |
2091 | | IXGBE_MRQC_RSS_FIELD_IPV6_TCP | |
2092 | | IXGBE_MRQC_RSS_FIELD_IPV6_UDP; | |
021230d4 | 2093 | } |
2a41ff81 | 2094 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); |
9a799d71 | 2095 | |
021230d4 AV |
2096 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); |
2097 | ||
2098 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED || | |
2099 | adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) { | |
2100 | /* Disable indicating checksum in descriptor, enables | |
2101 | * RSS hash */ | |
9a799d71 | 2102 | rxcsum |= IXGBE_RXCSUM_PCSD; |
9a799d71 | 2103 | } |
021230d4 AV |
2104 | if (!(rxcsum & IXGBE_RXCSUM_PCSD)) { |
2105 | /* Enable IPv4 payload checksum for UDP fragments | |
2106 | * if PCSD is not set */ | |
2107 | rxcsum |= IXGBE_RXCSUM_IPPCSE; | |
2108 | } | |
2109 | ||
2110 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
e8e26350 PW |
2111 | |
2112 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
2113 | rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
2114 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
f8212f97 | 2115 | rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; |
e8e26350 PW |
2116 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); |
2117 | } | |
f8212f97 | 2118 | |
df647b5c | 2119 | if (adapter->flags & IXGBE_FLAG2_RSC_ENABLED) { |
f8212f97 AD |
2120 | /* Enable 82599 HW-RSC */ |
2121 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
2122 | j = adapter->rx_ring[i].reg_idx; | |
2123 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j)); | |
2124 | rscctrl |= IXGBE_RSCCTL_RSCEN; | |
2125 | /* | |
e76678dd AD |
2126 | * we must limit the number of descriptors so that the |
2127 | * total size of max desc * buf_len is not greater | |
2128 | * than 65535 | |
f8212f97 | 2129 | */ |
e76678dd AD |
2130 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { |
2131 | #if (MAX_SKB_FRAGS > 16) | |
2132 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2133 | #elif (MAX_SKB_FRAGS > 8) | |
f8212f97 | 2134 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; |
e76678dd AD |
2135 | #elif (MAX_SKB_FRAGS > 4) |
2136 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
f8212f97 | 2137 | #else |
e76678dd | 2138 | rscctrl |= IXGBE_RSCCTL_MAXDESC_1; |
f8212f97 | 2139 | #endif |
e76678dd AD |
2140 | } else { |
2141 | if (rx_buf_len < IXGBE_RXBUFFER_4096) | |
2142 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2143 | else if (rx_buf_len < IXGBE_RXBUFFER_8192) | |
2144 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
2145 | else | |
2146 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
2147 | } | |
f8212f97 AD |
2148 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl); |
2149 | } | |
2150 | /* Disable RSC for ACK packets */ | |
2151 | IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, | |
2152 | (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); | |
2153 | } | |
9a799d71 AK |
2154 | } |
2155 | ||
068c89b0 DS |
2156 | static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
2157 | { | |
2158 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2159 | struct ixgbe_hw *hw = &adapter->hw; | |
2160 | ||
2161 | /* add VID to filter table */ | |
2162 | hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true); | |
2163 | } | |
2164 | ||
2165 | static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |
2166 | { | |
2167 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2168 | struct ixgbe_hw *hw = &adapter->hw; | |
2169 | ||
2170 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2171 | ixgbe_irq_disable(adapter); | |
2172 | ||
2173 | vlan_group_set_device(adapter->vlgrp, vid, NULL); | |
2174 | ||
2175 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2176 | ixgbe_irq_enable(adapter); | |
2177 | ||
2178 | /* remove VID from filter table */ | |
2179 | hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false); | |
2180 | } | |
2181 | ||
9a799d71 | 2182 | static void ixgbe_vlan_rx_register(struct net_device *netdev, |
b4617240 | 2183 | struct vlan_group *grp) |
9a799d71 AK |
2184 | { |
2185 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2186 | u32 ctrl; | |
e8e26350 | 2187 | int i, j; |
9a799d71 | 2188 | |
d4f80882 AV |
2189 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2190 | ixgbe_irq_disable(adapter); | |
9a799d71 AK |
2191 | adapter->vlgrp = grp; |
2192 | ||
2f90b865 AD |
2193 | /* |
2194 | * For a DCB driver, always enable VLAN tag stripping so we can | |
2195 | * still receive traffic from a DCB-enabled host even if we're | |
2196 | * not in DCB mode. | |
2197 | */ | |
2198 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL); | |
e8e26350 PW |
2199 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
2200 | ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE; | |
2201 | ctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2202 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl); | |
2203 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
2204 | ctrl |= IXGBE_VLNCTRL_VFE; | |
9a799d71 AK |
2205 | /* enable VLAN tag insert/strip */ |
2206 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL); | |
9a799d71 AK |
2207 | ctrl &= ~IXGBE_VLNCTRL_CFIEN; |
2208 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl); | |
e8e26350 PW |
2209 | for (i = 0; i < adapter->num_rx_queues; i++) { |
2210 | j = adapter->rx_ring[i].reg_idx; | |
2211 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j)); | |
2212 | ctrl |= IXGBE_RXDCTL_VME; | |
2213 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl); | |
2214 | } | |
9a799d71 | 2215 | } |
e8e26350 | 2216 | ixgbe_vlan_rx_add_vid(netdev, 0); |
9a799d71 | 2217 | |
d4f80882 AV |
2218 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2219 | ixgbe_irq_enable(adapter); | |
9a799d71 AK |
2220 | } |
2221 | ||
9a799d71 AK |
2222 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
2223 | { | |
2224 | ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp); | |
2225 | ||
2226 | if (adapter->vlgrp) { | |
2227 | u16 vid; | |
2228 | for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) { | |
2229 | if (!vlan_group_get_device(adapter->vlgrp, vid)) | |
2230 | continue; | |
2231 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
2232 | } | |
2233 | } | |
2234 | } | |
2235 | ||
2c5645cf CL |
2236 | static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq) |
2237 | { | |
2238 | struct dev_mc_list *mc_ptr; | |
2239 | u8 *addr = *mc_addr_ptr; | |
2240 | *vmdq = 0; | |
2241 | ||
2242 | mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]); | |
2243 | if (mc_ptr->next) | |
2244 | *mc_addr_ptr = mc_ptr->next->dmi_addr; | |
2245 | else | |
2246 | *mc_addr_ptr = NULL; | |
2247 | ||
2248 | return addr; | |
2249 | } | |
2250 | ||
9a799d71 | 2251 | /** |
2c5645cf | 2252 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
2253 | * @netdev: network interface device structure |
2254 | * | |
2c5645cf CL |
2255 | * The set_rx_method entry point is called whenever the unicast/multicast |
2256 | * address list or the network interface flags are updated. This routine is | |
2257 | * responsible for configuring the hardware for proper unicast, multicast and | |
2258 | * promiscuous mode. | |
9a799d71 | 2259 | **/ |
2c5645cf | 2260 | static void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
2261 | { |
2262 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2263 | struct ixgbe_hw *hw = &adapter->hw; | |
3d01625a | 2264 | u32 fctrl, vlnctrl; |
2c5645cf CL |
2265 | u8 *addr_list = NULL; |
2266 | int addr_count = 0; | |
9a799d71 AK |
2267 | |
2268 | /* Check for Promiscuous and All Multicast modes */ | |
2269 | ||
2270 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3d01625a | 2271 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
9a799d71 AK |
2272 | |
2273 | if (netdev->flags & IFF_PROMISC) { | |
2c5645cf | 2274 | hw->addr_ctrl.user_set_promisc = 1; |
9a799d71 | 2275 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
3d01625a | 2276 | vlnctrl &= ~IXGBE_VLNCTRL_VFE; |
9a799d71 | 2277 | } else { |
746b9f02 PM |
2278 | if (netdev->flags & IFF_ALLMULTI) { |
2279 | fctrl |= IXGBE_FCTRL_MPE; | |
2280 | fctrl &= ~IXGBE_FCTRL_UPE; | |
2281 | } else { | |
2282 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
2283 | } | |
3d01625a | 2284 | vlnctrl |= IXGBE_VLNCTRL_VFE; |
2c5645cf | 2285 | hw->addr_ctrl.user_set_promisc = 0; |
9a799d71 AK |
2286 | } |
2287 | ||
2288 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
3d01625a | 2289 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
9a799d71 | 2290 | |
2c5645cf | 2291 | /* reprogram secondary unicast list */ |
ccffad25 | 2292 | hw->mac.ops.update_uc_addr_list(hw, &netdev->uc_list); |
9a799d71 | 2293 | |
2c5645cf CL |
2294 | /* reprogram multicast list */ |
2295 | addr_count = netdev->mc_count; | |
2296 | if (addr_count) | |
2297 | addr_list = netdev->mc_list->dmi_addr; | |
c44ade9e JB |
2298 | hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count, |
2299 | ixgbe_addr_list_itr); | |
9a799d71 AK |
2300 | } |
2301 | ||
021230d4 AV |
2302 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
2303 | { | |
2304 | int q_idx; | |
2305 | struct ixgbe_q_vector *q_vector; | |
2306 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2307 | ||
2308 | /* legacy and MSI only use one vector */ | |
2309 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2310 | q_vectors = 1; | |
2311 | ||
2312 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
f0848276 | 2313 | struct napi_struct *napi; |
7a921c93 | 2314 | q_vector = adapter->q_vector[q_idx]; |
f0848276 | 2315 | napi = &q_vector->napi; |
91281fd3 AD |
2316 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
2317 | if (!q_vector->rxr_count || !q_vector->txr_count) { | |
2318 | if (q_vector->txr_count == 1) | |
2319 | napi->poll = &ixgbe_clean_txonly; | |
2320 | else if (q_vector->rxr_count == 1) | |
2321 | napi->poll = &ixgbe_clean_rxonly; | |
2322 | } | |
2323 | } | |
f0848276 JB |
2324 | |
2325 | napi_enable(napi); | |
021230d4 AV |
2326 | } |
2327 | } | |
2328 | ||
2329 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
2330 | { | |
2331 | int q_idx; | |
2332 | struct ixgbe_q_vector *q_vector; | |
2333 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2334 | ||
2335 | /* legacy and MSI only use one vector */ | |
2336 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2337 | q_vectors = 1; | |
2338 | ||
2339 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
7a921c93 | 2340 | q_vector = adapter->q_vector[q_idx]; |
021230d4 AV |
2341 | napi_disable(&q_vector->napi); |
2342 | } | |
2343 | } | |
2344 | ||
7a6b6f51 | 2345 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
2346 | /* |
2347 | * ixgbe_configure_dcb - Configure DCB hardware | |
2348 | * @adapter: ixgbe adapter struct | |
2349 | * | |
2350 | * This is called by the driver on open to configure the DCB hardware. | |
2351 | * This is also called by the gennetlink interface when reconfiguring | |
2352 | * the DCB state. | |
2353 | */ | |
2354 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
2355 | { | |
2356 | struct ixgbe_hw *hw = &adapter->hw; | |
2357 | u32 txdctl, vlnctrl; | |
2358 | int i, j; | |
2359 | ||
2360 | ixgbe_dcb_check_config(&adapter->dcb_cfg); | |
2361 | ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG); | |
2362 | ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG); | |
2363 | ||
2364 | /* reconfigure the hardware */ | |
2365 | ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg); | |
2366 | ||
2367 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2368 | j = adapter->tx_ring[i].reg_idx; | |
2369 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
2370 | /* PThresh workaround for Tx hang with DFP enabled. */ | |
2371 | txdctl |= 32; | |
2372 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); | |
2373 | } | |
2374 | /* Enable VLAN tag insert/strip */ | |
2375 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
e8e26350 PW |
2376 | if (hw->mac.type == ixgbe_mac_82598EB) { |
2377 | vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE; | |
2378 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2379 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
2380 | } else if (hw->mac.type == ixgbe_mac_82599EB) { | |
2381 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
2382 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2383 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
2384 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
2385 | j = adapter->rx_ring[i].reg_idx; | |
2386 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
2387 | vlnctrl |= IXGBE_RXDCTL_VME; | |
2388 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
2389 | } | |
2390 | } | |
2f90b865 AD |
2391 | hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); |
2392 | } | |
2393 | ||
2394 | #endif | |
9a799d71 AK |
2395 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
2396 | { | |
2397 | struct net_device *netdev = adapter->netdev; | |
c4cf55e5 | 2398 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
2399 | int i; |
2400 | ||
2c5645cf | 2401 | ixgbe_set_rx_mode(netdev); |
9a799d71 AK |
2402 | |
2403 | ixgbe_restore_vlan(adapter); | |
7a6b6f51 | 2404 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
2405 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
2406 | netif_set_gso_max_size(netdev, 32768); | |
2407 | ixgbe_configure_dcb(adapter); | |
2408 | } else { | |
2409 | netif_set_gso_max_size(netdev, 65536); | |
2410 | } | |
2411 | #else | |
2412 | netif_set_gso_max_size(netdev, 65536); | |
2413 | #endif | |
9a799d71 | 2414 | |
eacd73f7 YZ |
2415 | #ifdef IXGBE_FCOE |
2416 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
2417 | ixgbe_configure_fcoe(adapter); | |
2418 | ||
2419 | #endif /* IXGBE_FCOE */ | |
c4cf55e5 PWJ |
2420 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
2421 | for (i = 0; i < adapter->num_tx_queues; i++) | |
2422 | adapter->tx_ring[i].atr_sample_rate = | |
2423 | adapter->atr_sample_rate; | |
2424 | ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc); | |
2425 | } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { | |
2426 | ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc); | |
2427 | } | |
2428 | ||
9a799d71 AK |
2429 | ixgbe_configure_tx(adapter); |
2430 | ixgbe_configure_rx(adapter); | |
2431 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2432 | ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i], | |
b4617240 | 2433 | (adapter->rx_ring[i].count - 1)); |
9a799d71 AK |
2434 | } |
2435 | ||
e8e26350 PW |
2436 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
2437 | { | |
2438 | switch (hw->phy.type) { | |
2439 | case ixgbe_phy_sfp_avago: | |
2440 | case ixgbe_phy_sfp_ftl: | |
2441 | case ixgbe_phy_sfp_intel: | |
2442 | case ixgbe_phy_sfp_unknown: | |
2443 | case ixgbe_phy_tw_tyco: | |
2444 | case ixgbe_phy_tw_unknown: | |
2445 | return true; | |
2446 | default: | |
2447 | return false; | |
2448 | } | |
2449 | } | |
2450 | ||
0ecc061d | 2451 | /** |
e8e26350 PW |
2452 | * ixgbe_sfp_link_config - set up SFP+ link |
2453 | * @adapter: pointer to private adapter struct | |
2454 | **/ | |
2455 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
2456 | { | |
2457 | struct ixgbe_hw *hw = &adapter->hw; | |
2458 | ||
2459 | if (hw->phy.multispeed_fiber) { | |
2460 | /* | |
2461 | * In multispeed fiber setups, the device may not have | |
2462 | * had a physical connection when the driver loaded. | |
2463 | * If that's the case, the initial link configuration | |
2464 | * couldn't get the MAC into 10G or 1G mode, so we'll | |
2465 | * never have a link status change interrupt fire. | |
2466 | * We need to try and force an autonegotiation | |
2467 | * session, then bring up link. | |
2468 | */ | |
2469 | hw->mac.ops.setup_sfp(hw); | |
2470 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) | |
2471 | schedule_work(&adapter->multispeed_fiber_task); | |
2472 | } else { | |
2473 | /* | |
2474 | * Direct Attach Cu and non-multispeed fiber modules | |
2475 | * still need to be configured properly prior to | |
2476 | * attempting link. | |
2477 | */ | |
2478 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK)) | |
2479 | schedule_work(&adapter->sfp_config_module_task); | |
2480 | } | |
2481 | } | |
2482 | ||
2483 | /** | |
2484 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
2485 | * @hw: pointer to private hardware struct |
2486 | * | |
2487 | * Returns 0 on success, negative on failure | |
2488 | **/ | |
e8e26350 | 2489 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d PWJ |
2490 | { |
2491 | u32 autoneg; | |
2492 | bool link_up = false; | |
2493 | u32 ret = IXGBE_ERR_LINK_SETUP; | |
2494 | ||
2495 | if (hw->mac.ops.check_link) | |
2496 | ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
2497 | ||
2498 | if (ret) | |
2499 | goto link_cfg_out; | |
2500 | ||
2501 | if (hw->mac.ops.get_link_capabilities) | |
2502 | ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, | |
2503 | &hw->mac.autoneg); | |
2504 | if (ret) | |
2505 | goto link_cfg_out; | |
2506 | ||
2507 | if (hw->mac.ops.setup_link_speed) | |
2508 | ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up); | |
0ecc061d PWJ |
2509 | link_cfg_out: |
2510 | return ret; | |
2511 | } | |
2512 | ||
e8e26350 PW |
2513 | #define IXGBE_MAX_RX_DESC_POLL 10 |
2514 | static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
2515 | int rxr) | |
2516 | { | |
2517 | int j = adapter->rx_ring[rxr].reg_idx; | |
2518 | int k; | |
2519 | ||
2520 | for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) { | |
2521 | if (IXGBE_READ_REG(&adapter->hw, | |
2522 | IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE) | |
2523 | break; | |
2524 | else | |
2525 | msleep(1); | |
2526 | } | |
2527 | if (k >= IXGBE_MAX_RX_DESC_POLL) { | |
2528 | DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d " | |
2529 | "not set within the polling period\n", rxr); | |
2530 | } | |
2531 | ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr], | |
2532 | (adapter->rx_ring[rxr].count - 1)); | |
2533 | } | |
2534 | ||
9a799d71 AK |
2535 | static int ixgbe_up_complete(struct ixgbe_adapter *adapter) |
2536 | { | |
2537 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 2538 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 2539 | int i, j = 0; |
e8e26350 | 2540 | int num_rx_rings = adapter->num_rx_queues; |
0ecc061d | 2541 | int err; |
9a799d71 | 2542 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
021230d4 | 2543 | u32 txdctl, rxdctl, mhadd; |
e8e26350 | 2544 | u32 dmatxctl; |
021230d4 | 2545 | u32 gpie; |
9a799d71 | 2546 | |
5eba3699 AV |
2547 | ixgbe_get_hw_control(adapter); |
2548 | ||
021230d4 AV |
2549 | if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) || |
2550 | (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) { | |
9a799d71 AK |
2551 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
2552 | gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME | | |
b4617240 | 2553 | IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD); |
9a799d71 AK |
2554 | } else { |
2555 | /* MSI only */ | |
021230d4 | 2556 | gpie = 0; |
9a799d71 | 2557 | } |
021230d4 AV |
2558 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
2559 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
2560 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
9a799d71 AK |
2561 | } |
2562 | ||
021230d4 AV |
2563 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
2564 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, | |
2565 | * specifically only auto mask tx and rx interrupts */ | |
2566 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
2567 | } | |
9a799d71 | 2568 | |
0befdb3e JB |
2569 | /* Enable fan failure interrupt if media type is copper */ |
2570 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
2571 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
2572 | gpie |= IXGBE_SDP1_GPIEN; | |
2573 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
2574 | } | |
2575 | ||
e8e26350 PW |
2576 | if (hw->mac.type == ixgbe_mac_82599EB) { |
2577 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
2578 | gpie |= IXGBE_SDP1_GPIEN; | |
2579 | gpie |= IXGBE_SDP2_GPIEN; | |
2580 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
2581 | } | |
2582 | ||
63f39bd1 YZ |
2583 | #ifdef IXGBE_FCOE |
2584 | /* adjust max frame to be able to do baby jumbo for FCoE */ | |
2585 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
2586 | (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) | |
2587 | max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
2588 | ||
2589 | #endif /* IXGBE_FCOE */ | |
021230d4 | 2590 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); |
9a799d71 AK |
2591 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { |
2592 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
2593 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
2594 | ||
2595 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
2596 | } | |
2597 | ||
2598 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
021230d4 AV |
2599 | j = adapter->tx_ring[i].reg_idx; |
2600 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
e01c31a5 JB |
2601 | /* enable WTHRESH=8 descriptors, to encourage burst writeback */ |
2602 | txdctl |= (8 << 16); | |
e8e26350 PW |
2603 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); |
2604 | } | |
2605 | ||
2606 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
2607 | /* DMATXCTL.EN must be set after all Tx queue config is done */ | |
2608 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
2609 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
2610 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
2611 | } | |
2612 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2613 | j = adapter->tx_ring[i].reg_idx; | |
2614 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
9a799d71 | 2615 | txdctl |= IXGBE_TXDCTL_ENABLE; |
021230d4 | 2616 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); |
9a799d71 AK |
2617 | } |
2618 | ||
e8e26350 | 2619 | for (i = 0; i < num_rx_rings; i++) { |
021230d4 AV |
2620 | j = adapter->rx_ring[i].reg_idx; |
2621 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
2622 | /* enable PTHRESH=32 descriptors (half the internal cache) | |
2623 | * and HTHRESH=0 descriptors (to minimize latency on fetch), | |
2624 | * this also removes a pesky rx_no_buffer_count increment */ | |
2625 | rxdctl |= 0x0020; | |
9a799d71 | 2626 | rxdctl |= IXGBE_RXDCTL_ENABLE; |
021230d4 | 2627 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl); |
e8e26350 PW |
2628 | if (hw->mac.type == ixgbe_mac_82599EB) |
2629 | ixgbe_rx_desc_queue_enable(adapter, i); | |
9a799d71 AK |
2630 | } |
2631 | /* enable all receives */ | |
2632 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
e8e26350 PW |
2633 | if (hw->mac.type == ixgbe_mac_82598EB) |
2634 | rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN); | |
2635 | else | |
2636 | rxdctl |= IXGBE_RXCTRL_RXEN; | |
2637 | hw->mac.ops.enable_rx_dma(hw, rxdctl); | |
9a799d71 AK |
2638 | |
2639 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) | |
2640 | ixgbe_configure_msix(adapter); | |
2641 | else | |
2642 | ixgbe_configure_msi_and_legacy(adapter); | |
2643 | ||
2644 | clear_bit(__IXGBE_DOWN, &adapter->state); | |
021230d4 AV |
2645 | ixgbe_napi_enable_all(adapter); |
2646 | ||
2647 | /* clear any pending interrupts, may auto mask */ | |
2648 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
2649 | ||
9a799d71 AK |
2650 | ixgbe_irq_enable(adapter); |
2651 | ||
bf069c97 DS |
2652 | /* |
2653 | * If this adapter has a fan, check to see if we had a failure | |
2654 | * before we enabled the interrupt. | |
2655 | */ | |
2656 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
2657 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
2658 | if (esdp & IXGBE_ESDP_SDP1) | |
2659 | DPRINTK(DRV, CRIT, | |
2660 | "Fan has stopped, replace the adapter\n"); | |
2661 | } | |
2662 | ||
e8e26350 PW |
2663 | /* |
2664 | * For hot-pluggable SFP+ devices, a new SFP+ module may have | |
2665 | * arrived before interrupts were enabled. We need to kick off | |
2666 | * the SFP+ module setup first, then try to bring up link. | |
2667 | * If we're not hot-pluggable SFP+, we just need to configure link | |
2668 | * and bring it up. | |
2669 | */ | |
2670 | err = hw->phy.ops.identify(hw); | |
2671 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
2672 | DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err); | |
2673 | ixgbe_down(adapter); | |
2674 | return err; | |
2675 | } | |
2676 | ||
2677 | if (ixgbe_is_sfp(hw)) { | |
2678 | ixgbe_sfp_link_config(adapter); | |
2679 | } else { | |
2680 | err = ixgbe_non_sfp_link_config(hw); | |
2681 | if (err) | |
2682 | DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err); | |
2683 | } | |
0ecc061d | 2684 | |
c4cf55e5 PWJ |
2685 | for (i = 0; i < adapter->num_tx_queues; i++) |
2686 | set_bit(__IXGBE_FDIR_INIT_DONE, | |
2687 | &(adapter->tx_ring[i].reinit_state)); | |
2688 | ||
1da100bb PWJ |
2689 | /* enable transmits */ |
2690 | netif_tx_start_all_queues(netdev); | |
2691 | ||
9a799d71 AK |
2692 | /* bring the link up in the watchdog, this could race with our first |
2693 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
2694 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
2695 | adapter->link_check_timeout = jiffies; | |
9a799d71 AK |
2696 | mod_timer(&adapter->watchdog_timer, jiffies); |
2697 | return 0; | |
2698 | } | |
2699 | ||
d4f80882 AV |
2700 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
2701 | { | |
2702 | WARN_ON(in_interrupt()); | |
2703 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) | |
2704 | msleep(1); | |
2705 | ixgbe_down(adapter); | |
2706 | ixgbe_up(adapter); | |
2707 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
2708 | } | |
2709 | ||
9a799d71 AK |
2710 | int ixgbe_up(struct ixgbe_adapter *adapter) |
2711 | { | |
2712 | /* hardware has been reset, we need to reload some things */ | |
2713 | ixgbe_configure(adapter); | |
2714 | ||
2715 | return ixgbe_up_complete(adapter); | |
2716 | } | |
2717 | ||
2718 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
2719 | { | |
c44ade9e | 2720 | struct ixgbe_hw *hw = &adapter->hw; |
8ca783ab DS |
2721 | int err; |
2722 | ||
2723 | err = hw->mac.ops.init_hw(hw); | |
da4dd0f7 PWJ |
2724 | switch (err) { |
2725 | case 0: | |
2726 | case IXGBE_ERR_SFP_NOT_PRESENT: | |
2727 | break; | |
2728 | case IXGBE_ERR_MASTER_REQUESTS_PENDING: | |
2729 | dev_err(&adapter->pdev->dev, "master disable timed out\n"); | |
2730 | break; | |
794caeb2 PWJ |
2731 | case IXGBE_ERR_EEPROM_VERSION: |
2732 | /* We are running on a pre-production device, log a warning */ | |
2733 | dev_warn(&adapter->pdev->dev, "This device is a pre-production " | |
2734 | "adapter/LOM. Please be aware there may be issues " | |
2735 | "associated with your hardware. If you are " | |
2736 | "experiencing problems please contact your Intel or " | |
2737 | "hardware representative who provided you with this " | |
2738 | "hardware.\n"); | |
2739 | break; | |
da4dd0f7 PWJ |
2740 | default: |
2741 | dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err); | |
2742 | } | |
9a799d71 AK |
2743 | |
2744 | /* reprogram the RAR[0] in case user changed it. */ | |
c44ade9e | 2745 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
9a799d71 AK |
2746 | } |
2747 | ||
9a799d71 AK |
2748 | /** |
2749 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
2750 | * @adapter: board private structure | |
2751 | * @rx_ring: ring to free buffers from | |
2752 | **/ | |
2753 | static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 2754 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
2755 | { |
2756 | struct pci_dev *pdev = adapter->pdev; | |
2757 | unsigned long size; | |
2758 | unsigned int i; | |
2759 | ||
2760 | /* Free all the Rx ring sk_buffs */ | |
2761 | ||
2762 | for (i = 0; i < rx_ring->count; i++) { | |
2763 | struct ixgbe_rx_buffer *rx_buffer_info; | |
2764 | ||
2765 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
2766 | if (rx_buffer_info->dma) { | |
2767 | pci_unmap_single(pdev, rx_buffer_info->dma, | |
b4617240 PW |
2768 | rx_ring->rx_buf_len, |
2769 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
2770 | rx_buffer_info->dma = 0; |
2771 | } | |
2772 | if (rx_buffer_info->skb) { | |
f8212f97 | 2773 | struct sk_buff *skb = rx_buffer_info->skb; |
9a799d71 | 2774 | rx_buffer_info->skb = NULL; |
f8212f97 AD |
2775 | do { |
2776 | struct sk_buff *this = skb; | |
2777 | skb = skb->prev; | |
2778 | dev_kfree_skb(this); | |
2779 | } while (skb); | |
9a799d71 AK |
2780 | } |
2781 | if (!rx_buffer_info->page) | |
2782 | continue; | |
762f4c57 JB |
2783 | pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2, |
2784 | PCI_DMA_FROMDEVICE); | |
9a799d71 | 2785 | rx_buffer_info->page_dma = 0; |
9a799d71 AK |
2786 | put_page(rx_buffer_info->page); |
2787 | rx_buffer_info->page = NULL; | |
762f4c57 | 2788 | rx_buffer_info->page_offset = 0; |
9a799d71 AK |
2789 | } |
2790 | ||
2791 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
2792 | memset(rx_ring->rx_buffer_info, 0, size); | |
2793 | ||
2794 | /* Zero out the descriptor ring */ | |
2795 | memset(rx_ring->desc, 0, rx_ring->size); | |
2796 | ||
2797 | rx_ring->next_to_clean = 0; | |
2798 | rx_ring->next_to_use = 0; | |
2799 | ||
9891ca7c JB |
2800 | if (rx_ring->head) |
2801 | writel(0, adapter->hw.hw_addr + rx_ring->head); | |
2802 | if (rx_ring->tail) | |
2803 | writel(0, adapter->hw.hw_addr + rx_ring->tail); | |
9a799d71 AK |
2804 | } |
2805 | ||
2806 | /** | |
2807 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
2808 | * @adapter: board private structure | |
2809 | * @tx_ring: ring to be cleaned | |
2810 | **/ | |
2811 | static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 2812 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
2813 | { |
2814 | struct ixgbe_tx_buffer *tx_buffer_info; | |
2815 | unsigned long size; | |
2816 | unsigned int i; | |
2817 | ||
2818 | /* Free all the Tx ring sk_buffs */ | |
2819 | ||
2820 | for (i = 0; i < tx_ring->count; i++) { | |
2821 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
2822 | ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info); | |
2823 | } | |
2824 | ||
2825 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; | |
2826 | memset(tx_ring->tx_buffer_info, 0, size); | |
2827 | ||
2828 | /* Zero out the descriptor ring */ | |
2829 | memset(tx_ring->desc, 0, tx_ring->size); | |
2830 | ||
2831 | tx_ring->next_to_use = 0; | |
2832 | tx_ring->next_to_clean = 0; | |
2833 | ||
9891ca7c JB |
2834 | if (tx_ring->head) |
2835 | writel(0, adapter->hw.hw_addr + tx_ring->head); | |
2836 | if (tx_ring->tail) | |
2837 | writel(0, adapter->hw.hw_addr + tx_ring->tail); | |
9a799d71 AK |
2838 | } |
2839 | ||
2840 | /** | |
021230d4 | 2841 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
2842 | * @adapter: board private structure |
2843 | **/ | |
021230d4 | 2844 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2845 | { |
2846 | int i; | |
2847 | ||
021230d4 AV |
2848 | for (i = 0; i < adapter->num_rx_queues; i++) |
2849 | ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]); | |
9a799d71 AK |
2850 | } |
2851 | ||
2852 | /** | |
021230d4 | 2853 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
2854 | * @adapter: board private structure |
2855 | **/ | |
021230d4 | 2856 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2857 | { |
2858 | int i; | |
2859 | ||
021230d4 AV |
2860 | for (i = 0; i < adapter->num_tx_queues; i++) |
2861 | ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]); | |
9a799d71 AK |
2862 | } |
2863 | ||
2864 | void ixgbe_down(struct ixgbe_adapter *adapter) | |
2865 | { | |
2866 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 2867 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 2868 | u32 rxctrl; |
7f821875 JB |
2869 | u32 txdctl; |
2870 | int i, j; | |
9a799d71 AK |
2871 | |
2872 | /* signal that we are down to the interrupt handler */ | |
2873 | set_bit(__IXGBE_DOWN, &adapter->state); | |
2874 | ||
2875 | /* disable receives */ | |
7f821875 JB |
2876 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
2877 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 AK |
2878 | |
2879 | netif_tx_disable(netdev); | |
2880 | ||
7f821875 | 2881 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
2882 | msleep(10); |
2883 | ||
7f821875 JB |
2884 | netif_tx_stop_all_queues(netdev); |
2885 | ||
9a799d71 AK |
2886 | ixgbe_irq_disable(adapter); |
2887 | ||
021230d4 | 2888 | ixgbe_napi_disable_all(adapter); |
7f821875 | 2889 | |
9a799d71 | 2890 | del_timer_sync(&adapter->watchdog_timer); |
cf8280ee | 2891 | cancel_work_sync(&adapter->watchdog_task); |
9a799d71 | 2892 | |
c4cf55e5 PWJ |
2893 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
2894 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
2895 | cancel_work_sync(&adapter->fdir_reinit_task); | |
2896 | ||
7f821875 JB |
2897 | /* disable transmits in the hardware now that interrupts are off */ |
2898 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2899 | j = adapter->tx_ring[i].reg_idx; | |
2900 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
2901 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), | |
2902 | (txdctl & ~IXGBE_TXDCTL_ENABLE)); | |
2903 | } | |
88512539 PW |
2904 | /* Disable the Tx DMA engine on 82599 */ |
2905 | if (hw->mac.type == ixgbe_mac_82599EB) | |
2906 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, | |
2907 | (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & | |
2908 | ~IXGBE_DMATXCTL_TE)); | |
7f821875 | 2909 | |
9a799d71 | 2910 | netif_carrier_off(netdev); |
9a799d71 | 2911 | |
6f4a0e45 PL |
2912 | if (!pci_channel_offline(adapter->pdev)) |
2913 | ixgbe_reset(adapter); | |
9a799d71 AK |
2914 | ixgbe_clean_all_tx_rings(adapter); |
2915 | ixgbe_clean_all_rx_rings(adapter); | |
2916 | ||
5dd2d332 | 2917 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 | 2918 | /* since we reset the hardware DCA settings were cleared */ |
e35ec126 | 2919 | ixgbe_setup_dca(adapter); |
96b0e0f6 | 2920 | #endif |
9a799d71 AK |
2921 | } |
2922 | ||
9a799d71 | 2923 | /** |
021230d4 AV |
2924 | * ixgbe_poll - NAPI Rx polling callback |
2925 | * @napi: structure for representing this polling device | |
2926 | * @budget: how many packets driver is allowed to clean | |
2927 | * | |
2928 | * This function is used for legacy and MSI, NAPI mode | |
9a799d71 | 2929 | **/ |
021230d4 | 2930 | static int ixgbe_poll(struct napi_struct *napi, int budget) |
9a799d71 | 2931 | { |
9a1a69ad JB |
2932 | struct ixgbe_q_vector *q_vector = |
2933 | container_of(napi, struct ixgbe_q_vector, napi); | |
021230d4 | 2934 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a1a69ad | 2935 | int tx_clean_complete, work_done = 0; |
9a799d71 | 2936 | |
5dd2d332 | 2937 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
2938 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
2939 | ixgbe_update_tx_dca(adapter, adapter->tx_ring); | |
2940 | ixgbe_update_rx_dca(adapter, adapter->rx_ring); | |
2941 | } | |
2942 | #endif | |
2943 | ||
fe49f04a | 2944 | tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring); |
78b6f4ce | 2945 | ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget); |
9a799d71 | 2946 | |
9a1a69ad | 2947 | if (!tx_clean_complete) |
d2c7ddd6 DM |
2948 | work_done = budget; |
2949 | ||
53e52c72 DM |
2950 | /* If budget not fully consumed, exit the polling mode */ |
2951 | if (work_done < budget) { | |
288379f0 | 2952 | napi_complete(napi); |
509ee935 | 2953 | if (adapter->itr_setting & 1) |
f494e8fa | 2954 | ixgbe_set_itr(adapter); |
d4f80882 | 2955 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
835462fc | 2956 | ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE); |
9a799d71 | 2957 | } |
9a799d71 AK |
2958 | return work_done; |
2959 | } | |
2960 | ||
2961 | /** | |
2962 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
2963 | * @netdev: network interface device structure | |
2964 | **/ | |
2965 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
2966 | { | |
2967 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2968 | ||
2969 | /* Do the reset outside of interrupt context */ | |
2970 | schedule_work(&adapter->reset_task); | |
2971 | } | |
2972 | ||
2973 | static void ixgbe_reset_task(struct work_struct *work) | |
2974 | { | |
2975 | struct ixgbe_adapter *adapter; | |
2976 | adapter = container_of(work, struct ixgbe_adapter, reset_task); | |
2977 | ||
2f90b865 AD |
2978 | /* If we're already down or resetting, just bail */ |
2979 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
2980 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
2981 | return; | |
2982 | ||
9a799d71 AK |
2983 | adapter->tx_timeout_count++; |
2984 | ||
d4f80882 | 2985 | ixgbe_reinit_locked(adapter); |
9a799d71 AK |
2986 | } |
2987 | ||
bc97114d PWJ |
2988 | #ifdef CONFIG_IXGBE_DCB |
2989 | static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter) | |
b9804972 | 2990 | { |
bc97114d | 2991 | bool ret = false; |
0cefafad | 2992 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB]; |
b9804972 | 2993 | |
0cefafad JB |
2994 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) |
2995 | return ret; | |
2996 | ||
2997 | f->mask = 0x7 << 3; | |
2998 | adapter->num_rx_queues = f->indices; | |
2999 | adapter->num_tx_queues = f->indices; | |
3000 | ret = true; | |
2f90b865 | 3001 | |
bc97114d PWJ |
3002 | return ret; |
3003 | } | |
3004 | #endif | |
3005 | ||
4df10466 JB |
3006 | /** |
3007 | * ixgbe_set_rss_queues: Allocate queues for RSS | |
3008 | * @adapter: board private structure to initialize | |
3009 | * | |
3010 | * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try | |
3011 | * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. | |
3012 | * | |
3013 | **/ | |
bc97114d PWJ |
3014 | static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter) |
3015 | { | |
3016 | bool ret = false; | |
0cefafad | 3017 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS]; |
bc97114d PWJ |
3018 | |
3019 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
0cefafad JB |
3020 | f->mask = 0xF; |
3021 | adapter->num_rx_queues = f->indices; | |
3022 | adapter->num_tx_queues = f->indices; | |
bc97114d PWJ |
3023 | ret = true; |
3024 | } else { | |
bc97114d | 3025 | ret = false; |
b9804972 JB |
3026 | } |
3027 | ||
bc97114d PWJ |
3028 | return ret; |
3029 | } | |
3030 | ||
c4cf55e5 PWJ |
3031 | /** |
3032 | * ixgbe_set_fdir_queues: Allocate queues for Flow Director | |
3033 | * @adapter: board private structure to initialize | |
3034 | * | |
3035 | * Flow Director is an advanced Rx filter, attempting to get Rx flows back | |
3036 | * to the original CPU that initiated the Tx session. This runs in addition | |
3037 | * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the | |
3038 | * Rx load across CPUs using RSS. | |
3039 | * | |
3040 | **/ | |
3041 | static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter) | |
3042 | { | |
3043 | bool ret = false; | |
3044 | struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR]; | |
3045 | ||
3046 | f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices); | |
3047 | f_fdir->mask = 0; | |
3048 | ||
3049 | /* Flow Director must have RSS enabled */ | |
3050 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED && | |
3051 | ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || | |
3052 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) { | |
3053 | adapter->num_tx_queues = f_fdir->indices; | |
3054 | adapter->num_rx_queues = f_fdir->indices; | |
3055 | ret = true; | |
3056 | } else { | |
3057 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
3058 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
3059 | } | |
3060 | return ret; | |
3061 | } | |
3062 | ||
0331a832 YZ |
3063 | #ifdef IXGBE_FCOE |
3064 | /** | |
3065 | * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE) | |
3066 | * @adapter: board private structure to initialize | |
3067 | * | |
3068 | * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges. | |
3069 | * The ring feature mask is not used as a mask for FCoE, as it can take any 8 | |
3070 | * rx queues out of the max number of rx queues, instead, it is used as the | |
3071 | * index of the first rx queue used by FCoE. | |
3072 | * | |
3073 | **/ | |
3074 | static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter) | |
3075 | { | |
3076 | bool ret = false; | |
3077 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; | |
3078 | ||
3079 | f->indices = min((int)num_online_cpus(), f->indices); | |
3080 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
3081 | #ifdef CONFIG_IXGBE_DCB | |
3082 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
3083 | DPRINTK(PROBE, INFO, "FCOE enabled with DCB \n"); | |
3084 | ixgbe_set_dcb_queues(adapter); | |
3085 | } | |
3086 | #endif | |
3087 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
3088 | DPRINTK(PROBE, INFO, "FCOE enabled with RSS \n"); | |
3089 | ixgbe_set_rss_queues(adapter); | |
3090 | } | |
3091 | /* adding FCoE rx rings to the end */ | |
3092 | f->mask = adapter->num_rx_queues; | |
3093 | adapter->num_rx_queues += f->indices; | |
3094 | if (adapter->num_tx_queues == 0) | |
3095 | adapter->num_tx_queues = f->indices; | |
3096 | ||
3097 | ret = true; | |
3098 | } | |
3099 | ||
3100 | return ret; | |
3101 | } | |
3102 | ||
3103 | #endif /* IXGBE_FCOE */ | |
4df10466 JB |
3104 | /* |
3105 | * ixgbe_set_num_queues: Allocate queues for device, feature dependant | |
3106 | * @adapter: board private structure to initialize | |
3107 | * | |
3108 | * This is the top level queue allocation routine. The order here is very | |
3109 | * important, starting with the "most" number of features turned on at once, | |
3110 | * and ending with the smallest set of features. This way large combinations | |
3111 | * can be allocated if they're turned on, and smaller combinations are the | |
3112 | * fallthrough conditions. | |
3113 | * | |
3114 | **/ | |
bc97114d PWJ |
3115 | static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter) |
3116 | { | |
0331a832 YZ |
3117 | #ifdef IXGBE_FCOE |
3118 | if (ixgbe_set_fcoe_queues(adapter)) | |
3119 | goto done; | |
3120 | ||
3121 | #endif /* IXGBE_FCOE */ | |
bc97114d PWJ |
3122 | #ifdef CONFIG_IXGBE_DCB |
3123 | if (ixgbe_set_dcb_queues(adapter)) | |
af22ab1b | 3124 | goto done; |
bc97114d PWJ |
3125 | |
3126 | #endif | |
c4cf55e5 PWJ |
3127 | if (ixgbe_set_fdir_queues(adapter)) |
3128 | goto done; | |
3129 | ||
bc97114d | 3130 | if (ixgbe_set_rss_queues(adapter)) |
af22ab1b WF |
3131 | goto done; |
3132 | ||
3133 | /* fallback to base case */ | |
3134 | adapter->num_rx_queues = 1; | |
3135 | adapter->num_tx_queues = 1; | |
3136 | ||
3137 | done: | |
3138 | /* Notify the stack of the (possibly) reduced Tx Queue count. */ | |
3139 | adapter->netdev->real_num_tx_queues = adapter->num_tx_queues; | |
b9804972 JB |
3140 | } |
3141 | ||
021230d4 | 3142 | static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 3143 | int vectors) |
021230d4 AV |
3144 | { |
3145 | int err, vector_threshold; | |
3146 | ||
3147 | /* We'll want at least 3 (vector_threshold): | |
3148 | * 1) TxQ[0] Cleanup | |
3149 | * 2) RxQ[0] Cleanup | |
3150 | * 3) Other (Link Status Change, etc.) | |
3151 | * 4) TCP Timer (optional) | |
3152 | */ | |
3153 | vector_threshold = MIN_MSIX_COUNT; | |
3154 | ||
3155 | /* The more we get, the more we will assign to Tx/Rx Cleanup | |
3156 | * for the separate queues...where Rx Cleanup >= Tx Cleanup. | |
3157 | * Right now, we simply care about how many we'll get; we'll | |
3158 | * set them up later while requesting irq's. | |
3159 | */ | |
3160 | while (vectors >= vector_threshold) { | |
3161 | err = pci_enable_msix(adapter->pdev, adapter->msix_entries, | |
b4617240 | 3162 | vectors); |
021230d4 AV |
3163 | if (!err) /* Success in acquiring all requested vectors. */ |
3164 | break; | |
3165 | else if (err < 0) | |
3166 | vectors = 0; /* Nasty failure, quit now */ | |
3167 | else /* err == number of vectors we should try again with */ | |
3168 | vectors = err; | |
3169 | } | |
3170 | ||
3171 | if (vectors < vector_threshold) { | |
3172 | /* Can't allocate enough MSI-X interrupts? Oh well. | |
3173 | * This just means we'll go with either a single MSI | |
3174 | * vector or fall back to legacy interrupts. | |
3175 | */ | |
3176 | DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n"); | |
3177 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
3178 | kfree(adapter->msix_entries); | |
3179 | adapter->msix_entries = NULL; | |
021230d4 AV |
3180 | } else { |
3181 | adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */ | |
eb7f139c PWJ |
3182 | /* |
3183 | * Adjust for only the vectors we'll use, which is minimum | |
3184 | * of max_msix_q_vectors + NON_Q_VECTORS, or the number of | |
3185 | * vectors we were allocated. | |
3186 | */ | |
3187 | adapter->num_msix_vectors = min(vectors, | |
3188 | adapter->max_msix_q_vectors + NON_Q_VECTORS); | |
021230d4 AV |
3189 | } |
3190 | } | |
3191 | ||
021230d4 | 3192 | /** |
bc97114d | 3193 | * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS |
021230d4 AV |
3194 | * @adapter: board private structure to initialize |
3195 | * | |
bc97114d PWJ |
3196 | * Cache the descriptor ring offsets for RSS to the assigned rings. |
3197 | * | |
021230d4 | 3198 | **/ |
bc97114d | 3199 | static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter) |
021230d4 | 3200 | { |
bc97114d PWJ |
3201 | int i; |
3202 | bool ret = false; | |
3203 | ||
3204 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
3205 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3206 | adapter->rx_ring[i].reg_idx = i; | |
3207 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3208 | adapter->tx_ring[i].reg_idx = i; | |
3209 | ret = true; | |
3210 | } else { | |
3211 | ret = false; | |
3212 | } | |
3213 | ||
3214 | return ret; | |
3215 | } | |
3216 | ||
3217 | #ifdef CONFIG_IXGBE_DCB | |
3218 | /** | |
3219 | * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB | |
3220 | * @adapter: board private structure to initialize | |
3221 | * | |
3222 | * Cache the descriptor ring offsets for DCB to the assigned rings. | |
3223 | * | |
3224 | **/ | |
3225 | static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) | |
3226 | { | |
3227 | int i; | |
3228 | bool ret = false; | |
3229 | int dcb_i = adapter->ring_feature[RING_F_DCB].indices; | |
3230 | ||
3231 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
3232 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
2f90b865 AD |
3233 | /* the number of queues is assumed to be symmetric */ |
3234 | for (i = 0; i < dcb_i; i++) { | |
3235 | adapter->rx_ring[i].reg_idx = i << 3; | |
3236 | adapter->tx_ring[i].reg_idx = i << 2; | |
3237 | } | |
bc97114d | 3238 | ret = true; |
e8e26350 | 3239 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
f92ef202 PW |
3240 | if (dcb_i == 8) { |
3241 | /* | |
3242 | * Tx TC0 starts at: descriptor queue 0 | |
3243 | * Tx TC1 starts at: descriptor queue 32 | |
3244 | * Tx TC2 starts at: descriptor queue 64 | |
3245 | * Tx TC3 starts at: descriptor queue 80 | |
3246 | * Tx TC4 starts at: descriptor queue 96 | |
3247 | * Tx TC5 starts at: descriptor queue 104 | |
3248 | * Tx TC6 starts at: descriptor queue 112 | |
3249 | * Tx TC7 starts at: descriptor queue 120 | |
3250 | * | |
3251 | * Rx TC0-TC7 are offset by 16 queues each | |
3252 | */ | |
3253 | for (i = 0; i < 3; i++) { | |
3254 | adapter->tx_ring[i].reg_idx = i << 5; | |
3255 | adapter->rx_ring[i].reg_idx = i << 4; | |
3256 | } | |
3257 | for ( ; i < 5; i++) { | |
3258 | adapter->tx_ring[i].reg_idx = | |
3259 | ((i + 2) << 4); | |
3260 | adapter->rx_ring[i].reg_idx = i << 4; | |
3261 | } | |
3262 | for ( ; i < dcb_i; i++) { | |
3263 | adapter->tx_ring[i].reg_idx = | |
3264 | ((i + 8) << 3); | |
3265 | adapter->rx_ring[i].reg_idx = i << 4; | |
3266 | } | |
3267 | ||
3268 | ret = true; | |
3269 | } else if (dcb_i == 4) { | |
3270 | /* | |
3271 | * Tx TC0 starts at: descriptor queue 0 | |
3272 | * Tx TC1 starts at: descriptor queue 64 | |
3273 | * Tx TC2 starts at: descriptor queue 96 | |
3274 | * Tx TC3 starts at: descriptor queue 112 | |
3275 | * | |
3276 | * Rx TC0-TC3 are offset by 32 queues each | |
3277 | */ | |
3278 | adapter->tx_ring[0].reg_idx = 0; | |
3279 | adapter->tx_ring[1].reg_idx = 64; | |
3280 | adapter->tx_ring[2].reg_idx = 96; | |
3281 | adapter->tx_ring[3].reg_idx = 112; | |
3282 | for (i = 0 ; i < dcb_i; i++) | |
3283 | adapter->rx_ring[i].reg_idx = i << 5; | |
3284 | ||
3285 | ret = true; | |
3286 | } else { | |
3287 | ret = false; | |
e8e26350 | 3288 | } |
bc97114d PWJ |
3289 | } else { |
3290 | ret = false; | |
021230d4 | 3291 | } |
bc97114d PWJ |
3292 | } else { |
3293 | ret = false; | |
021230d4 | 3294 | } |
bc97114d PWJ |
3295 | |
3296 | return ret; | |
3297 | } | |
3298 | #endif | |
3299 | ||
c4cf55e5 PWJ |
3300 | /** |
3301 | * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director | |
3302 | * @adapter: board private structure to initialize | |
3303 | * | |
3304 | * Cache the descriptor ring offsets for Flow Director to the assigned rings. | |
3305 | * | |
3306 | **/ | |
3307 | static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter) | |
3308 | { | |
3309 | int i; | |
3310 | bool ret = false; | |
3311 | ||
3312 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED && | |
3313 | ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || | |
3314 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) { | |
3315 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3316 | adapter->rx_ring[i].reg_idx = i; | |
3317 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3318 | adapter->tx_ring[i].reg_idx = i; | |
3319 | ret = true; | |
3320 | } | |
3321 | ||
3322 | return ret; | |
3323 | } | |
3324 | ||
0331a832 YZ |
3325 | #ifdef IXGBE_FCOE |
3326 | /** | |
3327 | * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE | |
3328 | * @adapter: board private structure to initialize | |
3329 | * | |
3330 | * Cache the descriptor ring offsets for FCoE mode to the assigned rings. | |
3331 | * | |
3332 | */ | |
3333 | static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter) | |
3334 | { | |
3335 | int i, fcoe_i = 0; | |
3336 | bool ret = false; | |
3337 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; | |
3338 | ||
3339 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
3340 | #ifdef CONFIG_IXGBE_DCB | |
3341 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
3342 | ixgbe_cache_ring_dcb(adapter); | |
3343 | fcoe_i = adapter->rx_ring[0].reg_idx + 1; | |
3344 | } | |
3345 | #endif /* CONFIG_IXGBE_DCB */ | |
3346 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
3347 | ixgbe_cache_ring_rss(adapter); | |
3348 | fcoe_i = f->mask; | |
3349 | } | |
3350 | for (i = 0; i < f->indices; i++, fcoe_i++) | |
3351 | adapter->rx_ring[f->mask + i].reg_idx = fcoe_i; | |
3352 | ret = true; | |
3353 | } | |
3354 | return ret; | |
3355 | } | |
3356 | ||
3357 | #endif /* IXGBE_FCOE */ | |
bc97114d PWJ |
3358 | /** |
3359 | * ixgbe_cache_ring_register - Descriptor ring to register mapping | |
3360 | * @adapter: board private structure to initialize | |
3361 | * | |
3362 | * Once we know the feature-set enabled for the device, we'll cache | |
3363 | * the register offset the descriptor ring is assigned to. | |
3364 | * | |
3365 | * Note, the order the various feature calls is important. It must start with | |
3366 | * the "most" features enabled at the same time, then trickle down to the | |
3367 | * least amount of features turned on at once. | |
3368 | **/ | |
3369 | static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) | |
3370 | { | |
3371 | /* start with default case */ | |
3372 | adapter->rx_ring[0].reg_idx = 0; | |
3373 | adapter->tx_ring[0].reg_idx = 0; | |
3374 | ||
0331a832 YZ |
3375 | #ifdef IXGBE_FCOE |
3376 | if (ixgbe_cache_ring_fcoe(adapter)) | |
3377 | return; | |
3378 | ||
3379 | #endif /* IXGBE_FCOE */ | |
bc97114d PWJ |
3380 | #ifdef CONFIG_IXGBE_DCB |
3381 | if (ixgbe_cache_ring_dcb(adapter)) | |
3382 | return; | |
3383 | ||
3384 | #endif | |
c4cf55e5 PWJ |
3385 | if (ixgbe_cache_ring_fdir(adapter)) |
3386 | return; | |
3387 | ||
bc97114d PWJ |
3388 | if (ixgbe_cache_ring_rss(adapter)) |
3389 | return; | |
021230d4 AV |
3390 | } |
3391 | ||
9a799d71 AK |
3392 | /** |
3393 | * ixgbe_alloc_queues - Allocate memory for all rings | |
3394 | * @adapter: board private structure to initialize | |
3395 | * | |
3396 | * We allocate one ring per queue at run-time since we don't know the | |
4df10466 JB |
3397 | * number of queues at compile-time. The polling_netdev array is |
3398 | * intended for Multiqueue, but should work fine with a single queue. | |
9a799d71 | 3399 | **/ |
2f90b865 | 3400 | static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter) |
9a799d71 AK |
3401 | { |
3402 | int i; | |
3403 | ||
3404 | adapter->tx_ring = kcalloc(adapter->num_tx_queues, | |
b4617240 | 3405 | sizeof(struct ixgbe_ring), GFP_KERNEL); |
9a799d71 | 3406 | if (!adapter->tx_ring) |
021230d4 | 3407 | goto err_tx_ring_allocation; |
9a799d71 AK |
3408 | |
3409 | adapter->rx_ring = kcalloc(adapter->num_rx_queues, | |
b4617240 | 3410 | sizeof(struct ixgbe_ring), GFP_KERNEL); |
021230d4 AV |
3411 | if (!adapter->rx_ring) |
3412 | goto err_rx_ring_allocation; | |
9a799d71 | 3413 | |
021230d4 | 3414 | for (i = 0; i < adapter->num_tx_queues; i++) { |
b9804972 | 3415 | adapter->tx_ring[i].count = adapter->tx_ring_count; |
021230d4 AV |
3416 | adapter->tx_ring[i].queue_index = i; |
3417 | } | |
b9804972 | 3418 | |
9a799d71 | 3419 | for (i = 0; i < adapter->num_rx_queues; i++) { |
b9804972 | 3420 | adapter->rx_ring[i].count = adapter->rx_ring_count; |
021230d4 AV |
3421 | adapter->rx_ring[i].queue_index = i; |
3422 | } | |
3423 | ||
3424 | ixgbe_cache_ring_register(adapter); | |
3425 | ||
3426 | return 0; | |
3427 | ||
3428 | err_rx_ring_allocation: | |
3429 | kfree(adapter->tx_ring); | |
3430 | err_tx_ring_allocation: | |
3431 | return -ENOMEM; | |
3432 | } | |
3433 | ||
3434 | /** | |
3435 | * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported | |
3436 | * @adapter: board private structure to initialize | |
3437 | * | |
3438 | * Attempt to configure the interrupts using the best available | |
3439 | * capabilities of the hardware and the kernel. | |
3440 | **/ | |
feea6a57 | 3441 | static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 | 3442 | { |
8be0e467 | 3443 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 AV |
3444 | int err = 0; |
3445 | int vector, v_budget; | |
3446 | ||
3447 | /* | |
3448 | * It's easy to be greedy for MSI-X vectors, but it really | |
3449 | * doesn't do us much good if we have a lot more vectors | |
3450 | * than CPU's. So let's be conservative and only ask for | |
3451 | * (roughly) twice the number of vectors as there are CPU's. | |
3452 | */ | |
3453 | v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues, | |
b4617240 | 3454 | (int)(num_online_cpus() * 2)) + NON_Q_VECTORS; |
021230d4 AV |
3455 | |
3456 | /* | |
3457 | * At the same time, hardware can only support a maximum of | |
8be0e467 PW |
3458 | * hw.mac->max_msix_vectors vectors. With features |
3459 | * such as RSS and VMDq, we can easily surpass the number of Rx and Tx | |
3460 | * descriptor queues supported by our device. Thus, we cap it off in | |
3461 | * those rare cases where the cpu count also exceeds our vector limit. | |
021230d4 | 3462 | */ |
8be0e467 | 3463 | v_budget = min(v_budget, (int)hw->mac.max_msix_vectors); |
021230d4 AV |
3464 | |
3465 | /* A failure in MSI-X entry allocation isn't fatal, but it does | |
3466 | * mean we disable MSI-X capabilities of the adapter. */ | |
3467 | adapter->msix_entries = kcalloc(v_budget, | |
b4617240 | 3468 | sizeof(struct msix_entry), GFP_KERNEL); |
7a921c93 AD |
3469 | if (adapter->msix_entries) { |
3470 | for (vector = 0; vector < v_budget; vector++) | |
3471 | adapter->msix_entries[vector].entry = vector; | |
021230d4 | 3472 | |
7a921c93 | 3473 | ixgbe_acquire_msix_vectors(adapter, v_budget); |
021230d4 | 3474 | |
7a921c93 AD |
3475 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
3476 | goto out; | |
3477 | } | |
021230d4 | 3478 | |
7a921c93 AD |
3479 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; |
3480 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
c4cf55e5 PWJ |
3481 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; |
3482 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
3483 | adapter->atr_sample_rate = 0; | |
7a921c93 | 3484 | ixgbe_set_num_queues(adapter); |
021230d4 | 3485 | |
021230d4 AV |
3486 | err = pci_enable_msi(adapter->pdev); |
3487 | if (!err) { | |
3488 | adapter->flags |= IXGBE_FLAG_MSI_ENABLED; | |
3489 | } else { | |
3490 | DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, " | |
b4617240 | 3491 | "falling back to legacy. Error: %d\n", err); |
021230d4 AV |
3492 | /* reset err */ |
3493 | err = 0; | |
3494 | } | |
3495 | ||
3496 | out: | |
021230d4 AV |
3497 | return err; |
3498 | } | |
3499 | ||
7a921c93 AD |
3500 | /** |
3501 | * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors | |
3502 | * @adapter: board private structure to initialize | |
3503 | * | |
3504 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
3505 | * return -ENOMEM. | |
3506 | **/ | |
3507 | static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter) | |
3508 | { | |
3509 | int q_idx, num_q_vectors; | |
3510 | struct ixgbe_q_vector *q_vector; | |
3511 | int napi_vectors; | |
3512 | int (*poll)(struct napi_struct *, int); | |
3513 | ||
3514 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
3515 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3516 | napi_vectors = adapter->num_rx_queues; | |
91281fd3 | 3517 | poll = &ixgbe_clean_rxtx_many; |
7a921c93 AD |
3518 | } else { |
3519 | num_q_vectors = 1; | |
3520 | napi_vectors = 1; | |
3521 | poll = &ixgbe_poll; | |
3522 | } | |
3523 | ||
3524 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
3525 | q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL); | |
3526 | if (!q_vector) | |
3527 | goto err_out; | |
3528 | q_vector->adapter = adapter; | |
7a921c93 | 3529 | q_vector->eitr = adapter->eitr_param; |
fe49f04a | 3530 | q_vector->v_idx = q_idx; |
91281fd3 | 3531 | netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64); |
7a921c93 AD |
3532 | adapter->q_vector[q_idx] = q_vector; |
3533 | } | |
3534 | ||
3535 | return 0; | |
3536 | ||
3537 | err_out: | |
3538 | while (q_idx) { | |
3539 | q_idx--; | |
3540 | q_vector = adapter->q_vector[q_idx]; | |
3541 | netif_napi_del(&q_vector->napi); | |
3542 | kfree(q_vector); | |
3543 | adapter->q_vector[q_idx] = NULL; | |
3544 | } | |
3545 | return -ENOMEM; | |
3546 | } | |
3547 | ||
3548 | /** | |
3549 | * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors | |
3550 | * @adapter: board private structure to initialize | |
3551 | * | |
3552 | * This function frees the memory allocated to the q_vectors. In addition if | |
3553 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
3554 | * to freeing the q_vector. | |
3555 | **/ | |
3556 | static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter) | |
3557 | { | |
3558 | int q_idx, num_q_vectors; | |
7a921c93 | 3559 | |
91281fd3 | 3560 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
7a921c93 | 3561 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
91281fd3 | 3562 | else |
7a921c93 | 3563 | num_q_vectors = 1; |
7a921c93 AD |
3564 | |
3565 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
3566 | struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx]; | |
7a921c93 | 3567 | adapter->q_vector[q_idx] = NULL; |
91281fd3 | 3568 | netif_napi_del(&q_vector->napi); |
7a921c93 AD |
3569 | kfree(q_vector); |
3570 | } | |
3571 | } | |
3572 | ||
2f90b865 | 3573 | void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 AV |
3574 | { |
3575 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
3576 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
3577 | pci_disable_msix(adapter->pdev); | |
3578 | kfree(adapter->msix_entries); | |
3579 | adapter->msix_entries = NULL; | |
3580 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
3581 | adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; | |
3582 | pci_disable_msi(adapter->pdev); | |
3583 | } | |
3584 | return; | |
3585 | } | |
3586 | ||
3587 | /** | |
3588 | * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme | |
3589 | * @adapter: board private structure to initialize | |
3590 | * | |
3591 | * We determine which interrupt scheme to use based on... | |
3592 | * - Kernel support (MSI, MSI-X) | |
3593 | * - which can be user-defined (via MODULE_PARAM) | |
3594 | * - Hardware queue count (num_*_queues) | |
3595 | * - defined by miscellaneous hardware support/features (RSS, etc.) | |
3596 | **/ | |
2f90b865 | 3597 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) |
021230d4 AV |
3598 | { |
3599 | int err; | |
3600 | ||
3601 | /* Number of supported queues */ | |
3602 | ixgbe_set_num_queues(adapter); | |
3603 | ||
021230d4 AV |
3604 | err = ixgbe_set_interrupt_capability(adapter); |
3605 | if (err) { | |
3606 | DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n"); | |
3607 | goto err_set_interrupt; | |
9a799d71 AK |
3608 | } |
3609 | ||
7a921c93 AD |
3610 | err = ixgbe_alloc_q_vectors(adapter); |
3611 | if (err) { | |
3612 | DPRINTK(PROBE, ERR, "Unable to allocate memory for queue " | |
3613 | "vectors\n"); | |
3614 | goto err_alloc_q_vectors; | |
3615 | } | |
3616 | ||
3617 | err = ixgbe_alloc_queues(adapter); | |
3618 | if (err) { | |
3619 | DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n"); | |
3620 | goto err_alloc_queues; | |
3621 | } | |
3622 | ||
021230d4 | 3623 | DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, " |
b4617240 PW |
3624 | "Tx Queue count = %u\n", |
3625 | (adapter->num_rx_queues > 1) ? "Enabled" : | |
3626 | "Disabled", adapter->num_rx_queues, adapter->num_tx_queues); | |
021230d4 AV |
3627 | |
3628 | set_bit(__IXGBE_DOWN, &adapter->state); | |
3629 | ||
9a799d71 | 3630 | return 0; |
021230d4 | 3631 | |
7a921c93 AD |
3632 | err_alloc_queues: |
3633 | ixgbe_free_q_vectors(adapter); | |
3634 | err_alloc_q_vectors: | |
3635 | ixgbe_reset_interrupt_capability(adapter); | |
021230d4 | 3636 | err_set_interrupt: |
7a921c93 AD |
3637 | return err; |
3638 | } | |
3639 | ||
3640 | /** | |
3641 | * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings | |
3642 | * @adapter: board private structure to clear interrupt scheme on | |
3643 | * | |
3644 | * We go through and clear interrupt specific resources and reset the structure | |
3645 | * to pre-load conditions | |
3646 | **/ | |
3647 | void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter) | |
3648 | { | |
021230d4 AV |
3649 | kfree(adapter->tx_ring); |
3650 | kfree(adapter->rx_ring); | |
7a921c93 AD |
3651 | adapter->tx_ring = NULL; |
3652 | adapter->rx_ring = NULL; | |
3653 | ||
3654 | ixgbe_free_q_vectors(adapter); | |
3655 | ixgbe_reset_interrupt_capability(adapter); | |
9a799d71 AK |
3656 | } |
3657 | ||
c4900be0 DS |
3658 | /** |
3659 | * ixgbe_sfp_timer - worker thread to find a missing module | |
3660 | * @data: pointer to our adapter struct | |
3661 | **/ | |
3662 | static void ixgbe_sfp_timer(unsigned long data) | |
3663 | { | |
3664 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
3665 | ||
4df10466 JB |
3666 | /* |
3667 | * Do the sfp_timer outside of interrupt context due to the | |
c4900be0 DS |
3668 | * delays that sfp+ detection requires |
3669 | */ | |
3670 | schedule_work(&adapter->sfp_task); | |
3671 | } | |
3672 | ||
3673 | /** | |
3674 | * ixgbe_sfp_task - worker thread to find a missing module | |
3675 | * @work: pointer to work_struct containing our data | |
3676 | **/ | |
3677 | static void ixgbe_sfp_task(struct work_struct *work) | |
3678 | { | |
3679 | struct ixgbe_adapter *adapter = container_of(work, | |
3680 | struct ixgbe_adapter, | |
3681 | sfp_task); | |
3682 | struct ixgbe_hw *hw = &adapter->hw; | |
3683 | ||
3684 | if ((hw->phy.type == ixgbe_phy_nl) && | |
3685 | (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) { | |
3686 | s32 ret = hw->phy.ops.identify_sfp(hw); | |
3687 | if (ret) | |
3688 | goto reschedule; | |
3689 | ret = hw->phy.ops.reset(hw); | |
3690 | if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
3691 | DPRINTK(PROBE, ERR, "failed to initialize because an " | |
3692 | "unsupported SFP+ module type was detected.\n" | |
3693 | "Reload the driver after installing a " | |
3694 | "supported module.\n"); | |
3695 | unregister_netdev(adapter->netdev); | |
3696 | } else { | |
3697 | DPRINTK(PROBE, INFO, "detected SFP+: %d\n", | |
3698 | hw->phy.sfp_type); | |
3699 | } | |
3700 | /* don't need this routine any more */ | |
3701 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
3702 | } | |
3703 | return; | |
3704 | reschedule: | |
3705 | if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state)) | |
3706 | mod_timer(&adapter->sfp_timer, | |
3707 | round_jiffies(jiffies + (2 * HZ))); | |
3708 | } | |
3709 | ||
9a799d71 AK |
3710 | /** |
3711 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
3712 | * @adapter: board private structure to initialize | |
3713 | * | |
3714 | * ixgbe_sw_init initializes the Adapter private data structure. | |
3715 | * Fields are initialized based on PCI device information and | |
3716 | * OS network device settings (MTU size). | |
3717 | **/ | |
3718 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
3719 | { | |
3720 | struct ixgbe_hw *hw = &adapter->hw; | |
3721 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 3722 | unsigned int rss; |
7a6b6f51 | 3723 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
3724 | int j; |
3725 | struct tc_configuration *tc; | |
3726 | #endif | |
021230d4 | 3727 | |
c44ade9e JB |
3728 | /* PCI config space info */ |
3729 | ||
3730 | hw->vendor_id = pdev->vendor; | |
3731 | hw->device_id = pdev->device; | |
3732 | hw->revision_id = pdev->revision; | |
3733 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
3734 | hw->subsystem_device_id = pdev->subsystem_device; | |
3735 | ||
021230d4 AV |
3736 | /* Set capability flags */ |
3737 | rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus()); | |
3738 | adapter->ring_feature[RING_F_RSS].indices = rss; | |
3739 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; | |
2f90b865 | 3740 | adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES; |
bf069c97 DS |
3741 | if (hw->mac.type == ixgbe_mac_82598EB) { |
3742 | if (hw->device_id == IXGBE_DEV_ID_82598AT) | |
3743 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
e8e26350 | 3744 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598; |
bf069c97 | 3745 | } else if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 | 3746 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599; |
df647b5c PWJ |
3747 | adapter->flags |= IXGBE_FLAG2_RSC_CAPABLE; |
3748 | adapter->flags |= IXGBE_FLAG2_RSC_ENABLED; | |
c4cf55e5 PWJ |
3749 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; |
3750 | adapter->ring_feature[RING_F_FDIR].indices = | |
3751 | IXGBE_MAX_FDIR_INDICES; | |
3752 | adapter->atr_sample_rate = 20; | |
3753 | adapter->fdir_pballoc = 0; | |
eacd73f7 YZ |
3754 | #ifdef IXGBE_FCOE |
3755 | adapter->flags |= IXGBE_FLAG_FCOE_ENABLED; | |
0331a832 | 3756 | adapter->ring_feature[RING_F_FCOE].indices = IXGBE_FCRETA_SIZE; |
eacd73f7 | 3757 | #endif /* IXGBE_FCOE */ |
f8212f97 | 3758 | } |
2f90b865 | 3759 | |
7a6b6f51 | 3760 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
3761 | /* Configure DCB traffic classes */ |
3762 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
3763 | tc = &adapter->dcb_cfg.tc_config[j]; | |
3764 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
3765 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
3766 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
3767 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
3768 | tc->dcb_pfc = pfc_disabled; | |
3769 | } | |
3770 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; | |
3771 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
3772 | adapter->dcb_cfg.rx_pba_cfg = pba_equal; | |
264857b8 | 3773 | adapter->dcb_cfg.pfc_mode_enable = false; |
2f90b865 AD |
3774 | adapter->dcb_cfg.round_robin_enable = false; |
3775 | adapter->dcb_set_bitmap = 0x00; | |
3776 | ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, | |
3777 | adapter->ring_feature[RING_F_DCB].indices); | |
3778 | ||
3779 | #endif | |
9a799d71 AK |
3780 | |
3781 | /* default flow control settings */ | |
cd7664f6 | 3782 | hw->fc.requested_mode = ixgbe_fc_full; |
71fd570b | 3783 | hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ |
264857b8 PWJ |
3784 | #ifdef CONFIG_DCB |
3785 | adapter->last_lfc_mode = hw->fc.current_mode; | |
3786 | #endif | |
2b9ade93 JB |
3787 | hw->fc.high_water = IXGBE_DEFAULT_FCRTH; |
3788 | hw->fc.low_water = IXGBE_DEFAULT_FCRTL; | |
3789 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; | |
3790 | hw->fc.send_xon = true; | |
71fd570b | 3791 | hw->fc.disable_fc_autoneg = false; |
9a799d71 | 3792 | |
30efa5a3 JB |
3793 | /* enable itr by default in dynamic mode */ |
3794 | adapter->itr_setting = 1; | |
3795 | adapter->eitr_param = 20000; | |
3796 | ||
3797 | /* set defaults for eitr in MegaBytes */ | |
3798 | adapter->eitr_low = 10; | |
3799 | adapter->eitr_high = 20; | |
3800 | ||
3801 | /* set default ring sizes */ | |
3802 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
3803 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
3804 | ||
9a799d71 | 3805 | /* initialize eeprom parameters */ |
c44ade9e | 3806 | if (ixgbe_init_eeprom_params_generic(hw)) { |
9a799d71 AK |
3807 | dev_err(&pdev->dev, "EEPROM initialization failed\n"); |
3808 | return -EIO; | |
3809 | } | |
3810 | ||
021230d4 | 3811 | /* enable rx csum by default */ |
9a799d71 AK |
3812 | adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED; |
3813 | ||
9a799d71 AK |
3814 | set_bit(__IXGBE_DOWN, &adapter->state); |
3815 | ||
3816 | return 0; | |
3817 | } | |
3818 | ||
3819 | /** | |
3820 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
3821 | * @adapter: board private structure | |
3a581073 | 3822 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
3823 | * |
3824 | * Return 0 on success, negative on failure | |
3825 | **/ | |
3826 | int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter, | |
e01c31a5 | 3827 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
3828 | { |
3829 | struct pci_dev *pdev = adapter->pdev; | |
3830 | int size; | |
3831 | ||
3a581073 JB |
3832 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
3833 | tx_ring->tx_buffer_info = vmalloc(size); | |
e01c31a5 JB |
3834 | if (!tx_ring->tx_buffer_info) |
3835 | goto err; | |
3a581073 | 3836 | memset(tx_ring->tx_buffer_info, 0, size); |
9a799d71 AK |
3837 | |
3838 | /* round up to nearest 4K */ | |
12207e49 | 3839 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 3840 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 3841 | |
3a581073 JB |
3842 | tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, |
3843 | &tx_ring->dma); | |
e01c31a5 JB |
3844 | if (!tx_ring->desc) |
3845 | goto err; | |
9a799d71 | 3846 | |
3a581073 JB |
3847 | tx_ring->next_to_use = 0; |
3848 | tx_ring->next_to_clean = 0; | |
3849 | tx_ring->work_limit = tx_ring->count; | |
9a799d71 | 3850 | return 0; |
e01c31a5 JB |
3851 | |
3852 | err: | |
3853 | vfree(tx_ring->tx_buffer_info); | |
3854 | tx_ring->tx_buffer_info = NULL; | |
3855 | DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit " | |
3856 | "descriptor ring\n"); | |
3857 | return -ENOMEM; | |
9a799d71 AK |
3858 | } |
3859 | ||
69888674 AD |
3860 | /** |
3861 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
3862 | * @adapter: board private structure | |
3863 | * | |
3864 | * If this function returns with an error, then it's possible one or | |
3865 | * more of the rings is populated (while the rest are not). It is the | |
3866 | * callers duty to clean those orphaned rings. | |
3867 | * | |
3868 | * Return 0 on success, negative on failure | |
3869 | **/ | |
3870 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
3871 | { | |
3872 | int i, err = 0; | |
3873 | ||
3874 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
3875 | err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]); | |
3876 | if (!err) | |
3877 | continue; | |
3878 | DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i); | |
3879 | break; | |
3880 | } | |
3881 | ||
3882 | return err; | |
3883 | } | |
3884 | ||
9a799d71 AK |
3885 | /** |
3886 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
3887 | * @adapter: board private structure | |
3a581073 | 3888 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
3889 | * |
3890 | * Returns 0 on success, negative on failure | |
3891 | **/ | |
3892 | int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, | |
b4617240 | 3893 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
3894 | { |
3895 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 3896 | int size; |
9a799d71 | 3897 | |
3a581073 JB |
3898 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
3899 | rx_ring->rx_buffer_info = vmalloc(size); | |
3900 | if (!rx_ring->rx_buffer_info) { | |
9a799d71 | 3901 | DPRINTK(PROBE, ERR, |
b4617240 | 3902 | "vmalloc allocation failed for the rx desc ring\n"); |
177db6ff | 3903 | goto alloc_failed; |
9a799d71 | 3904 | } |
3a581073 | 3905 | memset(rx_ring->rx_buffer_info, 0, size); |
9a799d71 | 3906 | |
9a799d71 | 3907 | /* Round up to nearest 4K */ |
3a581073 JB |
3908 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
3909 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 3910 | |
3a581073 | 3911 | rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma); |
9a799d71 | 3912 | |
3a581073 | 3913 | if (!rx_ring->desc) { |
9a799d71 | 3914 | DPRINTK(PROBE, ERR, |
b4617240 | 3915 | "Memory allocation failed for the rx desc ring\n"); |
3a581073 | 3916 | vfree(rx_ring->rx_buffer_info); |
177db6ff | 3917 | goto alloc_failed; |
9a799d71 AK |
3918 | } |
3919 | ||
3a581073 JB |
3920 | rx_ring->next_to_clean = 0; |
3921 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
3922 | |
3923 | return 0; | |
177db6ff MC |
3924 | |
3925 | alloc_failed: | |
177db6ff | 3926 | return -ENOMEM; |
9a799d71 AK |
3927 | } |
3928 | ||
69888674 AD |
3929 | /** |
3930 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
3931 | * @adapter: board private structure | |
3932 | * | |
3933 | * If this function returns with an error, then it's possible one or | |
3934 | * more of the rings is populated (while the rest are not). It is the | |
3935 | * callers duty to clean those orphaned rings. | |
3936 | * | |
3937 | * Return 0 on success, negative on failure | |
3938 | **/ | |
3939 | ||
3940 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) | |
3941 | { | |
3942 | int i, err = 0; | |
3943 | ||
3944 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
3945 | err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]); | |
3946 | if (!err) | |
3947 | continue; | |
3948 | DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i); | |
3949 | break; | |
3950 | } | |
3951 | ||
3952 | return err; | |
3953 | } | |
3954 | ||
9a799d71 AK |
3955 | /** |
3956 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
3957 | * @adapter: board private structure | |
3958 | * @tx_ring: Tx descriptor ring for a specific queue | |
3959 | * | |
3960 | * Free all transmit software resources | |
3961 | **/ | |
c431f97e JB |
3962 | void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter, |
3963 | struct ixgbe_ring *tx_ring) | |
9a799d71 AK |
3964 | { |
3965 | struct pci_dev *pdev = adapter->pdev; | |
3966 | ||
3967 | ixgbe_clean_tx_ring(adapter, tx_ring); | |
3968 | ||
3969 | vfree(tx_ring->tx_buffer_info); | |
3970 | tx_ring->tx_buffer_info = NULL; | |
3971 | ||
3972 | pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma); | |
3973 | ||
3974 | tx_ring->desc = NULL; | |
3975 | } | |
3976 | ||
3977 | /** | |
3978 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
3979 | * @adapter: board private structure | |
3980 | * | |
3981 | * Free all transmit software resources | |
3982 | **/ | |
3983 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
3984 | { | |
3985 | int i; | |
3986 | ||
3987 | for (i = 0; i < adapter->num_tx_queues; i++) | |
9891ca7c JB |
3988 | if (adapter->tx_ring[i].desc) |
3989 | ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]); | |
9a799d71 AK |
3990 | } |
3991 | ||
3992 | /** | |
b4617240 | 3993 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
3994 | * @adapter: board private structure |
3995 | * @rx_ring: ring to clean the resources from | |
3996 | * | |
3997 | * Free all receive software resources | |
3998 | **/ | |
c431f97e JB |
3999 | void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter, |
4000 | struct ixgbe_ring *rx_ring) | |
9a799d71 AK |
4001 | { |
4002 | struct pci_dev *pdev = adapter->pdev; | |
4003 | ||
4004 | ixgbe_clean_rx_ring(adapter, rx_ring); | |
4005 | ||
4006 | vfree(rx_ring->rx_buffer_info); | |
4007 | rx_ring->rx_buffer_info = NULL; | |
4008 | ||
4009 | pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); | |
4010 | ||
4011 | rx_ring->desc = NULL; | |
4012 | } | |
4013 | ||
4014 | /** | |
4015 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
4016 | * @adapter: board private structure | |
4017 | * | |
4018 | * Free all receive software resources | |
4019 | **/ | |
4020 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
4021 | { | |
4022 | int i; | |
4023 | ||
4024 | for (i = 0; i < adapter->num_rx_queues; i++) | |
9891ca7c JB |
4025 | if (adapter->rx_ring[i].desc) |
4026 | ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]); | |
9a799d71 AK |
4027 | } |
4028 | ||
9a799d71 AK |
4029 | /** |
4030 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
4031 | * @netdev: network interface device structure | |
4032 | * @new_mtu: new value for maximum frame size | |
4033 | * | |
4034 | * Returns 0 on success, negative on failure | |
4035 | **/ | |
4036 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
4037 | { | |
4038 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4039 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
4040 | ||
42c783c5 JB |
4041 | /* MTU < 68 is an error and causes problems on some kernels */ |
4042 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) | |
9a799d71 AK |
4043 | return -EINVAL; |
4044 | ||
021230d4 | 4045 | DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n", |
b4617240 | 4046 | netdev->mtu, new_mtu); |
021230d4 | 4047 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
4048 | netdev->mtu = new_mtu; |
4049 | ||
d4f80882 AV |
4050 | if (netif_running(netdev)) |
4051 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
4052 | |
4053 | return 0; | |
4054 | } | |
4055 | ||
4056 | /** | |
4057 | * ixgbe_open - Called when a network interface is made active | |
4058 | * @netdev: network interface device structure | |
4059 | * | |
4060 | * Returns 0 on success, negative value on failure | |
4061 | * | |
4062 | * The open entry point is called when a network interface is made | |
4063 | * active by the system (IFF_UP). At this point all resources needed | |
4064 | * for transmit and receive operations are allocated, the interrupt | |
4065 | * handler is registered with the OS, the watchdog timer is started, | |
4066 | * and the stack is notified that the interface is ready. | |
4067 | **/ | |
4068 | static int ixgbe_open(struct net_device *netdev) | |
4069 | { | |
4070 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4071 | int err; | |
4bebfaa5 AK |
4072 | |
4073 | /* disallow open during test */ | |
4074 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
4075 | return -EBUSY; | |
9a799d71 | 4076 | |
54386467 JB |
4077 | netif_carrier_off(netdev); |
4078 | ||
9a799d71 AK |
4079 | /* allocate transmit descriptors */ |
4080 | err = ixgbe_setup_all_tx_resources(adapter); | |
4081 | if (err) | |
4082 | goto err_setup_tx; | |
4083 | ||
9a799d71 AK |
4084 | /* allocate receive descriptors */ |
4085 | err = ixgbe_setup_all_rx_resources(adapter); | |
4086 | if (err) | |
4087 | goto err_setup_rx; | |
4088 | ||
4089 | ixgbe_configure(adapter); | |
4090 | ||
021230d4 | 4091 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
4092 | if (err) |
4093 | goto err_req_irq; | |
4094 | ||
9a799d71 AK |
4095 | err = ixgbe_up_complete(adapter); |
4096 | if (err) | |
4097 | goto err_up; | |
4098 | ||
d55b53ff JK |
4099 | netif_tx_start_all_queues(netdev); |
4100 | ||
9a799d71 AK |
4101 | return 0; |
4102 | ||
4103 | err_up: | |
5eba3699 | 4104 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
4105 | ixgbe_free_irq(adapter); |
4106 | err_req_irq: | |
9a799d71 | 4107 | err_setup_rx: |
a20a1199 | 4108 | ixgbe_free_all_rx_resources(adapter); |
9a799d71 | 4109 | err_setup_tx: |
a20a1199 | 4110 | ixgbe_free_all_tx_resources(adapter); |
9a799d71 AK |
4111 | ixgbe_reset(adapter); |
4112 | ||
4113 | return err; | |
4114 | } | |
4115 | ||
4116 | /** | |
4117 | * ixgbe_close - Disables a network interface | |
4118 | * @netdev: network interface device structure | |
4119 | * | |
4120 | * Returns 0, this is not allowed to fail | |
4121 | * | |
4122 | * The close entry point is called when an interface is de-activated | |
4123 | * by the OS. The hardware is still under the drivers control, but | |
4124 | * needs to be disabled. A global MAC reset is issued to stop the | |
4125 | * hardware, and all transmit and receive resources are freed. | |
4126 | **/ | |
4127 | static int ixgbe_close(struct net_device *netdev) | |
4128 | { | |
4129 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 AK |
4130 | |
4131 | ixgbe_down(adapter); | |
4132 | ixgbe_free_irq(adapter); | |
4133 | ||
4134 | ixgbe_free_all_tx_resources(adapter); | |
4135 | ixgbe_free_all_rx_resources(adapter); | |
4136 | ||
5eba3699 | 4137 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
4138 | |
4139 | return 0; | |
4140 | } | |
4141 | ||
b3c8b4ba AD |
4142 | #ifdef CONFIG_PM |
4143 | static int ixgbe_resume(struct pci_dev *pdev) | |
4144 | { | |
4145 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4146 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4147 | u32 err; | |
4148 | ||
4149 | pci_set_power_state(pdev, PCI_D0); | |
4150 | pci_restore_state(pdev); | |
9ce77666 | 4151 | |
4152 | err = pci_enable_device_mem(pdev); | |
b3c8b4ba | 4153 | if (err) { |
69888674 | 4154 | printk(KERN_ERR "ixgbe: Cannot enable PCI device from " |
b3c8b4ba AD |
4155 | "suspend\n"); |
4156 | return err; | |
4157 | } | |
4158 | pci_set_master(pdev); | |
4159 | ||
dd4d8ca6 | 4160 | pci_wake_from_d3(pdev, false); |
b3c8b4ba AD |
4161 | |
4162 | err = ixgbe_init_interrupt_scheme(adapter); | |
4163 | if (err) { | |
4164 | printk(KERN_ERR "ixgbe: Cannot initialize interrupts for " | |
4165 | "device\n"); | |
4166 | return err; | |
4167 | } | |
4168 | ||
b3c8b4ba AD |
4169 | ixgbe_reset(adapter); |
4170 | ||
495dce12 WJP |
4171 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
4172 | ||
b3c8b4ba AD |
4173 | if (netif_running(netdev)) { |
4174 | err = ixgbe_open(adapter->netdev); | |
4175 | if (err) | |
4176 | return err; | |
4177 | } | |
4178 | ||
4179 | netif_device_attach(netdev); | |
4180 | ||
4181 | return 0; | |
4182 | } | |
b3c8b4ba | 4183 | #endif /* CONFIG_PM */ |
9d8d05ae RW |
4184 | |
4185 | static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) | |
b3c8b4ba AD |
4186 | { |
4187 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4188 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
e8e26350 PW |
4189 | struct ixgbe_hw *hw = &adapter->hw; |
4190 | u32 ctrl, fctrl; | |
4191 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
4192 | #ifdef CONFIG_PM |
4193 | int retval = 0; | |
4194 | #endif | |
4195 | ||
4196 | netif_device_detach(netdev); | |
4197 | ||
4198 | if (netif_running(netdev)) { | |
4199 | ixgbe_down(adapter); | |
4200 | ixgbe_free_irq(adapter); | |
4201 | ixgbe_free_all_tx_resources(adapter); | |
4202 | ixgbe_free_all_rx_resources(adapter); | |
4203 | } | |
7a921c93 | 4204 | ixgbe_clear_interrupt_scheme(adapter); |
b3c8b4ba AD |
4205 | |
4206 | #ifdef CONFIG_PM | |
4207 | retval = pci_save_state(pdev); | |
4208 | if (retval) | |
4209 | return retval; | |
4df10466 | 4210 | |
b3c8b4ba | 4211 | #endif |
e8e26350 PW |
4212 | if (wufc) { |
4213 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 4214 | |
e8e26350 PW |
4215 | /* turn on all-multi mode if wake on multicast is enabled */ |
4216 | if (wufc & IXGBE_WUFC_MC) { | |
4217 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
4218 | fctrl |= IXGBE_FCTRL_MPE; | |
4219 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
4220 | } | |
4221 | ||
4222 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
4223 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
4224 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
4225 | ||
4226 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
4227 | } else { | |
4228 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
4229 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
4230 | } | |
4231 | ||
dd4d8ca6 DS |
4232 | if (wufc && hw->mac.type == ixgbe_mac_82599EB) |
4233 | pci_wake_from_d3(pdev, true); | |
4234 | else | |
4235 | pci_wake_from_d3(pdev, false); | |
b3c8b4ba | 4236 | |
9d8d05ae RW |
4237 | *enable_wake = !!wufc; |
4238 | ||
b3c8b4ba AD |
4239 | ixgbe_release_hw_control(adapter); |
4240 | ||
4241 | pci_disable_device(pdev); | |
4242 | ||
9d8d05ae RW |
4243 | return 0; |
4244 | } | |
4245 | ||
4246 | #ifdef CONFIG_PM | |
4247 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
4248 | { | |
4249 | int retval; | |
4250 | bool wake; | |
4251 | ||
4252 | retval = __ixgbe_shutdown(pdev, &wake); | |
4253 | if (retval) | |
4254 | return retval; | |
4255 | ||
4256 | if (wake) { | |
4257 | pci_prepare_to_sleep(pdev); | |
4258 | } else { | |
4259 | pci_wake_from_d3(pdev, false); | |
4260 | pci_set_power_state(pdev, PCI_D3hot); | |
4261 | } | |
b3c8b4ba AD |
4262 | |
4263 | return 0; | |
4264 | } | |
9d8d05ae | 4265 | #endif /* CONFIG_PM */ |
b3c8b4ba AD |
4266 | |
4267 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
4268 | { | |
9d8d05ae RW |
4269 | bool wake; |
4270 | ||
4271 | __ixgbe_shutdown(pdev, &wake); | |
4272 | ||
4273 | if (system_state == SYSTEM_POWER_OFF) { | |
4274 | pci_wake_from_d3(pdev, wake); | |
4275 | pci_set_power_state(pdev, PCI_D3hot); | |
4276 | } | |
b3c8b4ba AD |
4277 | } |
4278 | ||
9a799d71 AK |
4279 | /** |
4280 | * ixgbe_update_stats - Update the board statistics counters. | |
4281 | * @adapter: board private structure | |
4282 | **/ | |
4283 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
4284 | { | |
4285 | struct ixgbe_hw *hw = &adapter->hw; | |
6f11eef7 AV |
4286 | u64 total_mpc = 0; |
4287 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
9a799d71 | 4288 | |
d51019a4 | 4289 | if (hw->mac.type == ixgbe_mac_82599EB) { |
f8212f97 | 4290 | u64 rsc_count = 0; |
d51019a4 PW |
4291 | for (i = 0; i < 16; i++) |
4292 | adapter->hw_rx_no_dma_resources += | |
4293 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
f8212f97 AD |
4294 | for (i = 0; i < adapter->num_rx_queues; i++) |
4295 | rsc_count += adapter->rx_ring[i].rsc_count; | |
4296 | adapter->rsc_count = rsc_count; | |
d51019a4 PW |
4297 | } |
4298 | ||
9a799d71 | 4299 | adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
6f11eef7 AV |
4300 | for (i = 0; i < 8; i++) { |
4301 | /* for packet buffers not used, the register should read 0 */ | |
4302 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
4303 | missed_rx += mpc; | |
4304 | adapter->stats.mpc[i] += mpc; | |
4305 | total_mpc += adapter->stats.mpc[i]; | |
e8e26350 PW |
4306 | if (hw->mac.type == ixgbe_mac_82598EB) |
4307 | adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); | |
2f90b865 AD |
4308 | adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); |
4309 | adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
4310 | adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
4311 | adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
e8e26350 PW |
4312 | if (hw->mac.type == ixgbe_mac_82599EB) { |
4313 | adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, | |
4314 | IXGBE_PXONRXCNT(i)); | |
4315 | adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, | |
4316 | IXGBE_PXOFFRXCNT(i)); | |
4317 | adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
e8e26350 PW |
4318 | } else { |
4319 | adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, | |
4320 | IXGBE_PXONRXC(i)); | |
4321 | adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, | |
4322 | IXGBE_PXOFFRXC(i)); | |
4323 | } | |
2f90b865 AD |
4324 | adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw, |
4325 | IXGBE_PXONTXC(i)); | |
2f90b865 | 4326 | adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw, |
e8e26350 | 4327 | IXGBE_PXOFFTXC(i)); |
6f11eef7 AV |
4328 | } |
4329 | adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); | |
4330 | /* work around hardware counting issue */ | |
4331 | adapter->stats.gprc -= missed_rx; | |
4332 | ||
4333 | /* 82598 hardware only has a 32 bit counter in the high register */ | |
e8e26350 PW |
4334 | if (hw->mac.type == ixgbe_mac_82599EB) { |
4335 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); | |
4336 | IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ | |
4337 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); | |
4338 | IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ | |
4339 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL); | |
4340 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ | |
4341 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); | |
4342 | adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); | |
c4cf55e5 PWJ |
4343 | adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); |
4344 | adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); | |
6d45522c YZ |
4345 | #ifdef IXGBE_FCOE |
4346 | adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); | |
4347 | adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); | |
4348 | adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); | |
4349 | adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); | |
4350 | adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); | |
4351 | adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); | |
4352 | #endif /* IXGBE_FCOE */ | |
e8e26350 PW |
4353 | } else { |
4354 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
4355 | adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
4356 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); | |
4357 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
4358 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
4359 | } | |
9a799d71 AK |
4360 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
4361 | adapter->stats.bprc += bprc; | |
4362 | adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 PW |
4363 | if (hw->mac.type == ixgbe_mac_82598EB) |
4364 | adapter->stats.mprc -= bprc; | |
9a799d71 AK |
4365 | adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC); |
4366 | adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
4367 | adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
4368 | adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
4369 | adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
4370 | adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
4371 | adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
9a799d71 | 4372 | adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); |
6f11eef7 AV |
4373 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
4374 | adapter->stats.lxontxc += lxon; | |
4375 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); | |
4376 | adapter->stats.lxofftxc += lxoff; | |
9a799d71 AK |
4377 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
4378 | adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); | |
6f11eef7 AV |
4379 | adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); |
4380 | /* | |
4381 | * 82598 errata - tx of flow control packets is included in tx counters | |
4382 | */ | |
4383 | xon_off_tot = lxon + lxoff; | |
4384 | adapter->stats.gptc -= xon_off_tot; | |
4385 | adapter->stats.mptc -= xon_off_tot; | |
4386 | adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
9a799d71 AK |
4387 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
4388 | adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
4389 | adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
9a799d71 AK |
4390 | adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR); |
4391 | adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
6f11eef7 | 4392 | adapter->stats.ptc64 -= xon_off_tot; |
9a799d71 AK |
4393 | adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); |
4394 | adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
4395 | adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
4396 | adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
4397 | adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
9a799d71 AK |
4398 | adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); |
4399 | ||
4400 | /* Fill out the OS statistics structure */ | |
9a799d71 AK |
4401 | adapter->net_stats.multicast = adapter->stats.mprc; |
4402 | ||
4403 | /* Rx Errors */ | |
4404 | adapter->net_stats.rx_errors = adapter->stats.crcerrs + | |
b4617240 | 4405 | adapter->stats.rlec; |
9a799d71 AK |
4406 | adapter->net_stats.rx_dropped = 0; |
4407 | adapter->net_stats.rx_length_errors = adapter->stats.rlec; | |
4408 | adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs; | |
6f11eef7 | 4409 | adapter->net_stats.rx_missed_errors = total_mpc; |
9a799d71 AK |
4410 | } |
4411 | ||
4412 | /** | |
4413 | * ixgbe_watchdog - Timer Call-back | |
4414 | * @data: pointer to adapter cast into an unsigned long | |
4415 | **/ | |
4416 | static void ixgbe_watchdog(unsigned long data) | |
4417 | { | |
4418 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
cf8280ee | 4419 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
4420 | u64 eics = 0; |
4421 | int i; | |
cf8280ee | 4422 | |
fe49f04a AD |
4423 | /* |
4424 | * Do the watchdog outside of interrupt context due to the lovely | |
4425 | * delays that some of the newer hardware requires | |
4426 | */ | |
22d5a71b | 4427 | |
fe49f04a AD |
4428 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
4429 | goto watchdog_short_circuit; | |
22d5a71b | 4430 | |
fe49f04a AD |
4431 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
4432 | /* | |
4433 | * for legacy and MSI interrupts don't set any bits | |
4434 | * that are enabled for EIAM, because this operation | |
4435 | * would set *both* EIMS and EICS for any bit in EIAM | |
4436 | */ | |
4437 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
4438 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
4439 | goto watchdog_reschedule; | |
4440 | } | |
4441 | ||
4442 | /* get one bit for every active tx/rx interrupt vector */ | |
4443 | for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) { | |
4444 | struct ixgbe_q_vector *qv = adapter->q_vector[i]; | |
4445 | if (qv->rxr_count || qv->txr_count) | |
4446 | eics |= ((u64)1 << i); | |
cf8280ee | 4447 | } |
9a799d71 | 4448 | |
fe49f04a AD |
4449 | /* Cause software interrupt to ensure rx rings are cleaned */ |
4450 | ixgbe_irq_rearm_queues(adapter, eics); | |
4451 | ||
4452 | watchdog_reschedule: | |
4453 | /* Reset the timer */ | |
4454 | mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ)); | |
4455 | ||
4456 | watchdog_short_circuit: | |
cf8280ee JB |
4457 | schedule_work(&adapter->watchdog_task); |
4458 | } | |
4459 | ||
e8e26350 PW |
4460 | /** |
4461 | * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber | |
4462 | * @work: pointer to work_struct containing our data | |
4463 | **/ | |
4464 | static void ixgbe_multispeed_fiber_task(struct work_struct *work) | |
4465 | { | |
4466 | struct ixgbe_adapter *adapter = container_of(work, | |
4467 | struct ixgbe_adapter, | |
4468 | multispeed_fiber_task); | |
4469 | struct ixgbe_hw *hw = &adapter->hw; | |
4470 | u32 autoneg; | |
4471 | ||
4472 | adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK; | |
4473 | if (hw->mac.ops.get_link_capabilities) | |
4474 | hw->mac.ops.get_link_capabilities(hw, &autoneg, | |
4475 | &hw->mac.autoneg); | |
4476 | if (hw->mac.ops.setup_link_speed) | |
4477 | hw->mac.ops.setup_link_speed(hw, autoneg, true, true); | |
4478 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
4479 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK; | |
4480 | } | |
4481 | ||
4482 | /** | |
4483 | * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module | |
4484 | * @work: pointer to work_struct containing our data | |
4485 | **/ | |
4486 | static void ixgbe_sfp_config_module_task(struct work_struct *work) | |
4487 | { | |
4488 | struct ixgbe_adapter *adapter = container_of(work, | |
4489 | struct ixgbe_adapter, | |
4490 | sfp_config_module_task); | |
4491 | struct ixgbe_hw *hw = &adapter->hw; | |
4492 | u32 err; | |
4493 | ||
4494 | adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK; | |
4495 | err = hw->phy.ops.identify_sfp(hw); | |
4496 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
4497 | DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err); | |
4498 | ixgbe_down(adapter); | |
4499 | return; | |
4500 | } | |
4501 | hw->mac.ops.setup_sfp(hw); | |
4502 | ||
8d1c3c07 | 4503 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) |
e8e26350 PW |
4504 | /* This will also work for DA Twinax connections */ |
4505 | schedule_work(&adapter->multispeed_fiber_task); | |
4506 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK; | |
4507 | } | |
4508 | ||
c4cf55e5 PWJ |
4509 | /** |
4510 | * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table | |
4511 | * @work: pointer to work_struct containing our data | |
4512 | **/ | |
4513 | static void ixgbe_fdir_reinit_task(struct work_struct *work) | |
4514 | { | |
4515 | struct ixgbe_adapter *adapter = container_of(work, | |
4516 | struct ixgbe_adapter, | |
4517 | fdir_reinit_task); | |
4518 | struct ixgbe_hw *hw = &adapter->hw; | |
4519 | int i; | |
4520 | ||
4521 | if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { | |
4522 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4523 | set_bit(__IXGBE_FDIR_INIT_DONE, | |
4524 | &(adapter->tx_ring[i].reinit_state)); | |
4525 | } else { | |
4526 | DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, " | |
4527 | "ignored adding FDIR ATR filters \n"); | |
4528 | } | |
4529 | /* Done FDIR Re-initialization, enable transmits */ | |
4530 | netif_tx_start_all_queues(adapter->netdev); | |
4531 | } | |
4532 | ||
cf8280ee | 4533 | /** |
69888674 AD |
4534 | * ixgbe_watchdog_task - worker thread to bring link up |
4535 | * @work: pointer to work_struct containing our data | |
cf8280ee JB |
4536 | **/ |
4537 | static void ixgbe_watchdog_task(struct work_struct *work) | |
4538 | { | |
4539 | struct ixgbe_adapter *adapter = container_of(work, | |
4540 | struct ixgbe_adapter, | |
4541 | watchdog_task); | |
4542 | struct net_device *netdev = adapter->netdev; | |
4543 | struct ixgbe_hw *hw = &adapter->hw; | |
4544 | u32 link_speed = adapter->link_speed; | |
4545 | bool link_up = adapter->link_up; | |
bc59fcda NS |
4546 | int i; |
4547 | struct ixgbe_ring *tx_ring; | |
4548 | int some_tx_pending = 0; | |
cf8280ee JB |
4549 | |
4550 | adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK; | |
4551 | ||
4552 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { | |
4553 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
264857b8 PWJ |
4554 | if (link_up) { |
4555 | #ifdef CONFIG_DCB | |
4556 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
4557 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) | |
620fa036 | 4558 | hw->mac.ops.fc_enable(hw, i); |
264857b8 | 4559 | } else { |
620fa036 | 4560 | hw->mac.ops.fc_enable(hw, 0); |
264857b8 PWJ |
4561 | } |
4562 | #else | |
620fa036 | 4563 | hw->mac.ops.fc_enable(hw, 0); |
264857b8 PWJ |
4564 | #endif |
4565 | } | |
4566 | ||
cf8280ee JB |
4567 | if (link_up || |
4568 | time_after(jiffies, (adapter->link_check_timeout + | |
4569 | IXGBE_TRY_LINK_TIMEOUT))) { | |
cf8280ee | 4570 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; |
264857b8 | 4571 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); |
cf8280ee JB |
4572 | } |
4573 | adapter->link_up = link_up; | |
4574 | adapter->link_speed = link_speed; | |
4575 | } | |
9a799d71 AK |
4576 | |
4577 | if (link_up) { | |
4578 | if (!netif_carrier_ok(netdev)) { | |
e8e26350 PW |
4579 | bool flow_rx, flow_tx; |
4580 | ||
4581 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
4582 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
4583 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
4584 | flow_rx = (mflcn & IXGBE_MFLCN_RFCE); | |
4585 | flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
4586 | } else { | |
4587 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
4588 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
4589 | flow_rx = (frctl & IXGBE_FCTRL_RFCE); | |
4590 | flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X); | |
4591 | } | |
4592 | ||
a46e534b JK |
4593 | printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, " |
4594 | "Flow Control: %s\n", | |
4595 | netdev->name, | |
4596 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? | |
4597 | "10 Gbps" : | |
4598 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
4599 | "1 Gbps" : "unknown speed")), | |
e8e26350 PW |
4600 | ((flow_rx && flow_tx) ? "RX/TX" : |
4601 | (flow_rx ? "RX" : | |
4602 | (flow_tx ? "TX" : "None")))); | |
9a799d71 AK |
4603 | |
4604 | netif_carrier_on(netdev); | |
9a799d71 AK |
4605 | } else { |
4606 | /* Force detection of hung controller */ | |
4607 | adapter->detect_tx_hung = true; | |
4608 | } | |
4609 | } else { | |
cf8280ee JB |
4610 | adapter->link_up = false; |
4611 | adapter->link_speed = 0; | |
9a799d71 | 4612 | if (netif_carrier_ok(netdev)) { |
a46e534b JK |
4613 | printk(KERN_INFO "ixgbe: %s NIC Link is Down\n", |
4614 | netdev->name); | |
9a799d71 | 4615 | netif_carrier_off(netdev); |
9a799d71 AK |
4616 | } |
4617 | } | |
4618 | ||
bc59fcda NS |
4619 | if (!netif_carrier_ok(netdev)) { |
4620 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4621 | tx_ring = &adapter->tx_ring[i]; | |
4622 | if (tx_ring->next_to_use != tx_ring->next_to_clean) { | |
4623 | some_tx_pending = 1; | |
4624 | break; | |
4625 | } | |
4626 | } | |
4627 | ||
4628 | if (some_tx_pending) { | |
4629 | /* We've lost link, so the controller stops DMA, | |
4630 | * but we've got queued Tx work that's never going | |
4631 | * to get done, so reset controller to flush Tx. | |
4632 | * (Do the reset outside of interrupt context). | |
4633 | */ | |
4634 | schedule_work(&adapter->reset_task); | |
4635 | } | |
4636 | } | |
4637 | ||
9a799d71 | 4638 | ixgbe_update_stats(adapter); |
cf8280ee | 4639 | adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK; |
9a799d71 AK |
4640 | } |
4641 | ||
9a799d71 | 4642 | static int ixgbe_tso(struct ixgbe_adapter *adapter, |
b4617240 PW |
4643 | struct ixgbe_ring *tx_ring, struct sk_buff *skb, |
4644 | u32 tx_flags, u8 *hdr_len) | |
9a799d71 AK |
4645 | { |
4646 | struct ixgbe_adv_tx_context_desc *context_desc; | |
4647 | unsigned int i; | |
4648 | int err; | |
4649 | struct ixgbe_tx_buffer *tx_buffer_info; | |
9f8cdf4f JB |
4650 | u32 vlan_macip_lens = 0, type_tucmd_mlhl; |
4651 | u32 mss_l4len_idx, l4len; | |
9a799d71 AK |
4652 | |
4653 | if (skb_is_gso(skb)) { | |
4654 | if (skb_header_cloned(skb)) { | |
4655 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
4656 | if (err) | |
4657 | return err; | |
4658 | } | |
4659 | l4len = tcp_hdrlen(skb); | |
4660 | *hdr_len += l4len; | |
4661 | ||
8327d000 | 4662 | if (skb->protocol == htons(ETH_P_IP)) { |
9a799d71 AK |
4663 | struct iphdr *iph = ip_hdr(skb); |
4664 | iph->tot_len = 0; | |
4665 | iph->check = 0; | |
4666 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
b4617240 PW |
4667 | iph->daddr, 0, |
4668 | IPPROTO_TCP, | |
4669 | 0); | |
9a799d71 AK |
4670 | adapter->hw_tso_ctxt++; |
4671 | } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) { | |
4672 | ipv6_hdr(skb)->payload_len = 0; | |
4673 | tcp_hdr(skb)->check = | |
4674 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
b4617240 PW |
4675 | &ipv6_hdr(skb)->daddr, |
4676 | 0, IPPROTO_TCP, 0); | |
9a799d71 AK |
4677 | adapter->hw_tso6_ctxt++; |
4678 | } | |
4679 | ||
4680 | i = tx_ring->next_to_use; | |
4681 | ||
4682 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4683 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
4684 | ||
4685 | /* VLAN MACLEN IPLEN */ | |
4686 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
4687 | vlan_macip_lens |= | |
4688 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
4689 | vlan_macip_lens |= ((skb_network_offset(skb)) << | |
b4617240 | 4690 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
4691 | *hdr_len += skb_network_offset(skb); |
4692 | vlan_macip_lens |= | |
4693 | (skb_transport_header(skb) - skb_network_header(skb)); | |
4694 | *hdr_len += | |
4695 | (skb_transport_header(skb) - skb_network_header(skb)); | |
4696 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
4697 | context_desc->seqnum_seed = 0; | |
4698 | ||
4699 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ | |
9f8cdf4f | 4700 | type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT | |
b4617240 | 4701 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 | 4702 | |
8327d000 | 4703 | if (skb->protocol == htons(ETH_P_IP)) |
9a799d71 AK |
4704 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
4705 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
4706 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
4707 | ||
4708 | /* MSS L4LEN IDX */ | |
9f8cdf4f | 4709 | mss_l4len_idx = |
9a799d71 AK |
4710 | (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT); |
4711 | mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT); | |
4eeae6fd PW |
4712 | /* use index 1 for TSO */ |
4713 | mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
4714 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); |
4715 | ||
4716 | tx_buffer_info->time_stamp = jiffies; | |
4717 | tx_buffer_info->next_to_watch = i; | |
4718 | ||
4719 | i++; | |
4720 | if (i == tx_ring->count) | |
4721 | i = 0; | |
4722 | tx_ring->next_to_use = i; | |
4723 | ||
4724 | return true; | |
4725 | } | |
4726 | return false; | |
4727 | } | |
4728 | ||
4729 | static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter, | |
b4617240 PW |
4730 | struct ixgbe_ring *tx_ring, |
4731 | struct sk_buff *skb, u32 tx_flags) | |
9a799d71 AK |
4732 | { |
4733 | struct ixgbe_adv_tx_context_desc *context_desc; | |
4734 | unsigned int i; | |
4735 | struct ixgbe_tx_buffer *tx_buffer_info; | |
4736 | u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0; | |
4737 | ||
4738 | if (skb->ip_summed == CHECKSUM_PARTIAL || | |
4739 | (tx_flags & IXGBE_TX_FLAGS_VLAN)) { | |
4740 | i = tx_ring->next_to_use; | |
4741 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4742 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
4743 | ||
4744 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
4745 | vlan_macip_lens |= | |
4746 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
4747 | vlan_macip_lens |= (skb_network_offset(skb) << | |
b4617240 | 4748 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
4749 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
4750 | vlan_macip_lens |= (skb_transport_header(skb) - | |
b4617240 | 4751 | skb_network_header(skb)); |
9a799d71 AK |
4752 | |
4753 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
4754 | context_desc->seqnum_seed = 0; | |
4755 | ||
4756 | type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT | | |
b4617240 | 4757 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 AK |
4758 | |
4759 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
41825d71 | 4760 | switch (skb->protocol) { |
09640e63 | 4761 | case cpu_to_be16(ETH_P_IP): |
9a799d71 | 4762 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
41825d71 AK |
4763 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) |
4764 | type_tucmd_mlhl |= | |
b4617240 | 4765 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
45a5ead0 JB |
4766 | else if (ip_hdr(skb)->protocol == IPPROTO_SCTP) |
4767 | type_tucmd_mlhl |= | |
4768 | IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
41825d71 | 4769 | break; |
09640e63 | 4770 | case cpu_to_be16(ETH_P_IPV6): |
41825d71 AK |
4771 | /* XXX what about other V6 headers?? */ |
4772 | if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) | |
4773 | type_tucmd_mlhl |= | |
b4617240 | 4774 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
45a5ead0 JB |
4775 | else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP) |
4776 | type_tucmd_mlhl |= | |
4777 | IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
41825d71 | 4778 | break; |
41825d71 AK |
4779 | default: |
4780 | if (unlikely(net_ratelimit())) { | |
4781 | DPRINTK(PROBE, WARNING, | |
4782 | "partial checksum but proto=%x!\n", | |
4783 | skb->protocol); | |
4784 | } | |
4785 | break; | |
4786 | } | |
9a799d71 AK |
4787 | } |
4788 | ||
4789 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
4eeae6fd | 4790 | /* use index zero for tx checksum offload */ |
9a799d71 AK |
4791 | context_desc->mss_l4len_idx = 0; |
4792 | ||
4793 | tx_buffer_info->time_stamp = jiffies; | |
4794 | tx_buffer_info->next_to_watch = i; | |
9f8cdf4f | 4795 | |
9a799d71 AK |
4796 | adapter->hw_csum_tx_good++; |
4797 | i++; | |
4798 | if (i == tx_ring->count) | |
4799 | i = 0; | |
4800 | tx_ring->next_to_use = i; | |
4801 | ||
4802 | return true; | |
4803 | } | |
9f8cdf4f | 4804 | |
9a799d71 AK |
4805 | return false; |
4806 | } | |
4807 | ||
4808 | static int ixgbe_tx_map(struct ixgbe_adapter *adapter, | |
b4617240 | 4809 | struct ixgbe_ring *tx_ring, |
eacd73f7 YZ |
4810 | struct sk_buff *skb, u32 tx_flags, |
4811 | unsigned int first) | |
9a799d71 AK |
4812 | { |
4813 | struct ixgbe_tx_buffer *tx_buffer_info; | |
eacd73f7 YZ |
4814 | unsigned int len; |
4815 | unsigned int total = skb->len; | |
9a799d71 AK |
4816 | unsigned int offset = 0, size, count = 0, i; |
4817 | unsigned int nr_frags = skb_shinfo(skb)->nr_frags; | |
4818 | unsigned int f; | |
44df32c5 | 4819 | dma_addr_t *map; |
9a799d71 AK |
4820 | |
4821 | i = tx_ring->next_to_use; | |
4822 | ||
44df32c5 AD |
4823 | if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) { |
4824 | dev_err(&adapter->pdev->dev, "TX DMA map failed\n"); | |
4825 | return 0; | |
4826 | } | |
4827 | ||
4828 | map = skb_shinfo(skb)->dma_maps; | |
4829 | ||
eacd73f7 YZ |
4830 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) |
4831 | /* excluding fcoe_crc_eof for FCoE */ | |
4832 | total -= sizeof(struct fcoe_crc_eof); | |
4833 | ||
4834 | len = min(skb_headlen(skb), total); | |
9a799d71 AK |
4835 | while (len) { |
4836 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4837 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
4838 | ||
4839 | tx_buffer_info->length = size; | |
042a53a9 | 4840 | tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset; |
9a799d71 AK |
4841 | tx_buffer_info->time_stamp = jiffies; |
4842 | tx_buffer_info->next_to_watch = i; | |
4843 | ||
4844 | len -= size; | |
eacd73f7 | 4845 | total -= size; |
9a799d71 AK |
4846 | offset += size; |
4847 | count++; | |
44df32c5 AD |
4848 | |
4849 | if (len) { | |
4850 | i++; | |
4851 | if (i == tx_ring->count) | |
4852 | i = 0; | |
4853 | } | |
9a799d71 AK |
4854 | } |
4855 | ||
4856 | for (f = 0; f < nr_frags; f++) { | |
4857 | struct skb_frag_struct *frag; | |
4858 | ||
4859 | frag = &skb_shinfo(skb)->frags[f]; | |
eacd73f7 | 4860 | len = min((unsigned int)frag->size, total); |
44df32c5 | 4861 | offset = 0; |
9a799d71 AK |
4862 | |
4863 | while (len) { | |
44df32c5 AD |
4864 | i++; |
4865 | if (i == tx_ring->count) | |
4866 | i = 0; | |
4867 | ||
9a799d71 AK |
4868 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
4869 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
4870 | ||
4871 | tx_buffer_info->length = size; | |
042a53a9 | 4872 | tx_buffer_info->dma = map[f] + offset; |
9a799d71 AK |
4873 | tx_buffer_info->time_stamp = jiffies; |
4874 | tx_buffer_info->next_to_watch = i; | |
4875 | ||
4876 | len -= size; | |
eacd73f7 | 4877 | total -= size; |
9a799d71 AK |
4878 | offset += size; |
4879 | count++; | |
9a799d71 | 4880 | } |
eacd73f7 YZ |
4881 | if (total == 0) |
4882 | break; | |
9a799d71 | 4883 | } |
44df32c5 | 4884 | |
9a799d71 AK |
4885 | tx_ring->tx_buffer_info[i].skb = skb; |
4886 | tx_ring->tx_buffer_info[first].next_to_watch = i; | |
4887 | ||
4888 | return count; | |
4889 | } | |
4890 | ||
4891 | static void ixgbe_tx_queue(struct ixgbe_adapter *adapter, | |
b4617240 PW |
4892 | struct ixgbe_ring *tx_ring, |
4893 | int tx_flags, int count, u32 paylen, u8 hdr_len) | |
9a799d71 AK |
4894 | { |
4895 | union ixgbe_adv_tx_desc *tx_desc = NULL; | |
4896 | struct ixgbe_tx_buffer *tx_buffer_info; | |
4897 | u32 olinfo_status = 0, cmd_type_len = 0; | |
4898 | unsigned int i; | |
4899 | u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS; | |
4900 | ||
4901 | cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA; | |
4902 | ||
4903 | cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT; | |
4904 | ||
4905 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
4906 | cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE; | |
4907 | ||
4908 | if (tx_flags & IXGBE_TX_FLAGS_TSO) { | |
4909 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
4910 | ||
4911 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 4912 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 4913 | |
4eeae6fd PW |
4914 | /* use index 1 context for tso */ |
4915 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
4916 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) |
4917 | olinfo_status |= IXGBE_TXD_POPTS_IXSM << | |
b4617240 | 4918 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 AK |
4919 | |
4920 | } else if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
4921 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 4922 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 4923 | |
eacd73f7 YZ |
4924 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { |
4925 | olinfo_status |= IXGBE_ADVTXD_CC; | |
4926 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
4927 | if (tx_flags & IXGBE_TX_FLAGS_FSO) | |
4928 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
4929 | } | |
4930 | ||
9a799d71 AK |
4931 | olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT); |
4932 | ||
4933 | i = tx_ring->next_to_use; | |
4934 | while (count--) { | |
4935 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4936 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); | |
4937 | tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma); | |
4938 | tx_desc->read.cmd_type_len = | |
b4617240 | 4939 | cpu_to_le32(cmd_type_len | tx_buffer_info->length); |
9a799d71 | 4940 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
9a799d71 AK |
4941 | i++; |
4942 | if (i == tx_ring->count) | |
4943 | i = 0; | |
4944 | } | |
4945 | ||
4946 | tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd); | |
4947 | ||
4948 | /* | |
4949 | * Force memory writes to complete before letting h/w | |
4950 | * know there are new descriptors to fetch. (Only | |
4951 | * applicable for weak-ordered memory model archs, | |
4952 | * such as IA-64). | |
4953 | */ | |
4954 | wmb(); | |
4955 | ||
4956 | tx_ring->next_to_use = i; | |
4957 | writel(i, adapter->hw.hw_addr + tx_ring->tail); | |
4958 | } | |
4959 | ||
c4cf55e5 PWJ |
4960 | static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb, |
4961 | int queue, u32 tx_flags) | |
4962 | { | |
4963 | /* Right now, we support IPv4 only */ | |
4964 | struct ixgbe_atr_input atr_input; | |
4965 | struct tcphdr *th; | |
4966 | struct udphdr *uh; | |
4967 | struct iphdr *iph = ip_hdr(skb); | |
4968 | struct ethhdr *eth = (struct ethhdr *)skb->data; | |
4969 | u16 vlan_id, src_port, dst_port, flex_bytes; | |
4970 | u32 src_ipv4_addr, dst_ipv4_addr; | |
4971 | u8 l4type = 0; | |
4972 | ||
4973 | /* check if we're UDP or TCP */ | |
4974 | if (iph->protocol == IPPROTO_TCP) { | |
4975 | th = tcp_hdr(skb); | |
4976 | src_port = th->source; | |
4977 | dst_port = th->dest; | |
4978 | l4type |= IXGBE_ATR_L4TYPE_TCP; | |
4979 | /* l4type IPv4 type is 0, no need to assign */ | |
4980 | } else if(iph->protocol == IPPROTO_UDP) { | |
4981 | uh = udp_hdr(skb); | |
4982 | src_port = uh->source; | |
4983 | dst_port = uh->dest; | |
4984 | l4type |= IXGBE_ATR_L4TYPE_UDP; | |
4985 | /* l4type IPv4 type is 0, no need to assign */ | |
4986 | } else { | |
4987 | /* Unsupported L4 header, just bail here */ | |
4988 | return; | |
4989 | } | |
4990 | ||
4991 | memset(&atr_input, 0, sizeof(struct ixgbe_atr_input)); | |
4992 | ||
4993 | vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >> | |
4994 | IXGBE_TX_FLAGS_VLAN_SHIFT; | |
4995 | src_ipv4_addr = iph->saddr; | |
4996 | dst_ipv4_addr = iph->daddr; | |
4997 | flex_bytes = eth->h_proto; | |
4998 | ||
4999 | ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id); | |
5000 | ixgbe_atr_set_src_port_82599(&atr_input, dst_port); | |
5001 | ixgbe_atr_set_dst_port_82599(&atr_input, src_port); | |
5002 | ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes); | |
5003 | ixgbe_atr_set_l4type_82599(&atr_input, l4type); | |
5004 | /* src and dst are inverted, think how the receiver sees them */ | |
5005 | ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr); | |
5006 | ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr); | |
5007 | ||
5008 | /* This assumes the Rx queue and Tx queue are bound to the same CPU */ | |
5009 | ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue); | |
5010 | } | |
5011 | ||
e092be60 | 5012 | static int __ixgbe_maybe_stop_tx(struct net_device *netdev, |
b4617240 | 5013 | struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
5014 | { |
5015 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5016 | ||
30eba97a | 5017 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
e092be60 AV |
5018 | /* Herbert's original patch had: |
5019 | * smp_mb__after_netif_stop_queue(); | |
5020 | * but since that doesn't exist yet, just open code it. */ | |
5021 | smp_mb(); | |
5022 | ||
5023 | /* We need to check again in a case another CPU has just | |
5024 | * made room available. */ | |
5025 | if (likely(IXGBE_DESC_UNUSED(tx_ring) < size)) | |
5026 | return -EBUSY; | |
5027 | ||
5028 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
af72166f | 5029 | netif_start_subqueue(netdev, tx_ring->queue_index); |
e092be60 AV |
5030 | ++adapter->restart_queue; |
5031 | return 0; | |
5032 | } | |
5033 | ||
5034 | static int ixgbe_maybe_stop_tx(struct net_device *netdev, | |
b4617240 | 5035 | struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
5036 | { |
5037 | if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size)) | |
5038 | return 0; | |
5039 | return __ixgbe_maybe_stop_tx(netdev, tx_ring, size); | |
5040 | } | |
5041 | ||
09a3b1f8 SH |
5042 | static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb) |
5043 | { | |
5044 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
5045 | ||
c4cf55e5 PWJ |
5046 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) |
5047 | return smp_processor_id(); | |
5048 | ||
09a3b1f8 SH |
5049 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) |
5050 | return 0; /* All traffic should default to class 0 */ | |
5051 | ||
5052 | return skb_tx_hash(dev, skb); | |
5053 | } | |
5054 | ||
9a799d71 AK |
5055 | static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev) |
5056 | { | |
5057 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5058 | struct ixgbe_ring *tx_ring; | |
9a799d71 AK |
5059 | unsigned int first; |
5060 | unsigned int tx_flags = 0; | |
30eba97a AV |
5061 | u8 hdr_len = 0; |
5062 | int r_idx = 0, tso; | |
9a799d71 AK |
5063 | int count = 0; |
5064 | unsigned int f; | |
9f8cdf4f | 5065 | |
95615d90 | 5066 | r_idx = skb->queue_mapping; |
30eba97a | 5067 | tx_ring = &adapter->tx_ring[r_idx]; |
9a799d71 | 5068 | |
9f8cdf4f JB |
5069 | if (adapter->vlgrp && vlan_tx_tag_present(skb)) { |
5070 | tx_flags |= vlan_tx_tag_get(skb); | |
2f90b865 AD |
5071 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
5072 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; | |
5073 | tx_flags |= (skb->queue_mapping << 13); | |
5074 | } | |
5075 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; | |
5076 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
5077 | } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
5078 | tx_flags |= (skb->queue_mapping << 13); | |
9f8cdf4f JB |
5079 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; |
5080 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
9a799d71 | 5081 | } |
eacd73f7 YZ |
5082 | |
5083 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
5084 | (skb->protocol == htons(ETH_P_FCOE))) | |
5085 | tx_flags |= IXGBE_TX_FLAGS_FCOE; | |
5086 | ||
5087 | /* four things can cause us to need a context descriptor */ | |
9f8cdf4f JB |
5088 | if (skb_is_gso(skb) || |
5089 | (skb->ip_summed == CHECKSUM_PARTIAL) || | |
eacd73f7 YZ |
5090 | (tx_flags & IXGBE_TX_FLAGS_VLAN) || |
5091 | (tx_flags & IXGBE_TX_FLAGS_FCOE)) | |
9a799d71 AK |
5092 | count++; |
5093 | ||
9f8cdf4f JB |
5094 | count += TXD_USE_COUNT(skb_headlen(skb)); |
5095 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
9a799d71 AK |
5096 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); |
5097 | ||
e092be60 | 5098 | if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) { |
9a799d71 | 5099 | adapter->tx_busy++; |
9a799d71 AK |
5100 | return NETDEV_TX_BUSY; |
5101 | } | |
9a799d71 | 5102 | |
9a799d71 | 5103 | first = tx_ring->next_to_use; |
eacd73f7 YZ |
5104 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { |
5105 | #ifdef IXGBE_FCOE | |
5106 | /* setup tx offload for FCoE */ | |
5107 | tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
5108 | if (tso < 0) { | |
5109 | dev_kfree_skb_any(skb); | |
5110 | return NETDEV_TX_OK; | |
5111 | } | |
5112 | if (tso) | |
5113 | tx_flags |= IXGBE_TX_FLAGS_FSO; | |
5114 | #endif /* IXGBE_FCOE */ | |
5115 | } else { | |
5116 | if (skb->protocol == htons(ETH_P_IP)) | |
5117 | tx_flags |= IXGBE_TX_FLAGS_IPV4; | |
5118 | tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
5119 | if (tso < 0) { | |
5120 | dev_kfree_skb_any(skb); | |
5121 | return NETDEV_TX_OK; | |
5122 | } | |
9a799d71 | 5123 | |
eacd73f7 YZ |
5124 | if (tso) |
5125 | tx_flags |= IXGBE_TX_FLAGS_TSO; | |
5126 | else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) && | |
5127 | (skb->ip_summed == CHECKSUM_PARTIAL)) | |
5128 | tx_flags |= IXGBE_TX_FLAGS_CSUM; | |
5129 | } | |
9a799d71 | 5130 | |
eacd73f7 | 5131 | count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first); |
44df32c5 | 5132 | if (count) { |
c4cf55e5 PWJ |
5133 | /* add the ATR filter if ATR is on */ |
5134 | if (tx_ring->atr_sample_rate) { | |
5135 | ++tx_ring->atr_count; | |
5136 | if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) && | |
5137 | test_bit(__IXGBE_FDIR_INIT_DONE, | |
5138 | &tx_ring->reinit_state)) { | |
5139 | ixgbe_atr(adapter, skb, tx_ring->queue_index, | |
5140 | tx_flags); | |
5141 | tx_ring->atr_count = 0; | |
5142 | } | |
5143 | } | |
44df32c5 AD |
5144 | ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len, |
5145 | hdr_len); | |
44df32c5 | 5146 | ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED); |
9a799d71 | 5147 | |
44df32c5 AD |
5148 | } else { |
5149 | dev_kfree_skb_any(skb); | |
5150 | tx_ring->tx_buffer_info[first].time_stamp = 0; | |
5151 | tx_ring->next_to_use = first; | |
5152 | } | |
9a799d71 AK |
5153 | |
5154 | return NETDEV_TX_OK; | |
5155 | } | |
5156 | ||
5157 | /** | |
5158 | * ixgbe_get_stats - Get System Network Statistics | |
5159 | * @netdev: network interface device structure | |
5160 | * | |
5161 | * Returns the address of the device statistics structure. | |
5162 | * The statistics are actually updated from the timer callback. | |
5163 | **/ | |
5164 | static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev) | |
5165 | { | |
5166 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5167 | ||
5168 | /* only return the current stats */ | |
5169 | return &adapter->net_stats; | |
5170 | } | |
5171 | ||
5172 | /** | |
5173 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
5174 | * @netdev: network interface device structure | |
5175 | * @p: pointer to an address structure | |
5176 | * | |
5177 | * Returns 0 on success, negative on failure | |
5178 | **/ | |
5179 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
5180 | { | |
5181 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 5182 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
5183 | struct sockaddr *addr = p; |
5184 | ||
5185 | if (!is_valid_ether_addr(addr->sa_data)) | |
5186 | return -EADDRNOTAVAIL; | |
5187 | ||
5188 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 5189 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 5190 | |
b4617240 | 5191 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
9a799d71 AK |
5192 | |
5193 | return 0; | |
5194 | } | |
5195 | ||
6b73e10d BH |
5196 | static int |
5197 | ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) | |
5198 | { | |
5199 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5200 | struct ixgbe_hw *hw = &adapter->hw; | |
5201 | u16 value; | |
5202 | int rc; | |
5203 | ||
5204 | if (prtad != hw->phy.mdio.prtad) | |
5205 | return -EINVAL; | |
5206 | rc = hw->phy.ops.read_reg(hw, addr, devad, &value); | |
5207 | if (!rc) | |
5208 | rc = value; | |
5209 | return rc; | |
5210 | } | |
5211 | ||
5212 | static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, | |
5213 | u16 addr, u16 value) | |
5214 | { | |
5215 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5216 | struct ixgbe_hw *hw = &adapter->hw; | |
5217 | ||
5218 | if (prtad != hw->phy.mdio.prtad) | |
5219 | return -EINVAL; | |
5220 | return hw->phy.ops.write_reg(hw, addr, devad, value); | |
5221 | } | |
5222 | ||
5223 | static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | |
5224 | { | |
5225 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5226 | ||
5227 | return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); | |
5228 | } | |
5229 | ||
0365e6e4 PW |
5230 | /** |
5231 | * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding | |
5232 | * netdev->dev_addr_list | |
5233 | * @netdev: network interface device structure | |
5234 | * | |
5235 | * Returns non-zero on failure | |
5236 | **/ | |
5237 | static int ixgbe_add_sanmac_netdev(struct net_device *dev) | |
5238 | { | |
5239 | int err = 0; | |
5240 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
5241 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
5242 | ||
5243 | if (is_valid_ether_addr(mac->san_addr)) { | |
5244 | rtnl_lock(); | |
5245 | err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
5246 | rtnl_unlock(); | |
5247 | } | |
5248 | return err; | |
5249 | } | |
5250 | ||
5251 | /** | |
5252 | * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding | |
5253 | * netdev->dev_addr_list | |
5254 | * @netdev: network interface device structure | |
5255 | * | |
5256 | * Returns non-zero on failure | |
5257 | **/ | |
5258 | static int ixgbe_del_sanmac_netdev(struct net_device *dev) | |
5259 | { | |
5260 | int err = 0; | |
5261 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
5262 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
5263 | ||
5264 | if (is_valid_ether_addr(mac->san_addr)) { | |
5265 | rtnl_lock(); | |
5266 | err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
5267 | rtnl_unlock(); | |
5268 | } | |
5269 | return err; | |
5270 | } | |
5271 | ||
9a799d71 AK |
5272 | #ifdef CONFIG_NET_POLL_CONTROLLER |
5273 | /* | |
5274 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
5275 | * without having to re-enable interrupts. It's not called while | |
5276 | * the interrupt routine is executing. | |
5277 | */ | |
5278 | static void ixgbe_netpoll(struct net_device *netdev) | |
5279 | { | |
5280 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5281 | ||
5282 | disable_irq(adapter->pdev->irq); | |
5283 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; | |
5284 | ixgbe_intr(adapter->pdev->irq, netdev); | |
5285 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; | |
5286 | enable_irq(adapter->pdev->irq); | |
5287 | } | |
5288 | #endif | |
5289 | ||
0edc3527 SH |
5290 | static const struct net_device_ops ixgbe_netdev_ops = { |
5291 | .ndo_open = ixgbe_open, | |
5292 | .ndo_stop = ixgbe_close, | |
00829823 | 5293 | .ndo_start_xmit = ixgbe_xmit_frame, |
09a3b1f8 | 5294 | .ndo_select_queue = ixgbe_select_queue, |
0edc3527 | 5295 | .ndo_get_stats = ixgbe_get_stats, |
e90d400c | 5296 | .ndo_set_rx_mode = ixgbe_set_rx_mode, |
0edc3527 SH |
5297 | .ndo_set_multicast_list = ixgbe_set_rx_mode, |
5298 | .ndo_validate_addr = eth_validate_addr, | |
5299 | .ndo_set_mac_address = ixgbe_set_mac, | |
5300 | .ndo_change_mtu = ixgbe_change_mtu, | |
5301 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
5302 | .ndo_vlan_rx_register = ixgbe_vlan_rx_register, | |
5303 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, | |
5304 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
6b73e10d | 5305 | .ndo_do_ioctl = ixgbe_ioctl, |
0edc3527 SH |
5306 | #ifdef CONFIG_NET_POLL_CONTROLLER |
5307 | .ndo_poll_controller = ixgbe_netpoll, | |
5308 | #endif | |
332d4a7d YZ |
5309 | #ifdef IXGBE_FCOE |
5310 | .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, | |
5311 | .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, | |
5312 | #endif /* IXGBE_FCOE */ | |
0edc3527 SH |
5313 | }; |
5314 | ||
9a799d71 AK |
5315 | /** |
5316 | * ixgbe_probe - Device Initialization Routine | |
5317 | * @pdev: PCI device information struct | |
5318 | * @ent: entry in ixgbe_pci_tbl | |
5319 | * | |
5320 | * Returns 0 on success, negative on failure | |
5321 | * | |
5322 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
5323 | * The OS initialization, configuring of the adapter private structure, | |
5324 | * and a hardware reset occur. | |
5325 | **/ | |
5326 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
b4617240 | 5327 | const struct pci_device_id *ent) |
9a799d71 AK |
5328 | { |
5329 | struct net_device *netdev; | |
5330 | struct ixgbe_adapter *adapter = NULL; | |
5331 | struct ixgbe_hw *hw; | |
5332 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
5333 | static int cards_found; |
5334 | int i, err, pci_using_dac; | |
eacd73f7 YZ |
5335 | #ifdef IXGBE_FCOE |
5336 | u16 device_caps; | |
5337 | #endif | |
c44ade9e | 5338 | u32 part_num, eec; |
9a799d71 | 5339 | |
9ce77666 | 5340 | err = pci_enable_device_mem(pdev); |
9a799d71 AK |
5341 | if (err) |
5342 | return err; | |
5343 | ||
6a35528a YH |
5344 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && |
5345 | !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { | |
9a799d71 AK |
5346 | pci_using_dac = 1; |
5347 | } else { | |
284901a9 | 5348 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
9a799d71 | 5349 | if (err) { |
284901a9 | 5350 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
9a799d71 | 5351 | if (err) { |
b4617240 PW |
5352 | dev_err(&pdev->dev, "No usable DMA " |
5353 | "configuration, aborting\n"); | |
9a799d71 AK |
5354 | goto err_dma; |
5355 | } | |
5356 | } | |
5357 | pci_using_dac = 0; | |
5358 | } | |
5359 | ||
9ce77666 | 5360 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
5361 | IORESOURCE_MEM), ixgbe_driver_name); | |
9a799d71 | 5362 | if (err) { |
9ce77666 | 5363 | dev_err(&pdev->dev, |
5364 | "pci_request_selected_regions failed 0x%x\n", err); | |
9a799d71 AK |
5365 | goto err_pci_reg; |
5366 | } | |
5367 | ||
6fabd715 PWJ |
5368 | err = pci_enable_pcie_error_reporting(pdev); |
5369 | if (err) { | |
5370 | dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed " | |
5371 | "0x%x\n", err); | |
5372 | /* non-fatal, continue */ | |
5373 | } | |
5374 | ||
9a799d71 | 5375 | pci_set_master(pdev); |
fb3b27bc | 5376 | pci_save_state(pdev); |
9a799d71 | 5377 | |
30eba97a | 5378 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES); |
9a799d71 AK |
5379 | if (!netdev) { |
5380 | err = -ENOMEM; | |
5381 | goto err_alloc_etherdev; | |
5382 | } | |
5383 | ||
9a799d71 AK |
5384 | SET_NETDEV_DEV(netdev, &pdev->dev); |
5385 | ||
5386 | pci_set_drvdata(pdev, netdev); | |
5387 | adapter = netdev_priv(netdev); | |
5388 | ||
5389 | adapter->netdev = netdev; | |
5390 | adapter->pdev = pdev; | |
5391 | hw = &adapter->hw; | |
5392 | hw->back = adapter; | |
5393 | adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1; | |
5394 | ||
05857980 JK |
5395 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
5396 | pci_resource_len(pdev, 0)); | |
9a799d71 AK |
5397 | if (!hw->hw_addr) { |
5398 | err = -EIO; | |
5399 | goto err_ioremap; | |
5400 | } | |
5401 | ||
5402 | for (i = 1; i <= 5; i++) { | |
5403 | if (pci_resource_len(pdev, i) == 0) | |
5404 | continue; | |
5405 | } | |
5406 | ||
0edc3527 | 5407 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 5408 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 5409 | netdev->watchdog_timeo = 5 * HZ; |
9a799d71 AK |
5410 | strcpy(netdev->name, pci_name(pdev)); |
5411 | ||
9a799d71 AK |
5412 | adapter->bd_number = cards_found; |
5413 | ||
9a799d71 AK |
5414 | /* Setup hw api */ |
5415 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 5416 | hw->mac.type = ii->mac; |
9a799d71 | 5417 | |
c44ade9e JB |
5418 | /* EEPROM */ |
5419 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
5420 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
5421 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
5422 | if (!(eec & (1 << 8))) | |
5423 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
5424 | ||
5425 | /* PHY */ | |
5426 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 | 5427 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
6b73e10d BH |
5428 | /* ixgbe_identify_phy_generic will set prtad and mmds properly */ |
5429 | hw->phy.mdio.prtad = MDIO_PRTAD_NONE; | |
5430 | hw->phy.mdio.mmds = 0; | |
5431 | hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
5432 | hw->phy.mdio.dev = netdev; | |
5433 | hw->phy.mdio.mdio_read = ixgbe_mdio_read; | |
5434 | hw->phy.mdio.mdio_write = ixgbe_mdio_write; | |
c4900be0 DS |
5435 | |
5436 | /* set up this timer and work struct before calling get_invariants | |
5437 | * which might start the timer | |
5438 | */ | |
5439 | init_timer(&adapter->sfp_timer); | |
5440 | adapter->sfp_timer.function = &ixgbe_sfp_timer; | |
5441 | adapter->sfp_timer.data = (unsigned long) adapter; | |
5442 | ||
5443 | INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task); | |
c44ade9e | 5444 | |
e8e26350 PW |
5445 | /* multispeed fiber has its own tasklet, called from GPI SDP1 context */ |
5446 | INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task); | |
5447 | ||
5448 | /* a new SFP+ module arrival, called from GPI SDP2 context */ | |
5449 | INIT_WORK(&adapter->sfp_config_module_task, | |
5450 | ixgbe_sfp_config_module_task); | |
5451 | ||
8ca783ab | 5452 | ii->get_invariants(hw); |
9a799d71 AK |
5453 | |
5454 | /* setup the private structure */ | |
5455 | err = ixgbe_sw_init(adapter); | |
5456 | if (err) | |
5457 | goto err_sw_init; | |
5458 | ||
bf069c97 DS |
5459 | /* |
5460 | * If there is a fan on this device and it has failed log the | |
5461 | * failure. | |
5462 | */ | |
5463 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
5464 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
5465 | if (esdp & IXGBE_ESDP_SDP1) | |
5466 | DPRINTK(PROBE, CRIT, | |
5467 | "Fan has stopped, replace the adapter\n"); | |
5468 | } | |
5469 | ||
c44ade9e JB |
5470 | /* reset_hw fills in the perm_addr as well */ |
5471 | err = hw->mac.ops.reset_hw(hw); | |
8ca783ab DS |
5472 | if (err == IXGBE_ERR_SFP_NOT_PRESENT && |
5473 | hw->mac.type == ixgbe_mac_82598EB) { | |
5474 | /* | |
5475 | * Start a kernel thread to watch for a module to arrive. | |
5476 | * Only do this for 82598, since 82599 will generate | |
5477 | * interrupts on module arrival. | |
5478 | */ | |
5479 | set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
5480 | mod_timer(&adapter->sfp_timer, | |
5481 | round_jiffies(jiffies + (2 * HZ))); | |
5482 | err = 0; | |
5483 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
04f165ef PW |
5484 | dev_err(&adapter->pdev->dev, "failed to load because an " |
5485 | "unsupported SFP+ module type was detected.\n"); | |
5486 | goto err_sw_init; | |
5487 | } else if (err) { | |
c44ade9e JB |
5488 | dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err); |
5489 | goto err_sw_init; | |
5490 | } | |
5491 | ||
9a799d71 | 5492 | netdev->features = NETIF_F_SG | |
b4617240 PW |
5493 | NETIF_F_IP_CSUM | |
5494 | NETIF_F_HW_VLAN_TX | | |
5495 | NETIF_F_HW_VLAN_RX | | |
5496 | NETIF_F_HW_VLAN_FILTER; | |
9a799d71 | 5497 | |
e9990a9c | 5498 | netdev->features |= NETIF_F_IPV6_CSUM; |
9a799d71 | 5499 | netdev->features |= NETIF_F_TSO; |
9a799d71 | 5500 | netdev->features |= NETIF_F_TSO6; |
78b6f4ce | 5501 | netdev->features |= NETIF_F_GRO; |
ad31c402 | 5502 | |
45a5ead0 JB |
5503 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) |
5504 | netdev->features |= NETIF_F_SCTP_CSUM; | |
5505 | ||
ad31c402 JK |
5506 | netdev->vlan_features |= NETIF_F_TSO; |
5507 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 5508 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
ad31c402 JK |
5509 | netdev->vlan_features |= NETIF_F_SG; |
5510 | ||
2f90b865 AD |
5511 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) |
5512 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
5513 | ||
7a6b6f51 | 5514 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
5515 | netdev->dcbnl_ops = &dcbnl_ops; |
5516 | #endif | |
5517 | ||
eacd73f7 YZ |
5518 | #ifdef IXGBE_FCOE |
5519 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
5520 | if (hw->mac.ops.get_device_caps) { | |
5521 | hw->mac.ops.get_device_caps(hw, &device_caps); | |
5522 | if (!(device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)) { | |
5523 | netdev->features |= NETIF_F_FCOE_CRC; | |
5524 | netdev->features |= NETIF_F_FSO; | |
332d4a7d | 5525 | netdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX - 1; |
c4cf55e5 PWJ |
5526 | DPRINTK(DRV, INFO, "FCoE enabled, " |
5527 | "disabling Flow Director\n"); | |
5528 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
5529 | adapter->flags &= | |
5530 | ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
5531 | adapter->atr_sample_rate = 0; | |
eacd73f7 YZ |
5532 | } else { |
5533 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
5534 | } | |
5535 | } | |
5536 | } | |
5537 | #endif /* IXGBE_FCOE */ | |
9a799d71 AK |
5538 | if (pci_using_dac) |
5539 | netdev->features |= NETIF_F_HIGHDMA; | |
5540 | ||
df647b5c | 5541 | if (adapter->flags & IXGBE_FLAG2_RSC_ENABLED) |
f8212f97 AD |
5542 | netdev->features |= NETIF_F_LRO; |
5543 | ||
9a799d71 | 5544 | /* make sure the EEPROM is good */ |
c44ade9e | 5545 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
9a799d71 AK |
5546 | dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n"); |
5547 | err = -EIO; | |
5548 | goto err_eeprom; | |
5549 | } | |
5550 | ||
5551 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
5552 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
5553 | ||
c44ade9e JB |
5554 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
5555 | dev_err(&pdev->dev, "invalid MAC address\n"); | |
9a799d71 AK |
5556 | err = -EIO; |
5557 | goto err_eeprom; | |
5558 | } | |
5559 | ||
5560 | init_timer(&adapter->watchdog_timer); | |
5561 | adapter->watchdog_timer.function = &ixgbe_watchdog; | |
5562 | adapter->watchdog_timer.data = (unsigned long)adapter; | |
5563 | ||
5564 | INIT_WORK(&adapter->reset_task, ixgbe_reset_task); | |
cf8280ee | 5565 | INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task); |
9a799d71 | 5566 | |
021230d4 AV |
5567 | err = ixgbe_init_interrupt_scheme(adapter); |
5568 | if (err) | |
5569 | goto err_sw_init; | |
9a799d71 | 5570 | |
e8e26350 PW |
5571 | switch (pdev->device) { |
5572 | case IXGBE_DEV_ID_82599_KX4: | |
495dce12 WJP |
5573 | adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX | |
5574 | IXGBE_WUFC_MC | IXGBE_WUFC_BC); | |
bdf0a550 PWJ |
5575 | /* Enable ACPI wakeup in GRC */ |
5576 | IXGBE_WRITE_REG(hw, IXGBE_GRC, | |
5577 | (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME)); | |
e8e26350 PW |
5578 | break; |
5579 | default: | |
5580 | adapter->wol = 0; | |
5581 | break; | |
5582 | } | |
5583 | device_init_wakeup(&adapter->pdev->dev, true); | |
5584 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); | |
5585 | ||
04f165ef PW |
5586 | /* pick up the PCI bus settings for reporting later */ |
5587 | hw->mac.ops.get_bus_info(hw); | |
5588 | ||
9a799d71 | 5589 | /* print bus type/speed/width info */ |
7c510e4b | 5590 | dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n", |
e8e26350 PW |
5591 | ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s": |
5592 | (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"), | |
5593 | ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" : | |
5594 | (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" : | |
5595 | (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" : | |
b4617240 | 5596 | "Unknown"), |
7c510e4b | 5597 | netdev->dev_addr); |
c44ade9e | 5598 | ixgbe_read_pba_num_generic(hw, &part_num); |
e8e26350 PW |
5599 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
5600 | dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n", | |
5601 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, | |
5602 | (part_num >> 8), (part_num & 0xff)); | |
5603 | else | |
5604 | dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n", | |
5605 | hw->mac.type, hw->phy.type, | |
5606 | (part_num >> 8), (part_num & 0xff)); | |
9a799d71 | 5607 | |
e8e26350 | 5608 | if (hw->bus.width <= ixgbe_bus_width_pcie_x4) { |
0c254d86 | 5609 | dev_warn(&pdev->dev, "PCI-Express bandwidth available for " |
b4617240 PW |
5610 | "this card is not sufficient for optimal " |
5611 | "performance.\n"); | |
0c254d86 | 5612 | dev_warn(&pdev->dev, "For optimal performance a x8 " |
b4617240 | 5613 | "PCI-Express slot is required.\n"); |
0c254d86 AK |
5614 | } |
5615 | ||
34b0368c PWJ |
5616 | /* save off EEPROM version number */ |
5617 | hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version); | |
5618 | ||
9a799d71 | 5619 | /* reset the hardware with the new settings */ |
794caeb2 | 5620 | err = hw->mac.ops.start_hw(hw); |
c44ade9e | 5621 | |
794caeb2 PWJ |
5622 | if (err == IXGBE_ERR_EEPROM_VERSION) { |
5623 | /* We are running on a pre-production device, log a warning */ | |
5624 | dev_warn(&pdev->dev, "This device is a pre-production " | |
5625 | "adapter/LOM. Please be aware there may be issues " | |
5626 | "associated with your hardware. If you are " | |
5627 | "experiencing problems please contact your Intel or " | |
5628 | "hardware representative who provided you with this " | |
5629 | "hardware.\n"); | |
5630 | } | |
9a799d71 AK |
5631 | strcpy(netdev->name, "eth%d"); |
5632 | err = register_netdev(netdev); | |
5633 | if (err) | |
5634 | goto err_register; | |
5635 | ||
54386467 JB |
5636 | /* carrier off reporting is important to ethtool even BEFORE open */ |
5637 | netif_carrier_off(netdev); | |
5638 | ||
c4cf55e5 PWJ |
5639 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
5640 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
5641 | INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task); | |
5642 | ||
5dd2d332 | 5643 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 5644 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd | 5645 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
5646 | ixgbe_setup_dca(adapter); |
5647 | } | |
5648 | #endif | |
0365e6e4 PW |
5649 | /* add san mac addr to netdev */ |
5650 | ixgbe_add_sanmac_netdev(netdev); | |
9a799d71 AK |
5651 | |
5652 | dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n"); | |
5653 | cards_found++; | |
5654 | return 0; | |
5655 | ||
5656 | err_register: | |
5eba3699 | 5657 | ixgbe_release_hw_control(adapter); |
7a921c93 | 5658 | ixgbe_clear_interrupt_scheme(adapter); |
9a799d71 AK |
5659 | err_sw_init: |
5660 | err_eeprom: | |
c4900be0 DS |
5661 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); |
5662 | del_timer_sync(&adapter->sfp_timer); | |
5663 | cancel_work_sync(&adapter->sfp_task); | |
e8e26350 PW |
5664 | cancel_work_sync(&adapter->multispeed_fiber_task); |
5665 | cancel_work_sync(&adapter->sfp_config_module_task); | |
9a799d71 AK |
5666 | iounmap(hw->hw_addr); |
5667 | err_ioremap: | |
5668 | free_netdev(netdev); | |
5669 | err_alloc_etherdev: | |
9ce77666 | 5670 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
5671 | IORESOURCE_MEM)); | |
9a799d71 AK |
5672 | err_pci_reg: |
5673 | err_dma: | |
5674 | pci_disable_device(pdev); | |
5675 | return err; | |
5676 | } | |
5677 | ||
5678 | /** | |
5679 | * ixgbe_remove - Device Removal Routine | |
5680 | * @pdev: PCI device information struct | |
5681 | * | |
5682 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
5683 | * that it should release a PCI device. The could be caused by a | |
5684 | * Hot-Plug event, or because the driver is going to be removed from | |
5685 | * memory. | |
5686 | **/ | |
5687 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
5688 | { | |
5689 | struct net_device *netdev = pci_get_drvdata(pdev); | |
5690 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6fabd715 | 5691 | int err; |
9a799d71 AK |
5692 | |
5693 | set_bit(__IXGBE_DOWN, &adapter->state); | |
c4900be0 DS |
5694 | /* clear the module not found bit to make sure the worker won't |
5695 | * reschedule | |
5696 | */ | |
5697 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
9a799d71 AK |
5698 | del_timer_sync(&adapter->watchdog_timer); |
5699 | ||
c4900be0 DS |
5700 | del_timer_sync(&adapter->sfp_timer); |
5701 | cancel_work_sync(&adapter->watchdog_task); | |
5702 | cancel_work_sync(&adapter->sfp_task); | |
e8e26350 PW |
5703 | cancel_work_sync(&adapter->multispeed_fiber_task); |
5704 | cancel_work_sync(&adapter->sfp_config_module_task); | |
c4cf55e5 PWJ |
5705 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
5706 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
5707 | cancel_work_sync(&adapter->fdir_reinit_task); | |
9a799d71 AK |
5708 | flush_scheduled_work(); |
5709 | ||
5dd2d332 | 5710 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
5711 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
5712 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
5713 | dca_remove_requester(&pdev->dev); | |
5714 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
5715 | } | |
5716 | ||
5717 | #endif | |
332d4a7d YZ |
5718 | #ifdef IXGBE_FCOE |
5719 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
5720 | ixgbe_cleanup_fcoe(adapter); | |
5721 | ||
5722 | #endif /* IXGBE_FCOE */ | |
0365e6e4 PW |
5723 | |
5724 | /* remove the added san mac */ | |
5725 | ixgbe_del_sanmac_netdev(netdev); | |
5726 | ||
c4900be0 DS |
5727 | if (netdev->reg_state == NETREG_REGISTERED) |
5728 | unregister_netdev(netdev); | |
9a799d71 | 5729 | |
7a921c93 | 5730 | ixgbe_clear_interrupt_scheme(adapter); |
5eba3699 | 5731 | |
021230d4 | 5732 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
5733 | |
5734 | iounmap(adapter->hw.hw_addr); | |
9ce77666 | 5735 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
5736 | IORESOURCE_MEM)); | |
9a799d71 | 5737 | |
021230d4 | 5738 | DPRINTK(PROBE, INFO, "complete\n"); |
021230d4 | 5739 | |
9a799d71 AK |
5740 | free_netdev(netdev); |
5741 | ||
6fabd715 PWJ |
5742 | err = pci_disable_pcie_error_reporting(pdev); |
5743 | if (err) | |
5744 | dev_err(&pdev->dev, | |
5745 | "pci_disable_pcie_error_reporting failed 0x%x\n", err); | |
5746 | ||
9a799d71 AK |
5747 | pci_disable_device(pdev); |
5748 | } | |
5749 | ||
5750 | /** | |
5751 | * ixgbe_io_error_detected - called when PCI error is detected | |
5752 | * @pdev: Pointer to PCI device | |
5753 | * @state: The current pci connection state | |
5754 | * | |
5755 | * This function is called after a PCI bus error affecting | |
5756 | * this device has been detected. | |
5757 | */ | |
5758 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
b4617240 | 5759 | pci_channel_state_t state) |
9a799d71 AK |
5760 | { |
5761 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 5762 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
5763 | |
5764 | netif_device_detach(netdev); | |
5765 | ||
3044b8d1 BL |
5766 | if (state == pci_channel_io_perm_failure) |
5767 | return PCI_ERS_RESULT_DISCONNECT; | |
5768 | ||
9a799d71 AK |
5769 | if (netif_running(netdev)) |
5770 | ixgbe_down(adapter); | |
5771 | pci_disable_device(pdev); | |
5772 | ||
b4617240 | 5773 | /* Request a slot reset. */ |
9a799d71 AK |
5774 | return PCI_ERS_RESULT_NEED_RESET; |
5775 | } | |
5776 | ||
5777 | /** | |
5778 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
5779 | * @pdev: Pointer to PCI device | |
5780 | * | |
5781 | * Restart the card from scratch, as if from a cold-boot. | |
5782 | */ | |
5783 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
5784 | { | |
5785 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 5786 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
6fabd715 PWJ |
5787 | pci_ers_result_t result; |
5788 | int err; | |
9a799d71 | 5789 | |
9ce77666 | 5790 | if (pci_enable_device_mem(pdev)) { |
9a799d71 | 5791 | DPRINTK(PROBE, ERR, |
b4617240 | 5792 | "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
5793 | result = PCI_ERS_RESULT_DISCONNECT; |
5794 | } else { | |
5795 | pci_set_master(pdev); | |
5796 | pci_restore_state(pdev); | |
9a799d71 | 5797 | |
dd4d8ca6 | 5798 | pci_wake_from_d3(pdev, false); |
9a799d71 | 5799 | |
6fabd715 | 5800 | ixgbe_reset(adapter); |
88512539 | 5801 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6fabd715 PWJ |
5802 | result = PCI_ERS_RESULT_RECOVERED; |
5803 | } | |
5804 | ||
5805 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
5806 | if (err) { | |
5807 | dev_err(&pdev->dev, | |
5808 | "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err); | |
5809 | /* non-fatal, continue */ | |
5810 | } | |
9a799d71 | 5811 | |
6fabd715 | 5812 | return result; |
9a799d71 AK |
5813 | } |
5814 | ||
5815 | /** | |
5816 | * ixgbe_io_resume - called when traffic can start flowing again. | |
5817 | * @pdev: Pointer to PCI device | |
5818 | * | |
5819 | * This callback is called when the error recovery driver tells us that | |
5820 | * its OK to resume normal operation. | |
5821 | */ | |
5822 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
5823 | { | |
5824 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 5825 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
5826 | |
5827 | if (netif_running(netdev)) { | |
5828 | if (ixgbe_up(adapter)) { | |
5829 | DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n"); | |
5830 | return; | |
5831 | } | |
5832 | } | |
5833 | ||
5834 | netif_device_attach(netdev); | |
9a799d71 AK |
5835 | } |
5836 | ||
5837 | static struct pci_error_handlers ixgbe_err_handler = { | |
5838 | .error_detected = ixgbe_io_error_detected, | |
5839 | .slot_reset = ixgbe_io_slot_reset, | |
5840 | .resume = ixgbe_io_resume, | |
5841 | }; | |
5842 | ||
5843 | static struct pci_driver ixgbe_driver = { | |
5844 | .name = ixgbe_driver_name, | |
5845 | .id_table = ixgbe_pci_tbl, | |
5846 | .probe = ixgbe_probe, | |
5847 | .remove = __devexit_p(ixgbe_remove), | |
5848 | #ifdef CONFIG_PM | |
5849 | .suspend = ixgbe_suspend, | |
5850 | .resume = ixgbe_resume, | |
5851 | #endif | |
5852 | .shutdown = ixgbe_shutdown, | |
5853 | .err_handler = &ixgbe_err_handler | |
5854 | }; | |
5855 | ||
5856 | /** | |
5857 | * ixgbe_init_module - Driver Registration Routine | |
5858 | * | |
5859 | * ixgbe_init_module is the first routine called when the driver is | |
5860 | * loaded. All it does is register with the PCI subsystem. | |
5861 | **/ | |
5862 | static int __init ixgbe_init_module(void) | |
5863 | { | |
5864 | int ret; | |
5865 | printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name, | |
5866 | ixgbe_driver_string, ixgbe_driver_version); | |
5867 | ||
5868 | printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright); | |
5869 | ||
5dd2d332 | 5870 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 5871 | dca_register_notify(&dca_notifier); |
bd0362dd | 5872 | #endif |
5dd2d332 | 5873 | |
9a799d71 AK |
5874 | ret = pci_register_driver(&ixgbe_driver); |
5875 | return ret; | |
5876 | } | |
b4617240 | 5877 | |
9a799d71 AK |
5878 | module_init(ixgbe_init_module); |
5879 | ||
5880 | /** | |
5881 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
5882 | * | |
5883 | * ixgbe_exit_module is called just before the driver is removed | |
5884 | * from memory. | |
5885 | **/ | |
5886 | static void __exit ixgbe_exit_module(void) | |
5887 | { | |
5dd2d332 | 5888 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
5889 | dca_unregister_notify(&dca_notifier); |
5890 | #endif | |
9a799d71 AK |
5891 | pci_unregister_driver(&ixgbe_driver); |
5892 | } | |
bd0362dd | 5893 | |
5dd2d332 | 5894 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 5895 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
b4617240 | 5896 | void *p) |
bd0362dd JC |
5897 | { |
5898 | int ret_val; | |
5899 | ||
5900 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
b4617240 | 5901 | __ixgbe_notify_dca); |
bd0362dd JC |
5902 | |
5903 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
5904 | } | |
b453368d | 5905 | |
5dd2d332 | 5906 | #endif /* CONFIG_IXGBE_DCA */ |
b453368d AD |
5907 | #ifdef DEBUG |
5908 | /** | |
5909 | * ixgbe_get_hw_dev_name - return device name string | |
5910 | * used by hardware layer to print debugging information | |
5911 | **/ | |
5912 | char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw) | |
5913 | { | |
5914 | struct ixgbe_adapter *adapter = hw->back; | |
5915 | return adapter->netdev->name; | |
5916 | } | |
bd0362dd | 5917 | |
b453368d | 5918 | #endif |
9a799d71 AK |
5919 | module_exit(ixgbe_exit_module); |
5920 | ||
5921 | /* ixgbe_main.c */ |